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opcodes: blackfin: decode insns with invalid register as illegal
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3
4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include <stdio.h>
22 #include <stdlib.h>
23 #include <string.h>
24
25 #include "opcode/bfin.h"
26
27 #define M_S2RND 1
28 #define M_T 2
29 #define M_W32 3
30 #define M_FU 4
31 #define M_TFU 6
32 #define M_IS 8
33 #define M_ISS2 9
34 #define M_IH 11
35 #define M_IU 12
36
37 #ifndef PRINTF
38 #define PRINTF printf
39 #endif
40
41 #ifndef EXIT
42 #define EXIT exit
43 #endif
44
45 typedef long TIword;
46
47 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
51
52 #include "dis-asm.h"
53
54 typedef unsigned int bu32;
55
56 static char comment = 0;
57 static char parallel = 0;
58
59 typedef enum
60 {
61 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
62 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
63 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
64 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
65 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
66 } const_forms_t;
67
68 static const struct
69 {
70 const char *name;
71 const int nbits;
72 const char reloc;
73 const char issigned;
74 const char pcrel;
75 const char scale;
76 const char offset;
77 const char negative;
78 const char positive;
79 const char decimal;
80 const char leading;
81 const char exact;
82 } constant_formats[] =
83 {
84 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
92 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
94 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
95 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
97 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
98 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
100 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
101 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
104 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
108 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
109 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
110 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
111 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
113 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
119 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
120 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
121 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
123 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
124 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
125 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
127 };
128
129 static const char *
130 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
131 {
132 static char buf[60];
133
134 if (constant_formats[cf].reloc)
135 {
136 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
137 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
138 if (constant_formats[cf].pcrel)
139 ea += pc;
140
141 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
142 {
143 outf->print_address_func (ea, outf);
144 return "";
145 }
146 else
147 {
148 sprintf (buf, "%lx", (unsigned long) x);
149 return buf;
150 }
151 }
152
153 /* Negative constants have an implied sign bit. */
154 if (constant_formats[cf].negative)
155 {
156 int nb = constant_formats[cf].nbits + 1;
157
158 x = x | (1 << constant_formats[cf].nbits);
159 x = SIGNEXTEND (x, nb);
160 }
161 else
162 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
163
164 if (constant_formats[cf].offset)
165 x += constant_formats[cf].offset;
166
167 if (constant_formats[cf].scale)
168 x <<= constant_formats[cf].scale;
169
170 if (constant_formats[cf].decimal)
171 {
172 if (constant_formats[cf].leading)
173 {
174 char ps[10];
175 sprintf (ps, "%%%ii", constant_formats[cf].leading);
176 sprintf (buf, ps, x);
177 }
178 else
179 sprintf (buf, "%li", x);
180 }
181 else
182 {
183 if (constant_formats[cf].issigned && x < 0)
184 sprintf (buf, "-0x%x", abs (x));
185 else
186 sprintf (buf, "0x%lx", (unsigned long) x);
187 }
188
189 return buf;
190 }
191
192 static bu32
193 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
194 {
195 if (0 && constant_formats[cf].reloc)
196 {
197 bu32 ea = (((constant_formats[cf].pcrel
198 ? SIGNEXTEND (x, constant_formats[cf].nbits)
199 : x) + constant_formats[cf].offset)
200 << constant_formats[cf].scale);
201 if (constant_formats[cf].pcrel)
202 ea += pc;
203
204 return ea;
205 }
206
207 /* Negative constants have an implied sign bit. */
208 if (constant_formats[cf].negative)
209 {
210 int nb = constant_formats[cf].nbits + 1;
211 x = x | (1 << constant_formats[cf].nbits);
212 x = SIGNEXTEND (x, nb);
213 }
214 else if (constant_formats[cf].issigned)
215 x = SIGNEXTEND (x, constant_formats[cf].nbits);
216
217 x += constant_formats[cf].offset;
218 x <<= constant_formats[cf].scale;
219
220 return x;
221 }
222
223 enum machine_registers
224 {
225 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
226 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
227 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
228 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
229 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
230 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
231 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
232 REG_L2, REG_L3,
233 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
234 REG_AQ, REG_V, REG_VS,
235 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
236 REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
237 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
238 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
239 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
240 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
241 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
242 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
243 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
244 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
245 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
246 REG_LASTREG,
247 };
248
249 enum reg_class
250 {
251 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
252 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
253 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
254 rc_sysregs3, rc_allregs,
255 LIM_REG_CLASSES
256 };
257
258 static const char *reg_names[] =
259 {
260 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
261 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
262 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
263 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
264 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
265 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
266 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
267 "L2", "L3",
268 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
269 "AQ", "V", "VS",
270 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
271 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
272 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
273 "RETE", "EMUDAT",
274 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
275 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
276 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
277 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
278 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
279 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
280 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
281 "AC0_COPY", "V_COPY", "RND_MOD",
282 "LASTREG",
283 0
284 };
285
286 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
287
288 /* RL(0..7). */
289 static enum machine_registers decode_dregs_lo[] =
290 {
291 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
292 };
293
294 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
295
296 /* RH(0..7). */
297 static enum machine_registers decode_dregs_hi[] =
298 {
299 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
300 };
301
302 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
303
304 /* R(0..7). */
305 static enum machine_registers decode_dregs[] =
306 {
307 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
308 };
309
310 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
311
312 /* R BYTE(0..7). */
313 static enum machine_registers decode_dregs_byte[] =
314 {
315 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
316 };
317
318 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
319
320 /* P(0..5) SP FP. */
321 static enum machine_registers decode_pregs[] =
322 {
323 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
324 };
325
326 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
327 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
328 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
329 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
330 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
331 #define accum(x) REGNAME (decode_accum[(x) & 1])
332
333 /* I(0..3). */
334 static enum machine_registers decode_iregs[] =
335 {
336 REG_I0, REG_I1, REG_I2, REG_I3,
337 };
338
339 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
340
341 /* M(0..3). */
342 static enum machine_registers decode_mregs[] =
343 {
344 REG_M0, REG_M1, REG_M2, REG_M3,
345 };
346
347 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
348 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
349 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
350
351 /* dregs pregs. */
352 static enum machine_registers decode_dpregs[] =
353 {
354 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
355 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
356 };
357
358 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
359
360 /* [dregs pregs]. */
361 static enum machine_registers decode_gregs[] =
362 {
363 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
364 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
365 };
366
367 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
368
369 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
370 static enum machine_registers decode_regs[] =
371 {
372 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
373 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
374 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
375 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
376 };
377
378 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
379
380 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
381 static enum machine_registers decode_regs_lo[] =
382 {
383 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
384 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
385 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
386 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
387 };
388
389 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
390 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
391 static enum machine_registers decode_regs_hi[] =
392 {
393 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
394 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
395 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
396 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
397 };
398
399 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
400
401 static enum machine_registers decode_statbits[] =
402 {
403 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
404 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
405 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
406 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
407 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
408 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
409 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
410 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
411 };
412
413 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
414
415 /* LC0 LC1. */
416 static enum machine_registers decode_counters[] =
417 {
418 REG_LC0, REG_LC1,
419 };
420
421 #define counters(x) REGNAME (decode_counters[(x) & 1])
422 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
423
424 /* [dregs pregs (iregs mregs) (bregs lregs)
425 dregs2_sysregs1 open sysregs2 sysregs3]. */
426 static enum machine_registers decode_allregs[] =
427 {
428 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
429 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
430 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
431 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
432 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
433 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
434 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
435 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
436 REG_LASTREG,
437 };
438
439 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
440 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
441 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
442 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
443 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
444 #define IS_SYSREG(g,r) \
445 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
446 #define IS_RESERVEDREG(g,r) \
447 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
448
449 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
450 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
451
452 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
453 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
454 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
455 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
456 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
457 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
458 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
459 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
460 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
461 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
462 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
463 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
464 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
465 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
466 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
467 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
468 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
469 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
470 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
471 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
472 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
473 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
474 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
475 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
476 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
477 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
478 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
479 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
480 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
481 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
482 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
483 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
484 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
485 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
486 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
487 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
488 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
489 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
490 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
491 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
492 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
493 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
494 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
495
496 /* (arch.pm)arch_disassembler_functions. */
497 #ifndef OUTS
498 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
499 #endif
500
501 static void
502 amod0 (int s0, int x0, disassemble_info *outf)
503 {
504 if (s0 == 1 && x0 == 0)
505 OUTS (outf, " (S)");
506 else if (s0 == 0 && x0 == 1)
507 OUTS (outf, " (CO)");
508 else if (s0 == 1 && x0 == 1)
509 OUTS (outf, " (SCO)");
510 }
511
512 static void
513 amod1 (int s0, int x0, disassemble_info *outf)
514 {
515 if (s0 == 0 && x0 == 0)
516 OUTS (outf, " (NS)");
517 else if (s0 == 1 && x0 == 0)
518 OUTS (outf, " (S)");
519 }
520
521 static void
522 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
523 {
524 if (s0 == 1 && x0 == 0 && aop0 == 0)
525 OUTS (outf, " (S)");
526 else if (s0 == 0 && x0 == 1 && aop0 == 0)
527 OUTS (outf, " (CO)");
528 else if (s0 == 1 && x0 == 1 && aop0 == 0)
529 OUTS (outf, " (SCO)");
530 else if (s0 == 0 && x0 == 0 && aop0 == 2)
531 OUTS (outf, " (ASR)");
532 else if (s0 == 1 && x0 == 0 && aop0 == 2)
533 OUTS (outf, " (S, ASR)");
534 else if (s0 == 0 && x0 == 1 && aop0 == 2)
535 OUTS (outf, " (CO, ASR)");
536 else if (s0 == 1 && x0 == 1 && aop0 == 2)
537 OUTS (outf, " (SCO, ASR)");
538 else if (s0 == 0 && x0 == 0 && aop0 == 3)
539 OUTS (outf, " (ASL)");
540 else if (s0 == 1 && x0 == 0 && aop0 == 3)
541 OUTS (outf, " (S, ASL)");
542 else if (s0 == 0 && x0 == 1 && aop0 == 3)
543 OUTS (outf, " (CO, ASL)");
544 else if (s0 == 1 && x0 == 1 && aop0 == 3)
545 OUTS (outf, " (SCO, ASL)");
546 }
547
548 static void
549 searchmod (int r0, disassemble_info *outf)
550 {
551 if (r0 == 0)
552 OUTS (outf, "GT");
553 else if (r0 == 1)
554 OUTS (outf, "GE");
555 else if (r0 == 2)
556 OUTS (outf, "LT");
557 else if (r0 == 3)
558 OUTS (outf, "LE");
559 }
560
561 static void
562 aligndir (int r0, disassemble_info *outf)
563 {
564 if (r0 == 1)
565 OUTS (outf, " (R)");
566 }
567
568 static int
569 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
570 {
571 const char *s0, *s1;
572
573 if (h0)
574 s0 = dregs_hi (src0);
575 else
576 s0 = dregs_lo (src0);
577
578 if (h1)
579 s1 = dregs_hi (src1);
580 else
581 s1 = dregs_lo (src1);
582
583 OUTS (outf, s0);
584 OUTS (outf, " * ");
585 OUTS (outf, s1);
586 return 0;
587 }
588
589 static int
590 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
591 {
592 const char *a;
593 const char *sop = "<unknown op>";
594
595 if (which)
596 a = "A1";
597 else
598 a = "A0";
599
600 if (op == 3)
601 {
602 OUTS (outf, a);
603 return 0;
604 }
605
606 switch (op)
607 {
608 case 0: sop = " = "; break;
609 case 1: sop = " += "; break;
610 case 2: sop = " -= "; break;
611 default: break;
612 }
613
614 OUTS (outf, a);
615 OUTS (outf, sop);
616 decode_multfunc (h0, h1, src0, src1, outf);
617
618 return 0;
619 }
620
621 static void
622 decode_optmode (int mod, int MM, disassemble_info *outf)
623 {
624 if (mod == 0 && MM == 0)
625 return;
626
627 OUTS (outf, " (");
628
629 if (MM && !mod)
630 {
631 OUTS (outf, "M)");
632 return;
633 }
634
635 if (MM)
636 OUTS (outf, "M, ");
637
638 if (mod == M_S2RND)
639 OUTS (outf, "S2RND");
640 else if (mod == M_T)
641 OUTS (outf, "T");
642 else if (mod == M_W32)
643 OUTS (outf, "W32");
644 else if (mod == M_FU)
645 OUTS (outf, "FU");
646 else if (mod == M_TFU)
647 OUTS (outf, "TFU");
648 else if (mod == M_IS)
649 OUTS (outf, "IS");
650 else if (mod == M_ISS2)
651 OUTS (outf, "ISS2");
652 else if (mod == M_IH)
653 OUTS (outf, "IH");
654 else if (mod == M_IU)
655 OUTS (outf, "IU");
656 else
657 abort ();
658
659 OUTS (outf, ")");
660 }
661
662 struct saved_state
663 {
664 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
665 bu32 a0x, a0w, a1x, a1w;
666 bu32 lt[2], lc[2], lb[2];
667 int ac0, ac0_copy, ac1, an, aq;
668 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
669 int rnd_mod;
670 int v_internal;
671 bu32 pc, rets;
672
673 int ticks;
674 int insts;
675
676 int exception;
677
678 int end_of_registers;
679
680 int msize;
681 unsigned char *memory;
682 unsigned long bfd_mach;
683 } saved_state;
684
685 #define DREG(x) (saved_state.dpregs[x])
686 #define GREG(x,i) DPREG ((x) | (i << 3))
687 #define DPREG(x) (saved_state.dpregs[x])
688 #define DREG(x) (saved_state.dpregs[x])
689 #define PREG(x) (saved_state.dpregs[x + 8])
690 #define SPREG PREG (6)
691 #define FPREG PREG (7)
692 #define IREG(x) (saved_state.iregs[x])
693 #define MREG(x) (saved_state.mregs[x])
694 #define BREG(x) (saved_state.bregs[x])
695 #define LREG(x) (saved_state.lregs[x])
696 #define A0XREG (saved_state.a0x)
697 #define A0WREG (saved_state.a0w)
698 #define A1XREG (saved_state.a1x)
699 #define A1WREG (saved_state.a1w)
700 #define CCREG (saved_state.cc)
701 #define LC0REG (saved_state.lc[0])
702 #define LT0REG (saved_state.lt[0])
703 #define LB0REG (saved_state.lb[0])
704 #define LC1REG (saved_state.lc[1])
705 #define LT1REG (saved_state.lt[1])
706 #define LB1REG (saved_state.lb[1])
707 #define RETSREG (saved_state.rets)
708 #define PCREG (saved_state.pc)
709
710 static bu32 *
711 get_allreg (int grp, int reg)
712 {
713 int fullreg = (grp << 3) | reg;
714 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
715 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
716 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
717 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
718 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
719 , , , , , , , ,
720 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
721 REG_CYCLES2,
722 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
723 REG_LASTREG */
724 switch (fullreg >> 2)
725 {
726 case 0: case 1: return &DREG (reg); break;
727 case 2: case 3: return &PREG (reg); break;
728 case 4: return &IREG (reg & 3); break;
729 case 5: return &MREG (reg & 3); break;
730 case 6: return &BREG (reg & 3); break;
731 case 7: return &LREG (reg & 3); break;
732 default:
733 switch (fullreg)
734 {
735 case 32: return &saved_state.a0x;
736 case 33: return &saved_state.a0w;
737 case 34: return &saved_state.a1x;
738 case 35: return &saved_state.a1w;
739 case 39: return &saved_state.rets;
740 case 48: return &LC0REG;
741 case 49: return &LT0REG;
742 case 50: return &LB0REG;
743 case 51: return &LC1REG;
744 case 52: return &LT1REG;
745 case 53: return &LB1REG;
746 }
747 return 0;
748 }
749 }
750
751 static int
752 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
753 {
754 /* ProgCtrl
755 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
756 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
757 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
758 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
759 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
760
761 if (prgfunc == 0 && poprnd == 0)
762 OUTS (outf, "NOP");
763 else if (prgfunc == 1 && poprnd == 0)
764 OUTS (outf, "RTS");
765 else if (prgfunc == 1 && poprnd == 1)
766 OUTS (outf, "RTI");
767 else if (prgfunc == 1 && poprnd == 2)
768 OUTS (outf, "RTX");
769 else if (prgfunc == 1 && poprnd == 3)
770 OUTS (outf, "RTN");
771 else if (prgfunc == 1 && poprnd == 4)
772 OUTS (outf, "RTE");
773 else if (prgfunc == 2 && poprnd == 0)
774 OUTS (outf, "IDLE");
775 else if (prgfunc == 2 && poprnd == 3)
776 OUTS (outf, "CSYNC");
777 else if (prgfunc == 2 && poprnd == 4)
778 OUTS (outf, "SSYNC");
779 else if (prgfunc == 2 && poprnd == 5)
780 OUTS (outf, "EMUEXCPT");
781 else if (prgfunc == 3 && IS_DREG (0, poprnd))
782 {
783 OUTS (outf, "CLI ");
784 OUTS (outf, dregs (poprnd));
785 }
786 else if (prgfunc == 4 && IS_DREG (0, poprnd))
787 {
788 OUTS (outf, "STI ");
789 OUTS (outf, dregs (poprnd));
790 }
791 else if (prgfunc == 5 && IS_PREG (1, poprnd))
792 {
793 OUTS (outf, "JUMP (");
794 OUTS (outf, pregs (poprnd));
795 OUTS (outf, ")");
796 }
797 else if (prgfunc == 6 && IS_PREG (1, poprnd))
798 {
799 OUTS (outf, "CALL (");
800 OUTS (outf, pregs (poprnd));
801 OUTS (outf, ")");
802 }
803 else if (prgfunc == 7 && IS_PREG (1, poprnd))
804 {
805 OUTS (outf, "CALL (PC + ");
806 OUTS (outf, pregs (poprnd));
807 OUTS (outf, ")");
808 }
809 else if (prgfunc == 8 && IS_PREG (1, poprnd))
810 {
811 OUTS (outf, "JUMP (PC + ");
812 OUTS (outf, pregs (poprnd));
813 OUTS (outf, ")");
814 }
815 else if (prgfunc == 9)
816 {
817 OUTS (outf, "RAISE ");
818 OUTS (outf, uimm4 (poprnd));
819 }
820 else if (prgfunc == 10)
821 {
822 OUTS (outf, "EXCPT ");
823 OUTS (outf, uimm4 (poprnd));
824 }
825 else if (prgfunc == 11 && IS_PREG (1, poprnd))
826 {
827 OUTS (outf, "TESTSET (");
828 OUTS (outf, pregs (poprnd));
829 OUTS (outf, ")");
830 }
831 else
832 return 0;
833 return 2;
834 }
835
836 static int
837 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
838 {
839 /* CaCTRL
840 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
841 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
842 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
843 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
844 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
845 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
846
847 if (a == 0 && op == 0)
848 {
849 OUTS (outf, "PREFETCH[");
850 OUTS (outf, pregs (reg));
851 OUTS (outf, "]");
852 }
853 else if (a == 0 && op == 1)
854 {
855 OUTS (outf, "FLUSHINV[");
856 OUTS (outf, pregs (reg));
857 OUTS (outf, "]");
858 }
859 else if (a == 0 && op == 2)
860 {
861 OUTS (outf, "FLUSH[");
862 OUTS (outf, pregs (reg));
863 OUTS (outf, "]");
864 }
865 else if (a == 0 && op == 3)
866 {
867 OUTS (outf, "IFLUSH[");
868 OUTS (outf, pregs (reg));
869 OUTS (outf, "]");
870 }
871 else if (a == 1 && op == 0)
872 {
873 OUTS (outf, "PREFETCH[");
874 OUTS (outf, pregs (reg));
875 OUTS (outf, "++]");
876 }
877 else if (a == 1 && op == 1)
878 {
879 OUTS (outf, "FLUSHINV[");
880 OUTS (outf, pregs (reg));
881 OUTS (outf, "++]");
882 }
883 else if (a == 1 && op == 2)
884 {
885 OUTS (outf, "FLUSH[");
886 OUTS (outf, pregs (reg));
887 OUTS (outf, "++]");
888 }
889 else if (a == 1 && op == 3)
890 {
891 OUTS (outf, "IFLUSH[");
892 OUTS (outf, pregs (reg));
893 OUTS (outf, "++]");
894 }
895 else
896 return 0;
897 return 2;
898 }
899
900 static int
901 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
902 {
903 /* PushPopReg
904 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
905 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
906 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
907 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
908 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
909 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
910
911 if (W == 0 && mostreg (reg, grp))
912 {
913 OUTS (outf, allregs (reg, grp));
914 OUTS (outf, " = [SP++]");
915 }
916 else if (W == 1 && allreg (reg, grp))
917 {
918 OUTS (outf, "[--SP] = ");
919 OUTS (outf, allregs (reg, grp));
920 }
921 else
922 return 0;
923 return 2;
924 }
925
926 static int
927 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
928 {
929 /* PushPopMultiple
930 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
931 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
932 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
933 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
934 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
935 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
936 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
937 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
938
939 if (W == 1 && d == 1 && p == 1)
940 {
941 OUTS (outf, "[--SP] = (R7:");
942 OUTS (outf, imm5d (dr));
943 OUTS (outf, ", P5:");
944 OUTS (outf, imm5d (pr));
945 OUTS (outf, ")");
946 }
947 else if (W == 1 && d == 1 && p == 0)
948 {
949 OUTS (outf, "[--SP] = (R7:");
950 OUTS (outf, imm5d (dr));
951 OUTS (outf, ")");
952 }
953 else if (W == 1 && d == 0 && p == 1)
954 {
955 OUTS (outf, "[--SP] = (P5:");
956 OUTS (outf, imm5d (pr));
957 OUTS (outf, ")");
958 }
959 else if (W == 0 && d == 1 && p == 1)
960 {
961 OUTS (outf, "(R7:");
962 OUTS (outf, imm5d (dr));
963 OUTS (outf, ", P5:");
964 OUTS (outf, imm5d (pr));
965 OUTS (outf, ") = [SP++]");
966 }
967 else if (W == 0 && d == 1 && p == 0)
968 {
969 OUTS (outf, "(R7:");
970 OUTS (outf, imm5d (dr));
971 OUTS (outf, ") = [SP++]");
972 }
973 else if (W == 0 && d == 0 && p == 1)
974 {
975 OUTS (outf, "(P5:");
976 OUTS (outf, imm5d (pr));
977 OUTS (outf, ") = [SP++]");
978 }
979 else
980 return 0;
981 return 2;
982 }
983
984 static int
985 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
986 {
987 /* ccMV
988 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
989 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
990 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
991 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
992 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
993 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
994 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
995 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
996
997 if (T == 1)
998 {
999 OUTS (outf, "IF CC ");
1000 OUTS (outf, gregs (dst, d));
1001 OUTS (outf, " = ");
1002 OUTS (outf, gregs (src, s));
1003 }
1004 else if (T == 0)
1005 {
1006 OUTS (outf, "IF !CC ");
1007 OUTS (outf, gregs (dst, d));
1008 OUTS (outf, " = ");
1009 OUTS (outf, gregs (src, s));
1010 }
1011 else
1012 return 0;
1013 return 2;
1014 }
1015
1016 static int
1017 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1018 {
1019 /* CCflag
1020 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1021 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1022 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1023 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1024 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1025 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1026 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1027 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1028
1029 if (opc == 0 && I == 0 && G == 0)
1030 {
1031 OUTS (outf, "CC = ");
1032 OUTS (outf, dregs (x));
1033 OUTS (outf, " == ");
1034 OUTS (outf, dregs (y));
1035 }
1036 else if (opc == 1 && I == 0 && G == 0)
1037 {
1038 OUTS (outf, "CC = ");
1039 OUTS (outf, dregs (x));
1040 OUTS (outf, " < ");
1041 OUTS (outf, dregs (y));
1042 }
1043 else if (opc == 2 && I == 0 && G == 0)
1044 {
1045 OUTS (outf, "CC = ");
1046 OUTS (outf, dregs (x));
1047 OUTS (outf, " <= ");
1048 OUTS (outf, dregs (y));
1049 }
1050 else if (opc == 3 && I == 0 && G == 0)
1051 {
1052 OUTS (outf, "CC = ");
1053 OUTS (outf, dregs (x));
1054 OUTS (outf, " < ");
1055 OUTS (outf, dregs (y));
1056 OUTS (outf, " (IU)");
1057 }
1058 else if (opc == 4 && I == 0 && G == 0)
1059 {
1060 OUTS (outf, "CC = ");
1061 OUTS (outf, dregs (x));
1062 OUTS (outf, " <= ");
1063 OUTS (outf, dregs (y));
1064 OUTS (outf, " (IU)");
1065 }
1066 else if (opc == 0 && I == 1 && G == 0)
1067 {
1068 OUTS (outf, "CC = ");
1069 OUTS (outf, dregs (x));
1070 OUTS (outf, " == ");
1071 OUTS (outf, imm3 (y));
1072 }
1073 else if (opc == 1 && I == 1 && G == 0)
1074 {
1075 OUTS (outf, "CC = ");
1076 OUTS (outf, dregs (x));
1077 OUTS (outf, " < ");
1078 OUTS (outf, imm3 (y));
1079 }
1080 else if (opc == 2 && I == 1 && G == 0)
1081 {
1082 OUTS (outf, "CC = ");
1083 OUTS (outf, dregs (x));
1084 OUTS (outf, " <= ");
1085 OUTS (outf, imm3 (y));
1086 }
1087 else if (opc == 3 && I == 1 && G == 0)
1088 {
1089 OUTS (outf, "CC = ");
1090 OUTS (outf, dregs (x));
1091 OUTS (outf, " < ");
1092 OUTS (outf, uimm3 (y));
1093 OUTS (outf, " (IU)");
1094 }
1095 else if (opc == 4 && I == 1 && G == 0)
1096 {
1097 OUTS (outf, "CC = ");
1098 OUTS (outf, dregs (x));
1099 OUTS (outf, " <= ");
1100 OUTS (outf, uimm3 (y));
1101 OUTS (outf, " (IU)");
1102 }
1103 else if (opc == 0 && I == 0 && G == 1)
1104 {
1105 OUTS (outf, "CC = ");
1106 OUTS (outf, pregs (x));
1107 OUTS (outf, " == ");
1108 OUTS (outf, pregs (y));
1109 }
1110 else if (opc == 1 && I == 0 && G == 1)
1111 {
1112 OUTS (outf, "CC = ");
1113 OUTS (outf, pregs (x));
1114 OUTS (outf, " < ");
1115 OUTS (outf, pregs (y));
1116 }
1117 else if (opc == 2 && I == 0 && G == 1)
1118 {
1119 OUTS (outf, "CC = ");
1120 OUTS (outf, pregs (x));
1121 OUTS (outf, " <= ");
1122 OUTS (outf, pregs (y));
1123 }
1124 else if (opc == 3 && I == 0 && G == 1)
1125 {
1126 OUTS (outf, "CC = ");
1127 OUTS (outf, pregs (x));
1128 OUTS (outf, " < ");
1129 OUTS (outf, pregs (y));
1130 OUTS (outf, " (IU)");
1131 }
1132 else if (opc == 4 && I == 0 && G == 1)
1133 {
1134 OUTS (outf, "CC = ");
1135 OUTS (outf, pregs (x));
1136 OUTS (outf, " <= ");
1137 OUTS (outf, pregs (y));
1138 OUTS (outf, " (IU)");
1139 }
1140 else if (opc == 0 && I == 1 && G == 1)
1141 {
1142 OUTS (outf, "CC = ");
1143 OUTS (outf, pregs (x));
1144 OUTS (outf, " == ");
1145 OUTS (outf, imm3 (y));
1146 }
1147 else if (opc == 1 && I == 1 && G == 1)
1148 {
1149 OUTS (outf, "CC = ");
1150 OUTS (outf, pregs (x));
1151 OUTS (outf, " < ");
1152 OUTS (outf, imm3 (y));
1153 }
1154 else if (opc == 2 && I == 1 && G == 1)
1155 {
1156 OUTS (outf, "CC = ");
1157 OUTS (outf, pregs (x));
1158 OUTS (outf, " <= ");
1159 OUTS (outf, imm3 (y));
1160 }
1161 else if (opc == 3 && I == 1 && G == 1)
1162 {
1163 OUTS (outf, "CC = ");
1164 OUTS (outf, pregs (x));
1165 OUTS (outf, " < ");
1166 OUTS (outf, uimm3 (y));
1167 OUTS (outf, " (IU)");
1168 }
1169 else if (opc == 4 && I == 1 && G == 1)
1170 {
1171 OUTS (outf, "CC = ");
1172 OUTS (outf, pregs (x));
1173 OUTS (outf, " <= ");
1174 OUTS (outf, uimm3 (y));
1175 OUTS (outf, " (IU)");
1176 }
1177 else if (opc == 5 && I == 0 && G == 0)
1178 OUTS (outf, "CC = A0 == A1");
1179
1180 else if (opc == 6 && I == 0 && G == 0)
1181 OUTS (outf, "CC = A0 < A1");
1182
1183 else if (opc == 7 && I == 0 && G == 0)
1184 OUTS (outf, "CC = A0 <= A1");
1185
1186 else
1187 return 0;
1188 return 2;
1189 }
1190
1191 static int
1192 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1193 {
1194 /* CC2dreg
1195 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1196 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1197 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1198 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1199 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1200
1201 if (op == 0)
1202 {
1203 OUTS (outf, dregs (reg));
1204 OUTS (outf, " = CC");
1205 }
1206 else if (op == 1)
1207 {
1208 OUTS (outf, "CC = ");
1209 OUTS (outf, dregs (reg));
1210 }
1211 else if (op == 3 && reg == 0)
1212 OUTS (outf, "CC = !CC");
1213 else
1214 return 0;
1215
1216 return 2;
1217 }
1218
1219 static int
1220 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1221 {
1222 /* CC2stat
1223 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1224 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1225 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1226 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1227 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1228 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1229
1230 if (op == 0 && D == 0)
1231 {
1232 OUTS (outf, "CC = ");
1233 OUTS (outf, statbits (cbit));
1234 }
1235 else if (op == 1 && D == 0)
1236 {
1237 OUTS (outf, "CC |= ");
1238 OUTS (outf, statbits (cbit));
1239 }
1240 else if (op == 2 && D == 0)
1241 {
1242 OUTS (outf, "CC &= ");
1243 OUTS (outf, statbits (cbit));
1244 }
1245 else if (op == 3 && D == 0)
1246 {
1247 OUTS (outf, "CC ^= ");
1248 OUTS (outf, statbits (cbit));
1249 }
1250 else if (op == 0 && D == 1)
1251 {
1252 OUTS (outf, statbits (cbit));
1253 OUTS (outf, " = CC");
1254 }
1255 else if (op == 1 && D == 1)
1256 {
1257 OUTS (outf, statbits (cbit));
1258 OUTS (outf, " |= CC");
1259 }
1260 else if (op == 2 && D == 1)
1261 {
1262 OUTS (outf, statbits (cbit));
1263 OUTS (outf, " &= CC");
1264 }
1265 else if (op == 3 && D == 1)
1266 {
1267 OUTS (outf, statbits (cbit));
1268 OUTS (outf, " ^= CC");
1269 }
1270 else
1271 return 0;
1272
1273 return 2;
1274 }
1275
1276 static int
1277 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1278 {
1279 /* BRCC
1280 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1281 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1282 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1283 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1284 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1285 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1286
1287 if (T == 1 && B == 1)
1288 {
1289 OUTS (outf, "IF CC JUMP 0x");
1290 OUTS (outf, pcrel10 (offset));
1291 OUTS (outf, " (BP)");
1292 }
1293 else if (T == 0 && B == 1)
1294 {
1295 OUTS (outf, "IF !CC JUMP 0x");
1296 OUTS (outf, pcrel10 (offset));
1297 OUTS (outf, " (BP)");
1298 }
1299 else if (T == 1)
1300 {
1301 OUTS (outf, "IF CC JUMP 0x");
1302 OUTS (outf, pcrel10 (offset));
1303 }
1304 else if (T == 0)
1305 {
1306 OUTS (outf, "IF !CC JUMP 0x");
1307 OUTS (outf, pcrel10 (offset));
1308 }
1309 else
1310 return 0;
1311
1312 return 2;
1313 }
1314
1315 static int
1316 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1317 {
1318 /* UJUMP
1319 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1320 | 0 | 0 | 1 | 0 |.offset........................................|
1321 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1322 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1323
1324 OUTS (outf, "JUMP.S 0x");
1325 OUTS (outf, pcrel12 (offset));
1326 return 2;
1327 }
1328
1329 static int
1330 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1331 {
1332 /* REGMV
1333 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1334 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1335 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1336 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1337 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1338 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1339 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1340
1341 if (!((IS_GENREG (gd, dst) && IS_GENREG (gs, src))
1342 || (IS_GENREG (gd, dst) && IS_DAGREG (gs, src))
1343 || (IS_DAGREG (gd, dst) && IS_GENREG (gs, src))
1344 || (IS_DAGREG (gd, dst) && IS_DAGREG (gs, src))
1345 || (IS_GENREG (gd, dst) && gs == 7 && src == 0)
1346 || (gd == 7 && dst == 0 && IS_GENREG (gs, src))
1347 || (IS_DREG (gd, dst) && IS_SYSREG (gs, src))
1348 || (IS_PREG (gd, dst) && IS_SYSREG (gs, src))
1349 || (IS_SYSREG (gd, dst) && IS_DREG (gs, src))
1350 || (IS_SYSREG (gd, dst) && IS_PREG (gs, src))
1351 || (IS_SYSREG (gd, dst) && gs == 7 && src == 0)))
1352 return 0;
1353
1354 OUTS (outf, allregs (dst, gd));
1355 OUTS (outf, " = ");
1356 OUTS (outf, allregs (src, gs));
1357 return 2;
1358 }
1359
1360 static int
1361 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1362 {
1363 /* ALU2op
1364 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1365 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1366 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1367 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1368 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1369 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1370
1371 if (opc == 0)
1372 {
1373 OUTS (outf, dregs (dst));
1374 OUTS (outf, " >>>= ");
1375 OUTS (outf, dregs (src));
1376 }
1377 else if (opc == 1)
1378 {
1379 OUTS (outf, dregs (dst));
1380 OUTS (outf, " >>= ");
1381 OUTS (outf, dregs (src));
1382 }
1383 else if (opc == 2)
1384 {
1385 OUTS (outf, dregs (dst));
1386 OUTS (outf, " <<= ");
1387 OUTS (outf, dregs (src));
1388 }
1389 else if (opc == 3)
1390 {
1391 OUTS (outf, dregs (dst));
1392 OUTS (outf, " *= ");
1393 OUTS (outf, dregs (src));
1394 }
1395 else if (opc == 4)
1396 {
1397 OUTS (outf, dregs (dst));
1398 OUTS (outf, " = (");
1399 OUTS (outf, dregs (dst));
1400 OUTS (outf, " + ");
1401 OUTS (outf, dregs (src));
1402 OUTS (outf, ") << 0x1");
1403 }
1404 else if (opc == 5)
1405 {
1406 OUTS (outf, dregs (dst));
1407 OUTS (outf, " = (");
1408 OUTS (outf, dregs (dst));
1409 OUTS (outf, " + ");
1410 OUTS (outf, dregs (src));
1411 OUTS (outf, ") << 0x2");
1412 }
1413 else if (opc == 8)
1414 {
1415 OUTS (outf, "DIVQ (");
1416 OUTS (outf, dregs (dst));
1417 OUTS (outf, ", ");
1418 OUTS (outf, dregs (src));
1419 OUTS (outf, ")");
1420 }
1421 else if (opc == 9)
1422 {
1423 OUTS (outf, "DIVS (");
1424 OUTS (outf, dregs (dst));
1425 OUTS (outf, ", ");
1426 OUTS (outf, dregs (src));
1427 OUTS (outf, ")");
1428 }
1429 else if (opc == 10)
1430 {
1431 OUTS (outf, dregs (dst));
1432 OUTS (outf, " = ");
1433 OUTS (outf, dregs_lo (src));
1434 OUTS (outf, " (X)");
1435 }
1436 else if (opc == 11)
1437 {
1438 OUTS (outf, dregs (dst));
1439 OUTS (outf, " = ");
1440 OUTS (outf, dregs_lo (src));
1441 OUTS (outf, " (Z)");
1442 }
1443 else if (opc == 12)
1444 {
1445 OUTS (outf, dregs (dst));
1446 OUTS (outf, " = ");
1447 OUTS (outf, dregs_byte (src));
1448 OUTS (outf, " (X)");
1449 }
1450 else if (opc == 13)
1451 {
1452 OUTS (outf, dregs (dst));
1453 OUTS (outf, " = ");
1454 OUTS (outf, dregs_byte (src));
1455 OUTS (outf, " (Z)");
1456 }
1457 else if (opc == 14)
1458 {
1459 OUTS (outf, dregs (dst));
1460 OUTS (outf, " = -");
1461 OUTS (outf, dregs (src));
1462 }
1463 else if (opc == 15)
1464 {
1465 OUTS (outf, dregs (dst));
1466 OUTS (outf, " =~ ");
1467 OUTS (outf, dregs (src));
1468 }
1469 else
1470 return 0;
1471
1472 return 2;
1473 }
1474
1475 static int
1476 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1477 {
1478 /* PTR2op
1479 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1480 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1481 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1482 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1483 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1484 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1485
1486 if (opc == 0)
1487 {
1488 OUTS (outf, pregs (dst));
1489 OUTS (outf, " -= ");
1490 OUTS (outf, pregs (src));
1491 }
1492 else if (opc == 1)
1493 {
1494 OUTS (outf, pregs (dst));
1495 OUTS (outf, " = ");
1496 OUTS (outf, pregs (src));
1497 OUTS (outf, " << 0x2");
1498 }
1499 else if (opc == 3)
1500 {
1501 OUTS (outf, pregs (dst));
1502 OUTS (outf, " = ");
1503 OUTS (outf, pregs (src));
1504 OUTS (outf, " >> 0x2");
1505 }
1506 else if (opc == 4)
1507 {
1508 OUTS (outf, pregs (dst));
1509 OUTS (outf, " = ");
1510 OUTS (outf, pregs (src));
1511 OUTS (outf, " >> 0x1");
1512 }
1513 else if (opc == 5)
1514 {
1515 OUTS (outf, pregs (dst));
1516 OUTS (outf, " += ");
1517 OUTS (outf, pregs (src));
1518 OUTS (outf, " (BREV)");
1519 }
1520 else if (opc == 6)
1521 {
1522 OUTS (outf, pregs (dst));
1523 OUTS (outf, " = (");
1524 OUTS (outf, pregs (dst));
1525 OUTS (outf, " + ");
1526 OUTS (outf, pregs (src));
1527 OUTS (outf, ") << 0x1");
1528 }
1529 else if (opc == 7)
1530 {
1531 OUTS (outf, pregs (dst));
1532 OUTS (outf, " = (");
1533 OUTS (outf, pregs (dst));
1534 OUTS (outf, " + ");
1535 OUTS (outf, pregs (src));
1536 OUTS (outf, ") << 0x2");
1537 }
1538 else
1539 return 0;
1540
1541 return 2;
1542 }
1543
1544 static int
1545 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1546 {
1547 /* LOGI2op
1548 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1549 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1550 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1551 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1552 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1553 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1554
1555 if (opc == 0)
1556 {
1557 OUTS (outf, "CC = !BITTST (");
1558 OUTS (outf, dregs (dst));
1559 OUTS (outf, ", ");
1560 OUTS (outf, uimm5 (src));
1561 OUTS (outf, ");\t\t/* bit");
1562 OUTS (outf, imm7d (src));
1563 OUTS (outf, " */");
1564 comment = 1;
1565 }
1566 else if (opc == 1)
1567 {
1568 OUTS (outf, "CC = BITTST (");
1569 OUTS (outf, dregs (dst));
1570 OUTS (outf, ", ");
1571 OUTS (outf, uimm5 (src));
1572 OUTS (outf, ");\t\t/* bit");
1573 OUTS (outf, imm7d (src));
1574 OUTS (outf, " */");
1575 comment = 1;
1576 }
1577 else if (opc == 2)
1578 {
1579 OUTS (outf, "BITSET (");
1580 OUTS (outf, dregs (dst));
1581 OUTS (outf, ", ");
1582 OUTS (outf, uimm5 (src));
1583 OUTS (outf, ");\t\t/* bit");
1584 OUTS (outf, imm7d (src));
1585 OUTS (outf, " */");
1586 comment = 1;
1587 }
1588 else if (opc == 3)
1589 {
1590 OUTS (outf, "BITTGL (");
1591 OUTS (outf, dregs (dst));
1592 OUTS (outf, ", ");
1593 OUTS (outf, uimm5 (src));
1594 OUTS (outf, ");\t\t/* bit");
1595 OUTS (outf, imm7d (src));
1596 OUTS (outf, " */");
1597 comment = 1;
1598 }
1599 else if (opc == 4)
1600 {
1601 OUTS (outf, "BITCLR (");
1602 OUTS (outf, dregs (dst));
1603 OUTS (outf, ", ");
1604 OUTS (outf, uimm5 (src));
1605 OUTS (outf, ");\t\t/* bit");
1606 OUTS (outf, imm7d (src));
1607 OUTS (outf, " */");
1608 comment = 1;
1609 }
1610 else if (opc == 5)
1611 {
1612 OUTS (outf, dregs (dst));
1613 OUTS (outf, " >>>= ");
1614 OUTS (outf, uimm5 (src));
1615 }
1616 else if (opc == 6)
1617 {
1618 OUTS (outf, dregs (dst));
1619 OUTS (outf, " >>= ");
1620 OUTS (outf, uimm5 (src));
1621 }
1622 else if (opc == 7)
1623 {
1624 OUTS (outf, dregs (dst));
1625 OUTS (outf, " <<= ");
1626 OUTS (outf, uimm5 (src));
1627 }
1628 else
1629 return 0;
1630
1631 return 2;
1632 }
1633
1634 static int
1635 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1636 {
1637 /* COMP3op
1638 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1639 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1640 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1641 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1642 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1643 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1644 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1645
1646 if (opc == 5 && src1 == src0)
1647 {
1648 OUTS (outf, pregs (dst));
1649 OUTS (outf, " = ");
1650 OUTS (outf, pregs (src0));
1651 OUTS (outf, " << 0x1");
1652 }
1653 else if (opc == 1)
1654 {
1655 OUTS (outf, dregs (dst));
1656 OUTS (outf, " = ");
1657 OUTS (outf, dregs (src0));
1658 OUTS (outf, " - ");
1659 OUTS (outf, dregs (src1));
1660 }
1661 else if (opc == 2)
1662 {
1663 OUTS (outf, dregs (dst));
1664 OUTS (outf, " = ");
1665 OUTS (outf, dregs (src0));
1666 OUTS (outf, " & ");
1667 OUTS (outf, dregs (src1));
1668 }
1669 else if (opc == 3)
1670 {
1671 OUTS (outf, dregs (dst));
1672 OUTS (outf, " = ");
1673 OUTS (outf, dregs (src0));
1674 OUTS (outf, " | ");
1675 OUTS (outf, dregs (src1));
1676 }
1677 else if (opc == 4)
1678 {
1679 OUTS (outf, dregs (dst));
1680 OUTS (outf, " = ");
1681 OUTS (outf, dregs (src0));
1682 OUTS (outf, " ^ ");
1683 OUTS (outf, dregs (src1));
1684 }
1685 else if (opc == 5)
1686 {
1687 OUTS (outf, pregs (dst));
1688 OUTS (outf, " = ");
1689 OUTS (outf, pregs (src0));
1690 OUTS (outf, " + ");
1691 OUTS (outf, pregs (src1));
1692 }
1693 else if (opc == 6)
1694 {
1695 OUTS (outf, pregs (dst));
1696 OUTS (outf, " = ");
1697 OUTS (outf, pregs (src0));
1698 OUTS (outf, " + (");
1699 OUTS (outf, pregs (src1));
1700 OUTS (outf, " << 0x1)");
1701 }
1702 else if (opc == 7)
1703 {
1704 OUTS (outf, pregs (dst));
1705 OUTS (outf, " = ");
1706 OUTS (outf, pregs (src0));
1707 OUTS (outf, " + (");
1708 OUTS (outf, pregs (src1));
1709 OUTS (outf, " << 0x2)");
1710 }
1711 else if (opc == 0)
1712 {
1713 OUTS (outf, dregs (dst));
1714 OUTS (outf, " = ");
1715 OUTS (outf, dregs (src0));
1716 OUTS (outf, " + ");
1717 OUTS (outf, dregs (src1));
1718 }
1719 else
1720 return 0;
1721
1722 return 2;
1723 }
1724
1725 static int
1726 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1727 {
1728 /* COMPI2opD
1729 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1730 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1731 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1732 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1733 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1734 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1735
1736 bu32 *pval = get_allreg (0, dst);
1737
1738 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1739 to combine them, so it prints out the right values.
1740 Here we keep track of the registers. */
1741 if (op == 0)
1742 {
1743 *pval = imm7_val (src);
1744 if (src & 0x40)
1745 *pval |= 0xFFFFFF80;
1746 else
1747 *pval &= 0x7F;
1748 }
1749
1750 if (op == 0)
1751 {
1752 OUTS (outf, dregs (dst));
1753 OUTS (outf, " = ");
1754 OUTS (outf, imm7 (src));
1755 OUTS (outf, " (X);\t\t/*\t\t");
1756 OUTS (outf, dregs (dst));
1757 OUTS (outf, "=");
1758 OUTS (outf, uimm32 (*pval));
1759 OUTS (outf, "(");
1760 OUTS (outf, imm32 (*pval));
1761 OUTS (outf, ") */");
1762 comment = 1;
1763 }
1764 else if (op == 1)
1765 {
1766 OUTS (outf, dregs (dst));
1767 OUTS (outf, " += ");
1768 OUTS (outf, imm7 (src));
1769 OUTS (outf, ";\t\t/* (");
1770 OUTS (outf, imm7d (src));
1771 OUTS (outf, ") */");
1772 comment = 1;
1773 }
1774 else
1775 return 0;
1776
1777 return 2;
1778 }
1779
1780 static int
1781 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1782 {
1783 /* COMPI2opP
1784 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1785 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1786 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1787 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1788 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1789 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1790
1791 bu32 *pval = get_allreg (1, dst);
1792
1793 if (op == 0)
1794 {
1795 *pval = imm7_val (src);
1796 if (src & 0x40)
1797 *pval |= 0xFFFFFF80;
1798 else
1799 *pval &= 0x7F;
1800 }
1801
1802 if (op == 0)
1803 {
1804 OUTS (outf, pregs (dst));
1805 OUTS (outf, " = ");
1806 OUTS (outf, imm7 (src));
1807 OUTS (outf, " (X);\t\t/*\t\t");
1808 OUTS (outf, pregs (dst));
1809 OUTS (outf, "=");
1810 OUTS (outf, uimm32 (*pval));
1811 OUTS (outf, "(");
1812 OUTS (outf, imm32 (*pval));
1813 OUTS (outf, ") */");
1814 comment = 1;
1815 }
1816 else if (op == 1)
1817 {
1818 OUTS (outf, pregs (dst));
1819 OUTS (outf, " += ");
1820 OUTS (outf, imm7 (src));
1821 OUTS (outf, ";\t\t/* (");
1822 OUTS (outf, imm7d (src));
1823 OUTS (outf, ") */");
1824 comment = 1;
1825 }
1826 else
1827 return 0;
1828
1829 return 2;
1830 }
1831
1832 static int
1833 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1834 {
1835 /* LDSTpmod
1836 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1837 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1838 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1839 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1840 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1841 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1842 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1843 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1844
1845 if (aop == 1 && W == 0 && idx == ptr)
1846 {
1847 OUTS (outf, dregs_lo (reg));
1848 OUTS (outf, " = W[");
1849 OUTS (outf, pregs (ptr));
1850 OUTS (outf, "]");
1851 }
1852 else if (aop == 2 && W == 0 && idx == ptr)
1853 {
1854 OUTS (outf, dregs_hi (reg));
1855 OUTS (outf, " = W[");
1856 OUTS (outf, pregs (ptr));
1857 OUTS (outf, "]");
1858 }
1859 else if (aop == 1 && W == 1 && idx == ptr)
1860 {
1861 OUTS (outf, "W[");
1862 OUTS (outf, pregs (ptr));
1863 OUTS (outf, "] = ");
1864 OUTS (outf, dregs_lo (reg));
1865 }
1866 else if (aop == 2 && W == 1 && idx == ptr)
1867 {
1868 OUTS (outf, "W[");
1869 OUTS (outf, pregs (ptr));
1870 OUTS (outf, "] = ");
1871 OUTS (outf, dregs_hi (reg));
1872 }
1873 else if (aop == 0 && W == 0)
1874 {
1875 OUTS (outf, dregs (reg));
1876 OUTS (outf, " = [");
1877 OUTS (outf, pregs (ptr));
1878 OUTS (outf, " ++ ");
1879 OUTS (outf, pregs (idx));
1880 OUTS (outf, "]");
1881 }
1882 else if (aop == 1 && W == 0)
1883 {
1884 OUTS (outf, dregs_lo (reg));
1885 OUTS (outf, " = W[");
1886 OUTS (outf, pregs (ptr));
1887 OUTS (outf, " ++ ");
1888 OUTS (outf, pregs (idx));
1889 OUTS (outf, "]");
1890 }
1891 else if (aop == 2 && W == 0)
1892 {
1893 OUTS (outf, dregs_hi (reg));
1894 OUTS (outf, " = W[");
1895 OUTS (outf, pregs (ptr));
1896 OUTS (outf, " ++ ");
1897 OUTS (outf, pregs (idx));
1898 OUTS (outf, "]");
1899 }
1900 else if (aop == 3 && W == 0)
1901 {
1902 OUTS (outf, dregs (reg));
1903 OUTS (outf, " = W[");
1904 OUTS (outf, pregs (ptr));
1905 OUTS (outf, " ++ ");
1906 OUTS (outf, pregs (idx));
1907 OUTS (outf, "] (Z)");
1908 }
1909 else if (aop == 3 && W == 1)
1910 {
1911 OUTS (outf, dregs (reg));
1912 OUTS (outf, " = W[");
1913 OUTS (outf, pregs (ptr));
1914 OUTS (outf, " ++ ");
1915 OUTS (outf, pregs (idx));
1916 OUTS (outf, "] (X)");
1917 }
1918 else if (aop == 0 && W == 1)
1919 {
1920 OUTS (outf, "[");
1921 OUTS (outf, pregs (ptr));
1922 OUTS (outf, " ++ ");
1923 OUTS (outf, pregs (idx));
1924 OUTS (outf, "] = ");
1925 OUTS (outf, dregs (reg));
1926 }
1927 else if (aop == 1 && W == 1)
1928 {
1929 OUTS (outf, "W[");
1930 OUTS (outf, pregs (ptr));
1931 OUTS (outf, " ++ ");
1932 OUTS (outf, pregs (idx));
1933 OUTS (outf, "] = ");
1934 OUTS (outf, dregs_lo (reg));
1935 }
1936 else if (aop == 2 && W == 1)
1937 {
1938 OUTS (outf, "W[");
1939 OUTS (outf, pregs (ptr));
1940 OUTS (outf, " ++ ");
1941 OUTS (outf, pregs (idx));
1942 OUTS (outf, "] = ");
1943 OUTS (outf, dregs_hi (reg));
1944 }
1945 else
1946 return 0;
1947
1948 return 2;
1949 }
1950
1951 static int
1952 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1953 {
1954 /* dagMODim
1955 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1956 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1957 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1958 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1959 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1960 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1961 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1962
1963 if (op == 0 && br == 1)
1964 {
1965 OUTS (outf, iregs (i));
1966 OUTS (outf, " += ");
1967 OUTS (outf, mregs (m));
1968 OUTS (outf, " (BREV)");
1969 }
1970 else if (op == 0)
1971 {
1972 OUTS (outf, iregs (i));
1973 OUTS (outf, " += ");
1974 OUTS (outf, mregs (m));
1975 }
1976 else if (op == 1)
1977 {
1978 OUTS (outf, iregs (i));
1979 OUTS (outf, " -= ");
1980 OUTS (outf, mregs (m));
1981 }
1982 else
1983 return 0;
1984
1985 return 2;
1986 }
1987
1988 static int
1989 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
1990 {
1991 /* dagMODik
1992 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1993 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
1994 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1995 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
1996 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
1997
1998 if (op == 0)
1999 {
2000 OUTS (outf, iregs (i));
2001 OUTS (outf, " += 0x2");
2002 }
2003 else if (op == 1)
2004 {
2005 OUTS (outf, iregs (i));
2006 OUTS (outf, " -= 0x2");
2007 }
2008 else if (op == 2)
2009 {
2010 OUTS (outf, iregs (i));
2011 OUTS (outf, " += 0x4");
2012 }
2013 else if (op == 3)
2014 {
2015 OUTS (outf, iregs (i));
2016 OUTS (outf, " -= 0x4");
2017 }
2018 else
2019 return 0;
2020
2021 if (! parallel )
2022 {
2023 OUTS (outf, ";\t\t/* ( ");
2024 if (op == 0 || op == 1)
2025 OUTS (outf, "2");
2026 else if (op == 2 || op == 3)
2027 OUTS (outf, "4");
2028 OUTS (outf, ") */");
2029 comment = 1;
2030 }
2031
2032 return 2;
2033 }
2034
2035 static int
2036 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2037 {
2038 /* dspLDST
2039 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2040 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2041 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2042 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2043 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2044 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2045 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2046 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2047
2048 if (aop == 0 && W == 0 && m == 0)
2049 {
2050 OUTS (outf, dregs (reg));
2051 OUTS (outf, " = [");
2052 OUTS (outf, iregs (i));
2053 OUTS (outf, "++]");
2054 }
2055 else if (aop == 0 && W == 0 && m == 1)
2056 {
2057 OUTS (outf, dregs_lo (reg));
2058 OUTS (outf, " = W[");
2059 OUTS (outf, iregs (i));
2060 OUTS (outf, "++]");
2061 }
2062 else if (aop == 0 && W == 0 && m == 2)
2063 {
2064 OUTS (outf, dregs_hi (reg));
2065 OUTS (outf, " = W[");
2066 OUTS (outf, iregs (i));
2067 OUTS (outf, "++]");
2068 }
2069 else if (aop == 1 && W == 0 && m == 0)
2070 {
2071 OUTS (outf, dregs (reg));
2072 OUTS (outf, " = [");
2073 OUTS (outf, iregs (i));
2074 OUTS (outf, "--]");
2075 }
2076 else if (aop == 1 && W == 0 && m == 1)
2077 {
2078 OUTS (outf, dregs_lo (reg));
2079 OUTS (outf, " = W[");
2080 OUTS (outf, iregs (i));
2081 OUTS (outf, "--]");
2082 }
2083 else if (aop == 1 && W == 0 && m == 2)
2084 {
2085 OUTS (outf, dregs_hi (reg));
2086 OUTS (outf, " = W[");
2087 OUTS (outf, iregs (i));
2088 OUTS (outf, "--]");
2089 }
2090 else if (aop == 2 && W == 0 && m == 0)
2091 {
2092 OUTS (outf, dregs (reg));
2093 OUTS (outf, " = [");
2094 OUTS (outf, iregs (i));
2095 OUTS (outf, "]");
2096 }
2097 else if (aop == 2 && W == 0 && m == 1)
2098 {
2099 OUTS (outf, dregs_lo (reg));
2100 OUTS (outf, " = W[");
2101 OUTS (outf, iregs (i));
2102 OUTS (outf, "]");
2103 }
2104 else if (aop == 2 && W == 0 && m == 2)
2105 {
2106 OUTS (outf, dregs_hi (reg));
2107 OUTS (outf, " = W[");
2108 OUTS (outf, iregs (i));
2109 OUTS (outf, "]");
2110 }
2111 else if (aop == 0 && W == 1 && m == 0)
2112 {
2113 OUTS (outf, "[");
2114 OUTS (outf, iregs (i));
2115 OUTS (outf, "++] = ");
2116 OUTS (outf, dregs (reg));
2117 }
2118 else if (aop == 0 && W == 1 && m == 1)
2119 {
2120 OUTS (outf, "W[");
2121 OUTS (outf, iregs (i));
2122 OUTS (outf, "++] = ");
2123 OUTS (outf, dregs_lo (reg));
2124 }
2125 else if (aop == 0 && W == 1 && m == 2)
2126 {
2127 OUTS (outf, "W[");
2128 OUTS (outf, iregs (i));
2129 OUTS (outf, "++] = ");
2130 OUTS (outf, dregs_hi (reg));
2131 }
2132 else if (aop == 1 && W == 1 && m == 0)
2133 {
2134 OUTS (outf, "[");
2135 OUTS (outf, iregs (i));
2136 OUTS (outf, "--] = ");
2137 OUTS (outf, dregs (reg));
2138 }
2139 else if (aop == 1 && W == 1 && m == 1)
2140 {
2141 OUTS (outf, "W[");
2142 OUTS (outf, iregs (i));
2143 OUTS (outf, "--] = ");
2144 OUTS (outf, dregs_lo (reg));
2145 }
2146 else if (aop == 1 && W == 1 && m == 2)
2147 {
2148 OUTS (outf, "W[");
2149 OUTS (outf, iregs (i));
2150 OUTS (outf, "--] = ");
2151 OUTS (outf, dregs_hi (reg));
2152 }
2153 else if (aop == 2 && W == 1 && m == 0)
2154 {
2155 OUTS (outf, "[");
2156 OUTS (outf, iregs (i));
2157 OUTS (outf, "] = ");
2158 OUTS (outf, dregs (reg));
2159 }
2160 else if (aop == 2 && W == 1 && m == 1)
2161 {
2162 OUTS (outf, "W[");
2163 OUTS (outf, iregs (i));
2164 OUTS (outf, "] = ");
2165 OUTS (outf, dregs_lo (reg));
2166 }
2167 else if (aop == 2 && W == 1 && m == 2)
2168 {
2169 OUTS (outf, "W[");
2170 OUTS (outf, iregs (i));
2171 OUTS (outf, "] = ");
2172 OUTS (outf, dregs_hi (reg));
2173 }
2174 else if (aop == 3 && W == 0)
2175 {
2176 OUTS (outf, dregs (reg));
2177 OUTS (outf, " = [");
2178 OUTS (outf, iregs (i));
2179 OUTS (outf, " ++ ");
2180 OUTS (outf, mregs (m));
2181 OUTS (outf, "]");
2182 }
2183 else if (aop == 3 && W == 1)
2184 {
2185 OUTS (outf, "[");
2186 OUTS (outf, iregs (i));
2187 OUTS (outf, " ++ ");
2188 OUTS (outf, mregs (m));
2189 OUTS (outf, "] = ");
2190 OUTS (outf, dregs (reg));
2191 }
2192 else
2193 return 0;
2194
2195 return 2;
2196 }
2197
2198 static int
2199 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2200 {
2201 /* LDST
2202 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2203 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2204 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2205 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2206 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2207 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2208 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2209 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2210 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2211
2212 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2213 {
2214 OUTS (outf, dregs (reg));
2215 OUTS (outf, " = [");
2216 OUTS (outf, pregs (ptr));
2217 OUTS (outf, "++]");
2218 }
2219 else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
2220 {
2221 OUTS (outf, pregs (reg));
2222 OUTS (outf, " = [");
2223 OUTS (outf, pregs (ptr));
2224 OUTS (outf, "++]");
2225 }
2226 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2227 {
2228 OUTS (outf, dregs (reg));
2229 OUTS (outf, " = W[");
2230 OUTS (outf, pregs (ptr));
2231 OUTS (outf, "++] (Z)");
2232 }
2233 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2234 {
2235 OUTS (outf, dregs (reg));
2236 OUTS (outf, " = W[");
2237 OUTS (outf, pregs (ptr));
2238 OUTS (outf, "++] (X)");
2239 }
2240 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2241 {
2242 OUTS (outf, dregs (reg));
2243 OUTS (outf, " = B[");
2244 OUTS (outf, pregs (ptr));
2245 OUTS (outf, "++] (Z)");
2246 }
2247 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2248 {
2249 OUTS (outf, dregs (reg));
2250 OUTS (outf, " = B[");
2251 OUTS (outf, pregs (ptr));
2252 OUTS (outf, "++] (X)");
2253 }
2254 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2255 {
2256 OUTS (outf, dregs (reg));
2257 OUTS (outf, " = [");
2258 OUTS (outf, pregs (ptr));
2259 OUTS (outf, "--]");
2260 }
2261 else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
2262 {
2263 OUTS (outf, pregs (reg));
2264 OUTS (outf, " = [");
2265 OUTS (outf, pregs (ptr));
2266 OUTS (outf, "--]");
2267 }
2268 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2269 {
2270 OUTS (outf, dregs (reg));
2271 OUTS (outf, " = W[");
2272 OUTS (outf, pregs (ptr));
2273 OUTS (outf, "--] (Z)");
2274 }
2275 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2276 {
2277 OUTS (outf, dregs (reg));
2278 OUTS (outf, " = W[");
2279 OUTS (outf, pregs (ptr));
2280 OUTS (outf, "--] (X)");
2281 }
2282 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2283 {
2284 OUTS (outf, dregs (reg));
2285 OUTS (outf, " = B[");
2286 OUTS (outf, pregs (ptr));
2287 OUTS (outf, "--] (Z)");
2288 }
2289 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2290 {
2291 OUTS (outf, dregs (reg));
2292 OUTS (outf, " = B[");
2293 OUTS (outf, pregs (ptr));
2294 OUTS (outf, "--] (X)");
2295 }
2296 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2297 {
2298 OUTS (outf, dregs (reg));
2299 OUTS (outf, " = [");
2300 OUTS (outf, pregs (ptr));
2301 OUTS (outf, "]");
2302 }
2303 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2304 {
2305 OUTS (outf, pregs (reg));
2306 OUTS (outf, " = [");
2307 OUTS (outf, pregs (ptr));
2308 OUTS (outf, "]");
2309 }
2310 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2311 {
2312 OUTS (outf, dregs (reg));
2313 OUTS (outf, " = W[");
2314 OUTS (outf, pregs (ptr));
2315 OUTS (outf, "] (Z)");
2316 }
2317 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2318 {
2319 OUTS (outf, dregs (reg));
2320 OUTS (outf, " = W[");
2321 OUTS (outf, pregs (ptr));
2322 OUTS (outf, "] (X)");
2323 }
2324 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2325 {
2326 OUTS (outf, dregs (reg));
2327 OUTS (outf, " = B[");
2328 OUTS (outf, pregs (ptr));
2329 OUTS (outf, "] (Z)");
2330 }
2331 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2332 {
2333 OUTS (outf, dregs (reg));
2334 OUTS (outf, " = B[");
2335 OUTS (outf, pregs (ptr));
2336 OUTS (outf, "] (X)");
2337 }
2338 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2339 {
2340 OUTS (outf, "[");
2341 OUTS (outf, pregs (ptr));
2342 OUTS (outf, "++] = ");
2343 OUTS (outf, dregs (reg));
2344 }
2345 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2346 {
2347 OUTS (outf, "[");
2348 OUTS (outf, pregs (ptr));
2349 OUTS (outf, "++] = ");
2350 OUTS (outf, pregs (reg));
2351 }
2352 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2353 {
2354 OUTS (outf, "W[");
2355 OUTS (outf, pregs (ptr));
2356 OUTS (outf, "++] = ");
2357 OUTS (outf, dregs (reg));
2358 }
2359 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2360 {
2361 OUTS (outf, "B[");
2362 OUTS (outf, pregs (ptr));
2363 OUTS (outf, "++] = ");
2364 OUTS (outf, dregs (reg));
2365 }
2366 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2367 {
2368 OUTS (outf, "[");
2369 OUTS (outf, pregs (ptr));
2370 OUTS (outf, "--] = ");
2371 OUTS (outf, dregs (reg));
2372 }
2373 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2374 {
2375 OUTS (outf, "[");
2376 OUTS (outf, pregs (ptr));
2377 OUTS (outf, "--] = ");
2378 OUTS (outf, pregs (reg));
2379 }
2380 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2381 {
2382 OUTS (outf, "W[");
2383 OUTS (outf, pregs (ptr));
2384 OUTS (outf, "--] = ");
2385 OUTS (outf, dregs (reg));
2386 }
2387 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2388 {
2389 OUTS (outf, "B[");
2390 OUTS (outf, pregs (ptr));
2391 OUTS (outf, "--] = ");
2392 OUTS (outf, dregs (reg));
2393 }
2394 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2395 {
2396 OUTS (outf, "[");
2397 OUTS (outf, pregs (ptr));
2398 OUTS (outf, "] = ");
2399 OUTS (outf, dregs (reg));
2400 }
2401 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2402 {
2403 OUTS (outf, "[");
2404 OUTS (outf, pregs (ptr));
2405 OUTS (outf, "] = ");
2406 OUTS (outf, pregs (reg));
2407 }
2408 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2409 {
2410 OUTS (outf, "W[");
2411 OUTS (outf, pregs (ptr));
2412 OUTS (outf, "] = ");
2413 OUTS (outf, dregs (reg));
2414 }
2415 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2416 {
2417 OUTS (outf, "B[");
2418 OUTS (outf, pregs (ptr));
2419 OUTS (outf, "] = ");
2420 OUTS (outf, dregs (reg));
2421 }
2422 else
2423 return 0;
2424
2425 return 2;
2426 }
2427
2428 static int
2429 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2430 {
2431 /* LDSTiiFP
2432 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2433 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2434 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2435 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2436 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2437 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2438
2439 if (W == 0)
2440 {
2441 OUTS (outf, dpregs (reg));
2442 OUTS (outf, " = [FP ");
2443 OUTS (outf, negimm5s4 (offset));
2444 OUTS (outf, "]");
2445 }
2446 else if (W == 1)
2447 {
2448 OUTS (outf, "[FP ");
2449 OUTS (outf, negimm5s4 (offset));
2450 OUTS (outf, "] = ");
2451 OUTS (outf, dpregs (reg));
2452 }
2453 else
2454 return 0;
2455
2456 return 2;
2457 }
2458
2459 static int
2460 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2461 {
2462 /* LDSTii
2463 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2464 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2465 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2466 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2467 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2468 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2469 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2470 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2471
2472 if (W == 0 && op == 0)
2473 {
2474 OUTS (outf, dregs (reg));
2475 OUTS (outf, " = [");
2476 OUTS (outf, pregs (ptr));
2477 OUTS (outf, " + ");
2478 OUTS (outf, uimm4s4 (offset));
2479 OUTS (outf, "]");
2480 }
2481 else if (W == 0 && op == 1)
2482 {
2483 OUTS (outf, dregs (reg));
2484 OUTS (outf, " = W[");
2485 OUTS (outf, pregs (ptr));
2486 OUTS (outf, " + ");
2487 OUTS (outf, uimm4s2 (offset));
2488 OUTS (outf, "] (Z)");
2489 }
2490 else if (W == 0 && op == 2)
2491 {
2492 OUTS (outf, dregs (reg));
2493 OUTS (outf, " = W[");
2494 OUTS (outf, pregs (ptr));
2495 OUTS (outf, " + ");
2496 OUTS (outf, uimm4s2 (offset));
2497 OUTS (outf, "] (X)");
2498 }
2499 else if (W == 0 && op == 3)
2500 {
2501 OUTS (outf, pregs (reg));
2502 OUTS (outf, " = [");
2503 OUTS (outf, pregs (ptr));
2504 OUTS (outf, " + ");
2505 OUTS (outf, uimm4s4 (offset));
2506 OUTS (outf, "]");
2507 }
2508 else if (W == 1 && op == 0)
2509 {
2510 OUTS (outf, "[");
2511 OUTS (outf, pregs (ptr));
2512 OUTS (outf, " + ");
2513 OUTS (outf, uimm4s4 (offset));
2514 OUTS (outf, "] = ");
2515 OUTS (outf, dregs (reg));
2516 }
2517 else if (W == 1 && op == 1)
2518 {
2519 OUTS (outf, "W[");
2520 OUTS (outf, pregs (ptr));
2521 OUTS (outf, " + ");
2522 OUTS (outf, uimm4s2 (offset));
2523 OUTS (outf, "] = ");
2524 OUTS (outf, dregs (reg));
2525 }
2526 else if (W == 1 && op == 3)
2527 {
2528 OUTS (outf, "[");
2529 OUTS (outf, pregs (ptr));
2530 OUTS (outf, " + ");
2531 OUTS (outf, uimm4s4 (offset));
2532 OUTS (outf, "] = ");
2533 OUTS (outf, pregs (reg));
2534 }
2535 else
2536 return 0;
2537
2538 return 2;
2539 }
2540
2541 static int
2542 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2543 {
2544 /* LoopSetup
2545 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2546 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2547 |.reg...........| - | - |.eoffset...............................|
2548 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2549 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2550 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2551 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2552 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2553 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2554
2555 if (rop == 0)
2556 {
2557 OUTS (outf, "LSETUP");
2558 OUTS (outf, "(0x");
2559 OUTS (outf, pcrel4 (soffset));
2560 OUTS (outf, ", 0x");
2561 OUTS (outf, lppcrel10 (eoffset));
2562 OUTS (outf, ") ");
2563 OUTS (outf, counters (c));
2564 }
2565 else if (rop == 1)
2566 {
2567 OUTS (outf, "LSETUP");
2568 OUTS (outf, "(0x");
2569 OUTS (outf, pcrel4 (soffset));
2570 OUTS (outf, ", 0x");
2571 OUTS (outf, lppcrel10 (eoffset));
2572 OUTS (outf, ") ");
2573 OUTS (outf, counters (c));
2574 OUTS (outf, " = ");
2575 OUTS (outf, pregs (reg));
2576 }
2577 else if (rop == 3)
2578 {
2579 OUTS (outf, "LSETUP");
2580 OUTS (outf, "(0x");
2581 OUTS (outf, pcrel4 (soffset));
2582 OUTS (outf, ", 0x");
2583 OUTS (outf, lppcrel10 (eoffset));
2584 OUTS (outf, ") ");
2585 OUTS (outf, counters (c));
2586 OUTS (outf, " = ");
2587 OUTS (outf, pregs (reg));
2588 OUTS (outf, " >> 0x1");
2589 }
2590 else
2591 return 0;
2592
2593 return 4;
2594 }
2595
2596 static int
2597 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2598 {
2599 /* LDIMMhalf
2600 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2601 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2602 |.hword.........................................................|
2603 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2604 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2605 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2606 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2607 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2608 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2609 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2610
2611 bu32 *pval = get_allreg (grp, reg);
2612
2613 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2614 to combine them, so it prints out the right values.
2615 Here we keep track of the registers. */
2616 if (H == 0 && S == 1 && Z == 0)
2617 {
2618 /* regs = imm16 (x) */
2619 *pval = imm16_val (hword);
2620 if (hword & 0x8000)
2621 *pval |= 0xFFFF0000;
2622 else
2623 *pval &= 0xFFFF;
2624 }
2625 else if (H == 0 && S == 0 && Z == 1)
2626 {
2627 /* regs = luimm16 (Z) */
2628 *pval = luimm16_val (hword);
2629 *pval &= 0xFFFF;
2630 }
2631 else if (H == 0 && S == 0 && Z == 0)
2632 {
2633 /* regs_lo = luimm16 */
2634 *pval &= 0xFFFF0000;
2635 *pval |= luimm16_val (hword);
2636 }
2637 else if (H == 1 && S == 0 && Z == 0)
2638 {
2639 /* regs_hi = huimm16 */
2640 *pval &= 0xFFFF;
2641 *pval |= luimm16_val (hword) << 16;
2642 }
2643
2644 /* Here we do the disassembly */
2645 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2646 {
2647 OUTS (outf, dregs_lo (reg));
2648 OUTS (outf, " = ");
2649 OUTS (outf, uimm16 (hword));
2650 }
2651 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2652 {
2653 OUTS (outf, dregs_hi (reg));
2654 OUTS (outf, " = ");
2655 OUTS (outf, uimm16 (hword));
2656 }
2657 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2658 {
2659 OUTS (outf, dregs (reg));
2660 OUTS (outf, " = ");
2661 OUTS (outf, imm16 (hword));
2662 OUTS (outf, " (X)");
2663 }
2664 else if (H == 0 && S == 1 && Z == 0)
2665 {
2666 OUTS (outf, regs (reg, grp));
2667 OUTS (outf, " = ");
2668 OUTS (outf, imm16 (hword));
2669 OUTS (outf, " (X)");
2670 }
2671 else if (H == 0 && S == 0 && Z == 1)
2672 {
2673 OUTS (outf, regs (reg, grp));
2674 OUTS (outf, " = ");
2675 OUTS (outf, uimm16 (hword));
2676 OUTS (outf, " (Z)");
2677 }
2678 else if (H == 0 && S == 0 && Z == 0)
2679 {
2680 OUTS (outf, regs_lo (reg, grp));
2681 OUTS (outf, " = ");
2682 OUTS (outf, uimm16 (hword));
2683 }
2684 else if (H == 1 && S == 0 && Z == 0)
2685 {
2686 OUTS (outf, regs_hi (reg, grp));
2687 OUTS (outf, " = ");
2688 OUTS (outf, uimm16 (hword));
2689 }
2690 else
2691 return 0;
2692
2693 /* And we print out the 32-bit value if it is a pointer. */
2694 if (S == 0 && Z == 0)
2695 {
2696 OUTS (outf, ";\t\t/* (");
2697 OUTS (outf, imm16d (hword));
2698 OUTS (outf, ")\t");
2699
2700 /* If it is an MMR, don't print the symbol. */
2701 if (*pval < 0xFFC00000 && grp == 1)
2702 {
2703 OUTS (outf, regs (reg, grp));
2704 OUTS (outf, "=0x");
2705 OUTS (outf, huimm32e (*pval));
2706 }
2707 else
2708 {
2709 OUTS (outf, regs (reg, grp));
2710 OUTS (outf, "=0x");
2711 OUTS (outf, huimm32e (*pval));
2712 OUTS (outf, "(");
2713 OUTS (outf, imm32 (*pval));
2714 OUTS (outf, ")");
2715 }
2716
2717 OUTS (outf, " */");
2718 comment = 1;
2719 }
2720 if (S == 1 || Z == 1)
2721 {
2722 OUTS (outf, ";\t\t/*\t\t");
2723 OUTS (outf, regs (reg, grp));
2724 OUTS (outf, "=0x");
2725 OUTS (outf, huimm32e (*pval));
2726 OUTS (outf, "(");
2727 OUTS (outf, imm32 (*pval));
2728 OUTS (outf, ") */");
2729 comment = 1;
2730 }
2731 return 4;
2732 }
2733
2734 static int
2735 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2736 {
2737 /* CALLa
2738 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2739 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2740 |.lsw...........................................................|
2741 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2742 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2743 int lsw = ((iw1 >> 0) & 0xffff);
2744 int msw = ((iw0 >> 0) & 0xff);
2745
2746 if (S == 1)
2747 OUTS (outf, "CALL 0x");
2748 else if (S == 0)
2749 OUTS (outf, "JUMP.L 0x");
2750 else
2751 return 0;
2752
2753 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2754 return 4;
2755 }
2756
2757 static int
2758 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2759 {
2760 /* LDSTidxI
2761 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2762 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2763 |.offset........................................................|
2764 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2765 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2766 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2767 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2768 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2769 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2770 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2771
2772 if (W == 0 && sz == 0 && Z == 0)
2773 {
2774 OUTS (outf, dregs (reg));
2775 OUTS (outf, " = [");
2776 OUTS (outf, pregs (ptr));
2777 OUTS (outf, " + ");
2778 OUTS (outf, imm16s4 (offset));
2779 OUTS (outf, "]");
2780 }
2781 else if (W == 0 && sz == 0 && Z == 1)
2782 {
2783 OUTS (outf, pregs (reg));
2784 OUTS (outf, " = [");
2785 OUTS (outf, pregs (ptr));
2786 OUTS (outf, " + ");
2787 OUTS (outf, imm16s4 (offset));
2788 OUTS (outf, "]");
2789 }
2790 else if (W == 0 && sz == 1 && Z == 0)
2791 {
2792 OUTS (outf, dregs (reg));
2793 OUTS (outf, " = W[");
2794 OUTS (outf, pregs (ptr));
2795 OUTS (outf, " + ");
2796 OUTS (outf, imm16s2 (offset));
2797 OUTS (outf, "] (Z)");
2798 }
2799 else if (W == 0 && sz == 1 && Z == 1)
2800 {
2801 OUTS (outf, dregs (reg));
2802 OUTS (outf, " = W[");
2803 OUTS (outf, pregs (ptr));
2804 OUTS (outf, " + ");
2805 OUTS (outf, imm16s2 (offset));
2806 OUTS (outf, "] (X)");
2807 }
2808 else if (W == 0 && sz == 2 && Z == 0)
2809 {
2810 OUTS (outf, dregs (reg));
2811 OUTS (outf, " = B[");
2812 OUTS (outf, pregs (ptr));
2813 OUTS (outf, " + ");
2814 OUTS (outf, imm16 (offset));
2815 OUTS (outf, "] (Z)");
2816 }
2817 else if (W == 0 && sz == 2 && Z == 1)
2818 {
2819 OUTS (outf, dregs (reg));
2820 OUTS (outf, " = B[");
2821 OUTS (outf, pregs (ptr));
2822 OUTS (outf, " + ");
2823 OUTS (outf, imm16 (offset));
2824 OUTS (outf, "] (X)");
2825 }
2826 else if (W == 1 && sz == 0 && Z == 0)
2827 {
2828 OUTS (outf, "[");
2829 OUTS (outf, pregs (ptr));
2830 OUTS (outf, " + ");
2831 OUTS (outf, imm16s4 (offset));
2832 OUTS (outf, "] = ");
2833 OUTS (outf, dregs (reg));
2834 }
2835 else if (W == 1 && sz == 0 && Z == 1)
2836 {
2837 OUTS (outf, "[");
2838 OUTS (outf, pregs (ptr));
2839 OUTS (outf, " + ");
2840 OUTS (outf, imm16s4 (offset));
2841 OUTS (outf, "] = ");
2842 OUTS (outf, pregs (reg));
2843 }
2844 else if (W == 1 && sz == 1 && Z == 0)
2845 {
2846 OUTS (outf, "W[");
2847 OUTS (outf, pregs (ptr));
2848 OUTS (outf, " + ");
2849 OUTS (outf, imm16s2 (offset));
2850 OUTS (outf, "] = ");
2851 OUTS (outf, dregs (reg));
2852 }
2853 else if (W == 1 && sz == 2 && Z == 0)
2854 {
2855 OUTS (outf, "B[");
2856 OUTS (outf, pregs (ptr));
2857 OUTS (outf, " + ");
2858 OUTS (outf, imm16 (offset));
2859 OUTS (outf, "] = ");
2860 OUTS (outf, dregs (reg));
2861 }
2862 else
2863 return 0;
2864
2865 return 4;
2866 }
2867
2868 static int
2869 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2870 {
2871 /* linkage
2872 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2873 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2874 |.framesize.....................................................|
2875 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2876 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2877 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2878
2879 if (R == 0)
2880 {
2881 OUTS (outf, "LINK ");
2882 OUTS (outf, uimm16s4 (framesize));
2883 OUTS (outf, ";\t\t/* (");
2884 OUTS (outf, uimm16s4d (framesize));
2885 OUTS (outf, ") */");
2886 comment = 1;
2887 }
2888 else if (R == 1)
2889 OUTS (outf, "UNLINK");
2890 else
2891 return 0;
2892
2893 return 4;
2894 }
2895
2896 static int
2897 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2898 {
2899 /* dsp32mac
2900 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2901 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2902 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2903 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2904 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2905 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2906 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2907 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2908 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2909 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2910 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2911 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2912 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2913 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2914 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2915 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2916 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2917 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2918
2919 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2920 return 0;
2921
2922 if (op1 == 3 && MM)
2923 return 0;
2924
2925 if ((w1 || w0) && mmod == M_W32)
2926 return 0;
2927
2928 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2929 return 0;
2930
2931 if (w1 == 1 || op1 != 3)
2932 {
2933 if (w1)
2934 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2935
2936 if (op1 == 3)
2937 OUTS (outf, " = A1");
2938 else
2939 {
2940 if (w1)
2941 OUTS (outf, " = (");
2942 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2943 if (w1)
2944 OUTS (outf, ")");
2945 }
2946
2947 if (w0 == 1 || op0 != 3)
2948 {
2949 if (MM)
2950 OUTS (outf, " (M)");
2951 MM = 0;
2952 OUTS (outf, ", ");
2953 }
2954 }
2955
2956 if (w0 == 1 || op0 != 3)
2957 {
2958 if (w0)
2959 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
2960
2961 if (op0 == 3)
2962 OUTS (outf, " = A0");
2963 else
2964 {
2965 if (w0)
2966 OUTS (outf, " = (");
2967 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
2968 if (w0)
2969 OUTS (outf, ")");
2970 }
2971 }
2972
2973 decode_optmode (mmod, MM, outf);
2974
2975 return 4;
2976 }
2977
2978 static int
2979 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2980 {
2981 /* dsp32mult
2982 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2983 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2984 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2985 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2986 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2987 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2988 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2989 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2990 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2991 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2992 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2993 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2994 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2995 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2996 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2997 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2998
2999 if (w1 == 0 && w0 == 0)
3000 return 0;
3001
3002 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3003 return 0;
3004
3005 if (w1)
3006 {
3007 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
3008 OUTS (outf, " = ");
3009 decode_multfunc (h01, h11, src0, src1, outf);
3010
3011 if (w0)
3012 {
3013 if (MM)
3014 OUTS (outf, " (M)");
3015 MM = 0;
3016 OUTS (outf, ", ");
3017 }
3018 }
3019
3020 if (w0)
3021 {
3022 OUTS (outf, dregs (dst));
3023 OUTS (outf, " = ");
3024 decode_multfunc (h00, h10, src0, src1, outf);
3025 }
3026
3027 decode_optmode (mmod, MM, outf);
3028 return 4;
3029 }
3030
3031 static int
3032 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3033 {
3034 /* dsp32alu
3035 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3036 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3037 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3038 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3039 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3040 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3041 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3042 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3043 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3044 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3045 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3046 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3047 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3048
3049 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3050 {
3051 OUTS (outf, "A0.L = ");
3052 OUTS (outf, dregs_lo (src0));
3053 }
3054 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3055 {
3056 OUTS (outf, "A1.H = ");
3057 OUTS (outf, dregs_hi (src0));
3058 }
3059 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3060 {
3061 OUTS (outf, "A1.L = ");
3062 OUTS (outf, dregs_lo (src0));
3063 }
3064 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3065 {
3066 OUTS (outf, "A0.H = ");
3067 OUTS (outf, dregs_hi (src0));
3068 }
3069 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3070 {
3071 OUTS (outf, dregs_hi (dst0));
3072 OUTS (outf, " = ");
3073 OUTS (outf, dregs (src0));
3074 OUTS (outf, " - ");
3075 OUTS (outf, dregs (src1));
3076 OUTS (outf, " (RND20)");
3077 }
3078 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3079 {
3080 OUTS (outf, dregs_hi (dst0));
3081 OUTS (outf, " = ");
3082 OUTS (outf, dregs (src0));
3083 OUTS (outf, " + ");
3084 OUTS (outf, dregs (src1));
3085 OUTS (outf, " (RND20)");
3086 }
3087 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3088 {
3089 OUTS (outf, dregs_lo (dst0));
3090 OUTS (outf, " = ");
3091 OUTS (outf, dregs (src0));
3092 OUTS (outf, " - ");
3093 OUTS (outf, dregs (src1));
3094 OUTS (outf, " (RND12)");
3095 }
3096 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3097 {
3098 OUTS (outf, dregs_lo (dst0));
3099 OUTS (outf, " = ");
3100 OUTS (outf, dregs (src0));
3101 OUTS (outf, " + ");
3102 OUTS (outf, dregs (src1));
3103 OUTS (outf, " (RND12)");
3104 }
3105 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3106 {
3107 OUTS (outf, dregs_lo (dst0));
3108 OUTS (outf, " = ");
3109 OUTS (outf, dregs (src0));
3110 OUTS (outf, " - ");
3111 OUTS (outf, dregs (src1));
3112 OUTS (outf, " (RND20)");
3113 }
3114 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3115 {
3116 OUTS (outf, dregs_hi (dst0));
3117 OUTS (outf, " = ");
3118 OUTS (outf, dregs (src0));
3119 OUTS (outf, " + ");
3120 OUTS (outf, dregs (src1));
3121 OUTS (outf, " (RND12)");
3122 }
3123 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3124 {
3125 OUTS (outf, dregs_lo (dst0));
3126 OUTS (outf, " = ");
3127 OUTS (outf, dregs (src0));
3128 OUTS (outf, " + ");
3129 OUTS (outf, dregs (src1));
3130 OUTS (outf, " (RND20)");
3131 }
3132 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3133 {
3134 OUTS (outf, dregs_hi (dst0));
3135 OUTS (outf, " = ");
3136 OUTS (outf, dregs (src0));
3137 OUTS (outf, " - ");
3138 OUTS (outf, dregs (src1));
3139 OUTS (outf, " (RND12)");
3140 }
3141 else if (HL == 1 && aop == 0 && aopcde == 2)
3142 {
3143 OUTS (outf, dregs_hi (dst0));
3144 OUTS (outf, " = ");
3145 OUTS (outf, dregs_lo (src0));
3146 OUTS (outf, " + ");
3147 OUTS (outf, dregs_lo (src1));
3148 amod1 (s, x, outf);
3149 }
3150 else if (HL == 1 && aop == 1 && aopcde == 2)
3151 {
3152 OUTS (outf, dregs_hi (dst0));
3153 OUTS (outf, " = ");
3154 OUTS (outf, dregs_lo (src0));
3155 OUTS (outf, " + ");
3156 OUTS (outf, dregs_hi (src1));
3157 amod1 (s, x, outf);
3158 }
3159 else if (HL == 1 && aop == 2 && aopcde == 2)
3160 {
3161 OUTS (outf, dregs_hi (dst0));
3162 OUTS (outf, " = ");
3163 OUTS (outf, dregs_hi (src0));
3164 OUTS (outf, " + ");
3165 OUTS (outf, dregs_lo (src1));
3166 amod1 (s, x, outf);
3167 }
3168 else if (HL == 1 && aop == 3 && aopcde == 2)
3169 {
3170 OUTS (outf, dregs_hi (dst0));
3171 OUTS (outf, " = ");
3172 OUTS (outf, dregs_hi (src0));
3173 OUTS (outf, " + ");
3174 OUTS (outf, dregs_hi (src1));
3175 amod1 (s, x, outf);
3176 }
3177 else if (HL == 0 && aop == 0 && aopcde == 3)
3178 {
3179 OUTS (outf, dregs_lo (dst0));
3180 OUTS (outf, " = ");
3181 OUTS (outf, dregs_lo (src0));
3182 OUTS (outf, " - ");
3183 OUTS (outf, dregs_lo (src1));
3184 amod1 (s, x, outf);
3185 }
3186 else if (HL == 0 && aop == 1 && aopcde == 3)
3187 {
3188 OUTS (outf, dregs_lo (dst0));
3189 OUTS (outf, " = ");
3190 OUTS (outf, dregs_lo (src0));
3191 OUTS (outf, " - ");
3192 OUTS (outf, dregs_hi (src1));
3193 amod1 (s, x, outf);
3194 }
3195 else if (HL == 0 && aop == 3 && aopcde == 2)
3196 {
3197 OUTS (outf, dregs_lo (dst0));
3198 OUTS (outf, " = ");
3199 OUTS (outf, dregs_hi (src0));
3200 OUTS (outf, " + ");
3201 OUTS (outf, dregs_hi (src1));
3202 amod1 (s, x, outf);
3203 }
3204 else if (HL == 1 && aop == 0 && aopcde == 3)
3205 {
3206 OUTS (outf, dregs_hi (dst0));
3207 OUTS (outf, " = ");
3208 OUTS (outf, dregs_lo (src0));
3209 OUTS (outf, " - ");
3210 OUTS (outf, dregs_lo (src1));
3211 amod1 (s, x, outf);
3212 }
3213 else if (HL == 1 && aop == 1 && aopcde == 3)
3214 {
3215 OUTS (outf, dregs_hi (dst0));
3216 OUTS (outf, " = ");
3217 OUTS (outf, dregs_lo (src0));
3218 OUTS (outf, " - ");
3219 OUTS (outf, dregs_hi (src1));
3220 amod1 (s, x, outf);
3221 }
3222 else if (HL == 1 && aop == 2 && aopcde == 3)
3223 {
3224 OUTS (outf, dregs_hi (dst0));
3225 OUTS (outf, " = ");
3226 OUTS (outf, dregs_hi (src0));
3227 OUTS (outf, " - ");
3228 OUTS (outf, dregs_lo (src1));
3229 amod1 (s, x, outf);
3230 }
3231 else if (HL == 1 && aop == 3 && aopcde == 3)
3232 {
3233 OUTS (outf, dregs_hi (dst0));
3234 OUTS (outf, " = ");
3235 OUTS (outf, dregs_hi (src0));
3236 OUTS (outf, " - ");
3237 OUTS (outf, dregs_hi (src1));
3238 amod1 (s, x, outf);
3239 }
3240 else if (HL == 0 && aop == 2 && aopcde == 2)
3241 {
3242 OUTS (outf, dregs_lo (dst0));
3243 OUTS (outf, " = ");
3244 OUTS (outf, dregs_hi (src0));
3245 OUTS (outf, " + ");
3246 OUTS (outf, dregs_lo (src1));
3247 amod1 (s, x, outf);
3248 }
3249 else if (HL == 0 && aop == 1 && aopcde == 2)
3250 {
3251 OUTS (outf, dregs_lo (dst0));
3252 OUTS (outf, " = ");
3253 OUTS (outf, dregs_lo (src0));
3254 OUTS (outf, " + ");
3255 OUTS (outf, dregs_hi (src1));
3256 amod1 (s, x, outf);
3257 }
3258 else if (HL == 0 && aop == 2 && aopcde == 3)
3259 {
3260 OUTS (outf, dregs_lo (dst0));
3261 OUTS (outf, " = ");
3262 OUTS (outf, dregs_hi (src0));
3263 OUTS (outf, " - ");
3264 OUTS (outf, dregs_lo (src1));
3265 amod1 (s, x, outf);
3266 }
3267 else if (HL == 0 && aop == 3 && aopcde == 3)
3268 {
3269 OUTS (outf, dregs_lo (dst0));
3270 OUTS (outf, " = ");
3271 OUTS (outf, dregs_hi (src0));
3272 OUTS (outf, " - ");
3273 OUTS (outf, dregs_hi (src1));
3274 amod1 (s, x, outf);
3275 }
3276 else if (HL == 0 && aop == 0 && aopcde == 2)
3277 {
3278 OUTS (outf, dregs_lo (dst0));
3279 OUTS (outf, " = ");
3280 OUTS (outf, dregs_lo (src0));
3281 OUTS (outf, " + ");
3282 OUTS (outf, dregs_lo (src1));
3283 amod1 (s, x, outf);
3284 }
3285 else if (aop == 0 && aopcde == 9 && s == 1)
3286 {
3287 OUTS (outf, "A0 = ");
3288 OUTS (outf, dregs (src0));
3289 }
3290 else if (aop == 3 && aopcde == 11 && s == 0)
3291 OUTS (outf, "A0 -= A1");
3292
3293 else if (aop == 3 && aopcde == 11 && s == 1)
3294 OUTS (outf, "A0 -= A1 (W32)");
3295
3296 else if (aop == 3 && aopcde == 22 && HL == 1)
3297 {
3298 OUTS (outf, dregs (dst0));
3299 OUTS (outf, " = BYTEOP2M (");
3300 OUTS (outf, dregs (src0 + 1));
3301 OUTS (outf, ":");
3302 OUTS (outf, imm5 (src0));
3303 OUTS (outf, ", ");
3304 OUTS (outf, dregs (src1 + 1));
3305 OUTS (outf, ":");
3306 OUTS (outf, imm5 (src1));
3307 OUTS (outf, ") (TH");
3308 if (s == 1)
3309 OUTS (outf, ", R)");
3310 else
3311 OUTS (outf, ")");
3312 }
3313 else if (aop == 3 && aopcde == 22 && HL == 0)
3314 {
3315 OUTS (outf, dregs (dst0));
3316 OUTS (outf, " = BYTEOP2M (");
3317 OUTS (outf, dregs (src0 + 1));
3318 OUTS (outf, ":");
3319 OUTS (outf, imm5 (src0));
3320 OUTS (outf, ", ");
3321 OUTS (outf, dregs (src1 + 1));
3322 OUTS (outf, ":");
3323 OUTS (outf, imm5 (src1));
3324 OUTS (outf, ") (TL");
3325 if (s == 1)
3326 OUTS (outf, ", R)");
3327 else
3328 OUTS (outf, ")");
3329 }
3330 else if (aop == 2 && aopcde == 22 && HL == 1)
3331 {
3332 OUTS (outf, dregs (dst0));
3333 OUTS (outf, " = BYTEOP2M (");
3334 OUTS (outf, dregs (src0 + 1));
3335 OUTS (outf, ":");
3336 OUTS (outf, imm5 (src0));
3337 OUTS (outf, ", ");
3338 OUTS (outf, dregs (src1 + 1));
3339 OUTS (outf, ":");
3340 OUTS (outf, imm5 (src1));
3341 OUTS (outf, ") (RNDH");
3342 if (s == 1)
3343 OUTS (outf, ", R)");
3344 else
3345 OUTS (outf, ")");
3346 }
3347 else if (aop == 2 && aopcde == 22 && HL == 0)
3348 {
3349 OUTS (outf, dregs (dst0));
3350 OUTS (outf, " = BYTEOP2M (");
3351 OUTS (outf, dregs (src0 + 1));
3352 OUTS (outf, ":");
3353 OUTS (outf, imm5 (src0));
3354 OUTS (outf, ", ");
3355 OUTS (outf, dregs (src1 + 1));
3356 OUTS (outf, ":");
3357 OUTS (outf, imm5 (src1));
3358 OUTS (outf, ") (RNDL");
3359 if (s == 1)
3360 OUTS (outf, ", R)");
3361 else
3362 OUTS (outf, ")");
3363 }
3364 else if (aop == 1 && aopcde == 22 && HL == 1)
3365 {
3366 OUTS (outf, dregs (dst0));
3367 OUTS (outf, " = BYTEOP2P (");
3368 OUTS (outf, dregs (src0 + 1));
3369 OUTS (outf, ":");
3370 OUTS (outf, imm5d (src0));
3371 OUTS (outf, ", ");
3372 OUTS (outf, dregs (src1 + 1));
3373 OUTS (outf, ":");
3374 OUTS (outf, imm5d (src1));
3375 OUTS (outf, ") (TH");
3376 if (s == 1)
3377 OUTS (outf, ", R)");
3378 else
3379 OUTS (outf, ")");
3380 }
3381 else if (aop == 1 && aopcde == 22 && HL == 0)
3382 {
3383 OUTS (outf, dregs (dst0));
3384 OUTS (outf, " = BYTEOP2P (");
3385 OUTS (outf, dregs (src0 + 1));
3386 OUTS (outf, ":");
3387 OUTS (outf, imm5d (src0));
3388 OUTS (outf, ", ");
3389 OUTS (outf, dregs (src1 + 1));
3390 OUTS (outf, ":");
3391 OUTS (outf, imm5d (src1));
3392 OUTS (outf, ") (TL");
3393 if (s == 1)
3394 OUTS (outf, ", R)");
3395 else
3396 OUTS (outf, ")");
3397 }
3398 else if (aop == 0 && aopcde == 22 && HL == 1)
3399 {
3400 OUTS (outf, dregs (dst0));
3401 OUTS (outf, " = BYTEOP2P (");
3402 OUTS (outf, dregs (src0 + 1));
3403 OUTS (outf, ":");
3404 OUTS (outf, imm5d (src0));
3405 OUTS (outf, ", ");
3406 OUTS (outf, dregs (src1 + 1));
3407 OUTS (outf, ":");
3408 OUTS (outf, imm5d (src1));
3409 OUTS (outf, ") (RNDH");
3410 if (s == 1)
3411 OUTS (outf, ", R)");
3412 else
3413 OUTS (outf, ")");
3414 }
3415 else if (aop == 0 && aopcde == 22 && HL == 0)
3416 {
3417 OUTS (outf, dregs (dst0));
3418 OUTS (outf, " = BYTEOP2P (");
3419 OUTS (outf, dregs (src0 + 1));
3420 OUTS (outf, ":");
3421 OUTS (outf, imm5d (src0));
3422 OUTS (outf, ", ");
3423 OUTS (outf, dregs (src1 + 1));
3424 OUTS (outf, ":");
3425 OUTS (outf, imm5d (src1));
3426 OUTS (outf, ") (RNDL");
3427 if (s == 1)
3428 OUTS (outf, ", R)");
3429 else
3430 OUTS (outf, ")");
3431 }
3432 else if (aop == 0 && s == 0 && aopcde == 8)
3433 OUTS (outf, "A0 = 0");
3434
3435 else if (aop == 0 && s == 1 && aopcde == 8)
3436 OUTS (outf, "A0 = A0 (S)");
3437
3438 else if (aop == 1 && s == 0 && aopcde == 8)
3439 OUTS (outf, "A1 = 0");
3440
3441 else if (aop == 1 && s == 1 && aopcde == 8)
3442 OUTS (outf, "A1 = A1 (S)");
3443
3444 else if (aop == 2 && s == 0 && aopcde == 8)
3445 OUTS (outf, "A1 = A0 = 0");
3446
3447 else if (aop == 2 && s == 1 && aopcde == 8)
3448 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3449
3450 else if (aop == 3 && s == 0 && aopcde == 8)
3451 OUTS (outf, "A0 = A1");
3452
3453 else if (aop == 3 && s == 1 && aopcde == 8)
3454 OUTS (outf, "A1 = A0");
3455
3456 else if (aop == 1 && aopcde == 9 && s == 0)
3457 {
3458 OUTS (outf, "A0.X = ");
3459 OUTS (outf, dregs_lo (src0));
3460 }
3461 else if (aop == 1 && HL == 0 && aopcde == 11)
3462 {
3463 OUTS (outf, dregs_lo (dst0));
3464 OUTS (outf, " = (A0 += A1)");
3465 }
3466 else if (aop == 3 && HL == 0 && aopcde == 16)
3467 OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
3468
3469 else if (aop == 0 && aopcde == 23 && HL == 1)
3470 {
3471 OUTS (outf, dregs (dst0));
3472 OUTS (outf, " = BYTEOP3P (");
3473 OUTS (outf, dregs (src0 + 1));
3474 OUTS (outf, ":");
3475 OUTS (outf, imm5d (src0));
3476 OUTS (outf, ", ");
3477 OUTS (outf, dregs (src1 + 1));
3478 OUTS (outf, ":");
3479 OUTS (outf, imm5d (src1));
3480 OUTS (outf, ") (HI");
3481 if (s == 1)
3482 OUTS (outf, ", R)");
3483 else
3484 OUTS (outf, ")");
3485 }
3486 else if (aop == 3 && aopcde == 9 && s == 0)
3487 {
3488 OUTS (outf, "A1.X = ");
3489 OUTS (outf, dregs_lo (src0));
3490 }
3491 else if (aop == 1 && HL == 1 && aopcde == 16)
3492 OUTS (outf, "A1 = ABS A1");
3493
3494 else if (aop == 0 && HL == 1 && aopcde == 16)
3495 OUTS (outf, "A1 = ABS A0");
3496
3497 else if (aop == 2 && aopcde == 9 && s == 1)
3498 {
3499 OUTS (outf, "A1 = ");
3500 OUTS (outf, dregs (src0));
3501 }
3502 else if (HL == 0 && aop == 3 && aopcde == 12)
3503 {
3504 OUTS (outf, dregs_lo (dst0));
3505 OUTS (outf, " = ");
3506 OUTS (outf, dregs (src0));
3507 OUTS (outf, " (RND)");
3508 }
3509 else if (aop == 1 && HL == 0 && aopcde == 16)
3510 OUTS (outf, "A0 = ABS A1");
3511
3512 else if (aop == 0 && HL == 0 && aopcde == 16)
3513 OUTS (outf, "A0 = ABS A0");
3514
3515 else if (aop == 3 && HL == 0 && aopcde == 15)
3516 {
3517 OUTS (outf, dregs (dst0));
3518 OUTS (outf, " = -");
3519 OUTS (outf, dregs (src0));
3520 OUTS (outf, " (V)");
3521 }
3522 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3523 {
3524 OUTS (outf, dregs (dst0));
3525 OUTS (outf, " = -");
3526 OUTS (outf, dregs (src0));
3527 OUTS (outf, " (S)");
3528 }
3529 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3530 {
3531 OUTS (outf, dregs (dst0));
3532 OUTS (outf, " = -");
3533 OUTS (outf, dregs (src0));
3534 OUTS (outf, " (NS)");
3535 }
3536 else if (aop == 1 && HL == 1 && aopcde == 11)
3537 {
3538 OUTS (outf, dregs_hi (dst0));
3539 OUTS (outf, " = (A0 += A1)");
3540 }
3541 else if (aop == 2 && aopcde == 11 && s == 0)
3542 OUTS (outf, "A0 += A1");
3543
3544 else if (aop == 2 && aopcde == 11 && s == 1)
3545 OUTS (outf, "A0 += A1 (W32)");
3546
3547 else if (aop == 3 && HL == 0 && aopcde == 14)
3548 OUTS (outf, "A1 = -A1, A0 = -A0");
3549
3550 else if (HL == 1 && aop == 3 && aopcde == 12)
3551 {
3552 OUTS (outf, dregs_hi (dst0));
3553 OUTS (outf, " = ");
3554 OUTS (outf, dregs (src0));
3555 OUTS (outf, " (RND)");
3556 }
3557 else if (aop == 0 && aopcde == 23 && HL == 0)
3558 {
3559 OUTS (outf, dregs (dst0));
3560 OUTS (outf, " = BYTEOP3P (");
3561 OUTS (outf, dregs (src0 + 1));
3562 OUTS (outf, ":");
3563 OUTS (outf, imm5d (src0));
3564 OUTS (outf, ", ");
3565 OUTS (outf, dregs (src1 + 1));
3566 OUTS (outf, ":");
3567 OUTS (outf, imm5d (src1));
3568 OUTS (outf, ") (LO");
3569 if (s == 1)
3570 OUTS (outf, ", R)");
3571 else
3572 OUTS (outf, ")");
3573 }
3574 else if (aop == 0 && HL == 0 && aopcde == 14)
3575 OUTS (outf, "A0 = -A0");
3576
3577 else if (aop == 1 && HL == 0 && aopcde == 14)
3578 OUTS (outf, "A0 = -A1");
3579
3580 else if (aop == 0 && HL == 1 && aopcde == 14)
3581 OUTS (outf, "A1 = -A0");
3582
3583 else if (aop == 1 && HL == 1 && aopcde == 14)
3584 OUTS (outf, "A1 = -A1");
3585
3586 else if (aop == 0 && aopcde == 12)
3587 {
3588 OUTS (outf, dregs_hi (dst0));
3589 OUTS (outf, " = ");
3590 OUTS (outf, dregs_lo (dst0));
3591 OUTS (outf, " = SIGN (");
3592 OUTS (outf, dregs_hi (src0));
3593 OUTS (outf, ") * ");
3594 OUTS (outf, dregs_hi (src1));
3595 OUTS (outf, " + SIGN (");
3596 OUTS (outf, dregs_lo (src0));
3597 OUTS (outf, ") * ");
3598 OUTS (outf, dregs_lo (src1));
3599 }
3600 else if (aop == 2 && aopcde == 0)
3601 {
3602 OUTS (outf, dregs (dst0));
3603 OUTS (outf, " = ");
3604 OUTS (outf, dregs (src0));
3605 OUTS (outf, " -|+ ");
3606 OUTS (outf, dregs (src1));
3607 amod0 (s, x, outf);
3608 }
3609 else if (aop == 1 && aopcde == 12)
3610 {
3611 OUTS (outf, dregs (dst1));
3612 OUTS (outf, " = A1.L + A1.H, ");
3613 OUTS (outf, dregs (dst0));
3614 OUTS (outf, " = A0.L + A0.H");
3615 }
3616 else if (aop == 2 && aopcde == 4)
3617 {
3618 OUTS (outf, dregs (dst1));
3619 OUTS (outf, " = ");
3620 OUTS (outf, dregs (src0));
3621 OUTS (outf, " + ");
3622 OUTS (outf, dregs (src1));
3623 OUTS (outf, ", ");
3624 OUTS (outf, dregs (dst0));
3625 OUTS (outf, " = ");
3626 OUTS (outf, dregs (src0));
3627 OUTS (outf, " - ");
3628 OUTS (outf, dregs (src1));
3629 amod1 (s, x, outf);
3630 }
3631 else if (HL == 0 && aopcde == 1)
3632 {
3633 OUTS (outf, dregs (dst1));
3634 OUTS (outf, " = ");
3635 OUTS (outf, dregs (src0));
3636 OUTS (outf, " +|+ ");
3637 OUTS (outf, dregs (src1));
3638 OUTS (outf, ", ");
3639 OUTS (outf, dregs (dst0));
3640 OUTS (outf, " = ");
3641 OUTS (outf, dregs (src0));
3642 OUTS (outf, " -|- ");
3643 OUTS (outf, dregs (src1));
3644 amod0amod2 (s, x, aop, outf);
3645 }
3646 else if (aop == 0 && aopcde == 11)
3647 {
3648 OUTS (outf, dregs (dst0));
3649 OUTS (outf, " = (A0 += A1)");
3650 }
3651 else if (aop == 0 && aopcde == 10)
3652 {
3653 OUTS (outf, dregs_lo (dst0));
3654 OUTS (outf, " = A0.X");
3655 }
3656 else if (aop == 1 && aopcde == 10)
3657 {
3658 OUTS (outf, dregs_lo (dst0));
3659 OUTS (outf, " = A1.X");
3660 }
3661 else if (aop == 1 && aopcde == 0)
3662 {
3663 OUTS (outf, dregs (dst0));
3664 OUTS (outf, " = ");
3665 OUTS (outf, dregs (src0));
3666 OUTS (outf, " +|- ");
3667 OUTS (outf, dregs (src1));
3668 amod0 (s, x, outf);
3669 }
3670 else if (aop == 3 && aopcde == 0)
3671 {
3672 OUTS (outf, dregs (dst0));
3673 OUTS (outf, " = ");
3674 OUTS (outf, dregs (src0));
3675 OUTS (outf, " -|- ");
3676 OUTS (outf, dregs (src1));
3677 amod0 (s, x, outf);
3678 }
3679 else if (aop == 1 && aopcde == 4)
3680 {
3681 OUTS (outf, dregs (dst0));
3682 OUTS (outf, " = ");
3683 OUTS (outf, dregs (src0));
3684 OUTS (outf, " - ");
3685 OUTS (outf, dregs (src1));
3686 amod1 (s, x, outf);
3687 }
3688 else if (aop == 0 && aopcde == 17)
3689 {
3690 OUTS (outf, dregs (dst1));
3691 OUTS (outf, " = A1 + A0, ");
3692 OUTS (outf, dregs (dst0));
3693 OUTS (outf, " = A1 - A0");
3694 amod1 (s, x, outf);
3695 }
3696 else if (aop == 1 && aopcde == 17)
3697 {
3698 OUTS (outf, dregs (dst1));
3699 OUTS (outf, " = A0 + A1, ");
3700 OUTS (outf, dregs (dst0));
3701 OUTS (outf, " = A0 - A1");
3702 amod1 (s, x, outf);
3703 }
3704 else if (aop == 0 && aopcde == 18)
3705 {
3706 OUTS (outf, "SAA (");
3707 OUTS (outf, dregs (src0 + 1));
3708 OUTS (outf, ":");
3709 OUTS (outf, imm5d (src0));
3710 OUTS (outf, ", ");
3711 OUTS (outf, dregs (src1 + 1));
3712 OUTS (outf, ":");
3713 OUTS (outf, imm5d (src1));
3714 OUTS (outf, ")");
3715 aligndir (s, outf);
3716 }
3717 else if (aop == 3 && aopcde == 18)
3718 OUTS (outf, "DISALGNEXCPT");
3719
3720 else if (aop == 0 && aopcde == 20)
3721 {
3722 OUTS (outf, dregs (dst0));
3723 OUTS (outf, " = BYTEOP1P (");
3724 OUTS (outf, dregs (src0 + 1));
3725 OUTS (outf, ":");
3726 OUTS (outf, imm5d (src0));
3727 OUTS (outf, ", ");
3728 OUTS (outf, dregs (src1 + 1));
3729 OUTS (outf, ":");
3730 OUTS (outf, imm5d (src1));
3731 OUTS (outf, ")");
3732 aligndir (s, outf);
3733 }
3734 else if (aop == 1 && aopcde == 20)
3735 {
3736 OUTS (outf, dregs (dst0));
3737 OUTS (outf, " = BYTEOP1P (");
3738 OUTS (outf, dregs (src0 + 1));
3739 OUTS (outf, ":");
3740 OUTS (outf, imm5d (src0));
3741 OUTS (outf, ", ");
3742 OUTS (outf, dregs (src1 + 1));
3743 OUTS (outf, ":");
3744 OUTS (outf, imm5d (src1));
3745 OUTS (outf, ") (T");
3746 if (s == 1)
3747 OUTS (outf, ", R)");
3748 else
3749 OUTS (outf, ")");
3750 }
3751 else if (aop == 0 && aopcde == 21)
3752 {
3753 OUTS (outf, "(");
3754 OUTS (outf, dregs (dst1));
3755 OUTS (outf, ", ");
3756 OUTS (outf, dregs (dst0));
3757 OUTS (outf, ") = BYTEOP16P (");
3758 OUTS (outf, dregs (src0 + 1));
3759 OUTS (outf, ":");
3760 OUTS (outf, imm5d (src0));
3761 OUTS (outf, ", ");
3762 OUTS (outf, dregs (src1 + 1));
3763 OUTS (outf, ":");
3764 OUTS (outf, imm5d (src1));
3765 OUTS (outf, ")");
3766 aligndir (s, outf);
3767 }
3768 else if (aop == 1 && aopcde == 21)
3769 {
3770 OUTS (outf, "(");
3771 OUTS (outf, dregs (dst1));
3772 OUTS (outf, ", ");
3773 OUTS (outf, dregs (dst0));
3774 OUTS (outf, ") = BYTEOP16M (");
3775 OUTS (outf, dregs (src0 + 1));
3776 OUTS (outf, ":");
3777 OUTS (outf, imm5d (src0));
3778 OUTS (outf, ", ");
3779 OUTS (outf, dregs (src1 + 1));
3780 OUTS (outf, ":");
3781 OUTS (outf, imm5d (src1));
3782 OUTS (outf, ")");
3783 aligndir (s, outf);
3784 }
3785 else if (aop == 2 && aopcde == 7)
3786 {
3787 OUTS (outf, dregs (dst0));
3788 OUTS (outf, " = ABS ");
3789 OUTS (outf, dregs (src0));
3790 }
3791 else if (aop == 1 && aopcde == 7)
3792 {
3793 OUTS (outf, dregs (dst0));
3794 OUTS (outf, " = MIN (");
3795 OUTS (outf, dregs (src0));
3796 OUTS (outf, ", ");
3797 OUTS (outf, dregs (src1));
3798 OUTS (outf, ")");
3799 }
3800 else if (aop == 0 && aopcde == 7)
3801 {
3802 OUTS (outf, dregs (dst0));
3803 OUTS (outf, " = MAX (");
3804 OUTS (outf, dregs (src0));
3805 OUTS (outf, ", ");
3806 OUTS (outf, dregs (src1));
3807 OUTS (outf, ")");
3808 }
3809 else if (aop == 2 && aopcde == 6)
3810 {
3811 OUTS (outf, dregs (dst0));
3812 OUTS (outf, " = ABS ");
3813 OUTS (outf, dregs (src0));
3814 OUTS (outf, " (V)");
3815 }
3816 else if (aop == 1 && aopcde == 6)
3817 {
3818 OUTS (outf, dregs (dst0));
3819 OUTS (outf, " = MIN (");
3820 OUTS (outf, dregs (src0));
3821 OUTS (outf, ", ");
3822 OUTS (outf, dregs (src1));
3823 OUTS (outf, ") (V)");
3824 }
3825 else if (aop == 0 && aopcde == 6)
3826 {
3827 OUTS (outf, dregs (dst0));
3828 OUTS (outf, " = MAX (");
3829 OUTS (outf, dregs (src0));
3830 OUTS (outf, ", ");
3831 OUTS (outf, dregs (src1));
3832 OUTS (outf, ") (V)");
3833 }
3834 else if (HL == 1 && aopcde == 1)
3835 {
3836 OUTS (outf, dregs (dst1));
3837 OUTS (outf, " = ");
3838 OUTS (outf, dregs (src0));
3839 OUTS (outf, " +|- ");
3840 OUTS (outf, dregs (src1));
3841 OUTS (outf, ", ");
3842 OUTS (outf, dregs (dst0));
3843 OUTS (outf, " = ");
3844 OUTS (outf, dregs (src0));
3845 OUTS (outf, " -|+ ");
3846 OUTS (outf, dregs (src1));
3847 amod0amod2 (s, x, aop, outf);
3848 }
3849 else if (aop == 0 && aopcde == 4)
3850 {
3851 OUTS (outf, dregs (dst0));
3852 OUTS (outf, " = ");
3853 OUTS (outf, dregs (src0));
3854 OUTS (outf, " + ");
3855 OUTS (outf, dregs (src1));
3856 amod1 (s, x, outf);
3857 }
3858 else if (aop == 0 && aopcde == 0)
3859 {
3860 OUTS (outf, dregs (dst0));
3861 OUTS (outf, " = ");
3862 OUTS (outf, dregs (src0));
3863 OUTS (outf, " +|+ ");
3864 OUTS (outf, dregs (src1));
3865 amod0 (s, x, outf);
3866 }
3867 else if (aop == 0 && aopcde == 24)
3868 {
3869 OUTS (outf, dregs (dst0));
3870 OUTS (outf, " = BYTEPACK (");
3871 OUTS (outf, dregs (src0));
3872 OUTS (outf, ", ");
3873 OUTS (outf, dregs (src1));
3874 OUTS (outf, ")");
3875 }
3876 else if (aop == 1 && aopcde == 24)
3877 {
3878 OUTS (outf, "(");
3879 OUTS (outf, dregs (dst1));
3880 OUTS (outf, ", ");
3881 OUTS (outf, dregs (dst0));
3882 OUTS (outf, ") = BYTEUNPACK ");
3883 OUTS (outf, dregs (src0 + 1));
3884 OUTS (outf, ":");
3885 OUTS (outf, imm5d (src0));
3886 aligndir (s, outf);
3887 }
3888 else if (aopcde == 13)
3889 {
3890 OUTS (outf, "(");
3891 OUTS (outf, dregs (dst1));
3892 OUTS (outf, ", ");
3893 OUTS (outf, dregs (dst0));
3894 OUTS (outf, ") = SEARCH ");
3895 OUTS (outf, dregs (src0));
3896 OUTS (outf, " (");
3897 searchmod (aop, outf);
3898 OUTS (outf, ")");
3899 }
3900 else
3901 return 0;
3902
3903 return 4;
3904 }
3905
3906 static int
3907 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3908 {
3909 /* dsp32shift
3910 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3911 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3912 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3913 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3914 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3915 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3916 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3917 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3918 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3919 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3920 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3921
3922 if (HLs == 0 && sop == 0 && sopcde == 0)
3923 {
3924 OUTS (outf, dregs_lo (dst0));
3925 OUTS (outf, " = ASHIFT ");
3926 OUTS (outf, dregs_lo (src1));
3927 OUTS (outf, " BY ");
3928 OUTS (outf, dregs_lo (src0));
3929 }
3930 else if (HLs == 1 && sop == 0 && sopcde == 0)
3931 {
3932 OUTS (outf, dregs_lo (dst0));
3933 OUTS (outf, " = ASHIFT ");
3934 OUTS (outf, dregs_hi (src1));
3935 OUTS (outf, " BY ");
3936 OUTS (outf, dregs_lo (src0));
3937 }
3938 else if (HLs == 2 && sop == 0 && sopcde == 0)
3939 {
3940 OUTS (outf, dregs_hi (dst0));
3941 OUTS (outf, " = ASHIFT ");
3942 OUTS (outf, dregs_lo (src1));
3943 OUTS (outf, " BY ");
3944 OUTS (outf, dregs_lo (src0));
3945 }
3946 else if (HLs == 3 && sop == 0 && sopcde == 0)
3947 {
3948 OUTS (outf, dregs_hi (dst0));
3949 OUTS (outf, " = ASHIFT ");
3950 OUTS (outf, dregs_hi (src1));
3951 OUTS (outf, " BY ");
3952 OUTS (outf, dregs_lo (src0));
3953 }
3954 else if (HLs == 0 && sop == 1 && sopcde == 0)
3955 {
3956 OUTS (outf, dregs_lo (dst0));
3957 OUTS (outf, " = ASHIFT ");
3958 OUTS (outf, dregs_lo (src1));
3959 OUTS (outf, " BY ");
3960 OUTS (outf, dregs_lo (src0));
3961 OUTS (outf, " (S)");
3962 }
3963 else if (HLs == 1 && sop == 1 && sopcde == 0)
3964 {
3965 OUTS (outf, dregs_lo (dst0));
3966 OUTS (outf, " = ASHIFT ");
3967 OUTS (outf, dregs_hi (src1));
3968 OUTS (outf, " BY ");
3969 OUTS (outf, dregs_lo (src0));
3970 OUTS (outf, " (S)");
3971 }
3972 else if (HLs == 2 && sop == 1 && sopcde == 0)
3973 {
3974 OUTS (outf, dregs_hi (dst0));
3975 OUTS (outf, " = ASHIFT ");
3976 OUTS (outf, dregs_lo (src1));
3977 OUTS (outf, " BY ");
3978 OUTS (outf, dregs_lo (src0));
3979 OUTS (outf, " (S)");
3980 }
3981 else if (HLs == 3 && sop == 1 && sopcde == 0)
3982 {
3983 OUTS (outf, dregs_hi (dst0));
3984 OUTS (outf, " = ASHIFT ");
3985 OUTS (outf, dregs_hi (src1));
3986 OUTS (outf, " BY ");
3987 OUTS (outf, dregs_lo (src0));
3988 OUTS (outf, " (S)");
3989 }
3990 else if (sop == 2 && sopcde == 0)
3991 {
3992 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3993 OUTS (outf, " = LSHIFT ");
3994 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3995 OUTS (outf, " BY ");
3996 OUTS (outf, dregs_lo (src0));
3997 }
3998 else if (sop == 0 && sopcde == 3)
3999 {
4000 OUTS (outf, acc01);
4001 OUTS (outf, " = ASHIFT ");
4002 OUTS (outf, acc01);
4003 OUTS (outf, " BY ");
4004 OUTS (outf, dregs_lo (src0));
4005 }
4006 else if (sop == 1 && sopcde == 3)
4007 {
4008 OUTS (outf, acc01);
4009 OUTS (outf, " = LSHIFT ");
4010 OUTS (outf, acc01);
4011 OUTS (outf, " BY ");
4012 OUTS (outf, dregs_lo (src0));
4013 }
4014 else if (sop == 2 && sopcde == 3)
4015 {
4016 OUTS (outf, acc01);
4017 OUTS (outf, " = ROT ");
4018 OUTS (outf, acc01);
4019 OUTS (outf, " BY ");
4020 OUTS (outf, dregs_lo (src0));
4021 }
4022 else if (sop == 3 && sopcde == 3)
4023 {
4024 OUTS (outf, dregs (dst0));
4025 OUTS (outf, " = ROT ");
4026 OUTS (outf, dregs (src1));
4027 OUTS (outf, " BY ");
4028 OUTS (outf, dregs_lo (src0));
4029 }
4030 else if (sop == 1 && sopcde == 1)
4031 {
4032 OUTS (outf, dregs (dst0));
4033 OUTS (outf, " = ASHIFT ");
4034 OUTS (outf, dregs (src1));
4035 OUTS (outf, " BY ");
4036 OUTS (outf, dregs_lo (src0));
4037 OUTS (outf, " (V, S)");
4038 }
4039 else if (sop == 0 && sopcde == 1)
4040 {
4041 OUTS (outf, dregs (dst0));
4042 OUTS (outf, " = ASHIFT ");
4043 OUTS (outf, dregs (src1));
4044 OUTS (outf, " BY ");
4045 OUTS (outf, dregs_lo (src0));
4046 OUTS (outf, " (V)");
4047 }
4048 else if (sop == 0 && sopcde == 2)
4049 {
4050 OUTS (outf, dregs (dst0));
4051 OUTS (outf, " = ASHIFT ");
4052 OUTS (outf, dregs (src1));
4053 OUTS (outf, " BY ");
4054 OUTS (outf, dregs_lo (src0));
4055 }
4056 else if (sop == 1 && sopcde == 2)
4057 {
4058 OUTS (outf, dregs (dst0));
4059 OUTS (outf, " = ASHIFT ");
4060 OUTS (outf, dregs (src1));
4061 OUTS (outf, " BY ");
4062 OUTS (outf, dregs_lo (src0));
4063 OUTS (outf, " (S)");
4064 }
4065 else if (sop == 2 && sopcde == 2)
4066 {
4067 OUTS (outf, dregs (dst0));
4068 OUTS (outf, " = LSHIFT ");
4069 OUTS (outf, dregs (src1));
4070 OUTS (outf, " BY ");
4071 OUTS (outf, dregs_lo (src0));
4072 }
4073 else if (sop == 3 && sopcde == 2)
4074 {
4075 OUTS (outf, dregs (dst0));
4076 OUTS (outf, " = ROT ");
4077 OUTS (outf, dregs (src1));
4078 OUTS (outf, " BY ");
4079 OUTS (outf, dregs_lo (src0));
4080 }
4081 else if (sop == 2 && sopcde == 1)
4082 {
4083 OUTS (outf, dregs (dst0));
4084 OUTS (outf, " = LSHIFT ");
4085 OUTS (outf, dregs (src1));
4086 OUTS (outf, " BY ");
4087 OUTS (outf, dregs_lo (src0));
4088 OUTS (outf, " (V)");
4089 }
4090 else if (sop == 0 && sopcde == 4)
4091 {
4092 OUTS (outf, dregs (dst0));
4093 OUTS (outf, " = PACK (");
4094 OUTS (outf, dregs_lo (src1));
4095 OUTS (outf, ", ");
4096 OUTS (outf, dregs_lo (src0));
4097 OUTS (outf, ")");
4098 }
4099 else if (sop == 1 && sopcde == 4)
4100 {
4101 OUTS (outf, dregs (dst0));
4102 OUTS (outf, " = PACK (");
4103 OUTS (outf, dregs_lo (src1));
4104 OUTS (outf, ", ");
4105 OUTS (outf, dregs_hi (src0));
4106 OUTS (outf, ")");
4107 }
4108 else if (sop == 2 && sopcde == 4)
4109 {
4110 OUTS (outf, dregs (dst0));
4111 OUTS (outf, " = PACK (");
4112 OUTS (outf, dregs_hi (src1));
4113 OUTS (outf, ", ");
4114 OUTS (outf, dregs_lo (src0));
4115 OUTS (outf, ")");
4116 }
4117 else if (sop == 3 && sopcde == 4)
4118 {
4119 OUTS (outf, dregs (dst0));
4120 OUTS (outf, " = PACK (");
4121 OUTS (outf, dregs_hi (src1));
4122 OUTS (outf, ", ");
4123 OUTS (outf, dregs_hi (src0));
4124 OUTS (outf, ")");
4125 }
4126 else if (sop == 0 && sopcde == 5)
4127 {
4128 OUTS (outf, dregs_lo (dst0));
4129 OUTS (outf, " = SIGNBITS ");
4130 OUTS (outf, dregs (src1));
4131 }
4132 else if (sop == 1 && sopcde == 5)
4133 {
4134 OUTS (outf, dregs_lo (dst0));
4135 OUTS (outf, " = SIGNBITS ");
4136 OUTS (outf, dregs_lo (src1));
4137 }
4138 else if (sop == 2 && sopcde == 5)
4139 {
4140 OUTS (outf, dregs_lo (dst0));
4141 OUTS (outf, " = SIGNBITS ");
4142 OUTS (outf, dregs_hi (src1));
4143 }
4144 else if (sop == 0 && sopcde == 6)
4145 {
4146 OUTS (outf, dregs_lo (dst0));
4147 OUTS (outf, " = SIGNBITS A0");
4148 }
4149 else if (sop == 1 && sopcde == 6)
4150 {
4151 OUTS (outf, dregs_lo (dst0));
4152 OUTS (outf, " = SIGNBITS A1");
4153 }
4154 else if (sop == 3 && sopcde == 6)
4155 {
4156 OUTS (outf, dregs_lo (dst0));
4157 OUTS (outf, " = ONES ");
4158 OUTS (outf, dregs (src1));
4159 }
4160 else if (sop == 0 && sopcde == 7)
4161 {
4162 OUTS (outf, dregs_lo (dst0));
4163 OUTS (outf, " = EXPADJ (");
4164 OUTS (outf, dregs (src1));
4165 OUTS (outf, ", ");
4166 OUTS (outf, dregs_lo (src0));
4167 OUTS (outf, ")");
4168 }
4169 else if (sop == 1 && sopcde == 7)
4170 {
4171 OUTS (outf, dregs_lo (dst0));
4172 OUTS (outf, " = EXPADJ (");
4173 OUTS (outf, dregs (src1));
4174 OUTS (outf, ", ");
4175 OUTS (outf, dregs_lo (src0));
4176 OUTS (outf, ") (V)");
4177 }
4178 else if (sop == 2 && sopcde == 7)
4179 {
4180 OUTS (outf, dregs_lo (dst0));
4181 OUTS (outf, " = EXPADJ (");
4182 OUTS (outf, dregs_lo (src1));
4183 OUTS (outf, ", ");
4184 OUTS (outf, dregs_lo (src0));
4185 OUTS (outf, ")");
4186 }
4187 else if (sop == 3 && sopcde == 7)
4188 {
4189 OUTS (outf, dregs_lo (dst0));
4190 OUTS (outf, " = EXPADJ (");
4191 OUTS (outf, dregs_hi (src1));
4192 OUTS (outf, ", ");
4193 OUTS (outf, dregs_lo (src0));
4194 OUTS (outf, ")");
4195 }
4196 else if (sop == 0 && sopcde == 8)
4197 {
4198 OUTS (outf, "BITMUX (");
4199 OUTS (outf, dregs (src0));
4200 OUTS (outf, ", ");
4201 OUTS (outf, dregs (src1));
4202 OUTS (outf, ", A0) (ASR)");
4203 }
4204 else if (sop == 1 && sopcde == 8)
4205 {
4206 OUTS (outf, "BITMUX (");
4207 OUTS (outf, dregs (src0));
4208 OUTS (outf, ", ");
4209 OUTS (outf, dregs (src1));
4210 OUTS (outf, ", A0) (ASL)");
4211 }
4212 else if (sop == 0 && sopcde == 9)
4213 {
4214 OUTS (outf, dregs_lo (dst0));
4215 OUTS (outf, " = VIT_MAX (");
4216 OUTS (outf, dregs (src1));
4217 OUTS (outf, ") (ASL)");
4218 }
4219 else if (sop == 1 && sopcde == 9)
4220 {
4221 OUTS (outf, dregs_lo (dst0));
4222 OUTS (outf, " = VIT_MAX (");
4223 OUTS (outf, dregs (src1));
4224 OUTS (outf, ") (ASR)");
4225 }
4226 else if (sop == 2 && sopcde == 9)
4227 {
4228 OUTS (outf, dregs (dst0));
4229 OUTS (outf, " = VIT_MAX (");
4230 OUTS (outf, dregs (src1));
4231 OUTS (outf, ", ");
4232 OUTS (outf, dregs (src0));
4233 OUTS (outf, ") (ASL)");
4234 }
4235 else if (sop == 3 && sopcde == 9)
4236 {
4237 OUTS (outf, dregs (dst0));
4238 OUTS (outf, " = VIT_MAX (");
4239 OUTS (outf, dregs (src1));
4240 OUTS (outf, ", ");
4241 OUTS (outf, dregs (src0));
4242 OUTS (outf, ") (ASR)");
4243 }
4244 else if (sop == 0 && sopcde == 10)
4245 {
4246 OUTS (outf, dregs (dst0));
4247 OUTS (outf, " = EXTRACT (");
4248 OUTS (outf, dregs (src1));
4249 OUTS (outf, ", ");
4250 OUTS (outf, dregs_lo (src0));
4251 OUTS (outf, ") (Z)");
4252 }
4253 else if (sop == 1 && sopcde == 10)
4254 {
4255 OUTS (outf, dregs (dst0));
4256 OUTS (outf, " = EXTRACT (");
4257 OUTS (outf, dregs (src1));
4258 OUTS (outf, ", ");
4259 OUTS (outf, dregs_lo (src0));
4260 OUTS (outf, ") (X)");
4261 }
4262 else if (sop == 2 && sopcde == 10)
4263 {
4264 OUTS (outf, dregs (dst0));
4265 OUTS (outf, " = DEPOSIT (");
4266 OUTS (outf, dregs (src1));
4267 OUTS (outf, ", ");
4268 OUTS (outf, dregs (src0));
4269 OUTS (outf, ")");
4270 }
4271 else if (sop == 3 && sopcde == 10)
4272 {
4273 OUTS (outf, dregs (dst0));
4274 OUTS (outf, " = DEPOSIT (");
4275 OUTS (outf, dregs (src1));
4276 OUTS (outf, ", ");
4277 OUTS (outf, dregs (src0));
4278 OUTS (outf, ") (X)");
4279 }
4280 else if (sop == 0 && sopcde == 11)
4281 {
4282 OUTS (outf, dregs_lo (dst0));
4283 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4284 OUTS (outf, dregs (src0));
4285 OUTS (outf, ")");
4286 }
4287 else if (sop == 1 && sopcde == 11)
4288 {
4289 OUTS (outf, dregs_lo (dst0));
4290 OUTS (outf, " = CC = BXOR (A0, ");
4291 OUTS (outf, dregs (src0));
4292 OUTS (outf, ")");
4293 }
4294 else if (sop == 0 && sopcde == 12)
4295 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4296
4297 else if (sop == 1 && sopcde == 12)
4298 {
4299 OUTS (outf, dregs_lo (dst0));
4300 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4301 }
4302 else if (sop == 0 && sopcde == 13)
4303 {
4304 OUTS (outf, dregs (dst0));
4305 OUTS (outf, " = ALIGN8 (");
4306 OUTS (outf, dregs (src1));
4307 OUTS (outf, ", ");
4308 OUTS (outf, dregs (src0));
4309 OUTS (outf, ")");
4310 }
4311 else if (sop == 1 && sopcde == 13)
4312 {
4313 OUTS (outf, dregs (dst0));
4314 OUTS (outf, " = ALIGN16 (");
4315 OUTS (outf, dregs (src1));
4316 OUTS (outf, ", ");
4317 OUTS (outf, dregs (src0));
4318 OUTS (outf, ")");
4319 }
4320 else if (sop == 2 && sopcde == 13)
4321 {
4322 OUTS (outf, dregs (dst0));
4323 OUTS (outf, " = ALIGN24 (");
4324 OUTS (outf, dregs (src1));
4325 OUTS (outf, ", ");
4326 OUTS (outf, dregs (src0));
4327 OUTS (outf, ")");
4328 }
4329 else
4330 return 0;
4331
4332 return 4;
4333 }
4334
4335 static int
4336 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4337 {
4338 /* dsp32shiftimm
4339 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4340 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4341 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4342 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4343 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4344 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4345 int bit8 = ((iw1 >> 8) & 0x1);
4346 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4347 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4348 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4349 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4350 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4351
4352
4353 if (sop == 0 && sopcde == 0)
4354 {
4355 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4356 OUTS (outf, " = ");
4357 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4358 OUTS (outf, " >>> ");
4359 OUTS (outf, uimm4 (newimmag));
4360 }
4361 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4362 {
4363 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4364 OUTS (outf, " = ");
4365 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4366 OUTS (outf, " << ");
4367 OUTS (outf, uimm4 (immag));
4368 OUTS (outf, " (S)");
4369 }
4370 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4371 {
4372 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4373 OUTS (outf, " = ");
4374 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4375 OUTS (outf, " >>> ");
4376 OUTS (outf, uimm4 (newimmag));
4377 OUTS (outf, " (S)");
4378 }
4379 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4380 {
4381 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4382 OUTS (outf, " = ");
4383 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4384 OUTS (outf, " << ");
4385 OUTS (outf, uimm4 (immag));
4386 }
4387 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4388 {
4389 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4390 OUTS (outf, " = ");
4391 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4392 OUTS (outf, " >> ");
4393 OUTS (outf, uimm4 (newimmag));
4394 }
4395 else if (sop == 2 && sopcde == 3 && HLs == 1)
4396 {
4397 OUTS (outf, "A1 = ROT A1 BY ");
4398 OUTS (outf, imm6 (immag));
4399 }
4400 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4401 {
4402 OUTS (outf, "A0 = A0 << ");
4403 OUTS (outf, uimm5 (immag));
4404 }
4405 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4406 {
4407 OUTS (outf, "A0 = A0 >>> ");
4408 OUTS (outf, uimm5 (newimmag));
4409 }
4410 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4411 {
4412 OUTS (outf, "A1 = A1 << ");
4413 OUTS (outf, uimm5 (immag));
4414 }
4415 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4416 {
4417 OUTS (outf, "A1 = A1 >>> ");
4418 OUTS (outf, uimm5 (newimmag));
4419 }
4420 else if (sop == 1 && sopcde == 3 && HLs == 0)
4421 {
4422 OUTS (outf, "A0 = A0 >> ");
4423 OUTS (outf, uimm5 (newimmag));
4424 }
4425 else if (sop == 1 && sopcde == 3 && HLs == 1)
4426 {
4427 OUTS (outf, "A1 = A1 >> ");
4428 OUTS (outf, uimm5 (newimmag));
4429 }
4430 else if (sop == 2 && sopcde == 3 && HLs == 0)
4431 {
4432 OUTS (outf, "A0 = ROT A0 BY ");
4433 OUTS (outf, imm6 (immag));
4434 }
4435 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4436 {
4437 OUTS (outf, dregs (dst0));
4438 OUTS (outf, " = ");
4439 OUTS (outf, dregs (src1));
4440 OUTS (outf, " << ");
4441 OUTS (outf, uimm5 (immag));
4442 OUTS (outf, " (V, S)");
4443 }
4444 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4445 {
4446 OUTS (outf, dregs (dst0));
4447 OUTS (outf, " = ");
4448 OUTS (outf, dregs (src1));
4449 OUTS (outf, " >>> ");
4450 OUTS (outf, imm5 (-immag));
4451 OUTS (outf, " (V)");
4452 }
4453 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4454 {
4455 OUTS (outf, dregs (dst0));
4456 OUTS (outf, " = ");
4457 OUTS (outf, dregs (src1));
4458 OUTS (outf, " >> ");
4459 OUTS (outf, uimm5 (newimmag));
4460 OUTS (outf, " (V)");
4461 }
4462 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4463 {
4464 OUTS (outf, dregs (dst0));
4465 OUTS (outf, " = ");
4466 OUTS (outf, dregs (src1));
4467 OUTS (outf, " << ");
4468 OUTS (outf, imm5 (immag));
4469 OUTS (outf, " (V)");
4470 }
4471 else if (sop == 0 && sopcde == 1)
4472 {
4473 OUTS (outf, dregs (dst0));
4474 OUTS (outf, " = ");
4475 OUTS (outf, dregs (src1));
4476 OUTS (outf, " >>> ");
4477 OUTS (outf, uimm5 (newimmag));
4478 OUTS (outf, " (V)");
4479 }
4480 else if (sop == 1 && sopcde == 2)
4481 {
4482 OUTS (outf, dregs (dst0));
4483 OUTS (outf, " = ");
4484 OUTS (outf, dregs (src1));
4485 OUTS (outf, " << ");
4486 OUTS (outf, uimm5 (immag));
4487 OUTS (outf, " (S)");
4488 }
4489 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4490 {
4491 OUTS (outf, dregs (dst0));
4492 OUTS (outf, " = ");
4493 OUTS (outf, dregs (src1));
4494 OUTS (outf, " >> ");
4495 OUTS (outf, uimm5 (newimmag));
4496 }
4497 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4498 {
4499 OUTS (outf, dregs (dst0));
4500 OUTS (outf, " = ");
4501 OUTS (outf, dregs (src1));
4502 OUTS (outf, " << ");
4503 OUTS (outf, uimm5 (immag));
4504 }
4505 else if (sop == 3 && sopcde == 2)
4506 {
4507 OUTS (outf, dregs (dst0));
4508 OUTS (outf, " = ROT ");
4509 OUTS (outf, dregs (src1));
4510 OUTS (outf, " BY ");
4511 OUTS (outf, imm6 (immag));
4512 }
4513 else if (sop == 0 && sopcde == 2)
4514 {
4515 OUTS (outf, dregs (dst0));
4516 OUTS (outf, " = ");
4517 OUTS (outf, dregs (src1));
4518 OUTS (outf, " >>> ");
4519 OUTS (outf, uimm5 (newimmag));
4520 }
4521 else
4522 return 0;
4523
4524 return 4;
4525 }
4526
4527 static int
4528 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4529 {
4530 /* pseudoDEBUG
4531 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4532 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4533 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4534 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4535 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4536 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4537
4538 if (reg == 0 && fn == 3)
4539 OUTS (outf, "DBG A0");
4540
4541 else if (reg == 1 && fn == 3)
4542 OUTS (outf, "DBG A1");
4543
4544 else if (reg == 3 && fn == 3)
4545 OUTS (outf, "ABORT");
4546
4547 else if (reg == 4 && fn == 3)
4548 OUTS (outf, "HLT");
4549
4550 else if (reg == 5 && fn == 3)
4551 OUTS (outf, "DBGHALT");
4552
4553 else if (reg == 6 && fn == 3)
4554 {
4555 OUTS (outf, "DBGCMPLX (");
4556 OUTS (outf, dregs (grp));
4557 OUTS (outf, ")");
4558 }
4559 else if (reg == 7 && fn == 3)
4560 OUTS (outf, "DBG");
4561
4562 else if (grp == 0 && fn == 2)
4563 {
4564 OUTS (outf, "OUTC ");
4565 OUTS (outf, dregs (reg));
4566 }
4567 else if (fn == 0)
4568 {
4569 OUTS (outf, "DBG ");
4570 OUTS (outf, allregs (reg, grp));
4571 }
4572 else if (fn == 1)
4573 {
4574 OUTS (outf, "PRNT");
4575 OUTS (outf, allregs (reg, grp));
4576 }
4577 else
4578 return 0;
4579
4580 return 2;
4581 }
4582
4583 static int
4584 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4585 {
4586 /* psedoOChar
4587 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4588 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4589 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4590 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4591
4592 OUTS (outf, "OUTC ");
4593 OUTS (outf, uimm8 (ch));
4594
4595 return 2;
4596 }
4597
4598 static int
4599 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4600 {
4601 /* pseudodbg_assert
4602 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4603 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4604 |.expected......................................................|
4605 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4606 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4607 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4608 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4609 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4610
4611 if (dbgop == 0)
4612 {
4613 OUTS (outf, "DBGA (");
4614 OUTS (outf, regs_lo (regtest, grp));
4615 OUTS (outf, ", ");
4616 OUTS (outf, uimm16 (expected));
4617 OUTS (outf, ")");
4618 }
4619 else if (dbgop == 1)
4620 {
4621 OUTS (outf, "DBGA (");
4622 OUTS (outf, regs_hi (regtest, grp));
4623 OUTS (outf, ", ");
4624 OUTS (outf, uimm16 (expected));
4625 OUTS (outf, ")");
4626 }
4627 else if (dbgop == 2)
4628 {
4629 OUTS (outf, "DBGAL (");
4630 OUTS (outf, allregs (regtest, grp));
4631 OUTS (outf, ", ");
4632 OUTS (outf, uimm16 (expected));
4633 OUTS (outf, ")");
4634 }
4635 else if (dbgop == 3)
4636 {
4637 OUTS (outf, "DBGAH (");
4638 OUTS (outf, allregs (regtest, grp));
4639 OUTS (outf, ", ");
4640 OUTS (outf, uimm16 (expected));
4641 OUTS (outf, ")");
4642 }
4643 else
4644 return 0;
4645 return 4;
4646 }
4647
4648 static int
4649 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4650 {
4651 bfd_byte buf[4];
4652 TIword iw0;
4653 TIword iw1;
4654 int status;
4655 int rv = 0;
4656
4657 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4658 /* FIXME */
4659 (void) status;
4660 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4661 /* FIXME */
4662 (void) status;
4663
4664 iw0 = bfd_getl16 (buf);
4665 iw1 = bfd_getl16 (buf + 2);
4666
4667 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4668 {
4669 OUTS (outf, "MNOP");
4670 return 4;
4671 }
4672 else if ((iw0 & 0xff00) == 0x0000)
4673 rv = decode_ProgCtrl_0 (iw0, outf);
4674 else if ((iw0 & 0xffc0) == 0x0240)
4675 rv = decode_CaCTRL_0 (iw0, outf);
4676 else if ((iw0 & 0xff80) == 0x0100)
4677 rv = decode_PushPopReg_0 (iw0, outf);
4678 else if ((iw0 & 0xfe00) == 0x0400)
4679 rv = decode_PushPopMultiple_0 (iw0, outf);
4680 else if ((iw0 & 0xfe00) == 0x0600)
4681 rv = decode_ccMV_0 (iw0, outf);
4682 else if ((iw0 & 0xf800) == 0x0800)
4683 rv = decode_CCflag_0 (iw0, outf);
4684 else if ((iw0 & 0xffe0) == 0x0200)
4685 rv = decode_CC2dreg_0 (iw0, outf);
4686 else if ((iw0 & 0xff00) == 0x0300)
4687 rv = decode_CC2stat_0 (iw0, outf);
4688 else if ((iw0 & 0xf000) == 0x1000)
4689 rv = decode_BRCC_0 (iw0, pc, outf);
4690 else if ((iw0 & 0xf000) == 0x2000)
4691 rv = decode_UJUMP_0 (iw0, pc, outf);
4692 else if ((iw0 & 0xf000) == 0x3000)
4693 rv = decode_REGMV_0 (iw0, outf);
4694 else if ((iw0 & 0xfc00) == 0x4000)
4695 rv = decode_ALU2op_0 (iw0, outf);
4696 else if ((iw0 & 0xfe00) == 0x4400)
4697 rv = decode_PTR2op_0 (iw0, outf);
4698 else if ((iw0 & 0xf800) == 0x4800)
4699 rv = decode_LOGI2op_0 (iw0, outf);
4700 else if ((iw0 & 0xf000) == 0x5000)
4701 rv = decode_COMP3op_0 (iw0, outf);
4702 else if ((iw0 & 0xf800) == 0x6000)
4703 rv = decode_COMPI2opD_0 (iw0, outf);
4704 else if ((iw0 & 0xf800) == 0x6800)
4705 rv = decode_COMPI2opP_0 (iw0, outf);
4706 else if ((iw0 & 0xf000) == 0x8000)
4707 rv = decode_LDSTpmod_0 (iw0, outf);
4708 else if ((iw0 & 0xff60) == 0x9e60)
4709 rv = decode_dagMODim_0 (iw0, outf);
4710 else if ((iw0 & 0xfff0) == 0x9f60)
4711 rv = decode_dagMODik_0 (iw0, outf);
4712 else if ((iw0 & 0xfc00) == 0x9c00)
4713 rv = decode_dspLDST_0 (iw0, outf);
4714 else if ((iw0 & 0xf000) == 0x9000)
4715 rv = decode_LDST_0 (iw0, outf);
4716 else if ((iw0 & 0xfc00) == 0xb800)
4717 rv = decode_LDSTiiFP_0 (iw0, outf);
4718 else if ((iw0 & 0xe000) == 0xA000)
4719 rv = decode_LDSTii_0 (iw0, outf);
4720 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4721 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4722 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4723 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4724 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4725 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4726 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4727 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4728 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4729 rv = decode_linkage_0 (iw0, iw1, outf);
4730 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4731 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4732 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4733 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4734 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4735 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4736 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4737 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4738 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4739 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4740 else if ((iw0 & 0xff00) == 0xf800)
4741 rv = decode_pseudoDEBUG_0 (iw0, outf);
4742 else if ((iw0 & 0xFF00) == 0xF900)
4743 rv = decode_pseudoOChar_0 (iw0, outf);
4744 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4745 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4746
4747 return rv;
4748 }
4749
4750
4751 int
4752 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4753 {
4754 bfd_byte buf[2];
4755 unsigned short iw0;
4756 int status;
4757 int count = 0;
4758
4759 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4760 /* FIXME */
4761 (void) status;
4762 iw0 = bfd_getl16 (buf);
4763
4764 count += _print_insn_bfin (pc, outf);
4765
4766 /* Proper display of multiple issue instructions. */
4767
4768 if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4769 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4770 {
4771 parallel = 1;
4772 outf->fprintf_func (outf->stream, " || ");
4773 count += _print_insn_bfin (pc + 4, outf);
4774 outf->fprintf_func (outf->stream, " || ");
4775 count += _print_insn_bfin (pc + 6, outf);
4776 parallel = 0;
4777 }
4778 if (count == 0)
4779 {
4780 outf->fprintf_func (outf->stream, "ILLEGAL");
4781 return 2;
4782 }
4783 if (!comment)
4784 outf->fprintf_func (outf->stream, ";");
4785
4786 comment = 0;
4787
4788 return count;
4789 }
GDB Binutils - Deliverables
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