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opcodes: blackfin: push down global state
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright (C) 2005-2014 Free Software Foundation, Inc.
3
4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include "sysdep.h"
22 #include <stdio.h>
23
24 #include "opcode/bfin.h"
25
26 #ifndef PRINTF
27 #define PRINTF printf
28 #endif
29
30 #ifndef EXIT
31 #define EXIT exit
32 #endif
33
34 typedef long TIword;
35
36 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
37 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
38 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
39 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
40
41 #include "dis-asm.h"
42
43 typedef unsigned int bu32;
44
45 struct private
46 {
47 int comment, parallel;
48 };
49
50 typedef enum
51 {
52 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
53 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
57 } const_forms_t;
58
59 static const struct
60 {
61 const char *name;
62 const int nbits;
63 const char reloc;
64 const char issigned;
65 const char pcrel;
66 const char scale;
67 const char offset;
68 const char negative;
69 const char positive;
70 const char decimal;
71 const char leading;
72 const char exact;
73 } constant_formats[] =
74 {
75 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
109 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
118 };
119
120 static const char *
121 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
122 {
123 static char buf[60];
124
125 if (constant_formats[cf].reloc)
126 {
127 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
128 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
129 if (constant_formats[cf].pcrel)
130 ea += pc;
131
132 /* truncate to 32-bits for proper symbol lookup/matching */
133 ea = (bu32)ea;
134
135 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
136 {
137 outf->print_address_func (ea, outf);
138 return "";
139 }
140 else
141 {
142 sprintf (buf, "%lx", (unsigned long) x);
143 return buf;
144 }
145 }
146
147 /* Negative constants have an implied sign bit. */
148 if (constant_formats[cf].negative)
149 {
150 int nb = constant_formats[cf].nbits + 1;
151
152 x = x | (1 << constant_formats[cf].nbits);
153 x = SIGNEXTEND (x, nb);
154 }
155 else
156 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
157
158 if (constant_formats[cf].offset)
159 x += constant_formats[cf].offset;
160
161 if (constant_formats[cf].scale)
162 x <<= constant_formats[cf].scale;
163
164 if (constant_formats[cf].decimal)
165 sprintf (buf, "%*li", constant_formats[cf].leading, x);
166 else
167 {
168 if (constant_formats[cf].issigned && x < 0)
169 sprintf (buf, "-0x%x", abs (x));
170 else
171 sprintf (buf, "0x%lx", (unsigned long) x);
172 }
173
174 return buf;
175 }
176
177 static bu32
178 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
179 {
180 if (0 && constant_formats[cf].reloc)
181 {
182 bu32 ea = (((constant_formats[cf].pcrel
183 ? SIGNEXTEND (x, constant_formats[cf].nbits)
184 : x) + constant_formats[cf].offset)
185 << constant_formats[cf].scale);
186 if (constant_formats[cf].pcrel)
187 ea += pc;
188
189 return ea;
190 }
191
192 /* Negative constants have an implied sign bit. */
193 if (constant_formats[cf].negative)
194 {
195 int nb = constant_formats[cf].nbits + 1;
196 x = x | (1 << constant_formats[cf].nbits);
197 x = SIGNEXTEND (x, nb);
198 }
199 else if (constant_formats[cf].issigned)
200 x = SIGNEXTEND (x, constant_formats[cf].nbits);
201
202 x += constant_formats[cf].offset;
203 x <<= constant_formats[cf].scale;
204
205 return x;
206 }
207
208 enum machine_registers
209 {
210 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
211 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
212 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
213 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
214 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
215 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
216 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
217 REG_L2, REG_L3,
218 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
219 REG_AQ, REG_V, REG_VS,
220 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
221 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
222 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
223 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
224 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
225 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
226 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
227 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
228 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
229 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
230 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
231 REG_LASTREG,
232 };
233
234 enum reg_class
235 {
236 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
237 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
238 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
239 rc_sysregs3, rc_allregs,
240 LIM_REG_CLASSES
241 };
242
243 static const char * const reg_names[] =
244 {
245 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
246 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
247 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
248 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
249 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
250 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
251 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
252 "L2", "L3",
253 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
254 "AQ", "V", "VS",
255 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
256 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
257 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
258 "RETE", "EMUDAT",
259 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
260 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
261 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
262 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
263 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
264 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
265 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
266 "AC0_COPY", "V_COPY", "RND_MOD",
267 "LASTREG",
268 0
269 };
270
271 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
272
273 /* RL(0..7). */
274 static const enum machine_registers decode_dregs_lo[] =
275 {
276 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
277 };
278
279 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
280
281 /* RH(0..7). */
282 static const enum machine_registers decode_dregs_hi[] =
283 {
284 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
285 };
286
287 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
288
289 /* R(0..7). */
290 static const enum machine_registers decode_dregs[] =
291 {
292 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
293 };
294
295 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
296
297 /* R BYTE(0..7). */
298 static const enum machine_registers decode_dregs_byte[] =
299 {
300 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
301 };
302
303 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
304
305 /* P(0..5) SP FP. */
306 static const enum machine_registers decode_pregs[] =
307 {
308 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
309 };
310
311 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
312 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
313 #define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
314 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
315 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
316 #define accum(x) REGNAME (decode_accum[(x) & 1])
317
318 /* I(0..3). */
319 static const enum machine_registers decode_iregs[] =
320 {
321 REG_I0, REG_I1, REG_I2, REG_I3,
322 };
323
324 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
325
326 /* M(0..3). */
327 static const enum machine_registers decode_mregs[] =
328 {
329 REG_M0, REG_M1, REG_M2, REG_M3,
330 };
331
332 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
333 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
334 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
335
336 /* dregs pregs. */
337 static const enum machine_registers decode_dpregs[] =
338 {
339 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
340 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
341 };
342
343 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
344
345 /* [dregs pregs]. */
346 static const enum machine_registers decode_gregs[] =
347 {
348 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
349 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
350 };
351
352 #define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
353
354 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
355 static const enum machine_registers decode_regs[] =
356 {
357 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
358 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
359 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
360 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
361 };
362
363 #define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
364
365 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
366 static const enum machine_registers decode_regs_lo[] =
367 {
368 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
369 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
370 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
371 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
372 };
373
374 #define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
375
376 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
377 static const enum machine_registers decode_regs_hi[] =
378 {
379 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
380 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
381 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
382 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
383 };
384
385 #define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
386
387 static const enum machine_registers decode_statbits[] =
388 {
389 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
390 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
391 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
392 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
393 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
394 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
395 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
396 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
397 };
398
399 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
400
401 /* LC0 LC1. */
402 static const enum machine_registers decode_counters[] =
403 {
404 REG_LC0, REG_LC1,
405 };
406
407 #define counters(x) REGNAME (decode_counters[(x) & 1])
408 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
409
410 /* [dregs pregs (iregs mregs) (bregs lregs)
411 dregs2_sysregs1 open sysregs2 sysregs3]. */
412 static const enum machine_registers decode_allregs[] =
413 {
414 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
415 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
416 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
417 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
418 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
419 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
420 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
421 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
422 REG_LASTREG,
423 };
424
425 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
426 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
427 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
428 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
429 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
430 #define IS_SYSREG(g,r) \
431 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
432 #define IS_RESERVEDREG(g,r) \
433 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
434
435 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
436 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
437
438 #define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
439 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
440 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
441 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
442 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
443 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
444 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
445 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
446 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
447 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
448 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
449 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
450 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
451 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
452 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
453 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
454 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
455 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
456 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
457 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
458 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
459 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
460 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
461 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
462 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
463 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
464 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
465 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
466 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
467 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
468 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
469 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
470 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
471 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
472 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
473 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
474 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
475 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
476 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
477 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
478 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
479 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
480 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
481
482 /* (arch.pm)arch_disassembler_functions. */
483 #ifndef OUTS
484 #define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
485 #endif
486
487 static void
488 amod0 (int s0, int x0, disassemble_info *outf)
489 {
490 if (s0 == 1 && x0 == 0)
491 OUTS (outf, " (S)");
492 else if (s0 == 0 && x0 == 1)
493 OUTS (outf, " (CO)");
494 else if (s0 == 1 && x0 == 1)
495 OUTS (outf, " (SCO)");
496 }
497
498 static void
499 amod1 (int s0, int x0, disassemble_info *outf)
500 {
501 if (s0 == 0 && x0 == 0)
502 OUTS (outf, " (NS)");
503 else if (s0 == 1 && x0 == 0)
504 OUTS (outf, " (S)");
505 }
506
507 static void
508 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
509 {
510 if (s0 == 1 && x0 == 0 && aop0 == 0)
511 OUTS (outf, " (S)");
512 else if (s0 == 0 && x0 == 1 && aop0 == 0)
513 OUTS (outf, " (CO)");
514 else if (s0 == 1 && x0 == 1 && aop0 == 0)
515 OUTS (outf, " (SCO)");
516 else if (s0 == 0 && x0 == 0 && aop0 == 2)
517 OUTS (outf, " (ASR)");
518 else if (s0 == 1 && x0 == 0 && aop0 == 2)
519 OUTS (outf, " (S, ASR)");
520 else if (s0 == 0 && x0 == 1 && aop0 == 2)
521 OUTS (outf, " (CO, ASR)");
522 else if (s0 == 1 && x0 == 1 && aop0 == 2)
523 OUTS (outf, " (SCO, ASR)");
524 else if (s0 == 0 && x0 == 0 && aop0 == 3)
525 OUTS (outf, " (ASL)");
526 else if (s0 == 1 && x0 == 0 && aop0 == 3)
527 OUTS (outf, " (S, ASL)");
528 else if (s0 == 0 && x0 == 1 && aop0 == 3)
529 OUTS (outf, " (CO, ASL)");
530 else if (s0 == 1 && x0 == 1 && aop0 == 3)
531 OUTS (outf, " (SCO, ASL)");
532 }
533
534 static void
535 searchmod (int r0, disassemble_info *outf)
536 {
537 if (r0 == 0)
538 OUTS (outf, "GT");
539 else if (r0 == 1)
540 OUTS (outf, "GE");
541 else if (r0 == 2)
542 OUTS (outf, "LT");
543 else if (r0 == 3)
544 OUTS (outf, "LE");
545 }
546
547 static void
548 aligndir (int r0, disassemble_info *outf)
549 {
550 if (r0 == 1)
551 OUTS (outf, " (R)");
552 }
553
554 static int
555 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
556 {
557 const char *s0, *s1;
558
559 if (h0)
560 s0 = dregs_hi (src0);
561 else
562 s0 = dregs_lo (src0);
563
564 if (h1)
565 s1 = dregs_hi (src1);
566 else
567 s1 = dregs_lo (src1);
568
569 OUTS (outf, s0);
570 OUTS (outf, " * ");
571 OUTS (outf, s1);
572 return 0;
573 }
574
575 static int
576 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
577 {
578 const char *a;
579 const char *sop = "<unknown op>";
580
581 if (which)
582 a = "A1";
583 else
584 a = "A0";
585
586 if (op == 3)
587 {
588 OUTS (outf, a);
589 return 0;
590 }
591
592 switch (op)
593 {
594 case 0: sop = " = "; break;
595 case 1: sop = " += "; break;
596 case 2: sop = " -= "; break;
597 default: break;
598 }
599
600 OUTS (outf, a);
601 OUTS (outf, sop);
602 decode_multfunc (h0, h1, src0, src1, outf);
603
604 return 0;
605 }
606
607 static void
608 decode_optmode (int mod, int MM, disassemble_info *outf)
609 {
610 if (mod == 0 && MM == 0)
611 return;
612
613 OUTS (outf, " (");
614
615 if (MM && !mod)
616 {
617 OUTS (outf, "M)");
618 return;
619 }
620
621 if (MM)
622 OUTS (outf, "M, ");
623
624 if (mod == M_S2RND)
625 OUTS (outf, "S2RND");
626 else if (mod == M_T)
627 OUTS (outf, "T");
628 else if (mod == M_W32)
629 OUTS (outf, "W32");
630 else if (mod == M_FU)
631 OUTS (outf, "FU");
632 else if (mod == M_TFU)
633 OUTS (outf, "TFU");
634 else if (mod == M_IS)
635 OUTS (outf, "IS");
636 else if (mod == M_ISS2)
637 OUTS (outf, "ISS2");
638 else if (mod == M_IH)
639 OUTS (outf, "IH");
640 else if (mod == M_IU)
641 OUTS (outf, "IU");
642 else
643 abort ();
644
645 OUTS (outf, ")");
646 }
647
648 static struct saved_state
649 {
650 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
651 bu32 ax[2], aw[2];
652 bu32 lt[2], lc[2], lb[2];
653 bu32 rets;
654 } saved_state;
655
656 #define DREG(x) (saved_state.dpregs[x])
657 #define GREG(x, i) DPREG ((x) | ((i) << 3))
658 #define DPREG(x) (saved_state.dpregs[x])
659 #define DREG(x) (saved_state.dpregs[x])
660 #define PREG(x) (saved_state.dpregs[(x) + 8])
661 #define SPREG PREG (6)
662 #define FPREG PREG (7)
663 #define IREG(x) (saved_state.iregs[x])
664 #define MREG(x) (saved_state.mregs[x])
665 #define BREG(x) (saved_state.bregs[x])
666 #define LREG(x) (saved_state.lregs[x])
667 #define AXREG(x) (saved_state.ax[x])
668 #define AWREG(x) (saved_state.aw[x])
669 #define LCREG(x) (saved_state.lc[x])
670 #define LTREG(x) (saved_state.lt[x])
671 #define LBREG(x) (saved_state.lb[x])
672 #define RETSREG (saved_state.rets)
673
674 static bu32 *
675 get_allreg (int grp, int reg)
676 {
677 int fullreg = (grp << 3) | reg;
678 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
679 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
680 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
681 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
682 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
683 , , , , , , , ,
684 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
685 REG_CYCLES2,
686 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
687 REG_LASTREG */
688 switch (fullreg >> 2)
689 {
690 case 0: case 1: return &DREG (reg);
691 case 2: case 3: return &PREG (reg);
692 case 4: return &IREG (reg & 3);
693 case 5: return &MREG (reg & 3);
694 case 6: return &BREG (reg & 3);
695 case 7: return &LREG (reg & 3);
696 default:
697 switch (fullreg)
698 {
699 case 32: return &AXREG (0);
700 case 33: return &AWREG (0);
701 case 34: return &AXREG (1);
702 case 35: return &AWREG (1);
703 case 39: return &RETSREG;
704 case 48: return &LCREG (0);
705 case 49: return &LTREG (0);
706 case 50: return &LBREG (0);
707 case 51: return &LCREG (1);
708 case 52: return &LTREG (1);
709 case 53: return &LBREG (1);
710 }
711 }
712 abort ();
713 }
714
715 static int
716 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
717 {
718 struct private *priv = outf->private_data;
719 /* ProgCtrl
720 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
721 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
722 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
723 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
724 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
725
726 if (prgfunc == 0 && poprnd == 0)
727 OUTS (outf, "NOP");
728 else if (priv->parallel)
729 return 0;
730 else if (prgfunc == 1 && poprnd == 0)
731 OUTS (outf, "RTS");
732 else if (prgfunc == 1 && poprnd == 1)
733 OUTS (outf, "RTI");
734 else if (prgfunc == 1 && poprnd == 2)
735 OUTS (outf, "RTX");
736 else if (prgfunc == 1 && poprnd == 3)
737 OUTS (outf, "RTN");
738 else if (prgfunc == 1 && poprnd == 4)
739 OUTS (outf, "RTE");
740 else if (prgfunc == 2 && poprnd == 0)
741 OUTS (outf, "IDLE");
742 else if (prgfunc == 2 && poprnd == 3)
743 OUTS (outf, "CSYNC");
744 else if (prgfunc == 2 && poprnd == 4)
745 OUTS (outf, "SSYNC");
746 else if (prgfunc == 2 && poprnd == 5)
747 OUTS (outf, "EMUEXCPT");
748 else if (prgfunc == 3 && IS_DREG (0, poprnd))
749 {
750 OUTS (outf, "CLI ");
751 OUTS (outf, dregs (poprnd));
752 }
753 else if (prgfunc == 4 && IS_DREG (0, poprnd))
754 {
755 OUTS (outf, "STI ");
756 OUTS (outf, dregs (poprnd));
757 }
758 else if (prgfunc == 5 && IS_PREG (1, poprnd))
759 {
760 OUTS (outf, "JUMP (");
761 OUTS (outf, pregs (poprnd));
762 OUTS (outf, ")");
763 }
764 else if (prgfunc == 6 && IS_PREG (1, poprnd))
765 {
766 OUTS (outf, "CALL (");
767 OUTS (outf, pregs (poprnd));
768 OUTS (outf, ")");
769 }
770 else if (prgfunc == 7 && IS_PREG (1, poprnd))
771 {
772 OUTS (outf, "CALL (PC + ");
773 OUTS (outf, pregs (poprnd));
774 OUTS (outf, ")");
775 }
776 else if (prgfunc == 8 && IS_PREG (1, poprnd))
777 {
778 OUTS (outf, "JUMP (PC + ");
779 OUTS (outf, pregs (poprnd));
780 OUTS (outf, ")");
781 }
782 else if (prgfunc == 9)
783 {
784 OUTS (outf, "RAISE ");
785 OUTS (outf, uimm4 (poprnd));
786 }
787 else if (prgfunc == 10)
788 {
789 OUTS (outf, "EXCPT ");
790 OUTS (outf, uimm4 (poprnd));
791 }
792 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
793 {
794 OUTS (outf, "TESTSET (");
795 OUTS (outf, pregs (poprnd));
796 OUTS (outf, ")");
797 }
798 else
799 return 0;
800 return 2;
801 }
802
803 static int
804 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
805 {
806 struct private *priv = outf->private_data;
807 /* CaCTRL
808 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
809 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
810 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
811 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
812 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
813 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
814
815 if (priv->parallel)
816 return 0;
817
818 if (a == 0 && op == 0)
819 {
820 OUTS (outf, "PREFETCH[");
821 OUTS (outf, pregs (reg));
822 OUTS (outf, "]");
823 }
824 else if (a == 0 && op == 1)
825 {
826 OUTS (outf, "FLUSHINV[");
827 OUTS (outf, pregs (reg));
828 OUTS (outf, "]");
829 }
830 else if (a == 0 && op == 2)
831 {
832 OUTS (outf, "FLUSH[");
833 OUTS (outf, pregs (reg));
834 OUTS (outf, "]");
835 }
836 else if (a == 0 && op == 3)
837 {
838 OUTS (outf, "IFLUSH[");
839 OUTS (outf, pregs (reg));
840 OUTS (outf, "]");
841 }
842 else if (a == 1 && op == 0)
843 {
844 OUTS (outf, "PREFETCH[");
845 OUTS (outf, pregs (reg));
846 OUTS (outf, "++]");
847 }
848 else if (a == 1 && op == 1)
849 {
850 OUTS (outf, "FLUSHINV[");
851 OUTS (outf, pregs (reg));
852 OUTS (outf, "++]");
853 }
854 else if (a == 1 && op == 2)
855 {
856 OUTS (outf, "FLUSH[");
857 OUTS (outf, pregs (reg));
858 OUTS (outf, "++]");
859 }
860 else if (a == 1 && op == 3)
861 {
862 OUTS (outf, "IFLUSH[");
863 OUTS (outf, pregs (reg));
864 OUTS (outf, "++]");
865 }
866 else
867 return 0;
868 return 2;
869 }
870
871 static int
872 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
873 {
874 struct private *priv = outf->private_data;
875 /* PushPopReg
876 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
877 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
878 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
879 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
880 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
881 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
882
883 if (priv->parallel)
884 return 0;
885
886 if (W == 0 && mostreg (reg, grp))
887 {
888 OUTS (outf, allregs (reg, grp));
889 OUTS (outf, " = [SP++]");
890 }
891 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
892 {
893 OUTS (outf, "[--SP] = ");
894 OUTS (outf, allregs (reg, grp));
895 }
896 else
897 return 0;
898 return 2;
899 }
900
901 static int
902 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
903 {
904 struct private *priv = outf->private_data;
905 /* PushPopMultiple
906 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
907 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
908 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
909 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
910 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
911 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
912 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
913 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
914
915 if (priv->parallel)
916 return 0;
917
918 if (pr > 5)
919 return 0;
920
921 if (W == 1 && d == 1 && p == 1)
922 {
923 OUTS (outf, "[--SP] = (R7:");
924 OUTS (outf, imm5d (dr));
925 OUTS (outf, ", P5:");
926 OUTS (outf, imm5d (pr));
927 OUTS (outf, ")");
928 }
929 else if (W == 1 && d == 1 && p == 0 && pr == 0)
930 {
931 OUTS (outf, "[--SP] = (R7:");
932 OUTS (outf, imm5d (dr));
933 OUTS (outf, ")");
934 }
935 else if (W == 1 && d == 0 && p == 1 && dr == 0)
936 {
937 OUTS (outf, "[--SP] = (P5:");
938 OUTS (outf, imm5d (pr));
939 OUTS (outf, ")");
940 }
941 else if (W == 0 && d == 1 && p == 1)
942 {
943 OUTS (outf, "(R7:");
944 OUTS (outf, imm5d (dr));
945 OUTS (outf, ", P5:");
946 OUTS (outf, imm5d (pr));
947 OUTS (outf, ") = [SP++]");
948 }
949 else if (W == 0 && d == 1 && p == 0 && pr == 0)
950 {
951 OUTS (outf, "(R7:");
952 OUTS (outf, imm5d (dr));
953 OUTS (outf, ") = [SP++]");
954 }
955 else if (W == 0 && d == 0 && p == 1 && dr == 0)
956 {
957 OUTS (outf, "(P5:");
958 OUTS (outf, imm5d (pr));
959 OUTS (outf, ") = [SP++]");
960 }
961 else
962 return 0;
963 return 2;
964 }
965
966 static int
967 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
968 {
969 struct private *priv = outf->private_data;
970 /* ccMV
971 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
972 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
973 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
974 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
975 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
976 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
977 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
978 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
979
980 if (priv->parallel)
981 return 0;
982
983 if (T == 1)
984 {
985 OUTS (outf, "IF CC ");
986 OUTS (outf, gregs (dst, d));
987 OUTS (outf, " = ");
988 OUTS (outf, gregs (src, s));
989 }
990 else if (T == 0)
991 {
992 OUTS (outf, "IF !CC ");
993 OUTS (outf, gregs (dst, d));
994 OUTS (outf, " = ");
995 OUTS (outf, gregs (src, s));
996 }
997 else
998 return 0;
999 return 2;
1000 }
1001
1002 static int
1003 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1004 {
1005 struct private *priv = outf->private_data;
1006 /* CCflag
1007 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1008 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1009 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1010 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1011 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1012 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1013 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1014 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1015
1016 if (priv->parallel)
1017 return 0;
1018
1019 if (opc == 0 && I == 0 && G == 0)
1020 {
1021 OUTS (outf, "CC = ");
1022 OUTS (outf, dregs (x));
1023 OUTS (outf, " == ");
1024 OUTS (outf, dregs (y));
1025 }
1026 else if (opc == 1 && I == 0 && G == 0)
1027 {
1028 OUTS (outf, "CC = ");
1029 OUTS (outf, dregs (x));
1030 OUTS (outf, " < ");
1031 OUTS (outf, dregs (y));
1032 }
1033 else if (opc == 2 && I == 0 && G == 0)
1034 {
1035 OUTS (outf, "CC = ");
1036 OUTS (outf, dregs (x));
1037 OUTS (outf, " <= ");
1038 OUTS (outf, dregs (y));
1039 }
1040 else if (opc == 3 && I == 0 && G == 0)
1041 {
1042 OUTS (outf, "CC = ");
1043 OUTS (outf, dregs (x));
1044 OUTS (outf, " < ");
1045 OUTS (outf, dregs (y));
1046 OUTS (outf, " (IU)");
1047 }
1048 else if (opc == 4 && I == 0 && G == 0)
1049 {
1050 OUTS (outf, "CC = ");
1051 OUTS (outf, dregs (x));
1052 OUTS (outf, " <= ");
1053 OUTS (outf, dregs (y));
1054 OUTS (outf, " (IU)");
1055 }
1056 else if (opc == 0 && I == 1 && G == 0)
1057 {
1058 OUTS (outf, "CC = ");
1059 OUTS (outf, dregs (x));
1060 OUTS (outf, " == ");
1061 OUTS (outf, imm3 (y));
1062 }
1063 else if (opc == 1 && I == 1 && G == 0)
1064 {
1065 OUTS (outf, "CC = ");
1066 OUTS (outf, dregs (x));
1067 OUTS (outf, " < ");
1068 OUTS (outf, imm3 (y));
1069 }
1070 else if (opc == 2 && I == 1 && G == 0)
1071 {
1072 OUTS (outf, "CC = ");
1073 OUTS (outf, dregs (x));
1074 OUTS (outf, " <= ");
1075 OUTS (outf, imm3 (y));
1076 }
1077 else if (opc == 3 && I == 1 && G == 0)
1078 {
1079 OUTS (outf, "CC = ");
1080 OUTS (outf, dregs (x));
1081 OUTS (outf, " < ");
1082 OUTS (outf, uimm3 (y));
1083 OUTS (outf, " (IU)");
1084 }
1085 else if (opc == 4 && I == 1 && G == 0)
1086 {
1087 OUTS (outf, "CC = ");
1088 OUTS (outf, dregs (x));
1089 OUTS (outf, " <= ");
1090 OUTS (outf, uimm3 (y));
1091 OUTS (outf, " (IU)");
1092 }
1093 else if (opc == 0 && I == 0 && G == 1)
1094 {
1095 OUTS (outf, "CC = ");
1096 OUTS (outf, pregs (x));
1097 OUTS (outf, " == ");
1098 OUTS (outf, pregs (y));
1099 }
1100 else if (opc == 1 && I == 0 && G == 1)
1101 {
1102 OUTS (outf, "CC = ");
1103 OUTS (outf, pregs (x));
1104 OUTS (outf, " < ");
1105 OUTS (outf, pregs (y));
1106 }
1107 else if (opc == 2 && I == 0 && G == 1)
1108 {
1109 OUTS (outf, "CC = ");
1110 OUTS (outf, pregs (x));
1111 OUTS (outf, " <= ");
1112 OUTS (outf, pregs (y));
1113 }
1114 else if (opc == 3 && I == 0 && G == 1)
1115 {
1116 OUTS (outf, "CC = ");
1117 OUTS (outf, pregs (x));
1118 OUTS (outf, " < ");
1119 OUTS (outf, pregs (y));
1120 OUTS (outf, " (IU)");
1121 }
1122 else if (opc == 4 && I == 0 && G == 1)
1123 {
1124 OUTS (outf, "CC = ");
1125 OUTS (outf, pregs (x));
1126 OUTS (outf, " <= ");
1127 OUTS (outf, pregs (y));
1128 OUTS (outf, " (IU)");
1129 }
1130 else if (opc == 0 && I == 1 && G == 1)
1131 {
1132 OUTS (outf, "CC = ");
1133 OUTS (outf, pregs (x));
1134 OUTS (outf, " == ");
1135 OUTS (outf, imm3 (y));
1136 }
1137 else if (opc == 1 && I == 1 && G == 1)
1138 {
1139 OUTS (outf, "CC = ");
1140 OUTS (outf, pregs (x));
1141 OUTS (outf, " < ");
1142 OUTS (outf, imm3 (y));
1143 }
1144 else if (opc == 2 && I == 1 && G == 1)
1145 {
1146 OUTS (outf, "CC = ");
1147 OUTS (outf, pregs (x));
1148 OUTS (outf, " <= ");
1149 OUTS (outf, imm3 (y));
1150 }
1151 else if (opc == 3 && I == 1 && G == 1)
1152 {
1153 OUTS (outf, "CC = ");
1154 OUTS (outf, pregs (x));
1155 OUTS (outf, " < ");
1156 OUTS (outf, uimm3 (y));
1157 OUTS (outf, " (IU)");
1158 }
1159 else if (opc == 4 && I == 1 && G == 1)
1160 {
1161 OUTS (outf, "CC = ");
1162 OUTS (outf, pregs (x));
1163 OUTS (outf, " <= ");
1164 OUTS (outf, uimm3 (y));
1165 OUTS (outf, " (IU)");
1166 }
1167 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1168 OUTS (outf, "CC = A0 == A1");
1169
1170 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1171 OUTS (outf, "CC = A0 < A1");
1172
1173 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1174 OUTS (outf, "CC = A0 <= A1");
1175
1176 else
1177 return 0;
1178 return 2;
1179 }
1180
1181 static int
1182 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1183 {
1184 struct private *priv = outf->private_data;
1185 /* CC2dreg
1186 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1187 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1188 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1189 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1190 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1191
1192 if (priv->parallel)
1193 return 0;
1194
1195 if (op == 0)
1196 {
1197 OUTS (outf, dregs (reg));
1198 OUTS (outf, " = CC");
1199 }
1200 else if (op == 1)
1201 {
1202 OUTS (outf, "CC = ");
1203 OUTS (outf, dregs (reg));
1204 }
1205 else if (op == 3 && reg == 0)
1206 OUTS (outf, "CC = !CC");
1207 else
1208 return 0;
1209
1210 return 2;
1211 }
1212
1213 static int
1214 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1215 {
1216 struct private *priv = outf->private_data;
1217 /* CC2stat
1218 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1219 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1220 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1221 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1222 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1223 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1224
1225 const char *bitname = statbits (cbit);
1226
1227 if (priv->parallel)
1228 return 0;
1229
1230 if (decode_statbits[cbit] == REG_LASTREG)
1231 {
1232 /* All ASTAT bits except CC may be operated on in hardware, but may
1233 not have a dedicated insn, so still decode "valid" insns. */
1234 static char bitnames[64];
1235 if (cbit != 5)
1236 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1237 else
1238 return 0;
1239
1240 bitname = bitnames;
1241 }
1242
1243 if (op == 0 && D == 0)
1244 {
1245 OUTS (outf, "CC = ");
1246 OUTS (outf, bitname);
1247 }
1248 else if (op == 1 && D == 0)
1249 {
1250 OUTS (outf, "CC |= ");
1251 OUTS (outf, bitname);
1252 }
1253 else if (op == 2 && D == 0)
1254 {
1255 OUTS (outf, "CC &= ");
1256 OUTS (outf, bitname);
1257 }
1258 else if (op == 3 && D == 0)
1259 {
1260 OUTS (outf, "CC ^= ");
1261 OUTS (outf, bitname);
1262 }
1263 else if (op == 0 && D == 1)
1264 {
1265 OUTS (outf, bitname);
1266 OUTS (outf, " = CC");
1267 }
1268 else if (op == 1 && D == 1)
1269 {
1270 OUTS (outf, bitname);
1271 OUTS (outf, " |= CC");
1272 }
1273 else if (op == 2 && D == 1)
1274 {
1275 OUTS (outf, bitname);
1276 OUTS (outf, " &= CC");
1277 }
1278 else if (op == 3 && D == 1)
1279 {
1280 OUTS (outf, bitname);
1281 OUTS (outf, " ^= CC");
1282 }
1283 else
1284 return 0;
1285
1286 return 2;
1287 }
1288
1289 static int
1290 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1291 {
1292 struct private *priv = outf->private_data;
1293 /* BRCC
1294 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1295 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1296 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1297 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1298 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1299 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1300
1301 if (priv->parallel)
1302 return 0;
1303
1304 if (T == 1 && B == 1)
1305 {
1306 OUTS (outf, "IF CC JUMP 0x");
1307 OUTS (outf, pcrel10 (offset));
1308 OUTS (outf, " (BP)");
1309 }
1310 else if (T == 0 && B == 1)
1311 {
1312 OUTS (outf, "IF !CC JUMP 0x");
1313 OUTS (outf, pcrel10 (offset));
1314 OUTS (outf, " (BP)");
1315 }
1316 else if (T == 1)
1317 {
1318 OUTS (outf, "IF CC JUMP 0x");
1319 OUTS (outf, pcrel10 (offset));
1320 }
1321 else if (T == 0)
1322 {
1323 OUTS (outf, "IF !CC JUMP 0x");
1324 OUTS (outf, pcrel10 (offset));
1325 }
1326 else
1327 return 0;
1328
1329 return 2;
1330 }
1331
1332 static int
1333 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1334 {
1335 struct private *priv = outf->private_data;
1336 /* UJUMP
1337 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1338 | 0 | 0 | 1 | 0 |.offset........................................|
1339 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1340 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1341
1342 if (priv->parallel)
1343 return 0;
1344
1345 OUTS (outf, "JUMP.S 0x");
1346 OUTS (outf, pcrel12 (offset));
1347 return 2;
1348 }
1349
1350 static int
1351 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1352 {
1353 /* REGMV
1354 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1355 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1356 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1357 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1358 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1359 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1360 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1361
1362 /* Reserved slots cannot be a src/dst. */
1363 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1364 goto invalid_move;
1365
1366 /* Standard register moves */
1367 if ((gs < 2) || /* Dregs/Pregs as source */
1368 (gd < 2) || /* Dregs/Pregs as dest */
1369 (gs == 4 && src < 4) || /* Accumulators as source */
1370 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1371 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1372 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1373 goto valid_move;
1374
1375 /* dareg = dareg (IMBL) */
1376 if (gs < 4 && gd < 4)
1377 goto valid_move;
1378
1379 /* USP can be src to sysregs, but not dagregs. */
1380 if ((gs == 7 && src == 0) && (gd >= 4))
1381 goto valid_move;
1382
1383 /* USP can move between genregs (only check Accumulators). */
1384 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1385 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1386 goto valid_move;
1387
1388 /* Still here ? Invalid reg pair. */
1389 invalid_move:
1390 return 0;
1391
1392 valid_move:
1393 OUTS (outf, allregs (dst, gd));
1394 OUTS (outf, " = ");
1395 OUTS (outf, allregs (src, gs));
1396 return 2;
1397 }
1398
1399 static int
1400 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1401 {
1402 /* ALU2op
1403 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1404 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1405 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1406 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1407 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1408 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1409
1410 if (opc == 0)
1411 {
1412 OUTS (outf, dregs (dst));
1413 OUTS (outf, " >>>= ");
1414 OUTS (outf, dregs (src));
1415 }
1416 else if (opc == 1)
1417 {
1418 OUTS (outf, dregs (dst));
1419 OUTS (outf, " >>= ");
1420 OUTS (outf, dregs (src));
1421 }
1422 else if (opc == 2)
1423 {
1424 OUTS (outf, dregs (dst));
1425 OUTS (outf, " <<= ");
1426 OUTS (outf, dregs (src));
1427 }
1428 else if (opc == 3)
1429 {
1430 OUTS (outf, dregs (dst));
1431 OUTS (outf, " *= ");
1432 OUTS (outf, dregs (src));
1433 }
1434 else if (opc == 4)
1435 {
1436 OUTS (outf, dregs (dst));
1437 OUTS (outf, " = (");
1438 OUTS (outf, dregs (dst));
1439 OUTS (outf, " + ");
1440 OUTS (outf, dregs (src));
1441 OUTS (outf, ") << 0x1");
1442 }
1443 else if (opc == 5)
1444 {
1445 OUTS (outf, dregs (dst));
1446 OUTS (outf, " = (");
1447 OUTS (outf, dregs (dst));
1448 OUTS (outf, " + ");
1449 OUTS (outf, dregs (src));
1450 OUTS (outf, ") << 0x2");
1451 }
1452 else if (opc == 8)
1453 {
1454 OUTS (outf, "DIVQ (");
1455 OUTS (outf, dregs (dst));
1456 OUTS (outf, ", ");
1457 OUTS (outf, dregs (src));
1458 OUTS (outf, ")");
1459 }
1460 else if (opc == 9)
1461 {
1462 OUTS (outf, "DIVS (");
1463 OUTS (outf, dregs (dst));
1464 OUTS (outf, ", ");
1465 OUTS (outf, dregs (src));
1466 OUTS (outf, ")");
1467 }
1468 else if (opc == 10)
1469 {
1470 OUTS (outf, dregs (dst));
1471 OUTS (outf, " = ");
1472 OUTS (outf, dregs_lo (src));
1473 OUTS (outf, " (X)");
1474 }
1475 else if (opc == 11)
1476 {
1477 OUTS (outf, dregs (dst));
1478 OUTS (outf, " = ");
1479 OUTS (outf, dregs_lo (src));
1480 OUTS (outf, " (Z)");
1481 }
1482 else if (opc == 12)
1483 {
1484 OUTS (outf, dregs (dst));
1485 OUTS (outf, " = ");
1486 OUTS (outf, dregs_byte (src));
1487 OUTS (outf, " (X)");
1488 }
1489 else if (opc == 13)
1490 {
1491 OUTS (outf, dregs (dst));
1492 OUTS (outf, " = ");
1493 OUTS (outf, dregs_byte (src));
1494 OUTS (outf, " (Z)");
1495 }
1496 else if (opc == 14)
1497 {
1498 OUTS (outf, dregs (dst));
1499 OUTS (outf, " = -");
1500 OUTS (outf, dregs (src));
1501 }
1502 else if (opc == 15)
1503 {
1504 OUTS (outf, dregs (dst));
1505 OUTS (outf, " =~ ");
1506 OUTS (outf, dregs (src));
1507 }
1508 else
1509 return 0;
1510
1511 return 2;
1512 }
1513
1514 static int
1515 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1516 {
1517 /* PTR2op
1518 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1519 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1520 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1521 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1522 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1523 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1524
1525 if (opc == 0)
1526 {
1527 OUTS (outf, pregs (dst));
1528 OUTS (outf, " -= ");
1529 OUTS (outf, pregs (src));
1530 }
1531 else if (opc == 1)
1532 {
1533 OUTS (outf, pregs (dst));
1534 OUTS (outf, " = ");
1535 OUTS (outf, pregs (src));
1536 OUTS (outf, " << 0x2");
1537 }
1538 else if (opc == 3)
1539 {
1540 OUTS (outf, pregs (dst));
1541 OUTS (outf, " = ");
1542 OUTS (outf, pregs (src));
1543 OUTS (outf, " >> 0x2");
1544 }
1545 else if (opc == 4)
1546 {
1547 OUTS (outf, pregs (dst));
1548 OUTS (outf, " = ");
1549 OUTS (outf, pregs (src));
1550 OUTS (outf, " >> 0x1");
1551 }
1552 else if (opc == 5)
1553 {
1554 OUTS (outf, pregs (dst));
1555 OUTS (outf, " += ");
1556 OUTS (outf, pregs (src));
1557 OUTS (outf, " (BREV)");
1558 }
1559 else if (opc == 6)
1560 {
1561 OUTS (outf, pregs (dst));
1562 OUTS (outf, " = (");
1563 OUTS (outf, pregs (dst));
1564 OUTS (outf, " + ");
1565 OUTS (outf, pregs (src));
1566 OUTS (outf, ") << 0x1");
1567 }
1568 else if (opc == 7)
1569 {
1570 OUTS (outf, pregs (dst));
1571 OUTS (outf, " = (");
1572 OUTS (outf, pregs (dst));
1573 OUTS (outf, " + ");
1574 OUTS (outf, pregs (src));
1575 OUTS (outf, ") << 0x2");
1576 }
1577 else
1578 return 0;
1579
1580 return 2;
1581 }
1582
1583 static int
1584 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1585 {
1586 struct private *priv = outf->private_data;
1587 /* LOGI2op
1588 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1589 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1590 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1591 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1592 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1593 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1594
1595 if (priv->parallel)
1596 return 0;
1597
1598 if (opc == 0)
1599 {
1600 OUTS (outf, "CC = !BITTST (");
1601 OUTS (outf, dregs (dst));
1602 OUTS (outf, ", ");
1603 OUTS (outf, uimm5 (src));
1604 OUTS (outf, ");\t\t/* bit");
1605 OUTS (outf, imm7d (src));
1606 OUTS (outf, " */");
1607 priv->comment = 1;
1608 }
1609 else if (opc == 1)
1610 {
1611 OUTS (outf, "CC = BITTST (");
1612 OUTS (outf, dregs (dst));
1613 OUTS (outf, ", ");
1614 OUTS (outf, uimm5 (src));
1615 OUTS (outf, ");\t\t/* bit");
1616 OUTS (outf, imm7d (src));
1617 OUTS (outf, " */");
1618 priv->comment = 1;
1619 }
1620 else if (opc == 2)
1621 {
1622 OUTS (outf, "BITSET (");
1623 OUTS (outf, dregs (dst));
1624 OUTS (outf, ", ");
1625 OUTS (outf, uimm5 (src));
1626 OUTS (outf, ");\t\t/* bit");
1627 OUTS (outf, imm7d (src));
1628 OUTS (outf, " */");
1629 priv->comment = 1;
1630 }
1631 else if (opc == 3)
1632 {
1633 OUTS (outf, "BITTGL (");
1634 OUTS (outf, dregs (dst));
1635 OUTS (outf, ", ");
1636 OUTS (outf, uimm5 (src));
1637 OUTS (outf, ");\t\t/* bit");
1638 OUTS (outf, imm7d (src));
1639 OUTS (outf, " */");
1640 priv->comment = 1;
1641 }
1642 else if (opc == 4)
1643 {
1644 OUTS (outf, "BITCLR (");
1645 OUTS (outf, dregs (dst));
1646 OUTS (outf, ", ");
1647 OUTS (outf, uimm5 (src));
1648 OUTS (outf, ");\t\t/* bit");
1649 OUTS (outf, imm7d (src));
1650 OUTS (outf, " */");
1651 priv->comment = 1;
1652 }
1653 else if (opc == 5)
1654 {
1655 OUTS (outf, dregs (dst));
1656 OUTS (outf, " >>>= ");
1657 OUTS (outf, uimm5 (src));
1658 }
1659 else if (opc == 6)
1660 {
1661 OUTS (outf, dregs (dst));
1662 OUTS (outf, " >>= ");
1663 OUTS (outf, uimm5 (src));
1664 }
1665 else if (opc == 7)
1666 {
1667 OUTS (outf, dregs (dst));
1668 OUTS (outf, " <<= ");
1669 OUTS (outf, uimm5 (src));
1670 }
1671 else
1672 return 0;
1673
1674 return 2;
1675 }
1676
1677 static int
1678 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1679 {
1680 /* COMP3op
1681 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1682 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1683 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1684 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1685 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1686 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1687 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1688
1689 if (opc == 5 && src1 == src0)
1690 {
1691 OUTS (outf, pregs (dst));
1692 OUTS (outf, " = ");
1693 OUTS (outf, pregs (src0));
1694 OUTS (outf, " << 0x1");
1695 }
1696 else if (opc == 1)
1697 {
1698 OUTS (outf, dregs (dst));
1699 OUTS (outf, " = ");
1700 OUTS (outf, dregs (src0));
1701 OUTS (outf, " - ");
1702 OUTS (outf, dregs (src1));
1703 }
1704 else if (opc == 2)
1705 {
1706 OUTS (outf, dregs (dst));
1707 OUTS (outf, " = ");
1708 OUTS (outf, dregs (src0));
1709 OUTS (outf, " & ");
1710 OUTS (outf, dregs (src1));
1711 }
1712 else if (opc == 3)
1713 {
1714 OUTS (outf, dregs (dst));
1715 OUTS (outf, " = ");
1716 OUTS (outf, dregs (src0));
1717 OUTS (outf, " | ");
1718 OUTS (outf, dregs (src1));
1719 }
1720 else if (opc == 4)
1721 {
1722 OUTS (outf, dregs (dst));
1723 OUTS (outf, " = ");
1724 OUTS (outf, dregs (src0));
1725 OUTS (outf, " ^ ");
1726 OUTS (outf, dregs (src1));
1727 }
1728 else if (opc == 5)
1729 {
1730 OUTS (outf, pregs (dst));
1731 OUTS (outf, " = ");
1732 OUTS (outf, pregs (src0));
1733 OUTS (outf, " + ");
1734 OUTS (outf, pregs (src1));
1735 }
1736 else if (opc == 6)
1737 {
1738 OUTS (outf, pregs (dst));
1739 OUTS (outf, " = ");
1740 OUTS (outf, pregs (src0));
1741 OUTS (outf, " + (");
1742 OUTS (outf, pregs (src1));
1743 OUTS (outf, " << 0x1)");
1744 }
1745 else if (opc == 7)
1746 {
1747 OUTS (outf, pregs (dst));
1748 OUTS (outf, " = ");
1749 OUTS (outf, pregs (src0));
1750 OUTS (outf, " + (");
1751 OUTS (outf, pregs (src1));
1752 OUTS (outf, " << 0x2)");
1753 }
1754 else if (opc == 0)
1755 {
1756 OUTS (outf, dregs (dst));
1757 OUTS (outf, " = ");
1758 OUTS (outf, dregs (src0));
1759 OUTS (outf, " + ");
1760 OUTS (outf, dregs (src1));
1761 }
1762 else
1763 return 0;
1764
1765 return 2;
1766 }
1767
1768 static int
1769 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1770 {
1771 struct private *priv = outf->private_data;
1772 /* COMPI2opD
1773 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1774 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1775 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1776 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1777 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1778 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1779
1780 bu32 *pval = get_allreg (0, dst);
1781
1782 if (priv->parallel)
1783 return 0;
1784
1785 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1786 to combine them, so it prints out the right values.
1787 Here we keep track of the registers. */
1788 if (op == 0)
1789 {
1790 *pval = imm7_val (src);
1791 if (src & 0x40)
1792 *pval |= 0xFFFFFF80;
1793 else
1794 *pval &= 0x7F;
1795 }
1796
1797 if (op == 0)
1798 {
1799 OUTS (outf, dregs (dst));
1800 OUTS (outf, " = ");
1801 OUTS (outf, imm7 (src));
1802 OUTS (outf, " (X);\t\t/*\t\t");
1803 OUTS (outf, dregs (dst));
1804 OUTS (outf, "=");
1805 OUTS (outf, uimm32 (*pval));
1806 OUTS (outf, "(");
1807 OUTS (outf, imm32 (*pval));
1808 OUTS (outf, ") */");
1809 priv->comment = 1;
1810 }
1811 else if (op == 1)
1812 {
1813 OUTS (outf, dregs (dst));
1814 OUTS (outf, " += ");
1815 OUTS (outf, imm7 (src));
1816 OUTS (outf, ";\t\t/* (");
1817 OUTS (outf, imm7d (src));
1818 OUTS (outf, ") */");
1819 priv->comment = 1;
1820 }
1821 else
1822 return 0;
1823
1824 return 2;
1825 }
1826
1827 static int
1828 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1829 {
1830 struct private *priv = outf->private_data;
1831 /* COMPI2opP
1832 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1833 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1834 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1835 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1836 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1837 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1838
1839 bu32 *pval = get_allreg (1, dst);
1840
1841 if (priv->parallel)
1842 return 0;
1843
1844 if (op == 0)
1845 {
1846 *pval = imm7_val (src);
1847 if (src & 0x40)
1848 *pval |= 0xFFFFFF80;
1849 else
1850 *pval &= 0x7F;
1851 }
1852
1853 if (op == 0)
1854 {
1855 OUTS (outf, pregs (dst));
1856 OUTS (outf, " = ");
1857 OUTS (outf, imm7 (src));
1858 OUTS (outf, " (X);\t\t/*\t\t");
1859 OUTS (outf, pregs (dst));
1860 OUTS (outf, "=");
1861 OUTS (outf, uimm32 (*pval));
1862 OUTS (outf, "(");
1863 OUTS (outf, imm32 (*pval));
1864 OUTS (outf, ") */");
1865 priv->comment = 1;
1866 }
1867 else if (op == 1)
1868 {
1869 OUTS (outf, pregs (dst));
1870 OUTS (outf, " += ");
1871 OUTS (outf, imm7 (src));
1872 OUTS (outf, ";\t\t/* (");
1873 OUTS (outf, imm7d (src));
1874 OUTS (outf, ") */");
1875 priv->comment = 1;
1876 }
1877 else
1878 return 0;
1879
1880 return 2;
1881 }
1882
1883 static int
1884 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1885 {
1886 /* LDSTpmod
1887 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1888 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1889 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1890 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1891 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1892 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1893 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1894 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1895
1896 if (aop == 1 && W == 0 && idx == ptr)
1897 {
1898 OUTS (outf, dregs_lo (reg));
1899 OUTS (outf, " = W[");
1900 OUTS (outf, pregs (ptr));
1901 OUTS (outf, "]");
1902 }
1903 else if (aop == 2 && W == 0 && idx == ptr)
1904 {
1905 OUTS (outf, dregs_hi (reg));
1906 OUTS (outf, " = W[");
1907 OUTS (outf, pregs (ptr));
1908 OUTS (outf, "]");
1909 }
1910 else if (aop == 1 && W == 1 && idx == ptr)
1911 {
1912 OUTS (outf, "W[");
1913 OUTS (outf, pregs (ptr));
1914 OUTS (outf, "] = ");
1915 OUTS (outf, dregs_lo (reg));
1916 }
1917 else if (aop == 2 && W == 1 && idx == ptr)
1918 {
1919 OUTS (outf, "W[");
1920 OUTS (outf, pregs (ptr));
1921 OUTS (outf, "] = ");
1922 OUTS (outf, dregs_hi (reg));
1923 }
1924 else if (aop == 0 && W == 0)
1925 {
1926 OUTS (outf, dregs (reg));
1927 OUTS (outf, " = [");
1928 OUTS (outf, pregs (ptr));
1929 OUTS (outf, " ++ ");
1930 OUTS (outf, pregs (idx));
1931 OUTS (outf, "]");
1932 }
1933 else if (aop == 1 && W == 0)
1934 {
1935 OUTS (outf, dregs_lo (reg));
1936 OUTS (outf, " = W[");
1937 OUTS (outf, pregs (ptr));
1938 OUTS (outf, " ++ ");
1939 OUTS (outf, pregs (idx));
1940 OUTS (outf, "]");
1941 }
1942 else if (aop == 2 && W == 0)
1943 {
1944 OUTS (outf, dregs_hi (reg));
1945 OUTS (outf, " = W[");
1946 OUTS (outf, pregs (ptr));
1947 OUTS (outf, " ++ ");
1948 OUTS (outf, pregs (idx));
1949 OUTS (outf, "]");
1950 }
1951 else if (aop == 3 && W == 0)
1952 {
1953 OUTS (outf, dregs (reg));
1954 OUTS (outf, " = W[");
1955 OUTS (outf, pregs (ptr));
1956 OUTS (outf, " ++ ");
1957 OUTS (outf, pregs (idx));
1958 OUTS (outf, "] (Z)");
1959 }
1960 else if (aop == 3 && W == 1)
1961 {
1962 OUTS (outf, dregs (reg));
1963 OUTS (outf, " = W[");
1964 OUTS (outf, pregs (ptr));
1965 OUTS (outf, " ++ ");
1966 OUTS (outf, pregs (idx));
1967 OUTS (outf, "] (X)");
1968 }
1969 else if (aop == 0 && W == 1)
1970 {
1971 OUTS (outf, "[");
1972 OUTS (outf, pregs (ptr));
1973 OUTS (outf, " ++ ");
1974 OUTS (outf, pregs (idx));
1975 OUTS (outf, "] = ");
1976 OUTS (outf, dregs (reg));
1977 }
1978 else if (aop == 1 && W == 1)
1979 {
1980 OUTS (outf, "W[");
1981 OUTS (outf, pregs (ptr));
1982 OUTS (outf, " ++ ");
1983 OUTS (outf, pregs (idx));
1984 OUTS (outf, "] = ");
1985 OUTS (outf, dregs_lo (reg));
1986 }
1987 else if (aop == 2 && W == 1)
1988 {
1989 OUTS (outf, "W[");
1990 OUTS (outf, pregs (ptr));
1991 OUTS (outf, " ++ ");
1992 OUTS (outf, pregs (idx));
1993 OUTS (outf, "] = ");
1994 OUTS (outf, dregs_hi (reg));
1995 }
1996 else
1997 return 0;
1998
1999 return 2;
2000 }
2001
2002 static int
2003 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2004 {
2005 /* dagMODim
2006 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2007 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2008 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2009 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2010 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2011 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2012 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2013
2014 if (op == 0 && br == 1)
2015 {
2016 OUTS (outf, iregs (i));
2017 OUTS (outf, " += ");
2018 OUTS (outf, mregs (m));
2019 OUTS (outf, " (BREV)");
2020 }
2021 else if (op == 0)
2022 {
2023 OUTS (outf, iregs (i));
2024 OUTS (outf, " += ");
2025 OUTS (outf, mregs (m));
2026 }
2027 else if (op == 1 && br == 0)
2028 {
2029 OUTS (outf, iregs (i));
2030 OUTS (outf, " -= ");
2031 OUTS (outf, mregs (m));
2032 }
2033 else
2034 return 0;
2035
2036 return 2;
2037 }
2038
2039 static int
2040 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2041 {
2042 struct private *priv = outf->private_data;
2043 /* dagMODik
2044 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2045 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2046 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2047 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2048 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2049
2050 if (op == 0)
2051 {
2052 OUTS (outf, iregs (i));
2053 OUTS (outf, " += 0x2");
2054 }
2055 else if (op == 1)
2056 {
2057 OUTS (outf, iregs (i));
2058 OUTS (outf, " -= 0x2");
2059 }
2060 else if (op == 2)
2061 {
2062 OUTS (outf, iregs (i));
2063 OUTS (outf, " += 0x4");
2064 }
2065 else if (op == 3)
2066 {
2067 OUTS (outf, iregs (i));
2068 OUTS (outf, " -= 0x4");
2069 }
2070 else
2071 return 0;
2072
2073 if (!priv->parallel)
2074 {
2075 OUTS (outf, ";\t\t/* ( ");
2076 if (op == 0 || op == 1)
2077 OUTS (outf, "2");
2078 else if (op == 2 || op == 3)
2079 OUTS (outf, "4");
2080 OUTS (outf, ") */");
2081 priv->comment = 1;
2082 }
2083
2084 return 2;
2085 }
2086
2087 static int
2088 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2089 {
2090 /* dspLDST
2091 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2092 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2093 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2094 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2095 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2096 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2097 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2098 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2099
2100 if (aop == 0 && W == 0 && m == 0)
2101 {
2102 OUTS (outf, dregs (reg));
2103 OUTS (outf, " = [");
2104 OUTS (outf, iregs (i));
2105 OUTS (outf, "++]");
2106 }
2107 else if (aop == 0 && W == 0 && m == 1)
2108 {
2109 OUTS (outf, dregs_lo (reg));
2110 OUTS (outf, " = W[");
2111 OUTS (outf, iregs (i));
2112 OUTS (outf, "++]");
2113 }
2114 else if (aop == 0 && W == 0 && m == 2)
2115 {
2116 OUTS (outf, dregs_hi (reg));
2117 OUTS (outf, " = W[");
2118 OUTS (outf, iregs (i));
2119 OUTS (outf, "++]");
2120 }
2121 else if (aop == 1 && W == 0 && m == 0)
2122 {
2123 OUTS (outf, dregs (reg));
2124 OUTS (outf, " = [");
2125 OUTS (outf, iregs (i));
2126 OUTS (outf, "--]");
2127 }
2128 else if (aop == 1 && W == 0 && m == 1)
2129 {
2130 OUTS (outf, dregs_lo (reg));
2131 OUTS (outf, " = W[");
2132 OUTS (outf, iregs (i));
2133 OUTS (outf, "--]");
2134 }
2135 else if (aop == 1 && W == 0 && m == 2)
2136 {
2137 OUTS (outf, dregs_hi (reg));
2138 OUTS (outf, " = W[");
2139 OUTS (outf, iregs (i));
2140 OUTS (outf, "--]");
2141 }
2142 else if (aop == 2 && W == 0 && m == 0)
2143 {
2144 OUTS (outf, dregs (reg));
2145 OUTS (outf, " = [");
2146 OUTS (outf, iregs (i));
2147 OUTS (outf, "]");
2148 }
2149 else if (aop == 2 && W == 0 && m == 1)
2150 {
2151 OUTS (outf, dregs_lo (reg));
2152 OUTS (outf, " = W[");
2153 OUTS (outf, iregs (i));
2154 OUTS (outf, "]");
2155 }
2156 else if (aop == 2 && W == 0 && m == 2)
2157 {
2158 OUTS (outf, dregs_hi (reg));
2159 OUTS (outf, " = W[");
2160 OUTS (outf, iregs (i));
2161 OUTS (outf, "]");
2162 }
2163 else if (aop == 0 && W == 1 && m == 0)
2164 {
2165 OUTS (outf, "[");
2166 OUTS (outf, iregs (i));
2167 OUTS (outf, "++] = ");
2168 OUTS (outf, dregs (reg));
2169 }
2170 else if (aop == 0 && W == 1 && m == 1)
2171 {
2172 OUTS (outf, "W[");
2173 OUTS (outf, iregs (i));
2174 OUTS (outf, "++] = ");
2175 OUTS (outf, dregs_lo (reg));
2176 }
2177 else if (aop == 0 && W == 1 && m == 2)
2178 {
2179 OUTS (outf, "W[");
2180 OUTS (outf, iregs (i));
2181 OUTS (outf, "++] = ");
2182 OUTS (outf, dregs_hi (reg));
2183 }
2184 else if (aop == 1 && W == 1 && m == 0)
2185 {
2186 OUTS (outf, "[");
2187 OUTS (outf, iregs (i));
2188 OUTS (outf, "--] = ");
2189 OUTS (outf, dregs (reg));
2190 }
2191 else if (aop == 1 && W == 1 && m == 1)
2192 {
2193 OUTS (outf, "W[");
2194 OUTS (outf, iregs (i));
2195 OUTS (outf, "--] = ");
2196 OUTS (outf, dregs_lo (reg));
2197 }
2198 else if (aop == 1 && W == 1 && m == 2)
2199 {
2200 OUTS (outf, "W[");
2201 OUTS (outf, iregs (i));
2202 OUTS (outf, "--] = ");
2203 OUTS (outf, dregs_hi (reg));
2204 }
2205 else if (aop == 2 && W == 1 && m == 0)
2206 {
2207 OUTS (outf, "[");
2208 OUTS (outf, iregs (i));
2209 OUTS (outf, "] = ");
2210 OUTS (outf, dregs (reg));
2211 }
2212 else if (aop == 2 && W == 1 && m == 1)
2213 {
2214 OUTS (outf, "W[");
2215 OUTS (outf, iregs (i));
2216 OUTS (outf, "] = ");
2217 OUTS (outf, dregs_lo (reg));
2218 }
2219 else if (aop == 2 && W == 1 && m == 2)
2220 {
2221 OUTS (outf, "W[");
2222 OUTS (outf, iregs (i));
2223 OUTS (outf, "] = ");
2224 OUTS (outf, dregs_hi (reg));
2225 }
2226 else if (aop == 3 && W == 0)
2227 {
2228 OUTS (outf, dregs (reg));
2229 OUTS (outf, " = [");
2230 OUTS (outf, iregs (i));
2231 OUTS (outf, " ++ ");
2232 OUTS (outf, mregs (m));
2233 OUTS (outf, "]");
2234 }
2235 else if (aop == 3 && W == 1)
2236 {
2237 OUTS (outf, "[");
2238 OUTS (outf, iregs (i));
2239 OUTS (outf, " ++ ");
2240 OUTS (outf, mregs (m));
2241 OUTS (outf, "] = ");
2242 OUTS (outf, dregs (reg));
2243 }
2244 else
2245 return 0;
2246
2247 return 2;
2248 }
2249
2250 static int
2251 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2252 {
2253 /* LDST
2254 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2255 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2256 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2257 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2258 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2259 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2260 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2261 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2262 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2263
2264 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2265 {
2266 OUTS (outf, dregs (reg));
2267 OUTS (outf, " = [");
2268 OUTS (outf, pregs (ptr));
2269 OUTS (outf, "++]");
2270 }
2271 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2272 {
2273 OUTS (outf, pregs (reg));
2274 OUTS (outf, " = [");
2275 OUTS (outf, pregs (ptr));
2276 OUTS (outf, "++]");
2277 }
2278 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2279 {
2280 OUTS (outf, dregs (reg));
2281 OUTS (outf, " = W[");
2282 OUTS (outf, pregs (ptr));
2283 OUTS (outf, "++] (Z)");
2284 }
2285 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2286 {
2287 OUTS (outf, dregs (reg));
2288 OUTS (outf, " = W[");
2289 OUTS (outf, pregs (ptr));
2290 OUTS (outf, "++] (X)");
2291 }
2292 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2293 {
2294 OUTS (outf, dregs (reg));
2295 OUTS (outf, " = B[");
2296 OUTS (outf, pregs (ptr));
2297 OUTS (outf, "++] (Z)");
2298 }
2299 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2300 {
2301 OUTS (outf, dregs (reg));
2302 OUTS (outf, " = B[");
2303 OUTS (outf, pregs (ptr));
2304 OUTS (outf, "++] (X)");
2305 }
2306 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2307 {
2308 OUTS (outf, dregs (reg));
2309 OUTS (outf, " = [");
2310 OUTS (outf, pregs (ptr));
2311 OUTS (outf, "--]");
2312 }
2313 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2314 {
2315 OUTS (outf, pregs (reg));
2316 OUTS (outf, " = [");
2317 OUTS (outf, pregs (ptr));
2318 OUTS (outf, "--]");
2319 }
2320 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2321 {
2322 OUTS (outf, dregs (reg));
2323 OUTS (outf, " = W[");
2324 OUTS (outf, pregs (ptr));
2325 OUTS (outf, "--] (Z)");
2326 }
2327 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2328 {
2329 OUTS (outf, dregs (reg));
2330 OUTS (outf, " = W[");
2331 OUTS (outf, pregs (ptr));
2332 OUTS (outf, "--] (X)");
2333 }
2334 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2335 {
2336 OUTS (outf, dregs (reg));
2337 OUTS (outf, " = B[");
2338 OUTS (outf, pregs (ptr));
2339 OUTS (outf, "--] (Z)");
2340 }
2341 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2342 {
2343 OUTS (outf, dregs (reg));
2344 OUTS (outf, " = B[");
2345 OUTS (outf, pregs (ptr));
2346 OUTS (outf, "--] (X)");
2347 }
2348 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2349 {
2350 OUTS (outf, dregs (reg));
2351 OUTS (outf, " = [");
2352 OUTS (outf, pregs (ptr));
2353 OUTS (outf, "]");
2354 }
2355 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2356 {
2357 OUTS (outf, pregs (reg));
2358 OUTS (outf, " = [");
2359 OUTS (outf, pregs (ptr));
2360 OUTS (outf, "]");
2361 }
2362 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2363 {
2364 OUTS (outf, dregs (reg));
2365 OUTS (outf, " = W[");
2366 OUTS (outf, pregs (ptr));
2367 OUTS (outf, "] (Z)");
2368 }
2369 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2370 {
2371 OUTS (outf, dregs (reg));
2372 OUTS (outf, " = W[");
2373 OUTS (outf, pregs (ptr));
2374 OUTS (outf, "] (X)");
2375 }
2376 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2377 {
2378 OUTS (outf, dregs (reg));
2379 OUTS (outf, " = B[");
2380 OUTS (outf, pregs (ptr));
2381 OUTS (outf, "] (Z)");
2382 }
2383 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2384 {
2385 OUTS (outf, dregs (reg));
2386 OUTS (outf, " = B[");
2387 OUTS (outf, pregs (ptr));
2388 OUTS (outf, "] (X)");
2389 }
2390 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2391 {
2392 OUTS (outf, "[");
2393 OUTS (outf, pregs (ptr));
2394 OUTS (outf, "++] = ");
2395 OUTS (outf, dregs (reg));
2396 }
2397 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2398 {
2399 OUTS (outf, "[");
2400 OUTS (outf, pregs (ptr));
2401 OUTS (outf, "++] = ");
2402 OUTS (outf, pregs (reg));
2403 }
2404 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2405 {
2406 OUTS (outf, "W[");
2407 OUTS (outf, pregs (ptr));
2408 OUTS (outf, "++] = ");
2409 OUTS (outf, dregs (reg));
2410 }
2411 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2412 {
2413 OUTS (outf, "B[");
2414 OUTS (outf, pregs (ptr));
2415 OUTS (outf, "++] = ");
2416 OUTS (outf, dregs (reg));
2417 }
2418 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2419 {
2420 OUTS (outf, "[");
2421 OUTS (outf, pregs (ptr));
2422 OUTS (outf, "--] = ");
2423 OUTS (outf, dregs (reg));
2424 }
2425 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2426 {
2427 OUTS (outf, "[");
2428 OUTS (outf, pregs (ptr));
2429 OUTS (outf, "--] = ");
2430 OUTS (outf, pregs (reg));
2431 }
2432 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2433 {
2434 OUTS (outf, "W[");
2435 OUTS (outf, pregs (ptr));
2436 OUTS (outf, "--] = ");
2437 OUTS (outf, dregs (reg));
2438 }
2439 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2440 {
2441 OUTS (outf, "B[");
2442 OUTS (outf, pregs (ptr));
2443 OUTS (outf, "--] = ");
2444 OUTS (outf, dregs (reg));
2445 }
2446 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2447 {
2448 OUTS (outf, "[");
2449 OUTS (outf, pregs (ptr));
2450 OUTS (outf, "] = ");
2451 OUTS (outf, dregs (reg));
2452 }
2453 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2454 {
2455 OUTS (outf, "[");
2456 OUTS (outf, pregs (ptr));
2457 OUTS (outf, "] = ");
2458 OUTS (outf, pregs (reg));
2459 }
2460 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2461 {
2462 OUTS (outf, "W[");
2463 OUTS (outf, pregs (ptr));
2464 OUTS (outf, "] = ");
2465 OUTS (outf, dregs (reg));
2466 }
2467 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2468 {
2469 OUTS (outf, "B[");
2470 OUTS (outf, pregs (ptr));
2471 OUTS (outf, "] = ");
2472 OUTS (outf, dregs (reg));
2473 }
2474 else
2475 return 0;
2476
2477 return 2;
2478 }
2479
2480 static int
2481 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2482 {
2483 /* LDSTiiFP
2484 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2485 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2486 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2487 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2488 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2489 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2490
2491 if (W == 0)
2492 {
2493 OUTS (outf, dpregs (reg));
2494 OUTS (outf, " = [FP ");
2495 OUTS (outf, negimm5s4 (offset));
2496 OUTS (outf, "]");
2497 }
2498 else if (W == 1)
2499 {
2500 OUTS (outf, "[FP ");
2501 OUTS (outf, negimm5s4 (offset));
2502 OUTS (outf, "] = ");
2503 OUTS (outf, dpregs (reg));
2504 }
2505 else
2506 return 0;
2507
2508 return 2;
2509 }
2510
2511 static int
2512 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2513 {
2514 /* LDSTii
2515 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2516 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2517 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2518 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2519 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2520 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2521 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2522 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2523
2524 if (W == 0 && op == 0)
2525 {
2526 OUTS (outf, dregs (reg));
2527 OUTS (outf, " = [");
2528 OUTS (outf, pregs (ptr));
2529 OUTS (outf, " + ");
2530 OUTS (outf, uimm4s4 (offset));
2531 OUTS (outf, "]");
2532 }
2533 else if (W == 0 && op == 1)
2534 {
2535 OUTS (outf, dregs (reg));
2536 OUTS (outf, " = W[");
2537 OUTS (outf, pregs (ptr));
2538 OUTS (outf, " + ");
2539 OUTS (outf, uimm4s2 (offset));
2540 OUTS (outf, "] (Z)");
2541 }
2542 else if (W == 0 && op == 2)
2543 {
2544 OUTS (outf, dregs (reg));
2545 OUTS (outf, " = W[");
2546 OUTS (outf, pregs (ptr));
2547 OUTS (outf, " + ");
2548 OUTS (outf, uimm4s2 (offset));
2549 OUTS (outf, "] (X)");
2550 }
2551 else if (W == 0 && op == 3)
2552 {
2553 OUTS (outf, pregs (reg));
2554 OUTS (outf, " = [");
2555 OUTS (outf, pregs (ptr));
2556 OUTS (outf, " + ");
2557 OUTS (outf, uimm4s4 (offset));
2558 OUTS (outf, "]");
2559 }
2560 else if (W == 1 && op == 0)
2561 {
2562 OUTS (outf, "[");
2563 OUTS (outf, pregs (ptr));
2564 OUTS (outf, " + ");
2565 OUTS (outf, uimm4s4 (offset));
2566 OUTS (outf, "] = ");
2567 OUTS (outf, dregs (reg));
2568 }
2569 else if (W == 1 && op == 1)
2570 {
2571 OUTS (outf, "W[");
2572 OUTS (outf, pregs (ptr));
2573 OUTS (outf, " + ");
2574 OUTS (outf, uimm4s2 (offset));
2575 OUTS (outf, "] = ");
2576 OUTS (outf, dregs (reg));
2577 }
2578 else if (W == 1 && op == 3)
2579 {
2580 OUTS (outf, "[");
2581 OUTS (outf, pregs (ptr));
2582 OUTS (outf, " + ");
2583 OUTS (outf, uimm4s4 (offset));
2584 OUTS (outf, "] = ");
2585 OUTS (outf, pregs (reg));
2586 }
2587 else
2588 return 0;
2589
2590 return 2;
2591 }
2592
2593 static int
2594 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2595 {
2596 struct private *priv = outf->private_data;
2597 /* LoopSetup
2598 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2599 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2600 |.reg...........| - | - |.eoffset...............................|
2601 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2602 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2603 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2604 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2605 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2606 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2607
2608 if (priv->parallel)
2609 return 0;
2610
2611 if (reg > 7)
2612 return 0;
2613
2614 if (rop == 0)
2615 {
2616 OUTS (outf, "LSETUP");
2617 OUTS (outf, "(0x");
2618 OUTS (outf, pcrel4 (soffset));
2619 OUTS (outf, ", 0x");
2620 OUTS (outf, lppcrel10 (eoffset));
2621 OUTS (outf, ") ");
2622 OUTS (outf, counters (c));
2623 }
2624 else if (rop == 1)
2625 {
2626 OUTS (outf, "LSETUP");
2627 OUTS (outf, "(0x");
2628 OUTS (outf, pcrel4 (soffset));
2629 OUTS (outf, ", 0x");
2630 OUTS (outf, lppcrel10 (eoffset));
2631 OUTS (outf, ") ");
2632 OUTS (outf, counters (c));
2633 OUTS (outf, " = ");
2634 OUTS (outf, pregs (reg));
2635 }
2636 else if (rop == 3)
2637 {
2638 OUTS (outf, "LSETUP");
2639 OUTS (outf, "(0x");
2640 OUTS (outf, pcrel4 (soffset));
2641 OUTS (outf, ", 0x");
2642 OUTS (outf, lppcrel10 (eoffset));
2643 OUTS (outf, ") ");
2644 OUTS (outf, counters (c));
2645 OUTS (outf, " = ");
2646 OUTS (outf, pregs (reg));
2647 OUTS (outf, " >> 0x1");
2648 }
2649 else
2650 return 0;
2651
2652 return 4;
2653 }
2654
2655 static int
2656 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2657 {
2658 struct private *priv = outf->private_data;
2659 /* LDIMMhalf
2660 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2661 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2662 |.hword.........................................................|
2663 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2664 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2665 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2666 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2667 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2668 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2669 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2670
2671 bu32 *pval = get_allreg (grp, reg);
2672
2673 if (priv->parallel)
2674 return 0;
2675
2676 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2677 to combine them, so it prints out the right values.
2678 Here we keep track of the registers. */
2679 if (H == 0 && S == 1 && Z == 0)
2680 {
2681 /* regs = imm16 (x) */
2682 *pval = imm16_val (hword);
2683 if (hword & 0x8000)
2684 *pval |= 0xFFFF0000;
2685 else
2686 *pval &= 0xFFFF;
2687 }
2688 else if (H == 0 && S == 0 && Z == 1)
2689 {
2690 /* regs = luimm16 (Z) */
2691 *pval = luimm16_val (hword);
2692 *pval &= 0xFFFF;
2693 }
2694 else if (H == 0 && S == 0 && Z == 0)
2695 {
2696 /* regs_lo = luimm16 */
2697 *pval &= 0xFFFF0000;
2698 *pval |= luimm16_val (hword);
2699 }
2700 else if (H == 1 && S == 0 && Z == 0)
2701 {
2702 /* regs_hi = huimm16 */
2703 *pval &= 0xFFFF;
2704 *pval |= luimm16_val (hword) << 16;
2705 }
2706
2707 /* Here we do the disassembly */
2708 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2709 {
2710 OUTS (outf, dregs_lo (reg));
2711 OUTS (outf, " = ");
2712 OUTS (outf, uimm16 (hword));
2713 }
2714 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2715 {
2716 OUTS (outf, dregs_hi (reg));
2717 OUTS (outf, " = ");
2718 OUTS (outf, uimm16 (hword));
2719 }
2720 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2721 {
2722 OUTS (outf, dregs (reg));
2723 OUTS (outf, " = ");
2724 OUTS (outf, imm16 (hword));
2725 OUTS (outf, " (X)");
2726 }
2727 else if (H == 0 && S == 1 && Z == 0)
2728 {
2729 OUTS (outf, regs (reg, grp));
2730 OUTS (outf, " = ");
2731 OUTS (outf, imm16 (hword));
2732 OUTS (outf, " (X)");
2733 }
2734 else if (H == 0 && S == 0 && Z == 1)
2735 {
2736 OUTS (outf, regs (reg, grp));
2737 OUTS (outf, " = ");
2738 OUTS (outf, uimm16 (hword));
2739 OUTS (outf, " (Z)");
2740 }
2741 else if (H == 0 && S == 0 && Z == 0)
2742 {
2743 OUTS (outf, regs_lo (reg, grp));
2744 OUTS (outf, " = ");
2745 OUTS (outf, uimm16 (hword));
2746 }
2747 else if (H == 1 && S == 0 && Z == 0)
2748 {
2749 OUTS (outf, regs_hi (reg, grp));
2750 OUTS (outf, " = ");
2751 OUTS (outf, uimm16 (hword));
2752 }
2753 else
2754 return 0;
2755
2756 /* And we print out the 32-bit value if it is a pointer. */
2757 if (S == 0 && Z == 0)
2758 {
2759 OUTS (outf, ";\t\t/* (");
2760 OUTS (outf, imm16d (hword));
2761 OUTS (outf, ")\t");
2762
2763 /* If it is an MMR, don't print the symbol. */
2764 if (*pval < 0xFFC00000 && grp == 1)
2765 {
2766 OUTS (outf, regs (reg, grp));
2767 OUTS (outf, "=0x");
2768 OUTS (outf, huimm32e (*pval));
2769 }
2770 else
2771 {
2772 OUTS (outf, regs (reg, grp));
2773 OUTS (outf, "=0x");
2774 OUTS (outf, huimm32e (*pval));
2775 OUTS (outf, "(");
2776 OUTS (outf, imm32 (*pval));
2777 OUTS (outf, ")");
2778 }
2779
2780 OUTS (outf, " */");
2781 priv->comment = 1;
2782 }
2783 if (S == 1 || Z == 1)
2784 {
2785 OUTS (outf, ";\t\t/*\t\t");
2786 OUTS (outf, regs (reg, grp));
2787 OUTS (outf, "=0x");
2788 OUTS (outf, huimm32e (*pval));
2789 OUTS (outf, "(");
2790 OUTS (outf, imm32 (*pval));
2791 OUTS (outf, ") */");
2792 priv->comment = 1;
2793 }
2794 return 4;
2795 }
2796
2797 static int
2798 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2799 {
2800 struct private *priv = outf->private_data;
2801 /* CALLa
2802 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2803 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2804 |.lsw...........................................................|
2805 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2806 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2807 int lsw = ((iw1 >> 0) & 0xffff);
2808 int msw = ((iw0 >> 0) & 0xff);
2809
2810 if (priv->parallel)
2811 return 0;
2812
2813 if (S == 1)
2814 OUTS (outf, "CALL 0x");
2815 else if (S == 0)
2816 OUTS (outf, "JUMP.L 0x");
2817 else
2818 return 0;
2819
2820 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2821 return 4;
2822 }
2823
2824 static int
2825 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2826 {
2827 /* LDSTidxI
2828 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2829 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2830 |.offset........................................................|
2831 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2832 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2833 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2834 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2835 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2836 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2837 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2838
2839 if (W == 0 && sz == 0 && Z == 0)
2840 {
2841 OUTS (outf, dregs (reg));
2842 OUTS (outf, " = [");
2843 OUTS (outf, pregs (ptr));
2844 OUTS (outf, " + ");
2845 OUTS (outf, imm16s4 (offset));
2846 OUTS (outf, "]");
2847 }
2848 else if (W == 0 && sz == 0 && Z == 1)
2849 {
2850 OUTS (outf, pregs (reg));
2851 OUTS (outf, " = [");
2852 OUTS (outf, pregs (ptr));
2853 OUTS (outf, " + ");
2854 OUTS (outf, imm16s4 (offset));
2855 OUTS (outf, "]");
2856 }
2857 else if (W == 0 && sz == 1 && Z == 0)
2858 {
2859 OUTS (outf, dregs (reg));
2860 OUTS (outf, " = W[");
2861 OUTS (outf, pregs (ptr));
2862 OUTS (outf, " + ");
2863 OUTS (outf, imm16s2 (offset));
2864 OUTS (outf, "] (Z)");
2865 }
2866 else if (W == 0 && sz == 1 && Z == 1)
2867 {
2868 OUTS (outf, dregs (reg));
2869 OUTS (outf, " = W[");
2870 OUTS (outf, pregs (ptr));
2871 OUTS (outf, " + ");
2872 OUTS (outf, imm16s2 (offset));
2873 OUTS (outf, "] (X)");
2874 }
2875 else if (W == 0 && sz == 2 && Z == 0)
2876 {
2877 OUTS (outf, dregs (reg));
2878 OUTS (outf, " = B[");
2879 OUTS (outf, pregs (ptr));
2880 OUTS (outf, " + ");
2881 OUTS (outf, imm16 (offset));
2882 OUTS (outf, "] (Z)");
2883 }
2884 else if (W == 0 && sz == 2 && Z == 1)
2885 {
2886 OUTS (outf, dregs (reg));
2887 OUTS (outf, " = B[");
2888 OUTS (outf, pregs (ptr));
2889 OUTS (outf, " + ");
2890 OUTS (outf, imm16 (offset));
2891 OUTS (outf, "] (X)");
2892 }
2893 else if (W == 1 && sz == 0 && Z == 0)
2894 {
2895 OUTS (outf, "[");
2896 OUTS (outf, pregs (ptr));
2897 OUTS (outf, " + ");
2898 OUTS (outf, imm16s4 (offset));
2899 OUTS (outf, "] = ");
2900 OUTS (outf, dregs (reg));
2901 }
2902 else if (W == 1 && sz == 0 && Z == 1)
2903 {
2904 OUTS (outf, "[");
2905 OUTS (outf, pregs (ptr));
2906 OUTS (outf, " + ");
2907 OUTS (outf, imm16s4 (offset));
2908 OUTS (outf, "] = ");
2909 OUTS (outf, pregs (reg));
2910 }
2911 else if (W == 1 && sz == 1 && Z == 0)
2912 {
2913 OUTS (outf, "W[");
2914 OUTS (outf, pregs (ptr));
2915 OUTS (outf, " + ");
2916 OUTS (outf, imm16s2 (offset));
2917 OUTS (outf, "] = ");
2918 OUTS (outf, dregs (reg));
2919 }
2920 else if (W == 1 && sz == 2 && Z == 0)
2921 {
2922 OUTS (outf, "B[");
2923 OUTS (outf, pregs (ptr));
2924 OUTS (outf, " + ");
2925 OUTS (outf, imm16 (offset));
2926 OUTS (outf, "] = ");
2927 OUTS (outf, dregs (reg));
2928 }
2929 else
2930 return 0;
2931
2932 return 4;
2933 }
2934
2935 static int
2936 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2937 {
2938 struct private *priv = outf->private_data;
2939 /* linkage
2940 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2941 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2942 |.framesize.....................................................|
2943 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2944 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2945 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2946
2947 if (priv->parallel)
2948 return 0;
2949
2950 if (R == 0)
2951 {
2952 OUTS (outf, "LINK ");
2953 OUTS (outf, uimm16s4 (framesize));
2954 OUTS (outf, ";\t\t/* (");
2955 OUTS (outf, uimm16s4d (framesize));
2956 OUTS (outf, ") */");
2957 priv->comment = 1;
2958 }
2959 else if (R == 1)
2960 OUTS (outf, "UNLINK");
2961 else
2962 return 0;
2963
2964 return 4;
2965 }
2966
2967 static int
2968 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2969 {
2970 /* dsp32mac
2971 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2972 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2973 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2974 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2975 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2976 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2977 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2978 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2979 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2980 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2981 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2982 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2983 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2984 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2985 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2986 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2987 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2988 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2989
2990 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2991 return 0;
2992
2993 if (op1 == 3 && MM)
2994 return 0;
2995
2996 if ((w1 || w0) && mmod == M_W32)
2997 return 0;
2998
2999 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
3000 return 0;
3001
3002 if (w1 == 1 || op1 != 3)
3003 {
3004 if (w1)
3005 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3006
3007 if (op1 == 3)
3008 OUTS (outf, " = A1");
3009 else
3010 {
3011 if (w1)
3012 OUTS (outf, " = (");
3013 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3014 if (w1)
3015 OUTS (outf, ")");
3016 }
3017
3018 if (w0 == 1 || op0 != 3)
3019 {
3020 if (MM)
3021 OUTS (outf, " (M)");
3022 OUTS (outf, ", ");
3023 }
3024 }
3025
3026 if (w0 == 1 || op0 != 3)
3027 {
3028 /* Clear MM option since it only matters for MAC1, and if we made
3029 it this far, we've already shown it or we want to ignore it. */
3030 MM = 0;
3031
3032 if (w0)
3033 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3034
3035 if (op0 == 3)
3036 OUTS (outf, " = A0");
3037 else
3038 {
3039 if (w0)
3040 OUTS (outf, " = (");
3041 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3042 if (w0)
3043 OUTS (outf, ")");
3044 }
3045 }
3046
3047 decode_optmode (mmod, MM, outf);
3048
3049 return 4;
3050 }
3051
3052 static int
3053 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3054 {
3055 /* dsp32mult
3056 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3057 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3058 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3059 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3060 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3061 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3062 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3063 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3064 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3065 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3066 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3067 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3068 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3069 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3070 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3071 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3072
3073 if (w1 == 0 && w0 == 0)
3074 return 0;
3075
3076 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3077 return 0;
3078
3079 if (w1)
3080 {
3081 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3082 OUTS (outf, " = ");
3083 decode_multfunc (h01, h11, src0, src1, outf);
3084
3085 if (w0)
3086 {
3087 if (MM)
3088 OUTS (outf, " (M)");
3089 MM = 0;
3090 OUTS (outf, ", ");
3091 }
3092 }
3093
3094 if (w0)
3095 {
3096 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3097 OUTS (outf, " = ");
3098 decode_multfunc (h00, h10, src0, src1, outf);
3099 }
3100
3101 decode_optmode (mmod, MM, outf);
3102 return 4;
3103 }
3104
3105 static int
3106 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3107 {
3108 /* dsp32alu
3109 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3110 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3111 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3112 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3113 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3114 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3115 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3116 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3117 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3118 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3119 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3120 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3121 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3122
3123 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3124 {
3125 OUTS (outf, "A0.L = ");
3126 OUTS (outf, dregs_lo (src0));
3127 }
3128 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3129 {
3130 OUTS (outf, "A1.H = ");
3131 OUTS (outf, dregs_hi (src0));
3132 }
3133 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3134 {
3135 OUTS (outf, "A1.L = ");
3136 OUTS (outf, dregs_lo (src0));
3137 }
3138 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3139 {
3140 OUTS (outf, "A0.H = ");
3141 OUTS (outf, dregs_hi (src0));
3142 }
3143 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3144 {
3145 OUTS (outf, dregs_hi (dst0));
3146 OUTS (outf, " = ");
3147 OUTS (outf, dregs (src0));
3148 OUTS (outf, " - ");
3149 OUTS (outf, dregs (src1));
3150 OUTS (outf, " (RND20)");
3151 }
3152 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3153 {
3154 OUTS (outf, dregs_hi (dst0));
3155 OUTS (outf, " = ");
3156 OUTS (outf, dregs (src0));
3157 OUTS (outf, " + ");
3158 OUTS (outf, dregs (src1));
3159 OUTS (outf, " (RND20)");
3160 }
3161 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3162 {
3163 OUTS (outf, dregs_lo (dst0));
3164 OUTS (outf, " = ");
3165 OUTS (outf, dregs (src0));
3166 OUTS (outf, " - ");
3167 OUTS (outf, dregs (src1));
3168 OUTS (outf, " (RND12)");
3169 }
3170 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3171 {
3172 OUTS (outf, dregs_lo (dst0));
3173 OUTS (outf, " = ");
3174 OUTS (outf, dregs (src0));
3175 OUTS (outf, " + ");
3176 OUTS (outf, dregs (src1));
3177 OUTS (outf, " (RND12)");
3178 }
3179 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3180 {
3181 OUTS (outf, dregs_lo (dst0));
3182 OUTS (outf, " = ");
3183 OUTS (outf, dregs (src0));
3184 OUTS (outf, " - ");
3185 OUTS (outf, dregs (src1));
3186 OUTS (outf, " (RND20)");
3187 }
3188 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3189 {
3190 OUTS (outf, dregs_hi (dst0));
3191 OUTS (outf, " = ");
3192 OUTS (outf, dregs (src0));
3193 OUTS (outf, " + ");
3194 OUTS (outf, dregs (src1));
3195 OUTS (outf, " (RND12)");
3196 }
3197 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3198 {
3199 OUTS (outf, dregs_lo (dst0));
3200 OUTS (outf, " = ");
3201 OUTS (outf, dregs (src0));
3202 OUTS (outf, " + ");
3203 OUTS (outf, dregs (src1));
3204 OUTS (outf, " (RND20)");
3205 }
3206 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3207 {
3208 OUTS (outf, dregs_hi (dst0));
3209 OUTS (outf, " = ");
3210 OUTS (outf, dregs (src0));
3211 OUTS (outf, " - ");
3212 OUTS (outf, dregs (src1));
3213 OUTS (outf, " (RND12)");
3214 }
3215 else if (HL == 1 && aop == 0 && aopcde == 2)
3216 {
3217 OUTS (outf, dregs_hi (dst0));
3218 OUTS (outf, " = ");
3219 OUTS (outf, dregs_lo (src0));
3220 OUTS (outf, " + ");
3221 OUTS (outf, dregs_lo (src1));
3222 amod1 (s, x, outf);
3223 }
3224 else if (HL == 1 && aop == 1 && aopcde == 2)
3225 {
3226 OUTS (outf, dregs_hi (dst0));
3227 OUTS (outf, " = ");
3228 OUTS (outf, dregs_lo (src0));
3229 OUTS (outf, " + ");
3230 OUTS (outf, dregs_hi (src1));
3231 amod1 (s, x, outf);
3232 }
3233 else if (HL == 1 && aop == 2 && aopcde == 2)
3234 {
3235 OUTS (outf, dregs_hi (dst0));
3236 OUTS (outf, " = ");
3237 OUTS (outf, dregs_hi (src0));
3238 OUTS (outf, " + ");
3239 OUTS (outf, dregs_lo (src1));
3240 amod1 (s, x, outf);
3241 }
3242 else if (HL == 1 && aop == 3 && aopcde == 2)
3243 {
3244 OUTS (outf, dregs_hi (dst0));
3245 OUTS (outf, " = ");
3246 OUTS (outf, dregs_hi (src0));
3247 OUTS (outf, " + ");
3248 OUTS (outf, dregs_hi (src1));
3249 amod1 (s, x, outf);
3250 }
3251 else if (HL == 0 && aop == 0 && aopcde == 3)
3252 {
3253 OUTS (outf, dregs_lo (dst0));
3254 OUTS (outf, " = ");
3255 OUTS (outf, dregs_lo (src0));
3256 OUTS (outf, " - ");
3257 OUTS (outf, dregs_lo (src1));
3258 amod1 (s, x, outf);
3259 }
3260 else if (HL == 0 && aop == 1 && aopcde == 3)
3261 {
3262 OUTS (outf, dregs_lo (dst0));
3263 OUTS (outf, " = ");
3264 OUTS (outf, dregs_lo (src0));
3265 OUTS (outf, " - ");
3266 OUTS (outf, dregs_hi (src1));
3267 amod1 (s, x, outf);
3268 }
3269 else if (HL == 0 && aop == 3 && aopcde == 2)
3270 {
3271 OUTS (outf, dregs_lo (dst0));
3272 OUTS (outf, " = ");
3273 OUTS (outf, dregs_hi (src0));
3274 OUTS (outf, " + ");
3275 OUTS (outf, dregs_hi (src1));
3276 amod1 (s, x, outf);
3277 }
3278 else if (HL == 1 && aop == 0 && aopcde == 3)
3279 {
3280 OUTS (outf, dregs_hi (dst0));
3281 OUTS (outf, " = ");
3282 OUTS (outf, dregs_lo (src0));
3283 OUTS (outf, " - ");
3284 OUTS (outf, dregs_lo (src1));
3285 amod1 (s, x, outf);
3286 }
3287 else if (HL == 1 && aop == 1 && aopcde == 3)
3288 {
3289 OUTS (outf, dregs_hi (dst0));
3290 OUTS (outf, " = ");
3291 OUTS (outf, dregs_lo (src0));
3292 OUTS (outf, " - ");
3293 OUTS (outf, dregs_hi (src1));
3294 amod1 (s, x, outf);
3295 }
3296 else if (HL == 1 && aop == 2 && aopcde == 3)
3297 {
3298 OUTS (outf, dregs_hi (dst0));
3299 OUTS (outf, " = ");
3300 OUTS (outf, dregs_hi (src0));
3301 OUTS (outf, " - ");
3302 OUTS (outf, dregs_lo (src1));
3303 amod1 (s, x, outf);
3304 }
3305 else if (HL == 1 && aop == 3 && aopcde == 3)
3306 {
3307 OUTS (outf, dregs_hi (dst0));
3308 OUTS (outf, " = ");
3309 OUTS (outf, dregs_hi (src0));
3310 OUTS (outf, " - ");
3311 OUTS (outf, dregs_hi (src1));
3312 amod1 (s, x, outf);
3313 }
3314 else if (HL == 0 && aop == 2 && aopcde == 2)
3315 {
3316 OUTS (outf, dregs_lo (dst0));
3317 OUTS (outf, " = ");
3318 OUTS (outf, dregs_hi (src0));
3319 OUTS (outf, " + ");
3320 OUTS (outf, dregs_lo (src1));
3321 amod1 (s, x, outf);
3322 }
3323 else if (HL == 0 && aop == 1 && aopcde == 2)
3324 {
3325 OUTS (outf, dregs_lo (dst0));
3326 OUTS (outf, " = ");
3327 OUTS (outf, dregs_lo (src0));
3328 OUTS (outf, " + ");
3329 OUTS (outf, dregs_hi (src1));
3330 amod1 (s, x, outf);
3331 }
3332 else if (HL == 0 && aop == 2 && aopcde == 3)
3333 {
3334 OUTS (outf, dregs_lo (dst0));
3335 OUTS (outf, " = ");
3336 OUTS (outf, dregs_hi (src0));
3337 OUTS (outf, " - ");
3338 OUTS (outf, dregs_lo (src1));
3339 amod1 (s, x, outf);
3340 }
3341 else if (HL == 0 && aop == 3 && aopcde == 3)
3342 {
3343 OUTS (outf, dregs_lo (dst0));
3344 OUTS (outf, " = ");
3345 OUTS (outf, dregs_hi (src0));
3346 OUTS (outf, " - ");
3347 OUTS (outf, dregs_hi (src1));
3348 amod1 (s, x, outf);
3349 }
3350 else if (HL == 0 && aop == 0 && aopcde == 2)
3351 {
3352 OUTS (outf, dregs_lo (dst0));
3353 OUTS (outf, " = ");
3354 OUTS (outf, dregs_lo (src0));
3355 OUTS (outf, " + ");
3356 OUTS (outf, dregs_lo (src1));
3357 amod1 (s, x, outf);
3358 }
3359 else if (aop == 0 && aopcde == 9 && s == 1)
3360 {
3361 OUTS (outf, "A0 = ");
3362 OUTS (outf, dregs (src0));
3363 }
3364 else if (aop == 3 && aopcde == 11 && s == 0)
3365 OUTS (outf, "A0 -= A1");
3366
3367 else if (aop == 3 && aopcde == 11 && s == 1)
3368 OUTS (outf, "A0 -= A1 (W32)");
3369
3370 else if (aop == 1 && aopcde == 22 && HL == 1)
3371 {
3372 OUTS (outf, dregs (dst0));
3373 OUTS (outf, " = BYTEOP2P (");
3374 OUTS (outf, dregs (src0 + 1));
3375 OUTS (outf, ":");
3376 OUTS (outf, imm5d (src0));
3377 OUTS (outf, ", ");
3378 OUTS (outf, dregs (src1 + 1));
3379 OUTS (outf, ":");
3380 OUTS (outf, imm5d (src1));
3381 OUTS (outf, ") (TH");
3382 if (s == 1)
3383 OUTS (outf, ", R)");
3384 else
3385 OUTS (outf, ")");
3386 }
3387 else if (aop == 1 && aopcde == 22 && HL == 0)
3388 {
3389 OUTS (outf, dregs (dst0));
3390 OUTS (outf, " = BYTEOP2P (");
3391 OUTS (outf, dregs (src0 + 1));
3392 OUTS (outf, ":");
3393 OUTS (outf, imm5d (src0));
3394 OUTS (outf, ", ");
3395 OUTS (outf, dregs (src1 + 1));
3396 OUTS (outf, ":");
3397 OUTS (outf, imm5d (src1));
3398 OUTS (outf, ") (TL");
3399 if (s == 1)
3400 OUTS (outf, ", R)");
3401 else
3402 OUTS (outf, ")");
3403 }
3404 else if (aop == 0 && aopcde == 22 && HL == 1)
3405 {
3406 OUTS (outf, dregs (dst0));
3407 OUTS (outf, " = BYTEOP2P (");
3408 OUTS (outf, dregs (src0 + 1));
3409 OUTS (outf, ":");
3410 OUTS (outf, imm5d (src0));
3411 OUTS (outf, ", ");
3412 OUTS (outf, dregs (src1 + 1));
3413 OUTS (outf, ":");
3414 OUTS (outf, imm5d (src1));
3415 OUTS (outf, ") (RNDH");
3416 if (s == 1)
3417 OUTS (outf, ", R)");
3418 else
3419 OUTS (outf, ")");
3420 }
3421 else if (aop == 0 && aopcde == 22 && HL == 0)
3422 {
3423 OUTS (outf, dregs (dst0));
3424 OUTS (outf, " = BYTEOP2P (");
3425 OUTS (outf, dregs (src0 + 1));
3426 OUTS (outf, ":");
3427 OUTS (outf, imm5d (src0));
3428 OUTS (outf, ", ");
3429 OUTS (outf, dregs (src1 + 1));
3430 OUTS (outf, ":");
3431 OUTS (outf, imm5d (src1));
3432 OUTS (outf, ") (RNDL");
3433 if (s == 1)
3434 OUTS (outf, ", R)");
3435 else
3436 OUTS (outf, ")");
3437 }
3438 else if (aop == 0 && s == 0 && aopcde == 8)
3439 OUTS (outf, "A0 = 0");
3440
3441 else if (aop == 0 && s == 1 && aopcde == 8)
3442 OUTS (outf, "A0 = A0 (S)");
3443
3444 else if (aop == 1 && s == 0 && aopcde == 8)
3445 OUTS (outf, "A1 = 0");
3446
3447 else if (aop == 1 && s == 1 && aopcde == 8)
3448 OUTS (outf, "A1 = A1 (S)");
3449
3450 else if (aop == 2 && s == 0 && aopcde == 8)
3451 OUTS (outf, "A1 = A0 = 0");
3452
3453 else if (aop == 2 && s == 1 && aopcde == 8)
3454 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3455
3456 else if (aop == 3 && s == 0 && aopcde == 8)
3457 OUTS (outf, "A0 = A1");
3458
3459 else if (aop == 3 && s == 1 && aopcde == 8)
3460 OUTS (outf, "A1 = A0");
3461
3462 else if (aop == 1 && aopcde == 9 && s == 0)
3463 {
3464 OUTS (outf, "A0.X = ");
3465 OUTS (outf, dregs_lo (src0));
3466 }
3467 else if (aop == 1 && HL == 0 && aopcde == 11)
3468 {
3469 OUTS (outf, dregs_lo (dst0));
3470 OUTS (outf, " = (A0 += A1)");
3471 }
3472 else if (aop == 3 && HL == 0 && aopcde == 16)
3473 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
3474
3475 else if (aop == 0 && aopcde == 23 && HL == 1)
3476 {
3477 OUTS (outf, dregs (dst0));
3478 OUTS (outf, " = BYTEOP3P (");
3479 OUTS (outf, dregs (src0 + 1));
3480 OUTS (outf, ":");
3481 OUTS (outf, imm5d (src0));
3482 OUTS (outf, ", ");
3483 OUTS (outf, dregs (src1 + 1));
3484 OUTS (outf, ":");
3485 OUTS (outf, imm5d (src1));
3486 OUTS (outf, ") (HI");
3487 if (s == 1)
3488 OUTS (outf, ", R)");
3489 else
3490 OUTS (outf, ")");
3491 }
3492 else if (aop == 3 && aopcde == 9 && s == 0)
3493 {
3494 OUTS (outf, "A1.X = ");
3495 OUTS (outf, dregs_lo (src0));
3496 }
3497 else if (aop == 1 && HL == 1 && aopcde == 16)
3498 OUTS (outf, "A1 = ABS A1");
3499
3500 else if (aop == 0 && HL == 1 && aopcde == 16)
3501 OUTS (outf, "A1 = ABS A0");
3502
3503 else if (aop == 2 && aopcde == 9 && s == 1)
3504 {
3505 OUTS (outf, "A1 = ");
3506 OUTS (outf, dregs (src0));
3507 }
3508 else if (HL == 0 && aop == 3 && aopcde == 12)
3509 {
3510 OUTS (outf, dregs_lo (dst0));
3511 OUTS (outf, " = ");
3512 OUTS (outf, dregs (src0));
3513 OUTS (outf, " (RND)");
3514 }
3515 else if (aop == 1 && HL == 0 && aopcde == 16)
3516 OUTS (outf, "A0 = ABS A1");
3517
3518 else if (aop == 0 && HL == 0 && aopcde == 16)
3519 OUTS (outf, "A0 = ABS A0");
3520
3521 else if (aop == 3 && HL == 0 && aopcde == 15)
3522 {
3523 OUTS (outf, dregs (dst0));
3524 OUTS (outf, " = -");
3525 OUTS (outf, dregs (src0));
3526 OUTS (outf, " (V)");
3527 }
3528 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3529 {
3530 OUTS (outf, dregs (dst0));
3531 OUTS (outf, " = -");
3532 OUTS (outf, dregs (src0));
3533 OUTS (outf, " (S)");
3534 }
3535 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3536 {
3537 OUTS (outf, dregs (dst0));
3538 OUTS (outf, " = -");
3539 OUTS (outf, dregs (src0));
3540 OUTS (outf, " (NS)");
3541 }
3542 else if (aop == 1 && HL == 1 && aopcde == 11)
3543 {
3544 OUTS (outf, dregs_hi (dst0));
3545 OUTS (outf, " = (A0 += A1)");
3546 }
3547 else if (aop == 2 && aopcde == 11 && s == 0)
3548 OUTS (outf, "A0 += A1");
3549
3550 else if (aop == 2 && aopcde == 11 && s == 1)
3551 OUTS (outf, "A0 += A1 (W32)");
3552
3553 else if (aop == 3 && HL == 0 && aopcde == 14)
3554 OUTS (outf, "A1 = -A1, A0 = -A0");
3555
3556 else if (HL == 1 && aop == 3 && aopcde == 12)
3557 {
3558 OUTS (outf, dregs_hi (dst0));
3559 OUTS (outf, " = ");
3560 OUTS (outf, dregs (src0));
3561 OUTS (outf, " (RND)");
3562 }
3563 else if (aop == 0 && aopcde == 23 && HL == 0)
3564 {
3565 OUTS (outf, dregs (dst0));
3566 OUTS (outf, " = BYTEOP3P (");
3567 OUTS (outf, dregs (src0 + 1));
3568 OUTS (outf, ":");
3569 OUTS (outf, imm5d (src0));
3570 OUTS (outf, ", ");
3571 OUTS (outf, dregs (src1 + 1));
3572 OUTS (outf, ":");
3573 OUTS (outf, imm5d (src1));
3574 OUTS (outf, ") (LO");
3575 if (s == 1)
3576 OUTS (outf, ", R)");
3577 else
3578 OUTS (outf, ")");
3579 }
3580 else if (aop == 0 && HL == 0 && aopcde == 14)
3581 OUTS (outf, "A0 = -A0");
3582
3583 else if (aop == 1 && HL == 0 && aopcde == 14)
3584 OUTS (outf, "A0 = -A1");
3585
3586 else if (aop == 0 && HL == 1 && aopcde == 14)
3587 OUTS (outf, "A1 = -A0");
3588
3589 else if (aop == 1 && HL == 1 && aopcde == 14)
3590 OUTS (outf, "A1 = -A1");
3591
3592 else if (aop == 0 && aopcde == 12)
3593 {
3594 OUTS (outf, dregs_hi (dst0));
3595 OUTS (outf, " = ");
3596 OUTS (outf, dregs_lo (dst0));
3597 OUTS (outf, " = SIGN (");
3598 OUTS (outf, dregs_hi (src0));
3599 OUTS (outf, ") * ");
3600 OUTS (outf, dregs_hi (src1));
3601 OUTS (outf, " + SIGN (");
3602 OUTS (outf, dregs_lo (src0));
3603 OUTS (outf, ") * ");
3604 OUTS (outf, dregs_lo (src1));
3605 }
3606 else if (aop == 2 && aopcde == 0)
3607 {
3608 OUTS (outf, dregs (dst0));
3609 OUTS (outf, " = ");
3610 OUTS (outf, dregs (src0));
3611 OUTS (outf, " -|+ ");
3612 OUTS (outf, dregs (src1));
3613 amod0 (s, x, outf);
3614 }
3615 else if (aop == 1 && aopcde == 12)
3616 {
3617 OUTS (outf, dregs (dst1));
3618 OUTS (outf, " = A1.L + A1.H, ");
3619 OUTS (outf, dregs (dst0));
3620 OUTS (outf, " = A0.L + A0.H");
3621 }
3622 else if (aop == 2 && aopcde == 4)
3623 {
3624 OUTS (outf, dregs (dst1));
3625 OUTS (outf, " = ");
3626 OUTS (outf, dregs (src0));
3627 OUTS (outf, " + ");
3628 OUTS (outf, dregs (src1));
3629 OUTS (outf, ", ");
3630 OUTS (outf, dregs (dst0));
3631 OUTS (outf, " = ");
3632 OUTS (outf, dregs (src0));
3633 OUTS (outf, " - ");
3634 OUTS (outf, dregs (src1));
3635 amod1 (s, x, outf);
3636 }
3637 else if (HL == 0 && aopcde == 1)
3638 {
3639 OUTS (outf, dregs (dst1));
3640 OUTS (outf, " = ");
3641 OUTS (outf, dregs (src0));
3642 OUTS (outf, " +|+ ");
3643 OUTS (outf, dregs (src1));
3644 OUTS (outf, ", ");
3645 OUTS (outf, dregs (dst0));
3646 OUTS (outf, " = ");
3647 OUTS (outf, dregs (src0));
3648 OUTS (outf, " -|- ");
3649 OUTS (outf, dregs (src1));
3650 amod0amod2 (s, x, aop, outf);
3651 }
3652 else if (aop == 0 && aopcde == 11)
3653 {
3654 OUTS (outf, dregs (dst0));
3655 OUTS (outf, " = (A0 += A1)");
3656 }
3657 else if (aop == 0 && aopcde == 10)
3658 {
3659 OUTS (outf, dregs_lo (dst0));
3660 OUTS (outf, " = A0.X");
3661 }
3662 else if (aop == 1 && aopcde == 10)
3663 {
3664 OUTS (outf, dregs_lo (dst0));
3665 OUTS (outf, " = A1.X");
3666 }
3667 else if (aop == 1 && aopcde == 0)
3668 {
3669 OUTS (outf, dregs (dst0));
3670 OUTS (outf, " = ");
3671 OUTS (outf, dregs (src0));
3672 OUTS (outf, " +|- ");
3673 OUTS (outf, dregs (src1));
3674 amod0 (s, x, outf);
3675 }
3676 else if (aop == 3 && aopcde == 0)
3677 {
3678 OUTS (outf, dregs (dst0));
3679 OUTS (outf, " = ");
3680 OUTS (outf, dregs (src0));
3681 OUTS (outf, " -|- ");
3682 OUTS (outf, dregs (src1));
3683 amod0 (s, x, outf);
3684 }
3685 else if (aop == 1 && aopcde == 4)
3686 {
3687 OUTS (outf, dregs (dst0));
3688 OUTS (outf, " = ");
3689 OUTS (outf, dregs (src0));
3690 OUTS (outf, " - ");
3691 OUTS (outf, dregs (src1));
3692 amod1 (s, x, outf);
3693 }
3694 else if (aop == 0 && aopcde == 17)
3695 {
3696 OUTS (outf, dregs (dst1));
3697 OUTS (outf, " = A1 + A0, ");
3698 OUTS (outf, dregs (dst0));
3699 OUTS (outf, " = A1 - A0");
3700 amod1 (s, x, outf);
3701 }
3702 else if (aop == 1 && aopcde == 17)
3703 {
3704 OUTS (outf, dregs (dst1));
3705 OUTS (outf, " = A0 + A1, ");
3706 OUTS (outf, dregs (dst0));
3707 OUTS (outf, " = A0 - A1");
3708 amod1 (s, x, outf);
3709 }
3710 else if (aop == 0 && aopcde == 18)
3711 {
3712 OUTS (outf, "SAA (");
3713 OUTS (outf, dregs (src0 + 1));
3714 OUTS (outf, ":");
3715 OUTS (outf, imm5d (src0));
3716 OUTS (outf, ", ");
3717 OUTS (outf, dregs (src1 + 1));
3718 OUTS (outf, ":");
3719 OUTS (outf, imm5d (src1));
3720 OUTS (outf, ")");
3721 aligndir (s, outf);
3722 }
3723 else if (aop == 3 && aopcde == 18)
3724 OUTS (outf, "DISALGNEXCPT");
3725
3726 else if (aop == 0 && aopcde == 20)
3727 {
3728 OUTS (outf, dregs (dst0));
3729 OUTS (outf, " = BYTEOP1P (");
3730 OUTS (outf, dregs (src0 + 1));
3731 OUTS (outf, ":");
3732 OUTS (outf, imm5d (src0));
3733 OUTS (outf, ", ");
3734 OUTS (outf, dregs (src1 + 1));
3735 OUTS (outf, ":");
3736 OUTS (outf, imm5d (src1));
3737 OUTS (outf, ")");
3738 aligndir (s, outf);
3739 }
3740 else if (aop == 1 && aopcde == 20)
3741 {
3742 OUTS (outf, dregs (dst0));
3743 OUTS (outf, " = BYTEOP1P (");
3744 OUTS (outf, dregs (src0 + 1));
3745 OUTS (outf, ":");
3746 OUTS (outf, imm5d (src0));
3747 OUTS (outf, ", ");
3748 OUTS (outf, dregs (src1 + 1));
3749 OUTS (outf, ":");
3750 OUTS (outf, imm5d (src1));
3751 OUTS (outf, ") (T");
3752 if (s == 1)
3753 OUTS (outf, ", R)");
3754 else
3755 OUTS (outf, ")");
3756 }
3757 else if (aop == 0 && aopcde == 21)
3758 {
3759 OUTS (outf, "(");
3760 OUTS (outf, dregs (dst1));
3761 OUTS (outf, ", ");
3762 OUTS (outf, dregs (dst0));
3763 OUTS (outf, ") = BYTEOP16P (");
3764 OUTS (outf, dregs (src0 + 1));
3765 OUTS (outf, ":");
3766 OUTS (outf, imm5d (src0));
3767 OUTS (outf, ", ");
3768 OUTS (outf, dregs (src1 + 1));
3769 OUTS (outf, ":");
3770 OUTS (outf, imm5d (src1));
3771 OUTS (outf, ")");
3772 aligndir (s, outf);
3773 }
3774 else if (aop == 1 && aopcde == 21)
3775 {
3776 OUTS (outf, "(");
3777 OUTS (outf, dregs (dst1));
3778 OUTS (outf, ", ");
3779 OUTS (outf, dregs (dst0));
3780 OUTS (outf, ") = BYTEOP16M (");
3781 OUTS (outf, dregs (src0 + 1));
3782 OUTS (outf, ":");
3783 OUTS (outf, imm5d (src0));
3784 OUTS (outf, ", ");
3785 OUTS (outf, dregs (src1 + 1));
3786 OUTS (outf, ":");
3787 OUTS (outf, imm5d (src1));
3788 OUTS (outf, ")");
3789 aligndir (s, outf);
3790 }
3791 else if (aop == 2 && aopcde == 7)
3792 {
3793 OUTS (outf, dregs (dst0));
3794 OUTS (outf, " = ABS ");
3795 OUTS (outf, dregs (src0));
3796 }
3797 else if (aop == 1 && aopcde == 7)
3798 {
3799 OUTS (outf, dregs (dst0));
3800 OUTS (outf, " = MIN (");
3801 OUTS (outf, dregs (src0));
3802 OUTS (outf, ", ");
3803 OUTS (outf, dregs (src1));
3804 OUTS (outf, ")");
3805 }
3806 else if (aop == 0 && aopcde == 7)
3807 {
3808 OUTS (outf, dregs (dst0));
3809 OUTS (outf, " = MAX (");
3810 OUTS (outf, dregs (src0));
3811 OUTS (outf, ", ");
3812 OUTS (outf, dregs (src1));
3813 OUTS (outf, ")");
3814 }
3815 else if (aop == 2 && aopcde == 6)
3816 {
3817 OUTS (outf, dregs (dst0));
3818 OUTS (outf, " = ABS ");
3819 OUTS (outf, dregs (src0));
3820 OUTS (outf, " (V)");
3821 }
3822 else if (aop == 1 && aopcde == 6)
3823 {
3824 OUTS (outf, dregs (dst0));
3825 OUTS (outf, " = MIN (");
3826 OUTS (outf, dregs (src0));
3827 OUTS (outf, ", ");
3828 OUTS (outf, dregs (src1));
3829 OUTS (outf, ") (V)");
3830 }
3831 else if (aop == 0 && aopcde == 6)
3832 {
3833 OUTS (outf, dregs (dst0));
3834 OUTS (outf, " = MAX (");
3835 OUTS (outf, dregs (src0));
3836 OUTS (outf, ", ");
3837 OUTS (outf, dregs (src1));
3838 OUTS (outf, ") (V)");
3839 }
3840 else if (HL == 1 && aopcde == 1)
3841 {
3842 OUTS (outf, dregs (dst1));
3843 OUTS (outf, " = ");
3844 OUTS (outf, dregs (src0));
3845 OUTS (outf, " +|- ");
3846 OUTS (outf, dregs (src1));
3847 OUTS (outf, ", ");
3848 OUTS (outf, dregs (dst0));
3849 OUTS (outf, " = ");
3850 OUTS (outf, dregs (src0));
3851 OUTS (outf, " -|+ ");
3852 OUTS (outf, dregs (src1));
3853 amod0amod2 (s, x, aop, outf);
3854 }
3855 else if (aop == 0 && aopcde == 4)
3856 {
3857 OUTS (outf, dregs (dst0));
3858 OUTS (outf, " = ");
3859 OUTS (outf, dregs (src0));
3860 OUTS (outf, " + ");
3861 OUTS (outf, dregs (src1));
3862 amod1 (s, x, outf);
3863 }
3864 else if (aop == 0 && aopcde == 0)
3865 {
3866 OUTS (outf, dregs (dst0));
3867 OUTS (outf, " = ");
3868 OUTS (outf, dregs (src0));
3869 OUTS (outf, " +|+ ");
3870 OUTS (outf, dregs (src1));
3871 amod0 (s, x, outf);
3872 }
3873 else if (aop == 0 && aopcde == 24)
3874 {
3875 OUTS (outf, dregs (dst0));
3876 OUTS (outf, " = BYTEPACK (");
3877 OUTS (outf, dregs (src0));
3878 OUTS (outf, ", ");
3879 OUTS (outf, dregs (src1));
3880 OUTS (outf, ")");
3881 }
3882 else if (aop == 1 && aopcde == 24)
3883 {
3884 OUTS (outf, "(");
3885 OUTS (outf, dregs (dst1));
3886 OUTS (outf, ", ");
3887 OUTS (outf, dregs (dst0));
3888 OUTS (outf, ") = BYTEUNPACK ");
3889 OUTS (outf, dregs (src0 + 1));
3890 OUTS (outf, ":");
3891 OUTS (outf, imm5d (src0));
3892 aligndir (s, outf);
3893 }
3894 else if (aopcde == 13)
3895 {
3896 OUTS (outf, "(");
3897 OUTS (outf, dregs (dst1));
3898 OUTS (outf, ", ");
3899 OUTS (outf, dregs (dst0));
3900 OUTS (outf, ") = SEARCH ");
3901 OUTS (outf, dregs (src0));
3902 OUTS (outf, " (");
3903 searchmod (aop, outf);
3904 OUTS (outf, ")");
3905 }
3906 else
3907 return 0;
3908
3909 return 4;
3910 }
3911
3912 static int
3913 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3914 {
3915 /* dsp32shift
3916 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3917 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3918 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3919 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3920 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3921 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3922 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3923 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3924 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3925 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3926 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3927
3928 if (HLs == 0 && sop == 0 && sopcde == 0)
3929 {
3930 OUTS (outf, dregs_lo (dst0));
3931 OUTS (outf, " = ASHIFT ");
3932 OUTS (outf, dregs_lo (src1));
3933 OUTS (outf, " BY ");
3934 OUTS (outf, dregs_lo (src0));
3935 }
3936 else if (HLs == 1 && sop == 0 && sopcde == 0)
3937 {
3938 OUTS (outf, dregs_lo (dst0));
3939 OUTS (outf, " = ASHIFT ");
3940 OUTS (outf, dregs_hi (src1));
3941 OUTS (outf, " BY ");
3942 OUTS (outf, dregs_lo (src0));
3943 }
3944 else if (HLs == 2 && sop == 0 && sopcde == 0)
3945 {
3946 OUTS (outf, dregs_hi (dst0));
3947 OUTS (outf, " = ASHIFT ");
3948 OUTS (outf, dregs_lo (src1));
3949 OUTS (outf, " BY ");
3950 OUTS (outf, dregs_lo (src0));
3951 }
3952 else if (HLs == 3 && sop == 0 && sopcde == 0)
3953 {
3954 OUTS (outf, dregs_hi (dst0));
3955 OUTS (outf, " = ASHIFT ");
3956 OUTS (outf, dregs_hi (src1));
3957 OUTS (outf, " BY ");
3958 OUTS (outf, dregs_lo (src0));
3959 }
3960 else if (HLs == 0 && sop == 1 && sopcde == 0)
3961 {
3962 OUTS (outf, dregs_lo (dst0));
3963 OUTS (outf, " = ASHIFT ");
3964 OUTS (outf, dregs_lo (src1));
3965 OUTS (outf, " BY ");
3966 OUTS (outf, dregs_lo (src0));
3967 OUTS (outf, " (S)");
3968 }
3969 else if (HLs == 1 && sop == 1 && sopcde == 0)
3970 {
3971 OUTS (outf, dregs_lo (dst0));
3972 OUTS (outf, " = ASHIFT ");
3973 OUTS (outf, dregs_hi (src1));
3974 OUTS (outf, " BY ");
3975 OUTS (outf, dregs_lo (src0));
3976 OUTS (outf, " (S)");
3977 }
3978 else if (HLs == 2 && sop == 1 && sopcde == 0)
3979 {
3980 OUTS (outf, dregs_hi (dst0));
3981 OUTS (outf, " = ASHIFT ");
3982 OUTS (outf, dregs_lo (src1));
3983 OUTS (outf, " BY ");
3984 OUTS (outf, dregs_lo (src0));
3985 OUTS (outf, " (S)");
3986 }
3987 else if (HLs == 3 && sop == 1 && sopcde == 0)
3988 {
3989 OUTS (outf, dregs_hi (dst0));
3990 OUTS (outf, " = ASHIFT ");
3991 OUTS (outf, dregs_hi (src1));
3992 OUTS (outf, " BY ");
3993 OUTS (outf, dregs_lo (src0));
3994 OUTS (outf, " (S)");
3995 }
3996 else if (sop == 2 && sopcde == 0)
3997 {
3998 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3999 OUTS (outf, " = LSHIFT ");
4000 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4001 OUTS (outf, " BY ");
4002 OUTS (outf, dregs_lo (src0));
4003 }
4004 else if (sop == 0 && sopcde == 3)
4005 {
4006 OUTS (outf, acc01);
4007 OUTS (outf, " = ASHIFT ");
4008 OUTS (outf, acc01);
4009 OUTS (outf, " BY ");
4010 OUTS (outf, dregs_lo (src0));
4011 }
4012 else if (sop == 1 && sopcde == 3)
4013 {
4014 OUTS (outf, acc01);
4015 OUTS (outf, " = LSHIFT ");
4016 OUTS (outf, acc01);
4017 OUTS (outf, " BY ");
4018 OUTS (outf, dregs_lo (src0));
4019 }
4020 else if (sop == 2 && sopcde == 3)
4021 {
4022 OUTS (outf, acc01);
4023 OUTS (outf, " = ROT ");
4024 OUTS (outf, acc01);
4025 OUTS (outf, " BY ");
4026 OUTS (outf, dregs_lo (src0));
4027 }
4028 else if (sop == 3 && sopcde == 3)
4029 {
4030 OUTS (outf, dregs (dst0));
4031 OUTS (outf, " = ROT ");
4032 OUTS (outf, dregs (src1));
4033 OUTS (outf, " BY ");
4034 OUTS (outf, dregs_lo (src0));
4035 }
4036 else if (sop == 1 && sopcde == 1)
4037 {
4038 OUTS (outf, dregs (dst0));
4039 OUTS (outf, " = ASHIFT ");
4040 OUTS (outf, dregs (src1));
4041 OUTS (outf, " BY ");
4042 OUTS (outf, dregs_lo (src0));
4043 OUTS (outf, " (V, S)");
4044 }
4045 else if (sop == 0 && sopcde == 1)
4046 {
4047 OUTS (outf, dregs (dst0));
4048 OUTS (outf, " = ASHIFT ");
4049 OUTS (outf, dregs (src1));
4050 OUTS (outf, " BY ");
4051 OUTS (outf, dregs_lo (src0));
4052 OUTS (outf, " (V)");
4053 }
4054 else if (sop == 0 && sopcde == 2)
4055 {
4056 OUTS (outf, dregs (dst0));
4057 OUTS (outf, " = ASHIFT ");
4058 OUTS (outf, dregs (src1));
4059 OUTS (outf, " BY ");
4060 OUTS (outf, dregs_lo (src0));
4061 }
4062 else if (sop == 1 && sopcde == 2)
4063 {
4064 OUTS (outf, dregs (dst0));
4065 OUTS (outf, " = ASHIFT ");
4066 OUTS (outf, dregs (src1));
4067 OUTS (outf, " BY ");
4068 OUTS (outf, dregs_lo (src0));
4069 OUTS (outf, " (S)");
4070 }
4071 else if (sop == 2 && sopcde == 2)
4072 {
4073 OUTS (outf, dregs (dst0));
4074 OUTS (outf, " = LSHIFT ");
4075 OUTS (outf, dregs (src1));
4076 OUTS (outf, " BY ");
4077 OUTS (outf, dregs_lo (src0));
4078 }
4079 else if (sop == 3 && sopcde == 2)
4080 {
4081 OUTS (outf, dregs (dst0));
4082 OUTS (outf, " = ROT ");
4083 OUTS (outf, dregs (src1));
4084 OUTS (outf, " BY ");
4085 OUTS (outf, dregs_lo (src0));
4086 }
4087 else if (sop == 2 && sopcde == 1)
4088 {
4089 OUTS (outf, dregs (dst0));
4090 OUTS (outf, " = LSHIFT ");
4091 OUTS (outf, dregs (src1));
4092 OUTS (outf, " BY ");
4093 OUTS (outf, dregs_lo (src0));
4094 OUTS (outf, " (V)");
4095 }
4096 else if (sop == 0 && sopcde == 4)
4097 {
4098 OUTS (outf, dregs (dst0));
4099 OUTS (outf, " = PACK (");
4100 OUTS (outf, dregs_lo (src1));
4101 OUTS (outf, ", ");
4102 OUTS (outf, dregs_lo (src0));
4103 OUTS (outf, ")");
4104 }
4105 else if (sop == 1 && sopcde == 4)
4106 {
4107 OUTS (outf, dregs (dst0));
4108 OUTS (outf, " = PACK (");
4109 OUTS (outf, dregs_lo (src1));
4110 OUTS (outf, ", ");
4111 OUTS (outf, dregs_hi (src0));
4112 OUTS (outf, ")");
4113 }
4114 else if (sop == 2 && sopcde == 4)
4115 {
4116 OUTS (outf, dregs (dst0));
4117 OUTS (outf, " = PACK (");
4118 OUTS (outf, dregs_hi (src1));
4119 OUTS (outf, ", ");
4120 OUTS (outf, dregs_lo (src0));
4121 OUTS (outf, ")");
4122 }
4123 else if (sop == 3 && sopcde == 4)
4124 {
4125 OUTS (outf, dregs (dst0));
4126 OUTS (outf, " = PACK (");
4127 OUTS (outf, dregs_hi (src1));
4128 OUTS (outf, ", ");
4129 OUTS (outf, dregs_hi (src0));
4130 OUTS (outf, ")");
4131 }
4132 else if (sop == 0 && sopcde == 5)
4133 {
4134 OUTS (outf, dregs_lo (dst0));
4135 OUTS (outf, " = SIGNBITS ");
4136 OUTS (outf, dregs (src1));
4137 }
4138 else if (sop == 1 && sopcde == 5)
4139 {
4140 OUTS (outf, dregs_lo (dst0));
4141 OUTS (outf, " = SIGNBITS ");
4142 OUTS (outf, dregs_lo (src1));
4143 }
4144 else if (sop == 2 && sopcde == 5)
4145 {
4146 OUTS (outf, dregs_lo (dst0));
4147 OUTS (outf, " = SIGNBITS ");
4148 OUTS (outf, dregs_hi (src1));
4149 }
4150 else if (sop == 0 && sopcde == 6)
4151 {
4152 OUTS (outf, dregs_lo (dst0));
4153 OUTS (outf, " = SIGNBITS A0");
4154 }
4155 else if (sop == 1 && sopcde == 6)
4156 {
4157 OUTS (outf, dregs_lo (dst0));
4158 OUTS (outf, " = SIGNBITS A1");
4159 }
4160 else if (sop == 3 && sopcde == 6)
4161 {
4162 OUTS (outf, dregs_lo (dst0));
4163 OUTS (outf, " = ONES ");
4164 OUTS (outf, dregs (src1));
4165 }
4166 else if (sop == 0 && sopcde == 7)
4167 {
4168 OUTS (outf, dregs_lo (dst0));
4169 OUTS (outf, " = EXPADJ (");
4170 OUTS (outf, dregs (src1));
4171 OUTS (outf, ", ");
4172 OUTS (outf, dregs_lo (src0));
4173 OUTS (outf, ")");
4174 }
4175 else if (sop == 1 && sopcde == 7)
4176 {
4177 OUTS (outf, dregs_lo (dst0));
4178 OUTS (outf, " = EXPADJ (");
4179 OUTS (outf, dregs (src1));
4180 OUTS (outf, ", ");
4181 OUTS (outf, dregs_lo (src0));
4182 OUTS (outf, ") (V)");
4183 }
4184 else if (sop == 2 && sopcde == 7)
4185 {
4186 OUTS (outf, dregs_lo (dst0));
4187 OUTS (outf, " = EXPADJ (");
4188 OUTS (outf, dregs_lo (src1));
4189 OUTS (outf, ", ");
4190 OUTS (outf, dregs_lo (src0));
4191 OUTS (outf, ")");
4192 }
4193 else if (sop == 3 && sopcde == 7)
4194 {
4195 OUTS (outf, dregs_lo (dst0));
4196 OUTS (outf, " = EXPADJ (");
4197 OUTS (outf, dregs_hi (src1));
4198 OUTS (outf, ", ");
4199 OUTS (outf, dregs_lo (src0));
4200 OUTS (outf, ")");
4201 }
4202 else if (sop == 0 && sopcde == 8)
4203 {
4204 OUTS (outf, "BITMUX (");
4205 OUTS (outf, dregs (src0));
4206 OUTS (outf, ", ");
4207 OUTS (outf, dregs (src1));
4208 OUTS (outf, ", A0) (ASR)");
4209 }
4210 else if (sop == 1 && sopcde == 8)
4211 {
4212 OUTS (outf, "BITMUX (");
4213 OUTS (outf, dregs (src0));
4214 OUTS (outf, ", ");
4215 OUTS (outf, dregs (src1));
4216 OUTS (outf, ", A0) (ASL)");
4217 }
4218 else if (sop == 0 && sopcde == 9)
4219 {
4220 OUTS (outf, dregs_lo (dst0));
4221 OUTS (outf, " = VIT_MAX (");
4222 OUTS (outf, dregs (src1));
4223 OUTS (outf, ") (ASL)");
4224 }
4225 else if (sop == 1 && sopcde == 9)
4226 {
4227 OUTS (outf, dregs_lo (dst0));
4228 OUTS (outf, " = VIT_MAX (");
4229 OUTS (outf, dregs (src1));
4230 OUTS (outf, ") (ASR)");
4231 }
4232 else if (sop == 2 && sopcde == 9)
4233 {
4234 OUTS (outf, dregs (dst0));
4235 OUTS (outf, " = VIT_MAX (");
4236 OUTS (outf, dregs (src1));
4237 OUTS (outf, ", ");
4238 OUTS (outf, dregs (src0));
4239 OUTS (outf, ") (ASL)");
4240 }
4241 else if (sop == 3 && sopcde == 9)
4242 {
4243 OUTS (outf, dregs (dst0));
4244 OUTS (outf, " = VIT_MAX (");
4245 OUTS (outf, dregs (src1));
4246 OUTS (outf, ", ");
4247 OUTS (outf, dregs (src0));
4248 OUTS (outf, ") (ASR)");
4249 }
4250 else if (sop == 0 && sopcde == 10)
4251 {
4252 OUTS (outf, dregs (dst0));
4253 OUTS (outf, " = EXTRACT (");
4254 OUTS (outf, dregs (src1));
4255 OUTS (outf, ", ");
4256 OUTS (outf, dregs_lo (src0));
4257 OUTS (outf, ") (Z)");
4258 }
4259 else if (sop == 1 && sopcde == 10)
4260 {
4261 OUTS (outf, dregs (dst0));
4262 OUTS (outf, " = EXTRACT (");
4263 OUTS (outf, dregs (src1));
4264 OUTS (outf, ", ");
4265 OUTS (outf, dregs_lo (src0));
4266 OUTS (outf, ") (X)");
4267 }
4268 else if (sop == 2 && sopcde == 10)
4269 {
4270 OUTS (outf, dregs (dst0));
4271 OUTS (outf, " = DEPOSIT (");
4272 OUTS (outf, dregs (src1));
4273 OUTS (outf, ", ");
4274 OUTS (outf, dregs (src0));
4275 OUTS (outf, ")");
4276 }
4277 else if (sop == 3 && sopcde == 10)
4278 {
4279 OUTS (outf, dregs (dst0));
4280 OUTS (outf, " = DEPOSIT (");
4281 OUTS (outf, dregs (src1));
4282 OUTS (outf, ", ");
4283 OUTS (outf, dregs (src0));
4284 OUTS (outf, ") (X)");
4285 }
4286 else if (sop == 0 && sopcde == 11)
4287 {
4288 OUTS (outf, dregs_lo (dst0));
4289 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4290 OUTS (outf, dregs (src0));
4291 OUTS (outf, ")");
4292 }
4293 else if (sop == 1 && sopcde == 11)
4294 {
4295 OUTS (outf, dregs_lo (dst0));
4296 OUTS (outf, " = CC = BXOR (A0, ");
4297 OUTS (outf, dregs (src0));
4298 OUTS (outf, ")");
4299 }
4300 else if (sop == 0 && sopcde == 12)
4301 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4302
4303 else if (sop == 1 && sopcde == 12)
4304 {
4305 OUTS (outf, dregs_lo (dst0));
4306 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4307 }
4308 else if (sop == 0 && sopcde == 13)
4309 {
4310 OUTS (outf, dregs (dst0));
4311 OUTS (outf, " = ALIGN8 (");
4312 OUTS (outf, dregs (src1));
4313 OUTS (outf, ", ");
4314 OUTS (outf, dregs (src0));
4315 OUTS (outf, ")");
4316 }
4317 else if (sop == 1 && sopcde == 13)
4318 {
4319 OUTS (outf, dregs (dst0));
4320 OUTS (outf, " = ALIGN16 (");
4321 OUTS (outf, dregs (src1));
4322 OUTS (outf, ", ");
4323 OUTS (outf, dregs (src0));
4324 OUTS (outf, ")");
4325 }
4326 else if (sop == 2 && sopcde == 13)
4327 {
4328 OUTS (outf, dregs (dst0));
4329 OUTS (outf, " = ALIGN24 (");
4330 OUTS (outf, dregs (src1));
4331 OUTS (outf, ", ");
4332 OUTS (outf, dregs (src0));
4333 OUTS (outf, ")");
4334 }
4335 else
4336 return 0;
4337
4338 return 4;
4339 }
4340
4341 static int
4342 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4343 {
4344 /* dsp32shiftimm
4345 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4346 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4347 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4348 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4349 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4350 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4351 int bit8 = ((iw1 >> 8) & 0x1);
4352 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4353 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4354 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4355 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4356 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4357
4358 if (sop == 0 && sopcde == 0)
4359 {
4360 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4361 OUTS (outf, " = ");
4362 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4363 OUTS (outf, " >>> ");
4364 OUTS (outf, uimm4 (newimmag));
4365 }
4366 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4367 {
4368 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4369 OUTS (outf, " = ");
4370 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4371 OUTS (outf, " << ");
4372 OUTS (outf, uimm4 (immag));
4373 OUTS (outf, " (S)");
4374 }
4375 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4376 {
4377 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4378 OUTS (outf, " = ");
4379 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4380 OUTS (outf, " >>> ");
4381 OUTS (outf, uimm4 (newimmag));
4382 OUTS (outf, " (S)");
4383 }
4384 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4385 {
4386 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4387 OUTS (outf, " = ");
4388 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4389 OUTS (outf, " << ");
4390 OUTS (outf, uimm4 (immag));
4391 }
4392 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4393 {
4394 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4395 OUTS (outf, " = ");
4396 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4397 OUTS (outf, " >> ");
4398 OUTS (outf, uimm4 (newimmag));
4399 }
4400 else if (sop == 2 && sopcde == 3 && HLs == 1)
4401 {
4402 OUTS (outf, "A1 = ROT A1 BY ");
4403 OUTS (outf, imm6 (immag));
4404 }
4405 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4406 {
4407 OUTS (outf, "A0 = A0 << ");
4408 OUTS (outf, uimm5 (immag));
4409 }
4410 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4411 {
4412 OUTS (outf, "A0 = A0 >>> ");
4413 OUTS (outf, uimm5 (newimmag));
4414 }
4415 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4416 {
4417 OUTS (outf, "A1 = A1 << ");
4418 OUTS (outf, uimm5 (immag));
4419 }
4420 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4421 {
4422 OUTS (outf, "A1 = A1 >>> ");
4423 OUTS (outf, uimm5 (newimmag));
4424 }
4425 else if (sop == 1 && sopcde == 3 && HLs == 0)
4426 {
4427 OUTS (outf, "A0 = A0 >> ");
4428 OUTS (outf, uimm5 (newimmag));
4429 }
4430 else if (sop == 1 && sopcde == 3 && HLs == 1)
4431 {
4432 OUTS (outf, "A1 = A1 >> ");
4433 OUTS (outf, uimm5 (newimmag));
4434 }
4435 else if (sop == 2 && sopcde == 3 && HLs == 0)
4436 {
4437 OUTS (outf, "A0 = ROT A0 BY ");
4438 OUTS (outf, imm6 (immag));
4439 }
4440 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4441 {
4442 OUTS (outf, dregs (dst0));
4443 OUTS (outf, " = ");
4444 OUTS (outf, dregs (src1));
4445 OUTS (outf, " << ");
4446 OUTS (outf, uimm5 (immag));
4447 OUTS (outf, " (V, S)");
4448 }
4449 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4450 {
4451 OUTS (outf, dregs (dst0));
4452 OUTS (outf, " = ");
4453 OUTS (outf, dregs (src1));
4454 OUTS (outf, " >>> ");
4455 OUTS (outf, imm5 (-immag));
4456 OUTS (outf, " (V, S)");
4457 }
4458 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4459 {
4460 OUTS (outf, dregs (dst0));
4461 OUTS (outf, " = ");
4462 OUTS (outf, dregs (src1));
4463 OUTS (outf, " >> ");
4464 OUTS (outf, uimm5 (newimmag));
4465 OUTS (outf, " (V)");
4466 }
4467 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4468 {
4469 OUTS (outf, dregs (dst0));
4470 OUTS (outf, " = ");
4471 OUTS (outf, dregs (src1));
4472 OUTS (outf, " << ");
4473 OUTS (outf, imm5 (immag));
4474 OUTS (outf, " (V)");
4475 }
4476 else if (sop == 0 && sopcde == 1)
4477 {
4478 OUTS (outf, dregs (dst0));
4479 OUTS (outf, " = ");
4480 OUTS (outf, dregs (src1));
4481 OUTS (outf, " >>> ");
4482 OUTS (outf, uimm5 (newimmag));
4483 OUTS (outf, " (V)");
4484 }
4485 else if (sop == 1 && sopcde == 2)
4486 {
4487 OUTS (outf, dregs (dst0));
4488 OUTS (outf, " = ");
4489 OUTS (outf, dregs (src1));
4490 OUTS (outf, " << ");
4491 OUTS (outf, uimm5 (immag));
4492 OUTS (outf, " (S)");
4493 }
4494 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4495 {
4496 OUTS (outf, dregs (dst0));
4497 OUTS (outf, " = ");
4498 OUTS (outf, dregs (src1));
4499 OUTS (outf, " >> ");
4500 OUTS (outf, uimm5 (newimmag));
4501 }
4502 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4503 {
4504 OUTS (outf, dregs (dst0));
4505 OUTS (outf, " = ");
4506 OUTS (outf, dregs (src1));
4507 OUTS (outf, " << ");
4508 OUTS (outf, uimm5 (immag));
4509 }
4510 else if (sop == 3 && sopcde == 2)
4511 {
4512 OUTS (outf, dregs (dst0));
4513 OUTS (outf, " = ROT ");
4514 OUTS (outf, dregs (src1));
4515 OUTS (outf, " BY ");
4516 OUTS (outf, imm6 (immag));
4517 }
4518 else if (sop == 0 && sopcde == 2)
4519 {
4520 OUTS (outf, dregs (dst0));
4521 OUTS (outf, " = ");
4522 OUTS (outf, dregs (src1));
4523 OUTS (outf, " >>> ");
4524 OUTS (outf, uimm5 (newimmag));
4525 }
4526 else
4527 return 0;
4528
4529 return 4;
4530 }
4531
4532 static int
4533 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4534 {
4535 struct private *priv = outf->private_data;
4536 /* pseudoDEBUG
4537 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4538 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4539 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4540 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4541 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4542 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4543
4544 if (priv->parallel)
4545 return 0;
4546
4547 if (reg == 0 && fn == 3)
4548 OUTS (outf, "DBG A0");
4549
4550 else if (reg == 1 && fn == 3)
4551 OUTS (outf, "DBG A1");
4552
4553 else if (reg == 3 && fn == 3)
4554 OUTS (outf, "ABORT");
4555
4556 else if (reg == 4 && fn == 3)
4557 OUTS (outf, "HLT");
4558
4559 else if (reg == 5 && fn == 3)
4560 OUTS (outf, "DBGHALT");
4561
4562 else if (reg == 6 && fn == 3)
4563 {
4564 OUTS (outf, "DBGCMPLX (");
4565 OUTS (outf, dregs (grp));
4566 OUTS (outf, ")");
4567 }
4568 else if (reg == 7 && fn == 3)
4569 OUTS (outf, "DBG");
4570
4571 else if (grp == 0 && fn == 2)
4572 {
4573 OUTS (outf, "OUTC ");
4574 OUTS (outf, dregs (reg));
4575 }
4576 else if (fn == 0)
4577 {
4578 OUTS (outf, "DBG ");
4579 OUTS (outf, allregs (reg, grp));
4580 }
4581 else if (fn == 1)
4582 {
4583 OUTS (outf, "PRNT ");
4584 OUTS (outf, allregs (reg, grp));
4585 }
4586 else
4587 return 0;
4588
4589 return 2;
4590 }
4591
4592 static int
4593 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4594 {
4595 struct private *priv = outf->private_data;
4596 /* psedoOChar
4597 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4598 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4599 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4600 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4601
4602 if (priv->parallel)
4603 return 0;
4604
4605 OUTS (outf, "OUTC ");
4606 OUTS (outf, uimm8 (ch));
4607
4608 return 2;
4609 }
4610
4611 static int
4612 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4613 {
4614 struct private *priv = outf->private_data;
4615 /* pseudodbg_assert
4616 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4617 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4618 |.expected......................................................|
4619 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4620 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4621 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4622 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4623 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4624
4625 if (priv->parallel)
4626 return 0;
4627
4628 if (dbgop == 0)
4629 {
4630 OUTS (outf, "DBGA (");
4631 OUTS (outf, regs_lo (regtest, grp));
4632 OUTS (outf, ", ");
4633 OUTS (outf, uimm16 (expected));
4634 OUTS (outf, ")");
4635 }
4636 else if (dbgop == 1)
4637 {
4638 OUTS (outf, "DBGA (");
4639 OUTS (outf, regs_hi (regtest, grp));
4640 OUTS (outf, ", ");
4641 OUTS (outf, uimm16 (expected));
4642 OUTS (outf, ")");
4643 }
4644 else if (dbgop == 2)
4645 {
4646 OUTS (outf, "DBGAL (");
4647 OUTS (outf, allregs (regtest, grp));
4648 OUTS (outf, ", ");
4649 OUTS (outf, uimm16 (expected));
4650 OUTS (outf, ")");
4651 }
4652 else if (dbgop == 3)
4653 {
4654 OUTS (outf, "DBGAH (");
4655 OUTS (outf, allregs (regtest, grp));
4656 OUTS (outf, ", ");
4657 OUTS (outf, uimm16 (expected));
4658 OUTS (outf, ")");
4659 }
4660 else
4661 return 0;
4662 return 4;
4663 }
4664
4665 static int
4666 ifetch (bfd_vma pc, disassemble_info *outf, TIword *iw)
4667 {
4668 bfd_byte buf[2];
4669 int status;
4670
4671 status = (*outf->read_memory_func) (pc, buf, 2, outf);
4672 if (status != 0)
4673 {
4674 (*outf->memory_error_func) (status, pc, outf);
4675 return -1;
4676 }
4677
4678 *iw = bfd_getl16 (buf);
4679 return 0;
4680 }
4681
4682 static int
4683 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4684 {
4685 struct private *priv = outf->private_data;
4686 TIword iw0;
4687 TIword iw1;
4688 int rv = 0;
4689
4690 /* The PC must be 16-bit aligned. */
4691 if (pc & 1)
4692 {
4693 OUTS (outf, "ILLEGAL (UNALIGNED)");
4694 /* For people dumping data, just re-align the return value. */
4695 return 1;
4696 }
4697
4698 if (ifetch (pc, outf, &iw0))
4699 return -1;
4700
4701 if ((iw0 & 0xc000) == 0xc000)
4702 {
4703 /* 32-bit insn. */
4704 if (ifetch (pc + 2, outf, &iw1))
4705 return -1;
4706 }
4707 else
4708 /* 16-bit insn. */
4709 iw1 = 0;
4710
4711 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4712 {
4713 if (priv->parallel)
4714 {
4715 OUTS (outf, "ILLEGAL");
4716 return 0;
4717 }
4718 OUTS (outf, "MNOP");
4719 return 4;
4720 }
4721 else if ((iw0 & 0xff00) == 0x0000)
4722 rv = decode_ProgCtrl_0 (iw0, outf);
4723 else if ((iw0 & 0xffc0) == 0x0240)
4724 rv = decode_CaCTRL_0 (iw0, outf);
4725 else if ((iw0 & 0xff80) == 0x0100)
4726 rv = decode_PushPopReg_0 (iw0, outf);
4727 else if ((iw0 & 0xfe00) == 0x0400)
4728 rv = decode_PushPopMultiple_0 (iw0, outf);
4729 else if ((iw0 & 0xfe00) == 0x0600)
4730 rv = decode_ccMV_0 (iw0, outf);
4731 else if ((iw0 & 0xf800) == 0x0800)
4732 rv = decode_CCflag_0 (iw0, outf);
4733 else if ((iw0 & 0xffe0) == 0x0200)
4734 rv = decode_CC2dreg_0 (iw0, outf);
4735 else if ((iw0 & 0xff00) == 0x0300)
4736 rv = decode_CC2stat_0 (iw0, outf);
4737 else if ((iw0 & 0xf000) == 0x1000)
4738 rv = decode_BRCC_0 (iw0, pc, outf);
4739 else if ((iw0 & 0xf000) == 0x2000)
4740 rv = decode_UJUMP_0 (iw0, pc, outf);
4741 else if ((iw0 & 0xf000) == 0x3000)
4742 rv = decode_REGMV_0 (iw0, outf);
4743 else if ((iw0 & 0xfc00) == 0x4000)
4744 rv = decode_ALU2op_0 (iw0, outf);
4745 else if ((iw0 & 0xfe00) == 0x4400)
4746 rv = decode_PTR2op_0 (iw0, outf);
4747 else if ((iw0 & 0xf800) == 0x4800)
4748 rv = decode_LOGI2op_0 (iw0, outf);
4749 else if ((iw0 & 0xf000) == 0x5000)
4750 rv = decode_COMP3op_0 (iw0, outf);
4751 else if ((iw0 & 0xf800) == 0x6000)
4752 rv = decode_COMPI2opD_0 (iw0, outf);
4753 else if ((iw0 & 0xf800) == 0x6800)
4754 rv = decode_COMPI2opP_0 (iw0, outf);
4755 else if ((iw0 & 0xf000) == 0x8000)
4756 rv = decode_LDSTpmod_0 (iw0, outf);
4757 else if ((iw0 & 0xff60) == 0x9e60)
4758 rv = decode_dagMODim_0 (iw0, outf);
4759 else if ((iw0 & 0xfff0) == 0x9f60)
4760 rv = decode_dagMODik_0 (iw0, outf);
4761 else if ((iw0 & 0xfc00) == 0x9c00)
4762 rv = decode_dspLDST_0 (iw0, outf);
4763 else if ((iw0 & 0xf000) == 0x9000)
4764 rv = decode_LDST_0 (iw0, outf);
4765 else if ((iw0 & 0xfc00) == 0xb800)
4766 rv = decode_LDSTiiFP_0 (iw0, outf);
4767 else if ((iw0 & 0xe000) == 0xA000)
4768 rv = decode_LDSTii_0 (iw0, outf);
4769 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4770 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4771 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4772 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4773 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4774 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4775 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4776 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4777 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4778 rv = decode_linkage_0 (iw0, iw1, outf);
4779 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4780 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4781 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4782 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4783 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4784 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4785 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4786 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4787 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4788 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4789 else if ((iw0 & 0xff00) == 0xf800)
4790 rv = decode_pseudoDEBUG_0 (iw0, outf);
4791 else if ((iw0 & 0xFF00) == 0xF900)
4792 rv = decode_pseudoOChar_0 (iw0, outf);
4793 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4794 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4795
4796 if (rv == 0)
4797 OUTS (outf, "ILLEGAL");
4798
4799 return rv;
4800 }
4801
4802 int
4803 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4804 {
4805 struct private priv;
4806 TIword iw0;
4807 int count;
4808
4809 if (ifetch (pc, outf, &iw0) == -1)
4810 return -1;
4811
4812 priv.parallel = 0;
4813 priv.comment = 0;
4814 outf->private_data = &priv;
4815
4816 count = _print_insn_bfin (pc, outf);
4817 if (count == -1)
4818 return -1;
4819
4820 /* Proper display of multiple issue instructions. */
4821
4822 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4823 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4824 {
4825 int legal = 1;
4826 int len;
4827
4828 priv.parallel = 1;
4829 OUTS (outf, " || ");
4830 len = _print_insn_bfin (pc + 4, outf);
4831 if (len == -1)
4832 return -1;
4833 OUTS (outf, " || ");
4834 if (len != 2)
4835 legal = 0;
4836 len = _print_insn_bfin (pc + 6, outf);
4837 if (len == -1)
4838 return -1;
4839 if (len != 2)
4840 legal = 0;
4841
4842 if (legal)
4843 count = 8;
4844 else
4845 {
4846 OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4847 priv.comment = 1;
4848 count = 0;
4849 }
4850 }
4851
4852 if (!priv.comment)
4853 OUTS (outf, ";");
4854
4855 if (count == 0)
4856 return 2;
4857
4858 return count;
4859 }
GDB Binutils - Deliverables
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