opcodes/fr30-desc.h

   1 /* CPU data header for fr30.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef FR30_CPU_H
  26 #define FR30_CPU_H
  27
  28 #define CGEN_ARCH fr30
  29
  30 /* Given symbol S, return fr30_cgen_<S>.  */
  31 #define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_FR30BF
  35
  36 #define CGEN_INSN_LSB0_P 0
  37
  38 /* Minimum size of any insn (in bytes).  */
  39 #define CGEN_MIN_INSN_SIZE 2
  40
  41 /* Maximum size of any insn (in bytes).  */
  42 #define CGEN_MAX_INSN_SIZE 6
  43
  44 #define CGEN_INT_INSN_P 0
  45
  46 /* Maximum nymber of syntax bytes in an instruction.  */
  47 #define CGEN_ACTUAL_MAX_SYNTAX_BYTES 15
  48
  49 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  50    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  51    we can't hash on everything up to the space.  */
  52 #define CGEN_MNEMONIC_OPERANDS
  53
  54 /* Maximum number of fields in an instruction.  */
  55 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
  56
  57 /* Enums.  */
  58
  59 /* Enum declaration for insn op1 enums.  */
  60 typedef enum insn_op1 {
  61   OP1_0, OP1_1, OP1_2, OP1_3
  62  , OP1_4, OP1_5, OP1_6, OP1_7
  63  , OP1_8, OP1_9, OP1_A, OP1_B
  64  , OP1_C, OP1_D, OP1_E, OP1_F
  65 } INSN_OP1;
  66
  67 /* Enum declaration for insn op2 enums.  */
  68 typedef enum insn_op2 {
  69   OP2_0, OP2_1, OP2_2, OP2_3
  70  , OP2_4, OP2_5, OP2_6, OP2_7
  71  , OP2_8, OP2_9, OP2_A, OP2_B
  72  , OP2_C, OP2_D, OP2_E, OP2_F
  73 } INSN_OP2;
  74
  75 /* Enum declaration for insn op3 enums.  */
  76 typedef enum insn_op3 {
  77   OP3_0, OP3_1, OP3_2, OP3_3
  78  , OP3_4, OP3_5, OP3_6, OP3_7
  79  , OP3_8, OP3_9, OP3_A, OP3_B
  80  , OP3_C, OP3_D, OP3_E, OP3_F
  81 } INSN_OP3;
  82
  83 /* Enum declaration for insn op4 enums.  */
  84 typedef enum insn_op4 {
  85   OP4_0
  86 } INSN_OP4;
  87
  88 /* Enum declaration for insn op5 enums.  */
  89 typedef enum insn_op5 {
  90   OP5_0, OP5_1
  91 } INSN_OP5;
  92
  93 /* Enum declaration for insn cc enums.  */
  94 typedef enum insn_cc {
  95   CC_RA, CC_NO, CC_EQ, CC_NE
  96  , CC_C, CC_NC, CC_N, CC_P
  97  , CC_V, CC_NV, CC_LT, CC_GE
  98  , CC_LE, CC_GT, CC_LS, CC_HI
  99 } INSN_CC;
 100
 101 /* Enum declaration for .  */
 102 typedef enum gr_names {
 103   H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
 104  , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
 105  , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
 106  , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
 107  , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15
 108 } GR_NAMES;
 109
 110 /* Enum declaration for .  */
 111 typedef enum cr_names {
 112   H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
 113  , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
 114  , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
 115  , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
 116 } CR_NAMES;
 117
 118 /* Enum declaration for .  */
 119 typedef enum dr_names {
 120   H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
 121  , H_DR_MDH, H_DR_MDL
 122 } DR_NAMES;
 123
 124 /* Attributes.  */
 125
 126 /* Enum declaration for machine type selection.  */
 127 typedef enum mach_attr {
 128   MACH_BASE, MACH_FR30, MACH_MAX
 129 } MACH_ATTR;
 130
 131 /* Enum declaration for instruction set selection.  */
 132 typedef enum isa_attr {
 133   ISA_FR30, ISA_MAX
 134 } ISA_ATTR;
 135
 136 /* Number of architecture variants.  */
 137 #define MAX_ISAS  1
 138 #define MAX_MACHS ((int) MACH_MAX)
 139
 140 /* Ifield support.  */
 141
 142 extern const struct cgen_ifld fr30_cgen_ifld_table[];
 143
 144 /* Ifield attribute indices.  */
 145
 146 /* Enum declaration for cgen_ifld attrs.  */
 147 typedef enum cgen_ifld_attr {
 148   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 149  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 150  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 151 } CGEN_IFLD_ATTR;
 152
 153 /* Number of non-boolean elements in cgen_ifld_attr.  */
 154 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 155
 156 /* Enum declaration for fr30 ifield types.  */
 157 typedef enum ifield_type {
 158   FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2
 159  , FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC
 160  , FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1
 161  , FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ
 162  , FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4
 163  , FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4
 164  , FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6
 165  , FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10
 166  , FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9
 167  , FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST
 168  , FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX
 169 } IFIELD_TYPE;
 170
 171 #define MAX_IFLD ((int) FR30_F_MAX)
 172
 173 /* Hardware attribute indices.  */
 174
 175 /* Enum declaration for cgen_hw attrs.  */
 176 typedef enum cgen_hw_attr {
 177   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 178  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 179 } CGEN_HW_ATTR;
 180
 181 /* Number of non-boolean elements in cgen_hw_attr.  */
 182 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 183
 184 /* Enum declaration for fr30 hardware types.  */
 185 typedef enum cgen_hw_type {
 186   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 187  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR
 188  , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
 189  , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
 190  , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
 191  , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
 192  , HW_H_ILM, HW_MAX
 193 } CGEN_HW_TYPE;
 194
 195 #define MAX_HW ((int) HW_MAX)
 196
 197 /* Operand attribute indices.  */
 198
 199 /* Enum declaration for cgen_operand attrs.  */
 200 typedef enum cgen_operand_attr {
 201   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 202  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 203  , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
 204  , CGEN_OPERAND_END_NBOOLS
 205 } CGEN_OPERAND_ATTR;
 206
 207 /* Number of non-boolean elements in cgen_operand_attr.  */
 208 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 209
 210 /* Enum declaration for fr30 operand types.  */
 211 typedef enum cgen_operand_type {
 212   FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
 213  , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
 214  , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
 215  , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
 216  , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
 217  , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
 218  , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
 219  , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
 220  , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
 221  , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
 222  , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
 223  , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
 224  , FR30_OPERAND_ILM, FR30_OPERAND_MAX
 225 } CGEN_OPERAND_TYPE;
 226
 227 /* Number of operands types.  */
 228 #define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
 229
 230 /* Maximum number of operands referenced by any insn.  */
 231 #define MAX_OPERAND_INSTANCES 8
 232
 233 /* Insn attribute indices.  */
 234
 235 /* Enum declaration for cgen_insn attrs.  */
 236 typedef enum cgen_insn_attr {
 237   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 238  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
 239  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
 240  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 241 } CGEN_INSN_ATTR;
 242
 243 /* Number of non-boolean elements in cgen_insn_attr.  */
 244 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 245
 246 /* cgen.h uses things we just defined.  */
 247 #include "opcode/cgen.h"
 248
 249 /* Attributes.  */
 250 extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[];
 251 extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[];
 252 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
 253 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
 254
 255 /* Hardware decls.  */
 256
 257 extern CGEN_KEYWORD fr30_cgen_opval_gr_names;
 258 extern CGEN_KEYWORD fr30_cgen_opval_cr_names;
 259 extern CGEN_KEYWORD fr30_cgen_opval_dr_names;
 260 extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
 261 extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
 262 extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
 263 extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
 264
 265
 266
 267
 268 #endif /* FR30_CPU_H */