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1998-12-14 Dave Brolley <brolley@cygnus.com>
[deliverable/binutils-gdb.git] / opcodes / fr30-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "fr30-opc.h"
31 #include "opintl.h"
32
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
35
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40 static unsigned int asm_hash_insn PARAMS ((const char *));
41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
43
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
52 The result is a pointer to the insn table entry, or NULL if the instruction
53 wasn't recognized. */
54
55 const CGEN_INSN *
56 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63 {
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
65 unsigned char *bufp;
66 CGEN_INSN_INT base_insn;
67 #if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69 #else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72 #endif
73
74 #if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78 #else
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
81 ex_info.valid = -1;
82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
84 #endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
109 base_insn, fields,
110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145 }
146
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151 void
152 fr30_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157 {
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173 }
174
175 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 fr30_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183 const CGEN_INSN *
184 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190 {
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202 }
203 /* Attributes. */
204
205 static const CGEN_ATTR_ENTRY MACH_attr[] =
206 {
207 { "base", MACH_BASE },
208 { "fr30", MACH_FR30 },
209 { "max", MACH_MAX },
210 { 0, 0 }
211 };
212
213 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
214 {
215 { "CACHE-ADDR", NULL },
216 { "FUN-ACCESS", NULL },
217 { "PC", NULL },
218 { "PROFILE", NULL },
219 { 0, 0 }
220 };
221
222 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
223 {
224 { "ABS-ADDR", NULL },
225 { "HASH-PREFIX", NULL },
226 { "NEGATIVE", NULL },
227 { "PCREL-ADDR", NULL },
228 { "RELAX", NULL },
229 { "SEM-ONLY", NULL },
230 { "SIGN-OPT", NULL },
231 { "SIGNED", NULL },
232 { "UNSIGNED", NULL },
233 { "VIRTUAL", NULL },
234 { 0, 0 }
235 };
236
237 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
238 {
239 { "ALIAS", NULL },
240 { "COND-CTI", NULL },
241 { "DELAY-SLOT", NULL },
242 { "NO-DIS", NULL },
243 { "NOT-IN-DELAY-SLOT", NULL },
244 { "RELAX", NULL },
245 { "RELAXABLE", NULL },
246 { "SKIP-CTI", NULL },
247 { "UNCOND-CTI", NULL },
248 { "VIRTUAL", NULL },
249 { 0, 0 }
250 };
251
252 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
253 {
254 { "ac", 13 },
255 { "fp", 14 },
256 { "sp", 15 },
257 { "r0", 0 },
258 { "r1", 1 },
259 { "r2", 2 },
260 { "r3", 3 },
261 { "r4", 4 },
262 { "r5", 5 },
263 { "r6", 6 },
264 { "r7", 7 },
265 { "r8", 8 },
266 { "r9", 9 },
267 { "r10", 10 },
268 { "r11", 11 },
269 { "r12", 12 },
270 { "r13", 13 },
271 { "r14", 14 },
272 { "r15", 15 }
273 };
274
275 CGEN_KEYWORD fr30_cgen_opval_h_gr =
276 {
277 & fr30_cgen_opval_h_gr_entries[0],
278 19
279 };
280
281 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
282 {
283 { "cr0", 0 },
284 { "cr1", 1 },
285 { "cr2", 2 },
286 { "cr3", 3 },
287 { "cr4", 4 },
288 { "cr5", 5 },
289 { "cr6", 6 },
290 { "cr7", 7 },
291 { "cr8", 8 },
292 { "cr9", 9 },
293 { "cr10", 10 },
294 { "cr11", 11 },
295 { "cr12", 12 },
296 { "cr13", 13 },
297 { "cr14", 14 },
298 { "cr15", 15 }
299 };
300
301 CGEN_KEYWORD fr30_cgen_opval_h_cr =
302 {
303 & fr30_cgen_opval_h_cr_entries[0],
304 16
305 };
306
307 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
308 {
309 { "tbr", 0 },
310 { "rp", 1 },
311 { "ssp", 2 },
312 { "usp", 3 },
313 { "mdh", 4 },
314 { "mdl", 5 }
315 };
316
317 CGEN_KEYWORD fr30_cgen_opval_h_dr =
318 {
319 & fr30_cgen_opval_h_dr_entries[0],
320 6
321 };
322
323 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
324 {
325 { "ps", 0 }
326 };
327
328 CGEN_KEYWORD fr30_cgen_opval_h_ps =
329 {
330 & fr30_cgen_opval_h_ps_entries[0],
331 1
332 };
333
334 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
335 {
336 { "r13", 0 }
337 };
338
339 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
340 {
341 & fr30_cgen_opval_h_r13_entries[0],
342 1
343 };
344
345 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
346 {
347 { "r14", 0 }
348 };
349
350 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
351 {
352 & fr30_cgen_opval_h_r14_entries[0],
353 1
354 };
355
356 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
357 {
358 { "r15", 0 }
359 };
360
361 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
362 {
363 & fr30_cgen_opval_h_r15_entries[0],
364 1
365 };
366
367
368 /* The hardware table. */
369
370 #define HW_ENT(n) fr30_cgen_hw_entries[n]
371 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
372 {
373 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
374 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
375 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
376 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
377 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
378 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
379 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
380 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
381 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
382 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
383 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
384 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
385 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
386 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
387 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
388 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
389 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
390 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
391 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
392 { HW_H_TBIT, & HW_ENT (HW_H_TBIT + 1), "h-tbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
393 { HW_H_D0BIT, & HW_ENT (HW_H_D0BIT + 1), "h-d0bit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
394 { HW_H_D1BIT, & HW_ENT (HW_H_D1BIT + 1), "h-d1bit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
395 { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
396 { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
397 { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
398 { 0 }
399 };
400
401 /* The instruction field table. */
402
403 static const CGEN_IFLD fr30_cgen_ifld_table[] =
404 {
405 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
406 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
407 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
408 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
409 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
410 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
411 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
412 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
413 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
414 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
415 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
416 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
417 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
418 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
419 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
420 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
421 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
422 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
423 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
424 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
425 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
426 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
427 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
428 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
429 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
430 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
431 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
432 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
433 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
434 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
435 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
436 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
437 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
438 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
439 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
440 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
441 { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
442 { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
443 { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
444 { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
445 { 0 }
446 };
447
448 /* The operand table. */
449
450 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
451 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
452
453 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
454 {
455 /* pc: program counter */
456 { "pc", & HW_ENT (HW_H_PC), 0, 0,
457 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
458 /* Ri: destination register */
459 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
460 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
461 /* Rj: source register */
462 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
463 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
464 /* Ric: target register coproc insn */
465 { "Ric", & HW_ENT (HW_H_GR), 12, 4,
466 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
467 /* Rjc: source register coproc insn */
468 { "Rjc", & HW_ENT (HW_H_GR), 8, 4,
469 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
470 /* CRi: coprocessor register */
471 { "CRi", & HW_ENT (HW_H_CR), 12, 4,
472 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
473 /* CRj: coprocessor register */
474 { "CRj", & HW_ENT (HW_H_CR), 8, 4,
475 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
476 /* Rs1: dedicated register */
477 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
478 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
479 /* Rs2: dedicated register */
480 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
481 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
482 /* R13: General Register 13 */
483 { "R13", & HW_ENT (HW_H_R13), 0, 0,
484 { 0, 0, { 0 } } },
485 /* R14: General Register 14 */
486 { "R14", & HW_ENT (HW_H_R14), 0, 0,
487 { 0, 0, { 0 } } },
488 /* R15: General Register 15 */
489 { "R15", & HW_ENT (HW_H_R15), 0, 0,
490 { 0, 0, { 0 } } },
491 /* ps: Program Status register */
492 { "ps", & HW_ENT (HW_H_PS), 0, 0,
493 { 0, 0, { 0 } } },
494 /* u4: 4 bit unsigned immediate */
495 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
496 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
497 /* u4c: 4 bit unsigned immediate */
498 { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
499 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
500 /* u8: 8 bit unsigned immediate */
501 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
502 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
503 /* i8: 8 bit unsigned immediate */
504 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
505 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
506 /* udisp6: 6 bit unsigned immediate */
507 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
508 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
509 /* disp8: 8 bit signed immediate */
510 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
511 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
512 /* disp9: 9 bit signed immediate */
513 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
514 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
515 /* disp10: 10 bit signed immediate */
516 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
517 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
518 /* s10: 10 bit signed immediate */
519 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
520 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
521 /* u10: 10 bit unsigned immediate */
522 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
523 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
524 /* i32: 32 bit immediate */
525 { "i32", & HW_ENT (HW_H_UINT), 0, 32,
526 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
527 /* m4: 4 bit negative immediate */
528 { "m4", & HW_ENT (HW_H_SINT), 8, 4,
529 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
530 /* i20: 20 bit immediate */
531 { "i20", & HW_ENT (HW_H_UINT), 0, 20,
532 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { 0 } } },
533 /* dir8: 8 bit direct address */
534 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
535 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
536 /* dir9: 9 bit direct address */
537 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
538 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
539 /* dir10: 10 bit direct address */
540 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
541 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
542 /* label9: 9 bit pc relative address */
543 { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
544 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
545 /* label12: 12 bit pc relative address */
546 { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
547 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
548 /* reglist_low_ld: 8 bit register mask for ldm */
549 { "reglist_low_ld", & HW_ENT (HW_H_UINT), 8, 8,
550 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
551 /* reglist_hi_ld: 8 bit register mask for ldm */
552 { "reglist_hi_ld", & HW_ENT (HW_H_UINT), 8, 8,
553 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
554 /* reglist_low_st: 8 bit register mask for ldm */
555 { "reglist_low_st", & HW_ENT (HW_H_UINT), 8, 8,
556 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
557 /* reglist_hi_st: 8 bit register mask for ldm */
558 { "reglist_hi_st", & HW_ENT (HW_H_UINT), 8, 8,
559 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
560 /* cc: condition codes */
561 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
562 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
563 /* ccc: coprocessor calc */
564 { "ccc", & HW_ENT (HW_H_UINT), 0, 8,
565 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
566 /* nbit: negative bit */
567 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
568 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
569 /* vbit: overflow bit */
570 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
571 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
572 /* zbit: zero bit */
573 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
574 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
575 /* cbit: carry bit */
576 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
577 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
578 /* ibit: interrupt bit */
579 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
580 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
581 /* sbit: stack bit */
582 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
583 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
584 /* tbit: trace trap bit */
585 { "tbit", & HW_ENT (HW_H_TBIT), 0, 0,
586 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
587 /* d0bit: division 0 bit */
588 { "d0bit", & HW_ENT (HW_H_D0BIT), 0, 0,
589 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
590 /* d1bit: division 1 bit */
591 { "d1bit", & HW_ENT (HW_H_D1BIT), 0, 0,
592 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
593 /* ccr: condition code bits */
594 { "ccr", & HW_ENT (HW_H_CCR), 0, 0,
595 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
596 /* scr: system condition bits */
597 { "scr", & HW_ENT (HW_H_SCR), 0, 0,
598 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
599 /* ilm: condition code bits */
600 { "ilm", & HW_ENT (HW_H_ILM), 0, 0,
601 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
602 };
603
604 /* Operand references. */
605
606 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
607 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
608 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
609
610 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
611 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
612 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
613 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
614 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
615 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
616 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
617 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
618 { 0 }
619 };
620
621 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
622 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
623 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
624 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
625 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
626 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
627 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
628 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
629 { 0 }
630 };
631
632 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
633 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
634 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
635 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
636 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
637 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
638 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
639 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
640 { 0 }
641 };
642
643 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
644 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
645 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
646 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
647 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
648 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
649 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
650 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
651 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
652 { 0 }
653 };
654
655 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
656 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
657 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
658 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
659 { 0 }
660 };
661
662 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
663 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
664 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
665 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
666 { 0 }
667 };
668
669 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
670 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
671 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
672 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
673 { 0 }
674 };
675
676 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
677 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
678 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
679 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
680 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
681 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
682 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
683 { 0 }
684 };
685
686 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
687 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
688 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
689 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
690 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
691 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
692 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
693 { 0 }
694 };
695
696 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
697 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
698 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
699 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
700 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
701 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
702 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
703 { 0 }
704 };
705
706 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
707 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
708 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
709 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
710 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
711 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
712 { 0 }
713 };
714
715 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
716 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
717 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
718 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
719 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
720 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
721 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
722 { 0 }
723 };
724
725 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
726 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
727 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
728 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
729 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
730 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
731 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
732 { 0 }
733 };
734
735 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
736 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
737 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
738 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
739 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
740 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
741 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
742 { 0 }
743 };
744
745 static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
746 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
747 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
748 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
749 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
750 { 0 }
751 };
752
753 static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
754 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
755 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
756 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
757 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
758 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
759 { 0 }
760 };
761
762 static const CGEN_OPERAND_INSTANCE fmt_mul_ops[] = {
763 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
764 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
765 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
766 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
767 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
768 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
769 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
770 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
771 { 0 }
772 };
773
774 static const CGEN_OPERAND_INSTANCE fmt_mulu_ops[] = {
775 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
776 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
777 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
778 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
779 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
780 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
781 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
782 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
783 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
784 { 0 }
785 };
786
787 static const CGEN_OPERAND_INSTANCE fmt_mulh_ops[] = {
788 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
789 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
790 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
791 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
792 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
793 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
794 { 0 }
795 };
796
797 static const CGEN_OPERAND_INSTANCE fmt_div0s_ops[] = {
798 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
799 { INPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
800 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
801 { OUTPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
802 { OUTPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
803 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
804 { 0 }
805 };
806
807 static const CGEN_OPERAND_INSTANCE fmt_div0u_ops[] = {
808 { OUTPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
809 { OUTPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
810 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
811 { 0 }
812 };
813
814 static const CGEN_OPERAND_INSTANCE fmt_div1_ops[] = {
815 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
816 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
817 { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
818 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
819 { INPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
820 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
821 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
822 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
823 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
824 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
825 { 0 }
826 };
827
828 static const CGEN_OPERAND_INSTANCE fmt_div2_ops[] = {
829 { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
830 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
831 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
832 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
833 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, COND_REF },
834 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
835 { 0 }
836 };
837
838 static const CGEN_OPERAND_INSTANCE fmt_div3_ops[] = {
839 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
840 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
841 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
842 { 0 }
843 };
844
845 static const CGEN_OPERAND_INSTANCE fmt_div4s_ops[] = {
846 { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
847 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
848 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
849 { 0 }
850 };
851
852 static const CGEN_OPERAND_INSTANCE fmt_lsl_ops[] = {
853 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
854 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
855 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
856 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
857 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
858 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
859 { 0 }
860 };
861
862 static const CGEN_OPERAND_INSTANCE fmt_lsli_ops[] = {
863 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
864 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
865 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
866 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
867 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
868 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
869 { 0 }
870 };
871
872 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
873 { INPUT, "i8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I8), 0, 0 },
874 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
875 { 0 }
876 };
877
878 static const CGEN_OPERAND_INSTANCE fmt_ldi20_ops[] = {
879 { INPUT, "i20", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I20), 0, 0 },
880 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
881 { 0 }
882 };
883
884 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
885 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
886 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
887 { 0 }
888 };
889
890 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
891 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
892 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
893 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
894 { 0 }
895 };
896
897 static const CGEN_OPERAND_INSTANCE fmt_lduh_ops[] = {
898 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
899 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
900 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
901 { 0 }
902 };
903
904 static const CGEN_OPERAND_INSTANCE fmt_ldub_ops[] = {
905 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
906 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
907 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
908 { 0 }
909 };
910
911 static const CGEN_OPERAND_INSTANCE fmt_ldr13_ops[] = {
912 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
913 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
914 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
915 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
916 { 0 }
917 };
918
919 static const CGEN_OPERAND_INSTANCE fmt_ldr13uh_ops[] = {
920 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
921 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
922 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
923 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
924 { 0 }
925 };
926
927 static const CGEN_OPERAND_INSTANCE fmt_ldr13ub_ops[] = {
928 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
929 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
930 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
931 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
932 { 0 }
933 };
934
935 static const CGEN_OPERAND_INSTANCE fmt_ldr14_ops[] = {
936 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
937 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
938 { INPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
939 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
940 { 0 }
941 };
942
943 static const CGEN_OPERAND_INSTANCE fmt_ldr14uh_ops[] = {
944 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
945 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
946 { INPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
947 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
948 { 0 }
949 };
950
951 static const CGEN_OPERAND_INSTANCE fmt_ldr14ub_ops[] = {
952 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
953 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
954 { INPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
955 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
956 { 0 }
957 };
958
959 static const CGEN_OPERAND_INSTANCE fmt_ldr15_ops[] = {
960 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
961 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
962 { INPUT, "h_memory_add__VM_udisp6_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
963 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
964 { 0 }
965 };
966
967 static const CGEN_OPERAND_INSTANCE fmt_ldr15gr_ops[] = {
968 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
969 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
970 { INPUT, "f_Ri", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
971 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
972 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
973 { 0 }
974 };
975
976 static const CGEN_OPERAND_INSTANCE fmt_ldr15dr_ops[] = {
977 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
978 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
979 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
980 { OUTPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
981 { 0 }
982 };
983
984 static const CGEN_OPERAND_INSTANCE fmt_ldr15ps_ops[] = {
985 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
986 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
987 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
988 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
989 { 0 }
990 };
991
992 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
993 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
994 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
995 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
996 { 0 }
997 };
998
999 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
1000 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1001 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1002 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1003 { 0 }
1004 };
1005
1006 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
1007 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1008 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1009 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1010 { 0 }
1011 };
1012
1013 static const CGEN_OPERAND_INSTANCE fmt_str13_ops[] = {
1014 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1015 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1016 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1017 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1018 { 0 }
1019 };
1020
1021 static const CGEN_OPERAND_INSTANCE fmt_str13h_ops[] = {
1022 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1023 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1024 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1025 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1026 { 0 }
1027 };
1028
1029 static const CGEN_OPERAND_INSTANCE fmt_str13b_ops[] = {
1030 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1031 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1032 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1033 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1034 { 0 }
1035 };
1036
1037 static const CGEN_OPERAND_INSTANCE fmt_str14_ops[] = {
1038 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
1039 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1040 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1041 { OUTPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1042 { 0 }
1043 };
1044
1045 static const CGEN_OPERAND_INSTANCE fmt_str14h_ops[] = {
1046 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
1047 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1048 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1049 { OUTPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1050 { 0 }
1051 };
1052
1053 static const CGEN_OPERAND_INSTANCE fmt_str14b_ops[] = {
1054 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
1055 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1056 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1057 { OUTPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1058 { 0 }
1059 };
1060
1061 static const CGEN_OPERAND_INSTANCE fmt_str15_ops[] = {
1062 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1063 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
1064 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1065 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_15_udisp6", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1066 { 0 }
1067 };
1068
1069 static const CGEN_OPERAND_INSTANCE fmt_str15gr_ops[] = {
1070 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1071 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1072 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1073 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1074 { 0 }
1075 };
1076
1077 static const CGEN_OPERAND_INSTANCE fmt_str15dr_ops[] = {
1078 { INPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
1079 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1080 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1081 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1082 { 0 }
1083 };
1084
1085 static const CGEN_OPERAND_INSTANCE fmt_str15ps_ops[] = {
1086 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1087 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1088 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1089 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1090 { 0 }
1091 };
1092
1093 static const CGEN_OPERAND_INSTANCE fmt_mov_ops[] = {
1094 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1095 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1096 { 0 }
1097 };
1098
1099 static const CGEN_OPERAND_INSTANCE fmt_movdr_ops[] = {
1100 { INPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1101 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1102 { 0 }
1103 };
1104
1105 static const CGEN_OPERAND_INSTANCE fmt_movps_ops[] = {
1106 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1107 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1108 { 0 }
1109 };
1110
1111 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
1112 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1113 { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1114 { 0 }
1115 };
1116
1117 static const CGEN_OPERAND_INSTANCE fmt_mov2ps_ops[] = {
1118 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1119 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1120 { 0 }
1121 };
1122
1123 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
1124 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1125 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1126 { 0 }
1127 };
1128
1129 static const CGEN_OPERAND_INSTANCE fmt_callr_ops[] = {
1130 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1131 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1132 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1133 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1134 { 0 }
1135 };
1136
1137 static const CGEN_OPERAND_INSTANCE fmt_call_ops[] = {
1138 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1139 { INPUT, "label12", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL12), 0, 0 },
1140 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1141 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1142 { 0 }
1143 };
1144
1145 static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
1146 { INPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1147 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1148 { 0 }
1149 };
1150
1151 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
1152 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1153 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
1154 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
1155 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1156 { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1157 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1158 { 0 }
1159 };
1160
1161 static const CGEN_OPERAND_INSTANCE fmt_inte_ops[] = {
1162 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1163 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
1164 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1165 { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
1166 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1167 { 0 }
1168 };
1169
1170 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
1171 { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1172 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
1173 { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1174 { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
1175 { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1176 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1177 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
1178 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
1179 { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
1180 { 0 }
1181 };
1182
1183 static const CGEN_OPERAND_INSTANCE fmt_brad_ops[] = {
1184 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1185 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1186 { 0 }
1187 };
1188
1189 static const CGEN_OPERAND_INSTANCE fmt_beqd_ops[] = {
1190 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1191 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1192 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1193 { 0 }
1194 };
1195
1196 static const CGEN_OPERAND_INSTANCE fmt_bcd_ops[] = {
1197 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1198 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1199 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1200 { 0 }
1201 };
1202
1203 static const CGEN_OPERAND_INSTANCE fmt_bnd_ops[] = {
1204 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1205 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1206 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1207 { 0 }
1208 };
1209
1210 static const CGEN_OPERAND_INSTANCE fmt_bvd_ops[] = {
1211 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1212 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1213 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1214 { 0 }
1215 };
1216
1217 static const CGEN_OPERAND_INSTANCE fmt_bltd_ops[] = {
1218 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1219 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1220 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1221 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1222 { 0 }
1223 };
1224
1225 static const CGEN_OPERAND_INSTANCE fmt_bled_ops[] = {
1226 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1227 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1228 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1229 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1230 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1231 { 0 }
1232 };
1233
1234 static const CGEN_OPERAND_INSTANCE fmt_blsd_ops[] = {
1235 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1236 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1237 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1238 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1239 { 0 }
1240 };
1241
1242 static const CGEN_OPERAND_INSTANCE fmt_dmovr13_ops[] = {
1243 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1244 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1245 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1246 { 0 }
1247 };
1248
1249 static const CGEN_OPERAND_INSTANCE fmt_dmovr13h_ops[] = {
1250 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1251 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1252 { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1253 { 0 }
1254 };
1255
1256 static const CGEN_OPERAND_INSTANCE fmt_dmovr13b_ops[] = {
1257 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1258 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1259 { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1260 { 0 }
1261 };
1262
1263 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pi_ops[] = {
1264 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1265 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1266 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1267 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1268 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1269 { 0 }
1270 };
1271
1272 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pih_ops[] = {
1273 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1274 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1275 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1276 { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1277 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1278 { 0 }
1279 };
1280
1281 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pib_ops[] = {
1282 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1283 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1284 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1285 { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1286 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1287 { 0 }
1288 };
1289
1290 static const CGEN_OPERAND_INSTANCE fmt_dmovr15pi_ops[] = {
1291 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1292 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1293 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1294 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1295 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1296 { 0 }
1297 };
1298
1299 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13_ops[] = {
1300 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1301 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1302 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1303 { 0 }
1304 };
1305
1306 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13h_ops[] = {
1307 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1308 { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1309 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1310 { 0 }
1311 };
1312
1313 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13b_ops[] = {
1314 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1315 { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1316 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1317 { 0 }
1318 };
1319
1320 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pi_ops[] = {
1321 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1322 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1323 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1324 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1325 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1326 { 0 }
1327 };
1328
1329 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pih_ops[] = {
1330 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1331 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1332 { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1333 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1334 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1335 { 0 }
1336 };
1337
1338 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pib_ops[] = {
1339 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1340 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1341 { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1342 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1343 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1344 { 0 }
1345 };
1346
1347 static const CGEN_OPERAND_INSTANCE fmt_dmov2r15pd_ops[] = {
1348 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1349 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1350 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1351 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1352 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1353 { 0 }
1354 };
1355
1356 static const CGEN_OPERAND_INSTANCE fmt_andccr_ops[] = {
1357 { INPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1358 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1359 { OUTPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1360 { 0 }
1361 };
1362
1363 static const CGEN_OPERAND_INSTANCE fmt_stilm_ops[] = {
1364 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1365 { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
1366 { 0 }
1367 };
1368
1369 static const CGEN_OPERAND_INSTANCE fmt_addsp_ops[] = {
1370 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1371 { INPUT, "s10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (S10), 0, 0 },
1372 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1373 { 0 }
1374 };
1375
1376 static const CGEN_OPERAND_INSTANCE fmt_extsb_ops[] = {
1377 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RI), 0, 0 },
1378 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1379 { 0 }
1380 };
1381
1382 static const CGEN_OPERAND_INSTANCE fmt_extub_ops[] = {
1383 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UQI, & OP_ENT (RI), 0, 0 },
1384 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1385 { 0 }
1386 };
1387
1388 static const CGEN_OPERAND_INSTANCE fmt_extsh_ops[] = {
1389 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RI), 0, 0 },
1390 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1391 { 0 }
1392 };
1393
1394 static const CGEN_OPERAND_INSTANCE fmt_extuh_ops[] = {
1395 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UHI, & OP_ENT (RI), 0, 0 },
1396 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1397 { 0 }
1398 };
1399
1400 static const CGEN_OPERAND_INSTANCE fmt_ldm0_ops[] = {
1401 { INPUT, "reglist_low_ld", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW_LD), 0, 0 },
1402 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1403 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1404 { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
1405 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1406 { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, COND_REF },
1407 { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, COND_REF },
1408 { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, COND_REF },
1409 { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, COND_REF },
1410 { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, COND_REF },
1411 { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, COND_REF },
1412 { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, COND_REF },
1413 { 0 }
1414 };
1415
1416 static const CGEN_OPERAND_INSTANCE fmt_ldm1_ops[] = {
1417 { INPUT, "reglist_hi_ld", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_HI_LD), 0, 0 },
1418 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1419 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1420 { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, COND_REF },
1421 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1422 { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, COND_REF },
1423 { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, COND_REF },
1424 { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, COND_REF },
1425 { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, COND_REF },
1426 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, COND_REF },
1427 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
1428 { 0 }
1429 };
1430
1431 static const CGEN_OPERAND_INSTANCE fmt_stm0_ops[] = {
1432 { INPUT, "reglist_low_st", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW_ST), 0, 0 },
1433 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1434 { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, COND_REF },
1435 { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, COND_REF },
1436 { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, COND_REF },
1437 { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, COND_REF },
1438 { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, COND_REF },
1439 { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, COND_REF },
1440 { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, COND_REF },
1441 { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
1442 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1443 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1444 { 0 }
1445 };
1446
1447 static const CGEN_OPERAND_INSTANCE fmt_stm1_ops[] = {
1448 { INPUT, "reglist_hi_st", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_HI_ST), 0, 0 },
1449 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1450 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
1451 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, COND_REF },
1452 { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, COND_REF },
1453 { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, COND_REF },
1454 { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, COND_REF },
1455 { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, COND_REF },
1456 { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, COND_REF },
1457 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1458 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1459 { 0 }
1460 };
1461
1462 static const CGEN_OPERAND_INSTANCE fmt_enter_ops[] = {
1463 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1464 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1465 { INPUT, "u10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U10), 0, 0 },
1466 { OUTPUT, "h_memory_tmp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1467 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1468 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1469 { 0 }
1470 };
1471
1472 static const CGEN_OPERAND_INSTANCE fmt_leave_ops[] = {
1473 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1474 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1475 { INPUT, "h_memory_sub__VM_reg__VM_h_gr_15_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1476 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1477 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1478 { 0 }
1479 };
1480
1481 static const CGEN_OPERAND_INSTANCE fmt_xchb_ops[] = {
1482 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1483 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1484 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
1485 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1486 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
1487 { 0 }
1488 };
1489
1490 #undef INPUT
1491 #undef OUTPUT
1492 #undef COND_REF
1493
1494 /* Instruction formats. */
1495
1496 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
1497
1498 static const CGEN_IFMT fmt_add = {
1499 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1500 };
1501
1502 static const CGEN_IFMT fmt_addi = {
1503 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1504 };
1505
1506 static const CGEN_IFMT fmt_add2 = {
1507 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1508 };
1509
1510 static const CGEN_IFMT fmt_addc = {
1511 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1512 };
1513
1514 static const CGEN_IFMT fmt_addn = {
1515 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1516 };
1517
1518 static const CGEN_IFMT fmt_addni = {
1519 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1520 };
1521
1522 static const CGEN_IFMT fmt_addn2 = {
1523 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1524 };
1525
1526 static const CGEN_IFMT fmt_cmp = {
1527 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1528 };
1529
1530 static const CGEN_IFMT fmt_cmpi = {
1531 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1532 };
1533
1534 static const CGEN_IFMT fmt_cmp2 = {
1535 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1536 };
1537
1538 static const CGEN_IFMT fmt_and = {
1539 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1540 };
1541
1542 static const CGEN_IFMT fmt_andm = {
1543 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1544 };
1545
1546 static const CGEN_IFMT fmt_andh = {
1547 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1548 };
1549
1550 static const CGEN_IFMT fmt_andb = {
1551 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1552 };
1553
1554 static const CGEN_IFMT fmt_bandl = {
1555 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1556 };
1557
1558 static const CGEN_IFMT fmt_btstl = {
1559 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1560 };
1561
1562 static const CGEN_IFMT fmt_mul = {
1563 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1564 };
1565
1566 static const CGEN_IFMT fmt_mulu = {
1567 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1568 };
1569
1570 static const CGEN_IFMT fmt_mulh = {
1571 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1572 };
1573
1574 static const CGEN_IFMT fmt_div0s = {
1575 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1576 };
1577
1578 static const CGEN_IFMT fmt_div0u = {
1579 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1580 };
1581
1582 static const CGEN_IFMT fmt_div1 = {
1583 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1584 };
1585
1586 static const CGEN_IFMT fmt_div2 = {
1587 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1588 };
1589
1590 static const CGEN_IFMT fmt_div3 = {
1591 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1592 };
1593
1594 static const CGEN_IFMT fmt_div4s = {
1595 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1596 };
1597
1598 static const CGEN_IFMT fmt_lsl = {
1599 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1600 };
1601
1602 static const CGEN_IFMT fmt_lsli = {
1603 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1604 };
1605
1606 static const CGEN_IFMT fmt_ldi8 = {
1607 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
1608 };
1609
1610 static const CGEN_IFMT fmt_ldi20 = {
1611 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
1612 };
1613
1614 static const CGEN_IFMT fmt_ldi32 = {
1615 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1616 };
1617
1618 static const CGEN_IFMT fmt_ld = {
1619 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1620 };
1621
1622 static const CGEN_IFMT fmt_lduh = {
1623 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1624 };
1625
1626 static const CGEN_IFMT fmt_ldub = {
1627 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1628 };
1629
1630 static const CGEN_IFMT fmt_ldr13 = {
1631 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1632 };
1633
1634 static const CGEN_IFMT fmt_ldr13uh = {
1635 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1636 };
1637
1638 static const CGEN_IFMT fmt_ldr13ub = {
1639 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1640 };
1641
1642 static const CGEN_IFMT fmt_ldr14 = {
1643 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1644 };
1645
1646 static const CGEN_IFMT fmt_ldr14uh = {
1647 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1648 };
1649
1650 static const CGEN_IFMT fmt_ldr14ub = {
1651 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1652 };
1653
1654 static const CGEN_IFMT fmt_ldr15 = {
1655 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1656 };
1657
1658 static const CGEN_IFMT fmt_ldr15gr = {
1659 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1660 };
1661
1662 static const CGEN_IFMT fmt_ldr15dr = {
1663 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1664 };
1665
1666 static const CGEN_IFMT fmt_ldr15ps = {
1667 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1668 };
1669
1670 static const CGEN_IFMT fmt_st = {
1671 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1672 };
1673
1674 static const CGEN_IFMT fmt_sth = {
1675 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1676 };
1677
1678 static const CGEN_IFMT fmt_stb = {
1679 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1680 };
1681
1682 static const CGEN_IFMT fmt_str13 = {
1683 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1684 };
1685
1686 static const CGEN_IFMT fmt_str13h = {
1687 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1688 };
1689
1690 static const CGEN_IFMT fmt_str13b = {
1691 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1692 };
1693
1694 static const CGEN_IFMT fmt_str14 = {
1695 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1696 };
1697
1698 static const CGEN_IFMT fmt_str14h = {
1699 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1700 };
1701
1702 static const CGEN_IFMT fmt_str14b = {
1703 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1704 };
1705
1706 static const CGEN_IFMT fmt_str15 = {
1707 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1708 };
1709
1710 static const CGEN_IFMT fmt_str15gr = {
1711 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1712 };
1713
1714 static const CGEN_IFMT fmt_str15dr = {
1715 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1716 };
1717
1718 static const CGEN_IFMT fmt_str15ps = {
1719 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1720 };
1721
1722 static const CGEN_IFMT fmt_mov = {
1723 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1724 };
1725
1726 static const CGEN_IFMT fmt_movdr = {
1727 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1728 };
1729
1730 static const CGEN_IFMT fmt_movps = {
1731 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1732 };
1733
1734 static const CGEN_IFMT fmt_mov2dr = {
1735 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1736 };
1737
1738 static const CGEN_IFMT fmt_mov2ps = {
1739 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1740 };
1741
1742 static const CGEN_IFMT fmt_jmp = {
1743 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1744 };
1745
1746 static const CGEN_IFMT fmt_callr = {
1747 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1748 };
1749
1750 static const CGEN_IFMT fmt_call = {
1751 16, 16, 0xf800, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
1752 };
1753
1754 static const CGEN_IFMT fmt_ret = {
1755 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1756 };
1757
1758 static const CGEN_IFMT fmt_int = {
1759 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1760 };
1761
1762 static const CGEN_IFMT fmt_inte = {
1763 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1764 };
1765
1766 static const CGEN_IFMT fmt_reti = {
1767 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1768 };
1769
1770 static const CGEN_IFMT fmt_brad = {
1771 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1772 };
1773
1774 static const CGEN_IFMT fmt_beqd = {
1775 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1776 };
1777
1778 static const CGEN_IFMT fmt_bcd = {
1779 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1780 };
1781
1782 static const CGEN_IFMT fmt_bnd = {
1783 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1784 };
1785
1786 static const CGEN_IFMT fmt_bvd = {
1787 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1788 };
1789
1790 static const CGEN_IFMT fmt_bltd = {
1791 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1792 };
1793
1794 static const CGEN_IFMT fmt_bled = {
1795 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1796 };
1797
1798 static const CGEN_IFMT fmt_blsd = {
1799 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1800 };
1801
1802 static const CGEN_IFMT fmt_dmovr13 = {
1803 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1804 };
1805
1806 static const CGEN_IFMT fmt_dmovr13h = {
1807 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1808 };
1809
1810 static const CGEN_IFMT fmt_dmovr13b = {
1811 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1812 };
1813
1814 static const CGEN_IFMT fmt_dmovr13pi = {
1815 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1816 };
1817
1818 static const CGEN_IFMT fmt_dmovr13pih = {
1819 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1820 };
1821
1822 static const CGEN_IFMT fmt_dmovr13pib = {
1823 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1824 };
1825
1826 static const CGEN_IFMT fmt_dmovr15pi = {
1827 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1828 };
1829
1830 static const CGEN_IFMT fmt_dmov2r13 = {
1831 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1832 };
1833
1834 static const CGEN_IFMT fmt_dmov2r13h = {
1835 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1836 };
1837
1838 static const CGEN_IFMT fmt_dmov2r13b = {
1839 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1840 };
1841
1842 static const CGEN_IFMT fmt_dmov2r13pi = {
1843 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1844 };
1845
1846 static const CGEN_IFMT fmt_dmov2r13pih = {
1847 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1848 };
1849
1850 static const CGEN_IFMT fmt_dmov2r13pib = {
1851 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1852 };
1853
1854 static const CGEN_IFMT fmt_dmov2r15pd = {
1855 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1856 };
1857
1858 static const CGEN_IFMT fmt_ldres = {
1859 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1860 };
1861
1862 static const CGEN_IFMT fmt_copop = {
1863 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
1864 };
1865
1866 static const CGEN_IFMT fmt_copld = {
1867 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
1868 };
1869
1870 static const CGEN_IFMT fmt_copst = {
1871 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
1872 };
1873
1874 static const CGEN_IFMT fmt_nop = {
1875 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1876 };
1877
1878 static const CGEN_IFMT fmt_andccr = {
1879 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1880 };
1881
1882 static const CGEN_IFMT fmt_stilm = {
1883 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1884 };
1885
1886 static const CGEN_IFMT fmt_addsp = {
1887 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
1888 };
1889
1890 static const CGEN_IFMT fmt_extsb = {
1891 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1892 };
1893
1894 static const CGEN_IFMT fmt_extub = {
1895 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1896 };
1897
1898 static const CGEN_IFMT fmt_extsh = {
1899 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1900 };
1901
1902 static const CGEN_IFMT fmt_extuh = {
1903 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1904 };
1905
1906 static const CGEN_IFMT fmt_ldm0 = {
1907 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_LD), 0 }
1908 };
1909
1910 static const CGEN_IFMT fmt_ldm1 = {
1911 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_LD), 0 }
1912 };
1913
1914 static const CGEN_IFMT fmt_stm0 = {
1915 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_ST), 0 }
1916 };
1917
1918 static const CGEN_IFMT fmt_stm1 = {
1919 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_ST), 0 }
1920 };
1921
1922 static const CGEN_IFMT fmt_enter = {
1923 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
1924 };
1925
1926 static const CGEN_IFMT fmt_leave = {
1927 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1928 };
1929
1930 static const CGEN_IFMT fmt_xchb = {
1931 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1932 };
1933
1934 #undef F
1935
1936 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1937 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1938 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1939
1940 /* The instruction table.
1941 This is currently non-static because the simulator accesses it
1942 directly. */
1943
1944 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
1945 {
1946 /* Special null first entry.
1947 A `num' value of zero is thus invalid.
1948 Also, the special `invalid' insn resides here. */
1949 { { 0 }, 0 },
1950 /* add $Rj,$Ri */
1951 {
1952 { 1, 1, 1, 1 },
1953 FR30_INSN_ADD, "add", "add",
1954 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1955 & fmt_add, { 0xa600 },
1956 (PTR) & fmt_add_ops[0],
1957 { 0, 0, { 0 } }
1958 },
1959 /* add $u4,$Ri */
1960 {
1961 { 1, 1, 1, 1 },
1962 FR30_INSN_ADDI, "addi", "add",
1963 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1964 & fmt_addi, { 0xa400 },
1965 (PTR) & fmt_addi_ops[0],
1966 { 0, 0, { 0 } }
1967 },
1968 /* add2 $m4,$Ri */
1969 {
1970 { 1, 1, 1, 1 },
1971 FR30_INSN_ADD2, "add2", "add2",
1972 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1973 & fmt_add2, { 0xa500 },
1974 (PTR) & fmt_add2_ops[0],
1975 { 0, 0, { 0 } }
1976 },
1977 /* addc $Rj,$Ri */
1978 {
1979 { 1, 1, 1, 1 },
1980 FR30_INSN_ADDC, "addc", "addc",
1981 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1982 & fmt_addc, { 0xa700 },
1983 (PTR) & fmt_addc_ops[0],
1984 { 0, 0, { 0 } }
1985 },
1986 /* addn $Rj,$Ri */
1987 {
1988 { 1, 1, 1, 1 },
1989 FR30_INSN_ADDN, "addn", "addn",
1990 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1991 & fmt_addn, { 0xa200 },
1992 (PTR) & fmt_addn_ops[0],
1993 { 0, 0, { 0 } }
1994 },
1995 /* addn $u4,$Ri */
1996 {
1997 { 1, 1, 1, 1 },
1998 FR30_INSN_ADDNI, "addni", "addn",
1999 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2000 & fmt_addni, { 0xa000 },
2001 (PTR) & fmt_addni_ops[0],
2002 { 0, 0, { 0 } }
2003 },
2004 /* addn2 $m4,$Ri */
2005 {
2006 { 1, 1, 1, 1 },
2007 FR30_INSN_ADDN2, "addn2", "addn2",
2008 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
2009 & fmt_addn2, { 0xa100 },
2010 (PTR) & fmt_addn2_ops[0],
2011 { 0, 0, { 0 } }
2012 },
2013 /* sub $Rj,$Ri */
2014 {
2015 { 1, 1, 1, 1 },
2016 FR30_INSN_SUB, "sub", "sub",
2017 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2018 & fmt_add, { 0xac00 },
2019 (PTR) & fmt_add_ops[0],
2020 { 0, 0, { 0 } }
2021 },
2022 /* subc $Rj,$Ri */
2023 {
2024 { 1, 1, 1, 1 },
2025 FR30_INSN_SUBC, "subc", "subc",
2026 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2027 & fmt_addc, { 0xad00 },
2028 (PTR) & fmt_addc_ops[0],
2029 { 0, 0, { 0 } }
2030 },
2031 /* subn $Rj,$Ri */
2032 {
2033 { 1, 1, 1, 1 },
2034 FR30_INSN_SUBN, "subn", "subn",
2035 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2036 & fmt_addn, { 0xae00 },
2037 (PTR) & fmt_addn_ops[0],
2038 { 0, 0, { 0 } }
2039 },
2040 /* cmp $Rj,$Ri */
2041 {
2042 { 1, 1, 1, 1 },
2043 FR30_INSN_CMP, "cmp", "cmp",
2044 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2045 & fmt_cmp, { 0xaa00 },
2046 (PTR) & fmt_cmp_ops[0],
2047 { 0, 0, { 0 } }
2048 },
2049 /* cmp $u4,$Ri */
2050 {
2051 { 1, 1, 1, 1 },
2052 FR30_INSN_CMPI, "cmpi", "cmp",
2053 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2054 & fmt_cmpi, { 0xa800 },
2055 (PTR) & fmt_cmpi_ops[0],
2056 { 0, 0, { 0 } }
2057 },
2058 /* cmp2 $m4,$Ri */
2059 {
2060 { 1, 1, 1, 1 },
2061 FR30_INSN_CMP2, "cmp2", "cmp2",
2062 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
2063 & fmt_cmp2, { 0xa900 },
2064 (PTR) & fmt_cmp2_ops[0],
2065 { 0, 0, { 0 } }
2066 },
2067 /* and $Rj,$Ri */
2068 {
2069 { 1, 1, 1, 1 },
2070 FR30_INSN_AND, "and", "and",
2071 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2072 & fmt_and, { 0x8200 },
2073 (PTR) & fmt_and_ops[0],
2074 { 0, 0, { 0 } }
2075 },
2076 /* or $Rj,$Ri */
2077 {
2078 { 1, 1, 1, 1 },
2079 FR30_INSN_OR, "or", "or",
2080 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2081 & fmt_and, { 0x9200 },
2082 (PTR) & fmt_and_ops[0],
2083 { 0, 0, { 0 } }
2084 },
2085 /* eor $Rj,$Ri */
2086 {
2087 { 1, 1, 1, 1 },
2088 FR30_INSN_EOR, "eor", "eor",
2089 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2090 & fmt_and, { 0x9a00 },
2091 (PTR) & fmt_and_ops[0],
2092 { 0, 0, { 0 } }
2093 },
2094 /* and $Rj,@$Ri */
2095 {
2096 { 1, 1, 1, 1 },
2097 FR30_INSN_ANDM, "andm", "and",
2098 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2099 & fmt_andm, { 0x8400 },
2100 (PTR) & fmt_andm_ops[0],
2101 { 0, 0, { 0 } }
2102 },
2103 /* andh $Rj,@$Ri */
2104 {
2105 { 1, 1, 1, 1 },
2106 FR30_INSN_ANDH, "andh", "andh",
2107 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2108 & fmt_andh, { 0x8500 },
2109 (PTR) & fmt_andh_ops[0],
2110 { 0, 0, { 0 } }
2111 },
2112 /* andb $Rj,@$Ri */
2113 {
2114 { 1, 1, 1, 1 },
2115 FR30_INSN_ANDB, "andb", "andb",
2116 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2117 & fmt_andb, { 0x8600 },
2118 (PTR) & fmt_andb_ops[0],
2119 { 0, 0, { 0 } }
2120 },
2121 /* or $Rj,@$Ri */
2122 {
2123 { 1, 1, 1, 1 },
2124 FR30_INSN_ORM, "orm", "or",
2125 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2126 & fmt_andm, { 0x9400 },
2127 (PTR) & fmt_andm_ops[0],
2128 { 0, 0, { 0 } }
2129 },
2130 /* orh $Rj,@$Ri */
2131 {
2132 { 1, 1, 1, 1 },
2133 FR30_INSN_ORH, "orh", "orh",
2134 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2135 & fmt_andh, { 0x9500 },
2136 (PTR) & fmt_andh_ops[0],
2137 { 0, 0, { 0 } }
2138 },
2139 /* orb $Rj,@$Ri */
2140 {
2141 { 1, 1, 1, 1 },
2142 FR30_INSN_ORB, "orb", "orb",
2143 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2144 & fmt_andb, { 0x9600 },
2145 (PTR) & fmt_andb_ops[0],
2146 { 0, 0, { 0 } }
2147 },
2148 /* eor $Rj,@$Ri */
2149 {
2150 { 1, 1, 1, 1 },
2151 FR30_INSN_EORM, "eorm", "eor",
2152 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2153 & fmt_andm, { 0x9c00 },
2154 (PTR) & fmt_andm_ops[0],
2155 { 0, 0, { 0 } }
2156 },
2157 /* eorh $Rj,@$Ri */
2158 {
2159 { 1, 1, 1, 1 },
2160 FR30_INSN_EORH, "eorh", "eorh",
2161 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2162 & fmt_andh, { 0x9d00 },
2163 (PTR) & fmt_andh_ops[0],
2164 { 0, 0, { 0 } }
2165 },
2166 /* eorb $Rj,@$Ri */
2167 {
2168 { 1, 1, 1, 1 },
2169 FR30_INSN_EORB, "eorb", "eorb",
2170 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2171 & fmt_andb, { 0x9e00 },
2172 (PTR) & fmt_andb_ops[0],
2173 { 0, 0, { 0 } }
2174 },
2175 /* bandl $u4,@$Ri */
2176 {
2177 { 1, 1, 1, 1 },
2178 FR30_INSN_BANDL, "bandl", "bandl",
2179 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2180 & fmt_bandl, { 0x8000 },
2181 (PTR) & fmt_bandl_ops[0],
2182 { 0, 0, { 0 } }
2183 },
2184 /* borl $u4,@$Ri */
2185 {
2186 { 1, 1, 1, 1 },
2187 FR30_INSN_BORL, "borl", "borl",
2188 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2189 & fmt_bandl, { 0x9000 },
2190 (PTR) & fmt_bandl_ops[0],
2191 { 0, 0, { 0 } }
2192 },
2193 /* beorl $u4,@$Ri */
2194 {
2195 { 1, 1, 1, 1 },
2196 FR30_INSN_BEORL, "beorl", "beorl",
2197 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2198 & fmt_bandl, { 0x9800 },
2199 (PTR) & fmt_bandl_ops[0],
2200 { 0, 0, { 0 } }
2201 },
2202 /* bandh $u4,@$Ri */
2203 {
2204 { 1, 1, 1, 1 },
2205 FR30_INSN_BANDH, "bandh", "bandh",
2206 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2207 & fmt_bandl, { 0x8100 },
2208 (PTR) & fmt_bandl_ops[0],
2209 { 0, 0, { 0 } }
2210 },
2211 /* borh $u4,@$Ri */
2212 {
2213 { 1, 1, 1, 1 },
2214 FR30_INSN_BORH, "borh", "borh",
2215 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2216 & fmt_bandl, { 0x9100 },
2217 (PTR) & fmt_bandl_ops[0],
2218 { 0, 0, { 0 } }
2219 },
2220 /* beorh $u4,@$Ri */
2221 {
2222 { 1, 1, 1, 1 },
2223 FR30_INSN_BEORH, "beorh", "beorh",
2224 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2225 & fmt_bandl, { 0x9900 },
2226 (PTR) & fmt_bandl_ops[0],
2227 { 0, 0, { 0 } }
2228 },
2229 /* btstl $u4,@$Ri */
2230 {
2231 { 1, 1, 1, 1 },
2232 FR30_INSN_BTSTL, "btstl", "btstl",
2233 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2234 & fmt_btstl, { 0x8800 },
2235 (PTR) & fmt_btstl_ops[0],
2236 { 0, 0, { 0 } }
2237 },
2238 /* btsth $u4,@$Ri */
2239 {
2240 { 1, 1, 1, 1 },
2241 FR30_INSN_BTSTH, "btsth", "btsth",
2242 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2243 & fmt_btstl, { 0x8900 },
2244 (PTR) & fmt_btstl_ops[0],
2245 { 0, 0, { 0 } }
2246 },
2247 /* mul $Rj,$Ri */
2248 {
2249 { 1, 1, 1, 1 },
2250 FR30_INSN_MUL, "mul", "mul",
2251 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2252 & fmt_mul, { 0xaf00 },
2253 (PTR) & fmt_mul_ops[0],
2254 { 0, 0, { 0 } }
2255 },
2256 /* mulu $Rj,$Ri */
2257 {
2258 { 1, 1, 1, 1 },
2259 FR30_INSN_MULU, "mulu", "mulu",
2260 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2261 & fmt_mulu, { 0xab00 },
2262 (PTR) & fmt_mulu_ops[0],
2263 { 0, 0, { 0 } }
2264 },
2265 /* mulh $Rj,$Ri */
2266 {
2267 { 1, 1, 1, 1 },
2268 FR30_INSN_MULH, "mulh", "mulh",
2269 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2270 & fmt_mulh, { 0xbf00 },
2271 (PTR) & fmt_mulh_ops[0],
2272 { 0, 0, { 0 } }
2273 },
2274 /* muluh $Rj,$Ri */
2275 {
2276 { 1, 1, 1, 1 },
2277 FR30_INSN_MULUH, "muluh", "muluh",
2278 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2279 & fmt_mulh, { 0xbb00 },
2280 (PTR) & fmt_mulh_ops[0],
2281 { 0, 0, { 0 } }
2282 },
2283 /* div0s $Ri */
2284 {
2285 { 1, 1, 1, 1 },
2286 FR30_INSN_DIV0S, "div0s", "div0s",
2287 { { MNEM, ' ', OP (RI), 0 } },
2288 & fmt_div0s, { 0x9740 },
2289 (PTR) & fmt_div0s_ops[0],
2290 { 0, 0, { 0 } }
2291 },
2292 /* div0u $Ri */
2293 {
2294 { 1, 1, 1, 1 },
2295 FR30_INSN_DIV0U, "div0u", "div0u",
2296 { { MNEM, ' ', OP (RI), 0 } },
2297 & fmt_div0u, { 0x9750 },
2298 (PTR) & fmt_div0u_ops[0],
2299 { 0, 0, { 0 } }
2300 },
2301 /* div1 $Ri */
2302 {
2303 { 1, 1, 1, 1 },
2304 FR30_INSN_DIV1, "div1", "div1",
2305 { { MNEM, ' ', OP (RI), 0 } },
2306 & fmt_div1, { 0x9760 },
2307 (PTR) & fmt_div1_ops[0],
2308 { 0, 0, { 0 } }
2309 },
2310 /* div2 $Ri */
2311 {
2312 { 1, 1, 1, 1 },
2313 FR30_INSN_DIV2, "div2", "div2",
2314 { { MNEM, ' ', OP (RI), 0 } },
2315 & fmt_div2, { 0x9770 },
2316 (PTR) & fmt_div2_ops[0],
2317 { 0, 0, { 0 } }
2318 },
2319 /* div3 */
2320 {
2321 { 1, 1, 1, 1 },
2322 FR30_INSN_DIV3, "div3", "div3",
2323 { { MNEM, 0 } },
2324 & fmt_div3, { 0x9f60 },
2325 (PTR) & fmt_div3_ops[0],
2326 { 0, 0, { 0 } }
2327 },
2328 /* div4s */
2329 {
2330 { 1, 1, 1, 1 },
2331 FR30_INSN_DIV4S, "div4s", "div4s",
2332 { { MNEM, 0 } },
2333 & fmt_div4s, { 0x9f70 },
2334 (PTR) & fmt_div4s_ops[0],
2335 { 0, 0, { 0 } }
2336 },
2337 /* lsl $Rj,$Ri */
2338 {
2339 { 1, 1, 1, 1 },
2340 FR30_INSN_LSL, "lsl", "lsl",
2341 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2342 & fmt_lsl, { 0xb600 },
2343 (PTR) & fmt_lsl_ops[0],
2344 { 0, 0, { 0 } }
2345 },
2346 /* lsl $u4,$Ri */
2347 {
2348 { 1, 1, 1, 1 },
2349 FR30_INSN_LSLI, "lsli", "lsl",
2350 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2351 & fmt_lsli, { 0xb400 },
2352 (PTR) & fmt_lsli_ops[0],
2353 { 0, 0, { 0 } }
2354 },
2355 /* lsl2 $u4,$Ri */
2356 {
2357 { 1, 1, 1, 1 },
2358 FR30_INSN_LSL2, "lsl2", "lsl2",
2359 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2360 & fmt_lsli, { 0xb500 },
2361 (PTR) & fmt_lsli_ops[0],
2362 { 0, 0, { 0 } }
2363 },
2364 /* lsr $Rj,$Ri */
2365 {
2366 { 1, 1, 1, 1 },
2367 FR30_INSN_LSR, "lsr", "lsr",
2368 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2369 & fmt_lsl, { 0xb200 },
2370 (PTR) & fmt_lsl_ops[0],
2371 { 0, 0, { 0 } }
2372 },
2373 /* lsr $u4,$Ri */
2374 {
2375 { 1, 1, 1, 1 },
2376 FR30_INSN_LSRI, "lsri", "lsr",
2377 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2378 & fmt_lsli, { 0xb000 },
2379 (PTR) & fmt_lsli_ops[0],
2380 { 0, 0, { 0 } }
2381 },
2382 /* lsr2 $u4,$Ri */
2383 {
2384 { 1, 1, 1, 1 },
2385 FR30_INSN_LSR2, "lsr2", "lsr2",
2386 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2387 & fmt_lsli, { 0xb100 },
2388 (PTR) & fmt_lsli_ops[0],
2389 { 0, 0, { 0 } }
2390 },
2391 /* asr $Rj,$Ri */
2392 {
2393 { 1, 1, 1, 1 },
2394 FR30_INSN_ASR, "asr", "asr",
2395 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2396 & fmt_lsl, { 0xba00 },
2397 (PTR) & fmt_lsl_ops[0],
2398 { 0, 0, { 0 } }
2399 },
2400 /* asr $u4,$Ri */
2401 {
2402 { 1, 1, 1, 1 },
2403 FR30_INSN_ASRI, "asri", "asr",
2404 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2405 & fmt_lsli, { 0xb800 },
2406 (PTR) & fmt_lsli_ops[0],
2407 { 0, 0, { 0 } }
2408 },
2409 /* asr2 $u4,$Ri */
2410 {
2411 { 1, 1, 1, 1 },
2412 FR30_INSN_ASR2, "asr2", "asr2",
2413 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2414 & fmt_lsli, { 0xb900 },
2415 (PTR) & fmt_lsli_ops[0],
2416 { 0, 0, { 0 } }
2417 },
2418 /* ldi:8 $i8,$Ri */
2419 {
2420 { 1, 1, 1, 1 },
2421 FR30_INSN_LDI8, "ldi8", "ldi:8",
2422 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
2423 & fmt_ldi8, { 0xc000 },
2424 (PTR) & fmt_ldi8_ops[0],
2425 { 0, 0, { 0 } }
2426 },
2427 /* ldi:20 $i20,$Ri */
2428 {
2429 { 1, 1, 1, 1 },
2430 FR30_INSN_LDI20, "ldi20", "ldi:20",
2431 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
2432 & fmt_ldi20, { 0x9b00 },
2433 (PTR) & fmt_ldi20_ops[0],
2434 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
2435 },
2436 /* ldi:32 $i32,$Ri */
2437 {
2438 { 1, 1, 1, 1 },
2439 FR30_INSN_LDI32, "ldi32", "ldi:32",
2440 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2441 & fmt_ldi32, { 0x9f80 },
2442 (PTR) & fmt_ldi32_ops[0],
2443 { 0, 0, { 0 } }
2444 },
2445 /* ld @$Rj,$Ri */
2446 {
2447 { 1, 1, 1, 1 },
2448 FR30_INSN_LD, "ld", "ld",
2449 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2450 & fmt_ld, { 0x400 },
2451 (PTR) & fmt_ld_ops[0],
2452 { 0, 0, { 0 } }
2453 },
2454 /* lduh @$Rj,$Ri */
2455 {
2456 { 1, 1, 1, 1 },
2457 FR30_INSN_LDUH, "lduh", "lduh",
2458 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2459 & fmt_lduh, { 0x500 },
2460 (PTR) & fmt_lduh_ops[0],
2461 { 0, 0, { 0 } }
2462 },
2463 /* ldub @$Rj,$Ri */
2464 {
2465 { 1, 1, 1, 1 },
2466 FR30_INSN_LDUB, "ldub", "ldub",
2467 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2468 & fmt_ldub, { 0x600 },
2469 (PTR) & fmt_ldub_ops[0],
2470 { 0, 0, { 0 } }
2471 },
2472 /* ld @($R13,$Rj),$Ri */
2473 {
2474 { 1, 1, 1, 1 },
2475 FR30_INSN_LDR13, "ldr13", "ld",
2476 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2477 & fmt_ldr13, { 0x0 },
2478 (PTR) & fmt_ldr13_ops[0],
2479 { 0, 0, { 0 } }
2480 },
2481 /* lduh @($R13,$Rj),$Ri */
2482 {
2483 { 1, 1, 1, 1 },
2484 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
2485 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2486 & fmt_ldr13uh, { 0x100 },
2487 (PTR) & fmt_ldr13uh_ops[0],
2488 { 0, 0, { 0 } }
2489 },
2490 /* ldub @($R13,$Rj),$Ri */
2491 {
2492 { 1, 1, 1, 1 },
2493 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
2494 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2495 & fmt_ldr13ub, { 0x200 },
2496 (PTR) & fmt_ldr13ub_ops[0],
2497 { 0, 0, { 0 } }
2498 },
2499 /* ld @($R14,$disp10),$Ri */
2500 {
2501 { 1, 1, 1, 1 },
2502 FR30_INSN_LDR14, "ldr14", "ld",
2503 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
2504 & fmt_ldr14, { 0x2000 },
2505 (PTR) & fmt_ldr14_ops[0],
2506 { 0, 0, { 0 } }
2507 },
2508 /* lduh @($R14,$disp9),$Ri */
2509 {
2510 { 1, 1, 1, 1 },
2511 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
2512 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
2513 & fmt_ldr14uh, { 0x4000 },
2514 (PTR) & fmt_ldr14uh_ops[0],
2515 { 0, 0, { 0 } }
2516 },
2517 /* ldub @($R14,$disp8),$Ri */
2518 {
2519 { 1, 1, 1, 1 },
2520 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
2521 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
2522 & fmt_ldr14ub, { 0x6000 },
2523 (PTR) & fmt_ldr14ub_ops[0],
2524 { 0, 0, { 0 } }
2525 },
2526 /* ld @($R15,$udisp6),$Ri */
2527 {
2528 { 1, 1, 1, 1 },
2529 FR30_INSN_LDR15, "ldr15", "ld",
2530 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
2531 & fmt_ldr15, { 0x300 },
2532 (PTR) & fmt_ldr15_ops[0],
2533 { 0, 0, { 0 } }
2534 },
2535 /* ld @$R15+,$Ri */
2536 {
2537 { 1, 1, 1, 1 },
2538 FR30_INSN_LDR15GR, "ldr15gr", "ld",
2539 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
2540 & fmt_ldr15gr, { 0x700 },
2541 (PTR) & fmt_ldr15gr_ops[0],
2542 { 0, 0, { 0 } }
2543 },
2544 /* ld @$R15+,$Rs2 */
2545 {
2546 { 1, 1, 1, 1 },
2547 FR30_INSN_LDR15DR, "ldr15dr", "ld",
2548 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
2549 & fmt_ldr15dr, { 0x780 },
2550 (PTR) & fmt_ldr15dr_ops[0],
2551 { 0, 0, { 0 } }
2552 },
2553 /* ld @$R15+,$ps */
2554 {
2555 { 1, 1, 1, 1 },
2556 FR30_INSN_LDR15PS, "ldr15ps", "ld",
2557 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
2558 & fmt_ldr15ps, { 0x790 },
2559 (PTR) & fmt_ldr15ps_ops[0],
2560 { 0, 0, { 0 } }
2561 },
2562 /* st $Ri,@$Rj */
2563 {
2564 { 1, 1, 1, 1 },
2565 FR30_INSN_ST, "st", "st",
2566 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2567 & fmt_st, { 0x1400 },
2568 (PTR) & fmt_st_ops[0],
2569 { 0, 0, { 0 } }
2570 },
2571 /* sth $Ri,@$Rj */
2572 {
2573 { 1, 1, 1, 1 },
2574 FR30_INSN_STH, "sth", "sth",
2575 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2576 & fmt_sth, { 0x1500 },
2577 (PTR) & fmt_sth_ops[0],
2578 { 0, 0, { 0 } }
2579 },
2580 /* stb $Ri,@$Rj */
2581 {
2582 { 1, 1, 1, 1 },
2583 FR30_INSN_STB, "stb", "stb",
2584 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2585 & fmt_stb, { 0x1600 },
2586 (PTR) & fmt_stb_ops[0],
2587 { 0, 0, { 0 } }
2588 },
2589 /* st $Ri,@($R13,$Rj) */
2590 {
2591 { 1, 1, 1, 1 },
2592 FR30_INSN_STR13, "str13", "st",
2593 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2594 & fmt_str13, { 0x1000 },
2595 (PTR) & fmt_str13_ops[0],
2596 { 0, 0, { 0 } }
2597 },
2598 /* sth $Ri,@($R13,$Rj) */
2599 {
2600 { 1, 1, 1, 1 },
2601 FR30_INSN_STR13H, "str13h", "sth",
2602 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2603 & fmt_str13h, { 0x1100 },
2604 (PTR) & fmt_str13h_ops[0],
2605 { 0, 0, { 0 } }
2606 },
2607 /* stb $Ri,@($R13,$Rj) */
2608 {
2609 { 1, 1, 1, 1 },
2610 FR30_INSN_STR13B, "str13b", "stb",
2611 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2612 & fmt_str13b, { 0x1200 },
2613 (PTR) & fmt_str13b_ops[0],
2614 { 0, 0, { 0 } }
2615 },
2616 /* st $Ri,@($R14,$disp10) */
2617 {
2618 { 1, 1, 1, 1 },
2619 FR30_INSN_STR14, "str14", "st",
2620 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
2621 & fmt_str14, { 0x3000 },
2622 (PTR) & fmt_str14_ops[0],
2623 { 0, 0, { 0 } }
2624 },
2625 /* sth $Ri,@($R14,$disp9) */
2626 {
2627 { 1, 1, 1, 1 },
2628 FR30_INSN_STR14H, "str14h", "sth",
2629 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
2630 & fmt_str14h, { 0x5000 },
2631 (PTR) & fmt_str14h_ops[0],
2632 { 0, 0, { 0 } }
2633 },
2634 /* stb $Ri,@($R14,$disp8) */
2635 {
2636 { 1, 1, 1, 1 },
2637 FR30_INSN_STR14B, "str14b", "stb",
2638 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
2639 & fmt_str14b, { 0x7000 },
2640 (PTR) & fmt_str14b_ops[0],
2641 { 0, 0, { 0 } }
2642 },
2643 /* st $Ri,@($R15,$udisp6) */
2644 {
2645 { 1, 1, 1, 1 },
2646 FR30_INSN_STR15, "str15", "st",
2647 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
2648 & fmt_str15, { 0x1300 },
2649 (PTR) & fmt_str15_ops[0],
2650 { 0, 0, { 0 } }
2651 },
2652 /* st $Ri,@-$R15 */
2653 {
2654 { 1, 1, 1, 1 },
2655 FR30_INSN_STR15GR, "str15gr", "st",
2656 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
2657 & fmt_str15gr, { 0x1700 },
2658 (PTR) & fmt_str15gr_ops[0],
2659 { 0, 0, { 0 } }
2660 },
2661 /* st $Rs2,@-$R15 */
2662 {
2663 { 1, 1, 1, 1 },
2664 FR30_INSN_STR15DR, "str15dr", "st",
2665 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
2666 & fmt_str15dr, { 0x1780 },
2667 (PTR) & fmt_str15dr_ops[0],
2668 { 0, 0, { 0 } }
2669 },
2670 /* st $ps,@-$R15 */
2671 {
2672 { 1, 1, 1, 1 },
2673 FR30_INSN_STR15PS, "str15ps", "st",
2674 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
2675 & fmt_str15ps, { 0x1790 },
2676 (PTR) & fmt_str15ps_ops[0],
2677 { 0, 0, { 0 } }
2678 },
2679 /* mov $Rj,$Ri */
2680 {
2681 { 1, 1, 1, 1 },
2682 FR30_INSN_MOV, "mov", "mov",
2683 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2684 & fmt_mov, { 0x8b00 },
2685 (PTR) & fmt_mov_ops[0],
2686 { 0, 0, { 0 } }
2687 },
2688 /* mov $Rs1,$Ri */
2689 {
2690 { 1, 1, 1, 1 },
2691 FR30_INSN_MOVDR, "movdr", "mov",
2692 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
2693 & fmt_movdr, { 0xb700 },
2694 (PTR) & fmt_movdr_ops[0],
2695 { 0, 0, { 0 } }
2696 },
2697 /* mov $ps,$Ri */
2698 {
2699 { 1, 1, 1, 1 },
2700 FR30_INSN_MOVPS, "movps", "mov",
2701 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
2702 & fmt_movps, { 0x1710 },
2703 (PTR) & fmt_movps_ops[0],
2704 { 0, 0, { 0 } }
2705 },
2706 /* mov $Ri,$Rs1 */
2707 {
2708 { 1, 1, 1, 1 },
2709 FR30_INSN_MOV2DR, "mov2dr", "mov",
2710 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
2711 & fmt_mov2dr, { 0xb300 },
2712 (PTR) & fmt_mov2dr_ops[0],
2713 { 0, 0, { 0 } }
2714 },
2715 /* mov $Ri,$ps */
2716 {
2717 { 1, 1, 1, 1 },
2718 FR30_INSN_MOV2PS, "mov2ps", "mov",
2719 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
2720 & fmt_mov2ps, { 0x710 },
2721 (PTR) & fmt_mov2ps_ops[0],
2722 { 0, 0, { 0 } }
2723 },
2724 /* jmp @$Ri */
2725 {
2726 { 1, 1, 1, 1 },
2727 FR30_INSN_JMP, "jmp", "jmp",
2728 { { MNEM, ' ', '@', OP (RI), 0 } },
2729 & fmt_jmp, { 0x9700 },
2730 (PTR) & fmt_jmp_ops[0],
2731 { 0, 0|A(UNCOND_CTI), { 0 } }
2732 },
2733 /* jmp:d @$Ri */
2734 {
2735 { 1, 1, 1, 1 },
2736 FR30_INSN_JMPD, "jmpd", "jmp:d",
2737 { { MNEM, ' ', '@', OP (RI), 0 } },
2738 & fmt_jmp, { 0x9f00 },
2739 (PTR) & fmt_jmp_ops[0],
2740 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2741 },
2742 /* call @$Ri */
2743 {
2744 { 1, 1, 1, 1 },
2745 FR30_INSN_CALLR, "callr", "call",
2746 { { MNEM, ' ', '@', OP (RI), 0 } },
2747 & fmt_callr, { 0x9710 },
2748 (PTR) & fmt_callr_ops[0],
2749 { 0, 0|A(UNCOND_CTI), { 0 } }
2750 },
2751 /* call:d @$Ri */
2752 {
2753 { 1, 1, 1, 1 },
2754 FR30_INSN_CALLRD, "callrd", "call:d",
2755 { { MNEM, ' ', '@', OP (RI), 0 } },
2756 & fmt_callr, { 0x9f10 },
2757 (PTR) & fmt_callr_ops[0],
2758 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2759 },
2760 /* call $label12 */
2761 {
2762 { 1, 1, 1, 1 },
2763 FR30_INSN_CALL, "call", "call",
2764 { { MNEM, ' ', OP (LABEL12), 0 } },
2765 & fmt_call, { 0xd000 },
2766 (PTR) & fmt_call_ops[0],
2767 { 0, 0|A(UNCOND_CTI), { 0 } }
2768 },
2769 /* call:d $label12 */
2770 {
2771 { 1, 1, 1, 1 },
2772 FR30_INSN_CALLD, "calld", "call:d",
2773 { { MNEM, ' ', OP (LABEL12), 0 } },
2774 & fmt_call, { 0xd800 },
2775 (PTR) & fmt_call_ops[0],
2776 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2777 },
2778 /* ret */
2779 {
2780 { 1, 1, 1, 1 },
2781 FR30_INSN_RET, "ret", "ret",
2782 { { MNEM, 0 } },
2783 & fmt_ret, { 0x9720 },
2784 (PTR) & fmt_ret_ops[0],
2785 { 0, 0|A(UNCOND_CTI), { 0 } }
2786 },
2787 /* ret:d */
2788 {
2789 { 1, 1, 1, 1 },
2790 FR30_INSN_RET_D, "ret:d", "ret:d",
2791 { { MNEM, 0 } },
2792 & fmt_ret, { 0x9f20 },
2793 (PTR) & fmt_ret_ops[0],
2794 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2795 },
2796 /* int $u8 */
2797 {
2798 { 1, 1, 1, 1 },
2799 FR30_INSN_INT, "int", "int",
2800 { { MNEM, ' ', OP (U8), 0 } },
2801 & fmt_int, { 0x1f00 },
2802 (PTR) & fmt_int_ops[0],
2803 { 0, 0|A(UNCOND_CTI), { 0 } }
2804 },
2805 /* inte */
2806 {
2807 { 1, 1, 1, 1 },
2808 FR30_INSN_INTE, "inte", "inte",
2809 { { MNEM, 0 } },
2810 & fmt_inte, { 0x9f30 },
2811 (PTR) & fmt_inte_ops[0],
2812 { 0, 0|A(UNCOND_CTI), { 0 } }
2813 },
2814 /* reti */
2815 {
2816 { 1, 1, 1, 1 },
2817 FR30_INSN_RETI, "reti", "reti",
2818 { { MNEM, 0 } },
2819 & fmt_reti, { 0x9730 },
2820 (PTR) & fmt_reti_ops[0],
2821 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2822 },
2823 /* bra:d $label9 */
2824 {
2825 { 1, 1, 1, 1 },
2826 FR30_INSN_BRAD, "brad", "bra:d",
2827 { { MNEM, ' ', OP (LABEL9), 0 } },
2828 & fmt_brad, { 0xf000 },
2829 (PTR) & fmt_brad_ops[0],
2830 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2831 },
2832 /* bra $label9 */
2833 {
2834 { 1, 1, 1, 1 },
2835 FR30_INSN_BRA, "bra", "bra",
2836 { { MNEM, ' ', OP (LABEL9), 0 } },
2837 & fmt_brad, { 0xe000 },
2838 (PTR) & fmt_brad_ops[0],
2839 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2840 },
2841 /* bno:d $label9 */
2842 {
2843 { 1, 1, 1, 1 },
2844 FR30_INSN_BNOD, "bnod", "bno:d",
2845 { { MNEM, ' ', OP (LABEL9), 0 } },
2846 & fmt_brad, { 0xf100 },
2847 (PTR) & fmt_brad_ops[0],
2848 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2849 },
2850 /* bno $label9 */
2851 {
2852 { 1, 1, 1, 1 },
2853 FR30_INSN_BNO, "bno", "bno",
2854 { { MNEM, ' ', OP (LABEL9), 0 } },
2855 & fmt_brad, { 0xe100 },
2856 (PTR) & fmt_brad_ops[0],
2857 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2858 },
2859 /* beq:d $label9 */
2860 {
2861 { 1, 1, 1, 1 },
2862 FR30_INSN_BEQD, "beqd", "beq:d",
2863 { { MNEM, ' ', OP (LABEL9), 0 } },
2864 & fmt_beqd, { 0xf200 },
2865 (PTR) & fmt_beqd_ops[0],
2866 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2867 },
2868 /* beq $label9 */
2869 {
2870 { 1, 1, 1, 1 },
2871 FR30_INSN_BEQ, "beq", "beq",
2872 { { MNEM, ' ', OP (LABEL9), 0 } },
2873 & fmt_beqd, { 0xe200 },
2874 (PTR) & fmt_beqd_ops[0],
2875 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2876 },
2877 /* bne:d $label9 */
2878 {
2879 { 1, 1, 1, 1 },
2880 FR30_INSN_BNED, "bned", "bne:d",
2881 { { MNEM, ' ', OP (LABEL9), 0 } },
2882 & fmt_beqd, { 0xf300 },
2883 (PTR) & fmt_beqd_ops[0],
2884 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2885 },
2886 /* bne $label9 */
2887 {
2888 { 1, 1, 1, 1 },
2889 FR30_INSN_BNE, "bne", "bne",
2890 { { MNEM, ' ', OP (LABEL9), 0 } },
2891 & fmt_beqd, { 0xe300 },
2892 (PTR) & fmt_beqd_ops[0],
2893 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2894 },
2895 /* bc:d $label9 */
2896 {
2897 { 1, 1, 1, 1 },
2898 FR30_INSN_BCD, "bcd", "bc:d",
2899 { { MNEM, ' ', OP (LABEL9), 0 } },
2900 & fmt_bcd, { 0xf400 },
2901 (PTR) & fmt_bcd_ops[0],
2902 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2903 },
2904 /* bc $label9 */
2905 {
2906 { 1, 1, 1, 1 },
2907 FR30_INSN_BC, "bc", "bc",
2908 { { MNEM, ' ', OP (LABEL9), 0 } },
2909 & fmt_bcd, { 0xe400 },
2910 (PTR) & fmt_bcd_ops[0],
2911 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2912 },
2913 /* bnc:d $label9 */
2914 {
2915 { 1, 1, 1, 1 },
2916 FR30_INSN_BNCD, "bncd", "bnc:d",
2917 { { MNEM, ' ', OP (LABEL9), 0 } },
2918 & fmt_bcd, { 0xf500 },
2919 (PTR) & fmt_bcd_ops[0],
2920 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2921 },
2922 /* bnc $label9 */
2923 {
2924 { 1, 1, 1, 1 },
2925 FR30_INSN_BNC, "bnc", "bnc",
2926 { { MNEM, ' ', OP (LABEL9), 0 } },
2927 & fmt_bcd, { 0xe500 },
2928 (PTR) & fmt_bcd_ops[0],
2929 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2930 },
2931 /* bn:d $label9 */
2932 {
2933 { 1, 1, 1, 1 },
2934 FR30_INSN_BND, "bnd", "bn:d",
2935 { { MNEM, ' ', OP (LABEL9), 0 } },
2936 & fmt_bnd, { 0xf600 },
2937 (PTR) & fmt_bnd_ops[0],
2938 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2939 },
2940 /* bn $label9 */
2941 {
2942 { 1, 1, 1, 1 },
2943 FR30_INSN_BN, "bn", "bn",
2944 { { MNEM, ' ', OP (LABEL9), 0 } },
2945 & fmt_bnd, { 0xe600 },
2946 (PTR) & fmt_bnd_ops[0],
2947 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2948 },
2949 /* bp:d $label9 */
2950 {
2951 { 1, 1, 1, 1 },
2952 FR30_INSN_BPD, "bpd", "bp:d",
2953 { { MNEM, ' ', OP (LABEL9), 0 } },
2954 & fmt_bnd, { 0xf700 },
2955 (PTR) & fmt_bnd_ops[0],
2956 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2957 },
2958 /* bp $label9 */
2959 {
2960 { 1, 1, 1, 1 },
2961 FR30_INSN_BP, "bp", "bp",
2962 { { MNEM, ' ', OP (LABEL9), 0 } },
2963 & fmt_bnd, { 0xe700 },
2964 (PTR) & fmt_bnd_ops[0],
2965 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2966 },
2967 /* bv:d $label9 */
2968 {
2969 { 1, 1, 1, 1 },
2970 FR30_INSN_BVD, "bvd", "bv:d",
2971 { { MNEM, ' ', OP (LABEL9), 0 } },
2972 & fmt_bvd, { 0xf800 },
2973 (PTR) & fmt_bvd_ops[0],
2974 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2975 },
2976 /* bv $label9 */
2977 {
2978 { 1, 1, 1, 1 },
2979 FR30_INSN_BV, "bv", "bv",
2980 { { MNEM, ' ', OP (LABEL9), 0 } },
2981 & fmt_bvd, { 0xe800 },
2982 (PTR) & fmt_bvd_ops[0],
2983 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2984 },
2985 /* bnv:d $label9 */
2986 {
2987 { 1, 1, 1, 1 },
2988 FR30_INSN_BNVD, "bnvd", "bnv:d",
2989 { { MNEM, ' ', OP (LABEL9), 0 } },
2990 & fmt_bvd, { 0xf900 },
2991 (PTR) & fmt_bvd_ops[0],
2992 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2993 },
2994 /* bnv $label9 */
2995 {
2996 { 1, 1, 1, 1 },
2997 FR30_INSN_BNV, "bnv", "bnv",
2998 { { MNEM, ' ', OP (LABEL9), 0 } },
2999 & fmt_bvd, { 0xe900 },
3000 (PTR) & fmt_bvd_ops[0],
3001 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
3002 },
3003 /* blt:d $label9 */
3004 {
3005 { 1, 1, 1, 1 },
3006 FR30_INSN_BLTD, "bltd", "blt:d",
3007 { { MNEM, ' ', OP (LABEL9), 0 } },
3008 & fmt_bltd, { 0xfa00 },
3009 (PTR) & fmt_bltd_ops[0],
3010 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
3011 },
3012 /* blt $label9 */
3013 {
3014 { 1, 1, 1, 1 },
3015 FR30_INSN_BLT, "blt", "blt",
3016 { { MNEM, ' ', OP (LABEL9), 0 } },
3017 & fmt_bltd, { 0xea00 },
3018 (PTR) & fmt_bltd_ops[0],
3019 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
3020 },
3021 /* bge:d $label9 */
3022 {
3023 { 1, 1, 1, 1 },
3024 FR30_INSN_BGED, "bged", "bge:d",
3025 { { MNEM, ' ', OP (LABEL9), 0 } },
3026 & fmt_bltd, { 0xfb00 },
3027 (PTR) & fmt_bltd_ops[0],
3028 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
3029 },
3030 /* bge $label9 */
3031 {
3032 { 1, 1, 1, 1 },
3033 FR30_INSN_BGE, "bge", "bge",
3034 { { MNEM, ' ', OP (LABEL9), 0 } },
3035 & fmt_bltd, { 0xeb00 },
3036 (PTR) & fmt_bltd_ops[0],
3037 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
3038 },
3039 /* ble:d $label9 */
3040 {
3041 { 1, 1, 1, 1 },
3042 FR30_INSN_BLED, "bled", "ble:d",
3043 { { MNEM, ' ', OP (LABEL9), 0 } },
3044 & fmt_bled, { 0xfc00 },
3045 (PTR) & fmt_bled_ops[0],
3046 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
3047 },
3048 /* ble $label9 */
3049 {
3050 { 1, 1, 1, 1 },
3051 FR30_INSN_BLE, "ble", "ble",
3052 { { MNEM, ' ', OP (LABEL9), 0 } },
3053 & fmt_bled, { 0xec00 },
3054 (PTR) & fmt_bled_ops[0],
3055 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
3056 },
3057 /* bgt:d $label9 */
3058 {
3059 { 1, 1, 1, 1 },
3060 FR30_INSN_BGTD, "bgtd", "bgt:d",
3061 { { MNEM, ' ', OP (LABEL9), 0 } },
3062 & fmt_bled, { 0xfd00 },
3063 (PTR) & fmt_bled_ops[0],
3064 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
3065 },
3066 /* bgt $label9 */
3067 {
3068 { 1, 1, 1, 1 },
3069 FR30_INSN_BGT, "bgt", "bgt",
3070 { { MNEM, ' ', OP (LABEL9), 0 } },
3071 & fmt_bled, { 0xed00 },
3072 (PTR) & fmt_bled_ops[0],
3073 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
3074 },
3075 /* bls:d $label9 */
3076 {
3077 { 1, 1, 1, 1 },
3078 FR30_INSN_BLSD, "blsd", "bls:d",
3079 { { MNEM, ' ', OP (LABEL9), 0 } },
3080 & fmt_blsd, { 0xfe00 },
3081 (PTR) & fmt_blsd_ops[0],
3082 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
3083 },
3084 /* bls $label9 */
3085 {
3086 { 1, 1, 1, 1 },
3087 FR30_INSN_BLS, "bls", "bls",
3088 { { MNEM, ' ', OP (LABEL9), 0 } },
3089 & fmt_blsd, { 0xee00 },
3090 (PTR) & fmt_blsd_ops[0],
3091 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
3092 },
3093 /* bhi:d $label9 */
3094 {
3095 { 1, 1, 1, 1 },
3096 FR30_INSN_BHID, "bhid", "bhi:d",
3097 { { MNEM, ' ', OP (LABEL9), 0 } },
3098 & fmt_blsd, { 0xff00 },
3099 (PTR) & fmt_blsd_ops[0],
3100 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
3101 },
3102 /* bhi $label9 */
3103 {
3104 { 1, 1, 1, 1 },
3105 FR30_INSN_BHI, "bhi", "bhi",
3106 { { MNEM, ' ', OP (LABEL9), 0 } },
3107 & fmt_blsd, { 0xef00 },
3108 (PTR) & fmt_blsd_ops[0],
3109 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
3110 },
3111 /* dmov $R13,@$dir10 */
3112 {
3113 { 1, 1, 1, 1 },
3114 FR30_INSN_DMOVR13, "dmovr13", "dmov",
3115 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
3116 & fmt_dmovr13, { 0x1800 },
3117 (PTR) & fmt_dmovr13_ops[0],
3118 { 0, 0, { 0 } }
3119 },
3120 /* dmovh $R13,@$dir9 */
3121 {
3122 { 1, 1, 1, 1 },
3123 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
3124 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
3125 & fmt_dmovr13h, { 0x1900 },
3126 (PTR) & fmt_dmovr13h_ops[0],
3127 { 0, 0, { 0 } }
3128 },
3129 /* dmovb $R13,@$dir8 */
3130 {
3131 { 1, 1, 1, 1 },
3132 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
3133 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
3134 & fmt_dmovr13b, { 0x1a00 },
3135 (PTR) & fmt_dmovr13b_ops[0],
3136 { 0, 0, { 0 } }
3137 },
3138 /* dmov @$R13+,@$dir10 */
3139 {
3140 { 1, 1, 1, 1 },
3141 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
3142 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
3143 & fmt_dmovr13pi, { 0x1c00 },
3144 (PTR) & fmt_dmovr13pi_ops[0],
3145 { 0, 0, { 0 } }
3146 },
3147 /* dmovh @$R13+,@$dir9 */
3148 {
3149 { 1, 1, 1, 1 },
3150 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
3151 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
3152 & fmt_dmovr13pih, { 0x1d00 },
3153 (PTR) & fmt_dmovr13pih_ops[0],
3154 { 0, 0, { 0 } }
3155 },
3156 /* dmovb @$R13+,@$dir8 */
3157 {
3158 { 1, 1, 1, 1 },
3159 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
3160 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
3161 & fmt_dmovr13pib, { 0x1e00 },
3162 (PTR) & fmt_dmovr13pib_ops[0],
3163 { 0, 0, { 0 } }
3164 },
3165 /* dmov @$R15+,@$dir10 */
3166 {
3167 { 1, 1, 1, 1 },
3168 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
3169 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
3170 & fmt_dmovr15pi, { 0x1b00 },
3171 (PTR) & fmt_dmovr15pi_ops[0],
3172 { 0, 0, { 0 } }
3173 },
3174 /* dmov @$dir10,$R13 */
3175 {
3176 { 1, 1, 1, 1 },
3177 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
3178 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
3179 & fmt_dmov2r13, { 0x800 },
3180 (PTR) & fmt_dmov2r13_ops[0],
3181 { 0, 0, { 0 } }
3182 },
3183 /* dmovh @$dir9,$R13 */
3184 {
3185 { 1, 1, 1, 1 },
3186 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
3187 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
3188 & fmt_dmov2r13h, { 0x900 },
3189 (PTR) & fmt_dmov2r13h_ops[0],
3190 { 0, 0, { 0 } }
3191 },
3192 /* dmovb @$dir8,$R13 */
3193 {
3194 { 1, 1, 1, 1 },
3195 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
3196 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
3197 & fmt_dmov2r13b, { 0xa00 },
3198 (PTR) & fmt_dmov2r13b_ops[0],
3199 { 0, 0, { 0 } }
3200 },
3201 /* dmov @$dir10,@$R13+ */
3202 {
3203 { 1, 1, 1, 1 },
3204 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
3205 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
3206 & fmt_dmov2r13pi, { 0xc00 },
3207 (PTR) & fmt_dmov2r13pi_ops[0],
3208 { 0, 0, { 0 } }
3209 },
3210 /* dmovh @$dir9,@$R13+ */
3211 {
3212 { 1, 1, 1, 1 },
3213 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
3214 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
3215 & fmt_dmov2r13pih, { 0xd00 },
3216 (PTR) & fmt_dmov2r13pih_ops[0],
3217 { 0, 0, { 0 } }
3218 },
3219 /* dmovb @$dir8,@$R13+ */
3220 {
3221 { 1, 1, 1, 1 },
3222 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
3223 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
3224 & fmt_dmov2r13pib, { 0xe00 },
3225 (PTR) & fmt_dmov2r13pib_ops[0],
3226 { 0, 0, { 0 } }
3227 },
3228 /* dmov @$dir10,@-$R15 */
3229 {
3230 { 1, 1, 1, 1 },
3231 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
3232 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
3233 & fmt_dmov2r15pd, { 0xb00 },
3234 (PTR) & fmt_dmov2r15pd_ops[0],
3235 { 0, 0, { 0 } }
3236 },
3237 /* ldres @$Ri+,$u4 */
3238 {
3239 { 1, 1, 1, 1 },
3240 FR30_INSN_LDRES, "ldres", "ldres",
3241 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
3242 & fmt_ldres, { 0xbc00 },
3243 (PTR) 0,
3244 { 0, 0, { 0 } }
3245 },
3246 /* stres $u4,@$Ri+ */
3247 {
3248 { 1, 1, 1, 1 },
3249 FR30_INSN_STRES, "stres", "stres",
3250 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
3251 & fmt_ldres, { 0xbd00 },
3252 (PTR) 0,
3253 { 0, 0, { 0 } }
3254 },
3255 /* copop $u4c,$ccc,$CRj,$CRi */
3256 {
3257 { 1, 1, 1, 1 },
3258 FR30_INSN_COPOP, "copop", "copop",
3259 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
3260 & fmt_copop, { 0x9fc0 },
3261 (PTR) 0,
3262 { 0, 0, { 0 } }
3263 },
3264 /* copld $u4c,$ccc,$Rjc,$CRi */
3265 {
3266 { 1, 1, 1, 1 },
3267 FR30_INSN_COPLD, "copld", "copld",
3268 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
3269 & fmt_copld, { 0x9fd0 },
3270 (PTR) 0,
3271 { 0, 0, { 0 } }
3272 },
3273 /* copst $u4c,$ccc,$CRj,$Ric */
3274 {
3275 { 1, 1, 1, 1 },
3276 FR30_INSN_COPST, "copst", "copst",
3277 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
3278 & fmt_copst, { 0x9fe0 },
3279 (PTR) 0,
3280 { 0, 0, { 0 } }
3281 },
3282 /* copsv $u4c,$ccc,$CRj,$Ric */
3283 {
3284 { 1, 1, 1, 1 },
3285 FR30_INSN_COPSV, "copsv", "copsv",
3286 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
3287 & fmt_copst, { 0x9ff0 },
3288 (PTR) 0,
3289 { 0, 0, { 0 } }
3290 },
3291 /* nop */
3292 {
3293 { 1, 1, 1, 1 },
3294 FR30_INSN_NOP, "nop", "nop",
3295 { { MNEM, 0 } },
3296 & fmt_nop, { 0x9fa0 },
3297 (PTR) 0,
3298 { 0, 0, { 0 } }
3299 },
3300 /* andccr $u8 */
3301 {
3302 { 1, 1, 1, 1 },
3303 FR30_INSN_ANDCCR, "andccr", "andccr",
3304 { { MNEM, ' ', OP (U8), 0 } },
3305 & fmt_andccr, { 0x8300 },
3306 (PTR) & fmt_andccr_ops[0],
3307 { 0, 0, { 0 } }
3308 },
3309 /* orccr $u8 */
3310 {
3311 { 1, 1, 1, 1 },
3312 FR30_INSN_ORCCR, "orccr", "orccr",
3313 { { MNEM, ' ', OP (U8), 0 } },
3314 & fmt_andccr, { 0x9300 },
3315 (PTR) & fmt_andccr_ops[0],
3316 { 0, 0, { 0 } }
3317 },
3318 /* stilm $u8 */
3319 {
3320 { 1, 1, 1, 1 },
3321 FR30_INSN_STILM, "stilm", "stilm",
3322 { { MNEM, ' ', OP (U8), 0 } },
3323 & fmt_stilm, { 0x8700 },
3324 (PTR) & fmt_stilm_ops[0],
3325 { 0, 0, { 0 } }
3326 },
3327 /* addsp $s10 */
3328 {
3329 { 1, 1, 1, 1 },
3330 FR30_INSN_ADDSP, "addsp", "addsp",
3331 { { MNEM, ' ', OP (S10), 0 } },
3332 & fmt_addsp, { 0xa300 },
3333 (PTR) & fmt_addsp_ops[0],
3334 { 0, 0, { 0 } }
3335 },
3336 /* extsb $Ri */
3337 {
3338 { 1, 1, 1, 1 },
3339 FR30_INSN_EXTSB, "extsb", "extsb",
3340 { { MNEM, ' ', OP (RI), 0 } },
3341 & fmt_extsb, { 0x9780 },
3342 (PTR) & fmt_extsb_ops[0],
3343 { 0, 0, { 0 } }
3344 },
3345 /* extub $Ri */
3346 {
3347 { 1, 1, 1, 1 },
3348 FR30_INSN_EXTUB, "extub", "extub",
3349 { { MNEM, ' ', OP (RI), 0 } },
3350 & fmt_extub, { 0x9790 },
3351 (PTR) & fmt_extub_ops[0],
3352 { 0, 0, { 0 } }
3353 },
3354 /* extsh $Ri */
3355 {
3356 { 1, 1, 1, 1 },
3357 FR30_INSN_EXTSH, "extsh", "extsh",
3358 { { MNEM, ' ', OP (RI), 0 } },
3359 & fmt_extsh, { 0x97a0 },
3360 (PTR) & fmt_extsh_ops[0],
3361 { 0, 0, { 0 } }
3362 },
3363 /* extuh $Ri */
3364 {
3365 { 1, 1, 1, 1 },
3366 FR30_INSN_EXTUH, "extuh", "extuh",
3367 { { MNEM, ' ', OP (RI), 0 } },
3368 & fmt_extuh, { 0x97b0 },
3369 (PTR) & fmt_extuh_ops[0],
3370 { 0, 0, { 0 } }
3371 },
3372 /* ldm0 ($reglist_low_ld) */
3373 {
3374 { 1, 1, 1, 1 },
3375 FR30_INSN_LDM0, "ldm0", "ldm0",
3376 { { MNEM, ' ', '(', OP (REGLIST_LOW_LD), ')', 0 } },
3377 & fmt_ldm0, { 0x8c00 },
3378 (PTR) & fmt_ldm0_ops[0],
3379 { 0, 0, { 0 } }
3380 },
3381 /* ldm1 ($reglist_hi_ld) */
3382 {
3383 { 1, 1, 1, 1 },
3384 FR30_INSN_LDM1, "ldm1", "ldm1",
3385 { { MNEM, ' ', '(', OP (REGLIST_HI_LD), ')', 0 } },
3386 & fmt_ldm1, { 0x8d00 },
3387 (PTR) & fmt_ldm1_ops[0],
3388 { 0, 0, { 0 } }
3389 },
3390 /* stm0 ($reglist_low_st) */
3391 {
3392 { 1, 1, 1, 1 },
3393 FR30_INSN_STM0, "stm0", "stm0",
3394 { { MNEM, ' ', '(', OP (REGLIST_LOW_ST), ')', 0 } },
3395 & fmt_stm0, { 0x8e00 },
3396 (PTR) & fmt_stm0_ops[0],
3397 { 0, 0, { 0 } }
3398 },
3399 /* stm1 ($reglist_hi_st) */
3400 {
3401 { 1, 1, 1, 1 },
3402 FR30_INSN_STM1, "stm1", "stm1",
3403 { { MNEM, ' ', '(', OP (REGLIST_HI_ST), ')', 0 } },
3404 & fmt_stm1, { 0x8f00 },
3405 (PTR) & fmt_stm1_ops[0],
3406 { 0, 0, { 0 } }
3407 },
3408 /* enter $u10 */
3409 {
3410 { 1, 1, 1, 1 },
3411 FR30_INSN_ENTER, "enter", "enter",
3412 { { MNEM, ' ', OP (U10), 0 } },
3413 & fmt_enter, { 0xf00 },
3414 (PTR) & fmt_enter_ops[0],
3415 { 0, 0, { 0 } }
3416 },
3417 /* leave */
3418 {
3419 { 1, 1, 1, 1 },
3420 FR30_INSN_LEAVE, "leave", "leave",
3421 { { MNEM, 0 } },
3422 & fmt_leave, { 0x9f90 },
3423 (PTR) & fmt_leave_ops[0],
3424 { 0, 0, { 0 } }
3425 },
3426 /* xchb @$Rj,$Ri */
3427 {
3428 { 1, 1, 1, 1 },
3429 FR30_INSN_XCHB, "xchb", "xchb",
3430 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
3431 & fmt_xchb, { 0x8a00 },
3432 (PTR) & fmt_xchb_ops[0],
3433 { 0, 0, { 0 } }
3434 },
3435 };
3436
3437 #undef A
3438 #undef MNEM
3439 #undef OP
3440
3441 static const CGEN_INSN_TABLE insn_table =
3442 {
3443 & fr30_cgen_insn_table_entries[0],
3444 sizeof (CGEN_INSN),
3445 MAX_INSNS,
3446 NULL
3447 };
3448
3449 /* Formats for ALIAS macro-insns. */
3450
3451 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
3452
3453 static const CGEN_IFMT fmt_ldi8m = {
3454 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
3455 };
3456
3457 static const CGEN_IFMT fmt_ldi20m = {
3458 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
3459 };
3460
3461 static const CGEN_IFMT fmt_ldi32m = {
3462 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
3463 };
3464
3465 #undef F
3466
3467 /* Each non-simple macro entry points to an array of expansion possibilities. */
3468
3469 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
3470 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
3471 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
3472
3473 /* The macro instruction table. */
3474
3475 static const CGEN_INSN macro_insn_table_entries[] =
3476 {
3477 /* ldi8 $i8,$Ri */
3478 {
3479 { 1, 1, 1, 1 },
3480 -1, "ldi8m", "ldi8",
3481 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
3482 & fmt_ldi8m, { 0xc000 },
3483 (PTR) 0,
3484 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3485 },
3486 /* ldi20 $i20,$Ri */
3487 {
3488 { 1, 1, 1, 1 },
3489 -1, "ldi20m", "ldi20",
3490 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
3491 & fmt_ldi20m, { 0x9b00 },
3492 (PTR) 0,
3493 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3494 },
3495 /* ldi32 $i32,$Ri */
3496 {
3497 { 1, 1, 1, 1 },
3498 -1, "ldi32m", "ldi32",
3499 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
3500 & fmt_ldi32m, { 0x9f80 },
3501 (PTR) 0,
3502 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3503 },
3504 };
3505
3506 #undef A
3507 #undef MNEM
3508 #undef OP
3509
3510 static const CGEN_INSN_TABLE macro_insn_table =
3511 {
3512 & macro_insn_table_entries[0],
3513 sizeof (CGEN_INSN),
3514 (sizeof (macro_insn_table_entries) /
3515 sizeof (macro_insn_table_entries[0])),
3516 NULL
3517 };
3518
3519 static void
3520 init_tables ()
3521 {
3522 }
3523
3524 /* Return non-zero if INSN is to be added to the hash table.
3525 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3526
3527 static int
3528 asm_hash_insn_p (insn)
3529 const CGEN_INSN * insn;
3530 {
3531 return CGEN_ASM_HASH_P (insn);
3532 }
3533
3534 static int
3535 dis_hash_insn_p (insn)
3536 const CGEN_INSN * insn;
3537 {
3538 /* If building the hash table and the NO-DIS attribute is present,
3539 ignore. */
3540 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
3541 return 0;
3542 return CGEN_DIS_HASH_P (insn);
3543 }
3544
3545 /* The result is the hash value of the insn.
3546 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
3547
3548 static unsigned int
3549 asm_hash_insn (mnem)
3550 const char * mnem;
3551 {
3552 return CGEN_ASM_HASH (mnem);
3553 }
3554
3555 /* BUF is a pointer to the insn's bytes in target order.
3556 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3557 host order. */
3558
3559 static unsigned int
3560 dis_hash_insn (buf, value)
3561 const char * buf;
3562 CGEN_INSN_INT value;
3563 {
3564 return CGEN_DIS_HASH (buf, value);
3565 }
3566
3567 /* Initialize an opcode table and return a descriptor.
3568 It's much like opening a file, and must be the first function called. */
3569
3570 CGEN_OPCODE_DESC
3571 fr30_cgen_opcode_open (mach, endian)
3572 int mach;
3573 enum cgen_endian endian;
3574 {
3575 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
3576 static int init_p;
3577
3578 if (! init_p)
3579 {
3580 init_tables ();
3581 init_p = 1;
3582 }
3583
3584 memset (table, 0, sizeof (*table));
3585
3586 CGEN_OPCODE_MACH (table) = mach;
3587 CGEN_OPCODE_ENDIAN (table) = endian;
3588 /* FIXME: for the sparc case we can determine insn-endianness statically.
3589 The worry here is where both data and insn endian can be independently
3590 chosen, in which case this function will need another argument.
3591 Actually, will want to allow for more arguments in the future anyway. */
3592 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
3593
3594 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
3595
3596 CGEN_OPCODE_IFLD_TABLE (table) = & fr30_cgen_ifld_table[0];
3597
3598 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
3599
3600 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
3601
3602 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
3603
3604 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
3605 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
3606 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
3607
3608 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
3609 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
3610 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
3611
3612 return (CGEN_OPCODE_DESC) table;
3613 }
3614
3615 /* Close an opcode table. */
3616
3617 void
3618 fr30_cgen_opcode_close (desc)
3619 CGEN_OPCODE_DESC desc;
3620 {
3621 free (desc);
3622 }
3623
3624 /* Getting values from cgen_fields is handled by a collection of functions.
3625 They are distinguished by the type of the VALUE argument they return.
3626 TODO: floating point, inlining support, remove cases where result type
3627 not appropriate. */
3628
3629 int
3630 fr30_cgen_get_int_operand (opindex, fields)
3631 int opindex;
3632 const CGEN_FIELDS * fields;
3633 {
3634 int value;
3635
3636 switch (opindex)
3637 {
3638 case FR30_OPERAND_RI :
3639 value = fields->f_Ri;
3640 break;
3641 case FR30_OPERAND_RJ :
3642 value = fields->f_Rj;
3643 break;
3644 case FR30_OPERAND_RIC :
3645 value = fields->f_Ric;
3646 break;
3647 case FR30_OPERAND_RJC :
3648 value = fields->f_Rjc;
3649 break;
3650 case FR30_OPERAND_CRI :
3651 value = fields->f_CRi;
3652 break;
3653 case FR30_OPERAND_CRJ :
3654 value = fields->f_CRj;
3655 break;
3656 case FR30_OPERAND_RS1 :
3657 value = fields->f_Rs1;
3658 break;
3659 case FR30_OPERAND_RS2 :
3660 value = fields->f_Rs2;
3661 break;
3662 case FR30_OPERAND_R13 :
3663 value = fields->f_nil;
3664 break;
3665 case FR30_OPERAND_R14 :
3666 value = fields->f_nil;
3667 break;
3668 case FR30_OPERAND_R15 :
3669 value = fields->f_nil;
3670 break;
3671 case FR30_OPERAND_PS :
3672 value = fields->f_nil;
3673 break;
3674 case FR30_OPERAND_U4 :
3675 value = fields->f_u4;
3676 break;
3677 case FR30_OPERAND_U4C :
3678 value = fields->f_u4c;
3679 break;
3680 case FR30_OPERAND_U8 :
3681 value = fields->f_u8;
3682 break;
3683 case FR30_OPERAND_I8 :
3684 value = fields->f_i8;
3685 break;
3686 case FR30_OPERAND_UDISP6 :
3687 value = fields->f_udisp6;
3688 break;
3689 case FR30_OPERAND_DISP8 :
3690 value = fields->f_disp8;
3691 break;
3692 case FR30_OPERAND_DISP9 :
3693 value = fields->f_disp9;
3694 break;
3695 case FR30_OPERAND_DISP10 :
3696 value = fields->f_disp10;
3697 break;
3698 case FR30_OPERAND_S10 :
3699 value = fields->f_s10;
3700 break;
3701 case FR30_OPERAND_U10 :
3702 value = fields->f_u10;
3703 break;
3704 case FR30_OPERAND_I32 :
3705 value = fields->f_i32;
3706 break;
3707 case FR30_OPERAND_M4 :
3708 value = fields->f_m4;
3709 break;
3710 case FR30_OPERAND_I20 :
3711 value = fields->f_i20;
3712 break;
3713 case FR30_OPERAND_DIR8 :
3714 value = fields->f_dir8;
3715 break;
3716 case FR30_OPERAND_DIR9 :
3717 value = fields->f_dir9;
3718 break;
3719 case FR30_OPERAND_DIR10 :
3720 value = fields->f_dir10;
3721 break;
3722 case FR30_OPERAND_LABEL9 :
3723 value = fields->f_rel9;
3724 break;
3725 case FR30_OPERAND_LABEL12 :
3726 value = fields->f_rel12;
3727 break;
3728 case FR30_OPERAND_REGLIST_LOW_LD :
3729 value = fields->f_reglist_low_ld;
3730 break;
3731 case FR30_OPERAND_REGLIST_HI_LD :
3732 value = fields->f_reglist_hi_ld;
3733 break;
3734 case FR30_OPERAND_REGLIST_LOW_ST :
3735 value = fields->f_reglist_low_st;
3736 break;
3737 case FR30_OPERAND_REGLIST_HI_ST :
3738 value = fields->f_reglist_hi_st;
3739 break;
3740 case FR30_OPERAND_CC :
3741 value = fields->f_cc;
3742 break;
3743 case FR30_OPERAND_CCC :
3744 value = fields->f_ccc;
3745 break;
3746
3747 default :
3748 /* xgettext:c-format */
3749 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3750 opindex);
3751 abort ();
3752 }
3753
3754 return value;
3755 }
3756
3757 bfd_vma
3758 fr30_cgen_get_vma_operand (opindex, fields)
3759 int opindex;
3760 const CGEN_FIELDS * fields;
3761 {
3762 bfd_vma value;
3763
3764 switch (opindex)
3765 {
3766 case FR30_OPERAND_RI :
3767 value = fields->f_Ri;
3768 break;
3769 case FR30_OPERAND_RJ :
3770 value = fields->f_Rj;
3771 break;
3772 case FR30_OPERAND_RIC :
3773 value = fields->f_Ric;
3774 break;
3775 case FR30_OPERAND_RJC :
3776 value = fields->f_Rjc;
3777 break;
3778 case FR30_OPERAND_CRI :
3779 value = fields->f_CRi;
3780 break;
3781 case FR30_OPERAND_CRJ :
3782 value = fields->f_CRj;
3783 break;
3784 case FR30_OPERAND_RS1 :
3785 value = fields->f_Rs1;
3786 break;
3787 case FR30_OPERAND_RS2 :
3788 value = fields->f_Rs2;
3789 break;
3790 case FR30_OPERAND_R13 :
3791 value = fields->f_nil;
3792 break;
3793 case FR30_OPERAND_R14 :
3794 value = fields->f_nil;
3795 break;
3796 case FR30_OPERAND_R15 :
3797 value = fields->f_nil;
3798 break;
3799 case FR30_OPERAND_PS :
3800 value = fields->f_nil;
3801 break;
3802 case FR30_OPERAND_U4 :
3803 value = fields->f_u4;
3804 break;
3805 case FR30_OPERAND_U4C :
3806 value = fields->f_u4c;
3807 break;
3808 case FR30_OPERAND_U8 :
3809 value = fields->f_u8;
3810 break;
3811 case FR30_OPERAND_I8 :
3812 value = fields->f_i8;
3813 break;
3814 case FR30_OPERAND_UDISP6 :
3815 value = fields->f_udisp6;
3816 break;
3817 case FR30_OPERAND_DISP8 :
3818 value = fields->f_disp8;
3819 break;
3820 case FR30_OPERAND_DISP9 :
3821 value = fields->f_disp9;
3822 break;
3823 case FR30_OPERAND_DISP10 :
3824 value = fields->f_disp10;
3825 break;
3826 case FR30_OPERAND_S10 :
3827 value = fields->f_s10;
3828 break;
3829 case FR30_OPERAND_U10 :
3830 value = fields->f_u10;
3831 break;
3832 case FR30_OPERAND_I32 :
3833 value = fields->f_i32;
3834 break;
3835 case FR30_OPERAND_M4 :
3836 value = fields->f_m4;
3837 break;
3838 case FR30_OPERAND_I20 :
3839 value = fields->f_i20;
3840 break;
3841 case FR30_OPERAND_DIR8 :
3842 value = fields->f_dir8;
3843 break;
3844 case FR30_OPERAND_DIR9 :
3845 value = fields->f_dir9;
3846 break;
3847 case FR30_OPERAND_DIR10 :
3848 value = fields->f_dir10;
3849 break;
3850 case FR30_OPERAND_LABEL9 :
3851 value = fields->f_rel9;
3852 break;
3853 case FR30_OPERAND_LABEL12 :
3854 value = fields->f_rel12;
3855 break;
3856 case FR30_OPERAND_REGLIST_LOW_LD :
3857 value = fields->f_reglist_low_ld;
3858 break;
3859 case FR30_OPERAND_REGLIST_HI_LD :
3860 value = fields->f_reglist_hi_ld;
3861 break;
3862 case FR30_OPERAND_REGLIST_LOW_ST :
3863 value = fields->f_reglist_low_st;
3864 break;
3865 case FR30_OPERAND_REGLIST_HI_ST :
3866 value = fields->f_reglist_hi_st;
3867 break;
3868 case FR30_OPERAND_CC :
3869 value = fields->f_cc;
3870 break;
3871 case FR30_OPERAND_CCC :
3872 value = fields->f_ccc;
3873 break;
3874
3875 default :
3876 /* xgettext:c-format */
3877 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3878 opindex);
3879 abort ();
3880 }
3881
3882 return value;
3883 }
3884
3885 /* Stuffing values in cgen_fields is handled by a collection of functions.
3886 They are distinguished by the type of the VALUE argument they accept.
3887 TODO: floating point, inlining support, remove cases where argument type
3888 not appropriate. */
3889
3890 void
3891 fr30_cgen_set_int_operand (opindex, fields, value)
3892 int opindex;
3893 CGEN_FIELDS * fields;
3894 int value;
3895 {
3896 switch (opindex)
3897 {
3898 case FR30_OPERAND_RI :
3899 fields->f_Ri = value;
3900 break;
3901 case FR30_OPERAND_RJ :
3902 fields->f_Rj = value;
3903 break;
3904 case FR30_OPERAND_RIC :
3905 fields->f_Ric = value;
3906 break;
3907 case FR30_OPERAND_RJC :
3908 fields->f_Rjc = value;
3909 break;
3910 case FR30_OPERAND_CRI :
3911 fields->f_CRi = value;
3912 break;
3913 case FR30_OPERAND_CRJ :
3914 fields->f_CRj = value;
3915 break;
3916 case FR30_OPERAND_RS1 :
3917 fields->f_Rs1 = value;
3918 break;
3919 case FR30_OPERAND_RS2 :
3920 fields->f_Rs2 = value;
3921 break;
3922 case FR30_OPERAND_R13 :
3923 fields->f_nil = value;
3924 break;
3925 case FR30_OPERAND_R14 :
3926 fields->f_nil = value;
3927 break;
3928 case FR30_OPERAND_R15 :
3929 fields->f_nil = value;
3930 break;
3931 case FR30_OPERAND_PS :
3932 fields->f_nil = value;
3933 break;
3934 case FR30_OPERAND_U4 :
3935 fields->f_u4 = value;
3936 break;
3937 case FR30_OPERAND_U4C :
3938 fields->f_u4c = value;
3939 break;
3940 case FR30_OPERAND_U8 :
3941 fields->f_u8 = value;
3942 break;
3943 case FR30_OPERAND_I8 :
3944 fields->f_i8 = value;
3945 break;
3946 case FR30_OPERAND_UDISP6 :
3947 fields->f_udisp6 = value;
3948 break;
3949 case FR30_OPERAND_DISP8 :
3950 fields->f_disp8 = value;
3951 break;
3952 case FR30_OPERAND_DISP9 :
3953 fields->f_disp9 = value;
3954 break;
3955 case FR30_OPERAND_DISP10 :
3956 fields->f_disp10 = value;
3957 break;
3958 case FR30_OPERAND_S10 :
3959 fields->f_s10 = value;
3960 break;
3961 case FR30_OPERAND_U10 :
3962 fields->f_u10 = value;
3963 break;
3964 case FR30_OPERAND_I32 :
3965 fields->f_i32 = value;
3966 break;
3967 case FR30_OPERAND_M4 :
3968 fields->f_m4 = value;
3969 break;
3970 case FR30_OPERAND_I20 :
3971 fields->f_i20 = value;
3972 break;
3973 case FR30_OPERAND_DIR8 :
3974 fields->f_dir8 = value;
3975 break;
3976 case FR30_OPERAND_DIR9 :
3977 fields->f_dir9 = value;
3978 break;
3979 case FR30_OPERAND_DIR10 :
3980 fields->f_dir10 = value;
3981 break;
3982 case FR30_OPERAND_LABEL9 :
3983 fields->f_rel9 = value;
3984 break;
3985 case FR30_OPERAND_LABEL12 :
3986 fields->f_rel12 = value;
3987 break;
3988 case FR30_OPERAND_REGLIST_LOW_LD :
3989 fields->f_reglist_low_ld = value;
3990 break;
3991 case FR30_OPERAND_REGLIST_HI_LD :
3992 fields->f_reglist_hi_ld = value;
3993 break;
3994 case FR30_OPERAND_REGLIST_LOW_ST :
3995 fields->f_reglist_low_st = value;
3996 break;
3997 case FR30_OPERAND_REGLIST_HI_ST :
3998 fields->f_reglist_hi_st = value;
3999 break;
4000 case FR30_OPERAND_CC :
4001 fields->f_cc = value;
4002 break;
4003 case FR30_OPERAND_CCC :
4004 fields->f_ccc = value;
4005 break;
4006
4007 default :
4008 /* xgettext:c-format */
4009 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
4010 opindex);
4011 abort ();
4012 }
4013 }
4014
4015 void
4016 fr30_cgen_set_vma_operand (opindex, fields, value)
4017 int opindex;
4018 CGEN_FIELDS * fields;
4019 bfd_vma value;
4020 {
4021 switch (opindex)
4022 {
4023 case FR30_OPERAND_RI :
4024 fields->f_Ri = value;
4025 break;
4026 case FR30_OPERAND_RJ :
4027 fields->f_Rj = value;
4028 break;
4029 case FR30_OPERAND_RIC :
4030 fields->f_Ric = value;
4031 break;
4032 case FR30_OPERAND_RJC :
4033 fields->f_Rjc = value;
4034 break;
4035 case FR30_OPERAND_CRI :
4036 fields->f_CRi = value;
4037 break;
4038 case FR30_OPERAND_CRJ :
4039 fields->f_CRj = value;
4040 break;
4041 case FR30_OPERAND_RS1 :
4042 fields->f_Rs1 = value;
4043 break;
4044 case FR30_OPERAND_RS2 :
4045 fields->f_Rs2 = value;
4046 break;
4047 case FR30_OPERAND_R13 :
4048 fields->f_nil = value;
4049 break;
4050 case FR30_OPERAND_R14 :
4051 fields->f_nil = value;
4052 break;
4053 case FR30_OPERAND_R15 :
4054 fields->f_nil = value;
4055 break;
4056 case FR30_OPERAND_PS :
4057 fields->f_nil = value;
4058 break;
4059 case FR30_OPERAND_U4 :
4060 fields->f_u4 = value;
4061 break;
4062 case FR30_OPERAND_U4C :
4063 fields->f_u4c = value;
4064 break;
4065 case FR30_OPERAND_U8 :
4066 fields->f_u8 = value;
4067 break;
4068 case FR30_OPERAND_I8 :
4069 fields->f_i8 = value;
4070 break;
4071 case FR30_OPERAND_UDISP6 :
4072 fields->f_udisp6 = value;
4073 break;
4074 case FR30_OPERAND_DISP8 :
4075 fields->f_disp8 = value;
4076 break;
4077 case FR30_OPERAND_DISP9 :
4078 fields->f_disp9 = value;
4079 break;
4080 case FR30_OPERAND_DISP10 :
4081 fields->f_disp10 = value;
4082 break;
4083 case FR30_OPERAND_S10 :
4084 fields->f_s10 = value;
4085 break;
4086 case FR30_OPERAND_U10 :
4087 fields->f_u10 = value;
4088 break;
4089 case FR30_OPERAND_I32 :
4090 fields->f_i32 = value;
4091 break;
4092 case FR30_OPERAND_M4 :
4093 fields->f_m4 = value;
4094 break;
4095 case FR30_OPERAND_I20 :
4096 fields->f_i20 = value;
4097 break;
4098 case FR30_OPERAND_DIR8 :
4099 fields->f_dir8 = value;
4100 break;
4101 case FR30_OPERAND_DIR9 :
4102 fields->f_dir9 = value;
4103 break;
4104 case FR30_OPERAND_DIR10 :
4105 fields->f_dir10 = value;
4106 break;
4107 case FR30_OPERAND_LABEL9 :
4108 fields->f_rel9 = value;
4109 break;
4110 case FR30_OPERAND_LABEL12 :
4111 fields->f_rel12 = value;
4112 break;
4113 case FR30_OPERAND_REGLIST_LOW_LD :
4114 fields->f_reglist_low_ld = value;
4115 break;
4116 case FR30_OPERAND_REGLIST_HI_LD :
4117 fields->f_reglist_hi_ld = value;
4118 break;
4119 case FR30_OPERAND_REGLIST_LOW_ST :
4120 fields->f_reglist_low_st = value;
4121 break;
4122 case FR30_OPERAND_REGLIST_HI_ST :
4123 fields->f_reglist_hi_st = value;
4124 break;
4125 case FR30_OPERAND_CC :
4126 fields->f_cc = value;
4127 break;
4128 case FR30_OPERAND_CCC :
4129 fields->f_ccc = value;
4130 break;
4131
4132 default :
4133 /* xgettext:c-format */
4134 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
4135 opindex);
4136 abort ();
4137 }
4138 }
4139
GDB Binutils - Deliverables
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