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* cgen-asm.in (insert_normal): Use CGEN_BOOL_ATTR.
[deliverable/binutils-gdb.git] / opcodes / fr30-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "fr30-opc.h"
31 #include "opintl.h"
32
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
35
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40 static unsigned int asm_hash_insn PARAMS ((const char *));
41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
43
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
52 The result is a pointer to the insn table entry, or NULL if the instruction
53 wasn't recognized. */
54
55 const CGEN_INSN *
56 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63 {
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
65 unsigned char *bufp;
66 CGEN_INSN_INT base_insn;
67 #if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69 #else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72 #endif
73
74 #if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78 #else
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
81 ex_info.valid = -1;
82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
84 #endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
109 base_insn, fields,
110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145 }
146
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151 void
152 fr30_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157 {
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173 }
174
175 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 fr30_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183 const CGEN_INSN *
184 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190 {
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202 }
203 /* Attributes. */
204
205 static const CGEN_ATTR_ENTRY bool_attr[] =
206 {
207 { "#f", 0 },
208 { "#t", 1 },
209 { 0, 0 }
210 };
211
212 static const CGEN_ATTR_ENTRY MACH_attr[] =
213 {
214 { "base", MACH_BASE },
215 { "fr30", MACH_FR30 },
216 { "max", MACH_MAX },
217 { 0, 0 }
218 };
219
220 const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
221 {
222 { "MACH", & MACH_attr[0] },
223 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
224 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
225 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
226 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
227 { "RESERVED", &bool_attr[0], &bool_attr[0] },
228 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
229 { 0, 0, 0 }
230 };
231
232 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
233 {
234 { "MACH", & MACH_attr[0] },
235 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
236 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
237 { "SIGNED", &bool_attr[0], &bool_attr[0] },
238 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
239 { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
240 { "PC", &bool_attr[0], &bool_attr[0] },
241 { "PROFILE", &bool_attr[0], &bool_attr[0] },
242 { 0, 0, 0 }
243 };
244
245 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
246 {
247 { "MACH", & MACH_attr[0] },
248 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
249 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
250 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
251 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
252 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
253 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
254 { "RELAX", &bool_attr[0], &bool_attr[0] },
255 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
256 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
257 { 0, 0, 0 }
258 };
259
260 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
261 {
262 { "MACH", & MACH_attr[0] },
263 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
264 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
265 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
266 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
267 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
268 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
269 { "RELAX", &bool_attr[0], &bool_attr[0] },
270 { "ALIAS", &bool_attr[0], &bool_attr[0] },
271 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
272 { "PBB", &bool_attr[0], &bool_attr[0] },
273 { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
274 { 0, 0, 0 }
275 };
276
277 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
278 {
279 { "r0", 0 },
280 { "r1", 1 },
281 { "r2", 2 },
282 { "r3", 3 },
283 { "r4", 4 },
284 { "r5", 5 },
285 { "r6", 6 },
286 { "r7", 7 },
287 { "r8", 8 },
288 { "r9", 9 },
289 { "r10", 10 },
290 { "r11", 11 },
291 { "r12", 12 },
292 { "r13", 13 },
293 { "r14", 14 },
294 { "r15", 15 },
295 { "ac", 13 },
296 { "fp", 14 },
297 { "sp", 15 }
298 };
299
300 CGEN_KEYWORD fr30_cgen_opval_h_gr =
301 {
302 & fr30_cgen_opval_h_gr_entries[0],
303 19
304 };
305
306 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
307 {
308 { "cr0", 0 },
309 { "cr1", 1 },
310 { "cr2", 2 },
311 { "cr3", 3 },
312 { "cr4", 4 },
313 { "cr5", 5 },
314 { "cr6", 6 },
315 { "cr7", 7 },
316 { "cr8", 8 },
317 { "cr9", 9 },
318 { "cr10", 10 },
319 { "cr11", 11 },
320 { "cr12", 12 },
321 { "cr13", 13 },
322 { "cr14", 14 },
323 { "cr15", 15 }
324 };
325
326 CGEN_KEYWORD fr30_cgen_opval_h_cr =
327 {
328 & fr30_cgen_opval_h_cr_entries[0],
329 16
330 };
331
332 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
333 {
334 { "tbr", 0 },
335 { "rp", 1 },
336 { "ssp", 2 },
337 { "usp", 3 },
338 { "mdh", 4 },
339 { "mdl", 5 }
340 };
341
342 CGEN_KEYWORD fr30_cgen_opval_h_dr =
343 {
344 & fr30_cgen_opval_h_dr_entries[0],
345 6
346 };
347
348 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
349 {
350 { "ps", 0 }
351 };
352
353 CGEN_KEYWORD fr30_cgen_opval_h_ps =
354 {
355 & fr30_cgen_opval_h_ps_entries[0],
356 1
357 };
358
359 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
360 {
361 { "r13", 0 }
362 };
363
364 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
365 {
366 & fr30_cgen_opval_h_r13_entries[0],
367 1
368 };
369
370 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
371 {
372 { "r14", 0 }
373 };
374
375 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
376 {
377 & fr30_cgen_opval_h_r14_entries[0],
378 1
379 };
380
381 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
382 {
383 { "r15", 0 }
384 };
385
386 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
387 {
388 & fr30_cgen_opval_h_r15_entries[0],
389 1
390 };
391
392
393 /* The hardware table. */
394
395 #define HW_ENT(n) fr30_cgen_hw_entries[n]
396 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
397 {
398 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
399 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
400 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
401 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
402 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
403 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
404 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
405 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
406 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
407 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
408 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
409 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
410 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
411 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
412 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
413 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
414 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
415 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
416 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
417 { HW_H_TBIT, & HW_ENT (HW_H_TBIT + 1), "h-tbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
418 { HW_H_D0BIT, & HW_ENT (HW_H_D0BIT + 1), "h-d0bit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
419 { HW_H_D1BIT, & HW_ENT (HW_H_D1BIT + 1), "h-d1bit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
420 { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
421 { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
422 { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
423 { 0 }
424 };
425
426 /* The instruction field table. */
427
428 static const CGEN_IFLD fr30_cgen_ifld_table[] =
429 {
430 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
431 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
432 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
433 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
434 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
435 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
436 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
437 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
438 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
439 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
440 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
441 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
442 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
443 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
444 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
445 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
446 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
447 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
448 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
449 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
450 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
451 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
452 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
453 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
454 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
455 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
456 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
457 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
458 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
459 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
460 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
461 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
462 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
463 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
464 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
465 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
466 { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
467 { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
468 { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
469 { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
470 { 0 }
471 };
472
473 /* The operand table. */
474
475 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
476 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
477
478 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
479 {
480 /* pc: program counter */
481 { "pc", & HW_ENT (HW_H_PC), 0, 0,
482 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
483 /* Ri: destination register */
484 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
485 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
486 /* Rj: source register */
487 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
488 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
489 /* Ric: target register coproc insn */
490 { "Ric", & HW_ENT (HW_H_GR), 12, 4,
491 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
492 /* Rjc: source register coproc insn */
493 { "Rjc", & HW_ENT (HW_H_GR), 8, 4,
494 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
495 /* CRi: coprocessor register */
496 { "CRi", & HW_ENT (HW_H_CR), 12, 4,
497 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
498 /* CRj: coprocessor register */
499 { "CRj", & HW_ENT (HW_H_CR), 8, 4,
500 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
501 /* Rs1: dedicated register */
502 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
503 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
504 /* Rs2: dedicated register */
505 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
506 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
507 /* R13: General Register 13 */
508 { "R13", & HW_ENT (HW_H_R13), 0, 0,
509 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
510 /* R14: General Register 14 */
511 { "R14", & HW_ENT (HW_H_R14), 0, 0,
512 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
513 /* R15: General Register 15 */
514 { "R15", & HW_ENT (HW_H_R15), 0, 0,
515 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
516 /* ps: Program Status register */
517 { "ps", & HW_ENT (HW_H_PS), 0, 0,
518 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
519 /* u4: 4 bit unsigned immediate */
520 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
521 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
522 /* u4c: 4 bit unsigned immediate */
523 { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
524 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
525 /* u8: 8 bit unsigned immediate */
526 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
527 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
528 /* i8: 8 bit unsigned immediate */
529 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
530 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
531 /* udisp6: 6 bit unsigned immediate */
532 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
533 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
534 /* disp8: 8 bit signed immediate */
535 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
536 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
537 /* disp9: 9 bit signed immediate */
538 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
539 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
540 /* disp10: 10 bit signed immediate */
541 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
542 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
543 /* s10: 10 bit signed immediate */
544 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
545 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
546 /* u10: 10 bit unsigned immediate */
547 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
548 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
549 /* i32: 32 bit immediate */
550 { "i32", & HW_ENT (HW_H_UINT), 0, 32,
551 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
552 /* m4: 4 bit negative immediate */
553 { "m4", & HW_ENT (HW_H_SINT), 8, 4,
554 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
555 /* i20: 20 bit immediate */
556 { "i20", & HW_ENT (HW_H_UINT), 0, 20,
557 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { (1<<MACH_BASE) } } },
558 /* dir8: 8 bit direct address */
559 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
560 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
561 /* dir9: 9 bit direct address */
562 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
563 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
564 /* dir10: 10 bit direct address */
565 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
566 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
567 /* label9: 9 bit pc relative address */
568 { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
569 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
570 /* label12: 12 bit pc relative address */
571 { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
572 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
573 /* reglist_low_ld: 8 bit register mask for ldm */
574 { "reglist_low_ld", & HW_ENT (HW_H_UINT), 8, 8,
575 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
576 /* reglist_hi_ld: 8 bit register mask for ldm */
577 { "reglist_hi_ld", & HW_ENT (HW_H_UINT), 8, 8,
578 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
579 /* reglist_low_st: 8 bit register mask for ldm */
580 { "reglist_low_st", & HW_ENT (HW_H_UINT), 8, 8,
581 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
582 /* reglist_hi_st: 8 bit register mask for ldm */
583 { "reglist_hi_st", & HW_ENT (HW_H_UINT), 8, 8,
584 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
585 /* cc: condition codes */
586 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
587 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
588 /* ccc: coprocessor calc */
589 { "ccc", & HW_ENT (HW_H_UINT), 0, 8,
590 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
591 /* nbit: negative bit */
592 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
593 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
594 /* vbit: overflow bit */
595 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
596 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
597 /* zbit: zero bit */
598 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
599 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
600 /* cbit: carry bit */
601 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
602 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
603 /* ibit: interrupt bit */
604 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
605 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
606 /* sbit: stack bit */
607 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
608 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
609 /* tbit: trace trap bit */
610 { "tbit", & HW_ENT (HW_H_TBIT), 0, 0,
611 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
612 /* d0bit: division 0 bit */
613 { "d0bit", & HW_ENT (HW_H_D0BIT), 0, 0,
614 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
615 /* d1bit: division 1 bit */
616 { "d1bit", & HW_ENT (HW_H_D1BIT), 0, 0,
617 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
618 /* ccr: condition code bits */
619 { "ccr", & HW_ENT (HW_H_CCR), 0, 0,
620 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
621 /* scr: system condition bits */
622 { "scr", & HW_ENT (HW_H_SCR), 0, 0,
623 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
624 /* ilm: condition code bits */
625 { "ilm", & HW_ENT (HW_H_ILM), 0, 0,
626 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
627 };
628
629 /* Operand references. */
630
631 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
632 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
633 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
634
635 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
636 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
637 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
638 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
639 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
640 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
641 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
642 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
643 { 0 }
644 };
645
646 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
647 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
648 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
649 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
650 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
651 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
652 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
653 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
654 { 0 }
655 };
656
657 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
658 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
659 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
660 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
661 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
662 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
663 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
664 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
665 { 0 }
666 };
667
668 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
669 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
670 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
671 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
672 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
673 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
674 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
675 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
676 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
677 { 0 }
678 };
679
680 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
681 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
682 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
683 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
684 { 0 }
685 };
686
687 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
688 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
689 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
690 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
691 { 0 }
692 };
693
694 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
695 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
696 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
697 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
698 { 0 }
699 };
700
701 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
702 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
703 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
704 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
705 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
706 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
707 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
708 { 0 }
709 };
710
711 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
712 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
713 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
714 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
715 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
716 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
717 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
718 { 0 }
719 };
720
721 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
722 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
723 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
724 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
725 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
726 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
727 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
728 { 0 }
729 };
730
731 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
732 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
733 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
734 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
735 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
736 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
737 { 0 }
738 };
739
740 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
741 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
742 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
743 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
744 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
745 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
746 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
747 { 0 }
748 };
749
750 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
751 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
752 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
753 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
754 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
755 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
756 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
757 { 0 }
758 };
759
760 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
761 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
762 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
763 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
764 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
765 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
766 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
767 { 0 }
768 };
769
770 static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
771 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
772 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
773 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
774 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
775 { 0 }
776 };
777
778 static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
779 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
780 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
781 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
782 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
783 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
784 { 0 }
785 };
786
787 static const CGEN_OPERAND_INSTANCE fmt_mul_ops[] = {
788 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
789 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
790 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
791 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
792 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
793 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
794 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
795 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
796 { 0 }
797 };
798
799 static const CGEN_OPERAND_INSTANCE fmt_mulu_ops[] = {
800 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
801 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
802 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
803 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
804 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
805 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
806 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
807 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
808 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
809 { 0 }
810 };
811
812 static const CGEN_OPERAND_INSTANCE fmt_mulh_ops[] = {
813 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
814 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
815 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
816 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
817 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
818 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
819 { 0 }
820 };
821
822 static const CGEN_OPERAND_INSTANCE fmt_div0s_ops[] = {
823 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
824 { INPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
825 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
826 { OUTPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
827 { OUTPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
828 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
829 { 0 }
830 };
831
832 static const CGEN_OPERAND_INSTANCE fmt_div0u_ops[] = {
833 { OUTPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
834 { OUTPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
835 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
836 { 0 }
837 };
838
839 static const CGEN_OPERAND_INSTANCE fmt_div1_ops[] = {
840 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
841 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
842 { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
843 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
844 { INPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
845 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
846 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
847 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
848 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
849 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
850 { 0 }
851 };
852
853 static const CGEN_OPERAND_INSTANCE fmt_div2_ops[] = {
854 { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
855 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
856 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
857 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
858 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, COND_REF },
859 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
860 { 0 }
861 };
862
863 static const CGEN_OPERAND_INSTANCE fmt_div3_ops[] = {
864 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
865 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
866 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
867 { 0 }
868 };
869
870 static const CGEN_OPERAND_INSTANCE fmt_div4s_ops[] = {
871 { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
872 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
873 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
874 { 0 }
875 };
876
877 static const CGEN_OPERAND_INSTANCE fmt_lsl_ops[] = {
878 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
879 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
880 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
881 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
882 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
883 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
884 { 0 }
885 };
886
887 static const CGEN_OPERAND_INSTANCE fmt_lsli_ops[] = {
888 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
889 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
890 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
891 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
892 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
893 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
894 { 0 }
895 };
896
897 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
898 { INPUT, "i8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I8), 0, 0 },
899 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
900 { 0 }
901 };
902
903 static const CGEN_OPERAND_INSTANCE fmt_ldi20_ops[] = {
904 { INPUT, "i20", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I20), 0, 0 },
905 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
906 { 0 }
907 };
908
909 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
910 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
911 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
912 { 0 }
913 };
914
915 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
916 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
917 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
918 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
919 { 0 }
920 };
921
922 static const CGEN_OPERAND_INSTANCE fmt_lduh_ops[] = {
923 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
924 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
925 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
926 { 0 }
927 };
928
929 static const CGEN_OPERAND_INSTANCE fmt_ldub_ops[] = {
930 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
931 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
932 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
933 { 0 }
934 };
935
936 static const CGEN_OPERAND_INSTANCE fmt_ldr13_ops[] = {
937 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
938 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
939 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
940 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
941 { 0 }
942 };
943
944 static const CGEN_OPERAND_INSTANCE fmt_ldr13uh_ops[] = {
945 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
946 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
947 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
948 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
949 { 0 }
950 };
951
952 static const CGEN_OPERAND_INSTANCE fmt_ldr13ub_ops[] = {
953 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
954 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
955 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
956 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
957 { 0 }
958 };
959
960 static const CGEN_OPERAND_INSTANCE fmt_ldr14_ops[] = {
961 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
962 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
963 { INPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
964 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
965 { 0 }
966 };
967
968 static const CGEN_OPERAND_INSTANCE fmt_ldr14uh_ops[] = {
969 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
970 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
971 { INPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
972 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
973 { 0 }
974 };
975
976 static const CGEN_OPERAND_INSTANCE fmt_ldr14ub_ops[] = {
977 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
978 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
979 { INPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
980 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
981 { 0 }
982 };
983
984 static const CGEN_OPERAND_INSTANCE fmt_ldr15_ops[] = {
985 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
986 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
987 { INPUT, "h_memory_add__VM_udisp6_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
988 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
989 { 0 }
990 };
991
992 static const CGEN_OPERAND_INSTANCE fmt_ldr15gr_ops[] = {
993 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
994 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
995 { INPUT, "f_Ri", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
996 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
997 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
998 { 0 }
999 };
1000
1001 static const CGEN_OPERAND_INSTANCE fmt_ldr15dr_ops[] = {
1002 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1003 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1004 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1005 { OUTPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
1006 { 0 }
1007 };
1008
1009 static const CGEN_OPERAND_INSTANCE fmt_ldr15ps_ops[] = {
1010 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1011 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1012 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1013 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1014 { 0 }
1015 };
1016
1017 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
1018 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1019 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1020 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1021 { 0 }
1022 };
1023
1024 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
1025 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1026 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1027 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1028 { 0 }
1029 };
1030
1031 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
1032 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1033 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1034 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1035 { 0 }
1036 };
1037
1038 static const CGEN_OPERAND_INSTANCE fmt_str13_ops[] = {
1039 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1040 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1041 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1042 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1043 { 0 }
1044 };
1045
1046 static const CGEN_OPERAND_INSTANCE fmt_str13h_ops[] = {
1047 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1048 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1049 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1050 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1051 { 0 }
1052 };
1053
1054 static const CGEN_OPERAND_INSTANCE fmt_str13b_ops[] = {
1055 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1056 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1057 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1058 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1059 { 0 }
1060 };
1061
1062 static const CGEN_OPERAND_INSTANCE fmt_str14_ops[] = {
1063 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
1064 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1065 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1066 { OUTPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1067 { 0 }
1068 };
1069
1070 static const CGEN_OPERAND_INSTANCE fmt_str14h_ops[] = {
1071 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
1072 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1073 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1074 { OUTPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1075 { 0 }
1076 };
1077
1078 static const CGEN_OPERAND_INSTANCE fmt_str14b_ops[] = {
1079 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
1080 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1081 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1082 { OUTPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1083 { 0 }
1084 };
1085
1086 static const CGEN_OPERAND_INSTANCE fmt_str15_ops[] = {
1087 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1088 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
1089 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1090 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_15_udisp6", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1091 { 0 }
1092 };
1093
1094 static const CGEN_OPERAND_INSTANCE fmt_str15gr_ops[] = {
1095 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1096 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1097 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1098 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1099 { 0 }
1100 };
1101
1102 static const CGEN_OPERAND_INSTANCE fmt_str15dr_ops[] = {
1103 { INPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
1104 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1105 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1106 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1107 { 0 }
1108 };
1109
1110 static const CGEN_OPERAND_INSTANCE fmt_str15ps_ops[] = {
1111 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1112 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1113 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1114 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1115 { 0 }
1116 };
1117
1118 static const CGEN_OPERAND_INSTANCE fmt_mov_ops[] = {
1119 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1120 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1121 { 0 }
1122 };
1123
1124 static const CGEN_OPERAND_INSTANCE fmt_movdr_ops[] = {
1125 { INPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1126 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1127 { 0 }
1128 };
1129
1130 static const CGEN_OPERAND_INSTANCE fmt_movps_ops[] = {
1131 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1132 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1133 { 0 }
1134 };
1135
1136 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
1137 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1138 { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1139 { 0 }
1140 };
1141
1142 static const CGEN_OPERAND_INSTANCE fmt_mov2ps_ops[] = {
1143 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1144 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1145 { 0 }
1146 };
1147
1148 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
1149 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1150 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1151 { 0 }
1152 };
1153
1154 static const CGEN_OPERAND_INSTANCE fmt_callr_ops[] = {
1155 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1156 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1157 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1158 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1159 { 0 }
1160 };
1161
1162 static const CGEN_OPERAND_INSTANCE fmt_call_ops[] = {
1163 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1164 { INPUT, "label12", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL12), 0, 0 },
1165 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1166 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1167 { 0 }
1168 };
1169
1170 static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
1171 { INPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1172 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1173 { 0 }
1174 };
1175
1176 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
1177 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1178 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
1179 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
1180 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1181 { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1182 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1183 { 0 }
1184 };
1185
1186 static const CGEN_OPERAND_INSTANCE fmt_inte_ops[] = {
1187 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1188 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
1189 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1190 { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
1191 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1192 { 0 }
1193 };
1194
1195 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
1196 { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1197 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
1198 { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1199 { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
1200 { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1201 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1202 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
1203 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
1204 { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
1205 { 0 }
1206 };
1207
1208 static const CGEN_OPERAND_INSTANCE fmt_brad_ops[] = {
1209 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1210 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1211 { 0 }
1212 };
1213
1214 static const CGEN_OPERAND_INSTANCE fmt_beqd_ops[] = {
1215 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1216 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1217 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1218 { 0 }
1219 };
1220
1221 static const CGEN_OPERAND_INSTANCE fmt_bcd_ops[] = {
1222 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1223 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1224 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1225 { 0 }
1226 };
1227
1228 static const CGEN_OPERAND_INSTANCE fmt_bnd_ops[] = {
1229 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1230 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1231 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1232 { 0 }
1233 };
1234
1235 static const CGEN_OPERAND_INSTANCE fmt_bvd_ops[] = {
1236 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1237 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1238 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1239 { 0 }
1240 };
1241
1242 static const CGEN_OPERAND_INSTANCE fmt_bltd_ops[] = {
1243 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1244 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1245 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1246 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1247 { 0 }
1248 };
1249
1250 static const CGEN_OPERAND_INSTANCE fmt_bled_ops[] = {
1251 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1252 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1253 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1254 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1255 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1256 { 0 }
1257 };
1258
1259 static const CGEN_OPERAND_INSTANCE fmt_blsd_ops[] = {
1260 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1261 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1262 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1263 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1264 { 0 }
1265 };
1266
1267 static const CGEN_OPERAND_INSTANCE fmt_dmovr13_ops[] = {
1268 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1269 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1270 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1271 { 0 }
1272 };
1273
1274 static const CGEN_OPERAND_INSTANCE fmt_dmovr13h_ops[] = {
1275 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1276 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1277 { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1278 { 0 }
1279 };
1280
1281 static const CGEN_OPERAND_INSTANCE fmt_dmovr13b_ops[] = {
1282 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1283 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1284 { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1285 { 0 }
1286 };
1287
1288 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pi_ops[] = {
1289 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1290 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1291 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1292 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1293 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1294 { 0 }
1295 };
1296
1297 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pih_ops[] = {
1298 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1299 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1300 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1301 { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1302 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1303 { 0 }
1304 };
1305
1306 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pib_ops[] = {
1307 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1308 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1309 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1310 { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1311 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1312 { 0 }
1313 };
1314
1315 static const CGEN_OPERAND_INSTANCE fmt_dmovr15pi_ops[] = {
1316 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1317 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1318 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1319 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1320 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1321 { 0 }
1322 };
1323
1324 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13_ops[] = {
1325 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1326 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1327 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1328 { 0 }
1329 };
1330
1331 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13h_ops[] = {
1332 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1333 { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1334 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1335 { 0 }
1336 };
1337
1338 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13b_ops[] = {
1339 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1340 { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1341 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1342 { 0 }
1343 };
1344
1345 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pi_ops[] = {
1346 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1347 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1348 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1349 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1350 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1351 { 0 }
1352 };
1353
1354 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pih_ops[] = {
1355 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1356 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1357 { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1358 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1359 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1360 { 0 }
1361 };
1362
1363 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pib_ops[] = {
1364 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1365 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1366 { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1367 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1368 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1369 { 0 }
1370 };
1371
1372 static const CGEN_OPERAND_INSTANCE fmt_dmov2r15pd_ops[] = {
1373 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1374 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1375 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1376 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1377 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1378 { 0 }
1379 };
1380
1381 static const CGEN_OPERAND_INSTANCE fmt_ldres_ops[] = {
1382 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1383 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1384 { 0 }
1385 };
1386
1387 static const CGEN_OPERAND_INSTANCE fmt_andccr_ops[] = {
1388 { INPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1389 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1390 { OUTPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1391 { 0 }
1392 };
1393
1394 static const CGEN_OPERAND_INSTANCE fmt_stilm_ops[] = {
1395 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1396 { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
1397 { 0 }
1398 };
1399
1400 static const CGEN_OPERAND_INSTANCE fmt_addsp_ops[] = {
1401 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1402 { INPUT, "s10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (S10), 0, 0 },
1403 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1404 { 0 }
1405 };
1406
1407 static const CGEN_OPERAND_INSTANCE fmt_extsb_ops[] = {
1408 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RI), 0, 0 },
1409 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1410 { 0 }
1411 };
1412
1413 static const CGEN_OPERAND_INSTANCE fmt_extub_ops[] = {
1414 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UQI, & OP_ENT (RI), 0, 0 },
1415 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1416 { 0 }
1417 };
1418
1419 static const CGEN_OPERAND_INSTANCE fmt_extsh_ops[] = {
1420 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RI), 0, 0 },
1421 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1422 { 0 }
1423 };
1424
1425 static const CGEN_OPERAND_INSTANCE fmt_extuh_ops[] = {
1426 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UHI, & OP_ENT (RI), 0, 0 },
1427 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1428 { 0 }
1429 };
1430
1431 static const CGEN_OPERAND_INSTANCE fmt_ldm0_ops[] = {
1432 { INPUT, "reglist_low_ld", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW_LD), 0, 0 },
1433 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1434 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1435 { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
1436 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1437 { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, COND_REF },
1438 { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, COND_REF },
1439 { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, COND_REF },
1440 { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, COND_REF },
1441 { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, COND_REF },
1442 { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, COND_REF },
1443 { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, COND_REF },
1444 { 0 }
1445 };
1446
1447 static const CGEN_OPERAND_INSTANCE fmt_ldm1_ops[] = {
1448 { INPUT, "reglist_hi_ld", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_HI_LD), 0, 0 },
1449 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1450 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1451 { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, COND_REF },
1452 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1453 { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, COND_REF },
1454 { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, COND_REF },
1455 { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, COND_REF },
1456 { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, COND_REF },
1457 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, COND_REF },
1458 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
1459 { 0 }
1460 };
1461
1462 static const CGEN_OPERAND_INSTANCE fmt_stm0_ops[] = {
1463 { INPUT, "reglist_low_st", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW_ST), 0, 0 },
1464 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1465 { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, COND_REF },
1466 { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, COND_REF },
1467 { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, COND_REF },
1468 { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, COND_REF },
1469 { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, COND_REF },
1470 { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, COND_REF },
1471 { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, COND_REF },
1472 { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
1473 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1474 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1475 { 0 }
1476 };
1477
1478 static const CGEN_OPERAND_INSTANCE fmt_stm1_ops[] = {
1479 { INPUT, "reglist_hi_st", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_HI_ST), 0, 0 },
1480 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1481 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
1482 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, COND_REF },
1483 { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, COND_REF },
1484 { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, COND_REF },
1485 { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, COND_REF },
1486 { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, COND_REF },
1487 { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, COND_REF },
1488 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1489 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1490 { 0 }
1491 };
1492
1493 static const CGEN_OPERAND_INSTANCE fmt_enter_ops[] = {
1494 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1495 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1496 { INPUT, "u10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U10), 0, 0 },
1497 { OUTPUT, "h_memory_tmp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1498 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1499 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1500 { 0 }
1501 };
1502
1503 static const CGEN_OPERAND_INSTANCE fmt_leave_ops[] = {
1504 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1505 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1506 { INPUT, "h_memory_sub__VM_reg__VM_h_gr_15_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1507 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1508 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1509 { 0 }
1510 };
1511
1512 static const CGEN_OPERAND_INSTANCE fmt_xchb_ops[] = {
1513 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1514 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1515 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
1516 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1517 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
1518 { 0 }
1519 };
1520
1521 #undef INPUT
1522 #undef OUTPUT
1523 #undef COND_REF
1524
1525 /* Instruction formats. */
1526
1527 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
1528
1529 static const CGEN_IFMT fmt_empty = {
1530 0, 0, 0x0, { 0 }
1531 };
1532
1533 static const CGEN_IFMT fmt_add = {
1534 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1535 };
1536
1537 static const CGEN_IFMT fmt_addi = {
1538 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1539 };
1540
1541 static const CGEN_IFMT fmt_add2 = {
1542 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1543 };
1544
1545 static const CGEN_IFMT fmt_addc = {
1546 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1547 };
1548
1549 static const CGEN_IFMT fmt_addn = {
1550 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1551 };
1552
1553 static const CGEN_IFMT fmt_addni = {
1554 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1555 };
1556
1557 static const CGEN_IFMT fmt_addn2 = {
1558 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1559 };
1560
1561 static const CGEN_IFMT fmt_cmp = {
1562 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1563 };
1564
1565 static const CGEN_IFMT fmt_cmpi = {
1566 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1567 };
1568
1569 static const CGEN_IFMT fmt_cmp2 = {
1570 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1571 };
1572
1573 static const CGEN_IFMT fmt_and = {
1574 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1575 };
1576
1577 static const CGEN_IFMT fmt_andm = {
1578 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1579 };
1580
1581 static const CGEN_IFMT fmt_andh = {
1582 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1583 };
1584
1585 static const CGEN_IFMT fmt_andb = {
1586 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1587 };
1588
1589 static const CGEN_IFMT fmt_bandl = {
1590 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1591 };
1592
1593 static const CGEN_IFMT fmt_btstl = {
1594 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1595 };
1596
1597 static const CGEN_IFMT fmt_mul = {
1598 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1599 };
1600
1601 static const CGEN_IFMT fmt_mulu = {
1602 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1603 };
1604
1605 static const CGEN_IFMT fmt_mulh = {
1606 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1607 };
1608
1609 static const CGEN_IFMT fmt_div0s = {
1610 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1611 };
1612
1613 static const CGEN_IFMT fmt_div0u = {
1614 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1615 };
1616
1617 static const CGEN_IFMT fmt_div1 = {
1618 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1619 };
1620
1621 static const CGEN_IFMT fmt_div2 = {
1622 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1623 };
1624
1625 static const CGEN_IFMT fmt_div3 = {
1626 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1627 };
1628
1629 static const CGEN_IFMT fmt_div4s = {
1630 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1631 };
1632
1633 static const CGEN_IFMT fmt_lsl = {
1634 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1635 };
1636
1637 static const CGEN_IFMT fmt_lsli = {
1638 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1639 };
1640
1641 static const CGEN_IFMT fmt_ldi8 = {
1642 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
1643 };
1644
1645 static const CGEN_IFMT fmt_ldi20 = {
1646 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
1647 };
1648
1649 static const CGEN_IFMT fmt_ldi32 = {
1650 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1651 };
1652
1653 static const CGEN_IFMT fmt_ld = {
1654 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1655 };
1656
1657 static const CGEN_IFMT fmt_lduh = {
1658 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1659 };
1660
1661 static const CGEN_IFMT fmt_ldub = {
1662 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1663 };
1664
1665 static const CGEN_IFMT fmt_ldr13 = {
1666 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1667 };
1668
1669 static const CGEN_IFMT fmt_ldr13uh = {
1670 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1671 };
1672
1673 static const CGEN_IFMT fmt_ldr13ub = {
1674 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1675 };
1676
1677 static const CGEN_IFMT fmt_ldr14 = {
1678 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1679 };
1680
1681 static const CGEN_IFMT fmt_ldr14uh = {
1682 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1683 };
1684
1685 static const CGEN_IFMT fmt_ldr14ub = {
1686 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1687 };
1688
1689 static const CGEN_IFMT fmt_ldr15 = {
1690 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1691 };
1692
1693 static const CGEN_IFMT fmt_ldr15gr = {
1694 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1695 };
1696
1697 static const CGEN_IFMT fmt_ldr15dr = {
1698 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1699 };
1700
1701 static const CGEN_IFMT fmt_ldr15ps = {
1702 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1703 };
1704
1705 static const CGEN_IFMT fmt_st = {
1706 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1707 };
1708
1709 static const CGEN_IFMT fmt_sth = {
1710 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1711 };
1712
1713 static const CGEN_IFMT fmt_stb = {
1714 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1715 };
1716
1717 static const CGEN_IFMT fmt_str13 = {
1718 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1719 };
1720
1721 static const CGEN_IFMT fmt_str13h = {
1722 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1723 };
1724
1725 static const CGEN_IFMT fmt_str13b = {
1726 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1727 };
1728
1729 static const CGEN_IFMT fmt_str14 = {
1730 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1731 };
1732
1733 static const CGEN_IFMT fmt_str14h = {
1734 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1735 };
1736
1737 static const CGEN_IFMT fmt_str14b = {
1738 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1739 };
1740
1741 static const CGEN_IFMT fmt_str15 = {
1742 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1743 };
1744
1745 static const CGEN_IFMT fmt_str15gr = {
1746 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1747 };
1748
1749 static const CGEN_IFMT fmt_str15dr = {
1750 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1751 };
1752
1753 static const CGEN_IFMT fmt_str15ps = {
1754 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1755 };
1756
1757 static const CGEN_IFMT fmt_mov = {
1758 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1759 };
1760
1761 static const CGEN_IFMT fmt_movdr = {
1762 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1763 };
1764
1765 static const CGEN_IFMT fmt_movps = {
1766 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1767 };
1768
1769 static const CGEN_IFMT fmt_mov2dr = {
1770 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1771 };
1772
1773 static const CGEN_IFMT fmt_mov2ps = {
1774 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1775 };
1776
1777 static const CGEN_IFMT fmt_jmp = {
1778 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1779 };
1780
1781 static const CGEN_IFMT fmt_callr = {
1782 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1783 };
1784
1785 static const CGEN_IFMT fmt_call = {
1786 16, 16, 0xf800, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
1787 };
1788
1789 static const CGEN_IFMT fmt_ret = {
1790 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1791 };
1792
1793 static const CGEN_IFMT fmt_int = {
1794 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1795 };
1796
1797 static const CGEN_IFMT fmt_inte = {
1798 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1799 };
1800
1801 static const CGEN_IFMT fmt_reti = {
1802 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1803 };
1804
1805 static const CGEN_IFMT fmt_brad = {
1806 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1807 };
1808
1809 static const CGEN_IFMT fmt_beqd = {
1810 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1811 };
1812
1813 static const CGEN_IFMT fmt_bcd = {
1814 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1815 };
1816
1817 static const CGEN_IFMT fmt_bnd = {
1818 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1819 };
1820
1821 static const CGEN_IFMT fmt_bvd = {
1822 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1823 };
1824
1825 static const CGEN_IFMT fmt_bltd = {
1826 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1827 };
1828
1829 static const CGEN_IFMT fmt_bled = {
1830 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1831 };
1832
1833 static const CGEN_IFMT fmt_blsd = {
1834 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1835 };
1836
1837 static const CGEN_IFMT fmt_dmovr13 = {
1838 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1839 };
1840
1841 static const CGEN_IFMT fmt_dmovr13h = {
1842 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1843 };
1844
1845 static const CGEN_IFMT fmt_dmovr13b = {
1846 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1847 };
1848
1849 static const CGEN_IFMT fmt_dmovr13pi = {
1850 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1851 };
1852
1853 static const CGEN_IFMT fmt_dmovr13pih = {
1854 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1855 };
1856
1857 static const CGEN_IFMT fmt_dmovr13pib = {
1858 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1859 };
1860
1861 static const CGEN_IFMT fmt_dmovr15pi = {
1862 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1863 };
1864
1865 static const CGEN_IFMT fmt_dmov2r13 = {
1866 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1867 };
1868
1869 static const CGEN_IFMT fmt_dmov2r13h = {
1870 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1871 };
1872
1873 static const CGEN_IFMT fmt_dmov2r13b = {
1874 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1875 };
1876
1877 static const CGEN_IFMT fmt_dmov2r13pi = {
1878 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1879 };
1880
1881 static const CGEN_IFMT fmt_dmov2r13pih = {
1882 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1883 };
1884
1885 static const CGEN_IFMT fmt_dmov2r13pib = {
1886 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1887 };
1888
1889 static const CGEN_IFMT fmt_dmov2r15pd = {
1890 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1891 };
1892
1893 static const CGEN_IFMT fmt_ldres = {
1894 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1895 };
1896
1897 static const CGEN_IFMT fmt_copop = {
1898 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
1899 };
1900
1901 static const CGEN_IFMT fmt_copld = {
1902 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
1903 };
1904
1905 static const CGEN_IFMT fmt_copst = {
1906 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
1907 };
1908
1909 static const CGEN_IFMT fmt_nop = {
1910 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1911 };
1912
1913 static const CGEN_IFMT fmt_andccr = {
1914 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1915 };
1916
1917 static const CGEN_IFMT fmt_stilm = {
1918 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1919 };
1920
1921 static const CGEN_IFMT fmt_addsp = {
1922 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
1923 };
1924
1925 static const CGEN_IFMT fmt_extsb = {
1926 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1927 };
1928
1929 static const CGEN_IFMT fmt_extub = {
1930 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1931 };
1932
1933 static const CGEN_IFMT fmt_extsh = {
1934 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1935 };
1936
1937 static const CGEN_IFMT fmt_extuh = {
1938 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1939 };
1940
1941 static const CGEN_IFMT fmt_ldm0 = {
1942 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_LD), 0 }
1943 };
1944
1945 static const CGEN_IFMT fmt_ldm1 = {
1946 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_LD), 0 }
1947 };
1948
1949 static const CGEN_IFMT fmt_stm0 = {
1950 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_ST), 0 }
1951 };
1952
1953 static const CGEN_IFMT fmt_stm1 = {
1954 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_ST), 0 }
1955 };
1956
1957 static const CGEN_IFMT fmt_enter = {
1958 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
1959 };
1960
1961 static const CGEN_IFMT fmt_leave = {
1962 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1963 };
1964
1965 static const CGEN_IFMT fmt_xchb = {
1966 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1967 };
1968
1969 #undef F
1970
1971 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1972 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1973 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1974
1975 /* The instruction table.
1976 This is currently non-static because the simulator accesses it
1977 directly. */
1978
1979 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
1980 {
1981 /* Special null first entry.
1982 A `num' value of zero is thus invalid.
1983 Also, the special `invalid' insn resides here. */
1984 { { 0 }, 0 },
1985 /* add $Rj,$Ri */
1986 {
1987 { 1, 1, 1, 1 },
1988 FR30_INSN_ADD, "add", "add",
1989 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1990 & fmt_add, { 0xa600 },
1991 (PTR) & fmt_add_ops[0],
1992 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1993 },
1994 /* add $u4,$Ri */
1995 {
1996 { 1, 1, 1, 1 },
1997 FR30_INSN_ADDI, "addi", "add",
1998 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1999 & fmt_addi, { 0xa400 },
2000 (PTR) & fmt_addi_ops[0],
2001 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2002 },
2003 /* add2 $m4,$Ri */
2004 {
2005 { 1, 1, 1, 1 },
2006 FR30_INSN_ADD2, "add2", "add2",
2007 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
2008 & fmt_add2, { 0xa500 },
2009 (PTR) & fmt_add2_ops[0],
2010 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2011 },
2012 /* addc $Rj,$Ri */
2013 {
2014 { 1, 1, 1, 1 },
2015 FR30_INSN_ADDC, "addc", "addc",
2016 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2017 & fmt_addc, { 0xa700 },
2018 (PTR) & fmt_addc_ops[0],
2019 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2020 },
2021 /* addn $Rj,$Ri */
2022 {
2023 { 1, 1, 1, 1 },
2024 FR30_INSN_ADDN, "addn", "addn",
2025 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2026 & fmt_addn, { 0xa200 },
2027 (PTR) & fmt_addn_ops[0],
2028 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2029 },
2030 /* addn $u4,$Ri */
2031 {
2032 { 1, 1, 1, 1 },
2033 FR30_INSN_ADDNI, "addni", "addn",
2034 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2035 & fmt_addni, { 0xa000 },
2036 (PTR) & fmt_addni_ops[0],
2037 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2038 },
2039 /* addn2 $m4,$Ri */
2040 {
2041 { 1, 1, 1, 1 },
2042 FR30_INSN_ADDN2, "addn2", "addn2",
2043 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
2044 & fmt_addn2, { 0xa100 },
2045 (PTR) & fmt_addn2_ops[0],
2046 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2047 },
2048 /* sub $Rj,$Ri */
2049 {
2050 { 1, 1, 1, 1 },
2051 FR30_INSN_SUB, "sub", "sub",
2052 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2053 & fmt_add, { 0xac00 },
2054 (PTR) & fmt_add_ops[0],
2055 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2056 },
2057 /* subc $Rj,$Ri */
2058 {
2059 { 1, 1, 1, 1 },
2060 FR30_INSN_SUBC, "subc", "subc",
2061 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2062 & fmt_addc, { 0xad00 },
2063 (PTR) & fmt_addc_ops[0],
2064 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2065 },
2066 /* subn $Rj,$Ri */
2067 {
2068 { 1, 1, 1, 1 },
2069 FR30_INSN_SUBN, "subn", "subn",
2070 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2071 & fmt_addn, { 0xae00 },
2072 (PTR) & fmt_addn_ops[0],
2073 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2074 },
2075 /* cmp $Rj,$Ri */
2076 {
2077 { 1, 1, 1, 1 },
2078 FR30_INSN_CMP, "cmp", "cmp",
2079 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2080 & fmt_cmp, { 0xaa00 },
2081 (PTR) & fmt_cmp_ops[0],
2082 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2083 },
2084 /* cmp $u4,$Ri */
2085 {
2086 { 1, 1, 1, 1 },
2087 FR30_INSN_CMPI, "cmpi", "cmp",
2088 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2089 & fmt_cmpi, { 0xa800 },
2090 (PTR) & fmt_cmpi_ops[0],
2091 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2092 },
2093 /* cmp2 $m4,$Ri */
2094 {
2095 { 1, 1, 1, 1 },
2096 FR30_INSN_CMP2, "cmp2", "cmp2",
2097 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
2098 & fmt_cmp2, { 0xa900 },
2099 (PTR) & fmt_cmp2_ops[0],
2100 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2101 },
2102 /* and $Rj,$Ri */
2103 {
2104 { 1, 1, 1, 1 },
2105 FR30_INSN_AND, "and", "and",
2106 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2107 & fmt_and, { 0x8200 },
2108 (PTR) & fmt_and_ops[0],
2109 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2110 },
2111 /* or $Rj,$Ri */
2112 {
2113 { 1, 1, 1, 1 },
2114 FR30_INSN_OR, "or", "or",
2115 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2116 & fmt_and, { 0x9200 },
2117 (PTR) & fmt_and_ops[0],
2118 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2119 },
2120 /* eor $Rj,$Ri */
2121 {
2122 { 1, 1, 1, 1 },
2123 FR30_INSN_EOR, "eor", "eor",
2124 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2125 & fmt_and, { 0x9a00 },
2126 (PTR) & fmt_and_ops[0],
2127 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2128 },
2129 /* and $Rj,@$Ri */
2130 {
2131 { 1, 1, 1, 1 },
2132 FR30_INSN_ANDM, "andm", "and",
2133 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2134 & fmt_andm, { 0x8400 },
2135 (PTR) & fmt_andm_ops[0],
2136 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2137 },
2138 /* andh $Rj,@$Ri */
2139 {
2140 { 1, 1, 1, 1 },
2141 FR30_INSN_ANDH, "andh", "andh",
2142 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2143 & fmt_andh, { 0x8500 },
2144 (PTR) & fmt_andh_ops[0],
2145 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2146 },
2147 /* andb $Rj,@$Ri */
2148 {
2149 { 1, 1, 1, 1 },
2150 FR30_INSN_ANDB, "andb", "andb",
2151 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2152 & fmt_andb, { 0x8600 },
2153 (PTR) & fmt_andb_ops[0],
2154 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2155 },
2156 /* or $Rj,@$Ri */
2157 {
2158 { 1, 1, 1, 1 },
2159 FR30_INSN_ORM, "orm", "or",
2160 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2161 & fmt_andm, { 0x9400 },
2162 (PTR) & fmt_andm_ops[0],
2163 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2164 },
2165 /* orh $Rj,@$Ri */
2166 {
2167 { 1, 1, 1, 1 },
2168 FR30_INSN_ORH, "orh", "orh",
2169 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2170 & fmt_andh, { 0x9500 },
2171 (PTR) & fmt_andh_ops[0],
2172 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2173 },
2174 /* orb $Rj,@$Ri */
2175 {
2176 { 1, 1, 1, 1 },
2177 FR30_INSN_ORB, "orb", "orb",
2178 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2179 & fmt_andb, { 0x9600 },
2180 (PTR) & fmt_andb_ops[0],
2181 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2182 },
2183 /* eor $Rj,@$Ri */
2184 {
2185 { 1, 1, 1, 1 },
2186 FR30_INSN_EORM, "eorm", "eor",
2187 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2188 & fmt_andm, { 0x9c00 },
2189 (PTR) & fmt_andm_ops[0],
2190 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2191 },
2192 /* eorh $Rj,@$Ri */
2193 {
2194 { 1, 1, 1, 1 },
2195 FR30_INSN_EORH, "eorh", "eorh",
2196 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2197 & fmt_andh, { 0x9d00 },
2198 (PTR) & fmt_andh_ops[0],
2199 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2200 },
2201 /* eorb $Rj,@$Ri */
2202 {
2203 { 1, 1, 1, 1 },
2204 FR30_INSN_EORB, "eorb", "eorb",
2205 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2206 & fmt_andb, { 0x9e00 },
2207 (PTR) & fmt_andb_ops[0],
2208 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2209 },
2210 /* bandl $u4,@$Ri */
2211 {
2212 { 1, 1, 1, 1 },
2213 FR30_INSN_BANDL, "bandl", "bandl",
2214 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2215 & fmt_bandl, { 0x8000 },
2216 (PTR) & fmt_bandl_ops[0],
2217 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2218 },
2219 /* borl $u4,@$Ri */
2220 {
2221 { 1, 1, 1, 1 },
2222 FR30_INSN_BORL, "borl", "borl",
2223 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2224 & fmt_bandl, { 0x9000 },
2225 (PTR) & fmt_bandl_ops[0],
2226 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2227 },
2228 /* beorl $u4,@$Ri */
2229 {
2230 { 1, 1, 1, 1 },
2231 FR30_INSN_BEORL, "beorl", "beorl",
2232 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2233 & fmt_bandl, { 0x9800 },
2234 (PTR) & fmt_bandl_ops[0],
2235 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2236 },
2237 /* bandh $u4,@$Ri */
2238 {
2239 { 1, 1, 1, 1 },
2240 FR30_INSN_BANDH, "bandh", "bandh",
2241 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2242 & fmt_bandl, { 0x8100 },
2243 (PTR) & fmt_bandl_ops[0],
2244 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2245 },
2246 /* borh $u4,@$Ri */
2247 {
2248 { 1, 1, 1, 1 },
2249 FR30_INSN_BORH, "borh", "borh",
2250 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2251 & fmt_bandl, { 0x9100 },
2252 (PTR) & fmt_bandl_ops[0],
2253 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2254 },
2255 /* beorh $u4,@$Ri */
2256 {
2257 { 1, 1, 1, 1 },
2258 FR30_INSN_BEORH, "beorh", "beorh",
2259 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2260 & fmt_bandl, { 0x9900 },
2261 (PTR) & fmt_bandl_ops[0],
2262 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2263 },
2264 /* btstl $u4,@$Ri */
2265 {
2266 { 1, 1, 1, 1 },
2267 FR30_INSN_BTSTL, "btstl", "btstl",
2268 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2269 & fmt_btstl, { 0x8800 },
2270 (PTR) & fmt_btstl_ops[0],
2271 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2272 },
2273 /* btsth $u4,@$Ri */
2274 {
2275 { 1, 1, 1, 1 },
2276 FR30_INSN_BTSTH, "btsth", "btsth",
2277 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2278 & fmt_btstl, { 0x8900 },
2279 (PTR) & fmt_btstl_ops[0],
2280 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2281 },
2282 /* mul $Rj,$Ri */
2283 {
2284 { 1, 1, 1, 1 },
2285 FR30_INSN_MUL, "mul", "mul",
2286 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2287 & fmt_mul, { 0xaf00 },
2288 (PTR) & fmt_mul_ops[0],
2289 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2290 },
2291 /* mulu $Rj,$Ri */
2292 {
2293 { 1, 1, 1, 1 },
2294 FR30_INSN_MULU, "mulu", "mulu",
2295 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2296 & fmt_mulu, { 0xab00 },
2297 (PTR) & fmt_mulu_ops[0],
2298 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2299 },
2300 /* mulh $Rj,$Ri */
2301 {
2302 { 1, 1, 1, 1 },
2303 FR30_INSN_MULH, "mulh", "mulh",
2304 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2305 & fmt_mulh, { 0xbf00 },
2306 (PTR) & fmt_mulh_ops[0],
2307 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2308 },
2309 /* muluh $Rj,$Ri */
2310 {
2311 { 1, 1, 1, 1 },
2312 FR30_INSN_MULUH, "muluh", "muluh",
2313 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2314 & fmt_mulh, { 0xbb00 },
2315 (PTR) & fmt_mulh_ops[0],
2316 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2317 },
2318 /* div0s $Ri */
2319 {
2320 { 1, 1, 1, 1 },
2321 FR30_INSN_DIV0S, "div0s", "div0s",
2322 { { MNEM, ' ', OP (RI), 0 } },
2323 & fmt_div0s, { 0x9740 },
2324 (PTR) & fmt_div0s_ops[0],
2325 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2326 },
2327 /* div0u $Ri */
2328 {
2329 { 1, 1, 1, 1 },
2330 FR30_INSN_DIV0U, "div0u", "div0u",
2331 { { MNEM, ' ', OP (RI), 0 } },
2332 & fmt_div0u, { 0x9750 },
2333 (PTR) & fmt_div0u_ops[0],
2334 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2335 },
2336 /* div1 $Ri */
2337 {
2338 { 1, 1, 1, 1 },
2339 FR30_INSN_DIV1, "div1", "div1",
2340 { { MNEM, ' ', OP (RI), 0 } },
2341 & fmt_div1, { 0x9760 },
2342 (PTR) & fmt_div1_ops[0],
2343 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2344 },
2345 /* div2 $Ri */
2346 {
2347 { 1, 1, 1, 1 },
2348 FR30_INSN_DIV2, "div2", "div2",
2349 { { MNEM, ' ', OP (RI), 0 } },
2350 & fmt_div2, { 0x9770 },
2351 (PTR) & fmt_div2_ops[0],
2352 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2353 },
2354 /* div3 */
2355 {
2356 { 1, 1, 1, 1 },
2357 FR30_INSN_DIV3, "div3", "div3",
2358 { { MNEM, 0 } },
2359 & fmt_div3, { 0x9f60 },
2360 (PTR) & fmt_div3_ops[0],
2361 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2362 },
2363 /* div4s */
2364 {
2365 { 1, 1, 1, 1 },
2366 FR30_INSN_DIV4S, "div4s", "div4s",
2367 { { MNEM, 0 } },
2368 & fmt_div4s, { 0x9f70 },
2369 (PTR) & fmt_div4s_ops[0],
2370 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2371 },
2372 /* lsl $Rj,$Ri */
2373 {
2374 { 1, 1, 1, 1 },
2375 FR30_INSN_LSL, "lsl", "lsl",
2376 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2377 & fmt_lsl, { 0xb600 },
2378 (PTR) & fmt_lsl_ops[0],
2379 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2380 },
2381 /* lsl $u4,$Ri */
2382 {
2383 { 1, 1, 1, 1 },
2384 FR30_INSN_LSLI, "lsli", "lsl",
2385 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2386 & fmt_lsli, { 0xb400 },
2387 (PTR) & fmt_lsli_ops[0],
2388 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2389 },
2390 /* lsl2 $u4,$Ri */
2391 {
2392 { 1, 1, 1, 1 },
2393 FR30_INSN_LSL2, "lsl2", "lsl2",
2394 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2395 & fmt_lsli, { 0xb500 },
2396 (PTR) & fmt_lsli_ops[0],
2397 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2398 },
2399 /* lsr $Rj,$Ri */
2400 {
2401 { 1, 1, 1, 1 },
2402 FR30_INSN_LSR, "lsr", "lsr",
2403 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2404 & fmt_lsl, { 0xb200 },
2405 (PTR) & fmt_lsl_ops[0],
2406 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2407 },
2408 /* lsr $u4,$Ri */
2409 {
2410 { 1, 1, 1, 1 },
2411 FR30_INSN_LSRI, "lsri", "lsr",
2412 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2413 & fmt_lsli, { 0xb000 },
2414 (PTR) & fmt_lsli_ops[0],
2415 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2416 },
2417 /* lsr2 $u4,$Ri */
2418 {
2419 { 1, 1, 1, 1 },
2420 FR30_INSN_LSR2, "lsr2", "lsr2",
2421 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2422 & fmt_lsli, { 0xb100 },
2423 (PTR) & fmt_lsli_ops[0],
2424 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2425 },
2426 /* asr $Rj,$Ri */
2427 {
2428 { 1, 1, 1, 1 },
2429 FR30_INSN_ASR, "asr", "asr",
2430 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2431 & fmt_lsl, { 0xba00 },
2432 (PTR) & fmt_lsl_ops[0],
2433 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2434 },
2435 /* asr $u4,$Ri */
2436 {
2437 { 1, 1, 1, 1 },
2438 FR30_INSN_ASRI, "asri", "asr",
2439 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2440 & fmt_lsli, { 0xb800 },
2441 (PTR) & fmt_lsli_ops[0],
2442 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2443 },
2444 /* asr2 $u4,$Ri */
2445 {
2446 { 1, 1, 1, 1 },
2447 FR30_INSN_ASR2, "asr2", "asr2",
2448 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2449 & fmt_lsli, { 0xb900 },
2450 (PTR) & fmt_lsli_ops[0],
2451 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2452 },
2453 /* ldi:8 $i8,$Ri */
2454 {
2455 { 1, 1, 1, 1 },
2456 FR30_INSN_LDI8, "ldi8", "ldi:8",
2457 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
2458 & fmt_ldi8, { 0xc000 },
2459 (PTR) & fmt_ldi8_ops[0],
2460 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2461 },
2462 /* ldi:20 $i20,$Ri */
2463 {
2464 { 1, 1, 1, 1 },
2465 FR30_INSN_LDI20, "ldi20", "ldi:20",
2466 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
2467 & fmt_ldi20, { 0x9b00 },
2468 (PTR) & fmt_ldi20_ops[0],
2469 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2470 },
2471 /* ldi:32 $i32,$Ri */
2472 {
2473 { 1, 1, 1, 1 },
2474 FR30_INSN_LDI32, "ldi32", "ldi:32",
2475 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2476 & fmt_ldi32, { 0x9f80 },
2477 (PTR) & fmt_ldi32_ops[0],
2478 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2479 },
2480 /* ld @$Rj,$Ri */
2481 {
2482 { 1, 1, 1, 1 },
2483 FR30_INSN_LD, "ld", "ld",
2484 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2485 & fmt_ld, { 0x400 },
2486 (PTR) & fmt_ld_ops[0],
2487 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2488 },
2489 /* lduh @$Rj,$Ri */
2490 {
2491 { 1, 1, 1, 1 },
2492 FR30_INSN_LDUH, "lduh", "lduh",
2493 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2494 & fmt_lduh, { 0x500 },
2495 (PTR) & fmt_lduh_ops[0],
2496 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2497 },
2498 /* ldub @$Rj,$Ri */
2499 {
2500 { 1, 1, 1, 1 },
2501 FR30_INSN_LDUB, "ldub", "ldub",
2502 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2503 & fmt_ldub, { 0x600 },
2504 (PTR) & fmt_ldub_ops[0],
2505 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2506 },
2507 /* ld @($R13,$Rj),$Ri */
2508 {
2509 { 1, 1, 1, 1 },
2510 FR30_INSN_LDR13, "ldr13", "ld",
2511 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2512 & fmt_ldr13, { 0x0 },
2513 (PTR) & fmt_ldr13_ops[0],
2514 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2515 },
2516 /* lduh @($R13,$Rj),$Ri */
2517 {
2518 { 1, 1, 1, 1 },
2519 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
2520 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2521 & fmt_ldr13uh, { 0x100 },
2522 (PTR) & fmt_ldr13uh_ops[0],
2523 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2524 },
2525 /* ldub @($R13,$Rj),$Ri */
2526 {
2527 { 1, 1, 1, 1 },
2528 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
2529 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2530 & fmt_ldr13ub, { 0x200 },
2531 (PTR) & fmt_ldr13ub_ops[0],
2532 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2533 },
2534 /* ld @($R14,$disp10),$Ri */
2535 {
2536 { 1, 1, 1, 1 },
2537 FR30_INSN_LDR14, "ldr14", "ld",
2538 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
2539 & fmt_ldr14, { 0x2000 },
2540 (PTR) & fmt_ldr14_ops[0],
2541 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2542 },
2543 /* lduh @($R14,$disp9),$Ri */
2544 {
2545 { 1, 1, 1, 1 },
2546 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
2547 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
2548 & fmt_ldr14uh, { 0x4000 },
2549 (PTR) & fmt_ldr14uh_ops[0],
2550 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2551 },
2552 /* ldub @($R14,$disp8),$Ri */
2553 {
2554 { 1, 1, 1, 1 },
2555 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
2556 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
2557 & fmt_ldr14ub, { 0x6000 },
2558 (PTR) & fmt_ldr14ub_ops[0],
2559 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2560 },
2561 /* ld @($R15,$udisp6),$Ri */
2562 {
2563 { 1, 1, 1, 1 },
2564 FR30_INSN_LDR15, "ldr15", "ld",
2565 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
2566 & fmt_ldr15, { 0x300 },
2567 (PTR) & fmt_ldr15_ops[0],
2568 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2569 },
2570 /* ld @$R15+,$Ri */
2571 {
2572 { 1, 1, 1, 1 },
2573 FR30_INSN_LDR15GR, "ldr15gr", "ld",
2574 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
2575 & fmt_ldr15gr, { 0x700 },
2576 (PTR) & fmt_ldr15gr_ops[0],
2577 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2578 },
2579 /* ld @$R15+,$Rs2 */
2580 {
2581 { 1, 1, 1, 1 },
2582 FR30_INSN_LDR15DR, "ldr15dr", "ld",
2583 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
2584 & fmt_ldr15dr, { 0x780 },
2585 (PTR) & fmt_ldr15dr_ops[0],
2586 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2587 },
2588 /* ld @$R15+,$ps */
2589 {
2590 { 1, 1, 1, 1 },
2591 FR30_INSN_LDR15PS, "ldr15ps", "ld",
2592 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
2593 & fmt_ldr15ps, { 0x790 },
2594 (PTR) & fmt_ldr15ps_ops[0],
2595 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2596 },
2597 /* st $Ri,@$Rj */
2598 {
2599 { 1, 1, 1, 1 },
2600 FR30_INSN_ST, "st", "st",
2601 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2602 & fmt_st, { 0x1400 },
2603 (PTR) & fmt_st_ops[0],
2604 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2605 },
2606 /* sth $Ri,@$Rj */
2607 {
2608 { 1, 1, 1, 1 },
2609 FR30_INSN_STH, "sth", "sth",
2610 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2611 & fmt_sth, { 0x1500 },
2612 (PTR) & fmt_sth_ops[0],
2613 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2614 },
2615 /* stb $Ri,@$Rj */
2616 {
2617 { 1, 1, 1, 1 },
2618 FR30_INSN_STB, "stb", "stb",
2619 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2620 & fmt_stb, { 0x1600 },
2621 (PTR) & fmt_stb_ops[0],
2622 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2623 },
2624 /* st $Ri,@($R13,$Rj) */
2625 {
2626 { 1, 1, 1, 1 },
2627 FR30_INSN_STR13, "str13", "st",
2628 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2629 & fmt_str13, { 0x1000 },
2630 (PTR) & fmt_str13_ops[0],
2631 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2632 },
2633 /* sth $Ri,@($R13,$Rj) */
2634 {
2635 { 1, 1, 1, 1 },
2636 FR30_INSN_STR13H, "str13h", "sth",
2637 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2638 & fmt_str13h, { 0x1100 },
2639 (PTR) & fmt_str13h_ops[0],
2640 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2641 },
2642 /* stb $Ri,@($R13,$Rj) */
2643 {
2644 { 1, 1, 1, 1 },
2645 FR30_INSN_STR13B, "str13b", "stb",
2646 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2647 & fmt_str13b, { 0x1200 },
2648 (PTR) & fmt_str13b_ops[0],
2649 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2650 },
2651 /* st $Ri,@($R14,$disp10) */
2652 {
2653 { 1, 1, 1, 1 },
2654 FR30_INSN_STR14, "str14", "st",
2655 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
2656 & fmt_str14, { 0x3000 },
2657 (PTR) & fmt_str14_ops[0],
2658 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2659 },
2660 /* sth $Ri,@($R14,$disp9) */
2661 {
2662 { 1, 1, 1, 1 },
2663 FR30_INSN_STR14H, "str14h", "sth",
2664 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
2665 & fmt_str14h, { 0x5000 },
2666 (PTR) & fmt_str14h_ops[0],
2667 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2668 },
2669 /* stb $Ri,@($R14,$disp8) */
2670 {
2671 { 1, 1, 1, 1 },
2672 FR30_INSN_STR14B, "str14b", "stb",
2673 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
2674 & fmt_str14b, { 0x7000 },
2675 (PTR) & fmt_str14b_ops[0],
2676 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2677 },
2678 /* st $Ri,@($R15,$udisp6) */
2679 {
2680 { 1, 1, 1, 1 },
2681 FR30_INSN_STR15, "str15", "st",
2682 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
2683 & fmt_str15, { 0x1300 },
2684 (PTR) & fmt_str15_ops[0],
2685 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2686 },
2687 /* st $Ri,@-$R15 */
2688 {
2689 { 1, 1, 1, 1 },
2690 FR30_INSN_STR15GR, "str15gr", "st",
2691 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
2692 & fmt_str15gr, { 0x1700 },
2693 (PTR) & fmt_str15gr_ops[0],
2694 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2695 },
2696 /* st $Rs2,@-$R15 */
2697 {
2698 { 1, 1, 1, 1 },
2699 FR30_INSN_STR15DR, "str15dr", "st",
2700 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
2701 & fmt_str15dr, { 0x1780 },
2702 (PTR) & fmt_str15dr_ops[0],
2703 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2704 },
2705 /* st $ps,@-$R15 */
2706 {
2707 { 1, 1, 1, 1 },
2708 FR30_INSN_STR15PS, "str15ps", "st",
2709 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
2710 & fmt_str15ps, { 0x1790 },
2711 (PTR) & fmt_str15ps_ops[0],
2712 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2713 },
2714 /* mov $Rj,$Ri */
2715 {
2716 { 1, 1, 1, 1 },
2717 FR30_INSN_MOV, "mov", "mov",
2718 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2719 & fmt_mov, { 0x8b00 },
2720 (PTR) & fmt_mov_ops[0],
2721 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2722 },
2723 /* mov $Rs1,$Ri */
2724 {
2725 { 1, 1, 1, 1 },
2726 FR30_INSN_MOVDR, "movdr", "mov",
2727 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
2728 & fmt_movdr, { 0xb700 },
2729 (PTR) & fmt_movdr_ops[0],
2730 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2731 },
2732 /* mov $ps,$Ri */
2733 {
2734 { 1, 1, 1, 1 },
2735 FR30_INSN_MOVPS, "movps", "mov",
2736 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
2737 & fmt_movps, { 0x1710 },
2738 (PTR) & fmt_movps_ops[0],
2739 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2740 },
2741 /* mov $Ri,$Rs1 */
2742 {
2743 { 1, 1, 1, 1 },
2744 FR30_INSN_MOV2DR, "mov2dr", "mov",
2745 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
2746 & fmt_mov2dr, { 0xb300 },
2747 (PTR) & fmt_mov2dr_ops[0],
2748 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2749 },
2750 /* mov $Ri,$ps */
2751 {
2752 { 1, 1, 1, 1 },
2753 FR30_INSN_MOV2PS, "mov2ps", "mov",
2754 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
2755 & fmt_mov2ps, { 0x710 },
2756 (PTR) & fmt_mov2ps_ops[0],
2757 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2758 },
2759 /* jmp @$Ri */
2760 {
2761 { 1, 1, 1, 1 },
2762 FR30_INSN_JMP, "jmp", "jmp",
2763 { { MNEM, ' ', '@', OP (RI), 0 } },
2764 & fmt_jmp, { 0x9700 },
2765 (PTR) & fmt_jmp_ops[0],
2766 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2767 },
2768 /* jmp:d @$Ri */
2769 {
2770 { 1, 1, 1, 1 },
2771 FR30_INSN_JMPD, "jmpd", "jmp:d",
2772 { { MNEM, ' ', '@', OP (RI), 0 } },
2773 & fmt_jmp, { 0x9f00 },
2774 (PTR) & fmt_jmp_ops[0],
2775 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2776 },
2777 /* call @$Ri */
2778 {
2779 { 1, 1, 1, 1 },
2780 FR30_INSN_CALLR, "callr", "call",
2781 { { MNEM, ' ', '@', OP (RI), 0 } },
2782 & fmt_callr, { 0x9710 },
2783 (PTR) & fmt_callr_ops[0],
2784 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2785 },
2786 /* call:d @$Ri */
2787 {
2788 { 1, 1, 1, 1 },
2789 FR30_INSN_CALLRD, "callrd", "call:d",
2790 { { MNEM, ' ', '@', OP (RI), 0 } },
2791 & fmt_callr, { 0x9f10 },
2792 (PTR) & fmt_callr_ops[0],
2793 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2794 },
2795 /* call $label12 */
2796 {
2797 { 1, 1, 1, 1 },
2798 FR30_INSN_CALL, "call", "call",
2799 { { MNEM, ' ', OP (LABEL12), 0 } },
2800 & fmt_call, { 0xd000 },
2801 (PTR) & fmt_call_ops[0],
2802 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2803 },
2804 /* call:d $label12 */
2805 {
2806 { 1, 1, 1, 1 },
2807 FR30_INSN_CALLD, "calld", "call:d",
2808 { { MNEM, ' ', OP (LABEL12), 0 } },
2809 & fmt_call, { 0xd800 },
2810 (PTR) & fmt_call_ops[0],
2811 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2812 },
2813 /* ret */
2814 {
2815 { 1, 1, 1, 1 },
2816 FR30_INSN_RET, "ret", "ret",
2817 { { MNEM, 0 } },
2818 & fmt_ret, { 0x9720 },
2819 (PTR) & fmt_ret_ops[0],
2820 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2821 },
2822 /* ret:d */
2823 {
2824 { 1, 1, 1, 1 },
2825 FR30_INSN_RET_D, "ret:d", "ret:d",
2826 { { MNEM, 0 } },
2827 & fmt_ret, { 0x9f20 },
2828 (PTR) & fmt_ret_ops[0],
2829 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2830 },
2831 /* int $u8 */
2832 {
2833 { 1, 1, 1, 1 },
2834 FR30_INSN_INT, "int", "int",
2835 { { MNEM, ' ', OP (U8), 0 } },
2836 & fmt_int, { 0x1f00 },
2837 (PTR) & fmt_int_ops[0],
2838 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2839 },
2840 /* inte */
2841 {
2842 { 1, 1, 1, 1 },
2843 FR30_INSN_INTE, "inte", "inte",
2844 { { MNEM, 0 } },
2845 & fmt_inte, { 0x9f30 },
2846 (PTR) & fmt_inte_ops[0],
2847 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2848 },
2849 /* reti */
2850 {
2851 { 1, 1, 1, 1 },
2852 FR30_INSN_RETI, "reti", "reti",
2853 { { MNEM, 0 } },
2854 & fmt_reti, { 0x9730 },
2855 (PTR) & fmt_reti_ops[0],
2856 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2857 },
2858 /* bra:d $label9 */
2859 {
2860 { 1, 1, 1, 1 },
2861 FR30_INSN_BRAD, "brad", "bra:d",
2862 { { MNEM, ' ', OP (LABEL9), 0 } },
2863 & fmt_brad, { 0xf000 },
2864 (PTR) & fmt_brad_ops[0],
2865 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2866 },
2867 /* bra $label9 */
2868 {
2869 { 1, 1, 1, 1 },
2870 FR30_INSN_BRA, "bra", "bra",
2871 { { MNEM, ' ', OP (LABEL9), 0 } },
2872 & fmt_brad, { 0xe000 },
2873 (PTR) & fmt_brad_ops[0],
2874 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2875 },
2876 /* bno:d $label9 */
2877 {
2878 { 1, 1, 1, 1 },
2879 FR30_INSN_BNOD, "bnod", "bno:d",
2880 { { MNEM, ' ', OP (LABEL9), 0 } },
2881 & fmt_brad, { 0xf100 },
2882 (PTR) & fmt_brad_ops[0],
2883 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2884 },
2885 /* bno $label9 */
2886 {
2887 { 1, 1, 1, 1 },
2888 FR30_INSN_BNO, "bno", "bno",
2889 { { MNEM, ' ', OP (LABEL9), 0 } },
2890 & fmt_brad, { 0xe100 },
2891 (PTR) & fmt_brad_ops[0],
2892 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2893 },
2894 /* beq:d $label9 */
2895 {
2896 { 1, 1, 1, 1 },
2897 FR30_INSN_BEQD, "beqd", "beq:d",
2898 { { MNEM, ' ', OP (LABEL9), 0 } },
2899 & fmt_beqd, { 0xf200 },
2900 (PTR) & fmt_beqd_ops[0],
2901 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2902 },
2903 /* beq $label9 */
2904 {
2905 { 1, 1, 1, 1 },
2906 FR30_INSN_BEQ, "beq", "beq",
2907 { { MNEM, ' ', OP (LABEL9), 0 } },
2908 & fmt_beqd, { 0xe200 },
2909 (PTR) & fmt_beqd_ops[0],
2910 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2911 },
2912 /* bne:d $label9 */
2913 {
2914 { 1, 1, 1, 1 },
2915 FR30_INSN_BNED, "bned", "bne:d",
2916 { { MNEM, ' ', OP (LABEL9), 0 } },
2917 & fmt_beqd, { 0xf300 },
2918 (PTR) & fmt_beqd_ops[0],
2919 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2920 },
2921 /* bne $label9 */
2922 {
2923 { 1, 1, 1, 1 },
2924 FR30_INSN_BNE, "bne", "bne",
2925 { { MNEM, ' ', OP (LABEL9), 0 } },
2926 & fmt_beqd, { 0xe300 },
2927 (PTR) & fmt_beqd_ops[0],
2928 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2929 },
2930 /* bc:d $label9 */
2931 {
2932 { 1, 1, 1, 1 },
2933 FR30_INSN_BCD, "bcd", "bc:d",
2934 { { MNEM, ' ', OP (LABEL9), 0 } },
2935 & fmt_bcd, { 0xf400 },
2936 (PTR) & fmt_bcd_ops[0],
2937 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2938 },
2939 /* bc $label9 */
2940 {
2941 { 1, 1, 1, 1 },
2942 FR30_INSN_BC, "bc", "bc",
2943 { { MNEM, ' ', OP (LABEL9), 0 } },
2944 & fmt_bcd, { 0xe400 },
2945 (PTR) & fmt_bcd_ops[0],
2946 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2947 },
2948 /* bnc:d $label9 */
2949 {
2950 { 1, 1, 1, 1 },
2951 FR30_INSN_BNCD, "bncd", "bnc:d",
2952 { { MNEM, ' ', OP (LABEL9), 0 } },
2953 & fmt_bcd, { 0xf500 },
2954 (PTR) & fmt_bcd_ops[0],
2955 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2956 },
2957 /* bnc $label9 */
2958 {
2959 { 1, 1, 1, 1 },
2960 FR30_INSN_BNC, "bnc", "bnc",
2961 { { MNEM, ' ', OP (LABEL9), 0 } },
2962 & fmt_bcd, { 0xe500 },
2963 (PTR) & fmt_bcd_ops[0],
2964 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2965 },
2966 /* bn:d $label9 */
2967 {
2968 { 1, 1, 1, 1 },
2969 FR30_INSN_BND, "bnd", "bn:d",
2970 { { MNEM, ' ', OP (LABEL9), 0 } },
2971 & fmt_bnd, { 0xf600 },
2972 (PTR) & fmt_bnd_ops[0],
2973 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2974 },
2975 /* bn $label9 */
2976 {
2977 { 1, 1, 1, 1 },
2978 FR30_INSN_BN, "bn", "bn",
2979 { { MNEM, ' ', OP (LABEL9), 0 } },
2980 & fmt_bnd, { 0xe600 },
2981 (PTR) & fmt_bnd_ops[0],
2982 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2983 },
2984 /* bp:d $label9 */
2985 {
2986 { 1, 1, 1, 1 },
2987 FR30_INSN_BPD, "bpd", "bp:d",
2988 { { MNEM, ' ', OP (LABEL9), 0 } },
2989 & fmt_bnd, { 0xf700 },
2990 (PTR) & fmt_bnd_ops[0],
2991 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2992 },
2993 /* bp $label9 */
2994 {
2995 { 1, 1, 1, 1 },
2996 FR30_INSN_BP, "bp", "bp",
2997 { { MNEM, ' ', OP (LABEL9), 0 } },
2998 & fmt_bnd, { 0xe700 },
2999 (PTR) & fmt_bnd_ops[0],
3000 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3001 },
3002 /* bv:d $label9 */
3003 {
3004 { 1, 1, 1, 1 },
3005 FR30_INSN_BVD, "bvd", "bv:d",
3006 { { MNEM, ' ', OP (LABEL9), 0 } },
3007 & fmt_bvd, { 0xf800 },
3008 (PTR) & fmt_bvd_ops[0],
3009 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
3010 },
3011 /* bv $label9 */
3012 {
3013 { 1, 1, 1, 1 },
3014 FR30_INSN_BV, "bv", "bv",
3015 { { MNEM, ' ', OP (LABEL9), 0 } },
3016 & fmt_bvd, { 0xe800 },
3017 (PTR) & fmt_bvd_ops[0],
3018 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3019 },
3020 /* bnv:d $label9 */
3021 {
3022 { 1, 1, 1, 1 },
3023 FR30_INSN_BNVD, "bnvd", "bnv:d",
3024 { { MNEM, ' ', OP (LABEL9), 0 } },
3025 & fmt_bvd, { 0xf900 },
3026 (PTR) & fmt_bvd_ops[0],
3027 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
3028 },
3029 /* bnv $label9 */
3030 {
3031 { 1, 1, 1, 1 },
3032 FR30_INSN_BNV, "bnv", "bnv",
3033 { { MNEM, ' ', OP (LABEL9), 0 } },
3034 & fmt_bvd, { 0xe900 },
3035 (PTR) & fmt_bvd_ops[0],
3036 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3037 },
3038 /* blt:d $label9 */
3039 {
3040 { 1, 1, 1, 1 },
3041 FR30_INSN_BLTD, "bltd", "blt:d",
3042 { { MNEM, ' ', OP (LABEL9), 0 } },
3043 & fmt_bltd, { 0xfa00 },
3044 (PTR) & fmt_bltd_ops[0],
3045 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
3046 },
3047 /* blt $label9 */
3048 {
3049 { 1, 1, 1, 1 },
3050 FR30_INSN_BLT, "blt", "blt",
3051 { { MNEM, ' ', OP (LABEL9), 0 } },
3052 & fmt_bltd, { 0xea00 },
3053 (PTR) & fmt_bltd_ops[0],
3054 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3055 },
3056 /* bge:d $label9 */
3057 {
3058 { 1, 1, 1, 1 },
3059 FR30_INSN_BGED, "bged", "bge:d",
3060 { { MNEM, ' ', OP (LABEL9), 0 } },
3061 & fmt_bltd, { 0xfb00 },
3062 (PTR) & fmt_bltd_ops[0],
3063 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
3064 },
3065 /* bge $label9 */
3066 {
3067 { 1, 1, 1, 1 },
3068 FR30_INSN_BGE, "bge", "bge",
3069 { { MNEM, ' ', OP (LABEL9), 0 } },
3070 & fmt_bltd, { 0xeb00 },
3071 (PTR) & fmt_bltd_ops[0],
3072 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3073 },
3074 /* ble:d $label9 */
3075 {
3076 { 1, 1, 1, 1 },
3077 FR30_INSN_BLED, "bled", "ble:d",
3078 { { MNEM, ' ', OP (LABEL9), 0 } },
3079 & fmt_bled, { 0xfc00 },
3080 (PTR) & fmt_bled_ops[0],
3081 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
3082 },
3083 /* ble $label9 */
3084 {
3085 { 1, 1, 1, 1 },
3086 FR30_INSN_BLE, "ble", "ble",
3087 { { MNEM, ' ', OP (LABEL9), 0 } },
3088 & fmt_bled, { 0xec00 },
3089 (PTR) & fmt_bled_ops[0],
3090 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3091 },
3092 /* bgt:d $label9 */
3093 {
3094 { 1, 1, 1, 1 },
3095 FR30_INSN_BGTD, "bgtd", "bgt:d",
3096 { { MNEM, ' ', OP (LABEL9), 0 } },
3097 & fmt_bled, { 0xfd00 },
3098 (PTR) & fmt_bled_ops[0],
3099 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
3100 },
3101 /* bgt $label9 */
3102 {
3103 { 1, 1, 1, 1 },
3104 FR30_INSN_BGT, "bgt", "bgt",
3105 { { MNEM, ' ', OP (LABEL9), 0 } },
3106 & fmt_bled, { 0xed00 },
3107 (PTR) & fmt_bled_ops[0],
3108 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3109 },
3110 /* bls:d $label9 */
3111 {
3112 { 1, 1, 1, 1 },
3113 FR30_INSN_BLSD, "blsd", "bls:d",
3114 { { MNEM, ' ', OP (LABEL9), 0 } },
3115 & fmt_blsd, { 0xfe00 },
3116 (PTR) & fmt_blsd_ops[0],
3117 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
3118 },
3119 /* bls $label9 */
3120 {
3121 { 1, 1, 1, 1 },
3122 FR30_INSN_BLS, "bls", "bls",
3123 { { MNEM, ' ', OP (LABEL9), 0 } },
3124 & fmt_blsd, { 0xee00 },
3125 (PTR) & fmt_blsd_ops[0],
3126 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3127 },
3128 /* bhi:d $label9 */
3129 {
3130 { 1, 1, 1, 1 },
3131 FR30_INSN_BHID, "bhid", "bhi:d",
3132 { { MNEM, ' ', OP (LABEL9), 0 } },
3133 & fmt_blsd, { 0xff00 },
3134 (PTR) & fmt_blsd_ops[0],
3135 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
3136 },
3137 /* bhi $label9 */
3138 {
3139 { 1, 1, 1, 1 },
3140 FR30_INSN_BHI, "bhi", "bhi",
3141 { { MNEM, ' ', OP (LABEL9), 0 } },
3142 & fmt_blsd, { 0xef00 },
3143 (PTR) & fmt_blsd_ops[0],
3144 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3145 },
3146 /* dmov $R13,@$dir10 */
3147 {
3148 { 1, 1, 1, 1 },
3149 FR30_INSN_DMOVR13, "dmovr13", "dmov",
3150 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
3151 & fmt_dmovr13, { 0x1800 },
3152 (PTR) & fmt_dmovr13_ops[0],
3153 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3154 },
3155 /* dmovh $R13,@$dir9 */
3156 {
3157 { 1, 1, 1, 1 },
3158 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
3159 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
3160 & fmt_dmovr13h, { 0x1900 },
3161 (PTR) & fmt_dmovr13h_ops[0],
3162 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3163 },
3164 /* dmovb $R13,@$dir8 */
3165 {
3166 { 1, 1, 1, 1 },
3167 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
3168 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
3169 & fmt_dmovr13b, { 0x1a00 },
3170 (PTR) & fmt_dmovr13b_ops[0],
3171 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3172 },
3173 /* dmov @$R13+,@$dir10 */
3174 {
3175 { 1, 1, 1, 1 },
3176 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
3177 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
3178 & fmt_dmovr13pi, { 0x1c00 },
3179 (PTR) & fmt_dmovr13pi_ops[0],
3180 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3181 },
3182 /* dmovh @$R13+,@$dir9 */
3183 {
3184 { 1, 1, 1, 1 },
3185 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
3186 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
3187 & fmt_dmovr13pih, { 0x1d00 },
3188 (PTR) & fmt_dmovr13pih_ops[0],
3189 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3190 },
3191 /* dmovb @$R13+,@$dir8 */
3192 {
3193 { 1, 1, 1, 1 },
3194 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
3195 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
3196 & fmt_dmovr13pib, { 0x1e00 },
3197 (PTR) & fmt_dmovr13pib_ops[0],
3198 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3199 },
3200 /* dmov @$R15+,@$dir10 */
3201 {
3202 { 1, 1, 1, 1 },
3203 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
3204 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
3205 & fmt_dmovr15pi, { 0x1b00 },
3206 (PTR) & fmt_dmovr15pi_ops[0],
3207 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3208 },
3209 /* dmov @$dir10,$R13 */
3210 {
3211 { 1, 1, 1, 1 },
3212 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
3213 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
3214 & fmt_dmov2r13, { 0x800 },
3215 (PTR) & fmt_dmov2r13_ops[0],
3216 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3217 },
3218 /* dmovh @$dir9,$R13 */
3219 {
3220 { 1, 1, 1, 1 },
3221 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
3222 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
3223 & fmt_dmov2r13h, { 0x900 },
3224 (PTR) & fmt_dmov2r13h_ops[0],
3225 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3226 },
3227 /* dmovb @$dir8,$R13 */
3228 {
3229 { 1, 1, 1, 1 },
3230 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
3231 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
3232 & fmt_dmov2r13b, { 0xa00 },
3233 (PTR) & fmt_dmov2r13b_ops[0],
3234 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3235 },
3236 /* dmov @$dir10,@$R13+ */
3237 {
3238 { 1, 1, 1, 1 },
3239 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
3240 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
3241 & fmt_dmov2r13pi, { 0xc00 },
3242 (PTR) & fmt_dmov2r13pi_ops[0],
3243 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3244 },
3245 /* dmovh @$dir9,@$R13+ */
3246 {
3247 { 1, 1, 1, 1 },
3248 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
3249 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
3250 & fmt_dmov2r13pih, { 0xd00 },
3251 (PTR) & fmt_dmov2r13pih_ops[0],
3252 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3253 },
3254 /* dmovb @$dir8,@$R13+ */
3255 {
3256 { 1, 1, 1, 1 },
3257 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
3258 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
3259 & fmt_dmov2r13pib, { 0xe00 },
3260 (PTR) & fmt_dmov2r13pib_ops[0],
3261 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3262 },
3263 /* dmov @$dir10,@-$R15 */
3264 {
3265 { 1, 1, 1, 1 },
3266 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
3267 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
3268 & fmt_dmov2r15pd, { 0xb00 },
3269 (PTR) & fmt_dmov2r15pd_ops[0],
3270 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3271 },
3272 /* ldres @$Ri+,$u4 */
3273 {
3274 { 1, 1, 1, 1 },
3275 FR30_INSN_LDRES, "ldres", "ldres",
3276 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
3277 & fmt_ldres, { 0xbc00 },
3278 (PTR) & fmt_ldres_ops[0],
3279 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3280 },
3281 /* stres $u4,@$Ri+ */
3282 {
3283 { 1, 1, 1, 1 },
3284 FR30_INSN_STRES, "stres", "stres",
3285 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
3286 & fmt_ldres, { 0xbd00 },
3287 (PTR) & fmt_ldres_ops[0],
3288 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3289 },
3290 /* copop $u4c,$ccc,$CRj,$CRi */
3291 {
3292 { 1, 1, 1, 1 },
3293 FR30_INSN_COPOP, "copop", "copop",
3294 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
3295 & fmt_copop, { 0x9fc0 },
3296 (PTR) 0,
3297 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3298 },
3299 /* copld $u4c,$ccc,$Rjc,$CRi */
3300 {
3301 { 1, 1, 1, 1 },
3302 FR30_INSN_COPLD, "copld", "copld",
3303 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
3304 & fmt_copld, { 0x9fd0 },
3305 (PTR) 0,
3306 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3307 },
3308 /* copst $u4c,$ccc,$CRj,$Ric */
3309 {
3310 { 1, 1, 1, 1 },
3311 FR30_INSN_COPST, "copst", "copst",
3312 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
3313 & fmt_copst, { 0x9fe0 },
3314 (PTR) 0,
3315 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3316 },
3317 /* copsv $u4c,$ccc,$CRj,$Ric */
3318 {
3319 { 1, 1, 1, 1 },
3320 FR30_INSN_COPSV, "copsv", "copsv",
3321 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
3322 & fmt_copst, { 0x9ff0 },
3323 (PTR) 0,
3324 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3325 },
3326 /* nop */
3327 {
3328 { 1, 1, 1, 1 },
3329 FR30_INSN_NOP, "nop", "nop",
3330 { { MNEM, 0 } },
3331 & fmt_nop, { 0x9fa0 },
3332 (PTR) 0,
3333 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3334 },
3335 /* andccr $u8 */
3336 {
3337 { 1, 1, 1, 1 },
3338 FR30_INSN_ANDCCR, "andccr", "andccr",
3339 { { MNEM, ' ', OP (U8), 0 } },
3340 & fmt_andccr, { 0x8300 },
3341 (PTR) & fmt_andccr_ops[0],
3342 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3343 },
3344 /* orccr $u8 */
3345 {
3346 { 1, 1, 1, 1 },
3347 FR30_INSN_ORCCR, "orccr", "orccr",
3348 { { MNEM, ' ', OP (U8), 0 } },
3349 & fmt_andccr, { 0x9300 },
3350 (PTR) & fmt_andccr_ops[0],
3351 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3352 },
3353 /* stilm $u8 */
3354 {
3355 { 1, 1, 1, 1 },
3356 FR30_INSN_STILM, "stilm", "stilm",
3357 { { MNEM, ' ', OP (U8), 0 } },
3358 & fmt_stilm, { 0x8700 },
3359 (PTR) & fmt_stilm_ops[0],
3360 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3361 },
3362 /* addsp $s10 */
3363 {
3364 { 1, 1, 1, 1 },
3365 FR30_INSN_ADDSP, "addsp", "addsp",
3366 { { MNEM, ' ', OP (S10), 0 } },
3367 & fmt_addsp, { 0xa300 },
3368 (PTR) & fmt_addsp_ops[0],
3369 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3370 },
3371 /* extsb $Ri */
3372 {
3373 { 1, 1, 1, 1 },
3374 FR30_INSN_EXTSB, "extsb", "extsb",
3375 { { MNEM, ' ', OP (RI), 0 } },
3376 & fmt_extsb, { 0x9780 },
3377 (PTR) & fmt_extsb_ops[0],
3378 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3379 },
3380 /* extub $Ri */
3381 {
3382 { 1, 1, 1, 1 },
3383 FR30_INSN_EXTUB, "extub", "extub",
3384 { { MNEM, ' ', OP (RI), 0 } },
3385 & fmt_extub, { 0x9790 },
3386 (PTR) & fmt_extub_ops[0],
3387 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3388 },
3389 /* extsh $Ri */
3390 {
3391 { 1, 1, 1, 1 },
3392 FR30_INSN_EXTSH, "extsh", "extsh",
3393 { { MNEM, ' ', OP (RI), 0 } },
3394 & fmt_extsh, { 0x97a0 },
3395 (PTR) & fmt_extsh_ops[0],
3396 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3397 },
3398 /* extuh $Ri */
3399 {
3400 { 1, 1, 1, 1 },
3401 FR30_INSN_EXTUH, "extuh", "extuh",
3402 { { MNEM, ' ', OP (RI), 0 } },
3403 & fmt_extuh, { 0x97b0 },
3404 (PTR) & fmt_extuh_ops[0],
3405 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3406 },
3407 /* ldm0 ($reglist_low_ld) */
3408 {
3409 { 1, 1, 1, 1 },
3410 FR30_INSN_LDM0, "ldm0", "ldm0",
3411 { { MNEM, ' ', '(', OP (REGLIST_LOW_LD), ')', 0 } },
3412 & fmt_ldm0, { 0x8c00 },
3413 (PTR) & fmt_ldm0_ops[0],
3414 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3415 },
3416 /* ldm1 ($reglist_hi_ld) */
3417 {
3418 { 1, 1, 1, 1 },
3419 FR30_INSN_LDM1, "ldm1", "ldm1",
3420 { { MNEM, ' ', '(', OP (REGLIST_HI_LD), ')', 0 } },
3421 & fmt_ldm1, { 0x8d00 },
3422 (PTR) & fmt_ldm1_ops[0],
3423 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3424 },
3425 /* stm0 ($reglist_low_st) */
3426 {
3427 { 1, 1, 1, 1 },
3428 FR30_INSN_STM0, "stm0", "stm0",
3429 { { MNEM, ' ', '(', OP (REGLIST_LOW_ST), ')', 0 } },
3430 & fmt_stm0, { 0x8e00 },
3431 (PTR) & fmt_stm0_ops[0],
3432 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3433 },
3434 /* stm1 ($reglist_hi_st) */
3435 {
3436 { 1, 1, 1, 1 },
3437 FR30_INSN_STM1, "stm1", "stm1",
3438 { { MNEM, ' ', '(', OP (REGLIST_HI_ST), ')', 0 } },
3439 & fmt_stm1, { 0x8f00 },
3440 (PTR) & fmt_stm1_ops[0],
3441 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3442 },
3443 /* enter $u10 */
3444 {
3445 { 1, 1, 1, 1 },
3446 FR30_INSN_ENTER, "enter", "enter",
3447 { { MNEM, ' ', OP (U10), 0 } },
3448 & fmt_enter, { 0xf00 },
3449 (PTR) & fmt_enter_ops[0],
3450 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3451 },
3452 /* leave */
3453 {
3454 { 1, 1, 1, 1 },
3455 FR30_INSN_LEAVE, "leave", "leave",
3456 { { MNEM, 0 } },
3457 & fmt_leave, { 0x9f90 },
3458 (PTR) & fmt_leave_ops[0],
3459 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3460 },
3461 /* xchb @$Rj,$Ri */
3462 {
3463 { 1, 1, 1, 1 },
3464 FR30_INSN_XCHB, "xchb", "xchb",
3465 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
3466 & fmt_xchb, { 0x8a00 },
3467 (PTR) & fmt_xchb_ops[0],
3468 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
3469 },
3470 };
3471
3472 #undef A
3473 #undef MNEM
3474 #undef OP
3475
3476 static const CGEN_INSN_TABLE insn_table =
3477 {
3478 & fr30_cgen_insn_table_entries[0],
3479 sizeof (CGEN_INSN),
3480 MAX_INSNS,
3481 NULL
3482 };
3483
3484 /* Formats for ALIAS macro-insns. */
3485
3486 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
3487
3488 static const CGEN_IFMT fmt_ldi8m = {
3489 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
3490 };
3491
3492 static const CGEN_IFMT fmt_ldi20m = {
3493 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
3494 };
3495
3496 static const CGEN_IFMT fmt_ldi32m = {
3497 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
3498 };
3499
3500 #undef F
3501
3502 /* Each non-simple macro entry points to an array of expansion possibilities. */
3503
3504 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
3505 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
3506 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
3507
3508 /* The macro instruction table. */
3509
3510 static const CGEN_INSN macro_insn_table_entries[] =
3511 {
3512 /* ldi8 $i8,$Ri */
3513 {
3514 { 1, 1, 1, 1 },
3515 -1, "ldi8m", "ldi8",
3516 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
3517 & fmt_ldi8m, { 0xc000 },
3518 (PTR) 0,
3519 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
3520 },
3521 /* ldi20 $i20,$Ri */
3522 {
3523 { 1, 1, 1, 1 },
3524 -1, "ldi20m", "ldi20",
3525 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
3526 & fmt_ldi20m, { 0x9b00 },
3527 (PTR) 0,
3528 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
3529 },
3530 /* ldi32 $i32,$Ri */
3531 {
3532 { 1, 1, 1, 1 },
3533 -1, "ldi32m", "ldi32",
3534 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
3535 & fmt_ldi32m, { 0x9f80 },
3536 (PTR) 0,
3537 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
3538 },
3539 };
3540
3541 #undef A
3542 #undef MNEM
3543 #undef OP
3544
3545 static const CGEN_INSN_TABLE macro_insn_table =
3546 {
3547 & macro_insn_table_entries[0],
3548 sizeof (CGEN_INSN),
3549 (sizeof (macro_insn_table_entries) /
3550 sizeof (macro_insn_table_entries[0])),
3551 NULL
3552 };
3553
3554 static void
3555 init_tables ()
3556 {
3557 }
3558
3559 /* Return non-zero if INSN is to be added to the hash table.
3560 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3561
3562 static int
3563 asm_hash_insn_p (insn)
3564 const CGEN_INSN * insn;
3565 {
3566 return CGEN_ASM_HASH_P (insn);
3567 }
3568
3569 static int
3570 dis_hash_insn_p (insn)
3571 const CGEN_INSN * insn;
3572 {
3573 /* If building the hash table and the NO-DIS attribute is present,
3574 ignore. */
3575 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
3576 return 0;
3577 return CGEN_DIS_HASH_P (insn);
3578 }
3579
3580 /* The result is the hash value of the insn.
3581 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
3582
3583 static unsigned int
3584 asm_hash_insn (mnem)
3585 const char * mnem;
3586 {
3587 return CGEN_ASM_HASH (mnem);
3588 }
3589
3590 /* BUF is a pointer to the insn's bytes in target order.
3591 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3592 host order. */
3593
3594 static unsigned int
3595 dis_hash_insn (buf, value)
3596 const char * buf;
3597 CGEN_INSN_INT value;
3598 {
3599 return CGEN_DIS_HASH (buf, value);
3600 }
3601
3602 /* Initialize an opcode table and return a descriptor.
3603 It's much like opening a file, and must be the first function called. */
3604
3605 CGEN_OPCODE_DESC
3606 fr30_cgen_opcode_open (mach, endian)
3607 int mach;
3608 enum cgen_endian endian;
3609 {
3610 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
3611 static int init_p;
3612
3613 if (! init_p)
3614 {
3615 init_tables ();
3616 init_p = 1;
3617 }
3618
3619 memset (table, 0, sizeof (*table));
3620
3621 CGEN_OPCODE_MACH (table) = mach;
3622 CGEN_OPCODE_ENDIAN (table) = endian;
3623 /* FIXME: for the sparc case we can determine insn-endianness statically.
3624 The worry here is where both data and insn endian can be independently
3625 chosen, in which case this function will need another argument.
3626 Actually, will want to allow for more arguments in the future anyway. */
3627 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
3628
3629 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
3630
3631 CGEN_OPCODE_IFLD_TABLE (table) = & fr30_cgen_ifld_table[0];
3632
3633 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
3634
3635 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
3636
3637 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
3638
3639 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
3640 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
3641 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
3642
3643 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
3644 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
3645 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
3646
3647 return (CGEN_OPCODE_DESC) table;
3648 }
3649
3650 /* Close an opcode table. */
3651
3652 void
3653 fr30_cgen_opcode_close (desc)
3654 CGEN_OPCODE_DESC desc;
3655 {
3656 free (desc);
3657 }
3658
3659 /* Getting values from cgen_fields is handled by a collection of functions.
3660 They are distinguished by the type of the VALUE argument they return.
3661 TODO: floating point, inlining support, remove cases where result type
3662 not appropriate. */
3663
3664 int
3665 fr30_cgen_get_int_operand (opindex, fields)
3666 int opindex;
3667 const CGEN_FIELDS * fields;
3668 {
3669 int value;
3670
3671 switch (opindex)
3672 {
3673 case FR30_OPERAND_RI :
3674 value = fields->f_Ri;
3675 break;
3676 case FR30_OPERAND_RJ :
3677 value = fields->f_Rj;
3678 break;
3679 case FR30_OPERAND_RIC :
3680 value = fields->f_Ric;
3681 break;
3682 case FR30_OPERAND_RJC :
3683 value = fields->f_Rjc;
3684 break;
3685 case FR30_OPERAND_CRI :
3686 value = fields->f_CRi;
3687 break;
3688 case FR30_OPERAND_CRJ :
3689 value = fields->f_CRj;
3690 break;
3691 case FR30_OPERAND_RS1 :
3692 value = fields->f_Rs1;
3693 break;
3694 case FR30_OPERAND_RS2 :
3695 value = fields->f_Rs2;
3696 break;
3697 case FR30_OPERAND_R13 :
3698 value = fields->f_nil;
3699 break;
3700 case FR30_OPERAND_R14 :
3701 value = fields->f_nil;
3702 break;
3703 case FR30_OPERAND_R15 :
3704 value = fields->f_nil;
3705 break;
3706 case FR30_OPERAND_PS :
3707 value = fields->f_nil;
3708 break;
3709 case FR30_OPERAND_U4 :
3710 value = fields->f_u4;
3711 break;
3712 case FR30_OPERAND_U4C :
3713 value = fields->f_u4c;
3714 break;
3715 case FR30_OPERAND_U8 :
3716 value = fields->f_u8;
3717 break;
3718 case FR30_OPERAND_I8 :
3719 value = fields->f_i8;
3720 break;
3721 case FR30_OPERAND_UDISP6 :
3722 value = fields->f_udisp6;
3723 break;
3724 case FR30_OPERAND_DISP8 :
3725 value = fields->f_disp8;
3726 break;
3727 case FR30_OPERAND_DISP9 :
3728 value = fields->f_disp9;
3729 break;
3730 case FR30_OPERAND_DISP10 :
3731 value = fields->f_disp10;
3732 break;
3733 case FR30_OPERAND_S10 :
3734 value = fields->f_s10;
3735 break;
3736 case FR30_OPERAND_U10 :
3737 value = fields->f_u10;
3738 break;
3739 case FR30_OPERAND_I32 :
3740 value = fields->f_i32;
3741 break;
3742 case FR30_OPERAND_M4 :
3743 value = fields->f_m4;
3744 break;
3745 case FR30_OPERAND_I20 :
3746 value = fields->f_i20;
3747 break;
3748 case FR30_OPERAND_DIR8 :
3749 value = fields->f_dir8;
3750 break;
3751 case FR30_OPERAND_DIR9 :
3752 value = fields->f_dir9;
3753 break;
3754 case FR30_OPERAND_DIR10 :
3755 value = fields->f_dir10;
3756 break;
3757 case FR30_OPERAND_LABEL9 :
3758 value = fields->f_rel9;
3759 break;
3760 case FR30_OPERAND_LABEL12 :
3761 value = fields->f_rel12;
3762 break;
3763 case FR30_OPERAND_REGLIST_LOW_LD :
3764 value = fields->f_reglist_low_ld;
3765 break;
3766 case FR30_OPERAND_REGLIST_HI_LD :
3767 value = fields->f_reglist_hi_ld;
3768 break;
3769 case FR30_OPERAND_REGLIST_LOW_ST :
3770 value = fields->f_reglist_low_st;
3771 break;
3772 case FR30_OPERAND_REGLIST_HI_ST :
3773 value = fields->f_reglist_hi_st;
3774 break;
3775 case FR30_OPERAND_CC :
3776 value = fields->f_cc;
3777 break;
3778 case FR30_OPERAND_CCC :
3779 value = fields->f_ccc;
3780 break;
3781
3782 default :
3783 /* xgettext:c-format */
3784 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3785 opindex);
3786 abort ();
3787 }
3788
3789 return value;
3790 }
3791
3792 bfd_vma
3793 fr30_cgen_get_vma_operand (opindex, fields)
3794 int opindex;
3795 const CGEN_FIELDS * fields;
3796 {
3797 bfd_vma value;
3798
3799 switch (opindex)
3800 {
3801 case FR30_OPERAND_RI :
3802 value = fields->f_Ri;
3803 break;
3804 case FR30_OPERAND_RJ :
3805 value = fields->f_Rj;
3806 break;
3807 case FR30_OPERAND_RIC :
3808 value = fields->f_Ric;
3809 break;
3810 case FR30_OPERAND_RJC :
3811 value = fields->f_Rjc;
3812 break;
3813 case FR30_OPERAND_CRI :
3814 value = fields->f_CRi;
3815 break;
3816 case FR30_OPERAND_CRJ :
3817 value = fields->f_CRj;
3818 break;
3819 case FR30_OPERAND_RS1 :
3820 value = fields->f_Rs1;
3821 break;
3822 case FR30_OPERAND_RS2 :
3823 value = fields->f_Rs2;
3824 break;
3825 case FR30_OPERAND_R13 :
3826 value = fields->f_nil;
3827 break;
3828 case FR30_OPERAND_R14 :
3829 value = fields->f_nil;
3830 break;
3831 case FR30_OPERAND_R15 :
3832 value = fields->f_nil;
3833 break;
3834 case FR30_OPERAND_PS :
3835 value = fields->f_nil;
3836 break;
3837 case FR30_OPERAND_U4 :
3838 value = fields->f_u4;
3839 break;
3840 case FR30_OPERAND_U4C :
3841 value = fields->f_u4c;
3842 break;
3843 case FR30_OPERAND_U8 :
3844 value = fields->f_u8;
3845 break;
3846 case FR30_OPERAND_I8 :
3847 value = fields->f_i8;
3848 break;
3849 case FR30_OPERAND_UDISP6 :
3850 value = fields->f_udisp6;
3851 break;
3852 case FR30_OPERAND_DISP8 :
3853 value = fields->f_disp8;
3854 break;
3855 case FR30_OPERAND_DISP9 :
3856 value = fields->f_disp9;
3857 break;
3858 case FR30_OPERAND_DISP10 :
3859 value = fields->f_disp10;
3860 break;
3861 case FR30_OPERAND_S10 :
3862 value = fields->f_s10;
3863 break;
3864 case FR30_OPERAND_U10 :
3865 value = fields->f_u10;
3866 break;
3867 case FR30_OPERAND_I32 :
3868 value = fields->f_i32;
3869 break;
3870 case FR30_OPERAND_M4 :
3871 value = fields->f_m4;
3872 break;
3873 case FR30_OPERAND_I20 :
3874 value = fields->f_i20;
3875 break;
3876 case FR30_OPERAND_DIR8 :
3877 value = fields->f_dir8;
3878 break;
3879 case FR30_OPERAND_DIR9 :
3880 value = fields->f_dir9;
3881 break;
3882 case FR30_OPERAND_DIR10 :
3883 value = fields->f_dir10;
3884 break;
3885 case FR30_OPERAND_LABEL9 :
3886 value = fields->f_rel9;
3887 break;
3888 case FR30_OPERAND_LABEL12 :
3889 value = fields->f_rel12;
3890 break;
3891 case FR30_OPERAND_REGLIST_LOW_LD :
3892 value = fields->f_reglist_low_ld;
3893 break;
3894 case FR30_OPERAND_REGLIST_HI_LD :
3895 value = fields->f_reglist_hi_ld;
3896 break;
3897 case FR30_OPERAND_REGLIST_LOW_ST :
3898 value = fields->f_reglist_low_st;
3899 break;
3900 case FR30_OPERAND_REGLIST_HI_ST :
3901 value = fields->f_reglist_hi_st;
3902 break;
3903 case FR30_OPERAND_CC :
3904 value = fields->f_cc;
3905 break;
3906 case FR30_OPERAND_CCC :
3907 value = fields->f_ccc;
3908 break;
3909
3910 default :
3911 /* xgettext:c-format */
3912 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3913 opindex);
3914 abort ();
3915 }
3916
3917 return value;
3918 }
3919
3920 /* Stuffing values in cgen_fields is handled by a collection of functions.
3921 They are distinguished by the type of the VALUE argument they accept.
3922 TODO: floating point, inlining support, remove cases where argument type
3923 not appropriate. */
3924
3925 void
3926 fr30_cgen_set_int_operand (opindex, fields, value)
3927 int opindex;
3928 CGEN_FIELDS * fields;
3929 int value;
3930 {
3931 switch (opindex)
3932 {
3933 case FR30_OPERAND_RI :
3934 fields->f_Ri = value;
3935 break;
3936 case FR30_OPERAND_RJ :
3937 fields->f_Rj = value;
3938 break;
3939 case FR30_OPERAND_RIC :
3940 fields->f_Ric = value;
3941 break;
3942 case FR30_OPERAND_RJC :
3943 fields->f_Rjc = value;
3944 break;
3945 case FR30_OPERAND_CRI :
3946 fields->f_CRi = value;
3947 break;
3948 case FR30_OPERAND_CRJ :
3949 fields->f_CRj = value;
3950 break;
3951 case FR30_OPERAND_RS1 :
3952 fields->f_Rs1 = value;
3953 break;
3954 case FR30_OPERAND_RS2 :
3955 fields->f_Rs2 = value;
3956 break;
3957 case FR30_OPERAND_R13 :
3958 fields->f_nil = value;
3959 break;
3960 case FR30_OPERAND_R14 :
3961 fields->f_nil = value;
3962 break;
3963 case FR30_OPERAND_R15 :
3964 fields->f_nil = value;
3965 break;
3966 case FR30_OPERAND_PS :
3967 fields->f_nil = value;
3968 break;
3969 case FR30_OPERAND_U4 :
3970 fields->f_u4 = value;
3971 break;
3972 case FR30_OPERAND_U4C :
3973 fields->f_u4c = value;
3974 break;
3975 case FR30_OPERAND_U8 :
3976 fields->f_u8 = value;
3977 break;
3978 case FR30_OPERAND_I8 :
3979 fields->f_i8 = value;
3980 break;
3981 case FR30_OPERAND_UDISP6 :
3982 fields->f_udisp6 = value;
3983 break;
3984 case FR30_OPERAND_DISP8 :
3985 fields->f_disp8 = value;
3986 break;
3987 case FR30_OPERAND_DISP9 :
3988 fields->f_disp9 = value;
3989 break;
3990 case FR30_OPERAND_DISP10 :
3991 fields->f_disp10 = value;
3992 break;
3993 case FR30_OPERAND_S10 :
3994 fields->f_s10 = value;
3995 break;
3996 case FR30_OPERAND_U10 :
3997 fields->f_u10 = value;
3998 break;
3999 case FR30_OPERAND_I32 :
4000 fields->f_i32 = value;
4001 break;
4002 case FR30_OPERAND_M4 :
4003 fields->f_m4 = value;
4004 break;
4005 case FR30_OPERAND_I20 :
4006 fields->f_i20 = value;
4007 break;
4008 case FR30_OPERAND_DIR8 :
4009 fields->f_dir8 = value;
4010 break;
4011 case FR30_OPERAND_DIR9 :
4012 fields->f_dir9 = value;
4013 break;
4014 case FR30_OPERAND_DIR10 :
4015 fields->f_dir10 = value;
4016 break;
4017 case FR30_OPERAND_LABEL9 :
4018 fields->f_rel9 = value;
4019 break;
4020 case FR30_OPERAND_LABEL12 :
4021 fields->f_rel12 = value;
4022 break;
4023 case FR30_OPERAND_REGLIST_LOW_LD :
4024 fields->f_reglist_low_ld = value;
4025 break;
4026 case FR30_OPERAND_REGLIST_HI_LD :
4027 fields->f_reglist_hi_ld = value;
4028 break;
4029 case FR30_OPERAND_REGLIST_LOW_ST :
4030 fields->f_reglist_low_st = value;
4031 break;
4032 case FR30_OPERAND_REGLIST_HI_ST :
4033 fields->f_reglist_hi_st = value;
4034 break;
4035 case FR30_OPERAND_CC :
4036 fields->f_cc = value;
4037 break;
4038 case FR30_OPERAND_CCC :
4039 fields->f_ccc = value;
4040 break;
4041
4042 default :
4043 /* xgettext:c-format */
4044 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
4045 opindex);
4046 abort ();
4047 }
4048 }
4049
4050 void
4051 fr30_cgen_set_vma_operand (opindex, fields, value)
4052 int opindex;
4053 CGEN_FIELDS * fields;
4054 bfd_vma value;
4055 {
4056 switch (opindex)
4057 {
4058 case FR30_OPERAND_RI :
4059 fields->f_Ri = value;
4060 break;
4061 case FR30_OPERAND_RJ :
4062 fields->f_Rj = value;
4063 break;
4064 case FR30_OPERAND_RIC :
4065 fields->f_Ric = value;
4066 break;
4067 case FR30_OPERAND_RJC :
4068 fields->f_Rjc = value;
4069 break;
4070 case FR30_OPERAND_CRI :
4071 fields->f_CRi = value;
4072 break;
4073 case FR30_OPERAND_CRJ :
4074 fields->f_CRj = value;
4075 break;
4076 case FR30_OPERAND_RS1 :
4077 fields->f_Rs1 = value;
4078 break;
4079 case FR30_OPERAND_RS2 :
4080 fields->f_Rs2 = value;
4081 break;
4082 case FR30_OPERAND_R13 :
4083 fields->f_nil = value;
4084 break;
4085 case FR30_OPERAND_R14 :
4086 fields->f_nil = value;
4087 break;
4088 case FR30_OPERAND_R15 :
4089 fields->f_nil = value;
4090 break;
4091 case FR30_OPERAND_PS :
4092 fields->f_nil = value;
4093 break;
4094 case FR30_OPERAND_U4 :
4095 fields->f_u4 = value;
4096 break;
4097 case FR30_OPERAND_U4C :
4098 fields->f_u4c = value;
4099 break;
4100 case FR30_OPERAND_U8 :
4101 fields->f_u8 = value;
4102 break;
4103 case FR30_OPERAND_I8 :
4104 fields->f_i8 = value;
4105 break;
4106 case FR30_OPERAND_UDISP6 :
4107 fields->f_udisp6 = value;
4108 break;
4109 case FR30_OPERAND_DISP8 :
4110 fields->f_disp8 = value;
4111 break;
4112 case FR30_OPERAND_DISP9 :
4113 fields->f_disp9 = value;
4114 break;
4115 case FR30_OPERAND_DISP10 :
4116 fields->f_disp10 = value;
4117 break;
4118 case FR30_OPERAND_S10 :
4119 fields->f_s10 = value;
4120 break;
4121 case FR30_OPERAND_U10 :
4122 fields->f_u10 = value;
4123 break;
4124 case FR30_OPERAND_I32 :
4125 fields->f_i32 = value;
4126 break;
4127 case FR30_OPERAND_M4 :
4128 fields->f_m4 = value;
4129 break;
4130 case FR30_OPERAND_I20 :
4131 fields->f_i20 = value;
4132 break;
4133 case FR30_OPERAND_DIR8 :
4134 fields->f_dir8 = value;
4135 break;
4136 case FR30_OPERAND_DIR9 :
4137 fields->f_dir9 = value;
4138 break;
4139 case FR30_OPERAND_DIR10 :
4140 fields->f_dir10 = value;
4141 break;
4142 case FR30_OPERAND_LABEL9 :
4143 fields->f_rel9 = value;
4144 break;
4145 case FR30_OPERAND_LABEL12 :
4146 fields->f_rel12 = value;
4147 break;
4148 case FR30_OPERAND_REGLIST_LOW_LD :
4149 fields->f_reglist_low_ld = value;
4150 break;
4151 case FR30_OPERAND_REGLIST_HI_LD :
4152 fields->f_reglist_hi_ld = value;
4153 break;
4154 case FR30_OPERAND_REGLIST_LOW_ST :
4155 fields->f_reglist_low_st = value;
4156 break;
4157 case FR30_OPERAND_REGLIST_HI_ST :
4158 fields->f_reglist_hi_st = value;
4159 break;
4160 case FR30_OPERAND_CC :
4161 fields->f_cc = value;
4162 break;
4163 case FR30_OPERAND_CCC :
4164 fields->f_ccc = value;
4165 break;
4166
4167 default :
4168 /* xgettext:c-format */
4169 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
4170 opindex);
4171 abort ();
4172 }
4173 }
4174
GDB Binutils - Deliverables
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