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Fri Dec 4 17:08:08 1998 Dave Brolley <brolley@cygnus.com>
[deliverable/binutils-gdb.git] / opcodes / fr30-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "fr30-opc.h"
31 #include "opintl.h"
32
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
35
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40 static unsigned int asm_hash_insn PARAMS ((const char *));
41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
43
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
52 The result is a pointer to the insn table entry, or NULL if the instruction
53 wasn't recognized. */
54
55 const CGEN_INSN *
56 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63 {
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
65 unsigned char *bufp;
66 CGEN_INSN_INT base_insn;
67 #if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69 #else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72 #endif
73
74 #if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78 #else
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
81 ex_info.valid = -1;
82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
84 #endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
109 base_insn, fields,
110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145 }
146
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151 void
152 fr30_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157 {
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173 }
174
175 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 fr30_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183 const CGEN_INSN *
184 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190 {
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202 }
203 /* Attributes. */
204
205 static const CGEN_ATTR_ENTRY MACH_attr[] =
206 {
207 { "base", MACH_BASE },
208 { "fr30", MACH_FR30 },
209 { "max", MACH_MAX },
210 { 0, 0 }
211 };
212
213 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
214 {
215 { "CACHE-ADDR", NULL },
216 { "FUN-ACCESS", NULL },
217 { "PC", NULL },
218 { "PROFILE", NULL },
219 { 0, 0 }
220 };
221
222 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
223 {
224 { "ABS-ADDR", NULL },
225 { "HASH-PREFIX", NULL },
226 { "NEGATIVE", NULL },
227 { "PCREL-ADDR", NULL },
228 { "RELAX", NULL },
229 { "SEM-ONLY", NULL },
230 { "SIGN-OPT", NULL },
231 { "SIGNED", NULL },
232 { "UNSIGNED", NULL },
233 { "VIRTUAL", NULL },
234 { 0, 0 }
235 };
236
237 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
238 {
239 { "ALIAS", NULL },
240 { "COND-CTI", NULL },
241 { "DELAY-SLOT", NULL },
242 { "NO-DIS", NULL },
243 { "NOT-IN-DELAY-SLOT", NULL },
244 { "RELAX", NULL },
245 { "RELAXABLE", NULL },
246 { "SKIP-CTI", NULL },
247 { "UNCOND-CTI", NULL },
248 { "VIRTUAL", NULL },
249 { 0, 0 }
250 };
251
252 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
253 {
254 { "ac", 13 },
255 { "fp", 14 },
256 { "sp", 15 },
257 { "r0", 0 },
258 { "r1", 1 },
259 { "r2", 2 },
260 { "r3", 3 },
261 { "r4", 4 },
262 { "r5", 5 },
263 { "r6", 6 },
264 { "r7", 7 },
265 { "r8", 8 },
266 { "r9", 9 },
267 { "r10", 10 },
268 { "r11", 11 },
269 { "r12", 12 },
270 { "r13", 13 },
271 { "r14", 14 },
272 { "r15", 15 }
273 };
274
275 CGEN_KEYWORD fr30_cgen_opval_h_gr =
276 {
277 & fr30_cgen_opval_h_gr_entries[0],
278 19
279 };
280
281 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
282 {
283 { "cr0", 0 },
284 { "cr1", 1 },
285 { "cr2", 2 },
286 { "cr3", 3 },
287 { "cr4", 4 },
288 { "cr5", 5 },
289 { "cr6", 6 },
290 { "cr7", 7 },
291 { "cr8", 8 },
292 { "cr9", 9 },
293 { "cr10", 10 },
294 { "cr11", 11 },
295 { "cr12", 12 },
296 { "cr13", 13 },
297 { "cr14", 14 },
298 { "cr15", 15 }
299 };
300
301 CGEN_KEYWORD fr30_cgen_opval_h_cr =
302 {
303 & fr30_cgen_opval_h_cr_entries[0],
304 16
305 };
306
307 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
308 {
309 { "tbr", 0 },
310 { "rp", 1 },
311 { "ssp", 2 },
312 { "usp", 3 },
313 { "mdh", 4 },
314 { "mdl", 5 }
315 };
316
317 CGEN_KEYWORD fr30_cgen_opval_h_dr =
318 {
319 & fr30_cgen_opval_h_dr_entries[0],
320 6
321 };
322
323 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
324 {
325 { "ps", 0 }
326 };
327
328 CGEN_KEYWORD fr30_cgen_opval_h_ps =
329 {
330 & fr30_cgen_opval_h_ps_entries[0],
331 1
332 };
333
334 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
335 {
336 { "r13", 0 }
337 };
338
339 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
340 {
341 & fr30_cgen_opval_h_r13_entries[0],
342 1
343 };
344
345 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
346 {
347 { "r14", 0 }
348 };
349
350 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
351 {
352 & fr30_cgen_opval_h_r14_entries[0],
353 1
354 };
355
356 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
357 {
358 { "r15", 0 }
359 };
360
361 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
362 {
363 & fr30_cgen_opval_h_r15_entries[0],
364 1
365 };
366
367
368 /* The hardware table. */
369
370 #define HW_ENT(n) fr30_cgen_hw_entries[n]
371 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
372 {
373 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
374 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
375 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
376 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
377 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
378 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
379 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
380 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
381 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
382 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
383 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
384 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
385 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
386 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
387 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
388 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
389 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
390 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
391 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
392 { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
393 { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
394 { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
395 { 0 }
396 };
397
398 /* The instruction field table. */
399
400 static const CGEN_IFLD fr30_cgen_ifld_table[] =
401 {
402 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
403 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
404 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
405 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
406 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
407 { FR30_F_OP5, "f-op5", 0, 16, 5, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
408 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
409 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
410 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
411 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
412 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
413 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
414 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
415 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
416 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
417 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
418 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
419 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
420 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
421 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
422 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
423 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
424 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
425 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
426 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
427 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
428 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
429 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
430 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
431 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
432 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
433 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
434 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
435 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
436 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
437 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
438 { FR30_F_REGLIST_HI, "f-reglist_hi", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
439 { FR30_F_REGLIST_LOW, "f-reglist_low", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
440 { 0 }
441 };
442
443 /* The operand table. */
444
445 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
446 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
447
448 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
449 {
450 /* pc: program counter */
451 { "pc", & HW_ENT (HW_H_PC), 0, 0,
452 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
453 /* Ri: destination register */
454 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
455 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
456 /* Rj: source register */
457 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
458 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
459 /* Ric: target register coproc insn */
460 { "Ric", & HW_ENT (HW_H_GR), 12, 4,
461 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
462 /* Rjc: source register coproc insn */
463 { "Rjc", & HW_ENT (HW_H_GR), 8, 4,
464 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
465 /* CRi: coprocessor register */
466 { "CRi", & HW_ENT (HW_H_CR), 12, 4,
467 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
468 /* CRj: coprocessor register */
469 { "CRj", & HW_ENT (HW_H_CR), 8, 4,
470 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
471 /* Rs1: dedicated register */
472 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
473 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
474 /* Rs2: dedicated register */
475 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
476 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
477 /* R13: General Register 13 */
478 { "R13", & HW_ENT (HW_H_R13), 0, 0,
479 { 0, 0, { 0 } } },
480 /* R14: General Register 14 */
481 { "R14", & HW_ENT (HW_H_R14), 0, 0,
482 { 0, 0, { 0 } } },
483 /* R15: General Register 15 */
484 { "R15", & HW_ENT (HW_H_R15), 0, 0,
485 { 0, 0, { 0 } } },
486 /* ps: Program Status register */
487 { "ps", & HW_ENT (HW_H_PS), 0, 0,
488 { 0, 0, { 0 } } },
489 /* u4: 4 bit unsigned immediate */
490 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
491 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
492 /* u4c: 4 bit unsigned immediate */
493 { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
494 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
495 /* u8: 8 bit unsigned immediate */
496 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
497 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
498 /* i8: 8 bit unsigned immediate */
499 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
500 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
501 /* udisp6: 6 bit unsigned immediate */
502 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
503 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
504 /* disp8: 8 bit signed immediate */
505 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
506 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
507 /* disp9: 9 bit signed immediate */
508 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
509 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
510 /* disp10: 10 bit signed immediate */
511 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
512 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
513 /* s10: 10 bit signed immediate */
514 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
515 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
516 /* u10: 10 bit unsigned immediate */
517 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
518 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
519 /* i32: 32 bit immediate */
520 { "i32", & HW_ENT (HW_H_UINT), 0, 32,
521 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
522 /* m4: 4 bit negative immediate */
523 { "m4", & HW_ENT (HW_H_SINT), 8, 4,
524 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
525 /* i20: 20 bit immediate */
526 { "i20", & HW_ENT (HW_H_UINT), 0, 20,
527 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { 0 } } },
528 /* dir8: 8 bit direct address */
529 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
530 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
531 /* dir9: 9 bit direct address */
532 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
533 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
534 /* dir10: 10 bit direct address */
535 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
536 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
537 /* label9: 9 bit pc relative address */
538 { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
539 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
540 /* label12: 12 bit pc relative address */
541 { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
542 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
543 /* reglist_low: 8 bit register mask */
544 { "reglist_low", & HW_ENT (HW_H_UINT), 8, 8,
545 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
546 /* reglist_hi: 8 bit register mask */
547 { "reglist_hi", & HW_ENT (HW_H_UINT), 8, 8,
548 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
549 /* cc: condition codes */
550 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
551 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
552 /* ccc: coprocessor calc */
553 { "ccc", & HW_ENT (HW_H_UINT), 0, 8,
554 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
555 /* nbit: negative bit */
556 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
557 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
558 /* vbit: overflow bit */
559 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
560 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
561 /* zbit: zero bit */
562 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
563 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
564 /* cbit: carry bit */
565 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
566 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
567 /* ibit: interrupt bit */
568 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
569 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
570 /* sbit: stack bit */
571 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
572 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
573 /* ccr: condition code bits */
574 { "ccr", & HW_ENT (HW_H_CCR), 0, 0,
575 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
576 /* scr: system condition bits */
577 { "scr", & HW_ENT (HW_H_SCR), 0, 0,
578 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
579 /* ilm: condition code bits */
580 { "ilm", & HW_ENT (HW_H_ILM), 0, 0,
581 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
582 };
583
584 /* Operand references. */
585
586 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
587 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
588 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
589
590 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
591 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
592 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
593 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
594 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
595 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
596 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
597 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
598 { 0 }
599 };
600
601 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
602 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
603 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
604 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
605 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
606 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
607 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
608 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
609 { 0 }
610 };
611
612 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
613 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
614 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
615 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
616 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
617 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
618 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
619 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
620 { 0 }
621 };
622
623 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
624 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
625 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
626 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
627 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
628 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
629 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
630 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
631 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
632 { 0 }
633 };
634
635 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
636 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
637 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
638 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
639 { 0 }
640 };
641
642 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
643 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
644 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
645 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
646 { 0 }
647 };
648
649 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
650 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
651 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
652 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
653 { 0 }
654 };
655
656 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
657 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
658 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
659 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
660 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
661 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
662 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
663 { 0 }
664 };
665
666 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
667 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
668 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
669 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
670 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
671 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
672 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
673 { 0 }
674 };
675
676 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
677 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
678 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
679 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
680 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
681 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
682 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
683 { 0 }
684 };
685
686 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
687 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
688 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
689 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
690 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
691 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
692 { 0 }
693 };
694
695 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
696 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
697 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
698 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
699 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
700 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
701 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
702 { 0 }
703 };
704
705 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
706 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
707 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
708 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
709 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
710 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
711 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
712 { 0 }
713 };
714
715 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
716 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
717 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
718 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
719 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
720 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
721 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
722 { 0 }
723 };
724
725 static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
726 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
727 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
728 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
729 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
730 { 0 }
731 };
732
733 static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
734 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
735 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
736 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
737 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
738 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
739 { 0 }
740 };
741
742 static const CGEN_OPERAND_INSTANCE fmt_mul_ops[] = {
743 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
744 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
745 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
746 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
747 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
748 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
749 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
750 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
751 { 0 }
752 };
753
754 static const CGEN_OPERAND_INSTANCE fmt_mulu_ops[] = {
755 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
756 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
757 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
758 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
759 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
760 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
761 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
762 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
763 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
764 { 0 }
765 };
766
767 static const CGEN_OPERAND_INSTANCE fmt_mulh_ops[] = {
768 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
769 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
770 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
771 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
772 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
773 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
774 { 0 }
775 };
776
777 static const CGEN_OPERAND_INSTANCE fmt_lsl_ops[] = {
778 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
779 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
780 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
781 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
782 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
783 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
784 { 0 }
785 };
786
787 static const CGEN_OPERAND_INSTANCE fmt_lsli_ops[] = {
788 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
789 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
790 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
791 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
792 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
793 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
794 { 0 }
795 };
796
797 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
798 { INPUT, "i8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I8), 0, 0 },
799 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
800 { 0 }
801 };
802
803 static const CGEN_OPERAND_INSTANCE fmt_ldi20_ops[] = {
804 { INPUT, "i20", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I20), 0, 0 },
805 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
806 { 0 }
807 };
808
809 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
810 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
811 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
812 { 0 }
813 };
814
815 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
816 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
817 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
818 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
819 { 0 }
820 };
821
822 static const CGEN_OPERAND_INSTANCE fmt_lduh_ops[] = {
823 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
824 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
825 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
826 { 0 }
827 };
828
829 static const CGEN_OPERAND_INSTANCE fmt_ldub_ops[] = {
830 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
831 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
832 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
833 { 0 }
834 };
835
836 static const CGEN_OPERAND_INSTANCE fmt_ldr13_ops[] = {
837 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
838 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
839 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
840 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
841 { 0 }
842 };
843
844 static const CGEN_OPERAND_INSTANCE fmt_ldr13uh_ops[] = {
845 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
846 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
847 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
848 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
849 { 0 }
850 };
851
852 static const CGEN_OPERAND_INSTANCE fmt_ldr13ub_ops[] = {
853 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
854 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
855 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
856 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
857 { 0 }
858 };
859
860 static const CGEN_OPERAND_INSTANCE fmt_ldr14_ops[] = {
861 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
862 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
863 { INPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
864 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
865 { 0 }
866 };
867
868 static const CGEN_OPERAND_INSTANCE fmt_ldr14uh_ops[] = {
869 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
870 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
871 { INPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
872 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
873 { 0 }
874 };
875
876 static const CGEN_OPERAND_INSTANCE fmt_ldr14ub_ops[] = {
877 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
878 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
879 { INPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
880 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
881 { 0 }
882 };
883
884 static const CGEN_OPERAND_INSTANCE fmt_ldr15_ops[] = {
885 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
886 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
887 { INPUT, "h_memory_add__VM_udisp6_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
888 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
889 { 0 }
890 };
891
892 static const CGEN_OPERAND_INSTANCE fmt_ldr15gr_ops[] = {
893 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
894 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
895 { INPUT, "f_Ri", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
896 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
897 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
898 { 0 }
899 };
900
901 static const CGEN_OPERAND_INSTANCE fmt_ldr15dr_ops[] = {
902 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
903 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
904 { OUTPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
905 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
906 { 0 }
907 };
908
909 static const CGEN_OPERAND_INSTANCE fmt_ldr15ps_ops[] = {
910 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
911 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
912 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
913 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
914 { 0 }
915 };
916
917 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
918 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
919 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
920 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
921 { 0 }
922 };
923
924 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
925 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
926 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
927 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
928 { 0 }
929 };
930
931 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
932 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
933 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
934 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
935 { 0 }
936 };
937
938 static const CGEN_OPERAND_INSTANCE fmt_str13_ops[] = {
939 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
940 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
941 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
942 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
943 { 0 }
944 };
945
946 static const CGEN_OPERAND_INSTANCE fmt_str13h_ops[] = {
947 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
948 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
949 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
950 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
951 { 0 }
952 };
953
954 static const CGEN_OPERAND_INSTANCE fmt_str13b_ops[] = {
955 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
956 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
957 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
958 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
959 { 0 }
960 };
961
962 static const CGEN_OPERAND_INSTANCE fmt_str14_ops[] = {
963 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
964 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
965 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
966 { OUTPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
967 { 0 }
968 };
969
970 static const CGEN_OPERAND_INSTANCE fmt_str14h_ops[] = {
971 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
972 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
973 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
974 { OUTPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
975 { 0 }
976 };
977
978 static const CGEN_OPERAND_INSTANCE fmt_str14b_ops[] = {
979 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
980 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
981 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
982 { OUTPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
983 { 0 }
984 };
985
986 static const CGEN_OPERAND_INSTANCE fmt_str15_ops[] = {
987 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
988 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
989 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
990 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_15_udisp6", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
991 { 0 }
992 };
993
994 static const CGEN_OPERAND_INSTANCE fmt_str15gr_ops[] = {
995 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
996 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
997 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
998 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
999 { 0 }
1000 };
1001
1002 static const CGEN_OPERAND_INSTANCE fmt_str15dr_ops[] = {
1003 { INPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
1004 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1005 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1006 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1007 { 0 }
1008 };
1009
1010 static const CGEN_OPERAND_INSTANCE fmt_str15ps_ops[] = {
1011 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1012 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1013 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1014 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1015 { 0 }
1016 };
1017
1018 static const CGEN_OPERAND_INSTANCE fmt_mov_ops[] = {
1019 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1020 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1021 { 0 }
1022 };
1023
1024 static const CGEN_OPERAND_INSTANCE fmt_movdr_ops[] = {
1025 { INPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1026 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1027 { 0 }
1028 };
1029
1030 static const CGEN_OPERAND_INSTANCE fmt_movps_ops[] = {
1031 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1032 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1033 { 0 }
1034 };
1035
1036 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
1037 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1038 { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1039 { 0 }
1040 };
1041
1042 static const CGEN_OPERAND_INSTANCE fmt_mov2ps_ops[] = {
1043 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1044 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1045 { 0 }
1046 };
1047
1048 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
1049 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1050 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1051 { 0 }
1052 };
1053
1054 static const CGEN_OPERAND_INSTANCE fmt_callr_ops[] = {
1055 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1056 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1057 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1058 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1059 { 0 }
1060 };
1061
1062 static const CGEN_OPERAND_INSTANCE fmt_call_ops[] = {
1063 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1064 { INPUT, "label12", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL12), 0, 0 },
1065 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1066 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1067 { 0 }
1068 };
1069
1070 static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
1071 { INPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1072 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1073 { 0 }
1074 };
1075
1076 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
1077 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1078 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
1079 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
1080 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1081 { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1082 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1083 { 0 }
1084 };
1085
1086 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
1087 { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1088 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
1089 { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1090 { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
1091 { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1092 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1093 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
1094 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
1095 { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
1096 { 0 }
1097 };
1098
1099 static const CGEN_OPERAND_INSTANCE fmt_bra_ops[] = {
1100 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1101 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1102 { 0 }
1103 };
1104
1105 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
1106 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1107 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1108 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1109 { 0 }
1110 };
1111
1112 static const CGEN_OPERAND_INSTANCE fmt_bc_ops[] = {
1113 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1114 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1115 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1116 { 0 }
1117 };
1118
1119 static const CGEN_OPERAND_INSTANCE fmt_bn_ops[] = {
1120 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1121 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1122 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1123 { 0 }
1124 };
1125
1126 static const CGEN_OPERAND_INSTANCE fmt_bv_ops[] = {
1127 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1128 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1129 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1130 { 0 }
1131 };
1132
1133 static const CGEN_OPERAND_INSTANCE fmt_blt_ops[] = {
1134 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1135 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1136 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1137 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1138 { 0 }
1139 };
1140
1141 static const CGEN_OPERAND_INSTANCE fmt_ble_ops[] = {
1142 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1143 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1144 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1145 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1146 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1147 { 0 }
1148 };
1149
1150 static const CGEN_OPERAND_INSTANCE fmt_bls_ops[] = {
1151 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1152 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1153 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1154 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1155 { 0 }
1156 };
1157
1158 static const CGEN_OPERAND_INSTANCE fmt_andccr_ops[] = {
1159 { INPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1160 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1161 { OUTPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1162 { 0 }
1163 };
1164
1165 #undef INPUT
1166 #undef OUTPUT
1167 #undef COND_REF
1168
1169 /* Instruction formats. */
1170
1171 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
1172
1173 static const CGEN_IFMT fmt_add = {
1174 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1175 };
1176
1177 static const CGEN_IFMT fmt_addi = {
1178 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1179 };
1180
1181 static const CGEN_IFMT fmt_add2 = {
1182 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1183 };
1184
1185 static const CGEN_IFMT fmt_addc = {
1186 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1187 };
1188
1189 static const CGEN_IFMT fmt_addn = {
1190 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1191 };
1192
1193 static const CGEN_IFMT fmt_addni = {
1194 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1195 };
1196
1197 static const CGEN_IFMT fmt_addn2 = {
1198 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1199 };
1200
1201 static const CGEN_IFMT fmt_cmp = {
1202 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1203 };
1204
1205 static const CGEN_IFMT fmt_cmpi = {
1206 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1207 };
1208
1209 static const CGEN_IFMT fmt_cmp2 = {
1210 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1211 };
1212
1213 static const CGEN_IFMT fmt_and = {
1214 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1215 };
1216
1217 static const CGEN_IFMT fmt_andm = {
1218 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1219 };
1220
1221 static const CGEN_IFMT fmt_andh = {
1222 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1223 };
1224
1225 static const CGEN_IFMT fmt_andb = {
1226 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1227 };
1228
1229 static const CGEN_IFMT fmt_bandl = {
1230 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1231 };
1232
1233 static const CGEN_IFMT fmt_btstl = {
1234 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1235 };
1236
1237 static const CGEN_IFMT fmt_mul = {
1238 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1239 };
1240
1241 static const CGEN_IFMT fmt_mulu = {
1242 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1243 };
1244
1245 static const CGEN_IFMT fmt_mulh = {
1246 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1247 };
1248
1249 static const CGEN_IFMT fmt_div0s = {
1250 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1251 };
1252
1253 static const CGEN_IFMT fmt_div3 = {
1254 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1255 };
1256
1257 static const CGEN_IFMT fmt_lsl = {
1258 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1259 };
1260
1261 static const CGEN_IFMT fmt_lsli = {
1262 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1263 };
1264
1265 static const CGEN_IFMT fmt_ldi8 = {
1266 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
1267 };
1268
1269 static const CGEN_IFMT fmt_ldi20 = {
1270 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
1271 };
1272
1273 static const CGEN_IFMT fmt_ldi32 = {
1274 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1275 };
1276
1277 static const CGEN_IFMT fmt_ld = {
1278 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1279 };
1280
1281 static const CGEN_IFMT fmt_lduh = {
1282 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1283 };
1284
1285 static const CGEN_IFMT fmt_ldub = {
1286 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1287 };
1288
1289 static const CGEN_IFMT fmt_ldr13 = {
1290 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1291 };
1292
1293 static const CGEN_IFMT fmt_ldr13uh = {
1294 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1295 };
1296
1297 static const CGEN_IFMT fmt_ldr13ub = {
1298 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1299 };
1300
1301 static const CGEN_IFMT fmt_ldr14 = {
1302 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1303 };
1304
1305 static const CGEN_IFMT fmt_ldr14uh = {
1306 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1307 };
1308
1309 static const CGEN_IFMT fmt_ldr14ub = {
1310 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1311 };
1312
1313 static const CGEN_IFMT fmt_ldr15 = {
1314 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1315 };
1316
1317 static const CGEN_IFMT fmt_ldr15gr = {
1318 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1319 };
1320
1321 static const CGEN_IFMT fmt_ldr15dr = {
1322 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1323 };
1324
1325 static const CGEN_IFMT fmt_ldr15ps = {
1326 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1327 };
1328
1329 static const CGEN_IFMT fmt_st = {
1330 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1331 };
1332
1333 static const CGEN_IFMT fmt_sth = {
1334 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1335 };
1336
1337 static const CGEN_IFMT fmt_stb = {
1338 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1339 };
1340
1341 static const CGEN_IFMT fmt_str13 = {
1342 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1343 };
1344
1345 static const CGEN_IFMT fmt_str13h = {
1346 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1347 };
1348
1349 static const CGEN_IFMT fmt_str13b = {
1350 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1351 };
1352
1353 static const CGEN_IFMT fmt_str14 = {
1354 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1355 };
1356
1357 static const CGEN_IFMT fmt_str14h = {
1358 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1359 };
1360
1361 static const CGEN_IFMT fmt_str14b = {
1362 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1363 };
1364
1365 static const CGEN_IFMT fmt_str15 = {
1366 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1367 };
1368
1369 static const CGEN_IFMT fmt_str15gr = {
1370 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1371 };
1372
1373 static const CGEN_IFMT fmt_str15dr = {
1374 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1375 };
1376
1377 static const CGEN_IFMT fmt_str15ps = {
1378 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1379 };
1380
1381 static const CGEN_IFMT fmt_mov = {
1382 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1383 };
1384
1385 static const CGEN_IFMT fmt_movdr = {
1386 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1387 };
1388
1389 static const CGEN_IFMT fmt_movps = {
1390 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1391 };
1392
1393 static const CGEN_IFMT fmt_mov2dr = {
1394 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1395 };
1396
1397 static const CGEN_IFMT fmt_mov2ps = {
1398 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1399 };
1400
1401 static const CGEN_IFMT fmt_jmp = {
1402 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1403 };
1404
1405 static const CGEN_IFMT fmt_callr = {
1406 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1407 };
1408
1409 static const CGEN_IFMT fmt_call = {
1410 16, 16, 0xf400, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
1411 };
1412
1413 static const CGEN_IFMT fmt_ret = {
1414 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1415 };
1416
1417 static const CGEN_IFMT fmt_int = {
1418 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1419 };
1420
1421 static const CGEN_IFMT fmt_reti = {
1422 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1423 };
1424
1425 static const CGEN_IFMT fmt_bra = {
1426 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1427 };
1428
1429 static const CGEN_IFMT fmt_beq = {
1430 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1431 };
1432
1433 static const CGEN_IFMT fmt_bc = {
1434 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1435 };
1436
1437 static const CGEN_IFMT fmt_bn = {
1438 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1439 };
1440
1441 static const CGEN_IFMT fmt_bv = {
1442 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1443 };
1444
1445 static const CGEN_IFMT fmt_blt = {
1446 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1447 };
1448
1449 static const CGEN_IFMT fmt_ble = {
1450 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1451 };
1452
1453 static const CGEN_IFMT fmt_bls = {
1454 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1455 };
1456
1457 static const CGEN_IFMT fmt_dmovr13 = {
1458 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1459 };
1460
1461 static const CGEN_IFMT fmt_dmovr13h = {
1462 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1463 };
1464
1465 static const CGEN_IFMT fmt_dmovr13b = {
1466 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1467 };
1468
1469 static const CGEN_IFMT fmt_ldres = {
1470 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1471 };
1472
1473 static const CGEN_IFMT fmt_copop = {
1474 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
1475 };
1476
1477 static const CGEN_IFMT fmt_copld = {
1478 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
1479 };
1480
1481 static const CGEN_IFMT fmt_copst = {
1482 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
1483 };
1484
1485 static const CGEN_IFMT fmt_andccr = {
1486 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1487 };
1488
1489 static const CGEN_IFMT fmt_stilm = {
1490 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1491 };
1492
1493 static const CGEN_IFMT fmt_addsp = {
1494 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
1495 };
1496
1497 static const CGEN_IFMT fmt_ldm0 = {
1498 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW), 0 }
1499 };
1500
1501 static const CGEN_IFMT fmt_ldm1 = {
1502 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI), 0 }
1503 };
1504
1505 static const CGEN_IFMT fmt_enter = {
1506 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
1507 };
1508
1509 static const CGEN_IFMT fmt_xchb = {
1510 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1511 };
1512
1513 #undef F
1514
1515 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1516 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1517 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1518
1519 /* The instruction table.
1520 This is currently non-static because the simulator accesses it
1521 directly. */
1522
1523 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
1524 {
1525 /* Special null first entry.
1526 A `num' value of zero is thus invalid.
1527 Also, the special `invalid' insn resides here. */
1528 { { 0 }, 0 },
1529 /* add $Rj,$Ri */
1530 {
1531 { 1, 1, 1, 1 },
1532 FR30_INSN_ADD, "add", "add",
1533 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1534 & fmt_add, { 0xa600 },
1535 (PTR) & fmt_add_ops[0],
1536 { 0, 0, { 0 } }
1537 },
1538 /* add $u4,$Ri */
1539 {
1540 { 1, 1, 1, 1 },
1541 FR30_INSN_ADDI, "addi", "add",
1542 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1543 & fmt_addi, { 0xa400 },
1544 (PTR) & fmt_addi_ops[0],
1545 { 0, 0, { 0 } }
1546 },
1547 /* add2 $m4,$Ri */
1548 {
1549 { 1, 1, 1, 1 },
1550 FR30_INSN_ADD2, "add2", "add2",
1551 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1552 & fmt_add2, { 0xa500 },
1553 (PTR) & fmt_add2_ops[0],
1554 { 0, 0, { 0 } }
1555 },
1556 /* addc $Rj,$Ri */
1557 {
1558 { 1, 1, 1, 1 },
1559 FR30_INSN_ADDC, "addc", "addc",
1560 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1561 & fmt_addc, { 0xa700 },
1562 (PTR) & fmt_addc_ops[0],
1563 { 0, 0, { 0 } }
1564 },
1565 /* addn $Rj,$Ri */
1566 {
1567 { 1, 1, 1, 1 },
1568 FR30_INSN_ADDN, "addn", "addn",
1569 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1570 & fmt_addn, { 0xa200 },
1571 (PTR) & fmt_addn_ops[0],
1572 { 0, 0, { 0 } }
1573 },
1574 /* addn $u4,$Ri */
1575 {
1576 { 1, 1, 1, 1 },
1577 FR30_INSN_ADDNI, "addni", "addn",
1578 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1579 & fmt_addni, { 0xa000 },
1580 (PTR) & fmt_addni_ops[0],
1581 { 0, 0, { 0 } }
1582 },
1583 /* addn2 $m4,$Ri */
1584 {
1585 { 1, 1, 1, 1 },
1586 FR30_INSN_ADDN2, "addn2", "addn2",
1587 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1588 & fmt_addn2, { 0xa100 },
1589 (PTR) & fmt_addn2_ops[0],
1590 { 0, 0, { 0 } }
1591 },
1592 /* sub $Rj,$Ri */
1593 {
1594 { 1, 1, 1, 1 },
1595 FR30_INSN_SUB, "sub", "sub",
1596 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1597 & fmt_add, { 0xac00 },
1598 (PTR) & fmt_add_ops[0],
1599 { 0, 0, { 0 } }
1600 },
1601 /* subc $Rj,$Ri */
1602 {
1603 { 1, 1, 1, 1 },
1604 FR30_INSN_SUBC, "subc", "subc",
1605 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1606 & fmt_addc, { 0xad00 },
1607 (PTR) & fmt_addc_ops[0],
1608 { 0, 0, { 0 } }
1609 },
1610 /* subn $Rj,$Ri */
1611 {
1612 { 1, 1, 1, 1 },
1613 FR30_INSN_SUBN, "subn", "subn",
1614 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1615 & fmt_addn, { 0xae00 },
1616 (PTR) & fmt_addn_ops[0],
1617 { 0, 0, { 0 } }
1618 },
1619 /* cmp $Rj,$Ri */
1620 {
1621 { 1, 1, 1, 1 },
1622 FR30_INSN_CMP, "cmp", "cmp",
1623 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1624 & fmt_cmp, { 0xaa00 },
1625 (PTR) & fmt_cmp_ops[0],
1626 { 0, 0, { 0 } }
1627 },
1628 /* cmp $u4,$Ri */
1629 {
1630 { 1, 1, 1, 1 },
1631 FR30_INSN_CMPI, "cmpi", "cmp",
1632 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1633 & fmt_cmpi, { 0xa800 },
1634 (PTR) & fmt_cmpi_ops[0],
1635 { 0, 0, { 0 } }
1636 },
1637 /* cmp2 $m4,$Ri */
1638 {
1639 { 1, 1, 1, 1 },
1640 FR30_INSN_CMP2, "cmp2", "cmp2",
1641 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1642 & fmt_cmp2, { 0xa900 },
1643 (PTR) & fmt_cmp2_ops[0],
1644 { 0, 0, { 0 } }
1645 },
1646 /* and $Rj,$Ri */
1647 {
1648 { 1, 1, 1, 1 },
1649 FR30_INSN_AND, "and", "and",
1650 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1651 & fmt_and, { 0x8200 },
1652 (PTR) & fmt_and_ops[0],
1653 { 0, 0, { 0 } }
1654 },
1655 /* or $Rj,$Ri */
1656 {
1657 { 1, 1, 1, 1 },
1658 FR30_INSN_OR, "or", "or",
1659 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1660 & fmt_and, { 0x9200 },
1661 (PTR) & fmt_and_ops[0],
1662 { 0, 0, { 0 } }
1663 },
1664 /* eor $Rj,$Ri */
1665 {
1666 { 1, 1, 1, 1 },
1667 FR30_INSN_EOR, "eor", "eor",
1668 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1669 & fmt_and, { 0x9a00 },
1670 (PTR) & fmt_and_ops[0],
1671 { 0, 0, { 0 } }
1672 },
1673 /* and $Rj,@$Ri */
1674 {
1675 { 1, 1, 1, 1 },
1676 FR30_INSN_ANDM, "andm", "and",
1677 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1678 & fmt_andm, { 0x8400 },
1679 (PTR) & fmt_andm_ops[0],
1680 { 0, 0, { 0 } }
1681 },
1682 /* andh $Rj,@$Ri */
1683 {
1684 { 1, 1, 1, 1 },
1685 FR30_INSN_ANDH, "andh", "andh",
1686 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1687 & fmt_andh, { 0x8500 },
1688 (PTR) & fmt_andh_ops[0],
1689 { 0, 0, { 0 } }
1690 },
1691 /* andb $Rj,@$Ri */
1692 {
1693 { 1, 1, 1, 1 },
1694 FR30_INSN_ANDB, "andb", "andb",
1695 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1696 & fmt_andb, { 0x8600 },
1697 (PTR) & fmt_andb_ops[0],
1698 { 0, 0, { 0 } }
1699 },
1700 /* or $Rj,@$Ri */
1701 {
1702 { 1, 1, 1, 1 },
1703 FR30_INSN_ORM, "orm", "or",
1704 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1705 & fmt_andm, { 0x9400 },
1706 (PTR) & fmt_andm_ops[0],
1707 { 0, 0, { 0 } }
1708 },
1709 /* orh $Rj,@$Ri */
1710 {
1711 { 1, 1, 1, 1 },
1712 FR30_INSN_ORH, "orh", "orh",
1713 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1714 & fmt_andh, { 0x9500 },
1715 (PTR) & fmt_andh_ops[0],
1716 { 0, 0, { 0 } }
1717 },
1718 /* orb $Rj,@$Ri */
1719 {
1720 { 1, 1, 1, 1 },
1721 FR30_INSN_ORB, "orb", "orb",
1722 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1723 & fmt_andb, { 0x9600 },
1724 (PTR) & fmt_andb_ops[0],
1725 { 0, 0, { 0 } }
1726 },
1727 /* eor $Rj,@$Ri */
1728 {
1729 { 1, 1, 1, 1 },
1730 FR30_INSN_EORM, "eorm", "eor",
1731 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1732 & fmt_andm, { 0x9c00 },
1733 (PTR) & fmt_andm_ops[0],
1734 { 0, 0, { 0 } }
1735 },
1736 /* eorh $Rj,@$Ri */
1737 {
1738 { 1, 1, 1, 1 },
1739 FR30_INSN_EORH, "eorh", "eorh",
1740 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1741 & fmt_andh, { 0x9d00 },
1742 (PTR) & fmt_andh_ops[0],
1743 { 0, 0, { 0 } }
1744 },
1745 /* eorb $Rj,@$Ri */
1746 {
1747 { 1, 1, 1, 1 },
1748 FR30_INSN_EORB, "eorb", "eorb",
1749 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1750 & fmt_andb, { 0x9e00 },
1751 (PTR) & fmt_andb_ops[0],
1752 { 0, 0, { 0 } }
1753 },
1754 /* bandl $u4,@$Ri */
1755 {
1756 { 1, 1, 1, 1 },
1757 FR30_INSN_BANDL, "bandl", "bandl",
1758 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1759 & fmt_bandl, { 0x8000 },
1760 (PTR) & fmt_bandl_ops[0],
1761 { 0, 0, { 0 } }
1762 },
1763 /* borl $u4,@$Ri */
1764 {
1765 { 1, 1, 1, 1 },
1766 FR30_INSN_BORL, "borl", "borl",
1767 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1768 & fmt_bandl, { 0x9000 },
1769 (PTR) & fmt_bandl_ops[0],
1770 { 0, 0, { 0 } }
1771 },
1772 /* beorl $u4,@$Ri */
1773 {
1774 { 1, 1, 1, 1 },
1775 FR30_INSN_BEORL, "beorl", "beorl",
1776 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1777 & fmt_bandl, { 0x9800 },
1778 (PTR) & fmt_bandl_ops[0],
1779 { 0, 0, { 0 } }
1780 },
1781 /* bandh $u4,@$Ri */
1782 {
1783 { 1, 1, 1, 1 },
1784 FR30_INSN_BANDH, "bandh", "bandh",
1785 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1786 & fmt_bandl, { 0x8100 },
1787 (PTR) & fmt_bandl_ops[0],
1788 { 0, 0, { 0 } }
1789 },
1790 /* borh $u4,@$Ri */
1791 {
1792 { 1, 1, 1, 1 },
1793 FR30_INSN_BORH, "borh", "borh",
1794 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1795 & fmt_bandl, { 0x9100 },
1796 (PTR) & fmt_bandl_ops[0],
1797 { 0, 0, { 0 } }
1798 },
1799 /* beorh $u4,@$Ri */
1800 {
1801 { 1, 1, 1, 1 },
1802 FR30_INSN_BEORH, "beorh", "beorh",
1803 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1804 & fmt_bandl, { 0x9900 },
1805 (PTR) & fmt_bandl_ops[0],
1806 { 0, 0, { 0 } }
1807 },
1808 /* btstl $u4,@$Ri */
1809 {
1810 { 1, 1, 1, 1 },
1811 FR30_INSN_BTSTL, "btstl", "btstl",
1812 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1813 & fmt_btstl, { 0x8800 },
1814 (PTR) & fmt_btstl_ops[0],
1815 { 0, 0, { 0 } }
1816 },
1817 /* btsth $u4,@$Ri */
1818 {
1819 { 1, 1, 1, 1 },
1820 FR30_INSN_BTSTH, "btsth", "btsth",
1821 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1822 & fmt_btstl, { 0x8900 },
1823 (PTR) & fmt_btstl_ops[0],
1824 { 0, 0, { 0 } }
1825 },
1826 /* mul $Rj,$Ri */
1827 {
1828 { 1, 1, 1, 1 },
1829 FR30_INSN_MUL, "mul", "mul",
1830 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1831 & fmt_mul, { 0xaf00 },
1832 (PTR) & fmt_mul_ops[0],
1833 { 0, 0, { 0 } }
1834 },
1835 /* mulu $Rj,$Ri */
1836 {
1837 { 1, 1, 1, 1 },
1838 FR30_INSN_MULU, "mulu", "mulu",
1839 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1840 & fmt_mulu, { 0xab00 },
1841 (PTR) & fmt_mulu_ops[0],
1842 { 0, 0, { 0 } }
1843 },
1844 /* mulh $Rj,$Ri */
1845 {
1846 { 1, 1, 1, 1 },
1847 FR30_INSN_MULH, "mulh", "mulh",
1848 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1849 & fmt_mulh, { 0xbf00 },
1850 (PTR) & fmt_mulh_ops[0],
1851 { 0, 0, { 0 } }
1852 },
1853 /* muluh $Rj,$Ri */
1854 {
1855 { 1, 1, 1, 1 },
1856 FR30_INSN_MULUH, "muluh", "muluh",
1857 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1858 & fmt_mulh, { 0xbb00 },
1859 (PTR) & fmt_mulh_ops[0],
1860 { 0, 0, { 0 } }
1861 },
1862 /* div0s $Ri */
1863 {
1864 { 1, 1, 1, 1 },
1865 FR30_INSN_DIV0S, "div0s", "div0s",
1866 { { MNEM, ' ', OP (RI), 0 } },
1867 & fmt_div0s, { 0x9740 },
1868 (PTR) 0,
1869 { 0, 0, { 0 } }
1870 },
1871 /* div0u $Ri */
1872 {
1873 { 1, 1, 1, 1 },
1874 FR30_INSN_DIV0U, "div0u", "div0u",
1875 { { MNEM, ' ', OP (RI), 0 } },
1876 & fmt_div0s, { 0x9750 },
1877 (PTR) 0,
1878 { 0, 0, { 0 } }
1879 },
1880 /* div1 $Ri */
1881 {
1882 { 1, 1, 1, 1 },
1883 FR30_INSN_DIV1, "div1", "div1",
1884 { { MNEM, ' ', OP (RI), 0 } },
1885 & fmt_div0s, { 0x9760 },
1886 (PTR) 0,
1887 { 0, 0, { 0 } }
1888 },
1889 /* div2 $Ri */
1890 {
1891 { 1, 1, 1, 1 },
1892 FR30_INSN_DIV2, "div2", "div2",
1893 { { MNEM, ' ', OP (RI), 0 } },
1894 & fmt_div0s, { 0x9770 },
1895 (PTR) 0,
1896 { 0, 0, { 0 } }
1897 },
1898 /* div3 */
1899 {
1900 { 1, 1, 1, 1 },
1901 FR30_INSN_DIV3, "div3", "div3",
1902 { { MNEM, 0 } },
1903 & fmt_div3, { 0x9f60 },
1904 (PTR) 0,
1905 { 0, 0, { 0 } }
1906 },
1907 /* div4s */
1908 {
1909 { 1, 1, 1, 1 },
1910 FR30_INSN_DIV4S, "div4s", "div4s",
1911 { { MNEM, 0 } },
1912 & fmt_div3, { 0x9f70 },
1913 (PTR) 0,
1914 { 0, 0, { 0 } }
1915 },
1916 /* lsl $Rj,$Ri */
1917 {
1918 { 1, 1, 1, 1 },
1919 FR30_INSN_LSL, "lsl", "lsl",
1920 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1921 & fmt_lsl, { 0xb600 },
1922 (PTR) & fmt_lsl_ops[0],
1923 { 0, 0, { 0 } }
1924 },
1925 /* lsl $u4,$Ri */
1926 {
1927 { 1, 1, 1, 1 },
1928 FR30_INSN_LSLI, "lsli", "lsl",
1929 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1930 & fmt_lsli, { 0xb400 },
1931 (PTR) & fmt_lsli_ops[0],
1932 { 0, 0, { 0 } }
1933 },
1934 /* lsl2 $u4,$Ri */
1935 {
1936 { 1, 1, 1, 1 },
1937 FR30_INSN_LSL2, "lsl2", "lsl2",
1938 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1939 & fmt_lsli, { 0xb500 },
1940 (PTR) & fmt_lsli_ops[0],
1941 { 0, 0, { 0 } }
1942 },
1943 /* lsr $Rj,$Ri */
1944 {
1945 { 1, 1, 1, 1 },
1946 FR30_INSN_LSR, "lsr", "lsr",
1947 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1948 & fmt_lsl, { 0xb200 },
1949 (PTR) & fmt_lsl_ops[0],
1950 { 0, 0, { 0 } }
1951 },
1952 /* lsr $u4,$Ri */
1953 {
1954 { 1, 1, 1, 1 },
1955 FR30_INSN_LSRI, "lsri", "lsr",
1956 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1957 & fmt_lsli, { 0xb000 },
1958 (PTR) & fmt_lsli_ops[0],
1959 { 0, 0, { 0 } }
1960 },
1961 /* lsr2 $u4,$Ri */
1962 {
1963 { 1, 1, 1, 1 },
1964 FR30_INSN_LSR2, "lsr2", "lsr2",
1965 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1966 & fmt_lsli, { 0xb100 },
1967 (PTR) & fmt_lsli_ops[0],
1968 { 0, 0, { 0 } }
1969 },
1970 /* asr $Rj,$Ri */
1971 {
1972 { 1, 1, 1, 1 },
1973 FR30_INSN_ASR, "asr", "asr",
1974 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1975 & fmt_lsl, { 0xba00 },
1976 (PTR) & fmt_lsl_ops[0],
1977 { 0, 0, { 0 } }
1978 },
1979 /* asr $u4,$Ri */
1980 {
1981 { 1, 1, 1, 1 },
1982 FR30_INSN_ASRI, "asri", "asr",
1983 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1984 & fmt_lsli, { 0xb800 },
1985 (PTR) & fmt_lsli_ops[0],
1986 { 0, 0, { 0 } }
1987 },
1988 /* asr2 $u4,$Ri */
1989 {
1990 { 1, 1, 1, 1 },
1991 FR30_INSN_ASR2, "asr2", "asr2",
1992 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1993 & fmt_lsli, { 0xb900 },
1994 (PTR) & fmt_lsli_ops[0],
1995 { 0, 0, { 0 } }
1996 },
1997 /* ldi:8 $i8,$Ri */
1998 {
1999 { 1, 1, 1, 1 },
2000 FR30_INSN_LDI8, "ldi8", "ldi:8",
2001 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
2002 & fmt_ldi8, { 0xc000 },
2003 (PTR) & fmt_ldi8_ops[0],
2004 { 0, 0, { 0 } }
2005 },
2006 /* ldi:20 $i20,$Ri */
2007 {
2008 { 1, 1, 1, 1 },
2009 FR30_INSN_LDI20, "ldi20", "ldi:20",
2010 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
2011 & fmt_ldi20, { 0x9b00 },
2012 (PTR) & fmt_ldi20_ops[0],
2013 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
2014 },
2015 /* ldi:32 $i32,$Ri */
2016 {
2017 { 1, 1, 1, 1 },
2018 FR30_INSN_LDI32, "ldi32", "ldi:32",
2019 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2020 & fmt_ldi32, { 0x9f80 },
2021 (PTR) & fmt_ldi32_ops[0],
2022 { 0, 0, { 0 } }
2023 },
2024 /* ld @$Rj,$Ri */
2025 {
2026 { 1, 1, 1, 1 },
2027 FR30_INSN_LD, "ld", "ld",
2028 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2029 & fmt_ld, { 0x400 },
2030 (PTR) & fmt_ld_ops[0],
2031 { 0, 0, { 0 } }
2032 },
2033 /* lduh @$Rj,$Ri */
2034 {
2035 { 1, 1, 1, 1 },
2036 FR30_INSN_LDUH, "lduh", "lduh",
2037 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2038 & fmt_lduh, { 0x500 },
2039 (PTR) & fmt_lduh_ops[0],
2040 { 0, 0, { 0 } }
2041 },
2042 /* ldub @$Rj,$Ri */
2043 {
2044 { 1, 1, 1, 1 },
2045 FR30_INSN_LDUB, "ldub", "ldub",
2046 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2047 & fmt_ldub, { 0x600 },
2048 (PTR) & fmt_ldub_ops[0],
2049 { 0, 0, { 0 } }
2050 },
2051 /* ld @($R13,$Rj),$Ri */
2052 {
2053 { 1, 1, 1, 1 },
2054 FR30_INSN_LDR13, "ldr13", "ld",
2055 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2056 & fmt_ldr13, { 0x0 },
2057 (PTR) & fmt_ldr13_ops[0],
2058 { 0, 0, { 0 } }
2059 },
2060 /* lduh @($R13,$Rj),$Ri */
2061 {
2062 { 1, 1, 1, 1 },
2063 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
2064 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2065 & fmt_ldr13uh, { 0x100 },
2066 (PTR) & fmt_ldr13uh_ops[0],
2067 { 0, 0, { 0 } }
2068 },
2069 /* ldub @($R13,$Rj),$Ri */
2070 {
2071 { 1, 1, 1, 1 },
2072 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
2073 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2074 & fmt_ldr13ub, { 0x200 },
2075 (PTR) & fmt_ldr13ub_ops[0],
2076 { 0, 0, { 0 } }
2077 },
2078 /* ld @($R14,$disp10),$Ri */
2079 {
2080 { 1, 1, 1, 1 },
2081 FR30_INSN_LDR14, "ldr14", "ld",
2082 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
2083 & fmt_ldr14, { 0x2000 },
2084 (PTR) & fmt_ldr14_ops[0],
2085 { 0, 0, { 0 } }
2086 },
2087 /* lduh @($R14,$disp9),$Ri */
2088 {
2089 { 1, 1, 1, 1 },
2090 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
2091 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
2092 & fmt_ldr14uh, { 0x4000 },
2093 (PTR) & fmt_ldr14uh_ops[0],
2094 { 0, 0, { 0 } }
2095 },
2096 /* ldub @($R14,$disp8),$Ri */
2097 {
2098 { 1, 1, 1, 1 },
2099 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
2100 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
2101 & fmt_ldr14ub, { 0x6000 },
2102 (PTR) & fmt_ldr14ub_ops[0],
2103 { 0, 0, { 0 } }
2104 },
2105 /* ld @($R15,$udisp6),$Ri */
2106 {
2107 { 1, 1, 1, 1 },
2108 FR30_INSN_LDR15, "ldr15", "ld",
2109 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
2110 & fmt_ldr15, { 0x300 },
2111 (PTR) & fmt_ldr15_ops[0],
2112 { 0, 0, { 0 } }
2113 },
2114 /* ld @$R15+,$Ri */
2115 {
2116 { 1, 1, 1, 1 },
2117 FR30_INSN_LDR15GR, "ldr15gr", "ld",
2118 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
2119 & fmt_ldr15gr, { 0x700 },
2120 (PTR) & fmt_ldr15gr_ops[0],
2121 { 0, 0, { 0 } }
2122 },
2123 /* ld @$R15+,$Rs2 */
2124 {
2125 { 1, 1, 1, 1 },
2126 FR30_INSN_LDR15DR, "ldr15dr", "ld",
2127 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
2128 & fmt_ldr15dr, { 0x780 },
2129 (PTR) & fmt_ldr15dr_ops[0],
2130 { 0, 0, { 0 } }
2131 },
2132 /* ld @$R15+,$ps */
2133 {
2134 { 1, 1, 1, 1 },
2135 FR30_INSN_LDR15PS, "ldr15ps", "ld",
2136 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
2137 & fmt_ldr15ps, { 0x790 },
2138 (PTR) & fmt_ldr15ps_ops[0],
2139 { 0, 0, { 0 } }
2140 },
2141 /* st $Ri,@$Rj */
2142 {
2143 { 1, 1, 1, 1 },
2144 FR30_INSN_ST, "st", "st",
2145 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2146 & fmt_st, { 0x1400 },
2147 (PTR) & fmt_st_ops[0],
2148 { 0, 0, { 0 } }
2149 },
2150 /* sth $Ri,@$Rj */
2151 {
2152 { 1, 1, 1, 1 },
2153 FR30_INSN_STH, "sth", "sth",
2154 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2155 & fmt_sth, { 0x1500 },
2156 (PTR) & fmt_sth_ops[0],
2157 { 0, 0, { 0 } }
2158 },
2159 /* stb $Ri,@$Rj */
2160 {
2161 { 1, 1, 1, 1 },
2162 FR30_INSN_STB, "stb", "stb",
2163 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2164 & fmt_stb, { 0x1600 },
2165 (PTR) & fmt_stb_ops[0],
2166 { 0, 0, { 0 } }
2167 },
2168 /* st $Ri,@($R13,$Rj) */
2169 {
2170 { 1, 1, 1, 1 },
2171 FR30_INSN_STR13, "str13", "st",
2172 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2173 & fmt_str13, { 0x1000 },
2174 (PTR) & fmt_str13_ops[0],
2175 { 0, 0, { 0 } }
2176 },
2177 /* sth $Ri,@($R13,$Rj) */
2178 {
2179 { 1, 1, 1, 1 },
2180 FR30_INSN_STR13H, "str13h", "sth",
2181 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2182 & fmt_str13h, { 0x1100 },
2183 (PTR) & fmt_str13h_ops[0],
2184 { 0, 0, { 0 } }
2185 },
2186 /* stb $Ri,@($R13,$Rj) */
2187 {
2188 { 1, 1, 1, 1 },
2189 FR30_INSN_STR13B, "str13b", "stb",
2190 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2191 & fmt_str13b, { 0x1200 },
2192 (PTR) & fmt_str13b_ops[0],
2193 { 0, 0, { 0 } }
2194 },
2195 /* st Ri,@($R14,$disp10) */
2196 {
2197 { 1, 1, 1, 1 },
2198 FR30_INSN_STR14, "str14", "st",
2199 { { MNEM, ' ', 'R', 'i', ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
2200 & fmt_str14, { 0x3000 },
2201 (PTR) & fmt_str14_ops[0],
2202 { 0, 0, { 0 } }
2203 },
2204 /* sth Ri,@($R14,$disp9) */
2205 {
2206 { 1, 1, 1, 1 },
2207 FR30_INSN_STR14H, "str14h", "sth",
2208 { { MNEM, ' ', 'R', 'i', ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
2209 & fmt_str14h, { 0x5000 },
2210 (PTR) & fmt_str14h_ops[0],
2211 { 0, 0, { 0 } }
2212 },
2213 /* stb Ri,@($R14,$disp8) */
2214 {
2215 { 1, 1, 1, 1 },
2216 FR30_INSN_STR14B, "str14b", "stb",
2217 { { MNEM, ' ', 'R', 'i', ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
2218 & fmt_str14b, { 0x7000 },
2219 (PTR) & fmt_str14b_ops[0],
2220 { 0, 0, { 0 } }
2221 },
2222 /* st $Ri,@($R15,$udisp6) */
2223 {
2224 { 1, 1, 1, 1 },
2225 FR30_INSN_STR15, "str15", "st",
2226 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
2227 & fmt_str15, { 0x1300 },
2228 (PTR) & fmt_str15_ops[0],
2229 { 0, 0, { 0 } }
2230 },
2231 /* st $Ri,@-$R15 */
2232 {
2233 { 1, 1, 1, 1 },
2234 FR30_INSN_STR15GR, "str15gr", "st",
2235 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
2236 & fmt_str15gr, { 0x1700 },
2237 (PTR) & fmt_str15gr_ops[0],
2238 { 0, 0, { 0 } }
2239 },
2240 /* st $Rs2,@-$R15 */
2241 {
2242 { 1, 1, 1, 1 },
2243 FR30_INSN_STR15DR, "str15dr", "st",
2244 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
2245 & fmt_str15dr, { 0x1780 },
2246 (PTR) & fmt_str15dr_ops[0],
2247 { 0, 0, { 0 } }
2248 },
2249 /* st $ps,@-$R15 */
2250 {
2251 { 1, 1, 1, 1 },
2252 FR30_INSN_STR15PS, "str15ps", "st",
2253 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
2254 & fmt_str15ps, { 0x1790 },
2255 (PTR) & fmt_str15ps_ops[0],
2256 { 0, 0, { 0 } }
2257 },
2258 /* mov $Rj,$Ri */
2259 {
2260 { 1, 1, 1, 1 },
2261 FR30_INSN_MOV, "mov", "mov",
2262 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2263 & fmt_mov, { 0x8b00 },
2264 (PTR) & fmt_mov_ops[0],
2265 { 0, 0, { 0 } }
2266 },
2267 /* mov $Rs1,$Ri */
2268 {
2269 { 1, 1, 1, 1 },
2270 FR30_INSN_MOVDR, "movdr", "mov",
2271 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
2272 & fmt_movdr, { 0xb700 },
2273 (PTR) & fmt_movdr_ops[0],
2274 { 0, 0, { 0 } }
2275 },
2276 /* mov $ps,$Ri */
2277 {
2278 { 1, 1, 1, 1 },
2279 FR30_INSN_MOVPS, "movps", "mov",
2280 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
2281 & fmt_movps, { 0x1710 },
2282 (PTR) & fmt_movps_ops[0],
2283 { 0, 0, { 0 } }
2284 },
2285 /* mov $Ri,$Rs1 */
2286 {
2287 { 1, 1, 1, 1 },
2288 FR30_INSN_MOV2DR, "mov2dr", "mov",
2289 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
2290 & fmt_mov2dr, { 0xb300 },
2291 (PTR) & fmt_mov2dr_ops[0],
2292 { 0, 0, { 0 } }
2293 },
2294 /* mov $Ri,$ps */
2295 {
2296 { 1, 1, 1, 1 },
2297 FR30_INSN_MOV2PS, "mov2ps", "mov",
2298 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
2299 & fmt_mov2ps, { 0x710 },
2300 (PTR) & fmt_mov2ps_ops[0],
2301 { 0, 0, { 0 } }
2302 },
2303 /* jmp @$Ri */
2304 {
2305 { 1, 1, 1, 1 },
2306 FR30_INSN_JMP, "jmp", "jmp",
2307 { { MNEM, ' ', '@', OP (RI), 0 } },
2308 & fmt_jmp, { 0x9700 },
2309 (PTR) & fmt_jmp_ops[0],
2310 { 0, 0|A(UNCOND_CTI), { 0 } }
2311 },
2312 /* jmp:d @$Ri */
2313 {
2314 { 1, 1, 1, 1 },
2315 FR30_INSN_JMPD, "jmpd", "jmp:d",
2316 { { MNEM, ' ', '@', OP (RI), 0 } },
2317 & fmt_jmp, { 0x9f00 },
2318 (PTR) & fmt_jmp_ops[0],
2319 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2320 },
2321 /* call @$Ri */
2322 {
2323 { 1, 1, 1, 1 },
2324 FR30_INSN_CALLR, "callr", "call",
2325 { { MNEM, ' ', '@', OP (RI), 0 } },
2326 & fmt_callr, { 0x9710 },
2327 (PTR) & fmt_callr_ops[0],
2328 { 0, 0|A(UNCOND_CTI), { 0 } }
2329 },
2330 /* call:d @$Ri */
2331 {
2332 { 1, 1, 1, 1 },
2333 FR30_INSN_CALLRD, "callrd", "call:d",
2334 { { MNEM, ' ', '@', OP (RI), 0 } },
2335 & fmt_callr, { 0x9f10 },
2336 (PTR) & fmt_callr_ops[0],
2337 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2338 },
2339 /* call $label12 */
2340 {
2341 { 1, 1, 1, 1 },
2342 FR30_INSN_CALL, "call", "call",
2343 { { MNEM, ' ', OP (LABEL12), 0 } },
2344 & fmt_call, { 0xd000 },
2345 (PTR) & fmt_call_ops[0],
2346 { 0, 0|A(UNCOND_CTI), { 0 } }
2347 },
2348 /* call:d $label12 */
2349 {
2350 { 1, 1, 1, 1 },
2351 FR30_INSN_CALLD, "calld", "call:d",
2352 { { MNEM, ' ', OP (LABEL12), 0 } },
2353 & fmt_call, { 0xd400 },
2354 (PTR) & fmt_call_ops[0],
2355 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2356 },
2357 /* ret */
2358 {
2359 { 1, 1, 1, 1 },
2360 FR30_INSN_RET, "ret", "ret",
2361 { { MNEM, 0 } },
2362 & fmt_ret, { 0x9720 },
2363 (PTR) & fmt_ret_ops[0],
2364 { 0, 0|A(UNCOND_CTI), { 0 } }
2365 },
2366 /* ret:d */
2367 {
2368 { 1, 1, 1, 1 },
2369 FR30_INSN_RET_D, "ret:d", "ret:d",
2370 { { MNEM, 0 } },
2371 & fmt_ret, { 0x9f20 },
2372 (PTR) & fmt_ret_ops[0],
2373 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2374 },
2375 /* int $u8 */
2376 {
2377 { 1, 1, 1, 1 },
2378 FR30_INSN_INT, "int", "int",
2379 { { MNEM, ' ', OP (U8), 0 } },
2380 & fmt_int, { 0x1f00 },
2381 (PTR) & fmt_int_ops[0],
2382 { 0, 0|A(UNCOND_CTI), { 0 } }
2383 },
2384 /* inte */
2385 {
2386 { 1, 1, 1, 1 },
2387 FR30_INSN_INTE, "inte", "inte",
2388 { { MNEM, 0 } },
2389 & fmt_div3, { 0x9f30 },
2390 (PTR) 0,
2391 { 0, 0, { 0 } }
2392 },
2393 /* reti */
2394 {
2395 { 1, 1, 1, 1 },
2396 FR30_INSN_RETI, "reti", "reti",
2397 { { MNEM, 0 } },
2398 & fmt_reti, { 0x9730 },
2399 (PTR) & fmt_reti_ops[0],
2400 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2401 },
2402 /* bra $label9 */
2403 {
2404 { 1, 1, 1, 1 },
2405 FR30_INSN_BRA, "bra", "bra",
2406 { { MNEM, ' ', OP (LABEL9), 0 } },
2407 & fmt_bra, { 0xe000 },
2408 (PTR) & fmt_bra_ops[0],
2409 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2410 },
2411 /* bra:d $label9 */
2412 {
2413 { 1, 1, 1, 1 },
2414 FR30_INSN_BRAD, "brad", "bra:d",
2415 { { MNEM, ' ', OP (LABEL9), 0 } },
2416 & fmt_bra, { 0xf000 },
2417 (PTR) & fmt_bra_ops[0],
2418 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2419 },
2420 /* bno $label9 */
2421 {
2422 { 1, 1, 1, 1 },
2423 FR30_INSN_BNO, "bno", "bno",
2424 { { MNEM, ' ', OP (LABEL9), 0 } },
2425 & fmt_bra, { 0xe100 },
2426 (PTR) & fmt_bra_ops[0],
2427 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2428 },
2429 /* bno:d $label9 */
2430 {
2431 { 1, 1, 1, 1 },
2432 FR30_INSN_BNOD, "bnod", "bno:d",
2433 { { MNEM, ' ', OP (LABEL9), 0 } },
2434 & fmt_bra, { 0xf100 },
2435 (PTR) & fmt_bra_ops[0],
2436 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2437 },
2438 /* beq $label9 */
2439 {
2440 { 1, 1, 1, 1 },
2441 FR30_INSN_BEQ, "beq", "beq",
2442 { { MNEM, ' ', OP (LABEL9), 0 } },
2443 & fmt_beq, { 0xe200 },
2444 (PTR) & fmt_beq_ops[0],
2445 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2446 },
2447 /* beq:d $label9 */
2448 {
2449 { 1, 1, 1, 1 },
2450 FR30_INSN_BEQD, "beqd", "beq:d",
2451 { { MNEM, ' ', OP (LABEL9), 0 } },
2452 & fmt_beq, { 0xf200 },
2453 (PTR) & fmt_beq_ops[0],
2454 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2455 },
2456 /* bne $label9 */
2457 {
2458 { 1, 1, 1, 1 },
2459 FR30_INSN_BNE, "bne", "bne",
2460 { { MNEM, ' ', OP (LABEL9), 0 } },
2461 & fmt_beq, { 0xe300 },
2462 (PTR) & fmt_beq_ops[0],
2463 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2464 },
2465 /* bne:d $label9 */
2466 {
2467 { 1, 1, 1, 1 },
2468 FR30_INSN_BNED, "bned", "bne:d",
2469 { { MNEM, ' ', OP (LABEL9), 0 } },
2470 & fmt_beq, { 0xf300 },
2471 (PTR) & fmt_beq_ops[0],
2472 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2473 },
2474 /* bc $label9 */
2475 {
2476 { 1, 1, 1, 1 },
2477 FR30_INSN_BC, "bc", "bc",
2478 { { MNEM, ' ', OP (LABEL9), 0 } },
2479 & fmt_bc, { 0xe400 },
2480 (PTR) & fmt_bc_ops[0],
2481 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2482 },
2483 /* bc:d $label9 */
2484 {
2485 { 1, 1, 1, 1 },
2486 FR30_INSN_BCD, "bcd", "bc:d",
2487 { { MNEM, ' ', OP (LABEL9), 0 } },
2488 & fmt_bc, { 0xf400 },
2489 (PTR) & fmt_bc_ops[0],
2490 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2491 },
2492 /* bnc $label9 */
2493 {
2494 { 1, 1, 1, 1 },
2495 FR30_INSN_BNC, "bnc", "bnc",
2496 { { MNEM, ' ', OP (LABEL9), 0 } },
2497 & fmt_bc, { 0xe500 },
2498 (PTR) & fmt_bc_ops[0],
2499 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2500 },
2501 /* bnc:d $label9 */
2502 {
2503 { 1, 1, 1, 1 },
2504 FR30_INSN_BNCD, "bncd", "bnc:d",
2505 { { MNEM, ' ', OP (LABEL9), 0 } },
2506 & fmt_bc, { 0xf500 },
2507 (PTR) & fmt_bc_ops[0],
2508 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2509 },
2510 /* bn $label9 */
2511 {
2512 { 1, 1, 1, 1 },
2513 FR30_INSN_BN, "bn", "bn",
2514 { { MNEM, ' ', OP (LABEL9), 0 } },
2515 & fmt_bn, { 0xe600 },
2516 (PTR) & fmt_bn_ops[0],
2517 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2518 },
2519 /* bn:d $label9 */
2520 {
2521 { 1, 1, 1, 1 },
2522 FR30_INSN_BND, "bnd", "bn:d",
2523 { { MNEM, ' ', OP (LABEL9), 0 } },
2524 & fmt_bn, { 0xf600 },
2525 (PTR) & fmt_bn_ops[0],
2526 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2527 },
2528 /* bp $label9 */
2529 {
2530 { 1, 1, 1, 1 },
2531 FR30_INSN_BP, "bp", "bp",
2532 { { MNEM, ' ', OP (LABEL9), 0 } },
2533 & fmt_bn, { 0xe700 },
2534 (PTR) & fmt_bn_ops[0],
2535 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2536 },
2537 /* bp:d $label9 */
2538 {
2539 { 1, 1, 1, 1 },
2540 FR30_INSN_BPD, "bpd", "bp:d",
2541 { { MNEM, ' ', OP (LABEL9), 0 } },
2542 & fmt_bn, { 0xf700 },
2543 (PTR) & fmt_bn_ops[0],
2544 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2545 },
2546 /* bv $label9 */
2547 {
2548 { 1, 1, 1, 1 },
2549 FR30_INSN_BV, "bv", "bv",
2550 { { MNEM, ' ', OP (LABEL9), 0 } },
2551 & fmt_bv, { 0xe800 },
2552 (PTR) & fmt_bv_ops[0],
2553 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2554 },
2555 /* bv:d $label9 */
2556 {
2557 { 1, 1, 1, 1 },
2558 FR30_INSN_BVD, "bvd", "bv:d",
2559 { { MNEM, ' ', OP (LABEL9), 0 } },
2560 & fmt_bv, { 0xf800 },
2561 (PTR) & fmt_bv_ops[0],
2562 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2563 },
2564 /* bnv $label9 */
2565 {
2566 { 1, 1, 1, 1 },
2567 FR30_INSN_BNV, "bnv", "bnv",
2568 { { MNEM, ' ', OP (LABEL9), 0 } },
2569 & fmt_bv, { 0xe900 },
2570 (PTR) & fmt_bv_ops[0],
2571 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2572 },
2573 /* bnv:d $label9 */
2574 {
2575 { 1, 1, 1, 1 },
2576 FR30_INSN_BNVD, "bnvd", "bnv:d",
2577 { { MNEM, ' ', OP (LABEL9), 0 } },
2578 & fmt_bv, { 0xf900 },
2579 (PTR) & fmt_bv_ops[0],
2580 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2581 },
2582 /* blt $label9 */
2583 {
2584 { 1, 1, 1, 1 },
2585 FR30_INSN_BLT, "blt", "blt",
2586 { { MNEM, ' ', OP (LABEL9), 0 } },
2587 & fmt_blt, { 0xea00 },
2588 (PTR) & fmt_blt_ops[0],
2589 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2590 },
2591 /* blt:d $label9 */
2592 {
2593 { 1, 1, 1, 1 },
2594 FR30_INSN_BLTD, "bltd", "blt:d",
2595 { { MNEM, ' ', OP (LABEL9), 0 } },
2596 & fmt_blt, { 0xfa00 },
2597 (PTR) & fmt_blt_ops[0],
2598 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2599 },
2600 /* bge $label9 */
2601 {
2602 { 1, 1, 1, 1 },
2603 FR30_INSN_BGE, "bge", "bge",
2604 { { MNEM, ' ', OP (LABEL9), 0 } },
2605 & fmt_blt, { 0xeb00 },
2606 (PTR) & fmt_blt_ops[0],
2607 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2608 },
2609 /* bge:d $label9 */
2610 {
2611 { 1, 1, 1, 1 },
2612 FR30_INSN_BGED, "bged", "bge:d",
2613 { { MNEM, ' ', OP (LABEL9), 0 } },
2614 & fmt_blt, { 0xfb00 },
2615 (PTR) & fmt_blt_ops[0],
2616 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2617 },
2618 /* ble $label9 */
2619 {
2620 { 1, 1, 1, 1 },
2621 FR30_INSN_BLE, "ble", "ble",
2622 { { MNEM, ' ', OP (LABEL9), 0 } },
2623 & fmt_ble, { 0xec00 },
2624 (PTR) & fmt_ble_ops[0],
2625 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2626 },
2627 /* ble:d $label9 */
2628 {
2629 { 1, 1, 1, 1 },
2630 FR30_INSN_BLED, "bled", "ble:d",
2631 { { MNEM, ' ', OP (LABEL9), 0 } },
2632 & fmt_ble, { 0xfc00 },
2633 (PTR) & fmt_ble_ops[0],
2634 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2635 },
2636 /* bgt $label9 */
2637 {
2638 { 1, 1, 1, 1 },
2639 FR30_INSN_BGT, "bgt", "bgt",
2640 { { MNEM, ' ', OP (LABEL9), 0 } },
2641 & fmt_ble, { 0xed00 },
2642 (PTR) & fmt_ble_ops[0],
2643 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2644 },
2645 /* bgt:d $label9 */
2646 {
2647 { 1, 1, 1, 1 },
2648 FR30_INSN_BGTD, "bgtd", "bgt:d",
2649 { { MNEM, ' ', OP (LABEL9), 0 } },
2650 & fmt_ble, { 0xfd00 },
2651 (PTR) & fmt_ble_ops[0],
2652 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2653 },
2654 /* bls $label9 */
2655 {
2656 { 1, 1, 1, 1 },
2657 FR30_INSN_BLS, "bls", "bls",
2658 { { MNEM, ' ', OP (LABEL9), 0 } },
2659 & fmt_bls, { 0xee00 },
2660 (PTR) & fmt_bls_ops[0],
2661 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2662 },
2663 /* bls:d $label9 */
2664 {
2665 { 1, 1, 1, 1 },
2666 FR30_INSN_BLSD, "blsd", "bls:d",
2667 { { MNEM, ' ', OP (LABEL9), 0 } },
2668 & fmt_bls, { 0xfe00 },
2669 (PTR) & fmt_bls_ops[0],
2670 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2671 },
2672 /* bhi $label9 */
2673 {
2674 { 1, 1, 1, 1 },
2675 FR30_INSN_BHI, "bhi", "bhi",
2676 { { MNEM, ' ', OP (LABEL9), 0 } },
2677 & fmt_bls, { 0xef00 },
2678 (PTR) & fmt_bls_ops[0],
2679 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2680 },
2681 /* bhi:d $label9 */
2682 {
2683 { 1, 1, 1, 1 },
2684 FR30_INSN_BHID, "bhid", "bhi:d",
2685 { { MNEM, ' ', OP (LABEL9), 0 } },
2686 & fmt_bls, { 0xff00 },
2687 (PTR) & fmt_bls_ops[0],
2688 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2689 },
2690 /* dmov $R13,@$dir10 */
2691 {
2692 { 1, 1, 1, 1 },
2693 FR30_INSN_DMOVR13, "dmovr13", "dmov",
2694 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
2695 & fmt_dmovr13, { 0x1800 },
2696 (PTR) 0,
2697 { 0, 0, { 0 } }
2698 },
2699 /* dmovh $R13,@$dir9 */
2700 {
2701 { 1, 1, 1, 1 },
2702 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
2703 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
2704 & fmt_dmovr13h, { 0x1900 },
2705 (PTR) 0,
2706 { 0, 0, { 0 } }
2707 },
2708 /* dmovb $R13,@$dir8 */
2709 {
2710 { 1, 1, 1, 1 },
2711 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
2712 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
2713 & fmt_dmovr13b, { 0x1a00 },
2714 (PTR) 0,
2715 { 0, 0, { 0 } }
2716 },
2717 /* dmov @$R13+,@$dir10 */
2718 {
2719 { 1, 1, 1, 1 },
2720 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
2721 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
2722 & fmt_dmovr13, { 0x1c00 },
2723 (PTR) 0,
2724 { 0, 0, { 0 } }
2725 },
2726 /* dmovh @$R13+,@$dir9 */
2727 {
2728 { 1, 1, 1, 1 },
2729 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
2730 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
2731 & fmt_dmovr13h, { 0x1d00 },
2732 (PTR) 0,
2733 { 0, 0, { 0 } }
2734 },
2735 /* dmovb @$R13+,@$dir8 */
2736 {
2737 { 1, 1, 1, 1 },
2738 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
2739 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
2740 & fmt_dmovr13b, { 0x1e00 },
2741 (PTR) 0,
2742 { 0, 0, { 0 } }
2743 },
2744 /* dmov @$R15+,@$dir10 */
2745 {
2746 { 1, 1, 1, 1 },
2747 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
2748 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
2749 & fmt_dmovr13, { 0x1b00 },
2750 (PTR) 0,
2751 { 0, 0, { 0 } }
2752 },
2753 /* dmov @$dir10,$R13 */
2754 {
2755 { 1, 1, 1, 1 },
2756 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
2757 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
2758 & fmt_dmovr13, { 0x800 },
2759 (PTR) 0,
2760 { 0, 0, { 0 } }
2761 },
2762 /* dmovh @$dir9,$R13 */
2763 {
2764 { 1, 1, 1, 1 },
2765 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
2766 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
2767 & fmt_dmovr13h, { 0x900 },
2768 (PTR) 0,
2769 { 0, 0, { 0 } }
2770 },
2771 /* dmovb @$dir8,$R13 */
2772 {
2773 { 1, 1, 1, 1 },
2774 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
2775 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
2776 & fmt_dmovr13b, { 0xa00 },
2777 (PTR) 0,
2778 { 0, 0, { 0 } }
2779 },
2780 /* dmov @$dir10,@$R13+ */
2781 {
2782 { 1, 1, 1, 1 },
2783 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
2784 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
2785 & fmt_dmovr13, { 0xc00 },
2786 (PTR) 0,
2787 { 0, 0, { 0 } }
2788 },
2789 /* dmovh @$dir9,@$R13+ */
2790 {
2791 { 1, 1, 1, 1 },
2792 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
2793 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
2794 & fmt_dmovr13h, { 0xd00 },
2795 (PTR) 0,
2796 { 0, 0, { 0 } }
2797 },
2798 /* dmovb @$dir8,@$R13+ */
2799 {
2800 { 1, 1, 1, 1 },
2801 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
2802 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
2803 & fmt_dmovr13b, { 0xe00 },
2804 (PTR) 0,
2805 { 0, 0, { 0 } }
2806 },
2807 /* dmov @$dir10,@-$R15 */
2808 {
2809 { 1, 1, 1, 1 },
2810 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
2811 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
2812 & fmt_dmovr13, { 0xb00 },
2813 (PTR) 0,
2814 { 0, 0, { 0 } }
2815 },
2816 /* ldres @$Ri+,$u4 */
2817 {
2818 { 1, 1, 1, 1 },
2819 FR30_INSN_LDRES, "ldres", "ldres",
2820 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
2821 & fmt_ldres, { 0xbc00 },
2822 (PTR) 0,
2823 { 0, 0, { 0 } }
2824 },
2825 /* stres $u4,@$Ri+ */
2826 {
2827 { 1, 1, 1, 1 },
2828 FR30_INSN_STRES, "stres", "stres",
2829 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
2830 & fmt_ldres, { 0xbd00 },
2831 (PTR) 0,
2832 { 0, 0, { 0 } }
2833 },
2834 /* copop $u4c,$ccc,$CRj,$CRi */
2835 {
2836 { 1, 1, 1, 1 },
2837 FR30_INSN_COPOP, "copop", "copop",
2838 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
2839 & fmt_copop, { 0x9fc0 },
2840 (PTR) 0,
2841 { 0, 0, { 0 } }
2842 },
2843 /* copld $u4c,$ccc,$Rjc,$CRi */
2844 {
2845 { 1, 1, 1, 1 },
2846 FR30_INSN_COPLD, "copld", "copld",
2847 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
2848 & fmt_copld, { 0x9fd0 },
2849 (PTR) 0,
2850 { 0, 0, { 0 } }
2851 },
2852 /* copst $u4c,$ccc,$CRj,$Ric */
2853 {
2854 { 1, 1, 1, 1 },
2855 FR30_INSN_COPST, "copst", "copst",
2856 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2857 & fmt_copst, { 0x9fe0 },
2858 (PTR) 0,
2859 { 0, 0, { 0 } }
2860 },
2861 /* copsv $u4c,$ccc,$CRj,$Ric */
2862 {
2863 { 1, 1, 1, 1 },
2864 FR30_INSN_COPSV, "copsv", "copsv",
2865 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2866 & fmt_copst, { 0x9ff0 },
2867 (PTR) 0,
2868 { 0, 0, { 0 } }
2869 },
2870 /* nop */
2871 {
2872 { 1, 1, 1, 1 },
2873 FR30_INSN_NOP, "nop", "nop",
2874 { { MNEM, 0 } },
2875 & fmt_div3, { 0x9fa0 },
2876 (PTR) 0,
2877 { 0, 0, { 0 } }
2878 },
2879 /* andccr $u8 */
2880 {
2881 { 1, 1, 1, 1 },
2882 FR30_INSN_ANDCCR, "andccr", "andccr",
2883 { { MNEM, ' ', OP (U8), 0 } },
2884 & fmt_andccr, { 0x8300 },
2885 (PTR) & fmt_andccr_ops[0],
2886 { 0, 0, { 0 } }
2887 },
2888 /* orccr $u8 */
2889 {
2890 { 1, 1, 1, 1 },
2891 FR30_INSN_ORCCR, "orccr", "orccr",
2892 { { MNEM, ' ', OP (U8), 0 } },
2893 & fmt_andccr, { 0x9300 },
2894 (PTR) & fmt_andccr_ops[0],
2895 { 0, 0, { 0 } }
2896 },
2897 /* stilm $u8 */
2898 {
2899 { 1, 1, 1, 1 },
2900 FR30_INSN_STILM, "stilm", "stilm",
2901 { { MNEM, ' ', OP (U8), 0 } },
2902 & fmt_stilm, { 0x8700 },
2903 (PTR) 0,
2904 { 0, 0, { 0 } }
2905 },
2906 /* addsp $s10 */
2907 {
2908 { 1, 1, 1, 1 },
2909 FR30_INSN_ADDSP, "addsp", "addsp",
2910 { { MNEM, ' ', OP (S10), 0 } },
2911 & fmt_addsp, { 0xa300 },
2912 (PTR) 0,
2913 { 0, 0, { 0 } }
2914 },
2915 /* extsb $Ri */
2916 {
2917 { 1, 1, 1, 1 },
2918 FR30_INSN_EXTSB, "extsb", "extsb",
2919 { { MNEM, ' ', OP (RI), 0 } },
2920 & fmt_div0s, { 0x9780 },
2921 (PTR) 0,
2922 { 0, 0, { 0 } }
2923 },
2924 /* extub $Ri */
2925 {
2926 { 1, 1, 1, 1 },
2927 FR30_INSN_EXTUB, "extub", "extub",
2928 { { MNEM, ' ', OP (RI), 0 } },
2929 & fmt_div0s, { 0x9790 },
2930 (PTR) 0,
2931 { 0, 0, { 0 } }
2932 },
2933 /* extsh $Ri */
2934 {
2935 { 1, 1, 1, 1 },
2936 FR30_INSN_EXTSH, "extsh", "extsh",
2937 { { MNEM, ' ', OP (RI), 0 } },
2938 & fmt_div0s, { 0x97a0 },
2939 (PTR) 0,
2940 { 0, 0, { 0 } }
2941 },
2942 /* extuh $Ri */
2943 {
2944 { 1, 1, 1, 1 },
2945 FR30_INSN_EXTUH, "extuh", "extuh",
2946 { { MNEM, ' ', OP (RI), 0 } },
2947 & fmt_div0s, { 0x97b0 },
2948 (PTR) 0,
2949 { 0, 0, { 0 } }
2950 },
2951 /* ldm0 ($reglist_low) */
2952 {
2953 { 1, 1, 1, 1 },
2954 FR30_INSN_LDM0, "ldm0", "ldm0",
2955 { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2956 & fmt_ldm0, { 0x8c00 },
2957 (PTR) 0,
2958 { 0, 0, { 0 } }
2959 },
2960 /* ldm1 ($reglist_hi) */
2961 {
2962 { 1, 1, 1, 1 },
2963 FR30_INSN_LDM1, "ldm1", "ldm1",
2964 { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2965 & fmt_ldm1, { 0x8d00 },
2966 (PTR) 0,
2967 { 0, 0, { 0 } }
2968 },
2969 /* stm0 ($reglist_low) */
2970 {
2971 { 1, 1, 1, 1 },
2972 FR30_INSN_STM0, "stm0", "stm0",
2973 { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2974 & fmt_ldm0, { 0x8e00 },
2975 (PTR) 0,
2976 { 0, 0, { 0 } }
2977 },
2978 /* stm1 ($reglist_hi) */
2979 {
2980 { 1, 1, 1, 1 },
2981 FR30_INSN_STM1, "stm1", "stm1",
2982 { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2983 & fmt_ldm1, { 0x8f00 },
2984 (PTR) 0,
2985 { 0, 0, { 0 } }
2986 },
2987 /* enter $u10 */
2988 {
2989 { 1, 1, 1, 1 },
2990 FR30_INSN_ENTER, "enter", "enter",
2991 { { MNEM, ' ', OP (U10), 0 } },
2992 & fmt_enter, { 0xf00 },
2993 (PTR) 0,
2994 { 0, 0, { 0 } }
2995 },
2996 /* leave */
2997 {
2998 { 1, 1, 1, 1 },
2999 FR30_INSN_LEAVE, "leave", "leave",
3000 { { MNEM, 0 } },
3001 & fmt_div3, { 0x9f90 },
3002 (PTR) 0,
3003 { 0, 0, { 0 } }
3004 },
3005 /* xchb @$Rj,$Ri */
3006 {
3007 { 1, 1, 1, 1 },
3008 FR30_INSN_XCHB, "xchb", "xchb",
3009 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
3010 & fmt_xchb, { 0x8a00 },
3011 (PTR) 0,
3012 { 0, 0, { 0 } }
3013 },
3014 };
3015
3016 #undef A
3017 #undef MNEM
3018 #undef OP
3019
3020 static const CGEN_INSN_TABLE insn_table =
3021 {
3022 & fr30_cgen_insn_table_entries[0],
3023 sizeof (CGEN_INSN),
3024 MAX_INSNS,
3025 NULL
3026 };
3027
3028 /* Formats for ALIAS macro-insns. */
3029
3030 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
3031
3032 static const CGEN_IFMT fmt_ldi8m = {
3033 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
3034 };
3035
3036 static const CGEN_IFMT fmt_ldi20m = {
3037 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
3038 };
3039
3040 static const CGEN_IFMT fmt_ldi32m = {
3041 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
3042 };
3043
3044 #undef F
3045
3046 /* Each non-simple macro entry points to an array of expansion possibilities. */
3047
3048 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
3049 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
3050 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
3051
3052 /* The macro instruction table. */
3053
3054 static const CGEN_INSN macro_insn_table_entries[] =
3055 {
3056 /* ldi8 $i8,$Ri */
3057 {
3058 { 1, 1, 1, 1 },
3059 -1, "ldi8m", "ldi8",
3060 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
3061 & fmt_ldi8m, { 0xc000 },
3062 (PTR) 0,
3063 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3064 },
3065 /* ldi20 $i20,$Ri */
3066 {
3067 { 1, 1, 1, 1 },
3068 -1, "ldi20m", "ldi20",
3069 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
3070 & fmt_ldi20m, { 0x9b00 },
3071 (PTR) 0,
3072 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3073 },
3074 /* ldi32 $i32,$Ri */
3075 {
3076 { 1, 1, 1, 1 },
3077 -1, "ldi32m", "ldi32",
3078 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
3079 & fmt_ldi32m, { 0x9f80 },
3080 (PTR) 0,
3081 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3082 },
3083 };
3084
3085 #undef A
3086 #undef MNEM
3087 #undef OP
3088
3089 static const CGEN_INSN_TABLE macro_insn_table =
3090 {
3091 & macro_insn_table_entries[0],
3092 sizeof (CGEN_INSN),
3093 (sizeof (macro_insn_table_entries) /
3094 sizeof (macro_insn_table_entries[0])),
3095 NULL
3096 };
3097
3098 static void
3099 init_tables ()
3100 {
3101 }
3102
3103 /* Return non-zero if INSN is to be added to the hash table.
3104 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3105
3106 static int
3107 asm_hash_insn_p (insn)
3108 const CGEN_INSN * insn;
3109 {
3110 return CGEN_ASM_HASH_P (insn);
3111 }
3112
3113 static int
3114 dis_hash_insn_p (insn)
3115 const CGEN_INSN * insn;
3116 {
3117 /* If building the hash table and the NO-DIS attribute is present,
3118 ignore. */
3119 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
3120 return 0;
3121 return CGEN_DIS_HASH_P (insn);
3122 }
3123
3124 /* The result is the hash value of the insn.
3125 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
3126
3127 static unsigned int
3128 asm_hash_insn (mnem)
3129 const char * mnem;
3130 {
3131 return CGEN_ASM_HASH (mnem);
3132 }
3133
3134 /* BUF is a pointer to the insn's bytes in target order.
3135 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3136 host order. */
3137
3138 static unsigned int
3139 dis_hash_insn (buf, value)
3140 const char * buf;
3141 CGEN_INSN_INT value;
3142 {
3143 return CGEN_DIS_HASH (buf, value);
3144 }
3145
3146 /* Initialize an opcode table and return a descriptor.
3147 It's much like opening a file, and must be the first function called. */
3148
3149 CGEN_OPCODE_DESC
3150 fr30_cgen_opcode_open (mach, endian)
3151 int mach;
3152 enum cgen_endian endian;
3153 {
3154 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
3155 static int init_p;
3156
3157 if (! init_p)
3158 {
3159 init_tables ();
3160 init_p = 1;
3161 }
3162
3163 memset (table, 0, sizeof (*table));
3164
3165 CGEN_OPCODE_MACH (table) = mach;
3166 CGEN_OPCODE_ENDIAN (table) = endian;
3167 /* FIXME: for the sparc case we can determine insn-endianness statically.
3168 The worry here is where both data and insn endian can be independently
3169 chosen, in which case this function will need another argument.
3170 Actually, will want to allow for more arguments in the future anyway. */
3171 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
3172
3173 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
3174
3175 CGEN_OPCODE_IFLD_TABLE (table) = & fr30_cgen_ifld_table[0];
3176
3177 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
3178
3179 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
3180
3181 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
3182
3183 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
3184 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
3185 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
3186
3187 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
3188 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
3189 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
3190
3191 return (CGEN_OPCODE_DESC) table;
3192 }
3193
3194 /* Close an opcode table. */
3195
3196 void
3197 fr30_cgen_opcode_close (desc)
3198 CGEN_OPCODE_DESC desc;
3199 {
3200 free (desc);
3201 }
3202
3203 /* Getting values from cgen_fields is handled by a collection of functions.
3204 They are distinguished by the type of the VALUE argument they return.
3205 TODO: floating point, inlining support, remove cases where result type
3206 not appropriate. */
3207
3208 int
3209 fr30_cgen_get_int_operand (opindex, fields)
3210 int opindex;
3211 const CGEN_FIELDS * fields;
3212 {
3213 int value;
3214
3215 switch (opindex)
3216 {
3217 case FR30_OPERAND_RI :
3218 value = fields->f_Ri;
3219 break;
3220 case FR30_OPERAND_RJ :
3221 value = fields->f_Rj;
3222 break;
3223 case FR30_OPERAND_RIC :
3224 value = fields->f_Ric;
3225 break;
3226 case FR30_OPERAND_RJC :
3227 value = fields->f_Rjc;
3228 break;
3229 case FR30_OPERAND_CRI :
3230 value = fields->f_CRi;
3231 break;
3232 case FR30_OPERAND_CRJ :
3233 value = fields->f_CRj;
3234 break;
3235 case FR30_OPERAND_RS1 :
3236 value = fields->f_Rs1;
3237 break;
3238 case FR30_OPERAND_RS2 :
3239 value = fields->f_Rs2;
3240 break;
3241 case FR30_OPERAND_R13 :
3242 value = fields->f_nil;
3243 break;
3244 case FR30_OPERAND_R14 :
3245 value = fields->f_nil;
3246 break;
3247 case FR30_OPERAND_R15 :
3248 value = fields->f_nil;
3249 break;
3250 case FR30_OPERAND_PS :
3251 value = fields->f_nil;
3252 break;
3253 case FR30_OPERAND_U4 :
3254 value = fields->f_u4;
3255 break;
3256 case FR30_OPERAND_U4C :
3257 value = fields->f_u4c;
3258 break;
3259 case FR30_OPERAND_U8 :
3260 value = fields->f_u8;
3261 break;
3262 case FR30_OPERAND_I8 :
3263 value = fields->f_i8;
3264 break;
3265 case FR30_OPERAND_UDISP6 :
3266 value = fields->f_udisp6;
3267 break;
3268 case FR30_OPERAND_DISP8 :
3269 value = fields->f_disp8;
3270 break;
3271 case FR30_OPERAND_DISP9 :
3272 value = fields->f_disp9;
3273 break;
3274 case FR30_OPERAND_DISP10 :
3275 value = fields->f_disp10;
3276 break;
3277 case FR30_OPERAND_S10 :
3278 value = fields->f_s10;
3279 break;
3280 case FR30_OPERAND_U10 :
3281 value = fields->f_u10;
3282 break;
3283 case FR30_OPERAND_I32 :
3284 value = fields->f_i32;
3285 break;
3286 case FR30_OPERAND_M4 :
3287 value = fields->f_m4;
3288 break;
3289 case FR30_OPERAND_I20 :
3290 value = fields->f_i20;
3291 break;
3292 case FR30_OPERAND_DIR8 :
3293 value = fields->f_dir8;
3294 break;
3295 case FR30_OPERAND_DIR9 :
3296 value = fields->f_dir9;
3297 break;
3298 case FR30_OPERAND_DIR10 :
3299 value = fields->f_dir10;
3300 break;
3301 case FR30_OPERAND_LABEL9 :
3302 value = fields->f_rel9;
3303 break;
3304 case FR30_OPERAND_LABEL12 :
3305 value = fields->f_rel12;
3306 break;
3307 case FR30_OPERAND_REGLIST_LOW :
3308 value = fields->f_reglist_low;
3309 break;
3310 case FR30_OPERAND_REGLIST_HI :
3311 value = fields->f_reglist_hi;
3312 break;
3313 case FR30_OPERAND_CC :
3314 value = fields->f_cc;
3315 break;
3316 case FR30_OPERAND_CCC :
3317 value = fields->f_ccc;
3318 break;
3319
3320 default :
3321 /* xgettext:c-format */
3322 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3323 opindex);
3324 abort ();
3325 }
3326
3327 return value;
3328 }
3329
3330 bfd_vma
3331 fr30_cgen_get_vma_operand (opindex, fields)
3332 int opindex;
3333 const CGEN_FIELDS * fields;
3334 {
3335 bfd_vma value;
3336
3337 switch (opindex)
3338 {
3339 case FR30_OPERAND_RI :
3340 value = fields->f_Ri;
3341 break;
3342 case FR30_OPERAND_RJ :
3343 value = fields->f_Rj;
3344 break;
3345 case FR30_OPERAND_RIC :
3346 value = fields->f_Ric;
3347 break;
3348 case FR30_OPERAND_RJC :
3349 value = fields->f_Rjc;
3350 break;
3351 case FR30_OPERAND_CRI :
3352 value = fields->f_CRi;
3353 break;
3354 case FR30_OPERAND_CRJ :
3355 value = fields->f_CRj;
3356 break;
3357 case FR30_OPERAND_RS1 :
3358 value = fields->f_Rs1;
3359 break;
3360 case FR30_OPERAND_RS2 :
3361 value = fields->f_Rs2;
3362 break;
3363 case FR30_OPERAND_R13 :
3364 value = fields->f_nil;
3365 break;
3366 case FR30_OPERAND_R14 :
3367 value = fields->f_nil;
3368 break;
3369 case FR30_OPERAND_R15 :
3370 value = fields->f_nil;
3371 break;
3372 case FR30_OPERAND_PS :
3373 value = fields->f_nil;
3374 break;
3375 case FR30_OPERAND_U4 :
3376 value = fields->f_u4;
3377 break;
3378 case FR30_OPERAND_U4C :
3379 value = fields->f_u4c;
3380 break;
3381 case FR30_OPERAND_U8 :
3382 value = fields->f_u8;
3383 break;
3384 case FR30_OPERAND_I8 :
3385 value = fields->f_i8;
3386 break;
3387 case FR30_OPERAND_UDISP6 :
3388 value = fields->f_udisp6;
3389 break;
3390 case FR30_OPERAND_DISP8 :
3391 value = fields->f_disp8;
3392 break;
3393 case FR30_OPERAND_DISP9 :
3394 value = fields->f_disp9;
3395 break;
3396 case FR30_OPERAND_DISP10 :
3397 value = fields->f_disp10;
3398 break;
3399 case FR30_OPERAND_S10 :
3400 value = fields->f_s10;
3401 break;
3402 case FR30_OPERAND_U10 :
3403 value = fields->f_u10;
3404 break;
3405 case FR30_OPERAND_I32 :
3406 value = fields->f_i32;
3407 break;
3408 case FR30_OPERAND_M4 :
3409 value = fields->f_m4;
3410 break;
3411 case FR30_OPERAND_I20 :
3412 value = fields->f_i20;
3413 break;
3414 case FR30_OPERAND_DIR8 :
3415 value = fields->f_dir8;
3416 break;
3417 case FR30_OPERAND_DIR9 :
3418 value = fields->f_dir9;
3419 break;
3420 case FR30_OPERAND_DIR10 :
3421 value = fields->f_dir10;
3422 break;
3423 case FR30_OPERAND_LABEL9 :
3424 value = fields->f_rel9;
3425 break;
3426 case FR30_OPERAND_LABEL12 :
3427 value = fields->f_rel12;
3428 break;
3429 case FR30_OPERAND_REGLIST_LOW :
3430 value = fields->f_reglist_low;
3431 break;
3432 case FR30_OPERAND_REGLIST_HI :
3433 value = fields->f_reglist_hi;
3434 break;
3435 case FR30_OPERAND_CC :
3436 value = fields->f_cc;
3437 break;
3438 case FR30_OPERAND_CCC :
3439 value = fields->f_ccc;
3440 break;
3441
3442 default :
3443 /* xgettext:c-format */
3444 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3445 opindex);
3446 abort ();
3447 }
3448
3449 return value;
3450 }
3451
3452 /* Stuffing values in cgen_fields is handled by a collection of functions.
3453 They are distinguished by the type of the VALUE argument they accept.
3454 TODO: floating point, inlining support, remove cases where argument type
3455 not appropriate. */
3456
3457 void
3458 fr30_cgen_set_int_operand (opindex, fields, value)
3459 int opindex;
3460 CGEN_FIELDS * fields;
3461 int value;
3462 {
3463 switch (opindex)
3464 {
3465 case FR30_OPERAND_RI :
3466 fields->f_Ri = value;
3467 break;
3468 case FR30_OPERAND_RJ :
3469 fields->f_Rj = value;
3470 break;
3471 case FR30_OPERAND_RIC :
3472 fields->f_Ric = value;
3473 break;
3474 case FR30_OPERAND_RJC :
3475 fields->f_Rjc = value;
3476 break;
3477 case FR30_OPERAND_CRI :
3478 fields->f_CRi = value;
3479 break;
3480 case FR30_OPERAND_CRJ :
3481 fields->f_CRj = value;
3482 break;
3483 case FR30_OPERAND_RS1 :
3484 fields->f_Rs1 = value;
3485 break;
3486 case FR30_OPERAND_RS2 :
3487 fields->f_Rs2 = value;
3488 break;
3489 case FR30_OPERAND_R13 :
3490 fields->f_nil = value;
3491 break;
3492 case FR30_OPERAND_R14 :
3493 fields->f_nil = value;
3494 break;
3495 case FR30_OPERAND_R15 :
3496 fields->f_nil = value;
3497 break;
3498 case FR30_OPERAND_PS :
3499 fields->f_nil = value;
3500 break;
3501 case FR30_OPERAND_U4 :
3502 fields->f_u4 = value;
3503 break;
3504 case FR30_OPERAND_U4C :
3505 fields->f_u4c = value;
3506 break;
3507 case FR30_OPERAND_U8 :
3508 fields->f_u8 = value;
3509 break;
3510 case FR30_OPERAND_I8 :
3511 fields->f_i8 = value;
3512 break;
3513 case FR30_OPERAND_UDISP6 :
3514 fields->f_udisp6 = value;
3515 break;
3516 case FR30_OPERAND_DISP8 :
3517 fields->f_disp8 = value;
3518 break;
3519 case FR30_OPERAND_DISP9 :
3520 fields->f_disp9 = value;
3521 break;
3522 case FR30_OPERAND_DISP10 :
3523 fields->f_disp10 = value;
3524 break;
3525 case FR30_OPERAND_S10 :
3526 fields->f_s10 = value;
3527 break;
3528 case FR30_OPERAND_U10 :
3529 fields->f_u10 = value;
3530 break;
3531 case FR30_OPERAND_I32 :
3532 fields->f_i32 = value;
3533 break;
3534 case FR30_OPERAND_M4 :
3535 fields->f_m4 = value;
3536 break;
3537 case FR30_OPERAND_I20 :
3538 fields->f_i20 = value;
3539 break;
3540 case FR30_OPERAND_DIR8 :
3541 fields->f_dir8 = value;
3542 break;
3543 case FR30_OPERAND_DIR9 :
3544 fields->f_dir9 = value;
3545 break;
3546 case FR30_OPERAND_DIR10 :
3547 fields->f_dir10 = value;
3548 break;
3549 case FR30_OPERAND_LABEL9 :
3550 fields->f_rel9 = value;
3551 break;
3552 case FR30_OPERAND_LABEL12 :
3553 fields->f_rel12 = value;
3554 break;
3555 case FR30_OPERAND_REGLIST_LOW :
3556 fields->f_reglist_low = value;
3557 break;
3558 case FR30_OPERAND_REGLIST_HI :
3559 fields->f_reglist_hi = value;
3560 break;
3561 case FR30_OPERAND_CC :
3562 fields->f_cc = value;
3563 break;
3564 case FR30_OPERAND_CCC :
3565 fields->f_ccc = value;
3566 break;
3567
3568 default :
3569 /* xgettext:c-format */
3570 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3571 opindex);
3572 abort ();
3573 }
3574 }
3575
3576 void
3577 fr30_cgen_set_vma_operand (opindex, fields, value)
3578 int opindex;
3579 CGEN_FIELDS * fields;
3580 bfd_vma value;
3581 {
3582 switch (opindex)
3583 {
3584 case FR30_OPERAND_RI :
3585 fields->f_Ri = value;
3586 break;
3587 case FR30_OPERAND_RJ :
3588 fields->f_Rj = value;
3589 break;
3590 case FR30_OPERAND_RIC :
3591 fields->f_Ric = value;
3592 break;
3593 case FR30_OPERAND_RJC :
3594 fields->f_Rjc = value;
3595 break;
3596 case FR30_OPERAND_CRI :
3597 fields->f_CRi = value;
3598 break;
3599 case FR30_OPERAND_CRJ :
3600 fields->f_CRj = value;
3601 break;
3602 case FR30_OPERAND_RS1 :
3603 fields->f_Rs1 = value;
3604 break;
3605 case FR30_OPERAND_RS2 :
3606 fields->f_Rs2 = value;
3607 break;
3608 case FR30_OPERAND_R13 :
3609 fields->f_nil = value;
3610 break;
3611 case FR30_OPERAND_R14 :
3612 fields->f_nil = value;
3613 break;
3614 case FR30_OPERAND_R15 :
3615 fields->f_nil = value;
3616 break;
3617 case FR30_OPERAND_PS :
3618 fields->f_nil = value;
3619 break;
3620 case FR30_OPERAND_U4 :
3621 fields->f_u4 = value;
3622 break;
3623 case FR30_OPERAND_U4C :
3624 fields->f_u4c = value;
3625 break;
3626 case FR30_OPERAND_U8 :
3627 fields->f_u8 = value;
3628 break;
3629 case FR30_OPERAND_I8 :
3630 fields->f_i8 = value;
3631 break;
3632 case FR30_OPERAND_UDISP6 :
3633 fields->f_udisp6 = value;
3634 break;
3635 case FR30_OPERAND_DISP8 :
3636 fields->f_disp8 = value;
3637 break;
3638 case FR30_OPERAND_DISP9 :
3639 fields->f_disp9 = value;
3640 break;
3641 case FR30_OPERAND_DISP10 :
3642 fields->f_disp10 = value;
3643 break;
3644 case FR30_OPERAND_S10 :
3645 fields->f_s10 = value;
3646 break;
3647 case FR30_OPERAND_U10 :
3648 fields->f_u10 = value;
3649 break;
3650 case FR30_OPERAND_I32 :
3651 fields->f_i32 = value;
3652 break;
3653 case FR30_OPERAND_M4 :
3654 fields->f_m4 = value;
3655 break;
3656 case FR30_OPERAND_I20 :
3657 fields->f_i20 = value;
3658 break;
3659 case FR30_OPERAND_DIR8 :
3660 fields->f_dir8 = value;
3661 break;
3662 case FR30_OPERAND_DIR9 :
3663 fields->f_dir9 = value;
3664 break;
3665 case FR30_OPERAND_DIR10 :
3666 fields->f_dir10 = value;
3667 break;
3668 case FR30_OPERAND_LABEL9 :
3669 fields->f_rel9 = value;
3670 break;
3671 case FR30_OPERAND_LABEL12 :
3672 fields->f_rel12 = value;
3673 break;
3674 case FR30_OPERAND_REGLIST_LOW :
3675 fields->f_reglist_low = value;
3676 break;
3677 case FR30_OPERAND_REGLIST_HI :
3678 fields->f_reglist_hi = value;
3679 break;
3680 case FR30_OPERAND_CC :
3681 fields->f_cc = value;
3682 break;
3683 case FR30_OPERAND_CCC :
3684 fields->f_ccc = value;
3685 break;
3686
3687 default :
3688 /* xgettext:c-format */
3689 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3690 opindex);
3691 abort ();
3692 }
3693 }
3694
GDB Binutils - Deliverables
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