1 /* Instruction opcode table for fr30.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 #include "fr30-desc.h"
31 #include "libiberty.h"
33 /* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
36 static int asm_hash_insn_p
PARAMS ((const CGEN_INSN
*));
37 static unsigned int asm_hash_insn
PARAMS ((const char *));
38 static int dis_hash_insn_p
PARAMS ((const CGEN_INSN
*));
39 static unsigned int dis_hash_insn
PARAMS ((const char *, CGEN_INSN_INT
));
40 static void set_fields_bitsize
PARAMS ((CGEN_FIELDS
*, int));
42 /* Instruction formats. */
44 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
45 #define F(f) & fr30_cgen_ifld_table[FR30_##f]
47 #define F(f) & fr30_cgen_ifld_table[FR30_/**/f]
49 static const CGEN_IFMT ifmt_empty
= {
53 static const CGEN_IFMT ifmt_add
= {
54 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_RJ
) }, { F (F_RI
) }, { 0 } }
57 static const CGEN_IFMT ifmt_addi
= {
58 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_U4
) }, { F (F_RI
) }, { 0 } }
61 static const CGEN_IFMT ifmt_add2
= {
62 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_M4
) }, { F (F_RI
) }, { 0 } }
65 static const CGEN_IFMT ifmt_div0s
= {
66 16, 16, 0xfff0, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_OP3
) }, { F (F_RI
) }, { 0 } }
69 static const CGEN_IFMT ifmt_div3
= {
70 16, 16, 0xffff, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_OP3
) }, { F (F_OP4
) }, { 0 } }
73 static const CGEN_IFMT ifmt_ldi8
= {
74 16, 16, 0xf000, { { F (F_OP1
) }, { F (F_I8
) }, { F (F_RI
) }, { 0 } }
77 static const CGEN_IFMT ifmt_ldi20
= {
78 16, 32, 0xff00, { { F (F_OP1
) }, { F (F_I20
) }, { F (F_OP2
) }, { F (F_RI
) }, { 0 } }
81 static const CGEN_IFMT ifmt_ldi32
= {
82 16, 48, 0xfff0, { { F (F_OP1
) }, { F (F_I32
) }, { F (F_OP2
) }, { F (F_OP3
) }, { F (F_RI
) }, { 0 } }
85 static const CGEN_IFMT ifmt_ldr14
= {
86 16, 16, 0xf000, { { F (F_OP1
) }, { F (F_DISP10
) }, { F (F_RI
) }, { 0 } }
89 static const CGEN_IFMT ifmt_ldr14uh
= {
90 16, 16, 0xf000, { { F (F_OP1
) }, { F (F_DISP9
) }, { F (F_RI
) }, { 0 } }
93 static const CGEN_IFMT ifmt_ldr14ub
= {
94 16, 16, 0xf000, { { F (F_OP1
) }, { F (F_DISP8
) }, { F (F_RI
) }, { 0 } }
97 static const CGEN_IFMT ifmt_ldr15
= {
98 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_UDISP6
) }, { F (F_RI
) }, { 0 } }
101 static const CGEN_IFMT ifmt_ldr15dr
= {
102 16, 16, 0xfff0, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_OP3
) }, { F (F_RS2
) }, { 0 } }
105 static const CGEN_IFMT ifmt_movdr
= {
106 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_RS1
) }, { F (F_RI
) }, { 0 } }
109 static const CGEN_IFMT ifmt_call
= {
110 16, 16, 0xf800, { { F (F_OP1
) }, { F (F_OP5
) }, { F (F_REL12
) }, { 0 } }
113 static const CGEN_IFMT ifmt_int
= {
114 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_U8
) }, { 0 } }
117 static const CGEN_IFMT ifmt_brad
= {
118 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_CC
) }, { F (F_REL9
) }, { 0 } }
121 static const CGEN_IFMT ifmt_dmovr13
= {
122 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_DIR10
) }, { 0 } }
125 static const CGEN_IFMT ifmt_dmovr13h
= {
126 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_DIR9
) }, { 0 } }
129 static const CGEN_IFMT ifmt_dmovr13b
= {
130 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_DIR8
) }, { 0 } }
133 static const CGEN_IFMT ifmt_copop
= {
134 16, 32, 0xfff0, { { F (F_OP1
) }, { F (F_CCC
) }, { F (F_OP2
) }, { F (F_OP3
) }, { F (F_CRJ
) }, { F (F_U4C
) }, { F (F_CRI
) }, { 0 } }
137 static const CGEN_IFMT ifmt_copld
= {
138 16, 32, 0xfff0, { { F (F_OP1
) }, { F (F_CCC
) }, { F (F_OP2
) }, { F (F_OP3
) }, { F (F_RJC
) }, { F (F_U4C
) }, { F (F_CRI
) }, { 0 } }
141 static const CGEN_IFMT ifmt_copst
= {
142 16, 32, 0xfff0, { { F (F_OP1
) }, { F (F_CCC
) }, { F (F_OP2
) }, { F (F_OP3
) }, { F (F_CRJ
) }, { F (F_U4C
) }, { F (F_RIC
) }, { 0 } }
145 static const CGEN_IFMT ifmt_addsp
= {
146 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_S10
) }, { 0 } }
149 static const CGEN_IFMT ifmt_ldm0
= {
150 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_REGLIST_LOW_LD
) }, { 0 } }
153 static const CGEN_IFMT ifmt_ldm1
= {
154 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_REGLIST_HI_LD
) }, { 0 } }
157 static const CGEN_IFMT ifmt_stm0
= {
158 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_REGLIST_LOW_ST
) }, { 0 } }
161 static const CGEN_IFMT ifmt_stm1
= {
162 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_REGLIST_HI_ST
) }, { 0 } }
165 static const CGEN_IFMT ifmt_enter
= {
166 16, 16, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_U10
) }, { 0 } }
171 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
172 #define A(a) (1 << CGEN_INSN_##a)
174 #define A(a) (1 << CGEN_INSN_/**/a)
176 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
177 #define OPERAND(op) FR30_OPERAND_##op
179 #define OPERAND(op) FR30_OPERAND_/**/op
181 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
182 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
184 /* The instruction table. */
186 static const CGEN_OPCODE fr30_cgen_insn_opcode_table
[MAX_INSNS
] =
188 /* Special null first entry.
189 A `num' value of zero is thus invalid.
190 Also, the special `invalid' insn resides here. */
191 { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
195 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
196 & ifmt_add
, { 0xa600 }
201 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
202 & ifmt_addi
, { 0xa400 }
207 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
208 & ifmt_add2
, { 0xa500 }
213 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
214 & ifmt_add
, { 0xa700 }
219 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
220 & ifmt_add
, { 0xa200 }
225 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
226 & ifmt_addi
, { 0xa000 }
231 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
232 & ifmt_add2
, { 0xa100 }
237 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
238 & ifmt_add
, { 0xac00 }
243 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
244 & ifmt_add
, { 0xad00 }
249 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
250 & ifmt_add
, { 0xae00 }
255 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
256 & ifmt_add
, { 0xaa00 }
261 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
262 & ifmt_addi
, { 0xa800 }
267 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
268 & ifmt_add2
, { 0xa900 }
273 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
274 & ifmt_add
, { 0x8200 }
279 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
280 & ifmt_add
, { 0x9200 }
285 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
286 & ifmt_add
, { 0x9a00 }
291 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
292 & ifmt_add
, { 0x8400 }
297 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
298 & ifmt_add
, { 0x8500 }
303 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
304 & ifmt_add
, { 0x8600 }
309 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
310 & ifmt_add
, { 0x9400 }
315 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
316 & ifmt_add
, { 0x9500 }
321 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
322 & ifmt_add
, { 0x9600 }
327 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
328 & ifmt_add
, { 0x9c00 }
333 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
334 & ifmt_add
, { 0x9d00 }
339 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
340 & ifmt_add
, { 0x9e00 }
345 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
346 & ifmt_addi
, { 0x8000 }
351 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
352 & ifmt_addi
, { 0x9000 }
357 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
358 & ifmt_addi
, { 0x9800 }
363 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
364 & ifmt_addi
, { 0x8100 }
369 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
370 & ifmt_addi
, { 0x9100 }
375 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
376 & ifmt_addi
, { 0x9900 }
381 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
382 & ifmt_addi
, { 0x8800 }
387 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
388 & ifmt_addi
, { 0x8900 }
393 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
394 & ifmt_add
, { 0xaf00 }
399 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
400 & ifmt_add
, { 0xab00 }
405 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
406 & ifmt_add
, { 0xbf00 }
411 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
412 & ifmt_add
, { 0xbb00 }
417 { { MNEM
, ' ', OP (RI
), 0 } },
418 & ifmt_div0s
, { 0x9740 }
423 { { MNEM
, ' ', OP (RI
), 0 } },
424 & ifmt_div0s
, { 0x9750 }
429 { { MNEM
, ' ', OP (RI
), 0 } },
430 & ifmt_div0s
, { 0x9760 }
435 { { MNEM
, ' ', OP (RI
), 0 } },
436 & ifmt_div0s
, { 0x9770 }
442 & ifmt_div3
, { 0x9f60 }
448 & ifmt_div3
, { 0x9f70 }
453 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
454 & ifmt_add
, { 0xb600 }
459 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
460 & ifmt_addi
, { 0xb400 }
465 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
466 & ifmt_addi
, { 0xb500 }
471 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
472 & ifmt_add
, { 0xb200 }
477 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
478 & ifmt_addi
, { 0xb000 }
483 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
484 & ifmt_addi
, { 0xb100 }
489 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
490 & ifmt_add
, { 0xba00 }
495 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
496 & ifmt_addi
, { 0xb800 }
501 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
502 & ifmt_addi
, { 0xb900 }
507 { { MNEM
, ' ', OP (I8
), ',', OP (RI
), 0 } },
508 & ifmt_ldi8
, { 0xc000 }
510 /* ldi:20 $i20,$Ri */
513 { { MNEM
, ' ', OP (I20
), ',', OP (RI
), 0 } },
514 & ifmt_ldi20
, { 0x9b00 }
516 /* ldi:32 $i32,$Ri */
519 { { MNEM
, ' ', OP (I32
), ',', OP (RI
), 0 } },
520 & ifmt_ldi32
, { 0x9f80 }
525 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
526 & ifmt_add
, { 0x400 }
531 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
532 & ifmt_add
, { 0x500 }
537 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
538 & ifmt_add
, { 0x600 }
540 /* ld @($R13,$Rj),$Ri */
543 { { MNEM
, ' ', '@', '(', OP (R13
), ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
546 /* lduh @($R13,$Rj),$Ri */
549 { { MNEM
, ' ', '@', '(', OP (R13
), ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
550 & ifmt_add
, { 0x100 }
552 /* ldub @($R13,$Rj),$Ri */
555 { { MNEM
, ' ', '@', '(', OP (R13
), ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
556 & ifmt_add
, { 0x200 }
558 /* ld @($R14,$disp10),$Ri */
561 { { MNEM
, ' ', '@', '(', OP (R14
), ',', OP (DISP10
), ')', ',', OP (RI
), 0 } },
562 & ifmt_ldr14
, { 0x2000 }
564 /* lduh @($R14,$disp9),$Ri */
567 { { MNEM
, ' ', '@', '(', OP (R14
), ',', OP (DISP9
), ')', ',', OP (RI
), 0 } },
568 & ifmt_ldr14uh
, { 0x4000 }
570 /* ldub @($R14,$disp8),$Ri */
573 { { MNEM
, ' ', '@', '(', OP (R14
), ',', OP (DISP8
), ')', ',', OP (RI
), 0 } },
574 & ifmt_ldr14ub
, { 0x6000 }
576 /* ld @($R15,$udisp6),$Ri */
579 { { MNEM
, ' ', '@', '(', OP (R15
), ',', OP (UDISP6
), ')', ',', OP (RI
), 0 } },
580 & ifmt_ldr15
, { 0x300 }
585 { { MNEM
, ' ', '@', OP (R15
), '+', ',', OP (RI
), 0 } },
586 & ifmt_div0s
, { 0x700 }
591 { { MNEM
, ' ', '@', OP (R15
), '+', ',', OP (RS2
), 0 } },
592 & ifmt_ldr15dr
, { 0x780 }
597 { { MNEM
, ' ', '@', OP (R15
), '+', ',', OP (PS
), 0 } },
598 & ifmt_div3
, { 0x790 }
603 { { MNEM
, ' ', OP (RI
), ',', '@', OP (RJ
), 0 } },
604 & ifmt_add
, { 0x1400 }
609 { { MNEM
, ' ', OP (RI
), ',', '@', OP (RJ
), 0 } },
610 & ifmt_add
, { 0x1500 }
615 { { MNEM
, ' ', OP (RI
), ',', '@', OP (RJ
), 0 } },
616 & ifmt_add
, { 0x1600 }
618 /* st $Ri,@($R13,$Rj) */
621 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R13
), ',', OP (RJ
), ')', 0 } },
622 & ifmt_add
, { 0x1000 }
624 /* sth $Ri,@($R13,$Rj) */
627 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R13
), ',', OP (RJ
), ')', 0 } },
628 & ifmt_add
, { 0x1100 }
630 /* stb $Ri,@($R13,$Rj) */
633 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R13
), ',', OP (RJ
), ')', 0 } },
634 & ifmt_add
, { 0x1200 }
636 /* st $Ri,@($R14,$disp10) */
639 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R14
), ',', OP (DISP10
), ')', 0 } },
640 & ifmt_ldr14
, { 0x3000 }
642 /* sth $Ri,@($R14,$disp9) */
645 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R14
), ',', OP (DISP9
), ')', 0 } },
646 & ifmt_ldr14uh
, { 0x5000 }
648 /* stb $Ri,@($R14,$disp8) */
651 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R14
), ',', OP (DISP8
), ')', 0 } },
652 & ifmt_ldr14ub
, { 0x7000 }
654 /* st $Ri,@($R15,$udisp6) */
657 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R15
), ',', OP (UDISP6
), ')', 0 } },
658 & ifmt_ldr15
, { 0x1300 }
663 { { MNEM
, ' ', OP (RI
), ',', '@', '-', OP (R15
), 0 } },
664 & ifmt_div0s
, { 0x1700 }
669 { { MNEM
, ' ', OP (RS2
), ',', '@', '-', OP (R15
), 0 } },
670 & ifmt_ldr15dr
, { 0x1780 }
675 { { MNEM
, ' ', OP (PS
), ',', '@', '-', OP (R15
), 0 } },
676 & ifmt_div3
, { 0x1790 }
681 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
682 & ifmt_add
, { 0x8b00 }
687 { { MNEM
, ' ', OP (RS1
), ',', OP (RI
), 0 } },
688 & ifmt_movdr
, { 0xb700 }
693 { { MNEM
, ' ', OP (PS
), ',', OP (RI
), 0 } },
694 & ifmt_div0s
, { 0x1710 }
699 { { MNEM
, ' ', OP (RI
), ',', OP (RS1
), 0 } },
700 & ifmt_movdr
, { 0xb300 }
705 { { MNEM
, ' ', OP (RI
), ',', OP (PS
), 0 } },
706 & ifmt_div0s
, { 0x710 }
711 { { MNEM
, ' ', '@', OP (RI
), 0 } },
712 & ifmt_div0s
, { 0x9700 }
717 { { MNEM
, ' ', '@', OP (RI
), 0 } },
718 & ifmt_div0s
, { 0x9f00 }
723 { { MNEM
, ' ', '@', OP (RI
), 0 } },
724 & ifmt_div0s
, { 0x9710 }
729 { { MNEM
, ' ', '@', OP (RI
), 0 } },
730 & ifmt_div0s
, { 0x9f10 }
735 { { MNEM
, ' ', OP (LABEL12
), 0 } },
736 & ifmt_call
, { 0xd000 }
738 /* call:d $label12 */
741 { { MNEM
, ' ', OP (LABEL12
), 0 } },
742 & ifmt_call
, { 0xd800 }
748 & ifmt_div3
, { 0x9720 }
754 & ifmt_div3
, { 0x9f20 }
759 { { MNEM
, ' ', OP (U8
), 0 } },
760 & ifmt_int
, { 0x1f00 }
766 & ifmt_div3
, { 0x9f30 }
772 & ifmt_div3
, { 0x9730 }
777 { { MNEM
, ' ', OP (LABEL9
), 0 } },
778 & ifmt_brad
, { 0xf000 }
783 { { MNEM
, ' ', OP (LABEL9
), 0 } },
784 & ifmt_brad
, { 0xe000 }
789 { { MNEM
, ' ', OP (LABEL9
), 0 } },
790 & ifmt_brad
, { 0xf100 }
795 { { MNEM
, ' ', OP (LABEL9
), 0 } },
796 & ifmt_brad
, { 0xe100 }
801 { { MNEM
, ' ', OP (LABEL9
), 0 } },
802 & ifmt_brad
, { 0xf200 }
807 { { MNEM
, ' ', OP (LABEL9
), 0 } },
808 & ifmt_brad
, { 0xe200 }
813 { { MNEM
, ' ', OP (LABEL9
), 0 } },
814 & ifmt_brad
, { 0xf300 }
819 { { MNEM
, ' ', OP (LABEL9
), 0 } },
820 & ifmt_brad
, { 0xe300 }
825 { { MNEM
, ' ', OP (LABEL9
), 0 } },
826 & ifmt_brad
, { 0xf400 }
831 { { MNEM
, ' ', OP (LABEL9
), 0 } },
832 & ifmt_brad
, { 0xe400 }
837 { { MNEM
, ' ', OP (LABEL9
), 0 } },
838 & ifmt_brad
, { 0xf500 }
843 { { MNEM
, ' ', OP (LABEL9
), 0 } },
844 & ifmt_brad
, { 0xe500 }
849 { { MNEM
, ' ', OP (LABEL9
), 0 } },
850 & ifmt_brad
, { 0xf600 }
855 { { MNEM
, ' ', OP (LABEL9
), 0 } },
856 & ifmt_brad
, { 0xe600 }
861 { { MNEM
, ' ', OP (LABEL9
), 0 } },
862 & ifmt_brad
, { 0xf700 }
867 { { MNEM
, ' ', OP (LABEL9
), 0 } },
868 & ifmt_brad
, { 0xe700 }
873 { { MNEM
, ' ', OP (LABEL9
), 0 } },
874 & ifmt_brad
, { 0xf800 }
879 { { MNEM
, ' ', OP (LABEL9
), 0 } },
880 & ifmt_brad
, { 0xe800 }
885 { { MNEM
, ' ', OP (LABEL9
), 0 } },
886 & ifmt_brad
, { 0xf900 }
891 { { MNEM
, ' ', OP (LABEL9
), 0 } },
892 & ifmt_brad
, { 0xe900 }
897 { { MNEM
, ' ', OP (LABEL9
), 0 } },
898 & ifmt_brad
, { 0xfa00 }
903 { { MNEM
, ' ', OP (LABEL9
), 0 } },
904 & ifmt_brad
, { 0xea00 }
909 { { MNEM
, ' ', OP (LABEL9
), 0 } },
910 & ifmt_brad
, { 0xfb00 }
915 { { MNEM
, ' ', OP (LABEL9
), 0 } },
916 & ifmt_brad
, { 0xeb00 }
921 { { MNEM
, ' ', OP (LABEL9
), 0 } },
922 & ifmt_brad
, { 0xfc00 }
927 { { MNEM
, ' ', OP (LABEL9
), 0 } },
928 & ifmt_brad
, { 0xec00 }
933 { { MNEM
, ' ', OP (LABEL9
), 0 } },
934 & ifmt_brad
, { 0xfd00 }
939 { { MNEM
, ' ', OP (LABEL9
), 0 } },
940 & ifmt_brad
, { 0xed00 }
945 { { MNEM
, ' ', OP (LABEL9
), 0 } },
946 & ifmt_brad
, { 0xfe00 }
951 { { MNEM
, ' ', OP (LABEL9
), 0 } },
952 & ifmt_brad
, { 0xee00 }
957 { { MNEM
, ' ', OP (LABEL9
), 0 } },
958 & ifmt_brad
, { 0xff00 }
963 { { MNEM
, ' ', OP (LABEL9
), 0 } },
964 & ifmt_brad
, { 0xef00 }
966 /* dmov $R13,@$dir10 */
969 { { MNEM
, ' ', OP (R13
), ',', '@', OP (DIR10
), 0 } },
970 & ifmt_dmovr13
, { 0x1800 }
972 /* dmovh $R13,@$dir9 */
975 { { MNEM
, ' ', OP (R13
), ',', '@', OP (DIR9
), 0 } },
976 & ifmt_dmovr13h
, { 0x1900 }
978 /* dmovb $R13,@$dir8 */
981 { { MNEM
, ' ', OP (R13
), ',', '@', OP (DIR8
), 0 } },
982 & ifmt_dmovr13b
, { 0x1a00 }
984 /* dmov @$R13+,@$dir10 */
987 { { MNEM
, ' ', '@', OP (R13
), '+', ',', '@', OP (DIR10
), 0 } },
988 & ifmt_dmovr13
, { 0x1c00 }
990 /* dmovh @$R13+,@$dir9 */
993 { { MNEM
, ' ', '@', OP (R13
), '+', ',', '@', OP (DIR9
), 0 } },
994 & ifmt_dmovr13h
, { 0x1d00 }
996 /* dmovb @$R13+,@$dir8 */
999 { { MNEM
, ' ', '@', OP (R13
), '+', ',', '@', OP (DIR8
), 0 } },
1000 & ifmt_dmovr13b
, { 0x1e00 }
1002 /* dmov @$R15+,@$dir10 */
1005 { { MNEM
, ' ', '@', OP (R15
), '+', ',', '@', OP (DIR10
), 0 } },
1006 & ifmt_dmovr13
, { 0x1b00 }
1008 /* dmov @$dir10,$R13 */
1011 { { MNEM
, ' ', '@', OP (DIR10
), ',', OP (R13
), 0 } },
1012 & ifmt_dmovr13
, { 0x800 }
1014 /* dmovh @$dir9,$R13 */
1017 { { MNEM
, ' ', '@', OP (DIR9
), ',', OP (R13
), 0 } },
1018 & ifmt_dmovr13h
, { 0x900 }
1020 /* dmovb @$dir8,$R13 */
1023 { { MNEM
, ' ', '@', OP (DIR8
), ',', OP (R13
), 0 } },
1024 & ifmt_dmovr13b
, { 0xa00 }
1026 /* dmov @$dir10,@$R13+ */
1029 { { MNEM
, ' ', '@', OP (DIR10
), ',', '@', OP (R13
), '+', 0 } },
1030 & ifmt_dmovr13
, { 0xc00 }
1032 /* dmovh @$dir9,@$R13+ */
1035 { { MNEM
, ' ', '@', OP (DIR9
), ',', '@', OP (R13
), '+', 0 } },
1036 & ifmt_dmovr13h
, { 0xd00 }
1038 /* dmovb @$dir8,@$R13+ */
1041 { { MNEM
, ' ', '@', OP (DIR8
), ',', '@', OP (R13
), '+', 0 } },
1042 & ifmt_dmovr13b
, { 0xe00 }
1044 /* dmov @$dir10,@-$R15 */
1047 { { MNEM
, ' ', '@', OP (DIR10
), ',', '@', '-', OP (R15
), 0 } },
1048 & ifmt_dmovr13
, { 0xb00 }
1050 /* ldres @$Ri+,$u4 */
1053 { { MNEM
, ' ', '@', OP (RI
), '+', ',', OP (U4
), 0 } },
1054 & ifmt_addi
, { 0xbc00 }
1056 /* stres $u4,@$Ri+ */
1059 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), '+', 0 } },
1060 & ifmt_addi
, { 0xbd00 }
1062 /* copop $u4c,$ccc,$CRj,$CRi */
1065 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (CRJ
), ',', OP (CRI
), 0 } },
1066 & ifmt_copop
, { 0x9fc0 }
1068 /* copld $u4c,$ccc,$Rjc,$CRi */
1071 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (RJC
), ',', OP (CRI
), 0 } },
1072 & ifmt_copld
, { 0x9fd0 }
1074 /* copst $u4c,$ccc,$CRj,$Ric */
1077 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (CRJ
), ',', OP (RIC
), 0 } },
1078 & ifmt_copst
, { 0x9fe0 }
1080 /* copsv $u4c,$ccc,$CRj,$Ric */
1083 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (CRJ
), ',', OP (RIC
), 0 } },
1084 & ifmt_copst
, { 0x9ff0 }
1090 & ifmt_div3
, { 0x9fa0 }
1095 { { MNEM
, ' ', OP (U8
), 0 } },
1096 & ifmt_int
, { 0x8300 }
1101 { { MNEM
, ' ', OP (U8
), 0 } },
1102 & ifmt_int
, { 0x9300 }
1107 { { MNEM
, ' ', OP (U8
), 0 } },
1108 & ifmt_int
, { 0x8700 }
1113 { { MNEM
, ' ', OP (S10
), 0 } },
1114 & ifmt_addsp
, { 0xa300 }
1119 { { MNEM
, ' ', OP (RI
), 0 } },
1120 & ifmt_div0s
, { 0x9780 }
1125 { { MNEM
, ' ', OP (RI
), 0 } },
1126 & ifmt_div0s
, { 0x9790 }
1131 { { MNEM
, ' ', OP (RI
), 0 } },
1132 & ifmt_div0s
, { 0x97a0 }
1137 { { MNEM
, ' ', OP (RI
), 0 } },
1138 & ifmt_div0s
, { 0x97b0 }
1140 /* ldm0 ($reglist_low_ld) */
1143 { { MNEM
, ' ', '(', OP (REGLIST_LOW_LD
), ')', 0 } },
1144 & ifmt_ldm0
, { 0x8c00 }
1146 /* ldm1 ($reglist_hi_ld) */
1149 { { MNEM
, ' ', '(', OP (REGLIST_HI_LD
), ')', 0 } },
1150 & ifmt_ldm1
, { 0x8d00 }
1152 /* stm0 ($reglist_low_st) */
1155 { { MNEM
, ' ', '(', OP (REGLIST_LOW_ST
), ')', 0 } },
1156 & ifmt_stm0
, { 0x8e00 }
1158 /* stm1 ($reglist_hi_st) */
1161 { { MNEM
, ' ', '(', OP (REGLIST_HI_ST
), ')', 0 } },
1162 & ifmt_stm1
, { 0x8f00 }
1167 { { MNEM
, ' ', OP (U10
), 0 } },
1168 & ifmt_enter
, { 0xf00 }
1174 & ifmt_div3
, { 0x9f90 }
1179 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
1180 & ifmt_add
, { 0x8a00 }
1189 /* Formats for ALIAS macro-insns. */
1191 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1192 #define F(f) & fr30_cgen_ifld_table[FR30_##f]
1194 #define F(f) & fr30_cgen_ifld_table[FR30_/**/f]
1196 static const CGEN_IFMT ifmt_ldi8m
= {
1197 16, 16, 0xf000, { { F (F_OP1
) }, { F (F_I8
) }, { F (F_RI
) }, { 0 } }
1200 static const CGEN_IFMT ifmt_ldi20m
= {
1201 16, 32, 0xff00, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_RI
) }, { F (F_I20
) }, { 0 } }
1204 static const CGEN_IFMT ifmt_ldi32m
= {
1205 16, 48, 0xfff0, { { F (F_OP1
) }, { F (F_OP2
) }, { F (F_OP3
) }, { F (F_RI
) }, { F (F_I32
) }, { 0 } }
1210 /* Each non-simple macro entry points to an array of expansion possibilities. */
1212 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1213 #define A(a) (1 << CGEN_INSN_##a)
1215 #define A(a) (1 << CGEN_INSN_/**/a)
1217 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1218 #define OPERAND(op) FR30_OPERAND_##op
1220 #define OPERAND(op) FR30_OPERAND_/**/op
1222 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1223 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1225 /* The macro instruction table. */
1227 static const CGEN_IBASE fr30_cgen_macro_insn_table
[] =
1231 -1, "ldi8m", "ldi8", 16,
1232 { 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
) } }
1234 /* ldi20 $i20,$Ri */
1236 -1, "ldi20m", "ldi20", 32,
1237 { 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
) } }
1239 /* ldi32 $i32,$Ri */
1241 -1, "ldi32m", "ldi32", 48,
1242 { 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
) } }
1246 /* The macro instruction opcode table. */
1248 static const CGEN_OPCODE fr30_cgen_macro_insn_opcode_table
[] =
1253 { { MNEM
, ' ', OP (I8
), ',', OP (RI
), 0 } },
1254 & ifmt_ldi8m
, { 0xc000 }
1256 /* ldi20 $i20,$Ri */
1259 { { MNEM
, ' ', OP (I20
), ',', OP (RI
), 0 } },
1260 & ifmt_ldi20m
, { 0x9b00 }
1262 /* ldi32 $i32,$Ri */
1265 { { MNEM
, ' ', OP (I32
), ',', OP (RI
), 0 } },
1266 & ifmt_ldi32m
, { 0x9f80 }
1275 #ifndef CGEN_ASM_HASH_P
1276 #define CGEN_ASM_HASH_P(insn) 1
1279 #ifndef CGEN_DIS_HASH_P
1280 #define CGEN_DIS_HASH_P(insn) 1
1283 /* Return non-zero if INSN is to be added to the hash table.
1284 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
1287 asm_hash_insn_p (insn
)
1288 const CGEN_INSN
*insn ATTRIBUTE_UNUSED
;
1290 return CGEN_ASM_HASH_P (insn
);
1294 dis_hash_insn_p (insn
)
1295 const CGEN_INSN
*insn
;
1297 /* If building the hash table and the NO-DIS attribute is present,
1299 if (CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_NO_DIS
))
1301 return CGEN_DIS_HASH_P (insn
);
1304 #ifndef CGEN_ASM_HASH
1305 #define CGEN_ASM_HASH_SIZE 127
1306 #ifdef CGEN_MNEMONIC_OPERANDS
1307 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
1309 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
1313 /* It doesn't make much sense to provide a default here,
1314 but while this is under development we do.
1315 BUFFER is a pointer to the bytes of the insn, target order.
1316 VALUE is the first base_insn_bitsize bits as an int in host order. */
1318 #ifndef CGEN_DIS_HASH
1319 #define CGEN_DIS_HASH_SIZE 256
1320 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
1323 /* The result is the hash value of the insn.
1324 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
1327 asm_hash_insn (mnem
)
1330 return CGEN_ASM_HASH (mnem
);
1333 /* BUF is a pointer to the bytes of the insn, target order.
1334 VALUE is the first base_insn_bitsize bits as an int in host order. */
1337 dis_hash_insn (buf
, value
)
1339 CGEN_INSN_INT value ATTRIBUTE_UNUSED
;
1341 return CGEN_DIS_HASH (buf
, value
);
1344 /* Set the recorded length of the insn in the CGEN_FIELDS struct. */
1347 set_fields_bitsize (fields
, size
)
1348 CGEN_FIELDS
*fields
;
1351 CGEN_FIELDS_BITSIZE (fields
) = size
;
1354 /* Function to call before using the operand instance table.
1355 This plugs the opcode entries and macro instructions into the cpu table. */
1358 fr30_cgen_init_opcode_table (cd
)
1362 int num_macros
= (sizeof (fr30_cgen_macro_insn_table
) /
1363 sizeof (fr30_cgen_macro_insn_table
[0]));
1364 const CGEN_IBASE
*ib
= & fr30_cgen_macro_insn_table
[0];
1365 const CGEN_OPCODE
*oc
= & fr30_cgen_macro_insn_opcode_table
[0];
1366 CGEN_INSN
*insns
= (CGEN_INSN
*) xmalloc (num_macros
* sizeof (CGEN_INSN
));
1367 memset (insns
, 0, num_macros
* sizeof (CGEN_INSN
));
1368 for (i
= 0; i
< num_macros
; ++i
)
1370 insns
[i
].base
= &ib
[i
];
1371 insns
[i
].opcode
= &oc
[i
];
1372 fr30_cgen_build_insn_regex (& insns
[i
]);
1374 cd
->macro_insn_table
.init_entries
= insns
;
1375 cd
->macro_insn_table
.entry_size
= sizeof (CGEN_IBASE
);
1376 cd
->macro_insn_table
.num_init_entries
= num_macros
;
1378 oc
= & fr30_cgen_insn_opcode_table
[0];
1379 insns
= (CGEN_INSN
*) cd
->insn_table
.init_entries
;
1380 for (i
= 0; i
< MAX_INSNS
; ++i
)
1382 insns
[i
].opcode
= &oc
[i
];
1383 fr30_cgen_build_insn_regex (& insns
[i
]);
1386 cd
->sizeof_fields
= sizeof (CGEN_FIELDS
);
1387 cd
->set_fields_bitsize
= set_fields_bitsize
;
1389 cd
->asm_hash_p
= asm_hash_insn_p
;
1390 cd
->asm_hash
= asm_hash_insn
;
1391 cd
->asm_hash_size
= CGEN_ASM_HASH_SIZE
;
1393 cd
->dis_hash_p
= dis_hash_insn_p
;
1394 cd
->dis_hash
= dis_hash_insn
;
1395 cd
->dis_hash_size
= CGEN_DIS_HASH_SIZE
;