opcodes/fr30-opc.h

   1 /* Instruction description for fr30.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef FR30_OPC_H
  26 #define FR30_OPC_H
  27
  28 #define CGEN_ARCH fr30
  29
  30 /* Given symbol S, return fr30_cgen_<s>.  */
  31 #define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_FR30BF
  35
  36 #define CGEN_INSN_LSB0_P 0
  37 #define CGEN_WORD_BITSIZE 32
  38 #define CGEN_DEFAULT_INSN_BITSIZE 16
  39 #define CGEN_BASE_INSN_BITSIZE 16
  40 #define CGEN_MIN_INSN_BITSIZE 16
  41 #define CGEN_MAX_INSN_BITSIZE 16
  42 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
  43 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
  44 #define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
  45 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
  46 #define CGEN_INT_INSN_P 1
  47
  48 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  49
  50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  51    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  52    we can't hash on everything up to the space.  */
  53 #define CGEN_MNEMONIC_OPERANDS
  54 /* Maximum number of operands any insn or macro-insn has.  */
  55 #define CGEN_MAX_INSN_OPERANDS 16
  56
  57 /* Enums.  */
  58
  59 /* Enum declaration for insn op1 enums.  */
  60 typedef enum insn_op1 {
  61   OP1_0, OP1_1, OP1_2, OP1_3
  62  , OP1_4, OP1_5, OP1_6, OP1_7
  63  , OP1_8, OP1_9, OP1_A, OP1_B
  64  , OP1_C, OP1_D, OP1_E, OP1_F
  65 } INSN_OP1;
  66
  67 /* Enum declaration for insn op2 enums.  */
  68 typedef enum insn_op2 {
  69   OP2_0, OP2_1, OP2_2, OP2_3
  70  , OP2_4, OP2_5, OP2_6, OP2_7
  71  , OP2_8, OP2_9, OP2_A, OP2_B
  72  , OP2_C, OP2_D, OP2_E, OP2_F
  73 } INSN_OP2;
  74
  75 /* Enum declaration for insn op3 enums.  */
  76 typedef enum insn_op3 {
  77   OP3_0, OP3_1, OP3_2, OP3_3
  78  , OP3_4, OP3_5, OP3_6, OP3_7
  79  , OP3_8, OP3_9, OP3_A, OP3_B
  80  , OP3_C, OP3_D, OP3_E, OP3_F
  81 } INSN_OP3;
  82
  83 /* Enum declaration for insn op4 enums.  */
  84 typedef enum insn_op4 {
  85   OP4_0
  86 } INSN_OP4;
  87
  88 /* Enum declaration for insn op5 enums.  */
  89 typedef enum insn_op5 {
  90   OP5_0, OP5_1
  91 } INSN_OP5;
  92
  93 /* Enum declaration for insn cc enums.  */
  94 typedef enum insn_cc {
  95   CC_RA, CC_NO, CC_EQ, CC_NE
  96  , CC_C, CC_NC, CC_N, CC_P
  97  , CC_V, CC_NV, CC_LT, CC_GE
  98  , CC_LE, CC_GT, CC_LS, CC_HI
  99 } INSN_CC;
 100
 101 /* Enum declaration for general registers.  */
 102 typedef enum h_gr {
 103   H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_R0 = 0
 104  , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
 105  , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
 106  , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
 107  , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
 108 } H_GR;
 109
 110 /* Enum declaration for dedicated registers.  */
 111 typedef enum h_dr {
 112   H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
 113  , H_DR_MDH, H_DR_MDL
 114 } H_DR;
 115
 116 /* Enum declaration for control registers.  */
 117 typedef enum h_cr {
 118   H_CR_PC, H_CR_PS
 119 } H_CR;
 120
 121 /* Enum declaration for fr30 operand types.  */
 122 typedef enum cgen_operand_type {
 123   FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RS1
 124  , FR30_OPERAND_RS2, FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_M4
 125  , FR30_OPERAND_I8, FR30_OPERAND_U8, FR30_OPERAND_O8, FR30_OPERAND_S10
 126  , FR30_OPERAND_U10, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10
 127  , FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_CC, FR30_OPERAND_NBIT
 128  , FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_MAX
 129 } CGEN_OPERAND_TYPE;
 130
 131 /* Non-boolean attributes.  */
 132
 133 /* Enum declaration for machine type selection.  */
 134 typedef enum mach_attr {
 135   MACH_BASE, MACH_FR30, MACH_MAX
 136 } MACH_ATTR;
 137
 138 /* Number of architecture variants.  */
 139 #define MAX_MACHS ((int) MACH_MAX)
 140
 141 /* Number of operands types.  */
 142 #define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
 143
 144 /* Maximum number of operands referenced by any insn.  */
 145 #define MAX_OPERAND_INSTANCES 8
 146
 147 /* Hardware, operand and instruction attribute indices.  */
 148
 149 /* Enum declaration for cgen_hw attrs.  */
 150 typedef enum cgen_hw_attr {
 151   CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 152 } CGEN_HW_ATTR;
 153
 154 /* Number of non-boolean elements in cgen_hw.  */
 155 #define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)
 156
 157 /* Enum declaration for cgen_operand attrs.  */
 158 typedef enum cgen_operand_attr {
 159   CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR
 160  , CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED
 161  , CGEN_OPERAND_UNSIGNED
 162 } CGEN_OPERAND_ATTR;
 163
 164 /* Number of non-boolean elements in cgen_operand.  */
 165 #define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
 166
 167 /* Enum declaration for cgen_insn attrs.  */
 168 typedef enum cgen_insn_attr {
 169   CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_NO_DIS, CGEN_INSN_RELAX
 170  , CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI, CGEN_INSN_UNCOND_CTI, CGEN_INSN_VIRTUAL
 171 } CGEN_INSN_ATTR;
 172
 173 /* Number of non-boolean elements in cgen_insn.  */
 174 #define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
 175
 176 /* Enum declaration for fr30 instruction types.  */
 177 typedef enum cgen_insn_type {
 178   FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2
 179  , FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2
 180  , FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP
 181  , FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR
 182  , FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB
 183  , FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM
 184  , FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL
 185  , FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH
 186  , FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU
 187  , FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U
 188  , FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S
 189  , FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR
 190  , FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI
 191  , FR30_INSN_ASR2, FR30_INSN_LDI_8, FR30_INSN_LD, FR30_INSN_LDUH
 192  , FR30_INSN_LDUB, FR30_INSN_LDR13, FR30_INSN_LDR13UH, FR30_INSN_LDR13UB
 193  , FR30_INSN_LDR14, FR30_INSN_LDR14UH, FR30_INSN_LDR14UB, FR30_INSN_LDR15
 194  , FR30_INSN_LDR15GR, FR30_INSN_LDR15DR, FR30_INSN_LDR15PS, FR30_INSN_ST
 195  , FR30_INSN_STH, FR30_INSN_STB, FR30_INSN_STR13, FR30_INSN_STR13H
 196  , FR30_INSN_STR13B, FR30_INSN_STR14, FR30_INSN_STR14H, FR30_INSN_STR14B
 197  , FR30_INSN_STR15, FR30_INSN_STR15GR, FR30_INSN_STR15DR, FR30_INSN_STR15PS
 198  , FR30_INSN_MOV, FR30_INSN_MOVDR, FR30_INSN_MOVPS, FR30_INSN_MOV2DR
 199  , FR30_INSN_MOV2PS, FR30_INSN_JMP, FR30_INSN_CALL, FR30_INSN_CALLR
 200  , FR30_INSN_RET, FR30_INSN_INT, FR30_INSN_INTE, FR30_INSN_RETI
 201  , FR30_INSN_BRA, FR30_INSN_BNO, FR30_INSN_BEQ, FR30_INSN_BNE
 202  , FR30_INSN_BC, FR30_INSN_BNC, FR30_INSN_BN, FR30_INSN_BP
 203  , FR30_INSN_BV, FR30_INSN_BNV, FR30_INSN_BLT, FR30_INSN_BGE
 204  , FR30_INSN_BLE, FR30_INSN_BGT, FR30_INSN_BLS, FR30_INSN_BHI
 205  , FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B, FR30_INSN_DMOVR13
 206  , FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B, FR30_INSN_DMOV2R13PI, FR30_INSN_DMOV2R13PIH
 207  , FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV13PI, FR30_INSN_DMOV13PIH, FR30_INSN_DMOV13PIB
 208  , FR30_INSN_DMOV2R15PD, FR30_INSN_DMOV15PI, FR30_INSN_LDRES, FR30_INSN_STRES
 209  , FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR, FR30_INSN_STILM
 210  , FR30_INSN_ADDSP, FR30_INSN_EXTSB, FR30_INSN_EXTUB, FR30_INSN_EXTSH
 211  , FR30_INSN_EXTUH, FR30_INSN_ENTER, FR30_INSN_LEAVE, FR30_INSN_XCHB
 212  , FR30_INSN_MAX
 213 } CGEN_INSN_TYPE;
 214
 215 /* Index of `invalid' insn place holder.  */
 216 #define CGEN_INSN_INVALID FR30_INSN_INVALID
 217 /* Total number of insns in table.  */
 218 #define MAX_INSNS ((int) FR30_INSN_MAX)
 219
 220 /* cgen.h uses things we just defined.  */
 221 #include "opcode/cgen.h"
 222
 223 /* This struct records data prior to insertion or after extraction.  */
 224 struct cgen_fields
 225 {
 226   long f_nil;
 227   long f_op1;
 228   long f_op2;
 229   long f_op3;
 230   long f_op4;
 231   long f_op5;
 232   long f_cc;
 233   long f_Rj;
 234   long f_Ri;
 235   long f_Rs1;
 236   long f_Rs2;
 237   long f_u4;
 238   long f_i4;
 239   long f_m4;
 240   long f_u8;
 241   long f_i8;
 242   long f_o8;
 243   long f_s10;
 244   long f_u10;
 245   long f_rel8;
 246   long f_dir8;
 247   long f_dir9;
 248   long f_dir10;
 249   long f_rlist;
 250   long f_rel11;
 251   int length;
 252 };
 253
 254 /* Attributes.  */
 255 extern const CGEN_ATTR_TABLE fr30_cgen_hw_attr_table[];
 256 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
 257 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
 258
 259 /* Enum declaration for fr30 hardware types.  */
 260 typedef enum hw_type {
 261   HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
 262  , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_DR
 263  , HW_H_CR, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
 264  , HW_H_CBIT, HW_MAX
 265 } HW_TYPE;
 266
 267 #define MAX_HW ((int) HW_MAX)
 268
 269 /* Hardware decls.  */
 270
 271 extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
 272 extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
 273 extern CGEN_KEYWORD fr30_cgen_opval_h_cr;
 274
 275 #define CGEN_INIT_PARSE(od) \
 276 {\
 277 }
 278 #define CGEN_INIT_INSERT(od) \
 279 {\
 280 }
 281 #define CGEN_INIT_EXTRACT(od) \
 282 {\
 283 }
 284 #define CGEN_INIT_PRINT(od) \
 285 {\
 286 }
 287
 288
 289
 290 #endif /* FR30_OPC_H */