opcodes/fr30-opc.h

   1 /* Instruction description for fr30.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef FR30_OPC_H
  26 #define FR30_OPC_H
  27
  28 #define CGEN_ARCH fr30
  29
  30 /* Given symbol S, return fr30_cgen_<S>.  */
  31 #define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_FR30BF
  35
  36 #define CGEN_INSN_LSB0_P 0
  37 #define CGEN_WORD_BITSIZE 32
  38 #define CGEN_DEFAULT_INSN_BITSIZE 16
  39 #define CGEN_BASE_INSN_BITSIZE 16
  40 #define CGEN_MIN_INSN_BITSIZE 16
  41 #define CGEN_MAX_INSN_BITSIZE 48
  42 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
  43 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
  44 #define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
  45 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
  46 #define CGEN_INT_INSN_P 0
  47
  48 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  49
  50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  51    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  52    we can't hash on everything up to the space.  */
  53 #define CGEN_MNEMONIC_OPERANDS
  54 /* Maximum number of operands any insn or macro-insn has.  */
  55 #define CGEN_MAX_INSN_OPERANDS 16
  56
  57 /* Maximum number of fields in an instruction.  */
  58 #define CGEN_MAX_IFMT_OPERANDS 7
  59
  60 /* Enums.  */
  61
  62 /* Enum declaration for insn op1 enums.  */
  63 typedef enum insn_op1 {
  64   OP1_0, OP1_1, OP1_2, OP1_3
  65  , OP1_4, OP1_5, OP1_6, OP1_7
  66  , OP1_8, OP1_9, OP1_A, OP1_B
  67  , OP1_C, OP1_D, OP1_E, OP1_F
  68 } INSN_OP1;
  69
  70 /* Enum declaration for insn op2 enums.  */
  71 typedef enum insn_op2 {
  72   OP2_0, OP2_1, OP2_2, OP2_3
  73  , OP2_4, OP2_5, OP2_6, OP2_7
  74  , OP2_8, OP2_9, OP2_A, OP2_B
  75  , OP2_C, OP2_D, OP2_E, OP2_F
  76 } INSN_OP2;
  77
  78 /* Enum declaration for insn op3 enums.  */
  79 typedef enum insn_op3 {
  80   OP3_0, OP3_1, OP3_2, OP3_3
  81  , OP3_4, OP3_5, OP3_6, OP3_7
  82  , OP3_8, OP3_9, OP3_A, OP3_B
  83  , OP3_C, OP3_D, OP3_E, OP3_F
  84 } INSN_OP3;
  85
  86 /* Enum declaration for insn op4 enums.  */
  87 typedef enum insn_op4 {
  88   OP4_0
  89 } INSN_OP4;
  90
  91 /* Enum declaration for insn op5 enums.  */
  92 typedef enum insn_op5 {
  93   OP5_0, OP5_1
  94 } INSN_OP5;
  95
  96 /* Enum declaration for insn cc enums.  */
  97 typedef enum insn_cc {
  98   CC_RA, CC_NO, CC_EQ, CC_NE
  99  , CC_C, CC_NC, CC_N, CC_P
 100  , CC_V, CC_NV, CC_LT, CC_GE
 101  , CC_LE, CC_GT, CC_LS, CC_HI
 102 } INSN_CC;
 103
 104 /* Enum declaration for general registers.  */
 105 typedef enum h_gr {
 106   H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_R0 = 0
 107  , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
 108  , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
 109  , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
 110  , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
 111 } H_GR;
 112
 113 /* Enum declaration for coprocessor registers.  */
 114 typedef enum h_cr {
 115   H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
 116  , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
 117  , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
 118  , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
 119 } H_CR;
 120
 121 /* Enum declaration for dedicated registers.  */
 122 typedef enum h_dr {
 123   H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
 124  , H_DR_MDH, H_DR_MDL
 125 } H_DR;
 126
 127 /* Enum declaration for program status.  */
 128 typedef enum h_ps {
 129   H_PS_PS
 130 } H_PS;
 131
 132 /* Enum declaration for General Register 13 explicitely required.  */
 133 typedef enum h_r13 {
 134   H_R13_R13
 135 } H_R13;
 136
 137 /* Enum declaration for General Register 14 explicitely required.  */
 138 typedef enum h_r14 {
 139   H_R14_R14
 140 } H_R14;
 141
 142 /* Enum declaration for General Register 15 explicitely required.  */
 143 typedef enum h_r15 {
 144   H_R15_R15
 145 } H_R15;
 146
 147 /* Enum declaration for fr30 operand types.  */
 148 typedef enum cgen_operand_type {
 149   FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
 150  , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
 151  , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
 152  , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
 153  , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
 154  , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
 155  , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
 156  , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
 157  , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
 158  , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
 159  , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_CCR
 160  , FR30_OPERAND_SCR, FR30_OPERAND_ILM, FR30_OPERAND_MAX
 161 } CGEN_OPERAND_TYPE;
 162
 163 /* Non-boolean attributes.  */
 164
 165 /* Enum declaration for machine type selection.  */
 166 typedef enum mach_attr {
 167   MACH_BASE, MACH_FR30, MACH_MAX
 168 } MACH_ATTR;
 169
 170 /* Number of architecture variants.  */
 171 #define MAX_MACHS ((int) MACH_MAX)
 172
 173 /* Number of operands types.  */
 174 #define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
 175
 176 /* Maximum number of operands referenced by any insn.  */
 177 #define MAX_OPERAND_INSTANCES 12
 178
 179 /* Hardware, operand and instruction attribute indices.  */
 180
 181 /* Enum declaration for cgen_hw attrs.  */
 182 typedef enum cgen_hw_attr {
 183   CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE
 184 } CGEN_HW_ATTR;
 185
 186 /* Number of non-boolean elements in cgen_hw.  */
 187 #define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)
 188
 189 /* Hardware, operand and instruction attribute indices.  */
 190
 191 /* Enum declaration for cgen_ifld attrs.  */
 192 typedef enum cgen_ifld_attr {
 193   CGEN_IFLD_ABS_ADDR, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT
 194  , CGEN_IFLD_SIGNED, CGEN_IFLD_UNSIGNED, CGEN_IFLD_VIRTUAL
 195 } CGEN_IFLD_ATTR;
 196
 197 /* Number of non-boolean elements in cgen_ifld.  */
 198 #define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_ABS_ADDR)
 199
 200 /* Enum declaration for fr30 ifield types.  */
 201 typedef enum ifield_type {
 202   FR30_F_NIL, FR30_F_OP1, FR30_F_OP2, FR30_F_OP3
 203  , FR30_F_OP4, FR30_F_OP5, FR30_F_CC, FR30_F_CCC
 204  , FR30_F_RJ, FR30_F_RI, FR30_F_RS1, FR30_F_RS2
 205  , FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ, FR30_F_CRI
 206  , FR30_F_U4, FR30_F_U4C, FR30_F_I4, FR30_F_M4
 207  , FR30_F_U8, FR30_F_I8, FR30_F_I20_4, FR30_F_I20_16
 208  , FR30_F_I20, FR30_F_I32, FR30_F_UDISP6, FR30_F_DISP8
 209  , FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10, FR30_F_U10
 210  , FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9, FR30_F_DIR10
 211  , FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST, FR30_F_REGLIST_HI_LD
 212  , FR30_F_REGLIST_LOW_LD, FR30_F_MAX
 213 } IFIELD_TYPE;
 214
 215 #define MAX_IFLD ((int) FR30_F_MAX)
 216
 217 /* Enum declaration for cgen_operand attrs.  */
 218 typedef enum cgen_operand_attr {
 219   CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR
 220  , CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED
 221  , CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_VIRTUAL
 222 } CGEN_OPERAND_ATTR;
 223
 224 /* Number of non-boolean elements in cgen_operand.  */
 225 #define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
 226
 227 /* Enum declaration for cgen_insn attrs.  */
 228 typedef enum cgen_insn_attr {
 229   CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_NO_DIS
 230  , CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI
 231  , CGEN_INSN_UNCOND_CTI, CGEN_INSN_VIRTUAL
 232 } CGEN_INSN_ATTR;
 233
 234 /* Number of non-boolean elements in cgen_insn.  */
 235 #define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
 236
 237 /* Enum declaration for fr30 instruction types.  */
 238 typedef enum cgen_insn_type {
 239   FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2
 240  , FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2
 241  , FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP
 242  , FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR
 243  , FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB
 244  , FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM
 245  , FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL
 246  , FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH
 247  , FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU
 248  , FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U
 249  , FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S
 250  , FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR
 251  , FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI
 252  , FR30_INSN_ASR2, FR30_INSN_LDI8, FR30_INSN_LDI20, FR30_INSN_LDI32
 253  , FR30_INSN_LD, FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13
 254  , FR30_INSN_LDR13UH, FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH
 255  , FR30_INSN_LDR14UB, FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR
 256  , FR30_INSN_LDR15PS, FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB
 257  , FR30_INSN_STR13, FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14
 258  , FR30_INSN_STR14H, FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR
 259  , FR30_INSN_STR15DR, FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR
 260  , FR30_INSN_MOVPS, FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP
 261  , FR30_INSN_JMPD, FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL
 262  , FR30_INSN_CALLD, FR30_INSN_RET, FR30_INSN_RET_D, FR30_INSN_INT
 263  , FR30_INSN_INTE, FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BRAD
 264  , FR30_INSN_BNO, FR30_INSN_BNOD, FR30_INSN_BEQ, FR30_INSN_BEQD
 265  , FR30_INSN_BNE, FR30_INSN_BNED, FR30_INSN_BC, FR30_INSN_BCD
 266  , FR30_INSN_BNC, FR30_INSN_BNCD, FR30_INSN_BN, FR30_INSN_BND
 267  , FR30_INSN_BP, FR30_INSN_BPD, FR30_INSN_BV, FR30_INSN_BVD
 268  , FR30_INSN_BNV, FR30_INSN_BNVD, FR30_INSN_BLT, FR30_INSN_BLTD
 269  , FR30_INSN_BGE, FR30_INSN_BGED, FR30_INSN_BLE, FR30_INSN_BLED
 270  , FR30_INSN_BGT, FR30_INSN_BGTD, FR30_INSN_BLS, FR30_INSN_BLSD
 271  , FR30_INSN_BHI, FR30_INSN_BHID, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H
 272  , FR30_INSN_DMOVR13B, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB
 273  , FR30_INSN_DMOVR15PI, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B
 274  , FR30_INSN_DMOV2R13PI, FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD
 275  , FR30_INSN_LDRES, FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD
 276  , FR30_INSN_COPST, FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR
 277  , FR30_INSN_ORCCR, FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB
 278  , FR30_INSN_EXTUB, FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0
 279  , FR30_INSN_LDM1, FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER
 280  , FR30_INSN_LEAVE, FR30_INSN_XCHB, FR30_INSN_MAX
 281 } CGEN_INSN_TYPE;
 282
 283 /* Index of `invalid' insn place holder.  */
 284 #define CGEN_INSN_INVALID FR30_INSN_INVALID
 285 /* Total number of insns in table.  */
 286 #define MAX_INSNS ((int) FR30_INSN_MAX)
 287
 288 /* cgen.h uses things we just defined.  */
 289 #include "opcode/cgen.h"
 290
 291 /* This struct records data prior to insertion or after extraction.  */
 292 struct cgen_fields
 293 {
 294   long f_nil;
 295   long f_op1;
 296   long f_op2;
 297   long f_op3;
 298   long f_op4;
 299   long f_op5;
 300   long f_cc;
 301   long f_ccc;
 302   long f_Rj;
 303   long f_Ri;
 304   long f_Rs1;
 305   long f_Rs2;
 306   long f_Rjc;
 307   long f_Ric;
 308   long f_CRj;
 309   long f_CRi;
 310   long f_u4;
 311   long f_u4c;
 312   long f_i4;
 313   long f_m4;
 314   long f_u8;
 315   long f_i8;
 316   long f_i20_4;
 317   long f_i20_16;
 318   long f_i20;
 319   long f_i32;
 320   long f_udisp6;
 321   long f_disp8;
 322   long f_disp9;
 323   long f_disp10;
 324   long f_s10;
 325   long f_u10;
 326   long f_rel9;
 327   long f_dir8;
 328   long f_dir9;
 329   long f_dir10;
 330   long f_rel12;
 331   long f_reglist_hi_st;
 332   long f_reglist_low_st;
 333   long f_reglist_hi_ld;
 334   long f_reglist_low_ld;
 335   int length;
 336 };
 337
 338 /* Attributes.  */
 339 extern const CGEN_ATTR_TABLE fr30_cgen_hw_attr_table[];
 340 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
 341 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
 342
 343 /* Enum declaration for fr30 hardware types.  */
 344 typedef enum hw_type {
 345   HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
 346  , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR
 347  , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
 348  , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
 349  , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_CCR
 350  , HW_H_SCR, HW_H_ILM, HW_MAX
 351 } HW_TYPE;
 352
 353 #define MAX_HW ((int) HW_MAX)
 354
 355 /* Hardware decls.  */
 356
 357 extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
 358 extern CGEN_KEYWORD fr30_cgen_opval_h_cr;
 359 extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
 360 extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
 361 extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
 362 extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
 363 extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
 364
 365 #define CGEN_INIT_PARSE(od) \
 366 {\
 367 }
 368 #define CGEN_INIT_INSERT(od) \
 369 {\
 370 }
 371 #define CGEN_INIT_EXTRACT(od) \
 372 {\
 373 }
 374 #define CGEN_INIT_PRINT(od) \
 375 {\
 376 }
 377
 378 /* -- opc.h */
 379
 380 /* ??? This can be improved upon.  */
 381 #undef CGEN_DIS_HASH_SIZE
 382 #define CGEN_DIS_HASH_SIZE 16
 383 #undef CGEN_DIS_HASH
 384 #define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4)
 385
 386 /* -- */
 387
 388
 389 #endif /* FR30_OPC_H */