opcodes/fr30-opc.h

   1 /* Instruction description for fr30.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef FR30_OPC_H
  26 #define FR30_OPC_H
  27
  28 #define CGEN_ARCH fr30
  29
  30 /* Given symbol S, return fr30_cgen_<s>.  */
  31 #define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_FR30BF
  35
  36 #define CGEN_INSN_LSB0_P 0
  37 #define CGEN_WORD_BITSIZE 32
  38 #define CGEN_DEFAULT_INSN_BITSIZE 16
  39 #define CGEN_BASE_INSN_BITSIZE 16
  40 #define CGEN_MIN_INSN_BITSIZE 16
  41 #define CGEN_MAX_INSN_BITSIZE 48
  42 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
  43 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
  44 #define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
  45 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
  46 #define CGEN_INT_INSN_P 0
  47
  48 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  49
  50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  51    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  52    we can't hash on everything up to the space.  */
  53 #define CGEN_MNEMONIC_OPERANDS
  54 /* Maximum number of operands any insn or macro-insn has.  */
  55 #define CGEN_MAX_INSN_OPERANDS 16
  56
  57 /* Enums.  */
  58
  59 /* Enum declaration for insn op1 enums.  */
  60 typedef enum insn_op1 {
  61   OP1_0, OP1_1, OP1_2, OP1_3
  62  , OP1_4, OP1_5, OP1_6, OP1_7
  63  , OP1_8, OP1_9, OP1_A, OP1_B
  64  , OP1_C, OP1_D, OP1_E, OP1_F
  65 } INSN_OP1;
  66
  67 /* Enum declaration for insn op2 enums.  */
  68 typedef enum insn_op2 {
  69   OP2_0, OP2_1, OP2_2, OP2_3
  70  , OP2_4, OP2_5, OP2_6, OP2_7
  71  , OP2_8, OP2_9, OP2_A, OP2_B
  72  , OP2_C, OP2_D, OP2_E, OP2_F
  73 } INSN_OP2;
  74
  75 /* Enum declaration for insn op3 enums.  */
  76 typedef enum insn_op3 {
  77   OP3_0, OP3_1, OP3_2, OP3_3
  78  , OP3_4, OP3_5, OP3_6, OP3_7
  79  , OP3_8, OP3_9, OP3_A, OP3_B
  80  , OP3_C, OP3_D, OP3_E, OP3_F
  81 } INSN_OP3;
  82
  83 /* Enum declaration for insn op4 enums.  */
  84 typedef enum insn_op4 {
  85   OP4_0
  86 } INSN_OP4;
  87
  88 /* Enum declaration for insn op5 enums.  */
  89 typedef enum insn_op5 {
  90   OP5_0, OP5_1
  91 } INSN_OP5;
  92
  93 /* Enum declaration for insn cc enums.  */
  94 typedef enum insn_cc {
  95   CC_RA, CC_NO, CC_EQ, CC_NE
  96  , CC_C, CC_NC, CC_N, CC_P
  97  , CC_V, CC_NV, CC_LT, CC_GE
  98  , CC_LE, CC_GT, CC_LS, CC_HI
  99 } INSN_CC;
 100
 101 /* Enum declaration for general registers.  */
 102 typedef enum h_gr {
 103   H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_R0 = 0
 104  , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
 105  , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
 106  , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
 107  , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
 108 } H_GR;
 109
 110 /* Enum declaration for coprocessor registers.  */
 111 typedef enum h_cr {
 112   H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
 113  , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
 114  , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
 115  , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
 116 } H_CR;
 117
 118 /* Enum declaration for dedicated registers.  */
 119 typedef enum h_dr {
 120   H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
 121  , H_DR_MDH, H_DR_MDL
 122 } H_DR;
 123
 124 /* Enum declaration for program status.  */
 125 typedef enum h_ps {
 126   H_PS_PS
 127 } H_PS;
 128
 129 /* Enum declaration for General Register 13 explicitely required.  */
 130 typedef enum h_r13 {
 131   H_R13_R13
 132 } H_R13;
 133
 134 /* Enum declaration for General Register 14 explicitely required.  */
 135 typedef enum h_r14 {
 136   H_R14_R14
 137 } H_R14;
 138
 139 /* Enum declaration for General Register 15 explicitely required.  */
 140 typedef enum h_r15 {
 141   H_R15_R15
 142 } H_R15;
 143
 144 /* Enum declaration for fr30 operand types.  */
 145 typedef enum cgen_operand_type {
 146   FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
 147  , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
 148  , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
 149  , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_M4
 150  , FR30_OPERAND_U8, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8
 151  , FR30_OPERAND_DISP9, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10
 152  , FR30_OPERAND_I32, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10
 153  , FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW, FR30_OPERAND_REGLIST_HI
 154  , FR30_OPERAND_CC, FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT
 155  , FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT
 156  , FR30_OPERAND_MAX
 157 } CGEN_OPERAND_TYPE;
 158
 159 /* Non-boolean attributes.  */
 160
 161 /* Enum declaration for machine type selection.  */
 162 typedef enum mach_attr {
 163   MACH_BASE, MACH_FR30, MACH_MAX
 164 } MACH_ATTR;
 165
 166 /* Number of architecture variants.  */
 167 #define MAX_MACHS ((int) MACH_MAX)
 168
 169 /* Number of operands types.  */
 170 #define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
 171
 172 /* Maximum number of operands referenced by any insn.  */
 173 #define MAX_OPERAND_INSTANCES 9
 174
 175 /* Hardware, operand and instruction attribute indices.  */
 176
 177 /* Enum declaration for cgen_hw attrs.  */
 178 typedef enum cgen_hw_attr {
 179   CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE
 180 } CGEN_HW_ATTR;
 181
 182 /* Number of non-boolean elements in cgen_hw.  */
 183 #define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)
 184
 185 /* Enum declaration for cgen_operand attrs.  */
 186 typedef enum cgen_operand_attr {
 187   CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR
 188  , CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED
 189  , CGEN_OPERAND_UNSIGNED
 190 } CGEN_OPERAND_ATTR;
 191
 192 /* Number of non-boolean elements in cgen_operand.  */
 193 #define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
 194
 195 /* Enum declaration for cgen_insn attrs.  */
 196 typedef enum cgen_insn_attr {
 197   CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_NO_DIS, CGEN_INSN_RELAX
 198  , CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI, CGEN_INSN_UNCOND_CTI, CGEN_INSN_VIRTUAL
 199 } CGEN_INSN_ATTR;
 200
 201 /* Number of non-boolean elements in cgen_insn.  */
 202 #define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
 203
 204 /* Enum declaration for fr30 instruction types.  */
 205 typedef enum cgen_insn_type {
 206   FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2
 207  , FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2
 208  , FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP
 209  , FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR
 210  , FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB
 211  , FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM
 212  , FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL
 213  , FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH
 214  , FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU
 215  , FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U
 216  , FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S
 217  , FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR
 218  , FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI
 219  , FR30_INSN_ASR2, FR30_INSN_LDI_8, FR30_INSN_LDI32, FR30_INSN_LD
 220  , FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13, FR30_INSN_LDR13UH
 221  , FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH, FR30_INSN_LDR14UB
 222  , FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR, FR30_INSN_LDR15PS
 223  , FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB, FR30_INSN_STR13
 224  , FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14, FR30_INSN_STR14H
 225  , FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR, FR30_INSN_STR15DR
 226  , FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR, FR30_INSN_MOVPS
 227  , FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP, FR30_INSN_JMPD
 228  , FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL, FR30_INSN_CALLD
 229  , FR30_INSN_RET, FR30_INSN_RETD, FR30_INSN_INT, FR30_INSN_INTE
 230  , FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BNO, FR30_INSN_BEQ
 231  , FR30_INSN_BNE, FR30_INSN_BC, FR30_INSN_BNC, FR30_INSN_BN
 232  , FR30_INSN_BP, FR30_INSN_BV, FR30_INSN_BNV, FR30_INSN_BLT
 233  , FR30_INSN_BGE, FR30_INSN_BLE, FR30_INSN_BGT, FR30_INSN_BLS
 234  , FR30_INSN_BHI, FR30_INSN_BRAD, FR30_INSN_BNOD, FR30_INSN_BEQD
 235  , FR30_INSN_BNED, FR30_INSN_BCD, FR30_INSN_BNCD, FR30_INSN_BND
 236  , FR30_INSN_BPD, FR30_INSN_BVD, FR30_INSN_BNVD, FR30_INSN_BLTD
 237  , FR30_INSN_BGED, FR30_INSN_BLED, FR30_INSN_BGTD, FR30_INSN_BLSD
 238  , FR30_INSN_BHID, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B
 239  , FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB, FR30_INSN_DMOVR15PI
 240  , FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B, FR30_INSN_DMOV2R13PI
 241  , FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD, FR30_INSN_LDRES
 242  , FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD, FR30_INSN_COPST
 243  , FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR
 244  , FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB, FR30_INSN_EXTUB
 245  , FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0, FR30_INSN_LDM1
 246  , FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER, FR30_INSN_LEAVE
 247  , FR30_INSN_XCHB, FR30_INSN_MAX
 248 } CGEN_INSN_TYPE;
 249
 250 /* Index of `invalid' insn place holder.  */
 251 #define CGEN_INSN_INVALID FR30_INSN_INVALID
 252 /* Total number of insns in table.  */
 253 #define MAX_INSNS ((int) FR30_INSN_MAX)
 254
 255 /* cgen.h uses things we just defined.  */
 256 #include "opcode/cgen.h"
 257
 258 /* This struct records data prior to insertion or after extraction.  */
 259 struct cgen_fields
 260 {
 261   long f_nil;
 262   long f_op1;
 263   long f_op2;
 264   long f_op3;
 265   long f_op4;
 266   long f_op5;
 267   long f_cc;
 268   long f_ccc;
 269   long f_Rj;
 270   long f_Ri;
 271   long f_Rs1;
 272   long f_Rs2;
 273   long f_Rjc;
 274   long f_Ric;
 275   long f_CRj;
 276   long f_CRi;
 277   long f_u4;
 278   long f_u4c;
 279   long f_i4;
 280   long f_m4;
 281   long f_u8;
 282   long f_i8;
 283   long f_i32;
 284   long f_udisp6;
 285   long f_disp8;
 286   long f_disp9;
 287   long f_disp10;
 288   long f_s10;
 289   long f_u10;
 290   long f_rel9;
 291   long f_dir8;
 292   long f_dir9;
 293   long f_dir10;
 294   long f_rel12;
 295   long f_reglist_hi;
 296   long f_reglist_low;
 297   int length;
 298 };
 299
 300 /* Attributes.  */
 301 extern const CGEN_ATTR_TABLE fr30_cgen_hw_attr_table[];
 302 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
 303 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
 304
 305 /* Enum declaration for fr30 hardware types.  */
 306 typedef enum hw_type {
 307   HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
 308  , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR
 309  , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
 310  , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
 311  , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_MAX
 312 } HW_TYPE;
 313
 314 #define MAX_HW ((int) HW_MAX)
 315
 316 /* Hardware decls.  */
 317
 318 extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
 319 extern CGEN_KEYWORD fr30_cgen_opval_h_cr;
 320 extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
 321 extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
 322 extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
 323 extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
 324 extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
 325
 326 #define CGEN_INIT_PARSE(od) \
 327 {\
 328 }
 329 #define CGEN_INIT_INSERT(od) \
 330 {\
 331 }
 332 #define CGEN_INIT_EXTRACT(od) \
 333 {\
 334 }
 335 #define CGEN_INIT_PRINT(od) \
 336 {\
 337 }
 338
 339
 340
 341 #endif /* FR30_OPC_H */