opcodes/frv-desc.c

   1 /* CPU data for frv.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "frv-desc.h"
  32 #include "frv-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35 #include "xregex.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] =
  47 {
  48   { "base", MACH_BASE },
  49   { "frv", MACH_FRV },
  50   { "fr550", MACH_FR550 },
  51   { "fr500", MACH_FR500 },
  52   { "fr450", MACH_FR450 },
  53   { "fr400", MACH_FR400 },
  54   { "tomcat", MACH_TOMCAT },
  55   { "simple", MACH_SIMPLE },
  56   { "max", MACH_MAX },
  57   { 0, 0 }
  58 };
  59
  60 static const CGEN_ATTR_ENTRY ISA_attr[] =
  61 {
  62   { "frv", ISA_FRV },
  63   { "max", ISA_MAX },
  64   { 0, 0 }
  65 };
  66
  67 static const CGEN_ATTR_ENTRY UNIT_attr[] =
  68 {
  69   { "NIL", UNIT_NIL },
  70   { "I0", UNIT_I0 },
  71   { "I1", UNIT_I1 },
  72   { "I01", UNIT_I01 },
  73   { "I2", UNIT_I2 },
  74   { "I3", UNIT_I3 },
  75   { "IALL", UNIT_IALL },
  76   { "FM0", UNIT_FM0 },
  77   { "FM1", UNIT_FM1 },
  78   { "FM01", UNIT_FM01 },
  79   { "FM2", UNIT_FM2 },
  80   { "FM3", UNIT_FM3 },
  81   { "FMALL", UNIT_FMALL },
  82   { "FMLOW", UNIT_FMLOW },
  83   { "B0", UNIT_B0 },
  84   { "B1", UNIT_B1 },
  85   { "B01", UNIT_B01 },
  86   { "C", UNIT_C },
  87   { "MULT_DIV", UNIT_MULT_DIV },
  88   { "IACC", UNIT_IACC },
  89   { "LOAD", UNIT_LOAD },
  90   { "STORE", UNIT_STORE },
  91   { "SCAN", UNIT_SCAN },
  92   { "DCPL", UNIT_DCPL },
  93   { "MDUALACC", UNIT_MDUALACC },
  94   { "MDCUTSSI", UNIT_MDCUTSSI },
  95   { "MCLRACC_1", UNIT_MCLRACC_1 },
  96   { "NUM_UNITS", UNIT_NUM_UNITS },
  97   { 0, 0 }
  98 };
  99
 100 static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] =
 101 {
 102   { "NONE", FR400_MAJOR_NONE },
 103   { "I_1", FR400_MAJOR_I_1 },
 104   { "I_2", FR400_MAJOR_I_2 },
 105   { "I_3", FR400_MAJOR_I_3 },
 106   { "I_4", FR400_MAJOR_I_4 },
 107   { "I_5", FR400_MAJOR_I_5 },
 108   { "B_1", FR400_MAJOR_B_1 },
 109   { "B_2", FR400_MAJOR_B_2 },
 110   { "B_3", FR400_MAJOR_B_3 },
 111   { "B_4", FR400_MAJOR_B_4 },
 112   { "B_5", FR400_MAJOR_B_5 },
 113   { "B_6", FR400_MAJOR_B_6 },
 114   { "C_1", FR400_MAJOR_C_1 },
 115   { "C_2", FR400_MAJOR_C_2 },
 116   { "M_1", FR400_MAJOR_M_1 },
 117   { "M_2", FR400_MAJOR_M_2 },
 118   { 0, 0 }
 119 };
 120
 121 static const CGEN_ATTR_ENTRY FR450_MAJOR_attr[] =
 122 {
 123   { "NONE", FR450_MAJOR_NONE },
 124   { "I_1", FR450_MAJOR_I_1 },
 125   { "I_2", FR450_MAJOR_I_2 },
 126   { "I_3", FR450_MAJOR_I_3 },
 127   { "I_4", FR450_MAJOR_I_4 },
 128   { "I_5", FR450_MAJOR_I_5 },
 129   { "B_1", FR450_MAJOR_B_1 },
 130   { "B_2", FR450_MAJOR_B_2 },
 131   { "B_3", FR450_MAJOR_B_3 },
 132   { "B_4", FR450_MAJOR_B_4 },
 133   { "B_5", FR450_MAJOR_B_5 },
 134   { "B_6", FR450_MAJOR_B_6 },
 135   { "C_1", FR450_MAJOR_C_1 },
 136   { "C_2", FR450_MAJOR_C_2 },
 137   { "M_1", FR450_MAJOR_M_1 },
 138   { "M_2", FR450_MAJOR_M_2 },
 139   { "M_3", FR450_MAJOR_M_3 },
 140   { "M_4", FR450_MAJOR_M_4 },
 141   { "M_5", FR450_MAJOR_M_5 },
 142   { "M_6", FR450_MAJOR_M_6 },
 143   { 0, 0 }
 144 };
 145
 146 static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] =
 147 {
 148   { "NONE", FR500_MAJOR_NONE },
 149   { "I_1", FR500_MAJOR_I_1 },
 150   { "I_2", FR500_MAJOR_I_2 },
 151   { "I_3", FR500_MAJOR_I_3 },
 152   { "I_4", FR500_MAJOR_I_4 },
 153   { "I_5", FR500_MAJOR_I_5 },
 154   { "I_6", FR500_MAJOR_I_6 },
 155   { "B_1", FR500_MAJOR_B_1 },
 156   { "B_2", FR500_MAJOR_B_2 },
 157   { "B_3", FR500_MAJOR_B_3 },
 158   { "B_4", FR500_MAJOR_B_4 },
 159   { "B_5", FR500_MAJOR_B_5 },
 160   { "B_6", FR500_MAJOR_B_6 },
 161   { "C_1", FR500_MAJOR_C_1 },
 162   { "C_2", FR500_MAJOR_C_2 },
 163   { "F_1", FR500_MAJOR_F_1 },
 164   { "F_2", FR500_MAJOR_F_2 },
 165   { "F_3", FR500_MAJOR_F_3 },
 166   { "F_4", FR500_MAJOR_F_4 },
 167   { "F_5", FR500_MAJOR_F_5 },
 168   { "F_6", FR500_MAJOR_F_6 },
 169   { "F_7", FR500_MAJOR_F_7 },
 170   { "F_8", FR500_MAJOR_F_8 },
 171   { "M_1", FR500_MAJOR_M_1 },
 172   { "M_2", FR500_MAJOR_M_2 },
 173   { "M_3", FR500_MAJOR_M_3 },
 174   { "M_4", FR500_MAJOR_M_4 },
 175   { "M_5", FR500_MAJOR_M_5 },
 176   { "M_6", FR500_MAJOR_M_6 },
 177   { "M_7", FR500_MAJOR_M_7 },
 178   { "M_8", FR500_MAJOR_M_8 },
 179   { 0, 0 }
 180 };
 181
 182 static const CGEN_ATTR_ENTRY FR550_MAJOR_attr[] =
 183 {
 184   { "NONE", FR550_MAJOR_NONE },
 185   { "I_1", FR550_MAJOR_I_1 },
 186   { "I_2", FR550_MAJOR_I_2 },
 187   { "I_3", FR550_MAJOR_I_3 },
 188   { "I_4", FR550_MAJOR_I_4 },
 189   { "I_5", FR550_MAJOR_I_5 },
 190   { "I_6", FR550_MAJOR_I_6 },
 191   { "I_7", FR550_MAJOR_I_7 },
 192   { "I_8", FR550_MAJOR_I_8 },
 193   { "B_1", FR550_MAJOR_B_1 },
 194   { "B_2", FR550_MAJOR_B_2 },
 195   { "B_3", FR550_MAJOR_B_3 },
 196   { "B_4", FR550_MAJOR_B_4 },
 197   { "B_5", FR550_MAJOR_B_5 },
 198   { "B_6", FR550_MAJOR_B_6 },
 199   { "C_1", FR550_MAJOR_C_1 },
 200   { "C_2", FR550_MAJOR_C_2 },
 201   { "F_1", FR550_MAJOR_F_1 },
 202   { "F_2", FR550_MAJOR_F_2 },
 203   { "F_3", FR550_MAJOR_F_3 },
 204   { "F_4", FR550_MAJOR_F_4 },
 205   { "M_1", FR550_MAJOR_M_1 },
 206   { "M_2", FR550_MAJOR_M_2 },
 207   { "M_3", FR550_MAJOR_M_3 },
 208   { "M_4", FR550_MAJOR_M_4 },
 209   { "M_5", FR550_MAJOR_M_5 },
 210   { 0, 0 }
 211 };
 212
 213 const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] =
 214 {
 215   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 216   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 217   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 218   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 219   { "RESERVED", &bool_attr[0], &bool_attr[0] },
 220   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 221   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 222   { 0, 0, 0 }
 223 };
 224
 225 const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] =
 226 {
 227   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 228   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 229   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
 230   { "PC", &bool_attr[0], &bool_attr[0] },
 231   { "PROFILE", &bool_attr[0], &bool_attr[0] },
 232   { 0, 0, 0 }
 233 };
 234
 235 const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] =
 236 {
 237   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 238   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 239   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 240   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 241   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 242   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 243   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 244   { "RELAX", &bool_attr[0], &bool_attr[0] },
 245   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 246   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
 247   { 0, 0, 0 }
 248 };
 249
 250 const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
 251 {
 252   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 253   { "UNIT", & UNIT_attr[0], & UNIT_attr[0] },
 254   { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] },
 255   { "FR450-MAJOR", & FR450_MAJOR_attr[0], & FR450_MAJOR_attr[0] },
 256   { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] },
 257   { "FR550-MAJOR", & FR550_MAJOR_attr[0], & FR550_MAJOR_attr[0] },
 258   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 259   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 260   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 261   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 262   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 263   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 264   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 265   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 266   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 267   { "PBB", &bool_attr[0], &bool_attr[0] },
 268   { "PRIVILEGED", &bool_attr[0], &bool_attr[0] },
 269   { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] },
 270   { "CONDITIONAL", &bool_attr[0], &bool_attr[0] },
 271   { "FR-ACCESS", &bool_attr[0], &bool_attr[0] },
 272   { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] },
 273   { "AUDIO", &bool_attr[0], &bool_attr[0] },
 274   { 0, 0, 0 }
 275 };
 276
 277 /* Instruction set variants.  */
 278
 279 static const CGEN_ISA frv_cgen_isa_table[] = {
 280   { "frv", 32, 32, 32, 32 },
 281   { 0, 0, 0, 0, 0 }
 282 };
 283
 284 /* Machine variants.  */
 285
 286 static const CGEN_MACH frv_cgen_mach_table[] = {
 287   { "frv", "frv", MACH_FRV, 0 },
 288   { "fr550", "fr550", MACH_FR550, 0 },
 289   { "fr500", "fr500", MACH_FR500, 0 },
 290   { "tomcat", "tomcat", MACH_TOMCAT, 0 },
 291   { "fr400", "fr400", MACH_FR400, 0 },
 292   { "fr450", "fr450", MACH_FR450, 0 },
 293   { "simple", "simple", MACH_SIMPLE, 0 },
 294   { 0, 0, 0, 0 }
 295 };
 296
 297 static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] =
 298 {
 299   { "sp", 1, {0, {0}}, 0, 0 },
 300   { "fp", 2, {0, {0}}, 0, 0 },
 301   { "gr0", 0, {0, {0}}, 0, 0 },
 302   { "gr1", 1, {0, {0}}, 0, 0 },
 303   { "gr2", 2, {0, {0}}, 0, 0 },
 304   { "gr3", 3, {0, {0}}, 0, 0 },
 305   { "gr4", 4, {0, {0}}, 0, 0 },
 306   { "gr5", 5, {0, {0}}, 0, 0 },
 307   { "gr6", 6, {0, {0}}, 0, 0 },
 308   { "gr7", 7, {0, {0}}, 0, 0 },
 309   { "gr8", 8, {0, {0}}, 0, 0 },
 310   { "gr9", 9, {0, {0}}, 0, 0 },
 311   { "gr10", 10, {0, {0}}, 0, 0 },
 312   { "gr11", 11, {0, {0}}, 0, 0 },
 313   { "gr12", 12, {0, {0}}, 0, 0 },
 314   { "gr13", 13, {0, {0}}, 0, 0 },
 315   { "gr14", 14, {0, {0}}, 0, 0 },
 316   { "gr15", 15, {0, {0}}, 0, 0 },
 317   { "gr16", 16, {0, {0}}, 0, 0 },
 318   { "gr17", 17, {0, {0}}, 0, 0 },
 319   { "gr18", 18, {0, {0}}, 0, 0 },
 320   { "gr19", 19, {0, {0}}, 0, 0 },
 321   { "gr20", 20, {0, {0}}, 0, 0 },
 322   { "gr21", 21, {0, {0}}, 0, 0 },
 323   { "gr22", 22, {0, {0}}, 0, 0 },
 324   { "gr23", 23, {0, {0}}, 0, 0 },
 325   { "gr24", 24, {0, {0}}, 0, 0 },
 326   { "gr25", 25, {0, {0}}, 0, 0 },
 327   { "gr26", 26, {0, {0}}, 0, 0 },
 328   { "gr27", 27, {0, {0}}, 0, 0 },
 329   { "gr28", 28, {0, {0}}, 0, 0 },
 330   { "gr29", 29, {0, {0}}, 0, 0 },
 331   { "gr30", 30, {0, {0}}, 0, 0 },
 332   { "gr31", 31, {0, {0}}, 0, 0 },
 333   { "gr32", 32, {0, {0}}, 0, 0 },
 334   { "gr33", 33, {0, {0}}, 0, 0 },
 335   { "gr34", 34, {0, {0}}, 0, 0 },
 336   { "gr35", 35, {0, {0}}, 0, 0 },
 337   { "gr36", 36, {0, {0}}, 0, 0 },
 338   { "gr37", 37, {0, {0}}, 0, 0 },
 339   { "gr38", 38, {0, {0}}, 0, 0 },
 340   { "gr39", 39, {0, {0}}, 0, 0 },
 341   { "gr40", 40, {0, {0}}, 0, 0 },
 342   { "gr41", 41, {0, {0}}, 0, 0 },
 343   { "gr42", 42, {0, {0}}, 0, 0 },
 344   { "gr43", 43, {0, {0}}, 0, 0 },
 345   { "gr44", 44, {0, {0}}, 0, 0 },
 346   { "gr45", 45, {0, {0}}, 0, 0 },
 347   { "gr46", 46, {0, {0}}, 0, 0 },
 348   { "gr47", 47, {0, {0}}, 0, 0 },
 349   { "gr48", 48, {0, {0}}, 0, 0 },
 350   { "gr49", 49, {0, {0}}, 0, 0 },
 351   { "gr50", 50, {0, {0}}, 0, 0 },
 352   { "gr51", 51, {0, {0}}, 0, 0 },
 353   { "gr52", 52, {0, {0}}, 0, 0 },
 354   { "gr53", 53, {0, {0}}, 0, 0 },
 355   { "gr54", 54, {0, {0}}, 0, 0 },
 356   { "gr55", 55, {0, {0}}, 0, 0 },
 357   { "gr56", 56, {0, {0}}, 0, 0 },
 358   { "gr57", 57, {0, {0}}, 0, 0 },
 359   { "gr58", 58, {0, {0}}, 0, 0 },
 360   { "gr59", 59, {0, {0}}, 0, 0 },
 361   { "gr60", 60, {0, {0}}, 0, 0 },
 362   { "gr61", 61, {0, {0}}, 0, 0 },
 363   { "gr62", 62, {0, {0}}, 0, 0 },
 364   { "gr63", 63, {0, {0}}, 0, 0 }
 365 };
 366
 367 CGEN_KEYWORD frv_cgen_opval_gr_names =
 368 {
 369   & frv_cgen_opval_gr_names_entries[0],
 370   66,
 371   0, 0, 0, 0, ""
 372 };
 373
 374 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] =
 375 {
 376   { "fr0", 0, {0, {0}}, 0, 0 },
 377   { "fr1", 1, {0, {0}}, 0, 0 },
 378   { "fr2", 2, {0, {0}}, 0, 0 },
 379   { "fr3", 3, {0, {0}}, 0, 0 },
 380   { "fr4", 4, {0, {0}}, 0, 0 },
 381   { "fr5", 5, {0, {0}}, 0, 0 },
 382   { "fr6", 6, {0, {0}}, 0, 0 },
 383   { "fr7", 7, {0, {0}}, 0, 0 },
 384   { "fr8", 8, {0, {0}}, 0, 0 },
 385   { "fr9", 9, {0, {0}}, 0, 0 },
 386   { "fr10", 10, {0, {0}}, 0, 0 },
 387   { "fr11", 11, {0, {0}}, 0, 0 },
 388   { "fr12", 12, {0, {0}}, 0, 0 },
 389   { "fr13", 13, {0, {0}}, 0, 0 },
 390   { "fr14", 14, {0, {0}}, 0, 0 },
 391   { "fr15", 15, {0, {0}}, 0, 0 },
 392   { "fr16", 16, {0, {0}}, 0, 0 },
 393   { "fr17", 17, {0, {0}}, 0, 0 },
 394   { "fr18", 18, {0, {0}}, 0, 0 },
 395   { "fr19", 19, {0, {0}}, 0, 0 },
 396   { "fr20", 20, {0, {0}}, 0, 0 },
 397   { "fr21", 21, {0, {0}}, 0, 0 },
 398   { "fr22", 22, {0, {0}}, 0, 0 },
 399   { "fr23", 23, {0, {0}}, 0, 0 },
 400   { "fr24", 24, {0, {0}}, 0, 0 },
 401   { "fr25", 25, {0, {0}}, 0, 0 },
 402   { "fr26", 26, {0, {0}}, 0, 0 },
 403   { "fr27", 27, {0, {0}}, 0, 0 },
 404   { "fr28", 28, {0, {0}}, 0, 0 },
 405   { "fr29", 29, {0, {0}}, 0, 0 },
 406   { "fr30", 30, {0, {0}}, 0, 0 },
 407   { "fr31", 31, {0, {0}}, 0, 0 },
 408   { "fr32", 32, {0, {0}}, 0, 0 },
 409   { "fr33", 33, {0, {0}}, 0, 0 },
 410   { "fr34", 34, {0, {0}}, 0, 0 },
 411   { "fr35", 35, {0, {0}}, 0, 0 },
 412   { "fr36", 36, {0, {0}}, 0, 0 },
 413   { "fr37", 37, {0, {0}}, 0, 0 },
 414   { "fr38", 38, {0, {0}}, 0, 0 },
 415   { "fr39", 39, {0, {0}}, 0, 0 },
 416   { "fr40", 40, {0, {0}}, 0, 0 },
 417   { "fr41", 41, {0, {0}}, 0, 0 },
 418   { "fr42", 42, {0, {0}}, 0, 0 },
 419   { "fr43", 43, {0, {0}}, 0, 0 },
 420   { "fr44", 44, {0, {0}}, 0, 0 },
 421   { "fr45", 45, {0, {0}}, 0, 0 },
 422   { "fr46", 46, {0, {0}}, 0, 0 },
 423   { "fr47", 47, {0, {0}}, 0, 0 },
 424   { "fr48", 48, {0, {0}}, 0, 0 },
 425   { "fr49", 49, {0, {0}}, 0, 0 },
 426   { "fr50", 50, {0, {0}}, 0, 0 },
 427   { "fr51", 51, {0, {0}}, 0, 0 },
 428   { "fr52", 52, {0, {0}}, 0, 0 },
 429   { "fr53", 53, {0, {0}}, 0, 0 },
 430   { "fr54", 54, {0, {0}}, 0, 0 },
 431   { "fr55", 55, {0, {0}}, 0, 0 },
 432   { "fr56", 56, {0, {0}}, 0, 0 },
 433   { "fr57", 57, {0, {0}}, 0, 0 },
 434   { "fr58", 58, {0, {0}}, 0, 0 },
 435   { "fr59", 59, {0, {0}}, 0, 0 },
 436   { "fr60", 60, {0, {0}}, 0, 0 },
 437   { "fr61", 61, {0, {0}}, 0, 0 },
 438   { "fr62", 62, {0, {0}}, 0, 0 },
 439   { "fr63", 63, {0, {0}}, 0, 0 }
 440 };
 441
 442 CGEN_KEYWORD frv_cgen_opval_fr_names =
 443 {
 444   & frv_cgen_opval_fr_names_entries[0],
 445   64,
 446   0, 0, 0, 0, ""
 447 };
 448
 449 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] =
 450 {
 451   { "cpr0", 0, {0, {0}}, 0, 0 },
 452   { "cpr1", 1, {0, {0}}, 0, 0 },
 453   { "cpr2", 2, {0, {0}}, 0, 0 },
 454   { "cpr3", 3, {0, {0}}, 0, 0 },
 455   { "cpr4", 4, {0, {0}}, 0, 0 },
 456   { "cpr5", 5, {0, {0}}, 0, 0 },
 457   { "cpr6", 6, {0, {0}}, 0, 0 },
 458   { "cpr7", 7, {0, {0}}, 0, 0 },
 459   { "cpr8", 8, {0, {0}}, 0, 0 },
 460   { "cpr9", 9, {0, {0}}, 0, 0 },
 461   { "cpr10", 10, {0, {0}}, 0, 0 },
 462   { "cpr11", 11, {0, {0}}, 0, 0 },
 463   { "cpr12", 12, {0, {0}}, 0, 0 },
 464   { "cpr13", 13, {0, {0}}, 0, 0 },
 465   { "cpr14", 14, {0, {0}}, 0, 0 },
 466   { "cpr15", 15, {0, {0}}, 0, 0 },
 467   { "cpr16", 16, {0, {0}}, 0, 0 },
 468   { "cpr17", 17, {0, {0}}, 0, 0 },
 469   { "cpr18", 18, {0, {0}}, 0, 0 },
 470   { "cpr19", 19, {0, {0}}, 0, 0 },
 471   { "cpr20", 20, {0, {0}}, 0, 0 },
 472   { "cpr21", 21, {0, {0}}, 0, 0 },
 473   { "cpr22", 22, {0, {0}}, 0, 0 },
 474   { "cpr23", 23, {0, {0}}, 0, 0 },
 475   { "cpr24", 24, {0, {0}}, 0, 0 },
 476   { "cpr25", 25, {0, {0}}, 0, 0 },
 477   { "cpr26", 26, {0, {0}}, 0, 0 },
 478   { "cpr27", 27, {0, {0}}, 0, 0 },
 479   { "cpr28", 28, {0, {0}}, 0, 0 },
 480   { "cpr29", 29, {0, {0}}, 0, 0 },
 481   { "cpr30", 30, {0, {0}}, 0, 0 },
 482   { "cpr31", 31, {0, {0}}, 0, 0 },
 483   { "cpr32", 32, {0, {0}}, 0, 0 },
 484   { "cpr33", 33, {0, {0}}, 0, 0 },
 485   { "cpr34", 34, {0, {0}}, 0, 0 },
 486   { "cpr35", 35, {0, {0}}, 0, 0 },
 487   { "cpr36", 36, {0, {0}}, 0, 0 },
 488   { "cpr37", 37, {0, {0}}, 0, 0 },
 489   { "cpr38", 38, {0, {0}}, 0, 0 },
 490   { "cpr39", 39, {0, {0}}, 0, 0 },
 491   { "cpr40", 40, {0, {0}}, 0, 0 },
 492   { "cpr41", 41, {0, {0}}, 0, 0 },
 493   { "cpr42", 42, {0, {0}}, 0, 0 },
 494   { "cpr43", 43, {0, {0}}, 0, 0 },
 495   { "cpr44", 44, {0, {0}}, 0, 0 },
 496   { "cpr45", 45, {0, {0}}, 0, 0 },
 497   { "cpr46", 46, {0, {0}}, 0, 0 },
 498   { "cpr47", 47, {0, {0}}, 0, 0 },
 499   { "cpr48", 48, {0, {0}}, 0, 0 },
 500   { "cpr49", 49, {0, {0}}, 0, 0 },
 501   { "cpr50", 50, {0, {0}}, 0, 0 },
 502   { "cpr51", 51, {0, {0}}, 0, 0 },
 503   { "cpr52", 52, {0, {0}}, 0, 0 },
 504   { "cpr53", 53, {0, {0}}, 0, 0 },
 505   { "cpr54", 54, {0, {0}}, 0, 0 },
 506   { "cpr55", 55, {0, {0}}, 0, 0 },
 507   { "cpr56", 56, {0, {0}}, 0, 0 },
 508   { "cpr57", 57, {0, {0}}, 0, 0 },
 509   { "cpr58", 58, {0, {0}}, 0, 0 },
 510   { "cpr59", 59, {0, {0}}, 0, 0 },
 511   { "cpr60", 60, {0, {0}}, 0, 0 },
 512   { "cpr61", 61, {0, {0}}, 0, 0 },
 513   { "cpr62", 62, {0, {0}}, 0, 0 },
 514   { "cpr63", 63, {0, {0}}, 0, 0 }
 515 };
 516
 517 CGEN_KEYWORD frv_cgen_opval_cpr_names =
 518 {
 519   & frv_cgen_opval_cpr_names_entries[0],
 520   64,
 521   0, 0, 0, 0, ""
 522 };
 523
 524 static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
 525 {
 526   { "psr", 0, {0, {0}}, 0, 0 },
 527   { "pcsr", 1, {0, {0}}, 0, 0 },
 528   { "bpcsr", 2, {0, {0}}, 0, 0 },
 529   { "tbr", 3, {0, {0}}, 0, 0 },
 530   { "bpsr", 4, {0, {0}}, 0, 0 },
 531   { "hsr0", 16, {0, {0}}, 0, 0 },
 532   { "hsr1", 17, {0, {0}}, 0, 0 },
 533   { "hsr2", 18, {0, {0}}, 0, 0 },
 534   { "hsr3", 19, {0, {0}}, 0, 0 },
 535   { "hsr4", 20, {0, {0}}, 0, 0 },
 536   { "hsr5", 21, {0, {0}}, 0, 0 },
 537   { "hsr6", 22, {0, {0}}, 0, 0 },
 538   { "hsr7", 23, {0, {0}}, 0, 0 },
 539   { "hsr8", 24, {0, {0}}, 0, 0 },
 540   { "hsr9", 25, {0, {0}}, 0, 0 },
 541   { "hsr10", 26, {0, {0}}, 0, 0 },
 542   { "hsr11", 27, {0, {0}}, 0, 0 },
 543   { "hsr12", 28, {0, {0}}, 0, 0 },
 544   { "hsr13", 29, {0, {0}}, 0, 0 },
 545   { "hsr14", 30, {0, {0}}, 0, 0 },
 546   { "hsr15", 31, {0, {0}}, 0, 0 },
 547   { "hsr16", 32, {0, {0}}, 0, 0 },
 548   { "hsr17", 33, {0, {0}}, 0, 0 },
 549   { "hsr18", 34, {0, {0}}, 0, 0 },
 550   { "hsr19", 35, {0, {0}}, 0, 0 },
 551   { "hsr20", 36, {0, {0}}, 0, 0 },
 552   { "hsr21", 37, {0, {0}}, 0, 0 },
 553   { "hsr22", 38, {0, {0}}, 0, 0 },
 554   { "hsr23", 39, {0, {0}}, 0, 0 },
 555   { "hsr24", 40, {0, {0}}, 0, 0 },
 556   { "hsr25", 41, {0, {0}}, 0, 0 },
 557   { "hsr26", 42, {0, {0}}, 0, 0 },
 558   { "hsr27", 43, {0, {0}}, 0, 0 },
 559   { "hsr28", 44, {0, {0}}, 0, 0 },
 560   { "hsr29", 45, {0, {0}}, 0, 0 },
 561   { "hsr30", 46, {0, {0}}, 0, 0 },
 562   { "hsr31", 47, {0, {0}}, 0, 0 },
 563   { "hsr32", 48, {0, {0}}, 0, 0 },
 564   { "hsr33", 49, {0, {0}}, 0, 0 },
 565   { "hsr34", 50, {0, {0}}, 0, 0 },
 566   { "hsr35", 51, {0, {0}}, 0, 0 },
 567   { "hsr36", 52, {0, {0}}, 0, 0 },
 568   { "hsr37", 53, {0, {0}}, 0, 0 },
 569   { "hsr38", 54, {0, {0}}, 0, 0 },
 570   { "hsr39", 55, {0, {0}}, 0, 0 },
 571   { "hsr40", 56, {0, {0}}, 0, 0 },
 572   { "hsr41", 57, {0, {0}}, 0, 0 },
 573   { "hsr42", 58, {0, {0}}, 0, 0 },
 574   { "hsr43", 59, {0, {0}}, 0, 0 },
 575   { "hsr44", 60, {0, {0}}, 0, 0 },
 576   { "hsr45", 61, {0, {0}}, 0, 0 },
 577   { "hsr46", 62, {0, {0}}, 0, 0 },
 578   { "hsr47", 63, {0, {0}}, 0, 0 },
 579   { "hsr48", 64, {0, {0}}, 0, 0 },
 580   { "hsr49", 65, {0, {0}}, 0, 0 },
 581   { "hsr50", 66, {0, {0}}, 0, 0 },
 582   { "hsr51", 67, {0, {0}}, 0, 0 },
 583   { "hsr52", 68, {0, {0}}, 0, 0 },
 584   { "hsr53", 69, {0, {0}}, 0, 0 },
 585   { "hsr54", 70, {0, {0}}, 0, 0 },
 586   { "hsr55", 71, {0, {0}}, 0, 0 },
 587   { "hsr56", 72, {0, {0}}, 0, 0 },
 588   { "hsr57", 73, {0, {0}}, 0, 0 },
 589   { "hsr58", 74, {0, {0}}, 0, 0 },
 590   { "hsr59", 75, {0, {0}}, 0, 0 },
 591   { "hsr60", 76, {0, {0}}, 0, 0 },
 592   { "hsr61", 77, {0, {0}}, 0, 0 },
 593   { "hsr62", 78, {0, {0}}, 0, 0 },
 594   { "hsr63", 79, {0, {0}}, 0, 0 },
 595   { "ccr", 256, {0, {0}}, 0, 0 },
 596   { "cccr", 263, {0, {0}}, 0, 0 },
 597   { "lr", 272, {0, {0}}, 0, 0 },
 598   { "lcr", 273, {0, {0}}, 0, 0 },
 599   { "iacc0h", 280, {0, {0}}, 0, 0 },
 600   { "iacc0l", 281, {0, {0}}, 0, 0 },
 601   { "isr", 288, {0, {0}}, 0, 0 },
 602   { "neear0", 352, {0, {0}}, 0, 0 },
 603   { "neear1", 353, {0, {0}}, 0, 0 },
 604   { "neear2", 354, {0, {0}}, 0, 0 },
 605   { "neear3", 355, {0, {0}}, 0, 0 },
 606   { "neear4", 356, {0, {0}}, 0, 0 },
 607   { "neear5", 357, {0, {0}}, 0, 0 },
 608   { "neear6", 358, {0, {0}}, 0, 0 },
 609   { "neear7", 359, {0, {0}}, 0, 0 },
 610   { "neear8", 360, {0, {0}}, 0, 0 },
 611   { "neear9", 361, {0, {0}}, 0, 0 },
 612   { "neear10", 362, {0, {0}}, 0, 0 },
 613   { "neear11", 363, {0, {0}}, 0, 0 },
 614   { "neear12", 364, {0, {0}}, 0, 0 },
 615   { "neear13", 365, {0, {0}}, 0, 0 },
 616   { "neear14", 366, {0, {0}}, 0, 0 },
 617   { "neear15", 367, {0, {0}}, 0, 0 },
 618   { "neear16", 368, {0, {0}}, 0, 0 },
 619   { "neear17", 369, {0, {0}}, 0, 0 },
 620   { "neear18", 370, {0, {0}}, 0, 0 },
 621   { "neear19", 371, {0, {0}}, 0, 0 },
 622   { "neear20", 372, {0, {0}}, 0, 0 },
 623   { "neear21", 373, {0, {0}}, 0, 0 },
 624   { "neear22", 374, {0, {0}}, 0, 0 },
 625   { "neear23", 375, {0, {0}}, 0, 0 },
 626   { "neear24", 376, {0, {0}}, 0, 0 },
 627   { "neear25", 377, {0, {0}}, 0, 0 },
 628   { "neear26", 378, {0, {0}}, 0, 0 },
 629   { "neear27", 379, {0, {0}}, 0, 0 },
 630   { "neear28", 380, {0, {0}}, 0, 0 },
 631   { "neear29", 381, {0, {0}}, 0, 0 },
 632   { "neear30", 382, {0, {0}}, 0, 0 },
 633   { "neear31", 383, {0, {0}}, 0, 0 },
 634   { "nesr0", 384, {0, {0}}, 0, 0 },
 635   { "nesr1", 385, {0, {0}}, 0, 0 },
 636   { "nesr2", 386, {0, {0}}, 0, 0 },
 637   { "nesr3", 387, {0, {0}}, 0, 0 },
 638   { "nesr4", 388, {0, {0}}, 0, 0 },
 639   { "nesr5", 389, {0, {0}}, 0, 0 },
 640   { "nesr6", 390, {0, {0}}, 0, 0 },
 641   { "nesr7", 391, {0, {0}}, 0, 0 },
 642   { "nesr8", 392, {0, {0}}, 0, 0 },
 643   { "nesr9", 393, {0, {0}}, 0, 0 },
 644   { "nesr10", 394, {0, {0}}, 0, 0 },
 645   { "nesr11", 395, {0, {0}}, 0, 0 },
 646   { "nesr12", 396, {0, {0}}, 0, 0 },
 647   { "nesr13", 397, {0, {0}}, 0, 0 },
 648   { "nesr14", 398, {0, {0}}, 0, 0 },
 649   { "nesr15", 399, {0, {0}}, 0, 0 },
 650   { "nesr16", 400, {0, {0}}, 0, 0 },
 651   { "nesr17", 401, {0, {0}}, 0, 0 },
 652   { "nesr18", 402, {0, {0}}, 0, 0 },
 653   { "nesr19", 403, {0, {0}}, 0, 0 },
 654   { "nesr20", 404, {0, {0}}, 0, 0 },
 655   { "nesr21", 405, {0, {0}}, 0, 0 },
 656   { "nesr22", 406, {0, {0}}, 0, 0 },
 657   { "nesr23", 407, {0, {0}}, 0, 0 },
 658   { "nesr24", 408, {0, {0}}, 0, 0 },
 659   { "nesr25", 409, {0, {0}}, 0, 0 },
 660   { "nesr26", 410, {0, {0}}, 0, 0 },
 661   { "nesr27", 411, {0, {0}}, 0, 0 },
 662   { "nesr28", 412, {0, {0}}, 0, 0 },
 663   { "nesr29", 413, {0, {0}}, 0, 0 },
 664   { "nesr30", 414, {0, {0}}, 0, 0 },
 665   { "nesr31", 415, {0, {0}}, 0, 0 },
 666   { "necr", 416, {0, {0}}, 0, 0 },
 667   { "gner0", 432, {0, {0}}, 0, 0 },
 668   { "gner1", 433, {0, {0}}, 0, 0 },
 669   { "fner0", 434, {0, {0}}, 0, 0 },
 670   { "fner1", 435, {0, {0}}, 0, 0 },
 671   { "epcr0", 512, {0, {0}}, 0, 0 },
 672   { "epcr1", 513, {0, {0}}, 0, 0 },
 673   { "epcr2", 514, {0, {0}}, 0, 0 },
 674   { "epcr3", 515, {0, {0}}, 0, 0 },
 675   { "epcr4", 516, {0, {0}}, 0, 0 },
 676   { "epcr5", 517, {0, {0}}, 0, 0 },
 677   { "epcr6", 518, {0, {0}}, 0, 0 },
 678   { "epcr7", 519, {0, {0}}, 0, 0 },
 679   { "epcr8", 520, {0, {0}}, 0, 0 },
 680   { "epcr9", 521, {0, {0}}, 0, 0 },
 681   { "epcr10", 522, {0, {0}}, 0, 0 },
 682   { "epcr11", 523, {0, {0}}, 0, 0 },
 683   { "epcr12", 524, {0, {0}}, 0, 0 },
 684   { "epcr13", 525, {0, {0}}, 0, 0 },
 685   { "epcr14", 526, {0, {0}}, 0, 0 },
 686   { "epcr15", 527, {0, {0}}, 0, 0 },
 687   { "epcr16", 528, {0, {0}}, 0, 0 },
 688   { "epcr17", 529, {0, {0}}, 0, 0 },
 689   { "epcr18", 530, {0, {0}}, 0, 0 },
 690   { "epcr19", 531, {0, {0}}, 0, 0 },
 691   { "epcr20", 532, {0, {0}}, 0, 0 },
 692   { "epcr21", 533, {0, {0}}, 0, 0 },
 693   { "epcr22", 534, {0, {0}}, 0, 0 },
 694   { "epcr23", 535, {0, {0}}, 0, 0 },
 695   { "epcr24", 536, {0, {0}}, 0, 0 },
 696   { "epcr25", 537, {0, {0}}, 0, 0 },
 697   { "epcr26", 538, {0, {0}}, 0, 0 },
 698   { "epcr27", 539, {0, {0}}, 0, 0 },
 699   { "epcr28", 540, {0, {0}}, 0, 0 },
 700   { "epcr29", 541, {0, {0}}, 0, 0 },
 701   { "epcr30", 542, {0, {0}}, 0, 0 },
 702   { "epcr31", 543, {0, {0}}, 0, 0 },
 703   { "epcr32", 544, {0, {0}}, 0, 0 },
 704   { "epcr33", 545, {0, {0}}, 0, 0 },
 705   { "epcr34", 546, {0, {0}}, 0, 0 },
 706   { "epcr35", 547, {0, {0}}, 0, 0 },
 707   { "epcr36", 548, {0, {0}}, 0, 0 },
 708   { "epcr37", 549, {0, {0}}, 0, 0 },
 709   { "epcr38", 550, {0, {0}}, 0, 0 },
 710   { "epcr39", 551, {0, {0}}, 0, 0 },
 711   { "epcr40", 552, {0, {0}}, 0, 0 },
 712   { "epcr41", 553, {0, {0}}, 0, 0 },
 713   { "epcr42", 554, {0, {0}}, 0, 0 },
 714   { "epcr43", 555, {0, {0}}, 0, 0 },
 715   { "epcr44", 556, {0, {0}}, 0, 0 },
 716   { "epcr45", 557, {0, {0}}, 0, 0 },
 717   { "epcr46", 558, {0, {0}}, 0, 0 },
 718   { "epcr47", 559, {0, {0}}, 0, 0 },
 719   { "epcr48", 560, {0, {0}}, 0, 0 },
 720   { "epcr49", 561, {0, {0}}, 0, 0 },
 721   { "epcr50", 562, {0, {0}}, 0, 0 },
 722   { "epcr51", 563, {0, {0}}, 0, 0 },
 723   { "epcr52", 564, {0, {0}}, 0, 0 },
 724   { "epcr53", 565, {0, {0}}, 0, 0 },
 725   { "epcr54", 566, {0, {0}}, 0, 0 },
 726   { "epcr55", 567, {0, {0}}, 0, 0 },
 727   { "epcr56", 568, {0, {0}}, 0, 0 },
 728   { "epcr57", 569, {0, {0}}, 0, 0 },
 729   { "epcr58", 570, {0, {0}}, 0, 0 },
 730   { "epcr59", 571, {0, {0}}, 0, 0 },
 731   { "epcr60", 572, {0, {0}}, 0, 0 },
 732   { "epcr61", 573, {0, {0}}, 0, 0 },
 733   { "epcr62", 574, {0, {0}}, 0, 0 },
 734   { "epcr63", 575, {0, {0}}, 0, 0 },
 735   { "esr0", 576, {0, {0}}, 0, 0 },
 736   { "esr1", 577, {0, {0}}, 0, 0 },
 737   { "esr2", 578, {0, {0}}, 0, 0 },
 738   { "esr3", 579, {0, {0}}, 0, 0 },
 739   { "esr4", 580, {0, {0}}, 0, 0 },
 740   { "esr5", 581, {0, {0}}, 0, 0 },
 741   { "esr6", 582, {0, {0}}, 0, 0 },
 742   { "esr7", 583, {0, {0}}, 0, 0 },
 743   { "esr8", 584, {0, {0}}, 0, 0 },
 744   { "esr9", 585, {0, {0}}, 0, 0 },
 745   { "esr10", 586, {0, {0}}, 0, 0 },
 746   { "esr11", 587, {0, {0}}, 0, 0 },
 747   { "esr12", 588, {0, {0}}, 0, 0 },
 748   { "esr13", 589, {0, {0}}, 0, 0 },
 749   { "esr14", 590, {0, {0}}, 0, 0 },
 750   { "esr15", 591, {0, {0}}, 0, 0 },
 751   { "esr16", 592, {0, {0}}, 0, 0 },
 752   { "esr17", 593, {0, {0}}, 0, 0 },
 753   { "esr18", 594, {0, {0}}, 0, 0 },
 754   { "esr19", 595, {0, {0}}, 0, 0 },
 755   { "esr20", 596, {0, {0}}, 0, 0 },
 756   { "esr21", 597, {0, {0}}, 0, 0 },
 757   { "esr22", 598, {0, {0}}, 0, 0 },
 758   { "esr23", 599, {0, {0}}, 0, 0 },
 759   { "esr24", 600, {0, {0}}, 0, 0 },
 760   { "esr25", 601, {0, {0}}, 0, 0 },
 761   { "esr26", 602, {0, {0}}, 0, 0 },
 762   { "esr27", 603, {0, {0}}, 0, 0 },
 763   { "esr28", 604, {0, {0}}, 0, 0 },
 764   { "esr29", 605, {0, {0}}, 0, 0 },
 765   { "esr30", 606, {0, {0}}, 0, 0 },
 766   { "esr31", 607, {0, {0}}, 0, 0 },
 767   { "esr32", 608, {0, {0}}, 0, 0 },
 768   { "esr33", 609, {0, {0}}, 0, 0 },
 769   { "esr34", 610, {0, {0}}, 0, 0 },
 770   { "esr35", 611, {0, {0}}, 0, 0 },
 771   { "esr36", 612, {0, {0}}, 0, 0 },
 772   { "esr37", 613, {0, {0}}, 0, 0 },
 773   { "esr38", 614, {0, {0}}, 0, 0 },
 774   { "esr39", 615, {0, {0}}, 0, 0 },
 775   { "esr40", 616, {0, {0}}, 0, 0 },
 776   { "esr41", 617, {0, {0}}, 0, 0 },
 777   { "esr42", 618, {0, {0}}, 0, 0 },
 778   { "esr43", 619, {0, {0}}, 0, 0 },
 779   { "esr44", 620, {0, {0}}, 0, 0 },
 780   { "esr45", 621, {0, {0}}, 0, 0 },
 781   { "esr46", 622, {0, {0}}, 0, 0 },
 782   { "esr47", 623, {0, {0}}, 0, 0 },
 783   { "esr48", 624, {0, {0}}, 0, 0 },
 784   { "esr49", 625, {0, {0}}, 0, 0 },
 785   { "esr50", 626, {0, {0}}, 0, 0 },
 786   { "esr51", 627, {0, {0}}, 0, 0 },
 787   { "esr52", 628, {0, {0}}, 0, 0 },
 788   { "esr53", 629, {0, {0}}, 0, 0 },
 789   { "esr54", 630, {0, {0}}, 0, 0 },
 790   { "esr55", 631, {0, {0}}, 0, 0 },
 791   { "esr56", 632, {0, {0}}, 0, 0 },
 792   { "esr57", 633, {0, {0}}, 0, 0 },
 793   { "esr58", 634, {0, {0}}, 0, 0 },
 794   { "esr59", 635, {0, {0}}, 0, 0 },
 795   { "esr60", 636, {0, {0}}, 0, 0 },
 796   { "esr61", 637, {0, {0}}, 0, 0 },
 797   { "esr62", 638, {0, {0}}, 0, 0 },
 798   { "esr63", 639, {0, {0}}, 0, 0 },
 799   { "eir0", 640, {0, {0}}, 0, 0 },
 800   { "eir1", 641, {0, {0}}, 0, 0 },
 801   { "eir2", 642, {0, {0}}, 0, 0 },
 802   { "eir3", 643, {0, {0}}, 0, 0 },
 803   { "eir4", 644, {0, {0}}, 0, 0 },
 804   { "eir5", 645, {0, {0}}, 0, 0 },
 805   { "eir6", 646, {0, {0}}, 0, 0 },
 806   { "eir7", 647, {0, {0}}, 0, 0 },
 807   { "eir8", 648, {0, {0}}, 0, 0 },
 808   { "eir9", 649, {0, {0}}, 0, 0 },
 809   { "eir10", 650, {0, {0}}, 0, 0 },
 810   { "eir11", 651, {0, {0}}, 0, 0 },
 811   { "eir12", 652, {0, {0}}, 0, 0 },
 812   { "eir13", 653, {0, {0}}, 0, 0 },
 813   { "eir14", 654, {0, {0}}, 0, 0 },
 814   { "eir15", 655, {0, {0}}, 0, 0 },
 815   { "eir16", 656, {0, {0}}, 0, 0 },
 816   { "eir17", 657, {0, {0}}, 0, 0 },
 817   { "eir18", 658, {0, {0}}, 0, 0 },
 818   { "eir19", 659, {0, {0}}, 0, 0 },
 819   { "eir20", 660, {0, {0}}, 0, 0 },
 820   { "eir21", 661, {0, {0}}, 0, 0 },
 821   { "eir22", 662, {0, {0}}, 0, 0 },
 822   { "eir23", 663, {0, {0}}, 0, 0 },
 823   { "eir24", 664, {0, {0}}, 0, 0 },
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1000   { "msr29", 1309, {0, {0}}, 0, 0 },
1001   { "msr30", 1310, {0, {0}}, 0, 0 },
1002   { "msr31", 1311, {0, {0}}, 0, 0 },
1003   { "msr32", 1312, {0, {0}}, 0, 0 },
1004   { "msr33", 1313, {0, {0}}, 0, 0 },
1005   { "msr34", 1314, {0, {0}}, 0, 0 },
1006   { "msr35", 1315, {0, {0}}, 0, 0 },
1007   { "msr36", 1316, {0, {0}}, 0, 0 },
1008   { "msr37", 1317, {0, {0}}, 0, 0 },
1009   { "msr38", 1318, {0, {0}}, 0, 0 },
1010   { "msr39", 1319, {0, {0}}, 0, 0 },
1011   { "msr40", 1320, {0, {0}}, 0, 0 },
1012   { "msr41", 1321, {0, {0}}, 0, 0 },
1013   { "msr42", 1322, {0, {0}}, 0, 0 },
1014   { "msr43", 1323, {0, {0}}, 0, 0 },
1015   { "msr44", 1324, {0, {0}}, 0, 0 },
1016   { "msr45", 1325, {0, {0}}, 0, 0 },
1017   { "msr46", 1326, {0, {0}}, 0, 0 },
1018   { "msr47", 1327, {0, {0}}, 0, 0 },
1019   { "msr48", 1328, {0, {0}}, 0, 0 },
1020   { "msr49", 1329, {0, {0}}, 0, 0 },
1021   { "msr50", 1330, {0, {0}}, 0, 0 },
1022   { "msr51", 1331, {0, {0}}, 0, 0 },
1023   { "msr52", 1332, {0, {0}}, 0, 0 },
1024   { "msr53", 1333, {0, {0}}, 0, 0 },
1025   { "msr54", 1334, {0, {0}}, 0, 0 },
1026   { "msr55", 1335, {0, {0}}, 0, 0 },
1027   { "msr56", 1336, {0, {0}}, 0, 0 },
1028   { "msr57", 1337, {0, {0}}, 0, 0 },
1029   { "msr58", 1338, {0, {0}}, 0, 0 },
1030   { "msr59", 1339, {0, {0}}, 0, 0 },
1031   { "msr60", 1340, {0, {0}}, 0, 0 },
1032   { "msr61", 1341, {0, {0}}, 0, 0 },
1033   { "msr62", 1342, {0, {0}}, 0, 0 },
1034   { "msr63", 1343, {0, {0}}, 0, 0 },
1035   { "mqop0", 1344, {0, {0}}, 0, 0 },
1036   { "mqop1", 1346, {0, {0}}, 0, 0 },
1037   { "mqop2", 1348, {0, {0}}, 0, 0 },
1038   { "mqop3", 1350, {0, {0}}, 0, 0 },
1039   { "mqop4", 1352, {0, {0}}, 0, 0 },
1040   { "mqop5", 1354, {0, {0}}, 0, 0 },
1041   { "mqop6", 1356, {0, {0}}, 0, 0 },
1042   { "mqop7", 1358, {0, {0}}, 0, 0 },
1043   { "mqop8", 1360, {0, {0}}, 0, 0 },
1044   { "mqop9", 1362, {0, {0}}, 0, 0 },
1045   { "mqop10", 1364, {0, {0}}, 0, 0 },
1046   { "mqop11", 1366, {0, {0}}, 0, 0 },
1047   { "mqop12", 1368, {0, {0}}, 0, 0 },
1048   { "mqop13", 1370, {0, {0}}, 0, 0 },
1049   { "mqop14", 1372, {0, {0}}, 0, 0 },
1050   { "mqop15", 1374, {0, {0}}, 0, 0 },
1051   { "mqop16", 1376, {0, {0}}, 0, 0 },
1052   { "mqop17", 1378, {0, {0}}, 0, 0 },
1053   { "mqop18", 1380, {0, {0}}, 0, 0 },
1054   { "mqop19", 1382, {0, {0}}, 0, 0 },
1055   { "mqop20", 1384, {0, {0}}, 0, 0 },
1056   { "mqop21", 1386, {0, {0}}, 0, 0 },
1057   { "mqop22", 1388, {0, {0}}, 0, 0 },
1058   { "mqop23", 1390, {0, {0}}, 0, 0 },
1059   { "mqop24", 1392, {0, {0}}, 0, 0 },
1060   { "mqop25", 1394, {0, {0}}, 0, 0 },
1061   { "mqop26", 1396, {0, {0}}, 0, 0 },
1062   { "mqop27", 1398, {0, {0}}, 0, 0 },
1063   { "mqop28", 1400, {0, {0}}, 0, 0 },
1064   { "mqop29", 1402, {0, {0}}, 0, 0 },
1065   { "mqop30", 1404, {0, {0}}, 0, 0 },
1066   { "mqop31", 1406, {0, {0}}, 0, 0 },
1067   { "mqst0", 1345, {0, {0}}, 0, 0 },
1068   { "mqst1", 1347, {0, {0}}, 0, 0 },
1069   { "mqst2", 1349, {0, {0}}, 0, 0 },
1070   { "mqst3", 1351, {0, {0}}, 0, 0 },
1071   { "mqst4", 1353, {0, {0}}, 0, 0 },
1072   { "mqst5", 1355, {0, {0}}, 0, 0 },
1073   { "mqst6", 1357, {0, {0}}, 0, 0 },
1074   { "mqst7", 1359, {0, {0}}, 0, 0 },
1075   { "mqst8", 1361, {0, {0}}, 0, 0 },
1076   { "mqst9", 1363, {0, {0}}, 0, 0 },
1077   { "mqst10", 1365, {0, {0}}, 0, 0 },
1078   { "mqst11", 1367, {0, {0}}, 0, 0 },
1079   { "mqst12", 1369, {0, {0}}, 0, 0 },
1080   { "mqst13", 1371, {0, {0}}, 0, 0 },
1081   { "mqst14", 1373, {0, {0}}, 0, 0 },
1082   { "mqst15", 1375, {0, {0}}, 0, 0 },
1083   { "mqst16", 1377, {0, {0}}, 0, 0 },
1084   { "mqst17", 1379, {0, {0}}, 0, 0 },
1085   { "mqst18", 1381, {0, {0}}, 0, 0 },
1086   { "mqst19", 1383, {0, {0}}, 0, 0 },
1087   { "mqst20", 1385, {0, {0}}, 0, 0 },
1088   { "mqst21", 1387, {0, {0}}, 0, 0 },
1089   { "mqst22", 1389, {0, {0}}, 0, 0 },
1090   { "mqst23", 1391, {0, {0}}, 0, 0 },
1091   { "mqst24", 1393, {0, {0}}, 0, 0 },
1092   { "mqst25", 1395, {0, {0}}, 0, 0 },
1093   { "mqst26", 1397, {0, {0}}, 0, 0 },
1094   { "mqst27", 1399, {0, {0}}, 0, 0 },
1095   { "mqst28", 1401, {0, {0}}, 0, 0 },
1096   { "mqst29", 1403, {0, {0}}, 0, 0 },
1097   { "mqst30", 1405, {0, {0}}, 0, 0 },
1098   { "mqst31", 1407, {0, {0}}, 0, 0 },
1099   { "ear0", 1536, {0, {0}}, 0, 0 },
1100   { "ear1", 1537, {0, {0}}, 0, 0 },
1101   { "ear2", 1538, {0, {0}}, 0, 0 },
1102   { "ear3", 1539, {0, {0}}, 0, 0 },
1103   { "ear4", 1540, {0, {0}}, 0, 0 },
1104   { "ear5", 1541, {0, {0}}, 0, 0 },
1105   { "ear6", 1542, {0, {0}}, 0, 0 },
1106   { "ear7", 1543, {0, {0}}, 0, 0 },
1107   { "ear8", 1544, {0, {0}}, 0, 0 },
1108   { "ear9", 1545, {0, {0}}, 0, 0 },
1109   { "ear10", 1546, {0, {0}}, 0, 0 },
1110   { "ear11", 1547, {0, {0}}, 0, 0 },
1111   { "ear12", 1548, {0, {0}}, 0, 0 },
1112   { "ear13", 1549, {0, {0}}, 0, 0 },
1113   { "ear14", 1550, {0, {0}}, 0, 0 },
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1119   { "ear20", 1556, {0, {0}}, 0, 0 },
1120   { "ear21", 1557, {0, {0}}, 0, 0 },
1121   { "ear22", 1558, {0, {0}}, 0, 0 },
1122   { "ear23", 1559, {0, {0}}, 0, 0 },
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1124   { "ear25", 1561, {0, {0}}, 0, 0 },
1125   { "ear26", 1562, {0, {0}}, 0, 0 },
1126   { "ear27", 1563, {0, {0}}, 0, 0 },
1127   { "ear28", 1564, {0, {0}}, 0, 0 },
1128   { "ear29", 1565, {0, {0}}, 0, 0 },
1129   { "ear30", 1566, {0, {0}}, 0, 0 },
1130   { "ear31", 1567, {0, {0}}, 0, 0 },
1131   { "ear32", 1568, {0, {0}}, 0, 0 },
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1162   { "ear63", 1599, {0, {0}}, 0, 0 },
1163   { "edr0", 1600, {0, {0}}, 0, 0 },
1164   { "edr1", 1601, {0, {0}}, 0, 0 },
1165   { "edr2", 1602, {0, {0}}, 0, 0 },
1166   { "edr3", 1603, {0, {0}}, 0, 0 },
1167   { "edr4", 1604, {0, {0}}, 0, 0 },
1168   { "edr5", 1605, {0, {0}}, 0, 0 },
1169   { "edr6", 1606, {0, {0}}, 0, 0 },
1170   { "edr7", 1607, {0, {0}}, 0, 0 },
1171   { "edr8", 1608, {0, {0}}, 0, 0 },
1172   { "edr9", 1609, {0, {0}}, 0, 0 },
1173   { "edr10", 1610, {0, {0}}, 0, 0 },
1174   { "edr11", 1611, {0, {0}}, 0, 0 },
1175   { "edr12", 1612, {0, {0}}, 0, 0 },
1176   { "edr13", 1613, {0, {0}}, 0, 0 },
1177   { "edr14", 1614, {0, {0}}, 0, 0 },
1178   { "edr15", 1615, {0, {0}}, 0, 0 },
1179   { "edr16", 1616, {0, {0}}, 0, 0 },
1180   { "edr17", 1617, {0, {0}}, 0, 0 },
1181   { "edr18", 1618, {0, {0}}, 0, 0 },
1182   { "edr19", 1619, {0, {0}}, 0, 0 },
1183   { "edr20", 1620, {0, {0}}, 0, 0 },
1184   { "edr21", 1621, {0, {0}}, 0, 0 },
1185   { "edr22", 1622, {0, {0}}, 0, 0 },
1186   { "edr23", 1623, {0, {0}}, 0, 0 },
1187   { "edr24", 1624, {0, {0}}, 0, 0 },
1188   { "edr25", 1625, {0, {0}}, 0, 0 },
1189   { "edr26", 1626, {0, {0}}, 0, 0 },
1190   { "edr27", 1627, {0, {0}}, 0, 0 },
1191   { "edr28", 1628, {0, {0}}, 0, 0 },
1192   { "edr29", 1629, {0, {0}}, 0, 0 },
1193   { "edr30", 1630, {0, {0}}, 0, 0 },
1194   { "edr31", 1631, {0, {0}}, 0, 0 },
1195   { "edr32", 1632, {0, {0}}, 0, 0 },
1196   { "edr33", 1636, {0, {0}}, 0, 0 },
1197   { "edr34", 1634, {0, {0}}, 0, 0 },
1198   { "edr35", 1635, {0, {0}}, 0, 0 },
1199   { "edr36", 1636, {0, {0}}, 0, 0 },
1200   { "edr37", 1637, {0, {0}}, 0, 0 },
1201   { "edr38", 1638, {0, {0}}, 0, 0 },
1202   { "edr39", 1639, {0, {0}}, 0, 0 },
1203   { "edr40", 1640, {0, {0}}, 0, 0 },
1204   { "edr41", 1641, {0, {0}}, 0, 0 },
1205   { "edr42", 1642, {0, {0}}, 0, 0 },
1206   { "edr43", 1643, {0, {0}}, 0, 0 },
1207   { "edr44", 1644, {0, {0}}, 0, 0 },
1208   { "edr45", 1645, {0, {0}}, 0, 0 },
1209   { "edr46", 1646, {0, {0}}, 0, 0 },
1210   { "edr47", 1647, {0, {0}}, 0, 0 },
1211   { "edr48", 1648, {0, {0}}, 0, 0 },
1212   { "edr49", 1649, {0, {0}}, 0, 0 },
1213   { "edr50", 1650, {0, {0}}, 0, 0 },
1214   { "edr51", 1651, {0, {0}}, 0, 0 },
1215   { "edr52", 1652, {0, {0}}, 0, 0 },
1216   { "edr53", 1653, {0, {0}}, 0, 0 },
1217   { "edr54", 1654, {0, {0}}, 0, 0 },
1218   { "edr55", 1655, {0, {0}}, 0, 0 },
1219   { "edr56", 1656, {0, {0}}, 0, 0 },
1220   { "edr57", 1657, {0, {0}}, 0, 0 },
1221   { "edr58", 1658, {0, {0}}, 0, 0 },
1222   { "edr59", 1659, {0, {0}}, 0, 0 },
1223   { "edr60", 1660, {0, {0}}, 0, 0 },
1224   { "edr61", 1661, {0, {0}}, 0, 0 },
1225   { "edr62", 1662, {0, {0}}, 0, 0 },
1226   { "edr63", 1663, {0, {0}}, 0, 0 },
1227   { "iamlr0", 1664, {0, {0}}, 0, 0 },
1228   { "iamlr1", 1665, {0, {0}}, 0, 0 },
1229   { "iamlr2", 1666, {0, {0}}, 0, 0 },
1230   { "iamlr3", 1667, {0, {0}}, 0, 0 },
1231   { "iamlr4", 1668, {0, {0}}, 0, 0 },
1232   { "iamlr5", 1669, {0, {0}}, 0, 0 },
1233   { "iamlr6", 1670, {0, {0}}, 0, 0 },
1234   { "iamlr7", 1671, {0, {0}}, 0, 0 },
1235   { "iamlr8", 1672, {0, {0}}, 0, 0 },
1236   { "iamlr9", 1673, {0, {0}}, 0, 0 },
1237   { "iamlr10", 1674, {0, {0}}, 0, 0 },
1238   { "iamlr11", 1675, {0, {0}}, 0, 0 },
1239   { "iamlr12", 1676, {0, {0}}, 0, 0 },
1240   { "iamlr13", 1677, {0, {0}}, 0, 0 },
1241   { "iamlr14", 1678, {0, {0}}, 0, 0 },
1242   { "iamlr15", 1679, {0, {0}}, 0, 0 },
1243   { "iamlr16", 1680, {0, {0}}, 0, 0 },
1244   { "iamlr17", 1681, {0, {0}}, 0, 0 },
1245   { "iamlr18", 1682, {0, {0}}, 0, 0 },
1246   { "iamlr19", 1683, {0, {0}}, 0, 0 },
1247   { "iamlr20", 1684, {0, {0}}, 0, 0 },
1248   { "iamlr21", 1685, {0, {0}}, 0, 0 },
1249   { "iamlr22", 1686, {0, {0}}, 0, 0 },
1250   { "iamlr23", 1687, {0, {0}}, 0, 0 },
1251   { "iamlr24", 1688, {0, {0}}, 0, 0 },
1252   { "iamlr25", 1689, {0, {0}}, 0, 0 },
1253   { "iamlr26", 1690, {0, {0}}, 0, 0 },
1254   { "iamlr27", 1691, {0, {0}}, 0, 0 },
1255   { "iamlr28", 1692, {0, {0}}, 0, 0 },
1256   { "iamlr29", 1693, {0, {0}}, 0, 0 },
1257   { "iamlr30", 1694, {0, {0}}, 0, 0 },
1258   { "iamlr31", 1695, {0, {0}}, 0, 0 },
1259   { "iamlr32", 1696, {0, {0}}, 0, 0 },
1260   { "iamlr33", 1697, {0, {0}}, 0, 0 },
1261   { "iamlr34", 1698, {0, {0}}, 0, 0 },
1262   { "iamlr35", 1699, {0, {0}}, 0, 0 },
1263   { "iamlr36", 1700, {0, {0}}, 0, 0 },
1264   { "iamlr37", 1701, {0, {0}}, 0, 0 },
1265   { "iamlr38", 1702, {0, {0}}, 0, 0 },
1266   { "iamlr39", 1703, {0, {0}}, 0, 0 },
1267   { "iamlr40", 1704, {0, {0}}, 0, 0 },
1268   { "iamlr41", 1705, {0, {0}}, 0, 0 },
1269   { "iamlr42", 1706, {0, {0}}, 0, 0 },
1270   { "iamlr43", 1707, {0, {0}}, 0, 0 },
1271   { "iamlr44", 1708, {0, {0}}, 0, 0 },
1272   { "iamlr45", 1709, {0, {0}}, 0, 0 },
1273   { "iamlr46", 1710, {0, {0}}, 0, 0 },
1274   { "iamlr47", 1711, {0, {0}}, 0, 0 },
1275   { "iamlr48", 1712, {0, {0}}, 0, 0 },
1276   { "iamlr49", 1713, {0, {0}}, 0, 0 },
1277   { "iamlr50", 1714, {0, {0}}, 0, 0 },
1278   { "iamlr51", 1715, {0, {0}}, 0, 0 },
1279   { "iamlr52", 1716, {0, {0}}, 0, 0 },
1280   { "iamlr53", 1717, {0, {0}}, 0, 0 },
1281   { "iamlr54", 1718, {0, {0}}, 0, 0 },
1282   { "iamlr55", 1719, {0, {0}}, 0, 0 },
1283   { "iamlr56", 1720, {0, {0}}, 0, 0 },
1284   { "iamlr57", 1721, {0, {0}}, 0, 0 },
1285   { "iamlr58", 1722, {0, {0}}, 0, 0 },
1286   { "iamlr59", 1723, {0, {0}}, 0, 0 },
1287   { "iamlr60", 1724, {0, {0}}, 0, 0 },
1288   { "iamlr61", 1725, {0, {0}}, 0, 0 },
1289   { "iamlr62", 1726, {0, {0}}, 0, 0 },
1290   { "iamlr63", 1727, {0, {0}}, 0, 0 },
1291   { "iampr0", 1728, {0, {0}}, 0, 0 },
1292   { "iampr1", 1729, {0, {0}}, 0, 0 },
1293   { "iampr2", 1730, {0, {0}}, 0, 0 },
1294   { "iampr3", 1731, {0, {0}}, 0, 0 },
1295   { "iampr4", 1732, {0, {0}}, 0, 0 },
1296   { "iampr5", 1733, {0, {0}}, 0, 0 },
1297   { "iampr6", 1734, {0, {0}}, 0, 0 },
1298   { "iampr7", 1735, {0, {0}}, 0, 0 },
1299   { "iampr8", 1736, {0, {0}}, 0, 0 },
1300   { "iampr9", 1737, {0, {0}}, 0, 0 },
1301   { "iampr10", 1738, {0, {0}}, 0, 0 },
1302   { "iampr11", 1739, {0, {0}}, 0, 0 },
1303   { "iampr12", 1740, {0, {0}}, 0, 0 },
1304   { "iampr13", 1741, {0, {0}}, 0, 0 },
1305   { "iampr14", 1742, {0, {0}}, 0, 0 },
1306   { "iampr15", 1743, {0, {0}}, 0, 0 },
1307   { "iampr16", 1744, {0, {0}}, 0, 0 },
1308   { "iampr17", 1745, {0, {0}}, 0, 0 },
1309   { "iampr18", 1746, {0, {0}}, 0, 0 },
1310   { "iampr19", 1747, {0, {0}}, 0, 0 },
1311   { "iampr20", 1748, {0, {0}}, 0, 0 },
1312   { "iampr21", 1749, {0, {0}}, 0, 0 },
1313   { "iampr22", 1750, {0, {0}}, 0, 0 },
1314   { "iampr23", 1751, {0, {0}}, 0, 0 },
1315   { "iampr24", 1752, {0, {0}}, 0, 0 },
1316   { "iampr25", 1753, {0, {0}}, 0, 0 },
1317   { "iampr26", 1754, {0, {0}}, 0, 0 },
1318   { "iampr27", 1755, {0, {0}}, 0, 0 },
1319   { "iampr28", 1756, {0, {0}}, 0, 0 },
1320   { "iampr29", 1757, {0, {0}}, 0, 0 },
1321   { "iampr30", 1758, {0, {0}}, 0, 0 },
1322   { "iampr31", 1759, {0, {0}}, 0, 0 },
1323   { "iampr32", 1760, {0, {0}}, 0, 0 },
1324   { "iampr33", 1761, {0, {0}}, 0, 0 },
1325   { "iampr34", 1762, {0, {0}}, 0, 0 },
1326   { "iampr35", 1763, {0, {0}}, 0, 0 },
1327   { "iampr36", 1764, {0, {0}}, 0, 0 },
1328   { "iampr37", 1765, {0, {0}}, 0, 0 },
1329   { "iampr38", 1766, {0, {0}}, 0, 0 },
1330   { "iampr39", 1767, {0, {0}}, 0, 0 },
1331   { "iampr40", 1768, {0, {0}}, 0, 0 },
1332   { "iampr41", 1769, {0, {0}}, 0, 0 },
1333   { "iampr42", 1770, {0, {0}}, 0, 0 },
1334   { "iampr43", 1771, {0, {0}}, 0, 0 },
1335   { "iampr44", 1772, {0, {0}}, 0, 0 },
1336   { "iampr45", 1773, {0, {0}}, 0, 0 },
1337   { "iampr46", 1774, {0, {0}}, 0, 0 },
1338   { "iampr47", 1775, {0, {0}}, 0, 0 },
1339   { "iampr48", 1776, {0, {0}}, 0, 0 },
1340   { "iampr49", 1777, {0, {0}}, 0, 0 },
1341   { "iampr50", 1778, {0, {0}}, 0, 0 },
1342   { "iampr51", 1779, {0, {0}}, 0, 0 },
1343   { "iampr52", 1780, {0, {0}}, 0, 0 },
1344   { "iampr53", 1781, {0, {0}}, 0, 0 },
1345   { "iampr54", 1782, {0, {0}}, 0, 0 },
1346   { "iampr55", 1783, {0, {0}}, 0, 0 },
1347   { "iampr56", 1784, {0, {0}}, 0, 0 },
1348   { "iampr57", 1785, {0, {0}}, 0, 0 },
1349   { "iampr58", 1786, {0, {0}}, 0, 0 },
1350   { "iampr59", 1787, {0, {0}}, 0, 0 },
1351   { "iampr60", 1788, {0, {0}}, 0, 0 },
1352   { "iampr61", 1789, {0, {0}}, 0, 0 },
1353   { "iampr62", 1790, {0, {0}}, 0, 0 },
1354   { "iampr63", 1791, {0, {0}}, 0, 0 },
1355   { "damlr0", 1792, {0, {0}}, 0, 0 },
1356   { "damlr1", 1793, {0, {0}}, 0, 0 },
1357   { "damlr2", 1794, {0, {0}}, 0, 0 },
1358   { "damlr3", 1795, {0, {0}}, 0, 0 },
1359   { "damlr4", 1796, {0, {0}}, 0, 0 },
1360   { "damlr5", 1797, {0, {0}}, 0, 0 },
1361   { "damlr6", 1798, {0, {0}}, 0, 0 },
1362   { "damlr7", 1799, {0, {0}}, 0, 0 },
1363   { "damlr8", 1800, {0, {0}}, 0, 0 },
1364   { "damlr9", 1801, {0, {0}}, 0, 0 },
1365   { "damlr10", 1802, {0, {0}}, 0, 0 },
1366   { "damlr11", 1803, {0, {0}}, 0, 0 },
1367   { "damlr12", 1804, {0, {0}}, 0, 0 },
1368   { "damlr13", 1805, {0, {0}}, 0, 0 },
1369   { "damlr14", 1806, {0, {0}}, 0, 0 },
1370   { "damlr15", 1807, {0, {0}}, 0, 0 },
1371   { "damlr16", 1808, {0, {0}}, 0, 0 },
1372   { "damlr17", 1809, {0, {0}}, 0, 0 },
1373   { "damlr18", 1810, {0, {0}}, 0, 0 },
1374   { "damlr19", 1811, {0, {0}}, 0, 0 },
1375   { "damlr20", 1812, {0, {0}}, 0, 0 },
1376   { "damlr21", 1813, {0, {0}}, 0, 0 },
1377   { "damlr22", 1814, {0, {0}}, 0, 0 },
1378   { "damlr23", 1815, {0, {0}}, 0, 0 },
1379   { "damlr24", 1816, {0, {0}}, 0, 0 },
1380   { "damlr25", 1817, {0, {0}}, 0, 0 },
1381   { "damlr26", 1818, {0, {0}}, 0, 0 },
1382   { "damlr27", 1819, {0, {0}}, 0, 0 },
1383   { "damlr28", 1820, {0, {0}}, 0, 0 },
1384   { "damlr29", 1821, {0, {0}}, 0, 0 },
1385   { "damlr30", 1822, {0, {0}}, 0, 0 },
1386   { "damlr31", 1823, {0, {0}}, 0, 0 },
1387   { "damlr32", 1824, {0, {0}}, 0, 0 },
1388   { "damlr33", 1825, {0, {0}}, 0, 0 },
1389   { "damlr34", 1826, {0, {0}}, 0, 0 },
1390   { "damlr35", 1827, {0, {0}}, 0, 0 },
1391   { "damlr36", 1828, {0, {0}}, 0, 0 },
1392   { "damlr37", 1829, {0, {0}}, 0, 0 },
1393   { "damlr38", 1830, {0, {0}}, 0, 0 },
1394   { "damlr39", 1831, {0, {0}}, 0, 0 },
1395   { "damlr40", 1832, {0, {0}}, 0, 0 },
1396   { "damlr41", 1833, {0, {0}}, 0, 0 },
1397   { "damlr42", 1834, {0, {0}}, 0, 0 },
1398   { "damlr43", 1835, {0, {0}}, 0, 0 },
1399   { "damlr44", 1836, {0, {0}}, 0, 0 },
1400   { "damlr45", 1837, {0, {0}}, 0, 0 },
1401   { "damlr46", 1838, {0, {0}}, 0, 0 },
1402   { "damlr47", 1839, {0, {0}}, 0, 0 },
1403   { "damlr48", 1840, {0, {0}}, 0, 0 },
1404   { "damlr49", 1841, {0, {0}}, 0, 0 },
1405   { "damlr50", 1842, {0, {0}}, 0, 0 },
1406   { "damlr51", 1843, {0, {0}}, 0, 0 },
1407   { "damlr52", 1844, {0, {0}}, 0, 0 },
1408   { "damlr53", 1845, {0, {0}}, 0, 0 },
1409   { "damlr54", 1846, {0, {0}}, 0, 0 },
1410   { "damlr55", 1847, {0, {0}}, 0, 0 },
1411   { "damlr56", 1848, {0, {0}}, 0, 0 },
1412   { "damlr57", 1849, {0, {0}}, 0, 0 },
1413   { "damlr58", 1850, {0, {0}}, 0, 0 },
1414   { "damlr59", 1851, {0, {0}}, 0, 0 },
1415   { "damlr60", 1852, {0, {0}}, 0, 0 },
1416   { "damlr61", 1853, {0, {0}}, 0, 0 },
1417   { "damlr62", 1854, {0, {0}}, 0, 0 },
1418   { "damlr63", 1855, {0, {0}}, 0, 0 },
1419   { "dampr0", 1856, {0, {0}}, 0, 0 },
1420   { "dampr1", 1857, {0, {0}}, 0, 0 },
1421   { "dampr2", 1858, {0, {0}}, 0, 0 },
1422   { "dampr3", 1859, {0, {0}}, 0, 0 },
1423   { "dampr4", 1860, {0, {0}}, 0, 0 },
1424   { "dampr5", 1861, {0, {0}}, 0, 0 },
1425   { "dampr6", 1862, {0, {0}}, 0, 0 },
1426   { "dampr7", 1863, {0, {0}}, 0, 0 },
1427   { "dampr8", 1864, {0, {0}}, 0, 0 },
1428   { "dampr9", 1865, {0, {0}}, 0, 0 },
1429   { "dampr10", 1866, {0, {0}}, 0, 0 },
1430   { "dampr11", 1867, {0, {0}}, 0, 0 },
1431   { "dampr12", 1868, {0, {0}}, 0, 0 },
1432   { "dampr13", 1869, {0, {0}}, 0, 0 },
1433   { "dampr14", 1870, {0, {0}}, 0, 0 },
1434   { "dampr15", 1871, {0, {0}}, 0, 0 },
1435   { "dampr16", 1872, {0, {0}}, 0, 0 },
1436   { "dampr17", 1873, {0, {0}}, 0, 0 },
1437   { "dampr18", 1874, {0, {0}}, 0, 0 },
1438   { "dampr19", 1875, {0, {0}}, 0, 0 },
1439   { "dampr20", 1876, {0, {0}}, 0, 0 },
1440   { "dampr21", 1877, {0, {0}}, 0, 0 },
1441   { "dampr22", 1878, {0, {0}}, 0, 0 },
1442   { "dampr23", 1879, {0, {0}}, 0, 0 },
1443   { "dampr24", 1880, {0, {0}}, 0, 0 },
1444   { "dampr25", 1881, {0, {0}}, 0, 0 },
1445   { "dampr26", 1882, {0, {0}}, 0, 0 },
1446   { "dampr27", 1883, {0, {0}}, 0, 0 },
1447   { "dampr28", 1884, {0, {0}}, 0, 0 },
1448   { "dampr29", 1885, {0, {0}}, 0, 0 },
1449   { "dampr30", 1886, {0, {0}}, 0, 0 },
1450   { "dampr31", 1887, {0, {0}}, 0, 0 },
1451   { "dampr32", 1888, {0, {0}}, 0, 0 },
1452   { "dampr33", 1889, {0, {0}}, 0, 0 },
1453   { "dampr34", 1890, {0, {0}}, 0, 0 },
1454   { "dampr35", 1891, {0, {0}}, 0, 0 },
1455   { "dampr36", 1892, {0, {0}}, 0, 0 },
1456   { "dampr37", 1893, {0, {0}}, 0, 0 },
1457   { "dampr38", 1894, {0, {0}}, 0, 0 },
1458   { "dampr39", 1895, {0, {0}}, 0, 0 },
1459   { "dampr40", 1896, {0, {0}}, 0, 0 },
1460   { "dampr41", 1897, {0, {0}}, 0, 0 },
1461   { "dampr42", 1898, {0, {0}}, 0, 0 },
1462   { "dampr43", 1899, {0, {0}}, 0, 0 },
1463   { "dampr44", 1900, {0, {0}}, 0, 0 },
1464   { "dampr45", 1901, {0, {0}}, 0, 0 },
1465   { "dampr46", 1902, {0, {0}}, 0, 0 },
1466   { "dampr47", 1903, {0, {0}}, 0, 0 },
1467   { "dampr48", 1904, {0, {0}}, 0, 0 },
1468   { "dampr49", 1905, {0, {0}}, 0, 0 },
1469   { "dampr50", 1906, {0, {0}}, 0, 0 },
1470   { "dampr51", 1907, {0, {0}}, 0, 0 },
1471   { "dampr52", 1908, {0, {0}}, 0, 0 },
1472   { "dampr53", 1909, {0, {0}}, 0, 0 },
1473   { "dampr54", 1910, {0, {0}}, 0, 0 },
1474   { "dampr55", 1911, {0, {0}}, 0, 0 },
1475   { "dampr56", 1912, {0, {0}}, 0, 0 },
1476   { "dampr57", 1913, {0, {0}}, 0, 0 },
1477   { "dampr58", 1914, {0, {0}}, 0, 0 },
1478   { "dampr59", 1915, {0, {0}}, 0, 0 },
1479   { "dampr60", 1916, {0, {0}}, 0, 0 },
1480   { "dampr61", 1917, {0, {0}}, 0, 0 },
1481   { "dampr62", 1918, {0, {0}}, 0, 0 },
1482   { "dampr63", 1919, {0, {0}}, 0, 0 },
1483   { "amcr", 1920, {0, {0}}, 0, 0 },
1484   { "stbar", 1921, {0, {0}}, 0, 0 },
1485   { "mmcr", 1922, {0, {0}}, 0, 0 },
1486   { "iamvr1", 1925, {0, {0}}, 0, 0 },
1487   { "damvr1", 1927, {0, {0}}, 0, 0 },
1488   { "cxnr", 1936, {0, {0}}, 0, 0 },
1489   { "ttbr", 1937, {0, {0}}, 0, 0 },
1490   { "tplr", 1938, {0, {0}}, 0, 0 },
1491   { "tppr", 1939, {0, {0}}, 0, 0 },
1492   { "tpxr", 1940, {0, {0}}, 0, 0 },
1493   { "timerh", 1952, {0, {0}}, 0, 0 },
1494   { "timerl", 1953, {0, {0}}, 0, 0 },
1495   { "timerd", 1954, {0, {0}}, 0, 0 },
1496   { "dcr", 2048, {0, {0}}, 0, 0 },
1497   { "brr", 2049, {0, {0}}, 0, 0 },
1498   { "nmar", 2050, {0, {0}}, 0, 0 },
1499   { "btbr", 2051, {0, {0}}, 0, 0 },
1500   { "ibar0", 2052, {0, {0}}, 0, 0 },
1501   { "ibar1", 2053, {0, {0}}, 0, 0 },
1502   { "ibar2", 2054, {0, {0}}, 0, 0 },
1503   { "ibar3", 2055, {0, {0}}, 0, 0 },
1504   { "dbar0", 2056, {0, {0}}, 0, 0 },
1505   { "dbar1", 2057, {0, {0}}, 0, 0 },
1506   { "dbar2", 2058, {0, {0}}, 0, 0 },
1507   { "dbar3", 2059, {0, {0}}, 0, 0 },
1508   { "dbdr00", 2060, {0, {0}}, 0, 0 },
1509   { "dbdr01", 2061, {0, {0}}, 0, 0 },
1510   { "dbdr02", 2062, {0, {0}}, 0, 0 },
1511   { "dbdr03", 2063, {0, {0}}, 0, 0 },
1512   { "dbdr10", 2064, {0, {0}}, 0, 0 },
1513   { "dbdr11", 2065, {0, {0}}, 0, 0 },
1514   { "dbdr12", 2066, {0, {0}}, 0, 0 },
1515   { "dbdr13", 2067, {0, {0}}, 0, 0 },
1516   { "dbdr20", 2068, {0, {0}}, 0, 0 },
1517   { "dbdr21", 2069, {0, {0}}, 0, 0 },
1518   { "dbdr22", 2070, {0, {0}}, 0, 0 },
1519   { "dbdr23", 2071, {0, {0}}, 0, 0 },
1520   { "dbdr30", 2072, {0, {0}}, 0, 0 },
1521   { "dbdr31", 2073, {0, {0}}, 0, 0 },
1522   { "dbdr32", 2074, {0, {0}}, 0, 0 },
1523   { "dbdr33", 2075, {0, {0}}, 0, 0 },
1524   { "dbmr00", 2076, {0, {0}}, 0, 0 },
1525   { "dbmr01", 2077, {0, {0}}, 0, 0 },
1526   { "dbmr02", 2078, {0, {0}}, 0, 0 },
1527   { "dbmr03", 2079, {0, {0}}, 0, 0 },
1528   { "dbmr10", 2080, {0, {0}}, 0, 0 },
1529   { "dbmr11", 2081, {0, {0}}, 0, 0 },
1530   { "dbmr12", 2082, {0, {0}}, 0, 0 },
1531   { "dbmr13", 2083, {0, {0}}, 0, 0 },
1532   { "dbmr20", 2084, {0, {0}}, 0, 0 },
1533   { "dbmr21", 2085, {0, {0}}, 0, 0 },
1534   { "dbmr22", 2086, {0, {0}}, 0, 0 },
1535   { "dbmr23", 2087, {0, {0}}, 0, 0 },
1536   { "dbmr30", 2088, {0, {0}}, 0, 0 },
1537   { "dbmr31", 2089, {0, {0}}, 0, 0 },
1538   { "dbmr32", 2090, {0, {0}}, 0, 0 },
1539   { "dbmr33", 2091, {0, {0}}, 0, 0 },
1540   { "cpcfr", 2092, {0, {0}}, 0, 0 },
1541   { "cpcr", 2093, {0, {0}}, 0, 0 },
1542   { "cpsr", 2094, {0, {0}}, 0, 0 },
1543   { "cpesr0", 2096, {0, {0}}, 0, 0 },
1544   { "cpesr1", 2097, {0, {0}}, 0, 0 },
1545   { "cpemr0", 2098, {0, {0}}, 0, 0 },
1546   { "cpemr1", 2099, {0, {0}}, 0, 0 },
1547   { "ihsr8", 3848, {0, {0}}, 0, 0 }
1548 };
1549
1550 CGEN_KEYWORD frv_cgen_opval_spr_names =
1551 {
1552   & frv_cgen_opval_spr_names_entries[0],
1553   1022,
1554   0, 0, 0, 0, ""
1555 };
1556
1557 static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] =
1558 {
1559   { "accg0", 0, {0, {0}}, 0, 0 },
1560   { "accg1", 1, {0, {0}}, 0, 0 },
1561   { "accg2", 2, {0, {0}}, 0, 0 },
1562   { "accg3", 3, {0, {0}}, 0, 0 },
1563   { "accg4", 4, {0, {0}}, 0, 0 },
1564   { "accg5", 5, {0, {0}}, 0, 0 },
1565   { "accg6", 6, {0, {0}}, 0, 0 },
1566   { "accg7", 7, {0, {0}}, 0, 0 },
1567   { "accg8", 8, {0, {0}}, 0, 0 },
1568   { "accg9", 9, {0, {0}}, 0, 0 },
1569   { "accg10", 10, {0, {0}}, 0, 0 },
1570   { "accg11", 11, {0, {0}}, 0, 0 },
1571   { "accg12", 12, {0, {0}}, 0, 0 },
1572   { "accg13", 13, {0, {0}}, 0, 0 },
1573   { "accg14", 14, {0, {0}}, 0, 0 },
1574   { "accg15", 15, {0, {0}}, 0, 0 },
1575   { "accg16", 16, {0, {0}}, 0, 0 },
1576   { "accg17", 17, {0, {0}}, 0, 0 },
1577   { "accg18", 18, {0, {0}}, 0, 0 },
1578   { "accg19", 19, {0, {0}}, 0, 0 },
1579   { "accg20", 20, {0, {0}}, 0, 0 },
1580   { "accg21", 21, {0, {0}}, 0, 0 },
1581   { "accg22", 22, {0, {0}}, 0, 0 },
1582   { "accg23", 23, {0, {0}}, 0, 0 },
1583   { "accg24", 24, {0, {0}}, 0, 0 },
1584   { "accg25", 25, {0, {0}}, 0, 0 },
1585   { "accg26", 26, {0, {0}}, 0, 0 },
1586   { "accg27", 27, {0, {0}}, 0, 0 },
1587   { "accg28", 28, {0, {0}}, 0, 0 },
1588   { "accg29", 29, {0, {0}}, 0, 0 },
1589   { "accg30", 30, {0, {0}}, 0, 0 },
1590   { "accg31", 31, {0, {0}}, 0, 0 },
1591   { "accg32", 32, {0, {0}}, 0, 0 },
1592   { "accg33", 33, {0, {0}}, 0, 0 },
1593   { "accg34", 34, {0, {0}}, 0, 0 },
1594   { "accg35", 35, {0, {0}}, 0, 0 },
1595   { "accg36", 36, {0, {0}}, 0, 0 },
1596   { "accg37", 37, {0, {0}}, 0, 0 },
1597   { "accg38", 38, {0, {0}}, 0, 0 },
1598   { "accg39", 39, {0, {0}}, 0, 0 },
1599   { "accg40", 40, {0, {0}}, 0, 0 },
1600   { "accg41", 41, {0, {0}}, 0, 0 },
1601   { "accg42", 42, {0, {0}}, 0, 0 },
1602   { "accg43", 43, {0, {0}}, 0, 0 },
1603   { "accg44", 44, {0, {0}}, 0, 0 },
1604   { "accg45", 45, {0, {0}}, 0, 0 },
1605   { "accg46", 46, {0, {0}}, 0, 0 },
1606   { "accg47", 47, {0, {0}}, 0, 0 },
1607   { "accg48", 48, {0, {0}}, 0, 0 },
1608   { "accg49", 49, {0, {0}}, 0, 0 },
1609   { "accg50", 50, {0, {0}}, 0, 0 },
1610   { "accg51", 51, {0, {0}}, 0, 0 },
1611   { "accg52", 52, {0, {0}}, 0, 0 },
1612   { "accg53", 53, {0, {0}}, 0, 0 },
1613   { "accg54", 54, {0, {0}}, 0, 0 },
1614   { "accg55", 55, {0, {0}}, 0, 0 },
1615   { "accg56", 56, {0, {0}}, 0, 0 },
1616   { "accg57", 57, {0, {0}}, 0, 0 },
1617   { "accg58", 58, {0, {0}}, 0, 0 },
1618   { "accg59", 59, {0, {0}}, 0, 0 },
1619   { "accg60", 60, {0, {0}}, 0, 0 },
1620   { "accg61", 61, {0, {0}}, 0, 0 },
1621   { "accg62", 62, {0, {0}}, 0, 0 },
1622   { "accg63", 63, {0, {0}}, 0, 0 }
1623 };
1624
1625 CGEN_KEYWORD frv_cgen_opval_accg_names =
1626 {
1627   & frv_cgen_opval_accg_names_entries[0],
1628   64,
1629   0, 0, 0, 0, ""
1630 };
1631
1632 static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] =
1633 {
1634   { "acc0", 0, {0, {0}}, 0, 0 },
1635   { "acc1", 1, {0, {0}}, 0, 0 },
1636   { "acc2", 2, {0, {0}}, 0, 0 },
1637   { "acc3", 3, {0, {0}}, 0, 0 },
1638   { "acc4", 4, {0, {0}}, 0, 0 },
1639   { "acc5", 5, {0, {0}}, 0, 0 },
1640   { "acc6", 6, {0, {0}}, 0, 0 },
1641   { "acc7", 7, {0, {0}}, 0, 0 },
1642   { "acc8", 8, {0, {0}}, 0, 0 },
1643   { "acc9", 9, {0, {0}}, 0, 0 },
1644   { "acc10", 10, {0, {0}}, 0, 0 },
1645   { "acc11", 11, {0, {0}}, 0, 0 },
1646   { "acc12", 12, {0, {0}}, 0, 0 },
1647   { "acc13", 13, {0, {0}}, 0, 0 },
1648   { "acc14", 14, {0, {0}}, 0, 0 },
1649   { "acc15", 15, {0, {0}}, 0, 0 },
1650   { "acc16", 16, {0, {0}}, 0, 0 },
1651   { "acc17", 17, {0, {0}}, 0, 0 },
1652   { "acc18", 18, {0, {0}}, 0, 0 },
1653   { "acc19", 19, {0, {0}}, 0, 0 },
1654   { "acc20", 20, {0, {0}}, 0, 0 },
1655   { "acc21", 21, {0, {0}}, 0, 0 },
1656   { "acc22", 22, {0, {0}}, 0, 0 },
1657   { "acc23", 23, {0, {0}}, 0, 0 },
1658   { "acc24", 24, {0, {0}}, 0, 0 },
1659   { "acc25", 25, {0, {0}}, 0, 0 },
1660   { "acc26", 26, {0, {0}}, 0, 0 },
1661   { "acc27", 27, {0, {0}}, 0, 0 },
1662   { "acc28", 28, {0, {0}}, 0, 0 },
1663   { "acc29", 29, {0, {0}}, 0, 0 },
1664   { "acc30", 30, {0, {0}}, 0, 0 },
1665   { "acc31", 31, {0, {0}}, 0, 0 },
1666   { "acc32", 32, {0, {0}}, 0, 0 },
1667   { "acc33", 33, {0, {0}}, 0, 0 },
1668   { "acc34", 34, {0, {0}}, 0, 0 },
1669   { "acc35", 35, {0, {0}}, 0, 0 },
1670   { "acc36", 36, {0, {0}}, 0, 0 },
1671   { "acc37", 37, {0, {0}}, 0, 0 },
1672   { "acc38", 38, {0, {0}}, 0, 0 },
1673   { "acc39", 39, {0, {0}}, 0, 0 },
1674   { "acc40", 40, {0, {0}}, 0, 0 },
1675   { "acc41", 41, {0, {0}}, 0, 0 },
1676   { "acc42", 42, {0, {0}}, 0, 0 },
1677   { "acc43", 43, {0, {0}}, 0, 0 },
1678   { "acc44", 44, {0, {0}}, 0, 0 },
1679   { "acc45", 45, {0, {0}}, 0, 0 },
1680   { "acc46", 46, {0, {0}}, 0, 0 },
1681   { "acc47", 47, {0, {0}}, 0, 0 },
1682   { "acc48", 48, {0, {0}}, 0, 0 },
1683   { "acc49", 49, {0, {0}}, 0, 0 },
1684   { "acc50", 50, {0, {0}}, 0, 0 },
1685   { "acc51", 51, {0, {0}}, 0, 0 },
1686   { "acc52", 52, {0, {0}}, 0, 0 },
1687   { "acc53", 53, {0, {0}}, 0, 0 },
1688   { "acc54", 54, {0, {0}}, 0, 0 },
1689   { "acc55", 55, {0, {0}}, 0, 0 },
1690   { "acc56", 56, {0, {0}}, 0, 0 },
1691   { "acc57", 57, {0, {0}}, 0, 0 },
1692   { "acc58", 58, {0, {0}}, 0, 0 },
1693   { "acc59", 59, {0, {0}}, 0, 0 },
1694   { "acc60", 60, {0, {0}}, 0, 0 },
1695   { "acc61", 61, {0, {0}}, 0, 0 },
1696   { "acc62", 62, {0, {0}}, 0, 0 },
1697   { "acc63", 63, {0, {0}}, 0, 0 }
1698 };
1699
1700 CGEN_KEYWORD frv_cgen_opval_acc_names =
1701 {
1702   & frv_cgen_opval_acc_names_entries[0],
1703   64,
1704   0, 0, 0, 0, ""
1705 };
1706
1707 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iacc0_names_entries[] =
1708 {
1709   { "iacc0", 0, {0, {0}}, 0, 0 }
1710 };
1711
1712 CGEN_KEYWORD frv_cgen_opval_iacc0_names =
1713 {
1714   & frv_cgen_opval_iacc0_names_entries[0],
1715   1,
1716   0, 0, 0, 0, ""
1717 };
1718
1719 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] =
1720 {
1721   { "icc0", 0, {0, {0}}, 0, 0 },
1722   { "icc1", 1, {0, {0}}, 0, 0 },
1723   { "icc2", 2, {0, {0}}, 0, 0 },
1724   { "icc3", 3, {0, {0}}, 0, 0 }
1725 };
1726
1727 CGEN_KEYWORD frv_cgen_opval_iccr_names =
1728 {
1729   & frv_cgen_opval_iccr_names_entries[0],
1730   4,
1731   0, 0, 0, 0, ""
1732 };
1733
1734 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] =
1735 {
1736   { "fcc0", 0, {0, {0}}, 0, 0 },
1737   { "fcc1", 1, {0, {0}}, 0, 0 },
1738   { "fcc2", 2, {0, {0}}, 0, 0 },
1739   { "fcc3", 3, {0, {0}}, 0, 0 }
1740 };
1741
1742 CGEN_KEYWORD frv_cgen_opval_fccr_names =
1743 {
1744   & frv_cgen_opval_fccr_names_entries[0],
1745   4,
1746   0, 0, 0, 0, ""
1747 };
1748
1749 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] =
1750 {
1751   { "cc0", 0, {0, {0}}, 0, 0 },
1752   { "cc1", 1, {0, {0}}, 0, 0 },
1753   { "cc2", 2, {0, {0}}, 0, 0 },
1754   { "cc3", 3, {0, {0}}, 0, 0 },
1755   { "cc4", 4, {0, {0}}, 0, 0 },
1756   { "cc5", 5, {0, {0}}, 0, 0 },
1757   { "cc6", 6, {0, {0}}, 0, 0 },
1758   { "cc7", 7, {0, {0}}, 0, 0 }
1759 };
1760
1761 CGEN_KEYWORD frv_cgen_opval_cccr_names =
1762 {
1763   & frv_cgen_opval_cccr_names_entries[0],
1764   8,
1765   0, 0, 0, 0, ""
1766 };
1767
1768 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] =
1769 {
1770   { "", 1, {0, {0}}, 0, 0 },
1771   { ".p", 0, {0, {0}}, 0, 0 },
1772   { ".P", 0, {0, {0}}, 0, 0 }
1773 };
1774
1775 CGEN_KEYWORD frv_cgen_opval_h_pack =
1776 {
1777   & frv_cgen_opval_h_pack_entries[0],
1778   3,
1779   0, 0, 0, 0, ""
1780 };
1781
1782 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] =
1783 {
1784   { "", 2, {0, {0}}, 0, 0 },
1785   { "", 0, {0, {0}}, 0, 0 },
1786   { "", 1, {0, {0}}, 0, 0 },
1787   { "", 3, {0, {0}}, 0, 0 }
1788 };
1789
1790 CGEN_KEYWORD frv_cgen_opval_h_hint_taken =
1791 {
1792   & frv_cgen_opval_h_hint_taken_entries[0],
1793   4,
1794   0, 0, 0, 0, ""
1795 };
1796
1797 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] =
1798 {
1799   { "", 0, {0, {0}}, 0, 0 },
1800   { "", 1, {0, {0}}, 0, 0 },
1801   { "", 2, {0, {0}}, 0, 0 },
1802   { "", 3, {0, {0}}, 0, 0 }
1803 };
1804
1805 CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken =
1806 {
1807   & frv_cgen_opval_h_hint_not_taken_entries[0],
1808   4,
1809   0, 0, 0, 0, ""
1810 };
1811
1812
1813 /* The hardware table.  */
1814
1815 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1816 #define A(a) (1 << CGEN_HW_##a)
1817 #else
1818 #define A(a) (1 << CGEN_HW_/**/a)
1819 #endif
1820
1821 const CGEN_HW_ENTRY frv_cgen_hw_table[] =
1822 {
1823   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1824   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1825   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1826   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1827   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1828   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
1829   { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1830   { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1831   { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1832   { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1833   { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1834   { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1835   { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1836   { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1837   { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1838   { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1839   { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1840   { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1841   { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1842   { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1843   { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1844   { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1845   { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1846   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1847   { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1848   { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1849   { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1850   { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1851   { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1852   { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1853   { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1854   { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1855   { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1856   { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1857   { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1858   { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1859   { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } },
1860   { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } },
1861   { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1862   { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1863   { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1864   { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1865   { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FR400)|(1<<MACH_FR450) } } },
1866   { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1867   { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1868   { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1869   { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } },
1870   { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } },
1871   { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } },
1872   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
1873 };
1874
1875 #undef A
1876
1877
1878 /* The instruction field table.  */
1879
1880 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1881 #define A(a) (1 << CGEN_IFLD_##a)
1882 #else
1883 #define A(a) (1 << CGEN_IFLD_/**/a)
1884 #endif
1885
1886 const CGEN_IFLD frv_cgen_ifld_table[] =
1887 {
1888   { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
1889   { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
1890   { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } }  },
1891   { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } }  },
1892   { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
1893   { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } }  },
1894   { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } }  },
1895   { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } }  },
1896   { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1897   { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1898   { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1899   { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1900   { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1901   { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1902   { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1903   { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1904   { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1905   { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1906   { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1907   { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1908   { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1909   { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1910   { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1911   { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
1912   { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } }  },
1913   { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } }  },
1914   { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } }  },
1915   { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1916   { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1917   { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
1918   { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1919   { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
1920   { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
1921   { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1922   { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
1923   { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
1924   { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1925   { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } }  },
1926   { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
1927   { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
1928   { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
1929   { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
1930   { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1931   { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
1932   { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1933   { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } }  },
1934   { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1935   { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
1936   { FRV_F_U12, "f-u12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
1937   { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
1938   { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
1939   { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
1940   { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } }  },
1941   { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } }  },
1942   { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1943   { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1944   { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1945   { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } }  },
1946   { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1947   { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1948   { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
1949   { FRV_F_SPR, "f-spr", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
1950   { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
1951   { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
1952   { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } }  },
1953   { FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
1954   { FRV_F_LRAE, "f-LRAE", 0, 32, 5, 1, { 0, { (1<<MACH_BASE) } }  },
1955   { FRV_F_LRAD, "f-LRAD", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } }  },
1956   { FRV_F_LRAS, "f-LRAS", 0, 32, 3, 1, { 0, { (1<<MACH_BASE) } }  },
1957   { FRV_F_TLBPROPX, "f-TLBPRopx", 0, 32, 28, 3, { 0, { (1<<MACH_BASE) } }  },
1958   { FRV_F_TLBPRL, "f-TLBPRL", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
1959   { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1960   { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1961   { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1962   { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1963   { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1964   { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1965   { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1966   { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1967   { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1968   { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1969   { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1970   { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1971   { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1972   { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1973   { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1974   { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1975   { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1976   { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1977   { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1978   { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1979   { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1980   { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1981   { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1982   { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1983   { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1984   { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1985   { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1986   { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1987   { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1988   { FRV_F_LRA_NULL, "f-LRA-null", 0, 32, 2, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1989   { FRV_F_TLBPR_NULL, "f-TLBPR-null", 0, 32, 30, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1990   { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1991   { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
1992   { 0, 0, 0, 0, 0, 0, {0, {0}} }
1993 };
1994
1995 #undef A
1996
1997
1998
1999 /* multi ifield declarations */
2000
2001 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [];
2002 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [];
2003 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [];
2004
2005
2006 /* multi ifield definitions */
2007
2008 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] =
2009 {
2010     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_H] } },
2011     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_L] } },
2012     { 0, { (const PTR) 0 } }
2013 };
2014 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] =
2015 {
2016     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_H] } },
2017     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_L] } },
2018     { 0, { (const PTR) 0 } }
2019 };
2020 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] =
2021 {
2022     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELH6] } },
2023     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELL18] } },
2024     { 0, { (const PTR) 0 } }
2025 };
2026
2027 /* The operand table.  */
2028
2029 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2030 #define A(a) (1 << CGEN_OPERAND_##a)
2031 #else
2032 #define A(a) (1 << CGEN_OPERAND_/**/a)
2033 #endif
2034 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2035 #define OPERAND(op) FRV_OPERAND_##op
2036 #else
2037 #define OPERAND(op) FRV_OPERAND_/**/op
2038 #endif
2039
2040 const CGEN_OPERAND frv_cgen_operand_table[] =
2041 {
2042 /* pc: program counter */
2043   { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
2044     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } },
2045     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2046 /* pack: packing bit */
2047   { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
2048     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } },
2049     { 0, { (1<<MACH_BASE) } }  },
2050 /* GRi: source register 1 */
2051   { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
2052     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } },
2053     { 0, { (1<<MACH_BASE) } }  },
2054 /* GRj: source register 2 */
2055   { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
2056     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } },
2057     { 0, { (1<<MACH_BASE) } }  },
2058 /* GRk: destination register */
2059   { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
2060     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
2061     { 0, { (1<<MACH_BASE) } }  },
2062 /* GRkhi: destination register */
2063   { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
2064     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
2065     { 0, { (1<<MACH_BASE) } }  },
2066 /* GRklo: destination register */
2067   { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
2068     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
2069     { 0, { (1<<MACH_BASE) } }  },
2070 /* GRdoublek: destination register */
2071   { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
2072     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
2073     { 0, { (1<<MACH_BASE) } }  },
2074 /* ACC40Si: signed accumulator */
2075   { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
2076     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
2077     { 0, { (1<<MACH_BASE) } }  },
2078 /* ACC40Ui: unsigned accumulator */
2079   { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
2080     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
2081     { 0, { (1<<MACH_BASE) } }  },
2082 /* ACC40Sk: target accumulator */
2083   { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
2084     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
2085     { 0, { (1<<MACH_BASE) } }  },
2086 /* ACC40Uk: target accumulator */
2087   { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
2088     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
2089     { 0, { (1<<MACH_BASE) } }  },
2090 /* ACCGi: source register */
2091   { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
2092     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } },
2093     { 0, { (1<<MACH_BASE) } }  },
2094 /* ACCGk: target register */
2095   { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
2096     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } },
2097     { 0, { (1<<MACH_BASE) } }  },
2098 /* CPRi: source register */
2099   { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
2100     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } },
2101     { 0, { (1<<MACH_FRV) } }  },
2102 /* CPRj: source register */
2103   { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
2104     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } },
2105     { 0, { (1<<MACH_FRV) } }  },
2106 /* CPRk: destination register */
2107   { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
2108     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
2109     { 0, { (1<<MACH_FRV) } }  },
2110 /* CPRdoublek: destination register */
2111   { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
2112     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
2113     { 0, { (1<<MACH_FRV) } }  },
2114 /* FRinti: source register 1 */
2115   { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
2116     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2117     { 0, { (1<<MACH_BASE) } }  },
2118 /* FRintj: source register 2 */
2119   { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
2120     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2121     { 0, { (1<<MACH_BASE) } }  },
2122 /* FRintk: target register */
2123   { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
2124     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2125     { 0, { (1<<MACH_BASE) } }  },
2126 /* FRi: source register 1 */
2127   { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
2128     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2129     { 0, { (1<<MACH_BASE) } }  },
2130 /* FRj: source register 2 */
2131   { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
2132     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2133     { 0, { (1<<MACH_BASE) } }  },
2134 /* FRk: destination register */
2135   { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
2136     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2137     { 0, { (1<<MACH_BASE) } }  },
2138 /* FRkhi: destination register */
2139   { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
2140     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2141     { 0, { (1<<MACH_BASE) } }  },
2142 /* FRklo: destination register */
2143   { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
2144     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2145     { 0, { (1<<MACH_BASE) } }  },
2146 /* FRdoublei: source register 1 */
2147   { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
2148     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2149     { 0, { (1<<MACH_BASE) } }  },
2150 /* FRdoublej: source register 2 */
2151   { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
2152     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2153     { 0, { (1<<MACH_BASE) } }  },
2154 /* FRdoublek: target register */
2155   { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
2156     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2157     { 0, { (1<<MACH_BASE) } }  },
2158 /* CRi: source register 1 */
2159   { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
2160     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } },
2161     { 0, { (1<<MACH_BASE) } }  },
2162 /* CRj: source register 2 */
2163   { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
2164     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } },
2165     { 0, { (1<<MACH_BASE) } }  },
2166 /* CRj_int: destination register */
2167   { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
2168     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
2169     { 0, { (1<<MACH_BASE) } }  },
2170 /* CRj_float: destination register */
2171   { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
2172     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
2173     { 0, { (1<<MACH_BASE) } }  },
2174 /* CRk: destination register */
2175   { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
2176     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } },
2177     { 0, { (1<<MACH_BASE) } }  },
2178 /* CCi: condition   register */
2179   { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
2180     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } },
2181     { 0, { (1<<MACH_BASE) } }  },
2182 /* ICCi_1: condition   register */
2183   { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
2184     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
2185     { 0, { (1<<MACH_BASE) } }  },
2186 /* ICCi_2: condition   register */
2187   { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
2188     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
2189     { 0, { (1<<MACH_BASE) } }  },
2190 /* ICCi_3: condition   register */
2191   { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
2192     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
2193     { 0, { (1<<MACH_BASE) } }  },
2194 /* FCCi_1: condition   register */
2195   { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
2196     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
2197     { 0, { (1<<MACH_BASE) } }  },
2198 /* FCCi_2: condition   register */
2199   { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
2200     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
2201     { 0, { (1<<MACH_BASE) } }  },
2202 /* FCCi_3: condition   register */
2203   { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
2204     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
2205     { 0, { (1<<MACH_BASE) } }  },
2206 /* FCCk: condition   register */
2207   { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
2208     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } },
2209     { 0, { (1<<MACH_BASE) } }  },
2210 /* eir: exception insn reg */
2211   { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
2212     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } },
2213     { 0, { (1<<MACH_BASE) } }  },
2214 /* s10: 10 bit signed immediate */
2215   { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
2216     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } },
2217     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2218 /* u16: 16 bit unsigned immediate */
2219   { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
2220     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
2221     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2222 /* s16: 16 bit signed   immediate */
2223   { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
2224     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
2225     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2226 /* s6: 6  bit signed   immediate */
2227   { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
2228     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } },
2229     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2230 /* s6_1: 6  bit signed   immediate */
2231   { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
2232     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } },
2233     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2234 /* u6: 6  bit unsigned immediate */
2235   { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
2236     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } },
2237     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2238 /* s5: 5  bit signed   immediate */
2239   { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
2240     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } },
2241     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2242 /* cond: conditional arithmetic */
2243   { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
2244     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } },
2245     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2246 /* ccond: lr branch condition */
2247   { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
2248     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } },
2249     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2250 /* hint: 2 bit branch predictor */
2251   { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
2252     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
2253     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2254 /* hint_taken: 2 bit branch predictor */
2255   { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
2256     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
2257     { 0, { (1<<MACH_BASE) } }  },
2258 /* hint_not_taken: 2 bit branch predictor */
2259   { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
2260     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
2261     { 0, { (1<<MACH_BASE) } }  },
2262 /* LI: link indicator */
2263   { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
2264     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } },
2265     { 0, { (1<<MACH_BASE) } }  },
2266 /* lock: cache lock indicator */
2267   { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
2268     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } },
2269     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2270 /* debug: debug mode indicator */
2271   { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
2272     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } },
2273     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2274 /* ae: all entries indicator */
2275   { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
2276     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } },
2277     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2278 /* label16: 18 bit pc relative address */
2279   { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
2280     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } },
2281     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
2282 /* label24: 26 bit pc relative address */
2283   { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
2284     { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
2285     { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2286 /* LRAE: Load Real Address E flag */
2287   { "LRAE", FRV_OPERAND_LRAE, HW_H_UINT, 5, 1,
2288     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } },
2289     { 0, { (1<<MACH_BASE) } }  },
2290 /* LRAD: Load Real Address D flag */
2291   { "LRAD", FRV_OPERAND_LRAD, HW_H_UINT, 4, 1,
2292     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } },
2293     { 0, { (1<<MACH_BASE) } }  },
2294 /* LRAS: Load Real Address S flag */
2295   { "LRAS", FRV_OPERAND_LRAS, HW_H_UINT, 3, 1,
2296     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } },
2297     { 0, { (1<<MACH_BASE) } }  },
2298 /* TLBPRopx: TLB Probe operation number */
2299   { "TLBPRopx", FRV_OPERAND_TLBPROPX, HW_H_UINT, 28, 3,
2300     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } },
2301     { 0, { (1<<MACH_BASE) } }  },
2302 /* TLBPRL: TLB Probe L flag */
2303   { "TLBPRL", FRV_OPERAND_TLBPRL, HW_H_UINT, 25, 1,
2304     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } },
2305     { 0, { (1<<MACH_BASE) } }  },
2306 /* A0: A==0 operand of mclracc */
2307   { "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1,
2308     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
2309     { 0, { (1<<MACH_BASE) } }  },
2310 /* A1: A==1 operand of mclracc */
2311   { "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1,
2312     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
2313     { 0, { (1<<MACH_BASE) } }  },
2314 /* FRintieven: (even) source register 1 */
2315   { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6,
2316     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2317     { 0, { (1<<MACH_BASE) } }  },
2318 /* FRintjeven: (even) source register 2 */
2319   { "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6,
2320     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2321     { 0, { (1<<MACH_BASE) } }  },
2322 /* FRintkeven: (even) target register */
2323   { "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6,
2324     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2325     { 0, { (1<<MACH_BASE) } }  },
2326 /* d12: 12 bit signed immediate */
2327   { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
2328     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
2329     { 0, { (1<<MACH_BASE) } }  },
2330 /* s12: 12 bit signed immediate */
2331   { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
2332     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
2333     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
2334 /* u12: 12 bit signed immediate */
2335   { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
2336     { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
2337     { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2338 /* spr: special purpose register */
2339   { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
2340     { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
2341     { 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
2342 /* ulo16: 16 bit unsigned immediate, for #lo() */
2343   { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
2344     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
2345     { 0, { (1<<MACH_BASE) } }  },
2346 /* slo16: 16 bit unsigned immediate, for #lo() */
2347   { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
2348     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
2349     { 0, { (1<<MACH_BASE) } }  },
2350 /* uhi16: 16 bit unsigned immediate, for #hi() */
2351   { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
2352     { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
2353     { 0, { (1<<MACH_BASE) } }  },
2354 /* psr_esr: PSR.ESR bit */
2355   { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
2356     { 0, { (const PTR) 0 } },
2357     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2358 /* psr_s: PSR.S   bit */
2359   { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
2360     { 0, { (const PTR) 0 } },
2361     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2362 /* psr_ps: PSR.PS  bit */
2363   { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
2364     { 0, { (const PTR) 0 } },
2365     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2366 /* psr_et: PSR.ET  bit */
2367   { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
2368     { 0, { (const PTR) 0 } },
2369     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2370 /* bpsr_bs: BPSR.BS  bit */
2371   { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
2372     { 0, { (const PTR) 0 } },
2373     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2374 /* bpsr_bet: BPSR.BET bit */
2375   { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
2376     { 0, { (const PTR) 0 } },
2377     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2378 /* tbr_tba: TBR.TBA */
2379   { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
2380     { 0, { (const PTR) 0 } },
2381     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2382 /* tbr_tt: TBR.TT */
2383   { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
2384     { 0, { (const PTR) 0 } },
2385     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
2386 /* sentinel */
2387   { 0, 0, 0, 0, 0,
2388     { 0, { (const PTR) 0 } },
2389     { 0, { 0 } } }
2390 };
2391
2392 #undef A
2393
2394
2395 /* The instruction table.  */
2396
2397 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2398 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2399 #define A(a) (1 << CGEN_INSN_##a)
2400 #else
2401 #define A(a) (1 << CGEN_INSN_/**/a)
2402 #endif
2403
2404 static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
2405 {
2406   /* Special null first entry.
2407      A `num' value of zero is thus invalid.
2408      Also, the special `invalid' insn resides here.  */
2409   { 0, 0, 0, 0, {0, {0}} },
2410 /* add$pack $GRi,$GRj,$GRk */
2411   {
2412     FRV_INSN_ADD, "add", "add", 32,
2413     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2414   },
2415 /* sub$pack $GRi,$GRj,$GRk */
2416   {
2417     FRV_INSN_SUB, "sub", "sub", 32,
2418     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2419   },
2420 /* and$pack $GRi,$GRj,$GRk */
2421   {
2422     FRV_INSN_AND, "and", "and", 32,
2423     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2424   },
2425 /* or$pack $GRi,$GRj,$GRk */
2426   {
2427     FRV_INSN_OR, "or", "or", 32,
2428     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2429   },
2430 /* xor$pack $GRi,$GRj,$GRk */
2431   {
2432     FRV_INSN_XOR, "xor", "xor", 32,
2433     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2434   },
2435 /* not$pack $GRj,$GRk */
2436   {
2437     FRV_INSN_NOT, "not", "not", 32,
2438     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2439   },
2440 /* sdiv$pack $GRi,$GRj,$GRk */
2441   {
2442     FRV_INSN_SDIV, "sdiv", "sdiv", 32,
2443     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2444   },
2445 /* nsdiv$pack $GRi,$GRj,$GRk */
2446   {
2447     FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
2448     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2449   },
2450 /* udiv$pack $GRi,$GRj,$GRk */
2451   {
2452     FRV_INSN_UDIV, "udiv", "udiv", 32,
2453     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2454   },
2455 /* nudiv$pack $GRi,$GRj,$GRk */
2456   {
2457     FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
2458     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2459   },
2460 /* smul$pack $GRi,$GRj,$GRdoublek */
2461   {
2462     FRV_INSN_SMUL, "smul", "smul", 32,
2463     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2464   },
2465 /* umul$pack $GRi,$GRj,$GRdoublek */
2466   {
2467     FRV_INSN_UMUL, "umul", "umul", 32,
2468     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2469   },
2470 /* smu$pack $GRi,$GRj */
2471   {
2472     FRV_INSN_SMU, "smu", "smu", 32,
2473     { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
2474   },
2475 /* smass$pack $GRi,$GRj */
2476   {
2477     FRV_INSN_SMASS, "smass", "smass", 32,
2478     { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
2479   },
2480 /* smsss$pack $GRi,$GRj */
2481   {
2482     FRV_INSN_SMSSS, "smsss", "smsss", 32,
2483     { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
2484   },
2485 /* sll$pack $GRi,$GRj,$GRk */
2486   {
2487     FRV_INSN_SLL, "sll", "sll", 32,
2488     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2489   },
2490 /* srl$pack $GRi,$GRj,$GRk */
2491   {
2492     FRV_INSN_SRL, "srl", "srl", 32,
2493     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2494   },
2495 /* sra$pack $GRi,$GRj,$GRk */
2496   {
2497     FRV_INSN_SRA, "sra", "sra", 32,
2498     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2499   },
2500 /* slass$pack $GRi,$GRj,$GRk */
2501   {
2502     FRV_INSN_SLASS, "slass", "slass", 32,
2503     { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
2504   },
2505 /* scutss$pack $GRj,$GRk */
2506   {
2507     FRV_INSN_SCUTSS, "scutss", "scutss", 32,
2508     { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_I0, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
2509   },
2510 /* scan$pack $GRi,$GRj,$GRk */
2511   {
2512     FRV_INSN_SCAN, "scan", "scan", 32,
2513     { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2514   },
2515 /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
2516   {
2517     FRV_INSN_CADD, "cadd", "cadd", 32,
2518     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2519   },
2520 /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
2521   {
2522     FRV_INSN_CSUB, "csub", "csub", 32,
2523     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2524   },
2525 /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
2526   {
2527     FRV_INSN_CAND, "cand", "cand", 32,
2528     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2529   },
2530 /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
2531   {
2532     FRV_INSN_COR, "cor", "cor", 32,
2533     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2534   },
2535 /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
2536   {
2537     FRV_INSN_CXOR, "cxor", "cxor", 32,
2538     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2539   },
2540 /* cnot$pack $GRj,$GRk,$CCi,$cond */
2541   {
2542     FRV_INSN_CNOT, "cnot", "cnot", 32,
2543     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2544   },
2545 /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
2546   {
2547     FRV_INSN_CSMUL, "csmul", "csmul", 32,
2548     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2549   },
2550 /* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
2551   {
2552     FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
2553     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2554   },
2555 /* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
2556   {
2557     FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
2558     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2559   },
2560 /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
2561   {
2562     FRV_INSN_CSLL, "csll", "csll", 32,
2563     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2564   },
2565 /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
2566   {
2567     FRV_INSN_CSRL, "csrl", "csrl", 32,
2568     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2569   },
2570 /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
2571   {
2572     FRV_INSN_CSRA, "csra", "csra", 32,
2573     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2574   },
2575 /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
2576   {
2577     FRV_INSN_CSCAN, "cscan", "cscan", 32,
2578     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2579   },
2580 /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2581   {
2582     FRV_INSN_ADDCC, "addcc", "addcc", 32,
2583     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2584   },
2585 /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2586   {
2587     FRV_INSN_SUBCC, "subcc", "subcc", 32,
2588     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2589   },
2590 /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2591   {
2592     FRV_INSN_ANDCC, "andcc", "andcc", 32,
2593     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2594   },
2595 /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2596   {
2597     FRV_INSN_ORCC, "orcc", "orcc", 32,
2598     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2599   },
2600 /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2601   {
2602     FRV_INSN_XORCC, "xorcc", "xorcc", 32,
2603     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2604   },
2605 /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2606   {
2607     FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
2608     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2609   },
2610 /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2611   {
2612     FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
2613     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2614   },
2615 /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2616   {
2617     FRV_INSN_SRACC, "sracc", "sracc", 32,
2618     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2619   },
2620 /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
2621   {
2622     FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
2623     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2624   },
2625 /* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
2626   {
2627     FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
2628     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2629   },
2630 /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2631   {
2632     FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
2633     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2634   },
2635 /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2636   {
2637     FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
2638     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2639   },
2640 /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
2641   {
2642     FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
2643     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2644   },
2645 /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2646   {
2647     FRV_INSN_CANDCC, "candcc", "candcc", 32,
2648     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2649   },
2650 /* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2651   {
2652     FRV_INSN_CORCC, "corcc", "corcc", 32,
2653     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2654   },
2655 /* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2656   {
2657     FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
2658     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2659   },
2660 /* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2661   {
2662     FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
2663     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2664   },
2665 /* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2666   {
2667     FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
2668     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2669   },
2670 /* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2671   {
2672     FRV_INSN_CSRACC, "csracc", "csracc", 32,
2673     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2674   },
2675 /* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
2676   {
2677     FRV_INSN_ADDX, "addx", "addx", 32,
2678     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2679   },
2680 /* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
2681   {
2682     FRV_INSN_SUBX, "subx", "subx", 32,
2683     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2684   },
2685 /* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2686   {
2687     FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
2688     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2689   },
2690 /* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2691   {
2692     FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
2693     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2694   },
2695 /* addss$pack $GRi,$GRj,$GRk */
2696   {
2697     FRV_INSN_ADDSS, "addss", "addss", 32,
2698     { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
2699   },
2700 /* subss$pack $GRi,$GRj,$GRk */
2701   {
2702     FRV_INSN_SUBSS, "subss", "subss", 32,
2703     { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
2704   },
2705 /* addi$pack $GRi,$s12,$GRk */
2706   {
2707     FRV_INSN_ADDI, "addi", "addi", 32,
2708     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2709   },
2710 /* subi$pack $GRi,$s12,$GRk */
2711   {
2712     FRV_INSN_SUBI, "subi", "subi", 32,
2713     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2714   },
2715 /* andi$pack $GRi,$s12,$GRk */
2716   {
2717     FRV_INSN_ANDI, "andi", "andi", 32,
2718     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2719   },
2720 /* ori$pack $GRi,$s12,$GRk */
2721   {
2722     FRV_INSN_ORI, "ori", "ori", 32,
2723     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2724   },
2725 /* xori$pack $GRi,$s12,$GRk */
2726   {
2727     FRV_INSN_XORI, "xori", "xori", 32,
2728     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2729   },
2730 /* sdivi$pack $GRi,$s12,$GRk */
2731   {
2732     FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
2733     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2734   },
2735 /* nsdivi$pack $GRi,$s12,$GRk */
2736   {
2737     FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
2738     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2739   },
2740 /* udivi$pack $GRi,$s12,$GRk */
2741   {
2742     FRV_INSN_UDIVI, "udivi", "udivi", 32,
2743     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2744   },
2745 /* nudivi$pack $GRi,$s12,$GRk */
2746   {
2747     FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
2748     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2749   },
2750 /* smuli$pack $GRi,$s12,$GRdoublek */
2751   {
2752     FRV_INSN_SMULI, "smuli", "smuli", 32,
2753     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2754   },
2755 /* umuli$pack $GRi,$s12,$GRdoublek */
2756   {
2757     FRV_INSN_UMULI, "umuli", "umuli", 32,
2758     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2759   },
2760 /* slli$pack $GRi,$s12,$GRk */
2761   {
2762     FRV_INSN_SLLI, "slli", "slli", 32,
2763     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2764   },
2765 /* srli$pack $GRi,$s12,$GRk */
2766   {
2767     FRV_INSN_SRLI, "srli", "srli", 32,
2768     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2769   },
2770 /* srai$pack $GRi,$s12,$GRk */
2771   {
2772     FRV_INSN_SRAI, "srai", "srai", 32,
2773     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2774   },
2775 /* scani$pack $GRi,$s12,$GRk */
2776   {
2777     FRV_INSN_SCANI, "scani", "scani", 32,
2778     { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2779   },
2780 /* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2781   {
2782     FRV_INSN_ADDICC, "addicc", "addicc", 32,
2783     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2784   },
2785 /* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2786   {
2787     FRV_INSN_SUBICC, "subicc", "subicc", 32,
2788     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2789   },
2790 /* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2791   {
2792     FRV_INSN_ANDICC, "andicc", "andicc", 32,
2793     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2794   },
2795 /* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
2796   {
2797     FRV_INSN_ORICC, "oricc", "oricc", 32,
2798     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2799   },
2800 /* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
2801   {
2802     FRV_INSN_XORICC, "xoricc", "xoricc", 32,
2803     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2804   },
2805 /* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
2806   {
2807     FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
2808     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2809   },
2810 /* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
2811   {
2812     FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
2813     { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
2814   },
2815 /* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2816   {
2817     FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
2818     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2819   },
2820 /* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2821   {
2822     FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
2823     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2824   },
2825 /* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2826   {
2827     FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
2828     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2829   },
2830 /* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
2831   {
2832     FRV_INSN_ADDXI, "addxi", "addxi", 32,
2833     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2834   },
2835 /* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
2836   {
2837     FRV_INSN_SUBXI, "subxi", "subxi", 32,
2838     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2839   },
2840 /* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2841   {
2842     FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
2843     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2844   },
2845 /* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2846   {
2847     FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
2848     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2849   },
2850 /* cmpb$pack $GRi,$GRj,$ICCi_1 */
2851   {
2852     FRV_INSN_CMPB, "cmpb", "cmpb", 32,
2853     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
2854   },
2855 /* cmpba$pack $GRi,$GRj,$ICCi_1 */
2856   {
2857     FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
2858     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
2859   },
2860 /* setlo$pack $ulo16,$GRklo */
2861   {
2862     FRV_INSN_SETLO, "setlo", "setlo", 32,
2863     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2864   },
2865 /* sethi$pack $uhi16,$GRkhi */
2866   {
2867     FRV_INSN_SETHI, "sethi", "sethi", 32,
2868     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2869   },
2870 /* setlos$pack $slo16,$GRk */
2871   {
2872     FRV_INSN_SETLOS, "setlos", "setlos", 32,
2873     { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
2874   },
2875 /* ldsb$pack @($GRi,$GRj),$GRk */
2876   {
2877     FRV_INSN_LDSB, "ldsb", "ldsb", 32,
2878     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2879   },
2880 /* ldub$pack @($GRi,$GRj),$GRk */
2881   {
2882     FRV_INSN_LDUB, "ldub", "ldub", 32,
2883     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2884   },
2885 /* ldsh$pack @($GRi,$GRj),$GRk */
2886   {
2887     FRV_INSN_LDSH, "ldsh", "ldsh", 32,
2888     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2889   },
2890 /* lduh$pack @($GRi,$GRj),$GRk */
2891   {
2892     FRV_INSN_LDUH, "lduh", "lduh", 32,
2893     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2894   },
2895 /* ld$pack @($GRi,$GRj),$GRk */
2896   {
2897     FRV_INSN_LD, "ld", "ld", 32,
2898     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2899   },
2900 /* ldbf$pack @($GRi,$GRj),$FRintk */
2901   {
2902     FRV_INSN_LDBF, "ldbf", "ldbf", 32,
2903     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2904   },
2905 /* ldhf$pack @($GRi,$GRj),$FRintk */
2906   {
2907     FRV_INSN_LDHF, "ldhf", "ldhf", 32,
2908     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2909   },
2910 /* ldf$pack @($GRi,$GRj),$FRintk */
2911   {
2912     FRV_INSN_LDF, "ldf", "ldf", 32,
2913     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2914   },
2915 /* ldc$pack @($GRi,$GRj),$CPRk */
2916   {
2917     FRV_INSN_LDC, "ldc", "ldc", 32,
2918     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
2919   },
2920 /* nldsb$pack @($GRi,$GRj),$GRk */
2921   {
2922     FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
2923     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2924   },
2925 /* nldub$pack @($GRi,$GRj),$GRk */
2926   {
2927     FRV_INSN_NLDUB, "nldub", "nldub", 32,
2928     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2929   },
2930 /* nldsh$pack @($GRi,$GRj),$GRk */
2931   {
2932     FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
2933     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2934   },
2935 /* nlduh$pack @($GRi,$GRj),$GRk */
2936   {
2937     FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
2938     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2939   },
2940 /* nld$pack @($GRi,$GRj),$GRk */
2941   {
2942     FRV_INSN_NLD, "nld", "nld", 32,
2943     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2944   },
2945 /* nldbf$pack @($GRi,$GRj),$FRintk */
2946   {
2947     FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
2948     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2949   },
2950 /* nldhf$pack @($GRi,$GRj),$FRintk */
2951   {
2952     FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
2953     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2954   },
2955 /* nldf$pack @($GRi,$GRj),$FRintk */
2956   {
2957     FRV_INSN_NLDF, "nldf", "nldf", 32,
2958     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2959   },
2960 /* ldd$pack @($GRi,$GRj),$GRdoublek */
2961   {
2962     FRV_INSN_LDD, "ldd", "ldd", 32,
2963     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2964   },
2965 /* lddf$pack @($GRi,$GRj),$FRdoublek */
2966   {
2967     FRV_INSN_LDDF, "lddf", "lddf", 32,
2968     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2969   },
2970 /* lddc$pack @($GRi,$GRj),$CPRdoublek */
2971   {
2972     FRV_INSN_LDDC, "lddc", "lddc", 32,
2973     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2974   },
2975 /* nldd$pack @($GRi,$GRj),$GRdoublek */
2976   {
2977     FRV_INSN_NLDD, "nldd", "nldd", 32,
2978     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2979   },
2980 /* nlddf$pack @($GRi,$GRj),$FRdoublek */
2981   {
2982     FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
2983     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
2984   },
2985 /* ldq$pack @($GRi,$GRj),$GRk */
2986   {
2987     FRV_INSN_LDQ, "ldq", "ldq", 32,
2988     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
2989   },
2990 /* ldqf$pack @($GRi,$GRj),$FRintk */
2991   {
2992     FRV_INSN_LDQF, "ldqf", "ldqf", 32,
2993     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
2994   },
2995 /* ldqc$pack @($GRi,$GRj),$CPRk */
2996   {
2997     FRV_INSN_LDQC, "ldqc", "ldqc", 32,
2998     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
2999   },
3000 /* nldq$pack @($GRi,$GRj),$GRk */
3001   {
3002     FRV_INSN_NLDQ, "nldq", "nldq", 32,
3003     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3004   },
3005 /* nldqf$pack @($GRi,$GRj),$FRintk */
3006   {
3007     FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
3008     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3009   },
3010 /* ldsbu$pack @($GRi,$GRj),$GRk */
3011   {
3012     FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
3013     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3014   },
3015 /* ldubu$pack @($GRi,$GRj),$GRk */
3016   {
3017     FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
3018     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3019   },
3020 /* ldshu$pack @($GRi,$GRj),$GRk */
3021   {
3022     FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
3023     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3024   },
3025 /* lduhu$pack @($GRi,$GRj),$GRk */
3026   {
3027     FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
3028     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3029   },
3030 /* ldu$pack @($GRi,$GRj),$GRk */
3031   {
3032     FRV_INSN_LDU, "ldu", "ldu", 32,
3033     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3034   },
3035 /* nldsbu$pack @($GRi,$GRj),$GRk */
3036   {
3037     FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
3038     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3039   },
3040 /* nldubu$pack @($GRi,$GRj),$GRk */
3041   {
3042     FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
3043     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3044   },
3045 /* nldshu$pack @($GRi,$GRj),$GRk */
3046   {
3047     FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
3048     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3049   },
3050 /* nlduhu$pack @($GRi,$GRj),$GRk */
3051   {
3052     FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
3053     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3054   },
3055 /* nldu$pack @($GRi,$GRj),$GRk */
3056   {
3057     FRV_INSN_NLDU, "nldu", "nldu", 32,
3058     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3059   },
3060 /* ldbfu$pack @($GRi,$GRj),$FRintk */
3061   {
3062     FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
3063     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3064   },
3065 /* ldhfu$pack @($GRi,$GRj),$FRintk */
3066   {
3067     FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
3068     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3069   },
3070 /* ldfu$pack @($GRi,$GRj),$FRintk */
3071   {
3072     FRV_INSN_LDFU, "ldfu", "ldfu", 32,
3073     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3074   },
3075 /* ldcu$pack @($GRi,$GRj),$CPRk */
3076   {
3077     FRV_INSN_LDCU, "ldcu", "ldcu", 32,
3078     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3079   },
3080 /* nldbfu$pack @($GRi,$GRj),$FRintk */
3081   {
3082     FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
3083     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3084   },
3085 /* nldhfu$pack @($GRi,$GRj),$FRintk */
3086   {
3087     FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
3088     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3089   },
3090 /* nldfu$pack @($GRi,$GRj),$FRintk */
3091   {
3092     FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
3093     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3094   },
3095 /* lddu$pack @($GRi,$GRj),$GRdoublek */
3096   {
3097     FRV_INSN_LDDU, "lddu", "lddu", 32,
3098     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3099   },
3100 /* nlddu$pack @($GRi,$GRj),$GRdoublek */
3101   {
3102     FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
3103     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3104   },
3105 /* lddfu$pack @($GRi,$GRj),$FRdoublek */
3106   {
3107     FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
3108     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3109   },
3110 /* lddcu$pack @($GRi,$GRj),$CPRdoublek */
3111   {
3112     FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
3113     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3114   },
3115 /* nlddfu$pack @($GRi,$GRj),$FRdoublek */
3116   {
3117     FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
3118     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3119   },
3120 /* ldqu$pack @($GRi,$GRj),$GRk */
3121   {
3122     FRV_INSN_LDQU, "ldqu", "ldqu", 32,
3123     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3124   },
3125 /* nldqu$pack @($GRi,$GRj),$GRk */
3126   {
3127     FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
3128     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3129   },
3130 /* ldqfu$pack @($GRi,$GRj),$FRintk */
3131   {
3132     FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
3133     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3134   },
3135 /* ldqcu$pack @($GRi,$GRj),$CPRk */
3136   {
3137     FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
3138     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3139   },
3140 /* nldqfu$pack @($GRi,$GRj),$FRintk */
3141   {
3142     FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
3143     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3144   },
3145 /* ldsbi$pack @($GRi,$d12),$GRk */
3146   {
3147     FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
3148     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3149   },
3150 /* ldshi$pack @($GRi,$d12),$GRk */
3151   {
3152     FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
3153     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3154   },
3155 /* ldi$pack @($GRi,$d12),$GRk */
3156   {
3157     FRV_INSN_LDI, "ldi", "ldi", 32,
3158     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3159   },
3160 /* ldubi$pack @($GRi,$d12),$GRk */
3161   {
3162     FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
3163     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3164   },
3165 /* lduhi$pack @($GRi,$d12),$GRk */
3166   {
3167     FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
3168     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3169   },
3170 /* ldbfi$pack @($GRi,$d12),$FRintk */
3171   {
3172     FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
3173     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3174   },
3175 /* ldhfi$pack @($GRi,$d12),$FRintk */
3176   {
3177     FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
3178     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3179   },
3180 /* ldfi$pack @($GRi,$d12),$FRintk */
3181   {
3182     FRV_INSN_LDFI, "ldfi", "ldfi", 32,
3183     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3184   },
3185 /* nldsbi$pack @($GRi,$d12),$GRk */
3186   {
3187     FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
3188     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3189   },
3190 /* nldubi$pack @($GRi,$d12),$GRk */
3191   {
3192     FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
3193     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3194   },
3195 /* nldshi$pack @($GRi,$d12),$GRk */
3196   {
3197     FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
3198     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3199   },
3200 /* nlduhi$pack @($GRi,$d12),$GRk */
3201   {
3202     FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
3203     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3204   },
3205 /* nldi$pack @($GRi,$d12),$GRk */
3206   {
3207     FRV_INSN_NLDI, "nldi", "nldi", 32,
3208     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3209   },
3210 /* nldbfi$pack @($GRi,$d12),$FRintk */
3211   {
3212     FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
3213     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3214   },
3215 /* nldhfi$pack @($GRi,$d12),$FRintk */
3216   {
3217     FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
3218     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3219   },
3220 /* nldfi$pack @($GRi,$d12),$FRintk */
3221   {
3222     FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
3223     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3224   },
3225 /* lddi$pack @($GRi,$d12),$GRdoublek */
3226   {
3227     FRV_INSN_LDDI, "lddi", "lddi", 32,
3228     { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3229   },
3230 /* lddfi$pack @($GRi,$d12),$FRdoublek */
3231   {
3232     FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
3233     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3234   },
3235 /* nlddi$pack @($GRi,$d12),$GRdoublek */
3236   {
3237     FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
3238     { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3239   },
3240 /* nlddfi$pack @($GRi,$d12),$FRdoublek */
3241   {
3242     FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
3243     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3244   },
3245 /* ldqi$pack @($GRi,$d12),$GRk */
3246   {
3247     FRV_INSN_LDQI, "ldqi", "ldqi", 32,
3248     { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3249   },
3250 /* ldqfi$pack @($GRi,$d12),$FRintk */
3251   {
3252     FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
3253     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3254   },
3255 /* nldqfi$pack @($GRi,$d12),$FRintk */
3256   {
3257     FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
3258     { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3259   },
3260 /* stb$pack $GRk,@($GRi,$GRj) */
3261   {
3262     FRV_INSN_STB, "stb", "stb", 32,
3263     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3264   },
3265 /* sth$pack $GRk,@($GRi,$GRj) */
3266   {
3267     FRV_INSN_STH, "sth", "sth", 32,
3268     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3269   },
3270 /* st$pack $GRk,@($GRi,$GRj) */
3271   {
3272     FRV_INSN_ST, "st", "st", 32,
3273     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3274   },
3275 /* stbf$pack $FRintk,@($GRi,$GRj) */
3276   {
3277     FRV_INSN_STBF, "stbf", "stbf", 32,
3278     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3279   },
3280 /* sthf$pack $FRintk,@($GRi,$GRj) */
3281   {
3282     FRV_INSN_STHF, "sthf", "sthf", 32,
3283     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3284   },
3285 /* stf$pack $FRintk,@($GRi,$GRj) */
3286   {
3287     FRV_INSN_STF, "stf", "stf", 32,
3288     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3289   },
3290 /* stc$pack $CPRk,@($GRi,$GRj) */
3291   {
3292     FRV_INSN_STC, "stc", "stc", 32,
3293     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3294   },
3295 /* std$pack $GRdoublek,@($GRi,$GRj) */
3296   {
3297     FRV_INSN_STD, "std", "std", 32,
3298     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3299   },
3300 /* stdf$pack $FRdoublek,@($GRi,$GRj) */
3301   {
3302     FRV_INSN_STDF, "stdf", "stdf", 32,
3303     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3304   },
3305 /* stdc$pack $CPRdoublek,@($GRi,$GRj) */
3306   {
3307     FRV_INSN_STDC, "stdc", "stdc", 32,
3308     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3309   },
3310 /* stq$pack $GRk,@($GRi,$GRj) */
3311   {
3312     FRV_INSN_STQ, "stq", "stq", 32,
3313     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
3314   },
3315 /* stqf$pack $FRintk,@($GRi,$GRj) */
3316   {
3317     FRV_INSN_STQF, "stqf", "stqf", 32,
3318     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
3319   },
3320 /* stqc$pack $CPRk,@($GRi,$GRj) */
3321   {
3322     FRV_INSN_STQC, "stqc", "stqc", 32,
3323     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
3324   },
3325 /* stbu$pack $GRk,@($GRi,$GRj) */
3326   {
3327     FRV_INSN_STBU, "stbu", "stbu", 32,
3328     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3329   },
3330 /* sthu$pack $GRk,@($GRi,$GRj) */
3331   {
3332     FRV_INSN_STHU, "sthu", "sthu", 32,
3333     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3334   },
3335 /* stu$pack $GRk,@($GRi,$GRj) */
3336   {
3337     FRV_INSN_STU, "stu", "stu", 32,
3338     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3339   },
3340 /* stbfu$pack $FRintk,@($GRi,$GRj) */
3341   {
3342     FRV_INSN_STBFU, "stbfu", "stbfu", 32,
3343     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3344   },
3345 /* sthfu$pack $FRintk,@($GRi,$GRj) */
3346   {
3347     FRV_INSN_STHFU, "sthfu", "sthfu", 32,
3348     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3349   },
3350 /* stfu$pack $FRintk,@($GRi,$GRj) */
3351   {
3352     FRV_INSN_STFU, "stfu", "stfu", 32,
3353     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3354   },
3355 /* stcu$pack $CPRk,@($GRi,$GRj) */
3356   {
3357     FRV_INSN_STCU, "stcu", "stcu", 32,
3358     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3359   },
3360 /* stdu$pack $GRdoublek,@($GRi,$GRj) */
3361   {
3362     FRV_INSN_STDU, "stdu", "stdu", 32,
3363     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3364   },
3365 /* stdfu$pack $FRdoublek,@($GRi,$GRj) */
3366   {
3367     FRV_INSN_STDFU, "stdfu", "stdfu", 32,
3368     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3369   },
3370 /* stdcu$pack $CPRdoublek,@($GRi,$GRj) */
3371   {
3372     FRV_INSN_STDCU, "stdcu", "stdcu", 32,
3373     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3374   },
3375 /* stqu$pack $GRk,@($GRi,$GRj) */
3376   {
3377     FRV_INSN_STQU, "stqu", "stqu", 32,
3378     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
3379   },
3380 /* stqfu$pack $FRintk,@($GRi,$GRj) */
3381   {
3382     FRV_INSN_STQFU, "stqfu", "stqfu", 32,
3383     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
3384   },
3385 /* stqcu$pack $CPRk,@($GRi,$GRj) */
3386   {
3387     FRV_INSN_STQCU, "stqcu", "stqcu", 32,
3388     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
3389   },
3390 /* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3391   {
3392     FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
3393     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3394   },
3395 /* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3396   {
3397     FRV_INSN_CLDUB, "cldub", "cldub", 32,
3398     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3399   },
3400 /* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3401   {
3402     FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
3403     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3404   },
3405 /* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3406   {
3407     FRV_INSN_CLDUH, "clduh", "clduh", 32,
3408     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3409   },
3410 /* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3411   {
3412     FRV_INSN_CLD, "cld", "cld", 32,
3413     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3414   },
3415 /* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3416   {
3417     FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
3418     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3419   },
3420 /* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3421   {
3422     FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
3423     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3424   },
3425 /* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3426   {
3427     FRV_INSN_CLDF, "cldf", "cldf", 32,
3428     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3429   },
3430 /* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
3431   {
3432     FRV_INSN_CLDD, "cldd", "cldd", 32,
3433     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3434   },
3435 /* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
3436   {
3437     FRV_INSN_CLDDF, "clddf", "clddf", 32,
3438     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3439   },
3440 /* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3441   {
3442     FRV_INSN_CLDQ, "cldq", "cldq", 32,
3443     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3444   },
3445 /* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3446   {
3447     FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
3448     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3449   },
3450 /* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3451   {
3452     FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
3453     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3454   },
3455 /* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3456   {
3457     FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
3458     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3459   },
3460 /* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3461   {
3462     FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
3463     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3464   },
3465 /* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3466   {
3467     FRV_INSN_CLDU, "cldu", "cldu", 32,
3468     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3469   },
3470 /* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3471   {
3472     FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
3473     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3474   },
3475 /* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3476   {
3477     FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
3478     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3479   },
3480 /* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3481   {
3482     FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
3483     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3484   },
3485 /* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
3486   {
3487     FRV_INSN_CLDDU, "clddu", "clddu", 32,
3488     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3489   },
3490 /* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
3491   {
3492     FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
3493     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
3494   },
3495 /* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3496   {
3497     FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
3498     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
3499   },
3500 /* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3501   {
3502     FRV_INSN_CSTB, "cstb", "cstb", 32,
3503     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3504   },
3505 /* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3506   {
3507     FRV_INSN_CSTH, "csth", "csth", 32,
3508     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3509   },
3510 /* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3511   {
3512     FRV_INSN_CST, "cst", "cst", 32,
3513     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3514   },
3515 /* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3516   {
3517     FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
3518     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3519   },
3520 /* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3521   {
3522     FRV_INSN_CSTHF, "csthf", "csthf", 32,
3523     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3524   },
3525 /* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3526   {
3527     FRV_INSN_CSTF, "cstf", "cstf", 32,
3528     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3529   },
3530 /* cstd$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
3531   {
3532     FRV_INSN_CSTD, "cstd", "cstd", 32,
3533     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3534   },
3535 /* cstdf$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
3536   {
3537     FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
3538     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3539   },
3540 /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3541   {
3542     FRV_INSN_CSTQ, "cstq", "cstq", 32,
3543     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
3544   },
3545 /* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3546   {
3547     FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
3548     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3549   },
3550 /* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3551   {
3552     FRV_INSN_CSTHU, "csthu", "csthu", 32,
3553     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3554   },
3555 /* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3556   {
3557     FRV_INSN_CSTU, "cstu", "cstu", 32,
3558     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3559   },
3560 /* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3561   {
3562     FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
3563     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3564   },
3565 /* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3566   {
3567     FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
3568     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3569   },
3570 /* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3571   {
3572     FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
3573     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3574   },
3575 /* cstdu$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
3576   {
3577     FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
3578     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3579   },
3580 /* cstdfu$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
3581   {
3582     FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
3583     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3584   },
3585 /* stbi$pack $GRk,@($GRi,$d12) */
3586   {
3587     FRV_INSN_STBI, "stbi", "stbi", 32,
3588     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3589   },
3590 /* sthi$pack $GRk,@($GRi,$d12) */
3591   {
3592     FRV_INSN_STHI, "sthi", "sthi", 32,
3593     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3594   },
3595 /* sti$pack $GRk,@($GRi,$d12) */
3596   {
3597     FRV_INSN_STI, "sti", "sti", 32,
3598     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3599   },
3600 /* stbfi$pack $FRintk,@($GRi,$d12) */
3601   {
3602     FRV_INSN_STBFI, "stbfi", "stbfi", 32,
3603     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3604   },
3605 /* sthfi$pack $FRintk,@($GRi,$d12) */
3606   {
3607     FRV_INSN_STHFI, "sthfi", "sthfi", 32,
3608     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3609   },
3610 /* stfi$pack $FRintk,@($GRi,$d12) */
3611   {
3612     FRV_INSN_STFI, "stfi", "stfi", 32,
3613     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3614   },
3615 /* stdi$pack $GRdoublek,@($GRi,$d12) */
3616   {
3617     FRV_INSN_STDI, "stdi", "stdi", 32,
3618     { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3619   },
3620 /* stdfi$pack $FRdoublek,@($GRi,$d12) */
3621   {
3622     FRV_INSN_STDFI, "stdfi", "stdfi", 32,
3623     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
3624   },
3625 /* stqi$pack $GRk,@($GRi,$d12) */
3626   {
3627     FRV_INSN_STQI, "stqi", "stqi", 32,
3628     { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
3629   },
3630 /* stqfi$pack $FRintk,@($GRi,$d12) */
3631   {
3632     FRV_INSN_STQFI, "stqfi", "stqfi", 32,
3633     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
3634   },
3635 /* swap$pack @($GRi,$GRj),$GRk */
3636   {
3637     FRV_INSN_SWAP, "swap", "swap", 32,
3638     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
3639   },
3640 /* swapi$pack @($GRi,$d12),$GRk */
3641   {
3642     FRV_INSN_SWAPI, "swapi", "swapi", 32,
3643     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
3644   },
3645 /* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3646   {
3647     FRV_INSN_CSWAP, "cswap", "cswap", 32,
3648     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
3649   },
3650 /* movgf$pack $GRj,$FRintk */
3651   {
3652     FRV_INSN_MOVGF, "movgf", "movgf", 32,
3653     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
3654   },
3655 /* movfg$pack $FRintk,$GRj */
3656   {
3657     FRV_INSN_MOVFG, "movfg", "movfg", 32,
3658     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
3659   },
3660 /* movgfd$pack $GRj,$FRintk */
3661   {
3662     FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
3663     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
3664   },
3665 /* movfgd$pack $FRintk,$GRj */
3666   {
3667     FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
3668     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
3669   },
3670 /* movgfq$pack $GRj,$FRintk */
3671   {
3672     FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
3673     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
3674   },
3675 /* movfgq$pack $FRintk,$GRj */
3676   {
3677     FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
3678     { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
3679   },
3680 /* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
3681   {
3682     FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
3683     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
3684   },
3685 /* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
3686   {
3687     FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
3688     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
3689   },
3690 /* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
3691   {
3692     FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
3693     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
3694   },
3695 /* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
3696   {
3697     FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
3698     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
3699   },
3700 /* movgs$pack $GRj,$spr */
3701   {
3702     FRV_INSN_MOVGS, "movgs", "movgs", 32,
3703     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
3704   },
3705 /* movsg$pack $spr,$GRj */
3706   {
3707     FRV_INSN_MOVSG, "movsg", "movsg", 32,
3708     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
3709   },
3710 /* bra$pack $hint_taken$label16 */
3711   {
3712     FRV_INSN_BRA, "bra", "bra", 32,
3713     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3714   },
3715 /* bno$pack$hint_not_taken */
3716   {
3717     FRV_INSN_BNO, "bno", "bno", 32,
3718     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3719   },
3720 /* beq$pack $ICCi_2,$hint,$label16 */
3721   {
3722     FRV_INSN_BEQ, "beq", "beq", 32,
3723     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3724   },
3725 /* bne$pack $ICCi_2,$hint,$label16 */
3726   {
3727     FRV_INSN_BNE, "bne", "bne", 32,
3728     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3729   },
3730 /* ble$pack $ICCi_2,$hint,$label16 */
3731   {
3732     FRV_INSN_BLE, "ble", "ble", 32,
3733     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3734   },
3735 /* bgt$pack $ICCi_2,$hint,$label16 */
3736   {
3737     FRV_INSN_BGT, "bgt", "bgt", 32,
3738     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3739   },
3740 /* blt$pack $ICCi_2,$hint,$label16 */
3741   {
3742     FRV_INSN_BLT, "blt", "blt", 32,
3743     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3744   },
3745 /* bge$pack $ICCi_2,$hint,$label16 */
3746   {
3747     FRV_INSN_BGE, "bge", "bge", 32,
3748     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3749   },
3750 /* bls$pack $ICCi_2,$hint,$label16 */
3751   {
3752     FRV_INSN_BLS, "bls", "bls", 32,
3753     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3754   },
3755 /* bhi$pack $ICCi_2,$hint,$label16 */
3756   {
3757     FRV_INSN_BHI, "bhi", "bhi", 32,
3758     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3759   },
3760 /* bc$pack $ICCi_2,$hint,$label16 */
3761   {
3762     FRV_INSN_BC, "bc", "bc", 32,
3763     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3764   },
3765 /* bnc$pack $ICCi_2,$hint,$label16 */
3766   {
3767     FRV_INSN_BNC, "bnc", "bnc", 32,
3768     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3769   },
3770 /* bn$pack $ICCi_2,$hint,$label16 */
3771   {
3772     FRV_INSN_BN, "bn", "bn", 32,
3773     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3774   },
3775 /* bp$pack $ICCi_2,$hint,$label16 */
3776   {
3777     FRV_INSN_BP, "bp", "bp", 32,
3778     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3779   },
3780 /* bv$pack $ICCi_2,$hint,$label16 */
3781   {
3782     FRV_INSN_BV, "bv", "bv", 32,
3783     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3784   },
3785 /* bnv$pack $ICCi_2,$hint,$label16 */
3786   {
3787     FRV_INSN_BNV, "bnv", "bnv", 32,
3788     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3789   },
3790 /* fbra$pack $hint_taken$label16 */
3791   {
3792     FRV_INSN_FBRA, "fbra", "fbra", 32,
3793     { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3794   },
3795 /* fbno$pack$hint_not_taken */
3796   {
3797     FRV_INSN_FBNO, "fbno", "fbno", 32,
3798     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3799   },
3800 /* fbne$pack $FCCi_2,$hint,$label16 */
3801   {
3802     FRV_INSN_FBNE, "fbne", "fbne", 32,
3803     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3804   },
3805 /* fbeq$pack $FCCi_2,$hint,$label16 */
3806   {
3807     FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
3808     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3809   },
3810 /* fblg$pack $FCCi_2,$hint,$label16 */
3811   {
3812     FRV_INSN_FBLG, "fblg", "fblg", 32,
3813     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3814   },
3815 /* fbue$pack $FCCi_2,$hint,$label16 */
3816   {
3817     FRV_INSN_FBUE, "fbue", "fbue", 32,
3818     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3819   },
3820 /* fbul$pack $FCCi_2,$hint,$label16 */
3821   {
3822     FRV_INSN_FBUL, "fbul", "fbul", 32,
3823     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3824   },
3825 /* fbge$pack $FCCi_2,$hint,$label16 */
3826   {
3827     FRV_INSN_FBGE, "fbge", "fbge", 32,
3828     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3829   },
3830 /* fblt$pack $FCCi_2,$hint,$label16 */
3831   {
3832     FRV_INSN_FBLT, "fblt", "fblt", 32,
3833     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3834   },
3835 /* fbuge$pack $FCCi_2,$hint,$label16 */
3836   {
3837     FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
3838     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3839   },
3840 /* fbug$pack $FCCi_2,$hint,$label16 */
3841   {
3842     FRV_INSN_FBUG, "fbug", "fbug", 32,
3843     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3844   },
3845 /* fble$pack $FCCi_2,$hint,$label16 */
3846   {
3847     FRV_INSN_FBLE, "fble", "fble", 32,
3848     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3849   },
3850 /* fbgt$pack $FCCi_2,$hint,$label16 */
3851   {
3852     FRV_INSN_FBGT, "fbgt", "fbgt", 32,
3853     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3854   },
3855 /* fbule$pack $FCCi_2,$hint,$label16 */
3856   {
3857     FRV_INSN_FBULE, "fbule", "fbule", 32,
3858     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3859   },
3860 /* fbu$pack $FCCi_2,$hint,$label16 */
3861   {
3862     FRV_INSN_FBU, "fbu", "fbu", 32,
3863     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3864   },
3865 /* fbo$pack $FCCi_2,$hint,$label16 */
3866   {
3867     FRV_INSN_FBO, "fbo", "fbo", 32,
3868     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
3869   },
3870 /* bctrlr$pack $ccond,$hint */
3871   {
3872     FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
3873     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
3874   },
3875 /* bralr$pack$hint_taken */
3876   {
3877     FRV_INSN_BRALR, "bralr", "bralr", 32,
3878     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3879   },
3880 /* bnolr$pack$hint_not_taken */
3881   {
3882     FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
3883     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3884   },
3885 /* beqlr$pack $ICCi_2,$hint */
3886   {
3887     FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
3888     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3889   },
3890 /* bnelr$pack $ICCi_2,$hint */
3891   {
3892     FRV_INSN_BNELR, "bnelr", "bnelr", 32,
3893     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3894   },
3895 /* blelr$pack $ICCi_2,$hint */
3896   {
3897     FRV_INSN_BLELR, "blelr", "blelr", 32,
3898     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3899   },
3900 /* bgtlr$pack $ICCi_2,$hint */
3901   {
3902     FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
3903     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3904   },
3905 /* bltlr$pack $ICCi_2,$hint */
3906   {
3907     FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
3908     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3909   },
3910 /* bgelr$pack $ICCi_2,$hint */
3911   {
3912     FRV_INSN_BGELR, "bgelr", "bgelr", 32,
3913     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3914   },
3915 /* blslr$pack $ICCi_2,$hint */
3916   {
3917     FRV_INSN_BLSLR, "blslr", "blslr", 32,
3918     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3919   },
3920 /* bhilr$pack $ICCi_2,$hint */
3921   {
3922     FRV_INSN_BHILR, "bhilr", "bhilr", 32,
3923     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3924   },
3925 /* bclr$pack $ICCi_2,$hint */
3926   {
3927     FRV_INSN_BCLR, "bclr", "bclr", 32,
3928     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3929   },
3930 /* bnclr$pack $ICCi_2,$hint */
3931   {
3932     FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
3933     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3934   },
3935 /* bnlr$pack $ICCi_2,$hint */
3936   {
3937     FRV_INSN_BNLR, "bnlr", "bnlr", 32,
3938     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3939   },
3940 /* bplr$pack $ICCi_2,$hint */
3941   {
3942     FRV_INSN_BPLR, "bplr", "bplr", 32,
3943     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3944   },
3945 /* bvlr$pack $ICCi_2,$hint */
3946   {
3947     FRV_INSN_BVLR, "bvlr", "bvlr", 32,
3948     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3949   },
3950 /* bnvlr$pack $ICCi_2,$hint */
3951   {
3952     FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
3953     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3954   },
3955 /* fbralr$pack$hint_taken */
3956   {
3957     FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
3958     { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3959   },
3960 /* fbnolr$pack$hint_not_taken */
3961   {
3962     FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
3963     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3964   },
3965 /* fbeqlr$pack $FCCi_2,$hint */
3966   {
3967     FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
3968     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3969   },
3970 /* fbnelr$pack $FCCi_2,$hint */
3971   {
3972     FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
3973     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3974   },
3975 /* fblglr$pack $FCCi_2,$hint */
3976   {
3977     FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
3978     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3979   },
3980 /* fbuelr$pack $FCCi_2,$hint */
3981   {
3982     FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
3983     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3984   },
3985 /* fbullr$pack $FCCi_2,$hint */
3986   {
3987     FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
3988     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3989   },
3990 /* fbgelr$pack $FCCi_2,$hint */
3991   {
3992     FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
3993     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3994   },
3995 /* fbltlr$pack $FCCi_2,$hint */
3996   {
3997     FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
3998     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
3999   },
4000 /* fbugelr$pack $FCCi_2,$hint */
4001   {
4002     FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
4003     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
4004   },
4005 /* fbuglr$pack $FCCi_2,$hint */
4006   {
4007     FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
4008     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
4009   },
4010 /* fblelr$pack $FCCi_2,$hint */
4011   {
4012     FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
4013     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
4014   },
4015 /* fbgtlr$pack $FCCi_2,$hint */
4016   {
4017     FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
4018     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
4019   },
4020 /* fbulelr$pack $FCCi_2,$hint */
4021   {
4022     FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
4023     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
4024   },
4025 /* fbulr$pack $FCCi_2,$hint */
4026   {
4027     FRV_INSN_FBULR, "fbulr", "fbulr", 32,
4028     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
4029   },
4030 /* fbolr$pack $FCCi_2,$hint */
4031   {
4032     FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
4033     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
4034   },
4035 /* bcralr$pack $ccond$hint_taken */
4036   {
4037     FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
4038     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4039   },
4040 /* bcnolr$pack$hint_not_taken */
4041   {
4042     FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
4043     { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4044   },
4045 /* bceqlr$pack $ICCi_2,$ccond,$hint */
4046   {
4047     FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
4048     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4049   },
4050 /* bcnelr$pack $ICCi_2,$ccond,$hint */
4051   {
4052     FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
4053     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4054   },
4055 /* bclelr$pack $ICCi_2,$ccond,$hint */
4056   {
4057     FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
4058     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4059   },
4060 /* bcgtlr$pack $ICCi_2,$ccond,$hint */
4061   {
4062     FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
4063     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4064   },
4065 /* bcltlr$pack $ICCi_2,$ccond,$hint */
4066   {
4067     FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
4068     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4069   },
4070 /* bcgelr$pack $ICCi_2,$ccond,$hint */
4071   {
4072     FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
4073     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4074   },
4075 /* bclslr$pack $ICCi_2,$ccond,$hint */
4076   {
4077     FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
4078     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4079   },
4080 /* bchilr$pack $ICCi_2,$ccond,$hint */
4081   {
4082     FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
4083     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4084   },
4085 /* bcclr$pack $ICCi_2,$ccond,$hint */
4086   {
4087     FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
4088     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4089   },
4090 /* bcnclr$pack $ICCi_2,$ccond,$hint */
4091   {
4092     FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
4093     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4094   },
4095 /* bcnlr$pack $ICCi_2,$ccond,$hint */
4096   {
4097     FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
4098     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4099   },
4100 /* bcplr$pack $ICCi_2,$ccond,$hint */
4101   {
4102     FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
4103     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4104   },
4105 /* bcvlr$pack $ICCi_2,$ccond,$hint */
4106   {
4107     FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
4108     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4109   },
4110 /* bcnvlr$pack $ICCi_2,$ccond,$hint */
4111   {
4112     FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
4113     { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4114   },
4115 /* fcbralr$pack $ccond$hint_taken */
4116   {
4117     FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
4118     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4119   },
4120 /* fcbnolr$pack$hint_not_taken */
4121   {
4122     FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
4123     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4124   },
4125 /* fcbeqlr$pack $FCCi_2,$ccond,$hint */
4126   {
4127     FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
4128     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4129   },
4130 /* fcbnelr$pack $FCCi_2,$ccond,$hint */
4131   {
4132     FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
4133     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4134   },
4135 /* fcblglr$pack $FCCi_2,$ccond,$hint */
4136   {
4137     FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
4138     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4139   },
4140 /* fcbuelr$pack $FCCi_2,$ccond,$hint */
4141   {
4142     FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
4143     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4144   },
4145 /* fcbullr$pack $FCCi_2,$ccond,$hint */
4146   {
4147     FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
4148     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4149   },
4150 /* fcbgelr$pack $FCCi_2,$ccond,$hint */
4151   {
4152     FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
4153     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4154   },
4155 /* fcbltlr$pack $FCCi_2,$ccond,$hint */
4156   {
4157     FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
4158     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4159   },
4160 /* fcbugelr$pack $FCCi_2,$ccond,$hint */
4161   {
4162     FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
4163     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4164   },
4165 /* fcbuglr$pack $FCCi_2,$ccond,$hint */
4166   {
4167     FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
4168     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4169   },
4170 /* fcblelr$pack $FCCi_2,$ccond,$hint */
4171   {
4172     FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
4173     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4174   },
4175 /* fcbgtlr$pack $FCCi_2,$ccond,$hint */
4176   {
4177     FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
4178     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4179   },
4180 /* fcbulelr$pack $FCCi_2,$ccond,$hint */
4181   {
4182     FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
4183     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4184   },
4185 /* fcbulr$pack $FCCi_2,$ccond,$hint */
4186   {
4187     FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
4188     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4189   },
4190 /* fcbolr$pack $FCCi_2,$ccond,$hint */
4191   {
4192     FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
4193     { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
4194   },
4195 /* jmpl$pack @($GRi,$GRj) */
4196   {
4197     FRV_INSN_JMPL, "jmpl", "jmpl", 32,
4198     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
4199   },
4200 /* calll$pack @($GRi,$GRj) */
4201   {
4202     FRV_INSN_CALLL, "calll", "calll", 32,
4203     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
4204   },
4205 /* jmpil$pack @($GRi,$s12) */
4206   {
4207     FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
4208     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
4209   },
4210 /* callil$pack @($GRi,$s12) */
4211   {
4212     FRV_INSN_CALLIL, "callil", "callil", 32,
4213     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
4214   },
4215 /* call$pack $label24 */
4216   {
4217     FRV_INSN_CALL, "call", "call", 32,
4218     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR450_MAJOR_B_4, FR500_MAJOR_B_4, FR550_MAJOR_B_4 } }
4219   },
4220 /* rett$pack $debug */
4221   {
4222     FRV_INSN_RETT, "rett", "rett", 32,
4223     { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
4224   },
4225 /* rei$pack $eir */
4226   {
4227     FRV_INSN_REI, "rei", "rei", 32,
4228     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_1, FR550_MAJOR_NONE } }
4229   },
4230 /* tra$pack $GRi,$GRj */
4231   {
4232     FRV_INSN_TRA, "tra", "tra", 32,
4233     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4234   },
4235 /* tno$pack */
4236   {
4237     FRV_INSN_TNO, "tno", "tno", 32,
4238     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4239   },
4240 /* teq$pack $ICCi_2,$GRi,$GRj */
4241   {
4242     FRV_INSN_TEQ, "teq", "teq", 32,
4243     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4244   },
4245 /* tne$pack $ICCi_2,$GRi,$GRj */
4246   {
4247     FRV_INSN_TNE, "tne", "tne", 32,
4248     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4249   },
4250 /* tle$pack $ICCi_2,$GRi,$GRj */
4251   {
4252     FRV_INSN_TLE, "tle", "tle", 32,
4253     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4254   },
4255 /* tgt$pack $ICCi_2,$GRi,$GRj */
4256   {
4257     FRV_INSN_TGT, "tgt", "tgt", 32,
4258     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4259   },
4260 /* tlt$pack $ICCi_2,$GRi,$GRj */
4261   {
4262     FRV_INSN_TLT, "tlt", "tlt", 32,
4263     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4264   },
4265 /* tge$pack $ICCi_2,$GRi,$GRj */
4266   {
4267     FRV_INSN_TGE, "tge", "tge", 32,
4268     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4269   },
4270 /* tls$pack $ICCi_2,$GRi,$GRj */
4271   {
4272     FRV_INSN_TLS, "tls", "tls", 32,
4273     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4274   },
4275 /* thi$pack $ICCi_2,$GRi,$GRj */
4276   {
4277     FRV_INSN_THI, "thi", "thi", 32,
4278     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4279   },
4280 /* tc$pack $ICCi_2,$GRi,$GRj */
4281   {
4282     FRV_INSN_TC, "tc", "tc", 32,
4283     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4284   },
4285 /* tnc$pack $ICCi_2,$GRi,$GRj */
4286   {
4287     FRV_INSN_TNC, "tnc", "tnc", 32,
4288     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4289   },
4290 /* tn$pack $ICCi_2,$GRi,$GRj */
4291   {
4292     FRV_INSN_TN, "tn", "tn", 32,
4293     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4294   },
4295 /* tp$pack $ICCi_2,$GRi,$GRj */
4296   {
4297     FRV_INSN_TP, "tp", "tp", 32,
4298     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4299   },
4300 /* tv$pack $ICCi_2,$GRi,$GRj */
4301   {
4302     FRV_INSN_TV, "tv", "tv", 32,
4303     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4304   },
4305 /* tnv$pack $ICCi_2,$GRi,$GRj */
4306   {
4307     FRV_INSN_TNV, "tnv", "tnv", 32,
4308     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4309   },
4310 /* ftra$pack $GRi,$GRj */
4311   {
4312     FRV_INSN_FTRA, "ftra", "ftra", 32,
4313     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4314   },
4315 /* ftno$pack */
4316   {
4317     FRV_INSN_FTNO, "ftno", "ftno", 32,
4318     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4319   },
4320 /* ftne$pack $FCCi_2,$GRi,$GRj */
4321   {
4322     FRV_INSN_FTNE, "ftne", "ftne", 32,
4323     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4324   },
4325 /* fteq$pack $FCCi_2,$GRi,$GRj */
4326   {
4327     FRV_INSN_FTEQ, "fteq", "fteq", 32,
4328     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4329   },
4330 /* ftlg$pack $FCCi_2,$GRi,$GRj */
4331   {
4332     FRV_INSN_FTLG, "ftlg", "ftlg", 32,
4333     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4334   },
4335 /* ftue$pack $FCCi_2,$GRi,$GRj */
4336   {
4337     FRV_INSN_FTUE, "ftue", "ftue", 32,
4338     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4339   },
4340 /* ftul$pack $FCCi_2,$GRi,$GRj */
4341   {
4342     FRV_INSN_FTUL, "ftul", "ftul", 32,
4343     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4344   },
4345 /* ftge$pack $FCCi_2,$GRi,$GRj */
4346   {
4347     FRV_INSN_FTGE, "ftge", "ftge", 32,
4348     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4349   },
4350 /* ftlt$pack $FCCi_2,$GRi,$GRj */
4351   {
4352     FRV_INSN_FTLT, "ftlt", "ftlt", 32,
4353     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4354   },
4355 /* ftuge$pack $FCCi_2,$GRi,$GRj */
4356   {
4357     FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
4358     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4359   },
4360 /* ftug$pack $FCCi_2,$GRi,$GRj */
4361   {
4362     FRV_INSN_FTUG, "ftug", "ftug", 32,
4363     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4364   },
4365 /* ftle$pack $FCCi_2,$GRi,$GRj */
4366   {
4367     FRV_INSN_FTLE, "ftle", "ftle", 32,
4368     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4369   },
4370 /* ftgt$pack $FCCi_2,$GRi,$GRj */
4371   {
4372     FRV_INSN_FTGT, "ftgt", "ftgt", 32,
4373     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4374   },
4375 /* ftule$pack $FCCi_2,$GRi,$GRj */
4376   {
4377     FRV_INSN_FTULE, "ftule", "ftule", 32,
4378     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4379   },
4380 /* ftu$pack $FCCi_2,$GRi,$GRj */
4381   {
4382     FRV_INSN_FTU, "ftu", "ftu", 32,
4383     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4384   },
4385 /* fto$pack $FCCi_2,$GRi,$GRj */
4386   {
4387     FRV_INSN_FTO, "fto", "fto", 32,
4388     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4389   },
4390 /* tira$pack $GRi,$s12 */
4391   {
4392     FRV_INSN_TIRA, "tira", "tira", 32,
4393     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4394   },
4395 /* tino$pack */
4396   {
4397     FRV_INSN_TINO, "tino", "tino", 32,
4398     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4399   },
4400 /* tieq$pack $ICCi_2,$GRi,$s12 */
4401   {
4402     FRV_INSN_TIEQ, "tieq", "tieq", 32,
4403     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4404   },
4405 /* tine$pack $ICCi_2,$GRi,$s12 */
4406   {
4407     FRV_INSN_TINE, "tine", "tine", 32,
4408     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4409   },
4410 /* tile$pack $ICCi_2,$GRi,$s12 */
4411   {
4412     FRV_INSN_TILE, "tile", "tile", 32,
4413     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4414   },
4415 /* tigt$pack $ICCi_2,$GRi,$s12 */
4416   {
4417     FRV_INSN_TIGT, "tigt", "tigt", 32,
4418     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4419   },
4420 /* tilt$pack $ICCi_2,$GRi,$s12 */
4421   {
4422     FRV_INSN_TILT, "tilt", "tilt", 32,
4423     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4424   },
4425 /* tige$pack $ICCi_2,$GRi,$s12 */
4426   {
4427     FRV_INSN_TIGE, "tige", "tige", 32,
4428     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4429   },
4430 /* tils$pack $ICCi_2,$GRi,$s12 */
4431   {
4432     FRV_INSN_TILS, "tils", "tils", 32,
4433     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4434   },
4435 /* tihi$pack $ICCi_2,$GRi,$s12 */
4436   {
4437     FRV_INSN_TIHI, "tihi", "tihi", 32,
4438     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4439   },
4440 /* tic$pack $ICCi_2,$GRi,$s12 */
4441   {
4442     FRV_INSN_TIC, "tic", "tic", 32,
4443     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4444   },
4445 /* tinc$pack $ICCi_2,$GRi,$s12 */
4446   {
4447     FRV_INSN_TINC, "tinc", "tinc", 32,
4448     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4449   },
4450 /* tin$pack $ICCi_2,$GRi,$s12 */
4451   {
4452     FRV_INSN_TIN, "tin", "tin", 32,
4453     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4454   },
4455 /* tip$pack $ICCi_2,$GRi,$s12 */
4456   {
4457     FRV_INSN_TIP, "tip", "tip", 32,
4458     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4459   },
4460 /* tiv$pack $ICCi_2,$GRi,$s12 */
4461   {
4462     FRV_INSN_TIV, "tiv", "tiv", 32,
4463     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4464   },
4465 /* tinv$pack $ICCi_2,$GRi,$s12 */
4466   {
4467     FRV_INSN_TINV, "tinv", "tinv", 32,
4468     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4469   },
4470 /* ftira$pack $GRi,$s12 */
4471   {
4472     FRV_INSN_FTIRA, "ftira", "ftira", 32,
4473     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4474   },
4475 /* ftino$pack */
4476   {
4477     FRV_INSN_FTINO, "ftino", "ftino", 32,
4478     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4479   },
4480 /* ftine$pack $FCCi_2,$GRi,$s12 */
4481   {
4482     FRV_INSN_FTINE, "ftine", "ftine", 32,
4483     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4484   },
4485 /* ftieq$pack $FCCi_2,$GRi,$s12 */
4486   {
4487     FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
4488     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4489   },
4490 /* ftilg$pack $FCCi_2,$GRi,$s12 */
4491   {
4492     FRV_INSN_FTILG, "ftilg", "ftilg", 32,
4493     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4494   },
4495 /* ftiue$pack $FCCi_2,$GRi,$s12 */
4496   {
4497     FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
4498     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4499   },
4500 /* ftiul$pack $FCCi_2,$GRi,$s12 */
4501   {
4502     FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
4503     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4504   },
4505 /* ftige$pack $FCCi_2,$GRi,$s12 */
4506   {
4507     FRV_INSN_FTIGE, "ftige", "ftige", 32,
4508     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4509   },
4510 /* ftilt$pack $FCCi_2,$GRi,$s12 */
4511   {
4512     FRV_INSN_FTILT, "ftilt", "ftilt", 32,
4513     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4514   },
4515 /* ftiuge$pack $FCCi_2,$GRi,$s12 */
4516   {
4517     FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
4518     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4519   },
4520 /* ftiug$pack $FCCi_2,$GRi,$s12 */
4521   {
4522     FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
4523     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4524   },
4525 /* ftile$pack $FCCi_2,$GRi,$s12 */
4526   {
4527     FRV_INSN_FTILE, "ftile", "ftile", 32,
4528     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4529   },
4530 /* ftigt$pack $FCCi_2,$GRi,$s12 */
4531   {
4532     FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
4533     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4534   },
4535 /* ftiule$pack $FCCi_2,$GRi,$s12 */
4536   {
4537     FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
4538     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4539   },
4540 /* ftiu$pack $FCCi_2,$GRi,$s12 */
4541   {
4542     FRV_INSN_FTIU, "ftiu", "ftiu", 32,
4543     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4544   },
4545 /* ftio$pack $FCCi_2,$GRi,$s12 */
4546   {
4547     FRV_INSN_FTIO, "ftio", "ftio", 32,
4548     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4549   },
4550 /* break$pack */
4551   {
4552     FRV_INSN_BREAK, "break", "break", 32,
4553     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4554   },
4555 /* mtrap$pack */
4556   {
4557     FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
4558     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
4559   },
4560 /* andcr$pack $CRi,$CRj,$CRk */
4561   {
4562     FRV_INSN_ANDCR, "andcr", "andcr", 32,
4563     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
4564   },
4565 /* orcr$pack $CRi,$CRj,$CRk */
4566   {
4567     FRV_INSN_ORCR, "orcr", "orcr", 32,
4568     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
4569   },
4570 /* xorcr$pack $CRi,$CRj,$CRk */
4571   {
4572     FRV_INSN_XORCR, "xorcr", "xorcr", 32,
4573     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
4574   },
4575 /* nandcr$pack $CRi,$CRj,$CRk */
4576   {
4577     FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
4578     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
4579   },
4580 /* norcr$pack $CRi,$CRj,$CRk */
4581   {
4582     FRV_INSN_NORCR, "norcr", "norcr", 32,
4583     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
4584   },
4585 /* andncr$pack $CRi,$CRj,$CRk */
4586   {
4587     FRV_INSN_ANDNCR, "andncr", "andncr", 32,
4588     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
4589   },
4590 /* orncr$pack $CRi,$CRj,$CRk */
4591   {
4592     FRV_INSN_ORNCR, "orncr", "orncr", 32,
4593     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
4594   },
4595 /* nandncr$pack $CRi,$CRj,$CRk */
4596   {
4597     FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
4598     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
4599   },
4600 /* norncr$pack $CRi,$CRj,$CRk */
4601   {
4602     FRV_INSN_NORNCR, "norncr", "norncr", 32,
4603     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
4604   },
4605 /* notcr$pack $CRj,$CRk */
4606   {
4607     FRV_INSN_NOTCR, "notcr", "notcr", 32,
4608     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
4609   },
4610 /* ckra$pack $CRj_int */
4611   {
4612     FRV_INSN_CKRA, "ckra", "ckra", 32,
4613     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4614   },
4615 /* ckno$pack $CRj_int */
4616   {
4617     FRV_INSN_CKNO, "ckno", "ckno", 32,
4618     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4619   },
4620 /* ckeq$pack $ICCi_3,$CRj_int */
4621   {
4622     FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
4623     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4624   },
4625 /* ckne$pack $ICCi_3,$CRj_int */
4626   {
4627     FRV_INSN_CKNE, "ckne", "ckne", 32,
4628     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4629   },
4630 /* ckle$pack $ICCi_3,$CRj_int */
4631   {
4632     FRV_INSN_CKLE, "ckle", "ckle", 32,
4633     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4634   },
4635 /* ckgt$pack $ICCi_3,$CRj_int */
4636   {
4637     FRV_INSN_CKGT, "ckgt", "ckgt", 32,
4638     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4639   },
4640 /* cklt$pack $ICCi_3,$CRj_int */
4641   {
4642     FRV_INSN_CKLT, "cklt", "cklt", 32,
4643     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4644   },
4645 /* ckge$pack $ICCi_3,$CRj_int */
4646   {
4647     FRV_INSN_CKGE, "ckge", "ckge", 32,
4648     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4649   },
4650 /* ckls$pack $ICCi_3,$CRj_int */
4651   {
4652     FRV_INSN_CKLS, "ckls", "ckls", 32,
4653     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4654   },
4655 /* ckhi$pack $ICCi_3,$CRj_int */
4656   {
4657     FRV_INSN_CKHI, "ckhi", "ckhi", 32,
4658     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4659   },
4660 /* ckc$pack $ICCi_3,$CRj_int */
4661   {
4662     FRV_INSN_CKC, "ckc", "ckc", 32,
4663     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4664   },
4665 /* cknc$pack $ICCi_3,$CRj_int */
4666   {
4667     FRV_INSN_CKNC, "cknc", "cknc", 32,
4668     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4669   },
4670 /* ckn$pack $ICCi_3,$CRj_int */
4671   {
4672     FRV_INSN_CKN, "ckn", "ckn", 32,
4673     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4674   },
4675 /* ckp$pack $ICCi_3,$CRj_int */
4676   {
4677     FRV_INSN_CKP, "ckp", "ckp", 32,
4678     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4679   },
4680 /* ckv$pack $ICCi_3,$CRj_int */
4681   {
4682     FRV_INSN_CKV, "ckv", "ckv", 32,
4683     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4684   },
4685 /* cknv$pack $ICCi_3,$CRj_int */
4686   {
4687     FRV_INSN_CKNV, "cknv", "cknv", 32,
4688     { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4689   },
4690 /* fckra$pack $CRj_float */
4691   {
4692     FRV_INSN_FCKRA, "fckra", "fckra", 32,
4693     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4694   },
4695 /* fckno$pack $CRj_float */
4696   {
4697     FRV_INSN_FCKNO, "fckno", "fckno", 32,
4698     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4699   },
4700 /* fckne$pack $FCCi_3,$CRj_float */
4701   {
4702     FRV_INSN_FCKNE, "fckne", "fckne", 32,
4703     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4704   },
4705 /* fckeq$pack $FCCi_3,$CRj_float */
4706   {
4707     FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
4708     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4709   },
4710 /* fcklg$pack $FCCi_3,$CRj_float */
4711   {
4712     FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
4713     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4714   },
4715 /* fckue$pack $FCCi_3,$CRj_float */
4716   {
4717     FRV_INSN_FCKUE, "fckue", "fckue", 32,
4718     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4719   },
4720 /* fckul$pack $FCCi_3,$CRj_float */
4721   {
4722     FRV_INSN_FCKUL, "fckul", "fckul", 32,
4723     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4724   },
4725 /* fckge$pack $FCCi_3,$CRj_float */
4726   {
4727     FRV_INSN_FCKGE, "fckge", "fckge", 32,
4728     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4729   },
4730 /* fcklt$pack $FCCi_3,$CRj_float */
4731   {
4732     FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
4733     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4734   },
4735 /* fckuge$pack $FCCi_3,$CRj_float */
4736   {
4737     FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
4738     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4739   },
4740 /* fckug$pack $FCCi_3,$CRj_float */
4741   {
4742     FRV_INSN_FCKUG, "fckug", "fckug", 32,
4743     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4744   },
4745 /* fckle$pack $FCCi_3,$CRj_float */
4746   {
4747     FRV_INSN_FCKLE, "fckle", "fckle", 32,
4748     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4749   },
4750 /* fckgt$pack $FCCi_3,$CRj_float */
4751   {
4752     FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
4753     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4754   },
4755 /* fckule$pack $FCCi_3,$CRj_float */
4756   {
4757     FRV_INSN_FCKULE, "fckule", "fckule", 32,
4758     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4759   },
4760 /* fcku$pack $FCCi_3,$CRj_float */
4761   {
4762     FRV_INSN_FCKU, "fcku", "fcku", 32,
4763     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4764   },
4765 /* fcko$pack $FCCi_3,$CRj_float */
4766   {
4767     FRV_INSN_FCKO, "fcko", "fcko", 32,
4768     { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4769   },
4770 /* cckra$pack $CRj_int,$CCi,$cond */
4771   {
4772     FRV_INSN_CCKRA, "cckra", "cckra", 32,
4773     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4774   },
4775 /* cckno$pack $CRj_int,$CCi,$cond */
4776   {
4777     FRV_INSN_CCKNO, "cckno", "cckno", 32,
4778     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4779   },
4780 /* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
4781   {
4782     FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
4783     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4784   },
4785 /* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
4786   {
4787     FRV_INSN_CCKNE, "cckne", "cckne", 32,
4788     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4789   },
4790 /* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
4791   {
4792     FRV_INSN_CCKLE, "cckle", "cckle", 32,
4793     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4794   },
4795 /* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
4796   {
4797     FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
4798     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4799   },
4800 /* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
4801   {
4802     FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
4803     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4804   },
4805 /* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
4806   {
4807     FRV_INSN_CCKGE, "cckge", "cckge", 32,
4808     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4809   },
4810 /* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
4811   {
4812     FRV_INSN_CCKLS, "cckls", "cckls", 32,
4813     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4814   },
4815 /* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
4816   {
4817     FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
4818     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4819   },
4820 /* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
4821   {
4822     FRV_INSN_CCKC, "cckc", "cckc", 32,
4823     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4824   },
4825 /* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
4826   {
4827     FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
4828     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4829   },
4830 /* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
4831   {
4832     FRV_INSN_CCKN, "cckn", "cckn", 32,
4833     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4834   },
4835 /* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
4836   {
4837     FRV_INSN_CCKP, "cckp", "cckp", 32,
4838     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4839   },
4840 /* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
4841   {
4842     FRV_INSN_CCKV, "cckv", "cckv", 32,
4843     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4844   },
4845 /* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
4846   {
4847     FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
4848     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4849   },
4850 /* cfckra$pack $CRj_float,$CCi,$cond */
4851   {
4852     FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
4853     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4854   },
4855 /* cfckno$pack $CRj_float,$CCi,$cond */
4856   {
4857     FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
4858     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4859   },
4860 /* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
4861   {
4862     FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
4863     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4864   },
4865 /* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
4866   {
4867     FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
4868     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4869   },
4870 /* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
4871   {
4872     FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
4873     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4874   },
4875 /* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
4876   {
4877     FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
4878     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4879   },
4880 /* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
4881   {
4882     FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
4883     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4884   },
4885 /* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
4886   {
4887     FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
4888     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4889   },
4890 /* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
4891   {
4892     FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
4893     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4894   },
4895 /* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
4896   {
4897     FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
4898     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4899   },
4900 /* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
4901   {
4902     FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
4903     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4904   },
4905 /* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
4906   {
4907     FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
4908     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4909   },
4910 /* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
4911   {
4912     FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
4913     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4914   },
4915 /* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
4916   {
4917     FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
4918     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4919   },
4920 /* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
4921   {
4922     FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
4923     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4924   },
4925 /* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
4926   {
4927     FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
4928     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
4929   },
4930 /* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
4931   {
4932     FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
4933     { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
4934   },
4935 /* ccalll$pack @($GRi,$GRj),$CCi,$cond */
4936   {
4937     FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
4938     { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
4939   },
4940 /* ici$pack @($GRi,$GRj) */
4941   {
4942     FRV_INSN_ICI, "ici", "ici", 32,
4943     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
4944   },
4945 /* dci$pack @($GRi,$GRj) */
4946   {
4947     FRV_INSN_DCI, "dci", "dci", 32,
4948     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
4949   },
4950 /* icei$pack @($GRi,$GRj),$ae */
4951   {
4952     FRV_INSN_ICEI, "icei", "icei", 32,
4953     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
4954   },
4955 /* dcei$pack @($GRi,$GRj),$ae */
4956   {
4957     FRV_INSN_DCEI, "dcei", "dcei", 32,
4958     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
4959   },
4960 /* dcf$pack @($GRi,$GRj) */
4961   {
4962     FRV_INSN_DCF, "dcf", "dcf", 32,
4963     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
4964   },
4965 /* dcef$pack @($GRi,$GRj),$ae */
4966   {
4967     FRV_INSN_DCEF, "dcef", "dcef", 32,
4968     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
4969   },
4970 /* witlb$pack $GRk,@($GRi,$GRj) */
4971   {
4972     FRV_INSN_WITLB, "witlb", "witlb", 32,
4973     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
4974   },
4975 /* wdtlb$pack $GRk,@($GRi,$GRj) */
4976   {
4977     FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
4978     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
4979   },
4980 /* itlbi$pack @($GRi,$GRj) */
4981   {
4982     FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
4983     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
4984   },
4985 /* dtlbi$pack @($GRi,$GRj) */
4986   {
4987     FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
4988     { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
4989   },
4990 /* icpl$pack $GRi,$GRj,$lock */
4991   {
4992     FRV_INSN_ICPL, "icpl", "icpl", 32,
4993     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
4994   },
4995 /* dcpl$pack $GRi,$GRj,$lock */
4996   {
4997     FRV_INSN_DCPL, "dcpl", "dcpl", 32,
4998     { 0, { (1<<MACH_BASE), UNIT_DCPL, FR400_MAJOR_C_2, FR450_MAJOR_I_2, FR500_MAJOR_C_2, FR550_MAJOR_I_8 } }
4999   },
5000 /* icul$pack $GRi */
5001   {
5002     FRV_INSN_ICUL, "icul", "icul", 32,
5003     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
5004   },
5005 /* dcul$pack $GRi */
5006   {
5007     FRV_INSN_DCUL, "dcul", "dcul", 32,
5008     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
5009   },
5010 /* bar$pack */
5011   {
5012     FRV_INSN_BAR, "bar", "bar", 32,
5013     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
5014   },
5015 /* membar$pack */
5016   {
5017     FRV_INSN_MEMBAR, "membar", "membar", 32,
5018     { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
5019   },
5020 /* lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
5021   {
5022     FRV_INSN_LRAI, "lrai", "lrai", 32,
5023     { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
5024   },
5025 /* lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
5026   {
5027     FRV_INSN_LRAD, "lrad", "lrad", 32,
5028     { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
5029   },
5030 /* tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */
5031   {
5032     FRV_INSN_TLBPR, "tlbpr", "tlbpr", 32,
5033     { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
5034   },
5035 /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
5036   {
5037     FRV_INSN_COP1, "cop1", "cop1", 32,
5038     { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
5039   },
5040 /* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
5041   {
5042     FRV_INSN_COP2, "cop2", "cop2", 32,
5043     { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
5044   },
5045 /* clrgr$pack $GRk */
5046   {
5047     FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
5048     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
5049   },
5050 /* clrfr$pack $FRk */
5051   {
5052     FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
5053     { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
5054   },
5055 /* clrga$pack */
5056   {
5057     FRV_INSN_CLRGA, "clrga", "clrga", 32,
5058     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
5059   },
5060 /* clrfa$pack */
5061   {
5062     FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
5063     { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
5064   },
5065 /* commitgr$pack $GRk */
5066   {
5067     FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
5068     { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
5069   },
5070 /* commitfr$pack $FRk */
5071   {
5072     FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
5073     { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
5074   },
5075 /* commitga$pack */
5076   {
5077     FRV_INSN_COMMITGA, "commitga", "commitga", 32,
5078     { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
5079   },
5080 /* commitfa$pack */
5081   {
5082     FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
5083     { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
5084   },
5085 /* fitos$pack $FRintj,$FRk */
5086   {
5087     FRV_INSN_FITOS, "fitos", "fitos", 32,
5088     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5089   },
5090 /* fstoi$pack $FRj,$FRintk */
5091   {
5092     FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
5093     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5094   },
5095 /* fitod$pack $FRintj,$FRdoublek */
5096   {
5097     FRV_INSN_FITOD, "fitod", "fitod", 32,
5098     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5099   },
5100 /* fdtoi$pack $FRdoublej,$FRintk */
5101   {
5102     FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
5103     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5104   },
5105 /* fditos$pack $FRintj,$FRk */
5106   {
5107     FRV_INSN_FDITOS, "fditos", "fditos", 32,
5108     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5109   },
5110 /* fdstoi$pack $FRj,$FRintk */
5111   {
5112     FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
5113     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5114   },
5115 /* nfditos$pack $FRintj,$FRk */
5116   {
5117     FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
5118     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5119   },
5120 /* nfdstoi$pack $FRj,$FRintk */
5121   {
5122     FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
5123     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5124   },
5125 /* cfitos$pack $FRintj,$FRk,$CCi,$cond */
5126   {
5127     FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
5128     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5129   },
5130 /* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
5131   {
5132     FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
5133     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5134   },
5135 /* nfitos$pack $FRintj,$FRk */
5136   {
5137     FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
5138     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5139   },
5140 /* nfstoi$pack $FRj,$FRintk */
5141   {
5142     FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
5143     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5144   },
5145 /* fmovs$pack $FRj,$FRk */
5146   {
5147     FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
5148     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5149   },
5150 /* fmovd$pack $FRdoublej,$FRdoublek */
5151   {
5152     FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
5153     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5154   },
5155 /* fdmovs$pack $FRj,$FRk */
5156   {
5157     FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
5158     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5159   },
5160 /* cfmovs$pack $FRj,$FRk,$CCi,$cond */
5161   {
5162     FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
5163     { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5164   },
5165 /* fnegs$pack $FRj,$FRk */
5166   {
5167     FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
5168     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5169   },
5170 /* fnegd$pack $FRdoublej,$FRdoublek */
5171   {
5172     FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
5173     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5174   },
5175 /* fdnegs$pack $FRj,$FRk */
5176   {
5177     FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
5178     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5179   },
5180 /* cfnegs$pack $FRj,$FRk,$CCi,$cond */
5181   {
5182     FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
5183     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5184   },
5185 /* fabss$pack $FRj,$FRk */
5186   {
5187     FRV_INSN_FABSS, "fabss", "fabss", 32,
5188     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5189   },
5190 /* fabsd$pack $FRdoublej,$FRdoublek */
5191   {
5192     FRV_INSN_FABSD, "fabsd", "fabsd", 32,
5193     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5194   },
5195 /* fdabss$pack $FRj,$FRk */
5196   {
5197     FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
5198     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
5199   },
5200 /* cfabss$pack $FRj,$FRk,$CCi,$cond */
5201   {
5202     FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
5203     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
5204   },
5205 /* fsqrts$pack $FRj,$FRk */
5206   {
5207     FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
5208     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
5209   },
5210 /* fdsqrts$pack $FRj,$FRk */
5211   {
5212     FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
5213     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
5214   },
5215 /* nfdsqrts$pack $FRj,$FRk */
5216   {
5217     FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
5218     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
5219   },
5220 /* fsqrtd$pack $FRdoublej,$FRdoublek */
5221   {
5222     FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
5223     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
5224   },
5225 /* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
5226   {
5227     FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
5228     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
5229   },
5230 /* nfsqrts$pack $FRj,$FRk */
5231   {
5232     FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
5233     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
5234   },
5235 /* fadds$pack $FRi,$FRj,$FRk */
5236   {
5237     FRV_INSN_FADDS, "fadds", "fadds", 32,
5238     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
5239   },
5240 /* fsubs$pack $FRi,$FRj,$FRk */
5241   {
5242     FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
5243     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
5244   },
5245 /* fmuls$pack $FRi,$FRj,$FRk */
5246   {
5247     FRV_INSN_FMULS, "fmuls", "fmuls", 32,
5248     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
5249   },
5250 /* fdivs$pack $FRi,$FRj,$FRk */
5251   {
5252     FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
5253     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
5254   },
5255 /* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5256   {
5257     FRV_INSN_FADDD, "faddd", "faddd", 32,
5258     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
5259   },
5260 /* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5261   {
5262     FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
5263     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
5264   },
5265 /* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
5266   {
5267     FRV_INSN_FMULD, "fmuld", "fmuld", 32,
5268     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_NONE } }
5269   },
5270 /* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5271   {
5272     FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
5273     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
5274   },
5275 /* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
5276   {
5277     FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
5278     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
5279   },
5280 /* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5281   {
5282     FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
5283     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
5284   },
5285 /* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
5286   {
5287     FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
5288     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
5289   },
5290 /* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5291   {
5292     FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
5293     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
5294   },
5295 /* nfadds$pack $FRi,$FRj,$FRk */
5296   {
5297     FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
5298     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
5299   },
5300 /* nfsubs$pack $FRi,$FRj,$FRk */
5301   {
5302     FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
5303     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
5304   },
5305 /* nfmuls$pack $FRi,$FRj,$FRk */
5306   {
5307     FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
5308     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
5309   },
5310 /* nfdivs$pack $FRi,$FRj,$FRk */
5311   {
5312     FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
5313     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
5314   },
5315 /* fcmps$pack $FRi,$FRj,$FCCi_2 */
5316   {
5317     FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
5318     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
5319   },
5320 /* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
5321   {
5322     FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
5323     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
5324   },
5325 /* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
5326   {
5327     FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
5328     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
5329   },
5330 /* fdcmps$pack $FRi,$FRj,$FCCi_2 */
5331   {
5332     FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
5333     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
5334   },
5335 /* fmadds$pack $FRi,$FRj,$FRk */
5336   {
5337     FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
5338     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5339   },
5340 /* fmsubs$pack $FRi,$FRj,$FRk */
5341   {
5342     FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
5343     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5344   },
5345 /* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5346   {
5347     FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
5348     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5349   },
5350 /* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5351   {
5352     FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
5353     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5354   },
5355 /* fdmadds$pack $FRi,$FRj,$FRk */
5356   {
5357     FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
5358     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5359   },
5360 /* nfdmadds$pack $FRi,$FRj,$FRk */
5361   {
5362     FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
5363     { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5364   },
5365 /* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
5366   {
5367     FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
5368     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5369   },
5370 /* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5371   {
5372     FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
5373     { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5374   },
5375 /* nfmadds$pack $FRi,$FRj,$FRk */
5376   {
5377     FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
5378     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5379   },
5380 /* nfmsubs$pack $FRi,$FRj,$FRk */
5381   {
5382     FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
5383     { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5384   },
5385 /* fmas$pack $FRi,$FRj,$FRk */
5386   {
5387     FRV_INSN_FMAS, "fmas", "fmas", 32,
5388     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
5389   },
5390 /* fmss$pack $FRi,$FRj,$FRk */
5391   {
5392     FRV_INSN_FMSS, "fmss", "fmss", 32,
5393     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
5394   },
5395 /* fdmas$pack $FRi,$FRj,$FRk */
5396   {
5397     FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
5398     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5399   },
5400 /* fdmss$pack $FRi,$FRj,$FRk */
5401   {
5402     FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
5403     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5404   },
5405 /* nfdmas$pack $FRi,$FRj,$FRk */
5406   {
5407     FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
5408     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5409   },
5410 /* nfdmss$pack $FRi,$FRj,$FRk */
5411   {
5412     FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
5413     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5414   },
5415 /* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
5416   {
5417     FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
5418     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
5419   },
5420 /* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
5421   {
5422     FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
5423     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
5424   },
5425 /* fmad$pack $FRi,$FRj,$FRk */
5426   {
5427     FRV_INSN_FMAD, "fmad", "fmad", 32,
5428     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5429   },
5430 /* fmsd$pack $FRi,$FRj,$FRk */
5431   {
5432     FRV_INSN_FMSD, "fmsd", "fmsd", 32,
5433     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
5434   },
5435 /* nfmas$pack $FRi,$FRj,$FRk */
5436   {
5437     FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
5438     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
5439   },
5440 /* nfmss$pack $FRi,$FRj,$FRk */
5441   {
5442     FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
5443     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
5444   },
5445 /* fdadds$pack $FRi,$FRj,$FRk */
5446   {
5447     FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
5448     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
5449   },
5450 /* fdsubs$pack $FRi,$FRj,$FRk */
5451   {
5452     FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
5453     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
5454   },
5455 /* fdmuls$pack $FRi,$FRj,$FRk */
5456   {
5457     FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
5458     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
5459   },
5460 /* fddivs$pack $FRi,$FRj,$FRk */
5461   {
5462     FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
5463     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
5464   },
5465 /* fdsads$pack $FRi,$FRj,$FRk */
5466   {
5467     FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
5468     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
5469   },
5470 /* fdmulcs$pack $FRi,$FRj,$FRk */
5471   {
5472     FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
5473     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
5474   },
5475 /* nfdmulcs$pack $FRi,$FRj,$FRk */
5476   {
5477     FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
5478     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
5479   },
5480 /* nfdadds$pack $FRi,$FRj,$FRk */
5481   {
5482     FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
5483     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
5484   },
5485 /* nfdsubs$pack $FRi,$FRj,$FRk */
5486   {
5487     FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
5488     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
5489   },
5490 /* nfdmuls$pack $FRi,$FRj,$FRk */
5491   {
5492     FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
5493     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
5494   },
5495 /* nfddivs$pack $FRi,$FRj,$FRk */
5496   {
5497     FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
5498     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
5499   },
5500 /* nfdsads$pack $FRi,$FRj,$FRk */
5501   {
5502     FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
5503     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
5504   },
5505 /* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
5506   {
5507     FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
5508     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_NONE } }
5509   },
5510 /* mhsetlos$pack $u12,$FRklo */
5511   {
5512     FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
5513     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
5514   },
5515 /* mhsethis$pack $u12,$FRkhi */
5516   {
5517     FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
5518     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
5519   },
5520 /* mhdsets$pack $u12,$FRintk */
5521   {
5522     FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
5523     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
5524   },
5525 /* mhsetloh$pack $s5,$FRklo */
5526   {
5527     FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
5528     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
5529   },
5530 /* mhsethih$pack $s5,$FRkhi */
5531   {
5532     FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
5533     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
5534   },
5535 /* mhdseth$pack $s5,$FRintk */
5536   {
5537     FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
5538     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
5539   },
5540 /* mand$pack $FRinti,$FRintj,$FRintk */
5541   {
5542     FRV_INSN_MAND, "mand", "mand", 32,
5543     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5544   },
5545 /* mor$pack $FRinti,$FRintj,$FRintk */
5546   {
5547     FRV_INSN_MOR, "mor", "mor", 32,
5548     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5549   },
5550 /* mxor$pack $FRinti,$FRintj,$FRintk */
5551   {
5552     FRV_INSN_MXOR, "mxor", "mxor", 32,
5553     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5554   },
5555 /* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5556   {
5557     FRV_INSN_CMAND, "cmand", "cmand", 32,
5558     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5559   },
5560 /* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5561   {
5562     FRV_INSN_CMOR, "cmor", "cmor", 32,
5563     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5564   },
5565 /* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5566   {
5567     FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
5568     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5569   },
5570 /* mnot$pack $FRintj,$FRintk */
5571   {
5572     FRV_INSN_MNOT, "mnot", "mnot", 32,
5573     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5574   },
5575 /* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
5576   {
5577     FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
5578     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5579   },
5580 /* mrotli$pack $FRinti,$u6,$FRintk */
5581   {
5582     FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
5583     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5584   },
5585 /* mrotri$pack $FRinti,$u6,$FRintk */
5586   {
5587     FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
5588     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5589   },
5590 /* mwcut$pack $FRinti,$FRintj,$FRintk */
5591   {
5592     FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
5593     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5594   },
5595 /* mwcuti$pack $FRinti,$u6,$FRintk */
5596   {
5597     FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
5598     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5599   },
5600 /* mcut$pack $ACC40Si,$FRintj,$FRintk */
5601   {
5602     FRV_INSN_MCUT, "mcut", "mcut", 32,
5603     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5604   },
5605 /* mcuti$pack $ACC40Si,$s6,$FRintk */
5606   {
5607     FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
5608     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5609   },
5610 /* mcutss$pack $ACC40Si,$FRintj,$FRintk */
5611   {
5612     FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
5613     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5614   },
5615 /* mcutssi$pack $ACC40Si,$s6,$FRintk */
5616   {
5617     FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
5618     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5619   },
5620 /* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */
5621   {
5622     FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
5623     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDCUTSSI, FR400_MAJOR_M_2, FR450_MAJOR_M_6, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
5624   },
5625 /* maveh$pack $FRinti,$FRintj,$FRintk */
5626   {
5627     FRV_INSN_MAVEH, "maveh", "maveh", 32,
5628     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5629   },
5630 /* msllhi$pack $FRinti,$u6,$FRintk */
5631   {
5632     FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
5633     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5634   },
5635 /* msrlhi$pack $FRinti,$u6,$FRintk */
5636   {
5637     FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
5638     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5639   },
5640 /* msrahi$pack $FRinti,$u6,$FRintk */
5641   {
5642     FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
5643     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
5644   },
5645 /* mdrotli$pack $FRintieven,$s6,$FRintkeven */
5646   {
5647     FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
5648     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
5649   },
5650 /* mcplhi$pack $FRinti,$u6,$FRintk */
5651   {
5652     FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
5653     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
5654   },
5655 /* mcpli$pack $FRinti,$u6,$FRintk */
5656   {
5657     FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
5658     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
5659   },
5660 /* msaths$pack $FRinti,$FRintj,$FRintk */
5661   {
5662     FRV_INSN_MSATHS, "msaths", "msaths", 32,
5663     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5664   },
5665 /* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
5666   {
5667     FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
5668     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
5669   },
5670 /* msathu$pack $FRinti,$FRintj,$FRintk */
5671   {
5672     FRV_INSN_MSATHU, "msathu", "msathu", 32,
5673     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5674   },
5675 /* mcmpsh$pack $FRinti,$FRintj,$FCCk */
5676   {
5677     FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
5678     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5679   },
5680 /* mcmpuh$pack $FRinti,$FRintj,$FCCk */
5681   {
5682     FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
5683     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5684   },
5685 /* mabshs$pack $FRintj,$FRintk */
5686   {
5687     FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
5688     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
5689   },
5690 /* maddhss$pack $FRinti,$FRintj,$FRintk */
5691   {
5692     FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
5693     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5694   },
5695 /* maddhus$pack $FRinti,$FRintj,$FRintk */
5696   {
5697     FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
5698     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5699   },
5700 /* msubhss$pack $FRinti,$FRintj,$FRintk */
5701   {
5702     FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
5703     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5704   },
5705 /* msubhus$pack $FRinti,$FRintj,$FRintk */
5706   {
5707     FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
5708     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5709   },
5710 /* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5711   {
5712     FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
5713     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5714   },
5715 /* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5716   {
5717     FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
5718     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5719   },
5720 /* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5721   {
5722     FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
5723     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5724   },
5725 /* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5726   {
5727     FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
5728     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5729   },
5730 /* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */
5731   {
5732     FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
5733     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5734   },
5735 /* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */
5736   {
5737     FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
5738     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5739   },
5740 /* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */
5741   {
5742     FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
5743     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5744   },
5745 /* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */
5746   {
5747     FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
5748     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5749   },
5750 /* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5751   {
5752     FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
5753     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5754   },
5755 /* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5756   {
5757     FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
5758     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5759   },
5760 /* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5761   {
5762     FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
5763     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5764   },
5765 /* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5766   {
5767     FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
5768     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
5769   },
5770 /* mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */
5771   {
5772     FRV_INSN_MQLCLRHS, "mqlclrhs", "mqlclrhs", 32,
5773     { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
5774   },
5775 /* mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */
5776   {
5777     FRV_INSN_MQLMTHS, "mqlmths", "mqlmths", 32,
5778     { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
5779   },
5780 /* mqsllhi$pack $FRintieven,$u6,$FRintkeven */
5781   {
5782     FRV_INSN_MQSLLHI, "mqsllhi", "mqsllhi", 32,
5783     { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
5784   },
5785 /* mqsrahi$pack $FRintieven,$u6,$FRintkeven */
5786   {
5787     FRV_INSN_MQSRAHI, "mqsrahi", "mqsrahi", 32,
5788     { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
5789   },
5790 /* maddaccs$pack $ACC40Si,$ACC40Sk */
5791   {
5792     FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
5793     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
5794   },
5795 /* msubaccs$pack $ACC40Si,$ACC40Sk */
5796   {
5797     FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
5798     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
5799   },
5800 /* mdaddaccs$pack $ACC40Si,$ACC40Sk */
5801   {
5802     FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
5803     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
5804   },
5805 /* mdsubaccs$pack $ACC40Si,$ACC40Sk */
5806   {
5807     FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
5808     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
5809   },
5810 /* masaccs$pack $ACC40Si,$ACC40Sk */
5811   {
5812     FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
5813     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
5814   },
5815 /* mdasaccs$pack $ACC40Si,$ACC40Sk */
5816   {
5817     FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
5818     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
5819   },
5820 /* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
5821   {
5822     FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
5823     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5824   },
5825 /* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
5826   {
5827     FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
5828     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5829   },
5830 /* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
5831   {
5832     FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
5833     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5834   },
5835 /* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
5836   {
5837     FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
5838     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5839   },
5840 /* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5841   {
5842     FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
5843     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5844   },
5845 /* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5846   {
5847     FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
5848     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5849   },
5850 /* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5851   {
5852     FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
5853     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5854   },
5855 /* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
5856   {
5857     FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
5858     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5859   },
5860 /* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5861   {
5862     FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
5863     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5864   },
5865 /* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
5866   {
5867     FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
5868     { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5869   },
5870 /* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
5871   {
5872     FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
5873     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5874   },
5875 /* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
5876   {
5877     FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
5878     { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5879   },
5880 /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
5881   {
5882     FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
5883     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5884   },
5885 /* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
5886   {
5887     FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
5888     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5889   },
5890 /* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
5891   {
5892     FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
5893     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5894   },
5895 /* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
5896   {
5897     FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
5898     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5899   },
5900 /* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5901   {
5902     FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
5903     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5904   },
5905 /* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
5906   {
5907     FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
5908     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5909   },
5910 /* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5911   {
5912     FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
5913     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5914   },
5915 /* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */
5916   {
5917     FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
5918     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5919   },
5920 /* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
5921   {
5922     FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
5923     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5924   },
5925 /* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */
5926   {
5927     FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
5928     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5929   },
5930 /* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5931   {
5932     FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
5933     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
5934   },
5935 /* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5936   {
5937     FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
5938     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
5939   },
5940 /* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5941   {
5942     FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
5943     { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
5944   },
5945 /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
5946   {
5947     FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
5948     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5949   },
5950 /* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
5951   {
5952     FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
5953     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5954   },
5955 /* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
5956   {
5957     FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
5958     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5959   },
5960 /* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
5961   {
5962     FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
5963     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5964   },
5965 /* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5966   {
5967     FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
5968     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5969   },
5970 /* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5971   {
5972     FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
5973     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5974   },
5975 /* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5976   {
5977     FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
5978     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5979   },
5980 /* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5981   {
5982     FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
5983     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5984   },
5985 /* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5986   {
5987     FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
5988     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5989   },
5990 /* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */
5991   {
5992     FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
5993     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5994   },
5995 /* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */
5996   {
5997     FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
5998     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
5999   },
6000 /* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */
6001   {
6002     FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
6003     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
6004   },
6005 /* mexpdhw$pack $FRinti,$u6,$FRintk */
6006   {
6007     FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
6008     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6009   },
6010 /* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
6011   {
6012     FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
6013     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6014   },
6015 /* mexpdhd$pack $FRinti,$u6,$FRintkeven */
6016   {
6017     FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
6018     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6019   },
6020 /* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */
6021   {
6022     FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
6023     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6024   },
6025 /* mpackh$pack $FRinti,$FRintj,$FRintk */
6026   {
6027     FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
6028     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6029   },
6030 /* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */
6031   {
6032     FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
6033     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_5, FR550_MAJOR_M_3 } }
6034   },
6035 /* munpackh$pack $FRinti,$FRintkeven */
6036   {
6037     FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
6038     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6039   },
6040 /* mdunpackh$pack $FRintieven,$FRintk */
6041   {
6042     FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
6043     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
6044   },
6045 /* mbtoh$pack $FRintj,$FRintkeven */
6046   {
6047     FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
6048     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6049   },
6050 /* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */
6051   {
6052     FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
6053     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6054   },
6055 /* mhtob$pack $FRintjeven,$FRintk */
6056   {
6057     FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
6058     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6059   },
6060 /* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */
6061   {
6062     FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
6063     { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6064   },
6065 /* mbtohe$pack $FRintj,$FRintk */
6066   {
6067     FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
6068     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
6069   },
6070 /* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
6071   {
6072     FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
6073     { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
6074   },
6075 /* mnop$pack */
6076   {
6077     FRV_INSN_MNOP, "mnop", "mnop", 32,
6078     { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_1 } }
6079   },
6080 /* mclracc$pack $ACC40Sk,$A0 */
6081   {
6082     FRV_INSN_MCLRACC_0, "mclracc-0", "mclracc", 32,
6083     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
6084   },
6085 /* mclracc$pack $ACC40Sk,$A1 */
6086   {
6087     FRV_INSN_MCLRACC_1, "mclracc-1", "mclracc", 32,
6088     { 0, { (1<<MACH_BASE), UNIT_MCLRACC_1, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_6, FR550_MAJOR_M_3 } }
6089   },
6090 /* mrdacc$pack $ACC40Si,$FRintk */
6091   {
6092     FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
6093     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6094   },
6095 /* mrdaccg$pack $ACCGi,$FRintk */
6096   {
6097     FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
6098     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
6099   },
6100 /* mwtacc$pack $FRinti,$ACC40Sk */
6101   {
6102     FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
6103     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
6104   },
6105 /* mwtaccg$pack $FRinti,$ACCGk */
6106   {
6107     FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
6108     { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
6109   },
6110 /* mcop1$pack $FRi,$FRj,$FRk */
6111   {
6112     FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
6113     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
6114   },
6115 /* mcop2$pack $FRi,$FRj,$FRk */
6116   {
6117     FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
6118     { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
6119   },
6120 /* fnop$pack */
6121   {
6122     FRV_INSN_FNOP, "fnop", "fnop", 32,
6123     { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_8, FR550_MAJOR_F_1 } }
6124   },
6125 };
6126
6127 #undef OP
6128 #undef A
6129
6130 /* Initialize anything needed to be done once, before any cpu_open call.  */
6131 static void init_tables PARAMS ((void));
6132
6133 static void
6134 init_tables ()
6135 {
6136 }
6137
6138 static const CGEN_MACH * lookup_mach_via_bfd_name
6139   PARAMS ((const CGEN_MACH *, const char *));
6140 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
6141 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
6142 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
6143 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
6144 static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
6145
6146 /* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name.  */
6147
6148 static const CGEN_MACH *
6149 lookup_mach_via_bfd_name (table, name)
6150      const CGEN_MACH *table;
6151      const char *name;
6152 {
6153   while (table->name)
6154     {
6155       if (strcmp (name, table->bfd_name) == 0)
6156         return table;
6157       ++table;
6158     }
6159   abort ();
6160 }
6161
6162 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
6163
6164 static void
6165 build_hw_table (cd)
6166      CGEN_CPU_TABLE *cd;
6167 {
6168   int i;
6169   int machs = cd->machs;
6170   const CGEN_HW_ENTRY *init = & frv_cgen_hw_table[0];
6171   /* MAX_HW is only an upper bound on the number of selected entries.
6172      However each entry is indexed by it's enum so there can be holes in
6173      the table.  */
6174   const CGEN_HW_ENTRY **selected =
6175     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
6176
6177   cd->hw_table.init_entries = init;
6178   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
6179   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
6180   /* ??? For now we just use machs to determine which ones we want.  */
6181   for (i = 0; init[i].name != NULL; ++i)
6182     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
6183         & machs)
6184       selected[init[i].type] = &init[i];
6185   cd->hw_table.entries = selected;
6186   cd->hw_table.num_entries = MAX_HW;
6187 }
6188
6189 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
6190
6191 static void
6192 build_ifield_table (cd)
6193      CGEN_CPU_TABLE *cd;
6194 {
6195   cd->ifld_table = & frv_cgen_ifld_table[0];
6196 }
6197
6198 /* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
6199
6200 static void
6201 build_operand_table (cd)
6202      CGEN_CPU_TABLE *cd;
6203 {
6204   int i;
6205   int machs = cd->machs;
6206   const CGEN_OPERAND *init = & frv_cgen_operand_table[0];
6207   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
6208      However each entry is indexed by it's enum so there can be holes in
6209      the table.  */
6210   const CGEN_OPERAND **selected =
6211     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6212
6213   cd->operand_table.init_entries = init;
6214   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
6215   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6216   /* ??? For now we just use mach to determine which ones we want.  */
6217   for (i = 0; init[i].name != NULL; ++i)
6218     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
6219         & machs)
6220       selected[init[i].type] = &init[i];
6221   cd->operand_table.entries = selected;
6222   cd->operand_table.num_entries = MAX_OPERANDS;
6223 }
6224
6225 /* Subroutine of frv_cgen_cpu_open to build the hardware table.
6226    ??? This could leave out insns not supported by the specified mach/isa,
6227    but that would cause errors like "foo only supported by bar" to become
6228    "unknown insn", so for now we include all insns and require the app to
6229    do the checking later.
6230    ??? On the other hand, parsing of such insns may require their hardware or
6231    operand elements to be in the table [which they mightn't be].  */
6232
6233 static void
6234 build_insn_table (cd)
6235      CGEN_CPU_TABLE *cd;
6236 {
6237   int i;
6238   const CGEN_IBASE *ib = & frv_cgen_insn_table[0];
6239   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
6240
6241   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
6242   for (i = 0; i < MAX_INSNS; ++i)
6243     insns[i].base = &ib[i];
6244   cd->insn_table.init_entries = insns;
6245   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
6246   cd->insn_table.num_init_entries = MAX_INSNS;
6247 }
6248
6249 /* Subroutine of frv_cgen_cpu_open to rebuild the tables.  */
6250
6251 static void
6252 frv_cgen_rebuild_tables (cd)
6253      CGEN_CPU_TABLE *cd;
6254 {
6255   int i;
6256   unsigned int isas = cd->isas;
6257   unsigned int machs = cd->machs;
6258
6259   cd->int_insn_p = CGEN_INT_INSN_P;
6260
6261   /* Data derived from the isa spec.  */
6262 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
6263   cd->default_insn_bitsize = UNSET;
6264   cd->base_insn_bitsize = UNSET;
6265   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
6266   cd->max_insn_bitsize = 0;
6267   for (i = 0; i < MAX_ISAS; ++i)
6268     if (((1 << i) & isas) != 0)
6269       {
6270         const CGEN_ISA *isa = & frv_cgen_isa_table[i];
6271
6272         /* Default insn sizes of all selected isas must be
6273            equal or we set the result to 0, meaning "unknown".  */
6274         if (cd->default_insn_bitsize == UNSET)
6275           cd->default_insn_bitsize = isa->default_insn_bitsize;
6276         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
6277           ; /* this is ok */
6278         else
6279           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
6280
6281         /* Base insn sizes of all selected isas must be equal
6282            or we set the result to 0, meaning "unknown".  */
6283         if (cd->base_insn_bitsize == UNSET)
6284           cd->base_insn_bitsize = isa->base_insn_bitsize;
6285         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
6286           ; /* this is ok */
6287         else
6288           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
6289
6290         /* Set min,max insn sizes.  */
6291         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
6292           cd->min_insn_bitsize = isa->min_insn_bitsize;
6293         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
6294           cd->max_insn_bitsize = isa->max_insn_bitsize;
6295       }
6296
6297   /* Data derived from the mach spec.  */
6298   for (i = 0; i < MAX_MACHS; ++i)
6299     if (((1 << i) & machs) != 0)
6300       {
6301         const CGEN_MACH *mach = & frv_cgen_mach_table[i];
6302
6303         if (mach->insn_chunk_bitsize != 0)
6304         {
6305           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
6306             {
6307               fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
6308                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
6309               abort ();
6310             }
6311
6312           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
6313         }
6314       }
6315
6316   /* Determine which hw elements are used by MACH.  */
6317   build_hw_table (cd);
6318
6319   /* Build the ifield table.  */
6320   build_ifield_table (cd);
6321
6322   /* Determine which operands are used by MACH/ISA.  */
6323   build_operand_table (cd);
6324
6325   /* Build the instruction table.  */
6326   build_insn_table (cd);
6327 }
6328
6329 /* Initialize a cpu table and return a descriptor.
6330    It's much like opening a file, and must be the first function called.
6331    The arguments are a set of (type/value) pairs, terminated with
6332    CGEN_CPU_OPEN_END.
6333
6334    Currently supported values:
6335    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
6336    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
6337    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
6338    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
6339    CGEN_CPU_OPEN_END:     terminates arguments
6340
6341    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
6342    precluded.
6343
6344    ??? We only support ISO C stdargs here, not K&R.
6345    Laziness, plus experiment to see if anything requires K&R - eventually
6346    K&R will no longer be supported - e.g. GDB is currently trying this.  */
6347
6348 CGEN_CPU_DESC
6349 frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
6350 {
6351   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
6352   static int init_p;
6353   unsigned int isas = 0;  /* 0 = "unspecified" */
6354   unsigned int machs = 0; /* 0 = "unspecified" */
6355   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
6356   va_list ap;
6357
6358   if (! init_p)
6359     {
6360       init_tables ();
6361       init_p = 1;
6362     }
6363
6364   memset (cd, 0, sizeof (*cd));
6365
6366   va_start (ap, arg_type);
6367   while (arg_type != CGEN_CPU_OPEN_END)
6368     {
6369       switch (arg_type)
6370         {
6371         case CGEN_CPU_OPEN_ISAS :
6372           isas = va_arg (ap, unsigned int);
6373           break;
6374         case CGEN_CPU_OPEN_MACHS :
6375           machs = va_arg (ap, unsigned int);
6376           break;
6377         case CGEN_CPU_OPEN_BFDMACH :
6378           {
6379             const char *name = va_arg (ap, const char *);
6380             const CGEN_MACH *mach =
6381               lookup_mach_via_bfd_name (frv_cgen_mach_table, name);
6382
6383             machs |= 1 << mach->num;
6384             break;
6385           }
6386         case CGEN_CPU_OPEN_ENDIAN :
6387           endian = va_arg (ap, enum cgen_endian);
6388           break;
6389         default :
6390           fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n",
6391                    arg_type);
6392           abort (); /* ??? return NULL? */
6393         }
6394       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
6395     }
6396   va_end (ap);
6397
6398   /* mach unspecified means "all" */
6399   if (machs == 0)
6400     machs = (1 << MAX_MACHS) - 1;
6401   /* base mach is always selected */
6402   machs |= 1;
6403   /* isa unspecified means "all" */
6404   if (isas == 0)
6405     isas = (1 << MAX_ISAS) - 1;
6406   if (endian == CGEN_ENDIAN_UNKNOWN)
6407     {
6408       /* ??? If target has only one, could have a default.  */
6409       fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n");
6410       abort ();
6411     }
6412
6413   cd->isas = isas;
6414   cd->machs = machs;
6415   cd->endian = endian;
6416   /* FIXME: for the sparc case we can determine insn-endianness statically.
6417      The worry here is where both data and insn endian can be independently
6418      chosen, in which case this function will need another argument.
6419      Actually, will want to allow for more arguments in the future anyway.  */
6420   cd->insn_endian = endian;
6421
6422   /* Table (re)builder.  */
6423   cd->rebuild_tables = frv_cgen_rebuild_tables;
6424   frv_cgen_rebuild_tables (cd);
6425
6426   /* Default to not allowing signed overflow.  */
6427   cd->signed_overflow_ok_p = 0;
6428
6429   return (CGEN_CPU_DESC) cd;
6430 }
6431
6432 /* Cover fn to frv_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
6433    MACH_NAME is the bfd name of the mach.  */
6434
6435 CGEN_CPU_DESC
6436 frv_cgen_cpu_open_1 (mach_name, endian)
6437      const char *mach_name;
6438      enum cgen_endian endian;
6439 {
6440   return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
6441                                CGEN_CPU_OPEN_ENDIAN, endian,
6442                                CGEN_CPU_OPEN_END);
6443 }
6444
6445 /* Close a cpu table.
6446    ??? This can live in a machine independent file, but there's currently
6447    no place to put this file (there's no libcgen).  libopcodes is the wrong
6448    place as some simulator ports use this but they don't use libopcodes.  */
6449
6450 void
6451 frv_cgen_cpu_close (cd)
6452      CGEN_CPU_DESC cd;
6453 {
6454   unsigned int i;
6455   const CGEN_INSN *insns;
6456
6457   if (cd->macro_insn_table.init_entries)
6458     {
6459       insns = cd->macro_insn_table.init_entries;
6460       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
6461         {
6462           if (CGEN_INSN_RX ((insns)))
6463             regfree (CGEN_INSN_RX (insns));
6464         }
6465     }
6466
6467   if (cd->insn_table.init_entries)
6468     {
6469       insns = cd->insn_table.init_entries;
6470       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
6471         {
6472           if (CGEN_INSN_RX (insns))
6473             regfree (CGEN_INSN_RX (insns));
6474         }
6475     }
6476
6477
6478
6479   if (cd->macro_insn_table.init_entries)
6480     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
6481
6482   if (cd->insn_table.init_entries)
6483     free ((CGEN_INSN *) cd->insn_table.init_entries);
6484
6485   if (cd->hw_table.entries)
6486     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
6487
6488   if (cd->operand_table.entries)
6489     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
6490
6491   free (cd);
6492 }
6493