3 { "vmovupX", { XM
, EXEvexXNoBcst
}, PREFIX_OPCODE
},
4 { VEX_W_TABLE (EVEX_W_0F10_P_1
) },
5 { "vmovupX", { XM
, EXEvexXNoBcst
}, PREFIX_OPCODE
},
6 { VEX_W_TABLE (EVEX_W_0F10_P_3
) },
10 { "vmovupX", { EXxS
, XM
}, PREFIX_OPCODE
},
11 { VEX_W_TABLE (EVEX_W_0F11_P_1
) },
12 { "vmovupX", { EXxS
, XM
}, PREFIX_OPCODE
},
13 { VEX_W_TABLE (EVEX_W_0F11_P_3
) },
15 /* PREFIX_EVEX_0F12 */
17 { MOD_TABLE (MOD_EVEX_0F12_PREFIX_0
) },
18 { VEX_W_TABLE (EVEX_W_0F12_P_1
) },
19 { MOD_TABLE (MOD_EVEX_0F12_PREFIX_2
) },
20 { VEX_W_TABLE (EVEX_W_0F12_P_3
) },
22 /* PREFIX_EVEX_0F16 */
24 { MOD_TABLE (MOD_EVEX_0F16_PREFIX_0
) },
25 { VEX_W_TABLE (EVEX_W_0F16_P_1
) },
26 { MOD_TABLE (MOD_EVEX_0F16_PREFIX_2
) },
28 /* PREFIX_EVEX_0F2A */
31 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
33 { VEX_W_TABLE (EVEX_W_0F2A_P_3
) },
35 /* PREFIX_EVEX_0F2C */
38 { "vcvttss2si", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
40 { "vcvttsd2si", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
42 /* PREFIX_EVEX_0F2D */
45 { "vcvtss2si", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
47 { "vcvtsd2si", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
49 /* PREFIX_EVEX_0F2E */
51 { "vucomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
53 { "vucomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
55 /* PREFIX_EVEX_0F2F */
57 { "vcomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
59 { "vcomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
61 /* PREFIX_EVEX_0F51 */
63 { "vsqrtpX", { XM
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
64 { VEX_W_TABLE (EVEX_W_0F51_P_1
) },
65 { "vsqrtpX", { XM
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
66 { VEX_W_TABLE (EVEX_W_0F51_P_3
) },
68 /* PREFIX_EVEX_0F58 */
70 { "vaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
71 { VEX_W_TABLE (EVEX_W_0F58_P_1
) },
72 { "vaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
73 { VEX_W_TABLE (EVEX_W_0F58_P_3
) },
75 /* PREFIX_EVEX_0F59 */
77 { "vmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
78 { VEX_W_TABLE (EVEX_W_0F59_P_1
) },
79 { "vmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
80 { VEX_W_TABLE (EVEX_W_0F59_P_3
) },
82 /* PREFIX_EVEX_0F5A */
84 { VEX_W_TABLE (EVEX_W_0F5A_P_0
) },
85 { VEX_W_TABLE (EVEX_W_0F5A_P_1
) },
86 { VEX_W_TABLE (EVEX_W_0F5A_P_2
) },
87 { VEX_W_TABLE (EVEX_W_0F5A_P_3
) },
89 /* PREFIX_EVEX_0F5B */
91 { VEX_W_TABLE (EVEX_W_0F5B_P_0
) },
92 { VEX_W_TABLE (EVEX_W_0F5B_P_1
) },
93 { VEX_W_TABLE (EVEX_W_0F5B_P_2
) },
95 /* PREFIX_EVEX_0F5C */
97 { "vsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
98 { VEX_W_TABLE (EVEX_W_0F5C_P_1
) },
99 { "vsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
100 { VEX_W_TABLE (EVEX_W_0F5C_P_3
) },
102 /* PREFIX_EVEX_0F5D */
104 { "vminpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
105 { VEX_W_TABLE (EVEX_W_0F5D_P_1
) },
106 { "vminpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
107 { VEX_W_TABLE (EVEX_W_0F5D_P_3
) },
109 /* PREFIX_EVEX_0F5E */
111 { "vdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
112 { VEX_W_TABLE (EVEX_W_0F5E_P_1
) },
113 { "vdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
114 { VEX_W_TABLE (EVEX_W_0F5E_P_3
) },
116 /* PREFIX_EVEX_0F5F */
118 { "vmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
119 { VEX_W_TABLE (EVEX_W_0F5F_P_1
) },
120 { "vmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
121 { VEX_W_TABLE (EVEX_W_0F5F_P_3
) },
123 /* PREFIX_EVEX_0F60 */
127 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
129 /* PREFIX_EVEX_0F61 */
133 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
135 /* PREFIX_EVEX_0F62 */
139 { VEX_W_TABLE (EVEX_W_0F62_P_2
) },
141 /* PREFIX_EVEX_0F63 */
145 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
147 /* PREFIX_EVEX_0F64 */
151 { "vpcmpgtb", { XMask
, Vex
, EXx
}, 0 },
153 /* PREFIX_EVEX_0F65 */
157 { "vpcmpgtw", { XMask
, Vex
, EXx
}, 0 },
159 /* PREFIX_EVEX_0F66 */
163 { VEX_W_TABLE (EVEX_W_0F66_P_2
) },
165 /* PREFIX_EVEX_0F67 */
169 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
171 /* PREFIX_EVEX_0F68 */
175 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
177 /* PREFIX_EVEX_0F69 */
181 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
183 /* PREFIX_EVEX_0F6A */
187 { VEX_W_TABLE (EVEX_W_0F6A_P_2
) },
189 /* PREFIX_EVEX_0F6B */
193 { VEX_W_TABLE (EVEX_W_0F6B_P_2
) },
195 /* PREFIX_EVEX_0F6C */
199 { VEX_W_TABLE (EVEX_W_0F6C_P_2
) },
201 /* PREFIX_EVEX_0F6D */
205 { VEX_W_TABLE (EVEX_W_0F6D_P_2
) },
207 /* PREFIX_EVEX_0F6E */
211 { EVEX_LEN_TABLE (EVEX_LEN_0F6E_P_2
) },
213 /* PREFIX_EVEX_0F6F */
216 { VEX_W_TABLE (EVEX_W_0F6F_P_1
) },
217 { VEX_W_TABLE (EVEX_W_0F6F_P_2
) },
218 { VEX_W_TABLE (EVEX_W_0F6F_P_3
) },
220 /* PREFIX_EVEX_0F70 */
223 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
224 { VEX_W_TABLE (EVEX_W_0F70_P_2
) },
225 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
227 /* PREFIX_EVEX_0F71_REG_2 */
231 { "vpsrlw", { Vex
, EXx
, Ib
}, 0 },
233 /* PREFIX_EVEX_0F71_REG_4 */
237 { "vpsraw", { Vex
, EXx
, Ib
}, 0 },
239 /* PREFIX_EVEX_0F71_REG_6 */
243 { "vpsllw", { Vex
, EXx
, Ib
}, 0 },
245 /* PREFIX_EVEX_0F72_REG_0 */
249 { "vpror%LW", { Vex
, EXx
, Ib
}, 0 },
251 /* PREFIX_EVEX_0F72_REG_1 */
255 { "vprol%LW", { Vex
, EXx
, Ib
}, 0 },
257 /* PREFIX_EVEX_0F72_REG_2 */
261 { VEX_W_TABLE (EVEX_W_0F72_R_2_P_2
) },
263 /* PREFIX_EVEX_0F72_REG_4 */
267 { "vpsra%LW", { Vex
, EXx
, Ib
}, 0 },
269 /* PREFIX_EVEX_0F72_REG_6 */
273 { VEX_W_TABLE (EVEX_W_0F72_R_6_P_2
) },
275 /* PREFIX_EVEX_0F73_REG_2 */
279 { VEX_W_TABLE (EVEX_W_0F73_R_2_P_2
) },
281 /* PREFIX_EVEX_0F73_REG_3 */
285 { "vpsrldq", { Vex
, EXx
, Ib
}, 0 },
287 /* PREFIX_EVEX_0F73_REG_6 */
291 { VEX_W_TABLE (EVEX_W_0F73_R_6_P_2
) },
293 /* PREFIX_EVEX_0F73_REG_7 */
297 { "vpslldq", { Vex
, EXx
, Ib
}, 0 },
299 /* PREFIX_EVEX_0F74 */
303 { "vpcmpeqb", { XMask
, Vex
, EXx
}, 0 },
305 /* PREFIX_EVEX_0F75 */
309 { "vpcmpeqw", { XMask
, Vex
, EXx
}, 0 },
311 /* PREFIX_EVEX_0F76 */
315 { VEX_W_TABLE (EVEX_W_0F76_P_2
) },
317 /* PREFIX_EVEX_0F78 */
319 { VEX_W_TABLE (EVEX_W_0F78_P_0
) },
320 { "vcvttss2usi", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
321 { VEX_W_TABLE (EVEX_W_0F78_P_2
) },
322 { "vcvttsd2usi", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
324 /* PREFIX_EVEX_0F79 */
326 { VEX_W_TABLE (EVEX_W_0F79_P_0
) },
327 { "vcvtss2usi", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
328 { VEX_W_TABLE (EVEX_W_0F79_P_2
) },
329 { "vcvtsd2usi", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
331 /* PREFIX_EVEX_0F7A */
334 { VEX_W_TABLE (EVEX_W_0F7A_P_1
) },
335 { VEX_W_TABLE (EVEX_W_0F7A_P_2
) },
336 { VEX_W_TABLE (EVEX_W_0F7A_P_3
) },
338 /* PREFIX_EVEX_0F7B */
341 { "vcvtusi2ss%LQ", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
342 { VEX_W_TABLE (EVEX_W_0F7B_P_2
) },
343 { VEX_W_TABLE (EVEX_W_0F7B_P_3
) },
345 /* PREFIX_EVEX_0F7E */
348 { EVEX_LEN_TABLE (EVEX_LEN_0F7E_P_1
) },
349 { EVEX_LEN_TABLE (EVEX_LEN_0F7E_P_2
) },
351 /* PREFIX_EVEX_0F7F */
354 { VEX_W_TABLE (EVEX_W_0F7F_P_1
) },
355 { VEX_W_TABLE (EVEX_W_0F7F_P_2
) },
356 { VEX_W_TABLE (EVEX_W_0F7F_P_3
) },
358 /* PREFIX_EVEX_0FC2 */
360 { "vcmppX", { XMask
, Vex
, EXx
, EXxEVexS
, VCMP
}, PREFIX_OPCODE
},
361 { VEX_W_TABLE (EVEX_W_0FC2_P_1
) },
362 { "vcmppX", { XMask
, Vex
, EXx
, EXxEVexS
, VCMP
}, PREFIX_OPCODE
},
363 { VEX_W_TABLE (EVEX_W_0FC2_P_3
) },
365 /* PREFIX_EVEX_0FC4 */
369 { "vpinsrw", { XM
, Vex128
, Edw
, Ib
}, 0 },
371 /* PREFIX_EVEX_0FC5 */
375 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
377 /* PREFIX_EVEX_0FD1 */
381 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
383 /* PREFIX_EVEX_0FD2 */
387 { VEX_W_TABLE (EVEX_W_0FD2_P_2
) },
389 /* PREFIX_EVEX_0FD3 */
393 { VEX_W_TABLE (EVEX_W_0FD3_P_2
) },
395 /* PREFIX_EVEX_0FD4 */
399 { VEX_W_TABLE (EVEX_W_0FD4_P_2
) },
401 /* PREFIX_EVEX_0FD5 */
405 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
407 /* PREFIX_EVEX_0FD6 */
411 { EVEX_LEN_TABLE (EVEX_LEN_0FD6_P_2
) },
413 /* PREFIX_EVEX_0FD8 */
417 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
419 /* PREFIX_EVEX_0FD9 */
423 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
425 /* PREFIX_EVEX_0FDA */
429 { "vpminub", { XM
, Vex
, EXx
}, 0 },
431 /* PREFIX_EVEX_0FDB */
435 { "vpand%LW", { XM
, Vex
, EXx
}, 0 },
437 /* PREFIX_EVEX_0FDC */
441 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
443 /* PREFIX_EVEX_0FDD */
447 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
449 /* PREFIX_EVEX_0FDE */
453 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
455 /* PREFIX_EVEX_0FDF */
459 { "vpandn%LW", { XM
, Vex
, EXx
}, 0 },
461 /* PREFIX_EVEX_0FE0 */
465 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
467 /* PREFIX_EVEX_0FE1 */
471 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
473 /* PREFIX_EVEX_0FE2 */
477 { "vpsra%LW", { XM
, Vex
, EXxmm
}, 0 },
479 /* PREFIX_EVEX_0FE3 */
483 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
485 /* PREFIX_EVEX_0FE4 */
489 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
491 /* PREFIX_EVEX_0FE5 */
495 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
497 /* PREFIX_EVEX_0FE6 */
500 { VEX_W_TABLE (EVEX_W_0FE6_P_1
) },
501 { VEX_W_TABLE (EVEX_W_0FE6_P_2
) },
502 { VEX_W_TABLE (EVEX_W_0FE6_P_3
) },
504 /* PREFIX_EVEX_0FE7 */
508 { VEX_W_TABLE (EVEX_W_0FE7_P_2
) },
510 /* PREFIX_EVEX_0FE8 */
514 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
516 /* PREFIX_EVEX_0FE9 */
520 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
522 /* PREFIX_EVEX_0FEA */
526 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
528 /* PREFIX_EVEX_0FEB */
532 { "vpor%LW", { XM
, Vex
, EXx
}, 0 },
534 /* PREFIX_EVEX_0FEC */
538 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
540 /* PREFIX_EVEX_0FED */
544 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
546 /* PREFIX_EVEX_0FEE */
550 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
552 /* PREFIX_EVEX_0FEF */
556 { "vpxor%LW", { XM
, Vex
, EXx
}, 0 },
558 /* PREFIX_EVEX_0FF1 */
562 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
564 /* PREFIX_EVEX_0FF2 */
568 { VEX_W_TABLE (EVEX_W_0FF2_P_2
) },
570 /* PREFIX_EVEX_0FF3 */
574 { VEX_W_TABLE (EVEX_W_0FF3_P_2
) },
576 /* PREFIX_EVEX_0FF4 */
580 { VEX_W_TABLE (EVEX_W_0FF4_P_2
) },
582 /* PREFIX_EVEX_0FF5 */
586 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
588 /* PREFIX_EVEX_0FF6 */
592 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
594 /* PREFIX_EVEX_0FF8 */
598 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
600 /* PREFIX_EVEX_0FF9 */
604 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
606 /* PREFIX_EVEX_0FFA */
610 { VEX_W_TABLE (EVEX_W_0FFA_P_2
) },
612 /* PREFIX_EVEX_0FFB */
616 { VEX_W_TABLE (EVEX_W_0FFB_P_2
) },
618 /* PREFIX_EVEX_0FFC */
622 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
624 /* PREFIX_EVEX_0FFD */
628 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
630 /* PREFIX_EVEX_0FFE */
634 { VEX_W_TABLE (EVEX_W_0FFE_P_2
) },
636 /* PREFIX_EVEX_0F3800 */
640 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
642 /* PREFIX_EVEX_0F3804 */
646 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
648 /* PREFIX_EVEX_0F380B */
652 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
654 /* PREFIX_EVEX_0F380C */
658 { VEX_W_TABLE (EVEX_W_0F380C_P_2
) },
660 /* PREFIX_EVEX_0F380D */
664 { VEX_W_TABLE (EVEX_W_0F380D_P_2
) },
666 /* PREFIX_EVEX_0F3810 */
669 { VEX_W_TABLE (EVEX_W_0F3810_P_1
) },
670 { VEX_W_TABLE (EVEX_W_0F3810_P_2
) },
672 /* PREFIX_EVEX_0F3811 */
675 { VEX_W_TABLE (EVEX_W_0F3811_P_1
) },
676 { VEX_W_TABLE (EVEX_W_0F3811_P_2
) },
678 /* PREFIX_EVEX_0F3812 */
681 { VEX_W_TABLE (EVEX_W_0F3812_P_1
) },
682 { VEX_W_TABLE (EVEX_W_0F3812_P_2
) },
684 /* PREFIX_EVEX_0F3813 */
687 { VEX_W_TABLE (EVEX_W_0F3813_P_1
) },
688 { VEX_W_TABLE (EVEX_W_0F3813_P_2
) },
690 /* PREFIX_EVEX_0F3814 */
693 { VEX_W_TABLE (EVEX_W_0F3814_P_1
) },
694 { "vprorv%LW", { XM
, Vex
, EXx
}, 0 },
696 /* PREFIX_EVEX_0F3815 */
699 { VEX_W_TABLE (EVEX_W_0F3815_P_1
) },
700 { "vprolv%LW", { XM
, Vex
, EXx
}, 0 },
702 /* PREFIX_EVEX_0F3816 */
706 { "vpermp%XW", { XM
, Vex
, EXx
}, 0 },
708 /* PREFIX_EVEX_0F3818 */
712 { VEX_W_TABLE (EVEX_W_0F3818_P_2
) },
714 /* PREFIX_EVEX_0F3819 */
718 { VEX_W_TABLE (EVEX_W_0F3819_P_2
) },
720 /* PREFIX_EVEX_0F381A */
724 { VEX_W_TABLE (EVEX_W_0F381A_P_2
) },
726 /* PREFIX_EVEX_0F381B */
730 { VEX_W_TABLE (EVEX_W_0F381B_P_2
) },
732 /* PREFIX_EVEX_0F381C */
736 { "vpabsb", { XM
, EXx
}, 0 },
738 /* PREFIX_EVEX_0F381D */
742 { "vpabsw", { XM
, EXx
}, 0 },
744 /* PREFIX_EVEX_0F381E */
748 { VEX_W_TABLE (EVEX_W_0F381E_P_2
) },
750 /* PREFIX_EVEX_0F381F */
754 { VEX_W_TABLE (EVEX_W_0F381F_P_2
) },
756 /* PREFIX_EVEX_0F3820 */
759 { VEX_W_TABLE (EVEX_W_0F3820_P_1
) },
760 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
762 /* PREFIX_EVEX_0F3821 */
765 { VEX_W_TABLE (EVEX_W_0F3821_P_1
) },
766 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
768 /* PREFIX_EVEX_0F3822 */
771 { VEX_W_TABLE (EVEX_W_0F3822_P_1
) },
772 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
774 /* PREFIX_EVEX_0F3823 */
777 { VEX_W_TABLE (EVEX_W_0F3823_P_1
) },
778 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
780 /* PREFIX_EVEX_0F3824 */
783 { VEX_W_TABLE (EVEX_W_0F3824_P_1
) },
784 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
786 /* PREFIX_EVEX_0F3825 */
789 { VEX_W_TABLE (EVEX_W_0F3825_P_1
) },
790 { VEX_W_TABLE (EVEX_W_0F3825_P_2
) },
792 /* PREFIX_EVEX_0F3826 */
795 { VEX_W_TABLE (EVEX_W_0F3826_P_1
) },
796 { VEX_W_TABLE (EVEX_W_0F3826_P_2
) },
798 /* PREFIX_EVEX_0F3827 */
801 { "vptestnm%LW", { XMask
, Vex
, EXx
}, 0 },
802 { "vptestm%LW", { XMask
, Vex
, EXx
}, 0 },
804 /* PREFIX_EVEX_0F3828 */
807 { VEX_W_TABLE (EVEX_W_0F3828_P_1
) },
808 { VEX_W_TABLE (EVEX_W_0F3828_P_2
) },
810 /* PREFIX_EVEX_0F3829 */
813 { VEX_W_TABLE (EVEX_W_0F3829_P_1
) },
814 { VEX_W_TABLE (EVEX_W_0F3829_P_2
) },
816 /* PREFIX_EVEX_0F382A */
819 { VEX_W_TABLE (EVEX_W_0F382A_P_1
) },
820 { VEX_W_TABLE (EVEX_W_0F382A_P_2
) },
822 /* PREFIX_EVEX_0F382B */
826 { VEX_W_TABLE (EVEX_W_0F382B_P_2
) },
828 /* PREFIX_EVEX_0F382C */
832 { "vscalefp%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
834 /* PREFIX_EVEX_0F382D */
838 { "vscalefs%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
840 /* PREFIX_EVEX_0F3830 */
843 { VEX_W_TABLE (EVEX_W_0F3830_P_1
) },
844 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
846 /* PREFIX_EVEX_0F3831 */
849 { VEX_W_TABLE (EVEX_W_0F3831_P_1
) },
850 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
852 /* PREFIX_EVEX_0F3832 */
855 { VEX_W_TABLE (EVEX_W_0F3832_P_1
) },
856 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
858 /* PREFIX_EVEX_0F3833 */
861 { VEX_W_TABLE (EVEX_W_0F3833_P_1
) },
862 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
864 /* PREFIX_EVEX_0F3834 */
867 { VEX_W_TABLE (EVEX_W_0F3834_P_1
) },
868 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
870 /* PREFIX_EVEX_0F3835 */
873 { VEX_W_TABLE (EVEX_W_0F3835_P_1
) },
874 { VEX_W_TABLE (EVEX_W_0F3835_P_2
) },
876 /* PREFIX_EVEX_0F3836 */
880 { "vperm%LW", { XM
, Vex
, EXx
}, 0 },
882 /* PREFIX_EVEX_0F3837 */
886 { VEX_W_TABLE (EVEX_W_0F3837_P_2
) },
888 /* PREFIX_EVEX_0F3838 */
891 { VEX_W_TABLE (EVEX_W_0F3838_P_1
) },
892 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
894 /* PREFIX_EVEX_0F3839 */
897 { VEX_W_TABLE (EVEX_W_0F3839_P_1
) },
898 { "vpmins%LW", { XM
, Vex
, EXx
}, 0 },
900 /* PREFIX_EVEX_0F383A */
903 { VEX_W_TABLE (EVEX_W_0F383A_P_1
) },
904 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
906 /* PREFIX_EVEX_0F383B */
910 { "vpminu%LW", { XM
, Vex
, EXx
}, 0 },
912 /* PREFIX_EVEX_0F383C */
916 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
918 /* PREFIX_EVEX_0F383D */
922 { "vpmaxs%LW", { XM
, Vex
, EXx
}, 0 },
924 /* PREFIX_EVEX_0F383E */
928 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
930 /* PREFIX_EVEX_0F383F */
934 { "vpmaxu%LW", { XM
, Vex
, EXx
}, 0 },
936 /* PREFIX_EVEX_0F3840 */
940 { VEX_W_TABLE (EVEX_W_0F3840_P_2
) },
942 /* PREFIX_EVEX_0F3842 */
946 { "vgetexpp%XW", { XM
, EXx
, EXxEVexS
}, 0 },
948 /* PREFIX_EVEX_0F3843 */
952 { "vgetexps%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
954 /* PREFIX_EVEX_0F3844 */
958 { "vplzcnt%LW", { XM
, EXx
}, 0 },
960 /* PREFIX_EVEX_0F3845 */
964 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
966 /* PREFIX_EVEX_0F3846 */
970 { "vpsrav%LW", { XM
, Vex
, EXx
}, 0 },
972 /* PREFIX_EVEX_0F3847 */
976 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
978 /* PREFIX_EVEX_0F384C */
982 { "vrcp14p%XW", { XM
, EXx
}, 0 },
984 /* PREFIX_EVEX_0F384D */
988 { "vrcp14s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
990 /* PREFIX_EVEX_0F384E */
994 { "vrsqrt14p%XW", { XM
, EXx
}, 0 },
996 /* PREFIX_EVEX_0F384F */
1000 { "vrsqrt14s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
1002 /* PREFIX_EVEX_0F3850 */
1006 { "vpdpbusd", { XM
, Vex
, EXx
}, 0 },
1008 /* PREFIX_EVEX_0F3851 */
1012 { "vpdpbusds", { XM
, Vex
, EXx
}, 0 },
1014 /* PREFIX_EVEX_0F3852 */
1017 { VEX_W_TABLE (EVEX_W_0F3852_P_1
) },
1018 { "vpdpwssd", { XM
, Vex
, EXx
}, 0 },
1019 { "vp4dpwssd", { XM
, Vex
, EXxmm
}, 0 },
1021 /* PREFIX_EVEX_0F3853 */
1025 { "vpdpwssds", { XM
, Vex
, EXx
}, 0 },
1026 { "vp4dpwssds", { XM
, Vex
, EXxmm
}, 0 },
1028 /* PREFIX_EVEX_0F3854 */
1032 { VEX_W_TABLE (EVEX_W_0F3854_P_2
) },
1034 /* PREFIX_EVEX_0F3855 */
1038 { VEX_W_TABLE (EVEX_W_0F3855_P_2
) },
1040 /* PREFIX_EVEX_0F3858 */
1044 { VEX_W_TABLE (EVEX_W_0F3858_P_2
) },
1046 /* PREFIX_EVEX_0F3859 */
1050 { VEX_W_TABLE (EVEX_W_0F3859_P_2
) },
1052 /* PREFIX_EVEX_0F385A */
1056 { VEX_W_TABLE (EVEX_W_0F385A_P_2
) },
1058 /* PREFIX_EVEX_0F385B */
1062 { VEX_W_TABLE (EVEX_W_0F385B_P_2
) },
1064 /* PREFIX_EVEX_0F3862 */
1068 { VEX_W_TABLE (EVEX_W_0F3862_P_2
) },
1070 /* PREFIX_EVEX_0F3863 */
1074 { VEX_W_TABLE (EVEX_W_0F3863_P_2
) },
1076 /* PREFIX_EVEX_0F3864 */
1080 { "vpblendm%LW", { XM
, Vex
, EXx
}, 0 },
1082 /* PREFIX_EVEX_0F3865 */
1086 { "vblendmp%XW", { XM
, Vex
, EXx
}, 0 },
1088 /* PREFIX_EVEX_0F3866 */
1092 { VEX_W_TABLE (EVEX_W_0F3866_P_2
) },
1094 /* PREFIX_EVEX_0F3868 */
1099 { VEX_W_TABLE (EVEX_W_0F3868_P_3
) },
1101 /* PREFIX_EVEX_0F3870 */
1105 { VEX_W_TABLE (EVEX_W_0F3870_P_2
) },
1107 /* PREFIX_EVEX_0F3871 */
1111 { VEX_W_TABLE (EVEX_W_0F3871_P_2
) },
1113 /* PREFIX_EVEX_0F3872 */
1116 { VEX_W_TABLE (EVEX_W_0F3872_P_1
) },
1117 { VEX_W_TABLE (EVEX_W_0F3872_P_2
) },
1118 { VEX_W_TABLE (EVEX_W_0F3872_P_3
) },
1120 /* PREFIX_EVEX_0F3873 */
1124 { VEX_W_TABLE (EVEX_W_0F3873_P_2
) },
1126 /* PREFIX_EVEX_0F3875 */
1130 { VEX_W_TABLE (EVEX_W_0F3875_P_2
) },
1132 /* PREFIX_EVEX_0F3876 */
1136 { "vpermi2%LW", { XM
, Vex
, EXx
}, 0 },
1138 /* PREFIX_EVEX_0F3877 */
1142 { "vpermi2p%XW", { XM
, Vex
, EXx
}, 0 },
1144 /* PREFIX_EVEX_0F3878 */
1148 { VEX_W_TABLE (EVEX_W_0F3878_P_2
) },
1150 /* PREFIX_EVEX_0F3879 */
1154 { VEX_W_TABLE (EVEX_W_0F3879_P_2
) },
1156 /* PREFIX_EVEX_0F387A */
1160 { VEX_W_TABLE (EVEX_W_0F387A_P_2
) },
1162 /* PREFIX_EVEX_0F387B */
1166 { VEX_W_TABLE (EVEX_W_0F387B_P_2
) },
1168 /* PREFIX_EVEX_0F387C */
1172 { "vpbroadcastK", { XM
, Rdq
}, 0 },
1174 /* PREFIX_EVEX_0F387D */
1178 { VEX_W_TABLE (EVEX_W_0F387D_P_2
) },
1180 /* PREFIX_EVEX_0F387E */
1184 { "vpermt2%LW", { XM
, Vex
, EXx
}, 0 },
1186 /* PREFIX_EVEX_0F387F */
1190 { "vpermt2p%XW", { XM
, Vex
, EXx
}, 0 },
1192 /* PREFIX_EVEX_0F3883 */
1196 { VEX_W_TABLE (EVEX_W_0F3883_P_2
) },
1198 /* PREFIX_EVEX_0F3888 */
1202 { "vexpandp%XW", { XM
, EXEvexXGscat
}, 0 },
1204 /* PREFIX_EVEX_0F3889 */
1208 { "vpexpand%LW", { XM
, EXEvexXGscat
}, 0 },
1210 /* PREFIX_EVEX_0F388A */
1214 { "vcompressp%XW", { EXEvexXGscat
, XM
}, 0 },
1216 /* PREFIX_EVEX_0F388B */
1220 { "vpcompress%LW", { EXEvexXGscat
, XM
}, 0 },
1222 /* PREFIX_EVEX_0F388D */
1226 { VEX_W_TABLE (EVEX_W_0F388D_P_2
) },
1228 /* PREFIX_EVEX_0F388F */
1232 { "vpshufbitqmb", { XMask
, Vex
, EXx
}, 0 },
1234 /* PREFIX_EVEX_0F3890 */
1238 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
}, 0 },
1240 /* PREFIX_EVEX_0F3891 */
1244 { VEX_W_TABLE (EVEX_W_0F3891_P_2
) },
1246 /* PREFIX_EVEX_0F3892 */
1250 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
}, 0 },
1252 /* PREFIX_EVEX_0F3893 */
1256 { VEX_W_TABLE (EVEX_W_0F3893_P_2
) },
1258 /* PREFIX_EVEX_0F3896 */
1262 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1264 /* PREFIX_EVEX_0F3897 */
1268 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1270 /* PREFIX_EVEX_0F3898 */
1274 { "vfmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1276 /* PREFIX_EVEX_0F3899 */
1280 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1282 /* PREFIX_EVEX_0F389A */
1286 { "vfmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1287 { "v4fmaddps", { XM
, Vex
, Mxmm
}, 0 },
1289 /* PREFIX_EVEX_0F389B */
1293 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1294 { "v4fmaddss", { XMScalar
, VexScalar
, Mxmm
}, 0 },
1296 /* PREFIX_EVEX_0F389C */
1300 { "vfnmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1302 /* PREFIX_EVEX_0F389D */
1306 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1308 /* PREFIX_EVEX_0F389E */
1312 { "vfnmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1314 /* PREFIX_EVEX_0F389F */
1318 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1320 /* PREFIX_EVEX_0F38A0 */
1324 { "vpscatterd%LW", { MVexVSIBDWpX
, XM
}, 0 },
1326 /* PREFIX_EVEX_0F38A1 */
1330 { VEX_W_TABLE (EVEX_W_0F38A1_P_2
) },
1332 /* PREFIX_EVEX_0F38A2 */
1336 { "vscatterdp%XW", { MVexVSIBDWpX
, XM
}, 0 },
1338 /* PREFIX_EVEX_0F38A3 */
1342 { VEX_W_TABLE (EVEX_W_0F38A3_P_2
) },
1344 /* PREFIX_EVEX_0F38A6 */
1348 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1350 /* PREFIX_EVEX_0F38A7 */
1354 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1356 /* PREFIX_EVEX_0F38A8 */
1360 { "vfmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1362 /* PREFIX_EVEX_0F38A9 */
1366 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1368 /* PREFIX_EVEX_0F38AA */
1372 { "vfmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1373 { "v4fnmaddps", { XM
, Vex
, Mxmm
}, 0 },
1375 /* PREFIX_EVEX_0F38AB */
1379 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1380 { "v4fnmaddss", { XMScalar
, VexScalar
, Mxmm
}, 0 },
1382 /* PREFIX_EVEX_0F38AC */
1386 { "vfnmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1388 /* PREFIX_EVEX_0F38AD */
1392 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1394 /* PREFIX_EVEX_0F38AE */
1398 { "vfnmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1400 /* PREFIX_EVEX_0F38AF */
1404 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1406 /* PREFIX_EVEX_0F38B4 */
1410 { "vpmadd52luq", { XM
, Vex
, EXx
}, 0 },
1412 /* PREFIX_EVEX_0F38B5 */
1416 { "vpmadd52huq", { XM
, Vex
, EXx
}, 0 },
1418 /* PREFIX_EVEX_0F38B6 */
1422 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1424 /* PREFIX_EVEX_0F38B7 */
1428 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1430 /* PREFIX_EVEX_0F38B8 */
1434 { "vfmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1436 /* PREFIX_EVEX_0F38B9 */
1440 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1442 /* PREFIX_EVEX_0F38BA */
1446 { "vfmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1448 /* PREFIX_EVEX_0F38BB */
1452 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1454 /* PREFIX_EVEX_0F38BC */
1458 { "vfnmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1460 /* PREFIX_EVEX_0F38BD */
1464 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1466 /* PREFIX_EVEX_0F38BE */
1470 { "vfnmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1472 /* PREFIX_EVEX_0F38BF */
1476 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1478 /* PREFIX_EVEX_0F38C4 */
1482 { "vpconflict%LW", { XM
, EXx
}, 0 },
1484 /* PREFIX_EVEX_0F38C6_REG_1 */
1488 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_1_PREFIX_2
) },
1490 /* PREFIX_EVEX_0F38C6_REG_2 */
1494 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_2_PREFIX_2
) },
1496 /* PREFIX_EVEX_0F38C6_REG_5 */
1500 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_5_PREFIX_2
) },
1502 /* PREFIX_EVEX_0F38C6_REG_6 */
1506 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_6_PREFIX_2
) },
1508 /* PREFIX_EVEX_0F38C7_REG_1 */
1512 { VEX_W_TABLE (EVEX_W_0F38C7_R_1_P_2
) },
1514 /* PREFIX_EVEX_0F38C7_REG_2 */
1518 { VEX_W_TABLE (EVEX_W_0F38C7_R_2_P_2
) },
1520 /* PREFIX_EVEX_0F38C7_REG_5 */
1524 { VEX_W_TABLE (EVEX_W_0F38C7_R_5_P_2
) },
1526 /* PREFIX_EVEX_0F38C7_REG_6 */
1530 { VEX_W_TABLE (EVEX_W_0F38C7_R_6_P_2
) },
1532 /* PREFIX_EVEX_0F38C8 */
1536 { "vexp2p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1538 /* PREFIX_EVEX_0F38CA */
1542 { "vrcp28p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1544 /* PREFIX_EVEX_0F38CB */
1548 { "vrcp28s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
1550 /* PREFIX_EVEX_0F38CC */
1554 { "vrsqrt28p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1556 /* PREFIX_EVEX_0F38CD */
1560 { "vrsqrt28s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
1562 /* PREFIX_EVEX_0F38CF */
1566 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
1568 /* PREFIX_EVEX_0F38DC */
1572 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
1574 /* PREFIX_EVEX_0F38DD */
1578 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
1580 /* PREFIX_EVEX_0F38DE */
1584 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
1586 /* PREFIX_EVEX_0F38DF */
1590 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
1592 /* PREFIX_EVEX_0F3A00 */
1596 { VEX_W_TABLE (EVEX_W_0F3A00_P_2
) },
1598 /* PREFIX_EVEX_0F3A01 */
1602 { VEX_W_TABLE (EVEX_W_0F3A01_P_2
) },
1604 /* PREFIX_EVEX_0F3A03 */
1608 { "valign%LW", { XM
, Vex
, EXx
, Ib
}, 0 },
1610 /* PREFIX_EVEX_0F3A04 */
1614 { VEX_W_TABLE (EVEX_W_0F3A04_P_2
) },
1616 /* PREFIX_EVEX_0F3A05 */
1620 { VEX_W_TABLE (EVEX_W_0F3A05_P_2
) },
1622 /* PREFIX_EVEX_0F3A08 */
1626 { VEX_W_TABLE (EVEX_W_0F3A08_P_2
) },
1628 /* PREFIX_EVEX_0F3A09 */
1632 { VEX_W_TABLE (EVEX_W_0F3A09_P_2
) },
1634 /* PREFIX_EVEX_0F3A0A */
1638 { VEX_W_TABLE (EVEX_W_0F3A0A_P_2
) },
1640 /* PREFIX_EVEX_0F3A0B */
1644 { VEX_W_TABLE (EVEX_W_0F3A0B_P_2
) },
1646 /* PREFIX_EVEX_0F3A0F */
1650 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
1652 /* PREFIX_EVEX_0F3A14 */
1656 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
1658 /* PREFIX_EVEX_0F3A15 */
1662 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
1664 /* PREFIX_EVEX_0F3A16 */
1668 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
1670 /* PREFIX_EVEX_0F3A17 */
1674 { "vextractps", { Edqd
, XMM
, Ib
}, 0 },
1676 /* PREFIX_EVEX_0F3A18 */
1680 { VEX_W_TABLE (EVEX_W_0F3A18_P_2
) },
1682 /* PREFIX_EVEX_0F3A19 */
1686 { VEX_W_TABLE (EVEX_W_0F3A19_P_2
) },
1688 /* PREFIX_EVEX_0F3A1A */
1692 { VEX_W_TABLE (EVEX_W_0F3A1A_P_2
) },
1694 /* PREFIX_EVEX_0F3A1B */
1698 { VEX_W_TABLE (EVEX_W_0F3A1B_P_2
) },
1700 /* PREFIX_EVEX_0F3A1D */
1704 { VEX_W_TABLE (EVEX_W_0F3A1D_P_2
) },
1706 /* PREFIX_EVEX_0F3A1E */
1710 { "vpcmpu%LW", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1712 /* PREFIX_EVEX_0F3A1F */
1716 { "vpcmp%LW", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1718 /* PREFIX_EVEX_0F3A20 */
1722 { "vpinsrb", { XM
, Vex128
, Edb
, Ib
}, 0 },
1724 /* PREFIX_EVEX_0F3A21 */
1728 { VEX_W_TABLE (EVEX_W_0F3A21_P_2
) },
1730 /* PREFIX_EVEX_0F3A22 */
1734 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
1736 /* PREFIX_EVEX_0F3A23 */
1740 { VEX_W_TABLE (EVEX_W_0F3A23_P_2
) },
1742 /* PREFIX_EVEX_0F3A25 */
1746 { "vpternlog%LW", { XM
, Vex
, EXx
, Ib
}, 0 },
1748 /* PREFIX_EVEX_0F3A26 */
1752 { "vgetmantp%XW", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
1754 /* PREFIX_EVEX_0F3A27 */
1758 { "vgetmants%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1760 /* PREFIX_EVEX_0F3A38 */
1764 { VEX_W_TABLE (EVEX_W_0F3A38_P_2
) },
1766 /* PREFIX_EVEX_0F3A39 */
1770 { VEX_W_TABLE (EVEX_W_0F3A39_P_2
) },
1772 /* PREFIX_EVEX_0F3A3A */
1776 { VEX_W_TABLE (EVEX_W_0F3A3A_P_2
) },
1778 /* PREFIX_EVEX_0F3A3B */
1782 { VEX_W_TABLE (EVEX_W_0F3A3B_P_2
) },
1784 /* PREFIX_EVEX_0F3A3E */
1788 { VEX_W_TABLE (EVEX_W_0F3A3E_P_2
) },
1790 /* PREFIX_EVEX_0F3A3F */
1794 { VEX_W_TABLE (EVEX_W_0F3A3F_P_2
) },
1796 /* PREFIX_EVEX_0F3A42 */
1800 { VEX_W_TABLE (EVEX_W_0F3A42_P_2
) },
1802 /* PREFIX_EVEX_0F3A43 */
1806 { VEX_W_TABLE (EVEX_W_0F3A43_P_2
) },
1808 /* PREFIX_EVEX_0F3A44 */
1812 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
1814 /* PREFIX_EVEX_0F3A50 */
1818 { VEX_W_TABLE (EVEX_W_0F3A50_P_2
) },
1820 /* PREFIX_EVEX_0F3A51 */
1824 { VEX_W_TABLE (EVEX_W_0F3A51_P_2
) },
1826 /* PREFIX_EVEX_0F3A54 */
1830 { "vfixupimmp%XW", { XM
, Vex
, EXx
, EXxEVexS
, Ib
}, 0 },
1832 /* PREFIX_EVEX_0F3A55 */
1836 { "vfixupimms%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1838 /* PREFIX_EVEX_0F3A56 */
1842 { VEX_W_TABLE (EVEX_W_0F3A56_P_2
) },
1844 /* PREFIX_EVEX_0F3A57 */
1848 { VEX_W_TABLE (EVEX_W_0F3A57_P_2
) },
1850 /* PREFIX_EVEX_0F3A66 */
1854 { VEX_W_TABLE (EVEX_W_0F3A66_P_2
) },
1856 /* PREFIX_EVEX_0F3A67 */
1860 { VEX_W_TABLE (EVEX_W_0F3A67_P_2
) },
1862 /* PREFIX_EVEX_0F3A70 */
1866 { VEX_W_TABLE (EVEX_W_0F3A70_P_2
) },
1868 /* PREFIX_EVEX_0F3A71 */
1872 { VEX_W_TABLE (EVEX_W_0F3A71_P_2
) },
1874 /* PREFIX_EVEX_0F3A72 */
1878 { VEX_W_TABLE (EVEX_W_0F3A72_P_2
) },
1880 /* PREFIX_EVEX_0F3A73 */
1884 { VEX_W_TABLE (EVEX_W_0F3A73_P_2
) },
1886 /* PREFIX_EVEX_0F3ACE */
1890 { VEX_W_TABLE (EVEX_W_0F3ACE_P_2
) },
1892 /* PREFIX_EVEX_0F3ACF */
1896 { VEX_W_TABLE (EVEX_W_0F3ACF_P_2
) },