opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2021 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_VexR (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_Rounding (int, int);
  93 static void OP_REG_VexI4 (int, int);
  94 static void OP_VexI4 (int, int);
  95 static void PCLMUL_Fixup (int, int);
  96 static void VPCMP_Fixup (int, int);
  97 static void VPCOM_Fixup (int, int);
  98 static void OP_0f07 (int, int);
  99 static void OP_Monitor (int, int);
 100 static void OP_Mwait (int, int);
 101 static void NOP_Fixup1 (int, int);
 102 static void NOP_Fixup2 (int, int);
 103 static void OP_3DNowSuffix (int, int);
 104 static void CMP_Fixup (int, int);
 105 static void BadOp (void);
 106 static void REP_Fixup (int, int);
 107 static void SEP_Fixup (int, int);
 108 static void BND_Fixup (int, int);
 109 static void NOTRACK_Fixup (int, int);
 110 static void HLE_Fixup1 (int, int);
 111 static void HLE_Fixup2 (int, int);
 112 static void HLE_Fixup3 (int, int);
 113 static void CMPXCHG8B_Fixup (int, int);
 114 static void XMM_Fixup (int, int);
 115 static void FXSAVE_Fixup (int, int);
 116
 117 static void MOVSXD_Fixup (int, int);
 118
 119 static void OP_Mask (int, int);
 120
 121 struct dis_private {
 122   /* Points to first byte not fetched.  */
 123   bfd_byte *max_fetched;
 124   bfd_byte the_buffer[MAX_MNEM_SIZE];
 125   bfd_vma insn_start;
 126   int orig_sizeflag;
 127   OPCODES_SIGJMP_BUF bailout;
 128 };
 129
 130 enum address_mode
 131 {
 132   mode_16bit,
 133   mode_32bit,
 134   mode_64bit
 135 };
 136
 137 enum address_mode address_mode;
 138
 139 /* Flags for the prefixes for the current instruction.  See below.  */
 140 static int prefixes;
 141
 142 /* REX prefix the current instruction.  See below.  */
 143 static int rex;
 144 /* Bits of REX we've already used.  */
 145 static int rex_used;
 146 /* Mark parts used in the REX prefix.  When we are testing for
 147    empty prefix (for 8bit register REX extension), just mask it
 148    out.  Otherwise test for REX bit is excuse for existence of REX
 149    only in case value is nonzero.  */
 150 #define USED_REX(value)                                 \
 151   {                                                     \
 152     if (value)                                          \
 153       {                                                 \
 154         if ((rex & value))                              \
 155           rex_used |= (value) | REX_OPCODE;             \
 156       }                                                 \
 157     else                                                \
 158       rex_used |= REX_OPCODE;                           \
 159   }
 160
 161 /* Flags for prefixes which we somehow handled when printing the
 162    current instruction.  */
 163 static int used_prefixes;
 164
 165 /* Flags stored in PREFIXES.  */
 166 #define PREFIX_REPZ 1
 167 #define PREFIX_REPNZ 2
 168 #define PREFIX_LOCK 4
 169 #define PREFIX_CS 8
 170 #define PREFIX_SS 0x10
 171 #define PREFIX_DS 0x20
 172 #define PREFIX_ES 0x40
 173 #define PREFIX_FS 0x80
 174 #define PREFIX_GS 0x100
 175 #define PREFIX_DATA 0x200
 176 #define PREFIX_ADDR 0x400
 177 #define PREFIX_FWAIT 0x800
 178
 179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 180    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 181    on error.  */
 182 #define FETCH_DATA(info, addr) \
 183   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 184    ? 1 : fetch_data ((info), (addr)))
 185
 186 static int
 187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 188 {
 189   int status;
 190   struct dis_private *priv = (struct dis_private *) info->private_data;
 191   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 192
 193   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 194     status = (*info->read_memory_func) (start,
 195                                         priv->max_fetched,
 196                                         addr - priv->max_fetched,
 197                                         info);
 198   else
 199     status = -1;
 200   if (status != 0)
 201     {
 202       /* If we did manage to read at least one byte, then
 203          print_insn_i386 will do something sensible.  Otherwise, print
 204          an error.  We do that here because this is where we know
 205          STATUS.  */
 206       if (priv->max_fetched == priv->the_buffer)
 207         (*info->memory_error_func) (status, start, info);
 208       OPCODES_SIGLONGJMP (priv->bailout, 1);
 209     }
 210   else
 211     priv->max_fetched = addr;
 212   return 1;
 213 }
 214
 215 /* Possible values for prefix requirement.  */
 216 #define PREFIX_IGNORED_SHIFT    16
 217 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 218 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 219 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 222
 223 /* Opcode prefixes.  */
 224 #define PREFIX_OPCODE           (PREFIX_REPZ \
 225                                  | PREFIX_REPNZ \
 226                                  | PREFIX_DATA)
 227
 228 /* Prefixes ignored.  */
 229 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 230                                  | PREFIX_IGNORED_REPNZ \
 231                                  | PREFIX_IGNORED_DATA)
 232
 233 #define XX { NULL, 0 }
 234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 235
 236 #define Eb { OP_E, b_mode }
 237 #define Ebnd { OP_E, bnd_mode }
 238 #define EbS { OP_E, b_swap_mode }
 239 #define EbndS { OP_E, bnd_swap_mode }
 240 #define Ev { OP_E, v_mode }
 241 #define Eva { OP_E, va_mode }
 242 #define Ev_bnd { OP_E, v_bnd_mode }
 243 #define EvS { OP_E, v_swap_mode }
 244 #define Ed { OP_E, d_mode }
 245 #define Edq { OP_E, dq_mode }
 246 #define Edqw { OP_E, dqw_mode }
 247 #define Edqb { OP_E, dqb_mode }
 248 #define Edb { OP_E, db_mode }
 249 #define Edw { OP_E, dw_mode }
 250 #define Edqd { OP_E, dqd_mode }
 251 #define Eq { OP_E, q_mode }
 252 #define indirEv { OP_indirE, indir_v_mode }
 253 #define indirEp { OP_indirE, f_mode }
 254 #define stackEv { OP_E, stack_v_mode }
 255 #define Em { OP_E, m_mode }
 256 #define Ew { OP_E, w_mode }
 257 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 258 #define Ma { OP_M, a_mode }
 259 #define Mb { OP_M, b_mode }
 260 #define Md { OP_M, d_mode }
 261 #define Mo { OP_M, o_mode }
 262 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 263 #define Mq { OP_M, q_mode }
 264 #define Mv { OP_M, v_mode }
 265 #define Mv_bnd { OP_M, v_bndmk_mode }
 266 #define Mx { OP_M, x_mode }
 267 #define Mxmm { OP_M, xmm_mode }
 268 #define Gb { OP_G, b_mode }
 269 #define Gbnd { OP_G, bnd_mode }
 270 #define Gv { OP_G, v_mode }
 271 #define Gd { OP_G, d_mode }
 272 #define Gdq { OP_G, dq_mode }
 273 #define Gm { OP_G, m_mode }
 274 #define Gva { OP_G, va_mode }
 275 #define Gw { OP_G, w_mode }
 276 #define Ib { OP_I, b_mode }
 277 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 279 #define Iv { OP_I, v_mode }
 280 #define sIv { OP_sI, v_mode }
 281 #define Iv64 { OP_I64, v_mode }
 282 #define Id { OP_I, d_mode }
 283 #define Iw { OP_I, w_mode }
 284 #define I1 { OP_I, const_1_mode }
 285 #define Jb { OP_J, b_mode }
 286 #define Jv { OP_J, v_mode }
 287 #define Jdqw { OP_J, dqw_mode }
 288 #define Cm { OP_C, m_mode }
 289 #define Dm { OP_D, m_mode }
 290 #define Td { OP_T, d_mode }
 291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 292
 293 #define RMeAX { OP_REG, eAX_reg }
 294 #define RMeBX { OP_REG, eBX_reg }
 295 #define RMeCX { OP_REG, eCX_reg }
 296 #define RMeDX { OP_REG, eDX_reg }
 297 #define RMeSP { OP_REG, eSP_reg }
 298 #define RMeBP { OP_REG, eBP_reg }
 299 #define RMeSI { OP_REG, eSI_reg }
 300 #define RMeDI { OP_REG, eDI_reg }
 301 #define RMrAX { OP_REG, rAX_reg }
 302 #define RMrBX { OP_REG, rBX_reg }
 303 #define RMrCX { OP_REG, rCX_reg }
 304 #define RMrDX { OP_REG, rDX_reg }
 305 #define RMrSP { OP_REG, rSP_reg }
 306 #define RMrBP { OP_REG, rBP_reg }
 307 #define RMrSI { OP_REG, rSI_reg }
 308 #define RMrDI { OP_REG, rDI_reg }
 309 #define RMAL { OP_REG, al_reg }
 310 #define RMCL { OP_REG, cl_reg }
 311 #define RMDL { OP_REG, dl_reg }
 312 #define RMBL { OP_REG, bl_reg }
 313 #define RMAH { OP_REG, ah_reg }
 314 #define RMCH { OP_REG, ch_reg }
 315 #define RMDH { OP_REG, dh_reg }
 316 #define RMBH { OP_REG, bh_reg }
 317 #define RMAX { OP_REG, ax_reg }
 318 #define RMDX { OP_REG, dx_reg }
 319
 320 #define eAX { OP_IMREG, eAX_reg }
 321 #define AL { OP_IMREG, al_reg }
 322 #define CL { OP_IMREG, cl_reg }
 323 #define zAX { OP_IMREG, z_mode_ax_reg }
 324 #define indirDX { OP_IMREG, indir_dx_reg }
 325
 326 #define Sw { OP_SEG, w_mode }
 327 #define Sv { OP_SEG, v_mode }
 328 #define Ap { OP_DIR, 0 }
 329 #define Ob { OP_OFF64, b_mode }
 330 #define Ov { OP_OFF64, v_mode }
 331 #define Xb { OP_DSreg, eSI_reg }
 332 #define Xv { OP_DSreg, eSI_reg }
 333 #define Xz { OP_DSreg, eSI_reg }
 334 #define Yb { OP_ESreg, eDI_reg }
 335 #define Yv { OP_ESreg, eDI_reg }
 336 #define DSBX { OP_DSreg, eBX_reg }
 337
 338 #define es { OP_REG, es_reg }
 339 #define ss { OP_REG, ss_reg }
 340 #define cs { OP_REG, cs_reg }
 341 #define ds { OP_REG, ds_reg }
 342 #define fs { OP_REG, fs_reg }
 343 #define gs { OP_REG, gs_reg }
 344
 345 #define MX { OP_MMX, 0 }
 346 #define XM { OP_XMM, 0 }
 347 #define XMScalar { OP_XMM, scalar_mode }
 348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 349 #define XMM { OP_XMM, xmm_mode }
 350 #define TMM { OP_XMM, tmm_mode }
 351 #define XMxmmq { OP_XMM, xmmq_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMS { OP_EM, v_swap_mode }
 354 #define EMd { OP_EM, d_mode }
 355 #define EMx { OP_EM, x_mode }
 356 #define EXbwUnit { OP_EX, bw_unit_mode }
 357 #define EXw { OP_EX, w_mode }
 358 #define EXd { OP_EX, d_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXq { OP_EX, q_mode }
 361 #define EXqS { OP_EX, q_swap_mode }
 362 #define EXx { OP_EX, x_mode }
 363 #define EXxS { OP_EX, x_swap_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXymm { OP_EX, ymm_mode }
 366 #define EXtmm { OP_EX, tmm_mode }
 367 #define EXxmmq { OP_EX, xmmq_mode }
 368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 371 #define EXxmm_md { OP_EX, xmm_md_mode }
 372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 373 #define EXxmmdw { OP_EX, xmmdw_mode }
 374 #define EXxmmqd { OP_EX, xmmqd_mode }
 375 #define EXymmq { OP_EX, ymmq_mode }
 376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 379 #define MS { OP_MS, v_mode }
 380 #define XS { OP_XS, v_mode }
 381 #define EMCq { OP_EMC, q_mode }
 382 #define MXC { OP_MXC, 0 }
 383 #define OPSUF { OP_3DNowSuffix, 0 }
 384 #define SEP { SEP_Fixup, 0 }
 385 #define CMP { CMP_Fixup, 0 }
 386 #define XMM0 { XMM_Fixup, 0 }
 387 #define FXSAVE { FXSAVE_Fixup, 0 }
 388
 389 #define Vex { OP_VEX, vex_mode }
 390 #define VexW { OP_VexW, vex_mode }
 391 #define VexScalar { OP_VEX, vex_scalar_mode }
 392 #define VexScalarR { OP_VexR, vex_scalar_mode }
 393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 394 #define VexGdq { OP_VEX, dq_mode }
 395 #define VexTmm { OP_VEX, tmm_mode }
 396 #define XMVexI4 { OP_REG_VexI4, x_mode }
 397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 398 #define VexI4 { OP_VexI4, 0 }
 399 #define PCLMUL { PCLMUL_Fixup, 0 }
 400 #define VPCMP { VPCMP_Fixup, 0 }
 401 #define VPCOM { VPCOM_Fixup, 0 }
 402
 403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 406
 407 #define XMask { OP_Mask, mask_mode }
 408 #define MaskG { OP_G, mask_mode }
 409 #define MaskE { OP_E, mask_mode }
 410 #define MaskBDE { OP_E, mask_bd_mode }
 411 #define MaskVex { OP_VEX, mask_mode }
 412
 413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 414 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 415
 416 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 417
 418 /* Used handle "rep" prefix for string instructions.  */
 419 #define Xbr { REP_Fixup, eSI_reg }
 420 #define Xvr { REP_Fixup, eSI_reg }
 421 #define Ybr { REP_Fixup, eDI_reg }
 422 #define Yvr { REP_Fixup, eDI_reg }
 423 #define Yzr { REP_Fixup, eDI_reg }
 424 #define indirDXr { REP_Fixup, indir_dx_reg }
 425 #define ALr { REP_Fixup, al_reg }
 426 #define eAXr { REP_Fixup, eAX_reg }
 427
 428 /* Used handle HLE prefix for lockable instructions.  */
 429 #define Ebh1 { HLE_Fixup1, b_mode }
 430 #define Evh1 { HLE_Fixup1, v_mode }
 431 #define Ebh2 { HLE_Fixup2, b_mode }
 432 #define Evh2 { HLE_Fixup2, v_mode }
 433 #define Ebh3 { HLE_Fixup3, b_mode }
 434 #define Evh3 { HLE_Fixup3, v_mode }
 435
 436 #define BND { BND_Fixup, 0 }
 437 #define NOTRACK { NOTRACK_Fixup, 0 }
 438
 439 #define cond_jump_flag { NULL, cond_jump_mode }
 440 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 441
 442 /* bits in sizeflag */
 443 #define SUFFIX_ALWAYS 4
 444 #define AFLAG 2
 445 #define DFLAG 1
 446
 447 enum
 448 {
 449   /* byte operand */
 450   b_mode = 1,
 451   /* byte operand with operand swapped */
 452   b_swap_mode,
 453   /* byte operand, sign extend like 'T' suffix */
 454   b_T_mode,
 455   /* operand size depends on prefixes */
 456   v_mode,
 457   /* operand size depends on prefixes with operand swapped */
 458   v_swap_mode,
 459   /* operand size depends on address prefix */
 460   va_mode,
 461   /* word operand */
 462   w_mode,
 463   /* double word operand  */
 464   d_mode,
 465   /* double word operand with operand swapped */
 466   d_swap_mode,
 467   /* quad word operand */
 468   q_mode,
 469   /* quad word operand with operand swapped */
 470   q_swap_mode,
 471   /* ten-byte operand */
 472   t_mode,
 473   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 474      broadcast enabled.  */
 475   x_mode,
 476   /* Similar to x_mode, but with different EVEX mem shifts.  */
 477   evex_x_gscat_mode,
 478   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 479   bw_unit_mode,
 480   /* Similar to x_mode, but with disabled broadcast.  */
 481   evex_x_nobcst_mode,
 482   /* Similar to x_mode, but with operands swapped and disabled broadcast
 483      in EVEX.  */
 484   x_swap_mode,
 485   /* 16-byte XMM operand */
 486   xmm_mode,
 487   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 488      memory operand (depending on vector length).  Broadcast isn't
 489      allowed.  */
 490   xmmq_mode,
 491   /* Same as xmmq_mode, but broadcast is allowed.  */
 492   evex_half_bcst_xmmq_mode,
 493   /* XMM register or byte memory operand */
 494   xmm_mb_mode,
 495   /* XMM register or word memory operand */
 496   xmm_mw_mode,
 497   /* XMM register or double word memory operand */
 498   xmm_md_mode,
 499   /* XMM register or quad word memory operand */
 500   xmm_mq_mode,
 501   /* 16-byte XMM, word, double word or quad word operand.  */
 502   xmmdw_mode,
 503   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 504   xmmqd_mode,
 505   /* 32-byte YMM operand */
 506   ymm_mode,
 507   /* quad word, ymmword or zmmword memory operand.  */
 508   ymmq_mode,
 509   /* 32-byte YMM or 16-byte word operand */
 510   ymmxmm_mode,
 511   /* TMM operand */
 512   tmm_mode,
 513   /* d_mode in 32bit, q_mode in 64bit mode.  */
 514   m_mode,
 515   /* pair of v_mode operands */
 516   a_mode,
 517   cond_jump_mode,
 518   loop_jcxz_mode,
 519   movsxd_mode,
 520   v_bnd_mode,
 521   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 522   v_bndmk_mode,
 523   /* operand size depends on REX prefixes.  */
 524   dq_mode,
 525   /* registers like dq_mode, memory like w_mode, displacements like
 526      v_mode without considering Intel64 ISA.  */
 527   dqw_mode,
 528   /* bounds operand */
 529   bnd_mode,
 530   /* bounds operand with operand swapped */
 531   bnd_swap_mode,
 532   /* 4- or 6-byte pointer operand */
 533   f_mode,
 534   const_1_mode,
 535   /* v_mode for indirect branch opcodes.  */
 536   indir_v_mode,
 537   /* v_mode for stack-related opcodes.  */
 538   stack_v_mode,
 539   /* non-quad operand size depends on prefixes */
 540   z_mode,
 541   /* 16-byte operand */
 542   o_mode,
 543   /* registers like dq_mode, memory like b_mode.  */
 544   dqb_mode,
 545   /* registers like d_mode, memory like b_mode.  */
 546   db_mode,
 547   /* registers like d_mode, memory like w_mode.  */
 548   dw_mode,
 549   /* registers like dq_mode, memory like d_mode.  */
 550   dqd_mode,
 551   /* normal vex mode */
 552   vex_mode,
 553
 554   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 555   vex_vsib_d_w_dq_mode,
 556   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 557   vex_vsib_q_w_dq_mode,
 558   /* mandatory non-vector SIB.  */
 559   vex_sibmem_mode,
 560
 561   /* scalar, ignore vector length.  */
 562   scalar_mode,
 563   /* like vex_mode, ignore vector length.  */
 564   vex_scalar_mode,
 565   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 566   vex_scalar_w_dq_mode,
 567
 568   /* Static rounding.  */
 569   evex_rounding_mode,
 570   /* Static rounding, 64-bit mode only.  */
 571   evex_rounding_64_mode,
 572   /* Supress all exceptions.  */
 573   evex_sae_mode,
 574
 575   /* Mask register operand.  */
 576   mask_mode,
 577   /* Mask register operand.  */
 578   mask_bd_mode,
 579
 580   es_reg,
 581   cs_reg,
 582   ss_reg,
 583   ds_reg,
 584   fs_reg,
 585   gs_reg,
 586
 587   eAX_reg,
 588   eCX_reg,
 589   eDX_reg,
 590   eBX_reg,
 591   eSP_reg,
 592   eBP_reg,
 593   eSI_reg,
 594   eDI_reg,
 595
 596   al_reg,
 597   cl_reg,
 598   dl_reg,
 599   bl_reg,
 600   ah_reg,
 601   ch_reg,
 602   dh_reg,
 603   bh_reg,
 604
 605   ax_reg,
 606   cx_reg,
 607   dx_reg,
 608   bx_reg,
 609   sp_reg,
 610   bp_reg,
 611   si_reg,
 612   di_reg,
 613
 614   rAX_reg,
 615   rCX_reg,
 616   rDX_reg,
 617   rBX_reg,
 618   rSP_reg,
 619   rBP_reg,
 620   rSI_reg,
 621   rDI_reg,
 622
 623   z_mode_ax_reg,
 624   indir_dx_reg
 625 };
 626
 627 enum
 628 {
 629   FLOATCODE = 1,
 630   USE_REG_TABLE,
 631   USE_MOD_TABLE,
 632   USE_RM_TABLE,
 633   USE_PREFIX_TABLE,
 634   USE_X86_64_TABLE,
 635   USE_3BYTE_TABLE,
 636   USE_XOP_8F_TABLE,
 637   USE_VEX_C4_TABLE,
 638   USE_VEX_C5_TABLE,
 639   USE_VEX_LEN_TABLE,
 640   USE_VEX_W_TABLE,
 641   USE_EVEX_TABLE,
 642   USE_EVEX_LEN_TABLE
 643 };
 644
 645 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 646
 647 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 648 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 649 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 650 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 651 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 652 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 653 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 654 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 655 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 656 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 657 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 658 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 659 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 660 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 661 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 662 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 663
 664 enum
 665 {
 666   REG_80 = 0,
 667   REG_81,
 668   REG_83,
 669   REG_8F,
 670   REG_C0,
 671   REG_C1,
 672   REG_C6,
 673   REG_C7,
 674   REG_D0,
 675   REG_D1,
 676   REG_D2,
 677   REG_D3,
 678   REG_F6,
 679   REG_F7,
 680   REG_FE,
 681   REG_FF,
 682   REG_0F00,
 683   REG_0F01,
 684   REG_0F0D,
 685   REG_0F18,
 686   REG_0F1C_P_0_MOD_0,
 687   REG_0F1E_P_1_MOD_3,
 688   REG_0F38D8_PREFIX_1,
 689   REG_0F3A0F_PREFIX_1_MOD_3,
 690   REG_0F71_MOD_0,
 691   REG_0F72_MOD_0,
 692   REG_0F73_MOD_0,
 693   REG_0FA6,
 694   REG_0FA7,
 695   REG_0FAE,
 696   REG_0FBA,
 697   REG_0FC7,
 698   REG_VEX_0F71_M_0,
 699   REG_VEX_0F72_M_0,
 700   REG_VEX_0F73_M_0,
 701   REG_VEX_0FAE,
 702   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 703   REG_VEX_0F38F3_L_0,
 704
 705   REG_XOP_09_01_L_0,
 706   REG_XOP_09_02_L_0,
 707   REG_XOP_09_12_M_1_L_0,
 708   REG_XOP_0A_12_L_0,
 709
 710   REG_EVEX_0F71,
 711   REG_EVEX_0F72,
 712   REG_EVEX_0F73,
 713   REG_EVEX_0F38C6_M_0_L_2,
 714   REG_EVEX_0F38C7_M_0_L_2
 715 };
 716
 717 enum
 718 {
 719   MOD_62_32BIT = 0,
 720   MOD_8D,
 721   MOD_C4_32BIT,
 722   MOD_C5_32BIT,
 723   MOD_C6_REG_7,
 724   MOD_C7_REG_7,
 725   MOD_FF_REG_3,
 726   MOD_FF_REG_5,
 727   MOD_0F01_REG_0,
 728   MOD_0F01_REG_1,
 729   MOD_0F01_REG_2,
 730   MOD_0F01_REG_3,
 731   MOD_0F01_REG_5,
 732   MOD_0F01_REG_7,
 733   MOD_0F12_PREFIX_0,
 734   MOD_0F12_PREFIX_2,
 735   MOD_0F13,
 736   MOD_0F16_PREFIX_0,
 737   MOD_0F16_PREFIX_2,
 738   MOD_0F17,
 739   MOD_0F18_REG_0,
 740   MOD_0F18_REG_1,
 741   MOD_0F18_REG_2,
 742   MOD_0F18_REG_3,
 743   MOD_0F1A_PREFIX_0,
 744   MOD_0F1B_PREFIX_0,
 745   MOD_0F1B_PREFIX_1,
 746   MOD_0F1C_PREFIX_0,
 747   MOD_0F1E_PREFIX_1,
 748   MOD_0F2B_PREFIX_0,
 749   MOD_0F2B_PREFIX_1,
 750   MOD_0F2B_PREFIX_2,
 751   MOD_0F2B_PREFIX_3,
 752   MOD_0F50,
 753   MOD_0F71,
 754   MOD_0F72,
 755   MOD_0F73,
 756   MOD_0FAE_REG_0,
 757   MOD_0FAE_REG_1,
 758   MOD_0FAE_REG_2,
 759   MOD_0FAE_REG_3,
 760   MOD_0FAE_REG_4,
 761   MOD_0FAE_REG_5,
 762   MOD_0FAE_REG_6,
 763   MOD_0FAE_REG_7,
 764   MOD_0FB2,
 765   MOD_0FB4,
 766   MOD_0FB5,
 767   MOD_0FC3,
 768   MOD_0FC7_REG_3,
 769   MOD_0FC7_REG_4,
 770   MOD_0FC7_REG_5,
 771   MOD_0FC7_REG_6,
 772   MOD_0FC7_REG_7,
 773   MOD_0FD7,
 774   MOD_0FE7_PREFIX_2,
 775   MOD_0FF0_PREFIX_3,
 776   MOD_0F382A,
 777   MOD_0F38DC_PREFIX_1,
 778   MOD_0F38DD_PREFIX_1,
 779   MOD_0F38DE_PREFIX_1,
 780   MOD_0F38DF_PREFIX_1,
 781   MOD_0F38F5,
 782   MOD_0F38F6_PREFIX_0,
 783   MOD_0F38F8_PREFIX_1,
 784   MOD_0F38F8_PREFIX_2,
 785   MOD_0F38F8_PREFIX_3,
 786   MOD_0F38F9,
 787   MOD_0F38FA_PREFIX_1,
 788   MOD_0F38FB_PREFIX_1,
 789   MOD_0F3A0F_PREFIX_1,
 790
 791   MOD_VEX_0F12_PREFIX_0,
 792   MOD_VEX_0F12_PREFIX_2,
 793   MOD_VEX_0F13,
 794   MOD_VEX_0F16_PREFIX_0,
 795   MOD_VEX_0F16_PREFIX_2,
 796   MOD_VEX_0F17,
 797   MOD_VEX_0F2B,
 798   MOD_VEX_0F41_L_1,
 799   MOD_VEX_0F42_L_1,
 800   MOD_VEX_0F44_L_0,
 801   MOD_VEX_0F45_L_1,
 802   MOD_VEX_0F46_L_1,
 803   MOD_VEX_0F47_L_1,
 804   MOD_VEX_0F4A_L_1,
 805   MOD_VEX_0F4B_L_1,
 806   MOD_VEX_0F50,
 807   MOD_VEX_0F71,
 808   MOD_VEX_0F72,
 809   MOD_VEX_0F73,
 810   MOD_VEX_0F91_L_0,
 811   MOD_VEX_0F92_L_0,
 812   MOD_VEX_0F93_L_0,
 813   MOD_VEX_0F98_L_0,
 814   MOD_VEX_0F99_L_0,
 815   MOD_VEX_0FAE_REG_2,
 816   MOD_VEX_0FAE_REG_3,
 817   MOD_VEX_0FD7,
 818   MOD_VEX_0FE7,
 819   MOD_VEX_0FF0_PREFIX_3,
 820   MOD_VEX_0F381A,
 821   MOD_VEX_0F382A,
 822   MOD_VEX_0F382C,
 823   MOD_VEX_0F382D,
 824   MOD_VEX_0F382E,
 825   MOD_VEX_0F382F,
 826   MOD_VEX_0F3849_X86_64_P_0_W_0,
 827   MOD_VEX_0F3849_X86_64_P_2_W_0,
 828   MOD_VEX_0F3849_X86_64_P_3_W_0,
 829   MOD_VEX_0F384B_X86_64_P_1_W_0,
 830   MOD_VEX_0F384B_X86_64_P_2_W_0,
 831   MOD_VEX_0F384B_X86_64_P_3_W_0,
 832   MOD_VEX_0F385A,
 833   MOD_VEX_0F385C_X86_64_P_1_W_0,
 834   MOD_VEX_0F385E_X86_64_P_0_W_0,
 835   MOD_VEX_0F385E_X86_64_P_1_W_0,
 836   MOD_VEX_0F385E_X86_64_P_2_W_0,
 837   MOD_VEX_0F385E_X86_64_P_3_W_0,
 838   MOD_VEX_0F388C,
 839   MOD_VEX_0F388E,
 840   MOD_VEX_0F3A30_L_0,
 841   MOD_VEX_0F3A31_L_0,
 842   MOD_VEX_0F3A32_L_0,
 843   MOD_VEX_0F3A33_L_0,
 844
 845   MOD_XOP_09_12,
 846
 847   MOD_EVEX_0F12_PREFIX_0,
 848   MOD_EVEX_0F12_PREFIX_2,
 849   MOD_EVEX_0F13,
 850   MOD_EVEX_0F16_PREFIX_0,
 851   MOD_EVEX_0F16_PREFIX_2,
 852   MOD_EVEX_0F17,
 853   MOD_EVEX_0F2B,
 854   MOD_EVEX_0F381A,
 855   MOD_EVEX_0F381B,
 856   MOD_EVEX_0F3828_P_1,
 857   MOD_EVEX_0F382A_P_1_W_1,
 858   MOD_EVEX_0F3838_P_1,
 859   MOD_EVEX_0F383A_P_1_W_0,
 860   MOD_EVEX_0F385A,
 861   MOD_EVEX_0F385B,
 862   MOD_EVEX_0F387A_W_0,
 863   MOD_EVEX_0F387B_W_0,
 864   MOD_EVEX_0F387C,
 865   MOD_EVEX_0F38C6,
 866   MOD_EVEX_0F38C7
 867 };
 868
 869 enum
 870 {
 871   RM_C6_REG_7 = 0,
 872   RM_C7_REG_7,
 873   RM_0F01_REG_0,
 874   RM_0F01_REG_1,
 875   RM_0F01_REG_2,
 876   RM_0F01_REG_3,
 877   RM_0F01_REG_5_MOD_3,
 878   RM_0F01_REG_7_MOD_3,
 879   RM_0F1E_P_1_MOD_3_REG_7,
 880   RM_0FAE_REG_6_MOD_3_P_0,
 881   RM_0FAE_REG_7_MOD_3,
 882   RM_0F3A0F_P_1_MOD_3_REG_0,
 883
 884   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 885 };
 886
 887 enum
 888 {
 889   PREFIX_90 = 0,
 890   PREFIX_0F01_REG_1_RM_4,
 891   PREFIX_0F01_REG_1_RM_5,
 892   PREFIX_0F01_REG_1_RM_6,
 893   PREFIX_0F01_REG_1_RM_7,
 894   PREFIX_0F01_REG_3_RM_1,
 895   PREFIX_0F01_REG_5_MOD_0,
 896   PREFIX_0F01_REG_5_MOD_3_RM_0,
 897   PREFIX_0F01_REG_5_MOD_3_RM_1,
 898   PREFIX_0F01_REG_5_MOD_3_RM_2,
 899   PREFIX_0F01_REG_5_MOD_3_RM_4,
 900   PREFIX_0F01_REG_5_MOD_3_RM_5,
 901   PREFIX_0F01_REG_5_MOD_3_RM_6,
 902   PREFIX_0F01_REG_5_MOD_3_RM_7,
 903   PREFIX_0F01_REG_7_MOD_3_RM_2,
 904   PREFIX_0F01_REG_7_MOD_3_RM_6,
 905   PREFIX_0F01_REG_7_MOD_3_RM_7,
 906   PREFIX_0F09,
 907   PREFIX_0F10,
 908   PREFIX_0F11,
 909   PREFIX_0F12,
 910   PREFIX_0F16,
 911   PREFIX_0F1A,
 912   PREFIX_0F1B,
 913   PREFIX_0F1C,
 914   PREFIX_0F1E,
 915   PREFIX_0F2A,
 916   PREFIX_0F2B,
 917   PREFIX_0F2C,
 918   PREFIX_0F2D,
 919   PREFIX_0F2E,
 920   PREFIX_0F2F,
 921   PREFIX_0F51,
 922   PREFIX_0F52,
 923   PREFIX_0F53,
 924   PREFIX_0F58,
 925   PREFIX_0F59,
 926   PREFIX_0F5A,
 927   PREFIX_0F5B,
 928   PREFIX_0F5C,
 929   PREFIX_0F5D,
 930   PREFIX_0F5E,
 931   PREFIX_0F5F,
 932   PREFIX_0F60,
 933   PREFIX_0F61,
 934   PREFIX_0F62,
 935   PREFIX_0F6F,
 936   PREFIX_0F70,
 937   PREFIX_0F78,
 938   PREFIX_0F79,
 939   PREFIX_0F7C,
 940   PREFIX_0F7D,
 941   PREFIX_0F7E,
 942   PREFIX_0F7F,
 943   PREFIX_0FAE_REG_0_MOD_3,
 944   PREFIX_0FAE_REG_1_MOD_3,
 945   PREFIX_0FAE_REG_2_MOD_3,
 946   PREFIX_0FAE_REG_3_MOD_3,
 947   PREFIX_0FAE_REG_4_MOD_0,
 948   PREFIX_0FAE_REG_4_MOD_3,
 949   PREFIX_0FAE_REG_5_MOD_3,
 950   PREFIX_0FAE_REG_6_MOD_0,
 951   PREFIX_0FAE_REG_6_MOD_3,
 952   PREFIX_0FAE_REG_7_MOD_0,
 953   PREFIX_0FB8,
 954   PREFIX_0FBC,
 955   PREFIX_0FBD,
 956   PREFIX_0FC2,
 957   PREFIX_0FC7_REG_6_MOD_0,
 958   PREFIX_0FC7_REG_6_MOD_3,
 959   PREFIX_0FC7_REG_7_MOD_3,
 960   PREFIX_0FD0,
 961   PREFIX_0FD6,
 962   PREFIX_0FE6,
 963   PREFIX_0FE7,
 964   PREFIX_0FF0,
 965   PREFIX_0FF7,
 966   PREFIX_0F38D8,
 967   PREFIX_0F38DC,
 968   PREFIX_0F38DD,
 969   PREFIX_0F38DE,
 970   PREFIX_0F38DF,
 971   PREFIX_0F38F0,
 972   PREFIX_0F38F1,
 973   PREFIX_0F38F6,
 974   PREFIX_0F38F8,
 975   PREFIX_0F38FA,
 976   PREFIX_0F38FB,
 977   PREFIX_0F3A0F,
 978   PREFIX_VEX_0F10,
 979   PREFIX_VEX_0F11,
 980   PREFIX_VEX_0F12,
 981   PREFIX_VEX_0F16,
 982   PREFIX_VEX_0F2A,
 983   PREFIX_VEX_0F2C,
 984   PREFIX_VEX_0F2D,
 985   PREFIX_VEX_0F2E,
 986   PREFIX_VEX_0F2F,
 987   PREFIX_VEX_0F41_L_1_M_1_W_0,
 988   PREFIX_VEX_0F41_L_1_M_1_W_1,
 989   PREFIX_VEX_0F42_L_1_M_1_W_0,
 990   PREFIX_VEX_0F42_L_1_M_1_W_1,
 991   PREFIX_VEX_0F44_L_0_M_1_W_0,
 992   PREFIX_VEX_0F44_L_0_M_1_W_1,
 993   PREFIX_VEX_0F45_L_1_M_1_W_0,
 994   PREFIX_VEX_0F45_L_1_M_1_W_1,
 995   PREFIX_VEX_0F46_L_1_M_1_W_0,
 996   PREFIX_VEX_0F46_L_1_M_1_W_1,
 997   PREFIX_VEX_0F47_L_1_M_1_W_0,
 998   PREFIX_VEX_0F47_L_1_M_1_W_1,
 999   PREFIX_VEX_0F4A_L_1_M_1_W_0,
1000   PREFIX_VEX_0F4A_L_1_M_1_W_1,
1001   PREFIX_VEX_0F4B_L_1_M_1_W_0,
1002   PREFIX_VEX_0F4B_L_1_M_1_W_1,
1003   PREFIX_VEX_0F51,
1004   PREFIX_VEX_0F52,
1005   PREFIX_VEX_0F53,
1006   PREFIX_VEX_0F58,
1007   PREFIX_VEX_0F59,
1008   PREFIX_VEX_0F5A,
1009   PREFIX_VEX_0F5B,
1010   PREFIX_VEX_0F5C,
1011   PREFIX_VEX_0F5D,
1012   PREFIX_VEX_0F5E,
1013   PREFIX_VEX_0F5F,
1014   PREFIX_VEX_0F6F,
1015   PREFIX_VEX_0F70,
1016   PREFIX_VEX_0F7C,
1017   PREFIX_VEX_0F7D,
1018   PREFIX_VEX_0F7E,
1019   PREFIX_VEX_0F7F,
1020   PREFIX_VEX_0F90_L_0_W_0,
1021   PREFIX_VEX_0F90_L_0_W_1,
1022   PREFIX_VEX_0F91_L_0_M_0_W_0,
1023   PREFIX_VEX_0F91_L_0_M_0_W_1,
1024   PREFIX_VEX_0F92_L_0_M_1_W_0,
1025   PREFIX_VEX_0F92_L_0_M_1_W_1,
1026   PREFIX_VEX_0F93_L_0_M_1_W_0,
1027   PREFIX_VEX_0F93_L_0_M_1_W_1,
1028   PREFIX_VEX_0F98_L_0_M_1_W_0,
1029   PREFIX_VEX_0F98_L_0_M_1_W_1,
1030   PREFIX_VEX_0F99_L_0_M_1_W_0,
1031   PREFIX_VEX_0F99_L_0_M_1_W_1,
1032   PREFIX_VEX_0FC2,
1033   PREFIX_VEX_0FD0,
1034   PREFIX_VEX_0FE6,
1035   PREFIX_VEX_0FF0,
1036   PREFIX_VEX_0F3849_X86_64,
1037   PREFIX_VEX_0F384B_X86_64,
1038   PREFIX_VEX_0F385C_X86_64,
1039   PREFIX_VEX_0F385E_X86_64,
1040   PREFIX_VEX_0F38F5_L_0,
1041   PREFIX_VEX_0F38F6_L_0,
1042   PREFIX_VEX_0F38F7_L_0,
1043   PREFIX_VEX_0F3AF0_L_0,
1044
1045   PREFIX_EVEX_0F10,
1046   PREFIX_EVEX_0F11,
1047   PREFIX_EVEX_0F12,
1048   PREFIX_EVEX_0F16,
1049   PREFIX_EVEX_0F2A,
1050   PREFIX_EVEX_0F51,
1051   PREFIX_EVEX_0F58,
1052   PREFIX_EVEX_0F59,
1053   PREFIX_EVEX_0F5A,
1054   PREFIX_EVEX_0F5B,
1055   PREFIX_EVEX_0F5C,
1056   PREFIX_EVEX_0F5D,
1057   PREFIX_EVEX_0F5E,
1058   PREFIX_EVEX_0F5F,
1059   PREFIX_EVEX_0F6F,
1060   PREFIX_EVEX_0F70,
1061   PREFIX_EVEX_0F78,
1062   PREFIX_EVEX_0F79,
1063   PREFIX_EVEX_0F7A,
1064   PREFIX_EVEX_0F7B,
1065   PREFIX_EVEX_0F7E,
1066   PREFIX_EVEX_0F7F,
1067   PREFIX_EVEX_0FC2,
1068   PREFIX_EVEX_0FE6,
1069   PREFIX_EVEX_0F3810,
1070   PREFIX_EVEX_0F3811,
1071   PREFIX_EVEX_0F3812,
1072   PREFIX_EVEX_0F3813,
1073   PREFIX_EVEX_0F3814,
1074   PREFIX_EVEX_0F3815,
1075   PREFIX_EVEX_0F3820,
1076   PREFIX_EVEX_0F3821,
1077   PREFIX_EVEX_0F3822,
1078   PREFIX_EVEX_0F3823,
1079   PREFIX_EVEX_0F3824,
1080   PREFIX_EVEX_0F3825,
1081   PREFIX_EVEX_0F3826,
1082   PREFIX_EVEX_0F3827,
1083   PREFIX_EVEX_0F3828,
1084   PREFIX_EVEX_0F3829,
1085   PREFIX_EVEX_0F382A,
1086   PREFIX_EVEX_0F3830,
1087   PREFIX_EVEX_0F3831,
1088   PREFIX_EVEX_0F3832,
1089   PREFIX_EVEX_0F3833,
1090   PREFIX_EVEX_0F3834,
1091   PREFIX_EVEX_0F3835,
1092   PREFIX_EVEX_0F3838,
1093   PREFIX_EVEX_0F3839,
1094   PREFIX_EVEX_0F383A,
1095   PREFIX_EVEX_0F3852,
1096   PREFIX_EVEX_0F3853,
1097   PREFIX_EVEX_0F3868,
1098   PREFIX_EVEX_0F3872,
1099   PREFIX_EVEX_0F389A,
1100   PREFIX_EVEX_0F389B,
1101   PREFIX_EVEX_0F38AA,
1102   PREFIX_EVEX_0F38AB,
1103 };
1104
1105 enum
1106 {
1107   X86_64_06 = 0,
1108   X86_64_07,
1109   X86_64_0E,
1110   X86_64_16,
1111   X86_64_17,
1112   X86_64_1E,
1113   X86_64_1F,
1114   X86_64_27,
1115   X86_64_2F,
1116   X86_64_37,
1117   X86_64_3F,
1118   X86_64_60,
1119   X86_64_61,
1120   X86_64_62,
1121   X86_64_63,
1122   X86_64_6D,
1123   X86_64_6F,
1124   X86_64_82,
1125   X86_64_9A,
1126   X86_64_C2,
1127   X86_64_C3,
1128   X86_64_C4,
1129   X86_64_C5,
1130   X86_64_CE,
1131   X86_64_D4,
1132   X86_64_D5,
1133   X86_64_E8,
1134   X86_64_E9,
1135   X86_64_EA,
1136   X86_64_0F01_REG_0,
1137   X86_64_0F01_REG_1,
1138   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1139   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1140   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1141   X86_64_0F01_REG_2,
1142   X86_64_0F01_REG_3,
1143   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1144   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1145   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1146   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1147   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1148   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1149   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1150   X86_64_0F24,
1151   X86_64_0F26,
1152   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1153
1154   X86_64_VEX_0F3849,
1155   X86_64_VEX_0F384B,
1156   X86_64_VEX_0F385C,
1157   X86_64_VEX_0F385E
1158 };
1159
1160 enum
1161 {
1162   THREE_BYTE_0F38 = 0,
1163   THREE_BYTE_0F3A
1164 };
1165
1166 enum
1167 {
1168   XOP_08 = 0,
1169   XOP_09,
1170   XOP_0A
1171 };
1172
1173 enum
1174 {
1175   VEX_0F = 0,
1176   VEX_0F38,
1177   VEX_0F3A
1178 };
1179
1180 enum
1181 {
1182   EVEX_0F = 0,
1183   EVEX_0F38,
1184   EVEX_0F3A
1185 };
1186
1187 enum
1188 {
1189   VEX_LEN_0F12_P_0_M_0 = 0,
1190   VEX_LEN_0F12_P_0_M_1,
1191 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1192   VEX_LEN_0F13_M_0,
1193   VEX_LEN_0F16_P_0_M_0,
1194   VEX_LEN_0F16_P_0_M_1,
1195 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1196   VEX_LEN_0F17_M_0,
1197   VEX_LEN_0F41,
1198   VEX_LEN_0F42,
1199   VEX_LEN_0F44,
1200   VEX_LEN_0F45,
1201   VEX_LEN_0F46,
1202   VEX_LEN_0F47,
1203   VEX_LEN_0F4A,
1204   VEX_LEN_0F4B,
1205   VEX_LEN_0F6E,
1206   VEX_LEN_0F77,
1207   VEX_LEN_0F7E_P_1,
1208   VEX_LEN_0F7E_P_2,
1209   VEX_LEN_0F90,
1210   VEX_LEN_0F91,
1211   VEX_LEN_0F92,
1212   VEX_LEN_0F93,
1213   VEX_LEN_0F98,
1214   VEX_LEN_0F99,
1215   VEX_LEN_0FAE_R_2_M_0,
1216   VEX_LEN_0FAE_R_3_M_0,
1217   VEX_LEN_0FC4,
1218   VEX_LEN_0FC5,
1219   VEX_LEN_0FD6,
1220   VEX_LEN_0FF7,
1221   VEX_LEN_0F3816,
1222   VEX_LEN_0F3819,
1223   VEX_LEN_0F381A_M_0,
1224   VEX_LEN_0F3836,
1225   VEX_LEN_0F3841,
1226   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1227   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1228   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1229   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1230   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1231   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1232   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1233   VEX_LEN_0F385A_M_0,
1234   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1235   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1236   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1237   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1238   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1239   VEX_LEN_0F38DB,
1240   VEX_LEN_0F38F2,
1241   VEX_LEN_0F38F3,
1242   VEX_LEN_0F38F5,
1243   VEX_LEN_0F38F6,
1244   VEX_LEN_0F38F7,
1245   VEX_LEN_0F3A00,
1246   VEX_LEN_0F3A01,
1247   VEX_LEN_0F3A06,
1248   VEX_LEN_0F3A14,
1249   VEX_LEN_0F3A15,
1250   VEX_LEN_0F3A16,
1251   VEX_LEN_0F3A17,
1252   VEX_LEN_0F3A18,
1253   VEX_LEN_0F3A19,
1254   VEX_LEN_0F3A20,
1255   VEX_LEN_0F3A21,
1256   VEX_LEN_0F3A22,
1257   VEX_LEN_0F3A30,
1258   VEX_LEN_0F3A31,
1259   VEX_LEN_0F3A32,
1260   VEX_LEN_0F3A33,
1261   VEX_LEN_0F3A38,
1262   VEX_LEN_0F3A39,
1263   VEX_LEN_0F3A41,
1264   VEX_LEN_0F3A46,
1265   VEX_LEN_0F3A60,
1266   VEX_LEN_0F3A61,
1267   VEX_LEN_0F3A62,
1268   VEX_LEN_0F3A63,
1269   VEX_LEN_0F3ADF,
1270   VEX_LEN_0F3AF0,
1271   VEX_LEN_0FXOP_08_85,
1272   VEX_LEN_0FXOP_08_86,
1273   VEX_LEN_0FXOP_08_87,
1274   VEX_LEN_0FXOP_08_8E,
1275   VEX_LEN_0FXOP_08_8F,
1276   VEX_LEN_0FXOP_08_95,
1277   VEX_LEN_0FXOP_08_96,
1278   VEX_LEN_0FXOP_08_97,
1279   VEX_LEN_0FXOP_08_9E,
1280   VEX_LEN_0FXOP_08_9F,
1281   VEX_LEN_0FXOP_08_A3,
1282   VEX_LEN_0FXOP_08_A6,
1283   VEX_LEN_0FXOP_08_B6,
1284   VEX_LEN_0FXOP_08_C0,
1285   VEX_LEN_0FXOP_08_C1,
1286   VEX_LEN_0FXOP_08_C2,
1287   VEX_LEN_0FXOP_08_C3,
1288   VEX_LEN_0FXOP_08_CC,
1289   VEX_LEN_0FXOP_08_CD,
1290   VEX_LEN_0FXOP_08_CE,
1291   VEX_LEN_0FXOP_08_CF,
1292   VEX_LEN_0FXOP_08_EC,
1293   VEX_LEN_0FXOP_08_ED,
1294   VEX_LEN_0FXOP_08_EE,
1295   VEX_LEN_0FXOP_08_EF,
1296   VEX_LEN_0FXOP_09_01,
1297   VEX_LEN_0FXOP_09_02,
1298   VEX_LEN_0FXOP_09_12_M_1,
1299   VEX_LEN_0FXOP_09_82_W_0,
1300   VEX_LEN_0FXOP_09_83_W_0,
1301   VEX_LEN_0FXOP_09_90,
1302   VEX_LEN_0FXOP_09_91,
1303   VEX_LEN_0FXOP_09_92,
1304   VEX_LEN_0FXOP_09_93,
1305   VEX_LEN_0FXOP_09_94,
1306   VEX_LEN_0FXOP_09_95,
1307   VEX_LEN_0FXOP_09_96,
1308   VEX_LEN_0FXOP_09_97,
1309   VEX_LEN_0FXOP_09_98,
1310   VEX_LEN_0FXOP_09_99,
1311   VEX_LEN_0FXOP_09_9A,
1312   VEX_LEN_0FXOP_09_9B,
1313   VEX_LEN_0FXOP_09_C1,
1314   VEX_LEN_0FXOP_09_C2,
1315   VEX_LEN_0FXOP_09_C3,
1316   VEX_LEN_0FXOP_09_C6,
1317   VEX_LEN_0FXOP_09_C7,
1318   VEX_LEN_0FXOP_09_CB,
1319   VEX_LEN_0FXOP_09_D1,
1320   VEX_LEN_0FXOP_09_D2,
1321   VEX_LEN_0FXOP_09_D3,
1322   VEX_LEN_0FXOP_09_D6,
1323   VEX_LEN_0FXOP_09_D7,
1324   VEX_LEN_0FXOP_09_DB,
1325   VEX_LEN_0FXOP_09_E1,
1326   VEX_LEN_0FXOP_09_E2,
1327   VEX_LEN_0FXOP_09_E3,
1328   VEX_LEN_0FXOP_0A_12,
1329 };
1330
1331 enum
1332 {
1333   EVEX_LEN_0F3816 = 0,
1334   EVEX_LEN_0F3819,
1335   EVEX_LEN_0F381A_M_0,
1336   EVEX_LEN_0F381B_M_0,
1337   EVEX_LEN_0F3836,
1338   EVEX_LEN_0F385A_M_0,
1339   EVEX_LEN_0F385B_M_0,
1340   EVEX_LEN_0F38C6_M_0,
1341   EVEX_LEN_0F38C7_M_0,
1342   EVEX_LEN_0F3A00,
1343   EVEX_LEN_0F3A01,
1344   EVEX_LEN_0F3A18,
1345   EVEX_LEN_0F3A19,
1346   EVEX_LEN_0F3A1A,
1347   EVEX_LEN_0F3A1B,
1348   EVEX_LEN_0F3A23,
1349   EVEX_LEN_0F3A38,
1350   EVEX_LEN_0F3A39,
1351   EVEX_LEN_0F3A3A,
1352   EVEX_LEN_0F3A3B,
1353   EVEX_LEN_0F3A43
1354 };
1355
1356 enum
1357 {
1358   VEX_W_0F41_L_1_M_1 = 0,
1359   VEX_W_0F42_L_1_M_1,
1360   VEX_W_0F44_L_0_M_1,
1361   VEX_W_0F45_L_1_M_1,
1362   VEX_W_0F46_L_1_M_1,
1363   VEX_W_0F47_L_1_M_1,
1364   VEX_W_0F4A_L_1_M_1,
1365   VEX_W_0F4B_L_1_M_1,
1366   VEX_W_0F90_L_0,
1367   VEX_W_0F91_L_0_M_0,
1368   VEX_W_0F92_L_0_M_1,
1369   VEX_W_0F93_L_0_M_1,
1370   VEX_W_0F98_L_0_M_1,
1371   VEX_W_0F99_L_0_M_1,
1372   VEX_W_0F380C,
1373   VEX_W_0F380D,
1374   VEX_W_0F380E,
1375   VEX_W_0F380F,
1376   VEX_W_0F3813,
1377   VEX_W_0F3816_L_1,
1378   VEX_W_0F3818,
1379   VEX_W_0F3819_L_1,
1380   VEX_W_0F381A_M_0_L_1,
1381   VEX_W_0F382C_M_0,
1382   VEX_W_0F382D_M_0,
1383   VEX_W_0F382E_M_0,
1384   VEX_W_0F382F_M_0,
1385   VEX_W_0F3836,
1386   VEX_W_0F3846,
1387   VEX_W_0F3849_X86_64_P_0,
1388   VEX_W_0F3849_X86_64_P_2,
1389   VEX_W_0F3849_X86_64_P_3,
1390   VEX_W_0F384B_X86_64_P_1,
1391   VEX_W_0F384B_X86_64_P_2,
1392   VEX_W_0F384B_X86_64_P_3,
1393   VEX_W_0F3850,
1394   VEX_W_0F3851,
1395   VEX_W_0F3852,
1396   VEX_W_0F3853,
1397   VEX_W_0F3858,
1398   VEX_W_0F3859,
1399   VEX_W_0F385A_M_0_L_0,
1400   VEX_W_0F385C_X86_64_P_1,
1401   VEX_W_0F385E_X86_64_P_0,
1402   VEX_W_0F385E_X86_64_P_1,
1403   VEX_W_0F385E_X86_64_P_2,
1404   VEX_W_0F385E_X86_64_P_3,
1405   VEX_W_0F3878,
1406   VEX_W_0F3879,
1407   VEX_W_0F38CF,
1408   VEX_W_0F3A00_L_1,
1409   VEX_W_0F3A01_L_1,
1410   VEX_W_0F3A02,
1411   VEX_W_0F3A04,
1412   VEX_W_0F3A05,
1413   VEX_W_0F3A06_L_1,
1414   VEX_W_0F3A18_L_1,
1415   VEX_W_0F3A19_L_1,
1416   VEX_W_0F3A1D,
1417   VEX_W_0F3A38_L_1,
1418   VEX_W_0F3A39_L_1,
1419   VEX_W_0F3A46_L_1,
1420   VEX_W_0F3A4A,
1421   VEX_W_0F3A4B,
1422   VEX_W_0F3A4C,
1423   VEX_W_0F3ACE,
1424   VEX_W_0F3ACF,
1425
1426   VEX_W_0FXOP_08_85_L_0,
1427   VEX_W_0FXOP_08_86_L_0,
1428   VEX_W_0FXOP_08_87_L_0,
1429   VEX_W_0FXOP_08_8E_L_0,
1430   VEX_W_0FXOP_08_8F_L_0,
1431   VEX_W_0FXOP_08_95_L_0,
1432   VEX_W_0FXOP_08_96_L_0,
1433   VEX_W_0FXOP_08_97_L_0,
1434   VEX_W_0FXOP_08_9E_L_0,
1435   VEX_W_0FXOP_08_9F_L_0,
1436   VEX_W_0FXOP_08_A6_L_0,
1437   VEX_W_0FXOP_08_B6_L_0,
1438   VEX_W_0FXOP_08_C0_L_0,
1439   VEX_W_0FXOP_08_C1_L_0,
1440   VEX_W_0FXOP_08_C2_L_0,
1441   VEX_W_0FXOP_08_C3_L_0,
1442   VEX_W_0FXOP_08_CC_L_0,
1443   VEX_W_0FXOP_08_CD_L_0,
1444   VEX_W_0FXOP_08_CE_L_0,
1445   VEX_W_0FXOP_08_CF_L_0,
1446   VEX_W_0FXOP_08_EC_L_0,
1447   VEX_W_0FXOP_08_ED_L_0,
1448   VEX_W_0FXOP_08_EE_L_0,
1449   VEX_W_0FXOP_08_EF_L_0,
1450
1451   VEX_W_0FXOP_09_80,
1452   VEX_W_0FXOP_09_81,
1453   VEX_W_0FXOP_09_82,
1454   VEX_W_0FXOP_09_83,
1455   VEX_W_0FXOP_09_C1_L_0,
1456   VEX_W_0FXOP_09_C2_L_0,
1457   VEX_W_0FXOP_09_C3_L_0,
1458   VEX_W_0FXOP_09_C6_L_0,
1459   VEX_W_0FXOP_09_C7_L_0,
1460   VEX_W_0FXOP_09_CB_L_0,
1461   VEX_W_0FXOP_09_D1_L_0,
1462   VEX_W_0FXOP_09_D2_L_0,
1463   VEX_W_0FXOP_09_D3_L_0,
1464   VEX_W_0FXOP_09_D6_L_0,
1465   VEX_W_0FXOP_09_D7_L_0,
1466   VEX_W_0FXOP_09_DB_L_0,
1467   VEX_W_0FXOP_09_E1_L_0,
1468   VEX_W_0FXOP_09_E2_L_0,
1469   VEX_W_0FXOP_09_E3_L_0,
1470
1471   EVEX_W_0F10_P_1,
1472   EVEX_W_0F10_P_3,
1473   EVEX_W_0F11_P_1,
1474   EVEX_W_0F11_P_3,
1475   EVEX_W_0F12_P_0_M_1,
1476   EVEX_W_0F12_P_1,
1477   EVEX_W_0F12_P_3,
1478   EVEX_W_0F16_P_0_M_1,
1479   EVEX_W_0F16_P_1,
1480   EVEX_W_0F2A_P_3,
1481   EVEX_W_0F51_P_1,
1482   EVEX_W_0F51_P_3,
1483   EVEX_W_0F58_P_1,
1484   EVEX_W_0F58_P_3,
1485   EVEX_W_0F59_P_1,
1486   EVEX_W_0F59_P_3,
1487   EVEX_W_0F5A_P_0,
1488   EVEX_W_0F5A_P_1,
1489   EVEX_W_0F5A_P_2,
1490   EVEX_W_0F5A_P_3,
1491   EVEX_W_0F5B_P_0,
1492   EVEX_W_0F5B_P_1,
1493   EVEX_W_0F5B_P_2,
1494   EVEX_W_0F5C_P_1,
1495   EVEX_W_0F5C_P_3,
1496   EVEX_W_0F5D_P_1,
1497   EVEX_W_0F5D_P_3,
1498   EVEX_W_0F5E_P_1,
1499   EVEX_W_0F5E_P_3,
1500   EVEX_W_0F5F_P_1,
1501   EVEX_W_0F5F_P_3,
1502   EVEX_W_0F62,
1503   EVEX_W_0F66,
1504   EVEX_W_0F6A,
1505   EVEX_W_0F6B,
1506   EVEX_W_0F6C,
1507   EVEX_W_0F6D,
1508   EVEX_W_0F6F_P_1,
1509   EVEX_W_0F6F_P_2,
1510   EVEX_W_0F6F_P_3,
1511   EVEX_W_0F70_P_2,
1512   EVEX_W_0F72_R_2,
1513   EVEX_W_0F72_R_6,
1514   EVEX_W_0F73_R_2,
1515   EVEX_W_0F73_R_6,
1516   EVEX_W_0F76,
1517   EVEX_W_0F78_P_0,
1518   EVEX_W_0F78_P_2,
1519   EVEX_W_0F79_P_0,
1520   EVEX_W_0F79_P_2,
1521   EVEX_W_0F7A_P_1,
1522   EVEX_W_0F7A_P_2,
1523   EVEX_W_0F7A_P_3,
1524   EVEX_W_0F7B_P_2,
1525   EVEX_W_0F7B_P_3,
1526   EVEX_W_0F7E_P_1,
1527   EVEX_W_0F7F_P_1,
1528   EVEX_W_0F7F_P_2,
1529   EVEX_W_0F7F_P_3,
1530   EVEX_W_0FC2_P_1,
1531   EVEX_W_0FC2_P_3,
1532   EVEX_W_0FD2,
1533   EVEX_W_0FD3,
1534   EVEX_W_0FD4,
1535   EVEX_W_0FD6,
1536   EVEX_W_0FE6_P_1,
1537   EVEX_W_0FE6_P_2,
1538   EVEX_W_0FE6_P_3,
1539   EVEX_W_0FE7,
1540   EVEX_W_0FF2,
1541   EVEX_W_0FF3,
1542   EVEX_W_0FF4,
1543   EVEX_W_0FFA,
1544   EVEX_W_0FFB,
1545   EVEX_W_0FFE,
1546   EVEX_W_0F380D,
1547   EVEX_W_0F3810_P_1,
1548   EVEX_W_0F3810_P_2,
1549   EVEX_W_0F3811_P_1,
1550   EVEX_W_0F3811_P_2,
1551   EVEX_W_0F3812_P_1,
1552   EVEX_W_0F3812_P_2,
1553   EVEX_W_0F3813_P_1,
1554   EVEX_W_0F3813_P_2,
1555   EVEX_W_0F3814_P_1,
1556   EVEX_W_0F3815_P_1,
1557   EVEX_W_0F3819_L_n,
1558   EVEX_W_0F381A_M_0_L_n,
1559   EVEX_W_0F381B_M_0_L_2,
1560   EVEX_W_0F381E,
1561   EVEX_W_0F381F,
1562   EVEX_W_0F3820_P_1,
1563   EVEX_W_0F3821_P_1,
1564   EVEX_W_0F3822_P_1,
1565   EVEX_W_0F3823_P_1,
1566   EVEX_W_0F3824_P_1,
1567   EVEX_W_0F3825_P_1,
1568   EVEX_W_0F3825_P_2,
1569   EVEX_W_0F3828_P_2,
1570   EVEX_W_0F3829_P_2,
1571   EVEX_W_0F382A_P_1,
1572   EVEX_W_0F382A_P_2,
1573   EVEX_W_0F382B,
1574   EVEX_W_0F3830_P_1,
1575   EVEX_W_0F3831_P_1,
1576   EVEX_W_0F3832_P_1,
1577   EVEX_W_0F3833_P_1,
1578   EVEX_W_0F3834_P_1,
1579   EVEX_W_0F3835_P_1,
1580   EVEX_W_0F3835_P_2,
1581   EVEX_W_0F3837,
1582   EVEX_W_0F383A_P_1,
1583   EVEX_W_0F3852_P_1,
1584   EVEX_W_0F3859,
1585   EVEX_W_0F385A_M_0_L_n,
1586   EVEX_W_0F385B_M_0_L_2,
1587   EVEX_W_0F3870,
1588   EVEX_W_0F3872_P_1,
1589   EVEX_W_0F3872_P_2,
1590   EVEX_W_0F3872_P_3,
1591   EVEX_W_0F387A,
1592   EVEX_W_0F387B,
1593   EVEX_W_0F3883,
1594
1595   EVEX_W_0F3A05,
1596   EVEX_W_0F3A08,
1597   EVEX_W_0F3A09,
1598   EVEX_W_0F3A0A,
1599   EVEX_W_0F3A0B,
1600   EVEX_W_0F3A18_L_n,
1601   EVEX_W_0F3A19_L_n,
1602   EVEX_W_0F3A1A_L_2,
1603   EVEX_W_0F3A1B_L_2,
1604   EVEX_W_0F3A21,
1605   EVEX_W_0F3A23_L_n,
1606   EVEX_W_0F3A38_L_n,
1607   EVEX_W_0F3A39_L_n,
1608   EVEX_W_0F3A3A_L_2,
1609   EVEX_W_0F3A3B_L_2,
1610   EVEX_W_0F3A42,
1611   EVEX_W_0F3A43_L_n,
1612   EVEX_W_0F3A70,
1613   EVEX_W_0F3A72,
1614 };
1615
1616 typedef void (*op_rtn) (int bytemode, int sizeflag);
1617
1618 struct dis386 {
1619   const char *name;
1620   struct
1621     {
1622       op_rtn rtn;
1623       int bytemode;
1624     } op[MAX_OPERANDS];
1625   unsigned int prefix_requirement;
1626 };
1627
1628 /* Upper case letters in the instruction names here are macros.
1629    'A' => print 'b' if no register operands or suffix_always is true
1630    'B' => print 'b' if suffix_always is true
1631    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1632           size prefix
1633    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1634           suffix_always is true
1635    'E' => print 'e' if 32-bit form of jcxz
1636    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1637    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1638    'H' => print ",pt" or ",pn" branch hint
1639    'I' unused.
1640    'J' unused.
1641    'K' => print 'd' or 'q' if rex prefix is present.
1642    'L' unused.
1643    'M' => print 'r' if intel_mnemonic is false.
1644    'N' => print 'n' if instruction has no wait "prefix"
1645    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1646    'P' => behave as 'T' except with register operand outside of suffix_always
1647           mode
1648    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1649           is true
1650    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1651    'S' => print 'w', 'l' or 'q' if suffix_always is true
1652    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1653           prefix or if suffix_always is true.
1654    'U' unused.
1655    'V' unused.
1656    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1657    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1658    'Y' unused.
1659    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1660    '!' => change condition from true to false or from false to true.
1661    '%' => add 1 upper case letter to the macro.
1662    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1663           prefix or suffix_always is true (lcall/ljmp).
1664    '@' => in 64bit mode for Intel64 ISA or if instruction
1665           has no operand sizing prefix, print 'q' if suffix_always is true or
1666           nothing otherwise; behave as 'P' in all other cases
1667
1668    2 upper case letter macros:
1669    "XY" => print 'x' or 'y' if suffix_always is true or no register
1670            operands and no broadcast.
1671    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1672            register operands and no broadcast.
1673    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1674    "XV" => print "{vex3}" pseudo prefix
1675    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1676            being false, or no operand at all in 64bit mode, or if suffix_always
1677            is true.
1678    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1679    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1680    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1681    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1682    "BW" => print 'b' or 'w' depending on the VEX.W bit
1683    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1684            an operand size prefix, or suffix_always is true.  print
1685            'q' if rex prefix is present.
1686
1687    Many of the above letters print nothing in Intel mode.  See "putop"
1688    for the details.
1689
1690    Braces '{' and '}', and vertical bars '|', indicate alternative
1691    mnemonic strings for AT&T and Intel.  */
1692
1693 static const struct dis386 dis386[] = {
1694   /* 00 */
1695   { "addB",             { Ebh1, Gb }, 0 },
1696   { "addS",             { Evh1, Gv }, 0 },
1697   { "addB",             { Gb, EbS }, 0 },
1698   { "addS",             { Gv, EvS }, 0 },
1699   { "addB",             { AL, Ib }, 0 },
1700   { "addS",             { eAX, Iv }, 0 },
1701   { X86_64_TABLE (X86_64_06) },
1702   { X86_64_TABLE (X86_64_07) },
1703   /* 08 */
1704   { "orB",              { Ebh1, Gb }, 0 },
1705   { "orS",              { Evh1, Gv }, 0 },
1706   { "orB",              { Gb, EbS }, 0 },
1707   { "orS",              { Gv, EvS }, 0 },
1708   { "orB",              { AL, Ib }, 0 },
1709   { "orS",              { eAX, Iv }, 0 },
1710   { X86_64_TABLE (X86_64_0E) },
1711   { Bad_Opcode },       /* 0x0f extended opcode escape */
1712   /* 10 */
1713   { "adcB",             { Ebh1, Gb }, 0 },
1714   { "adcS",             { Evh1, Gv }, 0 },
1715   { "adcB",             { Gb, EbS }, 0 },
1716   { "adcS",             { Gv, EvS }, 0 },
1717   { "adcB",             { AL, Ib }, 0 },
1718   { "adcS",             { eAX, Iv }, 0 },
1719   { X86_64_TABLE (X86_64_16) },
1720   { X86_64_TABLE (X86_64_17) },
1721   /* 18 */
1722   { "sbbB",             { Ebh1, Gb }, 0 },
1723   { "sbbS",             { Evh1, Gv }, 0 },
1724   { "sbbB",             { Gb, EbS }, 0 },
1725   { "sbbS",             { Gv, EvS }, 0 },
1726   { "sbbB",             { AL, Ib }, 0 },
1727   { "sbbS",             { eAX, Iv }, 0 },
1728   { X86_64_TABLE (X86_64_1E) },
1729   { X86_64_TABLE (X86_64_1F) },
1730   /* 20 */
1731   { "andB",             { Ebh1, Gb }, 0 },
1732   { "andS",             { Evh1, Gv }, 0 },
1733   { "andB",             { Gb, EbS }, 0 },
1734   { "andS",             { Gv, EvS }, 0 },
1735   { "andB",             { AL, Ib }, 0 },
1736   { "andS",             { eAX, Iv }, 0 },
1737   { Bad_Opcode },       /* SEG ES prefix */
1738   { X86_64_TABLE (X86_64_27) },
1739   /* 28 */
1740   { "subB",             { Ebh1, Gb }, 0 },
1741   { "subS",             { Evh1, Gv }, 0 },
1742   { "subB",             { Gb, EbS }, 0 },
1743   { "subS",             { Gv, EvS }, 0 },
1744   { "subB",             { AL, Ib }, 0 },
1745   { "subS",             { eAX, Iv }, 0 },
1746   { Bad_Opcode },       /* SEG CS prefix */
1747   { X86_64_TABLE (X86_64_2F) },
1748   /* 30 */
1749   { "xorB",             { Ebh1, Gb }, 0 },
1750   { "xorS",             { Evh1, Gv }, 0 },
1751   { "xorB",             { Gb, EbS }, 0 },
1752   { "xorS",             { Gv, EvS }, 0 },
1753   { "xorB",             { AL, Ib }, 0 },
1754   { "xorS",             { eAX, Iv }, 0 },
1755   { Bad_Opcode },       /* SEG SS prefix */
1756   { X86_64_TABLE (X86_64_37) },
1757   /* 38 */
1758   { "cmpB",             { Eb, Gb }, 0 },
1759   { "cmpS",             { Ev, Gv }, 0 },
1760   { "cmpB",             { Gb, EbS }, 0 },
1761   { "cmpS",             { Gv, EvS }, 0 },
1762   { "cmpB",             { AL, Ib }, 0 },
1763   { "cmpS",             { eAX, Iv }, 0 },
1764   { Bad_Opcode },       /* SEG DS prefix */
1765   { X86_64_TABLE (X86_64_3F) },
1766   /* 40 */
1767   { "inc{S|}",          { RMeAX }, 0 },
1768   { "inc{S|}",          { RMeCX }, 0 },
1769   { "inc{S|}",          { RMeDX }, 0 },
1770   { "inc{S|}",          { RMeBX }, 0 },
1771   { "inc{S|}",          { RMeSP }, 0 },
1772   { "inc{S|}",          { RMeBP }, 0 },
1773   { "inc{S|}",          { RMeSI }, 0 },
1774   { "inc{S|}",          { RMeDI }, 0 },
1775   /* 48 */
1776   { "dec{S|}",          { RMeAX }, 0 },
1777   { "dec{S|}",          { RMeCX }, 0 },
1778   { "dec{S|}",          { RMeDX }, 0 },
1779   { "dec{S|}",          { RMeBX }, 0 },
1780   { "dec{S|}",          { RMeSP }, 0 },
1781   { "dec{S|}",          { RMeBP }, 0 },
1782   { "dec{S|}",          { RMeSI }, 0 },
1783   { "dec{S|}",          { RMeDI }, 0 },
1784   /* 50 */
1785   { "push{!P|}",                { RMrAX }, 0 },
1786   { "push{!P|}",                { RMrCX }, 0 },
1787   { "push{!P|}",                { RMrDX }, 0 },
1788   { "push{!P|}",                { RMrBX }, 0 },
1789   { "push{!P|}",                { RMrSP }, 0 },
1790   { "push{!P|}",                { RMrBP }, 0 },
1791   { "push{!P|}",                { RMrSI }, 0 },
1792   { "push{!P|}",                { RMrDI }, 0 },
1793   /* 58 */
1794   { "pop{!P|}",         { RMrAX }, 0 },
1795   { "pop{!P|}",         { RMrCX }, 0 },
1796   { "pop{!P|}",         { RMrDX }, 0 },
1797   { "pop{!P|}",         { RMrBX }, 0 },
1798   { "pop{!P|}",         { RMrSP }, 0 },
1799   { "pop{!P|}",         { RMrBP }, 0 },
1800   { "pop{!P|}",         { RMrSI }, 0 },
1801   { "pop{!P|}",         { RMrDI }, 0 },
1802   /* 60 */
1803   { X86_64_TABLE (X86_64_60) },
1804   { X86_64_TABLE (X86_64_61) },
1805   { X86_64_TABLE (X86_64_62) },
1806   { X86_64_TABLE (X86_64_63) },
1807   { Bad_Opcode },       /* seg fs */
1808   { Bad_Opcode },       /* seg gs */
1809   { Bad_Opcode },       /* op size prefix */
1810   { Bad_Opcode },       /* adr size prefix */
1811   /* 68 */
1812   { "pushP",            { sIv }, 0 },
1813   { "imulS",            { Gv, Ev, Iv }, 0 },
1814   { "pushP",            { sIbT }, 0 },
1815   { "imulS",            { Gv, Ev, sIb }, 0 },
1816   { "ins{b|}",          { Ybr, indirDX }, 0 },
1817   { X86_64_TABLE (X86_64_6D) },
1818   { "outs{b|}",         { indirDXr, Xb }, 0 },
1819   { X86_64_TABLE (X86_64_6F) },
1820   /* 70 */
1821   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1822   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1823   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1824   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1825   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1826   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1827   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1828   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1829   /* 78 */
1830   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1831   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1832   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1833   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1834   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1835   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1836   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1837   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1838   /* 80 */
1839   { REG_TABLE (REG_80) },
1840   { REG_TABLE (REG_81) },
1841   { X86_64_TABLE (X86_64_82) },
1842   { REG_TABLE (REG_83) },
1843   { "testB",            { Eb, Gb }, 0 },
1844   { "testS",            { Ev, Gv }, 0 },
1845   { "xchgB",            { Ebh2, Gb }, 0 },
1846   { "xchgS",            { Evh2, Gv }, 0 },
1847   /* 88 */
1848   { "movB",             { Ebh3, Gb }, 0 },
1849   { "movS",             { Evh3, Gv }, 0 },
1850   { "movB",             { Gb, EbS }, 0 },
1851   { "movS",             { Gv, EvS }, 0 },
1852   { "movD",             { Sv, Sw }, 0 },
1853   { MOD_TABLE (MOD_8D) },
1854   { "movD",             { Sw, Sv }, 0 },
1855   { REG_TABLE (REG_8F) },
1856   /* 90 */
1857   { PREFIX_TABLE (PREFIX_90) },
1858   { "xchgS",            { RMeCX, eAX }, 0 },
1859   { "xchgS",            { RMeDX, eAX }, 0 },
1860   { "xchgS",            { RMeBX, eAX }, 0 },
1861   { "xchgS",            { RMeSP, eAX }, 0 },
1862   { "xchgS",            { RMeBP, eAX }, 0 },
1863   { "xchgS",            { RMeSI, eAX }, 0 },
1864   { "xchgS",            { RMeDI, eAX }, 0 },
1865   /* 98 */
1866   { "cW{t|}R",          { XX }, 0 },
1867   { "cR{t|}O",          { XX }, 0 },
1868   { X86_64_TABLE (X86_64_9A) },
1869   { Bad_Opcode },       /* fwait */
1870   { "pushfP",           { XX }, 0 },
1871   { "popfP",            { XX }, 0 },
1872   { "sahf",             { XX }, 0 },
1873   { "lahf",             { XX }, 0 },
1874   /* a0 */
1875   { "mov%LB",           { AL, Ob }, 0 },
1876   { "mov%LS",           { eAX, Ov }, 0 },
1877   { "mov%LB",           { Ob, AL }, 0 },
1878   { "mov%LS",           { Ov, eAX }, 0 },
1879   { "movs{b|}",         { Ybr, Xb }, 0 },
1880   { "movs{R|}",         { Yvr, Xv }, 0 },
1881   { "cmps{b|}",         { Xb, Yb }, 0 },
1882   { "cmps{R|}",         { Xv, Yv }, 0 },
1883   /* a8 */
1884   { "testB",            { AL, Ib }, 0 },
1885   { "testS",            { eAX, Iv }, 0 },
1886   { "stosB",            { Ybr, AL }, 0 },
1887   { "stosS",            { Yvr, eAX }, 0 },
1888   { "lodsB",            { ALr, Xb }, 0 },
1889   { "lodsS",            { eAXr, Xv }, 0 },
1890   { "scasB",            { AL, Yb }, 0 },
1891   { "scasS",            { eAX, Yv }, 0 },
1892   /* b0 */
1893   { "movB",             { RMAL, Ib }, 0 },
1894   { "movB",             { RMCL, Ib }, 0 },
1895   { "movB",             { RMDL, Ib }, 0 },
1896   { "movB",             { RMBL, Ib }, 0 },
1897   { "movB",             { RMAH, Ib }, 0 },
1898   { "movB",             { RMCH, Ib }, 0 },
1899   { "movB",             { RMDH, Ib }, 0 },
1900   { "movB",             { RMBH, Ib }, 0 },
1901   /* b8 */
1902   { "mov%LV",           { RMeAX, Iv64 }, 0 },
1903   { "mov%LV",           { RMeCX, Iv64 }, 0 },
1904   { "mov%LV",           { RMeDX, Iv64 }, 0 },
1905   { "mov%LV",           { RMeBX, Iv64 }, 0 },
1906   { "mov%LV",           { RMeSP, Iv64 }, 0 },
1907   { "mov%LV",           { RMeBP, Iv64 }, 0 },
1908   { "mov%LV",           { RMeSI, Iv64 }, 0 },
1909   { "mov%LV",           { RMeDI, Iv64 }, 0 },
1910   /* c0 */
1911   { REG_TABLE (REG_C0) },
1912   { REG_TABLE (REG_C1) },
1913   { X86_64_TABLE (X86_64_C2) },
1914   { X86_64_TABLE (X86_64_C3) },
1915   { X86_64_TABLE (X86_64_C4) },
1916   { X86_64_TABLE (X86_64_C5) },
1917   { REG_TABLE (REG_C6) },
1918   { REG_TABLE (REG_C7) },
1919   /* c8 */
1920   { "enterP",           { Iw, Ib }, 0 },
1921   { "leaveP",           { XX }, 0 },
1922   { "{l|}ret{|f}%LP",   { Iw }, 0 },
1923   { "{l|}ret{|f}%LP",   { XX }, 0 },
1924   { "int3",             { XX }, 0 },
1925   { "int",              { Ib }, 0 },
1926   { X86_64_TABLE (X86_64_CE) },
1927   { "iret%LP",          { XX }, 0 },
1928   /* d0 */
1929   { REG_TABLE (REG_D0) },
1930   { REG_TABLE (REG_D1) },
1931   { REG_TABLE (REG_D2) },
1932   { REG_TABLE (REG_D3) },
1933   { X86_64_TABLE (X86_64_D4) },
1934   { X86_64_TABLE (X86_64_D5) },
1935   { Bad_Opcode },
1936   { "xlat",             { DSBX }, 0 },
1937   /* d8 */
1938   { FLOAT },
1939   { FLOAT },
1940   { FLOAT },
1941   { FLOAT },
1942   { FLOAT },
1943   { FLOAT },
1944   { FLOAT },
1945   { FLOAT },
1946   /* e0 */
1947   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
1948   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
1949   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
1950   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
1951   { "inB",              { AL, Ib }, 0 },
1952   { "inG",              { zAX, Ib }, 0 },
1953   { "outB",             { Ib, AL }, 0 },
1954   { "outG",             { Ib, zAX }, 0 },
1955   /* e8 */
1956   { X86_64_TABLE (X86_64_E8) },
1957   { X86_64_TABLE (X86_64_E9) },
1958   { X86_64_TABLE (X86_64_EA) },
1959   { "jmp",              { Jb, BND }, 0 },
1960   { "inB",              { AL, indirDX }, 0 },
1961   { "inG",              { zAX, indirDX }, 0 },
1962   { "outB",             { indirDX, AL }, 0 },
1963   { "outG",             { indirDX, zAX }, 0 },
1964   /* f0 */
1965   { Bad_Opcode },       /* lock prefix */
1966   { "icebp",            { XX }, 0 },
1967   { Bad_Opcode },       /* repne */
1968   { Bad_Opcode },       /* repz */
1969   { "hlt",              { XX }, 0 },
1970   { "cmc",              { XX }, 0 },
1971   { REG_TABLE (REG_F6) },
1972   { REG_TABLE (REG_F7) },
1973   /* f8 */
1974   { "clc",              { XX }, 0 },
1975   { "stc",              { XX }, 0 },
1976   { "cli",              { XX }, 0 },
1977   { "sti",              { XX }, 0 },
1978   { "cld",              { XX }, 0 },
1979   { "std",              { XX }, 0 },
1980   { REG_TABLE (REG_FE) },
1981   { REG_TABLE (REG_FF) },
1982 };
1983
1984 static const struct dis386 dis386_twobyte[] = {
1985   /* 00 */
1986   { REG_TABLE (REG_0F00 ) },
1987   { REG_TABLE (REG_0F01 ) },
1988   { "larS",             { Gv, Ew }, 0 },
1989   { "lslS",             { Gv, Ew }, 0 },
1990   { Bad_Opcode },
1991   { "syscall",          { XX }, 0 },
1992   { "clts",             { XX }, 0 },
1993   { "sysret%LQ",                { XX }, 0 },
1994   /* 08 */
1995   { "invd",             { XX }, 0 },
1996   { PREFIX_TABLE (PREFIX_0F09) },
1997   { Bad_Opcode },
1998   { "ud2",              { XX }, 0 },
1999   { Bad_Opcode },
2000   { REG_TABLE (REG_0F0D) },
2001   { "femms",            { XX }, 0 },
2002   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2003   /* 10 */
2004   { PREFIX_TABLE (PREFIX_0F10) },
2005   { PREFIX_TABLE (PREFIX_0F11) },
2006   { PREFIX_TABLE (PREFIX_0F12) },
2007   { MOD_TABLE (MOD_0F13) },
2008   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2009   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2010   { PREFIX_TABLE (PREFIX_0F16) },
2011   { MOD_TABLE (MOD_0F17) },
2012   /* 18 */
2013   { REG_TABLE (REG_0F18) },
2014   { "nopQ",             { Ev }, 0 },
2015   { PREFIX_TABLE (PREFIX_0F1A) },
2016   { PREFIX_TABLE (PREFIX_0F1B) },
2017   { PREFIX_TABLE (PREFIX_0F1C) },
2018   { "nopQ",             { Ev }, 0 },
2019   { PREFIX_TABLE (PREFIX_0F1E) },
2020   { "nopQ",             { Ev }, 0 },
2021   /* 20 */
2022   { "movZ",             { Em, Cm }, 0 },
2023   { "movZ",             { Em, Dm }, 0 },
2024   { "movZ",             { Cm, Em }, 0 },
2025   { "movZ",             { Dm, Em }, 0 },
2026   { X86_64_TABLE (X86_64_0F24) },
2027   { Bad_Opcode },
2028   { X86_64_TABLE (X86_64_0F26) },
2029   { Bad_Opcode },
2030   /* 28 */
2031   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2032   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2033   { PREFIX_TABLE (PREFIX_0F2A) },
2034   { PREFIX_TABLE (PREFIX_0F2B) },
2035   { PREFIX_TABLE (PREFIX_0F2C) },
2036   { PREFIX_TABLE (PREFIX_0F2D) },
2037   { PREFIX_TABLE (PREFIX_0F2E) },
2038   { PREFIX_TABLE (PREFIX_0F2F) },
2039   /* 30 */
2040   { "wrmsr",            { XX }, 0 },
2041   { "rdtsc",            { XX }, 0 },
2042   { "rdmsr",            { XX }, 0 },
2043   { "rdpmc",            { XX }, 0 },
2044   { "sysenter",         { SEP }, 0 },
2045   { "sysexit%LQ",       { SEP }, 0 },
2046   { Bad_Opcode },
2047   { "getsec",           { XX }, 0 },
2048   /* 38 */
2049   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2050   { Bad_Opcode },
2051   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2052   { Bad_Opcode },
2053   { Bad_Opcode },
2054   { Bad_Opcode },
2055   { Bad_Opcode },
2056   { Bad_Opcode },
2057   /* 40 */
2058   { "cmovoS",           { Gv, Ev }, 0 },
2059   { "cmovnoS",          { Gv, Ev }, 0 },
2060   { "cmovbS",           { Gv, Ev }, 0 },
2061   { "cmovaeS",          { Gv, Ev }, 0 },
2062   { "cmoveS",           { Gv, Ev }, 0 },
2063   { "cmovneS",          { Gv, Ev }, 0 },
2064   { "cmovbeS",          { Gv, Ev }, 0 },
2065   { "cmovaS",           { Gv, Ev }, 0 },
2066   /* 48 */
2067   { "cmovsS",           { Gv, Ev }, 0 },
2068   { "cmovnsS",          { Gv, Ev }, 0 },
2069   { "cmovpS",           { Gv, Ev }, 0 },
2070   { "cmovnpS",          { Gv, Ev }, 0 },
2071   { "cmovlS",           { Gv, Ev }, 0 },
2072   { "cmovgeS",          { Gv, Ev }, 0 },
2073   { "cmovleS",          { Gv, Ev }, 0 },
2074   { "cmovgS",           { Gv, Ev }, 0 },
2075   /* 50 */
2076   { MOD_TABLE (MOD_0F50) },
2077   { PREFIX_TABLE (PREFIX_0F51) },
2078   { PREFIX_TABLE (PREFIX_0F52) },
2079   { PREFIX_TABLE (PREFIX_0F53) },
2080   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2081   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2082   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2083   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2084   /* 58 */
2085   { PREFIX_TABLE (PREFIX_0F58) },
2086   { PREFIX_TABLE (PREFIX_0F59) },
2087   { PREFIX_TABLE (PREFIX_0F5A) },
2088   { PREFIX_TABLE (PREFIX_0F5B) },
2089   { PREFIX_TABLE (PREFIX_0F5C) },
2090   { PREFIX_TABLE (PREFIX_0F5D) },
2091   { PREFIX_TABLE (PREFIX_0F5E) },
2092   { PREFIX_TABLE (PREFIX_0F5F) },
2093   /* 60 */
2094   { PREFIX_TABLE (PREFIX_0F60) },
2095   { PREFIX_TABLE (PREFIX_0F61) },
2096   { PREFIX_TABLE (PREFIX_0F62) },
2097   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2098   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2099   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2100   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2101   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2102   /* 68 */
2103   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2104   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2105   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2106   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2107   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2108   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2109   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2110   { PREFIX_TABLE (PREFIX_0F6F) },
2111   /* 70 */
2112   { PREFIX_TABLE (PREFIX_0F70) },
2113   { MOD_TABLE (MOD_0F71) },
2114   { MOD_TABLE (MOD_0F72) },
2115   { MOD_TABLE (MOD_0F73) },
2116   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2117   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2118   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2119   { "emms",             { XX }, PREFIX_OPCODE },
2120   /* 78 */
2121   { PREFIX_TABLE (PREFIX_0F78) },
2122   { PREFIX_TABLE (PREFIX_0F79) },
2123   { Bad_Opcode },
2124   { Bad_Opcode },
2125   { PREFIX_TABLE (PREFIX_0F7C) },
2126   { PREFIX_TABLE (PREFIX_0F7D) },
2127   { PREFIX_TABLE (PREFIX_0F7E) },
2128   { PREFIX_TABLE (PREFIX_0F7F) },
2129   /* 80 */
2130   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2131   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2132   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2133   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2134   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2135   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2136   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2137   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2138   /* 88 */
2139   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2140   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2141   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2142   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2143   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2144   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2145   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2146   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2147   /* 90 */
2148   { "seto",             { Eb }, 0 },
2149   { "setno",            { Eb }, 0 },
2150   { "setb",             { Eb }, 0 },
2151   { "setae",            { Eb }, 0 },
2152   { "sete",             { Eb }, 0 },
2153   { "setne",            { Eb }, 0 },
2154   { "setbe",            { Eb }, 0 },
2155   { "seta",             { Eb }, 0 },
2156   /* 98 */
2157   { "sets",             { Eb }, 0 },
2158   { "setns",            { Eb }, 0 },
2159   { "setp",             { Eb }, 0 },
2160   { "setnp",            { Eb }, 0 },
2161   { "setl",             { Eb }, 0 },
2162   { "setge",            { Eb }, 0 },
2163   { "setle",            { Eb }, 0 },
2164   { "setg",             { Eb }, 0 },
2165   /* a0 */
2166   { "pushP",            { fs }, 0 },
2167   { "popP",             { fs }, 0 },
2168   { "cpuid",            { XX }, 0 },
2169   { "btS",              { Ev, Gv }, 0 },
2170   { "shldS",            { Ev, Gv, Ib }, 0 },
2171   { "shldS",            { Ev, Gv, CL }, 0 },
2172   { REG_TABLE (REG_0FA6) },
2173   { REG_TABLE (REG_0FA7) },
2174   /* a8 */
2175   { "pushP",            { gs }, 0 },
2176   { "popP",             { gs }, 0 },
2177   { "rsm",              { XX }, 0 },
2178   { "btsS",             { Evh1, Gv }, 0 },
2179   { "shrdS",            { Ev, Gv, Ib }, 0 },
2180   { "shrdS",            { Ev, Gv, CL }, 0 },
2181   { REG_TABLE (REG_0FAE) },
2182   { "imulS",            { Gv, Ev }, 0 },
2183   /* b0 */
2184   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2185   { "cmpxchgS",         { Evh1, Gv }, 0 },
2186   { MOD_TABLE (MOD_0FB2) },
2187   { "btrS",             { Evh1, Gv }, 0 },
2188   { MOD_TABLE (MOD_0FB4) },
2189   { MOD_TABLE (MOD_0FB5) },
2190   { "movz{bR|x}",       { Gv, Eb }, 0 },
2191   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2192   /* b8 */
2193   { PREFIX_TABLE (PREFIX_0FB8) },
2194   { "ud1S",             { Gv, Ev }, 0 },
2195   { REG_TABLE (REG_0FBA) },
2196   { "btcS",             { Evh1, Gv }, 0 },
2197   { PREFIX_TABLE (PREFIX_0FBC) },
2198   { PREFIX_TABLE (PREFIX_0FBD) },
2199   { "movs{bR|x}",       { Gv, Eb }, 0 },
2200   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2201   /* c0 */
2202   { "xaddB",            { Ebh1, Gb }, 0 },
2203   { "xaddS",            { Evh1, Gv }, 0 },
2204   { PREFIX_TABLE (PREFIX_0FC2) },
2205   { MOD_TABLE (MOD_0FC3) },
2206   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2207   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2208   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2209   { REG_TABLE (REG_0FC7) },
2210   /* c8 */
2211   { "bswap",            { RMeAX }, 0 },
2212   { "bswap",            { RMeCX }, 0 },
2213   { "bswap",            { RMeDX }, 0 },
2214   { "bswap",            { RMeBX }, 0 },
2215   { "bswap",            { RMeSP }, 0 },
2216   { "bswap",            { RMeBP }, 0 },
2217   { "bswap",            { RMeSI }, 0 },
2218   { "bswap",            { RMeDI }, 0 },
2219   /* d0 */
2220   { PREFIX_TABLE (PREFIX_0FD0) },
2221   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2222   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2223   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2224   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2225   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2226   { PREFIX_TABLE (PREFIX_0FD6) },
2227   { MOD_TABLE (MOD_0FD7) },
2228   /* d8 */
2229   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2230   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2231   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2232   { "pand",             { MX, EM }, PREFIX_OPCODE },
2233   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2234   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2235   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2236   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2237   /* e0 */
2238   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2239   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2240   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2241   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2242   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2243   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2244   { PREFIX_TABLE (PREFIX_0FE6) },
2245   { PREFIX_TABLE (PREFIX_0FE7) },
2246   /* e8 */
2247   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2248   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2249   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2250   { "por",              { MX, EM }, PREFIX_OPCODE },
2251   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2252   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2253   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2254   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2255   /* f0 */
2256   { PREFIX_TABLE (PREFIX_0FF0) },
2257   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2258   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2259   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2260   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2261   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2262   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2263   { PREFIX_TABLE (PREFIX_0FF7) },
2264   /* f8 */
2265   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2266   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2267   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2268   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2269   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2270   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2271   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2272   { "ud0S",             { Gv, Ev }, 0 },
2273 };
2274
2275 static const unsigned char onebyte_has_modrm[256] = {
2276   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2277   /*       -------------------------------        */
2278   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2279   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2280   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2281   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2282   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2283   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2284   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2285   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2286   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2287   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2288   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2289   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2290   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2291   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2292   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2293   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2294   /*       -------------------------------        */
2295   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2296 };
2297
2298 static const unsigned char twobyte_has_modrm[256] = {
2299   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2300   /*       -------------------------------        */
2301   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2302   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2303   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2304   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2305   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2306   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2307   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2308   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2309   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2310   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2311   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2312   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2313   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2314   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2315   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2316   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2317   /*       -------------------------------        */
2318   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2319 };
2320
2321 static char obuf[100];
2322 static char *obufp;
2323 static char *mnemonicendp;
2324 static char scratchbuf[100];
2325 static unsigned char *start_codep;
2326 static unsigned char *insn_codep;
2327 static unsigned char *codep;
2328 static unsigned char *end_codep;
2329 static int last_lock_prefix;
2330 static int last_repz_prefix;
2331 static int last_repnz_prefix;
2332 static int last_data_prefix;
2333 static int last_addr_prefix;
2334 static int last_rex_prefix;
2335 static int last_seg_prefix;
2336 static int fwait_prefix;
2337 /* The active segment register prefix.  */
2338 static int active_seg_prefix;
2339 #define MAX_CODE_LENGTH 15
2340 /* We can up to 14 prefixes since the maximum instruction length is
2341    15bytes.  */
2342 static int all_prefixes[MAX_CODE_LENGTH - 1];
2343 static disassemble_info *the_info;
2344 static struct
2345   {
2346     int mod;
2347     int reg;
2348     int rm;
2349   }
2350 modrm;
2351 static unsigned char need_modrm;
2352 static struct
2353   {
2354     int scale;
2355     int index;
2356     int base;
2357   }
2358 sib;
2359 static struct
2360   {
2361     int register_specifier;
2362     int length;
2363     int prefix;
2364     int w;
2365     int evex;
2366     int r;
2367     int v;
2368     int mask_register_specifier;
2369     int zeroing;
2370     int ll;
2371     int b;
2372   }
2373 vex;
2374 static unsigned char need_vex;
2375
2376 struct op
2377   {
2378     const char *name;
2379     unsigned int len;
2380   };
2381
2382 /* If we are accessing mod/rm/reg without need_modrm set, then the
2383    values are stale.  Hitting this abort likely indicates that you
2384    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2385 #define MODRM_CHECK  if (!need_modrm) abort ()
2386
2387 static const char **names64;
2388 static const char **names32;
2389 static const char **names16;
2390 static const char **names8;
2391 static const char **names8rex;
2392 static const char **names_seg;
2393 static const char *index64;
2394 static const char *index32;
2395 static const char **index16;
2396 static const char **names_bnd;
2397
2398 static const char *intel_names64[] = {
2399   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2400   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2401 };
2402 static const char *intel_names32[] = {
2403   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2404   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2405 };
2406 static const char *intel_names16[] = {
2407   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2408   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2409 };
2410 static const char *intel_names8[] = {
2411   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2412 };
2413 static const char *intel_names8rex[] = {
2414   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2415   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2416 };
2417 static const char *intel_names_seg[] = {
2418   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2419 };
2420 static const char *intel_index64 = "riz";
2421 static const char *intel_index32 = "eiz";
2422 static const char *intel_index16[] = {
2423   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2424 };
2425
2426 static const char *att_names64[] = {
2427   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2428   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2429 };
2430 static const char *att_names32[] = {
2431   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2432   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2433 };
2434 static const char *att_names16[] = {
2435   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2436   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2437 };
2438 static const char *att_names8[] = {
2439   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2440 };
2441 static const char *att_names8rex[] = {
2442   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2443   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2444 };
2445 static const char *att_names_seg[] = {
2446   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2447 };
2448 static const char *att_index64 = "%riz";
2449 static const char *att_index32 = "%eiz";
2450 static const char *att_index16[] = {
2451   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2452 };
2453
2454 static const char **names_mm;
2455 static const char *intel_names_mm[] = {
2456   "mm0", "mm1", "mm2", "mm3",
2457   "mm4", "mm5", "mm6", "mm7"
2458 };
2459 static const char *att_names_mm[] = {
2460   "%mm0", "%mm1", "%mm2", "%mm3",
2461   "%mm4", "%mm5", "%mm6", "%mm7"
2462 };
2463
2464 static const char *intel_names_bnd[] = {
2465   "bnd0", "bnd1", "bnd2", "bnd3"
2466 };
2467
2468 static const char *att_names_bnd[] = {
2469   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2470 };
2471
2472 static const char **names_xmm;
2473 static const char *intel_names_xmm[] = {
2474   "xmm0", "xmm1", "xmm2", "xmm3",
2475   "xmm4", "xmm5", "xmm6", "xmm7",
2476   "xmm8", "xmm9", "xmm10", "xmm11",
2477   "xmm12", "xmm13", "xmm14", "xmm15",
2478   "xmm16", "xmm17", "xmm18", "xmm19",
2479   "xmm20", "xmm21", "xmm22", "xmm23",
2480   "xmm24", "xmm25", "xmm26", "xmm27",
2481   "xmm28", "xmm29", "xmm30", "xmm31"
2482 };
2483 static const char *att_names_xmm[] = {
2484   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2485   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2486   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2487   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2488   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2489   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2490   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2491   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2492 };
2493
2494 static const char **names_ymm;
2495 static const char *intel_names_ymm[] = {
2496   "ymm0", "ymm1", "ymm2", "ymm3",
2497   "ymm4", "ymm5", "ymm6", "ymm7",
2498   "ymm8", "ymm9", "ymm10", "ymm11",
2499   "ymm12", "ymm13", "ymm14", "ymm15",
2500   "ymm16", "ymm17", "ymm18", "ymm19",
2501   "ymm20", "ymm21", "ymm22", "ymm23",
2502   "ymm24", "ymm25", "ymm26", "ymm27",
2503   "ymm28", "ymm29", "ymm30", "ymm31"
2504 };
2505 static const char *att_names_ymm[] = {
2506   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2507   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2508   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2509   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2510   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2511   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2512   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2513   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2514 };
2515
2516 static const char **names_zmm;
2517 static const char *intel_names_zmm[] = {
2518   "zmm0", "zmm1", "zmm2", "zmm3",
2519   "zmm4", "zmm5", "zmm6", "zmm7",
2520   "zmm8", "zmm9", "zmm10", "zmm11",
2521   "zmm12", "zmm13", "zmm14", "zmm15",
2522   "zmm16", "zmm17", "zmm18", "zmm19",
2523   "zmm20", "zmm21", "zmm22", "zmm23",
2524   "zmm24", "zmm25", "zmm26", "zmm27",
2525   "zmm28", "zmm29", "zmm30", "zmm31"
2526 };
2527 static const char *att_names_zmm[] = {
2528   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2529   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2530   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2531   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2532   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2533   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2534   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2535   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2536 };
2537
2538 static const char **names_tmm;
2539 static const char *intel_names_tmm[] = {
2540   "tmm0", "tmm1", "tmm2", "tmm3",
2541   "tmm4", "tmm5", "tmm6", "tmm7"
2542 };
2543 static const char *att_names_tmm[] = {
2544   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2545   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2546 };
2547
2548 static const char **names_mask;
2549 static const char *intel_names_mask[] = {
2550   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2551 };
2552 static const char *att_names_mask[] = {
2553   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2554 };
2555
2556 static const char *names_rounding[] =
2557 {
2558   "{rn-sae}",
2559   "{rd-sae}",
2560   "{ru-sae}",
2561   "{rz-sae}"
2562 };
2563
2564 static const struct dis386 reg_table[][8] = {
2565   /* REG_80 */
2566   {
2567     { "addA",   { Ebh1, Ib }, 0 },
2568     { "orA",    { Ebh1, Ib }, 0 },
2569     { "adcA",   { Ebh1, Ib }, 0 },
2570     { "sbbA",   { Ebh1, Ib }, 0 },
2571     { "andA",   { Ebh1, Ib }, 0 },
2572     { "subA",   { Ebh1, Ib }, 0 },
2573     { "xorA",   { Ebh1, Ib }, 0 },
2574     { "cmpA",   { Eb, Ib }, 0 },
2575   },
2576   /* REG_81 */
2577   {
2578     { "addQ",   { Evh1, Iv }, 0 },
2579     { "orQ",    { Evh1, Iv }, 0 },
2580     { "adcQ",   { Evh1, Iv }, 0 },
2581     { "sbbQ",   { Evh1, Iv }, 0 },
2582     { "andQ",   { Evh1, Iv }, 0 },
2583     { "subQ",   { Evh1, Iv }, 0 },
2584     { "xorQ",   { Evh1, Iv }, 0 },
2585     { "cmpQ",   { Ev, Iv }, 0 },
2586   },
2587   /* REG_83 */
2588   {
2589     { "addQ",   { Evh1, sIb }, 0 },
2590     { "orQ",    { Evh1, sIb }, 0 },
2591     { "adcQ",   { Evh1, sIb }, 0 },
2592     { "sbbQ",   { Evh1, sIb }, 0 },
2593     { "andQ",   { Evh1, sIb }, 0 },
2594     { "subQ",   { Evh1, sIb }, 0 },
2595     { "xorQ",   { Evh1, sIb }, 0 },
2596     { "cmpQ",   { Ev, sIb }, 0 },
2597   },
2598   /* REG_8F */
2599   {
2600     { "pop{P|}", { stackEv }, 0 },
2601     { XOP_8F_TABLE (XOP_09) },
2602     { Bad_Opcode },
2603     { Bad_Opcode },
2604     { Bad_Opcode },
2605     { XOP_8F_TABLE (XOP_09) },
2606   },
2607   /* REG_C0 */
2608   {
2609     { "rolA",   { Eb, Ib }, 0 },
2610     { "rorA",   { Eb, Ib }, 0 },
2611     { "rclA",   { Eb, Ib }, 0 },
2612     { "rcrA",   { Eb, Ib }, 0 },
2613     { "shlA",   { Eb, Ib }, 0 },
2614     { "shrA",   { Eb, Ib }, 0 },
2615     { "shlA",   { Eb, Ib }, 0 },
2616     { "sarA",   { Eb, Ib }, 0 },
2617   },
2618   /* REG_C1 */
2619   {
2620     { "rolQ",   { Ev, Ib }, 0 },
2621     { "rorQ",   { Ev, Ib }, 0 },
2622     { "rclQ",   { Ev, Ib }, 0 },
2623     { "rcrQ",   { Ev, Ib }, 0 },
2624     { "shlQ",   { Ev, Ib }, 0 },
2625     { "shrQ",   { Ev, Ib }, 0 },
2626     { "shlQ",   { Ev, Ib }, 0 },
2627     { "sarQ",   { Ev, Ib }, 0 },
2628   },
2629   /* REG_C6 */
2630   {
2631     { "movA",   { Ebh3, Ib }, 0 },
2632     { Bad_Opcode },
2633     { Bad_Opcode },
2634     { Bad_Opcode },
2635     { Bad_Opcode },
2636     { Bad_Opcode },
2637     { Bad_Opcode },
2638     { MOD_TABLE (MOD_C6_REG_7) },
2639   },
2640   /* REG_C7 */
2641   {
2642     { "movQ",   { Evh3, Iv }, 0 },
2643     { Bad_Opcode },
2644     { Bad_Opcode },
2645     { Bad_Opcode },
2646     { Bad_Opcode },
2647     { Bad_Opcode },
2648     { Bad_Opcode },
2649     { MOD_TABLE (MOD_C7_REG_7) },
2650   },
2651   /* REG_D0 */
2652   {
2653     { "rolA",   { Eb, I1 }, 0 },
2654     { "rorA",   { Eb, I1 }, 0 },
2655     { "rclA",   { Eb, I1 }, 0 },
2656     { "rcrA",   { Eb, I1 }, 0 },
2657     { "shlA",   { Eb, I1 }, 0 },
2658     { "shrA",   { Eb, I1 }, 0 },
2659     { "shlA",   { Eb, I1 }, 0 },
2660     { "sarA",   { Eb, I1 }, 0 },
2661   },
2662   /* REG_D1 */
2663   {
2664     { "rolQ",   { Ev, I1 }, 0 },
2665     { "rorQ",   { Ev, I1 }, 0 },
2666     { "rclQ",   { Ev, I1 }, 0 },
2667     { "rcrQ",   { Ev, I1 }, 0 },
2668     { "shlQ",   { Ev, I1 }, 0 },
2669     { "shrQ",   { Ev, I1 }, 0 },
2670     { "shlQ",   { Ev, I1 }, 0 },
2671     { "sarQ",   { Ev, I1 }, 0 },
2672   },
2673   /* REG_D2 */
2674   {
2675     { "rolA",   { Eb, CL }, 0 },
2676     { "rorA",   { Eb, CL }, 0 },
2677     { "rclA",   { Eb, CL }, 0 },
2678     { "rcrA",   { Eb, CL }, 0 },
2679     { "shlA",   { Eb, CL }, 0 },
2680     { "shrA",   { Eb, CL }, 0 },
2681     { "shlA",   { Eb, CL }, 0 },
2682     { "sarA",   { Eb, CL }, 0 },
2683   },
2684   /* REG_D3 */
2685   {
2686     { "rolQ",   { Ev, CL }, 0 },
2687     { "rorQ",   { Ev, CL }, 0 },
2688     { "rclQ",   { Ev, CL }, 0 },
2689     { "rcrQ",   { Ev, CL }, 0 },
2690     { "shlQ",   { Ev, CL }, 0 },
2691     { "shrQ",   { Ev, CL }, 0 },
2692     { "shlQ",   { Ev, CL }, 0 },
2693     { "sarQ",   { Ev, CL }, 0 },
2694   },
2695   /* REG_F6 */
2696   {
2697     { "testA",  { Eb, Ib }, 0 },
2698     { "testA",  { Eb, Ib }, 0 },
2699     { "notA",   { Ebh1 }, 0 },
2700     { "negA",   { Ebh1 }, 0 },
2701     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2702     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2703     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2704     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2705   },
2706   /* REG_F7 */
2707   {
2708     { "testQ",  { Ev, Iv }, 0 },
2709     { "testQ",  { Ev, Iv }, 0 },
2710     { "notQ",   { Evh1 }, 0 },
2711     { "negQ",   { Evh1 }, 0 },
2712     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2713     { "imulQ",  { Ev }, 0 },
2714     { "divQ",   { Ev }, 0 },
2715     { "idivQ",  { Ev }, 0 },
2716   },
2717   /* REG_FE */
2718   {
2719     { "incA",   { Ebh1 }, 0 },
2720     { "decA",   { Ebh1 }, 0 },
2721   },
2722   /* REG_FF */
2723   {
2724     { "incQ",   { Evh1 }, 0 },
2725     { "decQ",   { Evh1 }, 0 },
2726     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2727     { MOD_TABLE (MOD_FF_REG_3) },
2728     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2729     { MOD_TABLE (MOD_FF_REG_5) },
2730     { "push{P|}", { stackEv }, 0 },
2731     { Bad_Opcode },
2732   },
2733   /* REG_0F00 */
2734   {
2735     { "sldtD",  { Sv }, 0 },
2736     { "strD",   { Sv }, 0 },
2737     { "lldt",   { Ew }, 0 },
2738     { "ltr",    { Ew }, 0 },
2739     { "verr",   { Ew }, 0 },
2740     { "verw",   { Ew }, 0 },
2741     { Bad_Opcode },
2742     { Bad_Opcode },
2743   },
2744   /* REG_0F01 */
2745   {
2746     { MOD_TABLE (MOD_0F01_REG_0) },
2747     { MOD_TABLE (MOD_0F01_REG_1) },
2748     { MOD_TABLE (MOD_0F01_REG_2) },
2749     { MOD_TABLE (MOD_0F01_REG_3) },
2750     { "smswD",  { Sv }, 0 },
2751     { MOD_TABLE (MOD_0F01_REG_5) },
2752     { "lmsw",   { Ew }, 0 },
2753     { MOD_TABLE (MOD_0F01_REG_7) },
2754   },
2755   /* REG_0F0D */
2756   {
2757     { "prefetch",       { Mb }, 0 },
2758     { "prefetchw",      { Mb }, 0 },
2759     { "prefetchwt1",    { Mb }, 0 },
2760     { "prefetch",       { Mb }, 0 },
2761     { "prefetch",       { Mb }, 0 },
2762     { "prefetch",       { Mb }, 0 },
2763     { "prefetch",       { Mb }, 0 },
2764     { "prefetch",       { Mb }, 0 },
2765   },
2766   /* REG_0F18 */
2767   {
2768     { MOD_TABLE (MOD_0F18_REG_0) },
2769     { MOD_TABLE (MOD_0F18_REG_1) },
2770     { MOD_TABLE (MOD_0F18_REG_2) },
2771     { MOD_TABLE (MOD_0F18_REG_3) },
2772     { "nopQ",           { Ev }, 0 },
2773     { "nopQ",           { Ev }, 0 },
2774     { "nopQ",           { Ev }, 0 },
2775     { "nopQ",           { Ev }, 0 },
2776   },
2777   /* REG_0F1C_P_0_MOD_0 */
2778   {
2779     { "cldemote",       { Mb }, 0 },
2780     { "nopQ",           { Ev }, 0 },
2781     { "nopQ",           { Ev }, 0 },
2782     { "nopQ",           { Ev }, 0 },
2783     { "nopQ",           { Ev }, 0 },
2784     { "nopQ",           { Ev }, 0 },
2785     { "nopQ",           { Ev }, 0 },
2786     { "nopQ",           { Ev }, 0 },
2787   },
2788   /* REG_0F1E_P_1_MOD_3 */
2789   {
2790     { "nopQ",           { Ev }, PREFIX_IGNORED },
2791     { "rdsspK",         { Edq }, 0 },
2792     { "nopQ",           { Ev }, PREFIX_IGNORED },
2793     { "nopQ",           { Ev }, PREFIX_IGNORED },
2794     { "nopQ",           { Ev }, PREFIX_IGNORED },
2795     { "nopQ",           { Ev }, PREFIX_IGNORED },
2796     { "nopQ",           { Ev }, PREFIX_IGNORED },
2797     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2798   },
2799   /* REG_0F38D8_PREFIX_1 */
2800   {
2801     { "aesencwide128kl",        { M }, 0 },
2802     { "aesdecwide128kl",        { M }, 0 },
2803     { "aesencwide256kl",        { M }, 0 },
2804     { "aesdecwide256kl",        { M }, 0 },
2805   },
2806   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2807   {
2808     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2809   },
2810   /* REG_0F71_MOD_0 */
2811   {
2812     { Bad_Opcode },
2813     { Bad_Opcode },
2814     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
2815     { Bad_Opcode },
2816     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
2817     { Bad_Opcode },
2818     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
2819   },
2820   /* REG_0F72_MOD_0 */
2821   {
2822     { Bad_Opcode },
2823     { Bad_Opcode },
2824     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
2825     { Bad_Opcode },
2826     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
2827     { Bad_Opcode },
2828     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
2829   },
2830   /* REG_0F73_MOD_0 */
2831   {
2832     { Bad_Opcode },
2833     { Bad_Opcode },
2834     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
2835     { "psrldq",         { XS, Ib }, PREFIX_DATA },
2836     { Bad_Opcode },
2837     { Bad_Opcode },
2838     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
2839     { "pslldq",         { XS, Ib }, PREFIX_DATA },
2840   },
2841   /* REG_0FA6 */
2842   {
2843     { "montmul",        { { OP_0f07, 0 } }, 0 },
2844     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2845     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2846   },
2847   /* REG_0FA7 */
2848   {
2849     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2850     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2851     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2852     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2853     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2854     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2855   },
2856   /* REG_0FAE */
2857   {
2858     { MOD_TABLE (MOD_0FAE_REG_0) },
2859     { MOD_TABLE (MOD_0FAE_REG_1) },
2860     { MOD_TABLE (MOD_0FAE_REG_2) },
2861     { MOD_TABLE (MOD_0FAE_REG_3) },
2862     { MOD_TABLE (MOD_0FAE_REG_4) },
2863     { MOD_TABLE (MOD_0FAE_REG_5) },
2864     { MOD_TABLE (MOD_0FAE_REG_6) },
2865     { MOD_TABLE (MOD_0FAE_REG_7) },
2866   },
2867   /* REG_0FBA */
2868   {
2869     { Bad_Opcode },
2870     { Bad_Opcode },
2871     { Bad_Opcode },
2872     { Bad_Opcode },
2873     { "btQ",    { Ev, Ib }, 0 },
2874     { "btsQ",   { Evh1, Ib }, 0 },
2875     { "btrQ",   { Evh1, Ib }, 0 },
2876     { "btcQ",   { Evh1, Ib }, 0 },
2877   },
2878   /* REG_0FC7 */
2879   {
2880     { Bad_Opcode },
2881     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2882     { Bad_Opcode },
2883     { MOD_TABLE (MOD_0FC7_REG_3) },
2884     { MOD_TABLE (MOD_0FC7_REG_4) },
2885     { MOD_TABLE (MOD_0FC7_REG_5) },
2886     { MOD_TABLE (MOD_0FC7_REG_6) },
2887     { MOD_TABLE (MOD_0FC7_REG_7) },
2888   },
2889   /* REG_VEX_0F71_M_0 */
2890   {
2891     { Bad_Opcode },
2892     { Bad_Opcode },
2893     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
2894     { Bad_Opcode },
2895     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
2896     { Bad_Opcode },
2897     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
2898   },
2899   /* REG_VEX_0F72_M_0 */
2900   {
2901     { Bad_Opcode },
2902     { Bad_Opcode },
2903     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
2904     { Bad_Opcode },
2905     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
2906     { Bad_Opcode },
2907     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
2908   },
2909   /* REG_VEX_0F73_M_0 */
2910   {
2911     { Bad_Opcode },
2912     { Bad_Opcode },
2913     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
2914     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
2915     { Bad_Opcode },
2916     { Bad_Opcode },
2917     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
2918     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
2919   },
2920   /* REG_VEX_0FAE */
2921   {
2922     { Bad_Opcode },
2923     { Bad_Opcode },
2924     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2925     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2926   },
2927   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2928   {
2929     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2930   },
2931   /* REG_VEX_0F38F3_L_0 */
2932   {
2933     { Bad_Opcode },
2934     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
2935     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
2936     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
2937   },
2938   /* REG_XOP_09_01_L_0 */
2939   {
2940     { Bad_Opcode },
2941     { "blcfill",        { VexGdq, Edq }, 0 },
2942     { "blsfill",        { VexGdq, Edq }, 0 },
2943     { "blcs",   { VexGdq, Edq }, 0 },
2944     { "tzmsk",  { VexGdq, Edq }, 0 },
2945     { "blcic",  { VexGdq, Edq }, 0 },
2946     { "blsic",  { VexGdq, Edq }, 0 },
2947     { "t1mskc", { VexGdq, Edq }, 0 },
2948   },
2949   /* REG_XOP_09_02_L_0 */
2950   {
2951     { Bad_Opcode },
2952     { "blcmsk", { VexGdq, Edq }, 0 },
2953     { Bad_Opcode },
2954     { Bad_Opcode },
2955     { Bad_Opcode },
2956     { Bad_Opcode },
2957     { "blci",   { VexGdq, Edq }, 0 },
2958   },
2959   /* REG_XOP_09_12_M_1_L_0 */
2960   {
2961     { "llwpcb", { Edq }, 0 },
2962     { "slwpcb", { Edq }, 0 },
2963   },
2964   /* REG_XOP_0A_12_L_0 */
2965   {
2966     { "lwpins", { VexGdq, Ed, Id }, 0 },
2967     { "lwpval", { VexGdq, Ed, Id }, 0 },
2968   },
2969
2970 #include "i386-dis-evex-reg.h"
2971 };
2972
2973 static const struct dis386 prefix_table[][4] = {
2974   /* PREFIX_90 */
2975   {
2976     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
2977     { "pause", { XX }, 0 },
2978     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
2979     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2980   },
2981
2982   /* PREFIX_0F01_REG_1_RM_4 */
2983   {
2984     { Bad_Opcode },
2985     { Bad_Opcode },
2986     { "tdcall",         { Skip_MODRM }, 0 },
2987     { Bad_Opcode },
2988   },
2989
2990   /* PREFIX_0F01_REG_1_RM_5 */
2991   {
2992     { Bad_Opcode },
2993     { Bad_Opcode },
2994     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2995     { Bad_Opcode },
2996   },
2997
2998   /* PREFIX_0F01_REG_1_RM_6 */
2999   {
3000     { Bad_Opcode },
3001     { Bad_Opcode },
3002     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3003     { Bad_Opcode },
3004   },
3005
3006   /* PREFIX_0F01_REG_1_RM_7 */
3007   {
3008     { "encls",          { Skip_MODRM }, 0 },
3009     { Bad_Opcode },
3010     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3011     { Bad_Opcode },
3012   },
3013
3014   /* PREFIX_0F01_REG_3_RM_1 */
3015   {
3016     { "vmmcall",        { Skip_MODRM }, 0 },
3017     { "vmgexit",        { Skip_MODRM }, 0 },
3018     { Bad_Opcode },
3019     { "vmgexit",        { Skip_MODRM }, 0 },
3020   },
3021
3022   /* PREFIX_0F01_REG_5_MOD_0 */
3023   {
3024     { Bad_Opcode },
3025     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3026   },
3027
3028   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3029   {
3030     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3031     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3032     { Bad_Opcode },
3033     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3034   },
3035
3036   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3037   {
3038     { Bad_Opcode },
3039     { Bad_Opcode },
3040     { Bad_Opcode },
3041     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3042   },
3043
3044   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3045   {
3046     { Bad_Opcode },
3047     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3048   },
3049
3050   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3051   {
3052     { Bad_Opcode },
3053     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3054   },
3055
3056   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3057   {
3058     { Bad_Opcode },
3059     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3060   },
3061
3062   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3063   {
3064     { "rdpkru", { Skip_MODRM }, 0 },
3065     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3066   },
3067
3068   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3069   {
3070     { "wrpkru", { Skip_MODRM }, 0 },
3071     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3072   },
3073
3074   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3075   {
3076     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3077     { "mcommit",        { Skip_MODRM }, 0 },
3078   },
3079
3080   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3081   {
3082     { "invlpgb",        { Skip_MODRM }, 0 },
3083     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3084     { Bad_Opcode },
3085     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3086   },
3087
3088   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3089   {
3090     { "tlbsync",        { Skip_MODRM }, 0 },
3091     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3092     { Bad_Opcode },
3093     { "pvalidate",      { Skip_MODRM }, 0 },
3094   },
3095
3096   /* PREFIX_0F09 */
3097   {
3098     { "wbinvd",   { XX }, 0 },
3099     { "wbnoinvd", { XX }, 0 },
3100   },
3101
3102   /* PREFIX_0F10 */
3103   {
3104     { "movups", { XM, EXx }, PREFIX_OPCODE },
3105     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3106     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3107     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3108   },
3109
3110   /* PREFIX_0F11 */
3111   {
3112     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3113     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3114     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3115     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3116   },
3117
3118   /* PREFIX_0F12 */
3119   {
3120     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3121     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3122     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3123     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3124   },
3125
3126   /* PREFIX_0F16 */
3127   {
3128     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3129     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3130     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3131   },
3132
3133   /* PREFIX_0F1A */
3134   {
3135     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3136     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3137     { "bndmov", { Gbnd, Ebnd }, 0 },
3138     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3139   },
3140
3141   /* PREFIX_0F1B */
3142   {
3143     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3144     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3145     { "bndmov", { EbndS, Gbnd }, 0 },
3146     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3147   },
3148
3149   /* PREFIX_0F1C */
3150   {
3151     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3152     { "nopQ",   { Ev }, PREFIX_IGNORED },
3153     { "nopQ",   { Ev }, 0 },
3154     { "nopQ",   { Ev }, PREFIX_IGNORED },
3155   },
3156
3157   /* PREFIX_0F1E */
3158   {
3159     { "nopQ",   { Ev }, 0 },
3160     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3161     { "nopQ",   { Ev }, 0 },
3162     { NULL,     { XX }, PREFIX_IGNORED },
3163   },
3164
3165   /* PREFIX_0F2A */
3166   {
3167     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3168     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3169     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3170     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3171   },
3172
3173   /* PREFIX_0F2B */
3174   {
3175     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3176     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3177     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3178     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3179   },
3180
3181   /* PREFIX_0F2C */
3182   {
3183     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3184     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3185     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3186     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3187   },
3188
3189   /* PREFIX_0F2D */
3190   {
3191     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3192     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3193     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3194     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3195   },
3196
3197   /* PREFIX_0F2E */
3198   {
3199     { "ucomiss",{ XM, EXd }, 0 },
3200     { Bad_Opcode },
3201     { "ucomisd",{ XM, EXq }, 0 },
3202   },
3203
3204   /* PREFIX_0F2F */
3205   {
3206     { "comiss", { XM, EXd }, 0 },
3207     { Bad_Opcode },
3208     { "comisd", { XM, EXq }, 0 },
3209   },
3210
3211   /* PREFIX_0F51 */
3212   {
3213     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3214     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3215     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3216     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3217   },
3218
3219   /* PREFIX_0F52 */
3220   {
3221     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3222     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3223   },
3224
3225   /* PREFIX_0F53 */
3226   {
3227     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3228     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3229   },
3230
3231   /* PREFIX_0F58 */
3232   {
3233     { "addps", { XM, EXx }, PREFIX_OPCODE },
3234     { "addss", { XM, EXd }, PREFIX_OPCODE },
3235     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3236     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3237   },
3238
3239   /* PREFIX_0F59 */
3240   {
3241     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3242     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3243     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3244     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3245   },
3246
3247   /* PREFIX_0F5A */
3248   {
3249     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3250     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3251     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3252     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3253   },
3254
3255   /* PREFIX_0F5B */
3256   {
3257     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3258     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3259     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3260   },
3261
3262   /* PREFIX_0F5C */
3263   {
3264     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3265     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3266     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3267     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3268   },
3269
3270   /* PREFIX_0F5D */
3271   {
3272     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3273     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3274     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3275     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3276   },
3277
3278   /* PREFIX_0F5E */
3279   {
3280     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3281     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3282     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3283     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3284   },
3285
3286   /* PREFIX_0F5F */
3287   {
3288     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3289     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3290     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3291     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3292   },
3293
3294   /* PREFIX_0F60 */
3295   {
3296     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3297     { Bad_Opcode },
3298     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3299   },
3300
3301   /* PREFIX_0F61 */
3302   {
3303     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3304     { Bad_Opcode },
3305     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3306   },
3307
3308   /* PREFIX_0F62 */
3309   {
3310     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3311     { Bad_Opcode },
3312     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3313   },
3314
3315   /* PREFIX_0F6F */
3316   {
3317     { "movq",   { MX, EM }, PREFIX_OPCODE },
3318     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3319     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3320   },
3321
3322   /* PREFIX_0F70 */
3323   {
3324     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3325     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3326     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3327     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3328   },
3329
3330   /* PREFIX_0F78 */
3331   {
3332     {"vmread",  { Em, Gm }, 0 },
3333     { Bad_Opcode },
3334     {"extrq",   { XS, Ib, Ib }, 0 },
3335     {"insertq", { XM, XS, Ib, Ib }, 0 },
3336   },
3337
3338   /* PREFIX_0F79 */
3339   {
3340     {"vmwrite", { Gm, Em }, 0 },
3341     { Bad_Opcode },
3342     {"extrq",   { XM, XS }, 0 },
3343     {"insertq", { XM, XS }, 0 },
3344   },
3345
3346   /* PREFIX_0F7C */
3347   {
3348     { Bad_Opcode },
3349     { Bad_Opcode },
3350     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3351     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3352   },
3353
3354   /* PREFIX_0F7D */
3355   {
3356     { Bad_Opcode },
3357     { Bad_Opcode },
3358     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3359     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3360   },
3361
3362   /* PREFIX_0F7E */
3363   {
3364     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3365     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3366     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3367   },
3368
3369   /* PREFIX_0F7F */
3370   {
3371     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3372     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3373     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3374   },
3375
3376   /* PREFIX_0FAE_REG_0_MOD_3 */
3377   {
3378     { Bad_Opcode },
3379     { "rdfsbase", { Ev }, 0 },
3380   },
3381
3382   /* PREFIX_0FAE_REG_1_MOD_3 */
3383   {
3384     { Bad_Opcode },
3385     { "rdgsbase", { Ev }, 0 },
3386   },
3387
3388   /* PREFIX_0FAE_REG_2_MOD_3 */
3389   {
3390     { Bad_Opcode },
3391     { "wrfsbase", { Ev }, 0 },
3392   },
3393
3394   /* PREFIX_0FAE_REG_3_MOD_3 */
3395   {
3396     { Bad_Opcode },
3397     { "wrgsbase", { Ev }, 0 },
3398   },
3399
3400   /* PREFIX_0FAE_REG_4_MOD_0 */
3401   {
3402     { "xsave",  { FXSAVE }, 0 },
3403     { "ptwrite{%LQ|}", { Edq }, 0 },
3404   },
3405
3406   /* PREFIX_0FAE_REG_4_MOD_3 */
3407   {
3408     { Bad_Opcode },
3409     { "ptwrite{%LQ|}", { Edq }, 0 },
3410   },
3411
3412   /* PREFIX_0FAE_REG_5_MOD_3 */
3413   {
3414     { "lfence",         { Skip_MODRM }, 0 },
3415     { "incsspK",        { Edq }, PREFIX_OPCODE },
3416   },
3417
3418   /* PREFIX_0FAE_REG_6_MOD_0 */
3419   {
3420     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3421     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3422     { "clwb",   { Mb }, PREFIX_OPCODE },
3423   },
3424
3425   /* PREFIX_0FAE_REG_6_MOD_3 */
3426   {
3427     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3428     { "umonitor",       { Eva }, PREFIX_OPCODE },
3429     { "tpause", { Edq }, PREFIX_OPCODE },
3430     { "umwait", { Edq }, PREFIX_OPCODE },
3431   },
3432
3433   /* PREFIX_0FAE_REG_7_MOD_0 */
3434   {
3435     { "clflush",        { Mb }, 0 },
3436     { Bad_Opcode },
3437     { "clflushopt",     { Mb }, 0 },
3438   },
3439
3440   /* PREFIX_0FB8 */
3441   {
3442     { Bad_Opcode },
3443     { "popcntS", { Gv, Ev }, 0 },
3444   },
3445
3446   /* PREFIX_0FBC */
3447   {
3448     { "bsfS",   { Gv, Ev }, 0 },
3449     { "tzcntS", { Gv, Ev }, 0 },
3450     { "bsfS",   { Gv, Ev }, 0 },
3451   },
3452
3453   /* PREFIX_0FBD */
3454   {
3455     { "bsrS",   { Gv, Ev }, 0 },
3456     { "lzcntS", { Gv, Ev }, 0 },
3457     { "bsrS",   { Gv, Ev }, 0 },
3458   },
3459
3460   /* PREFIX_0FC2 */
3461   {
3462     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3463     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3464     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3465     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3466   },
3467
3468   /* PREFIX_0FC7_REG_6_MOD_0 */
3469   {
3470     { "vmptrld",{ Mq }, 0 },
3471     { "vmxon",  { Mq }, 0 },
3472     { "vmclear",{ Mq }, 0 },
3473   },
3474
3475   /* PREFIX_0FC7_REG_6_MOD_3 */
3476   {
3477     { "rdrand", { Ev }, 0 },
3478     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3479     { "rdrand", { Ev }, 0 }
3480   },
3481
3482   /* PREFIX_0FC7_REG_7_MOD_3 */
3483   {
3484     { "rdseed", { Ev }, 0 },
3485     { "rdpid",  { Em }, 0 },
3486     { "rdseed", { Ev }, 0 },
3487   },
3488
3489   /* PREFIX_0FD0 */
3490   {
3491     { Bad_Opcode },
3492     { Bad_Opcode },
3493     { "addsubpd", { XM, EXx }, 0 },
3494     { "addsubps", { XM, EXx }, 0 },
3495   },
3496
3497   /* PREFIX_0FD6 */
3498   {
3499     { Bad_Opcode },
3500     { "movq2dq",{ XM, MS }, 0 },
3501     { "movq",   { EXqS, XM }, 0 },
3502     { "movdq2q",{ MX, XS }, 0 },
3503   },
3504
3505   /* PREFIX_0FE6 */
3506   {
3507     { Bad_Opcode },
3508     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3509     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3510     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3511   },
3512
3513   /* PREFIX_0FE7 */
3514   {
3515     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3516     { Bad_Opcode },
3517     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3518   },
3519
3520   /* PREFIX_0FF0 */
3521   {
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3526   },
3527
3528   /* PREFIX_0FF7 */
3529   {
3530     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3531     { Bad_Opcode },
3532     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3533   },
3534
3535   /* PREFIX_0F38D8 */
3536   {
3537     { Bad_Opcode },
3538     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3539   },
3540
3541   /* PREFIX_0F38DC */
3542   {
3543     { Bad_Opcode },
3544     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3545     { "aesenc", { XM, EXx }, 0 },
3546   },
3547
3548   /* PREFIX_0F38DD */
3549   {
3550     { Bad_Opcode },
3551     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3552     { "aesenclast", { XM, EXx }, 0 },
3553   },
3554
3555   /* PREFIX_0F38DE */
3556   {
3557     { Bad_Opcode },
3558     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3559     { "aesdec", { XM, EXx }, 0 },
3560   },
3561
3562   /* PREFIX_0F38DF */
3563   {
3564     { Bad_Opcode },
3565     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3566     { "aesdeclast", { XM, EXx }, 0 },
3567   },
3568
3569   /* PREFIX_0F38F0 */
3570   {
3571     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3572     { Bad_Opcode },
3573     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3574     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3575   },
3576
3577   /* PREFIX_0F38F1 */
3578   {
3579     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3580     { Bad_Opcode },
3581     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3582     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3583   },
3584
3585   /* PREFIX_0F38F6 */
3586   {
3587     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3588     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3589     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3590     { Bad_Opcode },
3591   },
3592
3593   /* PREFIX_0F38F8 */
3594   {
3595     { Bad_Opcode },
3596     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3597     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3598     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3599   },
3600   /* PREFIX_0F38FA */
3601   {
3602     { Bad_Opcode },
3603     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3604   },
3605
3606   /* PREFIX_0F38FB */
3607   {
3608     { Bad_Opcode },
3609     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3610   },
3611
3612   /* PREFIX_0F3A0F */
3613   {
3614     { Bad_Opcode },
3615     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3616   },
3617
3618   /* PREFIX_VEX_0F10 */
3619   {
3620     { "vmovups",        { XM, EXx }, 0 },
3621     { "vmovss",         { XMScalar, VexScalarR, EXxmm_md }, 0 },
3622     { "vmovupd",        { XM, EXx }, 0 },
3623     { "vmovsd",         { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3624   },
3625
3626   /* PREFIX_VEX_0F11 */
3627   {
3628     { "vmovups",        { EXxS, XM }, 0 },
3629     { "vmovss",         { EXdS, VexScalarR, XMScalar }, 0 },
3630     { "vmovupd",        { EXxS, XM }, 0 },
3631     { "vmovsd",         { EXqS, VexScalarR, XMScalar }, 0 },
3632   },
3633
3634   /* PREFIX_VEX_0F12 */
3635   {
3636     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3637     { "vmovsldup",      { XM, EXx }, 0 },
3638     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3639     { "vmovddup",       { XM, EXymmq }, 0 },
3640   },
3641
3642   /* PREFIX_VEX_0F16 */
3643   {
3644     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3645     { "vmovshdup",      { XM, EXx }, 0 },
3646     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3647   },
3648
3649   /* PREFIX_VEX_0F2A */
3650   {
3651     { Bad_Opcode },
3652     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3653     { Bad_Opcode },
3654     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3655   },
3656
3657   /* PREFIX_VEX_0F2C */
3658   {
3659     { Bad_Opcode },
3660     { "vcvttss2si",     { Gdq, EXxmm_md, EXxEVexS }, 0 },
3661     { Bad_Opcode },
3662     { "vcvttsd2si",     { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3663   },
3664
3665   /* PREFIX_VEX_0F2D */
3666   {
3667     { Bad_Opcode },
3668     { "vcvtss2si",      { Gdq, EXxmm_md, EXxEVexR }, 0 },
3669     { Bad_Opcode },
3670     { "vcvtsd2si",      { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3671   },
3672
3673   /* PREFIX_VEX_0F2E */
3674   {
3675     { "vucomisX",       { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3676     { Bad_Opcode },
3677     { "vucomisX",       { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3678   },
3679
3680   /* PREFIX_VEX_0F2F */
3681   {
3682     { "vcomisX",        { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3683     { Bad_Opcode },
3684     { "vcomisX",        { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3685   },
3686
3687   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3688   {
3689     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3690     { Bad_Opcode },
3691     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3692   },
3693
3694   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3695   {
3696     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3697     { Bad_Opcode },
3698     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3699   },
3700
3701   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3702   {
3703     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3704     { Bad_Opcode },
3705     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3706   },
3707
3708   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3709   {
3710     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3711     { Bad_Opcode },
3712     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3713   },
3714
3715   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3716   {
3717     { "knotw",          { MaskG, MaskE }, 0 },
3718     { Bad_Opcode },
3719     { "knotb",          { MaskG, MaskE }, 0 },
3720   },
3721
3722   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3723   {
3724     { "knotq",          { MaskG, MaskE }, 0 },
3725     { Bad_Opcode },
3726     { "knotd",          { MaskG, MaskE }, 0 },
3727   },
3728
3729   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3730   {
3731     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3732     { Bad_Opcode },
3733     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3734   },
3735
3736   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3737   {
3738     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3739     { Bad_Opcode },
3740     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3741   },
3742
3743   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3744   {
3745     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3746     { Bad_Opcode },
3747     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3748   },
3749
3750   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3751   {
3752     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3753     { Bad_Opcode },
3754     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3755   },
3756
3757   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3758   {
3759     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3760     { Bad_Opcode },
3761     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3762   },
3763
3764   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3765   {
3766     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3767     { Bad_Opcode },
3768     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3769   },
3770
3771   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3772   {
3773     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3774     { Bad_Opcode },
3775     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3776   },
3777
3778   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3779   {
3780     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3781     { Bad_Opcode },
3782     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3783   },
3784
3785   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3786   {
3787     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3788     { Bad_Opcode },
3789     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3790   },
3791
3792   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3793   {
3794     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3795   },
3796
3797   /* PREFIX_VEX_0F51 */
3798   {
3799     { "vsqrtps",        { XM, EXx }, 0 },
3800     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
3801     { "vsqrtpd",        { XM, EXx }, 0 },
3802     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
3803   },
3804
3805   /* PREFIX_VEX_0F52 */
3806   {
3807     { "vrsqrtps",       { XM, EXx }, 0 },
3808     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
3809   },
3810
3811   /* PREFIX_VEX_0F53 */
3812   {
3813     { "vrcpps",         { XM, EXx }, 0 },
3814     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3815   },
3816
3817   /* PREFIX_VEX_0F58 */
3818   {
3819     { "vaddps",         { XM, Vex, EXx }, 0 },
3820     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3821     { "vaddpd",         { XM, Vex, EXx }, 0 },
3822     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3823   },
3824
3825   /* PREFIX_VEX_0F59 */
3826   {
3827     { "vmulps",         { XM, Vex, EXx }, 0 },
3828     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3829     { "vmulpd",         { XM, Vex, EXx }, 0 },
3830     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3831   },
3832
3833   /* PREFIX_VEX_0F5A */
3834   {
3835     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
3836     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
3837     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3838     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
3839   },
3840
3841   /* PREFIX_VEX_0F5B */
3842   {
3843     { "vcvtdq2ps",      { XM, EXx }, 0 },
3844     { "vcvttps2dq",     { XM, EXx }, 0 },
3845     { "vcvtps2dq",      { XM, EXx }, 0 },
3846   },
3847
3848   /* PREFIX_VEX_0F5C */
3849   {
3850     { "vsubps",         { XM, Vex, EXx }, 0 },
3851     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3852     { "vsubpd",         { XM, Vex, EXx }, 0 },
3853     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3854   },
3855
3856   /* PREFIX_VEX_0F5D */
3857   {
3858     { "vminps",         { XM, Vex, EXx }, 0 },
3859     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3860     { "vminpd",         { XM, Vex, EXx }, 0 },
3861     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3862   },
3863
3864   /* PREFIX_VEX_0F5E */
3865   {
3866     { "vdivps",         { XM, Vex, EXx }, 0 },
3867     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3868     { "vdivpd",         { XM, Vex, EXx }, 0 },
3869     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3870   },
3871
3872   /* PREFIX_VEX_0F5F */
3873   {
3874     { "vmaxps",         { XM, Vex, EXx }, 0 },
3875     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3876     { "vmaxpd",         { XM, Vex, EXx }, 0 },
3877     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3878   },
3879
3880   /* PREFIX_VEX_0F6F */
3881   {
3882     { Bad_Opcode },
3883     { "vmovdqu",        { XM, EXx }, 0 },
3884     { "vmovdqa",        { XM, EXx }, 0 },
3885   },
3886
3887   /* PREFIX_VEX_0F70 */
3888   {
3889     { Bad_Opcode },
3890     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3891     { "vpshufd",        { XM, EXx, Ib }, 0 },
3892     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3893   },
3894
3895   /* PREFIX_VEX_0F7C */
3896   {
3897     { Bad_Opcode },
3898     { Bad_Opcode },
3899     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3900     { "vhaddps",        { XM, Vex, EXx }, 0 },
3901   },
3902
3903   /* PREFIX_VEX_0F7D */
3904   {
3905     { Bad_Opcode },
3906     { Bad_Opcode },
3907     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3908     { "vhsubps",        { XM, Vex, EXx }, 0 },
3909   },
3910
3911   /* PREFIX_VEX_0F7E */
3912   {
3913     { Bad_Opcode },
3914     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3915     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3916   },
3917
3918   /* PREFIX_VEX_0F7F */
3919   {
3920     { Bad_Opcode },
3921     { "vmovdqu",        { EXxS, XM }, 0 },
3922     { "vmovdqa",        { EXxS, XM }, 0 },
3923   },
3924
3925   /* PREFIX_VEX_0F90_L_0_W_0 */
3926   {
3927     { "kmovw",          { MaskG, MaskE }, 0 },
3928     { Bad_Opcode },
3929     { "kmovb",          { MaskG, MaskBDE }, 0 },
3930   },
3931
3932   /* PREFIX_VEX_0F90_L_0_W_1 */
3933   {
3934     { "kmovq",          { MaskG, MaskE }, 0 },
3935     { Bad_Opcode },
3936     { "kmovd",          { MaskG, MaskBDE }, 0 },
3937   },
3938
3939   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3940   {
3941     { "kmovw",          { Ew, MaskG }, 0 },
3942     { Bad_Opcode },
3943     { "kmovb",          { Eb, MaskG }, 0 },
3944   },
3945
3946   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3947   {
3948     { "kmovq",          { Eq, MaskG }, 0 },
3949     { Bad_Opcode },
3950     { "kmovd",          { Ed, MaskG }, 0 },
3951   },
3952
3953   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3954   {
3955     { "kmovw",          { MaskG, Edq }, 0 },
3956     { Bad_Opcode },
3957     { "kmovb",          { MaskG, Edq }, 0 },
3958     { "kmovd",          { MaskG, Edq }, 0 },
3959   },
3960
3961   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3962   {
3963     { Bad_Opcode },
3964     { Bad_Opcode },
3965     { Bad_Opcode },
3966     { "kmovK",          { MaskG, Edq }, 0 },
3967   },
3968
3969   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3970   {
3971     { "kmovw",          { Gdq, MaskE }, 0 },
3972     { Bad_Opcode },
3973     { "kmovb",          { Gdq, MaskE }, 0 },
3974     { "kmovd",          { Gdq, MaskE }, 0 },
3975   },
3976
3977   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3978   {
3979     { Bad_Opcode },
3980     { Bad_Opcode },
3981     { Bad_Opcode },
3982     { "kmovK",          { Gdq, MaskE }, 0 },
3983   },
3984
3985   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3986   {
3987     { "kortestw", { MaskG, MaskE }, 0 },
3988     { Bad_Opcode },
3989     { "kortestb", { MaskG, MaskE }, 0 },
3990   },
3991
3992   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3993   {
3994     { "kortestq", { MaskG, MaskE }, 0 },
3995     { Bad_Opcode },
3996     { "kortestd", { MaskG, MaskE }, 0 },
3997   },
3998
3999   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4000   {
4001     { "ktestw", { MaskG, MaskE }, 0 },
4002     { Bad_Opcode },
4003     { "ktestb", { MaskG, MaskE }, 0 },
4004   },
4005
4006   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4007   {
4008     { "ktestq", { MaskG, MaskE }, 0 },
4009     { Bad_Opcode },
4010     { "ktestd", { MaskG, MaskE }, 0 },
4011   },
4012
4013   /* PREFIX_VEX_0FC2 */
4014   {
4015     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
4016     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
4017     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
4018     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
4019   },
4020
4021   /* PREFIX_VEX_0FD0 */
4022   {
4023     { Bad_Opcode },
4024     { Bad_Opcode },
4025     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
4026     { "vaddsubps",      { XM, Vex, EXx }, 0 },
4027   },
4028
4029   /* PREFIX_VEX_0FE6 */
4030   {
4031     { Bad_Opcode },
4032     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
4033     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
4034     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
4035   },
4036
4037   /* PREFIX_VEX_0FF0 */
4038   {
4039     { Bad_Opcode },
4040     { Bad_Opcode },
4041     { Bad_Opcode },
4042     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4043   },
4044
4045   /* PREFIX_VEX_0F3849_X86_64 */
4046   {
4047     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4048     { Bad_Opcode },
4049     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4050     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4051   },
4052
4053   /* PREFIX_VEX_0F384B_X86_64 */
4054   {
4055     { Bad_Opcode },
4056     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4057     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4058     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4059   },
4060
4061   /* PREFIX_VEX_0F385C_X86_64 */
4062   {
4063     { Bad_Opcode },
4064     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4065     { Bad_Opcode },
4066   },
4067
4068   /* PREFIX_VEX_0F385E_X86_64 */
4069   {
4070     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4071     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4072     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4073     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4074   },
4075
4076   /* PREFIX_VEX_0F38F5_L_0 */
4077   {
4078     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4079     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4080     { Bad_Opcode },
4081     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4082   },
4083
4084   /* PREFIX_VEX_0F38F6_L_0 */
4085   {
4086     { Bad_Opcode },
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4090   },
4091
4092   /* PREFIX_VEX_0F38F7_L_0 */
4093   {
4094     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4095     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4096     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4097     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4098   },
4099
4100   /* PREFIX_VEX_0F3AF0_L_0 */
4101   {
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4106   },
4107
4108 #include "i386-dis-evex-prefix.h"
4109 };
4110
4111 static const struct dis386 x86_64_table[][2] = {
4112   /* X86_64_06 */
4113   {
4114     { "pushP", { es }, 0 },
4115   },
4116
4117   /* X86_64_07 */
4118   {
4119     { "popP", { es }, 0 },
4120   },
4121
4122   /* X86_64_0E */
4123   {
4124     { "pushP", { cs }, 0 },
4125   },
4126
4127   /* X86_64_16 */
4128   {
4129     { "pushP", { ss }, 0 },
4130   },
4131
4132   /* X86_64_17 */
4133   {
4134     { "popP", { ss }, 0 },
4135   },
4136
4137   /* X86_64_1E */
4138   {
4139     { "pushP", { ds }, 0 },
4140   },
4141
4142   /* X86_64_1F */
4143   {
4144     { "popP", { ds }, 0 },
4145   },
4146
4147   /* X86_64_27 */
4148   {
4149     { "daa", { XX }, 0 },
4150   },
4151
4152   /* X86_64_2F */
4153   {
4154     { "das", { XX }, 0 },
4155   },
4156
4157   /* X86_64_37 */
4158   {
4159     { "aaa", { XX }, 0 },
4160   },
4161
4162   /* X86_64_3F */
4163   {
4164     { "aas", { XX }, 0 },
4165   },
4166
4167   /* X86_64_60 */
4168   {
4169     { "pushaP", { XX }, 0 },
4170   },
4171
4172   /* X86_64_61 */
4173   {
4174     { "popaP", { XX }, 0 },
4175   },
4176
4177   /* X86_64_62 */
4178   {
4179     { MOD_TABLE (MOD_62_32BIT) },
4180     { EVEX_TABLE (EVEX_0F) },
4181   },
4182
4183   /* X86_64_63 */
4184   {
4185     { "arpl", { Ew, Gw }, 0 },
4186     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4187   },
4188
4189   /* X86_64_6D */
4190   {
4191     { "ins{R|}", { Yzr, indirDX }, 0 },
4192     { "ins{G|}", { Yzr, indirDX }, 0 },
4193   },
4194
4195   /* X86_64_6F */
4196   {
4197     { "outs{R|}", { indirDXr, Xz }, 0 },
4198     { "outs{G|}", { indirDXr, Xz }, 0 },
4199   },
4200
4201   /* X86_64_82 */
4202   {
4203     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4204     { REG_TABLE (REG_80) },
4205   },
4206
4207   /* X86_64_9A */
4208   {
4209     { "{l|}call{P|}", { Ap }, 0 },
4210   },
4211
4212   /* X86_64_C2 */
4213   {
4214     { "retP",           { Iw, BND }, 0 },
4215     { "ret@",           { Iw, BND }, 0 },
4216   },
4217
4218   /* X86_64_C3 */
4219   {
4220     { "retP",           { BND }, 0 },
4221     { "ret@",           { BND }, 0 },
4222   },
4223
4224   /* X86_64_C4 */
4225   {
4226     { MOD_TABLE (MOD_C4_32BIT) },
4227     { VEX_C4_TABLE (VEX_0F) },
4228   },
4229
4230   /* X86_64_C5 */
4231   {
4232     { MOD_TABLE (MOD_C5_32BIT) },
4233     { VEX_C5_TABLE (VEX_0F) },
4234   },
4235
4236   /* X86_64_CE */
4237   {
4238     { "into", { XX }, 0 },
4239   },
4240
4241   /* X86_64_D4 */
4242   {
4243     { "aam", { Ib }, 0 },
4244   },
4245
4246   /* X86_64_D5 */
4247   {
4248     { "aad", { Ib }, 0 },
4249   },
4250
4251   /* X86_64_E8 */
4252   {
4253     { "callP",          { Jv, BND }, 0 },
4254     { "call@",          { Jv, BND }, 0 }
4255   },
4256
4257   /* X86_64_E9 */
4258   {
4259     { "jmpP",           { Jv, BND }, 0 },
4260     { "jmp@",           { Jv, BND }, 0 }
4261   },
4262
4263   /* X86_64_EA */
4264   {
4265     { "{l|}jmp{P|}", { Ap }, 0 },
4266   },
4267
4268   /* X86_64_0F01_REG_0 */
4269   {
4270     { "sgdt{Q|Q}", { M }, 0 },
4271     { "sgdt", { M }, 0 },
4272   },
4273
4274   /* X86_64_0F01_REG_1 */
4275   {
4276     { "sidt{Q|Q}", { M }, 0 },
4277     { "sidt", { M }, 0 },
4278   },
4279
4280   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4281   {
4282     { Bad_Opcode },
4283     { "seamret",        { Skip_MODRM }, 0 },
4284   },
4285
4286   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4287   {
4288     { Bad_Opcode },
4289     { "seamops",        { Skip_MODRM }, 0 },
4290   },
4291
4292   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4293   {
4294     { Bad_Opcode },
4295     { "seamcall",       { Skip_MODRM }, 0 },
4296   },
4297
4298   /* X86_64_0F01_REG_2 */
4299   {
4300     { "lgdt{Q|Q}", { M }, 0 },
4301     { "lgdt", { M }, 0 },
4302   },
4303
4304   /* X86_64_0F01_REG_3 */
4305   {
4306     { "lidt{Q|Q}", { M }, 0 },
4307     { "lidt", { M }, 0 },
4308   },
4309
4310   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4311   {
4312     { Bad_Opcode },
4313     { "uiret",  { Skip_MODRM }, 0 },
4314   },
4315
4316   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4317   {
4318     { Bad_Opcode },
4319     { "testui", { Skip_MODRM }, 0 },
4320   },
4321
4322   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4323   {
4324     { Bad_Opcode },
4325     { "clui",   { Skip_MODRM }, 0 },
4326   },
4327
4328   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4329   {
4330     { Bad_Opcode },
4331     { "stui",   { Skip_MODRM }, 0 },
4332   },
4333
4334   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4335   {
4336     { Bad_Opcode },
4337     { "rmpadjust",      { Skip_MODRM }, 0 },
4338   },
4339
4340   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4341   {
4342     { Bad_Opcode },
4343     { "rmpupdate",      { Skip_MODRM }, 0 },
4344   },
4345
4346   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4347   {
4348     { Bad_Opcode },
4349     { "psmash", { Skip_MODRM }, 0 },
4350   },
4351
4352   {
4353     /* X86_64_0F24 */
4354     { "movZ",           { Em, Td }, 0 },
4355   },
4356
4357   {
4358     /* X86_64_0F26 */
4359     { "movZ",           { Td, Em }, 0 },
4360   },
4361
4362   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4363   {
4364     { Bad_Opcode },
4365     { "senduipi",       { Eq }, 0 },
4366   },
4367
4368   /* X86_64_VEX_0F3849 */
4369   {
4370     { Bad_Opcode },
4371     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4372   },
4373
4374   /* X86_64_VEX_0F384B */
4375   {
4376     { Bad_Opcode },
4377     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4378   },
4379
4380   /* X86_64_VEX_0F385C */
4381   {
4382     { Bad_Opcode },
4383     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4384   },
4385
4386   /* X86_64_VEX_0F385E */
4387   {
4388     { Bad_Opcode },
4389     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4390   },
4391 };
4392
4393 static const struct dis386 three_byte_table[][256] = {
4394
4395   /* THREE_BYTE_0F38 */
4396   {
4397     /* 00 */
4398     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4399     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4400     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4401     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4402     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4403     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4404     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4405     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4406     /* 08 */
4407     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4408     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4409     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4410     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     /* 10 */
4416     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4421     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4422     { Bad_Opcode },
4423     { "ptest",  { XM, EXx }, PREFIX_DATA },
4424     /* 18 */
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4430     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4431     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4432     { Bad_Opcode },
4433     /* 20 */
4434     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4435     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4436     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4437     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4438     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4439     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     /* 28 */
4443     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4444     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4445     { MOD_TABLE (MOD_0F382A) },
4446     { "packusdw", { XM, EXx }, PREFIX_DATA },
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     /* 30 */
4452     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4453     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4454     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4455     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4456     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4457     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4458     { Bad_Opcode },
4459     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4460     /* 38 */
4461     { "pminsb", { XM, EXx }, PREFIX_DATA },
4462     { "pminsd", { XM, EXx }, PREFIX_DATA },
4463     { "pminuw", { XM, EXx }, PREFIX_DATA },
4464     { "pminud", { XM, EXx }, PREFIX_DATA },
4465     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4466     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4467     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4468     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4469     /* 40 */
4470     { "pmulld", { XM, EXx }, PREFIX_DATA },
4471     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     /* 48 */
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     /* 50 */
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     /* 58 */
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     /* 60 */
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     /* 68 */
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     /* 70 */
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     /* 78 */
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     /* 80 */
4542     { "invept", { Gm, Mo }, PREFIX_DATA },
4543     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4544     { "invpcid", { Gm, M }, PREFIX_DATA },
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     /* 88 */
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     /* 90 */
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     /* 98 */
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     /* a0 */
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     /* a8 */
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     /* b0 */
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     /* b8 */
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     /* c0 */
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     /* c8 */
4623     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4624     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4625     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4626     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4627     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4628     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4629     { Bad_Opcode },
4630     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4631     /* d0 */
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     /* d8 */
4641     { PREFIX_TABLE (PREFIX_0F38D8) },
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     { "aesimc", { XM, EXx }, PREFIX_DATA },
4645     { PREFIX_TABLE (PREFIX_0F38DC) },
4646     { PREFIX_TABLE (PREFIX_0F38DD) },
4647     { PREFIX_TABLE (PREFIX_0F38DE) },
4648     { PREFIX_TABLE (PREFIX_0F38DF) },
4649     /* e0 */
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     /* e8 */
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     /* f0 */
4668     { PREFIX_TABLE (PREFIX_0F38F0) },
4669     { PREFIX_TABLE (PREFIX_0F38F1) },
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { MOD_TABLE (MOD_0F38F5) },
4674     { PREFIX_TABLE (PREFIX_0F38F6) },
4675     { Bad_Opcode },
4676     /* f8 */
4677     { PREFIX_TABLE (PREFIX_0F38F8) },
4678     { MOD_TABLE (MOD_0F38F9) },
4679     { PREFIX_TABLE (PREFIX_0F38FA) },
4680     { PREFIX_TABLE (PREFIX_0F38FB) },
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685   },
4686   /* THREE_BYTE_0F3A */
4687   {
4688     /* 00 */
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     /* 08 */
4698     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4699     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4700     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4701     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4702     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4703     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4704     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4705     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4706     /* 10 */
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4712     { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4713     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4714     { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4715     /* 18 */
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     /* 20 */
4725     { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4726     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4727     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     /* 28 */
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     /* 30 */
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     /* 38 */
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     /* 40 */
4761     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4762     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4763     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4764     { Bad_Opcode },
4765     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     /* 48 */
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     /* 50 */
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     /* 58 */
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     /* 60 */
4797     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4798     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4799     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4800     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     /* 68 */
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     /* 70 */
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     /* 78 */
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     /* 80 */
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     /* 88 */
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     /* 90 */
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     /* 98 */
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     /* a0 */
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     /* a8 */
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     /* b0 */
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     /* b8 */
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     /* c0 */
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     /* c8 */
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4919     { Bad_Opcode },
4920     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4921     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4922     /* d0 */
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     /* d8 */
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4940     /* e0 */
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     /* e8 */
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     /* f0 */
4959     { PREFIX_TABLE (PREFIX_0F3A0F) },
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     /* f8 */
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976   },
4977 };
4978
4979 static const struct dis386 xop_table[][256] = {
4980   /* XOP_08 */
4981   {
4982     /* 00 */
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     /* 08 */
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     /* 10 */
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     /* 18 */
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     /* 20 */
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     /* 28 */
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     /* 30 */
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     /* 38 */
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     /* 40 */
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     /* 48 */
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     /* 50 */
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     /* 58 */
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     /* 60 */
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     /* 68 */
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     /* 70 */
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     /* 78 */
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     /* 80 */
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5133     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5134     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5135     /* 88 */
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5143     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5144     /* 90 */
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5151     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5152     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5153     /* 98 */
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5161     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5162     /* a0 */
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5166     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5170     { Bad_Opcode },
5171     /* a8 */
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     /* b0 */
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5188     { Bad_Opcode },
5189     /* b8 */
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     /* c0 */
5199     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5200     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5201     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5202     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     /* c8 */
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5213     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5214     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5215     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5216     /* d0 */
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     /* d8 */
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     /* e0 */
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     /* e8 */
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5249     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5250     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5251     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5252     /* f0 */
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     /* f8 */
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270   },
5271   /* XOP_09 */
5272   {
5273     /* 00 */
5274     { Bad_Opcode },
5275     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5276     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     /* 08 */
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     /* 10 */
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { MOD_TABLE (MOD_XOP_09_12) },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     /* 18 */
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     /* 20 */
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     /* 28 */
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     /* 30 */
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     /* 38 */
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     /* 40 */
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     /* 48 */
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     /* 50 */
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     /* 58 */
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     /* 60 */
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     /* 68 */
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     /* 70 */
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     /* 78 */
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     /* 80 */
5418     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5419     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5420     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5421     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     /* 88 */
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     /* 90 */
5436     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5437     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5438     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5439     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5440     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5441     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5442     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5443     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5444     /* 98 */
5445     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5446     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5447     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5448     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     /* a0 */
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     /* a8 */
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     /* b0 */
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     /* b8 */
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     /* c0 */
5490     { Bad_Opcode },
5491     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5492     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5493     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5497     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5498     /* c8 */
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     /* d0 */
5508     { Bad_Opcode },
5509     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5510     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5511     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5515     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5516     /* d8 */
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     /* e0 */
5526     { Bad_Opcode },
5527     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5528     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5529     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     /* e8 */
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     /* f0 */
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     /* f8 */
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561   },
5562   /* XOP_0A */
5563   {
5564     /* 00 */
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     /* 08 */
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     /* 10 */
5583     { "bextrS", { Gdq, Edq, Id }, 0 },
5584     { Bad_Opcode },
5585     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     /* 18 */
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     /* 20 */
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     /* 28 */
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     /* 30 */
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     /* 38 */
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     /* 40 */
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     /* 48 */
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     /* 50 */
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     /* 58 */
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     /* 60 */
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     /* 68 */
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     /* 70 */
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     /* 78 */
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     /* 80 */
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     /* 88 */
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     /* 90 */
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     /* 98 */
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     /* a0 */
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     /* a8 */
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     /* b0 */
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     /* b8 */
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     /* c0 */
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     /* c8 */
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     /* d0 */
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     /* d8 */
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     /* e0 */
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     /* e8 */
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     /* f0 */
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     /* f8 */
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852   },
5853 };
5854
5855 static const struct dis386 vex_table[][256] = {
5856   /* VEX_0F */
5857   {
5858     /* 00 */
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     /* 08 */
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     /* 10 */
5877     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5878     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5879     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5880     { MOD_TABLE (MOD_VEX_0F13) },
5881     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5882     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5883     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5884     { MOD_TABLE (MOD_VEX_0F17) },
5885     /* 18 */
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     /* 20 */
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     /* 28 */
5904     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5905     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5906     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5907     { MOD_TABLE (MOD_VEX_0F2B) },
5908     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5909     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5910     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5911     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5912     /* 30 */
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     /* 38 */
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     /* 40 */
5931     { Bad_Opcode },
5932     { VEX_LEN_TABLE (VEX_LEN_0F41) },
5933     { VEX_LEN_TABLE (VEX_LEN_0F42) },
5934     { Bad_Opcode },
5935     { VEX_LEN_TABLE (VEX_LEN_0F44) },
5936     { VEX_LEN_TABLE (VEX_LEN_0F45) },
5937     { VEX_LEN_TABLE (VEX_LEN_0F46) },
5938     { VEX_LEN_TABLE (VEX_LEN_0F47) },
5939     /* 48 */
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5943     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     /* 50 */
5949     { MOD_TABLE (MOD_VEX_0F50) },
5950     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5951     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5952     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5953     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5954     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5955     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5956     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5957     /* 58 */
5958     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5959     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5960     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5961     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5962     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5963     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5964     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5965     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5966     /* 60 */
5967     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5968     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5969     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5970     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5971     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5972     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5973     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5974     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5975     /* 68 */
5976     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5977     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
5978     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
5979     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
5980     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5981     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5982     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5983     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5984     /* 70 */
5985     { PREFIX_TABLE (PREFIX_VEX_0F70) },
5986     { MOD_TABLE (MOD_VEX_0F71) },
5987     { MOD_TABLE (MOD_VEX_0F72) },
5988     { MOD_TABLE (MOD_VEX_0F73) },
5989     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
5990     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
5991     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
5992     { VEX_LEN_TABLE (VEX_LEN_0F77) },
5993     /* 78 */
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5999     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6000     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6001     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6002     /* 80 */
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     /* 88 */
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     /* 90 */
6021     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6022     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6023     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6024     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     /* 98 */
6030     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6031     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     /* a0 */
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     /* a8 */
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { REG_TABLE (REG_VEX_0FAE) },
6055     { Bad_Opcode },
6056     /* b0 */
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     /* b8 */
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     /* c0 */
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6078     { Bad_Opcode },
6079     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6080     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6081     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6082     { Bad_Opcode },
6083     /* c8 */
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     /* d0 */
6093     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6094     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6095     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6096     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6097     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6098     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6099     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6100     { MOD_TABLE (MOD_VEX_0FD7) },
6101     /* d8 */
6102     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6103     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6104     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6105     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6106     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6107     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6108     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6109     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6110     /* e0 */
6111     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6112     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6113     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6114     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6115     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6116     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6117     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6118     { MOD_TABLE (MOD_VEX_0FE7) },
6119     /* e8 */
6120     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6121     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6122     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6123     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6124     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6125     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6126     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6127     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6128     /* f0 */
6129     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6130     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6131     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6132     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6133     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6134     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6135     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6136     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6137     /* f8 */
6138     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6139     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6140     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6141     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6142     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6143     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6144     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6145     { Bad_Opcode },
6146   },
6147   /* VEX_0F38 */
6148   {
6149     /* 00 */
6150     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6151     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6152     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6153     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6154     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6155     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6156     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6157     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6158     /* 08 */
6159     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6160     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6161     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6162     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6163     { VEX_W_TABLE (VEX_W_0F380C) },
6164     { VEX_W_TABLE (VEX_W_0F380D) },
6165     { VEX_W_TABLE (VEX_W_0F380E) },
6166     { VEX_W_TABLE (VEX_W_0F380F) },
6167     /* 10 */
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { VEX_W_TABLE (VEX_W_0F3813) },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6175     { "vptest",         { XM, EXx }, PREFIX_DATA },
6176     /* 18 */
6177     { VEX_W_TABLE (VEX_W_0F3818) },
6178     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6179     { MOD_TABLE (MOD_VEX_0F381A) },
6180     { Bad_Opcode },
6181     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6182     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6183     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6184     { Bad_Opcode },
6185     /* 20 */
6186     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6187     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6188     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6189     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6190     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6191     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     /* 28 */
6195     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6196     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6197     { MOD_TABLE (MOD_VEX_0F382A) },
6198     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6199     { MOD_TABLE (MOD_VEX_0F382C) },
6200     { MOD_TABLE (MOD_VEX_0F382D) },
6201     { MOD_TABLE (MOD_VEX_0F382E) },
6202     { MOD_TABLE (MOD_VEX_0F382F) },
6203     /* 30 */
6204     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6205     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6206     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6207     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6208     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6209     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6210     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6211     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6212     /* 38 */
6213     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6214     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6215     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6216     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6217     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6218     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6219     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6220     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6221     /* 40 */
6222     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6223     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6228     { VEX_W_TABLE (VEX_W_0F3846) },
6229     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6230     /* 48 */
6231     { Bad_Opcode },
6232     { X86_64_TABLE (X86_64_VEX_0F3849) },
6233     { Bad_Opcode },
6234     { X86_64_TABLE (X86_64_VEX_0F384B) },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     /* 50 */
6240     { VEX_W_TABLE (VEX_W_0F3850) },
6241     { VEX_W_TABLE (VEX_W_0F3851) },
6242     { VEX_W_TABLE (VEX_W_0F3852) },
6243     { VEX_W_TABLE (VEX_W_0F3853) },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     /* 58 */
6249     { VEX_W_TABLE (VEX_W_0F3858) },
6250     { VEX_W_TABLE (VEX_W_0F3859) },
6251     { MOD_TABLE (MOD_VEX_0F385A) },
6252     { Bad_Opcode },
6253     { X86_64_TABLE (X86_64_VEX_0F385C) },
6254     { Bad_Opcode },
6255     { X86_64_TABLE (X86_64_VEX_0F385E) },
6256     { Bad_Opcode },
6257     /* 60 */
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     /* 68 */
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     /* 70 */
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     /* 78 */
6285     { VEX_W_TABLE (VEX_W_0F3878) },
6286     { VEX_W_TABLE (VEX_W_0F3879) },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     /* 80 */
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     /* 88 */
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { MOD_TABLE (MOD_VEX_0F388C) },
6308     { Bad_Opcode },
6309     { MOD_TABLE (MOD_VEX_0F388E) },
6310     { Bad_Opcode },
6311     /* 90 */
6312     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6313     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6314     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6315     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6319     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6320     /* 98 */
6321     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6322     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6323     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6324     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6325     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6326     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6327     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6328     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6329     /* a0 */
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6337     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6338     /* a8 */
6339     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6340     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6341     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6342     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6343     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6344     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6345     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6346     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6347     /* b0 */
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6355     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6356     /* b8 */
6357     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6358     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6359     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6360     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6361     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6362     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6363     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6364     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6365     /* c0 */
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     /* c8 */
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_W_TABLE (VEX_W_0F38CF) },
6383     /* d0 */
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     /* d8 */
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6397     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6398     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6399     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6400     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6401     /* e0 */
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     /* e8 */
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     /* f0 */
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6423     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6424     { Bad_Opcode },
6425     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6426     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6427     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6428     /* f8 */
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437   },
6438   /* VEX_0F3A */
6439   {
6440     /* 00 */
6441     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6442     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6443     { VEX_W_TABLE (VEX_W_0F3A02) },
6444     { Bad_Opcode },
6445     { VEX_W_TABLE (VEX_W_0F3A04) },
6446     { VEX_W_TABLE (VEX_W_0F3A05) },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6448     { Bad_Opcode },
6449     /* 08 */
6450     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6451     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6452     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6453     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6454     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6455     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6456     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6457     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6458     /* 10 */
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6464     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6465     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6467     /* 18 */
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6469     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_W_TABLE (VEX_W_0F3A1D) },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     /* 20 */
6477     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6478     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6479     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     /* 28 */
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     /* 30 */
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6497     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6498     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     /* 38 */
6504     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6505     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     /* 40 */
6513     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6514     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6515     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6516     { Bad_Opcode },
6517     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6518     { Bad_Opcode },
6519     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6520     { Bad_Opcode },
6521     /* 48 */
6522     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6523     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6524     { VEX_W_TABLE (VEX_W_0F3A4A) },
6525     { VEX_W_TABLE (VEX_W_0F3A4B) },
6526     { VEX_W_TABLE (VEX_W_0F3A4C) },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     /* 50 */
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     /* 58 */
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6545     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6546     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6547     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6548     /* 60 */
6549     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6550     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6551     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6552     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     /* 68 */
6558     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6559     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6560     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6561     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6562     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6563     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6564     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6565     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6566     /* 70 */
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     /* 78 */
6576     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6577     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6578     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6579     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6580     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6581     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6582     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6583     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6584     /* 80 */
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     /* 88 */
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     /* 90 */
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     /* 98 */
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     /* a0 */
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     /* a8 */
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     /* b0 */
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     /* b8 */
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     /* c0 */
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     /* c8 */
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_W_TABLE (VEX_W_0F3ACE) },
6673     { VEX_W_TABLE (VEX_W_0F3ACF) },
6674     /* d0 */
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     /* d8 */
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6692     /* e0 */
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     /* e8 */
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     /* f0 */
6711     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     /* f8 */
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728   },
6729 };
6730
6731 #include "i386-dis-evex.h"
6732
6733 static const struct dis386 vex_len_table[][2] = {
6734   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6735   {
6736     { "vmovlpX",        { XM, Vex, EXq }, 0 },
6737   },
6738
6739   /* VEX_LEN_0F12_P_0_M_1 */
6740   {
6741     { "vmovhlps",       { XM, Vex, EXq }, 0 },
6742   },
6743
6744   /* VEX_LEN_0F13_M_0 */
6745   {
6746     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6747   },
6748
6749   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6750   {
6751     { "vmovhpX",        { XM, Vex, EXq }, 0 },
6752   },
6753
6754   /* VEX_LEN_0F16_P_0_M_1 */
6755   {
6756     { "vmovlhps",       { XM, Vex, EXq }, 0 },
6757   },
6758
6759   /* VEX_LEN_0F17_M_0 */
6760   {
6761     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6762   },
6763
6764   /* VEX_LEN_0F41 */
6765   {
6766     { Bad_Opcode },
6767     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6768   },
6769
6770   /* VEX_LEN_0F42 */
6771   {
6772     { Bad_Opcode },
6773     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6774   },
6775
6776   /* VEX_LEN_0F44 */
6777   {
6778     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6779   },
6780
6781   /* VEX_LEN_0F45 */
6782   {
6783     { Bad_Opcode },
6784     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6785   },
6786
6787   /* VEX_LEN_0F46 */
6788   {
6789     { Bad_Opcode },
6790     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6791   },
6792
6793   /* VEX_LEN_0F47 */
6794   {
6795     { Bad_Opcode },
6796     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6797   },
6798
6799   /* VEX_LEN_0F4A */
6800   {
6801     { Bad_Opcode },
6802     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6803   },
6804
6805   /* VEX_LEN_0F4B */
6806   {
6807     { Bad_Opcode },
6808     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6809   },
6810
6811   /* VEX_LEN_0F6E */
6812   {
6813     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6814   },
6815
6816   /* VEX_LEN_0F77 */
6817   {
6818     { "vzeroupper",     { XX }, 0 },
6819     { "vzeroall",       { XX }, 0 },
6820   },
6821
6822   /* VEX_LEN_0F7E_P_1 */
6823   {
6824     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
6825   },
6826
6827   /* VEX_LEN_0F7E_P_2 */
6828   {
6829     { "vmovK",          { Edq, XMScalar }, 0 },
6830   },
6831
6832   /* VEX_LEN_0F90 */
6833   {
6834     { VEX_W_TABLE (VEX_W_0F90_L_0) },
6835   },
6836
6837   /* VEX_LEN_0F91 */
6838   {
6839     { MOD_TABLE (MOD_VEX_0F91_L_0) },
6840   },
6841
6842   /* VEX_LEN_0F92 */
6843   {
6844     { MOD_TABLE (MOD_VEX_0F92_L_0) },
6845   },
6846
6847   /* VEX_LEN_0F93 */
6848   {
6849     { MOD_TABLE (MOD_VEX_0F93_L_0) },
6850   },
6851
6852   /* VEX_LEN_0F98 */
6853   {
6854     { MOD_TABLE (MOD_VEX_0F98_L_0) },
6855   },
6856
6857   /* VEX_LEN_0F99 */
6858   {
6859     { MOD_TABLE (MOD_VEX_0F99_L_0) },
6860   },
6861
6862   /* VEX_LEN_0FAE_R_2_M_0 */
6863   {
6864     { "vldmxcsr",       { Md }, 0 },
6865   },
6866
6867   /* VEX_LEN_0FAE_R_3_M_0 */
6868   {
6869     { "vstmxcsr",       { Md }, 0 },
6870   },
6871
6872   /* VEX_LEN_0FC4 */
6873   {
6874     { "vpinsrw",        { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6875   },
6876
6877   /* VEX_LEN_0FC5 */
6878   {
6879     { "vpextrw",        { Gdq, XS, Ib }, PREFIX_DATA },
6880   },
6881
6882   /* VEX_LEN_0FD6 */
6883   {
6884     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6885   },
6886
6887   /* VEX_LEN_0FF7 */
6888   {
6889     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6890   },
6891
6892   /* VEX_LEN_0F3816 */
6893   {
6894     { Bad_Opcode },
6895     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6896   },
6897
6898   /* VEX_LEN_0F3819 */
6899   {
6900     { Bad_Opcode },
6901     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6902   },
6903
6904   /* VEX_LEN_0F381A_M_0 */
6905   {
6906     { Bad_Opcode },
6907     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6908   },
6909
6910   /* VEX_LEN_0F3836 */
6911   {
6912     { Bad_Opcode },
6913     { VEX_W_TABLE (VEX_W_0F3836) },
6914   },
6915
6916   /* VEX_LEN_0F3841 */
6917   {
6918     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6919   },
6920
6921    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6922   {
6923     { "ldtilecfg", { M }, 0 },
6924   },
6925
6926   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6927   {
6928     { "tilerelease", { Skip_MODRM }, 0 },
6929   },
6930
6931   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6932   {
6933     { "sttilecfg", { M }, 0 },
6934   },
6935
6936   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6937   {
6938     { "tilezero", { TMM, Skip_MODRM }, 0 },
6939   },
6940
6941   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6942   {
6943     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6944   },
6945   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6946   {
6947     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6948   },
6949
6950   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6951   {
6952     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6953   },
6954
6955   /* VEX_LEN_0F385A_M_0 */
6956   {
6957     { Bad_Opcode },
6958     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6959   },
6960
6961   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6962   {
6963     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6964   },
6965
6966   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6967   {
6968     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6969   },
6970
6971   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6972   {
6973     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6974   },
6975
6976   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6977   {
6978     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6979   },
6980
6981   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6982   {
6983     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6984   },
6985
6986   /* VEX_LEN_0F38DB */
6987   {
6988     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
6989   },
6990
6991   /* VEX_LEN_0F38F2 */
6992   {
6993     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6994   },
6995
6996   /* VEX_LEN_0F38F3 */
6997   {
6998     { REG_TABLE(REG_VEX_0F38F3_L_0) },
6999   },
7000
7001   /* VEX_LEN_0F38F5 */
7002   {
7003     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7004   },
7005
7006   /* VEX_LEN_0F38F6 */
7007   {
7008     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7009   },
7010
7011   /* VEX_LEN_0F38F7 */
7012   {
7013     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7014   },
7015
7016   /* VEX_LEN_0F3A00 */
7017   {
7018     { Bad_Opcode },
7019     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7020   },
7021
7022   /* VEX_LEN_0F3A01 */
7023   {
7024     { Bad_Opcode },
7025     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7026   },
7027
7028   /* VEX_LEN_0F3A06 */
7029   {
7030     { Bad_Opcode },
7031     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7032   },
7033
7034   /* VEX_LEN_0F3A14 */
7035   {
7036     { "vpextrb",        { Edqb, XM, Ib }, PREFIX_DATA },
7037   },
7038
7039   /* VEX_LEN_0F3A15 */
7040   {
7041     { "vpextrw",        { Edqw, XM, Ib }, PREFIX_DATA },
7042   },
7043
7044   /* VEX_LEN_0F3A16  */
7045   {
7046     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
7047   },
7048
7049   /* VEX_LEN_0F3A17 */
7050   {
7051     { "vextractps",     { Edqd, XM, Ib }, PREFIX_DATA },
7052   },
7053
7054   /* VEX_LEN_0F3A18 */
7055   {
7056     { Bad_Opcode },
7057     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7058   },
7059
7060   /* VEX_LEN_0F3A19 */
7061   {
7062     { Bad_Opcode },
7063     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7064   },
7065
7066   /* VEX_LEN_0F3A20 */
7067   {
7068     { "vpinsrb",        { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7069   },
7070
7071   /* VEX_LEN_0F3A21 */
7072   {
7073     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
7074   },
7075
7076   /* VEX_LEN_0F3A22 */
7077   {
7078     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
7079   },
7080
7081   /* VEX_LEN_0F3A30 */
7082   {
7083     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7084   },
7085
7086   /* VEX_LEN_0F3A31 */
7087   {
7088     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7089   },
7090
7091   /* VEX_LEN_0F3A32 */
7092   {
7093     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7094   },
7095
7096   /* VEX_LEN_0F3A33 */
7097   {
7098     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7099   },
7100
7101   /* VEX_LEN_0F3A38 */
7102   {
7103     { Bad_Opcode },
7104     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7105   },
7106
7107   /* VEX_LEN_0F3A39 */
7108   {
7109     { Bad_Opcode },
7110     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7111   },
7112
7113   /* VEX_LEN_0F3A41 */
7114   {
7115     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7116   },
7117
7118   /* VEX_LEN_0F3A46 */
7119   {
7120     { Bad_Opcode },
7121     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7122   },
7123
7124   /* VEX_LEN_0F3A60 */
7125   {
7126     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7127   },
7128
7129   /* VEX_LEN_0F3A61 */
7130   {
7131     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7132   },
7133
7134   /* VEX_LEN_0F3A62 */
7135   {
7136     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7137   },
7138
7139   /* VEX_LEN_0F3A63 */
7140   {
7141     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7142   },
7143
7144   /* VEX_LEN_0F3ADF */
7145   {
7146     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7147   },
7148
7149   /* VEX_LEN_0F3AF0 */
7150   {
7151     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7152   },
7153
7154   /* VEX_LEN_0FXOP_08_85 */
7155   {
7156     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7157   },
7158
7159   /* VEX_LEN_0FXOP_08_86 */
7160   {
7161     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7162   },
7163
7164   /* VEX_LEN_0FXOP_08_87 */
7165   {
7166     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7167   },
7168
7169   /* VEX_LEN_0FXOP_08_8E */
7170   {
7171     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7172   },
7173
7174   /* VEX_LEN_0FXOP_08_8F */
7175   {
7176     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7177   },
7178
7179   /* VEX_LEN_0FXOP_08_95 */
7180   {
7181     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7182   },
7183
7184   /* VEX_LEN_0FXOP_08_96 */
7185   {
7186     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7187   },
7188
7189   /* VEX_LEN_0FXOP_08_97 */
7190   {
7191     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7192   },
7193
7194   /* VEX_LEN_0FXOP_08_9E */
7195   {
7196     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7197   },
7198
7199   /* VEX_LEN_0FXOP_08_9F */
7200   {
7201     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7202   },
7203
7204   /* VEX_LEN_0FXOP_08_A3 */
7205   {
7206     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7207   },
7208
7209   /* VEX_LEN_0FXOP_08_A6 */
7210   {
7211     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7212   },
7213
7214   /* VEX_LEN_0FXOP_08_B6 */
7215   {
7216     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7217   },
7218
7219   /* VEX_LEN_0FXOP_08_C0 */
7220   {
7221     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7222   },
7223
7224   /* VEX_LEN_0FXOP_08_C1 */
7225   {
7226     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7227   },
7228
7229   /* VEX_LEN_0FXOP_08_C2 */
7230   {
7231     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7232   },
7233
7234   /* VEX_LEN_0FXOP_08_C3 */
7235   {
7236     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7237   },
7238
7239   /* VEX_LEN_0FXOP_08_CC */
7240   {
7241     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7242   },
7243
7244   /* VEX_LEN_0FXOP_08_CD */
7245   {
7246     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7247   },
7248
7249   /* VEX_LEN_0FXOP_08_CE */
7250   {
7251     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7252   },
7253
7254   /* VEX_LEN_0FXOP_08_CF */
7255   {
7256     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7257   },
7258
7259   /* VEX_LEN_0FXOP_08_EC */
7260   {
7261     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7262   },
7263
7264   /* VEX_LEN_0FXOP_08_ED */
7265   {
7266     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7267   },
7268
7269   /* VEX_LEN_0FXOP_08_EE */
7270   {
7271     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7272   },
7273
7274   /* VEX_LEN_0FXOP_08_EF */
7275   {
7276     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7277   },
7278
7279   /* VEX_LEN_0FXOP_09_01 */
7280   {
7281     { REG_TABLE (REG_XOP_09_01_L_0) },
7282   },
7283
7284   /* VEX_LEN_0FXOP_09_02 */
7285   {
7286     { REG_TABLE (REG_XOP_09_02_L_0) },
7287   },
7288
7289   /* VEX_LEN_0FXOP_09_12_M_1 */
7290   {
7291     { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7292   },
7293
7294   /* VEX_LEN_0FXOP_09_82_W_0 */
7295   {
7296     { "vfrczss",        { XM, EXd }, 0 },
7297   },
7298
7299   /* VEX_LEN_0FXOP_09_83_W_0 */
7300   {
7301     { "vfrczsd",        { XM, EXq }, 0 },
7302   },
7303
7304   /* VEX_LEN_0FXOP_09_90 */
7305   {
7306     { "vprotb",         { XM, EXx, VexW }, 0 },
7307   },
7308
7309   /* VEX_LEN_0FXOP_09_91 */
7310   {
7311     { "vprotw",         { XM, EXx, VexW }, 0 },
7312   },
7313
7314   /* VEX_LEN_0FXOP_09_92 */
7315   {
7316     { "vprotd",         { XM, EXx, VexW }, 0 },
7317   },
7318
7319   /* VEX_LEN_0FXOP_09_93 */
7320   {
7321     { "vprotq",         { XM, EXx, VexW }, 0 },
7322   },
7323
7324   /* VEX_LEN_0FXOP_09_94 */
7325   {
7326     { "vpshlb",         { XM, EXx, VexW }, 0 },
7327   },
7328
7329   /* VEX_LEN_0FXOP_09_95 */
7330   {
7331     { "vpshlw",         { XM, EXx, VexW }, 0 },
7332   },
7333
7334   /* VEX_LEN_0FXOP_09_96 */
7335   {
7336     { "vpshld",         { XM, EXx, VexW }, 0 },
7337   },
7338
7339   /* VEX_LEN_0FXOP_09_97 */
7340   {
7341     { "vpshlq",         { XM, EXx, VexW }, 0 },
7342   },
7343
7344   /* VEX_LEN_0FXOP_09_98 */
7345   {
7346     { "vpshab",         { XM, EXx, VexW }, 0 },
7347   },
7348
7349   /* VEX_LEN_0FXOP_09_99 */
7350   {
7351     { "vpshaw",         { XM, EXx, VexW }, 0 },
7352   },
7353
7354   /* VEX_LEN_0FXOP_09_9A */
7355   {
7356     { "vpshad",         { XM, EXx, VexW }, 0 },
7357   },
7358
7359   /* VEX_LEN_0FXOP_09_9B */
7360   {
7361     { "vpshaq",         { XM, EXx, VexW }, 0 },
7362   },
7363
7364   /* VEX_LEN_0FXOP_09_C1 */
7365   {
7366     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7367   },
7368
7369   /* VEX_LEN_0FXOP_09_C2 */
7370   {
7371     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7372   },
7373
7374   /* VEX_LEN_0FXOP_09_C3 */
7375   {
7376     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7377   },
7378
7379   /* VEX_LEN_0FXOP_09_C6 */
7380   {
7381     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7382   },
7383
7384   /* VEX_LEN_0FXOP_09_C7 */
7385   {
7386     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7387   },
7388
7389   /* VEX_LEN_0FXOP_09_CB */
7390   {
7391     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7392   },
7393
7394   /* VEX_LEN_0FXOP_09_D1 */
7395   {
7396     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7397   },
7398
7399   /* VEX_LEN_0FXOP_09_D2 */
7400   {
7401     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7402   },
7403
7404   /* VEX_LEN_0FXOP_09_D3 */
7405   {
7406     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7407   },
7408
7409   /* VEX_LEN_0FXOP_09_D6 */
7410   {
7411     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7412   },
7413
7414   /* VEX_LEN_0FXOP_09_D7 */
7415   {
7416     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7417   },
7418
7419   /* VEX_LEN_0FXOP_09_DB */
7420   {
7421     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7422   },
7423
7424   /* VEX_LEN_0FXOP_09_E1 */
7425   {
7426     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7427   },
7428
7429   /* VEX_LEN_0FXOP_09_E2 */
7430   {
7431     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7432   },
7433
7434   /* VEX_LEN_0FXOP_09_E3 */
7435   {
7436     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7437   },
7438
7439   /* VEX_LEN_0FXOP_0A_12 */
7440   {
7441     { REG_TABLE (REG_XOP_0A_12_L_0) },
7442   },
7443 };
7444
7445 #include "i386-dis-evex-len.h"
7446
7447 static const struct dis386 vex_w_table[][2] = {
7448   {
7449     /* VEX_W_0F41_L_1_M_1 */
7450     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7451     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7452   },
7453   {
7454     /* VEX_W_0F42_L_1_M_1 */
7455     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7456     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7457   },
7458   {
7459     /* VEX_W_0F44_L_0_M_1 */
7460     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7461     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7462   },
7463   {
7464     /* VEX_W_0F45_L_1_M_1 */
7465     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7466     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7467   },
7468   {
7469     /* VEX_W_0F46_L_1_M_1 */
7470     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7471     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7472   },
7473   {
7474     /* VEX_W_0F47_L_1_M_1 */
7475     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7476     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7477   },
7478   {
7479     /* VEX_W_0F4A_L_1_M_1 */
7480     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7481     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7482   },
7483   {
7484     /* VEX_W_0F4B_L_1_M_1 */
7485     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7486     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7487   },
7488   {
7489     /* VEX_W_0F90_L_0 */
7490     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7491     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7492   },
7493   {
7494     /* VEX_W_0F91_L_0_M_0 */
7495     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7496     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7497   },
7498   {
7499     /* VEX_W_0F92_L_0_M_1 */
7500     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7501     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7502   },
7503   {
7504     /* VEX_W_0F93_L_0_M_1 */
7505     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7506     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7507   },
7508   {
7509     /* VEX_W_0F98_L_0_M_1 */
7510     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7511     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7512   },
7513   {
7514     /* VEX_W_0F99_L_0_M_1 */
7515     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7516     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7517   },
7518   {
7519     /* VEX_W_0F380C  */
7520     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7521   },
7522   {
7523     /* VEX_W_0F380D  */
7524     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7525   },
7526   {
7527     /* VEX_W_0F380E  */
7528     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7529   },
7530   {
7531     /* VEX_W_0F380F  */
7532     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7533   },
7534   {
7535     /* VEX_W_0F3813 */
7536     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7537   },
7538   {
7539     /* VEX_W_0F3816_L_1  */
7540     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7541   },
7542   {
7543     /* VEX_W_0F3818 */
7544     { "vbroadcastss",   { XM, EXxmm_md }, PREFIX_DATA },
7545   },
7546   {
7547     /* VEX_W_0F3819_L_1 */
7548     { "vbroadcastsd",   { XM, EXxmm_mq }, PREFIX_DATA },
7549   },
7550   {
7551     /* VEX_W_0F381A_M_0_L_1 */
7552     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7553   },
7554   {
7555     /* VEX_W_0F382C_M_0 */
7556     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7557   },
7558   {
7559     /* VEX_W_0F382D_M_0 */
7560     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7561   },
7562   {
7563     /* VEX_W_0F382E_M_0 */
7564     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7565   },
7566   {
7567     /* VEX_W_0F382F_M_0 */
7568     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7569   },
7570   {
7571     /* VEX_W_0F3836  */
7572     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7573   },
7574   {
7575     /* VEX_W_0F3846 */
7576     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7577   },
7578   {
7579     /* VEX_W_0F3849_X86_64_P_0 */
7580     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7581   },
7582   {
7583     /* VEX_W_0F3849_X86_64_P_2 */
7584     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7585   },
7586   {
7587     /* VEX_W_0F3849_X86_64_P_3 */
7588     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7589   },
7590   {
7591     /* VEX_W_0F384B_X86_64_P_1 */
7592     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7593   },
7594   {
7595     /* VEX_W_0F384B_X86_64_P_2 */
7596     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7597   },
7598   {
7599     /* VEX_W_0F384B_X86_64_P_3 */
7600     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7601   },
7602   {
7603     /* VEX_W_0F3850 */
7604     { "%XV vpdpbusd",   { XM, Vex, EXx }, 0 },
7605   },
7606   {
7607     /* VEX_W_0F3851 */
7608     { "%XV vpdpbusds",  { XM, Vex, EXx }, 0 },
7609   },
7610   {
7611     /* VEX_W_0F3852 */
7612     { "%XV vpdpwssd",   { XM, Vex, EXx }, 0 },
7613   },
7614   {
7615     /* VEX_W_0F3853 */
7616     { "%XV vpdpwssds",  { XM, Vex, EXx }, 0 },
7617   },
7618   {
7619     /* VEX_W_0F3858 */
7620     { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7621   },
7622   {
7623     /* VEX_W_0F3859 */
7624     { "vpbroadcastq",   { XM, EXxmm_mq }, PREFIX_DATA },
7625   },
7626   {
7627     /* VEX_W_0F385A_M_0_L_0 */
7628     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7629   },
7630   {
7631     /* VEX_W_0F385C_X86_64_P_1 */
7632     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7633   },
7634   {
7635     /* VEX_W_0F385E_X86_64_P_0 */
7636     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7637   },
7638   {
7639     /* VEX_W_0F385E_X86_64_P_1 */
7640     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7641   },
7642   {
7643     /* VEX_W_0F385E_X86_64_P_2 */
7644     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7645   },
7646   {
7647     /* VEX_W_0F385E_X86_64_P_3 */
7648     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7649   },
7650   {
7651     /* VEX_W_0F3878 */
7652     { "vpbroadcastb",   { XM, EXxmm_mb }, PREFIX_DATA },
7653   },
7654   {
7655     /* VEX_W_0F3879 */
7656     { "vpbroadcastw",   { XM, EXxmm_mw }, PREFIX_DATA },
7657   },
7658   {
7659     /* VEX_W_0F38CF */
7660     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7661   },
7662   {
7663     /* VEX_W_0F3A00_L_1 */
7664     { Bad_Opcode },
7665     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7666   },
7667   {
7668     /* VEX_W_0F3A01_L_1 */
7669     { Bad_Opcode },
7670     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7671   },
7672   {
7673     /* VEX_W_0F3A02 */
7674     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7675   },
7676   {
7677     /* VEX_W_0F3A04 */
7678     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7679   },
7680   {
7681     /* VEX_W_0F3A05 */
7682     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7683   },
7684   {
7685     /* VEX_W_0F3A06_L_1 */
7686     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7687   },
7688   {
7689     /* VEX_W_0F3A18_L_1 */
7690     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7691   },
7692   {
7693     /* VEX_W_0F3A19_L_1 */
7694     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7695   },
7696   {
7697     /* VEX_W_0F3A1D */
7698     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7699   },
7700   {
7701     /* VEX_W_0F3A38_L_1 */
7702     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7703   },
7704   {
7705     /* VEX_W_0F3A39_L_1 */
7706     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7707   },
7708   {
7709     /* VEX_W_0F3A46_L_1 */
7710     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7711   },
7712   {
7713     /* VEX_W_0F3A4A */
7714     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7715   },
7716   {
7717     /* VEX_W_0F3A4B */
7718     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7719   },
7720   {
7721     /* VEX_W_0F3A4C */
7722     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7723   },
7724   {
7725     /* VEX_W_0F3ACE */
7726     { Bad_Opcode },
7727     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7728   },
7729   {
7730     /* VEX_W_0F3ACF */
7731     { Bad_Opcode },
7732     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7733   },
7734   /* VEX_W_0FXOP_08_85_L_0 */
7735   {
7736     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7737   },
7738   /* VEX_W_0FXOP_08_86_L_0 */
7739   {
7740     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7741   },
7742   /* VEX_W_0FXOP_08_87_L_0 */
7743   {
7744     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7745   },
7746   /* VEX_W_0FXOP_08_8E_L_0 */
7747   {
7748     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7749   },
7750   /* VEX_W_0FXOP_08_8F_L_0 */
7751   {
7752     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7753   },
7754   /* VEX_W_0FXOP_08_95_L_0 */
7755   {
7756     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7757   },
7758   /* VEX_W_0FXOP_08_96_L_0 */
7759   {
7760     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7761   },
7762   /* VEX_W_0FXOP_08_97_L_0 */
7763   {
7764     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7765   },
7766   /* VEX_W_0FXOP_08_9E_L_0 */
7767   {
7768     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7769   },
7770   /* VEX_W_0FXOP_08_9F_L_0 */
7771   {
7772     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7773   },
7774   /* VEX_W_0FXOP_08_A6_L_0 */
7775   {
7776     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7777   },
7778   /* VEX_W_0FXOP_08_B6_L_0 */
7779   {
7780     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7781   },
7782   /* VEX_W_0FXOP_08_C0_L_0 */
7783   {
7784     { "vprotb",         { XM, EXx, Ib }, 0 },
7785   },
7786   /* VEX_W_0FXOP_08_C1_L_0 */
7787   {
7788     { "vprotw",         { XM, EXx, Ib }, 0 },
7789   },
7790   /* VEX_W_0FXOP_08_C2_L_0 */
7791   {
7792     { "vprotd",         { XM, EXx, Ib }, 0 },
7793   },
7794   /* VEX_W_0FXOP_08_C3_L_0 */
7795   {
7796     { "vprotq",         { XM, EXx, Ib }, 0 },
7797   },
7798   /* VEX_W_0FXOP_08_CC_L_0 */
7799   {
7800      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7801   },
7802   /* VEX_W_0FXOP_08_CD_L_0 */
7803   {
7804      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7805   },
7806   /* VEX_W_0FXOP_08_CE_L_0 */
7807   {
7808      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7809   },
7810   /* VEX_W_0FXOP_08_CF_L_0 */
7811   {
7812      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7813   },
7814   /* VEX_W_0FXOP_08_EC_L_0 */
7815   {
7816      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7817   },
7818   /* VEX_W_0FXOP_08_ED_L_0 */
7819   {
7820      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7821   },
7822   /* VEX_W_0FXOP_08_EE_L_0 */
7823   {
7824      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7825   },
7826   /* VEX_W_0FXOP_08_EF_L_0 */
7827   {
7828      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7829   },
7830   /* VEX_W_0FXOP_09_80 */
7831   {
7832     { "vfrczps",        { XM, EXx }, 0 },
7833   },
7834   /* VEX_W_0FXOP_09_81 */
7835   {
7836     { "vfrczpd",        { XM, EXx }, 0 },
7837   },
7838   /* VEX_W_0FXOP_09_82 */
7839   {
7840     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7841   },
7842   /* VEX_W_0FXOP_09_83 */
7843   {
7844     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7845   },
7846   /* VEX_W_0FXOP_09_C1_L_0 */
7847   {
7848     { "vphaddbw",       { XM, EXxmm }, 0 },
7849   },
7850   /* VEX_W_0FXOP_09_C2_L_0 */
7851   {
7852     { "vphaddbd",       { XM, EXxmm }, 0 },
7853   },
7854   /* VEX_W_0FXOP_09_C3_L_0 */
7855   {
7856     { "vphaddbq",       { XM, EXxmm }, 0 },
7857   },
7858   /* VEX_W_0FXOP_09_C6_L_0 */
7859   {
7860     { "vphaddwd",       { XM, EXxmm }, 0 },
7861   },
7862   /* VEX_W_0FXOP_09_C7_L_0 */
7863   {
7864     { "vphaddwq",       { XM, EXxmm }, 0 },
7865   },
7866   /* VEX_W_0FXOP_09_CB_L_0 */
7867   {
7868     { "vphadddq",       { XM, EXxmm }, 0 },
7869   },
7870   /* VEX_W_0FXOP_09_D1_L_0 */
7871   {
7872     { "vphaddubw",      { XM, EXxmm }, 0 },
7873   },
7874   /* VEX_W_0FXOP_09_D2_L_0 */
7875   {
7876     { "vphaddubd",      { XM, EXxmm }, 0 },
7877   },
7878   /* VEX_W_0FXOP_09_D3_L_0 */
7879   {
7880     { "vphaddubq",      { XM, EXxmm }, 0 },
7881   },
7882   /* VEX_W_0FXOP_09_D6_L_0 */
7883   {
7884     { "vphadduwd",      { XM, EXxmm }, 0 },
7885   },
7886   /* VEX_W_0FXOP_09_D7_L_0 */
7887   {
7888     { "vphadduwq",      { XM, EXxmm }, 0 },
7889   },
7890   /* VEX_W_0FXOP_09_DB_L_0 */
7891   {
7892     { "vphaddudq",      { XM, EXxmm }, 0 },
7893   },
7894   /* VEX_W_0FXOP_09_E1_L_0 */
7895   {
7896     { "vphsubbw",       { XM, EXxmm }, 0 },
7897   },
7898   /* VEX_W_0FXOP_09_E2_L_0 */
7899   {
7900     { "vphsubwd",       { XM, EXxmm }, 0 },
7901   },
7902   /* VEX_W_0FXOP_09_E3_L_0 */
7903   {
7904     { "vphsubdq",       { XM, EXxmm }, 0 },
7905   },
7906
7907 #include "i386-dis-evex-w.h"
7908 };
7909
7910 static const struct dis386 mod_table[][2] = {
7911   {
7912     /* MOD_62_32BIT */
7913     { "bound{S|}",      { Gv, Ma }, 0 },
7914     { EVEX_TABLE (EVEX_0F) },
7915   },
7916   {
7917     /* MOD_8D */
7918     { "leaS",           { Gv, M }, 0 },
7919   },
7920   {
7921     /* MOD_C4_32BIT */
7922     { "lesS",           { Gv, Mp }, 0 },
7923     { VEX_C4_TABLE (VEX_0F) },
7924   },
7925   {
7926     /* MOD_C5_32BIT */
7927     { "ldsS",           { Gv, Mp }, 0 },
7928     { VEX_C5_TABLE (VEX_0F) },
7929   },
7930   {
7931     /* MOD_C6_REG_7 */
7932     { Bad_Opcode },
7933     { RM_TABLE (RM_C6_REG_7) },
7934   },
7935   {
7936     /* MOD_C7_REG_7 */
7937     { Bad_Opcode },
7938     { RM_TABLE (RM_C7_REG_7) },
7939   },
7940   {
7941     /* MOD_FF_REG_3 */
7942     { "{l|}call^", { indirEp }, 0 },
7943   },
7944   {
7945     /* MOD_FF_REG_5 */
7946     { "{l|}jmp^", { indirEp }, 0 },
7947   },
7948   {
7949     /* MOD_0F01_REG_0 */
7950     { X86_64_TABLE (X86_64_0F01_REG_0) },
7951     { RM_TABLE (RM_0F01_REG_0) },
7952   },
7953   {
7954     /* MOD_0F01_REG_1 */
7955     { X86_64_TABLE (X86_64_0F01_REG_1) },
7956     { RM_TABLE (RM_0F01_REG_1) },
7957   },
7958   {
7959     /* MOD_0F01_REG_2 */
7960     { X86_64_TABLE (X86_64_0F01_REG_2) },
7961     { RM_TABLE (RM_0F01_REG_2) },
7962   },
7963   {
7964     /* MOD_0F01_REG_3 */
7965     { X86_64_TABLE (X86_64_0F01_REG_3) },
7966     { RM_TABLE (RM_0F01_REG_3) },
7967   },
7968   {
7969     /* MOD_0F01_REG_5 */
7970     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7971     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7972   },
7973   {
7974     /* MOD_0F01_REG_7 */
7975     { "invlpg",         { Mb }, 0 },
7976     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7977   },
7978   {
7979     /* MOD_0F12_PREFIX_0 */
7980     { "movlpX",         { XM, EXq }, 0 },
7981     { "movhlps",        { XM, EXq }, 0 },
7982   },
7983   {
7984     /* MOD_0F12_PREFIX_2 */
7985     { "movlpX", { XM, EXq }, 0 },
7986   },
7987   {
7988     /* MOD_0F13 */
7989     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
7990   },
7991   {
7992     /* MOD_0F16_PREFIX_0 */
7993     { "movhpX",         { XM, EXq }, 0 },
7994     { "movlhps",        { XM, EXq }, 0 },
7995   },
7996   {
7997     /* MOD_0F16_PREFIX_2 */
7998     { "movhpX", { XM, EXq }, 0 },
7999   },
8000   {
8001     /* MOD_0F17 */
8002     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8003   },
8004   {
8005     /* MOD_0F18_REG_0 */
8006     { "prefetchnta",    { Mb }, 0 },
8007     { "nopQ",           { Ev }, 0 },
8008   },
8009   {
8010     /* MOD_0F18_REG_1 */
8011     { "prefetcht0",     { Mb }, 0 },
8012     { "nopQ",           { Ev }, 0 },
8013   },
8014   {
8015     /* MOD_0F18_REG_2 */
8016     { "prefetcht1",     { Mb }, 0 },
8017     { "nopQ",           { Ev }, 0 },
8018   },
8019   {
8020     /* MOD_0F18_REG_3 */
8021     { "prefetcht2",     { Mb }, 0 },
8022     { "nopQ",           { Ev }, 0 },
8023   },
8024   {
8025     /* MOD_0F1A_PREFIX_0 */
8026     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8027     { "nopQ",           { Ev }, 0 },
8028   },
8029   {
8030     /* MOD_0F1B_PREFIX_0 */
8031     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8032     { "nopQ",           { Ev }, 0 },
8033   },
8034   {
8035     /* MOD_0F1B_PREFIX_1 */
8036     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8037     { "nopQ",           { Ev }, PREFIX_IGNORED },
8038   },
8039   {
8040     /* MOD_0F1C_PREFIX_0 */
8041     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8042     { "nopQ",           { Ev }, 0 },
8043   },
8044   {
8045     /* MOD_0F1E_PREFIX_1 */
8046     { "nopQ",           { Ev }, PREFIX_IGNORED },
8047     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8048   },
8049   {
8050     /* MOD_0F2B_PREFIX_0 */
8051     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8052   },
8053   {
8054     /* MOD_0F2B_PREFIX_1 */
8055     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8056   },
8057   {
8058     /* MOD_0F2B_PREFIX_2 */
8059     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8060   },
8061   {
8062     /* MOD_0F2B_PREFIX_3 */
8063     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8064   },
8065   {
8066     /* MOD_0F50 */
8067     { Bad_Opcode },
8068     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8069   },
8070   {
8071     /* MOD_0F71 */
8072     { Bad_Opcode },
8073     { REG_TABLE (REG_0F71_MOD_0) },
8074   },
8075   {
8076     /* MOD_0F72 */
8077     { Bad_Opcode },
8078     { REG_TABLE (REG_0F72_MOD_0) },
8079   },
8080   {
8081     /* MOD_0F73 */
8082     { Bad_Opcode },
8083     { REG_TABLE (REG_0F73_MOD_0) },
8084   },
8085   {
8086     /* MOD_0FAE_REG_0 */
8087     { "fxsave",         { FXSAVE }, 0 },
8088     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8089   },
8090   {
8091     /* MOD_0FAE_REG_1 */
8092     { "fxrstor",        { FXSAVE }, 0 },
8093     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8094   },
8095   {
8096     /* MOD_0FAE_REG_2 */
8097     { "ldmxcsr",        { Md }, 0 },
8098     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8099   },
8100   {
8101     /* MOD_0FAE_REG_3 */
8102     { "stmxcsr",        { Md }, 0 },
8103     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8104   },
8105   {
8106     /* MOD_0FAE_REG_4 */
8107     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8108     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8109   },
8110   {
8111     /* MOD_0FAE_REG_5 */
8112     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8113     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8114   },
8115   {
8116     /* MOD_0FAE_REG_6 */
8117     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8118     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8119   },
8120   {
8121     /* MOD_0FAE_REG_7 */
8122     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8123     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8124   },
8125   {
8126     /* MOD_0FB2 */
8127     { "lssS",           { Gv, Mp }, 0 },
8128   },
8129   {
8130     /* MOD_0FB4 */
8131     { "lfsS",           { Gv, Mp }, 0 },
8132   },
8133   {
8134     /* MOD_0FB5 */
8135     { "lgsS",           { Gv, Mp }, 0 },
8136   },
8137   {
8138     /* MOD_0FC3 */
8139     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8140   },
8141   {
8142     /* MOD_0FC7_REG_3 */
8143     { "xrstors",        { FXSAVE }, 0 },
8144   },
8145   {
8146     /* MOD_0FC7_REG_4 */
8147     { "xsavec",         { FXSAVE }, 0 },
8148   },
8149   {
8150     /* MOD_0FC7_REG_5 */
8151     { "xsaves",         { FXSAVE }, 0 },
8152   },
8153   {
8154     /* MOD_0FC7_REG_6 */
8155     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8156     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8157   },
8158   {
8159     /* MOD_0FC7_REG_7 */
8160     { "vmptrst",        { Mq }, 0 },
8161     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8162   },
8163   {
8164     /* MOD_0FD7 */
8165     { Bad_Opcode },
8166     { "pmovmskb",       { Gdq, MS }, 0 },
8167   },
8168   {
8169     /* MOD_0FE7_PREFIX_2 */
8170     { "movntdq",        { Mx, XM }, 0 },
8171   },
8172   {
8173     /* MOD_0FF0_PREFIX_3 */
8174     { "lddqu",          { XM, M }, 0 },
8175   },
8176   {
8177     /* MOD_0F382A */
8178     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8179   },
8180   {
8181     /* MOD_0F38DC_PREFIX_1 */
8182     { "aesenc128kl",    { XM, M }, 0 },
8183     { "loadiwkey",      { XM, EXx }, 0 },
8184   },
8185   {
8186     /* MOD_0F38DD_PREFIX_1 */
8187     { "aesdec128kl",    { XM, M }, 0 },
8188   },
8189   {
8190     /* MOD_0F38DE_PREFIX_1 */
8191     { "aesenc256kl",    { XM, M }, 0 },
8192   },
8193   {
8194     /* MOD_0F38DF_PREFIX_1 */
8195     { "aesdec256kl",    { XM, M }, 0 },
8196   },
8197   {
8198     /* MOD_0F38F5 */
8199     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8200   },
8201   {
8202     /* MOD_0F38F6_PREFIX_0 */
8203     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8204   },
8205   {
8206     /* MOD_0F38F8_PREFIX_1 */
8207     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8208   },
8209   {
8210     /* MOD_0F38F8_PREFIX_2 */
8211     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8212   },
8213   {
8214     /* MOD_0F38F8_PREFIX_3 */
8215     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8216   },
8217   {
8218     /* MOD_0F38F9 */
8219     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8220   },
8221   {
8222     /* MOD_0F38FA_PREFIX_1 */
8223     { Bad_Opcode },
8224     { "encodekey128", { Gd, Ed }, 0 },
8225   },
8226   {
8227     /* MOD_0F38FB_PREFIX_1 */
8228     { Bad_Opcode },
8229     { "encodekey256", { Gd, Ed }, 0 },
8230   },
8231   {
8232     /* MOD_0F3A0F_PREFIX_1 */
8233     { Bad_Opcode },
8234     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8235   },
8236   {
8237     /* MOD_VEX_0F12_PREFIX_0 */
8238     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8239     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8240   },
8241   {
8242     /* MOD_VEX_0F12_PREFIX_2 */
8243     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8244   },
8245   {
8246     /* MOD_VEX_0F13 */
8247     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8248   },
8249   {
8250     /* MOD_VEX_0F16_PREFIX_0 */
8251     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8252     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8253   },
8254   {
8255     /* MOD_VEX_0F16_PREFIX_2 */
8256     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8257   },
8258   {
8259     /* MOD_VEX_0F17 */
8260     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8261   },
8262   {
8263     /* MOD_VEX_0F2B */
8264     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8265   },
8266   {
8267     /* MOD_VEX_0F41_L_1 */
8268     { Bad_Opcode },
8269     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8270   },
8271   {
8272     /* MOD_VEX_0F42_L_1 */
8273     { Bad_Opcode },
8274     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8275   },
8276   {
8277     /* MOD_VEX_0F44_L_0 */
8278     { Bad_Opcode },
8279     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8280   },
8281   {
8282     /* MOD_VEX_0F45_L_1 */
8283     { Bad_Opcode },
8284     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8285   },
8286   {
8287     /* MOD_VEX_0F46_L_1 */
8288     { Bad_Opcode },
8289     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8290   },
8291   {
8292     /* MOD_VEX_0F47_L_1 */
8293     { Bad_Opcode },
8294     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8295   },
8296   {
8297     /* MOD_VEX_0F4A_L_1 */
8298     { Bad_Opcode },
8299     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8300   },
8301   {
8302     /* MOD_VEX_0F4B_L_1 */
8303     { Bad_Opcode },
8304     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8305   },
8306   {
8307     /* MOD_VEX_0F50 */
8308     { Bad_Opcode },
8309     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8310   },
8311   {
8312     /* MOD_VEX_0F71 */
8313     { Bad_Opcode },
8314     { REG_TABLE (REG_VEX_0F71_M_0) },
8315   },
8316   {
8317     /* MOD_VEX_0F72 */
8318     { Bad_Opcode },
8319     { REG_TABLE (REG_VEX_0F72_M_0) },
8320   },
8321   {
8322     /* MOD_VEX_0F73 */
8323     { Bad_Opcode },
8324     { REG_TABLE (REG_VEX_0F73_M_0) },
8325   },
8326   {
8327     /* MOD_VEX_0F91_L_0 */
8328     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8329   },
8330   {
8331     /* MOD_VEX_0F92_L_0 */
8332     { Bad_Opcode },
8333     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8334   },
8335   {
8336     /* MOD_VEX_0F93_L_0 */
8337     { Bad_Opcode },
8338     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8339   },
8340   {
8341     /* MOD_VEX_0F98_L_0 */
8342     { Bad_Opcode },
8343     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8344   },
8345   {
8346     /* MOD_VEX_0F99_L_0 */
8347     { Bad_Opcode },
8348     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8349   },
8350   {
8351     /* MOD_VEX_0FAE_REG_2 */
8352     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8353   },
8354   {
8355     /* MOD_VEX_0FAE_REG_3 */
8356     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8357   },
8358   {
8359     /* MOD_VEX_0FD7 */
8360     { Bad_Opcode },
8361     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8362   },
8363   {
8364     /* MOD_VEX_0FE7 */
8365     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8366   },
8367   {
8368     /* MOD_VEX_0FF0_PREFIX_3 */
8369     { "vlddqu",         { XM, M }, 0 },
8370   },
8371   {
8372     /* MOD_VEX_0F381A */
8373     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8374   },
8375   {
8376     /* MOD_VEX_0F382A */
8377     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8378   },
8379   {
8380     /* MOD_VEX_0F382C */
8381     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8382   },
8383   {
8384     /* MOD_VEX_0F382D */
8385     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8386   },
8387   {
8388     /* MOD_VEX_0F382E */
8389     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8390   },
8391   {
8392     /* MOD_VEX_0F382F */
8393     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8394   },
8395   {
8396     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8397     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8398     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8399   },
8400   {
8401     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8402     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8403   },
8404   {
8405     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8406     { Bad_Opcode },
8407     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8408   },
8409   {
8410     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8411     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8412   },
8413   {
8414     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8415     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8416   },
8417   {
8418     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8419     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8420   },
8421   {
8422     /* MOD_VEX_0F385A */
8423     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8424   },
8425   {
8426     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8427     { Bad_Opcode },
8428     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8429   },
8430   {
8431     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8432     { Bad_Opcode },
8433     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8434   },
8435   {
8436     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8437     { Bad_Opcode },
8438     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8439   },
8440   {
8441     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8442     { Bad_Opcode },
8443     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8444   },
8445   {
8446     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8447     { Bad_Opcode },
8448     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8449   },
8450   {
8451     /* MOD_VEX_0F388C */
8452     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8453   },
8454   {
8455     /* MOD_VEX_0F388E */
8456     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8457   },
8458   {
8459     /* MOD_VEX_0F3A30_L_0 */
8460     { Bad_Opcode },
8461     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8462   },
8463   {
8464     /* MOD_VEX_0F3A31_L_0 */
8465     { Bad_Opcode },
8466     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8467   },
8468   {
8469     /* MOD_VEX_0F3A32_L_0 */
8470     { Bad_Opcode },
8471     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8472   },
8473   {
8474     /* MOD_VEX_0F3A33_L_0 */
8475     { Bad_Opcode },
8476     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8477   },
8478   {
8479     /* MOD_XOP_09_12 */
8480     { Bad_Opcode },
8481     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8482   },
8483
8484 #include "i386-dis-evex-mod.h"
8485 };
8486
8487 static const struct dis386 rm_table[][8] = {
8488   {
8489     /* RM_C6_REG_7 */
8490     { "xabort",         { Skip_MODRM, Ib }, 0 },
8491   },
8492   {
8493     /* RM_C7_REG_7 */
8494     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8495   },
8496   {
8497     /* RM_0F01_REG_0 */
8498     { "enclv",          { Skip_MODRM }, 0 },
8499     { "vmcall",         { Skip_MODRM }, 0 },
8500     { "vmlaunch",       { Skip_MODRM }, 0 },
8501     { "vmresume",       { Skip_MODRM }, 0 },
8502     { "vmxoff",         { Skip_MODRM }, 0 },
8503     { "pconfig",        { Skip_MODRM }, 0 },
8504   },
8505   {
8506     /* RM_0F01_REG_1 */
8507     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8508     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8509     { "clac",           { Skip_MODRM }, 0 },
8510     { "stac",           { Skip_MODRM }, 0 },
8511     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8512     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8513     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8514     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8515   },
8516   {
8517     /* RM_0F01_REG_2 */
8518     { "xgetbv",         { Skip_MODRM }, 0 },
8519     { "xsetbv",         { Skip_MODRM }, 0 },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { "vmfunc",         { Skip_MODRM }, 0 },
8523     { "xend",           { Skip_MODRM }, 0 },
8524     { "xtest",          { Skip_MODRM }, 0 },
8525     { "enclu",          { Skip_MODRM }, 0 },
8526   },
8527   {
8528     /* RM_0F01_REG_3 */
8529     { "vmrun",          { Skip_MODRM }, 0 },
8530     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8531     { "vmload",         { Skip_MODRM }, 0 },
8532     { "vmsave",         { Skip_MODRM }, 0 },
8533     { "stgi",           { Skip_MODRM }, 0 },
8534     { "clgi",           { Skip_MODRM }, 0 },
8535     { "skinit",         { Skip_MODRM }, 0 },
8536     { "invlpga",        { Skip_MODRM }, 0 },
8537   },
8538   {
8539     /* RM_0F01_REG_5_MOD_3 */
8540     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8541     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8542     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8543     { Bad_Opcode },
8544     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8545     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8546     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8547     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8548   },
8549   {
8550     /* RM_0F01_REG_7_MOD_3 */
8551     { "swapgs",         { Skip_MODRM }, 0  },
8552     { "rdtscp",         { Skip_MODRM }, 0  },
8553     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8554     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8555     { "clzero",         { Skip_MODRM }, 0  },
8556     { "rdpru",          { Skip_MODRM }, 0  },
8557     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8558     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8559   },
8560   {
8561     /* RM_0F1E_P_1_MOD_3_REG_7 */
8562     { "nopQ",           { Ev }, PREFIX_IGNORED },
8563     { "nopQ",           { Ev }, PREFIX_IGNORED },
8564     { "endbr64",        { Skip_MODRM }, 0 },
8565     { "endbr32",        { Skip_MODRM }, 0 },
8566     { "nopQ",           { Ev }, PREFIX_IGNORED },
8567     { "nopQ",           { Ev }, PREFIX_IGNORED },
8568     { "nopQ",           { Ev }, PREFIX_IGNORED },
8569     { "nopQ",           { Ev }, PREFIX_IGNORED },
8570   },
8571   {
8572     /* RM_0FAE_REG_6_MOD_3 */
8573     { "mfence",         { Skip_MODRM }, 0 },
8574   },
8575   {
8576     /* RM_0FAE_REG_7_MOD_3 */
8577     { "sfence",         { Skip_MODRM }, 0 },
8578   },
8579   {
8580     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8581     { "hreset",         { Skip_MODRM, Ib }, 0 },
8582   },
8583   {
8584     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8585     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8586   },
8587 };
8588
8589 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8590
8591 /* We use the high bit to indicate different name for the same
8592    prefix.  */
8593 #define REP_PREFIX      (0xf3 | 0x100)
8594 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8595 #define XRELEASE_PREFIX (0xf3 | 0x400)
8596 #define BND_PREFIX      (0xf2 | 0x400)
8597 #define NOTRACK_PREFIX  (0x3e | 0x100)
8598
8599 /* Remember if the current op is a jump instruction.  */
8600 static bfd_boolean op_is_jump = FALSE;
8601
8602 static int
8603 ckprefix (void)
8604 {
8605   int newrex, i, length;
8606   rex = 0;
8607   prefixes = 0;
8608   used_prefixes = 0;
8609   rex_used = 0;
8610   last_lock_prefix = -1;
8611   last_repz_prefix = -1;
8612   last_repnz_prefix = -1;
8613   last_data_prefix = -1;
8614   last_addr_prefix = -1;
8615   last_rex_prefix = -1;
8616   last_seg_prefix = -1;
8617   fwait_prefix = -1;
8618   active_seg_prefix = 0;
8619   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8620     all_prefixes[i] = 0;
8621   i = 0;
8622   length = 0;
8623   /* The maximum instruction length is 15bytes.  */
8624   while (length < MAX_CODE_LENGTH - 1)
8625     {
8626       FETCH_DATA (the_info, codep + 1);
8627       newrex = 0;
8628       switch (*codep)
8629         {
8630         /* REX prefixes family.  */
8631         case 0x40:
8632         case 0x41:
8633         case 0x42:
8634         case 0x43:
8635         case 0x44:
8636         case 0x45:
8637         case 0x46:
8638         case 0x47:
8639         case 0x48:
8640         case 0x49:
8641         case 0x4a:
8642         case 0x4b:
8643         case 0x4c:
8644         case 0x4d:
8645         case 0x4e:
8646         case 0x4f:
8647           if (address_mode == mode_64bit)
8648             newrex = *codep;
8649           else
8650             return 1;
8651           last_rex_prefix = i;
8652           break;
8653         case 0xf3:
8654           prefixes |= PREFIX_REPZ;
8655           last_repz_prefix = i;
8656           break;
8657         case 0xf2:
8658           prefixes |= PREFIX_REPNZ;
8659           last_repnz_prefix = i;
8660           break;
8661         case 0xf0:
8662           prefixes |= PREFIX_LOCK;
8663           last_lock_prefix = i;
8664           break;
8665         case 0x2e:
8666           prefixes |= PREFIX_CS;
8667           last_seg_prefix = i;
8668
8669           if (address_mode != mode_64bit)
8670             active_seg_prefix = PREFIX_CS;
8671
8672           break;
8673         case 0x36:
8674           prefixes |= PREFIX_SS;
8675           last_seg_prefix = i;
8676
8677           if (address_mode != mode_64bit)
8678             active_seg_prefix = PREFIX_SS;
8679
8680           break;
8681         case 0x3e:
8682           prefixes |= PREFIX_DS;
8683           last_seg_prefix = i;
8684
8685           if (address_mode != mode_64bit)
8686             active_seg_prefix = PREFIX_DS;
8687
8688           break;
8689         case 0x26:
8690           prefixes |= PREFIX_ES;
8691           last_seg_prefix = i;
8692
8693           if (address_mode != mode_64bit)
8694             active_seg_prefix = PREFIX_ES;
8695
8696           break;
8697         case 0x64:
8698           prefixes |= PREFIX_FS;
8699           last_seg_prefix = i;
8700           active_seg_prefix = PREFIX_FS;
8701           break;
8702         case 0x65:
8703           prefixes |= PREFIX_GS;
8704           last_seg_prefix = i;
8705           active_seg_prefix = PREFIX_GS;
8706           break;
8707         case 0x66:
8708           prefixes |= PREFIX_DATA;
8709           last_data_prefix = i;
8710           break;
8711         case 0x67:
8712           prefixes |= PREFIX_ADDR;
8713           last_addr_prefix = i;
8714           break;
8715         case FWAIT_OPCODE:
8716           /* fwait is really an instruction.  If there are prefixes
8717              before the fwait, they belong to the fwait, *not* to the
8718              following instruction.  */
8719           fwait_prefix = i;
8720           if (prefixes || rex)
8721             {
8722               prefixes |= PREFIX_FWAIT;
8723               codep++;
8724               /* This ensures that the previous REX prefixes are noticed
8725                  as unused prefixes, as in the return case below.  */
8726               rex_used = rex;
8727               return 1;
8728             }
8729           prefixes = PREFIX_FWAIT;
8730           break;
8731         default:
8732           return 1;
8733         }
8734       /* Rex is ignored when followed by another prefix.  */
8735       if (rex)
8736         {
8737           rex_used = rex;
8738           return 1;
8739         }
8740       if (*codep != FWAIT_OPCODE)
8741         all_prefixes[i++] = *codep;
8742       rex = newrex;
8743       codep++;
8744       length++;
8745     }
8746   return 0;
8747 }
8748
8749 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8750    prefix byte.  */
8751
8752 static const char *
8753 prefix_name (int pref, int sizeflag)
8754 {
8755   static const char *rexes [16] =
8756     {
8757       "rex",            /* 0x40 */
8758       "rex.B",          /* 0x41 */
8759       "rex.X",          /* 0x42 */
8760       "rex.XB",         /* 0x43 */
8761       "rex.R",          /* 0x44 */
8762       "rex.RB",         /* 0x45 */
8763       "rex.RX",         /* 0x46 */
8764       "rex.RXB",        /* 0x47 */
8765       "rex.W",          /* 0x48 */
8766       "rex.WB",         /* 0x49 */
8767       "rex.WX",         /* 0x4a */
8768       "rex.WXB",        /* 0x4b */
8769       "rex.WR",         /* 0x4c */
8770       "rex.WRB",        /* 0x4d */
8771       "rex.WRX",        /* 0x4e */
8772       "rex.WRXB",       /* 0x4f */
8773     };
8774
8775   switch (pref)
8776     {
8777     /* REX prefixes family.  */
8778     case 0x40:
8779     case 0x41:
8780     case 0x42:
8781     case 0x43:
8782     case 0x44:
8783     case 0x45:
8784     case 0x46:
8785     case 0x47:
8786     case 0x48:
8787     case 0x49:
8788     case 0x4a:
8789     case 0x4b:
8790     case 0x4c:
8791     case 0x4d:
8792     case 0x4e:
8793     case 0x4f:
8794       return rexes [pref - 0x40];
8795     case 0xf3:
8796       return "repz";
8797     case 0xf2:
8798       return "repnz";
8799     case 0xf0:
8800       return "lock";
8801     case 0x2e:
8802       return "cs";
8803     case 0x36:
8804       return "ss";
8805     case 0x3e:
8806       return "ds";
8807     case 0x26:
8808       return "es";
8809     case 0x64:
8810       return "fs";
8811     case 0x65:
8812       return "gs";
8813     case 0x66:
8814       return (sizeflag & DFLAG) ? "data16" : "data32";
8815     case 0x67:
8816       if (address_mode == mode_64bit)
8817         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8818       else
8819         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8820     case FWAIT_OPCODE:
8821       return "fwait";
8822     case REP_PREFIX:
8823       return "rep";
8824     case XACQUIRE_PREFIX:
8825       return "xacquire";
8826     case XRELEASE_PREFIX:
8827       return "xrelease";
8828     case BND_PREFIX:
8829       return "bnd";
8830     case NOTRACK_PREFIX:
8831       return "notrack";
8832     default:
8833       return NULL;
8834     }
8835 }
8836
8837 static char op_out[MAX_OPERANDS][100];
8838 static int op_ad, op_index[MAX_OPERANDS];
8839 static int two_source_ops;
8840 static bfd_vma op_address[MAX_OPERANDS];
8841 static bfd_vma op_riprel[MAX_OPERANDS];
8842 static bfd_vma start_pc;
8843
8844 /*
8845  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8846  *   (see topic "Redundant prefixes" in the "Differences from 8086"
8847  *   section of the "Virtual 8086 Mode" chapter.)
8848  * 'pc' should be the address of this instruction, it will
8849  *   be used to print the target address if this is a relative jump or call
8850  * The function returns the length of this instruction in bytes.
8851  */
8852
8853 static char intel_syntax;
8854 static char intel_mnemonic = !SYSV386_COMPAT;
8855 static char open_char;
8856 static char close_char;
8857 static char separator_char;
8858 static char scale_char;
8859
8860 enum x86_64_isa
8861 {
8862   amd64 = 1,
8863   intel64
8864 };
8865
8866 static enum x86_64_isa isa64;
8867
8868 /* Here for backwards compatibility.  When gdb stops using
8869    print_insn_i386_att and print_insn_i386_intel these functions can
8870    disappear, and print_insn_i386 be merged into print_insn.  */
8871 int
8872 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
8873 {
8874   intel_syntax = 0;
8875
8876   return print_insn (pc, info);
8877 }
8878
8879 int
8880 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
8881 {
8882   intel_syntax = 1;
8883
8884   return print_insn (pc, info);
8885 }
8886
8887 int
8888 print_insn_i386 (bfd_vma pc, disassemble_info *info)
8889 {
8890   intel_syntax = -1;
8891
8892   return print_insn (pc, info);
8893 }
8894
8895 void
8896 print_i386_disassembler_options (FILE *stream)
8897 {
8898   fprintf (stream, _("\n\
8899 The following i386/x86-64 specific disassembler options are supported for use\n\
8900 with the -M switch (multiple options should be separated by commas):\n"));
8901
8902   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8903   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8904   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8905   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8906   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8907   fprintf (stream, _("  att-mnemonic\n"
8908                      "              Display instruction in AT&T mnemonic\n"));
8909   fprintf (stream, _("  intel-mnemonic\n"
8910                      "              Display instruction in Intel mnemonic\n"));
8911   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8912   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8913   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8914   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8915   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8916   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8917   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8918   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8919 }
8920
8921 /* Bad opcode.  */
8922 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8923
8924 /* Get a pointer to struct dis386 with a valid name.  */
8925
8926 static const struct dis386 *
8927 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
8928 {
8929   int vindex, vex_table_index;
8930
8931   if (dp->name != NULL)
8932     return dp;
8933
8934   switch (dp->op[0].bytemode)
8935     {
8936     case USE_REG_TABLE:
8937       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
8938       break;
8939
8940     case USE_MOD_TABLE:
8941       vindex = modrm.mod == 0x3 ? 1 : 0;
8942       dp = &mod_table[dp->op[1].bytemode][vindex];
8943       break;
8944
8945     case USE_RM_TABLE:
8946       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
8947       break;
8948
8949     case USE_PREFIX_TABLE:
8950       if (need_vex)
8951         {
8952           /* The prefix in VEX is implicit.  */
8953           switch (vex.prefix)
8954             {
8955             case 0:
8956               vindex = 0;
8957               break;
8958             case REPE_PREFIX_OPCODE:
8959               vindex = 1;
8960               break;
8961             case DATA_PREFIX_OPCODE:
8962               vindex = 2;
8963               break;
8964             case REPNE_PREFIX_OPCODE:
8965               vindex = 3;
8966               break;
8967             default:
8968               abort ();
8969               break;
8970             }
8971         }
8972       else
8973         {
8974           int last_prefix = -1;
8975           int prefix = 0;
8976           vindex = 0;
8977           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8978              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8979              last one wins.  */
8980           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8981             {
8982               if (last_repz_prefix > last_repnz_prefix)
8983                 {
8984                   vindex = 1;
8985                   prefix = PREFIX_REPZ;
8986                   last_prefix = last_repz_prefix;
8987                 }
8988               else
8989                 {
8990                   vindex = 3;
8991                   prefix = PREFIX_REPNZ;
8992                   last_prefix = last_repnz_prefix;
8993                 }
8994
8995               /* Check if prefix should be ignored.  */
8996               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8997                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8998                    & prefix) != 0
8999                   && !prefix_table[dp->op[1].bytemode][vindex].name)
9000                 vindex = 0;
9001             }
9002
9003           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9004             {
9005               vindex = 2;
9006               prefix = PREFIX_DATA;
9007               last_prefix = last_data_prefix;
9008             }
9009
9010           if (vindex != 0)
9011             {
9012               used_prefixes |= prefix;
9013               all_prefixes[last_prefix] = 0;
9014             }
9015         }
9016       dp = &prefix_table[dp->op[1].bytemode][vindex];
9017       break;
9018
9019     case USE_X86_64_TABLE:
9020       vindex = address_mode == mode_64bit ? 1 : 0;
9021       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9022       break;
9023
9024     case USE_3BYTE_TABLE:
9025       FETCH_DATA (info, codep + 2);
9026       vindex = *codep++;
9027       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9028       end_codep = codep;
9029       modrm.mod = (*codep >> 6) & 3;
9030       modrm.reg = (*codep >> 3) & 7;
9031       modrm.rm = *codep & 7;
9032       break;
9033
9034     case USE_VEX_LEN_TABLE:
9035       if (!need_vex)
9036         abort ();
9037
9038       switch (vex.length)
9039         {
9040         case 128:
9041           vindex = 0;
9042           break;
9043         case 512:
9044           /* This allows re-using in particular table entries where only
9045              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
9046           if (vex.evex)
9047             {
9048         case 256:
9049               vindex = 1;
9050               break;
9051             }
9052         /* Fall through.  */
9053         default:
9054           abort ();
9055           break;
9056         }
9057
9058       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9059       break;
9060
9061     case USE_EVEX_LEN_TABLE:
9062       if (!vex.evex)
9063         abort ();
9064
9065       switch (vex.length)
9066         {
9067         case 128:
9068           vindex = 0;
9069           break;
9070         case 256:
9071           vindex = 1;
9072           break;
9073         case 512:
9074           vindex = 2;
9075           break;
9076         default:
9077           abort ();
9078           break;
9079         }
9080
9081       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9082       break;
9083
9084     case USE_XOP_8F_TABLE:
9085       FETCH_DATA (info, codep + 3);
9086       rex = ~(*codep >> 5) & 0x7;
9087
9088       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9089       switch ((*codep & 0x1f))
9090         {
9091         default:
9092           dp = &bad_opcode;
9093           return dp;
9094         case 0x8:
9095           vex_table_index = XOP_08;
9096           break;
9097         case 0x9:
9098           vex_table_index = XOP_09;
9099           break;
9100         case 0xa:
9101           vex_table_index = XOP_0A;
9102           break;
9103         }
9104       codep++;
9105       vex.w = *codep & 0x80;
9106       if (vex.w && address_mode == mode_64bit)
9107         rex |= REX_W;
9108
9109       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9110       if (address_mode != mode_64bit)
9111         {
9112           /* In 16/32-bit mode REX_B is silently ignored.  */
9113           rex &= ~REX_B;
9114         }
9115
9116       vex.length = (*codep & 0x4) ? 256 : 128;
9117       switch ((*codep & 0x3))
9118         {
9119         case 0:
9120           break;
9121         case 1:
9122           vex.prefix = DATA_PREFIX_OPCODE;
9123           break;
9124         case 2:
9125           vex.prefix = REPE_PREFIX_OPCODE;
9126           break;
9127         case 3:
9128           vex.prefix = REPNE_PREFIX_OPCODE;
9129           break;
9130         }
9131       need_vex = 1;
9132       codep++;
9133       vindex = *codep++;
9134       dp = &xop_table[vex_table_index][vindex];
9135
9136       end_codep = codep;
9137       FETCH_DATA (info, codep + 1);
9138       modrm.mod = (*codep >> 6) & 3;
9139       modrm.reg = (*codep >> 3) & 7;
9140       modrm.rm = *codep & 7;
9141
9142       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9143          having to decode the bits for every otherwise valid encoding.  */
9144       if (vex.prefix)
9145         return &bad_opcode;
9146       break;
9147
9148     case USE_VEX_C4_TABLE:
9149       /* VEX prefix.  */
9150       FETCH_DATA (info, codep + 3);
9151       rex = ~(*codep >> 5) & 0x7;
9152       switch ((*codep & 0x1f))
9153         {
9154         default:
9155           dp = &bad_opcode;
9156           return dp;
9157         case 0x1:
9158           vex_table_index = VEX_0F;
9159           break;
9160         case 0x2:
9161           vex_table_index = VEX_0F38;
9162           break;
9163         case 0x3:
9164           vex_table_index = VEX_0F3A;
9165           break;
9166         }
9167       codep++;
9168       vex.w = *codep & 0x80;
9169       if (address_mode == mode_64bit)
9170         {
9171           if (vex.w)
9172             rex |= REX_W;
9173         }
9174       else
9175         {
9176           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9177              is ignored, other REX bits are 0 and the highest bit in
9178              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9179           rex = 0;
9180         }
9181       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9182       vex.length = (*codep & 0x4) ? 256 : 128;
9183       switch ((*codep & 0x3))
9184         {
9185         case 0:
9186           break;
9187         case 1:
9188           vex.prefix = DATA_PREFIX_OPCODE;
9189           break;
9190         case 2:
9191           vex.prefix = REPE_PREFIX_OPCODE;
9192           break;
9193         case 3:
9194           vex.prefix = REPNE_PREFIX_OPCODE;
9195           break;
9196         }
9197       need_vex = 1;
9198       codep++;
9199       vindex = *codep++;
9200       dp = &vex_table[vex_table_index][vindex];
9201       end_codep = codep;
9202       /* There is no MODRM byte for VEX0F 77.  */
9203       if (vex_table_index != VEX_0F || vindex != 0x77)
9204         {
9205           FETCH_DATA (info, codep + 1);
9206           modrm.mod = (*codep >> 6) & 3;
9207           modrm.reg = (*codep >> 3) & 7;
9208           modrm.rm = *codep & 7;
9209         }
9210       break;
9211
9212     case USE_VEX_C5_TABLE:
9213       /* VEX prefix.  */
9214       FETCH_DATA (info, codep + 2);
9215       rex = (*codep & 0x80) ? 0 : REX_R;
9216
9217       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9218          VEX.vvvv is 1.  */
9219       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9220       vex.length = (*codep & 0x4) ? 256 : 128;
9221       switch ((*codep & 0x3))
9222         {
9223         case 0:
9224           break;
9225         case 1:
9226           vex.prefix = DATA_PREFIX_OPCODE;
9227           break;
9228         case 2:
9229           vex.prefix = REPE_PREFIX_OPCODE;
9230           break;
9231         case 3:
9232           vex.prefix = REPNE_PREFIX_OPCODE;
9233           break;
9234         }
9235       need_vex = 1;
9236       codep++;
9237       vindex = *codep++;
9238       dp = &vex_table[dp->op[1].bytemode][vindex];
9239       end_codep = codep;
9240       /* There is no MODRM byte for VEX 77.  */
9241       if (vindex != 0x77)
9242         {
9243           FETCH_DATA (info, codep + 1);
9244           modrm.mod = (*codep >> 6) & 3;
9245           modrm.reg = (*codep >> 3) & 7;
9246           modrm.rm = *codep & 7;
9247         }
9248       break;
9249
9250     case USE_VEX_W_TABLE:
9251       if (!need_vex)
9252         abort ();
9253
9254       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9255       break;
9256
9257     case USE_EVEX_TABLE:
9258       two_source_ops = 0;
9259       /* EVEX prefix.  */
9260       vex.evex = 1;
9261       FETCH_DATA (info, codep + 4);
9262       /* The first byte after 0x62.  */
9263       rex = ~(*codep >> 5) & 0x7;
9264       vex.r = *codep & 0x10;
9265       switch ((*codep & 0xf))
9266         {
9267         default:
9268           return &bad_opcode;
9269         case 0x1:
9270           vex_table_index = EVEX_0F;
9271           break;
9272         case 0x2:
9273           vex_table_index = EVEX_0F38;
9274           break;
9275         case 0x3:
9276           vex_table_index = EVEX_0F3A;
9277           break;
9278         }
9279
9280       /* The second byte after 0x62.  */
9281       codep++;
9282       vex.w = *codep & 0x80;
9283       if (vex.w && address_mode == mode_64bit)
9284         rex |= REX_W;
9285
9286       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9287
9288       /* The U bit.  */
9289       if (!(*codep & 0x4))
9290         return &bad_opcode;
9291
9292       switch ((*codep & 0x3))
9293         {
9294         case 0:
9295           break;
9296         case 1:
9297           vex.prefix = DATA_PREFIX_OPCODE;
9298           break;
9299         case 2:
9300           vex.prefix = REPE_PREFIX_OPCODE;
9301           break;
9302         case 3:
9303           vex.prefix = REPNE_PREFIX_OPCODE;
9304           break;
9305         }
9306
9307       /* The third byte after 0x62.  */
9308       codep++;
9309
9310       /* Remember the static rounding bits.  */
9311       vex.ll = (*codep >> 5) & 3;
9312       vex.b = (*codep & 0x10) != 0;
9313
9314       vex.v = *codep & 0x8;
9315       vex.mask_register_specifier = *codep & 0x7;
9316       vex.zeroing = *codep & 0x80;
9317
9318       if (address_mode != mode_64bit)
9319         {
9320           /* In 16/32-bit mode silently ignore following bits.  */
9321           rex &= ~REX_B;
9322           vex.r = 1;
9323           vex.v = 1;
9324         }
9325
9326       need_vex = 1;
9327       codep++;
9328       vindex = *codep++;
9329       dp = &evex_table[vex_table_index][vindex];
9330       end_codep = codep;
9331       FETCH_DATA (info, codep + 1);
9332       modrm.mod = (*codep >> 6) & 3;
9333       modrm.reg = (*codep >> 3) & 7;
9334       modrm.rm = *codep & 7;
9335
9336       /* Set vector length.  */
9337       if (modrm.mod == 3 && vex.b)
9338         vex.length = 512;
9339       else
9340         {
9341           switch (vex.ll)
9342             {
9343             case 0x0:
9344               vex.length = 128;
9345               break;
9346             case 0x1:
9347               vex.length = 256;
9348               break;
9349             case 0x2:
9350               vex.length = 512;
9351               break;
9352             default:
9353               return &bad_opcode;
9354             }
9355         }
9356       break;
9357
9358     case 0:
9359       dp = &bad_opcode;
9360       break;
9361
9362     default:
9363       abort ();
9364     }
9365
9366   if (dp->name != NULL)
9367     return dp;
9368   else
9369     return get_valid_dis386 (dp, info);
9370 }
9371
9372 static void
9373 get_sib (disassemble_info *info, int sizeflag)
9374 {
9375   /* If modrm.mod == 3, operand must be register.  */
9376   if (need_modrm
9377       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9378       && modrm.mod != 3
9379       && modrm.rm == 4)
9380     {
9381       FETCH_DATA (info, codep + 2);
9382       sib.index = (codep [1] >> 3) & 7;
9383       sib.scale = (codep [1] >> 6) & 3;
9384       sib.base = codep [1] & 7;
9385     }
9386 }
9387
9388 static int
9389 print_insn (bfd_vma pc, disassemble_info *info)
9390 {
9391   const struct dis386 *dp;
9392   int i;
9393   char *op_txt[MAX_OPERANDS];
9394   int needcomma;
9395   int sizeflag, orig_sizeflag;
9396   const char *p;
9397   struct dis_private priv;
9398   int prefix_length;
9399
9400   priv.orig_sizeflag = AFLAG | DFLAG;
9401   if ((info->mach & bfd_mach_i386_i386) != 0)
9402     address_mode = mode_32bit;
9403   else if (info->mach == bfd_mach_i386_i8086)
9404     {
9405       address_mode = mode_16bit;
9406       priv.orig_sizeflag = 0;
9407     }
9408   else
9409     address_mode = mode_64bit;
9410
9411   if (intel_syntax == (char) -1)
9412     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9413
9414   for (p = info->disassembler_options; p != NULL; )
9415     {
9416       if (startswith (p, "amd64"))
9417         isa64 = amd64;
9418       else if (startswith (p, "intel64"))
9419         isa64 = intel64;
9420       else if (startswith (p, "x86-64"))
9421         {
9422           address_mode = mode_64bit;
9423           priv.orig_sizeflag |= AFLAG | DFLAG;
9424         }
9425       else if (startswith (p, "i386"))
9426         {
9427           address_mode = mode_32bit;
9428           priv.orig_sizeflag |= AFLAG | DFLAG;
9429         }
9430       else if (startswith (p, "i8086"))
9431         {
9432           address_mode = mode_16bit;
9433           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9434         }
9435       else if (startswith (p, "intel"))
9436         {
9437           intel_syntax = 1;
9438           if (startswith (p + 5, "-mnemonic"))
9439             intel_mnemonic = 1;
9440         }
9441       else if (startswith (p, "att"))
9442         {
9443           intel_syntax = 0;
9444           if (startswith (p + 3, "-mnemonic"))
9445             intel_mnemonic = 0;
9446         }
9447       else if (startswith (p, "addr"))
9448         {
9449           if (address_mode == mode_64bit)
9450             {
9451               if (p[4] == '3' && p[5] == '2')
9452                 priv.orig_sizeflag &= ~AFLAG;
9453               else if (p[4] == '6' && p[5] == '4')
9454                 priv.orig_sizeflag |= AFLAG;
9455             }
9456           else
9457             {
9458               if (p[4] == '1' && p[5] == '6')
9459                 priv.orig_sizeflag &= ~AFLAG;
9460               else if (p[4] == '3' && p[5] == '2')
9461                 priv.orig_sizeflag |= AFLAG;
9462             }
9463         }
9464       else if (startswith (p, "data"))
9465         {
9466           if (p[4] == '1' && p[5] == '6')
9467             priv.orig_sizeflag &= ~DFLAG;
9468           else if (p[4] == '3' && p[5] == '2')
9469             priv.orig_sizeflag |= DFLAG;
9470         }
9471       else if (startswith (p, "suffix"))
9472         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9473
9474       p = strchr (p, ',');
9475       if (p != NULL)
9476         p++;
9477     }
9478
9479   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9480     {
9481       (*info->fprintf_func) (info->stream,
9482                              _("64-bit address is disabled"));
9483       return -1;
9484     }
9485
9486   if (intel_syntax)
9487     {
9488       names64 = intel_names64;
9489       names32 = intel_names32;
9490       names16 = intel_names16;
9491       names8 = intel_names8;
9492       names8rex = intel_names8rex;
9493       names_seg = intel_names_seg;
9494       names_mm = intel_names_mm;
9495       names_bnd = intel_names_bnd;
9496       names_xmm = intel_names_xmm;
9497       names_ymm = intel_names_ymm;
9498       names_zmm = intel_names_zmm;
9499       names_tmm = intel_names_tmm;
9500       index64 = intel_index64;
9501       index32 = intel_index32;
9502       names_mask = intel_names_mask;
9503       index16 = intel_index16;
9504       open_char = '[';
9505       close_char = ']';
9506       separator_char = '+';
9507       scale_char = '*';
9508     }
9509   else
9510     {
9511       names64 = att_names64;
9512       names32 = att_names32;
9513       names16 = att_names16;
9514       names8 = att_names8;
9515       names8rex = att_names8rex;
9516       names_seg = att_names_seg;
9517       names_mm = att_names_mm;
9518       names_bnd = att_names_bnd;
9519       names_xmm = att_names_xmm;
9520       names_ymm = att_names_ymm;
9521       names_zmm = att_names_zmm;
9522       names_tmm = att_names_tmm;
9523       index64 = att_index64;
9524       index32 = att_index32;
9525       names_mask = att_names_mask;
9526       index16 = att_index16;
9527       open_char = '(';
9528       close_char =  ')';
9529       separator_char = ',';
9530       scale_char = ',';
9531     }
9532
9533   /* The output looks better if we put 7 bytes on a line, since that
9534      puts most long word instructions on a single line.  Use 8 bytes
9535      for Intel L1OM.  */
9536   if ((info->mach & bfd_mach_l1om) != 0)
9537     info->bytes_per_line = 8;
9538   else
9539     info->bytes_per_line = 7;
9540
9541   info->private_data = &priv;
9542   priv.max_fetched = priv.the_buffer;
9543   priv.insn_start = pc;
9544
9545   obuf[0] = 0;
9546   for (i = 0; i < MAX_OPERANDS; ++i)
9547     {
9548       op_out[i][0] = 0;
9549       op_index[i] = -1;
9550     }
9551
9552   the_info = info;
9553   start_pc = pc;
9554   start_codep = priv.the_buffer;
9555   codep = priv.the_buffer;
9556
9557   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9558     {
9559       const char *name;
9560
9561       /* Getting here means we tried for data but didn't get it.  That
9562          means we have an incomplete instruction of some sort.  Just
9563          print the first byte as a prefix or a .byte pseudo-op.  */
9564       if (codep > priv.the_buffer)
9565         {
9566           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9567           if (name != NULL)
9568             (*info->fprintf_func) (info->stream, "%s", name);
9569           else
9570             {
9571               /* Just print the first byte as a .byte instruction.  */
9572               (*info->fprintf_func) (info->stream, ".byte 0x%x",
9573                                      (unsigned int) priv.the_buffer[0]);
9574             }
9575
9576           return 1;
9577         }
9578
9579       return -1;
9580     }
9581
9582   obufp = obuf;
9583   sizeflag = priv.orig_sizeflag;
9584
9585   if (!ckprefix () || rex_used)
9586     {
9587       /* Too many prefixes or unused REX prefixes.  */
9588       for (i = 0;
9589            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9590            i++)
9591         (*info->fprintf_func) (info->stream, "%s%s",
9592                                i == 0 ? "" : " ",
9593                                prefix_name (all_prefixes[i], sizeflag));
9594       return i;
9595     }
9596
9597   insn_codep = codep;
9598
9599   FETCH_DATA (info, codep + 1);
9600   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9601
9602   if (((prefixes & PREFIX_FWAIT)
9603        && ((*codep < 0xd8) || (*codep > 0xdf))))
9604     {
9605       /* Handle prefixes before fwait.  */
9606       for (i = 0; i < fwait_prefix && all_prefixes[i];
9607            i++)
9608         (*info->fprintf_func) (info->stream, "%s ",
9609                                prefix_name (all_prefixes[i], sizeflag));
9610       (*info->fprintf_func) (info->stream, "fwait");
9611       return i + 1;
9612     }
9613
9614   if (*codep == 0x0f)
9615     {
9616       unsigned char threebyte;
9617
9618       codep++;
9619       FETCH_DATA (info, codep + 1);
9620       threebyte = *codep;
9621       dp = &dis386_twobyte[threebyte];
9622       need_modrm = twobyte_has_modrm[threebyte];
9623       codep++;
9624     }
9625   else
9626     {
9627       dp = &dis386[*codep];
9628       need_modrm = onebyte_has_modrm[*codep];
9629       codep++;
9630     }
9631
9632   /* Save sizeflag for printing the extra prefixes later before updating
9633      it for mnemonic and operand processing.  The prefix names depend
9634      only on the address mode.  */
9635   orig_sizeflag = sizeflag;
9636   if (prefixes & PREFIX_ADDR)
9637     sizeflag ^= AFLAG;
9638   if ((prefixes & PREFIX_DATA))
9639     sizeflag ^= DFLAG;
9640
9641   end_codep = codep;
9642   if (need_modrm)
9643     {
9644       FETCH_DATA (info, codep + 1);
9645       modrm.mod = (*codep >> 6) & 3;
9646       modrm.reg = (*codep >> 3) & 7;
9647       modrm.rm = *codep & 7;
9648     }
9649   else
9650     memset (&modrm, 0, sizeof (modrm));
9651
9652   need_vex = 0;
9653   memset (&vex, 0, sizeof (vex));
9654
9655   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9656     {
9657       get_sib (info, sizeflag);
9658       dofloat (sizeflag);
9659     }
9660   else
9661     {
9662       dp = get_valid_dis386 (dp, info);
9663       if (dp != NULL && putop (dp->name, sizeflag) == 0)
9664         {
9665           get_sib (info, sizeflag);
9666           for (i = 0; i < MAX_OPERANDS; ++i)
9667             {
9668               obufp = op_out[i];
9669               op_ad = MAX_OPERANDS - 1 - i;
9670               if (dp->op[i].rtn)
9671                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9672               /* For EVEX instruction after the last operand masking
9673                  should be printed.  */
9674               if (i == 0 && vex.evex)
9675                 {
9676                   /* Don't print {%k0}.  */
9677                   if (vex.mask_register_specifier)
9678                     {
9679                       oappend ("{");
9680                       oappend (names_mask[vex.mask_register_specifier]);
9681                       oappend ("}");
9682                     }
9683                   if (vex.zeroing)
9684                     oappend ("{z}");
9685                 }
9686             }
9687         }
9688     }
9689
9690   /* Clear instruction information.  */
9691   if (the_info)
9692     {
9693       the_info->insn_info_valid = 0;
9694       the_info->branch_delay_insns = 0;
9695       the_info->data_size = 0;
9696       the_info->insn_type = dis_noninsn;
9697       the_info->target = 0;
9698       the_info->target2 = 0;
9699     }
9700
9701   /* Reset jump operation indicator.  */
9702   op_is_jump = FALSE;
9703
9704   {
9705     int jump_detection = 0;
9706
9707     /* Extract flags.  */
9708     for (i = 0; i < MAX_OPERANDS; ++i)
9709       {
9710         if ((dp->op[i].rtn == OP_J)
9711             || (dp->op[i].rtn == OP_indirE))
9712           jump_detection |= 1;
9713         else if ((dp->op[i].rtn == BND_Fixup)
9714                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9715           jump_detection |= 2;
9716         else if ((dp->op[i].bytemode == cond_jump_mode)
9717                  || (dp->op[i].bytemode == loop_jcxz_mode))
9718           jump_detection |= 4;
9719       }
9720
9721     /* Determine if this is a jump or branch.  */
9722     if ((jump_detection & 0x3) == 0x3)
9723       {
9724         op_is_jump = TRUE;
9725         if (jump_detection & 0x4)
9726           the_info->insn_type = dis_condbranch;
9727         else
9728           the_info->insn_type =
9729             (dp->name && !strncmp(dp->name, "call", 4))
9730             ? dis_jsr : dis_branch;
9731       }
9732   }
9733
9734   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9735      are all 0s in inverted form.  */
9736   if (need_vex && vex.register_specifier != 0)
9737     {
9738       (*info->fprintf_func) (info->stream, "(bad)");
9739       return end_codep - priv.the_buffer;
9740     }
9741
9742   /* If EVEX.z is set, there must be an actual mask register in use.  */
9743   if (vex.zeroing && vex.mask_register_specifier == 0)
9744     {
9745       (*info->fprintf_func) (info->stream, "(bad)");
9746       return end_codep - priv.the_buffer;
9747     }
9748
9749   switch (dp->prefix_requirement)
9750     {
9751     case PREFIX_DATA:
9752       /* If only the data prefix is marked as mandatory, its absence renders
9753          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9754       if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9755         {
9756           (*info->fprintf_func) (info->stream, "(bad)");
9757           return end_codep - priv.the_buffer;
9758         }
9759       used_prefixes |= PREFIX_DATA;
9760       /* Fall through.  */
9761     case PREFIX_OPCODE:
9762       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9763          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9764          used by putop and MMX/SSE operand and may be overridden by the
9765          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9766          separately.  */
9767       if (((need_vex
9768             ? vex.prefix == REPE_PREFIX_OPCODE
9769               || vex.prefix == REPNE_PREFIX_OPCODE
9770             : (prefixes
9771                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9772            && (used_prefixes
9773                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9774           || (((need_vex
9775                 ? vex.prefix == DATA_PREFIX_OPCODE
9776                 : ((prefixes
9777                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9778                    == PREFIX_DATA))
9779                && (used_prefixes & PREFIX_DATA) == 0))
9780           || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9781               && !vex.w != !(used_prefixes & PREFIX_DATA)))
9782         {
9783           (*info->fprintf_func) (info->stream, "(bad)");
9784           return end_codep - priv.the_buffer;
9785         }
9786       break;
9787
9788     case PREFIX_IGNORED:
9789       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9790          origins in all_prefixes.  */
9791       used_prefixes &= ~PREFIX_OPCODE;
9792       if (last_data_prefix >= 0)
9793         all_prefixes[last_data_prefix] = 0x66;
9794       if (last_repz_prefix >= 0)
9795         all_prefixes[last_repz_prefix] = 0xf3;
9796       if (last_repnz_prefix >= 0)
9797         all_prefixes[last_repnz_prefix] = 0xf2;
9798       break;
9799     }
9800
9801   /* Check if the REX prefix is used.  */
9802   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9803     all_prefixes[last_rex_prefix] = 0;
9804
9805   /* Check if the SEG prefix is used.  */
9806   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9807                    | PREFIX_FS | PREFIX_GS)) != 0
9808       && (used_prefixes & active_seg_prefix) != 0)
9809     all_prefixes[last_seg_prefix] = 0;
9810
9811   /* Check if the ADDR prefix is used.  */
9812   if ((prefixes & PREFIX_ADDR) != 0
9813       && (used_prefixes & PREFIX_ADDR) != 0)
9814     all_prefixes[last_addr_prefix] = 0;
9815
9816   /* Check if the DATA prefix is used.  */
9817   if ((prefixes & PREFIX_DATA) != 0
9818       && (used_prefixes & PREFIX_DATA) != 0
9819       && !need_vex)
9820     all_prefixes[last_data_prefix] = 0;
9821
9822   /* Print the extra prefixes.  */
9823   prefix_length = 0;
9824   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9825     if (all_prefixes[i])
9826       {
9827         const char *name;
9828         name = prefix_name (all_prefixes[i], orig_sizeflag);
9829         if (name == NULL)
9830           abort ();
9831         prefix_length += strlen (name) + 1;
9832         (*info->fprintf_func) (info->stream, "%s ", name);
9833       }
9834
9835   /* Check maximum code length.  */
9836   if ((codep - start_codep) > MAX_CODE_LENGTH)
9837     {
9838       (*info->fprintf_func) (info->stream, "(bad)");
9839       return MAX_CODE_LENGTH;
9840     }
9841
9842   obufp = mnemonicendp;
9843   for (i = strlen (obuf) + prefix_length; i < 6; i++)
9844     oappend (" ");
9845   oappend (" ");
9846   (*info->fprintf_func) (info->stream, "%s", obuf);
9847
9848   /* The enter and bound instructions are printed with operands in the same
9849      order as the intel book; everything else is printed in reverse order.  */
9850   if (intel_syntax || two_source_ops)
9851     {
9852       bfd_vma riprel;
9853
9854       for (i = 0; i < MAX_OPERANDS; ++i)
9855         op_txt[i] = op_out[i];
9856
9857       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9858           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9859         {
9860           op_txt[2] = op_out[3];
9861           op_txt[3] = op_out[2];
9862         }
9863
9864       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9865         {
9866           op_ad = op_index[i];
9867           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9868           op_index[MAX_OPERANDS - 1 - i] = op_ad;
9869           riprel = op_riprel[i];
9870           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9871           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9872         }
9873     }
9874   else
9875     {
9876       for (i = 0; i < MAX_OPERANDS; ++i)
9877         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9878     }
9879
9880   needcomma = 0;
9881   for (i = 0; i < MAX_OPERANDS; ++i)
9882     if (*op_txt[i])
9883       {
9884         if (needcomma)
9885           (*info->fprintf_func) (info->stream, ",");
9886         if (op_index[i] != -1 && !op_riprel[i])
9887           {
9888             bfd_vma target = (bfd_vma) op_address[op_index[i]];
9889
9890             if (the_info && op_is_jump)
9891               {
9892                 the_info->insn_info_valid = 1;
9893                 the_info->branch_delay_insns = 0;
9894                 the_info->data_size = 0;
9895                 the_info->target = target;
9896                 the_info->target2 = 0;
9897               }
9898             (*info->print_address_func) (target, info);
9899           }
9900         else
9901           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9902         needcomma = 1;
9903       }
9904
9905   for (i = 0; i < MAX_OPERANDS; i++)
9906     if (op_index[i] != -1 && op_riprel[i])
9907       {
9908         (*info->fprintf_func) (info->stream, "        # ");
9909         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
9910                                                 + op_address[op_index[i]]), info);
9911         break;
9912       }
9913   return codep - priv.the_buffer;
9914 }
9915
9916 static const char *float_mem[] = {
9917   /* d8 */
9918   "fadd{s|}",
9919   "fmul{s|}",
9920   "fcom{s|}",
9921   "fcomp{s|}",
9922   "fsub{s|}",
9923   "fsubr{s|}",
9924   "fdiv{s|}",
9925   "fdivr{s|}",
9926   /* d9 */
9927   "fld{s|}",
9928   "(bad)",
9929   "fst{s|}",
9930   "fstp{s|}",
9931   "fldenv{C|C}",
9932   "fldcw",
9933   "fNstenv{C|C}",
9934   "fNstcw",
9935   /* da */
9936   "fiadd{l|}",
9937   "fimul{l|}",
9938   "ficom{l|}",
9939   "ficomp{l|}",
9940   "fisub{l|}",
9941   "fisubr{l|}",
9942   "fidiv{l|}",
9943   "fidivr{l|}",
9944   /* db */
9945   "fild{l|}",
9946   "fisttp{l|}",
9947   "fist{l|}",
9948   "fistp{l|}",
9949   "(bad)",
9950   "fld{t|}",
9951   "(bad)",
9952   "fstp{t|}",
9953   /* dc */
9954   "fadd{l|}",
9955   "fmul{l|}",
9956   "fcom{l|}",
9957   "fcomp{l|}",
9958   "fsub{l|}",
9959   "fsubr{l|}",
9960   "fdiv{l|}",
9961   "fdivr{l|}",
9962   /* dd */
9963   "fld{l|}",
9964   "fisttp{ll|}",
9965   "fst{l||}",
9966   "fstp{l|}",
9967   "frstor{C|C}",
9968   "(bad)",
9969   "fNsave{C|C}",
9970   "fNstsw",
9971   /* de */
9972   "fiadd{s|}",
9973   "fimul{s|}",
9974   "ficom{s|}",
9975   "ficomp{s|}",
9976   "fisub{s|}",
9977   "fisubr{s|}",
9978   "fidiv{s|}",
9979   "fidivr{s|}",
9980   /* df */
9981   "fild{s|}",
9982   "fisttp{s|}",
9983   "fist{s|}",
9984   "fistp{s|}",
9985   "fbld",
9986   "fild{ll|}",
9987   "fbstp",
9988   "fistp{ll|}",
9989 };
9990
9991 static const unsigned char float_mem_mode[] = {
9992   /* d8 */
9993   d_mode,
9994   d_mode,
9995   d_mode,
9996   d_mode,
9997   d_mode,
9998   d_mode,
9999   d_mode,
10000   d_mode,
10001   /* d9 */
10002   d_mode,
10003   0,
10004   d_mode,
10005   d_mode,
10006   0,
10007   w_mode,
10008   0,
10009   w_mode,
10010   /* da */
10011   d_mode,
10012   d_mode,
10013   d_mode,
10014   d_mode,
10015   d_mode,
10016   d_mode,
10017   d_mode,
10018   d_mode,
10019   /* db */
10020   d_mode,
10021   d_mode,
10022   d_mode,
10023   d_mode,
10024   0,
10025   t_mode,
10026   0,
10027   t_mode,
10028   /* dc */
10029   q_mode,
10030   q_mode,
10031   q_mode,
10032   q_mode,
10033   q_mode,
10034   q_mode,
10035   q_mode,
10036   q_mode,
10037   /* dd */
10038   q_mode,
10039   q_mode,
10040   q_mode,
10041   q_mode,
10042   0,
10043   0,
10044   0,
10045   w_mode,
10046   /* de */
10047   w_mode,
10048   w_mode,
10049   w_mode,
10050   w_mode,
10051   w_mode,
10052   w_mode,
10053   w_mode,
10054   w_mode,
10055   /* df */
10056   w_mode,
10057   w_mode,
10058   w_mode,
10059   w_mode,
10060   t_mode,
10061   q_mode,
10062   t_mode,
10063   q_mode
10064 };
10065
10066 #define ST { OP_ST, 0 }
10067 #define STi { OP_STi, 0 }
10068
10069 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10070 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10071 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10072 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10073 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10074 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10075 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10076 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10077 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10078
10079 static const struct dis386 float_reg[][8] = {
10080   /* d8 */
10081   {
10082     { "fadd",   { ST, STi }, 0 },
10083     { "fmul",   { ST, STi }, 0 },
10084     { "fcom",   { STi }, 0 },
10085     { "fcomp",  { STi }, 0 },
10086     { "fsub",   { ST, STi }, 0 },
10087     { "fsubr",  { ST, STi }, 0 },
10088     { "fdiv",   { ST, STi }, 0 },
10089     { "fdivr",  { ST, STi }, 0 },
10090   },
10091   /* d9 */
10092   {
10093     { "fld",    { STi }, 0 },
10094     { "fxch",   { STi }, 0 },
10095     { FGRPd9_2 },
10096     { Bad_Opcode },
10097     { FGRPd9_4 },
10098     { FGRPd9_5 },
10099     { FGRPd9_6 },
10100     { FGRPd9_7 },
10101   },
10102   /* da */
10103   {
10104     { "fcmovb", { ST, STi }, 0 },
10105     { "fcmove", { ST, STi }, 0 },
10106     { "fcmovbe",{ ST, STi }, 0 },
10107     { "fcmovu", { ST, STi }, 0 },
10108     { Bad_Opcode },
10109     { FGRPda_5 },
10110     { Bad_Opcode },
10111     { Bad_Opcode },
10112   },
10113   /* db */
10114   {
10115     { "fcmovnb",{ ST, STi }, 0 },
10116     { "fcmovne",{ ST, STi }, 0 },
10117     { "fcmovnbe",{ ST, STi }, 0 },
10118     { "fcmovnu",{ ST, STi }, 0 },
10119     { FGRPdb_4 },
10120     { "fucomi", { ST, STi }, 0 },
10121     { "fcomi",  { ST, STi }, 0 },
10122     { Bad_Opcode },
10123   },
10124   /* dc */
10125   {
10126     { "fadd",   { STi, ST }, 0 },
10127     { "fmul",   { STi, ST }, 0 },
10128     { Bad_Opcode },
10129     { Bad_Opcode },
10130     { "fsub{!M|r}",     { STi, ST }, 0 },
10131     { "fsub{M|}",       { STi, ST }, 0 },
10132     { "fdiv{!M|r}",     { STi, ST }, 0 },
10133     { "fdiv{M|}",       { STi, ST }, 0 },
10134   },
10135   /* dd */
10136   {
10137     { "ffree",  { STi }, 0 },
10138     { Bad_Opcode },
10139     { "fst",    { STi }, 0 },
10140     { "fstp",   { STi }, 0 },
10141     { "fucom",  { STi }, 0 },
10142     { "fucomp", { STi }, 0 },
10143     { Bad_Opcode },
10144     { Bad_Opcode },
10145   },
10146   /* de */
10147   {
10148     { "faddp",  { STi, ST }, 0 },
10149     { "fmulp",  { STi, ST }, 0 },
10150     { Bad_Opcode },
10151     { FGRPde_3 },
10152     { "fsub{!M|r}p",    { STi, ST }, 0 },
10153     { "fsub{M|}p",      { STi, ST }, 0 },
10154     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10155     { "fdiv{M|}p",      { STi, ST }, 0 },
10156   },
10157   /* df */
10158   {
10159     { "ffreep", { STi }, 0 },
10160     { Bad_Opcode },
10161     { Bad_Opcode },
10162     { Bad_Opcode },
10163     { FGRPdf_4 },
10164     { "fucomip", { ST, STi }, 0 },
10165     { "fcomip", { ST, STi }, 0 },
10166     { Bad_Opcode },
10167   },
10168 };
10169
10170 static char *fgrps[][8] = {
10171   /* Bad opcode 0 */
10172   {
10173     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10174   },
10175
10176   /* d9_2  1 */
10177   {
10178     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10179   },
10180
10181   /* d9_4  2 */
10182   {
10183     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10184   },
10185
10186   /* d9_5  3 */
10187   {
10188     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10189   },
10190
10191   /* d9_6  4 */
10192   {
10193     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10194   },
10195
10196   /* d9_7  5 */
10197   {
10198     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10199   },
10200
10201   /* da_5  6 */
10202   {
10203     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10204   },
10205
10206   /* db_4  7 */
10207   {
10208     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10209     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10210   },
10211
10212   /* de_3  8 */
10213   {
10214     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10215   },
10216
10217   /* df_4  9 */
10218   {
10219     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10220   },
10221 };
10222
10223 static void
10224 swap_operand (void)
10225 {
10226   mnemonicendp[0] = '.';
10227   mnemonicendp[1] = 's';
10228   mnemonicendp += 2;
10229 }
10230
10231 static void
10232 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10233                int sizeflag ATTRIBUTE_UNUSED)
10234 {
10235   /* Skip mod/rm byte.  */
10236   MODRM_CHECK;
10237   codep++;
10238 }
10239
10240 static void
10241 dofloat (int sizeflag)
10242 {
10243   const struct dis386 *dp;
10244   unsigned char floatop;
10245
10246   floatop = codep[-1];
10247
10248   if (modrm.mod != 3)
10249     {
10250       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10251
10252       putop (float_mem[fp_indx], sizeflag);
10253       obufp = op_out[0];
10254       op_ad = 2;
10255       OP_E (float_mem_mode[fp_indx], sizeflag);
10256       return;
10257     }
10258   /* Skip mod/rm byte.  */
10259   MODRM_CHECK;
10260   codep++;
10261
10262   dp = &float_reg[floatop - 0xd8][modrm.reg];
10263   if (dp->name == NULL)
10264     {
10265       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10266
10267       /* Instruction fnstsw is only one with strange arg.  */
10268       if (floatop == 0xdf && codep[-1] == 0xe0)
10269         strcpy (op_out[0], names16[0]);
10270     }
10271   else
10272     {
10273       putop (dp->name, sizeflag);
10274
10275       obufp = op_out[0];
10276       op_ad = 2;
10277       if (dp->op[0].rtn)
10278         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10279
10280       obufp = op_out[1];
10281       op_ad = 1;
10282       if (dp->op[1].rtn)
10283         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10284     }
10285 }
10286
10287 /* Like oappend (below), but S is a string starting with '%'.
10288    In Intel syntax, the '%' is elided.  */
10289 static void
10290 oappend_maybe_intel (const char *s)
10291 {
10292   oappend (s + intel_syntax);
10293 }
10294
10295 static void
10296 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10297 {
10298   oappend_maybe_intel ("%st");
10299 }
10300
10301 static void
10302 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10303 {
10304   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10305   oappend_maybe_intel (scratchbuf);
10306 }
10307
10308 /* Capital letters in template are macros.  */
10309 static int
10310 putop (const char *in_template, int sizeflag)
10311 {
10312   const char *p;
10313   int alt = 0;
10314   int cond = 1;
10315   unsigned int l = 0, len = 0;
10316   char last[4];
10317
10318   for (p = in_template; *p; p++)
10319     {
10320       if (len > l)
10321         {
10322           if (l >= sizeof (last) || !ISUPPER (*p))
10323             abort ();
10324           last[l++] = *p;
10325           continue;
10326         }
10327       switch (*p)
10328         {
10329         default:
10330           *obufp++ = *p;
10331           break;
10332         case '%':
10333           len++;
10334           break;
10335         case '!':
10336           cond = 0;
10337           break;
10338         case '{':
10339           if (intel_syntax)
10340             {
10341               while (*++p != '|')
10342                 if (*p == '}' || *p == '\0')
10343                   abort ();
10344               alt = 1;
10345             }
10346           break;
10347         case '|':
10348           while (*++p != '}')
10349             {
10350               if (*p == '\0')
10351                 abort ();
10352             }
10353           break;
10354         case '}':
10355           alt = 0;
10356           break;
10357         case 'A':
10358           if (intel_syntax)
10359             break;
10360           if ((need_modrm && modrm.mod != 3)
10361               || (sizeflag & SUFFIX_ALWAYS))
10362             *obufp++ = 'b';
10363           break;
10364         case 'B':
10365           if (l == 0)
10366             {
10367             case_B:
10368               if (intel_syntax)
10369                 break;
10370               if (sizeflag & SUFFIX_ALWAYS)
10371                 *obufp++ = 'b';
10372             }
10373           else if (l == 1 && last[0] == 'L')
10374             {
10375               if (address_mode == mode_64bit
10376                   && !(prefixes & PREFIX_ADDR))
10377                 {
10378                   *obufp++ = 'a';
10379                   *obufp++ = 'b';
10380                   *obufp++ = 's';
10381                 }
10382
10383               goto case_B;
10384             }
10385           else
10386             abort ();
10387           break;
10388         case 'C':
10389           if (intel_syntax && !alt)
10390             break;
10391           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10392             {
10393               if (sizeflag & DFLAG)
10394                 *obufp++ = intel_syntax ? 'd' : 'l';
10395               else
10396                 *obufp++ = intel_syntax ? 'w' : 's';
10397               used_prefixes |= (prefixes & PREFIX_DATA);
10398             }
10399           break;
10400         case 'D':
10401           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10402             break;
10403           USED_REX (REX_W);
10404           if (modrm.mod == 3)
10405             {
10406               if (rex & REX_W)
10407                 *obufp++ = 'q';
10408               else
10409                 {
10410                   if (sizeflag & DFLAG)
10411                     *obufp++ = intel_syntax ? 'd' : 'l';
10412                   else
10413                     *obufp++ = 'w';
10414                   used_prefixes |= (prefixes & PREFIX_DATA);
10415                 }
10416             }
10417           else
10418             *obufp++ = 'w';
10419           break;
10420         case 'E':               /* For jcxz/jecxz */
10421           if (address_mode == mode_64bit)
10422             {
10423               if (sizeflag & AFLAG)
10424                 *obufp++ = 'r';
10425               else
10426                 *obufp++ = 'e';
10427             }
10428           else
10429             if (sizeflag & AFLAG)
10430               *obufp++ = 'e';
10431           used_prefixes |= (prefixes & PREFIX_ADDR);
10432           break;
10433         case 'F':
10434           if (intel_syntax)
10435             break;
10436           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10437             {
10438               if (sizeflag & AFLAG)
10439                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10440               else
10441                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10442               used_prefixes |= (prefixes & PREFIX_ADDR);
10443             }
10444           break;
10445         case 'G':
10446           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10447             break;
10448           if ((rex & REX_W) || (sizeflag & DFLAG))
10449             *obufp++ = 'l';
10450           else
10451             *obufp++ = 'w';
10452           if (!(rex & REX_W))
10453             used_prefixes |= (prefixes & PREFIX_DATA);
10454           break;
10455         case 'H':
10456           if (intel_syntax)
10457             break;
10458           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10459               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10460             {
10461               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10462               *obufp++ = ',';
10463               *obufp++ = 'p';
10464
10465               /* Set active_seg_prefix even if not set in 64-bit mode
10466                  because here it is a valid branch hint. */
10467               if (prefixes & PREFIX_DS)
10468                 {
10469                   active_seg_prefix = PREFIX_DS;
10470                   *obufp++ = 't';
10471                 }
10472               else
10473                 {
10474                   active_seg_prefix = PREFIX_CS;
10475                   *obufp++ = 'n';
10476                 }
10477             }
10478           break;
10479         case 'K':
10480           USED_REX (REX_W);
10481           if (rex & REX_W)
10482             *obufp++ = 'q';
10483           else
10484             *obufp++ = 'd';
10485           break;
10486         case 'L':
10487           abort ();
10488         case 'M':
10489           if (intel_mnemonic != cond)
10490             *obufp++ = 'r';
10491           break;
10492         case 'N':
10493           if ((prefixes & PREFIX_FWAIT) == 0)
10494             *obufp++ = 'n';
10495           else
10496             used_prefixes |= PREFIX_FWAIT;
10497           break;
10498         case 'O':
10499           USED_REX (REX_W);
10500           if (rex & REX_W)
10501             *obufp++ = 'o';
10502           else if (intel_syntax && (sizeflag & DFLAG))
10503             *obufp++ = 'q';
10504           else
10505             *obufp++ = 'd';
10506           if (!(rex & REX_W))
10507             used_prefixes |= (prefixes & PREFIX_DATA);
10508           break;
10509         case '@':
10510           if (address_mode == mode_64bit
10511               && (isa64 == intel64 || (rex & REX_W)
10512                   || !(prefixes & PREFIX_DATA)))
10513             {
10514               if (sizeflag & SUFFIX_ALWAYS)
10515                 *obufp++ = 'q';
10516               break;
10517             }
10518           /* Fall through.  */
10519         case 'P':
10520           if (l == 0)
10521             {
10522               if ((modrm.mod == 3 || !cond)
10523                   && !(sizeflag & SUFFIX_ALWAYS))
10524                 break;
10525           /* Fall through.  */
10526         case 'T':
10527               if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10528                   || ((sizeflag & SUFFIX_ALWAYS)
10529                       && address_mode != mode_64bit))
10530                 {
10531                   *obufp++ = (sizeflag & DFLAG) ?
10532                              intel_syntax ? 'd' : 'l' : 'w';
10533                   used_prefixes |= (prefixes & PREFIX_DATA);
10534                 }
10535               else if (sizeflag & SUFFIX_ALWAYS)
10536                 *obufp++ = 'q';
10537             }
10538           else if (l == 1 && last[0] == 'L')
10539             {
10540               if ((prefixes & PREFIX_DATA)
10541                   || (rex & REX_W)
10542                   || (sizeflag & SUFFIX_ALWAYS))
10543                 {
10544                   USED_REX (REX_W);
10545                   if (rex & REX_W)
10546                     *obufp++ = 'q';
10547                   else
10548                     {
10549                       if (sizeflag & DFLAG)
10550                         *obufp++ = intel_syntax ? 'd' : 'l';
10551                       else
10552                         *obufp++ = 'w';
10553                       used_prefixes |= (prefixes & PREFIX_DATA);
10554                     }
10555                 }
10556             }
10557           else
10558             abort ();
10559           break;
10560         case 'Q':
10561           if (l == 0)
10562             {
10563               if (intel_syntax && !alt)
10564                 break;
10565               USED_REX (REX_W);
10566               if ((need_modrm && modrm.mod != 3)
10567                   || (sizeflag & SUFFIX_ALWAYS))
10568                 {
10569                   if (rex & REX_W)
10570                     *obufp++ = 'q';
10571                   else
10572                     {
10573                       if (sizeflag & DFLAG)
10574                         *obufp++ = intel_syntax ? 'd' : 'l';
10575                       else
10576                         *obufp++ = 'w';
10577                       used_prefixes |= (prefixes & PREFIX_DATA);
10578                     }
10579                 }
10580             }
10581           else if (l == 1 && last[0] == 'D')
10582             *obufp++ = vex.w ? 'q' : 'd';
10583           else if (l == 1 && last[0] == 'L')
10584             {
10585               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10586                        : address_mode != mode_64bit)
10587                 break;
10588               if ((rex & REX_W))
10589                 {
10590                   USED_REX (REX_W);
10591                   *obufp++ = 'q';
10592                 }
10593               else if((address_mode == mode_64bit && cond)
10594                       || (sizeflag & SUFFIX_ALWAYS))
10595                 *obufp++ = intel_syntax? 'd' : 'l';
10596             }
10597           else
10598             abort ();
10599           break;
10600         case 'R':
10601           USED_REX (REX_W);
10602           if (rex & REX_W)
10603             *obufp++ = 'q';
10604           else if (sizeflag & DFLAG)
10605             {
10606               if (intel_syntax)
10607                   *obufp++ = 'd';
10608               else
10609                   *obufp++ = 'l';
10610             }
10611           else
10612             *obufp++ = 'w';
10613           if (intel_syntax && !p[1]
10614               && ((rex & REX_W) || (sizeflag & DFLAG)))
10615             *obufp++ = 'e';
10616           if (!(rex & REX_W))
10617             used_prefixes |= (prefixes & PREFIX_DATA);
10618           break;
10619         case 'S':
10620           if (l == 0)
10621             {
10622             case_S:
10623               if (intel_syntax)
10624                 break;
10625               if (sizeflag & SUFFIX_ALWAYS)
10626                 {
10627                   if (rex & REX_W)
10628                     *obufp++ = 'q';
10629                   else
10630                     {
10631                       if (sizeflag & DFLAG)
10632                         *obufp++ = 'l';
10633                       else
10634                         *obufp++ = 'w';
10635                       used_prefixes |= (prefixes & PREFIX_DATA);
10636                     }
10637                 }
10638             }
10639           else if (l == 1 && last[0] == 'L')
10640             {
10641               if (address_mode == mode_64bit
10642                   && !(prefixes & PREFIX_ADDR))
10643                 {
10644                   *obufp++ = 'a';
10645                   *obufp++ = 'b';
10646                   *obufp++ = 's';
10647                 }
10648
10649               goto case_S;
10650             }
10651           else
10652             abort ();
10653           break;
10654         case 'V':
10655           if (l == 0)
10656             abort ();
10657           else if (l == 1
10658                    && (last[0] == 'L' || last[0] == 'X'))
10659             {
10660               if (last[0] == 'X')
10661                 {
10662                   *obufp++ = '{';
10663                   *obufp++ = 'v';
10664                   *obufp++ = 'e';
10665                   *obufp++ = 'x';
10666                   *obufp++ = '}';
10667                 }
10668               else if (rex & REX_W)
10669                 {
10670                   *obufp++ = 'a';
10671                   *obufp++ = 'b';
10672                   *obufp++ = 's';
10673                 }
10674             }
10675           else
10676             abort ();
10677           goto case_S;
10678         case 'W':
10679           if (l == 0)
10680             {
10681               /* operand size flag for cwtl, cbtw */
10682               USED_REX (REX_W);
10683               if (rex & REX_W)
10684                 {
10685                   if (intel_syntax)
10686                     *obufp++ = 'd';
10687                   else
10688                     *obufp++ = 'l';
10689                 }
10690               else if (sizeflag & DFLAG)
10691                 *obufp++ = 'w';
10692               else
10693                 *obufp++ = 'b';
10694               if (!(rex & REX_W))
10695                 used_prefixes |= (prefixes & PREFIX_DATA);
10696             }
10697           else if (l == 1)
10698             {
10699               if (!need_vex)
10700                 abort ();
10701               if (last[0] == 'X')
10702                 *obufp++ = vex.w ? 'd': 's';
10703               else if (last[0] == 'B')
10704                 *obufp++ = vex.w ? 'w': 'b';
10705               else
10706                 abort ();
10707             }
10708           else
10709             abort ();
10710           break;
10711         case 'X':
10712           if (l != 0)
10713             abort ();
10714           if (need_vex
10715               ? vex.prefix == DATA_PREFIX_OPCODE
10716               : prefixes & PREFIX_DATA)
10717             {
10718               *obufp++ = 'd';
10719               used_prefixes |= PREFIX_DATA;
10720             }
10721           else
10722             *obufp++ = 's';
10723           break;
10724         case 'Y':
10725           if (l == 1 && last[0] == 'X')
10726             {
10727               if (!need_vex)
10728                 abort ();
10729               if (intel_syntax
10730                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10731                 break;
10732               switch (vex.length)
10733                 {
10734                 case 128:
10735                   *obufp++ = 'x';
10736                   break;
10737                 case 256:
10738                   *obufp++ = 'y';
10739                   break;
10740                 case 512:
10741                   if (!vex.evex)
10742                 default:
10743                     abort ();
10744                 }
10745             }
10746           else
10747             abort ();
10748           break;
10749         case 'Z':
10750           if (l == 0)
10751             {
10752               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10753               modrm.mod = 3;
10754               if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10755                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10756             }
10757           else if (l == 1 && last[0] == 'X')
10758             {
10759               if (!vex.evex)
10760                 abort ();
10761               if (intel_syntax
10762                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10763                 break;
10764               switch (vex.length)
10765                 {
10766                 case 128:
10767                   *obufp++ = 'x';
10768                   break;
10769                 case 256:
10770                   *obufp++ = 'y';
10771                   break;
10772                 case 512:
10773                   *obufp++ = 'z';
10774                   break;
10775                 default:
10776                   abort ();
10777                 }
10778             }
10779           else
10780             abort ();
10781           break;
10782         case '^':
10783           if (intel_syntax)
10784             break;
10785           if (isa64 == intel64 && (rex & REX_W))
10786             {
10787               USED_REX (REX_W);
10788               *obufp++ = 'q';
10789               break;
10790             }
10791           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10792             {
10793               if (sizeflag & DFLAG)
10794                 *obufp++ = 'l';
10795               else
10796                 *obufp++ = 'w';
10797               used_prefixes |= (prefixes & PREFIX_DATA);
10798             }
10799           break;
10800         }
10801
10802       if (len == l)
10803         len = l = 0;
10804     }
10805   *obufp = 0;
10806   mnemonicendp = obufp;
10807   return 0;
10808 }
10809
10810 static void
10811 oappend (const char *s)
10812 {
10813   obufp = stpcpy (obufp, s);
10814 }
10815
10816 static void
10817 append_seg (void)
10818 {
10819   /* Only print the active segment register.  */
10820   if (!active_seg_prefix)
10821     return;
10822
10823   used_prefixes |= active_seg_prefix;
10824   switch (active_seg_prefix)
10825     {
10826     case PREFIX_CS:
10827       oappend_maybe_intel ("%cs:");
10828       break;
10829     case PREFIX_DS:
10830       oappend_maybe_intel ("%ds:");
10831       break;
10832     case PREFIX_SS:
10833       oappend_maybe_intel ("%ss:");
10834       break;
10835     case PREFIX_ES:
10836       oappend_maybe_intel ("%es:");
10837       break;
10838     case PREFIX_FS:
10839       oappend_maybe_intel ("%fs:");
10840       break;
10841     case PREFIX_GS:
10842       oappend_maybe_intel ("%gs:");
10843       break;
10844     default:
10845       break;
10846     }
10847 }
10848
10849 static void
10850 OP_indirE (int bytemode, int sizeflag)
10851 {
10852   if (!intel_syntax)
10853     oappend ("*");
10854   OP_E (bytemode, sizeflag);
10855 }
10856
10857 static void
10858 print_operand_value (char *buf, int hex, bfd_vma disp)
10859 {
10860   if (address_mode == mode_64bit)
10861     {
10862       if (hex)
10863         {
10864           char tmp[30];
10865           int i;
10866           buf[0] = '0';
10867           buf[1] = 'x';
10868           sprintf_vma (tmp, disp);
10869           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10870           strcpy (buf + 2, tmp + i);
10871         }
10872       else
10873         {
10874           bfd_signed_vma v = disp;
10875           char tmp[30];
10876           int i;
10877           if (v < 0)
10878             {
10879               *(buf++) = '-';
10880               v = -disp;
10881               /* Check for possible overflow on 0x8000000000000000.  */
10882               if (v < 0)
10883                 {
10884                   strcpy (buf, "9223372036854775808");
10885                   return;
10886                 }
10887             }
10888           if (!v)
10889             {
10890               strcpy (buf, "0");
10891               return;
10892             }
10893
10894           i = 0;
10895           tmp[29] = 0;
10896           while (v)
10897             {
10898               tmp[28 - i] = (v % 10) + '0';
10899               v /= 10;
10900               i++;
10901             }
10902           strcpy (buf, tmp + 29 - i);
10903         }
10904     }
10905   else
10906     {
10907       if (hex)
10908         sprintf (buf, "0x%x", (unsigned int) disp);
10909       else
10910         sprintf (buf, "%d", (int) disp);
10911     }
10912 }
10913
10914 /* Put DISP in BUF as signed hex number.  */
10915
10916 static void
10917 print_displacement (char *buf, bfd_vma disp)
10918 {
10919   bfd_signed_vma val = disp;
10920   char tmp[30];
10921   int i, j = 0;
10922
10923   if (val < 0)
10924     {
10925       buf[j++] = '-';
10926       val = -disp;
10927
10928       /* Check for possible overflow.  */
10929       if (val < 0)
10930         {
10931           switch (address_mode)
10932             {
10933             case mode_64bit:
10934               strcpy (buf + j, "0x8000000000000000");
10935               break;
10936             case mode_32bit:
10937               strcpy (buf + j, "0x80000000");
10938               break;
10939             case mode_16bit:
10940               strcpy (buf + j, "0x8000");
10941               break;
10942             }
10943           return;
10944         }
10945     }
10946
10947   buf[j++] = '0';
10948   buf[j++] = 'x';
10949
10950   sprintf_vma (tmp, (bfd_vma) val);
10951   for (i = 0; tmp[i] == '0'; i++)
10952     continue;
10953   if (tmp[i] == '\0')
10954     i--;
10955   strcpy (buf + j, tmp + i);
10956 }
10957
10958 static void
10959 intel_operand_size (int bytemode, int sizeflag)
10960 {
10961   if (vex.b
10962       && (bytemode == x_mode
10963           || bytemode == evex_half_bcst_xmmq_mode))
10964     {
10965       if (vex.w)
10966         oappend ("QWORD PTR ");
10967       else
10968         oappend ("DWORD PTR ");
10969       return;
10970     }
10971   switch (bytemode)
10972     {
10973     case b_mode:
10974     case b_swap_mode:
10975     case dqb_mode:
10976     case db_mode:
10977       oappend ("BYTE PTR ");
10978       break;
10979     case w_mode:
10980     case dw_mode:
10981     case dqw_mode:
10982       oappend ("WORD PTR ");
10983       break;
10984     case indir_v_mode:
10985       if (address_mode == mode_64bit && isa64 == intel64)
10986         {
10987           oappend ("QWORD PTR ");
10988           break;
10989         }
10990       /* Fall through.  */
10991     case stack_v_mode:
10992       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
10993         {
10994           oappend ("QWORD PTR ");
10995           break;
10996         }
10997       /* Fall through.  */
10998     case v_mode:
10999     case v_swap_mode:
11000     case dq_mode:
11001       USED_REX (REX_W);
11002       if (rex & REX_W)
11003         oappend ("QWORD PTR ");
11004       else if (bytemode == dq_mode)
11005         oappend ("DWORD PTR ");
11006       else
11007         {
11008           if (sizeflag & DFLAG)
11009             oappend ("DWORD PTR ");
11010           else
11011             oappend ("WORD PTR ");
11012           used_prefixes |= (prefixes & PREFIX_DATA);
11013         }
11014       break;
11015     case z_mode:
11016       if ((rex & REX_W) || (sizeflag & DFLAG))
11017         *obufp++ = 'D';
11018       oappend ("WORD PTR ");
11019       if (!(rex & REX_W))
11020         used_prefixes |= (prefixes & PREFIX_DATA);
11021       break;
11022     case a_mode:
11023       if (sizeflag & DFLAG)
11024         oappend ("QWORD PTR ");
11025       else
11026         oappend ("DWORD PTR ");
11027       used_prefixes |= (prefixes & PREFIX_DATA);
11028       break;
11029     case movsxd_mode:
11030       if (!(sizeflag & DFLAG) && isa64 == intel64)
11031         oappend ("WORD PTR ");
11032       else
11033         oappend ("DWORD PTR ");
11034       used_prefixes |= (prefixes & PREFIX_DATA);
11035       break;
11036     case d_mode:
11037     case d_swap_mode:
11038     case dqd_mode:
11039       oappend ("DWORD PTR ");
11040       break;
11041     case q_mode:
11042     case q_swap_mode:
11043       oappend ("QWORD PTR ");
11044       break;
11045     case m_mode:
11046       if (address_mode == mode_64bit)
11047         oappend ("QWORD PTR ");
11048       else
11049         oappend ("DWORD PTR ");
11050       break;
11051     case f_mode:
11052       if (sizeflag & DFLAG)
11053         oappend ("FWORD PTR ");
11054       else
11055         oappend ("DWORD PTR ");
11056       used_prefixes |= (prefixes & PREFIX_DATA);
11057       break;
11058     case t_mode:
11059       oappend ("TBYTE PTR ");
11060       break;
11061     case x_mode:
11062     case x_swap_mode:
11063     case evex_x_gscat_mode:
11064     case evex_x_nobcst_mode:
11065     case bw_unit_mode:
11066       if (need_vex)
11067         {
11068           switch (vex.length)
11069             {
11070             case 128:
11071               oappend ("XMMWORD PTR ");
11072               break;
11073             case 256:
11074               oappend ("YMMWORD PTR ");
11075               break;
11076             case 512:
11077               oappend ("ZMMWORD PTR ");
11078               break;
11079             default:
11080               abort ();
11081             }
11082         }
11083       else
11084         oappend ("XMMWORD PTR ");
11085       break;
11086     case xmm_mode:
11087       oappend ("XMMWORD PTR ");
11088       break;
11089     case ymm_mode:
11090       oappend ("YMMWORD PTR ");
11091       break;
11092     case xmmq_mode:
11093     case evex_half_bcst_xmmq_mode:
11094       if (!need_vex)
11095         abort ();
11096
11097       switch (vex.length)
11098         {
11099         case 128:
11100           oappend ("QWORD PTR ");
11101           break;
11102         case 256:
11103           oappend ("XMMWORD PTR ");
11104           break;
11105         case 512:
11106           oappend ("YMMWORD PTR ");
11107           break;
11108         default:
11109           abort ();
11110         }
11111       break;
11112     case xmm_mb_mode:
11113       if (!need_vex)
11114         abort ();
11115
11116       switch (vex.length)
11117         {
11118         case 128:
11119         case 256:
11120         case 512:
11121           oappend ("BYTE PTR ");
11122           break;
11123         default:
11124           abort ();
11125         }
11126       break;
11127     case xmm_mw_mode:
11128       if (!need_vex)
11129         abort ();
11130
11131       switch (vex.length)
11132         {
11133         case 128:
11134         case 256:
11135         case 512:
11136           oappend ("WORD PTR ");
11137           break;
11138         default:
11139           abort ();
11140         }
11141       break;
11142     case xmm_md_mode:
11143       if (!need_vex)
11144         abort ();
11145
11146       switch (vex.length)
11147         {
11148         case 128:
11149         case 256:
11150         case 512:
11151           oappend ("DWORD PTR ");
11152           break;
11153         default:
11154           abort ();
11155         }
11156       break;
11157     case xmm_mq_mode:
11158       if (!need_vex)
11159         abort ();
11160
11161       switch (vex.length)
11162         {
11163         case 128:
11164         case 256:
11165         case 512:
11166           oappend ("QWORD PTR ");
11167           break;
11168         default:
11169           abort ();
11170         }
11171       break;
11172     case xmmdw_mode:
11173       if (!need_vex)
11174         abort ();
11175
11176       switch (vex.length)
11177         {
11178         case 128:
11179           oappend ("WORD PTR ");
11180           break;
11181         case 256:
11182           oappend ("DWORD PTR ");
11183           break;
11184         case 512:
11185           oappend ("QWORD PTR ");
11186           break;
11187         default:
11188           abort ();
11189         }
11190       break;
11191     case xmmqd_mode:
11192       if (!need_vex)
11193         abort ();
11194
11195       switch (vex.length)
11196         {
11197         case 128:
11198           oappend ("DWORD PTR ");
11199           break;
11200         case 256:
11201           oappend ("QWORD PTR ");
11202           break;
11203         case 512:
11204           oappend ("XMMWORD PTR ");
11205           break;
11206         default:
11207           abort ();
11208         }
11209       break;
11210     case ymmq_mode:
11211       if (!need_vex)
11212         abort ();
11213
11214       switch (vex.length)
11215         {
11216         case 128:
11217           oappend ("QWORD PTR ");
11218           break;
11219         case 256:
11220           oappend ("YMMWORD PTR ");
11221           break;
11222         case 512:
11223           oappend ("ZMMWORD PTR ");
11224           break;
11225         default:
11226           abort ();
11227         }
11228       break;
11229     case ymmxmm_mode:
11230       if (!need_vex)
11231         abort ();
11232
11233       switch (vex.length)
11234         {
11235         case 128:
11236         case 256:
11237           oappend ("XMMWORD PTR ");
11238           break;
11239         default:
11240           abort ();
11241         }
11242       break;
11243     case o_mode:
11244       oappend ("OWORD PTR ");
11245       break;
11246     case vex_scalar_w_dq_mode:
11247       if (!need_vex)
11248         abort ();
11249
11250       if (vex.w)
11251         oappend ("QWORD PTR ");
11252       else
11253         oappend ("DWORD PTR ");
11254       break;
11255     case vex_vsib_d_w_dq_mode:
11256     case vex_vsib_q_w_dq_mode:
11257       if (!need_vex)
11258         abort ();
11259
11260       if (vex.w)
11261         oappend ("QWORD PTR ");
11262       else
11263         oappend ("DWORD PTR ");
11264       break;
11265     case mask_bd_mode:
11266       if (!need_vex || vex.length != 128)
11267         abort ();
11268       if (vex.w)
11269         oappend ("DWORD PTR ");
11270       else
11271         oappend ("BYTE PTR ");
11272       break;
11273     case mask_mode:
11274       if (!need_vex)
11275         abort ();
11276       if (vex.w)
11277         oappend ("QWORD PTR ");
11278       else
11279         oappend ("WORD PTR ");
11280       break;
11281     case v_bnd_mode:
11282     case v_bndmk_mode:
11283     default:
11284       break;
11285     }
11286 }
11287
11288 static void
11289 OP_E_register (int bytemode, int sizeflag)
11290 {
11291   int reg = modrm.rm;
11292   const char **names;
11293
11294   USED_REX (REX_B);
11295   if ((rex & REX_B))
11296     reg += 8;
11297
11298   if ((sizeflag & SUFFIX_ALWAYS)
11299       && (bytemode == b_swap_mode
11300           || bytemode == bnd_swap_mode
11301           || bytemode == v_swap_mode))
11302     swap_operand ();
11303
11304   switch (bytemode)
11305     {
11306     case b_mode:
11307     case b_swap_mode:
11308       if (reg & 4)
11309         USED_REX (0);
11310       if (rex)
11311         names = names8rex;
11312       else
11313         names = names8;
11314       break;
11315     case w_mode:
11316       names = names16;
11317       break;
11318     case d_mode:
11319     case dw_mode:
11320     case db_mode:
11321       names = names32;
11322       break;
11323     case q_mode:
11324       names = names64;
11325       break;
11326     case m_mode:
11327     case v_bnd_mode:
11328       names = address_mode == mode_64bit ? names64 : names32;
11329       break;
11330     case bnd_mode:
11331     case bnd_swap_mode:
11332       if (reg > 0x3)
11333         {
11334           oappend ("(bad)");
11335           return;
11336         }
11337       names = names_bnd;
11338       break;
11339     case indir_v_mode:
11340       if (address_mode == mode_64bit && isa64 == intel64)
11341         {
11342           names = names64;
11343           break;
11344         }
11345       /* Fall through.  */
11346     case stack_v_mode:
11347       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11348         {
11349           names = names64;
11350           break;
11351         }
11352       bytemode = v_mode;
11353       /* Fall through.  */
11354     case v_mode:
11355     case v_swap_mode:
11356     case dq_mode:
11357     case dqb_mode:
11358     case dqd_mode:
11359     case dqw_mode:
11360       USED_REX (REX_W);
11361       if (rex & REX_W)
11362         names = names64;
11363       else if (bytemode != v_mode && bytemode != v_swap_mode)
11364         names = names32;
11365       else
11366         {
11367           if (sizeflag & DFLAG)
11368             names = names32;
11369           else
11370             names = names16;
11371           used_prefixes |= (prefixes & PREFIX_DATA);
11372         }
11373       break;
11374     case movsxd_mode:
11375       if (!(sizeflag & DFLAG) && isa64 == intel64)
11376         names = names16;
11377       else
11378         names = names32;
11379       used_prefixes |= (prefixes & PREFIX_DATA);
11380       break;
11381     case va_mode:
11382       names = (address_mode == mode_64bit
11383                ? names64 : names32);
11384       if (!(prefixes & PREFIX_ADDR))
11385         names = (address_mode == mode_16bit
11386                      ? names16 : names);
11387       else
11388         {
11389           /* Remove "addr16/addr32".  */
11390           all_prefixes[last_addr_prefix] = 0;
11391           names = (address_mode != mode_32bit
11392                        ? names32 : names16);
11393           used_prefixes |= PREFIX_ADDR;
11394         }
11395       break;
11396     case mask_bd_mode:
11397     case mask_mode:
11398       if (reg > 0x7)
11399         {
11400           oappend ("(bad)");
11401           return;
11402         }
11403       names = names_mask;
11404       break;
11405     case 0:
11406       return;
11407     default:
11408       oappend (INTERNAL_DISASSEMBLER_ERROR);
11409       return;
11410     }
11411   oappend (names[reg]);
11412 }
11413
11414 static void
11415 OP_E_memory (int bytemode, int sizeflag)
11416 {
11417   bfd_vma disp = 0;
11418   int add = (rex & REX_B) ? 8 : 0;
11419   int riprel = 0;
11420   int shift;
11421
11422   if (vex.evex)
11423     {
11424       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
11425       if (vex.b
11426           && bytemode != x_mode
11427           && bytemode != evex_half_bcst_xmmq_mode)
11428         {
11429           BadOp ();
11430           return;
11431         }
11432       switch (bytemode)
11433         {
11434         case dqw_mode:
11435         case dw_mode:
11436         case xmm_mw_mode:
11437           shift = 1;
11438           break;
11439         case dqb_mode:
11440         case db_mode:
11441         case xmm_mb_mode:
11442           shift = 0;
11443           break;
11444         case dq_mode:
11445           if (address_mode != mode_64bit)
11446             {
11447         case dqd_mode:
11448         case xmm_md_mode:
11449         case d_mode:
11450         case d_swap_mode:
11451               shift = 2;
11452               break;
11453             }
11454             /* fall through */
11455         case vex_scalar_w_dq_mode:
11456         case vex_vsib_d_w_dq_mode:
11457         case vex_vsib_q_w_dq_mode:
11458         case evex_x_gscat_mode:
11459           shift = vex.w ? 3 : 2;
11460           break;
11461         case x_mode:
11462         case evex_half_bcst_xmmq_mode:
11463           if (vex.b)
11464             {
11465               shift = vex.w ? 3 : 2;
11466               break;
11467             }
11468           /* Fall through.  */
11469         case xmmqd_mode:
11470         case xmmdw_mode:
11471         case xmmq_mode:
11472         case ymmq_mode:
11473         case evex_x_nobcst_mode:
11474         case x_swap_mode:
11475           switch (vex.length)
11476             {
11477             case 128:
11478               shift = 4;
11479               break;
11480             case 256:
11481               shift = 5;
11482               break;
11483             case 512:
11484               shift = 6;
11485               break;
11486             default:
11487               abort ();
11488             }
11489           /* Make necessary corrections to shift for modes that need it.  */
11490           if (bytemode == xmmq_mode
11491               || bytemode == evex_half_bcst_xmmq_mode
11492               || (bytemode == ymmq_mode && vex.length == 128))
11493             shift -= 1;
11494           else if (bytemode == xmmqd_mode)
11495             shift -= 2;
11496           else if (bytemode == xmmdw_mode)
11497             shift -= 3;
11498           break;
11499         case ymm_mode:
11500           shift = 5;
11501           break;
11502         case xmm_mode:
11503           shift = 4;
11504           break;
11505         case xmm_mq_mode:
11506         case q_mode:
11507         case q_swap_mode:
11508           shift = 3;
11509           break;
11510         case bw_unit_mode:
11511           shift = vex.w ? 1 : 0;
11512           break;
11513         default:
11514           abort ();
11515         }
11516     }
11517   else
11518     shift = 0;
11519
11520   USED_REX (REX_B);
11521   if (intel_syntax)
11522     intel_operand_size (bytemode, sizeflag);
11523   append_seg ();
11524
11525   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11526     {
11527       /* 32/64 bit address mode */
11528       int havedisp;
11529       int havesib;
11530       int havebase;
11531       int haveindex;
11532       int needindex;
11533       int needaddr32;
11534       int base, rbase;
11535       int vindex = 0;
11536       int scale = 0;
11537       int addr32flag = !((sizeflag & AFLAG)
11538                          || bytemode == v_bnd_mode
11539                          || bytemode == v_bndmk_mode
11540                          || bytemode == bnd_mode
11541                          || bytemode == bnd_swap_mode);
11542       const char **indexes64 = names64;
11543       const char **indexes32 = names32;
11544
11545       havesib = 0;
11546       havebase = 1;
11547       haveindex = 0;
11548       base = modrm.rm;
11549
11550       if (base == 4)
11551         {
11552           havesib = 1;
11553           vindex = sib.index;
11554           USED_REX (REX_X);
11555           if (rex & REX_X)
11556             vindex += 8;
11557           switch (bytemode)
11558             {
11559             case vex_vsib_d_w_dq_mode:
11560             case vex_vsib_q_w_dq_mode:
11561               if (!need_vex)
11562                 abort ();
11563               if (vex.evex)
11564                 {
11565                   if (!vex.v)
11566                     vindex += 16;
11567                 }
11568
11569               haveindex = 1;
11570               switch (vex.length)
11571                 {
11572                 case 128:
11573                   indexes64 = indexes32 = names_xmm;
11574                   break;
11575                 case 256:
11576                   if (!vex.w
11577                       || bytemode == vex_vsib_q_w_dq_mode)
11578                     indexes64 = indexes32 = names_ymm;
11579                   else
11580                     indexes64 = indexes32 = names_xmm;
11581                   break;
11582                 case 512:
11583                   if (!vex.w
11584                       || bytemode == vex_vsib_q_w_dq_mode)
11585                     indexes64 = indexes32 = names_zmm;
11586                   else
11587                     indexes64 = indexes32 = names_ymm;
11588                   break;
11589                 default:
11590                   abort ();
11591                 }
11592               break;
11593             default:
11594               haveindex = vindex != 4;
11595               break;
11596             }
11597           scale = sib.scale;
11598           base = sib.base;
11599           codep++;
11600         }
11601       else
11602         {
11603           /* mandatory non-vector SIB must have sib */
11604           if (bytemode == vex_sibmem_mode)
11605             {
11606               oappend ("(bad)");
11607               return;
11608             }
11609         }
11610       rbase = base + add;
11611
11612       switch (modrm.mod)
11613         {
11614         case 0:
11615           if (base == 5)
11616             {
11617               havebase = 0;
11618               if (address_mode == mode_64bit && !havesib)
11619                 riprel = 1;
11620               disp = get32s ();
11621               if (riprel && bytemode == v_bndmk_mode)
11622                 {
11623                   oappend ("(bad)");
11624                   return;
11625                 }
11626             }
11627           break;
11628         case 1:
11629           FETCH_DATA (the_info, codep + 1);
11630           disp = *codep++;
11631           if ((disp & 0x80) != 0)
11632             disp -= 0x100;
11633           if (vex.evex && shift > 0)
11634             disp <<= shift;
11635           break;
11636         case 2:
11637           disp = get32s ();
11638           break;
11639         }
11640
11641       needindex = 0;
11642       needaddr32 = 0;
11643       if (havesib
11644           && !havebase
11645           && !haveindex
11646           && address_mode != mode_16bit)
11647         {
11648           if (address_mode == mode_64bit)
11649             {
11650               if (addr32flag)
11651                 {
11652                   /* Without base nor index registers, zero-extend the
11653                      lower 32-bit displacement to 64 bits.  */
11654                   disp = (unsigned int) disp;
11655                   needindex = 1;
11656                 }
11657               needaddr32 = 1;
11658             }
11659           else
11660             {
11661               /* In 32-bit mode, we need index register to tell [offset]
11662                  from [eiz*1 + offset].  */
11663               needindex = 1;
11664             }
11665         }
11666
11667       havedisp = (havebase
11668                   || needindex
11669                   || (havesib && (haveindex || scale != 0)));
11670
11671       if (!intel_syntax)
11672         if (modrm.mod != 0 || base == 5)
11673           {
11674             if (havedisp || riprel)
11675               print_displacement (scratchbuf, disp);
11676             else
11677               print_operand_value (scratchbuf, 1, disp);
11678             oappend (scratchbuf);
11679             if (riprel)
11680               {
11681                 set_op (disp, 1);
11682                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11683               }
11684           }
11685
11686       if ((havebase || haveindex || needindex || needaddr32 || riprel)
11687           && (address_mode != mode_64bit
11688               || ((bytemode != v_bnd_mode)
11689                   && (bytemode != v_bndmk_mode)
11690                   && (bytemode != bnd_mode)
11691                   && (bytemode != bnd_swap_mode))))
11692         used_prefixes |= PREFIX_ADDR;
11693
11694       if (havedisp || (intel_syntax && riprel))
11695         {
11696           *obufp++ = open_char;
11697           if (intel_syntax && riprel)
11698             {
11699               set_op (disp, 1);
11700               oappend (!addr32flag ? "rip" : "eip");
11701             }
11702           *obufp = '\0';
11703           if (havebase)
11704             oappend (address_mode == mode_64bit && !addr32flag
11705                      ? names64[rbase] : names32[rbase]);
11706           if (havesib)
11707             {
11708               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11709                  print index to tell base + index from base.  */
11710               if (scale != 0
11711                   || needindex
11712                   || haveindex
11713                   || (havebase && base != ESP_REG_NUM))
11714                 {
11715                   if (!intel_syntax || havebase)
11716                     {
11717                       *obufp++ = separator_char;
11718                       *obufp = '\0';
11719                     }
11720                   if (haveindex)
11721                     oappend (address_mode == mode_64bit && !addr32flag
11722                              ? indexes64[vindex] : indexes32[vindex]);
11723                   else
11724                     oappend (address_mode == mode_64bit && !addr32flag
11725                              ? index64 : index32);
11726
11727                   *obufp++ = scale_char;
11728                   *obufp = '\0';
11729                   sprintf (scratchbuf, "%d", 1 << scale);
11730                   oappend (scratchbuf);
11731                 }
11732             }
11733           if (intel_syntax
11734               && (disp || modrm.mod != 0 || base == 5))
11735             {
11736               if (!havedisp || (bfd_signed_vma) disp >= 0)
11737                 {
11738                   *obufp++ = '+';
11739                   *obufp = '\0';
11740                 }
11741               else if (modrm.mod != 1 && disp != -disp)
11742                 {
11743                   *obufp++ = '-';
11744                   *obufp = '\0';
11745                   disp = -disp;
11746                 }
11747
11748               if (havedisp)
11749                 print_displacement (scratchbuf, disp);
11750               else
11751                 print_operand_value (scratchbuf, 1, disp);
11752               oappend (scratchbuf);
11753             }
11754
11755           *obufp++ = close_char;
11756           *obufp = '\0';
11757         }
11758       else if (intel_syntax)
11759         {
11760           if (modrm.mod != 0 || base == 5)
11761             {
11762               if (!active_seg_prefix)
11763                 {
11764                   oappend (names_seg[ds_reg - es_reg]);
11765                   oappend (":");
11766                 }
11767               print_operand_value (scratchbuf, 1, disp);
11768               oappend (scratchbuf);
11769             }
11770         }
11771     }
11772   else if (bytemode == v_bnd_mode
11773            || bytemode == v_bndmk_mode
11774            || bytemode == bnd_mode
11775            || bytemode == bnd_swap_mode)
11776     {
11777       oappend ("(bad)");
11778       return;
11779     }
11780   else
11781     {
11782       /* 16 bit address mode */
11783       used_prefixes |= prefixes & PREFIX_ADDR;
11784       switch (modrm.mod)
11785         {
11786         case 0:
11787           if (modrm.rm == 6)
11788             {
11789               disp = get16 ();
11790               if ((disp & 0x8000) != 0)
11791                 disp -= 0x10000;
11792             }
11793           break;
11794         case 1:
11795           FETCH_DATA (the_info, codep + 1);
11796           disp = *codep++;
11797           if ((disp & 0x80) != 0)
11798             disp -= 0x100;
11799           if (vex.evex && shift > 0)
11800             disp <<= shift;
11801           break;
11802         case 2:
11803           disp = get16 ();
11804           if ((disp & 0x8000) != 0)
11805             disp -= 0x10000;
11806           break;
11807         }
11808
11809       if (!intel_syntax)
11810         if (modrm.mod != 0 || modrm.rm == 6)
11811           {
11812             print_displacement (scratchbuf, disp);
11813             oappend (scratchbuf);
11814           }
11815
11816       if (modrm.mod != 0 || modrm.rm != 6)
11817         {
11818           *obufp++ = open_char;
11819           *obufp = '\0';
11820           oappend (index16[modrm.rm]);
11821           if (intel_syntax
11822               && (disp || modrm.mod != 0 || modrm.rm == 6))
11823             {
11824               if ((bfd_signed_vma) disp >= 0)
11825                 {
11826                   *obufp++ = '+';
11827                   *obufp = '\0';
11828                 }
11829               else if (modrm.mod != 1)
11830                 {
11831                   *obufp++ = '-';
11832                   *obufp = '\0';
11833                   disp = -disp;
11834                 }
11835
11836               print_displacement (scratchbuf, disp);
11837               oappend (scratchbuf);
11838             }
11839
11840           *obufp++ = close_char;
11841           *obufp = '\0';
11842         }
11843       else if (intel_syntax)
11844         {
11845           if (!active_seg_prefix)
11846             {
11847               oappend (names_seg[ds_reg - es_reg]);
11848               oappend (":");
11849             }
11850           print_operand_value (scratchbuf, 1, disp & 0xffff);
11851           oappend (scratchbuf);
11852         }
11853     }
11854   if (vex.b
11855       && (bytemode == x_mode
11856           || bytemode == evex_half_bcst_xmmq_mode))
11857     {
11858       if (vex.w
11859           || bytemode == evex_half_bcst_xmmq_mode)
11860         {
11861           switch (vex.length)
11862             {
11863             case 128:
11864               oappend ("{1to2}");
11865               break;
11866             case 256:
11867               oappend ("{1to4}");
11868               break;
11869             case 512:
11870               oappend ("{1to8}");
11871               break;
11872             default:
11873               abort ();
11874             }
11875         }
11876       else
11877         {
11878           switch (vex.length)
11879             {
11880             case 128:
11881               oappend ("{1to4}");
11882               break;
11883             case 256:
11884               oappend ("{1to8}");
11885               break;
11886             case 512:
11887               oappend ("{1to16}");
11888               break;
11889             default:
11890               abort ();
11891             }
11892         }
11893     }
11894 }
11895
11896 static void
11897 OP_E (int bytemode, int sizeflag)
11898 {
11899   /* Skip mod/rm byte.  */
11900   MODRM_CHECK;
11901   codep++;
11902
11903   if (modrm.mod == 3)
11904     OP_E_register (bytemode, sizeflag);
11905   else
11906     OP_E_memory (bytemode, sizeflag);
11907 }
11908
11909 static void
11910 OP_G (int bytemode, int sizeflag)
11911 {
11912   int add = 0;
11913   const char **names;
11914   USED_REX (REX_R);
11915   if (rex & REX_R)
11916     add += 8;
11917   switch (bytemode)
11918     {
11919     case b_mode:
11920       if (modrm.reg & 4)
11921         USED_REX (0);
11922       if (rex)
11923         oappend (names8rex[modrm.reg + add]);
11924       else
11925         oappend (names8[modrm.reg + add]);
11926       break;
11927     case w_mode:
11928       oappend (names16[modrm.reg + add]);
11929       break;
11930     case d_mode:
11931     case db_mode:
11932     case dw_mode:
11933       oappend (names32[modrm.reg + add]);
11934       break;
11935     case q_mode:
11936       oappend (names64[modrm.reg + add]);
11937       break;
11938     case bnd_mode:
11939       if (modrm.reg > 0x3)
11940         {
11941           oappend ("(bad)");
11942           return;
11943         }
11944       oappend (names_bnd[modrm.reg]);
11945       break;
11946     case v_mode:
11947     case dq_mode:
11948     case dqb_mode:
11949     case dqd_mode:
11950     case dqw_mode:
11951     case movsxd_mode:
11952       USED_REX (REX_W);
11953       if (rex & REX_W)
11954         oappend (names64[modrm.reg + add]);
11955       else if (bytemode != v_mode && bytemode != movsxd_mode)
11956         oappend (names32[modrm.reg + add]);
11957       else
11958         {
11959           if (sizeflag & DFLAG)
11960             oappend (names32[modrm.reg + add]);
11961           else
11962             oappend (names16[modrm.reg + add]);
11963           used_prefixes |= (prefixes & PREFIX_DATA);
11964         }
11965       break;
11966     case va_mode:
11967       names = (address_mode == mode_64bit
11968                ? names64 : names32);
11969       if (!(prefixes & PREFIX_ADDR))
11970         {
11971           if (address_mode == mode_16bit)
11972             names = names16;
11973         }
11974       else
11975         {
11976           /* Remove "addr16/addr32".  */
11977           all_prefixes[last_addr_prefix] = 0;
11978           names = (address_mode != mode_32bit
11979                        ? names32 : names16);
11980           used_prefixes |= PREFIX_ADDR;
11981         }
11982       oappend (names[modrm.reg + add]);
11983       break;
11984     case m_mode:
11985       if (address_mode == mode_64bit)
11986         oappend (names64[modrm.reg + add]);
11987       else
11988         oappend (names32[modrm.reg + add]);
11989       break;
11990     case mask_bd_mode:
11991     case mask_mode:
11992       if ((modrm.reg + add) > 0x7)
11993         {
11994           oappend ("(bad)");
11995           return;
11996         }
11997       oappend (names_mask[modrm.reg + add]);
11998       break;
11999     default:
12000       oappend (INTERNAL_DISASSEMBLER_ERROR);
12001       break;
12002     }
12003 }
12004
12005 static bfd_vma
12006 get64 (void)
12007 {
12008   bfd_vma x;
12009 #ifdef BFD64
12010   unsigned int a;
12011   unsigned int b;
12012
12013   FETCH_DATA (the_info, codep + 8);
12014   a = *codep++ & 0xff;
12015   a |= (*codep++ & 0xff) << 8;
12016   a |= (*codep++ & 0xff) << 16;
12017   a |= (*codep++ & 0xffu) << 24;
12018   b = *codep++ & 0xff;
12019   b |= (*codep++ & 0xff) << 8;
12020   b |= (*codep++ & 0xff) << 16;
12021   b |= (*codep++ & 0xffu) << 24;
12022   x = a + ((bfd_vma) b << 32);
12023 #else
12024   abort ();
12025   x = 0;
12026 #endif
12027   return x;
12028 }
12029
12030 static bfd_signed_vma
12031 get32 (void)
12032 {
12033   bfd_vma x = 0;
12034
12035   FETCH_DATA (the_info, codep + 4);
12036   x = *codep++ & (bfd_vma) 0xff;
12037   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12038   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12039   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12040   return x;
12041 }
12042
12043 static bfd_signed_vma
12044 get32s (void)
12045 {
12046   bfd_vma x = 0;
12047
12048   FETCH_DATA (the_info, codep + 4);
12049   x = *codep++ & (bfd_vma) 0xff;
12050   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12051   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12052   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12053
12054   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12055
12056   return x;
12057 }
12058
12059 static int
12060 get16 (void)
12061 {
12062   int x = 0;
12063
12064   FETCH_DATA (the_info, codep + 2);
12065   x = *codep++ & 0xff;
12066   x |= (*codep++ & 0xff) << 8;
12067   return x;
12068 }
12069
12070 static void
12071 set_op (bfd_vma op, int riprel)
12072 {
12073   op_index[op_ad] = op_ad;
12074   if (address_mode == mode_64bit)
12075     {
12076       op_address[op_ad] = op;
12077       op_riprel[op_ad] = riprel;
12078     }
12079   else
12080     {
12081       /* Mask to get a 32-bit address.  */
12082       op_address[op_ad] = op & 0xffffffff;
12083       op_riprel[op_ad] = riprel & 0xffffffff;
12084     }
12085 }
12086
12087 static void
12088 OP_REG (int code, int sizeflag)
12089 {
12090   const char *s;
12091   int add;
12092
12093   switch (code)
12094     {
12095     case es_reg: case ss_reg: case cs_reg:
12096     case ds_reg: case fs_reg: case gs_reg:
12097       oappend (names_seg[code - es_reg]);
12098       return;
12099     }
12100
12101   USED_REX (REX_B);
12102   if (rex & REX_B)
12103     add = 8;
12104   else
12105     add = 0;
12106
12107   switch (code)
12108     {
12109     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12110     case sp_reg: case bp_reg: case si_reg: case di_reg:
12111       s = names16[code - ax_reg + add];
12112       break;
12113     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12114       USED_REX (0);
12115       /* Fall through.  */
12116     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12117       if (rex)
12118         s = names8rex[code - al_reg + add];
12119       else
12120         s = names8[code - al_reg];
12121       break;
12122     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12123     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12124       if (address_mode == mode_64bit
12125           && ((sizeflag & DFLAG) || (rex & REX_W)))
12126         {
12127           s = names64[code - rAX_reg + add];
12128           break;
12129         }
12130       code += eAX_reg - rAX_reg;
12131       /* Fall through.  */
12132     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12133     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12134       USED_REX (REX_W);
12135       if (rex & REX_W)
12136         s = names64[code - eAX_reg + add];
12137       else
12138         {
12139           if (sizeflag & DFLAG)
12140             s = names32[code - eAX_reg + add];
12141           else
12142             s = names16[code - eAX_reg + add];
12143           used_prefixes |= (prefixes & PREFIX_DATA);
12144         }
12145       break;
12146     default:
12147       s = INTERNAL_DISASSEMBLER_ERROR;
12148       break;
12149     }
12150   oappend (s);
12151 }
12152
12153 static void
12154 OP_IMREG (int code, int sizeflag)
12155 {
12156   const char *s;
12157
12158   switch (code)
12159     {
12160     case indir_dx_reg:
12161       if (intel_syntax)
12162         s = "dx";
12163       else
12164         s = "(%dx)";
12165       break;
12166     case al_reg: case cl_reg:
12167       s = names8[code - al_reg];
12168       break;
12169     case eAX_reg:
12170       USED_REX (REX_W);
12171       if (rex & REX_W)
12172         {
12173           s = *names64;
12174           break;
12175         }
12176       /* Fall through.  */
12177     case z_mode_ax_reg:
12178       if ((rex & REX_W) || (sizeflag & DFLAG))
12179         s = *names32;
12180       else
12181         s = *names16;
12182       if (!(rex & REX_W))
12183         used_prefixes |= (prefixes & PREFIX_DATA);
12184       break;
12185     default:
12186       s = INTERNAL_DISASSEMBLER_ERROR;
12187       break;
12188     }
12189   oappend (s);
12190 }
12191
12192 static void
12193 OP_I (int bytemode, int sizeflag)
12194 {
12195   bfd_signed_vma op;
12196   bfd_signed_vma mask = -1;
12197
12198   switch (bytemode)
12199     {
12200     case b_mode:
12201       FETCH_DATA (the_info, codep + 1);
12202       op = *codep++;
12203       mask = 0xff;
12204       break;
12205     case v_mode:
12206       USED_REX (REX_W);
12207       if (rex & REX_W)
12208         op = get32s ();
12209       else
12210         {
12211           if (sizeflag & DFLAG)
12212             {
12213               op = get32 ();
12214               mask = 0xffffffff;
12215             }
12216           else
12217             {
12218               op = get16 ();
12219               mask = 0xfffff;
12220             }
12221           used_prefixes |= (prefixes & PREFIX_DATA);
12222         }
12223       break;
12224     case d_mode:
12225       mask = 0xffffffff;
12226       op = get32 ();
12227       break;
12228     case w_mode:
12229       mask = 0xfffff;
12230       op = get16 ();
12231       break;
12232     case const_1_mode:
12233       if (intel_syntax)
12234         oappend ("1");
12235       return;
12236     default:
12237       oappend (INTERNAL_DISASSEMBLER_ERROR);
12238       return;
12239     }
12240
12241   op &= mask;
12242   scratchbuf[0] = '$';
12243   print_operand_value (scratchbuf + 1, 1, op);
12244   oappend_maybe_intel (scratchbuf);
12245   scratchbuf[0] = '\0';
12246 }
12247
12248 static void
12249 OP_I64 (int bytemode, int sizeflag)
12250 {
12251   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12252     {
12253       OP_I (bytemode, sizeflag);
12254       return;
12255     }
12256
12257   USED_REX (REX_W);
12258
12259   scratchbuf[0] = '$';
12260   print_operand_value (scratchbuf + 1, 1, get64 ());
12261   oappend_maybe_intel (scratchbuf);
12262   scratchbuf[0] = '\0';
12263 }
12264
12265 static void
12266 OP_sI (int bytemode, int sizeflag)
12267 {
12268   bfd_signed_vma op;
12269
12270   switch (bytemode)
12271     {
12272     case b_mode:
12273     case b_T_mode:
12274       FETCH_DATA (the_info, codep + 1);
12275       op = *codep++;
12276       if ((op & 0x80) != 0)
12277         op -= 0x100;
12278       if (bytemode == b_T_mode)
12279         {
12280           if (address_mode != mode_64bit
12281               || !((sizeflag & DFLAG) || (rex & REX_W)))
12282             {
12283               /* The operand-size prefix is overridden by a REX prefix.  */
12284               if ((sizeflag & DFLAG) || (rex & REX_W))
12285                 op &= 0xffffffff;
12286               else
12287                 op &= 0xffff;
12288           }
12289         }
12290       else
12291         {
12292           if (!(rex & REX_W))
12293             {
12294               if (sizeflag & DFLAG)
12295                 op &= 0xffffffff;
12296               else
12297                 op &= 0xffff;
12298             }
12299         }
12300       break;
12301     case v_mode:
12302       /* The operand-size prefix is overridden by a REX prefix.  */
12303       if ((sizeflag & DFLAG) || (rex & REX_W))
12304         op = get32s ();
12305       else
12306         op = get16 ();
12307       break;
12308     default:
12309       oappend (INTERNAL_DISASSEMBLER_ERROR);
12310       return;
12311     }
12312
12313   scratchbuf[0] = '$';
12314   print_operand_value (scratchbuf + 1, 1, op);
12315   oappend_maybe_intel (scratchbuf);
12316 }
12317
12318 static void
12319 OP_J (int bytemode, int sizeflag)
12320 {
12321   bfd_vma disp;
12322   bfd_vma mask = -1;
12323   bfd_vma segment = 0;
12324
12325   switch (bytemode)
12326     {
12327     case b_mode:
12328       FETCH_DATA (the_info, codep + 1);
12329       disp = *codep++;
12330       if ((disp & 0x80) != 0)
12331         disp -= 0x100;
12332       break;
12333     case v_mode:
12334     case dqw_mode:
12335       if ((sizeflag & DFLAG)
12336           || (address_mode == mode_64bit
12337               && ((isa64 == intel64 && bytemode != dqw_mode)
12338                   || (rex & REX_W))))
12339         disp = get32s ();
12340       else
12341         {
12342           disp = get16 ();
12343           if ((disp & 0x8000) != 0)
12344             disp -= 0x10000;
12345           /* In 16bit mode, address is wrapped around at 64k within
12346              the same segment.  Otherwise, a data16 prefix on a jump
12347              instruction means that the pc is masked to 16 bits after
12348              the displacement is added!  */
12349           mask = 0xffff;
12350           if ((prefixes & PREFIX_DATA) == 0)
12351             segment = ((start_pc + (codep - start_codep))
12352                        & ~((bfd_vma) 0xffff));
12353         }
12354       if (address_mode != mode_64bit
12355           || (isa64 != intel64 && !(rex & REX_W)))
12356         used_prefixes |= (prefixes & PREFIX_DATA);
12357       break;
12358     default:
12359       oappend (INTERNAL_DISASSEMBLER_ERROR);
12360       return;
12361     }
12362   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12363   set_op (disp, 0);
12364   print_operand_value (scratchbuf, 1, disp);
12365   oappend (scratchbuf);
12366 }
12367
12368 static void
12369 OP_SEG (int bytemode, int sizeflag)
12370 {
12371   if (bytemode == w_mode)
12372     oappend (names_seg[modrm.reg]);
12373   else
12374     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12375 }
12376
12377 static void
12378 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12379 {
12380   int seg, offset;
12381
12382   if (sizeflag & DFLAG)
12383     {
12384       offset = get32 ();
12385       seg = get16 ();
12386     }
12387   else
12388     {
12389       offset = get16 ();
12390       seg = get16 ();
12391     }
12392   used_prefixes |= (prefixes & PREFIX_DATA);
12393   if (intel_syntax)
12394     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12395   else
12396     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12397   oappend (scratchbuf);
12398 }
12399
12400 static void
12401 OP_OFF (int bytemode, int sizeflag)
12402 {
12403   bfd_vma off;
12404
12405   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12406     intel_operand_size (bytemode, sizeflag);
12407   append_seg ();
12408
12409   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12410     off = get32 ();
12411   else
12412     off = get16 ();
12413
12414   if (intel_syntax)
12415     {
12416       if (!active_seg_prefix)
12417         {
12418           oappend (names_seg[ds_reg - es_reg]);
12419           oappend (":");
12420         }
12421     }
12422   print_operand_value (scratchbuf, 1, off);
12423   oappend (scratchbuf);
12424 }
12425
12426 static void
12427 OP_OFF64 (int bytemode, int sizeflag)
12428 {
12429   bfd_vma off;
12430
12431   if (address_mode != mode_64bit
12432       || (prefixes & PREFIX_ADDR))
12433     {
12434       OP_OFF (bytemode, sizeflag);
12435       return;
12436     }
12437
12438   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12439     intel_operand_size (bytemode, sizeflag);
12440   append_seg ();
12441
12442   off = get64 ();
12443
12444   if (intel_syntax)
12445     {
12446       if (!active_seg_prefix)
12447         {
12448           oappend (names_seg[ds_reg - es_reg]);
12449           oappend (":");
12450         }
12451     }
12452   print_operand_value (scratchbuf, 1, off);
12453   oappend (scratchbuf);
12454 }
12455
12456 static void
12457 ptr_reg (int code, int sizeflag)
12458 {
12459   const char *s;
12460
12461   *obufp++ = open_char;
12462   used_prefixes |= (prefixes & PREFIX_ADDR);
12463   if (address_mode == mode_64bit)
12464     {
12465       if (!(sizeflag & AFLAG))
12466         s = names32[code - eAX_reg];
12467       else
12468         s = names64[code - eAX_reg];
12469     }
12470   else if (sizeflag & AFLAG)
12471     s = names32[code - eAX_reg];
12472   else
12473     s = names16[code - eAX_reg];
12474   oappend (s);
12475   *obufp++ = close_char;
12476   *obufp = 0;
12477 }
12478
12479 static void
12480 OP_ESreg (int code, int sizeflag)
12481 {
12482   if (intel_syntax)
12483     {
12484       switch (codep[-1])
12485         {
12486         case 0x6d:      /* insw/insl */
12487           intel_operand_size (z_mode, sizeflag);
12488           break;
12489         case 0xa5:      /* movsw/movsl/movsq */
12490         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12491         case 0xab:      /* stosw/stosl */
12492         case 0xaf:      /* scasw/scasl */
12493           intel_operand_size (v_mode, sizeflag);
12494           break;
12495         default:
12496           intel_operand_size (b_mode, sizeflag);
12497         }
12498     }
12499   oappend_maybe_intel ("%es:");
12500   ptr_reg (code, sizeflag);
12501 }
12502
12503 static void
12504 OP_DSreg (int code, int sizeflag)
12505 {
12506   if (intel_syntax)
12507     {
12508       switch (codep[-1])
12509         {
12510         case 0x6f:      /* outsw/outsl */
12511           intel_operand_size (z_mode, sizeflag);
12512           break;
12513         case 0xa5:      /* movsw/movsl/movsq */
12514         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12515         case 0xad:      /* lodsw/lodsl/lodsq */
12516           intel_operand_size (v_mode, sizeflag);
12517           break;
12518         default:
12519           intel_operand_size (b_mode, sizeflag);
12520         }
12521     }
12522   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12523      default segment register DS is printed.  */
12524   if (!active_seg_prefix)
12525     active_seg_prefix = PREFIX_DS;
12526   append_seg ();
12527   ptr_reg (code, sizeflag);
12528 }
12529
12530 static void
12531 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12532 {
12533   int add;
12534   if (rex & REX_R)
12535     {
12536       USED_REX (REX_R);
12537       add = 8;
12538     }
12539   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12540     {
12541       all_prefixes[last_lock_prefix] = 0;
12542       used_prefixes |= PREFIX_LOCK;
12543       add = 8;
12544     }
12545   else
12546     add = 0;
12547   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12548   oappend_maybe_intel (scratchbuf);
12549 }
12550
12551 static void
12552 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12553 {
12554   int add;
12555   USED_REX (REX_R);
12556   if (rex & REX_R)
12557     add = 8;
12558   else
12559     add = 0;
12560   if (intel_syntax)
12561     sprintf (scratchbuf, "dr%d", modrm.reg + add);
12562   else
12563     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12564   oappend (scratchbuf);
12565 }
12566
12567 static void
12568 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12569 {
12570   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12571   oappend_maybe_intel (scratchbuf);
12572 }
12573
12574 static void
12575 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12576 {
12577   int reg = modrm.reg;
12578   const char **names;
12579
12580   used_prefixes |= (prefixes & PREFIX_DATA);
12581   if (prefixes & PREFIX_DATA)
12582     {
12583       names = names_xmm;
12584       USED_REX (REX_R);
12585       if (rex & REX_R)
12586         reg += 8;
12587     }
12588   else
12589     names = names_mm;
12590   oappend (names[reg]);
12591 }
12592
12593 static void
12594 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12595 {
12596   int reg = modrm.reg;
12597   const char **names;
12598
12599   USED_REX (REX_R);
12600   if (rex & REX_R)
12601     reg += 8;
12602   if (vex.evex)
12603     {
12604       if (!vex.r)
12605         reg += 16;
12606     }
12607
12608   if (bytemode == xmmq_mode
12609       || bytemode == evex_half_bcst_xmmq_mode)
12610     {
12611       switch (vex.length)
12612         {
12613         case 128:
12614         case 256:
12615           names = names_xmm;
12616           break;
12617         case 512:
12618           names = names_ymm;
12619           break;
12620         default:
12621           abort ();
12622         }
12623     }
12624   else if (bytemode == ymm_mode)
12625     names = names_ymm;
12626   else if (bytemode == tmm_mode)
12627     {
12628       modrm.reg = reg;
12629       if (reg >= 8)
12630         {
12631           oappend ("(bad)");
12632           return;
12633         }
12634       names = names_tmm;
12635     }
12636   else if (need_vex
12637            && bytemode != xmm_mode
12638            && bytemode != scalar_mode)
12639     {
12640       switch (vex.length)
12641         {
12642         case 128:
12643           names = names_xmm;
12644           break;
12645         case 256:
12646           if (vex.w
12647               || bytemode != vex_vsib_q_w_dq_mode)
12648             names = names_ymm;
12649           else
12650             names = names_xmm;
12651           break;
12652         case 512:
12653           if (vex.w
12654               || bytemode != vex_vsib_q_w_dq_mode)
12655             names = names_zmm;
12656           else
12657             names = names_ymm;
12658           break;
12659         default:
12660           abort ();
12661         }
12662     }
12663   else
12664     names = names_xmm;
12665   oappend (names[reg]);
12666 }
12667
12668 static void
12669 OP_EM (int bytemode, int sizeflag)
12670 {
12671   int reg;
12672   const char **names;
12673
12674   if (modrm.mod != 3)
12675     {
12676       if (intel_syntax
12677           && (bytemode == v_mode || bytemode == v_swap_mode))
12678         {
12679           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12680           used_prefixes |= (prefixes & PREFIX_DATA);
12681         }
12682       OP_E (bytemode, sizeflag);
12683       return;
12684     }
12685
12686   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12687     swap_operand ();
12688
12689   /* Skip mod/rm byte.  */
12690   MODRM_CHECK;
12691   codep++;
12692   used_prefixes |= (prefixes & PREFIX_DATA);
12693   reg = modrm.rm;
12694   if (prefixes & PREFIX_DATA)
12695     {
12696       names = names_xmm;
12697       USED_REX (REX_B);
12698       if (rex & REX_B)
12699         reg += 8;
12700     }
12701   else
12702     names = names_mm;
12703   oappend (names[reg]);
12704 }
12705
12706 /* cvt* are the only instructions in sse2 which have
12707    both SSE and MMX operands and also have 0x66 prefix
12708    in their opcode. 0x66 was originally used to differentiate
12709    between SSE and MMX instruction(operands). So we have to handle the
12710    cvt* separately using OP_EMC and OP_MXC */
12711 static void
12712 OP_EMC (int bytemode, int sizeflag)
12713 {
12714   if (modrm.mod != 3)
12715     {
12716       if (intel_syntax && bytemode == v_mode)
12717         {
12718           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12719           used_prefixes |= (prefixes & PREFIX_DATA);
12720         }
12721       OP_E (bytemode, sizeflag);
12722       return;
12723     }
12724
12725   /* Skip mod/rm byte.  */
12726   MODRM_CHECK;
12727   codep++;
12728   used_prefixes |= (prefixes & PREFIX_DATA);
12729   oappend (names_mm[modrm.rm]);
12730 }
12731
12732 static void
12733 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12734 {
12735   used_prefixes |= (prefixes & PREFIX_DATA);
12736   oappend (names_mm[modrm.reg]);
12737 }
12738
12739 static void
12740 OP_EX (int bytemode, int sizeflag)
12741 {
12742   int reg;
12743   const char **names;
12744
12745   /* Skip mod/rm byte.  */
12746   MODRM_CHECK;
12747   codep++;
12748
12749   if (modrm.mod != 3)
12750     {
12751       OP_E_memory (bytemode, sizeflag);
12752       return;
12753     }
12754
12755   reg = modrm.rm;
12756   USED_REX (REX_B);
12757   if (rex & REX_B)
12758     reg += 8;
12759   if (vex.evex)
12760     {
12761       USED_REX (REX_X);
12762       if ((rex & REX_X))
12763         reg += 16;
12764     }
12765
12766   if ((sizeflag & SUFFIX_ALWAYS)
12767       && (bytemode == x_swap_mode
12768           || bytemode == d_swap_mode
12769           || bytemode == q_swap_mode))
12770     swap_operand ();
12771
12772   if (need_vex
12773       && bytemode != xmm_mode
12774       && bytemode != xmmdw_mode
12775       && bytemode != xmmqd_mode
12776       && bytemode != xmm_mb_mode
12777       && bytemode != xmm_mw_mode
12778       && bytemode != xmm_md_mode
12779       && bytemode != xmm_mq_mode
12780       && bytemode != xmmq_mode
12781       && bytemode != evex_half_bcst_xmmq_mode
12782       && bytemode != ymm_mode
12783       && bytemode != tmm_mode
12784       && bytemode != vex_scalar_w_dq_mode)
12785     {
12786       switch (vex.length)
12787         {
12788         case 128:
12789           names = names_xmm;
12790           break;
12791         case 256:
12792           names = names_ymm;
12793           break;
12794         case 512:
12795           names = names_zmm;
12796           break;
12797         default:
12798           abort ();
12799         }
12800     }
12801   else if (bytemode == xmmq_mode
12802            || bytemode == evex_half_bcst_xmmq_mode)
12803     {
12804       switch (vex.length)
12805         {
12806         case 128:
12807         case 256:
12808           names = names_xmm;
12809           break;
12810         case 512:
12811           names = names_ymm;
12812           break;
12813         default:
12814           abort ();
12815         }
12816     }
12817   else if (bytemode == tmm_mode)
12818     {
12819       modrm.rm = reg;
12820       if (reg >= 8)
12821         {
12822           oappend ("(bad)");
12823           return;
12824         }
12825       names = names_tmm;
12826     }
12827   else if (bytemode == ymm_mode)
12828     names = names_ymm;
12829   else
12830     names = names_xmm;
12831   oappend (names[reg]);
12832 }
12833
12834 static void
12835 OP_MS (int bytemode, int sizeflag)
12836 {
12837   if (modrm.mod == 3)
12838     OP_EM (bytemode, sizeflag);
12839   else
12840     BadOp ();
12841 }
12842
12843 static void
12844 OP_XS (int bytemode, int sizeflag)
12845 {
12846   if (modrm.mod == 3)
12847     OP_EX (bytemode, sizeflag);
12848   else
12849     BadOp ();
12850 }
12851
12852 static void
12853 OP_M (int bytemode, int sizeflag)
12854 {
12855   if (modrm.mod == 3)
12856     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12857     BadOp ();
12858   else
12859     OP_E (bytemode, sizeflag);
12860 }
12861
12862 static void
12863 OP_0f07 (int bytemode, int sizeflag)
12864 {
12865   if (modrm.mod != 3 || modrm.rm != 0)
12866     BadOp ();
12867   else
12868     OP_E (bytemode, sizeflag);
12869 }
12870
12871 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12872    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12873
12874 static void
12875 NOP_Fixup1 (int bytemode, int sizeflag)
12876 {
12877   if ((prefixes & PREFIX_DATA) != 0
12878       || (rex != 0
12879           && rex != 0x48
12880           && address_mode == mode_64bit))
12881     OP_REG (bytemode, sizeflag);
12882   else
12883     strcpy (obuf, "nop");
12884 }
12885
12886 static void
12887 NOP_Fixup2 (int bytemode, int sizeflag)
12888 {
12889   if ((prefixes & PREFIX_DATA) != 0
12890       || (rex != 0
12891           && rex != 0x48
12892           && address_mode == mode_64bit))
12893     OP_IMREG (bytemode, sizeflag);
12894 }
12895
12896 static const char *const Suffix3DNow[] = {
12897 /* 00 */        NULL,           NULL,           NULL,           NULL,
12898 /* 04 */        NULL,           NULL,           NULL,           NULL,
12899 /* 08 */        NULL,           NULL,           NULL,           NULL,
12900 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12901 /* 10 */        NULL,           NULL,           NULL,           NULL,
12902 /* 14 */        NULL,           NULL,           NULL,           NULL,
12903 /* 18 */        NULL,           NULL,           NULL,           NULL,
12904 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12905 /* 20 */        NULL,           NULL,           NULL,           NULL,
12906 /* 24 */        NULL,           NULL,           NULL,           NULL,
12907 /* 28 */        NULL,           NULL,           NULL,           NULL,
12908 /* 2C */        NULL,           NULL,           NULL,           NULL,
12909 /* 30 */        NULL,           NULL,           NULL,           NULL,
12910 /* 34 */        NULL,           NULL,           NULL,           NULL,
12911 /* 38 */        NULL,           NULL,           NULL,           NULL,
12912 /* 3C */        NULL,           NULL,           NULL,           NULL,
12913 /* 40 */        NULL,           NULL,           NULL,           NULL,
12914 /* 44 */        NULL,           NULL,           NULL,           NULL,
12915 /* 48 */        NULL,           NULL,           NULL,           NULL,
12916 /* 4C */        NULL,           NULL,           NULL,           NULL,
12917 /* 50 */        NULL,           NULL,           NULL,           NULL,
12918 /* 54 */        NULL,           NULL,           NULL,           NULL,
12919 /* 58 */        NULL,           NULL,           NULL,           NULL,
12920 /* 5C */        NULL,           NULL,           NULL,           NULL,
12921 /* 60 */        NULL,           NULL,           NULL,           NULL,
12922 /* 64 */        NULL,           NULL,           NULL,           NULL,
12923 /* 68 */        NULL,           NULL,           NULL,           NULL,
12924 /* 6C */        NULL,           NULL,           NULL,           NULL,
12925 /* 70 */        NULL,           NULL,           NULL,           NULL,
12926 /* 74 */        NULL,           NULL,           NULL,           NULL,
12927 /* 78 */        NULL,           NULL,           NULL,           NULL,
12928 /* 7C */        NULL,           NULL,           NULL,           NULL,
12929 /* 80 */        NULL,           NULL,           NULL,           NULL,
12930 /* 84 */        NULL,           NULL,           NULL,           NULL,
12931 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12932 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12933 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12934 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12935 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12936 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12937 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12938 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12939 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12940 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12941 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12942 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12943 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12944 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12945 /* C0 */        NULL,           NULL,           NULL,           NULL,
12946 /* C4 */        NULL,           NULL,           NULL,           NULL,
12947 /* C8 */        NULL,           NULL,           NULL,           NULL,
12948 /* CC */        NULL,           NULL,           NULL,           NULL,
12949 /* D0 */        NULL,           NULL,           NULL,           NULL,
12950 /* D4 */        NULL,           NULL,           NULL,           NULL,
12951 /* D8 */        NULL,           NULL,           NULL,           NULL,
12952 /* DC */        NULL,           NULL,           NULL,           NULL,
12953 /* E0 */        NULL,           NULL,           NULL,           NULL,
12954 /* E4 */        NULL,           NULL,           NULL,           NULL,
12955 /* E8 */        NULL,           NULL,           NULL,           NULL,
12956 /* EC */        NULL,           NULL,           NULL,           NULL,
12957 /* F0 */        NULL,           NULL,           NULL,           NULL,
12958 /* F4 */        NULL,           NULL,           NULL,           NULL,
12959 /* F8 */        NULL,           NULL,           NULL,           NULL,
12960 /* FC */        NULL,           NULL,           NULL,           NULL,
12961 };
12962
12963 static void
12964 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12965 {
12966   const char *mnemonic;
12967
12968   FETCH_DATA (the_info, codep + 1);
12969   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12970      place where an 8-bit immediate would normally go.  ie. the last
12971      byte of the instruction.  */
12972   obufp = mnemonicendp;
12973   mnemonic = Suffix3DNow[*codep++ & 0xff];
12974   if (mnemonic)
12975     oappend (mnemonic);
12976   else
12977     {
12978       /* Since a variable sized modrm/sib chunk is between the start
12979          of the opcode (0x0f0f) and the opcode suffix, we need to do
12980          all the modrm processing first, and don't know until now that
12981          we have a bad opcode.  This necessitates some cleaning up.  */
12982       op_out[0][0] = '\0';
12983       op_out[1][0] = '\0';
12984       BadOp ();
12985     }
12986   mnemonicendp = obufp;
12987 }
12988
12989 static const struct op simd_cmp_op[] =
12990 {
12991   { STRING_COMMA_LEN ("eq") },
12992   { STRING_COMMA_LEN ("lt") },
12993   { STRING_COMMA_LEN ("le") },
12994   { STRING_COMMA_LEN ("unord") },
12995   { STRING_COMMA_LEN ("neq") },
12996   { STRING_COMMA_LEN ("nlt") },
12997   { STRING_COMMA_LEN ("nle") },
12998   { STRING_COMMA_LEN ("ord") }
12999 };
13000
13001 static const struct op vex_cmp_op[] =
13002 {
13003   { STRING_COMMA_LEN ("eq_uq") },
13004   { STRING_COMMA_LEN ("nge") },
13005   { STRING_COMMA_LEN ("ngt") },
13006   { STRING_COMMA_LEN ("false") },
13007   { STRING_COMMA_LEN ("neq_oq") },
13008   { STRING_COMMA_LEN ("ge") },
13009   { STRING_COMMA_LEN ("gt") },
13010   { STRING_COMMA_LEN ("true") },
13011   { STRING_COMMA_LEN ("eq_os") },
13012   { STRING_COMMA_LEN ("lt_oq") },
13013   { STRING_COMMA_LEN ("le_oq") },
13014   { STRING_COMMA_LEN ("unord_s") },
13015   { STRING_COMMA_LEN ("neq_us") },
13016   { STRING_COMMA_LEN ("nlt_uq") },
13017   { STRING_COMMA_LEN ("nle_uq") },
13018   { STRING_COMMA_LEN ("ord_s") },
13019   { STRING_COMMA_LEN ("eq_us") },
13020   { STRING_COMMA_LEN ("nge_uq") },
13021   { STRING_COMMA_LEN ("ngt_uq") },
13022   { STRING_COMMA_LEN ("false_os") },
13023   { STRING_COMMA_LEN ("neq_os") },
13024   { STRING_COMMA_LEN ("ge_oq") },
13025   { STRING_COMMA_LEN ("gt_oq") },
13026   { STRING_COMMA_LEN ("true_us") },
13027 };
13028
13029 static void
13030 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13031 {
13032   unsigned int cmp_type;
13033
13034   FETCH_DATA (the_info, codep + 1);
13035   cmp_type = *codep++ & 0xff;
13036   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13037     {
13038       char suffix [3];
13039       char *p = mnemonicendp - 2;
13040       suffix[0] = p[0];
13041       suffix[1] = p[1];
13042       suffix[2] = '\0';
13043       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13044       mnemonicendp += simd_cmp_op[cmp_type].len;
13045     }
13046   else if (need_vex
13047            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13048     {
13049       char suffix [3];
13050       char *p = mnemonicendp - 2;
13051       suffix[0] = p[0];
13052       suffix[1] = p[1];
13053       suffix[2] = '\0';
13054       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13055       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13056       mnemonicendp += vex_cmp_op[cmp_type].len;
13057     }
13058   else
13059     {
13060       /* We have a reserved extension byte.  Output it directly.  */
13061       scratchbuf[0] = '$';
13062       print_operand_value (scratchbuf + 1, 1, cmp_type);
13063       oappend_maybe_intel (scratchbuf);
13064       scratchbuf[0] = '\0';
13065     }
13066 }
13067
13068 static void
13069 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13070 {
13071   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13072   if (!intel_syntax)
13073     {
13074       strcpy (op_out[0], names32[0]);
13075       strcpy (op_out[1], names32[1]);
13076       if (bytemode == eBX_reg)
13077         strcpy (op_out[2], names32[3]);
13078       two_source_ops = 1;
13079     }
13080   /* Skip mod/rm byte.  */
13081   MODRM_CHECK;
13082   codep++;
13083 }
13084
13085 static void
13086 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13087             int sizeflag ATTRIBUTE_UNUSED)
13088 {
13089   /* monitor %{e,r,}ax,%ecx,%edx"  */
13090   if (!intel_syntax)
13091     {
13092       const char **names = (address_mode == mode_64bit
13093                             ? names64 : names32);
13094
13095       if (prefixes & PREFIX_ADDR)
13096         {
13097           /* Remove "addr16/addr32".  */
13098           all_prefixes[last_addr_prefix] = 0;
13099           names = (address_mode != mode_32bit
13100                    ? names32 : names16);
13101           used_prefixes |= PREFIX_ADDR;
13102         }
13103       else if (address_mode == mode_16bit)
13104         names = names16;
13105       strcpy (op_out[0], names[0]);
13106       strcpy (op_out[1], names32[1]);
13107       strcpy (op_out[2], names32[2]);
13108       two_source_ops = 1;
13109     }
13110   /* Skip mod/rm byte.  */
13111   MODRM_CHECK;
13112   codep++;
13113 }
13114
13115 static void
13116 BadOp (void)
13117 {
13118   /* Throw away prefixes and 1st. opcode byte.  */
13119   codep = insn_codep + 1;
13120   oappend ("(bad)");
13121 }
13122
13123 static void
13124 REP_Fixup (int bytemode, int sizeflag)
13125 {
13126   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13127      lods and stos.  */
13128   if (prefixes & PREFIX_REPZ)
13129     all_prefixes[last_repz_prefix] = REP_PREFIX;
13130
13131   switch (bytemode)
13132     {
13133     case al_reg:
13134     case eAX_reg:
13135     case indir_dx_reg:
13136       OP_IMREG (bytemode, sizeflag);
13137       break;
13138     case eDI_reg:
13139       OP_ESreg (bytemode, sizeflag);
13140       break;
13141     case eSI_reg:
13142       OP_DSreg (bytemode, sizeflag);
13143       break;
13144     default:
13145       abort ();
13146       break;
13147     }
13148 }
13149
13150 static void
13151 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13152 {
13153   if ( isa64 != amd64 )
13154     return;
13155
13156   obufp = obuf;
13157   BadOp ();
13158   mnemonicendp = obufp;
13159   ++codep;
13160 }
13161
13162 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13163    "bnd".  */
13164
13165 static void
13166 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13167 {
13168   if (prefixes & PREFIX_REPNZ)
13169     all_prefixes[last_repnz_prefix] = BND_PREFIX;
13170 }
13171
13172 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13173    "notrack".  */
13174
13175 static void
13176 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13177                int sizeflag ATTRIBUTE_UNUSED)
13178 {
13179
13180   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13181      we've seen a PREFIX_DS.  */
13182   if ((prefixes & PREFIX_DS) != 0
13183       && (address_mode != mode_64bit || last_data_prefix < 0))
13184     {
13185       /* NOTRACK prefix is only valid on indirect branch instructions.
13186          NB: DATA prefix is unsupported for Intel64.  */
13187       active_seg_prefix = 0;
13188       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13189     }
13190 }
13191
13192 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13193    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13194  */
13195
13196 static void
13197 HLE_Fixup1 (int bytemode, int sizeflag)
13198 {
13199   if (modrm.mod != 3
13200       && (prefixes & PREFIX_LOCK) != 0)
13201     {
13202       if (prefixes & PREFIX_REPZ)
13203         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13204       if (prefixes & PREFIX_REPNZ)
13205         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13206     }
13207
13208   OP_E (bytemode, sizeflag);
13209 }
13210
13211 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13212    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13213  */
13214
13215 static void
13216 HLE_Fixup2 (int bytemode, int sizeflag)
13217 {
13218   if (modrm.mod != 3)
13219     {
13220       if (prefixes & PREFIX_REPZ)
13221         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13222       if (prefixes & PREFIX_REPNZ)
13223         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13224     }
13225
13226   OP_E (bytemode, sizeflag);
13227 }
13228
13229 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13230    "xrelease" for memory operand.  No check for LOCK prefix.   */
13231
13232 static void
13233 HLE_Fixup3 (int bytemode, int sizeflag)
13234 {
13235   if (modrm.mod != 3
13236       && last_repz_prefix > last_repnz_prefix
13237       && (prefixes & PREFIX_REPZ) != 0)
13238     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13239
13240   OP_E (bytemode, sizeflag);
13241 }
13242
13243 static void
13244 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13245 {
13246   USED_REX (REX_W);
13247   if (rex & REX_W)
13248     {
13249       /* Change cmpxchg8b to cmpxchg16b.  */
13250       char *p = mnemonicendp - 2;
13251       mnemonicendp = stpcpy (p, "16b");
13252       bytemode = o_mode;
13253     }
13254   else if ((prefixes & PREFIX_LOCK) != 0)
13255     {
13256       if (prefixes & PREFIX_REPZ)
13257         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13258       if (prefixes & PREFIX_REPNZ)
13259         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13260     }
13261
13262   OP_M (bytemode, sizeflag);
13263 }
13264
13265 static void
13266 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13267 {
13268   const char **names;
13269
13270   if (need_vex)
13271     {
13272       switch (vex.length)
13273         {
13274         case 128:
13275           names = names_xmm;
13276           break;
13277         case 256:
13278           names = names_ymm;
13279           break;
13280         default:
13281           abort ();
13282         }
13283     }
13284   else
13285     names = names_xmm;
13286   oappend (names[reg]);
13287 }
13288
13289 static void
13290 FXSAVE_Fixup (int bytemode, int sizeflag)
13291 {
13292   /* Add proper suffix to "fxsave" and "fxrstor".  */
13293   USED_REX (REX_W);
13294   if (rex & REX_W)
13295     {
13296       char *p = mnemonicendp;
13297       *p++ = '6';
13298       *p++ = '4';
13299       *p = '\0';
13300       mnemonicendp = p;
13301     }
13302   OP_M (bytemode, sizeflag);
13303 }
13304
13305 /* Display the destination register operand for instructions with
13306    VEX. */
13307
13308 static void
13309 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13310 {
13311   int reg;
13312   const char **names;
13313
13314   if (!need_vex)
13315     abort ();
13316
13317   reg = vex.register_specifier;
13318   vex.register_specifier = 0;
13319   if (address_mode != mode_64bit)
13320     reg &= 7;
13321   else if (vex.evex && !vex.v)
13322     reg += 16;
13323
13324   if (bytemode == vex_scalar_mode)
13325     {
13326       oappend (names_xmm[reg]);
13327       return;
13328     }
13329
13330   if (bytemode == tmm_mode)
13331     {
13332       /* All 3 TMM registers must be distinct.  */
13333       if (reg >= 8)
13334         oappend ("(bad)");
13335       else
13336         {
13337           /* This must be the 3rd operand.  */
13338           if (obufp != op_out[2])
13339             abort ();
13340           oappend (names_tmm[reg]);
13341           if (reg == modrm.reg || reg == modrm.rm)
13342             strcpy (obufp, "/(bad)");
13343         }
13344
13345       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13346         {
13347           if (modrm.reg <= 8
13348               && (modrm.reg == modrm.rm || modrm.reg == reg))
13349             strcat (op_out[0], "/(bad)");
13350           if (modrm.rm <= 8
13351               && (modrm.rm == modrm.reg || modrm.rm == reg))
13352             strcat (op_out[1], "/(bad)");
13353         }
13354
13355       return;
13356     }
13357
13358   switch (vex.length)
13359     {
13360     case 128:
13361       switch (bytemode)
13362         {
13363         case vex_mode:
13364         case vex_vsib_q_w_dq_mode:
13365           names = names_xmm;
13366           break;
13367         case dq_mode:
13368           if (rex & REX_W)
13369             names = names64;
13370           else
13371             names = names32;
13372           break;
13373         case mask_bd_mode:
13374         case mask_mode:
13375           if (reg > 0x7)
13376             {
13377               oappend ("(bad)");
13378               return;
13379             }
13380           names = names_mask;
13381           break;
13382         default:
13383           abort ();
13384           return;
13385         }
13386       break;
13387     case 256:
13388       switch (bytemode)
13389         {
13390         case vex_mode:
13391           names = names_ymm;
13392           break;
13393         case vex_vsib_q_w_dq_mode:
13394           names = vex.w ? names_ymm : names_xmm;
13395           break;
13396         case mask_bd_mode:
13397         case mask_mode:
13398           if (reg > 0x7)
13399             {
13400               oappend ("(bad)");
13401               return;
13402             }
13403           names = names_mask;
13404           break;
13405         default:
13406           /* See PR binutils/20893 for a reproducer.  */
13407           oappend ("(bad)");
13408           return;
13409         }
13410       break;
13411     case 512:
13412       names = names_zmm;
13413       break;
13414     default:
13415       abort ();
13416       break;
13417     }
13418   oappend (names[reg]);
13419 }
13420
13421 static void
13422 OP_VexR (int bytemode, int sizeflag)
13423 {
13424   if (modrm.mod == 3)
13425     OP_VEX (bytemode, sizeflag);
13426 }
13427
13428 static void
13429 OP_VexW (int bytemode, int sizeflag)
13430 {
13431   OP_VEX (bytemode, sizeflag);
13432
13433   if (vex.w)
13434     {
13435       /* Swap 2nd and 3rd operands.  */
13436       strcpy (scratchbuf, op_out[2]);
13437       strcpy (op_out[2], op_out[1]);
13438       strcpy (op_out[1], scratchbuf);
13439     }
13440 }
13441
13442 static void
13443 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13444 {
13445   int reg;
13446   const char **names = names_xmm;
13447
13448   FETCH_DATA (the_info, codep + 1);
13449   reg = *codep++;
13450
13451   if (bytemode != x_mode && bytemode != scalar_mode)
13452     abort ();
13453
13454   reg >>= 4;
13455   if (address_mode != mode_64bit)
13456     reg &= 7;
13457
13458   if (bytemode == x_mode && vex.length == 256)
13459     names = names_ymm;
13460
13461   oappend (names[reg]);
13462
13463   if (vex.w)
13464     {
13465       /* Swap 3rd and 4th operands.  */
13466       strcpy (scratchbuf, op_out[3]);
13467       strcpy (op_out[3], op_out[2]);
13468       strcpy (op_out[2], scratchbuf);
13469     }
13470 }
13471
13472 static void
13473 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13474           int sizeflag ATTRIBUTE_UNUSED)
13475 {
13476   scratchbuf[0] = '$';
13477   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13478   oappend_maybe_intel (scratchbuf);
13479 }
13480
13481 static void
13482 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13483              int sizeflag ATTRIBUTE_UNUSED)
13484 {
13485   unsigned int cmp_type;
13486
13487   if (!vex.evex)
13488     abort ();
13489
13490   FETCH_DATA (the_info, codep + 1);
13491   cmp_type = *codep++ & 0xff;
13492   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13493      If it's the case, print suffix, otherwise - print the immediate.  */
13494   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13495       && cmp_type != 3
13496       && cmp_type != 7)
13497     {
13498       char suffix [3];
13499       char *p = mnemonicendp - 2;
13500
13501       /* vpcmp* can have both one- and two-lettered suffix.  */
13502       if (p[0] == 'p')
13503         {
13504           p++;
13505           suffix[0] = p[0];
13506           suffix[1] = '\0';
13507         }
13508       else
13509         {
13510           suffix[0] = p[0];
13511           suffix[1] = p[1];
13512           suffix[2] = '\0';
13513         }
13514
13515       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13516       mnemonicendp += simd_cmp_op[cmp_type].len;
13517     }
13518   else
13519     {
13520       /* We have a reserved extension byte.  Output it directly.  */
13521       scratchbuf[0] = '$';
13522       print_operand_value (scratchbuf + 1, 1, cmp_type);
13523       oappend_maybe_intel (scratchbuf);
13524       scratchbuf[0] = '\0';
13525     }
13526 }
13527
13528 static const struct op xop_cmp_op[] =
13529 {
13530   { STRING_COMMA_LEN ("lt") },
13531   { STRING_COMMA_LEN ("le") },
13532   { STRING_COMMA_LEN ("gt") },
13533   { STRING_COMMA_LEN ("ge") },
13534   { STRING_COMMA_LEN ("eq") },
13535   { STRING_COMMA_LEN ("neq") },
13536   { STRING_COMMA_LEN ("false") },
13537   { STRING_COMMA_LEN ("true") }
13538 };
13539
13540 static void
13541 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13542              int sizeflag ATTRIBUTE_UNUSED)
13543 {
13544   unsigned int cmp_type;
13545
13546   FETCH_DATA (the_info, codep + 1);
13547   cmp_type = *codep++ & 0xff;
13548   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13549     {
13550       char suffix[3];
13551       char *p = mnemonicendp - 2;
13552
13553       /* vpcom* can have both one- and two-lettered suffix.  */
13554       if (p[0] == 'm')
13555         {
13556           p++;
13557           suffix[0] = p[0];
13558           suffix[1] = '\0';
13559         }
13560       else
13561         {
13562           suffix[0] = p[0];
13563           suffix[1] = p[1];
13564           suffix[2] = '\0';
13565         }
13566
13567       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13568       mnemonicendp += xop_cmp_op[cmp_type].len;
13569     }
13570   else
13571     {
13572       /* We have a reserved extension byte.  Output it directly.  */
13573       scratchbuf[0] = '$';
13574       print_operand_value (scratchbuf + 1, 1, cmp_type);
13575       oappend_maybe_intel (scratchbuf);
13576       scratchbuf[0] = '\0';
13577     }
13578 }
13579
13580 static const struct op pclmul_op[] =
13581 {
13582   { STRING_COMMA_LEN ("lql") },
13583   { STRING_COMMA_LEN ("hql") },
13584   { STRING_COMMA_LEN ("lqh") },
13585   { STRING_COMMA_LEN ("hqh") }
13586 };
13587
13588 static void
13589 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13590               int sizeflag ATTRIBUTE_UNUSED)
13591 {
13592   unsigned int pclmul_type;
13593
13594   FETCH_DATA (the_info, codep + 1);
13595   pclmul_type = *codep++ & 0xff;
13596   switch (pclmul_type)
13597     {
13598     case 0x10:
13599       pclmul_type = 2;
13600       break;
13601     case 0x11:
13602       pclmul_type = 3;
13603       break;
13604     default:
13605       break;
13606     }
13607   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13608     {
13609       char suffix [4];
13610       char *p = mnemonicendp - 3;
13611       suffix[0] = p[0];
13612       suffix[1] = p[1];
13613       suffix[2] = p[2];
13614       suffix[3] = '\0';
13615       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13616       mnemonicendp += pclmul_op[pclmul_type].len;
13617     }
13618   else
13619     {
13620       /* We have a reserved extension byte.  Output it directly.  */
13621       scratchbuf[0] = '$';
13622       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13623       oappend_maybe_intel (scratchbuf);
13624       scratchbuf[0] = '\0';
13625     }
13626 }
13627
13628 static void
13629 MOVSXD_Fixup (int bytemode, int sizeflag)
13630 {
13631   /* Add proper suffix to "movsxd".  */
13632   char *p = mnemonicendp;
13633
13634   switch (bytemode)
13635     {
13636     case movsxd_mode:
13637       if (intel_syntax)
13638         {
13639           *p++ = 'x';
13640           *p++ = 'd';
13641           goto skip;
13642         }
13643
13644       USED_REX (REX_W);
13645       if (rex & REX_W)
13646         {
13647           *p++ = 'l';
13648           *p++ = 'q';
13649         }
13650       else
13651         {
13652           *p++ = 'x';
13653           *p++ = 'd';
13654         }
13655       break;
13656     default:
13657       oappend (INTERNAL_DISASSEMBLER_ERROR);
13658       break;
13659     }
13660
13661  skip:
13662   mnemonicendp = p;
13663   *p = '\0';
13664   OP_E (bytemode, sizeflag);
13665 }
13666
13667 static void
13668 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13669 {
13670   if (!vex.evex
13671       || (bytemode != mask_mode && bytemode != mask_bd_mode))
13672     abort ();
13673
13674   USED_REX (REX_R);
13675   if ((rex & REX_R) != 0 || !vex.r)
13676     {
13677       BadOp ();
13678       return;
13679     }
13680
13681   oappend (names_mask [modrm.reg]);
13682 }
13683
13684 static void
13685 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13686 {
13687   if (modrm.mod == 3 && vex.b)
13688     switch (bytemode)
13689       {
13690       case evex_rounding_64_mode:
13691         if (address_mode != mode_64bit)
13692           {
13693             oappend ("(bad)");
13694             break;
13695           }
13696         /* Fall through.  */
13697       case evex_rounding_mode:
13698         oappend (names_rounding[vex.ll]);
13699         break;
13700       case evex_sae_mode:
13701         oappend ("{sae}");
13702         break;
13703       default:
13704         abort ();
13705         break;
13706       }
13707 }