opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void BND_Fixup (int, int);
 111 static void NOTRACK_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void PCMPESTR_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define EbndS { OP_E, bnd_swap_mode }
 250 #define Ev { OP_E, v_mode }
 251 #define Eva { OP_E, va_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mv_bnd { OP_M, v_bndmk_mode }
 275 #define Mx { OP_M, x_mode }
 276 #define Mxmm { OP_M, xmm_mode }
 277 #define Gb { OP_G, b_mode }
 278 #define Gbnd { OP_G, bnd_mode }
 279 #define Gv { OP_G, v_mode }
 280 #define Gd { OP_G, d_mode }
 281 #define Gdq { OP_G, dq_mode }
 282 #define Gm { OP_G, m_mode }
 283 #define Gva { OP_G, va_mode }
 284 #define Gw { OP_G, w_mode }
 285 #define Rd { OP_R, d_mode }
 286 #define Rdq { OP_R, dq_mode }
 287 #define Rm { OP_R, m_mode }
 288 #define Ib { OP_I, b_mode }
 289 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 290 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 291 #define Iv { OP_I, v_mode }
 292 #define sIv { OP_sI, v_mode }
 293 #define Iv64 { OP_I64, v_mode }
 294 #define Id { OP_I, d_mode }
 295 #define Iw { OP_I, w_mode }
 296 #define I1 { OP_I, const_1_mode }
 297 #define Jb { OP_J, b_mode }
 298 #define Jv { OP_J, v_mode }
 299 #define Cm { OP_C, m_mode }
 300 #define Dm { OP_D, m_mode }
 301 #define Td { OP_T, d_mode }
 302 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 303
 304 #define RMeAX { OP_REG, eAX_reg }
 305 #define RMeBX { OP_REG, eBX_reg }
 306 #define RMeCX { OP_REG, eCX_reg }
 307 #define RMeDX { OP_REG, eDX_reg }
 308 #define RMeSP { OP_REG, eSP_reg }
 309 #define RMeBP { OP_REG, eBP_reg }
 310 #define RMeSI { OP_REG, eSI_reg }
 311 #define RMeDI { OP_REG, eDI_reg }
 312 #define RMrAX { OP_REG, rAX_reg }
 313 #define RMrBX { OP_REG, rBX_reg }
 314 #define RMrCX { OP_REG, rCX_reg }
 315 #define RMrDX { OP_REG, rDX_reg }
 316 #define RMrSP { OP_REG, rSP_reg }
 317 #define RMrBP { OP_REG, rBP_reg }
 318 #define RMrSI { OP_REG, rSI_reg }
 319 #define RMrDI { OP_REG, rDI_reg }
 320 #define RMAL { OP_REG, al_reg }
 321 #define RMCL { OP_REG, cl_reg }
 322 #define RMDL { OP_REG, dl_reg }
 323 #define RMBL { OP_REG, bl_reg }
 324 #define RMAH { OP_REG, ah_reg }
 325 #define RMCH { OP_REG, ch_reg }
 326 #define RMDH { OP_REG, dh_reg }
 327 #define RMBH { OP_REG, bh_reg }
 328 #define RMAX { OP_REG, ax_reg }
 329 #define RMDX { OP_REG, dx_reg }
 330
 331 #define eAX { OP_IMREG, eAX_reg }
 332 #define eBX { OP_IMREG, eBX_reg }
 333 #define eCX { OP_IMREG, eCX_reg }
 334 #define eDX { OP_IMREG, eDX_reg }
 335 #define eSP { OP_IMREG, eSP_reg }
 336 #define eBP { OP_IMREG, eBP_reg }
 337 #define eSI { OP_IMREG, eSI_reg }
 338 #define eDI { OP_IMREG, eDI_reg }
 339 #define AL { OP_IMREG, al_reg }
 340 #define CL { OP_IMREG, cl_reg }
 341 #define DL { OP_IMREG, dl_reg }
 342 #define BL { OP_IMREG, bl_reg }
 343 #define AH { OP_IMREG, ah_reg }
 344 #define CH { OP_IMREG, ch_reg }
 345 #define DH { OP_IMREG, dh_reg }
 346 #define BH { OP_IMREG, bh_reg }
 347 #define AX { OP_IMREG, ax_reg }
 348 #define DX { OP_IMREG, dx_reg }
 349 #define zAX { OP_IMREG, z_mode_ax_reg }
 350 #define indirDX { OP_IMREG, indir_dx_reg }
 351
 352 #define Sw { OP_SEG, w_mode }
 353 #define Sv { OP_SEG, v_mode }
 354 #define Ap { OP_DIR, 0 }
 355 #define Ob { OP_OFF64, b_mode }
 356 #define Ov { OP_OFF64, v_mode }
 357 #define Xb { OP_DSreg, eSI_reg }
 358 #define Xv { OP_DSreg, eSI_reg }
 359 #define Xz { OP_DSreg, eSI_reg }
 360 #define Yb { OP_ESreg, eDI_reg }
 361 #define Yv { OP_ESreg, eDI_reg }
 362 #define DSBX { OP_DSreg, eBX_reg }
 363
 364 #define es { OP_REG, es_reg }
 365 #define ss { OP_REG, ss_reg }
 366 #define cs { OP_REG, cs_reg }
 367 #define ds { OP_REG, ds_reg }
 368 #define fs { OP_REG, fs_reg }
 369 #define gs { OP_REG, gs_reg }
 370
 371 #define MX { OP_MMX, 0 }
 372 #define XM { OP_XMM, 0 }
 373 #define XMScalar { OP_XMM, scalar_mode }
 374 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 375 #define XMM { OP_XMM, xmm_mode }
 376 #define XMxmmq { OP_XMM, xmmq_mode }
 377 #define EM { OP_EM, v_mode }
 378 #define EMS { OP_EM, v_swap_mode }
 379 #define EMd { OP_EM, d_mode }
 380 #define EMx { OP_EM, x_mode }
 381 #define EXbScalar { OP_EX, b_scalar_mode }
 382 #define EXw { OP_EX, w_mode }
 383 #define EXwScalar { OP_EX, w_scalar_mode }
 384 #define EXd { OP_EX, d_mode }
 385 #define EXdScalar { OP_EX, d_scalar_mode }
 386 #define EXdS { OP_EX, d_swap_mode }
 387 #define EXq { OP_EX, q_mode }
 388 #define EXqScalar { OP_EX, q_scalar_mode }
 389 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 390 #define EXqS { OP_EX, q_swap_mode }
 391 #define EXx { OP_EX, x_mode }
 392 #define EXxS { OP_EX, x_swap_mode }
 393 #define EXxmm { OP_EX, xmm_mode }
 394 #define EXymm { OP_EX, ymm_mode }
 395 #define EXxmmq { OP_EX, xmmq_mode }
 396 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 397 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 398 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 399 #define EXxmm_md { OP_EX, xmm_md_mode }
 400 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 401 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 402 #define EXxmmdw { OP_EX, xmmdw_mode }
 403 #define EXxmmqd { OP_EX, xmmqd_mode }
 404 #define EXymmq { OP_EX, ymmq_mode }
 405 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 406 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 407 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 408 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 409 #define MS { OP_MS, v_mode }
 410 #define XS { OP_XS, v_mode }
 411 #define EMCq { OP_EMC, q_mode }
 412 #define MXC { OP_MXC, 0 }
 413 #define OPSUF { OP_3DNowSuffix, 0 }
 414 #define CMP { CMP_Fixup, 0 }
 415 #define XMM0 { XMM_Fixup, 0 }
 416 #define FXSAVE { FXSAVE_Fixup, 0 }
 417 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 418 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 419
 420 #define Vex { OP_VEX, vex_mode }
 421 #define VexScalar { OP_VEX, vex_scalar_mode }
 422 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 423 #define Vex128 { OP_VEX, vex128_mode }
 424 #define Vex256 { OP_VEX, vex256_mode }
 425 #define VexGdq { OP_VEX, dq_mode }
 426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 428 #define EXVexW { OP_EX_VexW, x_mode }
 429 #define EXdVexW { OP_EX_VexW, d_mode }
 430 #define EXqVexW { OP_EX_VexW, q_mode }
 431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 432 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 433 #define XMVexW { OP_XMM_VexW, 0 }
 434 #define XMVexI4 { OP_REG_VexI4, x_mode }
 435 #define PCLMUL { PCLMUL_Fixup, 0 }
 436 #define VCMP { VCMP_Fixup, 0 }
 437 #define VPCMP { VPCMP_Fixup, 0 }
 438 #define VPCOM { VPCOM_Fixup, 0 }
 439
 440 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 441 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 443
 444 #define XMask { OP_Mask, mask_mode }
 445 #define MaskG { OP_G, mask_mode }
 446 #define MaskE { OP_E, mask_mode }
 447 #define MaskBDE { OP_E, mask_bd_mode }
 448 #define MaskR { OP_R, mask_mode }
 449 #define MaskVex { OP_VEX, mask_mode }
 450
 451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 455
 456 /* Used handle "rep" prefix for string instructions.  */
 457 #define Xbr { REP_Fixup, eSI_reg }
 458 #define Xvr { REP_Fixup, eSI_reg }
 459 #define Ybr { REP_Fixup, eDI_reg }
 460 #define Yvr { REP_Fixup, eDI_reg }
 461 #define Yzr { REP_Fixup, eDI_reg }
 462 #define indirDXr { REP_Fixup, indir_dx_reg }
 463 #define ALr { REP_Fixup, al_reg }
 464 #define eAXr { REP_Fixup, eAX_reg }
 465
 466 /* Used handle HLE prefix for lockable instructions.  */
 467 #define Ebh1 { HLE_Fixup1, b_mode }
 468 #define Evh1 { HLE_Fixup1, v_mode }
 469 #define Ebh2 { HLE_Fixup2, b_mode }
 470 #define Evh2 { HLE_Fixup2, v_mode }
 471 #define Ebh3 { HLE_Fixup3, b_mode }
 472 #define Evh3 { HLE_Fixup3, v_mode }
 473
 474 #define BND { BND_Fixup, 0 }
 475 #define NOTRACK { NOTRACK_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* operand size depends on address prefix */
 498   va_mode,
 499   /* word operand */
 500   w_mode,
 501   /* double word operand  */
 502   d_mode,
 503   /* double word operand with operand swapped */
 504   d_swap_mode,
 505   /* quad word operand */
 506   q_mode,
 507   /* quad word operand with operand swapped */
 508   q_swap_mode,
 509   /* ten-byte operand */
 510   t_mode,
 511   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 512      broadcast enabled.  */
 513   x_mode,
 514   /* Similar to x_mode, but with different EVEX mem shifts.  */
 515   evex_x_gscat_mode,
 516   /* Similar to x_mode, but with disabled broadcast.  */
 517   evex_x_nobcst_mode,
 518   /* Similar to x_mode, but with operands swapped and disabled broadcast
 519      in EVEX.  */
 520   x_swap_mode,
 521   /* 16-byte XMM operand */
 522   xmm_mode,
 523   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 524      memory operand (depending on vector length).  Broadcast isn't
 525      allowed.  */
 526   xmmq_mode,
 527   /* Same as xmmq_mode, but broadcast is allowed.  */
 528   evex_half_bcst_xmmq_mode,
 529   /* XMM register or byte memory operand */
 530   xmm_mb_mode,
 531   /* XMM register or word memory operand */
 532   xmm_mw_mode,
 533   /* XMM register or double word memory operand */
 534   xmm_md_mode,
 535   /* XMM register or quad word memory operand */
 536   xmm_mq_mode,
 537   /* XMM register or double/quad word memory operand, depending on
 538      VEX.W.  */
 539   xmm_mdq_mode,
 540   /* 16-byte XMM, word, double word or quad word operand.  */
 541   xmmdw_mode,
 542   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 543   xmmqd_mode,
 544   /* 32-byte YMM operand */
 545   ymm_mode,
 546   /* quad word, ymmword or zmmword memory operand.  */
 547   ymmq_mode,
 548   /* 32-byte YMM or 16-byte word operand */
 549   ymmxmm_mode,
 550   /* d_mode in 32bit, q_mode in 64bit mode.  */
 551   m_mode,
 552   /* pair of v_mode operands */
 553   a_mode,
 554   cond_jump_mode,
 555   loop_jcxz_mode,
 556   v_bnd_mode,
 557   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 558   v_bndmk_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode.  */
 562   dqw_mode,
 563   /* bounds operand */
 564   bnd_mode,
 565   /* bounds operand with operand swapped */
 566   bnd_swap_mode,
 567   /* 4- or 6-byte pointer operand */
 568   f_mode,
 569   const_1_mode,
 570   /* v_mode for indirect branch opcodes.  */
 571   indir_v_mode,
 572   /* v_mode for stack-related opcodes.  */
 573   stack_v_mode,
 574   /* non-quad operand size depends on prefixes */
 575   z_mode,
 576   /* 16-byte operand */
 577   o_mode,
 578   /* registers like dq_mode, memory like b_mode.  */
 579   dqb_mode,
 580   /* registers like d_mode, memory like b_mode.  */
 581   db_mode,
 582   /* registers like d_mode, memory like w_mode.  */
 583   dw_mode,
 584   /* registers like dq_mode, memory like d_mode.  */
 585   dqd_mode,
 586   /* normal vex mode */
 587   vex_mode,
 588   /* 128bit vex mode */
 589   vex128_mode,
 590   /* 256bit vex mode */
 591   vex256_mode,
 592   /* operand size depends on the VEX.W bit.  */
 593   vex_w_dq_mode,
 594
 595   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 596   vex_vsib_d_w_dq_mode,
 597   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 598   vex_vsib_d_w_d_mode,
 599   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 600   vex_vsib_q_w_dq_mode,
 601   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 602   vex_vsib_q_w_d_mode,
 603
 604   /* scalar, ignore vector length.  */
 605   scalar_mode,
 606   /* like b_mode, ignore vector length.  */
 607   b_scalar_mode,
 608   /* like w_mode, ignore vector length.  */
 609   w_scalar_mode,
 610   /* like d_mode, ignore vector length.  */
 611   d_scalar_mode,
 612   /* like d_swap_mode, ignore vector length.  */
 613   d_scalar_swap_mode,
 614   /* like q_mode, ignore vector length.  */
 615   q_scalar_mode,
 616   /* like q_swap_mode, ignore vector length.  */
 617   q_scalar_swap_mode,
 618   /* like vex_mode, ignore vector length.  */
 619   vex_scalar_mode,
 620   /* like vex_w_dq_mode, ignore vector length.  */
 621   vex_scalar_w_dq_mode,
 622
 623   /* Static rounding.  */
 624   evex_rounding_mode,
 625   /* Static rounding, 64-bit mode only.  */
 626   evex_rounding_64_mode,
 627   /* Supress all exceptions.  */
 628   evex_sae_mode,
 629
 630   /* Mask register operand.  */
 631   mask_mode,
 632   /* Mask register operand.  */
 633   mask_bd_mode,
 634
 635   es_reg,
 636   cs_reg,
 637   ss_reg,
 638   ds_reg,
 639   fs_reg,
 640   gs_reg,
 641
 642   eAX_reg,
 643   eCX_reg,
 644   eDX_reg,
 645   eBX_reg,
 646   eSP_reg,
 647   eBP_reg,
 648   eSI_reg,
 649   eDI_reg,
 650
 651   al_reg,
 652   cl_reg,
 653   dl_reg,
 654   bl_reg,
 655   ah_reg,
 656   ch_reg,
 657   dh_reg,
 658   bh_reg,
 659
 660   ax_reg,
 661   cx_reg,
 662   dx_reg,
 663   bx_reg,
 664   sp_reg,
 665   bp_reg,
 666   si_reg,
 667   di_reg,
 668
 669   rAX_reg,
 670   rCX_reg,
 671   rDX_reg,
 672   rBX_reg,
 673   rSP_reg,
 674   rBP_reg,
 675   rSI_reg,
 676   rDI_reg,
 677
 678   z_mode_ax_reg,
 679   indir_dx_reg
 680 };
 681
 682 enum
 683 {
 684   FLOATCODE = 1,
 685   USE_REG_TABLE,
 686   USE_MOD_TABLE,
 687   USE_RM_TABLE,
 688   USE_PREFIX_TABLE,
 689   USE_X86_64_TABLE,
 690   USE_3BYTE_TABLE,
 691   USE_XOP_8F_TABLE,
 692   USE_VEX_C4_TABLE,
 693   USE_VEX_C5_TABLE,
 694   USE_VEX_LEN_TABLE,
 695   USE_VEX_W_TABLE,
 696   USE_EVEX_TABLE,
 697   USE_EVEX_LEN_TABLE
 698 };
 699
 700 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 701
 702 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 703 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 704 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 705 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 706 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 707 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 708 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 709 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 710 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 711 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 712 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 713 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 714 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 715 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 716 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 717 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 718
 719 enum
 720 {
 721   REG_80 = 0,
 722   REG_81,
 723   REG_83,
 724   REG_8F,
 725   REG_C0,
 726   REG_C1,
 727   REG_C6,
 728   REG_C7,
 729   REG_D0,
 730   REG_D1,
 731   REG_D2,
 732   REG_D3,
 733   REG_F6,
 734   REG_F7,
 735   REG_FE,
 736   REG_FF,
 737   REG_0F00,
 738   REG_0F01,
 739   REG_0F0D,
 740   REG_0F18,
 741   REG_0F1C_P_0_MOD_0,
 742   REG_0F1E_P_1_MOD_3,
 743   REG_0F71,
 744   REG_0F72,
 745   REG_0F73,
 746   REG_0FA6,
 747   REG_0FA7,
 748   REG_0FAE,
 749   REG_0FBA,
 750   REG_0FC7,
 751   REG_VEX_0F71,
 752   REG_VEX_0F72,
 753   REG_VEX_0F73,
 754   REG_VEX_0FAE,
 755   REG_VEX_0F38F3,
 756   REG_XOP_LWPCB,
 757   REG_XOP_LWP,
 758   REG_XOP_TBM_01,
 759   REG_XOP_TBM_02,
 760
 761   REG_EVEX_0F71,
 762   REG_EVEX_0F72,
 763   REG_EVEX_0F73,
 764   REG_EVEX_0F38C6,
 765   REG_EVEX_0F38C7
 766 };
 767
 768 enum
 769 {
 770   MOD_8D = 0,
 771   MOD_C6_REG_7,
 772   MOD_C7_REG_7,
 773   MOD_FF_REG_3,
 774   MOD_FF_REG_5,
 775   MOD_0F01_REG_0,
 776   MOD_0F01_REG_1,
 777   MOD_0F01_REG_2,
 778   MOD_0F01_REG_3,
 779   MOD_0F01_REG_5,
 780   MOD_0F01_REG_7,
 781   MOD_0F12_PREFIX_0,
 782   MOD_0F13,
 783   MOD_0F16_PREFIX_0,
 784   MOD_0F17,
 785   MOD_0F18_REG_0,
 786   MOD_0F18_REG_1,
 787   MOD_0F18_REG_2,
 788   MOD_0F18_REG_3,
 789   MOD_0F18_REG_4,
 790   MOD_0F18_REG_5,
 791   MOD_0F18_REG_6,
 792   MOD_0F18_REG_7,
 793   MOD_0F1A_PREFIX_0,
 794   MOD_0F1B_PREFIX_0,
 795   MOD_0F1B_PREFIX_1,
 796   MOD_0F1C_PREFIX_0,
 797   MOD_0F1E_PREFIX_1,
 798   MOD_0F24,
 799   MOD_0F26,
 800   MOD_0F2B_PREFIX_0,
 801   MOD_0F2B_PREFIX_1,
 802   MOD_0F2B_PREFIX_2,
 803   MOD_0F2B_PREFIX_3,
 804   MOD_0F51,
 805   MOD_0F71_REG_2,
 806   MOD_0F71_REG_4,
 807   MOD_0F71_REG_6,
 808   MOD_0F72_REG_2,
 809   MOD_0F72_REG_4,
 810   MOD_0F72_REG_6,
 811   MOD_0F73_REG_2,
 812   MOD_0F73_REG_3,
 813   MOD_0F73_REG_6,
 814   MOD_0F73_REG_7,
 815   MOD_0FAE_REG_0,
 816   MOD_0FAE_REG_1,
 817   MOD_0FAE_REG_2,
 818   MOD_0FAE_REG_3,
 819   MOD_0FAE_REG_4,
 820   MOD_0FAE_REG_5,
 821   MOD_0FAE_REG_6,
 822   MOD_0FAE_REG_7,
 823   MOD_0FB2,
 824   MOD_0FB4,
 825   MOD_0FB5,
 826   MOD_0FC3,
 827   MOD_0FC7_REG_3,
 828   MOD_0FC7_REG_4,
 829   MOD_0FC7_REG_5,
 830   MOD_0FC7_REG_6,
 831   MOD_0FC7_REG_7,
 832   MOD_0FD7,
 833   MOD_0FE7_PREFIX_2,
 834   MOD_0FF0_PREFIX_3,
 835   MOD_0F382A_PREFIX_2,
 836   MOD_0F38F5_PREFIX_2,
 837   MOD_0F38F6_PREFIX_0,
 838   MOD_0F38F8_PREFIX_1,
 839   MOD_0F38F8_PREFIX_2,
 840   MOD_0F38F8_PREFIX_3,
 841   MOD_0F38F9_PREFIX_0,
 842   MOD_62_32BIT,
 843   MOD_C4_32BIT,
 844   MOD_C5_32BIT,
 845   MOD_VEX_0F12_PREFIX_0,
 846   MOD_VEX_0F13,
 847   MOD_VEX_0F16_PREFIX_0,
 848   MOD_VEX_0F17,
 849   MOD_VEX_0F2B,
 850   MOD_VEX_W_0_0F41_P_0_LEN_1,
 851   MOD_VEX_W_1_0F41_P_0_LEN_1,
 852   MOD_VEX_W_0_0F41_P_2_LEN_1,
 853   MOD_VEX_W_1_0F41_P_2_LEN_1,
 854   MOD_VEX_W_0_0F42_P_0_LEN_1,
 855   MOD_VEX_W_1_0F42_P_0_LEN_1,
 856   MOD_VEX_W_0_0F42_P_2_LEN_1,
 857   MOD_VEX_W_1_0F42_P_2_LEN_1,
 858   MOD_VEX_W_0_0F44_P_0_LEN_1,
 859   MOD_VEX_W_1_0F44_P_0_LEN_1,
 860   MOD_VEX_W_0_0F44_P_2_LEN_1,
 861   MOD_VEX_W_1_0F44_P_2_LEN_1,
 862   MOD_VEX_W_0_0F45_P_0_LEN_1,
 863   MOD_VEX_W_1_0F45_P_0_LEN_1,
 864   MOD_VEX_W_0_0F45_P_2_LEN_1,
 865   MOD_VEX_W_1_0F45_P_2_LEN_1,
 866   MOD_VEX_W_0_0F46_P_0_LEN_1,
 867   MOD_VEX_W_1_0F46_P_0_LEN_1,
 868   MOD_VEX_W_0_0F46_P_2_LEN_1,
 869   MOD_VEX_W_1_0F46_P_2_LEN_1,
 870   MOD_VEX_W_0_0F47_P_0_LEN_1,
 871   MOD_VEX_W_1_0F47_P_0_LEN_1,
 872   MOD_VEX_W_0_0F47_P_2_LEN_1,
 873   MOD_VEX_W_1_0F47_P_2_LEN_1,
 874   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 875   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 876   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 877   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 878   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 879   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 880   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 881   MOD_VEX_0F50,
 882   MOD_VEX_0F71_REG_2,
 883   MOD_VEX_0F71_REG_4,
 884   MOD_VEX_0F71_REG_6,
 885   MOD_VEX_0F72_REG_2,
 886   MOD_VEX_0F72_REG_4,
 887   MOD_VEX_0F72_REG_6,
 888   MOD_VEX_0F73_REG_2,
 889   MOD_VEX_0F73_REG_3,
 890   MOD_VEX_0F73_REG_6,
 891   MOD_VEX_0F73_REG_7,
 892   MOD_VEX_W_0_0F91_P_0_LEN_0,
 893   MOD_VEX_W_1_0F91_P_0_LEN_0,
 894   MOD_VEX_W_0_0F91_P_2_LEN_0,
 895   MOD_VEX_W_1_0F91_P_2_LEN_0,
 896   MOD_VEX_W_0_0F92_P_0_LEN_0,
 897   MOD_VEX_W_0_0F92_P_2_LEN_0,
 898   MOD_VEX_0F92_P_3_LEN_0,
 899   MOD_VEX_W_0_0F93_P_0_LEN_0,
 900   MOD_VEX_W_0_0F93_P_2_LEN_0,
 901   MOD_VEX_0F93_P_3_LEN_0,
 902   MOD_VEX_W_0_0F98_P_0_LEN_0,
 903   MOD_VEX_W_1_0F98_P_0_LEN_0,
 904   MOD_VEX_W_0_0F98_P_2_LEN_0,
 905   MOD_VEX_W_1_0F98_P_2_LEN_0,
 906   MOD_VEX_W_0_0F99_P_0_LEN_0,
 907   MOD_VEX_W_1_0F99_P_0_LEN_0,
 908   MOD_VEX_W_0_0F99_P_2_LEN_0,
 909   MOD_VEX_W_1_0F99_P_2_LEN_0,
 910   MOD_VEX_0FAE_REG_2,
 911   MOD_VEX_0FAE_REG_3,
 912   MOD_VEX_0FD7_PREFIX_2,
 913   MOD_VEX_0FE7_PREFIX_2,
 914   MOD_VEX_0FF0_PREFIX_3,
 915   MOD_VEX_0F381A_PREFIX_2,
 916   MOD_VEX_0F382A_PREFIX_2,
 917   MOD_VEX_0F382C_PREFIX_2,
 918   MOD_VEX_0F382D_PREFIX_2,
 919   MOD_VEX_0F382E_PREFIX_2,
 920   MOD_VEX_0F382F_PREFIX_2,
 921   MOD_VEX_0F385A_PREFIX_2,
 922   MOD_VEX_0F388C_PREFIX_2,
 923   MOD_VEX_0F388E_PREFIX_2,
 924   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 925   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 926   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 927   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 928   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 929   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 930   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 931   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 932
 933   MOD_EVEX_0F12_PREFIX_0,
 934   MOD_EVEX_0F16_PREFIX_0,
 935   MOD_EVEX_0F38C6_REG_1,
 936   MOD_EVEX_0F38C6_REG_2,
 937   MOD_EVEX_0F38C6_REG_5,
 938   MOD_EVEX_0F38C6_REG_6,
 939   MOD_EVEX_0F38C7_REG_1,
 940   MOD_EVEX_0F38C7_REG_2,
 941   MOD_EVEX_0F38C7_REG_5,
 942   MOD_EVEX_0F38C7_REG_6
 943 };
 944
 945 enum
 946 {
 947   RM_C6_REG_7 = 0,
 948   RM_C7_REG_7,
 949   RM_0F01_REG_0,
 950   RM_0F01_REG_1,
 951   RM_0F01_REG_2,
 952   RM_0F01_REG_3,
 953   RM_0F01_REG_5_MOD_3,
 954   RM_0F01_REG_7_MOD_3,
 955   RM_0F1E_P_1_MOD_3_REG_7,
 956   RM_0FAE_REG_6_MOD_3_P_0,
 957   RM_0FAE_REG_7_MOD_3,
 958 };
 959
 960 enum
 961 {
 962   PREFIX_90 = 0,
 963   PREFIX_0F01_REG_5_MOD_0,
 964   PREFIX_0F01_REG_5_MOD_3_RM_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_2,
 966   PREFIX_0F01_REG_7_MOD_3_RM_2,
 967   PREFIX_0F01_REG_7_MOD_3_RM_3,
 968   PREFIX_0F09,
 969   PREFIX_0F10,
 970   PREFIX_0F11,
 971   PREFIX_0F12,
 972   PREFIX_0F16,
 973   PREFIX_0F1A,
 974   PREFIX_0F1B,
 975   PREFIX_0F1C,
 976   PREFIX_0F1E,
 977   PREFIX_0F2A,
 978   PREFIX_0F2B,
 979   PREFIX_0F2C,
 980   PREFIX_0F2D,
 981   PREFIX_0F2E,
 982   PREFIX_0F2F,
 983   PREFIX_0F51,
 984   PREFIX_0F52,
 985   PREFIX_0F53,
 986   PREFIX_0F58,
 987   PREFIX_0F59,
 988   PREFIX_0F5A,
 989   PREFIX_0F5B,
 990   PREFIX_0F5C,
 991   PREFIX_0F5D,
 992   PREFIX_0F5E,
 993   PREFIX_0F5F,
 994   PREFIX_0F60,
 995   PREFIX_0F61,
 996   PREFIX_0F62,
 997   PREFIX_0F6C,
 998   PREFIX_0F6D,
 999   PREFIX_0F6F,
1000   PREFIX_0F70,
1001   PREFIX_0F73_REG_3,
1002   PREFIX_0F73_REG_7,
1003   PREFIX_0F78,
1004   PREFIX_0F79,
1005   PREFIX_0F7C,
1006   PREFIX_0F7D,
1007   PREFIX_0F7E,
1008   PREFIX_0F7F,
1009   PREFIX_0FAE_REG_0_MOD_3,
1010   PREFIX_0FAE_REG_1_MOD_3,
1011   PREFIX_0FAE_REG_2_MOD_3,
1012   PREFIX_0FAE_REG_3_MOD_3,
1013   PREFIX_0FAE_REG_4_MOD_0,
1014   PREFIX_0FAE_REG_4_MOD_3,
1015   PREFIX_0FAE_REG_5_MOD_0,
1016   PREFIX_0FAE_REG_5_MOD_3,
1017   PREFIX_0FAE_REG_6_MOD_0,
1018   PREFIX_0FAE_REG_6_MOD_3,
1019   PREFIX_0FAE_REG_7_MOD_0,
1020   PREFIX_0FB8,
1021   PREFIX_0FBC,
1022   PREFIX_0FBD,
1023   PREFIX_0FC2,
1024   PREFIX_0FC3_MOD_0,
1025   PREFIX_0FC7_REG_6_MOD_0,
1026   PREFIX_0FC7_REG_6_MOD_3,
1027   PREFIX_0FC7_REG_7_MOD_3,
1028   PREFIX_0FD0,
1029   PREFIX_0FD6,
1030   PREFIX_0FE6,
1031   PREFIX_0FE7,
1032   PREFIX_0FF0,
1033   PREFIX_0FF7,
1034   PREFIX_0F3810,
1035   PREFIX_0F3814,
1036   PREFIX_0F3815,
1037   PREFIX_0F3817,
1038   PREFIX_0F3820,
1039   PREFIX_0F3821,
1040   PREFIX_0F3822,
1041   PREFIX_0F3823,
1042   PREFIX_0F3824,
1043   PREFIX_0F3825,
1044   PREFIX_0F3828,
1045   PREFIX_0F3829,
1046   PREFIX_0F382A,
1047   PREFIX_0F382B,
1048   PREFIX_0F3830,
1049   PREFIX_0F3831,
1050   PREFIX_0F3832,
1051   PREFIX_0F3833,
1052   PREFIX_0F3834,
1053   PREFIX_0F3835,
1054   PREFIX_0F3837,
1055   PREFIX_0F3838,
1056   PREFIX_0F3839,
1057   PREFIX_0F383A,
1058   PREFIX_0F383B,
1059   PREFIX_0F383C,
1060   PREFIX_0F383D,
1061   PREFIX_0F383E,
1062   PREFIX_0F383F,
1063   PREFIX_0F3840,
1064   PREFIX_0F3841,
1065   PREFIX_0F3880,
1066   PREFIX_0F3881,
1067   PREFIX_0F3882,
1068   PREFIX_0F38C8,
1069   PREFIX_0F38C9,
1070   PREFIX_0F38CA,
1071   PREFIX_0F38CB,
1072   PREFIX_0F38CC,
1073   PREFIX_0F38CD,
1074   PREFIX_0F38CF,
1075   PREFIX_0F38DB,
1076   PREFIX_0F38DC,
1077   PREFIX_0F38DD,
1078   PREFIX_0F38DE,
1079   PREFIX_0F38DF,
1080   PREFIX_0F38F0,
1081   PREFIX_0F38F1,
1082   PREFIX_0F38F5,
1083   PREFIX_0F38F6,
1084   PREFIX_0F38F8,
1085   PREFIX_0F38F9,
1086   PREFIX_0F3A08,
1087   PREFIX_0F3A09,
1088   PREFIX_0F3A0A,
1089   PREFIX_0F3A0B,
1090   PREFIX_0F3A0C,
1091   PREFIX_0F3A0D,
1092   PREFIX_0F3A0E,
1093   PREFIX_0F3A14,
1094   PREFIX_0F3A15,
1095   PREFIX_0F3A16,
1096   PREFIX_0F3A17,
1097   PREFIX_0F3A20,
1098   PREFIX_0F3A21,
1099   PREFIX_0F3A22,
1100   PREFIX_0F3A40,
1101   PREFIX_0F3A41,
1102   PREFIX_0F3A42,
1103   PREFIX_0F3A44,
1104   PREFIX_0F3A60,
1105   PREFIX_0F3A61,
1106   PREFIX_0F3A62,
1107   PREFIX_0F3A63,
1108   PREFIX_0F3ACC,
1109   PREFIX_0F3ACE,
1110   PREFIX_0F3ACF,
1111   PREFIX_0F3ADF,
1112   PREFIX_VEX_0F10,
1113   PREFIX_VEX_0F11,
1114   PREFIX_VEX_0F12,
1115   PREFIX_VEX_0F16,
1116   PREFIX_VEX_0F2A,
1117   PREFIX_VEX_0F2C,
1118   PREFIX_VEX_0F2D,
1119   PREFIX_VEX_0F2E,
1120   PREFIX_VEX_0F2F,
1121   PREFIX_VEX_0F41,
1122   PREFIX_VEX_0F42,
1123   PREFIX_VEX_0F44,
1124   PREFIX_VEX_0F45,
1125   PREFIX_VEX_0F46,
1126   PREFIX_VEX_0F47,
1127   PREFIX_VEX_0F4A,
1128   PREFIX_VEX_0F4B,
1129   PREFIX_VEX_0F51,
1130   PREFIX_VEX_0F52,
1131   PREFIX_VEX_0F53,
1132   PREFIX_VEX_0F58,
1133   PREFIX_VEX_0F59,
1134   PREFIX_VEX_0F5A,
1135   PREFIX_VEX_0F5B,
1136   PREFIX_VEX_0F5C,
1137   PREFIX_VEX_0F5D,
1138   PREFIX_VEX_0F5E,
1139   PREFIX_VEX_0F5F,
1140   PREFIX_VEX_0F60,
1141   PREFIX_VEX_0F61,
1142   PREFIX_VEX_0F62,
1143   PREFIX_VEX_0F63,
1144   PREFIX_VEX_0F64,
1145   PREFIX_VEX_0F65,
1146   PREFIX_VEX_0F66,
1147   PREFIX_VEX_0F67,
1148   PREFIX_VEX_0F68,
1149   PREFIX_VEX_0F69,
1150   PREFIX_VEX_0F6A,
1151   PREFIX_VEX_0F6B,
1152   PREFIX_VEX_0F6C,
1153   PREFIX_VEX_0F6D,
1154   PREFIX_VEX_0F6E,
1155   PREFIX_VEX_0F6F,
1156   PREFIX_VEX_0F70,
1157   PREFIX_VEX_0F71_REG_2,
1158   PREFIX_VEX_0F71_REG_4,
1159   PREFIX_VEX_0F71_REG_6,
1160   PREFIX_VEX_0F72_REG_2,
1161   PREFIX_VEX_0F72_REG_4,
1162   PREFIX_VEX_0F72_REG_6,
1163   PREFIX_VEX_0F73_REG_2,
1164   PREFIX_VEX_0F73_REG_3,
1165   PREFIX_VEX_0F73_REG_6,
1166   PREFIX_VEX_0F73_REG_7,
1167   PREFIX_VEX_0F74,
1168   PREFIX_VEX_0F75,
1169   PREFIX_VEX_0F76,
1170   PREFIX_VEX_0F77,
1171   PREFIX_VEX_0F7C,
1172   PREFIX_VEX_0F7D,
1173   PREFIX_VEX_0F7E,
1174   PREFIX_VEX_0F7F,
1175   PREFIX_VEX_0F90,
1176   PREFIX_VEX_0F91,
1177   PREFIX_VEX_0F92,
1178   PREFIX_VEX_0F93,
1179   PREFIX_VEX_0F98,
1180   PREFIX_VEX_0F99,
1181   PREFIX_VEX_0FC2,
1182   PREFIX_VEX_0FC4,
1183   PREFIX_VEX_0FC5,
1184   PREFIX_VEX_0FD0,
1185   PREFIX_VEX_0FD1,
1186   PREFIX_VEX_0FD2,
1187   PREFIX_VEX_0FD3,
1188   PREFIX_VEX_0FD4,
1189   PREFIX_VEX_0FD5,
1190   PREFIX_VEX_0FD6,
1191   PREFIX_VEX_0FD7,
1192   PREFIX_VEX_0FD8,
1193   PREFIX_VEX_0FD9,
1194   PREFIX_VEX_0FDA,
1195   PREFIX_VEX_0FDB,
1196   PREFIX_VEX_0FDC,
1197   PREFIX_VEX_0FDD,
1198   PREFIX_VEX_0FDE,
1199   PREFIX_VEX_0FDF,
1200   PREFIX_VEX_0FE0,
1201   PREFIX_VEX_0FE1,
1202   PREFIX_VEX_0FE2,
1203   PREFIX_VEX_0FE3,
1204   PREFIX_VEX_0FE4,
1205   PREFIX_VEX_0FE5,
1206   PREFIX_VEX_0FE6,
1207   PREFIX_VEX_0FE7,
1208   PREFIX_VEX_0FE8,
1209   PREFIX_VEX_0FE9,
1210   PREFIX_VEX_0FEA,
1211   PREFIX_VEX_0FEB,
1212   PREFIX_VEX_0FEC,
1213   PREFIX_VEX_0FED,
1214   PREFIX_VEX_0FEE,
1215   PREFIX_VEX_0FEF,
1216   PREFIX_VEX_0FF0,
1217   PREFIX_VEX_0FF1,
1218   PREFIX_VEX_0FF2,
1219   PREFIX_VEX_0FF3,
1220   PREFIX_VEX_0FF4,
1221   PREFIX_VEX_0FF5,
1222   PREFIX_VEX_0FF6,
1223   PREFIX_VEX_0FF7,
1224   PREFIX_VEX_0FF8,
1225   PREFIX_VEX_0FF9,
1226   PREFIX_VEX_0FFA,
1227   PREFIX_VEX_0FFB,
1228   PREFIX_VEX_0FFC,
1229   PREFIX_VEX_0FFD,
1230   PREFIX_VEX_0FFE,
1231   PREFIX_VEX_0F3800,
1232   PREFIX_VEX_0F3801,
1233   PREFIX_VEX_0F3802,
1234   PREFIX_VEX_0F3803,
1235   PREFIX_VEX_0F3804,
1236   PREFIX_VEX_0F3805,
1237   PREFIX_VEX_0F3806,
1238   PREFIX_VEX_0F3807,
1239   PREFIX_VEX_0F3808,
1240   PREFIX_VEX_0F3809,
1241   PREFIX_VEX_0F380A,
1242   PREFIX_VEX_0F380B,
1243   PREFIX_VEX_0F380C,
1244   PREFIX_VEX_0F380D,
1245   PREFIX_VEX_0F380E,
1246   PREFIX_VEX_0F380F,
1247   PREFIX_VEX_0F3813,
1248   PREFIX_VEX_0F3816,
1249   PREFIX_VEX_0F3817,
1250   PREFIX_VEX_0F3818,
1251   PREFIX_VEX_0F3819,
1252   PREFIX_VEX_0F381A,
1253   PREFIX_VEX_0F381C,
1254   PREFIX_VEX_0F381D,
1255   PREFIX_VEX_0F381E,
1256   PREFIX_VEX_0F3820,
1257   PREFIX_VEX_0F3821,
1258   PREFIX_VEX_0F3822,
1259   PREFIX_VEX_0F3823,
1260   PREFIX_VEX_0F3824,
1261   PREFIX_VEX_0F3825,
1262   PREFIX_VEX_0F3828,
1263   PREFIX_VEX_0F3829,
1264   PREFIX_VEX_0F382A,
1265   PREFIX_VEX_0F382B,
1266   PREFIX_VEX_0F382C,
1267   PREFIX_VEX_0F382D,
1268   PREFIX_VEX_0F382E,
1269   PREFIX_VEX_0F382F,
1270   PREFIX_VEX_0F3830,
1271   PREFIX_VEX_0F3831,
1272   PREFIX_VEX_0F3832,
1273   PREFIX_VEX_0F3833,
1274   PREFIX_VEX_0F3834,
1275   PREFIX_VEX_0F3835,
1276   PREFIX_VEX_0F3836,
1277   PREFIX_VEX_0F3837,
1278   PREFIX_VEX_0F3838,
1279   PREFIX_VEX_0F3839,
1280   PREFIX_VEX_0F383A,
1281   PREFIX_VEX_0F383B,
1282   PREFIX_VEX_0F383C,
1283   PREFIX_VEX_0F383D,
1284   PREFIX_VEX_0F383E,
1285   PREFIX_VEX_0F383F,
1286   PREFIX_VEX_0F3840,
1287   PREFIX_VEX_0F3841,
1288   PREFIX_VEX_0F3845,
1289   PREFIX_VEX_0F3846,
1290   PREFIX_VEX_0F3847,
1291   PREFIX_VEX_0F3858,
1292   PREFIX_VEX_0F3859,
1293   PREFIX_VEX_0F385A,
1294   PREFIX_VEX_0F3878,
1295   PREFIX_VEX_0F3879,
1296   PREFIX_VEX_0F388C,
1297   PREFIX_VEX_0F388E,
1298   PREFIX_VEX_0F3890,
1299   PREFIX_VEX_0F3891,
1300   PREFIX_VEX_0F3892,
1301   PREFIX_VEX_0F3893,
1302   PREFIX_VEX_0F3896,
1303   PREFIX_VEX_0F3897,
1304   PREFIX_VEX_0F3898,
1305   PREFIX_VEX_0F3899,
1306   PREFIX_VEX_0F389A,
1307   PREFIX_VEX_0F389B,
1308   PREFIX_VEX_0F389C,
1309   PREFIX_VEX_0F389D,
1310   PREFIX_VEX_0F389E,
1311   PREFIX_VEX_0F389F,
1312   PREFIX_VEX_0F38A6,
1313   PREFIX_VEX_0F38A7,
1314   PREFIX_VEX_0F38A8,
1315   PREFIX_VEX_0F38A9,
1316   PREFIX_VEX_0F38AA,
1317   PREFIX_VEX_0F38AB,
1318   PREFIX_VEX_0F38AC,
1319   PREFIX_VEX_0F38AD,
1320   PREFIX_VEX_0F38AE,
1321   PREFIX_VEX_0F38AF,
1322   PREFIX_VEX_0F38B6,
1323   PREFIX_VEX_0F38B7,
1324   PREFIX_VEX_0F38B8,
1325   PREFIX_VEX_0F38B9,
1326   PREFIX_VEX_0F38BA,
1327   PREFIX_VEX_0F38BB,
1328   PREFIX_VEX_0F38BC,
1329   PREFIX_VEX_0F38BD,
1330   PREFIX_VEX_0F38BE,
1331   PREFIX_VEX_0F38BF,
1332   PREFIX_VEX_0F38CF,
1333   PREFIX_VEX_0F38DB,
1334   PREFIX_VEX_0F38DC,
1335   PREFIX_VEX_0F38DD,
1336   PREFIX_VEX_0F38DE,
1337   PREFIX_VEX_0F38DF,
1338   PREFIX_VEX_0F38F2,
1339   PREFIX_VEX_0F38F3_REG_1,
1340   PREFIX_VEX_0F38F3_REG_2,
1341   PREFIX_VEX_0F38F3_REG_3,
1342   PREFIX_VEX_0F38F5,
1343   PREFIX_VEX_0F38F6,
1344   PREFIX_VEX_0F38F7,
1345   PREFIX_VEX_0F3A00,
1346   PREFIX_VEX_0F3A01,
1347   PREFIX_VEX_0F3A02,
1348   PREFIX_VEX_0F3A04,
1349   PREFIX_VEX_0F3A05,
1350   PREFIX_VEX_0F3A06,
1351   PREFIX_VEX_0F3A08,
1352   PREFIX_VEX_0F3A09,
1353   PREFIX_VEX_0F3A0A,
1354   PREFIX_VEX_0F3A0B,
1355   PREFIX_VEX_0F3A0C,
1356   PREFIX_VEX_0F3A0D,
1357   PREFIX_VEX_0F3A0E,
1358   PREFIX_VEX_0F3A0F,
1359   PREFIX_VEX_0F3A14,
1360   PREFIX_VEX_0F3A15,
1361   PREFIX_VEX_0F3A16,
1362   PREFIX_VEX_0F3A17,
1363   PREFIX_VEX_0F3A18,
1364   PREFIX_VEX_0F3A19,
1365   PREFIX_VEX_0F3A1D,
1366   PREFIX_VEX_0F3A20,
1367   PREFIX_VEX_0F3A21,
1368   PREFIX_VEX_0F3A22,
1369   PREFIX_VEX_0F3A30,
1370   PREFIX_VEX_0F3A31,
1371   PREFIX_VEX_0F3A32,
1372   PREFIX_VEX_0F3A33,
1373   PREFIX_VEX_0F3A38,
1374   PREFIX_VEX_0F3A39,
1375   PREFIX_VEX_0F3A40,
1376   PREFIX_VEX_0F3A41,
1377   PREFIX_VEX_0F3A42,
1378   PREFIX_VEX_0F3A44,
1379   PREFIX_VEX_0F3A46,
1380   PREFIX_VEX_0F3A48,
1381   PREFIX_VEX_0F3A49,
1382   PREFIX_VEX_0F3A4A,
1383   PREFIX_VEX_0F3A4B,
1384   PREFIX_VEX_0F3A4C,
1385   PREFIX_VEX_0F3A5C,
1386   PREFIX_VEX_0F3A5D,
1387   PREFIX_VEX_0F3A5E,
1388   PREFIX_VEX_0F3A5F,
1389   PREFIX_VEX_0F3A60,
1390   PREFIX_VEX_0F3A61,
1391   PREFIX_VEX_0F3A62,
1392   PREFIX_VEX_0F3A63,
1393   PREFIX_VEX_0F3A68,
1394   PREFIX_VEX_0F3A69,
1395   PREFIX_VEX_0F3A6A,
1396   PREFIX_VEX_0F3A6B,
1397   PREFIX_VEX_0F3A6C,
1398   PREFIX_VEX_0F3A6D,
1399   PREFIX_VEX_0F3A6E,
1400   PREFIX_VEX_0F3A6F,
1401   PREFIX_VEX_0F3A78,
1402   PREFIX_VEX_0F3A79,
1403   PREFIX_VEX_0F3A7A,
1404   PREFIX_VEX_0F3A7B,
1405   PREFIX_VEX_0F3A7C,
1406   PREFIX_VEX_0F3A7D,
1407   PREFIX_VEX_0F3A7E,
1408   PREFIX_VEX_0F3A7F,
1409   PREFIX_VEX_0F3ACE,
1410   PREFIX_VEX_0F3ACF,
1411   PREFIX_VEX_0F3ADF,
1412   PREFIX_VEX_0F3AF0,
1413
1414   PREFIX_EVEX_0F10,
1415   PREFIX_EVEX_0F11,
1416   PREFIX_EVEX_0F12,
1417   PREFIX_EVEX_0F13,
1418   PREFIX_EVEX_0F14,
1419   PREFIX_EVEX_0F15,
1420   PREFIX_EVEX_0F16,
1421   PREFIX_EVEX_0F17,
1422   PREFIX_EVEX_0F28,
1423   PREFIX_EVEX_0F29,
1424   PREFIX_EVEX_0F2A,
1425   PREFIX_EVEX_0F2B,
1426   PREFIX_EVEX_0F2C,
1427   PREFIX_EVEX_0F2D,
1428   PREFIX_EVEX_0F2E,
1429   PREFIX_EVEX_0F2F,
1430   PREFIX_EVEX_0F51,
1431   PREFIX_EVEX_0F54,
1432   PREFIX_EVEX_0F55,
1433   PREFIX_EVEX_0F56,
1434   PREFIX_EVEX_0F57,
1435   PREFIX_EVEX_0F58,
1436   PREFIX_EVEX_0F59,
1437   PREFIX_EVEX_0F5A,
1438   PREFIX_EVEX_0F5B,
1439   PREFIX_EVEX_0F5C,
1440   PREFIX_EVEX_0F5D,
1441   PREFIX_EVEX_0F5E,
1442   PREFIX_EVEX_0F5F,
1443   PREFIX_EVEX_0F60,
1444   PREFIX_EVEX_0F61,
1445   PREFIX_EVEX_0F62,
1446   PREFIX_EVEX_0F63,
1447   PREFIX_EVEX_0F64,
1448   PREFIX_EVEX_0F65,
1449   PREFIX_EVEX_0F66,
1450   PREFIX_EVEX_0F67,
1451   PREFIX_EVEX_0F68,
1452   PREFIX_EVEX_0F69,
1453   PREFIX_EVEX_0F6A,
1454   PREFIX_EVEX_0F6B,
1455   PREFIX_EVEX_0F6C,
1456   PREFIX_EVEX_0F6D,
1457   PREFIX_EVEX_0F6E,
1458   PREFIX_EVEX_0F6F,
1459   PREFIX_EVEX_0F70,
1460   PREFIX_EVEX_0F71_REG_2,
1461   PREFIX_EVEX_0F71_REG_4,
1462   PREFIX_EVEX_0F71_REG_6,
1463   PREFIX_EVEX_0F72_REG_0,
1464   PREFIX_EVEX_0F72_REG_1,
1465   PREFIX_EVEX_0F72_REG_2,
1466   PREFIX_EVEX_0F72_REG_4,
1467   PREFIX_EVEX_0F72_REG_6,
1468   PREFIX_EVEX_0F73_REG_2,
1469   PREFIX_EVEX_0F73_REG_3,
1470   PREFIX_EVEX_0F73_REG_6,
1471   PREFIX_EVEX_0F73_REG_7,
1472   PREFIX_EVEX_0F74,
1473   PREFIX_EVEX_0F75,
1474   PREFIX_EVEX_0F76,
1475   PREFIX_EVEX_0F78,
1476   PREFIX_EVEX_0F79,
1477   PREFIX_EVEX_0F7A,
1478   PREFIX_EVEX_0F7B,
1479   PREFIX_EVEX_0F7E,
1480   PREFIX_EVEX_0F7F,
1481   PREFIX_EVEX_0FC2,
1482   PREFIX_EVEX_0FC4,
1483   PREFIX_EVEX_0FC5,
1484   PREFIX_EVEX_0FC6,
1485   PREFIX_EVEX_0FD1,
1486   PREFIX_EVEX_0FD2,
1487   PREFIX_EVEX_0FD3,
1488   PREFIX_EVEX_0FD4,
1489   PREFIX_EVEX_0FD5,
1490   PREFIX_EVEX_0FD6,
1491   PREFIX_EVEX_0FD8,
1492   PREFIX_EVEX_0FD9,
1493   PREFIX_EVEX_0FDA,
1494   PREFIX_EVEX_0FDB,
1495   PREFIX_EVEX_0FDC,
1496   PREFIX_EVEX_0FDD,
1497   PREFIX_EVEX_0FDE,
1498   PREFIX_EVEX_0FDF,
1499   PREFIX_EVEX_0FE0,
1500   PREFIX_EVEX_0FE1,
1501   PREFIX_EVEX_0FE2,
1502   PREFIX_EVEX_0FE3,
1503   PREFIX_EVEX_0FE4,
1504   PREFIX_EVEX_0FE5,
1505   PREFIX_EVEX_0FE6,
1506   PREFIX_EVEX_0FE7,
1507   PREFIX_EVEX_0FE8,
1508   PREFIX_EVEX_0FE9,
1509   PREFIX_EVEX_0FEA,
1510   PREFIX_EVEX_0FEB,
1511   PREFIX_EVEX_0FEC,
1512   PREFIX_EVEX_0FED,
1513   PREFIX_EVEX_0FEE,
1514   PREFIX_EVEX_0FEF,
1515   PREFIX_EVEX_0FF1,
1516   PREFIX_EVEX_0FF2,
1517   PREFIX_EVEX_0FF3,
1518   PREFIX_EVEX_0FF4,
1519   PREFIX_EVEX_0FF5,
1520   PREFIX_EVEX_0FF6,
1521   PREFIX_EVEX_0FF8,
1522   PREFIX_EVEX_0FF9,
1523   PREFIX_EVEX_0FFA,
1524   PREFIX_EVEX_0FFB,
1525   PREFIX_EVEX_0FFC,
1526   PREFIX_EVEX_0FFD,
1527   PREFIX_EVEX_0FFE,
1528   PREFIX_EVEX_0F3800,
1529   PREFIX_EVEX_0F3804,
1530   PREFIX_EVEX_0F380B,
1531   PREFIX_EVEX_0F380C,
1532   PREFIX_EVEX_0F380D,
1533   PREFIX_EVEX_0F3810,
1534   PREFIX_EVEX_0F3811,
1535   PREFIX_EVEX_0F3812,
1536   PREFIX_EVEX_0F3813,
1537   PREFIX_EVEX_0F3814,
1538   PREFIX_EVEX_0F3815,
1539   PREFIX_EVEX_0F3816,
1540   PREFIX_EVEX_0F3818,
1541   PREFIX_EVEX_0F3819,
1542   PREFIX_EVEX_0F381A,
1543   PREFIX_EVEX_0F381B,
1544   PREFIX_EVEX_0F381C,
1545   PREFIX_EVEX_0F381D,
1546   PREFIX_EVEX_0F381E,
1547   PREFIX_EVEX_0F381F,
1548   PREFIX_EVEX_0F3820,
1549   PREFIX_EVEX_0F3821,
1550   PREFIX_EVEX_0F3822,
1551   PREFIX_EVEX_0F3823,
1552   PREFIX_EVEX_0F3824,
1553   PREFIX_EVEX_0F3825,
1554   PREFIX_EVEX_0F3826,
1555   PREFIX_EVEX_0F3827,
1556   PREFIX_EVEX_0F3828,
1557   PREFIX_EVEX_0F3829,
1558   PREFIX_EVEX_0F382A,
1559   PREFIX_EVEX_0F382B,
1560   PREFIX_EVEX_0F382C,
1561   PREFIX_EVEX_0F382D,
1562   PREFIX_EVEX_0F3830,
1563   PREFIX_EVEX_0F3831,
1564   PREFIX_EVEX_0F3832,
1565   PREFIX_EVEX_0F3833,
1566   PREFIX_EVEX_0F3834,
1567   PREFIX_EVEX_0F3835,
1568   PREFIX_EVEX_0F3836,
1569   PREFIX_EVEX_0F3837,
1570   PREFIX_EVEX_0F3838,
1571   PREFIX_EVEX_0F3839,
1572   PREFIX_EVEX_0F383A,
1573   PREFIX_EVEX_0F383B,
1574   PREFIX_EVEX_0F383C,
1575   PREFIX_EVEX_0F383D,
1576   PREFIX_EVEX_0F383E,
1577   PREFIX_EVEX_0F383F,
1578   PREFIX_EVEX_0F3840,
1579   PREFIX_EVEX_0F3842,
1580   PREFIX_EVEX_0F3843,
1581   PREFIX_EVEX_0F3844,
1582   PREFIX_EVEX_0F3845,
1583   PREFIX_EVEX_0F3846,
1584   PREFIX_EVEX_0F3847,
1585   PREFIX_EVEX_0F384C,
1586   PREFIX_EVEX_0F384D,
1587   PREFIX_EVEX_0F384E,
1588   PREFIX_EVEX_0F384F,
1589   PREFIX_EVEX_0F3850,
1590   PREFIX_EVEX_0F3851,
1591   PREFIX_EVEX_0F3852,
1592   PREFIX_EVEX_0F3853,
1593   PREFIX_EVEX_0F3854,
1594   PREFIX_EVEX_0F3855,
1595   PREFIX_EVEX_0F3858,
1596   PREFIX_EVEX_0F3859,
1597   PREFIX_EVEX_0F385A,
1598   PREFIX_EVEX_0F385B,
1599   PREFIX_EVEX_0F3862,
1600   PREFIX_EVEX_0F3863,
1601   PREFIX_EVEX_0F3864,
1602   PREFIX_EVEX_0F3865,
1603   PREFIX_EVEX_0F3866,
1604   PREFIX_EVEX_0F3868,
1605   PREFIX_EVEX_0F3870,
1606   PREFIX_EVEX_0F3871,
1607   PREFIX_EVEX_0F3872,
1608   PREFIX_EVEX_0F3873,
1609   PREFIX_EVEX_0F3875,
1610   PREFIX_EVEX_0F3876,
1611   PREFIX_EVEX_0F3877,
1612   PREFIX_EVEX_0F3878,
1613   PREFIX_EVEX_0F3879,
1614   PREFIX_EVEX_0F387A,
1615   PREFIX_EVEX_0F387B,
1616   PREFIX_EVEX_0F387C,
1617   PREFIX_EVEX_0F387D,
1618   PREFIX_EVEX_0F387E,
1619   PREFIX_EVEX_0F387F,
1620   PREFIX_EVEX_0F3883,
1621   PREFIX_EVEX_0F3888,
1622   PREFIX_EVEX_0F3889,
1623   PREFIX_EVEX_0F388A,
1624   PREFIX_EVEX_0F388B,
1625   PREFIX_EVEX_0F388D,
1626   PREFIX_EVEX_0F388F,
1627   PREFIX_EVEX_0F3890,
1628   PREFIX_EVEX_0F3891,
1629   PREFIX_EVEX_0F3892,
1630   PREFIX_EVEX_0F3893,
1631   PREFIX_EVEX_0F3896,
1632   PREFIX_EVEX_0F3897,
1633   PREFIX_EVEX_0F3898,
1634   PREFIX_EVEX_0F3899,
1635   PREFIX_EVEX_0F389A,
1636   PREFIX_EVEX_0F389B,
1637   PREFIX_EVEX_0F389C,
1638   PREFIX_EVEX_0F389D,
1639   PREFIX_EVEX_0F389E,
1640   PREFIX_EVEX_0F389F,
1641   PREFIX_EVEX_0F38A0,
1642   PREFIX_EVEX_0F38A1,
1643   PREFIX_EVEX_0F38A2,
1644   PREFIX_EVEX_0F38A3,
1645   PREFIX_EVEX_0F38A6,
1646   PREFIX_EVEX_0F38A7,
1647   PREFIX_EVEX_0F38A8,
1648   PREFIX_EVEX_0F38A9,
1649   PREFIX_EVEX_0F38AA,
1650   PREFIX_EVEX_0F38AB,
1651   PREFIX_EVEX_0F38AC,
1652   PREFIX_EVEX_0F38AD,
1653   PREFIX_EVEX_0F38AE,
1654   PREFIX_EVEX_0F38AF,
1655   PREFIX_EVEX_0F38B4,
1656   PREFIX_EVEX_0F38B5,
1657   PREFIX_EVEX_0F38B6,
1658   PREFIX_EVEX_0F38B7,
1659   PREFIX_EVEX_0F38B8,
1660   PREFIX_EVEX_0F38B9,
1661   PREFIX_EVEX_0F38BA,
1662   PREFIX_EVEX_0F38BB,
1663   PREFIX_EVEX_0F38BC,
1664   PREFIX_EVEX_0F38BD,
1665   PREFIX_EVEX_0F38BE,
1666   PREFIX_EVEX_0F38BF,
1667   PREFIX_EVEX_0F38C4,
1668   PREFIX_EVEX_0F38C6_REG_1,
1669   PREFIX_EVEX_0F38C6_REG_2,
1670   PREFIX_EVEX_0F38C6_REG_5,
1671   PREFIX_EVEX_0F38C6_REG_6,
1672   PREFIX_EVEX_0F38C7_REG_1,
1673   PREFIX_EVEX_0F38C7_REG_2,
1674   PREFIX_EVEX_0F38C7_REG_5,
1675   PREFIX_EVEX_0F38C7_REG_6,
1676   PREFIX_EVEX_0F38C8,
1677   PREFIX_EVEX_0F38CA,
1678   PREFIX_EVEX_0F38CB,
1679   PREFIX_EVEX_0F38CC,
1680   PREFIX_EVEX_0F38CD,
1681   PREFIX_EVEX_0F38CF,
1682   PREFIX_EVEX_0F38DC,
1683   PREFIX_EVEX_0F38DD,
1684   PREFIX_EVEX_0F38DE,
1685   PREFIX_EVEX_0F38DF,
1686
1687   PREFIX_EVEX_0F3A00,
1688   PREFIX_EVEX_0F3A01,
1689   PREFIX_EVEX_0F3A03,
1690   PREFIX_EVEX_0F3A04,
1691   PREFIX_EVEX_0F3A05,
1692   PREFIX_EVEX_0F3A08,
1693   PREFIX_EVEX_0F3A09,
1694   PREFIX_EVEX_0F3A0A,
1695   PREFIX_EVEX_0F3A0B,
1696   PREFIX_EVEX_0F3A0F,
1697   PREFIX_EVEX_0F3A14,
1698   PREFIX_EVEX_0F3A15,
1699   PREFIX_EVEX_0F3A16,
1700   PREFIX_EVEX_0F3A17,
1701   PREFIX_EVEX_0F3A18,
1702   PREFIX_EVEX_0F3A19,
1703   PREFIX_EVEX_0F3A1A,
1704   PREFIX_EVEX_0F3A1B,
1705   PREFIX_EVEX_0F3A1D,
1706   PREFIX_EVEX_0F3A1E,
1707   PREFIX_EVEX_0F3A1F,
1708   PREFIX_EVEX_0F3A20,
1709   PREFIX_EVEX_0F3A21,
1710   PREFIX_EVEX_0F3A22,
1711   PREFIX_EVEX_0F3A23,
1712   PREFIX_EVEX_0F3A25,
1713   PREFIX_EVEX_0F3A26,
1714   PREFIX_EVEX_0F3A27,
1715   PREFIX_EVEX_0F3A38,
1716   PREFIX_EVEX_0F3A39,
1717   PREFIX_EVEX_0F3A3A,
1718   PREFIX_EVEX_0F3A3B,
1719   PREFIX_EVEX_0F3A3E,
1720   PREFIX_EVEX_0F3A3F,
1721   PREFIX_EVEX_0F3A42,
1722   PREFIX_EVEX_0F3A43,
1723   PREFIX_EVEX_0F3A44,
1724   PREFIX_EVEX_0F3A50,
1725   PREFIX_EVEX_0F3A51,
1726   PREFIX_EVEX_0F3A54,
1727   PREFIX_EVEX_0F3A55,
1728   PREFIX_EVEX_0F3A56,
1729   PREFIX_EVEX_0F3A57,
1730   PREFIX_EVEX_0F3A66,
1731   PREFIX_EVEX_0F3A67,
1732   PREFIX_EVEX_0F3A70,
1733   PREFIX_EVEX_0F3A71,
1734   PREFIX_EVEX_0F3A72,
1735   PREFIX_EVEX_0F3A73,
1736   PREFIX_EVEX_0F3ACE,
1737   PREFIX_EVEX_0F3ACF
1738 };
1739
1740 enum
1741 {
1742   X86_64_06 = 0,
1743   X86_64_07,
1744   X86_64_0D,
1745   X86_64_16,
1746   X86_64_17,
1747   X86_64_1E,
1748   X86_64_1F,
1749   X86_64_27,
1750   X86_64_2F,
1751   X86_64_37,
1752   X86_64_3F,
1753   X86_64_60,
1754   X86_64_61,
1755   X86_64_62,
1756   X86_64_63,
1757   X86_64_6D,
1758   X86_64_6F,
1759   X86_64_82,
1760   X86_64_9A,
1761   X86_64_C4,
1762   X86_64_C5,
1763   X86_64_CE,
1764   X86_64_D4,
1765   X86_64_D5,
1766   X86_64_E8,
1767   X86_64_E9,
1768   X86_64_EA,
1769   X86_64_0F01_REG_0,
1770   X86_64_0F01_REG_1,
1771   X86_64_0F01_REG_2,
1772   X86_64_0F01_REG_3
1773 };
1774
1775 enum
1776 {
1777   THREE_BYTE_0F38 = 0,
1778   THREE_BYTE_0F3A
1779 };
1780
1781 enum
1782 {
1783   XOP_08 = 0,
1784   XOP_09,
1785   XOP_0A
1786 };
1787
1788 enum
1789 {
1790   VEX_0F = 0,
1791   VEX_0F38,
1792   VEX_0F3A
1793 };
1794
1795 enum
1796 {
1797   EVEX_0F = 0,
1798   EVEX_0F38,
1799   EVEX_0F3A
1800 };
1801
1802 enum
1803 {
1804   VEX_LEN_0F12_P_0_M_0 = 0,
1805   VEX_LEN_0F12_P_0_M_1,
1806   VEX_LEN_0F12_P_2,
1807   VEX_LEN_0F13_M_0,
1808   VEX_LEN_0F16_P_0_M_0,
1809   VEX_LEN_0F16_P_0_M_1,
1810   VEX_LEN_0F16_P_2,
1811   VEX_LEN_0F17_M_0,
1812   VEX_LEN_0F41_P_0,
1813   VEX_LEN_0F41_P_2,
1814   VEX_LEN_0F42_P_0,
1815   VEX_LEN_0F42_P_2,
1816   VEX_LEN_0F44_P_0,
1817   VEX_LEN_0F44_P_2,
1818   VEX_LEN_0F45_P_0,
1819   VEX_LEN_0F45_P_2,
1820   VEX_LEN_0F46_P_0,
1821   VEX_LEN_0F46_P_2,
1822   VEX_LEN_0F47_P_0,
1823   VEX_LEN_0F47_P_2,
1824   VEX_LEN_0F4A_P_0,
1825   VEX_LEN_0F4A_P_2,
1826   VEX_LEN_0F4B_P_0,
1827   VEX_LEN_0F4B_P_2,
1828   VEX_LEN_0F6E_P_2,
1829   VEX_LEN_0F77_P_0,
1830   VEX_LEN_0F7E_P_1,
1831   VEX_LEN_0F7E_P_2,
1832   VEX_LEN_0F90_P_0,
1833   VEX_LEN_0F90_P_2,
1834   VEX_LEN_0F91_P_0,
1835   VEX_LEN_0F91_P_2,
1836   VEX_LEN_0F92_P_0,
1837   VEX_LEN_0F92_P_2,
1838   VEX_LEN_0F92_P_3,
1839   VEX_LEN_0F93_P_0,
1840   VEX_LEN_0F93_P_2,
1841   VEX_LEN_0F93_P_3,
1842   VEX_LEN_0F98_P_0,
1843   VEX_LEN_0F98_P_2,
1844   VEX_LEN_0F99_P_0,
1845   VEX_LEN_0F99_P_2,
1846   VEX_LEN_0FAE_R_2_M_0,
1847   VEX_LEN_0FAE_R_3_M_0,
1848   VEX_LEN_0FC4_P_2,
1849   VEX_LEN_0FC5_P_2,
1850   VEX_LEN_0FD6_P_2,
1851   VEX_LEN_0FF7_P_2,
1852   VEX_LEN_0F3816_P_2,
1853   VEX_LEN_0F3819_P_2,
1854   VEX_LEN_0F381A_P_2_M_0,
1855   VEX_LEN_0F3836_P_2,
1856   VEX_LEN_0F3841_P_2,
1857   VEX_LEN_0F385A_P_2_M_0,
1858   VEX_LEN_0F38DB_P_2,
1859   VEX_LEN_0F38F2_P_0,
1860   VEX_LEN_0F38F3_R_1_P_0,
1861   VEX_LEN_0F38F3_R_2_P_0,
1862   VEX_LEN_0F38F3_R_3_P_0,
1863   VEX_LEN_0F38F5_P_0,
1864   VEX_LEN_0F38F5_P_1,
1865   VEX_LEN_0F38F5_P_3,
1866   VEX_LEN_0F38F6_P_3,
1867   VEX_LEN_0F38F7_P_0,
1868   VEX_LEN_0F38F7_P_1,
1869   VEX_LEN_0F38F7_P_2,
1870   VEX_LEN_0F38F7_P_3,
1871   VEX_LEN_0F3A00_P_2,
1872   VEX_LEN_0F3A01_P_2,
1873   VEX_LEN_0F3A06_P_2,
1874   VEX_LEN_0F3A14_P_2,
1875   VEX_LEN_0F3A15_P_2,
1876   VEX_LEN_0F3A16_P_2,
1877   VEX_LEN_0F3A17_P_2,
1878   VEX_LEN_0F3A18_P_2,
1879   VEX_LEN_0F3A19_P_2,
1880   VEX_LEN_0F3A20_P_2,
1881   VEX_LEN_0F3A21_P_2,
1882   VEX_LEN_0F3A22_P_2,
1883   VEX_LEN_0F3A30_P_2,
1884   VEX_LEN_0F3A31_P_2,
1885   VEX_LEN_0F3A32_P_2,
1886   VEX_LEN_0F3A33_P_2,
1887   VEX_LEN_0F3A38_P_2,
1888   VEX_LEN_0F3A39_P_2,
1889   VEX_LEN_0F3A41_P_2,
1890   VEX_LEN_0F3A46_P_2,
1891   VEX_LEN_0F3A60_P_2,
1892   VEX_LEN_0F3A61_P_2,
1893   VEX_LEN_0F3A62_P_2,
1894   VEX_LEN_0F3A63_P_2,
1895   VEX_LEN_0F3A6A_P_2,
1896   VEX_LEN_0F3A6B_P_2,
1897   VEX_LEN_0F3A6E_P_2,
1898   VEX_LEN_0F3A6F_P_2,
1899   VEX_LEN_0F3A7A_P_2,
1900   VEX_LEN_0F3A7B_P_2,
1901   VEX_LEN_0F3A7E_P_2,
1902   VEX_LEN_0F3A7F_P_2,
1903   VEX_LEN_0F3ADF_P_2,
1904   VEX_LEN_0F3AF0_P_3,
1905   VEX_LEN_0FXOP_08_CC,
1906   VEX_LEN_0FXOP_08_CD,
1907   VEX_LEN_0FXOP_08_CE,
1908   VEX_LEN_0FXOP_08_CF,
1909   VEX_LEN_0FXOP_08_EC,
1910   VEX_LEN_0FXOP_08_ED,
1911   VEX_LEN_0FXOP_08_EE,
1912   VEX_LEN_0FXOP_08_EF,
1913   VEX_LEN_0FXOP_09_80,
1914   VEX_LEN_0FXOP_09_81
1915 };
1916
1917 enum
1918 {
1919   EVEX_LEN_0F6E_P_2 = 0,
1920   EVEX_LEN_0F7E_P_1,
1921   EVEX_LEN_0F7E_P_2,
1922   EVEX_LEN_0FD6_P_2,
1923   EVEX_LEN_0F3819_P_2_W_0,
1924   EVEX_LEN_0F3819_P_2_W_1,
1925   EVEX_LEN_0F381A_P_2_W_0,
1926   EVEX_LEN_0F381A_P_2_W_1,
1927   EVEX_LEN_0F381B_P_2_W_0,
1928   EVEX_LEN_0F381B_P_2_W_1,
1929   EVEX_LEN_0F385A_P_2_W_0,
1930   EVEX_LEN_0F385A_P_2_W_1,
1931   EVEX_LEN_0F385B_P_2_W_0,
1932   EVEX_LEN_0F385B_P_2_W_1,
1933   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1934   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1935   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1936   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1937   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1938   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1939   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1940   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1941   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1942   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1943   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1944   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1945   EVEX_LEN_0F3A18_P_2_W_0,
1946   EVEX_LEN_0F3A18_P_2_W_1,
1947   EVEX_LEN_0F3A19_P_2_W_0,
1948   EVEX_LEN_0F3A19_P_2_W_1,
1949   EVEX_LEN_0F3A1A_P_2_W_0,
1950   EVEX_LEN_0F3A1A_P_2_W_1,
1951   EVEX_LEN_0F3A1B_P_2_W_0,
1952   EVEX_LEN_0F3A1B_P_2_W_1,
1953   EVEX_LEN_0F3A23_P_2_W_0,
1954   EVEX_LEN_0F3A23_P_2_W_1,
1955   EVEX_LEN_0F3A38_P_2_W_0,
1956   EVEX_LEN_0F3A38_P_2_W_1,
1957   EVEX_LEN_0F3A39_P_2_W_0,
1958   EVEX_LEN_0F3A39_P_2_W_1,
1959   EVEX_LEN_0F3A3A_P_2_W_0,
1960   EVEX_LEN_0F3A3A_P_2_W_1,
1961   EVEX_LEN_0F3A3B_P_2_W_0,
1962   EVEX_LEN_0F3A3B_P_2_W_1,
1963   EVEX_LEN_0F3A43_P_2_W_0,
1964   EVEX_LEN_0F3A43_P_2_W_1
1965 };
1966
1967 enum
1968 {
1969   VEX_W_0F41_P_0_LEN_1 = 0,
1970   VEX_W_0F41_P_2_LEN_1,
1971   VEX_W_0F42_P_0_LEN_1,
1972   VEX_W_0F42_P_2_LEN_1,
1973   VEX_W_0F44_P_0_LEN_0,
1974   VEX_W_0F44_P_2_LEN_0,
1975   VEX_W_0F45_P_0_LEN_1,
1976   VEX_W_0F45_P_2_LEN_1,
1977   VEX_W_0F46_P_0_LEN_1,
1978   VEX_W_0F46_P_2_LEN_1,
1979   VEX_W_0F47_P_0_LEN_1,
1980   VEX_W_0F47_P_2_LEN_1,
1981   VEX_W_0F4A_P_0_LEN_1,
1982   VEX_W_0F4A_P_2_LEN_1,
1983   VEX_W_0F4B_P_0_LEN_1,
1984   VEX_W_0F4B_P_2_LEN_1,
1985   VEX_W_0F90_P_0_LEN_0,
1986   VEX_W_0F90_P_2_LEN_0,
1987   VEX_W_0F91_P_0_LEN_0,
1988   VEX_W_0F91_P_2_LEN_0,
1989   VEX_W_0F92_P_0_LEN_0,
1990   VEX_W_0F92_P_2_LEN_0,
1991   VEX_W_0F93_P_0_LEN_0,
1992   VEX_W_0F93_P_2_LEN_0,
1993   VEX_W_0F98_P_0_LEN_0,
1994   VEX_W_0F98_P_2_LEN_0,
1995   VEX_W_0F99_P_0_LEN_0,
1996   VEX_W_0F99_P_2_LEN_0,
1997   VEX_W_0F380C_P_2,
1998   VEX_W_0F380D_P_2,
1999   VEX_W_0F380E_P_2,
2000   VEX_W_0F380F_P_2,
2001   VEX_W_0F3816_P_2,
2002   VEX_W_0F3818_P_2,
2003   VEX_W_0F3819_P_2,
2004   VEX_W_0F381A_P_2_M_0,
2005   VEX_W_0F382C_P_2_M_0,
2006   VEX_W_0F382D_P_2_M_0,
2007   VEX_W_0F382E_P_2_M_0,
2008   VEX_W_0F382F_P_2_M_0,
2009   VEX_W_0F3836_P_2,
2010   VEX_W_0F3846_P_2,
2011   VEX_W_0F3858_P_2,
2012   VEX_W_0F3859_P_2,
2013   VEX_W_0F385A_P_2_M_0,
2014   VEX_W_0F3878_P_2,
2015   VEX_W_0F3879_P_2,
2016   VEX_W_0F38CF_P_2,
2017   VEX_W_0F3A00_P_2,
2018   VEX_W_0F3A01_P_2,
2019   VEX_W_0F3A02_P_2,
2020   VEX_W_0F3A04_P_2,
2021   VEX_W_0F3A05_P_2,
2022   VEX_W_0F3A06_P_2,
2023   VEX_W_0F3A18_P_2,
2024   VEX_W_0F3A19_P_2,
2025   VEX_W_0F3A30_P_2_LEN_0,
2026   VEX_W_0F3A31_P_2_LEN_0,
2027   VEX_W_0F3A32_P_2_LEN_0,
2028   VEX_W_0F3A33_P_2_LEN_0,
2029   VEX_W_0F3A38_P_2,
2030   VEX_W_0F3A39_P_2,
2031   VEX_W_0F3A46_P_2,
2032   VEX_W_0F3A48_P_2,
2033   VEX_W_0F3A49_P_2,
2034   VEX_W_0F3A4A_P_2,
2035   VEX_W_0F3A4B_P_2,
2036   VEX_W_0F3A4C_P_2,
2037   VEX_W_0F3ACE_P_2,
2038   VEX_W_0F3ACF_P_2,
2039
2040   EVEX_W_0F10_P_0,
2041   EVEX_W_0F10_P_1,
2042   EVEX_W_0F10_P_2,
2043   EVEX_W_0F10_P_3,
2044   EVEX_W_0F11_P_0,
2045   EVEX_W_0F11_P_1,
2046   EVEX_W_0F11_P_2,
2047   EVEX_W_0F11_P_3,
2048   EVEX_W_0F12_P_0_M_0,
2049   EVEX_W_0F12_P_0_M_1,
2050   EVEX_W_0F12_P_1,
2051   EVEX_W_0F12_P_2,
2052   EVEX_W_0F12_P_3,
2053   EVEX_W_0F13_P_0,
2054   EVEX_W_0F13_P_2,
2055   EVEX_W_0F14_P_0,
2056   EVEX_W_0F14_P_2,
2057   EVEX_W_0F15_P_0,
2058   EVEX_W_0F15_P_2,
2059   EVEX_W_0F16_P_0_M_0,
2060   EVEX_W_0F16_P_0_M_1,
2061   EVEX_W_0F16_P_1,
2062   EVEX_W_0F16_P_2,
2063   EVEX_W_0F17_P_0,
2064   EVEX_W_0F17_P_2,
2065   EVEX_W_0F28_P_0,
2066   EVEX_W_0F28_P_2,
2067   EVEX_W_0F29_P_0,
2068   EVEX_W_0F29_P_2,
2069   EVEX_W_0F2A_P_3,
2070   EVEX_W_0F2B_P_0,
2071   EVEX_W_0F2B_P_2,
2072   EVEX_W_0F2E_P_0,
2073   EVEX_W_0F2E_P_2,
2074   EVEX_W_0F2F_P_0,
2075   EVEX_W_0F2F_P_2,
2076   EVEX_W_0F51_P_0,
2077   EVEX_W_0F51_P_1,
2078   EVEX_W_0F51_P_2,
2079   EVEX_W_0F51_P_3,
2080   EVEX_W_0F54_P_0,
2081   EVEX_W_0F54_P_2,
2082   EVEX_W_0F55_P_0,
2083   EVEX_W_0F55_P_2,
2084   EVEX_W_0F56_P_0,
2085   EVEX_W_0F56_P_2,
2086   EVEX_W_0F57_P_0,
2087   EVEX_W_0F57_P_2,
2088   EVEX_W_0F58_P_0,
2089   EVEX_W_0F58_P_1,
2090   EVEX_W_0F58_P_2,
2091   EVEX_W_0F58_P_3,
2092   EVEX_W_0F59_P_0,
2093   EVEX_W_0F59_P_1,
2094   EVEX_W_0F59_P_2,
2095   EVEX_W_0F59_P_3,
2096   EVEX_W_0F5A_P_0,
2097   EVEX_W_0F5A_P_1,
2098   EVEX_W_0F5A_P_2,
2099   EVEX_W_0F5A_P_3,
2100   EVEX_W_0F5B_P_0,
2101   EVEX_W_0F5B_P_1,
2102   EVEX_W_0F5B_P_2,
2103   EVEX_W_0F5C_P_0,
2104   EVEX_W_0F5C_P_1,
2105   EVEX_W_0F5C_P_2,
2106   EVEX_W_0F5C_P_3,
2107   EVEX_W_0F5D_P_0,
2108   EVEX_W_0F5D_P_1,
2109   EVEX_W_0F5D_P_2,
2110   EVEX_W_0F5D_P_3,
2111   EVEX_W_0F5E_P_0,
2112   EVEX_W_0F5E_P_1,
2113   EVEX_W_0F5E_P_2,
2114   EVEX_W_0F5E_P_3,
2115   EVEX_W_0F5F_P_0,
2116   EVEX_W_0F5F_P_1,
2117   EVEX_W_0F5F_P_2,
2118   EVEX_W_0F5F_P_3,
2119   EVEX_W_0F62_P_2,
2120   EVEX_W_0F66_P_2,
2121   EVEX_W_0F6A_P_2,
2122   EVEX_W_0F6B_P_2,
2123   EVEX_W_0F6C_P_2,
2124   EVEX_W_0F6D_P_2,
2125   EVEX_W_0F6F_P_1,
2126   EVEX_W_0F6F_P_2,
2127   EVEX_W_0F6F_P_3,
2128   EVEX_W_0F70_P_2,
2129   EVEX_W_0F72_R_2_P_2,
2130   EVEX_W_0F72_R_6_P_2,
2131   EVEX_W_0F73_R_2_P_2,
2132   EVEX_W_0F73_R_6_P_2,
2133   EVEX_W_0F76_P_2,
2134   EVEX_W_0F78_P_0,
2135   EVEX_W_0F78_P_2,
2136   EVEX_W_0F79_P_0,
2137   EVEX_W_0F79_P_2,
2138   EVEX_W_0F7A_P_1,
2139   EVEX_W_0F7A_P_2,
2140   EVEX_W_0F7A_P_3,
2141   EVEX_W_0F7B_P_2,
2142   EVEX_W_0F7B_P_3,
2143   EVEX_W_0F7E_P_1,
2144   EVEX_W_0F7F_P_1,
2145   EVEX_W_0F7F_P_2,
2146   EVEX_W_0F7F_P_3,
2147   EVEX_W_0FC2_P_0,
2148   EVEX_W_0FC2_P_1,
2149   EVEX_W_0FC2_P_2,
2150   EVEX_W_0FC2_P_3,
2151   EVEX_W_0FC6_P_0,
2152   EVEX_W_0FC6_P_2,
2153   EVEX_W_0FD2_P_2,
2154   EVEX_W_0FD3_P_2,
2155   EVEX_W_0FD4_P_2,
2156   EVEX_W_0FD6_P_2,
2157   EVEX_W_0FE6_P_1,
2158   EVEX_W_0FE6_P_2,
2159   EVEX_W_0FE6_P_3,
2160   EVEX_W_0FE7_P_2,
2161   EVEX_W_0FF2_P_2,
2162   EVEX_W_0FF3_P_2,
2163   EVEX_W_0FF4_P_2,
2164   EVEX_W_0FFA_P_2,
2165   EVEX_W_0FFB_P_2,
2166   EVEX_W_0FFE_P_2,
2167   EVEX_W_0F380C_P_2,
2168   EVEX_W_0F380D_P_2,
2169   EVEX_W_0F3810_P_1,
2170   EVEX_W_0F3810_P_2,
2171   EVEX_W_0F3811_P_1,
2172   EVEX_W_0F3811_P_2,
2173   EVEX_W_0F3812_P_1,
2174   EVEX_W_0F3812_P_2,
2175   EVEX_W_0F3813_P_1,
2176   EVEX_W_0F3813_P_2,
2177   EVEX_W_0F3814_P_1,
2178   EVEX_W_0F3815_P_1,
2179   EVEX_W_0F3818_P_2,
2180   EVEX_W_0F3819_P_2,
2181   EVEX_W_0F381A_P_2,
2182   EVEX_W_0F381B_P_2,
2183   EVEX_W_0F381E_P_2,
2184   EVEX_W_0F381F_P_2,
2185   EVEX_W_0F3820_P_1,
2186   EVEX_W_0F3821_P_1,
2187   EVEX_W_0F3822_P_1,
2188   EVEX_W_0F3823_P_1,
2189   EVEX_W_0F3824_P_1,
2190   EVEX_W_0F3825_P_1,
2191   EVEX_W_0F3825_P_2,
2192   EVEX_W_0F3826_P_1,
2193   EVEX_W_0F3826_P_2,
2194   EVEX_W_0F3828_P_1,
2195   EVEX_W_0F3828_P_2,
2196   EVEX_W_0F3829_P_1,
2197   EVEX_W_0F3829_P_2,
2198   EVEX_W_0F382A_P_1,
2199   EVEX_W_0F382A_P_2,
2200   EVEX_W_0F382B_P_2,
2201   EVEX_W_0F3830_P_1,
2202   EVEX_W_0F3831_P_1,
2203   EVEX_W_0F3832_P_1,
2204   EVEX_W_0F3833_P_1,
2205   EVEX_W_0F3834_P_1,
2206   EVEX_W_0F3835_P_1,
2207   EVEX_W_0F3835_P_2,
2208   EVEX_W_0F3837_P_2,
2209   EVEX_W_0F3838_P_1,
2210   EVEX_W_0F3839_P_1,
2211   EVEX_W_0F383A_P_1,
2212   EVEX_W_0F3840_P_2,
2213   EVEX_W_0F3852_P_1,
2214   EVEX_W_0F3854_P_2,
2215   EVEX_W_0F3855_P_2,
2216   EVEX_W_0F3858_P_2,
2217   EVEX_W_0F3859_P_2,
2218   EVEX_W_0F385A_P_2,
2219   EVEX_W_0F385B_P_2,
2220   EVEX_W_0F3862_P_2,
2221   EVEX_W_0F3863_P_2,
2222   EVEX_W_0F3866_P_2,
2223   EVEX_W_0F3868_P_3,
2224   EVEX_W_0F3870_P_2,
2225   EVEX_W_0F3871_P_2,
2226   EVEX_W_0F3872_P_1,
2227   EVEX_W_0F3872_P_2,
2228   EVEX_W_0F3872_P_3,
2229   EVEX_W_0F3873_P_2,
2230   EVEX_W_0F3875_P_2,
2231   EVEX_W_0F3878_P_2,
2232   EVEX_W_0F3879_P_2,
2233   EVEX_W_0F387A_P_2,
2234   EVEX_W_0F387B_P_2,
2235   EVEX_W_0F387D_P_2,
2236   EVEX_W_0F3883_P_2,
2237   EVEX_W_0F388D_P_2,
2238   EVEX_W_0F3891_P_2,
2239   EVEX_W_0F3893_P_2,
2240   EVEX_W_0F38A1_P_2,
2241   EVEX_W_0F38A3_P_2,
2242   EVEX_W_0F38C7_R_1_P_2,
2243   EVEX_W_0F38C7_R_2_P_2,
2244   EVEX_W_0F38C7_R_5_P_2,
2245   EVEX_W_0F38C7_R_6_P_2,
2246
2247   EVEX_W_0F3A00_P_2,
2248   EVEX_W_0F3A01_P_2,
2249   EVEX_W_0F3A04_P_2,
2250   EVEX_W_0F3A05_P_2,
2251   EVEX_W_0F3A08_P_2,
2252   EVEX_W_0F3A09_P_2,
2253   EVEX_W_0F3A0A_P_2,
2254   EVEX_W_0F3A0B_P_2,
2255   EVEX_W_0F3A18_P_2,
2256   EVEX_W_0F3A19_P_2,
2257   EVEX_W_0F3A1A_P_2,
2258   EVEX_W_0F3A1B_P_2,
2259   EVEX_W_0F3A1D_P_2,
2260   EVEX_W_0F3A21_P_2,
2261   EVEX_W_0F3A23_P_2,
2262   EVEX_W_0F3A38_P_2,
2263   EVEX_W_0F3A39_P_2,
2264   EVEX_W_0F3A3A_P_2,
2265   EVEX_W_0F3A3B_P_2,
2266   EVEX_W_0F3A3E_P_2,
2267   EVEX_W_0F3A3F_P_2,
2268   EVEX_W_0F3A42_P_2,
2269   EVEX_W_0F3A43_P_2,
2270   EVEX_W_0F3A50_P_2,
2271   EVEX_W_0F3A51_P_2,
2272   EVEX_W_0F3A56_P_2,
2273   EVEX_W_0F3A57_P_2,
2274   EVEX_W_0F3A66_P_2,
2275   EVEX_W_0F3A67_P_2,
2276   EVEX_W_0F3A70_P_2,
2277   EVEX_W_0F3A71_P_2,
2278   EVEX_W_0F3A72_P_2,
2279   EVEX_W_0F3A73_P_2,
2280   EVEX_W_0F3ACE_P_2,
2281   EVEX_W_0F3ACF_P_2
2282 };
2283
2284 typedef void (*op_rtn) (int bytemode, int sizeflag);
2285
2286 struct dis386 {
2287   const char *name;
2288   struct
2289     {
2290       op_rtn rtn;
2291       int bytemode;
2292     } op[MAX_OPERANDS];
2293   unsigned int prefix_requirement;
2294 };
2295
2296 /* Upper case letters in the instruction names here are macros.
2297    'A' => print 'b' if no register operands or suffix_always is true
2298    'B' => print 'b' if suffix_always is true
2299    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2300           size prefix
2301    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2302           suffix_always is true
2303    'E' => print 'e' if 32-bit form of jcxz
2304    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2305    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2306    'H' => print ",pt" or ",pn" branch hint
2307    'I' => honor following macro letter even in Intel mode (implemented only
2308           for some of the macro letters)
2309    'J' => print 'l'
2310    'K' => print 'd' or 'q' if rex prefix is present.
2311    'L' => print 'l' if suffix_always is true
2312    'M' => print 'r' if intel_mnemonic is false.
2313    'N' => print 'n' if instruction has no wait "prefix"
2314    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2315    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2316           or suffix_always is true.  print 'q' if rex prefix is present.
2317    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2318           is true
2319    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2320    'S' => print 'w', 'l' or 'q' if suffix_always is true
2321    'T' => print 'q' in 64bit mode if instruction has no operand size
2322           prefix and behave as 'P' otherwise
2323    'U' => print 'q' in 64bit mode if instruction has no operand size
2324           prefix and behave as 'Q' otherwise
2325    'V' => print 'q' in 64bit mode if instruction has no operand size
2326           prefix and behave as 'S' otherwise
2327    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2328    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2329    'Y' unused.
2330    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2331    '!' => change condition from true to false or from false to true.
2332    '%' => add 1 upper case letter to the macro.
2333    '^' => print 'w' or 'l' depending on operand size prefix or
2334           suffix_always is true (lcall/ljmp).
2335    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2336           on operand size prefix.
2337    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2338           has no operand size prefix for AMD64 ISA, behave as 'P'
2339           otherwise
2340
2341    2 upper case letter macros:
2342    "XY" => print 'x' or 'y' if suffix_always is true or no register
2343            operands and no broadcast.
2344    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2345            register operands and no broadcast.
2346    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2347    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2348            or suffix_always is true
2349    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2350    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2351    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2352    "LW" => print 'd', 'q' depending on the VEX.W bit
2353    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2354            an operand size prefix, or suffix_always is true.  print
2355            'q' if rex prefix is present.
2356
2357    Many of the above letters print nothing in Intel mode.  See "putop"
2358    for the details.
2359
2360    Braces '{' and '}', and vertical bars '|', indicate alternative
2361    mnemonic strings for AT&T and Intel.  */
2362
2363 static const struct dis386 dis386[] = {
2364   /* 00 */
2365   { "addB",             { Ebh1, Gb }, 0 },
2366   { "addS",             { Evh1, Gv }, 0 },
2367   { "addB",             { Gb, EbS }, 0 },
2368   { "addS",             { Gv, EvS }, 0 },
2369   { "addB",             { AL, Ib }, 0 },
2370   { "addS",             { eAX, Iv }, 0 },
2371   { X86_64_TABLE (X86_64_06) },
2372   { X86_64_TABLE (X86_64_07) },
2373   /* 08 */
2374   { "orB",              { Ebh1, Gb }, 0 },
2375   { "orS",              { Evh1, Gv }, 0 },
2376   { "orB",              { Gb, EbS }, 0 },
2377   { "orS",              { Gv, EvS }, 0 },
2378   { "orB",              { AL, Ib }, 0 },
2379   { "orS",              { eAX, Iv }, 0 },
2380   { X86_64_TABLE (X86_64_0D) },
2381   { Bad_Opcode },       /* 0x0f extended opcode escape */
2382   /* 10 */
2383   { "adcB",             { Ebh1, Gb }, 0 },
2384   { "adcS",             { Evh1, Gv }, 0 },
2385   { "adcB",             { Gb, EbS }, 0 },
2386   { "adcS",             { Gv, EvS }, 0 },
2387   { "adcB",             { AL, Ib }, 0 },
2388   { "adcS",             { eAX, Iv }, 0 },
2389   { X86_64_TABLE (X86_64_16) },
2390   { X86_64_TABLE (X86_64_17) },
2391   /* 18 */
2392   { "sbbB",             { Ebh1, Gb }, 0 },
2393   { "sbbS",             { Evh1, Gv }, 0 },
2394   { "sbbB",             { Gb, EbS }, 0 },
2395   { "sbbS",             { Gv, EvS }, 0 },
2396   { "sbbB",             { AL, Ib }, 0 },
2397   { "sbbS",             { eAX, Iv }, 0 },
2398   { X86_64_TABLE (X86_64_1E) },
2399   { X86_64_TABLE (X86_64_1F) },
2400   /* 20 */
2401   { "andB",             { Ebh1, Gb }, 0 },
2402   { "andS",             { Evh1, Gv }, 0 },
2403   { "andB",             { Gb, EbS }, 0 },
2404   { "andS",             { Gv, EvS }, 0 },
2405   { "andB",             { AL, Ib }, 0 },
2406   { "andS",             { eAX, Iv }, 0 },
2407   { Bad_Opcode },       /* SEG ES prefix */
2408   { X86_64_TABLE (X86_64_27) },
2409   /* 28 */
2410   { "subB",             { Ebh1, Gb }, 0 },
2411   { "subS",             { Evh1, Gv }, 0 },
2412   { "subB",             { Gb, EbS }, 0 },
2413   { "subS",             { Gv, EvS }, 0 },
2414   { "subB",             { AL, Ib }, 0 },
2415   { "subS",             { eAX, Iv }, 0 },
2416   { Bad_Opcode },       /* SEG CS prefix */
2417   { X86_64_TABLE (X86_64_2F) },
2418   /* 30 */
2419   { "xorB",             { Ebh1, Gb }, 0 },
2420   { "xorS",             { Evh1, Gv }, 0 },
2421   { "xorB",             { Gb, EbS }, 0 },
2422   { "xorS",             { Gv, EvS }, 0 },
2423   { "xorB",             { AL, Ib }, 0 },
2424   { "xorS",             { eAX, Iv }, 0 },
2425   { Bad_Opcode },       /* SEG SS prefix */
2426   { X86_64_TABLE (X86_64_37) },
2427   /* 38 */
2428   { "cmpB",             { Eb, Gb }, 0 },
2429   { "cmpS",             { Ev, Gv }, 0 },
2430   { "cmpB",             { Gb, EbS }, 0 },
2431   { "cmpS",             { Gv, EvS }, 0 },
2432   { "cmpB",             { AL, Ib }, 0 },
2433   { "cmpS",             { eAX, Iv }, 0 },
2434   { Bad_Opcode },       /* SEG DS prefix */
2435   { X86_64_TABLE (X86_64_3F) },
2436   /* 40 */
2437   { "inc{S|}",          { RMeAX }, 0 },
2438   { "inc{S|}",          { RMeCX }, 0 },
2439   { "inc{S|}",          { RMeDX }, 0 },
2440   { "inc{S|}",          { RMeBX }, 0 },
2441   { "inc{S|}",          { RMeSP }, 0 },
2442   { "inc{S|}",          { RMeBP }, 0 },
2443   { "inc{S|}",          { RMeSI }, 0 },
2444   { "inc{S|}",          { RMeDI }, 0 },
2445   /* 48 */
2446   { "dec{S|}",          { RMeAX }, 0 },
2447   { "dec{S|}",          { RMeCX }, 0 },
2448   { "dec{S|}",          { RMeDX }, 0 },
2449   { "dec{S|}",          { RMeBX }, 0 },
2450   { "dec{S|}",          { RMeSP }, 0 },
2451   { "dec{S|}",          { RMeBP }, 0 },
2452   { "dec{S|}",          { RMeSI }, 0 },
2453   { "dec{S|}",          { RMeDI }, 0 },
2454   /* 50 */
2455   { "pushV",            { RMrAX }, 0 },
2456   { "pushV",            { RMrCX }, 0 },
2457   { "pushV",            { RMrDX }, 0 },
2458   { "pushV",            { RMrBX }, 0 },
2459   { "pushV",            { RMrSP }, 0 },
2460   { "pushV",            { RMrBP }, 0 },
2461   { "pushV",            { RMrSI }, 0 },
2462   { "pushV",            { RMrDI }, 0 },
2463   /* 58 */
2464   { "popV",             { RMrAX }, 0 },
2465   { "popV",             { RMrCX }, 0 },
2466   { "popV",             { RMrDX }, 0 },
2467   { "popV",             { RMrBX }, 0 },
2468   { "popV",             { RMrSP }, 0 },
2469   { "popV",             { RMrBP }, 0 },
2470   { "popV",             { RMrSI }, 0 },
2471   { "popV",             { RMrDI }, 0 },
2472   /* 60 */
2473   { X86_64_TABLE (X86_64_60) },
2474   { X86_64_TABLE (X86_64_61) },
2475   { X86_64_TABLE (X86_64_62) },
2476   { X86_64_TABLE (X86_64_63) },
2477   { Bad_Opcode },       /* seg fs */
2478   { Bad_Opcode },       /* seg gs */
2479   { Bad_Opcode },       /* op size prefix */
2480   { Bad_Opcode },       /* adr size prefix */
2481   /* 68 */
2482   { "pushT",            { sIv }, 0 },
2483   { "imulS",            { Gv, Ev, Iv }, 0 },
2484   { "pushT",            { sIbT }, 0 },
2485   { "imulS",            { Gv, Ev, sIb }, 0 },
2486   { "ins{b|}",          { Ybr, indirDX }, 0 },
2487   { X86_64_TABLE (X86_64_6D) },
2488   { "outs{b|}",         { indirDXr, Xb }, 0 },
2489   { X86_64_TABLE (X86_64_6F) },
2490   /* 70 */
2491   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2492   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2493   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2494   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2495   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2496   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2497   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2498   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2499   /* 78 */
2500   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2501   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2502   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2503   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2504   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2505   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2506   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2507   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2508   /* 80 */
2509   { REG_TABLE (REG_80) },
2510   { REG_TABLE (REG_81) },
2511   { X86_64_TABLE (X86_64_82) },
2512   { REG_TABLE (REG_83) },
2513   { "testB",            { Eb, Gb }, 0 },
2514   { "testS",            { Ev, Gv }, 0 },
2515   { "xchgB",            { Ebh2, Gb }, 0 },
2516   { "xchgS",            { Evh2, Gv }, 0 },
2517   /* 88 */
2518   { "movB",             { Ebh3, Gb }, 0 },
2519   { "movS",             { Evh3, Gv }, 0 },
2520   { "movB",             { Gb, EbS }, 0 },
2521   { "movS",             { Gv, EvS }, 0 },
2522   { "movD",             { Sv, Sw }, 0 },
2523   { MOD_TABLE (MOD_8D) },
2524   { "movD",             { Sw, Sv }, 0 },
2525   { REG_TABLE (REG_8F) },
2526   /* 90 */
2527   { PREFIX_TABLE (PREFIX_90) },
2528   { "xchgS",            { RMeCX, eAX }, 0 },
2529   { "xchgS",            { RMeDX, eAX }, 0 },
2530   { "xchgS",            { RMeBX, eAX }, 0 },
2531   { "xchgS",            { RMeSP, eAX }, 0 },
2532   { "xchgS",            { RMeBP, eAX }, 0 },
2533   { "xchgS",            { RMeSI, eAX }, 0 },
2534   { "xchgS",            { RMeDI, eAX }, 0 },
2535   /* 98 */
2536   { "cW{t|}R",          { XX }, 0 },
2537   { "cR{t|}O",          { XX }, 0 },
2538   { X86_64_TABLE (X86_64_9A) },
2539   { Bad_Opcode },       /* fwait */
2540   { "pushfT",           { XX }, 0 },
2541   { "popfT",            { XX }, 0 },
2542   { "sahf",             { XX }, 0 },
2543   { "lahf",             { XX }, 0 },
2544   /* a0 */
2545   { "mov%LB",           { AL, Ob }, 0 },
2546   { "mov%LS",           { eAX, Ov }, 0 },
2547   { "mov%LB",           { Ob, AL }, 0 },
2548   { "mov%LS",           { Ov, eAX }, 0 },
2549   { "movs{b|}",         { Ybr, Xb }, 0 },
2550   { "movs{R|}",         { Yvr, Xv }, 0 },
2551   { "cmps{b|}",         { Xb, Yb }, 0 },
2552   { "cmps{R|}",         { Xv, Yv }, 0 },
2553   /* a8 */
2554   { "testB",            { AL, Ib }, 0 },
2555   { "testS",            { eAX, Iv }, 0 },
2556   { "stosB",            { Ybr, AL }, 0 },
2557   { "stosS",            { Yvr, eAX }, 0 },
2558   { "lodsB",            { ALr, Xb }, 0 },
2559   { "lodsS",            { eAXr, Xv }, 0 },
2560   { "scasB",            { AL, Yb }, 0 },
2561   { "scasS",            { eAX, Yv }, 0 },
2562   /* b0 */
2563   { "movB",             { RMAL, Ib }, 0 },
2564   { "movB",             { RMCL, Ib }, 0 },
2565   { "movB",             { RMDL, Ib }, 0 },
2566   { "movB",             { RMBL, Ib }, 0 },
2567   { "movB",             { RMAH, Ib }, 0 },
2568   { "movB",             { RMCH, Ib }, 0 },
2569   { "movB",             { RMDH, Ib }, 0 },
2570   { "movB",             { RMBH, Ib }, 0 },
2571   /* b8 */
2572   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2573   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2574   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2575   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2576   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2577   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2578   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2579   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2580   /* c0 */
2581   { REG_TABLE (REG_C0) },
2582   { REG_TABLE (REG_C1) },
2583   { "retT",             { Iw, BND }, 0 },
2584   { "retT",             { BND }, 0 },
2585   { X86_64_TABLE (X86_64_C4) },
2586   { X86_64_TABLE (X86_64_C5) },
2587   { REG_TABLE (REG_C6) },
2588   { REG_TABLE (REG_C7) },
2589   /* c8 */
2590   { "enterT",           { Iw, Ib }, 0 },
2591   { "leaveT",           { XX }, 0 },
2592   { "Jret{|f}P",        { Iw }, 0 },
2593   { "Jret{|f}P",        { XX }, 0 },
2594   { "int3",             { XX }, 0 },
2595   { "int",              { Ib }, 0 },
2596   { X86_64_TABLE (X86_64_CE) },
2597   { "iret%LP",          { XX }, 0 },
2598   /* d0 */
2599   { REG_TABLE (REG_D0) },
2600   { REG_TABLE (REG_D1) },
2601   { REG_TABLE (REG_D2) },
2602   { REG_TABLE (REG_D3) },
2603   { X86_64_TABLE (X86_64_D4) },
2604   { X86_64_TABLE (X86_64_D5) },
2605   { Bad_Opcode },
2606   { "xlat",             { DSBX }, 0 },
2607   /* d8 */
2608   { FLOAT },
2609   { FLOAT },
2610   { FLOAT },
2611   { FLOAT },
2612   { FLOAT },
2613   { FLOAT },
2614   { FLOAT },
2615   { FLOAT },
2616   /* e0 */
2617   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2618   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2619   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2620   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2621   { "inB",              { AL, Ib }, 0 },
2622   { "inG",              { zAX, Ib }, 0 },
2623   { "outB",             { Ib, AL }, 0 },
2624   { "outG",             { Ib, zAX }, 0 },
2625   /* e8 */
2626   { X86_64_TABLE (X86_64_E8) },
2627   { X86_64_TABLE (X86_64_E9) },
2628   { X86_64_TABLE (X86_64_EA) },
2629   { "jmp",              { Jb, BND }, 0 },
2630   { "inB",              { AL, indirDX }, 0 },
2631   { "inG",              { zAX, indirDX }, 0 },
2632   { "outB",             { indirDX, AL }, 0 },
2633   { "outG",             { indirDX, zAX }, 0 },
2634   /* f0 */
2635   { Bad_Opcode },       /* lock prefix */
2636   { "icebp",            { XX }, 0 },
2637   { Bad_Opcode },       /* repne */
2638   { Bad_Opcode },       /* repz */
2639   { "hlt",              { XX }, 0 },
2640   { "cmc",              { XX }, 0 },
2641   { REG_TABLE (REG_F6) },
2642   { REG_TABLE (REG_F7) },
2643   /* f8 */
2644   { "clc",              { XX }, 0 },
2645   { "stc",              { XX }, 0 },
2646   { "cli",              { XX }, 0 },
2647   { "sti",              { XX }, 0 },
2648   { "cld",              { XX }, 0 },
2649   { "std",              { XX }, 0 },
2650   { REG_TABLE (REG_FE) },
2651   { REG_TABLE (REG_FF) },
2652 };
2653
2654 static const struct dis386 dis386_twobyte[] = {
2655   /* 00 */
2656   { REG_TABLE (REG_0F00 ) },
2657   { REG_TABLE (REG_0F01 ) },
2658   { "larS",             { Gv, Ew }, 0 },
2659   { "lslS",             { Gv, Ew }, 0 },
2660   { Bad_Opcode },
2661   { "syscall",          { XX }, 0 },
2662   { "clts",             { XX }, 0 },
2663   { "sysret%LP",                { XX }, 0 },
2664   /* 08 */
2665   { "invd",             { XX }, 0 },
2666   { PREFIX_TABLE (PREFIX_0F09) },
2667   { Bad_Opcode },
2668   { "ud2",              { XX }, 0 },
2669   { Bad_Opcode },
2670   { REG_TABLE (REG_0F0D) },
2671   { "femms",            { XX }, 0 },
2672   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2673   /* 10 */
2674   { PREFIX_TABLE (PREFIX_0F10) },
2675   { PREFIX_TABLE (PREFIX_0F11) },
2676   { PREFIX_TABLE (PREFIX_0F12) },
2677   { MOD_TABLE (MOD_0F13) },
2678   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2679   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2680   { PREFIX_TABLE (PREFIX_0F16) },
2681   { MOD_TABLE (MOD_0F17) },
2682   /* 18 */
2683   { REG_TABLE (REG_0F18) },
2684   { "nopQ",             { Ev }, 0 },
2685   { PREFIX_TABLE (PREFIX_0F1A) },
2686   { PREFIX_TABLE (PREFIX_0F1B) },
2687   { PREFIX_TABLE (PREFIX_0F1C) },
2688   { "nopQ",             { Ev }, 0 },
2689   { PREFIX_TABLE (PREFIX_0F1E) },
2690   { "nopQ",             { Ev }, 0 },
2691   /* 20 */
2692   { "movZ",             { Rm, Cm }, 0 },
2693   { "movZ",             { Rm, Dm }, 0 },
2694   { "movZ",             { Cm, Rm }, 0 },
2695   { "movZ",             { Dm, Rm }, 0 },
2696   { MOD_TABLE (MOD_0F24) },
2697   { Bad_Opcode },
2698   { MOD_TABLE (MOD_0F26) },
2699   { Bad_Opcode },
2700   /* 28 */
2701   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2702   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2703   { PREFIX_TABLE (PREFIX_0F2A) },
2704   { PREFIX_TABLE (PREFIX_0F2B) },
2705   { PREFIX_TABLE (PREFIX_0F2C) },
2706   { PREFIX_TABLE (PREFIX_0F2D) },
2707   { PREFIX_TABLE (PREFIX_0F2E) },
2708   { PREFIX_TABLE (PREFIX_0F2F) },
2709   /* 30 */
2710   { "wrmsr",            { XX }, 0 },
2711   { "rdtsc",            { XX }, 0 },
2712   { "rdmsr",            { XX }, 0 },
2713   { "rdpmc",            { XX }, 0 },
2714   { "sysenter",         { XX }, 0 },
2715   { "sysexit",          { XX }, 0 },
2716   { Bad_Opcode },
2717   { "getsec",           { XX }, 0 },
2718   /* 38 */
2719   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2720   { Bad_Opcode },
2721   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2722   { Bad_Opcode },
2723   { Bad_Opcode },
2724   { Bad_Opcode },
2725   { Bad_Opcode },
2726   { Bad_Opcode },
2727   /* 40 */
2728   { "cmovoS",           { Gv, Ev }, 0 },
2729   { "cmovnoS",          { Gv, Ev }, 0 },
2730   { "cmovbS",           { Gv, Ev }, 0 },
2731   { "cmovaeS",          { Gv, Ev }, 0 },
2732   { "cmoveS",           { Gv, Ev }, 0 },
2733   { "cmovneS",          { Gv, Ev }, 0 },
2734   { "cmovbeS",          { Gv, Ev }, 0 },
2735   { "cmovaS",           { Gv, Ev }, 0 },
2736   /* 48 */
2737   { "cmovsS",           { Gv, Ev }, 0 },
2738   { "cmovnsS",          { Gv, Ev }, 0 },
2739   { "cmovpS",           { Gv, Ev }, 0 },
2740   { "cmovnpS",          { Gv, Ev }, 0 },
2741   { "cmovlS",           { Gv, Ev }, 0 },
2742   { "cmovgeS",          { Gv, Ev }, 0 },
2743   { "cmovleS",          { Gv, Ev }, 0 },
2744   { "cmovgS",           { Gv, Ev }, 0 },
2745   /* 50 */
2746   { MOD_TABLE (MOD_0F51) },
2747   { PREFIX_TABLE (PREFIX_0F51) },
2748   { PREFIX_TABLE (PREFIX_0F52) },
2749   { PREFIX_TABLE (PREFIX_0F53) },
2750   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2751   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2752   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2753   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2754   /* 58 */
2755   { PREFIX_TABLE (PREFIX_0F58) },
2756   { PREFIX_TABLE (PREFIX_0F59) },
2757   { PREFIX_TABLE (PREFIX_0F5A) },
2758   { PREFIX_TABLE (PREFIX_0F5B) },
2759   { PREFIX_TABLE (PREFIX_0F5C) },
2760   { PREFIX_TABLE (PREFIX_0F5D) },
2761   { PREFIX_TABLE (PREFIX_0F5E) },
2762   { PREFIX_TABLE (PREFIX_0F5F) },
2763   /* 60 */
2764   { PREFIX_TABLE (PREFIX_0F60) },
2765   { PREFIX_TABLE (PREFIX_0F61) },
2766   { PREFIX_TABLE (PREFIX_0F62) },
2767   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2768   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2769   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2770   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2771   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2772   /* 68 */
2773   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2774   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2775   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2776   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2777   { PREFIX_TABLE (PREFIX_0F6C) },
2778   { PREFIX_TABLE (PREFIX_0F6D) },
2779   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2780   { PREFIX_TABLE (PREFIX_0F6F) },
2781   /* 70 */
2782   { PREFIX_TABLE (PREFIX_0F70) },
2783   { REG_TABLE (REG_0F71) },
2784   { REG_TABLE (REG_0F72) },
2785   { REG_TABLE (REG_0F73) },
2786   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2787   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2788   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2789   { "emms",             { XX }, PREFIX_OPCODE },
2790   /* 78 */
2791   { PREFIX_TABLE (PREFIX_0F78) },
2792   { PREFIX_TABLE (PREFIX_0F79) },
2793   { Bad_Opcode },
2794   { Bad_Opcode },
2795   { PREFIX_TABLE (PREFIX_0F7C) },
2796   { PREFIX_TABLE (PREFIX_0F7D) },
2797   { PREFIX_TABLE (PREFIX_0F7E) },
2798   { PREFIX_TABLE (PREFIX_0F7F) },
2799   /* 80 */
2800   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2801   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2802   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2803   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2804   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2805   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2806   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2807   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2808   /* 88 */
2809   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2810   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2811   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2812   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2813   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2814   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2815   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2816   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2817   /* 90 */
2818   { "seto",             { Eb }, 0 },
2819   { "setno",            { Eb }, 0 },
2820   { "setb",             { Eb }, 0 },
2821   { "setae",            { Eb }, 0 },
2822   { "sete",             { Eb }, 0 },
2823   { "setne",            { Eb }, 0 },
2824   { "setbe",            { Eb }, 0 },
2825   { "seta",             { Eb }, 0 },
2826   /* 98 */
2827   { "sets",             { Eb }, 0 },
2828   { "setns",            { Eb }, 0 },
2829   { "setp",             { Eb }, 0 },
2830   { "setnp",            { Eb }, 0 },
2831   { "setl",             { Eb }, 0 },
2832   { "setge",            { Eb }, 0 },
2833   { "setle",            { Eb }, 0 },
2834   { "setg",             { Eb }, 0 },
2835   /* a0 */
2836   { "pushT",            { fs }, 0 },
2837   { "popT",             { fs }, 0 },
2838   { "cpuid",            { XX }, 0 },
2839   { "btS",              { Ev, Gv }, 0 },
2840   { "shldS",            { Ev, Gv, Ib }, 0 },
2841   { "shldS",            { Ev, Gv, CL }, 0 },
2842   { REG_TABLE (REG_0FA6) },
2843   { REG_TABLE (REG_0FA7) },
2844   /* a8 */
2845   { "pushT",            { gs }, 0 },
2846   { "popT",             { gs }, 0 },
2847   { "rsm",              { XX }, 0 },
2848   { "btsS",             { Evh1, Gv }, 0 },
2849   { "shrdS",            { Ev, Gv, Ib }, 0 },
2850   { "shrdS",            { Ev, Gv, CL }, 0 },
2851   { REG_TABLE (REG_0FAE) },
2852   { "imulS",            { Gv, Ev }, 0 },
2853   /* b0 */
2854   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2855   { "cmpxchgS",         { Evh1, Gv }, 0 },
2856   { MOD_TABLE (MOD_0FB2) },
2857   { "btrS",             { Evh1, Gv }, 0 },
2858   { MOD_TABLE (MOD_0FB4) },
2859   { MOD_TABLE (MOD_0FB5) },
2860   { "movz{bR|x}",       { Gv, Eb }, 0 },
2861   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2862   /* b8 */
2863   { PREFIX_TABLE (PREFIX_0FB8) },
2864   { "ud1S",             { Gv, Ev }, 0 },
2865   { REG_TABLE (REG_0FBA) },
2866   { "btcS",             { Evh1, Gv }, 0 },
2867   { PREFIX_TABLE (PREFIX_0FBC) },
2868   { PREFIX_TABLE (PREFIX_0FBD) },
2869   { "movs{bR|x}",       { Gv, Eb }, 0 },
2870   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2871   /* c0 */
2872   { "xaddB",            { Ebh1, Gb }, 0 },
2873   { "xaddS",            { Evh1, Gv }, 0 },
2874   { PREFIX_TABLE (PREFIX_0FC2) },
2875   { MOD_TABLE (MOD_0FC3) },
2876   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2877   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2878   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2879   { REG_TABLE (REG_0FC7) },
2880   /* c8 */
2881   { "bswap",            { RMeAX }, 0 },
2882   { "bswap",            { RMeCX }, 0 },
2883   { "bswap",            { RMeDX }, 0 },
2884   { "bswap",            { RMeBX }, 0 },
2885   { "bswap",            { RMeSP }, 0 },
2886   { "bswap",            { RMeBP }, 0 },
2887   { "bswap",            { RMeSI }, 0 },
2888   { "bswap",            { RMeDI }, 0 },
2889   /* d0 */
2890   { PREFIX_TABLE (PREFIX_0FD0) },
2891   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2892   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2893   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2894   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2895   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2896   { PREFIX_TABLE (PREFIX_0FD6) },
2897   { MOD_TABLE (MOD_0FD7) },
2898   /* d8 */
2899   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2900   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2901   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2902   { "pand",             { MX, EM }, PREFIX_OPCODE },
2903   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2904   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2905   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2906   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2907   /* e0 */
2908   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2909   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2910   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2911   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2912   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2913   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2914   { PREFIX_TABLE (PREFIX_0FE6) },
2915   { PREFIX_TABLE (PREFIX_0FE7) },
2916   /* e8 */
2917   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2918   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2919   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2920   { "por",              { MX, EM }, PREFIX_OPCODE },
2921   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2922   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2923   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2924   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2925   /* f0 */
2926   { PREFIX_TABLE (PREFIX_0FF0) },
2927   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2928   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2929   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2930   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2931   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2932   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2933   { PREFIX_TABLE (PREFIX_0FF7) },
2934   /* f8 */
2935   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2936   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2937   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2938   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2939   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2940   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2941   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2942   { "ud0S",             { Gv, Ev }, 0 },
2943 };
2944
2945 static const unsigned char onebyte_has_modrm[256] = {
2946   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2947   /*       -------------------------------        */
2948   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2949   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2950   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2951   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2952   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2953   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2954   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2955   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2956   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2957   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2958   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2959   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2960   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2961   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2962   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2963   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2964   /*       -------------------------------        */
2965   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2966 };
2967
2968 static const unsigned char twobyte_has_modrm[256] = {
2969   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2970   /*       -------------------------------        */
2971   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2972   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2973   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2974   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2975   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2976   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2977   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2978   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2979   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2980   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2981   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2982   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2983   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2984   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2985   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2986   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2987   /*       -------------------------------        */
2988   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2989 };
2990
2991 static char obuf[100];
2992 static char *obufp;
2993 static char *mnemonicendp;
2994 static char scratchbuf[100];
2995 static unsigned char *start_codep;
2996 static unsigned char *insn_codep;
2997 static unsigned char *codep;
2998 static unsigned char *end_codep;
2999 static int last_lock_prefix;
3000 static int last_repz_prefix;
3001 static int last_repnz_prefix;
3002 static int last_data_prefix;
3003 static int last_addr_prefix;
3004 static int last_rex_prefix;
3005 static int last_seg_prefix;
3006 static int fwait_prefix;
3007 /* The active segment register prefix.  */
3008 static int active_seg_prefix;
3009 #define MAX_CODE_LENGTH 15
3010 /* We can up to 14 prefixes since the maximum instruction length is
3011    15bytes.  */
3012 static int all_prefixes[MAX_CODE_LENGTH - 1];
3013 static disassemble_info *the_info;
3014 static struct
3015   {
3016     int mod;
3017     int reg;
3018     int rm;
3019   }
3020 modrm;
3021 static unsigned char need_modrm;
3022 static struct
3023   {
3024     int scale;
3025     int index;
3026     int base;
3027   }
3028 sib;
3029 static struct
3030   {
3031     int register_specifier;
3032     int length;
3033     int prefix;
3034     int w;
3035     int evex;
3036     int r;
3037     int v;
3038     int mask_register_specifier;
3039     int zeroing;
3040     int ll;
3041     int b;
3042   }
3043 vex;
3044 static unsigned char need_vex;
3045 static unsigned char need_vex_reg;
3046 static unsigned char vex_w_done;
3047
3048 struct op
3049   {
3050     const char *name;
3051     unsigned int len;
3052   };
3053
3054 /* If we are accessing mod/rm/reg without need_modrm set, then the
3055    values are stale.  Hitting this abort likely indicates that you
3056    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3057 #define MODRM_CHECK  if (!need_modrm) abort ()
3058
3059 static const char **names64;
3060 static const char **names32;
3061 static const char **names16;
3062 static const char **names8;
3063 static const char **names8rex;
3064 static const char **names_seg;
3065 static const char *index64;
3066 static const char *index32;
3067 static const char **index16;
3068 static const char **names_bnd;
3069
3070 static const char *intel_names64[] = {
3071   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3072   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3073 };
3074 static const char *intel_names32[] = {
3075   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3076   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3077 };
3078 static const char *intel_names16[] = {
3079   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3080   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3081 };
3082 static const char *intel_names8[] = {
3083   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3084 };
3085 static const char *intel_names8rex[] = {
3086   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3087   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3088 };
3089 static const char *intel_names_seg[] = {
3090   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3091 };
3092 static const char *intel_index64 = "riz";
3093 static const char *intel_index32 = "eiz";
3094 static const char *intel_index16[] = {
3095   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3096 };
3097
3098 static const char *att_names64[] = {
3099   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3100   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3101 };
3102 static const char *att_names32[] = {
3103   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3104   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3105 };
3106 static const char *att_names16[] = {
3107   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3108   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3109 };
3110 static const char *att_names8[] = {
3111   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3112 };
3113 static const char *att_names8rex[] = {
3114   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3115   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3116 };
3117 static const char *att_names_seg[] = {
3118   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3119 };
3120 static const char *att_index64 = "%riz";
3121 static const char *att_index32 = "%eiz";
3122 static const char *att_index16[] = {
3123   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3124 };
3125
3126 static const char **names_mm;
3127 static const char *intel_names_mm[] = {
3128   "mm0", "mm1", "mm2", "mm3",
3129   "mm4", "mm5", "mm6", "mm7"
3130 };
3131 static const char *att_names_mm[] = {
3132   "%mm0", "%mm1", "%mm2", "%mm3",
3133   "%mm4", "%mm5", "%mm6", "%mm7"
3134 };
3135
3136 static const char *intel_names_bnd[] = {
3137   "bnd0", "bnd1", "bnd2", "bnd3"
3138 };
3139
3140 static const char *att_names_bnd[] = {
3141   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3142 };
3143
3144 static const char **names_xmm;
3145 static const char *intel_names_xmm[] = {
3146   "xmm0", "xmm1", "xmm2", "xmm3",
3147   "xmm4", "xmm5", "xmm6", "xmm7",
3148   "xmm8", "xmm9", "xmm10", "xmm11",
3149   "xmm12", "xmm13", "xmm14", "xmm15",
3150   "xmm16", "xmm17", "xmm18", "xmm19",
3151   "xmm20", "xmm21", "xmm22", "xmm23",
3152   "xmm24", "xmm25", "xmm26", "xmm27",
3153   "xmm28", "xmm29", "xmm30", "xmm31"
3154 };
3155 static const char *att_names_xmm[] = {
3156   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3157   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3158   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3159   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3160   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3161   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3162   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3163   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3164 };
3165
3166 static const char **names_ymm;
3167 static const char *intel_names_ymm[] = {
3168   "ymm0", "ymm1", "ymm2", "ymm3",
3169   "ymm4", "ymm5", "ymm6", "ymm7",
3170   "ymm8", "ymm9", "ymm10", "ymm11",
3171   "ymm12", "ymm13", "ymm14", "ymm15",
3172   "ymm16", "ymm17", "ymm18", "ymm19",
3173   "ymm20", "ymm21", "ymm22", "ymm23",
3174   "ymm24", "ymm25", "ymm26", "ymm27",
3175   "ymm28", "ymm29", "ymm30", "ymm31"
3176 };
3177 static const char *att_names_ymm[] = {
3178   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3179   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3180   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3181   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3182   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3183   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3184   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3185   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3186 };
3187
3188 static const char **names_zmm;
3189 static const char *intel_names_zmm[] = {
3190   "zmm0", "zmm1", "zmm2", "zmm3",
3191   "zmm4", "zmm5", "zmm6", "zmm7",
3192   "zmm8", "zmm9", "zmm10", "zmm11",
3193   "zmm12", "zmm13", "zmm14", "zmm15",
3194   "zmm16", "zmm17", "zmm18", "zmm19",
3195   "zmm20", "zmm21", "zmm22", "zmm23",
3196   "zmm24", "zmm25", "zmm26", "zmm27",
3197   "zmm28", "zmm29", "zmm30", "zmm31"
3198 };
3199 static const char *att_names_zmm[] = {
3200   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3201   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3202   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3203   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3204   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3205   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3206   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3207   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3208 };
3209
3210 static const char **names_mask;
3211 static const char *intel_names_mask[] = {
3212   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3213 };
3214 static const char *att_names_mask[] = {
3215   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3216 };
3217
3218 static const char *names_rounding[] =
3219 {
3220   "{rn-sae}",
3221   "{rd-sae}",
3222   "{ru-sae}",
3223   "{rz-sae}"
3224 };
3225
3226 static const struct dis386 reg_table[][8] = {
3227   /* REG_80 */
3228   {
3229     { "addA",   { Ebh1, Ib }, 0 },
3230     { "orA",    { Ebh1, Ib }, 0 },
3231     { "adcA",   { Ebh1, Ib }, 0 },
3232     { "sbbA",   { Ebh1, Ib }, 0 },
3233     { "andA",   { Ebh1, Ib }, 0 },
3234     { "subA",   { Ebh1, Ib }, 0 },
3235     { "xorA",   { Ebh1, Ib }, 0 },
3236     { "cmpA",   { Eb, Ib }, 0 },
3237   },
3238   /* REG_81 */
3239   {
3240     { "addQ",   { Evh1, Iv }, 0 },
3241     { "orQ",    { Evh1, Iv }, 0 },
3242     { "adcQ",   { Evh1, Iv }, 0 },
3243     { "sbbQ",   { Evh1, Iv }, 0 },
3244     { "andQ",   { Evh1, Iv }, 0 },
3245     { "subQ",   { Evh1, Iv }, 0 },
3246     { "xorQ",   { Evh1, Iv }, 0 },
3247     { "cmpQ",   { Ev, Iv }, 0 },
3248   },
3249   /* REG_83 */
3250   {
3251     { "addQ",   { Evh1, sIb }, 0 },
3252     { "orQ",    { Evh1, sIb }, 0 },
3253     { "adcQ",   { Evh1, sIb }, 0 },
3254     { "sbbQ",   { Evh1, sIb }, 0 },
3255     { "andQ",   { Evh1, sIb }, 0 },
3256     { "subQ",   { Evh1, sIb }, 0 },
3257     { "xorQ",   { Evh1, sIb }, 0 },
3258     { "cmpQ",   { Ev, sIb }, 0 },
3259   },
3260   /* REG_8F */
3261   {
3262     { "popU",   { stackEv }, 0 },
3263     { XOP_8F_TABLE (XOP_09) },
3264     { Bad_Opcode },
3265     { Bad_Opcode },
3266     { Bad_Opcode },
3267     { XOP_8F_TABLE (XOP_09) },
3268   },
3269   /* REG_C0 */
3270   {
3271     { "rolA",   { Eb, Ib }, 0 },
3272     { "rorA",   { Eb, Ib }, 0 },
3273     { "rclA",   { Eb, Ib }, 0 },
3274     { "rcrA",   { Eb, Ib }, 0 },
3275     { "shlA",   { Eb, Ib }, 0 },
3276     { "shrA",   { Eb, Ib }, 0 },
3277     { "shlA",   { Eb, Ib }, 0 },
3278     { "sarA",   { Eb, Ib }, 0 },
3279   },
3280   /* REG_C1 */
3281   {
3282     { "rolQ",   { Ev, Ib }, 0 },
3283     { "rorQ",   { Ev, Ib }, 0 },
3284     { "rclQ",   { Ev, Ib }, 0 },
3285     { "rcrQ",   { Ev, Ib }, 0 },
3286     { "shlQ",   { Ev, Ib }, 0 },
3287     { "shrQ",   { Ev, Ib }, 0 },
3288     { "shlQ",   { Ev, Ib }, 0 },
3289     { "sarQ",   { Ev, Ib }, 0 },
3290   },
3291   /* REG_C6 */
3292   {
3293     { "movA",   { Ebh3, Ib }, 0 },
3294     { Bad_Opcode },
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { MOD_TABLE (MOD_C6_REG_7) },
3301   },
3302   /* REG_C7 */
3303   {
3304     { "movQ",   { Evh3, Iv }, 0 },
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { MOD_TABLE (MOD_C7_REG_7) },
3312   },
3313   /* REG_D0 */
3314   {
3315     { "rolA",   { Eb, I1 }, 0 },
3316     { "rorA",   { Eb, I1 }, 0 },
3317     { "rclA",   { Eb, I1 }, 0 },
3318     { "rcrA",   { Eb, I1 }, 0 },
3319     { "shlA",   { Eb, I1 }, 0 },
3320     { "shrA",   { Eb, I1 }, 0 },
3321     { "shlA",   { Eb, I1 }, 0 },
3322     { "sarA",   { Eb, I1 }, 0 },
3323   },
3324   /* REG_D1 */
3325   {
3326     { "rolQ",   { Ev, I1 }, 0 },
3327     { "rorQ",   { Ev, I1 }, 0 },
3328     { "rclQ",   { Ev, I1 }, 0 },
3329     { "rcrQ",   { Ev, I1 }, 0 },
3330     { "shlQ",   { Ev, I1 }, 0 },
3331     { "shrQ",   { Ev, I1 }, 0 },
3332     { "shlQ",   { Ev, I1 }, 0 },
3333     { "sarQ",   { Ev, I1 }, 0 },
3334   },
3335   /* REG_D2 */
3336   {
3337     { "rolA",   { Eb, CL }, 0 },
3338     { "rorA",   { Eb, CL }, 0 },
3339     { "rclA",   { Eb, CL }, 0 },
3340     { "rcrA",   { Eb, CL }, 0 },
3341     { "shlA",   { Eb, CL }, 0 },
3342     { "shrA",   { Eb, CL }, 0 },
3343     { "shlA",   { Eb, CL }, 0 },
3344     { "sarA",   { Eb, CL }, 0 },
3345   },
3346   /* REG_D3 */
3347   {
3348     { "rolQ",   { Ev, CL }, 0 },
3349     { "rorQ",   { Ev, CL }, 0 },
3350     { "rclQ",   { Ev, CL }, 0 },
3351     { "rcrQ",   { Ev, CL }, 0 },
3352     { "shlQ",   { Ev, CL }, 0 },
3353     { "shrQ",   { Ev, CL }, 0 },
3354     { "shlQ",   { Ev, CL }, 0 },
3355     { "sarQ",   { Ev, CL }, 0 },
3356   },
3357   /* REG_F6 */
3358   {
3359     { "testA",  { Eb, Ib }, 0 },
3360     { "testA",  { Eb, Ib }, 0 },
3361     { "notA",   { Ebh1 }, 0 },
3362     { "negA",   { Ebh1 }, 0 },
3363     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3364     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3365     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3366     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3367   },
3368   /* REG_F7 */
3369   {
3370     { "testQ",  { Ev, Iv }, 0 },
3371     { "testQ",  { Ev, Iv }, 0 },
3372     { "notQ",   { Evh1 }, 0 },
3373     { "negQ",   { Evh1 }, 0 },
3374     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3375     { "imulQ",  { Ev }, 0 },
3376     { "divQ",   { Ev }, 0 },
3377     { "idivQ",  { Ev }, 0 },
3378   },
3379   /* REG_FE */
3380   {
3381     { "incA",   { Ebh1 }, 0 },
3382     { "decA",   { Ebh1 }, 0 },
3383   },
3384   /* REG_FF */
3385   {
3386     { "incQ",   { Evh1 }, 0 },
3387     { "decQ",   { Evh1 }, 0 },
3388     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3389     { MOD_TABLE (MOD_FF_REG_3) },
3390     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3391     { MOD_TABLE (MOD_FF_REG_5) },
3392     { "pushU",  { stackEv }, 0 },
3393     { Bad_Opcode },
3394   },
3395   /* REG_0F00 */
3396   {
3397     { "sldtD",  { Sv }, 0 },
3398     { "strD",   { Sv }, 0 },
3399     { "lldt",   { Ew }, 0 },
3400     { "ltr",    { Ew }, 0 },
3401     { "verr",   { Ew }, 0 },
3402     { "verw",   { Ew }, 0 },
3403     { Bad_Opcode },
3404     { Bad_Opcode },
3405   },
3406   /* REG_0F01 */
3407   {
3408     { MOD_TABLE (MOD_0F01_REG_0) },
3409     { MOD_TABLE (MOD_0F01_REG_1) },
3410     { MOD_TABLE (MOD_0F01_REG_2) },
3411     { MOD_TABLE (MOD_0F01_REG_3) },
3412     { "smswD",  { Sv }, 0 },
3413     { MOD_TABLE (MOD_0F01_REG_5) },
3414     { "lmsw",   { Ew }, 0 },
3415     { MOD_TABLE (MOD_0F01_REG_7) },
3416   },
3417   /* REG_0F0D */
3418   {
3419     { "prefetch",       { Mb }, 0 },
3420     { "prefetchw",      { Mb }, 0 },
3421     { "prefetchwt1",    { Mb }, 0 },
3422     { "prefetch",       { Mb }, 0 },
3423     { "prefetch",       { Mb }, 0 },
3424     { "prefetch",       { Mb }, 0 },
3425     { "prefetch",       { Mb }, 0 },
3426     { "prefetch",       { Mb }, 0 },
3427   },
3428   /* REG_0F18 */
3429   {
3430     { MOD_TABLE (MOD_0F18_REG_0) },
3431     { MOD_TABLE (MOD_0F18_REG_1) },
3432     { MOD_TABLE (MOD_0F18_REG_2) },
3433     { MOD_TABLE (MOD_0F18_REG_3) },
3434     { MOD_TABLE (MOD_0F18_REG_4) },
3435     { MOD_TABLE (MOD_0F18_REG_5) },
3436     { MOD_TABLE (MOD_0F18_REG_6) },
3437     { MOD_TABLE (MOD_0F18_REG_7) },
3438   },
3439   /* REG_0F1C_P_0_MOD_0 */
3440   {
3441     { "cldemote",       { Mb }, 0 },
3442     { "nopQ",           { Ev }, 0 },
3443     { "nopQ",           { Ev }, 0 },
3444     { "nopQ",           { Ev }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449   },
3450   /* REG_0F1E_P_1_MOD_3 */
3451   {
3452     { "nopQ",           { Ev }, 0 },
3453     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3454     { "nopQ",           { Ev }, 0 },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3460   },
3461   /* REG_0F71 */
3462   {
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { MOD_TABLE (MOD_0F71_REG_2) },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_0F71_REG_4) },
3468     { Bad_Opcode },
3469     { MOD_TABLE (MOD_0F71_REG_6) },
3470   },
3471   /* REG_0F72 */
3472   {
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475     { MOD_TABLE (MOD_0F72_REG_2) },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_0F72_REG_4) },
3478     { Bad_Opcode },
3479     { MOD_TABLE (MOD_0F72_REG_6) },
3480   },
3481   /* REG_0F73 */
3482   {
3483     { Bad_Opcode },
3484     { Bad_Opcode },
3485     { MOD_TABLE (MOD_0F73_REG_2) },
3486     { MOD_TABLE (MOD_0F73_REG_3) },
3487     { Bad_Opcode },
3488     { Bad_Opcode },
3489     { MOD_TABLE (MOD_0F73_REG_6) },
3490     { MOD_TABLE (MOD_0F73_REG_7) },
3491   },
3492   /* REG_0FA6 */
3493   {
3494     { "montmul",        { { OP_0f07, 0 } }, 0 },
3495     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3496     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3497   },
3498   /* REG_0FA7 */
3499   {
3500     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3501     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3502     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3503     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3504     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3505     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3506   },
3507   /* REG_0FAE */
3508   {
3509     { MOD_TABLE (MOD_0FAE_REG_0) },
3510     { MOD_TABLE (MOD_0FAE_REG_1) },
3511     { MOD_TABLE (MOD_0FAE_REG_2) },
3512     { MOD_TABLE (MOD_0FAE_REG_3) },
3513     { MOD_TABLE (MOD_0FAE_REG_4) },
3514     { MOD_TABLE (MOD_0FAE_REG_5) },
3515     { MOD_TABLE (MOD_0FAE_REG_6) },
3516     { MOD_TABLE (MOD_0FAE_REG_7) },
3517   },
3518   /* REG_0FBA */
3519   {
3520     { Bad_Opcode },
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { "btQ",    { Ev, Ib }, 0 },
3525     { "btsQ",   { Evh1, Ib }, 0 },
3526     { "btrQ",   { Evh1, Ib }, 0 },
3527     { "btcQ",   { Evh1, Ib }, 0 },
3528   },
3529   /* REG_0FC7 */
3530   {
3531     { Bad_Opcode },
3532     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3533     { Bad_Opcode },
3534     { MOD_TABLE (MOD_0FC7_REG_3) },
3535     { MOD_TABLE (MOD_0FC7_REG_4) },
3536     { MOD_TABLE (MOD_0FC7_REG_5) },
3537     { MOD_TABLE (MOD_0FC7_REG_6) },
3538     { MOD_TABLE (MOD_0FC7_REG_7) },
3539   },
3540   /* REG_VEX_0F71 */
3541   {
3542     { Bad_Opcode },
3543     { Bad_Opcode },
3544     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3547     { Bad_Opcode },
3548     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3549   },
3550   /* REG_VEX_0F72 */
3551   {
3552     { Bad_Opcode },
3553     { Bad_Opcode },
3554     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3555     { Bad_Opcode },
3556     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3557     { Bad_Opcode },
3558     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3559   },
3560   /* REG_VEX_0F73 */
3561   {
3562     { Bad_Opcode },
3563     { Bad_Opcode },
3564     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3565     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3566     { Bad_Opcode },
3567     { Bad_Opcode },
3568     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3569     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3570   },
3571   /* REG_VEX_0FAE */
3572   {
3573     { Bad_Opcode },
3574     { Bad_Opcode },
3575     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3576     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3577   },
3578   /* REG_VEX_0F38F3 */
3579   {
3580     { Bad_Opcode },
3581     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3582     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3583     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3584   },
3585   /* REG_XOP_LWPCB */
3586   {
3587     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3588     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3589   },
3590   /* REG_XOP_LWP */
3591   {
3592     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3593     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3594   },
3595   /* REG_XOP_TBM_01 */
3596   {
3597     { Bad_Opcode },
3598     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3599     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3600     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3601     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3602     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3603     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3604     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3605   },
3606   /* REG_XOP_TBM_02 */
3607   {
3608     { Bad_Opcode },
3609     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3610     { Bad_Opcode },
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3615   },
3616
3617 #include "i386-dis-evex-reg.h"
3618 };
3619
3620 static const struct dis386 prefix_table[][4] = {
3621   /* PREFIX_90 */
3622   {
3623     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3624     { "pause", { XX }, 0 },
3625     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3626     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3627   },
3628
3629   /* PREFIX_0F01_REG_5_MOD_0 */
3630   {
3631     { Bad_Opcode },
3632     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3633   },
3634
3635   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3636   {
3637     { Bad_Opcode },
3638     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3639   },
3640
3641   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3642   {
3643     { Bad_Opcode },
3644     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3645   },
3646
3647   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3648   {
3649     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3650   },
3651
3652   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3653   {
3654     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3655   },
3656
3657   /* PREFIX_0F09 */
3658   {
3659     { "wbinvd",   { XX }, 0 },
3660     { "wbnoinvd", { XX }, 0 },
3661   },
3662
3663   /* PREFIX_0F10 */
3664   {
3665     { "movups", { XM, EXx }, PREFIX_OPCODE },
3666     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3667     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3668     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3669   },
3670
3671   /* PREFIX_0F11 */
3672   {
3673     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3674     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3675     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3676     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3677   },
3678
3679   /* PREFIX_0F12 */
3680   {
3681     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3682     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3683     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3684     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3685   },
3686
3687   /* PREFIX_0F16 */
3688   {
3689     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3690     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3691     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3692   },
3693
3694   /* PREFIX_0F1A */
3695   {
3696     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3697     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3698     { "bndmov", { Gbnd, Ebnd }, 0 },
3699     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3700   },
3701
3702   /* PREFIX_0F1B */
3703   {
3704     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3705     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3706     { "bndmov", { EbndS, Gbnd }, 0 },
3707     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3708   },
3709
3710   /* PREFIX_0F1C */
3711   {
3712     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3713     { "nopQ",   { Ev }, PREFIX_OPCODE },
3714     { "nopQ",   { Ev }, PREFIX_OPCODE },
3715     { "nopQ",   { Ev }, PREFIX_OPCODE },
3716   },
3717
3718   /* PREFIX_0F1E */
3719   {
3720     { "nopQ",   { Ev }, PREFIX_OPCODE },
3721     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3722     { "nopQ",   { Ev }, PREFIX_OPCODE },
3723     { "nopQ",   { Ev }, PREFIX_OPCODE },
3724   },
3725
3726   /* PREFIX_0F2A */
3727   {
3728     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3729     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3730     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3731     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3732   },
3733
3734   /* PREFIX_0F2B */
3735   {
3736     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3737     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3738     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3739     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3740   },
3741
3742   /* PREFIX_0F2C */
3743   {
3744     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3745     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3746     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3747     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3748   },
3749
3750   /* PREFIX_0F2D */
3751   {
3752     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3753     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3754     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3755     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3756   },
3757
3758   /* PREFIX_0F2E */
3759   {
3760     { "ucomiss",{ XM, EXd }, 0 },
3761     { Bad_Opcode },
3762     { "ucomisd",{ XM, EXq }, 0 },
3763   },
3764
3765   /* PREFIX_0F2F */
3766   {
3767     { "comiss", { XM, EXd }, 0 },
3768     { Bad_Opcode },
3769     { "comisd", { XM, EXq }, 0 },
3770   },
3771
3772   /* PREFIX_0F51 */
3773   {
3774     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3775     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3776     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3777     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3778   },
3779
3780   /* PREFIX_0F52 */
3781   {
3782     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3783     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3784   },
3785
3786   /* PREFIX_0F53 */
3787   {
3788     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3789     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3790   },
3791
3792   /* PREFIX_0F58 */
3793   {
3794     { "addps", { XM, EXx }, PREFIX_OPCODE },
3795     { "addss", { XM, EXd }, PREFIX_OPCODE },
3796     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3797     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3798   },
3799
3800   /* PREFIX_0F59 */
3801   {
3802     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3803     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3804     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3805     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3806   },
3807
3808   /* PREFIX_0F5A */
3809   {
3810     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3811     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3812     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3813     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3814   },
3815
3816   /* PREFIX_0F5B */
3817   {
3818     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3819     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3820     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3821   },
3822
3823   /* PREFIX_0F5C */
3824   {
3825     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3826     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3827     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3828     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3829   },
3830
3831   /* PREFIX_0F5D */
3832   {
3833     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3834     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3835     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3836     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3837   },
3838
3839   /* PREFIX_0F5E */
3840   {
3841     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3842     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3843     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3844     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3845   },
3846
3847   /* PREFIX_0F5F */
3848   {
3849     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3850     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3851     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3852     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3853   },
3854
3855   /* PREFIX_0F60 */
3856   {
3857     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3858     { Bad_Opcode },
3859     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3860   },
3861
3862   /* PREFIX_0F61 */
3863   {
3864     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3865     { Bad_Opcode },
3866     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0F62 */
3870   {
3871     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3872     { Bad_Opcode },
3873     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3874   },
3875
3876   /* PREFIX_0F6C */
3877   {
3878     { Bad_Opcode },
3879     { Bad_Opcode },
3880     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3881   },
3882
3883   /* PREFIX_0F6D */
3884   {
3885     { Bad_Opcode },
3886     { Bad_Opcode },
3887     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3888   },
3889
3890   /* PREFIX_0F6F */
3891   {
3892     { "movq",   { MX, EM }, PREFIX_OPCODE },
3893     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3894     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3895   },
3896
3897   /* PREFIX_0F70 */
3898   {
3899     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3900     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3901     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3902     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3903   },
3904
3905   /* PREFIX_0F73_REG_3 */
3906   {
3907     { Bad_Opcode },
3908     { Bad_Opcode },
3909     { "psrldq", { XS, Ib }, 0 },
3910   },
3911
3912   /* PREFIX_0F73_REG_7 */
3913   {
3914     { Bad_Opcode },
3915     { Bad_Opcode },
3916     { "pslldq", { XS, Ib }, 0 },
3917   },
3918
3919   /* PREFIX_0F78 */
3920   {
3921     {"vmread",  { Em, Gm }, 0 },
3922     { Bad_Opcode },
3923     {"extrq",   { XS, Ib, Ib }, 0 },
3924     {"insertq", { XM, XS, Ib, Ib }, 0 },
3925   },
3926
3927   /* PREFIX_0F79 */
3928   {
3929     {"vmwrite", { Gm, Em }, 0 },
3930     { Bad_Opcode },
3931     {"extrq",   { XM, XS }, 0 },
3932     {"insertq", { XM, XS }, 0 },
3933   },
3934
3935   /* PREFIX_0F7C */
3936   {
3937     { Bad_Opcode },
3938     { Bad_Opcode },
3939     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3940     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3941   },
3942
3943   /* PREFIX_0F7D */
3944   {
3945     { Bad_Opcode },
3946     { Bad_Opcode },
3947     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3948     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3949   },
3950
3951   /* PREFIX_0F7E */
3952   {
3953     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3954     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3955     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3956   },
3957
3958   /* PREFIX_0F7F */
3959   {
3960     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3961     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3962     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0FAE_REG_0_MOD_3 */
3966   {
3967     { Bad_Opcode },
3968     { "rdfsbase", { Ev }, 0 },
3969   },
3970
3971   /* PREFIX_0FAE_REG_1_MOD_3 */
3972   {
3973     { Bad_Opcode },
3974     { "rdgsbase", { Ev }, 0 },
3975   },
3976
3977   /* PREFIX_0FAE_REG_2_MOD_3 */
3978   {
3979     { Bad_Opcode },
3980     { "wrfsbase", { Ev }, 0 },
3981   },
3982
3983   /* PREFIX_0FAE_REG_3_MOD_3 */
3984   {
3985     { Bad_Opcode },
3986     { "wrgsbase", { Ev }, 0 },
3987   },
3988
3989   /* PREFIX_0FAE_REG_4_MOD_0 */
3990   {
3991     { "xsave",  { FXSAVE }, 0 },
3992     { "ptwrite%LQ", { Edq }, 0 },
3993   },
3994
3995   /* PREFIX_0FAE_REG_4_MOD_3 */
3996   {
3997     { Bad_Opcode },
3998     { "ptwrite%LQ", { Edq }, 0 },
3999   },
4000
4001   /* PREFIX_0FAE_REG_5_MOD_0 */
4002   {
4003     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4004   },
4005
4006   /* PREFIX_0FAE_REG_5_MOD_3 */
4007   {
4008     { "lfence",         { Skip_MODRM }, 0 },
4009     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4010   },
4011
4012   /* PREFIX_0FAE_REG_6_MOD_0 */
4013   {
4014     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4015     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4016     { "clwb",   { Mb }, PREFIX_OPCODE },
4017   },
4018
4019   /* PREFIX_0FAE_REG_6_MOD_3 */
4020   {
4021     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4022     { "umonitor",       { Eva }, PREFIX_OPCODE },
4023     { "tpause", { Edq }, PREFIX_OPCODE },
4024     { "umwait", { Edq }, PREFIX_OPCODE },
4025   },
4026
4027   /* PREFIX_0FAE_REG_7_MOD_0 */
4028   {
4029     { "clflush",        { Mb }, 0 },
4030     { Bad_Opcode },
4031     { "clflushopt",     { Mb }, 0 },
4032   },
4033
4034   /* PREFIX_0FB8 */
4035   {
4036     { Bad_Opcode },
4037     { "popcntS", { Gv, Ev }, 0 },
4038   },
4039
4040   /* PREFIX_0FBC */
4041   {
4042     { "bsfS",   { Gv, Ev }, 0 },
4043     { "tzcntS", { Gv, Ev }, 0 },
4044     { "bsfS",   { Gv, Ev }, 0 },
4045   },
4046
4047   /* PREFIX_0FBD */
4048   {
4049     { "bsrS",   { Gv, Ev }, 0 },
4050     { "lzcntS", { Gv, Ev }, 0 },
4051     { "bsrS",   { Gv, Ev }, 0 },
4052   },
4053
4054   /* PREFIX_0FC2 */
4055   {
4056     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4057     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4058     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4059     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4060   },
4061
4062   /* PREFIX_0FC3_MOD_0 */
4063   {
4064     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4065   },
4066
4067   /* PREFIX_0FC7_REG_6_MOD_0 */
4068   {
4069     { "vmptrld",{ Mq }, 0 },
4070     { "vmxon",  { Mq }, 0 },
4071     { "vmclear",{ Mq }, 0 },
4072   },
4073
4074   /* PREFIX_0FC7_REG_6_MOD_3 */
4075   {
4076     { "rdrand", { Ev }, 0 },
4077     { Bad_Opcode },
4078     { "rdrand", { Ev }, 0 }
4079   },
4080
4081   /* PREFIX_0FC7_REG_7_MOD_3 */
4082   {
4083     { "rdseed", { Ev }, 0 },
4084     { "rdpid",  { Em }, 0 },
4085     { "rdseed", { Ev }, 0 },
4086   },
4087
4088   /* PREFIX_0FD0 */
4089   {
4090     { Bad_Opcode },
4091     { Bad_Opcode },
4092     { "addsubpd", { XM, EXx }, 0 },
4093     { "addsubps", { XM, EXx }, 0 },
4094   },
4095
4096   /* PREFIX_0FD6 */
4097   {
4098     { Bad_Opcode },
4099     { "movq2dq",{ XM, MS }, 0 },
4100     { "movq",   { EXqS, XM }, 0 },
4101     { "movdq2q",{ MX, XS }, 0 },
4102   },
4103
4104   /* PREFIX_0FE6 */
4105   {
4106     { Bad_Opcode },
4107     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4108     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4109     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4110   },
4111
4112   /* PREFIX_0FE7 */
4113   {
4114     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4115     { Bad_Opcode },
4116     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4117   },
4118
4119   /* PREFIX_0FF0 */
4120   {
4121     { Bad_Opcode },
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4125   },
4126
4127   /* PREFIX_0FF7 */
4128   {
4129     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4130     { Bad_Opcode },
4131     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F3810 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F3814 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0F3815 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4153   },
4154
4155   /* PREFIX_0F3817 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F3820 */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4167   },
4168
4169   /* PREFIX_0F3821 */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0F3822 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F3823 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4188   },
4189
4190   /* PREFIX_0F3824 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F3825 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4202   },
4203
4204   /* PREFIX_0F3828 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3829 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F382A */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4223   },
4224
4225   /* PREFIX_0F382B */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3830 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3831 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3832 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3833 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F3834 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F3835 */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4272   },
4273
4274   /* PREFIX_0F3837 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F3838 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4286   },
4287
4288   /* PREFIX_0F3839 */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4293   },
4294
4295   /* PREFIX_0F383A */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F383B */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F383C */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F383D */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F383E */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F383F */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3840 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F3841 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F3880 */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F3881 */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F3882 */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4370   },
4371
4372   /* PREFIX_0F38C8 */
4373   {
4374     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F38C9 */
4378   {
4379     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F38CA */
4383   {
4384     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F38CB */
4388   {
4389     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F38CC */
4393   {
4394     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4395   },
4396
4397   /* PREFIX_0F38CD */
4398   {
4399     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F38CF */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F38DB */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4414   },
4415
4416   /* PREFIX_0F38DC */
4417   {
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4421   },
4422
4423   /* PREFIX_0F38DD */
4424   {
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4428   },
4429
4430   /* PREFIX_0F38DE */
4431   {
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4435   },
4436
4437   /* PREFIX_0F38DF */
4438   {
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4442   },
4443
4444   /* PREFIX_0F38F0 */
4445   {
4446     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4447     { Bad_Opcode },
4448     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4449     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F38F1 */
4453   {
4454     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4455     { Bad_Opcode },
4456     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4457     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4458   },
4459
4460   /* PREFIX_0F38F5 */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4465   },
4466
4467   /* PREFIX_0F38F6 */
4468   {
4469     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4470     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4471     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4472     { Bad_Opcode },
4473   },
4474
4475   /* PREFIX_0F38F8 */
4476   {
4477     { Bad_Opcode },
4478     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4479     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4480     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4481   },
4482
4483   /* PREFIX_0F38F9 */
4484   {
4485     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4486   },
4487
4488   /* PREFIX_0F3A08 */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4493   },
4494
4495   /* PREFIX_0F3A09 */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F3A0A */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4507   },
4508
4509   /* PREFIX_0F3A0B */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4514   },
4515
4516   /* PREFIX_0F3A0C */
4517   {
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4521   },
4522
4523   /* PREFIX_0F3A0D */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4528   },
4529
4530   /* PREFIX_0F3A0E */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4535   },
4536
4537   /* PREFIX_0F3A14 */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4542   },
4543
4544   /* PREFIX_0F3A15 */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4549   },
4550
4551   /* PREFIX_0F3A16 */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4556   },
4557
4558   /* PREFIX_0F3A17 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4563   },
4564
4565   /* PREFIX_0F3A20 */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4570   },
4571
4572   /* PREFIX_0F3A21 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4577   },
4578
4579   /* PREFIX_0F3A22 */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4584   },
4585
4586   /* PREFIX_0F3A40 */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4591   },
4592
4593   /* PREFIX_0F3A41 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4598   },
4599
4600   /* PREFIX_0F3A42 */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4605   },
4606
4607   /* PREFIX_0F3A44 */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4612   },
4613
4614   /* PREFIX_0F3A60 */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4619   },
4620
4621   /* PREFIX_0F3A61 */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4626   },
4627
4628   /* PREFIX_0F3A62 */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4633   },
4634
4635   /* PREFIX_0F3A63 */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4640   },
4641
4642   /* PREFIX_0F3ACC */
4643   {
4644     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4645   },
4646
4647   /* PREFIX_0F3ACE */
4648   {
4649     { Bad_Opcode },
4650     { Bad_Opcode },
4651     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4652   },
4653
4654   /* PREFIX_0F3ACF */
4655   {
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4659   },
4660
4661   /* PREFIX_0F3ADF */
4662   {
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4666   },
4667
4668   /* PREFIX_VEX_0F10 */
4669   {
4670     { "vmovups",        { XM, EXx }, 0 },
4671     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4672     { "vmovupd",        { XM, EXx }, 0 },
4673     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4674   },
4675
4676   /* PREFIX_VEX_0F11 */
4677   {
4678     { "vmovups",        { EXxS, XM }, 0 },
4679     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4680     { "vmovupd",        { EXxS, XM }, 0 },
4681     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4682   },
4683
4684   /* PREFIX_VEX_0F12 */
4685   {
4686     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4687     { "vmovsldup",      { XM, EXx }, 0 },
4688     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4689     { "vmovddup",       { XM, EXymmq }, 0 },
4690   },
4691
4692   /* PREFIX_VEX_0F16 */
4693   {
4694     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4695     { "vmovshdup",      { XM, EXx }, 0 },
4696     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4697   },
4698
4699   /* PREFIX_VEX_0F2A */
4700   {
4701     { Bad_Opcode },
4702     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4703     { Bad_Opcode },
4704     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4705   },
4706
4707   /* PREFIX_VEX_0F2C */
4708   {
4709     { Bad_Opcode },
4710     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4711     { Bad_Opcode },
4712     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4713   },
4714
4715   /* PREFIX_VEX_0F2D */
4716   {
4717     { Bad_Opcode },
4718     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4719     { Bad_Opcode },
4720     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4721   },
4722
4723   /* PREFIX_VEX_0F2E */
4724   {
4725     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4726     { Bad_Opcode },
4727     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4728   },
4729
4730   /* PREFIX_VEX_0F2F */
4731   {
4732     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4733     { Bad_Opcode },
4734     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4735   },
4736
4737   /* PREFIX_VEX_0F41 */
4738   {
4739     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4740     { Bad_Opcode },
4741     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4742   },
4743
4744   /* PREFIX_VEX_0F42 */
4745   {
4746     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4747     { Bad_Opcode },
4748     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4749   },
4750
4751   /* PREFIX_VEX_0F44 */
4752   {
4753     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4754     { Bad_Opcode },
4755     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4756   },
4757
4758   /* PREFIX_VEX_0F45 */
4759   {
4760     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4761     { Bad_Opcode },
4762     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4763   },
4764
4765   /* PREFIX_VEX_0F46 */
4766   {
4767     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4768     { Bad_Opcode },
4769     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4770   },
4771
4772   /* PREFIX_VEX_0F47 */
4773   {
4774     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4775     { Bad_Opcode },
4776     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4777   },
4778
4779   /* PREFIX_VEX_0F4A */
4780   {
4781     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4782     { Bad_Opcode },
4783     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4784   },
4785
4786   /* PREFIX_VEX_0F4B */
4787   {
4788     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4789     { Bad_Opcode },
4790     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4791   },
4792
4793   /* PREFIX_VEX_0F51 */
4794   {
4795     { "vsqrtps",        { XM, EXx }, 0 },
4796     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4797     { "vsqrtpd",        { XM, EXx }, 0 },
4798     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4799   },
4800
4801   /* PREFIX_VEX_0F52 */
4802   {
4803     { "vrsqrtps",       { XM, EXx }, 0 },
4804     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4805   },
4806
4807   /* PREFIX_VEX_0F53 */
4808   {
4809     { "vrcpps",         { XM, EXx }, 0 },
4810     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4811   },
4812
4813   /* PREFIX_VEX_0F58 */
4814   {
4815     { "vaddps",         { XM, Vex, EXx }, 0 },
4816     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4817     { "vaddpd",         { XM, Vex, EXx }, 0 },
4818     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4819   },
4820
4821   /* PREFIX_VEX_0F59 */
4822   {
4823     { "vmulps",         { XM, Vex, EXx }, 0 },
4824     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4825     { "vmulpd",         { XM, Vex, EXx }, 0 },
4826     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4827   },
4828
4829   /* PREFIX_VEX_0F5A */
4830   {
4831     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4832     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4833     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4834     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4835   },
4836
4837   /* PREFIX_VEX_0F5B */
4838   {
4839     { "vcvtdq2ps",      { XM, EXx }, 0 },
4840     { "vcvttps2dq",     { XM, EXx }, 0 },
4841     { "vcvtps2dq",      { XM, EXx }, 0 },
4842   },
4843
4844   /* PREFIX_VEX_0F5C */
4845   {
4846     { "vsubps",         { XM, Vex, EXx }, 0 },
4847     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4848     { "vsubpd",         { XM, Vex, EXx }, 0 },
4849     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4850   },
4851
4852   /* PREFIX_VEX_0F5D */
4853   {
4854     { "vminps",         { XM, Vex, EXx }, 0 },
4855     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4856     { "vminpd",         { XM, Vex, EXx }, 0 },
4857     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4858   },
4859
4860   /* PREFIX_VEX_0F5E */
4861   {
4862     { "vdivps",         { XM, Vex, EXx }, 0 },
4863     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4864     { "vdivpd",         { XM, Vex, EXx }, 0 },
4865     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4866   },
4867
4868   /* PREFIX_VEX_0F5F */
4869   {
4870     { "vmaxps",         { XM, Vex, EXx }, 0 },
4871     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4872     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4873     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4874   },
4875
4876   /* PREFIX_VEX_0F60 */
4877   {
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4881   },
4882
4883   /* PREFIX_VEX_0F61 */
4884   {
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4888   },
4889
4890   /* PREFIX_VEX_0F62 */
4891   {
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4895   },
4896
4897   /* PREFIX_VEX_0F63 */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4902   },
4903
4904   /* PREFIX_VEX_0F64 */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4909   },
4910
4911   /* PREFIX_VEX_0F65 */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4916   },
4917
4918   /* PREFIX_VEX_0F66 */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4923   },
4924
4925   /* PREFIX_VEX_0F67 */
4926   {
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4930   },
4931
4932   /* PREFIX_VEX_0F68 */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4937   },
4938
4939   /* PREFIX_VEX_0F69 */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4944   },
4945
4946   /* PREFIX_VEX_0F6A */
4947   {
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4951   },
4952
4953   /* PREFIX_VEX_0F6B */
4954   {
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4958   },
4959
4960   /* PREFIX_VEX_0F6C */
4961   {
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4965   },
4966
4967   /* PREFIX_VEX_0F6D */
4968   {
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4972   },
4973
4974   /* PREFIX_VEX_0F6E */
4975   {
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4979   },
4980
4981   /* PREFIX_VEX_0F6F */
4982   {
4983     { Bad_Opcode },
4984     { "vmovdqu",        { XM, EXx }, 0 },
4985     { "vmovdqa",        { XM, EXx }, 0 },
4986   },
4987
4988   /* PREFIX_VEX_0F70 */
4989   {
4990     { Bad_Opcode },
4991     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4992     { "vpshufd",        { XM, EXx, Ib }, 0 },
4993     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4994   },
4995
4996   /* PREFIX_VEX_0F71_REG_2 */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5001   },
5002
5003   /* PREFIX_VEX_0F71_REG_4 */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { "vpsraw",         { Vex, XS, Ib }, 0 },
5008   },
5009
5010   /* PREFIX_VEX_0F71_REG_6 */
5011   {
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { "vpsllw",         { Vex, XS, Ib }, 0 },
5015   },
5016
5017   /* PREFIX_VEX_0F72_REG_2 */
5018   {
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { "vpsrld",         { Vex, XS, Ib }, 0 },
5022   },
5023
5024   /* PREFIX_VEX_0F72_REG_4 */
5025   {
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { "vpsrad",         { Vex, XS, Ib }, 0 },
5029   },
5030
5031   /* PREFIX_VEX_0F72_REG_6 */
5032   {
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { "vpslld",         { Vex, XS, Ib }, 0 },
5036   },
5037
5038   /* PREFIX_VEX_0F73_REG_2 */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5043   },
5044
5045   /* PREFIX_VEX_0F73_REG_3 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5050   },
5051
5052   /* PREFIX_VEX_0F73_REG_6 */
5053   {
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { "vpsllq",         { Vex, XS, Ib }, 0 },
5057   },
5058
5059   /* PREFIX_VEX_0F73_REG_7 */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { "vpslldq",        { Vex, XS, Ib }, 0 },
5064   },
5065
5066   /* PREFIX_VEX_0F74 */
5067   {
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5071   },
5072
5073   /* PREFIX_VEX_0F75 */
5074   {
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5078   },
5079
5080   /* PREFIX_VEX_0F76 */
5081   {
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5085   },
5086
5087   /* PREFIX_VEX_0F77 */
5088   {
5089     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5090   },
5091
5092   /* PREFIX_VEX_0F7C */
5093   {
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5097     { "vhaddps",        { XM, Vex, EXx }, 0 },
5098   },
5099
5100   /* PREFIX_VEX_0F7D */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5105     { "vhsubps",        { XM, Vex, EXx }, 0 },
5106   },
5107
5108   /* PREFIX_VEX_0F7E */
5109   {
5110     { Bad_Opcode },
5111     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5112     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5113   },
5114
5115   /* PREFIX_VEX_0F7F */
5116   {
5117     { Bad_Opcode },
5118     { "vmovdqu",        { EXxS, XM }, 0 },
5119     { "vmovdqa",        { EXxS, XM }, 0 },
5120   },
5121
5122   /* PREFIX_VEX_0F90 */
5123   {
5124     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5125     { Bad_Opcode },
5126     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5127   },
5128
5129   /* PREFIX_VEX_0F91 */
5130   {
5131     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5132     { Bad_Opcode },
5133     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5134   },
5135
5136   /* PREFIX_VEX_0F92 */
5137   {
5138     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5139     { Bad_Opcode },
5140     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5141     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5142   },
5143
5144   /* PREFIX_VEX_0F93 */
5145   {
5146     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5147     { Bad_Opcode },
5148     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5149     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5150   },
5151
5152   /* PREFIX_VEX_0F98 */
5153   {
5154     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5155     { Bad_Opcode },
5156     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5157   },
5158
5159   /* PREFIX_VEX_0F99 */
5160   {
5161     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5162     { Bad_Opcode },
5163     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_0FC2 */
5167   {
5168     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5169     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5170     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5171     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5172   },
5173
5174   /* PREFIX_VEX_0FC4 */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5179   },
5180
5181   /* PREFIX_VEX_0FC5 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5186   },
5187
5188   /* PREFIX_VEX_0FD0 */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5193     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5194   },
5195
5196   /* PREFIX_VEX_0FD1 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5201   },
5202
5203   /* PREFIX_VEX_0FD2 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5208   },
5209
5210   /* PREFIX_VEX_0FD3 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5215   },
5216
5217   /* PREFIX_VEX_0FD4 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { "vpaddq",         { XM, Vex, EXx }, 0 },
5222   },
5223
5224   /* PREFIX_VEX_0FD5 */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { "vpmullw",        { XM, Vex, EXx }, 0 },
5229   },
5230
5231   /* PREFIX_VEX_0FD6 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5236   },
5237
5238   /* PREFIX_VEX_0FD7 */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5243   },
5244
5245   /* PREFIX_VEX_0FD8 */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5250   },
5251
5252   /* PREFIX_VEX_0FD9 */
5253   {
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5257   },
5258
5259   /* PREFIX_VEX_0FDA */
5260   {
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { "vpminub",        { XM, Vex, EXx }, 0 },
5264   },
5265
5266   /* PREFIX_VEX_0FDB */
5267   {
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { "vpand",          { XM, Vex, EXx }, 0 },
5271   },
5272
5273   /* PREFIX_VEX_0FDC */
5274   {
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5278   },
5279
5280   /* PREFIX_VEX_0FDD */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5285   },
5286
5287   /* PREFIX_VEX_0FDE */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5292   },
5293
5294   /* PREFIX_VEX_0FDF */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { "vpandn",         { XM, Vex, EXx }, 0 },
5299   },
5300
5301   /* PREFIX_VEX_0FE0 */
5302   {
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { "vpavgb",         { XM, Vex, EXx }, 0 },
5306   },
5307
5308   /* PREFIX_VEX_0FE1 */
5309   {
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5313   },
5314
5315   /* PREFIX_VEX_0FE2 */
5316   {
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5320   },
5321
5322   /* PREFIX_VEX_0FE3 */
5323   {
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { "vpavgw",         { XM, Vex, EXx }, 0 },
5327   },
5328
5329   /* PREFIX_VEX_0FE4 */
5330   {
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5334   },
5335
5336   /* PREFIX_VEX_0FE5 */
5337   {
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5341   },
5342
5343   /* PREFIX_VEX_0FE6 */
5344   {
5345     { Bad_Opcode },
5346     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5347     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5348     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5349   },
5350
5351   /* PREFIX_VEX_0FE7 */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5356   },
5357
5358   /* PREFIX_VEX_0FE8 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5363   },
5364
5365   /* PREFIX_VEX_0FE9 */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5370   },
5371
5372   /* PREFIX_VEX_0FEA */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { "vpminsw",        { XM, Vex, EXx }, 0 },
5377   },
5378
5379   /* PREFIX_VEX_0FEB */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { "vpor",           { XM, Vex, EXx }, 0 },
5384   },
5385
5386   /* PREFIX_VEX_0FEC */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5391   },
5392
5393   /* PREFIX_VEX_0FED */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5398   },
5399
5400   /* PREFIX_VEX_0FEE */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5405   },
5406
5407   /* PREFIX_VEX_0FEF */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { "vpxor",          { XM, Vex, EXx }, 0 },
5412   },
5413
5414   /* PREFIX_VEX_0FF0 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5420   },
5421
5422   /* PREFIX_VEX_0FF1 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5427   },
5428
5429   /* PREFIX_VEX_0FF2 */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5434   },
5435
5436   /* PREFIX_VEX_0FF3 */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5441   },
5442
5443   /* PREFIX_VEX_0FF4 */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5448   },
5449
5450   /* PREFIX_VEX_0FF5 */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5455   },
5456
5457   /* PREFIX_VEX_0FF6 */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5462   },
5463
5464   /* PREFIX_VEX_0FF7 */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5469   },
5470
5471   /* PREFIX_VEX_0FF8 */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { "vpsubb",         { XM, Vex, EXx }, 0 },
5476   },
5477
5478   /* PREFIX_VEX_0FF9 */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { "vpsubw",         { XM, Vex, EXx }, 0 },
5483   },
5484
5485   /* PREFIX_VEX_0FFA */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { "vpsubd",         { XM, Vex, EXx }, 0 },
5490   },
5491
5492   /* PREFIX_VEX_0FFB */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { "vpsubq",         { XM, Vex, EXx }, 0 },
5497   },
5498
5499   /* PREFIX_VEX_0FFC */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { "vpaddb",         { XM, Vex, EXx }, 0 },
5504   },
5505
5506   /* PREFIX_VEX_0FFD */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { "vpaddw",         { XM, Vex, EXx }, 0 },
5511   },
5512
5513   /* PREFIX_VEX_0FFE */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { "vpaddd",         { XM, Vex, EXx }, 0 },
5518   },
5519
5520   /* PREFIX_VEX_0F3800 */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { "vpshufb",        { XM, Vex, EXx }, 0 },
5525   },
5526
5527   /* PREFIX_VEX_0F3801 */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { "vphaddw",        { XM, Vex, EXx }, 0 },
5532   },
5533
5534   /* PREFIX_VEX_0F3802 */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { "vphaddd",        { XM, Vex, EXx }, 0 },
5539   },
5540
5541   /* PREFIX_VEX_0F3803 */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5546   },
5547
5548   /* PREFIX_VEX_0F3804 */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5553   },
5554
5555   /* PREFIX_VEX_0F3805 */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { "vphsubw",        { XM, Vex, EXx }, 0 },
5560   },
5561
5562   /* PREFIX_VEX_0F3806 */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { "vphsubd",        { XM, Vex, EXx }, 0 },
5567   },
5568
5569   /* PREFIX_VEX_0F3807 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5574   },
5575
5576   /* PREFIX_VEX_0F3808 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { "vpsignb",        { XM, Vex, EXx }, 0 },
5581   },
5582
5583   /* PREFIX_VEX_0F3809 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { "vpsignw",        { XM, Vex, EXx }, 0 },
5588   },
5589
5590   /* PREFIX_VEX_0F380A */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { "vpsignd",        { XM, Vex, EXx }, 0 },
5595   },
5596
5597   /* PREFIX_VEX_0F380B */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5602   },
5603
5604   /* PREFIX_VEX_0F380C */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F380D */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5616   },
5617
5618   /* PREFIX_VEX_0F380E */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F380F */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F3813 */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5637   },
5638
5639   /* PREFIX_VEX_0F3816 */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5644   },
5645
5646   /* PREFIX_VEX_0F3817 */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { "vptest",         { XM, EXx }, 0 },
5651   },
5652
5653   /* PREFIX_VEX_0F3818 */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5658   },
5659
5660   /* PREFIX_VEX_0F3819 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5665   },
5666
5667   /* PREFIX_VEX_0F381A */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5672   },
5673
5674   /* PREFIX_VEX_0F381C */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { "vpabsb",         { XM, EXx }, 0 },
5679   },
5680
5681   /* PREFIX_VEX_0F381D */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { "vpabsw",         { XM, EXx }, 0 },
5686   },
5687
5688   /* PREFIX_VEX_0F381E */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { "vpabsd",         { XM, EXx }, 0 },
5693   },
5694
5695   /* PREFIX_VEX_0F3820 */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5700   },
5701
5702   /* PREFIX_VEX_0F3821 */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5707   },
5708
5709   /* PREFIX_VEX_0F3822 */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5714   },
5715
5716   /* PREFIX_VEX_0F3823 */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5721   },
5722
5723   /* PREFIX_VEX_0F3824 */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5728   },
5729
5730   /* PREFIX_VEX_0F3825 */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5735   },
5736
5737   /* PREFIX_VEX_0F3828 */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5742   },
5743
5744   /* PREFIX_VEX_0F3829 */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5749   },
5750
5751   /* PREFIX_VEX_0F382A */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F382B */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5763   },
5764
5765   /* PREFIX_VEX_0F382C */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5770   },
5771
5772   /* PREFIX_VEX_0F382D */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5777   },
5778
5779   /* PREFIX_VEX_0F382E */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5784   },
5785
5786   /* PREFIX_VEX_0F382F */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5791   },
5792
5793   /* PREFIX_VEX_0F3830 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5798   },
5799
5800   /* PREFIX_VEX_0F3831 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5805   },
5806
5807   /* PREFIX_VEX_0F3832 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5812   },
5813
5814   /* PREFIX_VEX_0F3833 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5819   },
5820
5821   /* PREFIX_VEX_0F3834 */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5826   },
5827
5828   /* PREFIX_VEX_0F3835 */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5833   },
5834
5835   /* PREFIX_VEX_0F3836 */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5840   },
5841
5842   /* PREFIX_VEX_0F3837 */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5847   },
5848
5849   /* PREFIX_VEX_0F3838 */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { "vpminsb",        { XM, Vex, EXx }, 0 },
5854   },
5855
5856   /* PREFIX_VEX_0F3839 */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { "vpminsd",        { XM, Vex, EXx }, 0 },
5861   },
5862
5863   /* PREFIX_VEX_0F383A */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { "vpminuw",        { XM, Vex, EXx }, 0 },
5868   },
5869
5870   /* PREFIX_VEX_0F383B */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { "vpminud",        { XM, Vex, EXx }, 0 },
5875   },
5876
5877   /* PREFIX_VEX_0F383C */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5882   },
5883
5884   /* PREFIX_VEX_0F383D */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5889   },
5890
5891   /* PREFIX_VEX_0F383E */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5896   },
5897
5898   /* PREFIX_VEX_0F383F */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5903   },
5904
5905   /* PREFIX_VEX_0F3840 */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { "vpmulld",        { XM, Vex, EXx }, 0 },
5910   },
5911
5912   /* PREFIX_VEX_0F3841 */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5917   },
5918
5919   /* PREFIX_VEX_0F3845 */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5924   },
5925
5926   /* PREFIX_VEX_0F3846 */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5931   },
5932
5933   /* PREFIX_VEX_0F3847 */
5934   {
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5938   },
5939
5940   /* PREFIX_VEX_0F3858 */
5941   {
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5945   },
5946
5947   /* PREFIX_VEX_0F3859 */
5948   {
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5952   },
5953
5954   /* PREFIX_VEX_0F385A */
5955   {
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5959   },
5960
5961   /* PREFIX_VEX_0F3878 */
5962   {
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5966   },
5967
5968   /* PREFIX_VEX_0F3879 */
5969   {
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5973   },
5974
5975   /* PREFIX_VEX_0F388C */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5980   },
5981
5982   /* PREFIX_VEX_0F388E */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5987   },
5988
5989   /* PREFIX_VEX_0F3890 */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5994   },
5995
5996   /* PREFIX_VEX_0F3891 */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6001   },
6002
6003   /* PREFIX_VEX_0F3892 */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6008   },
6009
6010   /* PREFIX_VEX_0F3893 */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6015   },
6016
6017   /* PREFIX_VEX_0F3896 */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6022   },
6023
6024   /* PREFIX_VEX_0F3897 */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6029   },
6030
6031   /* PREFIX_VEX_0F3898 */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6036   },
6037
6038   /* PREFIX_VEX_0F3899 */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6043   },
6044
6045   /* PREFIX_VEX_0F389A */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6050   },
6051
6052   /* PREFIX_VEX_0F389B */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6057   },
6058
6059   /* PREFIX_VEX_0F389C */
6060   {
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6064   },
6065
6066   /* PREFIX_VEX_0F389D */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6071   },
6072
6073   /* PREFIX_VEX_0F389E */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6078   },
6079
6080   /* PREFIX_VEX_0F389F */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6085   },
6086
6087   /* PREFIX_VEX_0F38A6 */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6092     { Bad_Opcode },
6093   },
6094
6095   /* PREFIX_VEX_0F38A7 */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6100   },
6101
6102   /* PREFIX_VEX_0F38A8 */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6107   },
6108
6109   /* PREFIX_VEX_0F38A9 */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6114   },
6115
6116   /* PREFIX_VEX_0F38AA */
6117   {
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6121   },
6122
6123   /* PREFIX_VEX_0F38AB */
6124   {
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6128   },
6129
6130   /* PREFIX_VEX_0F38AC */
6131   {
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6135   },
6136
6137   /* PREFIX_VEX_0F38AD */
6138   {
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6142   },
6143
6144   /* PREFIX_VEX_0F38AE */
6145   {
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6149   },
6150
6151   /* PREFIX_VEX_0F38AF */
6152   {
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6156   },
6157
6158   /* PREFIX_VEX_0F38B6 */
6159   {
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6163   },
6164
6165   /* PREFIX_VEX_0F38B7 */
6166   {
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6170   },
6171
6172   /* PREFIX_VEX_0F38B8 */
6173   {
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6177   },
6178
6179   /* PREFIX_VEX_0F38B9 */
6180   {
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6184   },
6185
6186   /* PREFIX_VEX_0F38BA */
6187   {
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6191   },
6192
6193   /* PREFIX_VEX_0F38BB */
6194   {
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6198   },
6199
6200   /* PREFIX_VEX_0F38BC */
6201   {
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6205   },
6206
6207   /* PREFIX_VEX_0F38BD */
6208   {
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6212   },
6213
6214   /* PREFIX_VEX_0F38BE */
6215   {
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6219   },
6220
6221   /* PREFIX_VEX_0F38BF */
6222   {
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6226   },
6227
6228   /* PREFIX_VEX_0F38CF */
6229   {
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6233   },
6234
6235   /* PREFIX_VEX_0F38DB */
6236   {
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6240   },
6241
6242   /* PREFIX_VEX_0F38DC */
6243   {
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { "vaesenc",        { XM, Vex, EXx }, 0 },
6247   },
6248
6249   /* PREFIX_VEX_0F38DD */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6254   },
6255
6256   /* PREFIX_VEX_0F38DE */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { "vaesdec",        { XM, Vex, EXx }, 0 },
6261   },
6262
6263   /* PREFIX_VEX_0F38DF */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6268   },
6269
6270   /* PREFIX_VEX_0F38F2 */
6271   {
6272     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6273   },
6274
6275   /* PREFIX_VEX_0F38F3_REG_1 */
6276   {
6277     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6278   },
6279
6280   /* PREFIX_VEX_0F38F3_REG_2 */
6281   {
6282     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6283   },
6284
6285   /* PREFIX_VEX_0F38F3_REG_3 */
6286   {
6287     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6288   },
6289
6290   /* PREFIX_VEX_0F38F5 */
6291   {
6292     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6293     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6294     { Bad_Opcode },
6295     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6296   },
6297
6298   /* PREFIX_VEX_0F38F6 */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6304   },
6305
6306   /* PREFIX_VEX_0F38F7 */
6307   {
6308     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6310     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6312   },
6313
6314   /* PREFIX_VEX_0F3A00 */
6315   {
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6319   },
6320
6321   /* PREFIX_VEX_0F3A01 */
6322   {
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6326   },
6327
6328   /* PREFIX_VEX_0F3A02 */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6333   },
6334
6335   /* PREFIX_VEX_0F3A04 */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6340   },
6341
6342   /* PREFIX_VEX_0F3A05 */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6347   },
6348
6349   /* PREFIX_VEX_0F3A06 */
6350   {
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6354   },
6355
6356   /* PREFIX_VEX_0F3A08 */
6357   {
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { "vroundps",       { XM, EXx, Ib }, 0 },
6361   },
6362
6363   /* PREFIX_VEX_0F3A09 */
6364   {
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { "vroundpd",       { XM, EXx, Ib }, 0 },
6368   },
6369
6370   /* PREFIX_VEX_0F3A0A */
6371   {
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6375   },
6376
6377   /* PREFIX_VEX_0F3A0B */
6378   {
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6382   },
6383
6384   /* PREFIX_VEX_0F3A0C */
6385   {
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6389   },
6390
6391   /* PREFIX_VEX_0F3A0D */
6392   {
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6396   },
6397
6398   /* PREFIX_VEX_0F3A0E */
6399   {
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6403   },
6404
6405   /* PREFIX_VEX_0F3A0F */
6406   {
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6410   },
6411
6412   /* PREFIX_VEX_0F3A14 */
6413   {
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6417   },
6418
6419   /* PREFIX_VEX_0F3A15 */
6420   {
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6424   },
6425
6426   /* PREFIX_VEX_0F3A16 */
6427   {
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6431   },
6432
6433   /* PREFIX_VEX_0F3A17 */
6434   {
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6438   },
6439
6440   /* PREFIX_VEX_0F3A18 */
6441   {
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6445   },
6446
6447   /* PREFIX_VEX_0F3A19 */
6448   {
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6452   },
6453
6454   /* PREFIX_VEX_0F3A1D */
6455   {
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6459   },
6460
6461   /* PREFIX_VEX_0F3A20 */
6462   {
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6466   },
6467
6468   /* PREFIX_VEX_0F3A21 */
6469   {
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6473   },
6474
6475   /* PREFIX_VEX_0F3A22 */
6476   {
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6480   },
6481
6482   /* PREFIX_VEX_0F3A30 */
6483   {
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6487   },
6488
6489   /* PREFIX_VEX_0F3A31 */
6490   {
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6494   },
6495
6496   /* PREFIX_VEX_0F3A32 */
6497   {
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6501   },
6502
6503   /* PREFIX_VEX_0F3A33 */
6504   {
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6508   },
6509
6510   /* PREFIX_VEX_0F3A38 */
6511   {
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6515   },
6516
6517   /* PREFIX_VEX_0F3A39 */
6518   {
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6522   },
6523
6524   /* PREFIX_VEX_0F3A40 */
6525   {
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6529   },
6530
6531   /* PREFIX_VEX_0F3A41 */
6532   {
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6536   },
6537
6538   /* PREFIX_VEX_0F3A42 */
6539   {
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6543   },
6544
6545   /* PREFIX_VEX_0F3A44 */
6546   {
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6550   },
6551
6552   /* PREFIX_VEX_0F3A46 */
6553   {
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6557   },
6558
6559   /* PREFIX_VEX_0F3A48 */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6564   },
6565
6566   /* PREFIX_VEX_0F3A49 */
6567   {
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6571   },
6572
6573   /* PREFIX_VEX_0F3A4A */
6574   {
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6578   },
6579
6580   /* PREFIX_VEX_0F3A4B */
6581   {
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6585   },
6586
6587   /* PREFIX_VEX_0F3A4C */
6588   {
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6592   },
6593
6594   /* PREFIX_VEX_0F3A5C */
6595   {
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6599   },
6600
6601   /* PREFIX_VEX_0F3A5D */
6602   {
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6606   },
6607
6608   /* PREFIX_VEX_0F3A5E */
6609   {
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6613   },
6614
6615   /* PREFIX_VEX_0F3A5F */
6616   {
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6620   },
6621
6622   /* PREFIX_VEX_0F3A60 */
6623   {
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6627     { Bad_Opcode },
6628   },
6629
6630   /* PREFIX_VEX_0F3A61 */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6635   },
6636
6637   /* PREFIX_VEX_0F3A62 */
6638   {
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6642   },
6643
6644   /* PREFIX_VEX_0F3A63 */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6649   },
6650
6651   /* PREFIX_VEX_0F3A68 */
6652   {
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6656   },
6657
6658   /* PREFIX_VEX_0F3A69 */
6659   {
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6663   },
6664
6665   /* PREFIX_VEX_0F3A6A */
6666   {
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6670   },
6671
6672   /* PREFIX_VEX_0F3A6B */
6673   {
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6677   },
6678
6679   /* PREFIX_VEX_0F3A6C */
6680   {
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6684   },
6685
6686   /* PREFIX_VEX_0F3A6D */
6687   {
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6691   },
6692
6693   /* PREFIX_VEX_0F3A6E */
6694   {
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6698   },
6699
6700   /* PREFIX_VEX_0F3A6F */
6701   {
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6705   },
6706
6707   /* PREFIX_VEX_0F3A78 */
6708   {
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6712   },
6713
6714   /* PREFIX_VEX_0F3A79 */
6715   {
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6719   },
6720
6721   /* PREFIX_VEX_0F3A7A */
6722   {
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6726   },
6727
6728   /* PREFIX_VEX_0F3A7B */
6729   {
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6733   },
6734
6735   /* PREFIX_VEX_0F3A7C */
6736   {
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6740     { Bad_Opcode },
6741   },
6742
6743   /* PREFIX_VEX_0F3A7D */
6744   {
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6748   },
6749
6750   /* PREFIX_VEX_0F3A7E */
6751   {
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6755   },
6756
6757   /* PREFIX_VEX_0F3A7F */
6758   {
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6762   },
6763
6764   /* PREFIX_VEX_0F3ACE */
6765   {
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6769   },
6770
6771   /* PREFIX_VEX_0F3ACF */
6772   {
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6776   },
6777
6778   /* PREFIX_VEX_0F3ADF */
6779   {
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6783   },
6784
6785   /* PREFIX_VEX_0F3AF0 */
6786   {
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6791   },
6792
6793 #include "i386-dis-evex-prefix.h"
6794 };
6795
6796 static const struct dis386 x86_64_table[][2] = {
6797   /* X86_64_06 */
6798   {
6799     { "pushP", { es }, 0 },
6800   },
6801
6802   /* X86_64_07 */
6803   {
6804     { "popP", { es }, 0 },
6805   },
6806
6807   /* X86_64_0D */
6808   {
6809     { "pushP", { cs }, 0 },
6810   },
6811
6812   /* X86_64_16 */
6813   {
6814     { "pushP", { ss }, 0 },
6815   },
6816
6817   /* X86_64_17 */
6818   {
6819     { "popP", { ss }, 0 },
6820   },
6821
6822   /* X86_64_1E */
6823   {
6824     { "pushP", { ds }, 0 },
6825   },
6826
6827   /* X86_64_1F */
6828   {
6829     { "popP", { ds }, 0 },
6830   },
6831
6832   /* X86_64_27 */
6833   {
6834     { "daa", { XX }, 0 },
6835   },
6836
6837   /* X86_64_2F */
6838   {
6839     { "das", { XX }, 0 },
6840   },
6841
6842   /* X86_64_37 */
6843   {
6844     { "aaa", { XX }, 0 },
6845   },
6846
6847   /* X86_64_3F */
6848   {
6849     { "aas", { XX }, 0 },
6850   },
6851
6852   /* X86_64_60 */
6853   {
6854     { "pushaP", { XX }, 0 },
6855   },
6856
6857   /* X86_64_61 */
6858   {
6859     { "popaP", { XX }, 0 },
6860   },
6861
6862   /* X86_64_62 */
6863   {
6864     { MOD_TABLE (MOD_62_32BIT) },
6865     { EVEX_TABLE (EVEX_0F) },
6866   },
6867
6868   /* X86_64_63 */
6869   {
6870     { "arpl", { Ew, Gw }, 0 },
6871     { "movs{lq|xd}", { Gv, Ed }, 0 },
6872   },
6873
6874   /* X86_64_6D */
6875   {
6876     { "ins{R|}", { Yzr, indirDX }, 0 },
6877     { "ins{G|}", { Yzr, indirDX }, 0 },
6878   },
6879
6880   /* X86_64_6F */
6881   {
6882     { "outs{R|}", { indirDXr, Xz }, 0 },
6883     { "outs{G|}", { indirDXr, Xz }, 0 },
6884   },
6885
6886   /* X86_64_82 */
6887   {
6888     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6889     { REG_TABLE (REG_80) },
6890   },
6891
6892   /* X86_64_9A */
6893   {
6894     { "Jcall{T|}", { Ap }, 0 },
6895   },
6896
6897   /* X86_64_C4 */
6898   {
6899     { MOD_TABLE (MOD_C4_32BIT) },
6900     { VEX_C4_TABLE (VEX_0F) },
6901   },
6902
6903   /* X86_64_C5 */
6904   {
6905     { MOD_TABLE (MOD_C5_32BIT) },
6906     { VEX_C5_TABLE (VEX_0F) },
6907   },
6908
6909   /* X86_64_CE */
6910   {
6911     { "into", { XX }, 0 },
6912   },
6913
6914   /* X86_64_D4 */
6915   {
6916     { "aam", { Ib }, 0 },
6917   },
6918
6919   /* X86_64_D5 */
6920   {
6921     { "aad", { Ib }, 0 },
6922   },
6923
6924   /* X86_64_E8 */
6925   {
6926     { "callP",          { Jv, BND }, 0 },
6927     { "call@",          { Jv, BND }, 0 }
6928   },
6929
6930   /* X86_64_E9 */
6931   {
6932     { "jmpP",           { Jv, BND }, 0 },
6933     { "jmp@",           { Jv, BND }, 0 }
6934   },
6935
6936   /* X86_64_EA */
6937   {
6938     { "Jjmp{T|}", { Ap }, 0 },
6939   },
6940
6941   /* X86_64_0F01_REG_0 */
6942   {
6943     { "sgdt{Q|IQ}", { M }, 0 },
6944     { "sgdt", { M }, 0 },
6945   },
6946
6947   /* X86_64_0F01_REG_1 */
6948   {
6949     { "sidt{Q|IQ}", { M }, 0 },
6950     { "sidt", { M }, 0 },
6951   },
6952
6953   /* X86_64_0F01_REG_2 */
6954   {
6955     { "lgdt{Q|Q}", { M }, 0 },
6956     { "lgdt", { M }, 0 },
6957   },
6958
6959   /* X86_64_0F01_REG_3 */
6960   {
6961     { "lidt{Q|Q}", { M }, 0 },
6962     { "lidt", { M }, 0 },
6963   },
6964 };
6965
6966 static const struct dis386 three_byte_table[][256] = {
6967
6968   /* THREE_BYTE_0F38 */
6969   {
6970     /* 00 */
6971     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6972     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6973     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6974     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6975     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6976     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6977     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6978     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6979     /* 08 */
6980     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6981     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6982     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6983     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 10 */
6989     { PREFIX_TABLE (PREFIX_0F3810) },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { PREFIX_TABLE (PREFIX_0F3814) },
6994     { PREFIX_TABLE (PREFIX_0F3815) },
6995     { Bad_Opcode },
6996     { PREFIX_TABLE (PREFIX_0F3817) },
6997     /* 18 */
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7003     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7004     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7005     { Bad_Opcode },
7006     /* 20 */
7007     { PREFIX_TABLE (PREFIX_0F3820) },
7008     { PREFIX_TABLE (PREFIX_0F3821) },
7009     { PREFIX_TABLE (PREFIX_0F3822) },
7010     { PREFIX_TABLE (PREFIX_0F3823) },
7011     { PREFIX_TABLE (PREFIX_0F3824) },
7012     { PREFIX_TABLE (PREFIX_0F3825) },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 28 */
7016     { PREFIX_TABLE (PREFIX_0F3828) },
7017     { PREFIX_TABLE (PREFIX_0F3829) },
7018     { PREFIX_TABLE (PREFIX_0F382A) },
7019     { PREFIX_TABLE (PREFIX_0F382B) },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* 30 */
7025     { PREFIX_TABLE (PREFIX_0F3830) },
7026     { PREFIX_TABLE (PREFIX_0F3831) },
7027     { PREFIX_TABLE (PREFIX_0F3832) },
7028     { PREFIX_TABLE (PREFIX_0F3833) },
7029     { PREFIX_TABLE (PREFIX_0F3834) },
7030     { PREFIX_TABLE (PREFIX_0F3835) },
7031     { Bad_Opcode },
7032     { PREFIX_TABLE (PREFIX_0F3837) },
7033     /* 38 */
7034     { PREFIX_TABLE (PREFIX_0F3838) },
7035     { PREFIX_TABLE (PREFIX_0F3839) },
7036     { PREFIX_TABLE (PREFIX_0F383A) },
7037     { PREFIX_TABLE (PREFIX_0F383B) },
7038     { PREFIX_TABLE (PREFIX_0F383C) },
7039     { PREFIX_TABLE (PREFIX_0F383D) },
7040     { PREFIX_TABLE (PREFIX_0F383E) },
7041     { PREFIX_TABLE (PREFIX_0F383F) },
7042     /* 40 */
7043     { PREFIX_TABLE (PREFIX_0F3840) },
7044     { PREFIX_TABLE (PREFIX_0F3841) },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* 48 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* 50 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* 58 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* 60 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* 68 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* 70 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* 78 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* 80 */
7115     { PREFIX_TABLE (PREFIX_0F3880) },
7116     { PREFIX_TABLE (PREFIX_0F3881) },
7117     { PREFIX_TABLE (PREFIX_0F3882) },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* 88 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     /* 90 */
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     /* 98 */
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     /* a0 */
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     /* a8 */
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     /* b0 */
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     /* b8 */
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     /* c0 */
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     /* c8 */
7196     { PREFIX_TABLE (PREFIX_0F38C8) },
7197     { PREFIX_TABLE (PREFIX_0F38C9) },
7198     { PREFIX_TABLE (PREFIX_0F38CA) },
7199     { PREFIX_TABLE (PREFIX_0F38CB) },
7200     { PREFIX_TABLE (PREFIX_0F38CC) },
7201     { PREFIX_TABLE (PREFIX_0F38CD) },
7202     { Bad_Opcode },
7203     { PREFIX_TABLE (PREFIX_0F38CF) },
7204     /* d0 */
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     /* d8 */
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { PREFIX_TABLE (PREFIX_0F38DB) },
7218     { PREFIX_TABLE (PREFIX_0F38DC) },
7219     { PREFIX_TABLE (PREFIX_0F38DD) },
7220     { PREFIX_TABLE (PREFIX_0F38DE) },
7221     { PREFIX_TABLE (PREFIX_0F38DF) },
7222     /* e0 */
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     /* e8 */
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     /* f0 */
7241     { PREFIX_TABLE (PREFIX_0F38F0) },
7242     { PREFIX_TABLE (PREFIX_0F38F1) },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { PREFIX_TABLE (PREFIX_0F38F5) },
7247     { PREFIX_TABLE (PREFIX_0F38F6) },
7248     { Bad_Opcode },
7249     /* f8 */
7250     { PREFIX_TABLE (PREFIX_0F38F8) },
7251     { PREFIX_TABLE (PREFIX_0F38F9) },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258   },
7259   /* THREE_BYTE_0F3A */
7260   {
7261     /* 00 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* 08 */
7271     { PREFIX_TABLE (PREFIX_0F3A08) },
7272     { PREFIX_TABLE (PREFIX_0F3A09) },
7273     { PREFIX_TABLE (PREFIX_0F3A0A) },
7274     { PREFIX_TABLE (PREFIX_0F3A0B) },
7275     { PREFIX_TABLE (PREFIX_0F3A0C) },
7276     { PREFIX_TABLE (PREFIX_0F3A0D) },
7277     { PREFIX_TABLE (PREFIX_0F3A0E) },
7278     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7279     /* 10 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { PREFIX_TABLE (PREFIX_0F3A14) },
7285     { PREFIX_TABLE (PREFIX_0F3A15) },
7286     { PREFIX_TABLE (PREFIX_0F3A16) },
7287     { PREFIX_TABLE (PREFIX_0F3A17) },
7288     /* 18 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 20 */
7298     { PREFIX_TABLE (PREFIX_0F3A20) },
7299     { PREFIX_TABLE (PREFIX_0F3A21) },
7300     { PREFIX_TABLE (PREFIX_0F3A22) },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 28 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* 30 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* 38 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* 40 */
7334     { PREFIX_TABLE (PREFIX_0F3A40) },
7335     { PREFIX_TABLE (PREFIX_0F3A41) },
7336     { PREFIX_TABLE (PREFIX_0F3A42) },
7337     { Bad_Opcode },
7338     { PREFIX_TABLE (PREFIX_0F3A44) },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* 48 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* 50 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* 58 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* 60 */
7370     { PREFIX_TABLE (PREFIX_0F3A60) },
7371     { PREFIX_TABLE (PREFIX_0F3A61) },
7372     { PREFIX_TABLE (PREFIX_0F3A62) },
7373     { PREFIX_TABLE (PREFIX_0F3A63) },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* 68 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* 70 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* 78 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* 80 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* 88 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* 90 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     /* 98 */
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     /* a0 */
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     /* a8 */
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     /* b0 */
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     /* b8 */
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     /* c0 */
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     /* c8 */
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { PREFIX_TABLE (PREFIX_0F3ACC) },
7492     { Bad_Opcode },
7493     { PREFIX_TABLE (PREFIX_0F3ACE) },
7494     { PREFIX_TABLE (PREFIX_0F3ACF) },
7495     /* d0 */
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     /* d8 */
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { PREFIX_TABLE (PREFIX_0F3ADF) },
7513     /* e0 */
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     /* e8 */
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     /* f0 */
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     /* f8 */
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549   },
7550 };
7551
7552 static const struct dis386 xop_table[][256] = {
7553   /* XOP_08 */
7554   {
7555     /* 00 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 08 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 10 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     /* 18 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     /* 20 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     /* 28 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     /* 30 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     /* 38 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     /* 40 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     /* 48 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     /* 50 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     /* 58 */
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     /* 60 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     /* 68 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     /* 70 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* 78 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     /* 80 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7706     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7707     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7708     /* 88 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7716     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7717     /* 90 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7724     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7725     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7726     /* 98 */
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7734     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7735     /* a0 */
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7739     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7743     { Bad_Opcode },
7744     /* a8 */
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     /* b0 */
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7761     { Bad_Opcode },
7762     /* b8 */
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     /* c0 */
7772     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7773     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7774     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7775     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     /* c8 */
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7786     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7787     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7789     /* d0 */
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     /* d8 */
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     /* e0 */
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     /* e8 */
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7822     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7823     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7824     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7825     /* f0 */
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     /* f8 */
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843   },
7844   /* XOP_09 */
7845   {
7846     /* 00 */
7847     { Bad_Opcode },
7848     { REG_TABLE (REG_XOP_TBM_01) },
7849     { REG_TABLE (REG_XOP_TBM_02) },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 08 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     /* 10 */
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { REG_TABLE (REG_XOP_LWPCB) },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 18 */
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     /* 20 */
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     /* 28 */
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     /* 30 */
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     /* 38 */
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* 40 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* 48 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* 50 */
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* 58 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* 60 */
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     /* 68 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* 70 */
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* 78 */
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* 80 */
7991     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7992     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7993     { "vfrczss",        { XM, EXd }, 0 },
7994     { "vfrczsd",        { XM, EXq }, 0 },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* 88 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     /* 90 */
8009     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8010     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8011     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8012     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     /* 98 */
8018     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     /* a0 */
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     /* a8 */
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     /* b0 */
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     /* b8 */
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     /* c0 */
8063     { Bad_Opcode },
8064     { "vphaddbw",       { XM, EXxmm }, 0 },
8065     { "vphaddbd",       { XM, EXxmm }, 0 },
8066     { "vphaddbq",       { XM, EXxmm }, 0 },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { "vphaddwd",       { XM, EXxmm }, 0 },
8070     { "vphaddwq",       { XM, EXxmm }, 0 },
8071     /* c8 */
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { "vphadddq",       { XM, EXxmm }, 0 },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     /* d0 */
8081     { Bad_Opcode },
8082     { "vphaddubw",      { XM, EXxmm }, 0 },
8083     { "vphaddubd",      { XM, EXxmm }, 0 },
8084     { "vphaddubq",      { XM, EXxmm }, 0 },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { "vphadduwd",      { XM, EXxmm }, 0 },
8088     { "vphadduwq",      { XM, EXxmm }, 0 },
8089     /* d8 */
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { "vphaddudq",      { XM, EXxmm }, 0 },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     /* e0 */
8099     { Bad_Opcode },
8100     { "vphsubbw",       { XM, EXxmm }, 0 },
8101     { "vphsubwd",       { XM, EXxmm }, 0 },
8102     { "vphsubdq",       { XM, EXxmm }, 0 },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     /* e8 */
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     /* f0 */
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     /* f8 */
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134   },
8135   /* XOP_0A */
8136   {
8137     /* 00 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     /* 08 */
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     /* 10 */
8156     { "bextrS", { Gdq, Edq, Id }, 0 },
8157     { Bad_Opcode },
8158     { REG_TABLE (REG_XOP_LWP) },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* 18 */
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     /* 20 */
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     /* 28 */
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     /* 30 */
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     /* 38 */
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     /* 40 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* 48 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* 50 */
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* 58 */
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     /* 60 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* 68 */
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     /* 70 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* 78 */
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* 80 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* 88 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     /* 90 */
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     /* 98 */
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     /* a0 */
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     /* a8 */
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     /* b0 */
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     /* b8 */
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     /* c0 */
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     /* c8 */
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     /* d0 */
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     /* d8 */
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     /* e0 */
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     /* e8 */
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     /* f0 */
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     /* f8 */
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425   },
8426 };
8427
8428 static const struct dis386 vex_table[][256] = {
8429   /* VEX_0F */
8430   {
8431     /* 00 */
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     /* 08 */
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     /* 10 */
8450     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8451     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8453     { MOD_TABLE (MOD_VEX_0F13) },
8454     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8455     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8456     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8457     { MOD_TABLE (MOD_VEX_0F17) },
8458     /* 18 */
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     /* 20 */
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     /* 28 */
8477     { "vmovapX",        { XM, EXx }, 0 },
8478     { "vmovapX",        { EXxS, XM }, 0 },
8479     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8480     { MOD_TABLE (MOD_VEX_0F2B) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8485     /* 30 */
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     /* 38 */
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     /* 40 */
8504     { Bad_Opcode },
8505     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8506     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8507     { Bad_Opcode },
8508     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8509     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8510     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8512     /* 48 */
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     /* 50 */
8522     { MOD_TABLE (MOD_VEX_0F50) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8526     { "vandpX",         { XM, Vex, EXx }, 0 },
8527     { "vandnpX",        { XM, Vex, EXx }, 0 },
8528     { "vorpX",          { XM, Vex, EXx }, 0 },
8529     { "vxorpX",         { XM, Vex, EXx }, 0 },
8530     /* 58 */
8531     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8539     /* 60 */
8540     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8548     /* 68 */
8549     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8557     /* 70 */
8558     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8559     { REG_TABLE (REG_VEX_0F71) },
8560     { REG_TABLE (REG_VEX_0F72) },
8561     { REG_TABLE (REG_VEX_0F73) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8566     /* 78 */
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8572     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8575     /* 80 */
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     /* 88 */
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     /* 90 */
8594     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     /* 98 */
8603     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     /* a0 */
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     /* a8 */
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { REG_TABLE (REG_VEX_0FAE) },
8628     { Bad_Opcode },
8629     /* b0 */
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     /* b8 */
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     /* c0 */
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8651     { Bad_Opcode },
8652     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8653     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8654     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8655     { Bad_Opcode },
8656     /* c8 */
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     /* d0 */
8666     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8674     /* d8 */
8675     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8683     /* e0 */
8684     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8692     /* e8 */
8693     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8701     /* f0 */
8702     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8710     /* f8 */
8711     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8718     { Bad_Opcode },
8719   },
8720   /* VEX_0F38 */
8721   {
8722     /* 00 */
8723     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8731     /* 08 */
8732     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8740     /* 10 */
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8749     /* 18 */
8750     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8753     { Bad_Opcode },
8754     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8757     { Bad_Opcode },
8758     /* 20 */
8759     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     /* 28 */
8768     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8776     /* 30 */
8777     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8785     /* 38 */
8786     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8794     /* 40 */
8795     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8803     /* 48 */
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     /* 50 */
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     /* 58 */
8822     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     /* 60 */
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     /* 68 */
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     /* 70 */
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     /* 78 */
8858     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     /* 80 */
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     /* 88 */
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8881     { Bad_Opcode },
8882     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8883     { Bad_Opcode },
8884     /* 90 */
8885     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8893     /* 98 */
8894     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8902     /* a0 */
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8911     /* a8 */
8912     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8920     /* b0 */
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8929     /* b8 */
8930     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8938     /* c0 */
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     /* c8 */
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8956     /* d0 */
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     /* d8 */
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8974     /* e0 */
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     /* e8 */
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     /* f0 */
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8996     { REG_TABLE (REG_VEX_0F38F3) },
8997     { Bad_Opcode },
8998     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9001     /* f8 */
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010   },
9011   /* VEX_0F3A */
9012   {
9013     /* 00 */
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9017     { Bad_Opcode },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9021     { Bad_Opcode },
9022     /* 08 */
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9031     /* 10 */
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9040     /* 18 */
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     /* 20 */
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     /* 28 */
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     /* 30 */
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     /* 38 */
9077     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     /* 40 */
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9089     { Bad_Opcode },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9091     { Bad_Opcode },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9093     { Bad_Opcode },
9094     /* 48 */
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     /* 50 */
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     /* 58 */
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9121     /* 60 */
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     /* 68 */
9131     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9139     /* 70 */
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     /* 78 */
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9157     /* 80 */
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     /* 88 */
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     /* 90 */
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     /* 98 */
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     /* a0 */
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     /* a8 */
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     /* b0 */
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     /* b8 */
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     /* c0 */
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     /* c8 */
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9246     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9247     /* d0 */
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     /* d8 */
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9265     /* e0 */
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     /* e8 */
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     /* f0 */
9284     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     /* f8 */
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301   },
9302 };
9303
9304 #include "i386-dis-evex.h"
9305
9306 static const struct dis386 vex_len_table[][2] = {
9307   /* VEX_LEN_0F12_P_0_M_0 */
9308   {
9309     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9310   },
9311
9312   /* VEX_LEN_0F12_P_0_M_1 */
9313   {
9314     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9315   },
9316
9317   /* VEX_LEN_0F12_P_2 */
9318   {
9319     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9320   },
9321
9322   /* VEX_LEN_0F13_M_0 */
9323   {
9324     { "vmovlpX",        { EXq, XM }, 0 },
9325   },
9326
9327   /* VEX_LEN_0F16_P_0_M_0 */
9328   {
9329     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9330   },
9331
9332   /* VEX_LEN_0F16_P_0_M_1 */
9333   {
9334     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9335   },
9336
9337   /* VEX_LEN_0F16_P_2 */
9338   {
9339     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9340   },
9341
9342   /* VEX_LEN_0F17_M_0 */
9343   {
9344     { "vmovhpX",        { EXq, XM }, 0 },
9345   },
9346
9347   /* VEX_LEN_0F41_P_0 */
9348   {
9349     { Bad_Opcode },
9350     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9351   },
9352   /* VEX_LEN_0F41_P_2 */
9353   {
9354     { Bad_Opcode },
9355     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9356   },
9357   /* VEX_LEN_0F42_P_0 */
9358   {
9359     { Bad_Opcode },
9360     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9361   },
9362   /* VEX_LEN_0F42_P_2 */
9363   {
9364     { Bad_Opcode },
9365     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9366   },
9367   /* VEX_LEN_0F44_P_0 */
9368   {
9369     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9370   },
9371   /* VEX_LEN_0F44_P_2 */
9372   {
9373     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9374   },
9375   /* VEX_LEN_0F45_P_0 */
9376   {
9377     { Bad_Opcode },
9378     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9379   },
9380   /* VEX_LEN_0F45_P_2 */
9381   {
9382     { Bad_Opcode },
9383     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9384   },
9385   /* VEX_LEN_0F46_P_0 */
9386   {
9387     { Bad_Opcode },
9388     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9389   },
9390   /* VEX_LEN_0F46_P_2 */
9391   {
9392     { Bad_Opcode },
9393     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9394   },
9395   /* VEX_LEN_0F47_P_0 */
9396   {
9397     { Bad_Opcode },
9398     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9399   },
9400   /* VEX_LEN_0F47_P_2 */
9401   {
9402     { Bad_Opcode },
9403     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9404   },
9405   /* VEX_LEN_0F4A_P_0 */
9406   {
9407     { Bad_Opcode },
9408     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9409   },
9410   /* VEX_LEN_0F4A_P_2 */
9411   {
9412     { Bad_Opcode },
9413     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9414   },
9415   /* VEX_LEN_0F4B_P_0 */
9416   {
9417     { Bad_Opcode },
9418     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9419   },
9420   /* VEX_LEN_0F4B_P_2 */
9421   {
9422     { Bad_Opcode },
9423     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9424   },
9425
9426   /* VEX_LEN_0F6E_P_2 */
9427   {
9428     { "vmovK",          { XMScalar, Edq }, 0 },
9429   },
9430
9431   /* VEX_LEN_0F77_P_1 */
9432   {
9433     { "vzeroupper",     { XX }, 0 },
9434     { "vzeroall",       { XX }, 0 },
9435   },
9436
9437   /* VEX_LEN_0F7E_P_1 */
9438   {
9439     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9440   },
9441
9442   /* VEX_LEN_0F7E_P_2 */
9443   {
9444     { "vmovK",          { Edq, XMScalar }, 0 },
9445   },
9446
9447   /* VEX_LEN_0F90_P_0 */
9448   {
9449     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9450   },
9451
9452   /* VEX_LEN_0F90_P_2 */
9453   {
9454     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9455   },
9456
9457   /* VEX_LEN_0F91_P_0 */
9458   {
9459     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9460   },
9461
9462   /* VEX_LEN_0F91_P_2 */
9463   {
9464     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9465   },
9466
9467   /* VEX_LEN_0F92_P_0 */
9468   {
9469     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9470   },
9471
9472   /* VEX_LEN_0F92_P_2 */
9473   {
9474     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9475   },
9476
9477   /* VEX_LEN_0F92_P_3 */
9478   {
9479     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9480   },
9481
9482   /* VEX_LEN_0F93_P_0 */
9483   {
9484     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9485   },
9486
9487   /* VEX_LEN_0F93_P_2 */
9488   {
9489     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9490   },
9491
9492   /* VEX_LEN_0F93_P_3 */
9493   {
9494     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9495   },
9496
9497   /* VEX_LEN_0F98_P_0 */
9498   {
9499     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9500   },
9501
9502   /* VEX_LEN_0F98_P_2 */
9503   {
9504     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9505   },
9506
9507   /* VEX_LEN_0F99_P_0 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9510   },
9511
9512   /* VEX_LEN_0F99_P_2 */
9513   {
9514     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9515   },
9516
9517   /* VEX_LEN_0FAE_R_2_M_0 */
9518   {
9519     { "vldmxcsr",       { Md }, 0 },
9520   },
9521
9522   /* VEX_LEN_0FAE_R_3_M_0 */
9523   {
9524     { "vstmxcsr",       { Md }, 0 },
9525   },
9526
9527   /* VEX_LEN_0FC4_P_2 */
9528   {
9529     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9530   },
9531
9532   /* VEX_LEN_0FC5_P_2 */
9533   {
9534     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9535   },
9536
9537   /* VEX_LEN_0FD6_P_2 */
9538   {
9539     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9540   },
9541
9542   /* VEX_LEN_0FF7_P_2 */
9543   {
9544     { "vmaskmovdqu",    { XM, XS }, 0 },
9545   },
9546
9547   /* VEX_LEN_0F3816_P_2 */
9548   {
9549     { Bad_Opcode },
9550     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9551   },
9552
9553   /* VEX_LEN_0F3819_P_2 */
9554   {
9555     { Bad_Opcode },
9556     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9557   },
9558
9559   /* VEX_LEN_0F381A_P_2_M_0 */
9560   {
9561     { Bad_Opcode },
9562     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9563   },
9564
9565   /* VEX_LEN_0F3836_P_2 */
9566   {
9567     { Bad_Opcode },
9568     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9569   },
9570
9571   /* VEX_LEN_0F3841_P_2 */
9572   {
9573     { "vphminposuw",    { XM, EXx }, 0 },
9574   },
9575
9576   /* VEX_LEN_0F385A_P_2_M_0 */
9577   {
9578     { Bad_Opcode },
9579     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9580   },
9581
9582   /* VEX_LEN_0F38DB_P_2 */
9583   {
9584     { "vaesimc",        { XM, EXx }, 0 },
9585   },
9586
9587   /* VEX_LEN_0F38F2_P_0 */
9588   {
9589     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9590   },
9591
9592   /* VEX_LEN_0F38F3_R_1_P_0 */
9593   {
9594     { "blsrS",          { VexGdq, Edq }, 0 },
9595   },
9596
9597   /* VEX_LEN_0F38F3_R_2_P_0 */
9598   {
9599     { "blsmskS",        { VexGdq, Edq }, 0 },
9600   },
9601
9602   /* VEX_LEN_0F38F3_R_3_P_0 */
9603   {
9604     { "blsiS",          { VexGdq, Edq }, 0 },
9605   },
9606
9607   /* VEX_LEN_0F38F5_P_0 */
9608   {
9609     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9610   },
9611
9612   /* VEX_LEN_0F38F5_P_1 */
9613   {
9614     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9615   },
9616
9617   /* VEX_LEN_0F38F5_P_3 */
9618   {
9619     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9620   },
9621
9622   /* VEX_LEN_0F38F6_P_3 */
9623   {
9624     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9625   },
9626
9627   /* VEX_LEN_0F38F7_P_0 */
9628   {
9629     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9630   },
9631
9632   /* VEX_LEN_0F38F7_P_1 */
9633   {
9634     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9635   },
9636
9637   /* VEX_LEN_0F38F7_P_2 */
9638   {
9639     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9640   },
9641
9642   /* VEX_LEN_0F38F7_P_3 */
9643   {
9644     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9645   },
9646
9647   /* VEX_LEN_0F3A00_P_2 */
9648   {
9649     { Bad_Opcode },
9650     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9651   },
9652
9653   /* VEX_LEN_0F3A01_P_2 */
9654   {
9655     { Bad_Opcode },
9656     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9657   },
9658
9659   /* VEX_LEN_0F3A06_P_2 */
9660   {
9661     { Bad_Opcode },
9662     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9663   },
9664
9665   /* VEX_LEN_0F3A14_P_2 */
9666   {
9667     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9668   },
9669
9670   /* VEX_LEN_0F3A15_P_2 */
9671   {
9672     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9673   },
9674
9675   /* VEX_LEN_0F3A16_P_2  */
9676   {
9677     { "vpextrK",        { Edq, XM, Ib }, 0 },
9678   },
9679
9680   /* VEX_LEN_0F3A17_P_2 */
9681   {
9682     { "vextractps",     { Edqd, XM, Ib }, 0 },
9683   },
9684
9685   /* VEX_LEN_0F3A18_P_2 */
9686   {
9687     { Bad_Opcode },
9688     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9689   },
9690
9691   /* VEX_LEN_0F3A19_P_2 */
9692   {
9693     { Bad_Opcode },
9694     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9695   },
9696
9697   /* VEX_LEN_0F3A20_P_2 */
9698   {
9699     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9700   },
9701
9702   /* VEX_LEN_0F3A21_P_2 */
9703   {
9704     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9705   },
9706
9707   /* VEX_LEN_0F3A22_P_2 */
9708   {
9709     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9710   },
9711
9712   /* VEX_LEN_0F3A30_P_2 */
9713   {
9714     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9715   },
9716
9717   /* VEX_LEN_0F3A31_P_2 */
9718   {
9719     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9720   },
9721
9722   /* VEX_LEN_0F3A32_P_2 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9725   },
9726
9727   /* VEX_LEN_0F3A33_P_2 */
9728   {
9729     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9730   },
9731
9732   /* VEX_LEN_0F3A38_P_2 */
9733   {
9734     { Bad_Opcode },
9735     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9736   },
9737
9738   /* VEX_LEN_0F3A39_P_2 */
9739   {
9740     { Bad_Opcode },
9741     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9742   },
9743
9744   /* VEX_LEN_0F3A41_P_2 */
9745   {
9746     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9747   },
9748
9749   /* VEX_LEN_0F3A46_P_2 */
9750   {
9751     { Bad_Opcode },
9752     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9753   },
9754
9755   /* VEX_LEN_0F3A60_P_2 */
9756   {
9757     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9758   },
9759
9760   /* VEX_LEN_0F3A61_P_2 */
9761   {
9762     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9763   },
9764
9765   /* VEX_LEN_0F3A62_P_2 */
9766   {
9767     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9768   },
9769
9770   /* VEX_LEN_0F3A63_P_2 */
9771   {
9772     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9773   },
9774
9775   /* VEX_LEN_0F3A6A_P_2 */
9776   {
9777     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9778   },
9779
9780   /* VEX_LEN_0F3A6B_P_2 */
9781   {
9782     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9783   },
9784
9785   /* VEX_LEN_0F3A6E_P_2 */
9786   {
9787     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9788   },
9789
9790   /* VEX_LEN_0F3A6F_P_2 */
9791   {
9792     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9793   },
9794
9795   /* VEX_LEN_0F3A7A_P_2 */
9796   {
9797     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9798   },
9799
9800   /* VEX_LEN_0F3A7B_P_2 */
9801   {
9802     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9803   },
9804
9805   /* VEX_LEN_0F3A7E_P_2 */
9806   {
9807     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9808   },
9809
9810   /* VEX_LEN_0F3A7F_P_2 */
9811   {
9812     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9813   },
9814
9815   /* VEX_LEN_0F3ADF_P_2 */
9816   {
9817     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9818   },
9819
9820   /* VEX_LEN_0F3AF0_P_3 */
9821   {
9822     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9823   },
9824
9825   /* VEX_LEN_0FXOP_08_CC */
9826   {
9827      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9828   },
9829
9830   /* VEX_LEN_0FXOP_08_CD */
9831   {
9832      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9833   },
9834
9835   /* VEX_LEN_0FXOP_08_CE */
9836   {
9837      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9838   },
9839
9840   /* VEX_LEN_0FXOP_08_CF */
9841   {
9842      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9843   },
9844
9845   /* VEX_LEN_0FXOP_08_EC */
9846   {
9847      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9848   },
9849
9850   /* VEX_LEN_0FXOP_08_ED */
9851   {
9852      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9853   },
9854
9855   /* VEX_LEN_0FXOP_08_EE */
9856   {
9857      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9858   },
9859
9860   /* VEX_LEN_0FXOP_08_EF */
9861   {
9862      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9863   },
9864
9865   /* VEX_LEN_0FXOP_09_80 */
9866   {
9867     { "vfrczps",        { XM, EXxmm }, 0 },
9868     { "vfrczps",        { XM, EXymmq }, 0 },
9869   },
9870
9871   /* VEX_LEN_0FXOP_09_81 */
9872   {
9873     { "vfrczpd",        { XM, EXxmm }, 0 },
9874     { "vfrczpd",        { XM, EXymmq }, 0 },
9875   },
9876 };
9877
9878 #include "i386-dis-evex-len.h"
9879
9880 static const struct dis386 vex_w_table[][2] = {
9881   {
9882     /* VEX_W_0F41_P_0_LEN_1 */
9883     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9884     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9885   },
9886   {
9887     /* VEX_W_0F41_P_2_LEN_1 */
9888     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9889     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9890   },
9891   {
9892     /* VEX_W_0F42_P_0_LEN_1 */
9893     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9894     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9895   },
9896   {
9897     /* VEX_W_0F42_P_2_LEN_1 */
9898     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9899     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9900   },
9901   {
9902     /* VEX_W_0F44_P_0_LEN_0 */
9903     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9904     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9905   },
9906   {
9907     /* VEX_W_0F44_P_2_LEN_0 */
9908     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9909     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9910   },
9911   {
9912     /* VEX_W_0F45_P_0_LEN_1 */
9913     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9914     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9915   },
9916   {
9917     /* VEX_W_0F45_P_2_LEN_1 */
9918     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9919     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9920   },
9921   {
9922     /* VEX_W_0F46_P_0_LEN_1 */
9923     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9924     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9925   },
9926   {
9927     /* VEX_W_0F46_P_2_LEN_1 */
9928     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9929     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9930   },
9931   {
9932     /* VEX_W_0F47_P_0_LEN_1 */
9933     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9934     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9935   },
9936   {
9937     /* VEX_W_0F47_P_2_LEN_1 */
9938     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9939     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9940   },
9941   {
9942     /* VEX_W_0F4A_P_0_LEN_1 */
9943     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9944     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9945   },
9946   {
9947     /* VEX_W_0F4A_P_2_LEN_1 */
9948     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9949     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9950   },
9951   {
9952     /* VEX_W_0F4B_P_0_LEN_1 */
9953     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9954     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9955   },
9956   {
9957     /* VEX_W_0F4B_P_2_LEN_1 */
9958     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9959   },
9960   {
9961     /* VEX_W_0F90_P_0_LEN_0 */
9962     { "kmovw",          { MaskG, MaskE }, 0 },
9963     { "kmovq",          { MaskG, MaskE }, 0 },
9964   },
9965   {
9966     /* VEX_W_0F90_P_2_LEN_0 */
9967     { "kmovb",          { MaskG, MaskBDE }, 0 },
9968     { "kmovd",          { MaskG, MaskBDE }, 0 },
9969   },
9970   {
9971     /* VEX_W_0F91_P_0_LEN_0 */
9972     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9973     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9974   },
9975   {
9976     /* VEX_W_0F91_P_2_LEN_0 */
9977     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9978     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9979   },
9980   {
9981     /* VEX_W_0F92_P_0_LEN_0 */
9982     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9983   },
9984   {
9985     /* VEX_W_0F92_P_2_LEN_0 */
9986     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9987   },
9988   {
9989     /* VEX_W_0F93_P_0_LEN_0 */
9990     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9991   },
9992   {
9993     /* VEX_W_0F93_P_2_LEN_0 */
9994     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9995   },
9996   {
9997     /* VEX_W_0F98_P_0_LEN_0 */
9998     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9999     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10000   },
10001   {
10002     /* VEX_W_0F98_P_2_LEN_0 */
10003     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10004     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10005   },
10006   {
10007     /* VEX_W_0F99_P_0_LEN_0 */
10008     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10009     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10010   },
10011   {
10012     /* VEX_W_0F99_P_2_LEN_0 */
10013     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10014     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10015   },
10016   {
10017     /* VEX_W_0F380C_P_2  */
10018     { "vpermilps",      { XM, Vex, EXx }, 0 },
10019   },
10020   {
10021     /* VEX_W_0F380D_P_2  */
10022     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10023   },
10024   {
10025     /* VEX_W_0F380E_P_2  */
10026     { "vtestps",        { XM, EXx }, 0 },
10027   },
10028   {
10029     /* VEX_W_0F380F_P_2  */
10030     { "vtestpd",        { XM, EXx }, 0 },
10031   },
10032   {
10033     /* VEX_W_0F3816_P_2  */
10034     { "vpermps",        { XM, Vex, EXx }, 0 },
10035   },
10036   {
10037     /* VEX_W_0F3818_P_2 */
10038     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10039   },
10040   {
10041     /* VEX_W_0F3819_P_2 */
10042     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10043   },
10044   {
10045     /* VEX_W_0F381A_P_2_M_0 */
10046     { "vbroadcastf128", { XM, Mxmm }, 0 },
10047   },
10048   {
10049     /* VEX_W_0F382C_P_2_M_0 */
10050     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10051   },
10052   {
10053     /* VEX_W_0F382D_P_2_M_0 */
10054     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10055   },
10056   {
10057     /* VEX_W_0F382E_P_2_M_0 */
10058     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10059   },
10060   {
10061     /* VEX_W_0F382F_P_2_M_0 */
10062     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10063   },
10064   {
10065     /* VEX_W_0F3836_P_2  */
10066     { "vpermd",         { XM, Vex, EXx }, 0 },
10067   },
10068   {
10069     /* VEX_W_0F3846_P_2 */
10070     { "vpsravd",        { XM, Vex, EXx }, 0 },
10071   },
10072   {
10073     /* VEX_W_0F3858_P_2 */
10074     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10075   },
10076   {
10077     /* VEX_W_0F3859_P_2 */
10078     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10079   },
10080   {
10081     /* VEX_W_0F385A_P_2_M_0 */
10082     { "vbroadcasti128", { XM, Mxmm }, 0 },
10083   },
10084   {
10085     /* VEX_W_0F3878_P_2 */
10086     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10087   },
10088   {
10089     /* VEX_W_0F3879_P_2 */
10090     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10091   },
10092   {
10093     /* VEX_W_0F38CF_P_2 */
10094     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10095   },
10096   {
10097     /* VEX_W_0F3A00_P_2 */
10098     { Bad_Opcode },
10099     { "vpermq",         { XM, EXx, Ib }, 0 },
10100   },
10101   {
10102     /* VEX_W_0F3A01_P_2 */
10103     { Bad_Opcode },
10104     { "vpermpd",        { XM, EXx, Ib }, 0 },
10105   },
10106   {
10107     /* VEX_W_0F3A02_P_2 */
10108     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10109   },
10110   {
10111     /* VEX_W_0F3A04_P_2 */
10112     { "vpermilps",      { XM, EXx, Ib }, 0 },
10113   },
10114   {
10115     /* VEX_W_0F3A05_P_2 */
10116     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10117   },
10118   {
10119     /* VEX_W_0F3A06_P_2 */
10120     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10121   },
10122   {
10123     /* VEX_W_0F3A18_P_2 */
10124     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10125   },
10126   {
10127     /* VEX_W_0F3A19_P_2 */
10128     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10129   },
10130   {
10131     /* VEX_W_0F3A30_P_2_LEN_0 */
10132     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10133     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10134   },
10135   {
10136     /* VEX_W_0F3A31_P_2_LEN_0 */
10137     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10138     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10139   },
10140   {
10141     /* VEX_W_0F3A32_P_2_LEN_0 */
10142     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10143     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10144   },
10145   {
10146     /* VEX_W_0F3A33_P_2_LEN_0 */
10147     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10148     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10149   },
10150   {
10151     /* VEX_W_0F3A38_P_2 */
10152     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10153   },
10154   {
10155     /* VEX_W_0F3A39_P_2 */
10156     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10157   },
10158   {
10159     /* VEX_W_0F3A46_P_2 */
10160     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10161   },
10162   {
10163     /* VEX_W_0F3A48_P_2 */
10164     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10165     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10166   },
10167   {
10168     /* VEX_W_0F3A49_P_2 */
10169     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10170     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10171   },
10172   {
10173     /* VEX_W_0F3A4A_P_2 */
10174     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10175   },
10176   {
10177     /* VEX_W_0F3A4B_P_2 */
10178     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10179   },
10180   {
10181     /* VEX_W_0F3A4C_P_2 */
10182     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10183   },
10184   {
10185     /* VEX_W_0F3ACE_P_2 */
10186     { Bad_Opcode },
10187     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10188   },
10189   {
10190     /* VEX_W_0F3ACF_P_2 */
10191     { Bad_Opcode },
10192     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10193   },
10194
10195 #include "i386-dis-evex-w.h"
10196 };
10197
10198 static const struct dis386 mod_table[][2] = {
10199   {
10200     /* MOD_8D */
10201     { "leaS",           { Gv, M }, 0 },
10202   },
10203   {
10204     /* MOD_C6_REG_7 */
10205     { Bad_Opcode },
10206     { RM_TABLE (RM_C6_REG_7) },
10207   },
10208   {
10209     /* MOD_C7_REG_7 */
10210     { Bad_Opcode },
10211     { RM_TABLE (RM_C7_REG_7) },
10212   },
10213   {
10214     /* MOD_FF_REG_3 */
10215     { "Jcall^", { indirEp }, 0 },
10216   },
10217   {
10218     /* MOD_FF_REG_5 */
10219     { "Jjmp^", { indirEp }, 0 },
10220   },
10221   {
10222     /* MOD_0F01_REG_0 */
10223     { X86_64_TABLE (X86_64_0F01_REG_0) },
10224     { RM_TABLE (RM_0F01_REG_0) },
10225   },
10226   {
10227     /* MOD_0F01_REG_1 */
10228     { X86_64_TABLE (X86_64_0F01_REG_1) },
10229     { RM_TABLE (RM_0F01_REG_1) },
10230   },
10231   {
10232     /* MOD_0F01_REG_2 */
10233     { X86_64_TABLE (X86_64_0F01_REG_2) },
10234     { RM_TABLE (RM_0F01_REG_2) },
10235   },
10236   {
10237     /* MOD_0F01_REG_3 */
10238     { X86_64_TABLE (X86_64_0F01_REG_3) },
10239     { RM_TABLE (RM_0F01_REG_3) },
10240   },
10241   {
10242     /* MOD_0F01_REG_5 */
10243     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10244     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10245   },
10246   {
10247     /* MOD_0F01_REG_7 */
10248     { "invlpg",         { Mb }, 0 },
10249     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10250   },
10251   {
10252     /* MOD_0F12_PREFIX_0 */
10253     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10254     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10255   },
10256   {
10257     /* MOD_0F13 */
10258     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10259   },
10260   {
10261     /* MOD_0F16_PREFIX_0 */
10262     { "movhps",         { XM, EXq }, 0 },
10263     { "movlhps",        { XM, EXq }, 0 },
10264   },
10265   {
10266     /* MOD_0F17 */
10267     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10268   },
10269   {
10270     /* MOD_0F18_REG_0 */
10271     { "prefetchnta",    { Mb }, 0 },
10272   },
10273   {
10274     /* MOD_0F18_REG_1 */
10275     { "prefetcht0",     { Mb }, 0 },
10276   },
10277   {
10278     /* MOD_0F18_REG_2 */
10279     { "prefetcht1",     { Mb }, 0 },
10280   },
10281   {
10282     /* MOD_0F18_REG_3 */
10283     { "prefetcht2",     { Mb }, 0 },
10284   },
10285   {
10286     /* MOD_0F18_REG_4 */
10287     { "nop/reserved",   { Mb }, 0 },
10288   },
10289   {
10290     /* MOD_0F18_REG_5 */
10291     { "nop/reserved",   { Mb }, 0 },
10292   },
10293   {
10294     /* MOD_0F18_REG_6 */
10295     { "nop/reserved",   { Mb }, 0 },
10296   },
10297   {
10298     /* MOD_0F18_REG_7 */
10299     { "nop/reserved",   { Mb }, 0 },
10300   },
10301   {
10302     /* MOD_0F1A_PREFIX_0 */
10303     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10304     { "nopQ",           { Ev }, 0 },
10305   },
10306   {
10307     /* MOD_0F1B_PREFIX_0 */
10308     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10309     { "nopQ",           { Ev }, 0 },
10310   },
10311   {
10312     /* MOD_0F1B_PREFIX_1 */
10313     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10314     { "nopQ",           { Ev }, 0 },
10315   },
10316   {
10317     /* MOD_0F1C_PREFIX_0 */
10318     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10319     { "nopQ",           { Ev }, 0 },
10320   },
10321   {
10322     /* MOD_0F1E_PREFIX_1 */
10323     { "nopQ",           { Ev }, 0 },
10324     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10325   },
10326   {
10327     /* MOD_0F24 */
10328     { Bad_Opcode },
10329     { "movL",           { Rd, Td }, 0 },
10330   },
10331   {
10332     /* MOD_0F26 */
10333     { Bad_Opcode },
10334     { "movL",           { Td, Rd }, 0 },
10335   },
10336   {
10337     /* MOD_0F2B_PREFIX_0 */
10338     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10339   },
10340   {
10341     /* MOD_0F2B_PREFIX_1 */
10342     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10343   },
10344   {
10345     /* MOD_0F2B_PREFIX_2 */
10346     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10347   },
10348   {
10349     /* MOD_0F2B_PREFIX_3 */
10350     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10351   },
10352   {
10353     /* MOD_0F51 */
10354     { Bad_Opcode },
10355     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10356   },
10357   {
10358     /* MOD_0F71_REG_2 */
10359     { Bad_Opcode },
10360     { "psrlw",          { MS, Ib }, 0 },
10361   },
10362   {
10363     /* MOD_0F71_REG_4 */
10364     { Bad_Opcode },
10365     { "psraw",          { MS, Ib }, 0 },
10366   },
10367   {
10368     /* MOD_0F71_REG_6 */
10369     { Bad_Opcode },
10370     { "psllw",          { MS, Ib }, 0 },
10371   },
10372   {
10373     /* MOD_0F72_REG_2 */
10374     { Bad_Opcode },
10375     { "psrld",          { MS, Ib }, 0 },
10376   },
10377   {
10378     /* MOD_0F72_REG_4 */
10379     { Bad_Opcode },
10380     { "psrad",          { MS, Ib }, 0 },
10381   },
10382   {
10383     /* MOD_0F72_REG_6 */
10384     { Bad_Opcode },
10385     { "pslld",          { MS, Ib }, 0 },
10386   },
10387   {
10388     /* MOD_0F73_REG_2 */
10389     { Bad_Opcode },
10390     { "psrlq",          { MS, Ib }, 0 },
10391   },
10392   {
10393     /* MOD_0F73_REG_3 */
10394     { Bad_Opcode },
10395     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10396   },
10397   {
10398     /* MOD_0F73_REG_6 */
10399     { Bad_Opcode },
10400     { "psllq",          { MS, Ib }, 0 },
10401   },
10402   {
10403     /* MOD_0F73_REG_7 */
10404     { Bad_Opcode },
10405     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10406   },
10407   {
10408     /* MOD_0FAE_REG_0 */
10409     { "fxsave",         { FXSAVE }, 0 },
10410     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10411   },
10412   {
10413     /* MOD_0FAE_REG_1 */
10414     { "fxrstor",        { FXSAVE }, 0 },
10415     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10416   },
10417   {
10418     /* MOD_0FAE_REG_2 */
10419     { "ldmxcsr",        { Md }, 0 },
10420     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10421   },
10422   {
10423     /* MOD_0FAE_REG_3 */
10424     { "stmxcsr",        { Md }, 0 },
10425     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10426   },
10427   {
10428     /* MOD_0FAE_REG_4 */
10429     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10430     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10431   },
10432   {
10433     /* MOD_0FAE_REG_5 */
10434     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10435     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10436   },
10437   {
10438     /* MOD_0FAE_REG_6 */
10439     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10440     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10441   },
10442   {
10443     /* MOD_0FAE_REG_7 */
10444     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10445     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10446   },
10447   {
10448     /* MOD_0FB2 */
10449     { "lssS",           { Gv, Mp }, 0 },
10450   },
10451   {
10452     /* MOD_0FB4 */
10453     { "lfsS",           { Gv, Mp }, 0 },
10454   },
10455   {
10456     /* MOD_0FB5 */
10457     { "lgsS",           { Gv, Mp }, 0 },
10458   },
10459   {
10460     /* MOD_0FC3 */
10461     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10462   },
10463   {
10464     /* MOD_0FC7_REG_3 */
10465     { "xrstors",        { FXSAVE }, 0 },
10466   },
10467   {
10468     /* MOD_0FC7_REG_4 */
10469     { "xsavec",         { FXSAVE }, 0 },
10470   },
10471   {
10472     /* MOD_0FC7_REG_5 */
10473     { "xsaves",         { FXSAVE }, 0 },
10474   },
10475   {
10476     /* MOD_0FC7_REG_6 */
10477     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10478     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10479   },
10480   {
10481     /* MOD_0FC7_REG_7 */
10482     { "vmptrst",        { Mq }, 0 },
10483     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10484   },
10485   {
10486     /* MOD_0FD7 */
10487     { Bad_Opcode },
10488     { "pmovmskb",       { Gdq, MS }, 0 },
10489   },
10490   {
10491     /* MOD_0FE7_PREFIX_2 */
10492     { "movntdq",        { Mx, XM }, 0 },
10493   },
10494   {
10495     /* MOD_0FF0_PREFIX_3 */
10496     { "lddqu",          { XM, M }, 0 },
10497   },
10498   {
10499     /* MOD_0F382A_PREFIX_2 */
10500     { "movntdqa",       { XM, Mx }, 0 },
10501   },
10502   {
10503     /* MOD_0F38F5_PREFIX_2 */
10504     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10505   },
10506   {
10507     /* MOD_0F38F6_PREFIX_0 */
10508     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10509   },
10510   {
10511     /* MOD_0F38F8_PREFIX_1 */
10512     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10513   },
10514   {
10515     /* MOD_0F38F8_PREFIX_2 */
10516     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10517   },
10518   {
10519     /* MOD_0F38F8_PREFIX_3 */
10520     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10521   },
10522   {
10523     /* MOD_0F38F9_PREFIX_0 */
10524     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10525   },
10526   {
10527     /* MOD_62_32BIT */
10528     { "bound{S|}",      { Gv, Ma }, 0 },
10529     { EVEX_TABLE (EVEX_0F) },
10530   },
10531   {
10532     /* MOD_C4_32BIT */
10533     { "lesS",           { Gv, Mp }, 0 },
10534     { VEX_C4_TABLE (VEX_0F) },
10535   },
10536   {
10537     /* MOD_C5_32BIT */
10538     { "ldsS",           { Gv, Mp }, 0 },
10539     { VEX_C5_TABLE (VEX_0F) },
10540   },
10541   {
10542     /* MOD_VEX_0F12_PREFIX_0 */
10543     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10544     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10545   },
10546   {
10547     /* MOD_VEX_0F13 */
10548     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10549   },
10550   {
10551     /* MOD_VEX_0F16_PREFIX_0 */
10552     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10553     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10554   },
10555   {
10556     /* MOD_VEX_0F17 */
10557     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10558   },
10559   {
10560     /* MOD_VEX_0F2B */
10561     { "vmovntpX",       { Mx, XM }, 0 },
10562   },
10563   {
10564     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10565     { Bad_Opcode },
10566     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10567   },
10568   {
10569     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10570     { Bad_Opcode },
10571     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10572   },
10573   {
10574     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10575     { Bad_Opcode },
10576     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10577   },
10578   {
10579     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10580     { Bad_Opcode },
10581     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10582   },
10583   {
10584     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10585     { Bad_Opcode },
10586     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10587   },
10588   {
10589     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10590     { Bad_Opcode },
10591     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10592   },
10593   {
10594     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10595     { Bad_Opcode },
10596     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10597   },
10598   {
10599     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10600     { Bad_Opcode },
10601     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10602   },
10603   {
10604     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10605     { Bad_Opcode },
10606     { "knotw",          { MaskG, MaskR }, 0 },
10607   },
10608   {
10609     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10610     { Bad_Opcode },
10611     { "knotq",          { MaskG, MaskR }, 0 },
10612   },
10613   {
10614     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10615     { Bad_Opcode },
10616     { "knotb",          { MaskG, MaskR }, 0 },
10617   },
10618   {
10619     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10620     { Bad_Opcode },
10621     { "knotd",          { MaskG, MaskR }, 0 },
10622   },
10623   {
10624     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10625     { Bad_Opcode },
10626     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10627   },
10628   {
10629     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10630     { Bad_Opcode },
10631     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10632   },
10633   {
10634     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10635     { Bad_Opcode },
10636     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10637   },
10638   {
10639     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10640     { Bad_Opcode },
10641     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10642   },
10643  {
10644     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10645     { Bad_Opcode },
10646     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10647   },
10648   {
10649     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10650     { Bad_Opcode },
10651     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10652   },
10653   {
10654     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10655     { Bad_Opcode },
10656     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10657   },
10658   {
10659     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10660     { Bad_Opcode },
10661     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10662   },
10663   {
10664     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10665     { Bad_Opcode },
10666     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10667   },
10668   {
10669     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10670     { Bad_Opcode },
10671     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10672   },
10673   {
10674     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10675     { Bad_Opcode },
10676     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10677   },
10678   {
10679     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10680     { Bad_Opcode },
10681     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10682   },
10683   {
10684     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10685     { Bad_Opcode },
10686     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10687   },
10688   {
10689     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10690     { Bad_Opcode },
10691     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10692   },
10693   {
10694     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10695     { Bad_Opcode },
10696     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10697   },
10698   {
10699     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10700     { Bad_Opcode },
10701     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10702   },
10703   {
10704     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10705     { Bad_Opcode },
10706     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10707   },
10708   {
10709     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10710     { Bad_Opcode },
10711     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10712   },
10713   {
10714     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10715     { Bad_Opcode },
10716     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10717   },
10718   {
10719     /* MOD_VEX_0F50 */
10720     { Bad_Opcode },
10721     { "vmovmskpX",      { Gdq, XS }, 0 },
10722   },
10723   {
10724     /* MOD_VEX_0F71_REG_2 */
10725     { Bad_Opcode },
10726     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10727   },
10728   {
10729     /* MOD_VEX_0F71_REG_4 */
10730     { Bad_Opcode },
10731     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10732   },
10733   {
10734     /* MOD_VEX_0F71_REG_6 */
10735     { Bad_Opcode },
10736     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10737   },
10738   {
10739     /* MOD_VEX_0F72_REG_2 */
10740     { Bad_Opcode },
10741     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10742   },
10743   {
10744     /* MOD_VEX_0F72_REG_4 */
10745     { Bad_Opcode },
10746     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10747   },
10748   {
10749     /* MOD_VEX_0F72_REG_6 */
10750     { Bad_Opcode },
10751     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10752   },
10753   {
10754     /* MOD_VEX_0F73_REG_2 */
10755     { Bad_Opcode },
10756     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10757   },
10758   {
10759     /* MOD_VEX_0F73_REG_3 */
10760     { Bad_Opcode },
10761     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10762   },
10763   {
10764     /* MOD_VEX_0F73_REG_6 */
10765     { Bad_Opcode },
10766     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10767   },
10768   {
10769     /* MOD_VEX_0F73_REG_7 */
10770     { Bad_Opcode },
10771     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10772   },
10773   {
10774     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10775     { "kmovw",          { Ew, MaskG }, 0 },
10776     { Bad_Opcode },
10777   },
10778   {
10779     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10780     { "kmovq",          { Eq, MaskG }, 0 },
10781     { Bad_Opcode },
10782   },
10783   {
10784     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10785     { "kmovb",          { Eb, MaskG }, 0 },
10786     { Bad_Opcode },
10787   },
10788   {
10789     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10790     { "kmovd",          { Ed, MaskG }, 0 },
10791     { Bad_Opcode },
10792   },
10793   {
10794     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10795     { Bad_Opcode },
10796     { "kmovw",          { MaskG, Rdq }, 0 },
10797   },
10798   {
10799     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10800     { Bad_Opcode },
10801     { "kmovb",          { MaskG, Rdq }, 0 },
10802   },
10803   {
10804     /* MOD_VEX_0F92_P_3_LEN_0 */
10805     { Bad_Opcode },
10806     { "kmovK",          { MaskG, Rdq }, 0 },
10807   },
10808   {
10809     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10810     { Bad_Opcode },
10811     { "kmovw",          { Gdq, MaskR }, 0 },
10812   },
10813   {
10814     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10815     { Bad_Opcode },
10816     { "kmovb",          { Gdq, MaskR }, 0 },
10817   },
10818   {
10819     /* MOD_VEX_0F93_P_3_LEN_0 */
10820     { Bad_Opcode },
10821     { "kmovK",          { Gdq, MaskR }, 0 },
10822   },
10823   {
10824     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10825     { Bad_Opcode },
10826     { "kortestw", { MaskG, MaskR }, 0 },
10827   },
10828   {
10829     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10830     { Bad_Opcode },
10831     { "kortestq", { MaskG, MaskR }, 0 },
10832   },
10833   {
10834     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10835     { Bad_Opcode },
10836     { "kortestb", { MaskG, MaskR }, 0 },
10837   },
10838   {
10839     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10840     { Bad_Opcode },
10841     { "kortestd", { MaskG, MaskR }, 0 },
10842   },
10843   {
10844     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10845     { Bad_Opcode },
10846     { "ktestw", { MaskG, MaskR }, 0 },
10847   },
10848   {
10849     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10850     { Bad_Opcode },
10851     { "ktestq", { MaskG, MaskR }, 0 },
10852   },
10853   {
10854     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10855     { Bad_Opcode },
10856     { "ktestb", { MaskG, MaskR }, 0 },
10857   },
10858   {
10859     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10860     { Bad_Opcode },
10861     { "ktestd", { MaskG, MaskR }, 0 },
10862   },
10863   {
10864     /* MOD_VEX_0FAE_REG_2 */
10865     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10866   },
10867   {
10868     /* MOD_VEX_0FAE_REG_3 */
10869     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10870   },
10871   {
10872     /* MOD_VEX_0FD7_PREFIX_2 */
10873     { Bad_Opcode },
10874     { "vpmovmskb",      { Gdq, XS }, 0 },
10875   },
10876   {
10877     /* MOD_VEX_0FE7_PREFIX_2 */
10878     { "vmovntdq",       { Mx, XM }, 0 },
10879   },
10880   {
10881     /* MOD_VEX_0FF0_PREFIX_3 */
10882     { "vlddqu",         { XM, M }, 0 },
10883   },
10884   {
10885     /* MOD_VEX_0F381A_PREFIX_2 */
10886     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10887   },
10888   {
10889     /* MOD_VEX_0F382A_PREFIX_2 */
10890     { "vmovntdqa",      { XM, Mx }, 0 },
10891   },
10892   {
10893     /* MOD_VEX_0F382C_PREFIX_2 */
10894     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10895   },
10896   {
10897     /* MOD_VEX_0F382D_PREFIX_2 */
10898     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10899   },
10900   {
10901     /* MOD_VEX_0F382E_PREFIX_2 */
10902     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10903   },
10904   {
10905     /* MOD_VEX_0F382F_PREFIX_2 */
10906     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10907   },
10908   {
10909     /* MOD_VEX_0F385A_PREFIX_2 */
10910     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10911   },
10912   {
10913     /* MOD_VEX_0F388C_PREFIX_2 */
10914     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10915   },
10916   {
10917     /* MOD_VEX_0F388E_PREFIX_2 */
10918     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10919   },
10920   {
10921     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10922     { Bad_Opcode },
10923     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10924   },
10925   {
10926     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10927     { Bad_Opcode },
10928     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10929   },
10930   {
10931     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10932     { Bad_Opcode },
10933     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10934   },
10935   {
10936     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10937     { Bad_Opcode },
10938     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10939   },
10940   {
10941     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10942     { Bad_Opcode },
10943     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10944   },
10945   {
10946     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10947     { Bad_Opcode },
10948     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10949   },
10950   {
10951     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10952     { Bad_Opcode },
10953     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10954   },
10955   {
10956     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10957     { Bad_Opcode },
10958     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10959   },
10960
10961 #include "i386-dis-evex-mod.h"
10962 };
10963
10964 static const struct dis386 rm_table[][8] = {
10965   {
10966     /* RM_C6_REG_7 */
10967     { "xabort",         { Skip_MODRM, Ib }, 0 },
10968   },
10969   {
10970     /* RM_C7_REG_7 */
10971     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10972   },
10973   {
10974     /* RM_0F01_REG_0 */
10975     { "enclv",          { Skip_MODRM }, 0 },
10976     { "vmcall",         { Skip_MODRM }, 0 },
10977     { "vmlaunch",       { Skip_MODRM }, 0 },
10978     { "vmresume",       { Skip_MODRM }, 0 },
10979     { "vmxoff",         { Skip_MODRM }, 0 },
10980     { "pconfig",        { Skip_MODRM }, 0 },
10981   },
10982   {
10983     /* RM_0F01_REG_1 */
10984     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10985     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10986     { "clac",           { Skip_MODRM }, 0 },
10987     { "stac",           { Skip_MODRM }, 0 },
10988     { Bad_Opcode },
10989     { Bad_Opcode },
10990     { Bad_Opcode },
10991     { "encls",          { Skip_MODRM }, 0 },
10992   },
10993   {
10994     /* RM_0F01_REG_2 */
10995     { "xgetbv",         { Skip_MODRM }, 0 },
10996     { "xsetbv",         { Skip_MODRM }, 0 },
10997     { Bad_Opcode },
10998     { Bad_Opcode },
10999     { "vmfunc",         { Skip_MODRM }, 0 },
11000     { "xend",           { Skip_MODRM }, 0 },
11001     { "xtest",          { Skip_MODRM }, 0 },
11002     { "enclu",          { Skip_MODRM }, 0 },
11003   },
11004   {
11005     /* RM_0F01_REG_3 */
11006     { "vmrun",          { Skip_MODRM }, 0 },
11007     { "vmmcall",        { Skip_MODRM }, 0 },
11008     { "vmload",         { Skip_MODRM }, 0 },
11009     { "vmsave",         { Skip_MODRM }, 0 },
11010     { "stgi",           { Skip_MODRM }, 0 },
11011     { "clgi",           { Skip_MODRM }, 0 },
11012     { "skinit",         { Skip_MODRM }, 0 },
11013     { "invlpga",        { Skip_MODRM }, 0 },
11014   },
11015   {
11016     /* RM_0F01_REG_5_MOD_3 */
11017     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11018     { Bad_Opcode },
11019     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11020     { Bad_Opcode },
11021     { Bad_Opcode },
11022     { Bad_Opcode },
11023     { "rdpkru",         { Skip_MODRM }, 0 },
11024     { "wrpkru",         { Skip_MODRM }, 0 },
11025   },
11026   {
11027     /* RM_0F01_REG_7_MOD_3 */
11028     { "swapgs",         { Skip_MODRM }, 0  },
11029     { "rdtscp",         { Skip_MODRM }, 0  },
11030     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11031     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11032     { "clzero",         { Skip_MODRM }, 0  },
11033   },
11034   {
11035     /* RM_0F1E_P_1_MOD_3_REG_7 */
11036     { "nopQ",           { Ev }, 0 },
11037     { "nopQ",           { Ev }, 0 },
11038     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11039     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11040     { "nopQ",           { Ev }, 0 },
11041     { "nopQ",           { Ev }, 0 },
11042     { "nopQ",           { Ev }, 0 },
11043     { "nopQ",           { Ev }, 0 },
11044   },
11045   {
11046     /* RM_0FAE_REG_6_MOD_3 */
11047     { "mfence",         { Skip_MODRM }, 0 },
11048   },
11049   {
11050     /* RM_0FAE_REG_7_MOD_3 */
11051     { "sfence",         { Skip_MODRM }, 0 },
11052
11053   },
11054 };
11055
11056 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11057
11058 /* We use the high bit to indicate different name for the same
11059    prefix.  */
11060 #define REP_PREFIX      (0xf3 | 0x100)
11061 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11062 #define XRELEASE_PREFIX (0xf3 | 0x400)
11063 #define BND_PREFIX      (0xf2 | 0x400)
11064 #define NOTRACK_PREFIX  (0x3e | 0x100)
11065
11066 static int
11067 ckprefix (void)
11068 {
11069   int newrex, i, length;
11070   rex = 0;
11071   rex_ignored = 0;
11072   prefixes = 0;
11073   used_prefixes = 0;
11074   rex_used = 0;
11075   last_lock_prefix = -1;
11076   last_repz_prefix = -1;
11077   last_repnz_prefix = -1;
11078   last_data_prefix = -1;
11079   last_addr_prefix = -1;
11080   last_rex_prefix = -1;
11081   last_seg_prefix = -1;
11082   fwait_prefix = -1;
11083   active_seg_prefix = 0;
11084   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11085     all_prefixes[i] = 0;
11086   i = 0;
11087   length = 0;
11088   /* The maximum instruction length is 15bytes.  */
11089   while (length < MAX_CODE_LENGTH - 1)
11090     {
11091       FETCH_DATA (the_info, codep + 1);
11092       newrex = 0;
11093       switch (*codep)
11094         {
11095         /* REX prefixes family.  */
11096         case 0x40:
11097         case 0x41:
11098         case 0x42:
11099         case 0x43:
11100         case 0x44:
11101         case 0x45:
11102         case 0x46:
11103         case 0x47:
11104         case 0x48:
11105         case 0x49:
11106         case 0x4a:
11107         case 0x4b:
11108         case 0x4c:
11109         case 0x4d:
11110         case 0x4e:
11111         case 0x4f:
11112           if (address_mode == mode_64bit)
11113             newrex = *codep;
11114           else
11115             return 1;
11116           last_rex_prefix = i;
11117           break;
11118         case 0xf3:
11119           prefixes |= PREFIX_REPZ;
11120           last_repz_prefix = i;
11121           break;
11122         case 0xf2:
11123           prefixes |= PREFIX_REPNZ;
11124           last_repnz_prefix = i;
11125           break;
11126         case 0xf0:
11127           prefixes |= PREFIX_LOCK;
11128           last_lock_prefix = i;
11129           break;
11130         case 0x2e:
11131           prefixes |= PREFIX_CS;
11132           last_seg_prefix = i;
11133           active_seg_prefix = PREFIX_CS;
11134           break;
11135         case 0x36:
11136           prefixes |= PREFIX_SS;
11137           last_seg_prefix = i;
11138           active_seg_prefix = PREFIX_SS;
11139           break;
11140         case 0x3e:
11141           prefixes |= PREFIX_DS;
11142           last_seg_prefix = i;
11143           active_seg_prefix = PREFIX_DS;
11144           break;
11145         case 0x26:
11146           prefixes |= PREFIX_ES;
11147           last_seg_prefix = i;
11148           active_seg_prefix = PREFIX_ES;
11149           break;
11150         case 0x64:
11151           prefixes |= PREFIX_FS;
11152           last_seg_prefix = i;
11153           active_seg_prefix = PREFIX_FS;
11154           break;
11155         case 0x65:
11156           prefixes |= PREFIX_GS;
11157           last_seg_prefix = i;
11158           active_seg_prefix = PREFIX_GS;
11159           break;
11160         case 0x66:
11161           prefixes |= PREFIX_DATA;
11162           last_data_prefix = i;
11163           break;
11164         case 0x67:
11165           prefixes |= PREFIX_ADDR;
11166           last_addr_prefix = i;
11167           break;
11168         case FWAIT_OPCODE:
11169           /* fwait is really an instruction.  If there are prefixes
11170              before the fwait, they belong to the fwait, *not* to the
11171              following instruction.  */
11172           fwait_prefix = i;
11173           if (prefixes || rex)
11174             {
11175               prefixes |= PREFIX_FWAIT;
11176               codep++;
11177               /* This ensures that the previous REX prefixes are noticed
11178                  as unused prefixes, as in the return case below.  */
11179               rex_used = rex;
11180               return 1;
11181             }
11182           prefixes = PREFIX_FWAIT;
11183           break;
11184         default:
11185           return 1;
11186         }
11187       /* Rex is ignored when followed by another prefix.  */
11188       if (rex)
11189         {
11190           rex_used = rex;
11191           return 1;
11192         }
11193       if (*codep != FWAIT_OPCODE)
11194         all_prefixes[i++] = *codep;
11195       rex = newrex;
11196       codep++;
11197       length++;
11198     }
11199   return 0;
11200 }
11201
11202 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11203    prefix byte.  */
11204
11205 static const char *
11206 prefix_name (int pref, int sizeflag)
11207 {
11208   static const char *rexes [16] =
11209     {
11210       "rex",            /* 0x40 */
11211       "rex.B",          /* 0x41 */
11212       "rex.X",          /* 0x42 */
11213       "rex.XB",         /* 0x43 */
11214       "rex.R",          /* 0x44 */
11215       "rex.RB",         /* 0x45 */
11216       "rex.RX",         /* 0x46 */
11217       "rex.RXB",        /* 0x47 */
11218       "rex.W",          /* 0x48 */
11219       "rex.WB",         /* 0x49 */
11220       "rex.WX",         /* 0x4a */
11221       "rex.WXB",        /* 0x4b */
11222       "rex.WR",         /* 0x4c */
11223       "rex.WRB",        /* 0x4d */
11224       "rex.WRX",        /* 0x4e */
11225       "rex.WRXB",       /* 0x4f */
11226     };
11227
11228   switch (pref)
11229     {
11230     /* REX prefixes family.  */
11231     case 0x40:
11232     case 0x41:
11233     case 0x42:
11234     case 0x43:
11235     case 0x44:
11236     case 0x45:
11237     case 0x46:
11238     case 0x47:
11239     case 0x48:
11240     case 0x49:
11241     case 0x4a:
11242     case 0x4b:
11243     case 0x4c:
11244     case 0x4d:
11245     case 0x4e:
11246     case 0x4f:
11247       return rexes [pref - 0x40];
11248     case 0xf3:
11249       return "repz";
11250     case 0xf2:
11251       return "repnz";
11252     case 0xf0:
11253       return "lock";
11254     case 0x2e:
11255       return "cs";
11256     case 0x36:
11257       return "ss";
11258     case 0x3e:
11259       return "ds";
11260     case 0x26:
11261       return "es";
11262     case 0x64:
11263       return "fs";
11264     case 0x65:
11265       return "gs";
11266     case 0x66:
11267       return (sizeflag & DFLAG) ? "data16" : "data32";
11268     case 0x67:
11269       if (address_mode == mode_64bit)
11270         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11271       else
11272         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11273     case FWAIT_OPCODE:
11274       return "fwait";
11275     case REP_PREFIX:
11276       return "rep";
11277     case XACQUIRE_PREFIX:
11278       return "xacquire";
11279     case XRELEASE_PREFIX:
11280       return "xrelease";
11281     case BND_PREFIX:
11282       return "bnd";
11283     case NOTRACK_PREFIX:
11284       return "notrack";
11285     default:
11286       return NULL;
11287     }
11288 }
11289
11290 static char op_out[MAX_OPERANDS][100];
11291 static int op_ad, op_index[MAX_OPERANDS];
11292 static int two_source_ops;
11293 static bfd_vma op_address[MAX_OPERANDS];
11294 static bfd_vma op_riprel[MAX_OPERANDS];
11295 static bfd_vma start_pc;
11296
11297 /*
11298  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11299  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11300  *   section of the "Virtual 8086 Mode" chapter.)
11301  * 'pc' should be the address of this instruction, it will
11302  *   be used to print the target address if this is a relative jump or call
11303  * The function returns the length of this instruction in bytes.
11304  */
11305
11306 static char intel_syntax;
11307 static char intel_mnemonic = !SYSV386_COMPAT;
11308 static char open_char;
11309 static char close_char;
11310 static char separator_char;
11311 static char scale_char;
11312
11313 enum x86_64_isa
11314 {
11315   amd64 = 0,
11316   intel64
11317 };
11318
11319 static enum x86_64_isa isa64;
11320
11321 /* Here for backwards compatibility.  When gdb stops using
11322    print_insn_i386_att and print_insn_i386_intel these functions can
11323    disappear, and print_insn_i386 be merged into print_insn.  */
11324 int
11325 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11326 {
11327   intel_syntax = 0;
11328
11329   return print_insn (pc, info);
11330 }
11331
11332 int
11333 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11334 {
11335   intel_syntax = 1;
11336
11337   return print_insn (pc, info);
11338 }
11339
11340 int
11341 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11342 {
11343   intel_syntax = -1;
11344
11345   return print_insn (pc, info);
11346 }
11347
11348 void
11349 print_i386_disassembler_options (FILE *stream)
11350 {
11351   fprintf (stream, _("\n\
11352 The following i386/x86-64 specific disassembler options are supported for use\n\
11353 with the -M switch (multiple options should be separated by commas):\n"));
11354
11355   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11356   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11357   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11358   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11359   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11360   fprintf (stream, _("  att-mnemonic\n"
11361                      "              Display instruction in AT&T mnemonic\n"));
11362   fprintf (stream, _("  intel-mnemonic\n"
11363                      "              Display instruction in Intel mnemonic\n"));
11364   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11365   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11366   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11367   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11368   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11369   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11370   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11371   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11372 }
11373
11374 /* Bad opcode.  */
11375 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11376
11377 /* Get a pointer to struct dis386 with a valid name.  */
11378
11379 static const struct dis386 *
11380 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11381 {
11382   int vindex, vex_table_index;
11383
11384   if (dp->name != NULL)
11385     return dp;
11386
11387   switch (dp->op[0].bytemode)
11388     {
11389     case USE_REG_TABLE:
11390       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11391       break;
11392
11393     case USE_MOD_TABLE:
11394       vindex = modrm.mod == 0x3 ? 1 : 0;
11395       dp = &mod_table[dp->op[1].bytemode][vindex];
11396       break;
11397
11398     case USE_RM_TABLE:
11399       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11400       break;
11401
11402     case USE_PREFIX_TABLE:
11403       if (need_vex)
11404         {
11405           /* The prefix in VEX is implicit.  */
11406           switch (vex.prefix)
11407             {
11408             case 0:
11409               vindex = 0;
11410               break;
11411             case REPE_PREFIX_OPCODE:
11412               vindex = 1;
11413               break;
11414             case DATA_PREFIX_OPCODE:
11415               vindex = 2;
11416               break;
11417             case REPNE_PREFIX_OPCODE:
11418               vindex = 3;
11419               break;
11420             default:
11421               abort ();
11422               break;
11423             }
11424         }
11425       else
11426         {
11427           int last_prefix = -1;
11428           int prefix = 0;
11429           vindex = 0;
11430           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11431              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11432              last one wins.  */
11433           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11434             {
11435               if (last_repz_prefix > last_repnz_prefix)
11436                 {
11437                   vindex = 1;
11438                   prefix = PREFIX_REPZ;
11439                   last_prefix = last_repz_prefix;
11440                 }
11441               else
11442                 {
11443                   vindex = 3;
11444                   prefix = PREFIX_REPNZ;
11445                   last_prefix = last_repnz_prefix;
11446                 }
11447
11448               /* Check if prefix should be ignored.  */
11449               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11450                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11451                    & prefix) != 0)
11452                 vindex = 0;
11453             }
11454
11455           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11456             {
11457               vindex = 2;
11458               prefix = PREFIX_DATA;
11459               last_prefix = last_data_prefix;
11460             }
11461
11462           if (vindex != 0)
11463             {
11464               used_prefixes |= prefix;
11465               all_prefixes[last_prefix] = 0;
11466             }
11467         }
11468       dp = &prefix_table[dp->op[1].bytemode][vindex];
11469       break;
11470
11471     case USE_X86_64_TABLE:
11472       vindex = address_mode == mode_64bit ? 1 : 0;
11473       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11474       break;
11475
11476     case USE_3BYTE_TABLE:
11477       FETCH_DATA (info, codep + 2);
11478       vindex = *codep++;
11479       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11480       end_codep = codep;
11481       modrm.mod = (*codep >> 6) & 3;
11482       modrm.reg = (*codep >> 3) & 7;
11483       modrm.rm = *codep & 7;
11484       break;
11485
11486     case USE_VEX_LEN_TABLE:
11487       if (!need_vex)
11488         abort ();
11489
11490       switch (vex.length)
11491         {
11492         case 128:
11493           vindex = 0;
11494           break;
11495         case 256:
11496           vindex = 1;
11497           break;
11498         default:
11499           abort ();
11500           break;
11501         }
11502
11503       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11504       break;
11505
11506     case USE_EVEX_LEN_TABLE:
11507       if (!vex.evex)
11508         abort ();
11509
11510       switch (vex.length)
11511         {
11512         case 128:
11513           vindex = 0;
11514           break;
11515         case 256:
11516           vindex = 1;
11517           break;
11518         case 512:
11519           vindex = 2;
11520           break;
11521         default:
11522           abort ();
11523           break;
11524         }
11525
11526       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11527       break;
11528
11529     case USE_XOP_8F_TABLE:
11530       FETCH_DATA (info, codep + 3);
11531       /* All bits in the REX prefix are ignored.  */
11532       rex_ignored = rex;
11533       rex = ~(*codep >> 5) & 0x7;
11534
11535       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11536       switch ((*codep & 0x1f))
11537         {
11538         default:
11539           dp = &bad_opcode;
11540           return dp;
11541         case 0x8:
11542           vex_table_index = XOP_08;
11543           break;
11544         case 0x9:
11545           vex_table_index = XOP_09;
11546           break;
11547         case 0xa:
11548           vex_table_index = XOP_0A;
11549           break;
11550         }
11551       codep++;
11552       vex.w = *codep & 0x80;
11553       if (vex.w && address_mode == mode_64bit)
11554         rex |= REX_W;
11555
11556       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11557       if (address_mode != mode_64bit)
11558         {
11559           /* In 16/32-bit mode REX_B is silently ignored.  */
11560           rex &= ~REX_B;
11561         }
11562
11563       vex.length = (*codep & 0x4) ? 256 : 128;
11564       switch ((*codep & 0x3))
11565         {
11566         case 0:
11567           break;
11568         case 1:
11569           vex.prefix = DATA_PREFIX_OPCODE;
11570           break;
11571         case 2:
11572           vex.prefix = REPE_PREFIX_OPCODE;
11573           break;
11574         case 3:
11575           vex.prefix = REPNE_PREFIX_OPCODE;
11576           break;
11577         }
11578       need_vex = 1;
11579       need_vex_reg = 1;
11580       codep++;
11581       vindex = *codep++;
11582       dp = &xop_table[vex_table_index][vindex];
11583
11584       end_codep = codep;
11585       FETCH_DATA (info, codep + 1);
11586       modrm.mod = (*codep >> 6) & 3;
11587       modrm.reg = (*codep >> 3) & 7;
11588       modrm.rm = *codep & 7;
11589       break;
11590
11591     case USE_VEX_C4_TABLE:
11592       /* VEX prefix.  */
11593       FETCH_DATA (info, codep + 3);
11594       /* All bits in the REX prefix are ignored.  */
11595       rex_ignored = rex;
11596       rex = ~(*codep >> 5) & 0x7;
11597       switch ((*codep & 0x1f))
11598         {
11599         default:
11600           dp = &bad_opcode;
11601           return dp;
11602         case 0x1:
11603           vex_table_index = VEX_0F;
11604           break;
11605         case 0x2:
11606           vex_table_index = VEX_0F38;
11607           break;
11608         case 0x3:
11609           vex_table_index = VEX_0F3A;
11610           break;
11611         }
11612       codep++;
11613       vex.w = *codep & 0x80;
11614       if (address_mode == mode_64bit)
11615         {
11616           if (vex.w)
11617             rex |= REX_W;
11618         }
11619       else
11620         {
11621           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11622              is ignored, other REX bits are 0 and the highest bit in
11623              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11624           rex = 0;
11625         }
11626       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11627       vex.length = (*codep & 0x4) ? 256 : 128;
11628       switch ((*codep & 0x3))
11629         {
11630         case 0:
11631           break;
11632         case 1:
11633           vex.prefix = DATA_PREFIX_OPCODE;
11634           break;
11635         case 2:
11636           vex.prefix = REPE_PREFIX_OPCODE;
11637           break;
11638         case 3:
11639           vex.prefix = REPNE_PREFIX_OPCODE;
11640           break;
11641         }
11642       need_vex = 1;
11643       need_vex_reg = 1;
11644       codep++;
11645       vindex = *codep++;
11646       dp = &vex_table[vex_table_index][vindex];
11647       end_codep = codep;
11648       /* There is no MODRM byte for VEX0F 77.  */
11649       if (vex_table_index != VEX_0F || vindex != 0x77)
11650         {
11651           FETCH_DATA (info, codep + 1);
11652           modrm.mod = (*codep >> 6) & 3;
11653           modrm.reg = (*codep >> 3) & 7;
11654           modrm.rm = *codep & 7;
11655         }
11656       break;
11657
11658     case USE_VEX_C5_TABLE:
11659       /* VEX prefix.  */
11660       FETCH_DATA (info, codep + 2);
11661       /* All bits in the REX prefix are ignored.  */
11662       rex_ignored = rex;
11663       rex = (*codep & 0x80) ? 0 : REX_R;
11664
11665       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11666          VEX.vvvv is 1.  */
11667       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11668       vex.length = (*codep & 0x4) ? 256 : 128;
11669       switch ((*codep & 0x3))
11670         {
11671         case 0:
11672           break;
11673         case 1:
11674           vex.prefix = DATA_PREFIX_OPCODE;
11675           break;
11676         case 2:
11677           vex.prefix = REPE_PREFIX_OPCODE;
11678           break;
11679         case 3:
11680           vex.prefix = REPNE_PREFIX_OPCODE;
11681           break;
11682         }
11683       need_vex = 1;
11684       need_vex_reg = 1;
11685       codep++;
11686       vindex = *codep++;
11687       dp = &vex_table[dp->op[1].bytemode][vindex];
11688       end_codep = codep;
11689       /* There is no MODRM byte for VEX 77.  */
11690       if (vindex != 0x77)
11691         {
11692           FETCH_DATA (info, codep + 1);
11693           modrm.mod = (*codep >> 6) & 3;
11694           modrm.reg = (*codep >> 3) & 7;
11695           modrm.rm = *codep & 7;
11696         }
11697       break;
11698
11699     case USE_VEX_W_TABLE:
11700       if (!need_vex)
11701         abort ();
11702
11703       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11704       break;
11705
11706     case USE_EVEX_TABLE:
11707       two_source_ops = 0;
11708       /* EVEX prefix.  */
11709       vex.evex = 1;
11710       FETCH_DATA (info, codep + 4);
11711       /* All bits in the REX prefix are ignored.  */
11712       rex_ignored = rex;
11713       /* The first byte after 0x62.  */
11714       rex = ~(*codep >> 5) & 0x7;
11715       vex.r = *codep & 0x10;
11716       switch ((*codep & 0xf))
11717         {
11718         default:
11719           return &bad_opcode;
11720         case 0x1:
11721           vex_table_index = EVEX_0F;
11722           break;
11723         case 0x2:
11724           vex_table_index = EVEX_0F38;
11725           break;
11726         case 0x3:
11727           vex_table_index = EVEX_0F3A;
11728           break;
11729         }
11730
11731       /* The second byte after 0x62.  */
11732       codep++;
11733       vex.w = *codep & 0x80;
11734       if (vex.w && address_mode == mode_64bit)
11735         rex |= REX_W;
11736
11737       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11738
11739       /* The U bit.  */
11740       if (!(*codep & 0x4))
11741         return &bad_opcode;
11742
11743       switch ((*codep & 0x3))
11744         {
11745         case 0:
11746           break;
11747         case 1:
11748           vex.prefix = DATA_PREFIX_OPCODE;
11749           break;
11750         case 2:
11751           vex.prefix = REPE_PREFIX_OPCODE;
11752           break;
11753         case 3:
11754           vex.prefix = REPNE_PREFIX_OPCODE;
11755           break;
11756         }
11757
11758       /* The third byte after 0x62.  */
11759       codep++;
11760
11761       /* Remember the static rounding bits.  */
11762       vex.ll = (*codep >> 5) & 3;
11763       vex.b = (*codep & 0x10) != 0;
11764
11765       vex.v = *codep & 0x8;
11766       vex.mask_register_specifier = *codep & 0x7;
11767       vex.zeroing = *codep & 0x80;
11768
11769       if (address_mode != mode_64bit)
11770         {
11771           /* In 16/32-bit mode silently ignore following bits.  */
11772           rex &= ~REX_B;
11773           vex.r = 1;
11774           vex.v = 1;
11775         }
11776
11777       need_vex = 1;
11778       need_vex_reg = 1;
11779       codep++;
11780       vindex = *codep++;
11781       dp = &evex_table[vex_table_index][vindex];
11782       end_codep = codep;
11783       FETCH_DATA (info, codep + 1);
11784       modrm.mod = (*codep >> 6) & 3;
11785       modrm.reg = (*codep >> 3) & 7;
11786       modrm.rm = *codep & 7;
11787
11788       /* Set vector length.  */
11789       if (modrm.mod == 3 && vex.b)
11790         vex.length = 512;
11791       else
11792         {
11793           switch (vex.ll)
11794             {
11795             case 0x0:
11796               vex.length = 128;
11797               break;
11798             case 0x1:
11799               vex.length = 256;
11800               break;
11801             case 0x2:
11802               vex.length = 512;
11803               break;
11804             default:
11805               return &bad_opcode;
11806             }
11807         }
11808       break;
11809
11810     case 0:
11811       dp = &bad_opcode;
11812       break;
11813
11814     default:
11815       abort ();
11816     }
11817
11818   if (dp->name != NULL)
11819     return dp;
11820   else
11821     return get_valid_dis386 (dp, info);
11822 }
11823
11824 static void
11825 get_sib (disassemble_info *info, int sizeflag)
11826 {
11827   /* If modrm.mod == 3, operand must be register.  */
11828   if (need_modrm
11829       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11830       && modrm.mod != 3
11831       && modrm.rm == 4)
11832     {
11833       FETCH_DATA (info, codep + 2);
11834       sib.index = (codep [1] >> 3) & 7;
11835       sib.scale = (codep [1] >> 6) & 3;
11836       sib.base = codep [1] & 7;
11837     }
11838 }
11839
11840 static int
11841 print_insn (bfd_vma pc, disassemble_info *info)
11842 {
11843   const struct dis386 *dp;
11844   int i;
11845   char *op_txt[MAX_OPERANDS];
11846   int needcomma;
11847   int sizeflag, orig_sizeflag;
11848   const char *p;
11849   struct dis_private priv;
11850   int prefix_length;
11851
11852   priv.orig_sizeflag = AFLAG | DFLAG;
11853   if ((info->mach & bfd_mach_i386_i386) != 0)
11854     address_mode = mode_32bit;
11855   else if (info->mach == bfd_mach_i386_i8086)
11856     {
11857       address_mode = mode_16bit;
11858       priv.orig_sizeflag = 0;
11859     }
11860   else
11861     address_mode = mode_64bit;
11862
11863   if (intel_syntax == (char) -1)
11864     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11865
11866   for (p = info->disassembler_options; p != NULL; )
11867     {
11868       if (CONST_STRNEQ (p, "amd64"))
11869         isa64 = amd64;
11870       else if (CONST_STRNEQ (p, "intel64"))
11871         isa64 = intel64;
11872       else if (CONST_STRNEQ (p, "x86-64"))
11873         {
11874           address_mode = mode_64bit;
11875           priv.orig_sizeflag = AFLAG | DFLAG;
11876         }
11877       else if (CONST_STRNEQ (p, "i386"))
11878         {
11879           address_mode = mode_32bit;
11880           priv.orig_sizeflag = AFLAG | DFLAG;
11881         }
11882       else if (CONST_STRNEQ (p, "i8086"))
11883         {
11884           address_mode = mode_16bit;
11885           priv.orig_sizeflag = 0;
11886         }
11887       else if (CONST_STRNEQ (p, "intel"))
11888         {
11889           intel_syntax = 1;
11890           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11891             intel_mnemonic = 1;
11892         }
11893       else if (CONST_STRNEQ (p, "att"))
11894         {
11895           intel_syntax = 0;
11896           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11897             intel_mnemonic = 0;
11898         }
11899       else if (CONST_STRNEQ (p, "addr"))
11900         {
11901           if (address_mode == mode_64bit)
11902             {
11903               if (p[4] == '3' && p[5] == '2')
11904                 priv.orig_sizeflag &= ~AFLAG;
11905               else if (p[4] == '6' && p[5] == '4')
11906                 priv.orig_sizeflag |= AFLAG;
11907             }
11908           else
11909             {
11910               if (p[4] == '1' && p[5] == '6')
11911                 priv.orig_sizeflag &= ~AFLAG;
11912               else if (p[4] == '3' && p[5] == '2')
11913                 priv.orig_sizeflag |= AFLAG;
11914             }
11915         }
11916       else if (CONST_STRNEQ (p, "data"))
11917         {
11918           if (p[4] == '1' && p[5] == '6')
11919             priv.orig_sizeflag &= ~DFLAG;
11920           else if (p[4] == '3' && p[5] == '2')
11921             priv.orig_sizeflag |= DFLAG;
11922         }
11923       else if (CONST_STRNEQ (p, "suffix"))
11924         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11925
11926       p = strchr (p, ',');
11927       if (p != NULL)
11928         p++;
11929     }
11930
11931   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11932     {
11933       (*info->fprintf_func) (info->stream,
11934                              _("64-bit address is disabled"));
11935       return -1;
11936     }
11937
11938   if (intel_syntax)
11939     {
11940       names64 = intel_names64;
11941       names32 = intel_names32;
11942       names16 = intel_names16;
11943       names8 = intel_names8;
11944       names8rex = intel_names8rex;
11945       names_seg = intel_names_seg;
11946       names_mm = intel_names_mm;
11947       names_bnd = intel_names_bnd;
11948       names_xmm = intel_names_xmm;
11949       names_ymm = intel_names_ymm;
11950       names_zmm = intel_names_zmm;
11951       index64 = intel_index64;
11952       index32 = intel_index32;
11953       names_mask = intel_names_mask;
11954       index16 = intel_index16;
11955       open_char = '[';
11956       close_char = ']';
11957       separator_char = '+';
11958       scale_char = '*';
11959     }
11960   else
11961     {
11962       names64 = att_names64;
11963       names32 = att_names32;
11964       names16 = att_names16;
11965       names8 = att_names8;
11966       names8rex = att_names8rex;
11967       names_seg = att_names_seg;
11968       names_mm = att_names_mm;
11969       names_bnd = att_names_bnd;
11970       names_xmm = att_names_xmm;
11971       names_ymm = att_names_ymm;
11972       names_zmm = att_names_zmm;
11973       index64 = att_index64;
11974       index32 = att_index32;
11975       names_mask = att_names_mask;
11976       index16 = att_index16;
11977       open_char = '(';
11978       close_char =  ')';
11979       separator_char = ',';
11980       scale_char = ',';
11981     }
11982
11983   /* The output looks better if we put 7 bytes on a line, since that
11984      puts most long word instructions on a single line.  Use 8 bytes
11985      for Intel L1OM.  */
11986   if ((info->mach & bfd_mach_l1om) != 0)
11987     info->bytes_per_line = 8;
11988   else
11989     info->bytes_per_line = 7;
11990
11991   info->private_data = &priv;
11992   priv.max_fetched = priv.the_buffer;
11993   priv.insn_start = pc;
11994
11995   obuf[0] = 0;
11996   for (i = 0; i < MAX_OPERANDS; ++i)
11997     {
11998       op_out[i][0] = 0;
11999       op_index[i] = -1;
12000     }
12001
12002   the_info = info;
12003   start_pc = pc;
12004   start_codep = priv.the_buffer;
12005   codep = priv.the_buffer;
12006
12007   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12008     {
12009       const char *name;
12010
12011       /* Getting here means we tried for data but didn't get it.  That
12012          means we have an incomplete instruction of some sort.  Just
12013          print the first byte as a prefix or a .byte pseudo-op.  */
12014       if (codep > priv.the_buffer)
12015         {
12016           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12017           if (name != NULL)
12018             (*info->fprintf_func) (info->stream, "%s", name);
12019           else
12020             {
12021               /* Just print the first byte as a .byte instruction.  */
12022               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12023                                      (unsigned int) priv.the_buffer[0]);
12024             }
12025
12026           return 1;
12027         }
12028
12029       return -1;
12030     }
12031
12032   obufp = obuf;
12033   sizeflag = priv.orig_sizeflag;
12034
12035   if (!ckprefix () || rex_used)
12036     {
12037       /* Too many prefixes or unused REX prefixes.  */
12038       for (i = 0;
12039            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12040            i++)
12041         (*info->fprintf_func) (info->stream, "%s%s",
12042                                i == 0 ? "" : " ",
12043                                prefix_name (all_prefixes[i], sizeflag));
12044       return i;
12045     }
12046
12047   insn_codep = codep;
12048
12049   FETCH_DATA (info, codep + 1);
12050   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12051
12052   if (((prefixes & PREFIX_FWAIT)
12053        && ((*codep < 0xd8) || (*codep > 0xdf))))
12054     {
12055       /* Handle prefixes before fwait.  */
12056       for (i = 0; i < fwait_prefix && all_prefixes[i];
12057            i++)
12058         (*info->fprintf_func) (info->stream, "%s ",
12059                                prefix_name (all_prefixes[i], sizeflag));
12060       (*info->fprintf_func) (info->stream, "fwait");
12061       return i + 1;
12062     }
12063
12064   if (*codep == 0x0f)
12065     {
12066       unsigned char threebyte;
12067
12068       codep++;
12069       FETCH_DATA (info, codep + 1);
12070       threebyte = *codep;
12071       dp = &dis386_twobyte[threebyte];
12072       need_modrm = twobyte_has_modrm[*codep];
12073       codep++;
12074     }
12075   else
12076     {
12077       dp = &dis386[*codep];
12078       need_modrm = onebyte_has_modrm[*codep];
12079       codep++;
12080     }
12081
12082   /* Save sizeflag for printing the extra prefixes later before updating
12083      it for mnemonic and operand processing.  The prefix names depend
12084      only on the address mode.  */
12085   orig_sizeflag = sizeflag;
12086   if (prefixes & PREFIX_ADDR)
12087     sizeflag ^= AFLAG;
12088   if ((prefixes & PREFIX_DATA))
12089     sizeflag ^= DFLAG;
12090
12091   end_codep = codep;
12092   if (need_modrm)
12093     {
12094       FETCH_DATA (info, codep + 1);
12095       modrm.mod = (*codep >> 6) & 3;
12096       modrm.reg = (*codep >> 3) & 7;
12097       modrm.rm = *codep & 7;
12098     }
12099
12100   need_vex = 0;
12101   need_vex_reg = 0;
12102   vex_w_done = 0;
12103   memset (&vex, 0, sizeof (vex));
12104
12105   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12106     {
12107       get_sib (info, sizeflag);
12108       dofloat (sizeflag);
12109     }
12110   else
12111     {
12112       dp = get_valid_dis386 (dp, info);
12113       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12114         {
12115           get_sib (info, sizeflag);
12116           for (i = 0; i < MAX_OPERANDS; ++i)
12117             {
12118               obufp = op_out[i];
12119               op_ad = MAX_OPERANDS - 1 - i;
12120               if (dp->op[i].rtn)
12121                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12122               /* For EVEX instruction after the last operand masking
12123                  should be printed.  */
12124               if (i == 0 && vex.evex)
12125                 {
12126                   /* Don't print {%k0}.  */
12127                   if (vex.mask_register_specifier)
12128                     {
12129                       oappend ("{");
12130                       oappend (names_mask[vex.mask_register_specifier]);
12131                       oappend ("}");
12132                     }
12133                   if (vex.zeroing)
12134                     oappend ("{z}");
12135                 }
12136             }
12137         }
12138     }
12139
12140   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12141      are all 0s in inverted form.  */
12142   if (need_vex && vex.register_specifier != 0)
12143     {
12144       (*info->fprintf_func) (info->stream, "(bad)");
12145       return end_codep - priv.the_buffer;
12146     }
12147
12148   /* Check if the REX prefix is used.  */
12149   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12150     all_prefixes[last_rex_prefix] = 0;
12151
12152   /* Check if the SEG prefix is used.  */
12153   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12154                    | PREFIX_FS | PREFIX_GS)) != 0
12155       && (used_prefixes & active_seg_prefix) != 0)
12156     all_prefixes[last_seg_prefix] = 0;
12157
12158   /* Check if the ADDR prefix is used.  */
12159   if ((prefixes & PREFIX_ADDR) != 0
12160       && (used_prefixes & PREFIX_ADDR) != 0)
12161     all_prefixes[last_addr_prefix] = 0;
12162
12163   /* Check if the DATA prefix is used.  */
12164   if ((prefixes & PREFIX_DATA) != 0
12165       && (used_prefixes & PREFIX_DATA) != 0)
12166     all_prefixes[last_data_prefix] = 0;
12167
12168   /* Print the extra prefixes.  */
12169   prefix_length = 0;
12170   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12171     if (all_prefixes[i])
12172       {
12173         const char *name;
12174         name = prefix_name (all_prefixes[i], orig_sizeflag);
12175         if (name == NULL)
12176           abort ();
12177         prefix_length += strlen (name) + 1;
12178         (*info->fprintf_func) (info->stream, "%s ", name);
12179       }
12180
12181   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12182      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12183      used by putop and MMX/SSE operand and may be overriden by the
12184      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12185      separately.  */
12186   if (dp->prefix_requirement == PREFIX_OPCODE
12187       && dp != &bad_opcode
12188       && (((prefixes
12189             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12190            && (used_prefixes
12191                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12192           || ((((prefixes
12193                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12194                 == PREFIX_DATA)
12195                && (used_prefixes & PREFIX_DATA) == 0))))
12196     {
12197       (*info->fprintf_func) (info->stream, "(bad)");
12198       return end_codep - priv.the_buffer;
12199     }
12200
12201   /* Check maximum code length.  */
12202   if ((codep - start_codep) > MAX_CODE_LENGTH)
12203     {
12204       (*info->fprintf_func) (info->stream, "(bad)");
12205       return MAX_CODE_LENGTH;
12206     }
12207
12208   obufp = mnemonicendp;
12209   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12210     oappend (" ");
12211   oappend (" ");
12212   (*info->fprintf_func) (info->stream, "%s", obuf);
12213
12214   /* The enter and bound instructions are printed with operands in the same
12215      order as the intel book; everything else is printed in reverse order.  */
12216   if (intel_syntax || two_source_ops)
12217     {
12218       bfd_vma riprel;
12219
12220       for (i = 0; i < MAX_OPERANDS; ++i)
12221         op_txt[i] = op_out[i];
12222
12223       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12224           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12225         {
12226           op_txt[2] = op_out[3];
12227           op_txt[3] = op_out[2];
12228         }
12229
12230       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12231         {
12232           op_ad = op_index[i];
12233           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12234           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12235           riprel = op_riprel[i];
12236           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12237           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12238         }
12239     }
12240   else
12241     {
12242       for (i = 0; i < MAX_OPERANDS; ++i)
12243         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12244     }
12245
12246   needcomma = 0;
12247   for (i = 0; i < MAX_OPERANDS; ++i)
12248     if (*op_txt[i])
12249       {
12250         if (needcomma)
12251           (*info->fprintf_func) (info->stream, ",");
12252         if (op_index[i] != -1 && !op_riprel[i])
12253           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12254         else
12255           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12256         needcomma = 1;
12257       }
12258
12259   for (i = 0; i < MAX_OPERANDS; i++)
12260     if (op_index[i] != -1 && op_riprel[i])
12261       {
12262         (*info->fprintf_func) (info->stream, "        # ");
12263         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12264                                                 + op_address[op_index[i]]), info);
12265         break;
12266       }
12267   return codep - priv.the_buffer;
12268 }
12269
12270 static const char *float_mem[] = {
12271   /* d8 */
12272   "fadd{s|}",
12273   "fmul{s|}",
12274   "fcom{s|}",
12275   "fcomp{s|}",
12276   "fsub{s|}",
12277   "fsubr{s|}",
12278   "fdiv{s|}",
12279   "fdivr{s|}",
12280   /* d9 */
12281   "fld{s|}",
12282   "(bad)",
12283   "fst{s|}",
12284   "fstp{s|}",
12285   "fldenvIC",
12286   "fldcw",
12287   "fNstenvIC",
12288   "fNstcw",
12289   /* da */
12290   "fiadd{l|}",
12291   "fimul{l|}",
12292   "ficom{l|}",
12293   "ficomp{l|}",
12294   "fisub{l|}",
12295   "fisubr{l|}",
12296   "fidiv{l|}",
12297   "fidivr{l|}",
12298   /* db */
12299   "fild{l|}",
12300   "fisttp{l|}",
12301   "fist{l|}",
12302   "fistp{l|}",
12303   "(bad)",
12304   "fld{t||t|}",
12305   "(bad)",
12306   "fstp{t||t|}",
12307   /* dc */
12308   "fadd{l|}",
12309   "fmul{l|}",
12310   "fcom{l|}",
12311   "fcomp{l|}",
12312   "fsub{l|}",
12313   "fsubr{l|}",
12314   "fdiv{l|}",
12315   "fdivr{l|}",
12316   /* dd */
12317   "fld{l|}",
12318   "fisttp{ll|}",
12319   "fst{l||}",
12320   "fstp{l|}",
12321   "frstorIC",
12322   "(bad)",
12323   "fNsaveIC",
12324   "fNstsw",
12325   /* de */
12326   "fiadd{s|}",
12327   "fimul{s|}",
12328   "ficom{s|}",
12329   "ficomp{s|}",
12330   "fisub{s|}",
12331   "fisubr{s|}",
12332   "fidiv{s|}",
12333   "fidivr{s|}",
12334   /* df */
12335   "fild{s|}",
12336   "fisttp{s|}",
12337   "fist{s|}",
12338   "fistp{s|}",
12339   "fbld",
12340   "fild{ll|}",
12341   "fbstp",
12342   "fistp{ll|}",
12343 };
12344
12345 static const unsigned char float_mem_mode[] = {
12346   /* d8 */
12347   d_mode,
12348   d_mode,
12349   d_mode,
12350   d_mode,
12351   d_mode,
12352   d_mode,
12353   d_mode,
12354   d_mode,
12355   /* d9 */
12356   d_mode,
12357   0,
12358   d_mode,
12359   d_mode,
12360   0,
12361   w_mode,
12362   0,
12363   w_mode,
12364   /* da */
12365   d_mode,
12366   d_mode,
12367   d_mode,
12368   d_mode,
12369   d_mode,
12370   d_mode,
12371   d_mode,
12372   d_mode,
12373   /* db */
12374   d_mode,
12375   d_mode,
12376   d_mode,
12377   d_mode,
12378   0,
12379   t_mode,
12380   0,
12381   t_mode,
12382   /* dc */
12383   q_mode,
12384   q_mode,
12385   q_mode,
12386   q_mode,
12387   q_mode,
12388   q_mode,
12389   q_mode,
12390   q_mode,
12391   /* dd */
12392   q_mode,
12393   q_mode,
12394   q_mode,
12395   q_mode,
12396   0,
12397   0,
12398   0,
12399   w_mode,
12400   /* de */
12401   w_mode,
12402   w_mode,
12403   w_mode,
12404   w_mode,
12405   w_mode,
12406   w_mode,
12407   w_mode,
12408   w_mode,
12409   /* df */
12410   w_mode,
12411   w_mode,
12412   w_mode,
12413   w_mode,
12414   t_mode,
12415   q_mode,
12416   t_mode,
12417   q_mode
12418 };
12419
12420 #define ST { OP_ST, 0 }
12421 #define STi { OP_STi, 0 }
12422
12423 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12424 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12425 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12426 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12427 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12428 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12429 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12430 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12431 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12432
12433 static const struct dis386 float_reg[][8] = {
12434   /* d8 */
12435   {
12436     { "fadd",   { ST, STi }, 0 },
12437     { "fmul",   { ST, STi }, 0 },
12438     { "fcom",   { STi }, 0 },
12439     { "fcomp",  { STi }, 0 },
12440     { "fsub",   { ST, STi }, 0 },
12441     { "fsubr",  { ST, STi }, 0 },
12442     { "fdiv",   { ST, STi }, 0 },
12443     { "fdivr",  { ST, STi }, 0 },
12444   },
12445   /* d9 */
12446   {
12447     { "fld",    { STi }, 0 },
12448     { "fxch",   { STi }, 0 },
12449     { FGRPd9_2 },
12450     { Bad_Opcode },
12451     { FGRPd9_4 },
12452     { FGRPd9_5 },
12453     { FGRPd9_6 },
12454     { FGRPd9_7 },
12455   },
12456   /* da */
12457   {
12458     { "fcmovb", { ST, STi }, 0 },
12459     { "fcmove", { ST, STi }, 0 },
12460     { "fcmovbe",{ ST, STi }, 0 },
12461     { "fcmovu", { ST, STi }, 0 },
12462     { Bad_Opcode },
12463     { FGRPda_5 },
12464     { Bad_Opcode },
12465     { Bad_Opcode },
12466   },
12467   /* db */
12468   {
12469     { "fcmovnb",{ ST, STi }, 0 },
12470     { "fcmovne",{ ST, STi }, 0 },
12471     { "fcmovnbe",{ ST, STi }, 0 },
12472     { "fcmovnu",{ ST, STi }, 0 },
12473     { FGRPdb_4 },
12474     { "fucomi", { ST, STi }, 0 },
12475     { "fcomi",  { ST, STi }, 0 },
12476     { Bad_Opcode },
12477   },
12478   /* dc */
12479   {
12480     { "fadd",   { STi, ST }, 0 },
12481     { "fmul",   { STi, ST }, 0 },
12482     { Bad_Opcode },
12483     { Bad_Opcode },
12484     { "fsub{!M|r}",     { STi, ST }, 0 },
12485     { "fsub{M|}",       { STi, ST }, 0 },
12486     { "fdiv{!M|r}",     { STi, ST }, 0 },
12487     { "fdiv{M|}",       { STi, ST }, 0 },
12488   },
12489   /* dd */
12490   {
12491     { "ffree",  { STi }, 0 },
12492     { Bad_Opcode },
12493     { "fst",    { STi }, 0 },
12494     { "fstp",   { STi }, 0 },
12495     { "fucom",  { STi }, 0 },
12496     { "fucomp", { STi }, 0 },
12497     { Bad_Opcode },
12498     { Bad_Opcode },
12499   },
12500   /* de */
12501   {
12502     { "faddp",  { STi, ST }, 0 },
12503     { "fmulp",  { STi, ST }, 0 },
12504     { Bad_Opcode },
12505     { FGRPde_3 },
12506     { "fsub{!M|r}p",    { STi, ST }, 0 },
12507     { "fsub{M|}p",      { STi, ST }, 0 },
12508     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12509     { "fdiv{M|}p",      { STi, ST }, 0 },
12510   },
12511   /* df */
12512   {
12513     { "ffreep", { STi }, 0 },
12514     { Bad_Opcode },
12515     { Bad_Opcode },
12516     { Bad_Opcode },
12517     { FGRPdf_4 },
12518     { "fucomip", { ST, STi }, 0 },
12519     { "fcomip", { ST, STi }, 0 },
12520     { Bad_Opcode },
12521   },
12522 };
12523
12524 static char *fgrps[][8] = {
12525   /* Bad opcode 0 */
12526   {
12527     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12528   },
12529
12530   /* d9_2  1 */
12531   {
12532     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12533   },
12534
12535   /* d9_4  2 */
12536   {
12537     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12538   },
12539
12540   /* d9_5  3 */
12541   {
12542     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12543   },
12544
12545   /* d9_6  4 */
12546   {
12547     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12548   },
12549
12550   /* d9_7  5 */
12551   {
12552     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12553   },
12554
12555   /* da_5  6 */
12556   {
12557     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12558   },
12559
12560   /* db_4  7 */
12561   {
12562     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12563     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12564   },
12565
12566   /* de_3  8 */
12567   {
12568     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12569   },
12570
12571   /* df_4  9 */
12572   {
12573     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12574   },
12575 };
12576
12577 static void
12578 swap_operand (void)
12579 {
12580   mnemonicendp[0] = '.';
12581   mnemonicendp[1] = 's';
12582   mnemonicendp += 2;
12583 }
12584
12585 static void
12586 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12587                int sizeflag ATTRIBUTE_UNUSED)
12588 {
12589   /* Skip mod/rm byte.  */
12590   MODRM_CHECK;
12591   codep++;
12592 }
12593
12594 static void
12595 dofloat (int sizeflag)
12596 {
12597   const struct dis386 *dp;
12598   unsigned char floatop;
12599
12600   floatop = codep[-1];
12601
12602   if (modrm.mod != 3)
12603     {
12604       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12605
12606       putop (float_mem[fp_indx], sizeflag);
12607       obufp = op_out[0];
12608       op_ad = 2;
12609       OP_E (float_mem_mode[fp_indx], sizeflag);
12610       return;
12611     }
12612   /* Skip mod/rm byte.  */
12613   MODRM_CHECK;
12614   codep++;
12615
12616   dp = &float_reg[floatop - 0xd8][modrm.reg];
12617   if (dp->name == NULL)
12618     {
12619       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12620
12621       /* Instruction fnstsw is only one with strange arg.  */
12622       if (floatop == 0xdf && codep[-1] == 0xe0)
12623         strcpy (op_out[0], names16[0]);
12624     }
12625   else
12626     {
12627       putop (dp->name, sizeflag);
12628
12629       obufp = op_out[0];
12630       op_ad = 2;
12631       if (dp->op[0].rtn)
12632         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12633
12634       obufp = op_out[1];
12635       op_ad = 1;
12636       if (dp->op[1].rtn)
12637         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12638     }
12639 }
12640
12641 /* Like oappend (below), but S is a string starting with '%'.
12642    In Intel syntax, the '%' is elided.  */
12643 static void
12644 oappend_maybe_intel (const char *s)
12645 {
12646   oappend (s + intel_syntax);
12647 }
12648
12649 static void
12650 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12651 {
12652   oappend_maybe_intel ("%st");
12653 }
12654
12655 static void
12656 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12657 {
12658   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12659   oappend_maybe_intel (scratchbuf);
12660 }
12661
12662 /* Capital letters in template are macros.  */
12663 static int
12664 putop (const char *in_template, int sizeflag)
12665 {
12666   const char *p;
12667   int alt = 0;
12668   int cond = 1;
12669   unsigned int l = 0, len = 1;
12670   char last[4];
12671
12672 #define SAVE_LAST(c)                    \
12673   if (l < len && l < sizeof (last))     \
12674     last[l++] = c;                      \
12675   else                                  \
12676     abort ();
12677
12678   for (p = in_template; *p; p++)
12679     {
12680       switch (*p)
12681         {
12682         default:
12683           *obufp++ = *p;
12684           break;
12685         case '%':
12686           len++;
12687           break;
12688         case '!':
12689           cond = 0;
12690           break;
12691         case '{':
12692           if (intel_syntax)
12693             {
12694               while (*++p != '|')
12695                 if (*p == '}' || *p == '\0')
12696                   abort ();
12697             }
12698           /* Fall through.  */
12699         case 'I':
12700           alt = 1;
12701           continue;
12702         case '|':
12703           while (*++p != '}')
12704             {
12705               if (*p == '\0')
12706                 abort ();
12707             }
12708           break;
12709         case '}':
12710           break;
12711         case 'A':
12712           if (intel_syntax)
12713             break;
12714           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12715             *obufp++ = 'b';
12716           break;
12717         case 'B':
12718           if (l == 0 && len == 1)
12719             {
12720 case_B:
12721               if (intel_syntax)
12722                 break;
12723               if (sizeflag & SUFFIX_ALWAYS)
12724                 *obufp++ = 'b';
12725             }
12726           else
12727             {
12728               if (l != 1
12729                   || len != 2
12730                   || last[0] != 'L')
12731                 {
12732                   SAVE_LAST (*p);
12733                   break;
12734                 }
12735
12736               if (address_mode == mode_64bit
12737                   && !(prefixes & PREFIX_ADDR))
12738                 {
12739                   *obufp++ = 'a';
12740                   *obufp++ = 'b';
12741                   *obufp++ = 's';
12742                 }
12743
12744               goto case_B;
12745             }
12746           break;
12747         case 'C':
12748           if (intel_syntax && !alt)
12749             break;
12750           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12751             {
12752               if (sizeflag & DFLAG)
12753                 *obufp++ = intel_syntax ? 'd' : 'l';
12754               else
12755                 *obufp++ = intel_syntax ? 'w' : 's';
12756               used_prefixes |= (prefixes & PREFIX_DATA);
12757             }
12758           break;
12759         case 'D':
12760           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12761             break;
12762           USED_REX (REX_W);
12763           if (modrm.mod == 3)
12764             {
12765               if (rex & REX_W)
12766                 *obufp++ = 'q';
12767               else
12768                 {
12769                   if (sizeflag & DFLAG)
12770                     *obufp++ = intel_syntax ? 'd' : 'l';
12771                   else
12772                     *obufp++ = 'w';
12773                   used_prefixes |= (prefixes & PREFIX_DATA);
12774                 }
12775             }
12776           else
12777             *obufp++ = 'w';
12778           break;
12779         case 'E':               /* For jcxz/jecxz */
12780           if (address_mode == mode_64bit)
12781             {
12782               if (sizeflag & AFLAG)
12783                 *obufp++ = 'r';
12784               else
12785                 *obufp++ = 'e';
12786             }
12787           else
12788             if (sizeflag & AFLAG)
12789               *obufp++ = 'e';
12790           used_prefixes |= (prefixes & PREFIX_ADDR);
12791           break;
12792         case 'F':
12793           if (intel_syntax)
12794             break;
12795           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12796             {
12797               if (sizeflag & AFLAG)
12798                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12799               else
12800                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12801               used_prefixes |= (prefixes & PREFIX_ADDR);
12802             }
12803           break;
12804         case 'G':
12805           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12806             break;
12807           if ((rex & REX_W) || (sizeflag & DFLAG))
12808             *obufp++ = 'l';
12809           else
12810             *obufp++ = 'w';
12811           if (!(rex & REX_W))
12812             used_prefixes |= (prefixes & PREFIX_DATA);
12813           break;
12814         case 'H':
12815           if (intel_syntax)
12816             break;
12817           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12818               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12819             {
12820               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12821               *obufp++ = ',';
12822               *obufp++ = 'p';
12823               if (prefixes & PREFIX_DS)
12824                 *obufp++ = 't';
12825               else
12826                 *obufp++ = 'n';
12827             }
12828           break;
12829         case 'J':
12830           if (intel_syntax)
12831             break;
12832           *obufp++ = 'l';
12833           break;
12834         case 'K':
12835           USED_REX (REX_W);
12836           if (rex & REX_W)
12837             *obufp++ = 'q';
12838           else
12839             *obufp++ = 'd';
12840           break;
12841         case 'Z':
12842           if (l != 0 || len != 1)
12843             {
12844               if (l != 1 || len != 2 || last[0] != 'X')
12845                 {
12846                   SAVE_LAST (*p);
12847                   break;
12848                 }
12849               if (!need_vex || !vex.evex)
12850                 abort ();
12851               if (intel_syntax
12852                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12853                 break;
12854               switch (vex.length)
12855                 {
12856                 case 128:
12857                   *obufp++ = 'x';
12858                   break;
12859                 case 256:
12860                   *obufp++ = 'y';
12861                   break;
12862                 case 512:
12863                   *obufp++ = 'z';
12864                   break;
12865                 default:
12866                   abort ();
12867                 }
12868               break;
12869             }
12870           if (intel_syntax)
12871             break;
12872           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12873             {
12874               *obufp++ = 'q';
12875               break;
12876             }
12877           /* Fall through.  */
12878           goto case_L;
12879         case 'L':
12880           if (l != 0 || len != 1)
12881             {
12882               SAVE_LAST (*p);
12883               break;
12884             }
12885 case_L:
12886           if (intel_syntax)
12887             break;
12888           if (sizeflag & SUFFIX_ALWAYS)
12889             *obufp++ = 'l';
12890           break;
12891         case 'M':
12892           if (intel_mnemonic != cond)
12893             *obufp++ = 'r';
12894           break;
12895         case 'N':
12896           if ((prefixes & PREFIX_FWAIT) == 0)
12897             *obufp++ = 'n';
12898           else
12899             used_prefixes |= PREFIX_FWAIT;
12900           break;
12901         case 'O':
12902           USED_REX (REX_W);
12903           if (rex & REX_W)
12904             *obufp++ = 'o';
12905           else if (intel_syntax && (sizeflag & DFLAG))
12906             *obufp++ = 'q';
12907           else
12908             *obufp++ = 'd';
12909           if (!(rex & REX_W))
12910             used_prefixes |= (prefixes & PREFIX_DATA);
12911           break;
12912         case '&':
12913           if (!intel_syntax
12914               && address_mode == mode_64bit
12915               && isa64 == intel64)
12916             {
12917               *obufp++ = 'q';
12918               break;
12919             }
12920           /* Fall through.  */
12921         case 'T':
12922           if (!intel_syntax
12923               && address_mode == mode_64bit
12924               && ((sizeflag & DFLAG) || (rex & REX_W)))
12925             {
12926               *obufp++ = 'q';
12927               break;
12928             }
12929           /* Fall through.  */
12930           goto case_P;
12931         case 'P':
12932           if (l == 0 && len == 1)
12933             {
12934 case_P:
12935               if (intel_syntax)
12936                 {
12937                   if ((rex & REX_W) == 0
12938                       && (prefixes & PREFIX_DATA))
12939                     {
12940                       if ((sizeflag & DFLAG) == 0)
12941                         *obufp++ = 'w';
12942                       used_prefixes |= (prefixes & PREFIX_DATA);
12943                     }
12944                   break;
12945                 }
12946               if ((prefixes & PREFIX_DATA)
12947                   || (rex & REX_W)
12948                   || (sizeflag & SUFFIX_ALWAYS))
12949                 {
12950                   USED_REX (REX_W);
12951                   if (rex & REX_W)
12952                     *obufp++ = 'q';
12953                   else
12954                     {
12955                       if (sizeflag & DFLAG)
12956                         *obufp++ = 'l';
12957                       else
12958                         *obufp++ = 'w';
12959                       used_prefixes |= (prefixes & PREFIX_DATA);
12960                     }
12961                 }
12962             }
12963           else
12964             {
12965               if (l != 1 || len != 2 || last[0] != 'L')
12966                 {
12967                   SAVE_LAST (*p);
12968                   break;
12969                 }
12970
12971               if ((prefixes & PREFIX_DATA)
12972                   || (rex & REX_W)
12973                   || (sizeflag & SUFFIX_ALWAYS))
12974                 {
12975                   USED_REX (REX_W);
12976                   if (rex & REX_W)
12977                     *obufp++ = 'q';
12978                   else
12979                     {
12980                       if (sizeflag & DFLAG)
12981                         *obufp++ = intel_syntax ? 'd' : 'l';
12982                       else
12983                         *obufp++ = 'w';
12984                       used_prefixes |= (prefixes & PREFIX_DATA);
12985                     }
12986                 }
12987             }
12988           break;
12989         case 'U':
12990           if (intel_syntax)
12991             break;
12992           if (address_mode == mode_64bit
12993               && ((sizeflag & DFLAG) || (rex & REX_W)))
12994             {
12995               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12996                 *obufp++ = 'q';
12997               break;
12998             }
12999           /* Fall through.  */
13000           goto case_Q;
13001         case 'Q':
13002           if (l == 0 && len == 1)
13003             {
13004 case_Q:
13005               if (intel_syntax && !alt)
13006                 break;
13007               USED_REX (REX_W);
13008               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13009                 {
13010                   if (rex & REX_W)
13011                     *obufp++ = 'q';
13012                   else
13013                     {
13014                       if (sizeflag & DFLAG)
13015                         *obufp++ = intel_syntax ? 'd' : 'l';
13016                       else
13017                         *obufp++ = 'w';
13018                       used_prefixes |= (prefixes & PREFIX_DATA);
13019                     }
13020                 }
13021             }
13022           else
13023             {
13024               if (l != 1 || len != 2 || last[0] != 'L')
13025                 {
13026                   SAVE_LAST (*p);
13027                   break;
13028                 }
13029               if (intel_syntax
13030                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13031                 break;
13032               if ((rex & REX_W))
13033                 {
13034                   USED_REX (REX_W);
13035                   *obufp++ = 'q';
13036                 }
13037               else
13038                 *obufp++ = 'l';
13039             }
13040           break;
13041         case 'R':
13042           USED_REX (REX_W);
13043           if (rex & REX_W)
13044             *obufp++ = 'q';
13045           else if (sizeflag & DFLAG)
13046             {
13047               if (intel_syntax)
13048                   *obufp++ = 'd';
13049               else
13050                   *obufp++ = 'l';
13051             }
13052           else
13053             *obufp++ = 'w';
13054           if (intel_syntax && !p[1]
13055               && ((rex & REX_W) || (sizeflag & DFLAG)))
13056             *obufp++ = 'e';
13057           if (!(rex & REX_W))
13058             used_prefixes |= (prefixes & PREFIX_DATA);
13059           break;
13060         case 'V':
13061           if (l == 0 && len == 1)
13062             {
13063               if (intel_syntax)
13064                 break;
13065               if (address_mode == mode_64bit
13066                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13067                 {
13068                   if (sizeflag & SUFFIX_ALWAYS)
13069                     *obufp++ = 'q';
13070                   break;
13071                 }
13072             }
13073           else
13074             {
13075               if (l != 1
13076                   || len != 2
13077                   || last[0] != 'L')
13078                 {
13079                   SAVE_LAST (*p);
13080                   break;
13081                 }
13082
13083               if (rex & REX_W)
13084                 {
13085                   *obufp++ = 'a';
13086                   *obufp++ = 'b';
13087                   *obufp++ = 's';
13088                 }
13089             }
13090           /* Fall through.  */
13091           goto case_S;
13092         case 'S':
13093           if (l == 0 && len == 1)
13094             {
13095 case_S:
13096               if (intel_syntax)
13097                 break;
13098               if (sizeflag & SUFFIX_ALWAYS)
13099                 {
13100                   if (rex & REX_W)
13101                     *obufp++ = 'q';
13102                   else
13103                     {
13104                       if (sizeflag & DFLAG)
13105                         *obufp++ = 'l';
13106                       else
13107                         *obufp++ = 'w';
13108                       used_prefixes |= (prefixes & PREFIX_DATA);
13109                     }
13110                 }
13111             }
13112           else
13113             {
13114               if (l != 1
13115                   || len != 2
13116                   || last[0] != 'L')
13117                 {
13118                   SAVE_LAST (*p);
13119                   break;
13120                 }
13121
13122               if (address_mode == mode_64bit
13123                   && !(prefixes & PREFIX_ADDR))
13124                 {
13125                   *obufp++ = 'a';
13126                   *obufp++ = 'b';
13127                   *obufp++ = 's';
13128                 }
13129
13130               goto case_S;
13131             }
13132           break;
13133         case 'X':
13134           if (l != 0 || len != 1)
13135             {
13136               SAVE_LAST (*p);
13137               break;
13138             }
13139           if (need_vex && vex.prefix)
13140             {
13141               if (vex.prefix == DATA_PREFIX_OPCODE)
13142                 *obufp++ = 'd';
13143               else
13144                 *obufp++ = 's';
13145             }
13146           else
13147             {
13148               if (prefixes & PREFIX_DATA)
13149                 *obufp++ = 'd';
13150               else
13151                 *obufp++ = 's';
13152               used_prefixes |= (prefixes & PREFIX_DATA);
13153             }
13154           break;
13155         case 'Y':
13156           if (l == 0 && len == 1)
13157             abort ();
13158           else
13159             {
13160               if (l != 1 || len != 2 || last[0] != 'X')
13161                 {
13162                   SAVE_LAST (*p);
13163                   break;
13164                 }
13165               if (!need_vex)
13166                 abort ();
13167               if (intel_syntax
13168                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13169                 break;
13170               switch (vex.length)
13171                 {
13172                 case 128:
13173                   *obufp++ = 'x';
13174                   break;
13175                 case 256:
13176                   *obufp++ = 'y';
13177                   break;
13178                 case 512:
13179                   if (!vex.evex)
13180                 default:
13181                     abort ();
13182                 }
13183             }
13184           break;
13185         case 'W':
13186           if (l == 0 && len == 1)
13187             {
13188               /* operand size flag for cwtl, cbtw */
13189               USED_REX (REX_W);
13190               if (rex & REX_W)
13191                 {
13192                   if (intel_syntax)
13193                     *obufp++ = 'd';
13194                   else
13195                     *obufp++ = 'l';
13196                 }
13197               else if (sizeflag & DFLAG)
13198                 *obufp++ = 'w';
13199               else
13200                 *obufp++ = 'b';
13201               if (!(rex & REX_W))
13202                 used_prefixes |= (prefixes & PREFIX_DATA);
13203             }
13204           else
13205             {
13206               if (l != 1
13207                   || len != 2
13208                   || (last[0] != 'X'
13209                       && last[0] != 'L'))
13210                 {
13211                   SAVE_LAST (*p);
13212                   break;
13213                 }
13214               if (!need_vex)
13215                 abort ();
13216               if (last[0] == 'X')
13217                 *obufp++ = vex.w ? 'd': 's';
13218               else
13219                 *obufp++ = vex.w ? 'q': 'd';
13220             }
13221           break;
13222         case '^':
13223           if (intel_syntax)
13224             break;
13225           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13226             {
13227               if (sizeflag & DFLAG)
13228                 *obufp++ = 'l';
13229               else
13230                 *obufp++ = 'w';
13231               used_prefixes |= (prefixes & PREFIX_DATA);
13232             }
13233           break;
13234         case '@':
13235           if (intel_syntax)
13236             break;
13237           if (address_mode == mode_64bit
13238               && (isa64 == intel64
13239                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13240               *obufp++ = 'q';
13241           else if ((prefixes & PREFIX_DATA))
13242             {
13243               if (!(sizeflag & DFLAG))
13244                 *obufp++ = 'w';
13245               used_prefixes |= (prefixes & PREFIX_DATA);
13246             }
13247           break;
13248         }
13249       alt = 0;
13250     }
13251   *obufp = 0;
13252   mnemonicendp = obufp;
13253   return 0;
13254 }
13255
13256 static void
13257 oappend (const char *s)
13258 {
13259   obufp = stpcpy (obufp, s);
13260 }
13261
13262 static void
13263 append_seg (void)
13264 {
13265   /* Only print the active segment register.  */
13266   if (!active_seg_prefix)
13267     return;
13268
13269   used_prefixes |= active_seg_prefix;
13270   switch (active_seg_prefix)
13271     {
13272     case PREFIX_CS:
13273       oappend_maybe_intel ("%cs:");
13274       break;
13275     case PREFIX_DS:
13276       oappend_maybe_intel ("%ds:");
13277       break;
13278     case PREFIX_SS:
13279       oappend_maybe_intel ("%ss:");
13280       break;
13281     case PREFIX_ES:
13282       oappend_maybe_intel ("%es:");
13283       break;
13284     case PREFIX_FS:
13285       oappend_maybe_intel ("%fs:");
13286       break;
13287     case PREFIX_GS:
13288       oappend_maybe_intel ("%gs:");
13289       break;
13290     default:
13291       break;
13292     }
13293 }
13294
13295 static void
13296 OP_indirE (int bytemode, int sizeflag)
13297 {
13298   if (!intel_syntax)
13299     oappend ("*");
13300   OP_E (bytemode, sizeflag);
13301 }
13302
13303 static void
13304 print_operand_value (char *buf, int hex, bfd_vma disp)
13305 {
13306   if (address_mode == mode_64bit)
13307     {
13308       if (hex)
13309         {
13310           char tmp[30];
13311           int i;
13312           buf[0] = '0';
13313           buf[1] = 'x';
13314           sprintf_vma (tmp, disp);
13315           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13316           strcpy (buf + 2, tmp + i);
13317         }
13318       else
13319         {
13320           bfd_signed_vma v = disp;
13321           char tmp[30];
13322           int i;
13323           if (v < 0)
13324             {
13325               *(buf++) = '-';
13326               v = -disp;
13327               /* Check for possible overflow on 0x8000000000000000.  */
13328               if (v < 0)
13329                 {
13330                   strcpy (buf, "9223372036854775808");
13331                   return;
13332                 }
13333             }
13334           if (!v)
13335             {
13336               strcpy (buf, "0");
13337               return;
13338             }
13339
13340           i = 0;
13341           tmp[29] = 0;
13342           while (v)
13343             {
13344               tmp[28 - i] = (v % 10) + '0';
13345               v /= 10;
13346               i++;
13347             }
13348           strcpy (buf, tmp + 29 - i);
13349         }
13350     }
13351   else
13352     {
13353       if (hex)
13354         sprintf (buf, "0x%x", (unsigned int) disp);
13355       else
13356         sprintf (buf, "%d", (int) disp);
13357     }
13358 }
13359
13360 /* Put DISP in BUF as signed hex number.  */
13361
13362 static void
13363 print_displacement (char *buf, bfd_vma disp)
13364 {
13365   bfd_signed_vma val = disp;
13366   char tmp[30];
13367   int i, j = 0;
13368
13369   if (val < 0)
13370     {
13371       buf[j++] = '-';
13372       val = -disp;
13373
13374       /* Check for possible overflow.  */
13375       if (val < 0)
13376         {
13377           switch (address_mode)
13378             {
13379             case mode_64bit:
13380               strcpy (buf + j, "0x8000000000000000");
13381               break;
13382             case mode_32bit:
13383               strcpy (buf + j, "0x80000000");
13384               break;
13385             case mode_16bit:
13386               strcpy (buf + j, "0x8000");
13387               break;
13388             }
13389           return;
13390         }
13391     }
13392
13393   buf[j++] = '0';
13394   buf[j++] = 'x';
13395
13396   sprintf_vma (tmp, (bfd_vma) val);
13397   for (i = 0; tmp[i] == '0'; i++)
13398     continue;
13399   if (tmp[i] == '\0')
13400     i--;
13401   strcpy (buf + j, tmp + i);
13402 }
13403
13404 static void
13405 intel_operand_size (int bytemode, int sizeflag)
13406 {
13407   if (vex.evex
13408       && vex.b
13409       && (bytemode == x_mode
13410           || bytemode == evex_half_bcst_xmmq_mode))
13411     {
13412       if (vex.w)
13413         oappend ("QWORD PTR ");
13414       else
13415         oappend ("DWORD PTR ");
13416       return;
13417     }
13418   switch (bytemode)
13419     {
13420     case b_mode:
13421     case b_swap_mode:
13422     case dqb_mode:
13423     case db_mode:
13424       oappend ("BYTE PTR ");
13425       break;
13426     case w_mode:
13427     case dw_mode:
13428     case dqw_mode:
13429       oappend ("WORD PTR ");
13430       break;
13431     case indir_v_mode:
13432       if (address_mode == mode_64bit && isa64 == intel64)
13433         {
13434           oappend ("QWORD PTR ");
13435           break;
13436         }
13437       /* Fall through.  */
13438     case stack_v_mode:
13439       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13440         {
13441           oappend ("QWORD PTR ");
13442           break;
13443         }
13444       /* Fall through.  */
13445     case v_mode:
13446     case v_swap_mode:
13447     case dq_mode:
13448       USED_REX (REX_W);
13449       if (rex & REX_W)
13450         oappend ("QWORD PTR ");
13451       else
13452         {
13453           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13454             oappend ("DWORD PTR ");
13455           else
13456             oappend ("WORD PTR ");
13457           used_prefixes |= (prefixes & PREFIX_DATA);
13458         }
13459       break;
13460     case z_mode:
13461       if ((rex & REX_W) || (sizeflag & DFLAG))
13462         *obufp++ = 'D';
13463       oappend ("WORD PTR ");
13464       if (!(rex & REX_W))
13465         used_prefixes |= (prefixes & PREFIX_DATA);
13466       break;
13467     case a_mode:
13468       if (sizeflag & DFLAG)
13469         oappend ("QWORD PTR ");
13470       else
13471         oappend ("DWORD PTR ");
13472       used_prefixes |= (prefixes & PREFIX_DATA);
13473       break;
13474     case d_mode:
13475     case d_scalar_mode:
13476     case d_scalar_swap_mode:
13477     case d_swap_mode:
13478     case dqd_mode:
13479       oappend ("DWORD PTR ");
13480       break;
13481     case q_mode:
13482     case q_scalar_mode:
13483     case q_scalar_swap_mode:
13484     case q_swap_mode:
13485       oappend ("QWORD PTR ");
13486       break;
13487     case m_mode:
13488       if (address_mode == mode_64bit)
13489         oappend ("QWORD PTR ");
13490       else
13491         oappend ("DWORD PTR ");
13492       break;
13493     case f_mode:
13494       if (sizeflag & DFLAG)
13495         oappend ("FWORD PTR ");
13496       else
13497         oappend ("DWORD PTR ");
13498       used_prefixes |= (prefixes & PREFIX_DATA);
13499       break;
13500     case t_mode:
13501       oappend ("TBYTE PTR ");
13502       break;
13503     case x_mode:
13504     case x_swap_mode:
13505     case evex_x_gscat_mode:
13506     case evex_x_nobcst_mode:
13507     case b_scalar_mode:
13508     case w_scalar_mode:
13509       if (need_vex)
13510         {
13511           switch (vex.length)
13512             {
13513             case 128:
13514               oappend ("XMMWORD PTR ");
13515               break;
13516             case 256:
13517               oappend ("YMMWORD PTR ");
13518               break;
13519             case 512:
13520               oappend ("ZMMWORD PTR ");
13521               break;
13522             default:
13523               abort ();
13524             }
13525         }
13526       else
13527         oappend ("XMMWORD PTR ");
13528       break;
13529     case xmm_mode:
13530       oappend ("XMMWORD PTR ");
13531       break;
13532     case ymm_mode:
13533       oappend ("YMMWORD PTR ");
13534       break;
13535     case xmmq_mode:
13536     case evex_half_bcst_xmmq_mode:
13537       if (!need_vex)
13538         abort ();
13539
13540       switch (vex.length)
13541         {
13542         case 128:
13543           oappend ("QWORD PTR ");
13544           break;
13545         case 256:
13546           oappend ("XMMWORD PTR ");
13547           break;
13548         case 512:
13549           oappend ("YMMWORD PTR ");
13550           break;
13551         default:
13552           abort ();
13553         }
13554       break;
13555     case xmm_mb_mode:
13556       if (!need_vex)
13557         abort ();
13558
13559       switch (vex.length)
13560         {
13561         case 128:
13562         case 256:
13563         case 512:
13564           oappend ("BYTE PTR ");
13565           break;
13566         default:
13567           abort ();
13568         }
13569       break;
13570     case xmm_mw_mode:
13571       if (!need_vex)
13572         abort ();
13573
13574       switch (vex.length)
13575         {
13576         case 128:
13577         case 256:
13578         case 512:
13579           oappend ("WORD PTR ");
13580           break;
13581         default:
13582           abort ();
13583         }
13584       break;
13585     case xmm_md_mode:
13586       if (!need_vex)
13587         abort ();
13588
13589       switch (vex.length)
13590         {
13591         case 128:
13592         case 256:
13593         case 512:
13594           oappend ("DWORD PTR ");
13595           break;
13596         default:
13597           abort ();
13598         }
13599       break;
13600     case xmm_mq_mode:
13601       if (!need_vex)
13602         abort ();
13603
13604       switch (vex.length)
13605         {
13606         case 128:
13607         case 256:
13608         case 512:
13609           oappend ("QWORD PTR ");
13610           break;
13611         default:
13612           abort ();
13613         }
13614       break;
13615     case xmmdw_mode:
13616       if (!need_vex)
13617         abort ();
13618
13619       switch (vex.length)
13620         {
13621         case 128:
13622           oappend ("WORD PTR ");
13623           break;
13624         case 256:
13625           oappend ("DWORD PTR ");
13626           break;
13627         case 512:
13628           oappend ("QWORD PTR ");
13629           break;
13630         default:
13631           abort ();
13632         }
13633       break;
13634     case xmmqd_mode:
13635       if (!need_vex)
13636         abort ();
13637
13638       switch (vex.length)
13639         {
13640         case 128:
13641           oappend ("DWORD PTR ");
13642           break;
13643         case 256:
13644           oappend ("QWORD PTR ");
13645           break;
13646         case 512:
13647           oappend ("XMMWORD PTR ");
13648           break;
13649         default:
13650           abort ();
13651         }
13652       break;
13653     case ymmq_mode:
13654       if (!need_vex)
13655         abort ();
13656
13657       switch (vex.length)
13658         {
13659         case 128:
13660           oappend ("QWORD PTR ");
13661           break;
13662         case 256:
13663           oappend ("YMMWORD PTR ");
13664           break;
13665         case 512:
13666           oappend ("ZMMWORD PTR ");
13667           break;
13668         default:
13669           abort ();
13670         }
13671       break;
13672     case ymmxmm_mode:
13673       if (!need_vex)
13674         abort ();
13675
13676       switch (vex.length)
13677         {
13678         case 128:
13679         case 256:
13680           oappend ("XMMWORD PTR ");
13681           break;
13682         default:
13683           abort ();
13684         }
13685       break;
13686     case o_mode:
13687       oappend ("OWORD PTR ");
13688       break;
13689     case xmm_mdq_mode:
13690     case vex_w_dq_mode:
13691     case vex_scalar_w_dq_mode:
13692       if (!need_vex)
13693         abort ();
13694
13695       if (vex.w)
13696         oappend ("QWORD PTR ");
13697       else
13698         oappend ("DWORD PTR ");
13699       break;
13700     case vex_vsib_d_w_dq_mode:
13701     case vex_vsib_q_w_dq_mode:
13702       if (!need_vex)
13703         abort ();
13704
13705       if (!vex.evex)
13706         {
13707           if (vex.w)
13708             oappend ("QWORD PTR ");
13709           else
13710             oappend ("DWORD PTR ");
13711         }
13712       else
13713         {
13714           switch (vex.length)
13715             {
13716             case 128:
13717               oappend ("XMMWORD PTR ");
13718               break;
13719             case 256:
13720               oappend ("YMMWORD PTR ");
13721               break;
13722             case 512:
13723               oappend ("ZMMWORD PTR ");
13724               break;
13725             default:
13726               abort ();
13727             }
13728         }
13729       break;
13730     case vex_vsib_q_w_d_mode:
13731     case vex_vsib_d_w_d_mode:
13732       if (!need_vex || !vex.evex)
13733         abort ();
13734
13735       switch (vex.length)
13736         {
13737         case 128:
13738           oappend ("QWORD PTR ");
13739           break;
13740         case 256:
13741           oappend ("XMMWORD PTR ");
13742           break;
13743         case 512:
13744           oappend ("YMMWORD PTR ");
13745           break;
13746         default:
13747           abort ();
13748         }
13749
13750       break;
13751     case mask_bd_mode:
13752       if (!need_vex || vex.length != 128)
13753         abort ();
13754       if (vex.w)
13755         oappend ("DWORD PTR ");
13756       else
13757         oappend ("BYTE PTR ");
13758       break;
13759     case mask_mode:
13760       if (!need_vex)
13761         abort ();
13762       if (vex.w)
13763         oappend ("QWORD PTR ");
13764       else
13765         oappend ("WORD PTR ");
13766       break;
13767     case v_bnd_mode:
13768     case v_bndmk_mode:
13769     default:
13770       break;
13771     }
13772 }
13773
13774 static void
13775 OP_E_register (int bytemode, int sizeflag)
13776 {
13777   int reg = modrm.rm;
13778   const char **names;
13779
13780   USED_REX (REX_B);
13781   if ((rex & REX_B))
13782     reg += 8;
13783
13784   if ((sizeflag & SUFFIX_ALWAYS)
13785       && (bytemode == b_swap_mode
13786           || bytemode == bnd_swap_mode
13787           || bytemode == v_swap_mode))
13788     swap_operand ();
13789
13790   switch (bytemode)
13791     {
13792     case b_mode:
13793     case b_swap_mode:
13794       USED_REX (0);
13795       if (rex)
13796         names = names8rex;
13797       else
13798         names = names8;
13799       break;
13800     case w_mode:
13801       names = names16;
13802       break;
13803     case d_mode:
13804     case dw_mode:
13805     case db_mode:
13806       names = names32;
13807       break;
13808     case q_mode:
13809       names = names64;
13810       break;
13811     case m_mode:
13812     case v_bnd_mode:
13813       names = address_mode == mode_64bit ? names64 : names32;
13814       break;
13815     case bnd_mode:
13816     case bnd_swap_mode:
13817       if (reg > 0x3)
13818         {
13819           oappend ("(bad)");
13820           return;
13821         }
13822       names = names_bnd;
13823       break;
13824     case indir_v_mode:
13825       if (address_mode == mode_64bit && isa64 == intel64)
13826         {
13827           names = names64;
13828           break;
13829         }
13830       /* Fall through.  */
13831     case stack_v_mode:
13832       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13833         {
13834           names = names64;
13835           break;
13836         }
13837       bytemode = v_mode;
13838       /* Fall through.  */
13839     case v_mode:
13840     case v_swap_mode:
13841     case dq_mode:
13842     case dqb_mode:
13843     case dqd_mode:
13844     case dqw_mode:
13845       USED_REX (REX_W);
13846       if (rex & REX_W)
13847         names = names64;
13848       else
13849         {
13850           if ((sizeflag & DFLAG)
13851               || (bytemode != v_mode
13852                   && bytemode != v_swap_mode))
13853             names = names32;
13854           else
13855             names = names16;
13856           used_prefixes |= (prefixes & PREFIX_DATA);
13857         }
13858       break;
13859     case va_mode:
13860       names = (address_mode == mode_64bit
13861                ? names64 : names32);
13862       if (!(prefixes & PREFIX_ADDR))
13863         names = (address_mode == mode_16bit
13864                      ? names16 : names);
13865       else
13866         {
13867           /* Remove "addr16/addr32".  */
13868           all_prefixes[last_addr_prefix] = 0;
13869           names = (address_mode != mode_32bit
13870                        ? names32 : names16);
13871           used_prefixes |= PREFIX_ADDR;
13872         }
13873       break;
13874     case mask_bd_mode:
13875     case mask_mode:
13876       if (reg > 0x7)
13877         {
13878           oappend ("(bad)");
13879           return;
13880         }
13881       names = names_mask;
13882       break;
13883     case 0:
13884       return;
13885     default:
13886       oappend (INTERNAL_DISASSEMBLER_ERROR);
13887       return;
13888     }
13889   oappend (names[reg]);
13890 }
13891
13892 static void
13893 OP_E_memory (int bytemode, int sizeflag)
13894 {
13895   bfd_vma disp = 0;
13896   int add = (rex & REX_B) ? 8 : 0;
13897   int riprel = 0;
13898   int shift;
13899
13900   if (vex.evex)
13901     {
13902       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13903       if (vex.b
13904           && bytemode != x_mode
13905           && bytemode != xmmq_mode
13906           && bytemode != evex_half_bcst_xmmq_mode)
13907         {
13908           BadOp ();
13909           return;
13910         }
13911       switch (bytemode)
13912         {
13913         case dqw_mode:
13914         case dw_mode:
13915           shift = 1;
13916           break;
13917         case dqb_mode:
13918         case db_mode:
13919           shift = 0;
13920           break;
13921         case dq_mode:
13922           if (address_mode != mode_64bit)
13923             {
13924               shift = 2;
13925               break;
13926             }
13927             /* fall through */
13928         case vex_vsib_d_w_dq_mode:
13929         case vex_vsib_d_w_d_mode:
13930         case vex_vsib_q_w_dq_mode:
13931         case vex_vsib_q_w_d_mode:
13932         case evex_x_gscat_mode:
13933         case xmm_mdq_mode:
13934           shift = vex.w ? 3 : 2;
13935           break;
13936         case x_mode:
13937         case evex_half_bcst_xmmq_mode:
13938         case xmmq_mode:
13939           if (vex.b)
13940             {
13941               shift = vex.w ? 3 : 2;
13942               break;
13943             }
13944           /* Fall through.  */
13945         case xmmqd_mode:
13946         case xmmdw_mode:
13947         case ymmq_mode:
13948         case evex_x_nobcst_mode:
13949         case x_swap_mode:
13950           switch (vex.length)
13951             {
13952             case 128:
13953               shift = 4;
13954               break;
13955             case 256:
13956               shift = 5;
13957               break;
13958             case 512:
13959               shift = 6;
13960               break;
13961             default:
13962               abort ();
13963             }
13964           break;
13965         case ymm_mode:
13966           shift = 5;
13967           break;
13968         case xmm_mode:
13969           shift = 4;
13970           break;
13971         case xmm_mq_mode:
13972         case q_mode:
13973         case q_scalar_mode:
13974         case q_swap_mode:
13975         case q_scalar_swap_mode:
13976           shift = 3;
13977           break;
13978         case dqd_mode:
13979         case xmm_md_mode:
13980         case d_mode:
13981         case d_scalar_mode:
13982         case d_swap_mode:
13983         case d_scalar_swap_mode:
13984           shift = 2;
13985           break;
13986         case w_scalar_mode:
13987         case xmm_mw_mode:
13988           shift = 1;
13989           break;
13990         case b_scalar_mode:
13991         case xmm_mb_mode:
13992           shift = 0;
13993           break;
13994         default:
13995           abort ();
13996         }
13997       /* Make necessary corrections to shift for modes that need it.
13998          For these modes we currently have shift 4, 5 or 6 depending on
13999          vex.length (it corresponds to xmmword, ymmword or zmmword
14000          operand).  We might want to make it 3, 4 or 5 (e.g. for
14001          xmmq_mode).  In case of broadcast enabled the corrections
14002          aren't needed, as element size is always 32 or 64 bits.  */
14003       if (!vex.b
14004           && (bytemode == xmmq_mode
14005               || bytemode == evex_half_bcst_xmmq_mode))
14006         shift -= 1;
14007       else if (bytemode == xmmqd_mode)
14008         shift -= 2;
14009       else if (bytemode == xmmdw_mode)
14010         shift -= 3;
14011       else if (bytemode == ymmq_mode && vex.length == 128)
14012         shift -= 1;
14013     }
14014   else
14015     shift = 0;
14016
14017   USED_REX (REX_B);
14018   if (intel_syntax)
14019     intel_operand_size (bytemode, sizeflag);
14020   append_seg ();
14021
14022   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14023     {
14024       /* 32/64 bit address mode */
14025       int havedisp;
14026       int havesib;
14027       int havebase;
14028       int haveindex;
14029       int needindex;
14030       int needaddr32;
14031       int base, rbase;
14032       int vindex = 0;
14033       int scale = 0;
14034       int addr32flag = !((sizeflag & AFLAG)
14035                          || bytemode == v_bnd_mode
14036                          || bytemode == v_bndmk_mode
14037                          || bytemode == bnd_mode
14038                          || bytemode == bnd_swap_mode);
14039       const char **indexes64 = names64;
14040       const char **indexes32 = names32;
14041
14042       havesib = 0;
14043       havebase = 1;
14044       haveindex = 0;
14045       base = modrm.rm;
14046
14047       if (base == 4)
14048         {
14049           havesib = 1;
14050           vindex = sib.index;
14051           USED_REX (REX_X);
14052           if (rex & REX_X)
14053             vindex += 8;
14054           switch (bytemode)
14055             {
14056             case vex_vsib_d_w_dq_mode:
14057             case vex_vsib_d_w_d_mode:
14058             case vex_vsib_q_w_dq_mode:
14059             case vex_vsib_q_w_d_mode:
14060               if (!need_vex)
14061                 abort ();
14062               if (vex.evex)
14063                 {
14064                   if (!vex.v)
14065                     vindex += 16;
14066                 }
14067
14068               haveindex = 1;
14069               switch (vex.length)
14070                 {
14071                 case 128:
14072                   indexes64 = indexes32 = names_xmm;
14073                   break;
14074                 case 256:
14075                   if (!vex.w
14076                       || bytemode == vex_vsib_q_w_dq_mode
14077                       || bytemode == vex_vsib_q_w_d_mode)
14078                     indexes64 = indexes32 = names_ymm;
14079                   else
14080                     indexes64 = indexes32 = names_xmm;
14081                   break;
14082                 case 512:
14083                   if (!vex.w
14084                       || bytemode == vex_vsib_q_w_dq_mode
14085                       || bytemode == vex_vsib_q_w_d_mode)
14086                     indexes64 = indexes32 = names_zmm;
14087                   else
14088                     indexes64 = indexes32 = names_ymm;
14089                   break;
14090                 default:
14091                   abort ();
14092                 }
14093               break;
14094             default:
14095               haveindex = vindex != 4;
14096               break;
14097             }
14098           scale = sib.scale;
14099           base = sib.base;
14100           codep++;
14101         }
14102       rbase = base + add;
14103
14104       switch (modrm.mod)
14105         {
14106         case 0:
14107           if (base == 5)
14108             {
14109               havebase = 0;
14110               if (address_mode == mode_64bit && !havesib)
14111                 riprel = 1;
14112               disp = get32s ();
14113               if (riprel && bytemode == v_bndmk_mode)
14114                 {
14115                   oappend ("(bad)");
14116                   return;
14117                 }
14118             }
14119           break;
14120         case 1:
14121           FETCH_DATA (the_info, codep + 1);
14122           disp = *codep++;
14123           if ((disp & 0x80) != 0)
14124             disp -= 0x100;
14125           if (vex.evex && shift > 0)
14126             disp <<= shift;
14127           break;
14128         case 2:
14129           disp = get32s ();
14130           break;
14131         }
14132
14133       needindex = 0;
14134       needaddr32 = 0;
14135       if (havesib
14136           && !havebase
14137           && !haveindex
14138           && address_mode != mode_16bit)
14139         {
14140           if (address_mode == mode_64bit)
14141             {
14142               /* Display eiz instead of addr32.  */
14143               needindex = addr32flag;
14144               needaddr32 = 1;
14145             }
14146           else
14147             {
14148               /* In 32-bit mode, we need index register to tell [offset]
14149                  from [eiz*1 + offset].  */
14150               needindex = 1;
14151             }
14152         }
14153
14154       havedisp = (havebase
14155                   || needindex
14156                   || (havesib && (haveindex || scale != 0)));
14157
14158       if (!intel_syntax)
14159         if (modrm.mod != 0 || base == 5)
14160           {
14161             if (havedisp || riprel)
14162               print_displacement (scratchbuf, disp);
14163             else
14164               print_operand_value (scratchbuf, 1, disp);
14165             oappend (scratchbuf);
14166             if (riprel)
14167               {
14168                 set_op (disp, 1);
14169                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14170               }
14171           }
14172
14173       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14174           && (bytemode != v_bnd_mode)
14175           && (bytemode != v_bndmk_mode)
14176           && (bytemode != bnd_mode)
14177           && (bytemode != bnd_swap_mode))
14178         used_prefixes |= PREFIX_ADDR;
14179
14180       if (havedisp || (intel_syntax && riprel))
14181         {
14182           *obufp++ = open_char;
14183           if (intel_syntax && riprel)
14184             {
14185               set_op (disp, 1);
14186               oappend (!addr32flag ? "rip" : "eip");
14187             }
14188           *obufp = '\0';
14189           if (havebase)
14190             oappend (address_mode == mode_64bit && !addr32flag
14191                      ? names64[rbase] : names32[rbase]);
14192           if (havesib)
14193             {
14194               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14195                  print index to tell base + index from base.  */
14196               if (scale != 0
14197                   || needindex
14198                   || haveindex
14199                   || (havebase && base != ESP_REG_NUM))
14200                 {
14201                   if (!intel_syntax || havebase)
14202                     {
14203                       *obufp++ = separator_char;
14204                       *obufp = '\0';
14205                     }
14206                   if (haveindex)
14207                     oappend (address_mode == mode_64bit && !addr32flag
14208                              ? indexes64[vindex] : indexes32[vindex]);
14209                   else
14210                     oappend (address_mode == mode_64bit && !addr32flag
14211                              ? index64 : index32);
14212
14213                   *obufp++ = scale_char;
14214                   *obufp = '\0';
14215                   sprintf (scratchbuf, "%d", 1 << scale);
14216                   oappend (scratchbuf);
14217                 }
14218             }
14219           if (intel_syntax
14220               && (disp || modrm.mod != 0 || base == 5))
14221             {
14222               if (!havedisp || (bfd_signed_vma) disp >= 0)
14223                 {
14224                   *obufp++ = '+';
14225                   *obufp = '\0';
14226                 }
14227               else if (modrm.mod != 1 && disp != -disp)
14228                 {
14229                   *obufp++ = '-';
14230                   *obufp = '\0';
14231                   disp = - (bfd_signed_vma) disp;
14232                 }
14233
14234               if (havedisp)
14235                 print_displacement (scratchbuf, disp);
14236               else
14237                 print_operand_value (scratchbuf, 1, disp);
14238               oappend (scratchbuf);
14239             }
14240
14241           *obufp++ = close_char;
14242           *obufp = '\0';
14243         }
14244       else if (intel_syntax)
14245         {
14246           if (modrm.mod != 0 || base == 5)
14247             {
14248               if (!active_seg_prefix)
14249                 {
14250                   oappend (names_seg[ds_reg - es_reg]);
14251                   oappend (":");
14252                 }
14253               print_operand_value (scratchbuf, 1, disp);
14254               oappend (scratchbuf);
14255             }
14256         }
14257     }
14258   else
14259     {
14260       /* 16 bit address mode */
14261       used_prefixes |= prefixes & PREFIX_ADDR;
14262       switch (modrm.mod)
14263         {
14264         case 0:
14265           if (modrm.rm == 6)
14266             {
14267               disp = get16 ();
14268               if ((disp & 0x8000) != 0)
14269                 disp -= 0x10000;
14270             }
14271           break;
14272         case 1:
14273           FETCH_DATA (the_info, codep + 1);
14274           disp = *codep++;
14275           if ((disp & 0x80) != 0)
14276             disp -= 0x100;
14277           if (vex.evex && shift > 0)
14278             disp <<= shift;
14279           break;
14280         case 2:
14281           disp = get16 ();
14282           if ((disp & 0x8000) != 0)
14283             disp -= 0x10000;
14284           break;
14285         }
14286
14287       if (!intel_syntax)
14288         if (modrm.mod != 0 || modrm.rm == 6)
14289           {
14290             print_displacement (scratchbuf, disp);
14291             oappend (scratchbuf);
14292           }
14293
14294       if (modrm.mod != 0 || modrm.rm != 6)
14295         {
14296           *obufp++ = open_char;
14297           *obufp = '\0';
14298           oappend (index16[modrm.rm]);
14299           if (intel_syntax
14300               && (disp || modrm.mod != 0 || modrm.rm == 6))
14301             {
14302               if ((bfd_signed_vma) disp >= 0)
14303                 {
14304                   *obufp++ = '+';
14305                   *obufp = '\0';
14306                 }
14307               else if (modrm.mod != 1)
14308                 {
14309                   *obufp++ = '-';
14310                   *obufp = '\0';
14311                   disp = - (bfd_signed_vma) disp;
14312                 }
14313
14314               print_displacement (scratchbuf, disp);
14315               oappend (scratchbuf);
14316             }
14317
14318           *obufp++ = close_char;
14319           *obufp = '\0';
14320         }
14321       else if (intel_syntax)
14322         {
14323           if (!active_seg_prefix)
14324             {
14325               oappend (names_seg[ds_reg - es_reg]);
14326               oappend (":");
14327             }
14328           print_operand_value (scratchbuf, 1, disp & 0xffff);
14329           oappend (scratchbuf);
14330         }
14331     }
14332   if (vex.evex && vex.b
14333       && (bytemode == x_mode
14334           || bytemode == xmmq_mode
14335           || bytemode == evex_half_bcst_xmmq_mode))
14336     {
14337       if (vex.w
14338           || bytemode == xmmq_mode
14339           || bytemode == evex_half_bcst_xmmq_mode)
14340         {
14341           switch (vex.length)
14342             {
14343             case 128:
14344               oappend ("{1to2}");
14345               break;
14346             case 256:
14347               oappend ("{1to4}");
14348               break;
14349             case 512:
14350               oappend ("{1to8}");
14351               break;
14352             default:
14353               abort ();
14354             }
14355         }
14356       else
14357         {
14358           switch (vex.length)
14359             {
14360             case 128:
14361               oappend ("{1to4}");
14362               break;
14363             case 256:
14364               oappend ("{1to8}");
14365               break;
14366             case 512:
14367               oappend ("{1to16}");
14368               break;
14369             default:
14370               abort ();
14371             }
14372         }
14373     }
14374 }
14375
14376 static void
14377 OP_E (int bytemode, int sizeflag)
14378 {
14379   /* Skip mod/rm byte.  */
14380   MODRM_CHECK;
14381   codep++;
14382
14383   if (modrm.mod == 3)
14384     OP_E_register (bytemode, sizeflag);
14385   else
14386     OP_E_memory (bytemode, sizeflag);
14387 }
14388
14389 static void
14390 OP_G (int bytemode, int sizeflag)
14391 {
14392   int add = 0;
14393   const char **names;
14394   USED_REX (REX_R);
14395   if (rex & REX_R)
14396     add += 8;
14397   switch (bytemode)
14398     {
14399     case b_mode:
14400       USED_REX (0);
14401       if (rex)
14402         oappend (names8rex[modrm.reg + add]);
14403       else
14404         oappend (names8[modrm.reg + add]);
14405       break;
14406     case w_mode:
14407       oappend (names16[modrm.reg + add]);
14408       break;
14409     case d_mode:
14410     case db_mode:
14411     case dw_mode:
14412       oappend (names32[modrm.reg + add]);
14413       break;
14414     case q_mode:
14415       oappend (names64[modrm.reg + add]);
14416       break;
14417     case bnd_mode:
14418       if (modrm.reg > 0x3)
14419         {
14420           oappend ("(bad)");
14421           return;
14422         }
14423       oappend (names_bnd[modrm.reg]);
14424       break;
14425     case v_mode:
14426     case dq_mode:
14427     case dqb_mode:
14428     case dqd_mode:
14429     case dqw_mode:
14430       USED_REX (REX_W);
14431       if (rex & REX_W)
14432         oappend (names64[modrm.reg + add]);
14433       else
14434         {
14435           if ((sizeflag & DFLAG) || bytemode != v_mode)
14436             oappend (names32[modrm.reg + add]);
14437           else
14438             oappend (names16[modrm.reg + add]);
14439           used_prefixes |= (prefixes & PREFIX_DATA);
14440         }
14441       break;
14442     case va_mode:
14443       names = (address_mode == mode_64bit
14444                ? names64 : names32);
14445       if (!(prefixes & PREFIX_ADDR))
14446         {
14447           if (address_mode == mode_16bit)
14448             names = names16;
14449         }
14450       else
14451         {
14452           /* Remove "addr16/addr32".  */
14453           all_prefixes[last_addr_prefix] = 0;
14454           names = (address_mode != mode_32bit
14455                        ? names32 : names16);
14456           used_prefixes |= PREFIX_ADDR;
14457         }
14458       oappend (names[modrm.reg + add]);
14459       break;
14460     case m_mode:
14461       if (address_mode == mode_64bit)
14462         oappend (names64[modrm.reg + add]);
14463       else
14464         oappend (names32[modrm.reg + add]);
14465       break;
14466     case mask_bd_mode:
14467     case mask_mode:
14468       if ((modrm.reg + add) > 0x7)
14469         {
14470           oappend ("(bad)");
14471           return;
14472         }
14473       oappend (names_mask[modrm.reg + add]);
14474       break;
14475     default:
14476       oappend (INTERNAL_DISASSEMBLER_ERROR);
14477       break;
14478     }
14479 }
14480
14481 static bfd_vma
14482 get64 (void)
14483 {
14484   bfd_vma x;
14485 #ifdef BFD64
14486   unsigned int a;
14487   unsigned int b;
14488
14489   FETCH_DATA (the_info, codep + 8);
14490   a = *codep++ & 0xff;
14491   a |= (*codep++ & 0xff) << 8;
14492   a |= (*codep++ & 0xff) << 16;
14493   a |= (*codep++ & 0xffu) << 24;
14494   b = *codep++ & 0xff;
14495   b |= (*codep++ & 0xff) << 8;
14496   b |= (*codep++ & 0xff) << 16;
14497   b |= (*codep++ & 0xffu) << 24;
14498   x = a + ((bfd_vma) b << 32);
14499 #else
14500   abort ();
14501   x = 0;
14502 #endif
14503   return x;
14504 }
14505
14506 static bfd_signed_vma
14507 get32 (void)
14508 {
14509   bfd_signed_vma x = 0;
14510
14511   FETCH_DATA (the_info, codep + 4);
14512   x = *codep++ & (bfd_signed_vma) 0xff;
14513   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14514   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14515   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14516   return x;
14517 }
14518
14519 static bfd_signed_vma
14520 get32s (void)
14521 {
14522   bfd_signed_vma x = 0;
14523
14524   FETCH_DATA (the_info, codep + 4);
14525   x = *codep++ & (bfd_signed_vma) 0xff;
14526   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14527   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14528   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14529
14530   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14531
14532   return x;
14533 }
14534
14535 static int
14536 get16 (void)
14537 {
14538   int x = 0;
14539
14540   FETCH_DATA (the_info, codep + 2);
14541   x = *codep++ & 0xff;
14542   x |= (*codep++ & 0xff) << 8;
14543   return x;
14544 }
14545
14546 static void
14547 set_op (bfd_vma op, int riprel)
14548 {
14549   op_index[op_ad] = op_ad;
14550   if (address_mode == mode_64bit)
14551     {
14552       op_address[op_ad] = op;
14553       op_riprel[op_ad] = riprel;
14554     }
14555   else
14556     {
14557       /* Mask to get a 32-bit address.  */
14558       op_address[op_ad] = op & 0xffffffff;
14559       op_riprel[op_ad] = riprel & 0xffffffff;
14560     }
14561 }
14562
14563 static void
14564 OP_REG (int code, int sizeflag)
14565 {
14566   const char *s;
14567   int add;
14568
14569   switch (code)
14570     {
14571     case es_reg: case ss_reg: case cs_reg:
14572     case ds_reg: case fs_reg: case gs_reg:
14573       oappend (names_seg[code - es_reg]);
14574       return;
14575     }
14576
14577   USED_REX (REX_B);
14578   if (rex & REX_B)
14579     add = 8;
14580   else
14581     add = 0;
14582
14583   switch (code)
14584     {
14585     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14586     case sp_reg: case bp_reg: case si_reg: case di_reg:
14587       s = names16[code - ax_reg + add];
14588       break;
14589     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14590     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14591       USED_REX (0);
14592       if (rex)
14593         s = names8rex[code - al_reg + add];
14594       else
14595         s = names8[code - al_reg];
14596       break;
14597     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14598     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14599       if (address_mode == mode_64bit
14600           && ((sizeflag & DFLAG) || (rex & REX_W)))
14601         {
14602           s = names64[code - rAX_reg + add];
14603           break;
14604         }
14605       code += eAX_reg - rAX_reg;
14606       /* Fall through.  */
14607     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14608     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14609       USED_REX (REX_W);
14610       if (rex & REX_W)
14611         s = names64[code - eAX_reg + add];
14612       else
14613         {
14614           if (sizeflag & DFLAG)
14615             s = names32[code - eAX_reg + add];
14616           else
14617             s = names16[code - eAX_reg + add];
14618           used_prefixes |= (prefixes & PREFIX_DATA);
14619         }
14620       break;
14621     default:
14622       s = INTERNAL_DISASSEMBLER_ERROR;
14623       break;
14624     }
14625   oappend (s);
14626 }
14627
14628 static void
14629 OP_IMREG (int code, int sizeflag)
14630 {
14631   const char *s;
14632
14633   switch (code)
14634     {
14635     case indir_dx_reg:
14636       if (intel_syntax)
14637         s = "dx";
14638       else
14639         s = "(%dx)";
14640       break;
14641     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14642     case sp_reg: case bp_reg: case si_reg: case di_reg:
14643       s = names16[code - ax_reg];
14644       break;
14645     case es_reg: case ss_reg: case cs_reg:
14646     case ds_reg: case fs_reg: case gs_reg:
14647       s = names_seg[code - es_reg];
14648       break;
14649     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14650     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14651       USED_REX (0);
14652       if (rex)
14653         s = names8rex[code - al_reg];
14654       else
14655         s = names8[code - al_reg];
14656       break;
14657     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14658     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14659       USED_REX (REX_W);
14660       if (rex & REX_W)
14661         s = names64[code - eAX_reg];
14662       else
14663         {
14664           if (sizeflag & DFLAG)
14665             s = names32[code - eAX_reg];
14666           else
14667             s = names16[code - eAX_reg];
14668           used_prefixes |= (prefixes & PREFIX_DATA);
14669         }
14670       break;
14671     case z_mode_ax_reg:
14672       if ((rex & REX_W) || (sizeflag & DFLAG))
14673         s = *names32;
14674       else
14675         s = *names16;
14676       if (!(rex & REX_W))
14677         used_prefixes |= (prefixes & PREFIX_DATA);
14678       break;
14679     default:
14680       s = INTERNAL_DISASSEMBLER_ERROR;
14681       break;
14682     }
14683   oappend (s);
14684 }
14685
14686 static void
14687 OP_I (int bytemode, int sizeflag)
14688 {
14689   bfd_signed_vma op;
14690   bfd_signed_vma mask = -1;
14691
14692   switch (bytemode)
14693     {
14694     case b_mode:
14695       FETCH_DATA (the_info, codep + 1);
14696       op = *codep++;
14697       mask = 0xff;
14698       break;
14699     case v_mode:
14700       USED_REX (REX_W);
14701       if (rex & REX_W)
14702         op = get32s ();
14703       else
14704         {
14705           if (sizeflag & DFLAG)
14706             {
14707               op = get32 ();
14708               mask = 0xffffffff;
14709             }
14710           else
14711             {
14712               op = get16 ();
14713               mask = 0xfffff;
14714             }
14715           used_prefixes |= (prefixes & PREFIX_DATA);
14716         }
14717       break;
14718     case d_mode:
14719       mask = 0xffffffff;
14720       op = get32 ();
14721       break;
14722     case w_mode:
14723       mask = 0xfffff;
14724       op = get16 ();
14725       break;
14726     case const_1_mode:
14727       if (intel_syntax)
14728         oappend ("1");
14729       return;
14730     default:
14731       oappend (INTERNAL_DISASSEMBLER_ERROR);
14732       return;
14733     }
14734
14735   op &= mask;
14736   scratchbuf[0] = '$';
14737   print_operand_value (scratchbuf + 1, 1, op);
14738   oappend_maybe_intel (scratchbuf);
14739   scratchbuf[0] = '\0';
14740 }
14741
14742 static void
14743 OP_I64 (int bytemode, int sizeflag)
14744 {
14745   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14746     {
14747       OP_I (bytemode, sizeflag);
14748       return;
14749     }
14750
14751   USED_REX (REX_W);
14752
14753   scratchbuf[0] = '$';
14754   print_operand_value (scratchbuf + 1, 1, get64 ());
14755   oappend_maybe_intel (scratchbuf);
14756   scratchbuf[0] = '\0';
14757 }
14758
14759 static void
14760 OP_sI (int bytemode, int sizeflag)
14761 {
14762   bfd_signed_vma op;
14763
14764   switch (bytemode)
14765     {
14766     case b_mode:
14767     case b_T_mode:
14768       FETCH_DATA (the_info, codep + 1);
14769       op = *codep++;
14770       if ((op & 0x80) != 0)
14771         op -= 0x100;
14772       if (bytemode == b_T_mode)
14773         {
14774           if (address_mode != mode_64bit
14775               || !((sizeflag & DFLAG) || (rex & REX_W)))
14776             {
14777               /* The operand-size prefix is overridden by a REX prefix.  */
14778               if ((sizeflag & DFLAG) || (rex & REX_W))
14779                 op &= 0xffffffff;
14780               else
14781                 op &= 0xffff;
14782           }
14783         }
14784       else
14785         {
14786           if (!(rex & REX_W))
14787             {
14788               if (sizeflag & DFLAG)
14789                 op &= 0xffffffff;
14790               else
14791                 op &= 0xffff;
14792             }
14793         }
14794       break;
14795     case v_mode:
14796       /* The operand-size prefix is overridden by a REX prefix.  */
14797       if ((sizeflag & DFLAG) || (rex & REX_W))
14798         op = get32s ();
14799       else
14800         op = get16 ();
14801       break;
14802     default:
14803       oappend (INTERNAL_DISASSEMBLER_ERROR);
14804       return;
14805     }
14806
14807   scratchbuf[0] = '$';
14808   print_operand_value (scratchbuf + 1, 1, op);
14809   oappend_maybe_intel (scratchbuf);
14810 }
14811
14812 static void
14813 OP_J (int bytemode, int sizeflag)
14814 {
14815   bfd_vma disp;
14816   bfd_vma mask = -1;
14817   bfd_vma segment = 0;
14818
14819   switch (bytemode)
14820     {
14821     case b_mode:
14822       FETCH_DATA (the_info, codep + 1);
14823       disp = *codep++;
14824       if ((disp & 0x80) != 0)
14825         disp -= 0x100;
14826       break;
14827     case v_mode:
14828       if (isa64 == amd64)
14829         USED_REX (REX_W);
14830       if ((sizeflag & DFLAG)
14831           || (address_mode == mode_64bit
14832               && (isa64 != amd64 || (rex & REX_W))))
14833         disp = get32s ();
14834       else
14835         {
14836           disp = get16 ();
14837           if ((disp & 0x8000) != 0)
14838             disp -= 0x10000;
14839           /* In 16bit mode, address is wrapped around at 64k within
14840              the same segment.  Otherwise, a data16 prefix on a jump
14841              instruction means that the pc is masked to 16 bits after
14842              the displacement is added!  */
14843           mask = 0xffff;
14844           if ((prefixes & PREFIX_DATA) == 0)
14845             segment = ((start_pc + (codep - start_codep))
14846                        & ~((bfd_vma) 0xffff));
14847         }
14848       if (address_mode != mode_64bit
14849           || (isa64 == amd64 && !(rex & REX_W)))
14850         used_prefixes |= (prefixes & PREFIX_DATA);
14851       break;
14852     default:
14853       oappend (INTERNAL_DISASSEMBLER_ERROR);
14854       return;
14855     }
14856   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14857   set_op (disp, 0);
14858   print_operand_value (scratchbuf, 1, disp);
14859   oappend (scratchbuf);
14860 }
14861
14862 static void
14863 OP_SEG (int bytemode, int sizeflag)
14864 {
14865   if (bytemode == w_mode)
14866     oappend (names_seg[modrm.reg]);
14867   else
14868     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14869 }
14870
14871 static void
14872 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14873 {
14874   int seg, offset;
14875
14876   if (sizeflag & DFLAG)
14877     {
14878       offset = get32 ();
14879       seg = get16 ();
14880     }
14881   else
14882     {
14883       offset = get16 ();
14884       seg = get16 ();
14885     }
14886   used_prefixes |= (prefixes & PREFIX_DATA);
14887   if (intel_syntax)
14888     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14889   else
14890     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14891   oappend (scratchbuf);
14892 }
14893
14894 static void
14895 OP_OFF (int bytemode, int sizeflag)
14896 {
14897   bfd_vma off;
14898
14899   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14900     intel_operand_size (bytemode, sizeflag);
14901   append_seg ();
14902
14903   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14904     off = get32 ();
14905   else
14906     off = get16 ();
14907
14908   if (intel_syntax)
14909     {
14910       if (!active_seg_prefix)
14911         {
14912           oappend (names_seg[ds_reg - es_reg]);
14913           oappend (":");
14914         }
14915     }
14916   print_operand_value (scratchbuf, 1, off);
14917   oappend (scratchbuf);
14918 }
14919
14920 static void
14921 OP_OFF64 (int bytemode, int sizeflag)
14922 {
14923   bfd_vma off;
14924
14925   if (address_mode != mode_64bit
14926       || (prefixes & PREFIX_ADDR))
14927     {
14928       OP_OFF (bytemode, sizeflag);
14929       return;
14930     }
14931
14932   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14933     intel_operand_size (bytemode, sizeflag);
14934   append_seg ();
14935
14936   off = get64 ();
14937
14938   if (intel_syntax)
14939     {
14940       if (!active_seg_prefix)
14941         {
14942           oappend (names_seg[ds_reg - es_reg]);
14943           oappend (":");
14944         }
14945     }
14946   print_operand_value (scratchbuf, 1, off);
14947   oappend (scratchbuf);
14948 }
14949
14950 static void
14951 ptr_reg (int code, int sizeflag)
14952 {
14953   const char *s;
14954
14955   *obufp++ = open_char;
14956   used_prefixes |= (prefixes & PREFIX_ADDR);
14957   if (address_mode == mode_64bit)
14958     {
14959       if (!(sizeflag & AFLAG))
14960         s = names32[code - eAX_reg];
14961       else
14962         s = names64[code - eAX_reg];
14963     }
14964   else if (sizeflag & AFLAG)
14965     s = names32[code - eAX_reg];
14966   else
14967     s = names16[code - eAX_reg];
14968   oappend (s);
14969   *obufp++ = close_char;
14970   *obufp = 0;
14971 }
14972
14973 static void
14974 OP_ESreg (int code, int sizeflag)
14975 {
14976   if (intel_syntax)
14977     {
14978       switch (codep[-1])
14979         {
14980         case 0x6d:      /* insw/insl */
14981           intel_operand_size (z_mode, sizeflag);
14982           break;
14983         case 0xa5:      /* movsw/movsl/movsq */
14984         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14985         case 0xab:      /* stosw/stosl */
14986         case 0xaf:      /* scasw/scasl */
14987           intel_operand_size (v_mode, sizeflag);
14988           break;
14989         default:
14990           intel_operand_size (b_mode, sizeflag);
14991         }
14992     }
14993   oappend_maybe_intel ("%es:");
14994   ptr_reg (code, sizeflag);
14995 }
14996
14997 static void
14998 OP_DSreg (int code, int sizeflag)
14999 {
15000   if (intel_syntax)
15001     {
15002       switch (codep[-1])
15003         {
15004         case 0x6f:      /* outsw/outsl */
15005           intel_operand_size (z_mode, sizeflag);
15006           break;
15007         case 0xa5:      /* movsw/movsl/movsq */
15008         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15009         case 0xad:      /* lodsw/lodsl/lodsq */
15010           intel_operand_size (v_mode, sizeflag);
15011           break;
15012         default:
15013           intel_operand_size (b_mode, sizeflag);
15014         }
15015     }
15016   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15017      default segment register DS is printed.  */
15018   if (!active_seg_prefix)
15019     active_seg_prefix = PREFIX_DS;
15020   append_seg ();
15021   ptr_reg (code, sizeflag);
15022 }
15023
15024 static void
15025 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15026 {
15027   int add;
15028   if (rex & REX_R)
15029     {
15030       USED_REX (REX_R);
15031       add = 8;
15032     }
15033   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15034     {
15035       all_prefixes[last_lock_prefix] = 0;
15036       used_prefixes |= PREFIX_LOCK;
15037       add = 8;
15038     }
15039   else
15040     add = 0;
15041   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15042   oappend_maybe_intel (scratchbuf);
15043 }
15044
15045 static void
15046 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15047 {
15048   int add;
15049   USED_REX (REX_R);
15050   if (rex & REX_R)
15051     add = 8;
15052   else
15053     add = 0;
15054   if (intel_syntax)
15055     sprintf (scratchbuf, "db%d", modrm.reg + add);
15056   else
15057     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15058   oappend (scratchbuf);
15059 }
15060
15061 static void
15062 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15063 {
15064   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15065   oappend_maybe_intel (scratchbuf);
15066 }
15067
15068 static void
15069 OP_R (int bytemode, int sizeflag)
15070 {
15071   /* Skip mod/rm byte.  */
15072   MODRM_CHECK;
15073   codep++;
15074   OP_E_register (bytemode, sizeflag);
15075 }
15076
15077 static void
15078 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15079 {
15080   int reg = modrm.reg;
15081   const char **names;
15082
15083   used_prefixes |= (prefixes & PREFIX_DATA);
15084   if (prefixes & PREFIX_DATA)
15085     {
15086       names = names_xmm;
15087       USED_REX (REX_R);
15088       if (rex & REX_R)
15089         reg += 8;
15090     }
15091   else
15092     names = names_mm;
15093   oappend (names[reg]);
15094 }
15095
15096 static void
15097 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15098 {
15099   int reg = modrm.reg;
15100   const char **names;
15101
15102   USED_REX (REX_R);
15103   if (rex & REX_R)
15104     reg += 8;
15105   if (vex.evex)
15106     {
15107       if (!vex.r)
15108         reg += 16;
15109     }
15110
15111   if (need_vex
15112       && bytemode != xmm_mode
15113       && bytemode != xmmq_mode
15114       && bytemode != evex_half_bcst_xmmq_mode
15115       && bytemode != ymm_mode
15116       && bytemode != scalar_mode)
15117     {
15118       switch (vex.length)
15119         {
15120         case 128:
15121           names = names_xmm;
15122           break;
15123         case 256:
15124           if (vex.w
15125               || (bytemode != vex_vsib_q_w_dq_mode
15126                   && bytemode != vex_vsib_q_w_d_mode))
15127             names = names_ymm;
15128           else
15129             names = names_xmm;
15130           break;
15131         case 512:
15132           names = names_zmm;
15133           break;
15134         default:
15135           abort ();
15136         }
15137     }
15138   else if (bytemode == xmmq_mode
15139            || bytemode == evex_half_bcst_xmmq_mode)
15140     {
15141       switch (vex.length)
15142         {
15143         case 128:
15144         case 256:
15145           names = names_xmm;
15146           break;
15147         case 512:
15148           names = names_ymm;
15149           break;
15150         default:
15151           abort ();
15152         }
15153     }
15154   else if (bytemode == ymm_mode)
15155     names = names_ymm;
15156   else
15157     names = names_xmm;
15158   oappend (names[reg]);
15159 }
15160
15161 static void
15162 OP_EM (int bytemode, int sizeflag)
15163 {
15164   int reg;
15165   const char **names;
15166
15167   if (modrm.mod != 3)
15168     {
15169       if (intel_syntax
15170           && (bytemode == v_mode || bytemode == v_swap_mode))
15171         {
15172           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15173           used_prefixes |= (prefixes & PREFIX_DATA);
15174         }
15175       OP_E (bytemode, sizeflag);
15176       return;
15177     }
15178
15179   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15180     swap_operand ();
15181
15182   /* Skip mod/rm byte.  */
15183   MODRM_CHECK;
15184   codep++;
15185   used_prefixes |= (prefixes & PREFIX_DATA);
15186   reg = modrm.rm;
15187   if (prefixes & PREFIX_DATA)
15188     {
15189       names = names_xmm;
15190       USED_REX (REX_B);
15191       if (rex & REX_B)
15192         reg += 8;
15193     }
15194   else
15195     names = names_mm;
15196   oappend (names[reg]);
15197 }
15198
15199 /* cvt* are the only instructions in sse2 which have
15200    both SSE and MMX operands and also have 0x66 prefix
15201    in their opcode. 0x66 was originally used to differentiate
15202    between SSE and MMX instruction(operands). So we have to handle the
15203    cvt* separately using OP_EMC and OP_MXC */
15204 static void
15205 OP_EMC (int bytemode, int sizeflag)
15206 {
15207   if (modrm.mod != 3)
15208     {
15209       if (intel_syntax && bytemode == v_mode)
15210         {
15211           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15212           used_prefixes |= (prefixes & PREFIX_DATA);
15213         }
15214       OP_E (bytemode, sizeflag);
15215       return;
15216     }
15217
15218   /* Skip mod/rm byte.  */
15219   MODRM_CHECK;
15220   codep++;
15221   used_prefixes |= (prefixes & PREFIX_DATA);
15222   oappend (names_mm[modrm.rm]);
15223 }
15224
15225 static void
15226 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15227 {
15228   used_prefixes |= (prefixes & PREFIX_DATA);
15229   oappend (names_mm[modrm.reg]);
15230 }
15231
15232 static void
15233 OP_EX (int bytemode, int sizeflag)
15234 {
15235   int reg;
15236   const char **names;
15237
15238   /* Skip mod/rm byte.  */
15239   MODRM_CHECK;
15240   codep++;
15241
15242   if (modrm.mod != 3)
15243     {
15244       OP_E_memory (bytemode, sizeflag);
15245       return;
15246     }
15247
15248   reg = modrm.rm;
15249   USED_REX (REX_B);
15250   if (rex & REX_B)
15251     reg += 8;
15252   if (vex.evex)
15253     {
15254       USED_REX (REX_X);
15255       if ((rex & REX_X))
15256         reg += 16;
15257     }
15258
15259   if ((sizeflag & SUFFIX_ALWAYS)
15260       && (bytemode == x_swap_mode
15261           || bytemode == d_swap_mode
15262           || bytemode == d_scalar_swap_mode
15263           || bytemode == q_swap_mode
15264           || bytemode == q_scalar_swap_mode))
15265     swap_operand ();
15266
15267   if (need_vex
15268       && bytemode != xmm_mode
15269       && bytemode != xmmdw_mode
15270       && bytemode != xmmqd_mode
15271       && bytemode != xmm_mb_mode
15272       && bytemode != xmm_mw_mode
15273       && bytemode != xmm_md_mode
15274       && bytemode != xmm_mq_mode
15275       && bytemode != xmm_mdq_mode
15276       && bytemode != xmmq_mode
15277       && bytemode != evex_half_bcst_xmmq_mode
15278       && bytemode != ymm_mode
15279       && bytemode != d_scalar_mode
15280       && bytemode != d_scalar_swap_mode
15281       && bytemode != q_scalar_mode
15282       && bytemode != q_scalar_swap_mode
15283       && bytemode != vex_scalar_w_dq_mode)
15284     {
15285       switch (vex.length)
15286         {
15287         case 128:
15288           names = names_xmm;
15289           break;
15290         case 256:
15291           names = names_ymm;
15292           break;
15293         case 512:
15294           names = names_zmm;
15295           break;
15296         default:
15297           abort ();
15298         }
15299     }
15300   else if (bytemode == xmmq_mode
15301            || bytemode == evex_half_bcst_xmmq_mode)
15302     {
15303       switch (vex.length)
15304         {
15305         case 128:
15306         case 256:
15307           names = names_xmm;
15308           break;
15309         case 512:
15310           names = names_ymm;
15311           break;
15312         default:
15313           abort ();
15314         }
15315     }
15316   else if (bytemode == ymm_mode)
15317     names = names_ymm;
15318   else
15319     names = names_xmm;
15320   oappend (names[reg]);
15321 }
15322
15323 static void
15324 OP_MS (int bytemode, int sizeflag)
15325 {
15326   if (modrm.mod == 3)
15327     OP_EM (bytemode, sizeflag);
15328   else
15329     BadOp ();
15330 }
15331
15332 static void
15333 OP_XS (int bytemode, int sizeflag)
15334 {
15335   if (modrm.mod == 3)
15336     OP_EX (bytemode, sizeflag);
15337   else
15338     BadOp ();
15339 }
15340
15341 static void
15342 OP_M (int bytemode, int sizeflag)
15343 {
15344   if (modrm.mod == 3)
15345     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15346     BadOp ();
15347   else
15348     OP_E (bytemode, sizeflag);
15349 }
15350
15351 static void
15352 OP_0f07 (int bytemode, int sizeflag)
15353 {
15354   if (modrm.mod != 3 || modrm.rm != 0)
15355     BadOp ();
15356   else
15357     OP_E (bytemode, sizeflag);
15358 }
15359
15360 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15361    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15362
15363 static void
15364 NOP_Fixup1 (int bytemode, int sizeflag)
15365 {
15366   if ((prefixes & PREFIX_DATA) != 0
15367       || (rex != 0
15368           && rex != 0x48
15369           && address_mode == mode_64bit))
15370     OP_REG (bytemode, sizeflag);
15371   else
15372     strcpy (obuf, "nop");
15373 }
15374
15375 static void
15376 NOP_Fixup2 (int bytemode, int sizeflag)
15377 {
15378   if ((prefixes & PREFIX_DATA) != 0
15379       || (rex != 0
15380           && rex != 0x48
15381           && address_mode == mode_64bit))
15382     OP_IMREG (bytemode, sizeflag);
15383 }
15384
15385 static const char *const Suffix3DNow[] = {
15386 /* 00 */        NULL,           NULL,           NULL,           NULL,
15387 /* 04 */        NULL,           NULL,           NULL,           NULL,
15388 /* 08 */        NULL,           NULL,           NULL,           NULL,
15389 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15390 /* 10 */        NULL,           NULL,           NULL,           NULL,
15391 /* 14 */        NULL,           NULL,           NULL,           NULL,
15392 /* 18 */        NULL,           NULL,           NULL,           NULL,
15393 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15394 /* 20 */        NULL,           NULL,           NULL,           NULL,
15395 /* 24 */        NULL,           NULL,           NULL,           NULL,
15396 /* 28 */        NULL,           NULL,           NULL,           NULL,
15397 /* 2C */        NULL,           NULL,           NULL,           NULL,
15398 /* 30 */        NULL,           NULL,           NULL,           NULL,
15399 /* 34 */        NULL,           NULL,           NULL,           NULL,
15400 /* 38 */        NULL,           NULL,           NULL,           NULL,
15401 /* 3C */        NULL,           NULL,           NULL,           NULL,
15402 /* 40 */        NULL,           NULL,           NULL,           NULL,
15403 /* 44 */        NULL,           NULL,           NULL,           NULL,
15404 /* 48 */        NULL,           NULL,           NULL,           NULL,
15405 /* 4C */        NULL,           NULL,           NULL,           NULL,
15406 /* 50 */        NULL,           NULL,           NULL,           NULL,
15407 /* 54 */        NULL,           NULL,           NULL,           NULL,
15408 /* 58 */        NULL,           NULL,           NULL,           NULL,
15409 /* 5C */        NULL,           NULL,           NULL,           NULL,
15410 /* 60 */        NULL,           NULL,           NULL,           NULL,
15411 /* 64 */        NULL,           NULL,           NULL,           NULL,
15412 /* 68 */        NULL,           NULL,           NULL,           NULL,
15413 /* 6C */        NULL,           NULL,           NULL,           NULL,
15414 /* 70 */        NULL,           NULL,           NULL,           NULL,
15415 /* 74 */        NULL,           NULL,           NULL,           NULL,
15416 /* 78 */        NULL,           NULL,           NULL,           NULL,
15417 /* 7C */        NULL,           NULL,           NULL,           NULL,
15418 /* 80 */        NULL,           NULL,           NULL,           NULL,
15419 /* 84 */        NULL,           NULL,           NULL,           NULL,
15420 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15421 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15422 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15423 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15424 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15425 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15426 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15427 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15428 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15429 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15430 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15431 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15432 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15433 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15434 /* C0 */        NULL,           NULL,           NULL,           NULL,
15435 /* C4 */        NULL,           NULL,           NULL,           NULL,
15436 /* C8 */        NULL,           NULL,           NULL,           NULL,
15437 /* CC */        NULL,           NULL,           NULL,           NULL,
15438 /* D0 */        NULL,           NULL,           NULL,           NULL,
15439 /* D4 */        NULL,           NULL,           NULL,           NULL,
15440 /* D8 */        NULL,           NULL,           NULL,           NULL,
15441 /* DC */        NULL,           NULL,           NULL,           NULL,
15442 /* E0 */        NULL,           NULL,           NULL,           NULL,
15443 /* E4 */        NULL,           NULL,           NULL,           NULL,
15444 /* E8 */        NULL,           NULL,           NULL,           NULL,
15445 /* EC */        NULL,           NULL,           NULL,           NULL,
15446 /* F0 */        NULL,           NULL,           NULL,           NULL,
15447 /* F4 */        NULL,           NULL,           NULL,           NULL,
15448 /* F8 */        NULL,           NULL,           NULL,           NULL,
15449 /* FC */        NULL,           NULL,           NULL,           NULL,
15450 };
15451
15452 static void
15453 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15454 {
15455   const char *mnemonic;
15456
15457   FETCH_DATA (the_info, codep + 1);
15458   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15459      place where an 8-bit immediate would normally go.  ie. the last
15460      byte of the instruction.  */
15461   obufp = mnemonicendp;
15462   mnemonic = Suffix3DNow[*codep++ & 0xff];
15463   if (mnemonic)
15464     oappend (mnemonic);
15465   else
15466     {
15467       /* Since a variable sized modrm/sib chunk is between the start
15468          of the opcode (0x0f0f) and the opcode suffix, we need to do
15469          all the modrm processing first, and don't know until now that
15470          we have a bad opcode.  This necessitates some cleaning up.  */
15471       op_out[0][0] = '\0';
15472       op_out[1][0] = '\0';
15473       BadOp ();
15474     }
15475   mnemonicendp = obufp;
15476 }
15477
15478 static struct op simd_cmp_op[] =
15479 {
15480   { STRING_COMMA_LEN ("eq") },
15481   { STRING_COMMA_LEN ("lt") },
15482   { STRING_COMMA_LEN ("le") },
15483   { STRING_COMMA_LEN ("unord") },
15484   { STRING_COMMA_LEN ("neq") },
15485   { STRING_COMMA_LEN ("nlt") },
15486   { STRING_COMMA_LEN ("nle") },
15487   { STRING_COMMA_LEN ("ord") }
15488 };
15489
15490 static void
15491 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15492 {
15493   unsigned int cmp_type;
15494
15495   FETCH_DATA (the_info, codep + 1);
15496   cmp_type = *codep++ & 0xff;
15497   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15498     {
15499       char suffix [3];
15500       char *p = mnemonicendp - 2;
15501       suffix[0] = p[0];
15502       suffix[1] = p[1];
15503       suffix[2] = '\0';
15504       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15505       mnemonicendp += simd_cmp_op[cmp_type].len;
15506     }
15507   else
15508     {
15509       /* We have a reserved extension byte.  Output it directly.  */
15510       scratchbuf[0] = '$';
15511       print_operand_value (scratchbuf + 1, 1, cmp_type);
15512       oappend_maybe_intel (scratchbuf);
15513       scratchbuf[0] = '\0';
15514     }
15515 }
15516
15517 static void
15518 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15519 {
15520   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15521   if (!intel_syntax)
15522     {
15523       const char **names = (address_mode == mode_64bit
15524                             ? names64 : names32);
15525       strcpy (op_out[0], names[0]);
15526       strcpy (op_out[1], names[1]);
15527       if (bytemode == eBX_reg)
15528         strcpy (op_out[2], names[3]);
15529       two_source_ops = 1;
15530     }
15531   /* Skip mod/rm byte.  */
15532   MODRM_CHECK;
15533   codep++;
15534 }
15535
15536 static void
15537 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15538             int sizeflag ATTRIBUTE_UNUSED)
15539 {
15540   /* monitor %eax,%ecx,%edx"  */
15541   if (!intel_syntax)
15542     {
15543       const char **op1_names;
15544       const char **names = (address_mode == mode_64bit
15545                             ? names64 : names32);
15546
15547       if (!(prefixes & PREFIX_ADDR))
15548         op1_names = (address_mode == mode_16bit
15549                      ? names16 : names);
15550       else
15551         {
15552           /* Remove "addr16/addr32".  */
15553           all_prefixes[last_addr_prefix] = 0;
15554           op1_names = (address_mode != mode_32bit
15555                        ? names32 : names16);
15556           used_prefixes |= PREFIX_ADDR;
15557         }
15558       strcpy (op_out[0], op1_names[0]);
15559       strcpy (op_out[1], names[1]);
15560       strcpy (op_out[2], names[2]);
15561       two_source_ops = 1;
15562     }
15563   /* Skip mod/rm byte.  */
15564   MODRM_CHECK;
15565   codep++;
15566 }
15567
15568 static void
15569 BadOp (void)
15570 {
15571   /* Throw away prefixes and 1st. opcode byte.  */
15572   codep = insn_codep + 1;
15573   oappend ("(bad)");
15574 }
15575
15576 static void
15577 REP_Fixup (int bytemode, int sizeflag)
15578 {
15579   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15580      lods and stos.  */
15581   if (prefixes & PREFIX_REPZ)
15582     all_prefixes[last_repz_prefix] = REP_PREFIX;
15583
15584   switch (bytemode)
15585     {
15586     case al_reg:
15587     case eAX_reg:
15588     case indir_dx_reg:
15589       OP_IMREG (bytemode, sizeflag);
15590       break;
15591     case eDI_reg:
15592       OP_ESreg (bytemode, sizeflag);
15593       break;
15594     case eSI_reg:
15595       OP_DSreg (bytemode, sizeflag);
15596       break;
15597     default:
15598       abort ();
15599       break;
15600     }
15601 }
15602
15603 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15604    "bnd".  */
15605
15606 static void
15607 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15608 {
15609   if (prefixes & PREFIX_REPNZ)
15610     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15611 }
15612
15613 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15614    "notrack".  */
15615
15616 static void
15617 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15618                int sizeflag ATTRIBUTE_UNUSED)
15619 {
15620   if (active_seg_prefix == PREFIX_DS
15621       && (address_mode != mode_64bit || last_data_prefix < 0))
15622     {
15623       /* NOTRACK prefix is only valid on indirect branch instructions.
15624          NB: DATA prefix is unsupported for Intel64.  */
15625       active_seg_prefix = 0;
15626       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15627     }
15628 }
15629
15630 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15631    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15632  */
15633
15634 static void
15635 HLE_Fixup1 (int bytemode, int sizeflag)
15636 {
15637   if (modrm.mod != 3
15638       && (prefixes & PREFIX_LOCK) != 0)
15639     {
15640       if (prefixes & PREFIX_REPZ)
15641         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15642       if (prefixes & PREFIX_REPNZ)
15643         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15644     }
15645
15646   OP_E (bytemode, sizeflag);
15647 }
15648
15649 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15650    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15651  */
15652
15653 static void
15654 HLE_Fixup2 (int bytemode, int sizeflag)
15655 {
15656   if (modrm.mod != 3)
15657     {
15658       if (prefixes & PREFIX_REPZ)
15659         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15660       if (prefixes & PREFIX_REPNZ)
15661         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15662     }
15663
15664   OP_E (bytemode, sizeflag);
15665 }
15666
15667 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15668    "xrelease" for memory operand.  No check for LOCK prefix.   */
15669
15670 static void
15671 HLE_Fixup3 (int bytemode, int sizeflag)
15672 {
15673   if (modrm.mod != 3
15674       && last_repz_prefix > last_repnz_prefix
15675       && (prefixes & PREFIX_REPZ) != 0)
15676     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15677
15678   OP_E (bytemode, sizeflag);
15679 }
15680
15681 static void
15682 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15683 {
15684   USED_REX (REX_W);
15685   if (rex & REX_W)
15686     {
15687       /* Change cmpxchg8b to cmpxchg16b.  */
15688       char *p = mnemonicendp - 2;
15689       mnemonicendp = stpcpy (p, "16b");
15690       bytemode = o_mode;
15691     }
15692   else if ((prefixes & PREFIX_LOCK) != 0)
15693     {
15694       if (prefixes & PREFIX_REPZ)
15695         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15696       if (prefixes & PREFIX_REPNZ)
15697         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15698     }
15699
15700   OP_M (bytemode, sizeflag);
15701 }
15702
15703 static void
15704 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15705 {
15706   const char **names;
15707
15708   if (need_vex)
15709     {
15710       switch (vex.length)
15711         {
15712         case 128:
15713           names = names_xmm;
15714           break;
15715         case 256:
15716           names = names_ymm;
15717           break;
15718         default:
15719           abort ();
15720         }
15721     }
15722   else
15723     names = names_xmm;
15724   oappend (names[reg]);
15725 }
15726
15727 static void
15728 CRC32_Fixup (int bytemode, int sizeflag)
15729 {
15730   /* Add proper suffix to "crc32".  */
15731   char *p = mnemonicendp;
15732
15733   switch (bytemode)
15734     {
15735     case b_mode:
15736       if (intel_syntax)
15737         goto skip;
15738
15739       *p++ = 'b';
15740       break;
15741     case v_mode:
15742       if (intel_syntax)
15743         goto skip;
15744
15745       USED_REX (REX_W);
15746       if (rex & REX_W)
15747         *p++ = 'q';
15748       else
15749         {
15750           if (sizeflag & DFLAG)
15751             *p++ = 'l';
15752           else
15753             *p++ = 'w';
15754           used_prefixes |= (prefixes & PREFIX_DATA);
15755         }
15756       break;
15757     default:
15758       oappend (INTERNAL_DISASSEMBLER_ERROR);
15759       break;
15760     }
15761   mnemonicendp = p;
15762   *p = '\0';
15763
15764 skip:
15765   if (modrm.mod == 3)
15766     {
15767       int add;
15768
15769       /* Skip mod/rm byte.  */
15770       MODRM_CHECK;
15771       codep++;
15772
15773       USED_REX (REX_B);
15774       add = (rex & REX_B) ? 8 : 0;
15775       if (bytemode == b_mode)
15776         {
15777           USED_REX (0);
15778           if (rex)
15779             oappend (names8rex[modrm.rm + add]);
15780           else
15781             oappend (names8[modrm.rm + add]);
15782         }
15783       else
15784         {
15785           USED_REX (REX_W);
15786           if (rex & REX_W)
15787             oappend (names64[modrm.rm + add]);
15788           else if ((prefixes & PREFIX_DATA))
15789             oappend (names16[modrm.rm + add]);
15790           else
15791             oappend (names32[modrm.rm + add]);
15792         }
15793     }
15794   else
15795     OP_E (bytemode, sizeflag);
15796 }
15797
15798 static void
15799 FXSAVE_Fixup (int bytemode, int sizeflag)
15800 {
15801   /* Add proper suffix to "fxsave" and "fxrstor".  */
15802   USED_REX (REX_W);
15803   if (rex & REX_W)
15804     {
15805       char *p = mnemonicendp;
15806       *p++ = '6';
15807       *p++ = '4';
15808       *p = '\0';
15809       mnemonicendp = p;
15810     }
15811   OP_M (bytemode, sizeflag);
15812 }
15813
15814 static void
15815 PCMPESTR_Fixup (int bytemode, int sizeflag)
15816 {
15817   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15818   if (!intel_syntax)
15819     {
15820       char *p = mnemonicendp;
15821
15822       USED_REX (REX_W);
15823       if (rex & REX_W)
15824         *p++ = 'q';
15825       else if (sizeflag & SUFFIX_ALWAYS)
15826         *p++ = 'l';
15827
15828       *p = '\0';
15829       mnemonicendp = p;
15830     }
15831
15832   OP_EX (bytemode, sizeflag);
15833 }
15834
15835 /* Display the destination register operand for instructions with
15836    VEX. */
15837
15838 static void
15839 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15840 {
15841   int reg;
15842   const char **names;
15843
15844   if (!need_vex)
15845     abort ();
15846
15847   if (!need_vex_reg)
15848     return;
15849
15850   reg = vex.register_specifier;
15851   vex.register_specifier = 0;
15852   if (address_mode != mode_64bit)
15853     reg &= 7;
15854   else if (vex.evex && !vex.v)
15855     reg += 16;
15856
15857   if (bytemode == vex_scalar_mode)
15858     {
15859       oappend (names_xmm[reg]);
15860       return;
15861     }
15862
15863   switch (vex.length)
15864     {
15865     case 128:
15866       switch (bytemode)
15867         {
15868         case vex_mode:
15869         case vex128_mode:
15870         case vex_vsib_q_w_dq_mode:
15871         case vex_vsib_q_w_d_mode:
15872           names = names_xmm;
15873           break;
15874         case dq_mode:
15875           if (rex & REX_W)
15876             names = names64;
15877           else
15878             names = names32;
15879           break;
15880         case mask_bd_mode:
15881         case mask_mode:
15882           if (reg > 0x7)
15883             {
15884               oappend ("(bad)");
15885               return;
15886             }
15887           names = names_mask;
15888           break;
15889         default:
15890           abort ();
15891           return;
15892         }
15893       break;
15894     case 256:
15895       switch (bytemode)
15896         {
15897         case vex_mode:
15898         case vex256_mode:
15899           names = names_ymm;
15900           break;
15901         case vex_vsib_q_w_dq_mode:
15902         case vex_vsib_q_w_d_mode:
15903           names = vex.w ? names_ymm : names_xmm;
15904           break;
15905         case mask_bd_mode:
15906         case mask_mode:
15907           if (reg > 0x7)
15908             {
15909               oappend ("(bad)");
15910               return;
15911             }
15912           names = names_mask;
15913           break;
15914         default:
15915           /* See PR binutils/20893 for a reproducer.  */
15916           oappend ("(bad)");
15917           return;
15918         }
15919       break;
15920     case 512:
15921       names = names_zmm;
15922       break;
15923     default:
15924       abort ();
15925       break;
15926     }
15927   oappend (names[reg]);
15928 }
15929
15930 /* Get the VEX immediate byte without moving codep.  */
15931
15932 static unsigned char
15933 get_vex_imm8 (int sizeflag, int opnum)
15934 {
15935   int bytes_before_imm = 0;
15936
15937   if (modrm.mod != 3)
15938     {
15939       /* There are SIB/displacement bytes.  */
15940       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15941         {
15942           /* 32/64 bit address mode */
15943           int base = modrm.rm;
15944
15945           /* Check SIB byte.  */
15946           if (base == 4)
15947             {
15948               FETCH_DATA (the_info, codep + 1);
15949               base = *codep & 7;
15950               /* When decoding the third source, don't increase
15951                  bytes_before_imm as this has already been incremented
15952                  by one in OP_E_memory while decoding the second
15953                  source operand.  */
15954               if (opnum == 0)
15955                 bytes_before_imm++;
15956             }
15957
15958           /* Don't increase bytes_before_imm when decoding the third source,
15959              it has already been incremented by OP_E_memory while decoding
15960              the second source operand.  */
15961           if (opnum == 0)
15962             {
15963               switch (modrm.mod)
15964                 {
15965                   case 0:
15966                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15967                        SIB == 5, there is a 4 byte displacement.  */
15968                     if (base != 5)
15969                       /* No displacement. */
15970                       break;
15971                     /* Fall through.  */
15972                   case 2:
15973                     /* 4 byte displacement.  */
15974                     bytes_before_imm += 4;
15975                     break;
15976                   case 1:
15977                     /* 1 byte displacement.  */
15978                     bytes_before_imm++;
15979                     break;
15980                 }
15981             }
15982         }
15983       else
15984         {
15985           /* 16 bit address mode */
15986           /* Don't increase bytes_before_imm when decoding the third source,
15987              it has already been incremented by OP_E_memory while decoding
15988              the second source operand.  */
15989           if (opnum == 0)
15990             {
15991               switch (modrm.mod)
15992                 {
15993                 case 0:
15994                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
15995                   if (modrm.rm != 6)
15996                     /* No displacement. */
15997                     break;
15998                   /* Fall through.  */
15999                 case 2:
16000                   /* 2 byte displacement.  */
16001                   bytes_before_imm += 2;
16002                   break;
16003                 case 1:
16004                   /* 1 byte displacement: when decoding the third source,
16005                      don't increase bytes_before_imm as this has already
16006                      been incremented by one in OP_E_memory while decoding
16007                      the second source operand.  */
16008                   if (opnum == 0)
16009                     bytes_before_imm++;
16010
16011                   break;
16012                 }
16013             }
16014         }
16015     }
16016
16017   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16018   return codep [bytes_before_imm];
16019 }
16020
16021 static void
16022 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16023 {
16024   const char **names;
16025
16026   if (reg == -1 && modrm.mod != 3)
16027     {
16028       OP_E_memory (bytemode, sizeflag);
16029       return;
16030     }
16031   else
16032     {
16033       if (reg == -1)
16034         {
16035           reg = modrm.rm;
16036           USED_REX (REX_B);
16037           if (rex & REX_B)
16038             reg += 8;
16039         }
16040       if (address_mode != mode_64bit)
16041         reg &= 7;
16042     }
16043
16044   switch (vex.length)
16045     {
16046     case 128:
16047       names = names_xmm;
16048       break;
16049     case 256:
16050       names = names_ymm;
16051       break;
16052     default:
16053       abort ();
16054     }
16055   oappend (names[reg]);
16056 }
16057
16058 static void
16059 OP_EX_VexImmW (int bytemode, int sizeflag)
16060 {
16061   int reg = -1;
16062   static unsigned char vex_imm8;
16063
16064   if (vex_w_done == 0)
16065     {
16066       vex_w_done = 1;
16067
16068       /* Skip mod/rm byte.  */
16069       MODRM_CHECK;
16070       codep++;
16071
16072       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16073
16074       if (vex.w)
16075           reg = vex_imm8 >> 4;
16076
16077       OP_EX_VexReg (bytemode, sizeflag, reg);
16078     }
16079   else if (vex_w_done == 1)
16080     {
16081       vex_w_done = 2;
16082
16083       if (!vex.w)
16084           reg = vex_imm8 >> 4;
16085
16086       OP_EX_VexReg (bytemode, sizeflag, reg);
16087     }
16088   else
16089     {
16090       /* Output the imm8 directly.  */
16091       scratchbuf[0] = '$';
16092       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16093       oappend_maybe_intel (scratchbuf);
16094       scratchbuf[0] = '\0';
16095       codep++;
16096     }
16097 }
16098
16099 static void
16100 OP_Vex_2src (int bytemode, int sizeflag)
16101 {
16102   if (modrm.mod == 3)
16103     {
16104       int reg = modrm.rm;
16105       USED_REX (REX_B);
16106       if (rex & REX_B)
16107         reg += 8;
16108       oappend (names_xmm[reg]);
16109     }
16110   else
16111     {
16112       if (intel_syntax
16113           && (bytemode == v_mode || bytemode == v_swap_mode))
16114         {
16115           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16116           used_prefixes |= (prefixes & PREFIX_DATA);
16117         }
16118       OP_E (bytemode, sizeflag);
16119     }
16120 }
16121
16122 static void
16123 OP_Vex_2src_1 (int bytemode, int sizeflag)
16124 {
16125   if (modrm.mod == 3)
16126     {
16127       /* Skip mod/rm byte.   */
16128       MODRM_CHECK;
16129       codep++;
16130     }
16131
16132   if (vex.w)
16133     {
16134       unsigned int reg = vex.register_specifier;
16135       vex.register_specifier = 0;
16136
16137       if (address_mode != mode_64bit)
16138         reg &= 7;
16139       oappend (names_xmm[reg]);
16140     }
16141   else
16142     OP_Vex_2src (bytemode, sizeflag);
16143 }
16144
16145 static void
16146 OP_Vex_2src_2 (int bytemode, int sizeflag)
16147 {
16148   if (vex.w)
16149     OP_Vex_2src (bytemode, sizeflag);
16150   else
16151     {
16152       unsigned int reg = vex.register_specifier;
16153       vex.register_specifier = 0;
16154
16155       if (address_mode != mode_64bit)
16156         reg &= 7;
16157       oappend (names_xmm[reg]);
16158     }
16159 }
16160
16161 static void
16162 OP_EX_VexW (int bytemode, int sizeflag)
16163 {
16164   int reg = -1;
16165
16166   if (!vex_w_done)
16167     {
16168       /* Skip mod/rm byte.  */
16169       MODRM_CHECK;
16170       codep++;
16171
16172       if (vex.w)
16173         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16174     }
16175   else
16176     {
16177       if (!vex.w)
16178         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16179     }
16180
16181   OP_EX_VexReg (bytemode, sizeflag, reg);
16182
16183   if (vex_w_done)
16184     codep++;
16185   vex_w_done = 1;
16186 }
16187
16188 static void
16189 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16190 {
16191   int reg;
16192   const char **names;
16193
16194   FETCH_DATA (the_info, codep + 1);
16195   reg = *codep++;
16196
16197   if (bytemode != x_mode)
16198     abort ();
16199
16200   reg >>= 4;
16201   if (address_mode != mode_64bit)
16202     reg &= 7;
16203
16204   switch (vex.length)
16205     {
16206     case 128:
16207       names = names_xmm;
16208       break;
16209     case 256:
16210       names = names_ymm;
16211       break;
16212     default:
16213       abort ();
16214     }
16215   oappend (names[reg]);
16216 }
16217
16218 static void
16219 OP_XMM_VexW (int bytemode, int sizeflag)
16220 {
16221   /* Turn off the REX.W bit since it is used for swapping operands
16222      now.  */
16223   rex &= ~REX_W;
16224   OP_XMM (bytemode, sizeflag);
16225 }
16226
16227 static void
16228 OP_EX_Vex (int bytemode, int sizeflag)
16229 {
16230   if (modrm.mod != 3)
16231     need_vex_reg = 0;
16232   OP_EX (bytemode, sizeflag);
16233 }
16234
16235 static void
16236 OP_XMM_Vex (int bytemode, int sizeflag)
16237 {
16238   if (modrm.mod != 3)
16239     need_vex_reg = 0;
16240   OP_XMM (bytemode, sizeflag);
16241 }
16242
16243 static struct op vex_cmp_op[] =
16244 {
16245   { STRING_COMMA_LEN ("eq") },
16246   { STRING_COMMA_LEN ("lt") },
16247   { STRING_COMMA_LEN ("le") },
16248   { STRING_COMMA_LEN ("unord") },
16249   { STRING_COMMA_LEN ("neq") },
16250   { STRING_COMMA_LEN ("nlt") },
16251   { STRING_COMMA_LEN ("nle") },
16252   { STRING_COMMA_LEN ("ord") },
16253   { STRING_COMMA_LEN ("eq_uq") },
16254   { STRING_COMMA_LEN ("nge") },
16255   { STRING_COMMA_LEN ("ngt") },
16256   { STRING_COMMA_LEN ("false") },
16257   { STRING_COMMA_LEN ("neq_oq") },
16258   { STRING_COMMA_LEN ("ge") },
16259   { STRING_COMMA_LEN ("gt") },
16260   { STRING_COMMA_LEN ("true") },
16261   { STRING_COMMA_LEN ("eq_os") },
16262   { STRING_COMMA_LEN ("lt_oq") },
16263   { STRING_COMMA_LEN ("le_oq") },
16264   { STRING_COMMA_LEN ("unord_s") },
16265   { STRING_COMMA_LEN ("neq_us") },
16266   { STRING_COMMA_LEN ("nlt_uq") },
16267   { STRING_COMMA_LEN ("nle_uq") },
16268   { STRING_COMMA_LEN ("ord_s") },
16269   { STRING_COMMA_LEN ("eq_us") },
16270   { STRING_COMMA_LEN ("nge_uq") },
16271   { STRING_COMMA_LEN ("ngt_uq") },
16272   { STRING_COMMA_LEN ("false_os") },
16273   { STRING_COMMA_LEN ("neq_os") },
16274   { STRING_COMMA_LEN ("ge_oq") },
16275   { STRING_COMMA_LEN ("gt_oq") },
16276   { STRING_COMMA_LEN ("true_us") },
16277 };
16278
16279 static void
16280 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16281 {
16282   unsigned int cmp_type;
16283
16284   FETCH_DATA (the_info, codep + 1);
16285   cmp_type = *codep++ & 0xff;
16286   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16287     {
16288       char suffix [3];
16289       char *p = mnemonicendp - 2;
16290       suffix[0] = p[0];
16291       suffix[1] = p[1];
16292       suffix[2] = '\0';
16293       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16294       mnemonicendp += vex_cmp_op[cmp_type].len;
16295     }
16296   else
16297     {
16298       /* We have a reserved extension byte.  Output it directly.  */
16299       scratchbuf[0] = '$';
16300       print_operand_value (scratchbuf + 1, 1, cmp_type);
16301       oappend_maybe_intel (scratchbuf);
16302       scratchbuf[0] = '\0';
16303     }
16304 }
16305
16306 static void
16307 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16308              int sizeflag ATTRIBUTE_UNUSED)
16309 {
16310   unsigned int cmp_type;
16311
16312   if (!vex.evex)
16313     abort ();
16314
16315   FETCH_DATA (the_info, codep + 1);
16316   cmp_type = *codep++ & 0xff;
16317   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16318      If it's the case, print suffix, otherwise - print the immediate.  */
16319   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16320       && cmp_type != 3
16321       && cmp_type != 7)
16322     {
16323       char suffix [3];
16324       char *p = mnemonicendp - 2;
16325
16326       /* vpcmp* can have both one- and two-lettered suffix.  */
16327       if (p[0] == 'p')
16328         {
16329           p++;
16330           suffix[0] = p[0];
16331           suffix[1] = '\0';
16332         }
16333       else
16334         {
16335           suffix[0] = p[0];
16336           suffix[1] = p[1];
16337           suffix[2] = '\0';
16338         }
16339
16340       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16341       mnemonicendp += simd_cmp_op[cmp_type].len;
16342     }
16343   else
16344     {
16345       /* We have a reserved extension byte.  Output it directly.  */
16346       scratchbuf[0] = '$';
16347       print_operand_value (scratchbuf + 1, 1, cmp_type);
16348       oappend_maybe_intel (scratchbuf);
16349       scratchbuf[0] = '\0';
16350     }
16351 }
16352
16353 static const struct op xop_cmp_op[] =
16354 {
16355   { STRING_COMMA_LEN ("lt") },
16356   { STRING_COMMA_LEN ("le") },
16357   { STRING_COMMA_LEN ("gt") },
16358   { STRING_COMMA_LEN ("ge") },
16359   { STRING_COMMA_LEN ("eq") },
16360   { STRING_COMMA_LEN ("neq") },
16361   { STRING_COMMA_LEN ("false") },
16362   { STRING_COMMA_LEN ("true") }
16363 };
16364
16365 static void
16366 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16367              int sizeflag ATTRIBUTE_UNUSED)
16368 {
16369   unsigned int cmp_type;
16370
16371   FETCH_DATA (the_info, codep + 1);
16372   cmp_type = *codep++ & 0xff;
16373   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16374     {
16375       char suffix[3];
16376       char *p = mnemonicendp - 2;
16377
16378       /* vpcom* can have both one- and two-lettered suffix.  */
16379       if (p[0] == 'm')
16380         {
16381           p++;
16382           suffix[0] = p[0];
16383           suffix[1] = '\0';
16384         }
16385       else
16386         {
16387           suffix[0] = p[0];
16388           suffix[1] = p[1];
16389           suffix[2] = '\0';
16390         }
16391
16392       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16393       mnemonicendp += xop_cmp_op[cmp_type].len;
16394     }
16395   else
16396     {
16397       /* We have a reserved extension byte.  Output it directly.  */
16398       scratchbuf[0] = '$';
16399       print_operand_value (scratchbuf + 1, 1, cmp_type);
16400       oappend_maybe_intel (scratchbuf);
16401       scratchbuf[0] = '\0';
16402     }
16403 }
16404
16405 static const struct op pclmul_op[] =
16406 {
16407   { STRING_COMMA_LEN ("lql") },
16408   { STRING_COMMA_LEN ("hql") },
16409   { STRING_COMMA_LEN ("lqh") },
16410   { STRING_COMMA_LEN ("hqh") }
16411 };
16412
16413 static void
16414 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16415               int sizeflag ATTRIBUTE_UNUSED)
16416 {
16417   unsigned int pclmul_type;
16418
16419   FETCH_DATA (the_info, codep + 1);
16420   pclmul_type = *codep++ & 0xff;
16421   switch (pclmul_type)
16422     {
16423     case 0x10:
16424       pclmul_type = 2;
16425       break;
16426     case 0x11:
16427       pclmul_type = 3;
16428       break;
16429     default:
16430       break;
16431     }
16432   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16433     {
16434       char suffix [4];
16435       char *p = mnemonicendp - 3;
16436       suffix[0] = p[0];
16437       suffix[1] = p[1];
16438       suffix[2] = p[2];
16439       suffix[3] = '\0';
16440       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16441       mnemonicendp += pclmul_op[pclmul_type].len;
16442     }
16443   else
16444     {
16445       /* We have a reserved extension byte.  Output it directly.  */
16446       scratchbuf[0] = '$';
16447       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16448       oappend_maybe_intel (scratchbuf);
16449       scratchbuf[0] = '\0';
16450     }
16451 }
16452
16453 static void
16454 MOVBE_Fixup (int bytemode, int sizeflag)
16455 {
16456   /* Add proper suffix to "movbe".  */
16457   char *p = mnemonicendp;
16458
16459   switch (bytemode)
16460     {
16461     case v_mode:
16462       if (intel_syntax)
16463         goto skip;
16464
16465       USED_REX (REX_W);
16466       if (sizeflag & SUFFIX_ALWAYS)
16467         {
16468           if (rex & REX_W)
16469             *p++ = 'q';
16470           else
16471             {
16472               if (sizeflag & DFLAG)
16473                 *p++ = 'l';
16474               else
16475                 *p++ = 'w';
16476               used_prefixes |= (prefixes & PREFIX_DATA);
16477             }
16478         }
16479       break;
16480     default:
16481       oappend (INTERNAL_DISASSEMBLER_ERROR);
16482       break;
16483     }
16484   mnemonicendp = p;
16485   *p = '\0';
16486
16487 skip:
16488   OP_M (bytemode, sizeflag);
16489 }
16490
16491 static void
16492 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16493 {
16494   int reg;
16495   const char **names;
16496
16497   /* Skip mod/rm byte.  */
16498   MODRM_CHECK;
16499   codep++;
16500
16501   if (rex & REX_W)
16502     names = names64;
16503   else
16504     names = names32;
16505
16506   reg = modrm.rm;
16507   USED_REX (REX_B);
16508   if (rex & REX_B)
16509     reg += 8;
16510
16511   oappend (names[reg]);
16512 }
16513
16514 static void
16515 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16516 {
16517   const char **names;
16518   unsigned int reg = vex.register_specifier;
16519   vex.register_specifier = 0;
16520
16521   if (rex & REX_W)
16522     names = names64;
16523   else
16524     names = names32;
16525
16526   if (address_mode != mode_64bit)
16527     reg &= 7;
16528   oappend (names[reg]);
16529 }
16530
16531 static void
16532 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16533 {
16534   if (!vex.evex
16535       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16536     abort ();
16537
16538   USED_REX (REX_R);
16539   if ((rex & REX_R) != 0 || !vex.r)
16540     {
16541       BadOp ();
16542       return;
16543     }
16544
16545   oappend (names_mask [modrm.reg]);
16546 }
16547
16548 static void
16549 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16550 {
16551   if (!vex.evex
16552       || (bytemode != evex_rounding_mode
16553           && bytemode != evex_rounding_64_mode
16554           && bytemode != evex_sae_mode))
16555     abort ();
16556   if (modrm.mod == 3 && vex.b)
16557     switch (bytemode)
16558       {
16559       case evex_rounding_64_mode:
16560         if (address_mode != mode_64bit)
16561           {
16562             oappend ("(bad)");
16563             break;
16564           }
16565         /* Fall through.  */
16566       case evex_rounding_mode:
16567         oappend (names_rounding[vex.ll]);
16568         break;
16569       case evex_sae_mode:
16570         oappend ("{sae}");
16571         break;
16572       default:
16573         break;
16574       }
16575 }