opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void BND_Fixup (int, int);
 111 static void NOTRACK_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void PCMPESTR_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define EbndS { OP_E, bnd_swap_mode }
 250 #define Ev { OP_E, v_mode }
 251 #define Eva { OP_E, va_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mv_bnd { OP_M, v_bndmk_mode }
 275 #define Mx { OP_M, x_mode }
 276 #define Mxmm { OP_M, xmm_mode }
 277 #define Gb { OP_G, b_mode }
 278 #define Gbnd { OP_G, bnd_mode }
 279 #define Gv { OP_G, v_mode }
 280 #define Gd { OP_G, d_mode }
 281 #define Gdq { OP_G, dq_mode }
 282 #define Gm { OP_G, m_mode }
 283 #define Gva { OP_G, va_mode }
 284 #define Gw { OP_G, w_mode }
 285 #define Rd { OP_R, d_mode }
 286 #define Rdq { OP_R, dq_mode }
 287 #define Rm { OP_R, m_mode }
 288 #define Ib { OP_I, b_mode }
 289 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 290 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 291 #define Iv { OP_I, v_mode }
 292 #define sIv { OP_sI, v_mode }
 293 #define Iv64 { OP_I64, v_mode }
 294 #define Id { OP_I, d_mode }
 295 #define Iw { OP_I, w_mode }
 296 #define I1 { OP_I, const_1_mode }
 297 #define Jb { OP_J, b_mode }
 298 #define Jv { OP_J, v_mode }
 299 #define Cm { OP_C, m_mode }
 300 #define Dm { OP_D, m_mode }
 301 #define Td { OP_T, d_mode }
 302 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 303
 304 #define RMeAX { OP_REG, eAX_reg }
 305 #define RMeBX { OP_REG, eBX_reg }
 306 #define RMeCX { OP_REG, eCX_reg }
 307 #define RMeDX { OP_REG, eDX_reg }
 308 #define RMeSP { OP_REG, eSP_reg }
 309 #define RMeBP { OP_REG, eBP_reg }
 310 #define RMeSI { OP_REG, eSI_reg }
 311 #define RMeDI { OP_REG, eDI_reg }
 312 #define RMrAX { OP_REG, rAX_reg }
 313 #define RMrBX { OP_REG, rBX_reg }
 314 #define RMrCX { OP_REG, rCX_reg }
 315 #define RMrDX { OP_REG, rDX_reg }
 316 #define RMrSP { OP_REG, rSP_reg }
 317 #define RMrBP { OP_REG, rBP_reg }
 318 #define RMrSI { OP_REG, rSI_reg }
 319 #define RMrDI { OP_REG, rDI_reg }
 320 #define RMAL { OP_REG, al_reg }
 321 #define RMCL { OP_REG, cl_reg }
 322 #define RMDL { OP_REG, dl_reg }
 323 #define RMBL { OP_REG, bl_reg }
 324 #define RMAH { OP_REG, ah_reg }
 325 #define RMCH { OP_REG, ch_reg }
 326 #define RMDH { OP_REG, dh_reg }
 327 #define RMBH { OP_REG, bh_reg }
 328 #define RMAX { OP_REG, ax_reg }
 329 #define RMDX { OP_REG, dx_reg }
 330
 331 #define eAX { OP_IMREG, eAX_reg }
 332 #define eBX { OP_IMREG, eBX_reg }
 333 #define eCX { OP_IMREG, eCX_reg }
 334 #define eDX { OP_IMREG, eDX_reg }
 335 #define eSP { OP_IMREG, eSP_reg }
 336 #define eBP { OP_IMREG, eBP_reg }
 337 #define eSI { OP_IMREG, eSI_reg }
 338 #define eDI { OP_IMREG, eDI_reg }
 339 #define AL { OP_IMREG, al_reg }
 340 #define CL { OP_IMREG, cl_reg }
 341 #define DL { OP_IMREG, dl_reg }
 342 #define BL { OP_IMREG, bl_reg }
 343 #define AH { OP_IMREG, ah_reg }
 344 #define CH { OP_IMREG, ch_reg }
 345 #define DH { OP_IMREG, dh_reg }
 346 #define BH { OP_IMREG, bh_reg }
 347 #define AX { OP_IMREG, ax_reg }
 348 #define DX { OP_IMREG, dx_reg }
 349 #define zAX { OP_IMREG, z_mode_ax_reg }
 350 #define indirDX { OP_IMREG, indir_dx_reg }
 351
 352 #define Sw { OP_SEG, w_mode }
 353 #define Sv { OP_SEG, v_mode }
 354 #define Ap { OP_DIR, 0 }
 355 #define Ob { OP_OFF64, b_mode }
 356 #define Ov { OP_OFF64, v_mode }
 357 #define Xb { OP_DSreg, eSI_reg }
 358 #define Xv { OP_DSreg, eSI_reg }
 359 #define Xz { OP_DSreg, eSI_reg }
 360 #define Yb { OP_ESreg, eDI_reg }
 361 #define Yv { OP_ESreg, eDI_reg }
 362 #define DSBX { OP_DSreg, eBX_reg }
 363
 364 #define es { OP_REG, es_reg }
 365 #define ss { OP_REG, ss_reg }
 366 #define cs { OP_REG, cs_reg }
 367 #define ds { OP_REG, ds_reg }
 368 #define fs { OP_REG, fs_reg }
 369 #define gs { OP_REG, gs_reg }
 370
 371 #define MX { OP_MMX, 0 }
 372 #define XM { OP_XMM, 0 }
 373 #define XMScalar { OP_XMM, scalar_mode }
 374 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 375 #define XMM { OP_XMM, xmm_mode }
 376 #define XMxmmq { OP_XMM, xmmq_mode }
 377 #define EM { OP_EM, v_mode }
 378 #define EMS { OP_EM, v_swap_mode }
 379 #define EMd { OP_EM, d_mode }
 380 #define EMx { OP_EM, x_mode }
 381 #define EXbScalar { OP_EX, b_scalar_mode }
 382 #define EXw { OP_EX, w_mode }
 383 #define EXwScalar { OP_EX, w_scalar_mode }
 384 #define EXd { OP_EX, d_mode }
 385 #define EXdScalar { OP_EX, d_scalar_mode }
 386 #define EXdS { OP_EX, d_swap_mode }
 387 #define EXq { OP_EX, q_mode }
 388 #define EXqScalar { OP_EX, q_scalar_mode }
 389 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 390 #define EXqS { OP_EX, q_swap_mode }
 391 #define EXx { OP_EX, x_mode }
 392 #define EXxS { OP_EX, x_swap_mode }
 393 #define EXxmm { OP_EX, xmm_mode }
 394 #define EXymm { OP_EX, ymm_mode }
 395 #define EXxmmq { OP_EX, xmmq_mode }
 396 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 397 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 398 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 399 #define EXxmm_md { OP_EX, xmm_md_mode }
 400 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 401 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 402 #define EXxmmdw { OP_EX, xmmdw_mode }
 403 #define EXxmmqd { OP_EX, xmmqd_mode }
 404 #define EXymmq { OP_EX, ymmq_mode }
 405 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 406 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 407 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 408 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 409 #define MS { OP_MS, v_mode }
 410 #define XS { OP_XS, v_mode }
 411 #define EMCq { OP_EMC, q_mode }
 412 #define MXC { OP_MXC, 0 }
 413 #define OPSUF { OP_3DNowSuffix, 0 }
 414 #define CMP { CMP_Fixup, 0 }
 415 #define XMM0 { XMM_Fixup, 0 }
 416 #define FXSAVE { FXSAVE_Fixup, 0 }
 417 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 418 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 419
 420 #define Vex { OP_VEX, vex_mode }
 421 #define VexScalar { OP_VEX, vex_scalar_mode }
 422 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 423 #define Vex128 { OP_VEX, vex128_mode }
 424 #define Vex256 { OP_VEX, vex256_mode }
 425 #define VexGdq { OP_VEX, dq_mode }
 426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 428 #define EXVexW { OP_EX_VexW, x_mode }
 429 #define EXdVexW { OP_EX_VexW, d_mode }
 430 #define EXqVexW { OP_EX_VexW, q_mode }
 431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 432 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 433 #define XMVexW { OP_XMM_VexW, 0 }
 434 #define XMVexI4 { OP_REG_VexI4, x_mode }
 435 #define PCLMUL { PCLMUL_Fixup, 0 }
 436 #define VCMP { VCMP_Fixup, 0 }
 437 #define VPCMP { VPCMP_Fixup, 0 }
 438 #define VPCOM { VPCOM_Fixup, 0 }
 439
 440 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 441 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 443
 444 #define XMask { OP_Mask, mask_mode }
 445 #define MaskG { OP_G, mask_mode }
 446 #define MaskE { OP_E, mask_mode }
 447 #define MaskBDE { OP_E, mask_bd_mode }
 448 #define MaskR { OP_R, mask_mode }
 449 #define MaskVex { OP_VEX, mask_mode }
 450
 451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 455
 456 /* Used handle "rep" prefix for string instructions.  */
 457 #define Xbr { REP_Fixup, eSI_reg }
 458 #define Xvr { REP_Fixup, eSI_reg }
 459 #define Ybr { REP_Fixup, eDI_reg }
 460 #define Yvr { REP_Fixup, eDI_reg }
 461 #define Yzr { REP_Fixup, eDI_reg }
 462 #define indirDXr { REP_Fixup, indir_dx_reg }
 463 #define ALr { REP_Fixup, al_reg }
 464 #define eAXr { REP_Fixup, eAX_reg }
 465
 466 /* Used handle HLE prefix for lockable instructions.  */
 467 #define Ebh1 { HLE_Fixup1, b_mode }
 468 #define Evh1 { HLE_Fixup1, v_mode }
 469 #define Ebh2 { HLE_Fixup2, b_mode }
 470 #define Evh2 { HLE_Fixup2, v_mode }
 471 #define Ebh3 { HLE_Fixup3, b_mode }
 472 #define Evh3 { HLE_Fixup3, v_mode }
 473
 474 #define BND { BND_Fixup, 0 }
 475 #define NOTRACK { NOTRACK_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* operand size depends on address prefix */
 498   va_mode,
 499   /* word operand */
 500   w_mode,
 501   /* double word operand  */
 502   d_mode,
 503   /* double word operand with operand swapped */
 504   d_swap_mode,
 505   /* quad word operand */
 506   q_mode,
 507   /* quad word operand with operand swapped */
 508   q_swap_mode,
 509   /* ten-byte operand */
 510   t_mode,
 511   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 512      broadcast enabled.  */
 513   x_mode,
 514   /* Similar to x_mode, but with different EVEX mem shifts.  */
 515   evex_x_gscat_mode,
 516   /* Similar to x_mode, but with disabled broadcast.  */
 517   evex_x_nobcst_mode,
 518   /* Similar to x_mode, but with operands swapped and disabled broadcast
 519      in EVEX.  */
 520   x_swap_mode,
 521   /* 16-byte XMM operand */
 522   xmm_mode,
 523   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 524      memory operand (depending on vector length).  Broadcast isn't
 525      allowed.  */
 526   xmmq_mode,
 527   /* Same as xmmq_mode, but broadcast is allowed.  */
 528   evex_half_bcst_xmmq_mode,
 529   /* XMM register or byte memory operand */
 530   xmm_mb_mode,
 531   /* XMM register or word memory operand */
 532   xmm_mw_mode,
 533   /* XMM register or double word memory operand */
 534   xmm_md_mode,
 535   /* XMM register or quad word memory operand */
 536   xmm_mq_mode,
 537   /* XMM register or double/quad word memory operand, depending on
 538      VEX.W.  */
 539   xmm_mdq_mode,
 540   /* 16-byte XMM, word, double word or quad word operand.  */
 541   xmmdw_mode,
 542   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 543   xmmqd_mode,
 544   /* 32-byte YMM operand */
 545   ymm_mode,
 546   /* quad word, ymmword or zmmword memory operand.  */
 547   ymmq_mode,
 548   /* 32-byte YMM or 16-byte word operand */
 549   ymmxmm_mode,
 550   /* d_mode in 32bit, q_mode in 64bit mode.  */
 551   m_mode,
 552   /* pair of v_mode operands */
 553   a_mode,
 554   cond_jump_mode,
 555   loop_jcxz_mode,
 556   v_bnd_mode,
 557   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 558   v_bndmk_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode.  */
 562   dqw_mode,
 563   /* bounds operand */
 564   bnd_mode,
 565   /* bounds operand with operand swapped */
 566   bnd_swap_mode,
 567   /* 4- or 6-byte pointer operand */
 568   f_mode,
 569   const_1_mode,
 570   /* v_mode for indirect branch opcodes.  */
 571   indir_v_mode,
 572   /* v_mode for stack-related opcodes.  */
 573   stack_v_mode,
 574   /* non-quad operand size depends on prefixes */
 575   z_mode,
 576   /* 16-byte operand */
 577   o_mode,
 578   /* registers like dq_mode, memory like b_mode.  */
 579   dqb_mode,
 580   /* registers like d_mode, memory like b_mode.  */
 581   db_mode,
 582   /* registers like d_mode, memory like w_mode.  */
 583   dw_mode,
 584   /* registers like dq_mode, memory like d_mode.  */
 585   dqd_mode,
 586   /* normal vex mode */
 587   vex_mode,
 588   /* 128bit vex mode */
 589   vex128_mode,
 590   /* 256bit vex mode */
 591   vex256_mode,
 592   /* operand size depends on the VEX.W bit.  */
 593   vex_w_dq_mode,
 594
 595   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 596   vex_vsib_d_w_dq_mode,
 597   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 598   vex_vsib_d_w_d_mode,
 599   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 600   vex_vsib_q_w_dq_mode,
 601   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 602   vex_vsib_q_w_d_mode,
 603
 604   /* scalar, ignore vector length.  */
 605   scalar_mode,
 606   /* like b_mode, ignore vector length.  */
 607   b_scalar_mode,
 608   /* like w_mode, ignore vector length.  */
 609   w_scalar_mode,
 610   /* like d_mode, ignore vector length.  */
 611   d_scalar_mode,
 612   /* like d_swap_mode, ignore vector length.  */
 613   d_scalar_swap_mode,
 614   /* like q_mode, ignore vector length.  */
 615   q_scalar_mode,
 616   /* like q_swap_mode, ignore vector length.  */
 617   q_scalar_swap_mode,
 618   /* like vex_mode, ignore vector length.  */
 619   vex_scalar_mode,
 620   /* like vex_w_dq_mode, ignore vector length.  */
 621   vex_scalar_w_dq_mode,
 622
 623   /* Static rounding.  */
 624   evex_rounding_mode,
 625   /* Static rounding, 64-bit mode only.  */
 626   evex_rounding_64_mode,
 627   /* Supress all exceptions.  */
 628   evex_sae_mode,
 629
 630   /* Mask register operand.  */
 631   mask_mode,
 632   /* Mask register operand.  */
 633   mask_bd_mode,
 634
 635   es_reg,
 636   cs_reg,
 637   ss_reg,
 638   ds_reg,
 639   fs_reg,
 640   gs_reg,
 641
 642   eAX_reg,
 643   eCX_reg,
 644   eDX_reg,
 645   eBX_reg,
 646   eSP_reg,
 647   eBP_reg,
 648   eSI_reg,
 649   eDI_reg,
 650
 651   al_reg,
 652   cl_reg,
 653   dl_reg,
 654   bl_reg,
 655   ah_reg,
 656   ch_reg,
 657   dh_reg,
 658   bh_reg,
 659
 660   ax_reg,
 661   cx_reg,
 662   dx_reg,
 663   bx_reg,
 664   sp_reg,
 665   bp_reg,
 666   si_reg,
 667   di_reg,
 668
 669   rAX_reg,
 670   rCX_reg,
 671   rDX_reg,
 672   rBX_reg,
 673   rSP_reg,
 674   rBP_reg,
 675   rSI_reg,
 676   rDI_reg,
 677
 678   z_mode_ax_reg,
 679   indir_dx_reg
 680 };
 681
 682 enum
 683 {
 684   FLOATCODE = 1,
 685   USE_REG_TABLE,
 686   USE_MOD_TABLE,
 687   USE_RM_TABLE,
 688   USE_PREFIX_TABLE,
 689   USE_X86_64_TABLE,
 690   USE_3BYTE_TABLE,
 691   USE_XOP_8F_TABLE,
 692   USE_VEX_C4_TABLE,
 693   USE_VEX_C5_TABLE,
 694   USE_VEX_LEN_TABLE,
 695   USE_VEX_W_TABLE,
 696   USE_EVEX_TABLE,
 697   USE_EVEX_LEN_TABLE
 698 };
 699
 700 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 701
 702 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 703 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 704 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 705 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 706 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 707 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 708 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 709 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 710 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 711 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 712 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 713 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 714 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 715 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 716 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 717 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 718
 719 enum
 720 {
 721   REG_80 = 0,
 722   REG_81,
 723   REG_83,
 724   REG_8F,
 725   REG_C0,
 726   REG_C1,
 727   REG_C6,
 728   REG_C7,
 729   REG_D0,
 730   REG_D1,
 731   REG_D2,
 732   REG_D3,
 733   REG_F6,
 734   REG_F7,
 735   REG_FE,
 736   REG_FF,
 737   REG_0F00,
 738   REG_0F01,
 739   REG_0F0D,
 740   REG_0F18,
 741   REG_0F1C_P_0_MOD_0,
 742   REG_0F1E_P_1_MOD_3,
 743   REG_0F71,
 744   REG_0F72,
 745   REG_0F73,
 746   REG_0FA6,
 747   REG_0FA7,
 748   REG_0FAE,
 749   REG_0FBA,
 750   REG_0FC7,
 751   REG_VEX_0F71,
 752   REG_VEX_0F72,
 753   REG_VEX_0F73,
 754   REG_VEX_0FAE,
 755   REG_VEX_0F38F3,
 756   REG_XOP_LWPCB,
 757   REG_XOP_LWP,
 758   REG_XOP_TBM_01,
 759   REG_XOP_TBM_02,
 760
 761   REG_EVEX_0F71,
 762   REG_EVEX_0F72,
 763   REG_EVEX_0F73,
 764   REG_EVEX_0F38C6,
 765   REG_EVEX_0F38C7
 766 };
 767
 768 enum
 769 {
 770   MOD_8D = 0,
 771   MOD_C6_REG_7,
 772   MOD_C7_REG_7,
 773   MOD_FF_REG_3,
 774   MOD_FF_REG_5,
 775   MOD_0F01_REG_0,
 776   MOD_0F01_REG_1,
 777   MOD_0F01_REG_2,
 778   MOD_0F01_REG_3,
 779   MOD_0F01_REG_5,
 780   MOD_0F01_REG_7,
 781   MOD_0F12_PREFIX_0,
 782   MOD_0F13,
 783   MOD_0F16_PREFIX_0,
 784   MOD_0F17,
 785   MOD_0F18_REG_0,
 786   MOD_0F18_REG_1,
 787   MOD_0F18_REG_2,
 788   MOD_0F18_REG_3,
 789   MOD_0F18_REG_4,
 790   MOD_0F18_REG_5,
 791   MOD_0F18_REG_6,
 792   MOD_0F18_REG_7,
 793   MOD_0F1A_PREFIX_0,
 794   MOD_0F1B_PREFIX_0,
 795   MOD_0F1B_PREFIX_1,
 796   MOD_0F1C_PREFIX_0,
 797   MOD_0F1E_PREFIX_1,
 798   MOD_0F24,
 799   MOD_0F26,
 800   MOD_0F2B_PREFIX_0,
 801   MOD_0F2B_PREFIX_1,
 802   MOD_0F2B_PREFIX_2,
 803   MOD_0F2B_PREFIX_3,
 804   MOD_0F51,
 805   MOD_0F71_REG_2,
 806   MOD_0F71_REG_4,
 807   MOD_0F71_REG_6,
 808   MOD_0F72_REG_2,
 809   MOD_0F72_REG_4,
 810   MOD_0F72_REG_6,
 811   MOD_0F73_REG_2,
 812   MOD_0F73_REG_3,
 813   MOD_0F73_REG_6,
 814   MOD_0F73_REG_7,
 815   MOD_0FAE_REG_0,
 816   MOD_0FAE_REG_1,
 817   MOD_0FAE_REG_2,
 818   MOD_0FAE_REG_3,
 819   MOD_0FAE_REG_4,
 820   MOD_0FAE_REG_5,
 821   MOD_0FAE_REG_6,
 822   MOD_0FAE_REG_7,
 823   MOD_0FB2,
 824   MOD_0FB4,
 825   MOD_0FB5,
 826   MOD_0FC3,
 827   MOD_0FC7_REG_3,
 828   MOD_0FC7_REG_4,
 829   MOD_0FC7_REG_5,
 830   MOD_0FC7_REG_6,
 831   MOD_0FC7_REG_7,
 832   MOD_0FD7,
 833   MOD_0FE7_PREFIX_2,
 834   MOD_0FF0_PREFIX_3,
 835   MOD_0F382A_PREFIX_2,
 836   MOD_0F38F5_PREFIX_2,
 837   MOD_0F38F6_PREFIX_0,
 838   MOD_0F38F8_PREFIX_1,
 839   MOD_0F38F8_PREFIX_2,
 840   MOD_0F38F8_PREFIX_3,
 841   MOD_0F38F9_PREFIX_0,
 842   MOD_62_32BIT,
 843   MOD_C4_32BIT,
 844   MOD_C5_32BIT,
 845   MOD_VEX_0F12_PREFIX_0,
 846   MOD_VEX_0F13,
 847   MOD_VEX_0F16_PREFIX_0,
 848   MOD_VEX_0F17,
 849   MOD_VEX_0F2B,
 850   MOD_VEX_W_0_0F41_P_0_LEN_1,
 851   MOD_VEX_W_1_0F41_P_0_LEN_1,
 852   MOD_VEX_W_0_0F41_P_2_LEN_1,
 853   MOD_VEX_W_1_0F41_P_2_LEN_1,
 854   MOD_VEX_W_0_0F42_P_0_LEN_1,
 855   MOD_VEX_W_1_0F42_P_0_LEN_1,
 856   MOD_VEX_W_0_0F42_P_2_LEN_1,
 857   MOD_VEX_W_1_0F42_P_2_LEN_1,
 858   MOD_VEX_W_0_0F44_P_0_LEN_1,
 859   MOD_VEX_W_1_0F44_P_0_LEN_1,
 860   MOD_VEX_W_0_0F44_P_2_LEN_1,
 861   MOD_VEX_W_1_0F44_P_2_LEN_1,
 862   MOD_VEX_W_0_0F45_P_0_LEN_1,
 863   MOD_VEX_W_1_0F45_P_0_LEN_1,
 864   MOD_VEX_W_0_0F45_P_2_LEN_1,
 865   MOD_VEX_W_1_0F45_P_2_LEN_1,
 866   MOD_VEX_W_0_0F46_P_0_LEN_1,
 867   MOD_VEX_W_1_0F46_P_0_LEN_1,
 868   MOD_VEX_W_0_0F46_P_2_LEN_1,
 869   MOD_VEX_W_1_0F46_P_2_LEN_1,
 870   MOD_VEX_W_0_0F47_P_0_LEN_1,
 871   MOD_VEX_W_1_0F47_P_0_LEN_1,
 872   MOD_VEX_W_0_0F47_P_2_LEN_1,
 873   MOD_VEX_W_1_0F47_P_2_LEN_1,
 874   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 875   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 876   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 877   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 878   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 879   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 880   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 881   MOD_VEX_0F50,
 882   MOD_VEX_0F71_REG_2,
 883   MOD_VEX_0F71_REG_4,
 884   MOD_VEX_0F71_REG_6,
 885   MOD_VEX_0F72_REG_2,
 886   MOD_VEX_0F72_REG_4,
 887   MOD_VEX_0F72_REG_6,
 888   MOD_VEX_0F73_REG_2,
 889   MOD_VEX_0F73_REG_3,
 890   MOD_VEX_0F73_REG_6,
 891   MOD_VEX_0F73_REG_7,
 892   MOD_VEX_W_0_0F91_P_0_LEN_0,
 893   MOD_VEX_W_1_0F91_P_0_LEN_0,
 894   MOD_VEX_W_0_0F91_P_2_LEN_0,
 895   MOD_VEX_W_1_0F91_P_2_LEN_0,
 896   MOD_VEX_W_0_0F92_P_0_LEN_0,
 897   MOD_VEX_W_0_0F92_P_2_LEN_0,
 898   MOD_VEX_0F92_P_3_LEN_0,
 899   MOD_VEX_W_0_0F93_P_0_LEN_0,
 900   MOD_VEX_W_0_0F93_P_2_LEN_0,
 901   MOD_VEX_0F93_P_3_LEN_0,
 902   MOD_VEX_W_0_0F98_P_0_LEN_0,
 903   MOD_VEX_W_1_0F98_P_0_LEN_0,
 904   MOD_VEX_W_0_0F98_P_2_LEN_0,
 905   MOD_VEX_W_1_0F98_P_2_LEN_0,
 906   MOD_VEX_W_0_0F99_P_0_LEN_0,
 907   MOD_VEX_W_1_0F99_P_0_LEN_0,
 908   MOD_VEX_W_0_0F99_P_2_LEN_0,
 909   MOD_VEX_W_1_0F99_P_2_LEN_0,
 910   MOD_VEX_0FAE_REG_2,
 911   MOD_VEX_0FAE_REG_3,
 912   MOD_VEX_0FD7_PREFIX_2,
 913   MOD_VEX_0FE7_PREFIX_2,
 914   MOD_VEX_0FF0_PREFIX_3,
 915   MOD_VEX_0F381A_PREFIX_2,
 916   MOD_VEX_0F382A_PREFIX_2,
 917   MOD_VEX_0F382C_PREFIX_2,
 918   MOD_VEX_0F382D_PREFIX_2,
 919   MOD_VEX_0F382E_PREFIX_2,
 920   MOD_VEX_0F382F_PREFIX_2,
 921   MOD_VEX_0F385A_PREFIX_2,
 922   MOD_VEX_0F388C_PREFIX_2,
 923   MOD_VEX_0F388E_PREFIX_2,
 924   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 925   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 926   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 927   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 928   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 929   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 930   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 931   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 932
 933   MOD_EVEX_0F12_PREFIX_0,
 934   MOD_EVEX_0F16_PREFIX_0,
 935   MOD_EVEX_0F38C6_REG_1,
 936   MOD_EVEX_0F38C6_REG_2,
 937   MOD_EVEX_0F38C6_REG_5,
 938   MOD_EVEX_0F38C6_REG_6,
 939   MOD_EVEX_0F38C7_REG_1,
 940   MOD_EVEX_0F38C7_REG_2,
 941   MOD_EVEX_0F38C7_REG_5,
 942   MOD_EVEX_0F38C7_REG_6
 943 };
 944
 945 enum
 946 {
 947   RM_C6_REG_7 = 0,
 948   RM_C7_REG_7,
 949   RM_0F01_REG_0,
 950   RM_0F01_REG_1,
 951   RM_0F01_REG_2,
 952   RM_0F01_REG_3,
 953   RM_0F01_REG_5_MOD_3,
 954   RM_0F01_REG_7_MOD_3,
 955   RM_0F1E_P_1_MOD_3_REG_7,
 956   RM_0FAE_REG_6_MOD_3_P_0,
 957   RM_0FAE_REG_7_MOD_3,
 958 };
 959
 960 enum
 961 {
 962   PREFIX_90 = 0,
 963   PREFIX_0F01_REG_5_MOD_0,
 964   PREFIX_0F01_REG_5_MOD_3_RM_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_2,
 966   PREFIX_0F01_REG_7_MOD_3_RM_2,
 967   PREFIX_0F01_REG_7_MOD_3_RM_3,
 968   PREFIX_0F09,
 969   PREFIX_0F10,
 970   PREFIX_0F11,
 971   PREFIX_0F12,
 972   PREFIX_0F16,
 973   PREFIX_0F1A,
 974   PREFIX_0F1B,
 975   PREFIX_0F1C,
 976   PREFIX_0F1E,
 977   PREFIX_0F2A,
 978   PREFIX_0F2B,
 979   PREFIX_0F2C,
 980   PREFIX_0F2D,
 981   PREFIX_0F2E,
 982   PREFIX_0F2F,
 983   PREFIX_0F51,
 984   PREFIX_0F52,
 985   PREFIX_0F53,
 986   PREFIX_0F58,
 987   PREFIX_0F59,
 988   PREFIX_0F5A,
 989   PREFIX_0F5B,
 990   PREFIX_0F5C,
 991   PREFIX_0F5D,
 992   PREFIX_0F5E,
 993   PREFIX_0F5F,
 994   PREFIX_0F60,
 995   PREFIX_0F61,
 996   PREFIX_0F62,
 997   PREFIX_0F6C,
 998   PREFIX_0F6D,
 999   PREFIX_0F6F,
1000   PREFIX_0F70,
1001   PREFIX_0F73_REG_3,
1002   PREFIX_0F73_REG_7,
1003   PREFIX_0F78,
1004   PREFIX_0F79,
1005   PREFIX_0F7C,
1006   PREFIX_0F7D,
1007   PREFIX_0F7E,
1008   PREFIX_0F7F,
1009   PREFIX_0FAE_REG_0_MOD_3,
1010   PREFIX_0FAE_REG_1_MOD_3,
1011   PREFIX_0FAE_REG_2_MOD_3,
1012   PREFIX_0FAE_REG_3_MOD_3,
1013   PREFIX_0FAE_REG_4_MOD_0,
1014   PREFIX_0FAE_REG_4_MOD_3,
1015   PREFIX_0FAE_REG_5_MOD_0,
1016   PREFIX_0FAE_REG_5_MOD_3,
1017   PREFIX_0FAE_REG_6_MOD_0,
1018   PREFIX_0FAE_REG_6_MOD_3,
1019   PREFIX_0FAE_REG_7_MOD_0,
1020   PREFIX_0FB8,
1021   PREFIX_0FBC,
1022   PREFIX_0FBD,
1023   PREFIX_0FC2,
1024   PREFIX_0FC3_MOD_0,
1025   PREFIX_0FC7_REG_6_MOD_0,
1026   PREFIX_0FC7_REG_6_MOD_3,
1027   PREFIX_0FC7_REG_7_MOD_3,
1028   PREFIX_0FD0,
1029   PREFIX_0FD6,
1030   PREFIX_0FE6,
1031   PREFIX_0FE7,
1032   PREFIX_0FF0,
1033   PREFIX_0FF7,
1034   PREFIX_0F3810,
1035   PREFIX_0F3814,
1036   PREFIX_0F3815,
1037   PREFIX_0F3817,
1038   PREFIX_0F3820,
1039   PREFIX_0F3821,
1040   PREFIX_0F3822,
1041   PREFIX_0F3823,
1042   PREFIX_0F3824,
1043   PREFIX_0F3825,
1044   PREFIX_0F3828,
1045   PREFIX_0F3829,
1046   PREFIX_0F382A,
1047   PREFIX_0F382B,
1048   PREFIX_0F3830,
1049   PREFIX_0F3831,
1050   PREFIX_0F3832,
1051   PREFIX_0F3833,
1052   PREFIX_0F3834,
1053   PREFIX_0F3835,
1054   PREFIX_0F3837,
1055   PREFIX_0F3838,
1056   PREFIX_0F3839,
1057   PREFIX_0F383A,
1058   PREFIX_0F383B,
1059   PREFIX_0F383C,
1060   PREFIX_0F383D,
1061   PREFIX_0F383E,
1062   PREFIX_0F383F,
1063   PREFIX_0F3840,
1064   PREFIX_0F3841,
1065   PREFIX_0F3880,
1066   PREFIX_0F3881,
1067   PREFIX_0F3882,
1068   PREFIX_0F38C8,
1069   PREFIX_0F38C9,
1070   PREFIX_0F38CA,
1071   PREFIX_0F38CB,
1072   PREFIX_0F38CC,
1073   PREFIX_0F38CD,
1074   PREFIX_0F38CF,
1075   PREFIX_0F38DB,
1076   PREFIX_0F38DC,
1077   PREFIX_0F38DD,
1078   PREFIX_0F38DE,
1079   PREFIX_0F38DF,
1080   PREFIX_0F38F0,
1081   PREFIX_0F38F1,
1082   PREFIX_0F38F5,
1083   PREFIX_0F38F6,
1084   PREFIX_0F38F8,
1085   PREFIX_0F38F9,
1086   PREFIX_0F3A08,
1087   PREFIX_0F3A09,
1088   PREFIX_0F3A0A,
1089   PREFIX_0F3A0B,
1090   PREFIX_0F3A0C,
1091   PREFIX_0F3A0D,
1092   PREFIX_0F3A0E,
1093   PREFIX_0F3A14,
1094   PREFIX_0F3A15,
1095   PREFIX_0F3A16,
1096   PREFIX_0F3A17,
1097   PREFIX_0F3A20,
1098   PREFIX_0F3A21,
1099   PREFIX_0F3A22,
1100   PREFIX_0F3A40,
1101   PREFIX_0F3A41,
1102   PREFIX_0F3A42,
1103   PREFIX_0F3A44,
1104   PREFIX_0F3A60,
1105   PREFIX_0F3A61,
1106   PREFIX_0F3A62,
1107   PREFIX_0F3A63,
1108   PREFIX_0F3ACC,
1109   PREFIX_0F3ACE,
1110   PREFIX_0F3ACF,
1111   PREFIX_0F3ADF,
1112   PREFIX_VEX_0F10,
1113   PREFIX_VEX_0F11,
1114   PREFIX_VEX_0F12,
1115   PREFIX_VEX_0F16,
1116   PREFIX_VEX_0F2A,
1117   PREFIX_VEX_0F2C,
1118   PREFIX_VEX_0F2D,
1119   PREFIX_VEX_0F2E,
1120   PREFIX_VEX_0F2F,
1121   PREFIX_VEX_0F41,
1122   PREFIX_VEX_0F42,
1123   PREFIX_VEX_0F44,
1124   PREFIX_VEX_0F45,
1125   PREFIX_VEX_0F46,
1126   PREFIX_VEX_0F47,
1127   PREFIX_VEX_0F4A,
1128   PREFIX_VEX_0F4B,
1129   PREFIX_VEX_0F51,
1130   PREFIX_VEX_0F52,
1131   PREFIX_VEX_0F53,
1132   PREFIX_VEX_0F58,
1133   PREFIX_VEX_0F59,
1134   PREFIX_VEX_0F5A,
1135   PREFIX_VEX_0F5B,
1136   PREFIX_VEX_0F5C,
1137   PREFIX_VEX_0F5D,
1138   PREFIX_VEX_0F5E,
1139   PREFIX_VEX_0F5F,
1140   PREFIX_VEX_0F60,
1141   PREFIX_VEX_0F61,
1142   PREFIX_VEX_0F62,
1143   PREFIX_VEX_0F63,
1144   PREFIX_VEX_0F64,
1145   PREFIX_VEX_0F65,
1146   PREFIX_VEX_0F66,
1147   PREFIX_VEX_0F67,
1148   PREFIX_VEX_0F68,
1149   PREFIX_VEX_0F69,
1150   PREFIX_VEX_0F6A,
1151   PREFIX_VEX_0F6B,
1152   PREFIX_VEX_0F6C,
1153   PREFIX_VEX_0F6D,
1154   PREFIX_VEX_0F6E,
1155   PREFIX_VEX_0F6F,
1156   PREFIX_VEX_0F70,
1157   PREFIX_VEX_0F71_REG_2,
1158   PREFIX_VEX_0F71_REG_4,
1159   PREFIX_VEX_0F71_REG_6,
1160   PREFIX_VEX_0F72_REG_2,
1161   PREFIX_VEX_0F72_REG_4,
1162   PREFIX_VEX_0F72_REG_6,
1163   PREFIX_VEX_0F73_REG_2,
1164   PREFIX_VEX_0F73_REG_3,
1165   PREFIX_VEX_0F73_REG_6,
1166   PREFIX_VEX_0F73_REG_7,
1167   PREFIX_VEX_0F74,
1168   PREFIX_VEX_0F75,
1169   PREFIX_VEX_0F76,
1170   PREFIX_VEX_0F77,
1171   PREFIX_VEX_0F7C,
1172   PREFIX_VEX_0F7D,
1173   PREFIX_VEX_0F7E,
1174   PREFIX_VEX_0F7F,
1175   PREFIX_VEX_0F90,
1176   PREFIX_VEX_0F91,
1177   PREFIX_VEX_0F92,
1178   PREFIX_VEX_0F93,
1179   PREFIX_VEX_0F98,
1180   PREFIX_VEX_0F99,
1181   PREFIX_VEX_0FC2,
1182   PREFIX_VEX_0FC4,
1183   PREFIX_VEX_0FC5,
1184   PREFIX_VEX_0FD0,
1185   PREFIX_VEX_0FD1,
1186   PREFIX_VEX_0FD2,
1187   PREFIX_VEX_0FD3,
1188   PREFIX_VEX_0FD4,
1189   PREFIX_VEX_0FD5,
1190   PREFIX_VEX_0FD6,
1191   PREFIX_VEX_0FD7,
1192   PREFIX_VEX_0FD8,
1193   PREFIX_VEX_0FD9,
1194   PREFIX_VEX_0FDA,
1195   PREFIX_VEX_0FDB,
1196   PREFIX_VEX_0FDC,
1197   PREFIX_VEX_0FDD,
1198   PREFIX_VEX_0FDE,
1199   PREFIX_VEX_0FDF,
1200   PREFIX_VEX_0FE0,
1201   PREFIX_VEX_0FE1,
1202   PREFIX_VEX_0FE2,
1203   PREFIX_VEX_0FE3,
1204   PREFIX_VEX_0FE4,
1205   PREFIX_VEX_0FE5,
1206   PREFIX_VEX_0FE6,
1207   PREFIX_VEX_0FE7,
1208   PREFIX_VEX_0FE8,
1209   PREFIX_VEX_0FE9,
1210   PREFIX_VEX_0FEA,
1211   PREFIX_VEX_0FEB,
1212   PREFIX_VEX_0FEC,
1213   PREFIX_VEX_0FED,
1214   PREFIX_VEX_0FEE,
1215   PREFIX_VEX_0FEF,
1216   PREFIX_VEX_0FF0,
1217   PREFIX_VEX_0FF1,
1218   PREFIX_VEX_0FF2,
1219   PREFIX_VEX_0FF3,
1220   PREFIX_VEX_0FF4,
1221   PREFIX_VEX_0FF5,
1222   PREFIX_VEX_0FF6,
1223   PREFIX_VEX_0FF7,
1224   PREFIX_VEX_0FF8,
1225   PREFIX_VEX_0FF9,
1226   PREFIX_VEX_0FFA,
1227   PREFIX_VEX_0FFB,
1228   PREFIX_VEX_0FFC,
1229   PREFIX_VEX_0FFD,
1230   PREFIX_VEX_0FFE,
1231   PREFIX_VEX_0F3800,
1232   PREFIX_VEX_0F3801,
1233   PREFIX_VEX_0F3802,
1234   PREFIX_VEX_0F3803,
1235   PREFIX_VEX_0F3804,
1236   PREFIX_VEX_0F3805,
1237   PREFIX_VEX_0F3806,
1238   PREFIX_VEX_0F3807,
1239   PREFIX_VEX_0F3808,
1240   PREFIX_VEX_0F3809,
1241   PREFIX_VEX_0F380A,
1242   PREFIX_VEX_0F380B,
1243   PREFIX_VEX_0F380C,
1244   PREFIX_VEX_0F380D,
1245   PREFIX_VEX_0F380E,
1246   PREFIX_VEX_0F380F,
1247   PREFIX_VEX_0F3813,
1248   PREFIX_VEX_0F3816,
1249   PREFIX_VEX_0F3817,
1250   PREFIX_VEX_0F3818,
1251   PREFIX_VEX_0F3819,
1252   PREFIX_VEX_0F381A,
1253   PREFIX_VEX_0F381C,
1254   PREFIX_VEX_0F381D,
1255   PREFIX_VEX_0F381E,
1256   PREFIX_VEX_0F3820,
1257   PREFIX_VEX_0F3821,
1258   PREFIX_VEX_0F3822,
1259   PREFIX_VEX_0F3823,
1260   PREFIX_VEX_0F3824,
1261   PREFIX_VEX_0F3825,
1262   PREFIX_VEX_0F3828,
1263   PREFIX_VEX_0F3829,
1264   PREFIX_VEX_0F382A,
1265   PREFIX_VEX_0F382B,
1266   PREFIX_VEX_0F382C,
1267   PREFIX_VEX_0F382D,
1268   PREFIX_VEX_0F382E,
1269   PREFIX_VEX_0F382F,
1270   PREFIX_VEX_0F3830,
1271   PREFIX_VEX_0F3831,
1272   PREFIX_VEX_0F3832,
1273   PREFIX_VEX_0F3833,
1274   PREFIX_VEX_0F3834,
1275   PREFIX_VEX_0F3835,
1276   PREFIX_VEX_0F3836,
1277   PREFIX_VEX_0F3837,
1278   PREFIX_VEX_0F3838,
1279   PREFIX_VEX_0F3839,
1280   PREFIX_VEX_0F383A,
1281   PREFIX_VEX_0F383B,
1282   PREFIX_VEX_0F383C,
1283   PREFIX_VEX_0F383D,
1284   PREFIX_VEX_0F383E,
1285   PREFIX_VEX_0F383F,
1286   PREFIX_VEX_0F3840,
1287   PREFIX_VEX_0F3841,
1288   PREFIX_VEX_0F3845,
1289   PREFIX_VEX_0F3846,
1290   PREFIX_VEX_0F3847,
1291   PREFIX_VEX_0F3858,
1292   PREFIX_VEX_0F3859,
1293   PREFIX_VEX_0F385A,
1294   PREFIX_VEX_0F3878,
1295   PREFIX_VEX_0F3879,
1296   PREFIX_VEX_0F388C,
1297   PREFIX_VEX_0F388E,
1298   PREFIX_VEX_0F3890,
1299   PREFIX_VEX_0F3891,
1300   PREFIX_VEX_0F3892,
1301   PREFIX_VEX_0F3893,
1302   PREFIX_VEX_0F3896,
1303   PREFIX_VEX_0F3897,
1304   PREFIX_VEX_0F3898,
1305   PREFIX_VEX_0F3899,
1306   PREFIX_VEX_0F389A,
1307   PREFIX_VEX_0F389B,
1308   PREFIX_VEX_0F389C,
1309   PREFIX_VEX_0F389D,
1310   PREFIX_VEX_0F389E,
1311   PREFIX_VEX_0F389F,
1312   PREFIX_VEX_0F38A6,
1313   PREFIX_VEX_0F38A7,
1314   PREFIX_VEX_0F38A8,
1315   PREFIX_VEX_0F38A9,
1316   PREFIX_VEX_0F38AA,
1317   PREFIX_VEX_0F38AB,
1318   PREFIX_VEX_0F38AC,
1319   PREFIX_VEX_0F38AD,
1320   PREFIX_VEX_0F38AE,
1321   PREFIX_VEX_0F38AF,
1322   PREFIX_VEX_0F38B6,
1323   PREFIX_VEX_0F38B7,
1324   PREFIX_VEX_0F38B8,
1325   PREFIX_VEX_0F38B9,
1326   PREFIX_VEX_0F38BA,
1327   PREFIX_VEX_0F38BB,
1328   PREFIX_VEX_0F38BC,
1329   PREFIX_VEX_0F38BD,
1330   PREFIX_VEX_0F38BE,
1331   PREFIX_VEX_0F38BF,
1332   PREFIX_VEX_0F38CF,
1333   PREFIX_VEX_0F38DB,
1334   PREFIX_VEX_0F38DC,
1335   PREFIX_VEX_0F38DD,
1336   PREFIX_VEX_0F38DE,
1337   PREFIX_VEX_0F38DF,
1338   PREFIX_VEX_0F38F2,
1339   PREFIX_VEX_0F38F3_REG_1,
1340   PREFIX_VEX_0F38F3_REG_2,
1341   PREFIX_VEX_0F38F3_REG_3,
1342   PREFIX_VEX_0F38F5,
1343   PREFIX_VEX_0F38F6,
1344   PREFIX_VEX_0F38F7,
1345   PREFIX_VEX_0F3A00,
1346   PREFIX_VEX_0F3A01,
1347   PREFIX_VEX_0F3A02,
1348   PREFIX_VEX_0F3A04,
1349   PREFIX_VEX_0F3A05,
1350   PREFIX_VEX_0F3A06,
1351   PREFIX_VEX_0F3A08,
1352   PREFIX_VEX_0F3A09,
1353   PREFIX_VEX_0F3A0A,
1354   PREFIX_VEX_0F3A0B,
1355   PREFIX_VEX_0F3A0C,
1356   PREFIX_VEX_0F3A0D,
1357   PREFIX_VEX_0F3A0E,
1358   PREFIX_VEX_0F3A0F,
1359   PREFIX_VEX_0F3A14,
1360   PREFIX_VEX_0F3A15,
1361   PREFIX_VEX_0F3A16,
1362   PREFIX_VEX_0F3A17,
1363   PREFIX_VEX_0F3A18,
1364   PREFIX_VEX_0F3A19,
1365   PREFIX_VEX_0F3A1D,
1366   PREFIX_VEX_0F3A20,
1367   PREFIX_VEX_0F3A21,
1368   PREFIX_VEX_0F3A22,
1369   PREFIX_VEX_0F3A30,
1370   PREFIX_VEX_0F3A31,
1371   PREFIX_VEX_0F3A32,
1372   PREFIX_VEX_0F3A33,
1373   PREFIX_VEX_0F3A38,
1374   PREFIX_VEX_0F3A39,
1375   PREFIX_VEX_0F3A40,
1376   PREFIX_VEX_0F3A41,
1377   PREFIX_VEX_0F3A42,
1378   PREFIX_VEX_0F3A44,
1379   PREFIX_VEX_0F3A46,
1380   PREFIX_VEX_0F3A48,
1381   PREFIX_VEX_0F3A49,
1382   PREFIX_VEX_0F3A4A,
1383   PREFIX_VEX_0F3A4B,
1384   PREFIX_VEX_0F3A4C,
1385   PREFIX_VEX_0F3A5C,
1386   PREFIX_VEX_0F3A5D,
1387   PREFIX_VEX_0F3A5E,
1388   PREFIX_VEX_0F3A5F,
1389   PREFIX_VEX_0F3A60,
1390   PREFIX_VEX_0F3A61,
1391   PREFIX_VEX_0F3A62,
1392   PREFIX_VEX_0F3A63,
1393   PREFIX_VEX_0F3A68,
1394   PREFIX_VEX_0F3A69,
1395   PREFIX_VEX_0F3A6A,
1396   PREFIX_VEX_0F3A6B,
1397   PREFIX_VEX_0F3A6C,
1398   PREFIX_VEX_0F3A6D,
1399   PREFIX_VEX_0F3A6E,
1400   PREFIX_VEX_0F3A6F,
1401   PREFIX_VEX_0F3A78,
1402   PREFIX_VEX_0F3A79,
1403   PREFIX_VEX_0F3A7A,
1404   PREFIX_VEX_0F3A7B,
1405   PREFIX_VEX_0F3A7C,
1406   PREFIX_VEX_0F3A7D,
1407   PREFIX_VEX_0F3A7E,
1408   PREFIX_VEX_0F3A7F,
1409   PREFIX_VEX_0F3ACE,
1410   PREFIX_VEX_0F3ACF,
1411   PREFIX_VEX_0F3ADF,
1412   PREFIX_VEX_0F3AF0,
1413
1414   PREFIX_EVEX_0F10,
1415   PREFIX_EVEX_0F11,
1416   PREFIX_EVEX_0F12,
1417   PREFIX_EVEX_0F13,
1418   PREFIX_EVEX_0F14,
1419   PREFIX_EVEX_0F15,
1420   PREFIX_EVEX_0F16,
1421   PREFIX_EVEX_0F17,
1422   PREFIX_EVEX_0F28,
1423   PREFIX_EVEX_0F29,
1424   PREFIX_EVEX_0F2A,
1425   PREFIX_EVEX_0F2B,
1426   PREFIX_EVEX_0F2C,
1427   PREFIX_EVEX_0F2D,
1428   PREFIX_EVEX_0F2E,
1429   PREFIX_EVEX_0F2F,
1430   PREFIX_EVEX_0F51,
1431   PREFIX_EVEX_0F54,
1432   PREFIX_EVEX_0F55,
1433   PREFIX_EVEX_0F56,
1434   PREFIX_EVEX_0F57,
1435   PREFIX_EVEX_0F58,
1436   PREFIX_EVEX_0F59,
1437   PREFIX_EVEX_0F5A,
1438   PREFIX_EVEX_0F5B,
1439   PREFIX_EVEX_0F5C,
1440   PREFIX_EVEX_0F5D,
1441   PREFIX_EVEX_0F5E,
1442   PREFIX_EVEX_0F5F,
1443   PREFIX_EVEX_0F60,
1444   PREFIX_EVEX_0F61,
1445   PREFIX_EVEX_0F62,
1446   PREFIX_EVEX_0F63,
1447   PREFIX_EVEX_0F64,
1448   PREFIX_EVEX_0F65,
1449   PREFIX_EVEX_0F66,
1450   PREFIX_EVEX_0F67,
1451   PREFIX_EVEX_0F68,
1452   PREFIX_EVEX_0F69,
1453   PREFIX_EVEX_0F6A,
1454   PREFIX_EVEX_0F6B,
1455   PREFIX_EVEX_0F6C,
1456   PREFIX_EVEX_0F6D,
1457   PREFIX_EVEX_0F6E,
1458   PREFIX_EVEX_0F6F,
1459   PREFIX_EVEX_0F70,
1460   PREFIX_EVEX_0F71_REG_2,
1461   PREFIX_EVEX_0F71_REG_4,
1462   PREFIX_EVEX_0F71_REG_6,
1463   PREFIX_EVEX_0F72_REG_0,
1464   PREFIX_EVEX_0F72_REG_1,
1465   PREFIX_EVEX_0F72_REG_2,
1466   PREFIX_EVEX_0F72_REG_4,
1467   PREFIX_EVEX_0F72_REG_6,
1468   PREFIX_EVEX_0F73_REG_2,
1469   PREFIX_EVEX_0F73_REG_3,
1470   PREFIX_EVEX_0F73_REG_6,
1471   PREFIX_EVEX_0F73_REG_7,
1472   PREFIX_EVEX_0F74,
1473   PREFIX_EVEX_0F75,
1474   PREFIX_EVEX_0F76,
1475   PREFIX_EVEX_0F78,
1476   PREFIX_EVEX_0F79,
1477   PREFIX_EVEX_0F7A,
1478   PREFIX_EVEX_0F7B,
1479   PREFIX_EVEX_0F7E,
1480   PREFIX_EVEX_0F7F,
1481   PREFIX_EVEX_0FC2,
1482   PREFIX_EVEX_0FC4,
1483   PREFIX_EVEX_0FC5,
1484   PREFIX_EVEX_0FC6,
1485   PREFIX_EVEX_0FD1,
1486   PREFIX_EVEX_0FD2,
1487   PREFIX_EVEX_0FD3,
1488   PREFIX_EVEX_0FD4,
1489   PREFIX_EVEX_0FD5,
1490   PREFIX_EVEX_0FD6,
1491   PREFIX_EVEX_0FD8,
1492   PREFIX_EVEX_0FD9,
1493   PREFIX_EVEX_0FDA,
1494   PREFIX_EVEX_0FDB,
1495   PREFIX_EVEX_0FDC,
1496   PREFIX_EVEX_0FDD,
1497   PREFIX_EVEX_0FDE,
1498   PREFIX_EVEX_0FDF,
1499   PREFIX_EVEX_0FE0,
1500   PREFIX_EVEX_0FE1,
1501   PREFIX_EVEX_0FE2,
1502   PREFIX_EVEX_0FE3,
1503   PREFIX_EVEX_0FE4,
1504   PREFIX_EVEX_0FE5,
1505   PREFIX_EVEX_0FE6,
1506   PREFIX_EVEX_0FE7,
1507   PREFIX_EVEX_0FE8,
1508   PREFIX_EVEX_0FE9,
1509   PREFIX_EVEX_0FEA,
1510   PREFIX_EVEX_0FEB,
1511   PREFIX_EVEX_0FEC,
1512   PREFIX_EVEX_0FED,
1513   PREFIX_EVEX_0FEE,
1514   PREFIX_EVEX_0FEF,
1515   PREFIX_EVEX_0FF1,
1516   PREFIX_EVEX_0FF2,
1517   PREFIX_EVEX_0FF3,
1518   PREFIX_EVEX_0FF4,
1519   PREFIX_EVEX_0FF5,
1520   PREFIX_EVEX_0FF6,
1521   PREFIX_EVEX_0FF8,
1522   PREFIX_EVEX_0FF9,
1523   PREFIX_EVEX_0FFA,
1524   PREFIX_EVEX_0FFB,
1525   PREFIX_EVEX_0FFC,
1526   PREFIX_EVEX_0FFD,
1527   PREFIX_EVEX_0FFE,
1528   PREFIX_EVEX_0F3800,
1529   PREFIX_EVEX_0F3804,
1530   PREFIX_EVEX_0F380B,
1531   PREFIX_EVEX_0F380C,
1532   PREFIX_EVEX_0F380D,
1533   PREFIX_EVEX_0F3810,
1534   PREFIX_EVEX_0F3811,
1535   PREFIX_EVEX_0F3812,
1536   PREFIX_EVEX_0F3813,
1537   PREFIX_EVEX_0F3814,
1538   PREFIX_EVEX_0F3815,
1539   PREFIX_EVEX_0F3816,
1540   PREFIX_EVEX_0F3818,
1541   PREFIX_EVEX_0F3819,
1542   PREFIX_EVEX_0F381A,
1543   PREFIX_EVEX_0F381B,
1544   PREFIX_EVEX_0F381C,
1545   PREFIX_EVEX_0F381D,
1546   PREFIX_EVEX_0F381E,
1547   PREFIX_EVEX_0F381F,
1548   PREFIX_EVEX_0F3820,
1549   PREFIX_EVEX_0F3821,
1550   PREFIX_EVEX_0F3822,
1551   PREFIX_EVEX_0F3823,
1552   PREFIX_EVEX_0F3824,
1553   PREFIX_EVEX_0F3825,
1554   PREFIX_EVEX_0F3826,
1555   PREFIX_EVEX_0F3827,
1556   PREFIX_EVEX_0F3828,
1557   PREFIX_EVEX_0F3829,
1558   PREFIX_EVEX_0F382A,
1559   PREFIX_EVEX_0F382B,
1560   PREFIX_EVEX_0F382C,
1561   PREFIX_EVEX_0F382D,
1562   PREFIX_EVEX_0F3830,
1563   PREFIX_EVEX_0F3831,
1564   PREFIX_EVEX_0F3832,
1565   PREFIX_EVEX_0F3833,
1566   PREFIX_EVEX_0F3834,
1567   PREFIX_EVEX_0F3835,
1568   PREFIX_EVEX_0F3836,
1569   PREFIX_EVEX_0F3837,
1570   PREFIX_EVEX_0F3838,
1571   PREFIX_EVEX_0F3839,
1572   PREFIX_EVEX_0F383A,
1573   PREFIX_EVEX_0F383B,
1574   PREFIX_EVEX_0F383C,
1575   PREFIX_EVEX_0F383D,
1576   PREFIX_EVEX_0F383E,
1577   PREFIX_EVEX_0F383F,
1578   PREFIX_EVEX_0F3840,
1579   PREFIX_EVEX_0F3842,
1580   PREFIX_EVEX_0F3843,
1581   PREFIX_EVEX_0F3844,
1582   PREFIX_EVEX_0F3845,
1583   PREFIX_EVEX_0F3846,
1584   PREFIX_EVEX_0F3847,
1585   PREFIX_EVEX_0F384C,
1586   PREFIX_EVEX_0F384D,
1587   PREFIX_EVEX_0F384E,
1588   PREFIX_EVEX_0F384F,
1589   PREFIX_EVEX_0F3850,
1590   PREFIX_EVEX_0F3851,
1591   PREFIX_EVEX_0F3852,
1592   PREFIX_EVEX_0F3853,
1593   PREFIX_EVEX_0F3854,
1594   PREFIX_EVEX_0F3855,
1595   PREFIX_EVEX_0F3858,
1596   PREFIX_EVEX_0F3859,
1597   PREFIX_EVEX_0F385A,
1598   PREFIX_EVEX_0F385B,
1599   PREFIX_EVEX_0F3862,
1600   PREFIX_EVEX_0F3863,
1601   PREFIX_EVEX_0F3864,
1602   PREFIX_EVEX_0F3865,
1603   PREFIX_EVEX_0F3866,
1604   PREFIX_EVEX_0F3868,
1605   PREFIX_EVEX_0F3870,
1606   PREFIX_EVEX_0F3871,
1607   PREFIX_EVEX_0F3872,
1608   PREFIX_EVEX_0F3873,
1609   PREFIX_EVEX_0F3875,
1610   PREFIX_EVEX_0F3876,
1611   PREFIX_EVEX_0F3877,
1612   PREFIX_EVEX_0F3878,
1613   PREFIX_EVEX_0F3879,
1614   PREFIX_EVEX_0F387A,
1615   PREFIX_EVEX_0F387B,
1616   PREFIX_EVEX_0F387C,
1617   PREFIX_EVEX_0F387D,
1618   PREFIX_EVEX_0F387E,
1619   PREFIX_EVEX_0F387F,
1620   PREFIX_EVEX_0F3883,
1621   PREFIX_EVEX_0F3888,
1622   PREFIX_EVEX_0F3889,
1623   PREFIX_EVEX_0F388A,
1624   PREFIX_EVEX_0F388B,
1625   PREFIX_EVEX_0F388D,
1626   PREFIX_EVEX_0F388F,
1627   PREFIX_EVEX_0F3890,
1628   PREFIX_EVEX_0F3891,
1629   PREFIX_EVEX_0F3892,
1630   PREFIX_EVEX_0F3893,
1631   PREFIX_EVEX_0F3896,
1632   PREFIX_EVEX_0F3897,
1633   PREFIX_EVEX_0F3898,
1634   PREFIX_EVEX_0F3899,
1635   PREFIX_EVEX_0F389A,
1636   PREFIX_EVEX_0F389B,
1637   PREFIX_EVEX_0F389C,
1638   PREFIX_EVEX_0F389D,
1639   PREFIX_EVEX_0F389E,
1640   PREFIX_EVEX_0F389F,
1641   PREFIX_EVEX_0F38A0,
1642   PREFIX_EVEX_0F38A1,
1643   PREFIX_EVEX_0F38A2,
1644   PREFIX_EVEX_0F38A3,
1645   PREFIX_EVEX_0F38A6,
1646   PREFIX_EVEX_0F38A7,
1647   PREFIX_EVEX_0F38A8,
1648   PREFIX_EVEX_0F38A9,
1649   PREFIX_EVEX_0F38AA,
1650   PREFIX_EVEX_0F38AB,
1651   PREFIX_EVEX_0F38AC,
1652   PREFIX_EVEX_0F38AD,
1653   PREFIX_EVEX_0F38AE,
1654   PREFIX_EVEX_0F38AF,
1655   PREFIX_EVEX_0F38B4,
1656   PREFIX_EVEX_0F38B5,
1657   PREFIX_EVEX_0F38B6,
1658   PREFIX_EVEX_0F38B7,
1659   PREFIX_EVEX_0F38B8,
1660   PREFIX_EVEX_0F38B9,
1661   PREFIX_EVEX_0F38BA,
1662   PREFIX_EVEX_0F38BB,
1663   PREFIX_EVEX_0F38BC,
1664   PREFIX_EVEX_0F38BD,
1665   PREFIX_EVEX_0F38BE,
1666   PREFIX_EVEX_0F38BF,
1667   PREFIX_EVEX_0F38C4,
1668   PREFIX_EVEX_0F38C6_REG_1,
1669   PREFIX_EVEX_0F38C6_REG_2,
1670   PREFIX_EVEX_0F38C6_REG_5,
1671   PREFIX_EVEX_0F38C6_REG_6,
1672   PREFIX_EVEX_0F38C7_REG_1,
1673   PREFIX_EVEX_0F38C7_REG_2,
1674   PREFIX_EVEX_0F38C7_REG_5,
1675   PREFIX_EVEX_0F38C7_REG_6,
1676   PREFIX_EVEX_0F38C8,
1677   PREFIX_EVEX_0F38CA,
1678   PREFIX_EVEX_0F38CB,
1679   PREFIX_EVEX_0F38CC,
1680   PREFIX_EVEX_0F38CD,
1681   PREFIX_EVEX_0F38CF,
1682   PREFIX_EVEX_0F38DC,
1683   PREFIX_EVEX_0F38DD,
1684   PREFIX_EVEX_0F38DE,
1685   PREFIX_EVEX_0F38DF,
1686
1687   PREFIX_EVEX_0F3A00,
1688   PREFIX_EVEX_0F3A01,
1689   PREFIX_EVEX_0F3A03,
1690   PREFIX_EVEX_0F3A04,
1691   PREFIX_EVEX_0F3A05,
1692   PREFIX_EVEX_0F3A08,
1693   PREFIX_EVEX_0F3A09,
1694   PREFIX_EVEX_0F3A0A,
1695   PREFIX_EVEX_0F3A0B,
1696   PREFIX_EVEX_0F3A0F,
1697   PREFIX_EVEX_0F3A14,
1698   PREFIX_EVEX_0F3A15,
1699   PREFIX_EVEX_0F3A16,
1700   PREFIX_EVEX_0F3A17,
1701   PREFIX_EVEX_0F3A18,
1702   PREFIX_EVEX_0F3A19,
1703   PREFIX_EVEX_0F3A1A,
1704   PREFIX_EVEX_0F3A1B,
1705   PREFIX_EVEX_0F3A1D,
1706   PREFIX_EVEX_0F3A1E,
1707   PREFIX_EVEX_0F3A1F,
1708   PREFIX_EVEX_0F3A20,
1709   PREFIX_EVEX_0F3A21,
1710   PREFIX_EVEX_0F3A22,
1711   PREFIX_EVEX_0F3A23,
1712   PREFIX_EVEX_0F3A25,
1713   PREFIX_EVEX_0F3A26,
1714   PREFIX_EVEX_0F3A27,
1715   PREFIX_EVEX_0F3A38,
1716   PREFIX_EVEX_0F3A39,
1717   PREFIX_EVEX_0F3A3A,
1718   PREFIX_EVEX_0F3A3B,
1719   PREFIX_EVEX_0F3A3E,
1720   PREFIX_EVEX_0F3A3F,
1721   PREFIX_EVEX_0F3A42,
1722   PREFIX_EVEX_0F3A43,
1723   PREFIX_EVEX_0F3A44,
1724   PREFIX_EVEX_0F3A50,
1725   PREFIX_EVEX_0F3A51,
1726   PREFIX_EVEX_0F3A54,
1727   PREFIX_EVEX_0F3A55,
1728   PREFIX_EVEX_0F3A56,
1729   PREFIX_EVEX_0F3A57,
1730   PREFIX_EVEX_0F3A66,
1731   PREFIX_EVEX_0F3A67,
1732   PREFIX_EVEX_0F3A70,
1733   PREFIX_EVEX_0F3A71,
1734   PREFIX_EVEX_0F3A72,
1735   PREFIX_EVEX_0F3A73,
1736   PREFIX_EVEX_0F3ACE,
1737   PREFIX_EVEX_0F3ACF
1738 };
1739
1740 enum
1741 {
1742   X86_64_06 = 0,
1743   X86_64_07,
1744   X86_64_0D,
1745   X86_64_16,
1746   X86_64_17,
1747   X86_64_1E,
1748   X86_64_1F,
1749   X86_64_27,
1750   X86_64_2F,
1751   X86_64_37,
1752   X86_64_3F,
1753   X86_64_60,
1754   X86_64_61,
1755   X86_64_62,
1756   X86_64_63,
1757   X86_64_6D,
1758   X86_64_6F,
1759   X86_64_82,
1760   X86_64_9A,
1761   X86_64_C4,
1762   X86_64_C5,
1763   X86_64_CE,
1764   X86_64_D4,
1765   X86_64_D5,
1766   X86_64_E8,
1767   X86_64_E9,
1768   X86_64_EA,
1769   X86_64_0F01_REG_0,
1770   X86_64_0F01_REG_1,
1771   X86_64_0F01_REG_2,
1772   X86_64_0F01_REG_3
1773 };
1774
1775 enum
1776 {
1777   THREE_BYTE_0F38 = 0,
1778   THREE_BYTE_0F3A
1779 };
1780
1781 enum
1782 {
1783   XOP_08 = 0,
1784   XOP_09,
1785   XOP_0A
1786 };
1787
1788 enum
1789 {
1790   VEX_0F = 0,
1791   VEX_0F38,
1792   VEX_0F3A
1793 };
1794
1795 enum
1796 {
1797   EVEX_0F = 0,
1798   EVEX_0F38,
1799   EVEX_0F3A
1800 };
1801
1802 enum
1803 {
1804   VEX_LEN_0F12_P_0_M_0 = 0,
1805   VEX_LEN_0F12_P_0_M_1,
1806   VEX_LEN_0F12_P_2,
1807   VEX_LEN_0F13_M_0,
1808   VEX_LEN_0F16_P_0_M_0,
1809   VEX_LEN_0F16_P_0_M_1,
1810   VEX_LEN_0F16_P_2,
1811   VEX_LEN_0F17_M_0,
1812   VEX_LEN_0F41_P_0,
1813   VEX_LEN_0F41_P_2,
1814   VEX_LEN_0F42_P_0,
1815   VEX_LEN_0F42_P_2,
1816   VEX_LEN_0F44_P_0,
1817   VEX_LEN_0F44_P_2,
1818   VEX_LEN_0F45_P_0,
1819   VEX_LEN_0F45_P_2,
1820   VEX_LEN_0F46_P_0,
1821   VEX_LEN_0F46_P_2,
1822   VEX_LEN_0F47_P_0,
1823   VEX_LEN_0F47_P_2,
1824   VEX_LEN_0F4A_P_0,
1825   VEX_LEN_0F4A_P_2,
1826   VEX_LEN_0F4B_P_0,
1827   VEX_LEN_0F4B_P_2,
1828   VEX_LEN_0F6E_P_2,
1829   VEX_LEN_0F77_P_0,
1830   VEX_LEN_0F7E_P_1,
1831   VEX_LEN_0F7E_P_2,
1832   VEX_LEN_0F90_P_0,
1833   VEX_LEN_0F90_P_2,
1834   VEX_LEN_0F91_P_0,
1835   VEX_LEN_0F91_P_2,
1836   VEX_LEN_0F92_P_0,
1837   VEX_LEN_0F92_P_2,
1838   VEX_LEN_0F92_P_3,
1839   VEX_LEN_0F93_P_0,
1840   VEX_LEN_0F93_P_2,
1841   VEX_LEN_0F93_P_3,
1842   VEX_LEN_0F98_P_0,
1843   VEX_LEN_0F98_P_2,
1844   VEX_LEN_0F99_P_0,
1845   VEX_LEN_0F99_P_2,
1846   VEX_LEN_0FAE_R_2_M_0,
1847   VEX_LEN_0FAE_R_3_M_0,
1848   VEX_LEN_0FC4_P_2,
1849   VEX_LEN_0FC5_P_2,
1850   VEX_LEN_0FD6_P_2,
1851   VEX_LEN_0FF7_P_2,
1852   VEX_LEN_0F3816_P_2,
1853   VEX_LEN_0F3819_P_2,
1854   VEX_LEN_0F381A_P_2_M_0,
1855   VEX_LEN_0F3836_P_2,
1856   VEX_LEN_0F3841_P_2,
1857   VEX_LEN_0F385A_P_2_M_0,
1858   VEX_LEN_0F38DB_P_2,
1859   VEX_LEN_0F38F2_P_0,
1860   VEX_LEN_0F38F3_R_1_P_0,
1861   VEX_LEN_0F38F3_R_2_P_0,
1862   VEX_LEN_0F38F3_R_3_P_0,
1863   VEX_LEN_0F38F5_P_0,
1864   VEX_LEN_0F38F5_P_1,
1865   VEX_LEN_0F38F5_P_3,
1866   VEX_LEN_0F38F6_P_3,
1867   VEX_LEN_0F38F7_P_0,
1868   VEX_LEN_0F38F7_P_1,
1869   VEX_LEN_0F38F7_P_2,
1870   VEX_LEN_0F38F7_P_3,
1871   VEX_LEN_0F3A00_P_2,
1872   VEX_LEN_0F3A01_P_2,
1873   VEX_LEN_0F3A06_P_2,
1874   VEX_LEN_0F3A14_P_2,
1875   VEX_LEN_0F3A15_P_2,
1876   VEX_LEN_0F3A16_P_2,
1877   VEX_LEN_0F3A17_P_2,
1878   VEX_LEN_0F3A18_P_2,
1879   VEX_LEN_0F3A19_P_2,
1880   VEX_LEN_0F3A20_P_2,
1881   VEX_LEN_0F3A21_P_2,
1882   VEX_LEN_0F3A22_P_2,
1883   VEX_LEN_0F3A30_P_2,
1884   VEX_LEN_0F3A31_P_2,
1885   VEX_LEN_0F3A32_P_2,
1886   VEX_LEN_0F3A33_P_2,
1887   VEX_LEN_0F3A38_P_2,
1888   VEX_LEN_0F3A39_P_2,
1889   VEX_LEN_0F3A41_P_2,
1890   VEX_LEN_0F3A46_P_2,
1891   VEX_LEN_0F3A60_P_2,
1892   VEX_LEN_0F3A61_P_2,
1893   VEX_LEN_0F3A62_P_2,
1894   VEX_LEN_0F3A63_P_2,
1895   VEX_LEN_0F3A6A_P_2,
1896   VEX_LEN_0F3A6B_P_2,
1897   VEX_LEN_0F3A6E_P_2,
1898   VEX_LEN_0F3A6F_P_2,
1899   VEX_LEN_0F3A7A_P_2,
1900   VEX_LEN_0F3A7B_P_2,
1901   VEX_LEN_0F3A7E_P_2,
1902   VEX_LEN_0F3A7F_P_2,
1903   VEX_LEN_0F3ADF_P_2,
1904   VEX_LEN_0F3AF0_P_3,
1905   VEX_LEN_0FXOP_08_CC,
1906   VEX_LEN_0FXOP_08_CD,
1907   VEX_LEN_0FXOP_08_CE,
1908   VEX_LEN_0FXOP_08_CF,
1909   VEX_LEN_0FXOP_08_EC,
1910   VEX_LEN_0FXOP_08_ED,
1911   VEX_LEN_0FXOP_08_EE,
1912   VEX_LEN_0FXOP_08_EF,
1913   VEX_LEN_0FXOP_09_80,
1914   VEX_LEN_0FXOP_09_81
1915 };
1916
1917 enum
1918 {
1919   EVEX_LEN_0F6E_P_2 = 0,
1920   EVEX_LEN_0F7E_P_1,
1921   EVEX_LEN_0F7E_P_2,
1922   EVEX_LEN_0FD6_P_2,
1923   EVEX_LEN_0F3819_P_2_W_0,
1924   EVEX_LEN_0F3819_P_2_W_1,
1925   EVEX_LEN_0F381A_P_2_W_0,
1926   EVEX_LEN_0F381A_P_2_W_1,
1927   EVEX_LEN_0F381B_P_2_W_0,
1928   EVEX_LEN_0F381B_P_2_W_1,
1929   EVEX_LEN_0F385A_P_2_W_0,
1930   EVEX_LEN_0F385A_P_2_W_1,
1931   EVEX_LEN_0F385B_P_2_W_0,
1932   EVEX_LEN_0F385B_P_2_W_1,
1933   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1934   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1935   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1936   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1937   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1938   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1939   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1940   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1941   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1942   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1943   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1944   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1945   EVEX_LEN_0F3A18_P_2_W_0,
1946   EVEX_LEN_0F3A18_P_2_W_1,
1947   EVEX_LEN_0F3A19_P_2_W_0,
1948   EVEX_LEN_0F3A19_P_2_W_1,
1949   EVEX_LEN_0F3A1A_P_2_W_0,
1950   EVEX_LEN_0F3A1A_P_2_W_1,
1951   EVEX_LEN_0F3A1B_P_2_W_0,
1952   EVEX_LEN_0F3A1B_P_2_W_1,
1953   EVEX_LEN_0F3A23_P_2_W_0,
1954   EVEX_LEN_0F3A23_P_2_W_1,
1955   EVEX_LEN_0F3A38_P_2_W_0,
1956   EVEX_LEN_0F3A38_P_2_W_1,
1957   EVEX_LEN_0F3A39_P_2_W_0,
1958   EVEX_LEN_0F3A39_P_2_W_1,
1959   EVEX_LEN_0F3A3A_P_2_W_0,
1960   EVEX_LEN_0F3A3A_P_2_W_1,
1961   EVEX_LEN_0F3A3B_P_2_W_0,
1962   EVEX_LEN_0F3A3B_P_2_W_1,
1963   EVEX_LEN_0F3A43_P_2_W_0,
1964   EVEX_LEN_0F3A43_P_2_W_1
1965 };
1966
1967 enum
1968 {
1969   VEX_W_0F41_P_0_LEN_1 = 0,
1970   VEX_W_0F41_P_2_LEN_1,
1971   VEX_W_0F42_P_0_LEN_1,
1972   VEX_W_0F42_P_2_LEN_1,
1973   VEX_W_0F44_P_0_LEN_0,
1974   VEX_W_0F44_P_2_LEN_0,
1975   VEX_W_0F45_P_0_LEN_1,
1976   VEX_W_0F45_P_2_LEN_1,
1977   VEX_W_0F46_P_0_LEN_1,
1978   VEX_W_0F46_P_2_LEN_1,
1979   VEX_W_0F47_P_0_LEN_1,
1980   VEX_W_0F47_P_2_LEN_1,
1981   VEX_W_0F4A_P_0_LEN_1,
1982   VEX_W_0F4A_P_2_LEN_1,
1983   VEX_W_0F4B_P_0_LEN_1,
1984   VEX_W_0F4B_P_2_LEN_1,
1985   VEX_W_0F90_P_0_LEN_0,
1986   VEX_W_0F90_P_2_LEN_0,
1987   VEX_W_0F91_P_0_LEN_0,
1988   VEX_W_0F91_P_2_LEN_0,
1989   VEX_W_0F92_P_0_LEN_0,
1990   VEX_W_0F92_P_2_LEN_0,
1991   VEX_W_0F93_P_0_LEN_0,
1992   VEX_W_0F93_P_2_LEN_0,
1993   VEX_W_0F98_P_0_LEN_0,
1994   VEX_W_0F98_P_2_LEN_0,
1995   VEX_W_0F99_P_0_LEN_0,
1996   VEX_W_0F99_P_2_LEN_0,
1997   VEX_W_0F380C_P_2,
1998   VEX_W_0F380D_P_2,
1999   VEX_W_0F380E_P_2,
2000   VEX_W_0F380F_P_2,
2001   VEX_W_0F3816_P_2,
2002   VEX_W_0F3818_P_2,
2003   VEX_W_0F3819_P_2,
2004   VEX_W_0F381A_P_2_M_0,
2005   VEX_W_0F382C_P_2_M_0,
2006   VEX_W_0F382D_P_2_M_0,
2007   VEX_W_0F382E_P_2_M_0,
2008   VEX_W_0F382F_P_2_M_0,
2009   VEX_W_0F3836_P_2,
2010   VEX_W_0F3846_P_2,
2011   VEX_W_0F3858_P_2,
2012   VEX_W_0F3859_P_2,
2013   VEX_W_0F385A_P_2_M_0,
2014   VEX_W_0F3878_P_2,
2015   VEX_W_0F3879_P_2,
2016   VEX_W_0F38CF_P_2,
2017   VEX_W_0F3A00_P_2,
2018   VEX_W_0F3A01_P_2,
2019   VEX_W_0F3A02_P_2,
2020   VEX_W_0F3A04_P_2,
2021   VEX_W_0F3A05_P_2,
2022   VEX_W_0F3A06_P_2,
2023   VEX_W_0F3A18_P_2,
2024   VEX_W_0F3A19_P_2,
2025   VEX_W_0F3A30_P_2_LEN_0,
2026   VEX_W_0F3A31_P_2_LEN_0,
2027   VEX_W_0F3A32_P_2_LEN_0,
2028   VEX_W_0F3A33_P_2_LEN_0,
2029   VEX_W_0F3A38_P_2,
2030   VEX_W_0F3A39_P_2,
2031   VEX_W_0F3A46_P_2,
2032   VEX_W_0F3A48_P_2,
2033   VEX_W_0F3A49_P_2,
2034   VEX_W_0F3A4A_P_2,
2035   VEX_W_0F3A4B_P_2,
2036   VEX_W_0F3A4C_P_2,
2037   VEX_W_0F3ACE_P_2,
2038   VEX_W_0F3ACF_P_2,
2039
2040   EVEX_W_0F10_P_0,
2041   EVEX_W_0F10_P_1,
2042   EVEX_W_0F10_P_2,
2043   EVEX_W_0F10_P_3,
2044   EVEX_W_0F11_P_0,
2045   EVEX_W_0F11_P_1,
2046   EVEX_W_0F11_P_2,
2047   EVEX_W_0F11_P_3,
2048   EVEX_W_0F12_P_0_M_0,
2049   EVEX_W_0F12_P_0_M_1,
2050   EVEX_W_0F12_P_1,
2051   EVEX_W_0F12_P_2,
2052   EVEX_W_0F12_P_3,
2053   EVEX_W_0F13_P_0,
2054   EVEX_W_0F13_P_2,
2055   EVEX_W_0F14_P_0,
2056   EVEX_W_0F14_P_2,
2057   EVEX_W_0F15_P_0,
2058   EVEX_W_0F15_P_2,
2059   EVEX_W_0F16_P_0_M_0,
2060   EVEX_W_0F16_P_0_M_1,
2061   EVEX_W_0F16_P_1,
2062   EVEX_W_0F16_P_2,
2063   EVEX_W_0F17_P_0,
2064   EVEX_W_0F17_P_2,
2065   EVEX_W_0F28_P_0,
2066   EVEX_W_0F28_P_2,
2067   EVEX_W_0F29_P_0,
2068   EVEX_W_0F29_P_2,
2069   EVEX_W_0F2A_P_3,
2070   EVEX_W_0F2B_P_0,
2071   EVEX_W_0F2B_P_2,
2072   EVEX_W_0F2E_P_0,
2073   EVEX_W_0F2E_P_2,
2074   EVEX_W_0F2F_P_0,
2075   EVEX_W_0F2F_P_2,
2076   EVEX_W_0F51_P_0,
2077   EVEX_W_0F51_P_1,
2078   EVEX_W_0F51_P_2,
2079   EVEX_W_0F51_P_3,
2080   EVEX_W_0F54_P_0,
2081   EVEX_W_0F54_P_2,
2082   EVEX_W_0F55_P_0,
2083   EVEX_W_0F55_P_2,
2084   EVEX_W_0F56_P_0,
2085   EVEX_W_0F56_P_2,
2086   EVEX_W_0F57_P_0,
2087   EVEX_W_0F57_P_2,
2088   EVEX_W_0F58_P_0,
2089   EVEX_W_0F58_P_1,
2090   EVEX_W_0F58_P_2,
2091   EVEX_W_0F58_P_3,
2092   EVEX_W_0F59_P_0,
2093   EVEX_W_0F59_P_1,
2094   EVEX_W_0F59_P_2,
2095   EVEX_W_0F59_P_3,
2096   EVEX_W_0F5A_P_0,
2097   EVEX_W_0F5A_P_1,
2098   EVEX_W_0F5A_P_2,
2099   EVEX_W_0F5A_P_3,
2100   EVEX_W_0F5B_P_0,
2101   EVEX_W_0F5B_P_1,
2102   EVEX_W_0F5B_P_2,
2103   EVEX_W_0F5C_P_0,
2104   EVEX_W_0F5C_P_1,
2105   EVEX_W_0F5C_P_2,
2106   EVEX_W_0F5C_P_3,
2107   EVEX_W_0F5D_P_0,
2108   EVEX_W_0F5D_P_1,
2109   EVEX_W_0F5D_P_2,
2110   EVEX_W_0F5D_P_3,
2111   EVEX_W_0F5E_P_0,
2112   EVEX_W_0F5E_P_1,
2113   EVEX_W_0F5E_P_2,
2114   EVEX_W_0F5E_P_3,
2115   EVEX_W_0F5F_P_0,
2116   EVEX_W_0F5F_P_1,
2117   EVEX_W_0F5F_P_2,
2118   EVEX_W_0F5F_P_3,
2119   EVEX_W_0F62_P_2,
2120   EVEX_W_0F66_P_2,
2121   EVEX_W_0F6A_P_2,
2122   EVEX_W_0F6B_P_2,
2123   EVEX_W_0F6C_P_2,
2124   EVEX_W_0F6D_P_2,
2125   EVEX_W_0F6F_P_1,
2126   EVEX_W_0F6F_P_2,
2127   EVEX_W_0F6F_P_3,
2128   EVEX_W_0F70_P_2,
2129   EVEX_W_0F72_R_2_P_2,
2130   EVEX_W_0F72_R_6_P_2,
2131   EVEX_W_0F73_R_2_P_2,
2132   EVEX_W_0F73_R_6_P_2,
2133   EVEX_W_0F76_P_2,
2134   EVEX_W_0F78_P_0,
2135   EVEX_W_0F78_P_2,
2136   EVEX_W_0F79_P_0,
2137   EVEX_W_0F79_P_2,
2138   EVEX_W_0F7A_P_1,
2139   EVEX_W_0F7A_P_2,
2140   EVEX_W_0F7A_P_3,
2141   EVEX_W_0F7B_P_2,
2142   EVEX_W_0F7B_P_3,
2143   EVEX_W_0F7E_P_1,
2144   EVEX_W_0F7F_P_1,
2145   EVEX_W_0F7F_P_2,
2146   EVEX_W_0F7F_P_3,
2147   EVEX_W_0FC2_P_0,
2148   EVEX_W_0FC2_P_1,
2149   EVEX_W_0FC2_P_2,
2150   EVEX_W_0FC2_P_3,
2151   EVEX_W_0FC6_P_0,
2152   EVEX_W_0FC6_P_2,
2153   EVEX_W_0FD2_P_2,
2154   EVEX_W_0FD3_P_2,
2155   EVEX_W_0FD4_P_2,
2156   EVEX_W_0FD6_P_2,
2157   EVEX_W_0FE6_P_1,
2158   EVEX_W_0FE6_P_2,
2159   EVEX_W_0FE6_P_3,
2160   EVEX_W_0FE7_P_2,
2161   EVEX_W_0FF2_P_2,
2162   EVEX_W_0FF3_P_2,
2163   EVEX_W_0FF4_P_2,
2164   EVEX_W_0FFA_P_2,
2165   EVEX_W_0FFB_P_2,
2166   EVEX_W_0FFE_P_2,
2167   EVEX_W_0F380C_P_2,
2168   EVEX_W_0F380D_P_2,
2169   EVEX_W_0F3810_P_1,
2170   EVEX_W_0F3810_P_2,
2171   EVEX_W_0F3811_P_1,
2172   EVEX_W_0F3811_P_2,
2173   EVEX_W_0F3812_P_1,
2174   EVEX_W_0F3812_P_2,
2175   EVEX_W_0F3813_P_1,
2176   EVEX_W_0F3813_P_2,
2177   EVEX_W_0F3814_P_1,
2178   EVEX_W_0F3815_P_1,
2179   EVEX_W_0F3818_P_2,
2180   EVEX_W_0F3819_P_2,
2181   EVEX_W_0F381A_P_2,
2182   EVEX_W_0F381B_P_2,
2183   EVEX_W_0F381E_P_2,
2184   EVEX_W_0F381F_P_2,
2185   EVEX_W_0F3820_P_1,
2186   EVEX_W_0F3821_P_1,
2187   EVEX_W_0F3822_P_1,
2188   EVEX_W_0F3823_P_1,
2189   EVEX_W_0F3824_P_1,
2190   EVEX_W_0F3825_P_1,
2191   EVEX_W_0F3825_P_2,
2192   EVEX_W_0F3826_P_1,
2193   EVEX_W_0F3826_P_2,
2194   EVEX_W_0F3828_P_1,
2195   EVEX_W_0F3828_P_2,
2196   EVEX_W_0F3829_P_1,
2197   EVEX_W_0F3829_P_2,
2198   EVEX_W_0F382A_P_1,
2199   EVEX_W_0F382A_P_2,
2200   EVEX_W_0F382B_P_2,
2201   EVEX_W_0F3830_P_1,
2202   EVEX_W_0F3831_P_1,
2203   EVEX_W_0F3832_P_1,
2204   EVEX_W_0F3833_P_1,
2205   EVEX_W_0F3834_P_1,
2206   EVEX_W_0F3835_P_1,
2207   EVEX_W_0F3835_P_2,
2208   EVEX_W_0F3837_P_2,
2209   EVEX_W_0F3838_P_1,
2210   EVEX_W_0F3839_P_1,
2211   EVEX_W_0F383A_P_1,
2212   EVEX_W_0F3840_P_2,
2213   EVEX_W_0F3852_P_1,
2214   EVEX_W_0F3854_P_2,
2215   EVEX_W_0F3855_P_2,
2216   EVEX_W_0F3858_P_2,
2217   EVEX_W_0F3859_P_2,
2218   EVEX_W_0F385A_P_2,
2219   EVEX_W_0F385B_P_2,
2220   EVEX_W_0F3862_P_2,
2221   EVEX_W_0F3863_P_2,
2222   EVEX_W_0F3866_P_2,
2223   EVEX_W_0F3868_P_3,
2224   EVEX_W_0F3870_P_2,
2225   EVEX_W_0F3871_P_2,
2226   EVEX_W_0F3872_P_1,
2227   EVEX_W_0F3872_P_2,
2228   EVEX_W_0F3872_P_3,
2229   EVEX_W_0F3873_P_2,
2230   EVEX_W_0F3875_P_2,
2231   EVEX_W_0F3878_P_2,
2232   EVEX_W_0F3879_P_2,
2233   EVEX_W_0F387A_P_2,
2234   EVEX_W_0F387B_P_2,
2235   EVEX_W_0F387D_P_2,
2236   EVEX_W_0F3883_P_2,
2237   EVEX_W_0F388D_P_2,
2238   EVEX_W_0F3891_P_2,
2239   EVEX_W_0F3893_P_2,
2240   EVEX_W_0F38A1_P_2,
2241   EVEX_W_0F38A3_P_2,
2242   EVEX_W_0F38C7_R_1_P_2,
2243   EVEX_W_0F38C7_R_2_P_2,
2244   EVEX_W_0F38C7_R_5_P_2,
2245   EVEX_W_0F38C7_R_6_P_2,
2246
2247   EVEX_W_0F3A00_P_2,
2248   EVEX_W_0F3A01_P_2,
2249   EVEX_W_0F3A04_P_2,
2250   EVEX_W_0F3A05_P_2,
2251   EVEX_W_0F3A08_P_2,
2252   EVEX_W_0F3A09_P_2,
2253   EVEX_W_0F3A0A_P_2,
2254   EVEX_W_0F3A0B_P_2,
2255   EVEX_W_0F3A18_P_2,
2256   EVEX_W_0F3A19_P_2,
2257   EVEX_W_0F3A1A_P_2,
2258   EVEX_W_0F3A1B_P_2,
2259   EVEX_W_0F3A1D_P_2,
2260   EVEX_W_0F3A21_P_2,
2261   EVEX_W_0F3A23_P_2,
2262   EVEX_W_0F3A38_P_2,
2263   EVEX_W_0F3A39_P_2,
2264   EVEX_W_0F3A3A_P_2,
2265   EVEX_W_0F3A3B_P_2,
2266   EVEX_W_0F3A3E_P_2,
2267   EVEX_W_0F3A3F_P_2,
2268   EVEX_W_0F3A42_P_2,
2269   EVEX_W_0F3A43_P_2,
2270   EVEX_W_0F3A50_P_2,
2271   EVEX_W_0F3A51_P_2,
2272   EVEX_W_0F3A56_P_2,
2273   EVEX_W_0F3A57_P_2,
2274   EVEX_W_0F3A66_P_2,
2275   EVEX_W_0F3A67_P_2,
2276   EVEX_W_0F3A70_P_2,
2277   EVEX_W_0F3A71_P_2,
2278   EVEX_W_0F3A72_P_2,
2279   EVEX_W_0F3A73_P_2,
2280   EVEX_W_0F3ACE_P_2,
2281   EVEX_W_0F3ACF_P_2
2282 };
2283
2284 typedef void (*op_rtn) (int bytemode, int sizeflag);
2285
2286 struct dis386 {
2287   const char *name;
2288   struct
2289     {
2290       op_rtn rtn;
2291       int bytemode;
2292     } op[MAX_OPERANDS];
2293   unsigned int prefix_requirement;
2294 };
2295
2296 /* Upper case letters in the instruction names here are macros.
2297    'A' => print 'b' if no register operands or suffix_always is true
2298    'B' => print 'b' if suffix_always is true
2299    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2300           size prefix
2301    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2302           suffix_always is true
2303    'E' => print 'e' if 32-bit form of jcxz
2304    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2305    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2306    'H' => print ",pt" or ",pn" branch hint
2307    'I' => honor following macro letter even in Intel mode (implemented only
2308           for some of the macro letters)
2309    'J' => print 'l'
2310    'K' => print 'd' or 'q' if rex prefix is present.
2311    'L' => print 'l' if suffix_always is true
2312    'M' => print 'r' if intel_mnemonic is false.
2313    'N' => print 'n' if instruction has no wait "prefix"
2314    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2315    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2316           or suffix_always is true.  print 'q' if rex prefix is present.
2317    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2318           is true
2319    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2320    'S' => print 'w', 'l' or 'q' if suffix_always is true
2321    'T' => print 'q' in 64bit mode if instruction has no operand size
2322           prefix and behave as 'P' otherwise
2323    'U' => print 'q' in 64bit mode if instruction has no operand size
2324           prefix and behave as 'Q' otherwise
2325    'V' => print 'q' in 64bit mode if instruction has no operand size
2326           prefix and behave as 'S' otherwise
2327    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2328    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2329    'Y' unused.
2330    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2331    '!' => change condition from true to false or from false to true.
2332    '%' => add 1 upper case letter to the macro.
2333    '^' => print 'w' or 'l' depending on operand size prefix or
2334           suffix_always is true (lcall/ljmp).
2335    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2336           on operand size prefix.
2337    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2338           has no operand size prefix for AMD64 ISA, behave as 'P'
2339           otherwise
2340
2341    2 upper case letter macros:
2342    "XY" => print 'x' or 'y' if suffix_always is true or no register
2343            operands and no broadcast.
2344    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2345            register operands and no broadcast.
2346    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2347    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2348            or suffix_always is true
2349    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2350    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2351    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2352    "LW" => print 'd', 'q' depending on the VEX.W bit
2353    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2354            an operand size prefix, or suffix_always is true.  print
2355            'q' if rex prefix is present.
2356
2357    Many of the above letters print nothing in Intel mode.  See "putop"
2358    for the details.
2359
2360    Braces '{' and '}', and vertical bars '|', indicate alternative
2361    mnemonic strings for AT&T and Intel.  */
2362
2363 static const struct dis386 dis386[] = {
2364   /* 00 */
2365   { "addB",             { Ebh1, Gb }, 0 },
2366   { "addS",             { Evh1, Gv }, 0 },
2367   { "addB",             { Gb, EbS }, 0 },
2368   { "addS",             { Gv, EvS }, 0 },
2369   { "addB",             { AL, Ib }, 0 },
2370   { "addS",             { eAX, Iv }, 0 },
2371   { X86_64_TABLE (X86_64_06) },
2372   { X86_64_TABLE (X86_64_07) },
2373   /* 08 */
2374   { "orB",              { Ebh1, Gb }, 0 },
2375   { "orS",              { Evh1, Gv }, 0 },
2376   { "orB",              { Gb, EbS }, 0 },
2377   { "orS",              { Gv, EvS }, 0 },
2378   { "orB",              { AL, Ib }, 0 },
2379   { "orS",              { eAX, Iv }, 0 },
2380   { X86_64_TABLE (X86_64_0D) },
2381   { Bad_Opcode },       /* 0x0f extended opcode escape */
2382   /* 10 */
2383   { "adcB",             { Ebh1, Gb }, 0 },
2384   { "adcS",             { Evh1, Gv }, 0 },
2385   { "adcB",             { Gb, EbS }, 0 },
2386   { "adcS",             { Gv, EvS }, 0 },
2387   { "adcB",             { AL, Ib }, 0 },
2388   { "adcS",             { eAX, Iv }, 0 },
2389   { X86_64_TABLE (X86_64_16) },
2390   { X86_64_TABLE (X86_64_17) },
2391   /* 18 */
2392   { "sbbB",             { Ebh1, Gb }, 0 },
2393   { "sbbS",             { Evh1, Gv }, 0 },
2394   { "sbbB",             { Gb, EbS }, 0 },
2395   { "sbbS",             { Gv, EvS }, 0 },
2396   { "sbbB",             { AL, Ib }, 0 },
2397   { "sbbS",             { eAX, Iv }, 0 },
2398   { X86_64_TABLE (X86_64_1E) },
2399   { X86_64_TABLE (X86_64_1F) },
2400   /* 20 */
2401   { "andB",             { Ebh1, Gb }, 0 },
2402   { "andS",             { Evh1, Gv }, 0 },
2403   { "andB",             { Gb, EbS }, 0 },
2404   { "andS",             { Gv, EvS }, 0 },
2405   { "andB",             { AL, Ib }, 0 },
2406   { "andS",             { eAX, Iv }, 0 },
2407   { Bad_Opcode },       /* SEG ES prefix */
2408   { X86_64_TABLE (X86_64_27) },
2409   /* 28 */
2410   { "subB",             { Ebh1, Gb }, 0 },
2411   { "subS",             { Evh1, Gv }, 0 },
2412   { "subB",             { Gb, EbS }, 0 },
2413   { "subS",             { Gv, EvS }, 0 },
2414   { "subB",             { AL, Ib }, 0 },
2415   { "subS",             { eAX, Iv }, 0 },
2416   { Bad_Opcode },       /* SEG CS prefix */
2417   { X86_64_TABLE (X86_64_2F) },
2418   /* 30 */
2419   { "xorB",             { Ebh1, Gb }, 0 },
2420   { "xorS",             { Evh1, Gv }, 0 },
2421   { "xorB",             { Gb, EbS }, 0 },
2422   { "xorS",             { Gv, EvS }, 0 },
2423   { "xorB",             { AL, Ib }, 0 },
2424   { "xorS",             { eAX, Iv }, 0 },
2425   { Bad_Opcode },       /* SEG SS prefix */
2426   { X86_64_TABLE (X86_64_37) },
2427   /* 38 */
2428   { "cmpB",             { Eb, Gb }, 0 },
2429   { "cmpS",             { Ev, Gv }, 0 },
2430   { "cmpB",             { Gb, EbS }, 0 },
2431   { "cmpS",             { Gv, EvS }, 0 },
2432   { "cmpB",             { AL, Ib }, 0 },
2433   { "cmpS",             { eAX, Iv }, 0 },
2434   { Bad_Opcode },       /* SEG DS prefix */
2435   { X86_64_TABLE (X86_64_3F) },
2436   /* 40 */
2437   { "inc{S|}",          { RMeAX }, 0 },
2438   { "inc{S|}",          { RMeCX }, 0 },
2439   { "inc{S|}",          { RMeDX }, 0 },
2440   { "inc{S|}",          { RMeBX }, 0 },
2441   { "inc{S|}",          { RMeSP }, 0 },
2442   { "inc{S|}",          { RMeBP }, 0 },
2443   { "inc{S|}",          { RMeSI }, 0 },
2444   { "inc{S|}",          { RMeDI }, 0 },
2445   /* 48 */
2446   { "dec{S|}",          { RMeAX }, 0 },
2447   { "dec{S|}",          { RMeCX }, 0 },
2448   { "dec{S|}",          { RMeDX }, 0 },
2449   { "dec{S|}",          { RMeBX }, 0 },
2450   { "dec{S|}",          { RMeSP }, 0 },
2451   { "dec{S|}",          { RMeBP }, 0 },
2452   { "dec{S|}",          { RMeSI }, 0 },
2453   { "dec{S|}",          { RMeDI }, 0 },
2454   /* 50 */
2455   { "pushV",            { RMrAX }, 0 },
2456   { "pushV",            { RMrCX }, 0 },
2457   { "pushV",            { RMrDX }, 0 },
2458   { "pushV",            { RMrBX }, 0 },
2459   { "pushV",            { RMrSP }, 0 },
2460   { "pushV",            { RMrBP }, 0 },
2461   { "pushV",            { RMrSI }, 0 },
2462   { "pushV",            { RMrDI }, 0 },
2463   /* 58 */
2464   { "popV",             { RMrAX }, 0 },
2465   { "popV",             { RMrCX }, 0 },
2466   { "popV",             { RMrDX }, 0 },
2467   { "popV",             { RMrBX }, 0 },
2468   { "popV",             { RMrSP }, 0 },
2469   { "popV",             { RMrBP }, 0 },
2470   { "popV",             { RMrSI }, 0 },
2471   { "popV",             { RMrDI }, 0 },
2472   /* 60 */
2473   { X86_64_TABLE (X86_64_60) },
2474   { X86_64_TABLE (X86_64_61) },
2475   { X86_64_TABLE (X86_64_62) },
2476   { X86_64_TABLE (X86_64_63) },
2477   { Bad_Opcode },       /* seg fs */
2478   { Bad_Opcode },       /* seg gs */
2479   { Bad_Opcode },       /* op size prefix */
2480   { Bad_Opcode },       /* adr size prefix */
2481   /* 68 */
2482   { "pushT",            { sIv }, 0 },
2483   { "imulS",            { Gv, Ev, Iv }, 0 },
2484   { "pushT",            { sIbT }, 0 },
2485   { "imulS",            { Gv, Ev, sIb }, 0 },
2486   { "ins{b|}",          { Ybr, indirDX }, 0 },
2487   { X86_64_TABLE (X86_64_6D) },
2488   { "outs{b|}",         { indirDXr, Xb }, 0 },
2489   { X86_64_TABLE (X86_64_6F) },
2490   /* 70 */
2491   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2492   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2493   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2494   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2495   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2496   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2497   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2498   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2499   /* 78 */
2500   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2501   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2502   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2503   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2504   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2505   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2506   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2507   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2508   /* 80 */
2509   { REG_TABLE (REG_80) },
2510   { REG_TABLE (REG_81) },
2511   { X86_64_TABLE (X86_64_82) },
2512   { REG_TABLE (REG_83) },
2513   { "testB",            { Eb, Gb }, 0 },
2514   { "testS",            { Ev, Gv }, 0 },
2515   { "xchgB",            { Ebh2, Gb }, 0 },
2516   { "xchgS",            { Evh2, Gv }, 0 },
2517   /* 88 */
2518   { "movB",             { Ebh3, Gb }, 0 },
2519   { "movS",             { Evh3, Gv }, 0 },
2520   { "movB",             { Gb, EbS }, 0 },
2521   { "movS",             { Gv, EvS }, 0 },
2522   { "movD",             { Sv, Sw }, 0 },
2523   { MOD_TABLE (MOD_8D) },
2524   { "movD",             { Sw, Sv }, 0 },
2525   { REG_TABLE (REG_8F) },
2526   /* 90 */
2527   { PREFIX_TABLE (PREFIX_90) },
2528   { "xchgS",            { RMeCX, eAX }, 0 },
2529   { "xchgS",            { RMeDX, eAX }, 0 },
2530   { "xchgS",            { RMeBX, eAX }, 0 },
2531   { "xchgS",            { RMeSP, eAX }, 0 },
2532   { "xchgS",            { RMeBP, eAX }, 0 },
2533   { "xchgS",            { RMeSI, eAX }, 0 },
2534   { "xchgS",            { RMeDI, eAX }, 0 },
2535   /* 98 */
2536   { "cW{t|}R",          { XX }, 0 },
2537   { "cR{t|}O",          { XX }, 0 },
2538   { X86_64_TABLE (X86_64_9A) },
2539   { Bad_Opcode },       /* fwait */
2540   { "pushfT",           { XX }, 0 },
2541   { "popfT",            { XX }, 0 },
2542   { "sahf",             { XX }, 0 },
2543   { "lahf",             { XX }, 0 },
2544   /* a0 */
2545   { "mov%LB",           { AL, Ob }, 0 },
2546   { "mov%LS",           { eAX, Ov }, 0 },
2547   { "mov%LB",           { Ob, AL }, 0 },
2548   { "mov%LS",           { Ov, eAX }, 0 },
2549   { "movs{b|}",         { Ybr, Xb }, 0 },
2550   { "movs{R|}",         { Yvr, Xv }, 0 },
2551   { "cmps{b|}",         { Xb, Yb }, 0 },
2552   { "cmps{R|}",         { Xv, Yv }, 0 },
2553   /* a8 */
2554   { "testB",            { AL, Ib }, 0 },
2555   { "testS",            { eAX, Iv }, 0 },
2556   { "stosB",            { Ybr, AL }, 0 },
2557   { "stosS",            { Yvr, eAX }, 0 },
2558   { "lodsB",            { ALr, Xb }, 0 },
2559   { "lodsS",            { eAXr, Xv }, 0 },
2560   { "scasB",            { AL, Yb }, 0 },
2561   { "scasS",            { eAX, Yv }, 0 },
2562   /* b0 */
2563   { "movB",             { RMAL, Ib }, 0 },
2564   { "movB",             { RMCL, Ib }, 0 },
2565   { "movB",             { RMDL, Ib }, 0 },
2566   { "movB",             { RMBL, Ib }, 0 },
2567   { "movB",             { RMAH, Ib }, 0 },
2568   { "movB",             { RMCH, Ib }, 0 },
2569   { "movB",             { RMDH, Ib }, 0 },
2570   { "movB",             { RMBH, Ib }, 0 },
2571   /* b8 */
2572   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2573   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2574   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2575   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2576   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2577   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2578   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2579   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2580   /* c0 */
2581   { REG_TABLE (REG_C0) },
2582   { REG_TABLE (REG_C1) },
2583   { "retT",             { Iw, BND }, 0 },
2584   { "retT",             { BND }, 0 },
2585   { X86_64_TABLE (X86_64_C4) },
2586   { X86_64_TABLE (X86_64_C5) },
2587   { REG_TABLE (REG_C6) },
2588   { REG_TABLE (REG_C7) },
2589   /* c8 */
2590   { "enterT",           { Iw, Ib }, 0 },
2591   { "leaveT",           { XX }, 0 },
2592   { "Jret{|f}P",        { Iw }, 0 },
2593   { "Jret{|f}P",        { XX }, 0 },
2594   { "int3",             { XX }, 0 },
2595   { "int",              { Ib }, 0 },
2596   { X86_64_TABLE (X86_64_CE) },
2597   { "iret%LP",          { XX }, 0 },
2598   /* d0 */
2599   { REG_TABLE (REG_D0) },
2600   { REG_TABLE (REG_D1) },
2601   { REG_TABLE (REG_D2) },
2602   { REG_TABLE (REG_D3) },
2603   { X86_64_TABLE (X86_64_D4) },
2604   { X86_64_TABLE (X86_64_D5) },
2605   { Bad_Opcode },
2606   { "xlat",             { DSBX }, 0 },
2607   /* d8 */
2608   { FLOAT },
2609   { FLOAT },
2610   { FLOAT },
2611   { FLOAT },
2612   { FLOAT },
2613   { FLOAT },
2614   { FLOAT },
2615   { FLOAT },
2616   /* e0 */
2617   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2618   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2619   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2620   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2621   { "inB",              { AL, Ib }, 0 },
2622   { "inG",              { zAX, Ib }, 0 },
2623   { "outB",             { Ib, AL }, 0 },
2624   { "outG",             { Ib, zAX }, 0 },
2625   /* e8 */
2626   { X86_64_TABLE (X86_64_E8) },
2627   { X86_64_TABLE (X86_64_E9) },
2628   { X86_64_TABLE (X86_64_EA) },
2629   { "jmp",              { Jb, BND }, 0 },
2630   { "inB",              { AL, indirDX }, 0 },
2631   { "inG",              { zAX, indirDX }, 0 },
2632   { "outB",             { indirDX, AL }, 0 },
2633   { "outG",             { indirDX, zAX }, 0 },
2634   /* f0 */
2635   { Bad_Opcode },       /* lock prefix */
2636   { "icebp",            { XX }, 0 },
2637   { Bad_Opcode },       /* repne */
2638   { Bad_Opcode },       /* repz */
2639   { "hlt",              { XX }, 0 },
2640   { "cmc",              { XX }, 0 },
2641   { REG_TABLE (REG_F6) },
2642   { REG_TABLE (REG_F7) },
2643   /* f8 */
2644   { "clc",              { XX }, 0 },
2645   { "stc",              { XX }, 0 },
2646   { "cli",              { XX }, 0 },
2647   { "sti",              { XX }, 0 },
2648   { "cld",              { XX }, 0 },
2649   { "std",              { XX }, 0 },
2650   { REG_TABLE (REG_FE) },
2651   { REG_TABLE (REG_FF) },
2652 };
2653
2654 static const struct dis386 dis386_twobyte[] = {
2655   /* 00 */
2656   { REG_TABLE (REG_0F00 ) },
2657   { REG_TABLE (REG_0F01 ) },
2658   { "larS",             { Gv, Ew }, 0 },
2659   { "lslS",             { Gv, Ew }, 0 },
2660   { Bad_Opcode },
2661   { "syscall",          { XX }, 0 },
2662   { "clts",             { XX }, 0 },
2663   { "sysret%LP",                { XX }, 0 },
2664   /* 08 */
2665   { "invd",             { XX }, 0 },
2666   { PREFIX_TABLE (PREFIX_0F09) },
2667   { Bad_Opcode },
2668   { "ud2",              { XX }, 0 },
2669   { Bad_Opcode },
2670   { REG_TABLE (REG_0F0D) },
2671   { "femms",            { XX }, 0 },
2672   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2673   /* 10 */
2674   { PREFIX_TABLE (PREFIX_0F10) },
2675   { PREFIX_TABLE (PREFIX_0F11) },
2676   { PREFIX_TABLE (PREFIX_0F12) },
2677   { MOD_TABLE (MOD_0F13) },
2678   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2679   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2680   { PREFIX_TABLE (PREFIX_0F16) },
2681   { MOD_TABLE (MOD_0F17) },
2682   /* 18 */
2683   { REG_TABLE (REG_0F18) },
2684   { "nopQ",             { Ev }, 0 },
2685   { PREFIX_TABLE (PREFIX_0F1A) },
2686   { PREFIX_TABLE (PREFIX_0F1B) },
2687   { PREFIX_TABLE (PREFIX_0F1C) },
2688   { "nopQ",             { Ev }, 0 },
2689   { PREFIX_TABLE (PREFIX_0F1E) },
2690   { "nopQ",             { Ev }, 0 },
2691   /* 20 */
2692   { "movZ",             { Rm, Cm }, 0 },
2693   { "movZ",             { Rm, Dm }, 0 },
2694   { "movZ",             { Cm, Rm }, 0 },
2695   { "movZ",             { Dm, Rm }, 0 },
2696   { MOD_TABLE (MOD_0F24) },
2697   { Bad_Opcode },
2698   { MOD_TABLE (MOD_0F26) },
2699   { Bad_Opcode },
2700   /* 28 */
2701   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2702   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2703   { PREFIX_TABLE (PREFIX_0F2A) },
2704   { PREFIX_TABLE (PREFIX_0F2B) },
2705   { PREFIX_TABLE (PREFIX_0F2C) },
2706   { PREFIX_TABLE (PREFIX_0F2D) },
2707   { PREFIX_TABLE (PREFIX_0F2E) },
2708   { PREFIX_TABLE (PREFIX_0F2F) },
2709   /* 30 */
2710   { "wrmsr",            { XX }, 0 },
2711   { "rdtsc",            { XX }, 0 },
2712   { "rdmsr",            { XX }, 0 },
2713   { "rdpmc",            { XX }, 0 },
2714   { "sysenter",         { XX }, 0 },
2715   { "sysexit",          { XX }, 0 },
2716   { Bad_Opcode },
2717   { "getsec",           { XX }, 0 },
2718   /* 38 */
2719   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2720   { Bad_Opcode },
2721   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2722   { Bad_Opcode },
2723   { Bad_Opcode },
2724   { Bad_Opcode },
2725   { Bad_Opcode },
2726   { Bad_Opcode },
2727   /* 40 */
2728   { "cmovoS",           { Gv, Ev }, 0 },
2729   { "cmovnoS",          { Gv, Ev }, 0 },
2730   { "cmovbS",           { Gv, Ev }, 0 },
2731   { "cmovaeS",          { Gv, Ev }, 0 },
2732   { "cmoveS",           { Gv, Ev }, 0 },
2733   { "cmovneS",          { Gv, Ev }, 0 },
2734   { "cmovbeS",          { Gv, Ev }, 0 },
2735   { "cmovaS",           { Gv, Ev }, 0 },
2736   /* 48 */
2737   { "cmovsS",           { Gv, Ev }, 0 },
2738   { "cmovnsS",          { Gv, Ev }, 0 },
2739   { "cmovpS",           { Gv, Ev }, 0 },
2740   { "cmovnpS",          { Gv, Ev }, 0 },
2741   { "cmovlS",           { Gv, Ev }, 0 },
2742   { "cmovgeS",          { Gv, Ev }, 0 },
2743   { "cmovleS",          { Gv, Ev }, 0 },
2744   { "cmovgS",           { Gv, Ev }, 0 },
2745   /* 50 */
2746   { MOD_TABLE (MOD_0F51) },
2747   { PREFIX_TABLE (PREFIX_0F51) },
2748   { PREFIX_TABLE (PREFIX_0F52) },
2749   { PREFIX_TABLE (PREFIX_0F53) },
2750   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2751   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2752   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2753   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2754   /* 58 */
2755   { PREFIX_TABLE (PREFIX_0F58) },
2756   { PREFIX_TABLE (PREFIX_0F59) },
2757   { PREFIX_TABLE (PREFIX_0F5A) },
2758   { PREFIX_TABLE (PREFIX_0F5B) },
2759   { PREFIX_TABLE (PREFIX_0F5C) },
2760   { PREFIX_TABLE (PREFIX_0F5D) },
2761   { PREFIX_TABLE (PREFIX_0F5E) },
2762   { PREFIX_TABLE (PREFIX_0F5F) },
2763   /* 60 */
2764   { PREFIX_TABLE (PREFIX_0F60) },
2765   { PREFIX_TABLE (PREFIX_0F61) },
2766   { PREFIX_TABLE (PREFIX_0F62) },
2767   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2768   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2769   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2770   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2771   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2772   /* 68 */
2773   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2774   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2775   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2776   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2777   { PREFIX_TABLE (PREFIX_0F6C) },
2778   { PREFIX_TABLE (PREFIX_0F6D) },
2779   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2780   { PREFIX_TABLE (PREFIX_0F6F) },
2781   /* 70 */
2782   { PREFIX_TABLE (PREFIX_0F70) },
2783   { REG_TABLE (REG_0F71) },
2784   { REG_TABLE (REG_0F72) },
2785   { REG_TABLE (REG_0F73) },
2786   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2787   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2788   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2789   { "emms",             { XX }, PREFIX_OPCODE },
2790   /* 78 */
2791   { PREFIX_TABLE (PREFIX_0F78) },
2792   { PREFIX_TABLE (PREFIX_0F79) },
2793   { Bad_Opcode },
2794   { Bad_Opcode },
2795   { PREFIX_TABLE (PREFIX_0F7C) },
2796   { PREFIX_TABLE (PREFIX_0F7D) },
2797   { PREFIX_TABLE (PREFIX_0F7E) },
2798   { PREFIX_TABLE (PREFIX_0F7F) },
2799   /* 80 */
2800   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2801   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2802   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2803   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2804   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2805   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2806   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2807   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2808   /* 88 */
2809   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2810   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2811   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2812   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2813   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2814   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2815   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2816   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2817   /* 90 */
2818   { "seto",             { Eb }, 0 },
2819   { "setno",            { Eb }, 0 },
2820   { "setb",             { Eb }, 0 },
2821   { "setae",            { Eb }, 0 },
2822   { "sete",             { Eb }, 0 },
2823   { "setne",            { Eb }, 0 },
2824   { "setbe",            { Eb }, 0 },
2825   { "seta",             { Eb }, 0 },
2826   /* 98 */
2827   { "sets",             { Eb }, 0 },
2828   { "setns",            { Eb }, 0 },
2829   { "setp",             { Eb }, 0 },
2830   { "setnp",            { Eb }, 0 },
2831   { "setl",             { Eb }, 0 },
2832   { "setge",            { Eb }, 0 },
2833   { "setle",            { Eb }, 0 },
2834   { "setg",             { Eb }, 0 },
2835   /* a0 */
2836   { "pushT",            { fs }, 0 },
2837   { "popT",             { fs }, 0 },
2838   { "cpuid",            { XX }, 0 },
2839   { "btS",              { Ev, Gv }, 0 },
2840   { "shldS",            { Ev, Gv, Ib }, 0 },
2841   { "shldS",            { Ev, Gv, CL }, 0 },
2842   { REG_TABLE (REG_0FA6) },
2843   { REG_TABLE (REG_0FA7) },
2844   /* a8 */
2845   { "pushT",            { gs }, 0 },
2846   { "popT",             { gs }, 0 },
2847   { "rsm",              { XX }, 0 },
2848   { "btsS",             { Evh1, Gv }, 0 },
2849   { "shrdS",            { Ev, Gv, Ib }, 0 },
2850   { "shrdS",            { Ev, Gv, CL }, 0 },
2851   { REG_TABLE (REG_0FAE) },
2852   { "imulS",            { Gv, Ev }, 0 },
2853   /* b0 */
2854   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2855   { "cmpxchgS",         { Evh1, Gv }, 0 },
2856   { MOD_TABLE (MOD_0FB2) },
2857   { "btrS",             { Evh1, Gv }, 0 },
2858   { MOD_TABLE (MOD_0FB4) },
2859   { MOD_TABLE (MOD_0FB5) },
2860   { "movz{bR|x}",       { Gv, Eb }, 0 },
2861   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2862   /* b8 */
2863   { PREFIX_TABLE (PREFIX_0FB8) },
2864   { "ud1S",             { Gv, Ev }, 0 },
2865   { REG_TABLE (REG_0FBA) },
2866   { "btcS",             { Evh1, Gv }, 0 },
2867   { PREFIX_TABLE (PREFIX_0FBC) },
2868   { PREFIX_TABLE (PREFIX_0FBD) },
2869   { "movs{bR|x}",       { Gv, Eb }, 0 },
2870   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2871   /* c0 */
2872   { "xaddB",            { Ebh1, Gb }, 0 },
2873   { "xaddS",            { Evh1, Gv }, 0 },
2874   { PREFIX_TABLE (PREFIX_0FC2) },
2875   { MOD_TABLE (MOD_0FC3) },
2876   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2877   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2878   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2879   { REG_TABLE (REG_0FC7) },
2880   /* c8 */
2881   { "bswap",            { RMeAX }, 0 },
2882   { "bswap",            { RMeCX }, 0 },
2883   { "bswap",            { RMeDX }, 0 },
2884   { "bswap",            { RMeBX }, 0 },
2885   { "bswap",            { RMeSP }, 0 },
2886   { "bswap",            { RMeBP }, 0 },
2887   { "bswap",            { RMeSI }, 0 },
2888   { "bswap",            { RMeDI }, 0 },
2889   /* d0 */
2890   { PREFIX_TABLE (PREFIX_0FD0) },
2891   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2892   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2893   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2894   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2895   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2896   { PREFIX_TABLE (PREFIX_0FD6) },
2897   { MOD_TABLE (MOD_0FD7) },
2898   /* d8 */
2899   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2900   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2901   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2902   { "pand",             { MX, EM }, PREFIX_OPCODE },
2903   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2904   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2905   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2906   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2907   /* e0 */
2908   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2909   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2910   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2911   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2912   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2913   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2914   { PREFIX_TABLE (PREFIX_0FE6) },
2915   { PREFIX_TABLE (PREFIX_0FE7) },
2916   /* e8 */
2917   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2918   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2919   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2920   { "por",              { MX, EM }, PREFIX_OPCODE },
2921   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2922   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2923   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2924   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2925   /* f0 */
2926   { PREFIX_TABLE (PREFIX_0FF0) },
2927   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2928   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2929   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2930   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2931   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2932   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2933   { PREFIX_TABLE (PREFIX_0FF7) },
2934   /* f8 */
2935   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2936   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2937   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2938   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2939   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2940   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2941   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2942   { "ud0S",             { Gv, Ev }, 0 },
2943 };
2944
2945 static const unsigned char onebyte_has_modrm[256] = {
2946   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2947   /*       -------------------------------        */
2948   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2949   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2950   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2951   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2952   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2953   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2954   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2955   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2956   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2957   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2958   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2959   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2960   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2961   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2962   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2963   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2964   /*       -------------------------------        */
2965   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2966 };
2967
2968 static const unsigned char twobyte_has_modrm[256] = {
2969   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2970   /*       -------------------------------        */
2971   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2972   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2973   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2974   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2975   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2976   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2977   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2978   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2979   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2980   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2981   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2982   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2983   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2984   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2985   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2986   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2987   /*       -------------------------------        */
2988   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2989 };
2990
2991 static char obuf[100];
2992 static char *obufp;
2993 static char *mnemonicendp;
2994 static char scratchbuf[100];
2995 static unsigned char *start_codep;
2996 static unsigned char *insn_codep;
2997 static unsigned char *codep;
2998 static unsigned char *end_codep;
2999 static int last_lock_prefix;
3000 static int last_repz_prefix;
3001 static int last_repnz_prefix;
3002 static int last_data_prefix;
3003 static int last_addr_prefix;
3004 static int last_rex_prefix;
3005 static int last_seg_prefix;
3006 static int fwait_prefix;
3007 /* The active segment register prefix.  */
3008 static int active_seg_prefix;
3009 #define MAX_CODE_LENGTH 15
3010 /* We can up to 14 prefixes since the maximum instruction length is
3011    15bytes.  */
3012 static int all_prefixes[MAX_CODE_LENGTH - 1];
3013 static disassemble_info *the_info;
3014 static struct
3015   {
3016     int mod;
3017     int reg;
3018     int rm;
3019   }
3020 modrm;
3021 static unsigned char need_modrm;
3022 static struct
3023   {
3024     int scale;
3025     int index;
3026     int base;
3027   }
3028 sib;
3029 static struct
3030   {
3031     int register_specifier;
3032     int length;
3033     int prefix;
3034     int w;
3035     int evex;
3036     int r;
3037     int v;
3038     int mask_register_specifier;
3039     int zeroing;
3040     int ll;
3041     int b;
3042   }
3043 vex;
3044 static unsigned char need_vex;
3045 static unsigned char need_vex_reg;
3046 static unsigned char vex_w_done;
3047
3048 struct op
3049   {
3050     const char *name;
3051     unsigned int len;
3052   };
3053
3054 /* If we are accessing mod/rm/reg without need_modrm set, then the
3055    values are stale.  Hitting this abort likely indicates that you
3056    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3057 #define MODRM_CHECK  if (!need_modrm) abort ()
3058
3059 static const char **names64;
3060 static const char **names32;
3061 static const char **names16;
3062 static const char **names8;
3063 static const char **names8rex;
3064 static const char **names_seg;
3065 static const char *index64;
3066 static const char *index32;
3067 static const char **index16;
3068 static const char **names_bnd;
3069
3070 static const char *intel_names64[] = {
3071   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3072   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3073 };
3074 static const char *intel_names32[] = {
3075   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3076   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3077 };
3078 static const char *intel_names16[] = {
3079   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3080   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3081 };
3082 static const char *intel_names8[] = {
3083   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3084 };
3085 static const char *intel_names8rex[] = {
3086   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3087   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3088 };
3089 static const char *intel_names_seg[] = {
3090   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3091 };
3092 static const char *intel_index64 = "riz";
3093 static const char *intel_index32 = "eiz";
3094 static const char *intel_index16[] = {
3095   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3096 };
3097
3098 static const char *att_names64[] = {
3099   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3100   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3101 };
3102 static const char *att_names32[] = {
3103   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3104   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3105 };
3106 static const char *att_names16[] = {
3107   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3108   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3109 };
3110 static const char *att_names8[] = {
3111   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3112 };
3113 static const char *att_names8rex[] = {
3114   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3115   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3116 };
3117 static const char *att_names_seg[] = {
3118   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3119 };
3120 static const char *att_index64 = "%riz";
3121 static const char *att_index32 = "%eiz";
3122 static const char *att_index16[] = {
3123   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3124 };
3125
3126 static const char **names_mm;
3127 static const char *intel_names_mm[] = {
3128   "mm0", "mm1", "mm2", "mm3",
3129   "mm4", "mm5", "mm6", "mm7"
3130 };
3131 static const char *att_names_mm[] = {
3132   "%mm0", "%mm1", "%mm2", "%mm3",
3133   "%mm4", "%mm5", "%mm6", "%mm7"
3134 };
3135
3136 static const char *intel_names_bnd[] = {
3137   "bnd0", "bnd1", "bnd2", "bnd3"
3138 };
3139
3140 static const char *att_names_bnd[] = {
3141   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3142 };
3143
3144 static const char **names_xmm;
3145 static const char *intel_names_xmm[] = {
3146   "xmm0", "xmm1", "xmm2", "xmm3",
3147   "xmm4", "xmm5", "xmm6", "xmm7",
3148   "xmm8", "xmm9", "xmm10", "xmm11",
3149   "xmm12", "xmm13", "xmm14", "xmm15",
3150   "xmm16", "xmm17", "xmm18", "xmm19",
3151   "xmm20", "xmm21", "xmm22", "xmm23",
3152   "xmm24", "xmm25", "xmm26", "xmm27",
3153   "xmm28", "xmm29", "xmm30", "xmm31"
3154 };
3155 static const char *att_names_xmm[] = {
3156   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3157   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3158   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3159   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3160   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3161   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3162   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3163   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3164 };
3165
3166 static const char **names_ymm;
3167 static const char *intel_names_ymm[] = {
3168   "ymm0", "ymm1", "ymm2", "ymm3",
3169   "ymm4", "ymm5", "ymm6", "ymm7",
3170   "ymm8", "ymm9", "ymm10", "ymm11",
3171   "ymm12", "ymm13", "ymm14", "ymm15",
3172   "ymm16", "ymm17", "ymm18", "ymm19",
3173   "ymm20", "ymm21", "ymm22", "ymm23",
3174   "ymm24", "ymm25", "ymm26", "ymm27",
3175   "ymm28", "ymm29", "ymm30", "ymm31"
3176 };
3177 static const char *att_names_ymm[] = {
3178   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3179   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3180   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3181   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3182   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3183   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3184   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3185   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3186 };
3187
3188 static const char **names_zmm;
3189 static const char *intel_names_zmm[] = {
3190   "zmm0", "zmm1", "zmm2", "zmm3",
3191   "zmm4", "zmm5", "zmm6", "zmm7",
3192   "zmm8", "zmm9", "zmm10", "zmm11",
3193   "zmm12", "zmm13", "zmm14", "zmm15",
3194   "zmm16", "zmm17", "zmm18", "zmm19",
3195   "zmm20", "zmm21", "zmm22", "zmm23",
3196   "zmm24", "zmm25", "zmm26", "zmm27",
3197   "zmm28", "zmm29", "zmm30", "zmm31"
3198 };
3199 static const char *att_names_zmm[] = {
3200   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3201   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3202   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3203   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3204   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3205   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3206   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3207   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3208 };
3209
3210 static const char **names_mask;
3211 static const char *intel_names_mask[] = {
3212   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3213 };
3214 static const char *att_names_mask[] = {
3215   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3216 };
3217
3218 static const char *names_rounding[] =
3219 {
3220   "{rn-sae}",
3221   "{rd-sae}",
3222   "{ru-sae}",
3223   "{rz-sae}"
3224 };
3225
3226 static const struct dis386 reg_table[][8] = {
3227   /* REG_80 */
3228   {
3229     { "addA",   { Ebh1, Ib }, 0 },
3230     { "orA",    { Ebh1, Ib }, 0 },
3231     { "adcA",   { Ebh1, Ib }, 0 },
3232     { "sbbA",   { Ebh1, Ib }, 0 },
3233     { "andA",   { Ebh1, Ib }, 0 },
3234     { "subA",   { Ebh1, Ib }, 0 },
3235     { "xorA",   { Ebh1, Ib }, 0 },
3236     { "cmpA",   { Eb, Ib }, 0 },
3237   },
3238   /* REG_81 */
3239   {
3240     { "addQ",   { Evh1, Iv }, 0 },
3241     { "orQ",    { Evh1, Iv }, 0 },
3242     { "adcQ",   { Evh1, Iv }, 0 },
3243     { "sbbQ",   { Evh1, Iv }, 0 },
3244     { "andQ",   { Evh1, Iv }, 0 },
3245     { "subQ",   { Evh1, Iv }, 0 },
3246     { "xorQ",   { Evh1, Iv }, 0 },
3247     { "cmpQ",   { Ev, Iv }, 0 },
3248   },
3249   /* REG_83 */
3250   {
3251     { "addQ",   { Evh1, sIb }, 0 },
3252     { "orQ",    { Evh1, sIb }, 0 },
3253     { "adcQ",   { Evh1, sIb }, 0 },
3254     { "sbbQ",   { Evh1, sIb }, 0 },
3255     { "andQ",   { Evh1, sIb }, 0 },
3256     { "subQ",   { Evh1, sIb }, 0 },
3257     { "xorQ",   { Evh1, sIb }, 0 },
3258     { "cmpQ",   { Ev, sIb }, 0 },
3259   },
3260   /* REG_8F */
3261   {
3262     { "popU",   { stackEv }, 0 },
3263     { XOP_8F_TABLE (XOP_09) },
3264     { Bad_Opcode },
3265     { Bad_Opcode },
3266     { Bad_Opcode },
3267     { XOP_8F_TABLE (XOP_09) },
3268   },
3269   /* REG_C0 */
3270   {
3271     { "rolA",   { Eb, Ib }, 0 },
3272     { "rorA",   { Eb, Ib }, 0 },
3273     { "rclA",   { Eb, Ib }, 0 },
3274     { "rcrA",   { Eb, Ib }, 0 },
3275     { "shlA",   { Eb, Ib }, 0 },
3276     { "shrA",   { Eb, Ib }, 0 },
3277     { "shlA",   { Eb, Ib }, 0 },
3278     { "sarA",   { Eb, Ib }, 0 },
3279   },
3280   /* REG_C1 */
3281   {
3282     { "rolQ",   { Ev, Ib }, 0 },
3283     { "rorQ",   { Ev, Ib }, 0 },
3284     { "rclQ",   { Ev, Ib }, 0 },
3285     { "rcrQ",   { Ev, Ib }, 0 },
3286     { "shlQ",   { Ev, Ib }, 0 },
3287     { "shrQ",   { Ev, Ib }, 0 },
3288     { "shlQ",   { Ev, Ib }, 0 },
3289     { "sarQ",   { Ev, Ib }, 0 },
3290   },
3291   /* REG_C6 */
3292   {
3293     { "movA",   { Ebh3, Ib }, 0 },
3294     { Bad_Opcode },
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { MOD_TABLE (MOD_C6_REG_7) },
3301   },
3302   /* REG_C7 */
3303   {
3304     { "movQ",   { Evh3, Iv }, 0 },
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { MOD_TABLE (MOD_C7_REG_7) },
3312   },
3313   /* REG_D0 */
3314   {
3315     { "rolA",   { Eb, I1 }, 0 },
3316     { "rorA",   { Eb, I1 }, 0 },
3317     { "rclA",   { Eb, I1 }, 0 },
3318     { "rcrA",   { Eb, I1 }, 0 },
3319     { "shlA",   { Eb, I1 }, 0 },
3320     { "shrA",   { Eb, I1 }, 0 },
3321     { "shlA",   { Eb, I1 }, 0 },
3322     { "sarA",   { Eb, I1 }, 0 },
3323   },
3324   /* REG_D1 */
3325   {
3326     { "rolQ",   { Ev, I1 }, 0 },
3327     { "rorQ",   { Ev, I1 }, 0 },
3328     { "rclQ",   { Ev, I1 }, 0 },
3329     { "rcrQ",   { Ev, I1 }, 0 },
3330     { "shlQ",   { Ev, I1 }, 0 },
3331     { "shrQ",   { Ev, I1 }, 0 },
3332     { "shlQ",   { Ev, I1 }, 0 },
3333     { "sarQ",   { Ev, I1 }, 0 },
3334   },
3335   /* REG_D2 */
3336   {
3337     { "rolA",   { Eb, CL }, 0 },
3338     { "rorA",   { Eb, CL }, 0 },
3339     { "rclA",   { Eb, CL }, 0 },
3340     { "rcrA",   { Eb, CL }, 0 },
3341     { "shlA",   { Eb, CL }, 0 },
3342     { "shrA",   { Eb, CL }, 0 },
3343     { "shlA",   { Eb, CL }, 0 },
3344     { "sarA",   { Eb, CL }, 0 },
3345   },
3346   /* REG_D3 */
3347   {
3348     { "rolQ",   { Ev, CL }, 0 },
3349     { "rorQ",   { Ev, CL }, 0 },
3350     { "rclQ",   { Ev, CL }, 0 },
3351     { "rcrQ",   { Ev, CL }, 0 },
3352     { "shlQ",   { Ev, CL }, 0 },
3353     { "shrQ",   { Ev, CL }, 0 },
3354     { "shlQ",   { Ev, CL }, 0 },
3355     { "sarQ",   { Ev, CL }, 0 },
3356   },
3357   /* REG_F6 */
3358   {
3359     { "testA",  { Eb, Ib }, 0 },
3360     { "testA",  { Eb, Ib }, 0 },
3361     { "notA",   { Ebh1 }, 0 },
3362     { "negA",   { Ebh1 }, 0 },
3363     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3364     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3365     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3366     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3367   },
3368   /* REG_F7 */
3369   {
3370     { "testQ",  { Ev, Iv }, 0 },
3371     { "testQ",  { Ev, Iv }, 0 },
3372     { "notQ",   { Evh1 }, 0 },
3373     { "negQ",   { Evh1 }, 0 },
3374     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3375     { "imulQ",  { Ev }, 0 },
3376     { "divQ",   { Ev }, 0 },
3377     { "idivQ",  { Ev }, 0 },
3378   },
3379   /* REG_FE */
3380   {
3381     { "incA",   { Ebh1 }, 0 },
3382     { "decA",   { Ebh1 }, 0 },
3383   },
3384   /* REG_FF */
3385   {
3386     { "incQ",   { Evh1 }, 0 },
3387     { "decQ",   { Evh1 }, 0 },
3388     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3389     { MOD_TABLE (MOD_FF_REG_3) },
3390     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3391     { MOD_TABLE (MOD_FF_REG_5) },
3392     { "pushU",  { stackEv }, 0 },
3393     { Bad_Opcode },
3394   },
3395   /* REG_0F00 */
3396   {
3397     { "sldtD",  { Sv }, 0 },
3398     { "strD",   { Sv }, 0 },
3399     { "lldt",   { Ew }, 0 },
3400     { "ltr",    { Ew }, 0 },
3401     { "verr",   { Ew }, 0 },
3402     { "verw",   { Ew }, 0 },
3403     { Bad_Opcode },
3404     { Bad_Opcode },
3405   },
3406   /* REG_0F01 */
3407   {
3408     { MOD_TABLE (MOD_0F01_REG_0) },
3409     { MOD_TABLE (MOD_0F01_REG_1) },
3410     { MOD_TABLE (MOD_0F01_REG_2) },
3411     { MOD_TABLE (MOD_0F01_REG_3) },
3412     { "smswD",  { Sv }, 0 },
3413     { MOD_TABLE (MOD_0F01_REG_5) },
3414     { "lmsw",   { Ew }, 0 },
3415     { MOD_TABLE (MOD_0F01_REG_7) },
3416   },
3417   /* REG_0F0D */
3418   {
3419     { "prefetch",       { Mb }, 0 },
3420     { "prefetchw",      { Mb }, 0 },
3421     { "prefetchwt1",    { Mb }, 0 },
3422     { "prefetch",       { Mb }, 0 },
3423     { "prefetch",       { Mb }, 0 },
3424     { "prefetch",       { Mb }, 0 },
3425     { "prefetch",       { Mb }, 0 },
3426     { "prefetch",       { Mb }, 0 },
3427   },
3428   /* REG_0F18 */
3429   {
3430     { MOD_TABLE (MOD_0F18_REG_0) },
3431     { MOD_TABLE (MOD_0F18_REG_1) },
3432     { MOD_TABLE (MOD_0F18_REG_2) },
3433     { MOD_TABLE (MOD_0F18_REG_3) },
3434     { MOD_TABLE (MOD_0F18_REG_4) },
3435     { MOD_TABLE (MOD_0F18_REG_5) },
3436     { MOD_TABLE (MOD_0F18_REG_6) },
3437     { MOD_TABLE (MOD_0F18_REG_7) },
3438   },
3439   /* REG_0F1C_P_0_MOD_0 */
3440   {
3441     { "cldemote",       { Mb }, 0 },
3442     { "nopQ",           { Ev }, 0 },
3443     { "nopQ",           { Ev }, 0 },
3444     { "nopQ",           { Ev }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449   },
3450   /* REG_0F1E_P_1_MOD_3 */
3451   {
3452     { "nopQ",           { Ev }, 0 },
3453     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3454     { "nopQ",           { Ev }, 0 },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3460   },
3461   /* REG_0F71 */
3462   {
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { MOD_TABLE (MOD_0F71_REG_2) },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_0F71_REG_4) },
3468     { Bad_Opcode },
3469     { MOD_TABLE (MOD_0F71_REG_6) },
3470   },
3471   /* REG_0F72 */
3472   {
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475     { MOD_TABLE (MOD_0F72_REG_2) },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_0F72_REG_4) },
3478     { Bad_Opcode },
3479     { MOD_TABLE (MOD_0F72_REG_6) },
3480   },
3481   /* REG_0F73 */
3482   {
3483     { Bad_Opcode },
3484     { Bad_Opcode },
3485     { MOD_TABLE (MOD_0F73_REG_2) },
3486     { MOD_TABLE (MOD_0F73_REG_3) },
3487     { Bad_Opcode },
3488     { Bad_Opcode },
3489     { MOD_TABLE (MOD_0F73_REG_6) },
3490     { MOD_TABLE (MOD_0F73_REG_7) },
3491   },
3492   /* REG_0FA6 */
3493   {
3494     { "montmul",        { { OP_0f07, 0 } }, 0 },
3495     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3496     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3497   },
3498   /* REG_0FA7 */
3499   {
3500     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3501     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3502     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3503     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3504     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3505     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3506   },
3507   /* REG_0FAE */
3508   {
3509     { MOD_TABLE (MOD_0FAE_REG_0) },
3510     { MOD_TABLE (MOD_0FAE_REG_1) },
3511     { MOD_TABLE (MOD_0FAE_REG_2) },
3512     { MOD_TABLE (MOD_0FAE_REG_3) },
3513     { MOD_TABLE (MOD_0FAE_REG_4) },
3514     { MOD_TABLE (MOD_0FAE_REG_5) },
3515     { MOD_TABLE (MOD_0FAE_REG_6) },
3516     { MOD_TABLE (MOD_0FAE_REG_7) },
3517   },
3518   /* REG_0FBA */
3519   {
3520     { Bad_Opcode },
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { "btQ",    { Ev, Ib }, 0 },
3525     { "btsQ",   { Evh1, Ib }, 0 },
3526     { "btrQ",   { Evh1, Ib }, 0 },
3527     { "btcQ",   { Evh1, Ib }, 0 },
3528   },
3529   /* REG_0FC7 */
3530   {
3531     { Bad_Opcode },
3532     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3533     { Bad_Opcode },
3534     { MOD_TABLE (MOD_0FC7_REG_3) },
3535     { MOD_TABLE (MOD_0FC7_REG_4) },
3536     { MOD_TABLE (MOD_0FC7_REG_5) },
3537     { MOD_TABLE (MOD_0FC7_REG_6) },
3538     { MOD_TABLE (MOD_0FC7_REG_7) },
3539   },
3540   /* REG_VEX_0F71 */
3541   {
3542     { Bad_Opcode },
3543     { Bad_Opcode },
3544     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3547     { Bad_Opcode },
3548     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3549   },
3550   /* REG_VEX_0F72 */
3551   {
3552     { Bad_Opcode },
3553     { Bad_Opcode },
3554     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3555     { Bad_Opcode },
3556     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3557     { Bad_Opcode },
3558     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3559   },
3560   /* REG_VEX_0F73 */
3561   {
3562     { Bad_Opcode },
3563     { Bad_Opcode },
3564     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3565     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3566     { Bad_Opcode },
3567     { Bad_Opcode },
3568     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3569     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3570   },
3571   /* REG_VEX_0FAE */
3572   {
3573     { Bad_Opcode },
3574     { Bad_Opcode },
3575     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3576     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3577   },
3578   /* REG_VEX_0F38F3 */
3579   {
3580     { Bad_Opcode },
3581     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3582     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3583     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3584   },
3585   /* REG_XOP_LWPCB */
3586   {
3587     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3588     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3589   },
3590   /* REG_XOP_LWP */
3591   {
3592     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3593     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3594   },
3595   /* REG_XOP_TBM_01 */
3596   {
3597     { Bad_Opcode },
3598     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3599     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3600     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3601     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3602     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3603     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3604     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3605   },
3606   /* REG_XOP_TBM_02 */
3607   {
3608     { Bad_Opcode },
3609     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3610     { Bad_Opcode },
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3615   },
3616
3617 #include "i386-dis-evex-reg.h"
3618 };
3619
3620 static const struct dis386 prefix_table[][4] = {
3621   /* PREFIX_90 */
3622   {
3623     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3624     { "pause", { XX }, 0 },
3625     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3626     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3627   },
3628
3629   /* PREFIX_0F01_REG_5_MOD_0 */
3630   {
3631     { Bad_Opcode },
3632     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3633   },
3634
3635   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3636   {
3637     { Bad_Opcode },
3638     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3639   },
3640
3641   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3642   {
3643     { Bad_Opcode },
3644     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3645   },
3646
3647   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3648   {
3649     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3650     { "mcommit",        { Skip_MODRM }, 0 },
3651   },
3652
3653   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3654   {
3655     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3656   },
3657
3658   /* PREFIX_0F09 */
3659   {
3660     { "wbinvd",   { XX }, 0 },
3661     { "wbnoinvd", { XX }, 0 },
3662   },
3663
3664   /* PREFIX_0F10 */
3665   {
3666     { "movups", { XM, EXx }, PREFIX_OPCODE },
3667     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3668     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3669     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3670   },
3671
3672   /* PREFIX_0F11 */
3673   {
3674     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3675     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3676     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3677     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3678   },
3679
3680   /* PREFIX_0F12 */
3681   {
3682     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3683     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3684     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3685     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3686   },
3687
3688   /* PREFIX_0F16 */
3689   {
3690     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3691     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3692     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3693   },
3694
3695   /* PREFIX_0F1A */
3696   {
3697     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3698     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3699     { "bndmov", { Gbnd, Ebnd }, 0 },
3700     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3701   },
3702
3703   /* PREFIX_0F1B */
3704   {
3705     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3706     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3707     { "bndmov", { EbndS, Gbnd }, 0 },
3708     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3709   },
3710
3711   /* PREFIX_0F1C */
3712   {
3713     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3714     { "nopQ",   { Ev }, PREFIX_OPCODE },
3715     { "nopQ",   { Ev }, PREFIX_OPCODE },
3716     { "nopQ",   { Ev }, PREFIX_OPCODE },
3717   },
3718
3719   /* PREFIX_0F1E */
3720   {
3721     { "nopQ",   { Ev }, PREFIX_OPCODE },
3722     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3723     { "nopQ",   { Ev }, PREFIX_OPCODE },
3724     { "nopQ",   { Ev }, PREFIX_OPCODE },
3725   },
3726
3727   /* PREFIX_0F2A */
3728   {
3729     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3730     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3731     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3732     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3733   },
3734
3735   /* PREFIX_0F2B */
3736   {
3737     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3738     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3739     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3740     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3741   },
3742
3743   /* PREFIX_0F2C */
3744   {
3745     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3746     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3747     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3748     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3749   },
3750
3751   /* PREFIX_0F2D */
3752   {
3753     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3754     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3755     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3756     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F2E */
3760   {
3761     { "ucomiss",{ XM, EXd }, 0 },
3762     { Bad_Opcode },
3763     { "ucomisd",{ XM, EXq }, 0 },
3764   },
3765
3766   /* PREFIX_0F2F */
3767   {
3768     { "comiss", { XM, EXd }, 0 },
3769     { Bad_Opcode },
3770     { "comisd", { XM, EXq }, 0 },
3771   },
3772
3773   /* PREFIX_0F51 */
3774   {
3775     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3776     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3777     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3778     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3779   },
3780
3781   /* PREFIX_0F52 */
3782   {
3783     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3784     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3785   },
3786
3787   /* PREFIX_0F53 */
3788   {
3789     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3790     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3791   },
3792
3793   /* PREFIX_0F58 */
3794   {
3795     { "addps", { XM, EXx }, PREFIX_OPCODE },
3796     { "addss", { XM, EXd }, PREFIX_OPCODE },
3797     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3798     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3799   },
3800
3801   /* PREFIX_0F59 */
3802   {
3803     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3804     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3805     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3806     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3807   },
3808
3809   /* PREFIX_0F5A */
3810   {
3811     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3812     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3813     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3814     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3815   },
3816
3817   /* PREFIX_0F5B */
3818   {
3819     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3820     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3821     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3822   },
3823
3824   /* PREFIX_0F5C */
3825   {
3826     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3827     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3828     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3829     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_0F5D */
3833   {
3834     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3835     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3836     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3837     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3838   },
3839
3840   /* PREFIX_0F5E */
3841   {
3842     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3843     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3844     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3845     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3846   },
3847
3848   /* PREFIX_0F5F */
3849   {
3850     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3851     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3852     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3853     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F60 */
3857   {
3858     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3859     { Bad_Opcode },
3860     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3861   },
3862
3863   /* PREFIX_0F61 */
3864   {
3865     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3866     { Bad_Opcode },
3867     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3868   },
3869
3870   /* PREFIX_0F62 */
3871   {
3872     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3873     { Bad_Opcode },
3874     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3875   },
3876
3877   /* PREFIX_0F6C */
3878   {
3879     { Bad_Opcode },
3880     { Bad_Opcode },
3881     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3882   },
3883
3884   /* PREFIX_0F6D */
3885   {
3886     { Bad_Opcode },
3887     { Bad_Opcode },
3888     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3889   },
3890
3891   /* PREFIX_0F6F */
3892   {
3893     { "movq",   { MX, EM }, PREFIX_OPCODE },
3894     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3895     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3896   },
3897
3898   /* PREFIX_0F70 */
3899   {
3900     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3901     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3902     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3903     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3904   },
3905
3906   /* PREFIX_0F73_REG_3 */
3907   {
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { "psrldq", { XS, Ib }, 0 },
3911   },
3912
3913   /* PREFIX_0F73_REG_7 */
3914   {
3915     { Bad_Opcode },
3916     { Bad_Opcode },
3917     { "pslldq", { XS, Ib }, 0 },
3918   },
3919
3920   /* PREFIX_0F78 */
3921   {
3922     {"vmread",  { Em, Gm }, 0 },
3923     { Bad_Opcode },
3924     {"extrq",   { XS, Ib, Ib }, 0 },
3925     {"insertq", { XM, XS, Ib, Ib }, 0 },
3926   },
3927
3928   /* PREFIX_0F79 */
3929   {
3930     {"vmwrite", { Gm, Em }, 0 },
3931     { Bad_Opcode },
3932     {"extrq",   { XM, XS }, 0 },
3933     {"insertq", { XM, XS }, 0 },
3934   },
3935
3936   /* PREFIX_0F7C */
3937   {
3938     { Bad_Opcode },
3939     { Bad_Opcode },
3940     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3941     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3942   },
3943
3944   /* PREFIX_0F7D */
3945   {
3946     { Bad_Opcode },
3947     { Bad_Opcode },
3948     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3949     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3950   },
3951
3952   /* PREFIX_0F7E */
3953   {
3954     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3955     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3956     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3957   },
3958
3959   /* PREFIX_0F7F */
3960   {
3961     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3962     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3963     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3964   },
3965
3966   /* PREFIX_0FAE_REG_0_MOD_3 */
3967   {
3968     { Bad_Opcode },
3969     { "rdfsbase", { Ev }, 0 },
3970   },
3971
3972   /* PREFIX_0FAE_REG_1_MOD_3 */
3973   {
3974     { Bad_Opcode },
3975     { "rdgsbase", { Ev }, 0 },
3976   },
3977
3978   /* PREFIX_0FAE_REG_2_MOD_3 */
3979   {
3980     { Bad_Opcode },
3981     { "wrfsbase", { Ev }, 0 },
3982   },
3983
3984   /* PREFIX_0FAE_REG_3_MOD_3 */
3985   {
3986     { Bad_Opcode },
3987     { "wrgsbase", { Ev }, 0 },
3988   },
3989
3990   /* PREFIX_0FAE_REG_4_MOD_0 */
3991   {
3992     { "xsave",  { FXSAVE }, 0 },
3993     { "ptwrite%LQ", { Edq }, 0 },
3994   },
3995
3996   /* PREFIX_0FAE_REG_4_MOD_3 */
3997   {
3998     { Bad_Opcode },
3999     { "ptwrite%LQ", { Edq }, 0 },
4000   },
4001
4002   /* PREFIX_0FAE_REG_5_MOD_0 */
4003   {
4004     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4005   },
4006
4007   /* PREFIX_0FAE_REG_5_MOD_3 */
4008   {
4009     { "lfence",         { Skip_MODRM }, 0 },
4010     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4011   },
4012
4013   /* PREFIX_0FAE_REG_6_MOD_0 */
4014   {
4015     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4016     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4017     { "clwb",   { Mb }, PREFIX_OPCODE },
4018   },
4019
4020   /* PREFIX_0FAE_REG_6_MOD_3 */
4021   {
4022     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4023     { "umonitor",       { Eva }, PREFIX_OPCODE },
4024     { "tpause", { Edq }, PREFIX_OPCODE },
4025     { "umwait", { Edq }, PREFIX_OPCODE },
4026   },
4027
4028   /* PREFIX_0FAE_REG_7_MOD_0 */
4029   {
4030     { "clflush",        { Mb }, 0 },
4031     { Bad_Opcode },
4032     { "clflushopt",     { Mb }, 0 },
4033   },
4034
4035   /* PREFIX_0FB8 */
4036   {
4037     { Bad_Opcode },
4038     { "popcntS", { Gv, Ev }, 0 },
4039   },
4040
4041   /* PREFIX_0FBC */
4042   {
4043     { "bsfS",   { Gv, Ev }, 0 },
4044     { "tzcntS", { Gv, Ev }, 0 },
4045     { "bsfS",   { Gv, Ev }, 0 },
4046   },
4047
4048   /* PREFIX_0FBD */
4049   {
4050     { "bsrS",   { Gv, Ev }, 0 },
4051     { "lzcntS", { Gv, Ev }, 0 },
4052     { "bsrS",   { Gv, Ev }, 0 },
4053   },
4054
4055   /* PREFIX_0FC2 */
4056   {
4057     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4058     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4059     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4060     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4061   },
4062
4063   /* PREFIX_0FC3_MOD_0 */
4064   {
4065     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4066   },
4067
4068   /* PREFIX_0FC7_REG_6_MOD_0 */
4069   {
4070     { "vmptrld",{ Mq }, 0 },
4071     { "vmxon",  { Mq }, 0 },
4072     { "vmclear",{ Mq }, 0 },
4073   },
4074
4075   /* PREFIX_0FC7_REG_6_MOD_3 */
4076   {
4077     { "rdrand", { Ev }, 0 },
4078     { Bad_Opcode },
4079     { "rdrand", { Ev }, 0 }
4080   },
4081
4082   /* PREFIX_0FC7_REG_7_MOD_3 */
4083   {
4084     { "rdseed", { Ev }, 0 },
4085     { "rdpid",  { Em }, 0 },
4086     { "rdseed", { Ev }, 0 },
4087   },
4088
4089   /* PREFIX_0FD0 */
4090   {
4091     { Bad_Opcode },
4092     { Bad_Opcode },
4093     { "addsubpd", { XM, EXx }, 0 },
4094     { "addsubps", { XM, EXx }, 0 },
4095   },
4096
4097   /* PREFIX_0FD6 */
4098   {
4099     { Bad_Opcode },
4100     { "movq2dq",{ XM, MS }, 0 },
4101     { "movq",   { EXqS, XM }, 0 },
4102     { "movdq2q",{ MX, XS }, 0 },
4103   },
4104
4105   /* PREFIX_0FE6 */
4106   {
4107     { Bad_Opcode },
4108     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4109     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4110     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0FE7 */
4114   {
4115     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4116     { Bad_Opcode },
4117     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4118   },
4119
4120   /* PREFIX_0FF0 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4126   },
4127
4128   /* PREFIX_0FF7 */
4129   {
4130     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4131     { Bad_Opcode },
4132     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4133   },
4134
4135   /* PREFIX_0F3810 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4140   },
4141
4142   /* PREFIX_0F3814 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4147   },
4148
4149   /* PREFIX_0F3815 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4154   },
4155
4156   /* PREFIX_0F3817 */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4161   },
4162
4163   /* PREFIX_0F3820 */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4168   },
4169
4170   /* PREFIX_0F3821 */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0F3822 */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4182   },
4183
4184   /* PREFIX_0F3823 */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4189   },
4190
4191   /* PREFIX_0F3824 */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4196   },
4197
4198   /* PREFIX_0F3825 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4203   },
4204
4205   /* PREFIX_0F3828 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4210   },
4211
4212   /* PREFIX_0F3829 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4217   },
4218
4219   /* PREFIX_0F382A */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4224   },
4225
4226   /* PREFIX_0F382B */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_0F3830 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4238   },
4239
4240   /* PREFIX_0F3831 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4245   },
4246
4247   /* PREFIX_0F3832 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F3833 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F3834 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F3835 */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_0F3837 */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F3838 */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_0F3839 */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F383A */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F383B */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F383C */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F383D */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F383E */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F383F */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4336   },
4337
4338   /* PREFIX_0F3840 */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4343   },
4344
4345   /* PREFIX_0F3841 */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4350   },
4351
4352   /* PREFIX_0F3880 */
4353   {
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4357   },
4358
4359   /* PREFIX_0F3881 */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F3882 */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F38C8 */
4374   {
4375     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F38C9 */
4379   {
4380     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F38CA */
4384   {
4385     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38CB */
4389   {
4390     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F38CC */
4394   {
4395     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F38CD */
4399   {
4400     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F38CF */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F38DB */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F38DC */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F38DD */
4425   {
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F38DE */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4436   },
4437
4438   /* PREFIX_0F38DF */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4443   },
4444
4445   /* PREFIX_0F38F0 */
4446   {
4447     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4448     { Bad_Opcode },
4449     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4450     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4451   },
4452
4453   /* PREFIX_0F38F1 */
4454   {
4455     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4456     { Bad_Opcode },
4457     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4458     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F38F5 */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4466   },
4467
4468   /* PREFIX_0F38F6 */
4469   {
4470     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4471     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4472     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4473     { Bad_Opcode },
4474   },
4475
4476   /* PREFIX_0F38F8 */
4477   {
4478     { Bad_Opcode },
4479     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4480     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4481     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4482   },
4483
4484   /* PREFIX_0F38F9 */
4485   {
4486     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4487   },
4488
4489   /* PREFIX_0F3A08 */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F3A09 */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F3A0A */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F3A0B */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3A0C */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3A0D */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A0E */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A14 */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A15 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A16 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A17 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A20 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A21 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A22 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A40 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A41 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3A42 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3A44 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F3A60 */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4620   },
4621
4622   /* PREFIX_0F3A61 */
4623   {
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4627   },
4628
4629   /* PREFIX_0F3A62 */
4630   {
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4634   },
4635
4636   /* PREFIX_0F3A63 */
4637   {
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4641   },
4642
4643   /* PREFIX_0F3ACC */
4644   {
4645     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4646   },
4647
4648   /* PREFIX_0F3ACE */
4649   {
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4653   },
4654
4655   /* PREFIX_0F3ACF */
4656   {
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4660   },
4661
4662   /* PREFIX_0F3ADF */
4663   {
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4667   },
4668
4669   /* PREFIX_VEX_0F10 */
4670   {
4671     { "vmovups",        { XM, EXx }, 0 },
4672     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4673     { "vmovupd",        { XM, EXx }, 0 },
4674     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4675   },
4676
4677   /* PREFIX_VEX_0F11 */
4678   {
4679     { "vmovups",        { EXxS, XM }, 0 },
4680     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4681     { "vmovupd",        { EXxS, XM }, 0 },
4682     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4683   },
4684
4685   /* PREFIX_VEX_0F12 */
4686   {
4687     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4688     { "vmovsldup",      { XM, EXx }, 0 },
4689     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4690     { "vmovddup",       { XM, EXymmq }, 0 },
4691   },
4692
4693   /* PREFIX_VEX_0F16 */
4694   {
4695     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4696     { "vmovshdup",      { XM, EXx }, 0 },
4697     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4698   },
4699
4700   /* PREFIX_VEX_0F2A */
4701   {
4702     { Bad_Opcode },
4703     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4704     { Bad_Opcode },
4705     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4706   },
4707
4708   /* PREFIX_VEX_0F2C */
4709   {
4710     { Bad_Opcode },
4711     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4712     { Bad_Opcode },
4713     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4714   },
4715
4716   /* PREFIX_VEX_0F2D */
4717   {
4718     { Bad_Opcode },
4719     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4720     { Bad_Opcode },
4721     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4722   },
4723
4724   /* PREFIX_VEX_0F2E */
4725   {
4726     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4727     { Bad_Opcode },
4728     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4729   },
4730
4731   /* PREFIX_VEX_0F2F */
4732   {
4733     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4734     { Bad_Opcode },
4735     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4736   },
4737
4738   /* PREFIX_VEX_0F41 */
4739   {
4740     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4741     { Bad_Opcode },
4742     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4743   },
4744
4745   /* PREFIX_VEX_0F42 */
4746   {
4747     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4750   },
4751
4752   /* PREFIX_VEX_0F44 */
4753   {
4754     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4755     { Bad_Opcode },
4756     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4757   },
4758
4759   /* PREFIX_VEX_0F45 */
4760   {
4761     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4762     { Bad_Opcode },
4763     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4764   },
4765
4766   /* PREFIX_VEX_0F46 */
4767   {
4768     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4769     { Bad_Opcode },
4770     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4771   },
4772
4773   /* PREFIX_VEX_0F47 */
4774   {
4775     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4776     { Bad_Opcode },
4777     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4778   },
4779
4780   /* PREFIX_VEX_0F4A */
4781   {
4782     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4783     { Bad_Opcode },
4784     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4785   },
4786
4787   /* PREFIX_VEX_0F4B */
4788   {
4789     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4790     { Bad_Opcode },
4791     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4792   },
4793
4794   /* PREFIX_VEX_0F51 */
4795   {
4796     { "vsqrtps",        { XM, EXx }, 0 },
4797     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4798     { "vsqrtpd",        { XM, EXx }, 0 },
4799     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4800   },
4801
4802   /* PREFIX_VEX_0F52 */
4803   {
4804     { "vrsqrtps",       { XM, EXx }, 0 },
4805     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4806   },
4807
4808   /* PREFIX_VEX_0F53 */
4809   {
4810     { "vrcpps",         { XM, EXx }, 0 },
4811     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4812   },
4813
4814   /* PREFIX_VEX_0F58 */
4815   {
4816     { "vaddps",         { XM, Vex, EXx }, 0 },
4817     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4818     { "vaddpd",         { XM, Vex, EXx }, 0 },
4819     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4820   },
4821
4822   /* PREFIX_VEX_0F59 */
4823   {
4824     { "vmulps",         { XM, Vex, EXx }, 0 },
4825     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4826     { "vmulpd",         { XM, Vex, EXx }, 0 },
4827     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4828   },
4829
4830   /* PREFIX_VEX_0F5A */
4831   {
4832     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4833     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4834     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4835     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4836   },
4837
4838   /* PREFIX_VEX_0F5B */
4839   {
4840     { "vcvtdq2ps",      { XM, EXx }, 0 },
4841     { "vcvttps2dq",     { XM, EXx }, 0 },
4842     { "vcvtps2dq",      { XM, EXx }, 0 },
4843   },
4844
4845   /* PREFIX_VEX_0F5C */
4846   {
4847     { "vsubps",         { XM, Vex, EXx }, 0 },
4848     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4849     { "vsubpd",         { XM, Vex, EXx }, 0 },
4850     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4851   },
4852
4853   /* PREFIX_VEX_0F5D */
4854   {
4855     { "vminps",         { XM, Vex, EXx }, 0 },
4856     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4857     { "vminpd",         { XM, Vex, EXx }, 0 },
4858     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4859   },
4860
4861   /* PREFIX_VEX_0F5E */
4862   {
4863     { "vdivps",         { XM, Vex, EXx }, 0 },
4864     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4865     { "vdivpd",         { XM, Vex, EXx }, 0 },
4866     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4867   },
4868
4869   /* PREFIX_VEX_0F5F */
4870   {
4871     { "vmaxps",         { XM, Vex, EXx }, 0 },
4872     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4873     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4874     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4875   },
4876
4877   /* PREFIX_VEX_0F60 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4882   },
4883
4884   /* PREFIX_VEX_0F61 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4889   },
4890
4891   /* PREFIX_VEX_0F62 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4896   },
4897
4898   /* PREFIX_VEX_0F63 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4903   },
4904
4905   /* PREFIX_VEX_0F64 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4910   },
4911
4912   /* PREFIX_VEX_0F65 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4917   },
4918
4919   /* PREFIX_VEX_0F66 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4924   },
4925
4926   /* PREFIX_VEX_0F67 */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4931   },
4932
4933   /* PREFIX_VEX_0F68 */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4938   },
4939
4940   /* PREFIX_VEX_0F69 */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4945   },
4946
4947   /* PREFIX_VEX_0F6A */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4952   },
4953
4954   /* PREFIX_VEX_0F6B */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4959   },
4960
4961   /* PREFIX_VEX_0F6C */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4966   },
4967
4968   /* PREFIX_VEX_0F6D */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4973   },
4974
4975   /* PREFIX_VEX_0F6E */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_0F6F */
4983   {
4984     { Bad_Opcode },
4985     { "vmovdqu",        { XM, EXx }, 0 },
4986     { "vmovdqa",        { XM, EXx }, 0 },
4987   },
4988
4989   /* PREFIX_VEX_0F70 */
4990   {
4991     { Bad_Opcode },
4992     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4993     { "vpshufd",        { XM, EXx, Ib }, 0 },
4994     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4995   },
4996
4997   /* PREFIX_VEX_0F71_REG_2 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5002   },
5003
5004   /* PREFIX_VEX_0F71_REG_4 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { "vpsraw",         { Vex, XS, Ib }, 0 },
5009   },
5010
5011   /* PREFIX_VEX_0F71_REG_6 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { "vpsllw",         { Vex, XS, Ib }, 0 },
5016   },
5017
5018   /* PREFIX_VEX_0F72_REG_2 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { "vpsrld",         { Vex, XS, Ib }, 0 },
5023   },
5024
5025   /* PREFIX_VEX_0F72_REG_4 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { "vpsrad",         { Vex, XS, Ib }, 0 },
5030   },
5031
5032   /* PREFIX_VEX_0F72_REG_6 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { "vpslld",         { Vex, XS, Ib }, 0 },
5037   },
5038
5039   /* PREFIX_VEX_0F73_REG_2 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5044   },
5045
5046   /* PREFIX_VEX_0F73_REG_3 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5051   },
5052
5053   /* PREFIX_VEX_0F73_REG_6 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { "vpsllq",         { Vex, XS, Ib }, 0 },
5058   },
5059
5060   /* PREFIX_VEX_0F73_REG_7 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { "vpslldq",        { Vex, XS, Ib }, 0 },
5065   },
5066
5067   /* PREFIX_VEX_0F74 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5072   },
5073
5074   /* PREFIX_VEX_0F75 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5079   },
5080
5081   /* PREFIX_VEX_0F76 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5086   },
5087
5088   /* PREFIX_VEX_0F77 */
5089   {
5090     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5091   },
5092
5093   /* PREFIX_VEX_0F7C */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5098     { "vhaddps",        { XM, Vex, EXx }, 0 },
5099   },
5100
5101   /* PREFIX_VEX_0F7D */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5106     { "vhsubps",        { XM, Vex, EXx }, 0 },
5107   },
5108
5109   /* PREFIX_VEX_0F7E */
5110   {
5111     { Bad_Opcode },
5112     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5113     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5114   },
5115
5116   /* PREFIX_VEX_0F7F */
5117   {
5118     { Bad_Opcode },
5119     { "vmovdqu",        { EXxS, XM }, 0 },
5120     { "vmovdqa",        { EXxS, XM }, 0 },
5121   },
5122
5123   /* PREFIX_VEX_0F90 */
5124   {
5125     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5126     { Bad_Opcode },
5127     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_0F91 */
5131   {
5132     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0F92 */
5138   {
5139     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5140     { Bad_Opcode },
5141     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5142     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5143   },
5144
5145   /* PREFIX_VEX_0F93 */
5146   {
5147     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5148     { Bad_Opcode },
5149     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5150     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5151   },
5152
5153   /* PREFIX_VEX_0F98 */
5154   {
5155     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5156     { Bad_Opcode },
5157     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5158   },
5159
5160   /* PREFIX_VEX_0F99 */
5161   {
5162     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5163     { Bad_Opcode },
5164     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5165   },
5166
5167   /* PREFIX_VEX_0FC2 */
5168   {
5169     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5170     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5171     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5172     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5173   },
5174
5175   /* PREFIX_VEX_0FC4 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5180   },
5181
5182   /* PREFIX_VEX_0FC5 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5187   },
5188
5189   /* PREFIX_VEX_0FD0 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5194     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5195   },
5196
5197   /* PREFIX_VEX_0FD1 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5202   },
5203
5204   /* PREFIX_VEX_0FD2 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5209   },
5210
5211   /* PREFIX_VEX_0FD3 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5216   },
5217
5218   /* PREFIX_VEX_0FD4 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { "vpaddq",         { XM, Vex, EXx }, 0 },
5223   },
5224
5225   /* PREFIX_VEX_0FD5 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { "vpmullw",        { XM, Vex, EXx }, 0 },
5230   },
5231
5232   /* PREFIX_VEX_0FD6 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0FD7 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5244   },
5245
5246   /* PREFIX_VEX_0FD8 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5251   },
5252
5253   /* PREFIX_VEX_0FD9 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5258   },
5259
5260   /* PREFIX_VEX_0FDA */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { "vpminub",        { XM, Vex, EXx }, 0 },
5265   },
5266
5267   /* PREFIX_VEX_0FDB */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vpand",          { XM, Vex, EXx }, 0 },
5272   },
5273
5274   /* PREFIX_VEX_0FDC */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5279   },
5280
5281   /* PREFIX_VEX_0FDD */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5286   },
5287
5288   /* PREFIX_VEX_0FDE */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5293   },
5294
5295   /* PREFIX_VEX_0FDF */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { "vpandn",         { XM, Vex, EXx }, 0 },
5300   },
5301
5302   /* PREFIX_VEX_0FE0 */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { "vpavgb",         { XM, Vex, EXx }, 0 },
5307   },
5308
5309   /* PREFIX_VEX_0FE1 */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5314   },
5315
5316   /* PREFIX_VEX_0FE2 */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5321   },
5322
5323   /* PREFIX_VEX_0FE3 */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { "vpavgw",         { XM, Vex, EXx }, 0 },
5328   },
5329
5330   /* PREFIX_VEX_0FE4 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5335   },
5336
5337   /* PREFIX_VEX_0FE5 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5342   },
5343
5344   /* PREFIX_VEX_0FE6 */
5345   {
5346     { Bad_Opcode },
5347     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5348     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5349     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5350   },
5351
5352   /* PREFIX_VEX_0FE7 */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5357   },
5358
5359   /* PREFIX_VEX_0FE8 */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5364   },
5365
5366   /* PREFIX_VEX_0FE9 */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5371   },
5372
5373   /* PREFIX_VEX_0FEA */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { "vpminsw",        { XM, Vex, EXx }, 0 },
5378   },
5379
5380   /* PREFIX_VEX_0FEB */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { "vpor",           { XM, Vex, EXx }, 0 },
5385   },
5386
5387   /* PREFIX_VEX_0FEC */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5392   },
5393
5394   /* PREFIX_VEX_0FED */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5399   },
5400
5401   /* PREFIX_VEX_0FEE */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5406   },
5407
5408   /* PREFIX_VEX_0FEF */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { "vpxor",          { XM, Vex, EXx }, 0 },
5413   },
5414
5415   /* PREFIX_VEX_0FF0 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5421   },
5422
5423   /* PREFIX_VEX_0FF1 */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5428   },
5429
5430   /* PREFIX_VEX_0FF2 */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5435   },
5436
5437   /* PREFIX_VEX_0FF3 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5442   },
5443
5444   /* PREFIX_VEX_0FF4 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5449   },
5450
5451   /* PREFIX_VEX_0FF5 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5456   },
5457
5458   /* PREFIX_VEX_0FF6 */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5463   },
5464
5465   /* PREFIX_VEX_0FF7 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0FF8 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { "vpsubb",         { XM, Vex, EXx }, 0 },
5477   },
5478
5479   /* PREFIX_VEX_0FF9 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { "vpsubw",         { XM, Vex, EXx }, 0 },
5484   },
5485
5486   /* PREFIX_VEX_0FFA */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { "vpsubd",         { XM, Vex, EXx }, 0 },
5491   },
5492
5493   /* PREFIX_VEX_0FFB */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { "vpsubq",         { XM, Vex, EXx }, 0 },
5498   },
5499
5500   /* PREFIX_VEX_0FFC */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { "vpaddb",         { XM, Vex, EXx }, 0 },
5505   },
5506
5507   /* PREFIX_VEX_0FFD */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { "vpaddw",         { XM, Vex, EXx }, 0 },
5512   },
5513
5514   /* PREFIX_VEX_0FFE */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { "vpaddd",         { XM, Vex, EXx }, 0 },
5519   },
5520
5521   /* PREFIX_VEX_0F3800 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { "vpshufb",        { XM, Vex, EXx }, 0 },
5526   },
5527
5528   /* PREFIX_VEX_0F3801 */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { "vphaddw",        { XM, Vex, EXx }, 0 },
5533   },
5534
5535   /* PREFIX_VEX_0F3802 */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { "vphaddd",        { XM, Vex, EXx }, 0 },
5540   },
5541
5542   /* PREFIX_VEX_0F3803 */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5547   },
5548
5549   /* PREFIX_VEX_0F3804 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5554   },
5555
5556   /* PREFIX_VEX_0F3805 */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { "vphsubw",        { XM, Vex, EXx }, 0 },
5561   },
5562
5563   /* PREFIX_VEX_0F3806 */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { "vphsubd",        { XM, Vex, EXx }, 0 },
5568   },
5569
5570   /* PREFIX_VEX_0F3807 */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5575   },
5576
5577   /* PREFIX_VEX_0F3808 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { "vpsignb",        { XM, Vex, EXx }, 0 },
5582   },
5583
5584   /* PREFIX_VEX_0F3809 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { "vpsignw",        { XM, Vex, EXx }, 0 },
5589   },
5590
5591   /* PREFIX_VEX_0F380A */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { "vpsignd",        { XM, Vex, EXx }, 0 },
5596   },
5597
5598   /* PREFIX_VEX_0F380B */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5603   },
5604
5605   /* PREFIX_VEX_0F380C */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F380D */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F380E */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F380F */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F3813 */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5638   },
5639
5640   /* PREFIX_VEX_0F3816 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F3817 */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { "vptest",         { XM, EXx }, 0 },
5652   },
5653
5654   /* PREFIX_VEX_0F3818 */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5659   },
5660
5661   /* PREFIX_VEX_0F3819 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0F381A */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5673   },
5674
5675   /* PREFIX_VEX_0F381C */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { "vpabsb",         { XM, EXx }, 0 },
5680   },
5681
5682   /* PREFIX_VEX_0F381D */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { "vpabsw",         { XM, EXx }, 0 },
5687   },
5688
5689   /* PREFIX_VEX_0F381E */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { "vpabsd",         { XM, EXx }, 0 },
5694   },
5695
5696   /* PREFIX_VEX_0F3820 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5701   },
5702
5703   /* PREFIX_VEX_0F3821 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5708   },
5709
5710   /* PREFIX_VEX_0F3822 */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5715   },
5716
5717   /* PREFIX_VEX_0F3823 */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5722   },
5723
5724   /* PREFIX_VEX_0F3824 */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5729   },
5730
5731   /* PREFIX_VEX_0F3825 */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5736   },
5737
5738   /* PREFIX_VEX_0F3828 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5743   },
5744
5745   /* PREFIX_VEX_0F3829 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5750   },
5751
5752   /* PREFIX_VEX_0F382A */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F382B */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5764   },
5765
5766   /* PREFIX_VEX_0F382C */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F382D */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F382E */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F382F */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F3830 */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5799   },
5800
5801   /* PREFIX_VEX_0F3831 */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5806   },
5807
5808   /* PREFIX_VEX_0F3832 */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5813   },
5814
5815   /* PREFIX_VEX_0F3833 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5820   },
5821
5822   /* PREFIX_VEX_0F3834 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5827   },
5828
5829   /* PREFIX_VEX_0F3835 */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5834   },
5835
5836   /* PREFIX_VEX_0F3836 */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5841   },
5842
5843   /* PREFIX_VEX_0F3837 */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5848   },
5849
5850   /* PREFIX_VEX_0F3838 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { "vpminsb",        { XM, Vex, EXx }, 0 },
5855   },
5856
5857   /* PREFIX_VEX_0F3839 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { "vpminsd",        { XM, Vex, EXx }, 0 },
5862   },
5863
5864   /* PREFIX_VEX_0F383A */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { "vpminuw",        { XM, Vex, EXx }, 0 },
5869   },
5870
5871   /* PREFIX_VEX_0F383B */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { "vpminud",        { XM, Vex, EXx }, 0 },
5876   },
5877
5878   /* PREFIX_VEX_0F383C */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5883   },
5884
5885   /* PREFIX_VEX_0F383D */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5890   },
5891
5892   /* PREFIX_VEX_0F383E */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5897   },
5898
5899   /* PREFIX_VEX_0F383F */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5904   },
5905
5906   /* PREFIX_VEX_0F3840 */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { "vpmulld",        { XM, Vex, EXx }, 0 },
5911   },
5912
5913   /* PREFIX_VEX_0F3841 */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F3845 */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5925   },
5926
5927   /* PREFIX_VEX_0F3846 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F3847 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5939   },
5940
5941   /* PREFIX_VEX_0F3858 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5946   },
5947
5948   /* PREFIX_VEX_0F3859 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5953   },
5954
5955   /* PREFIX_VEX_0F385A */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5960   },
5961
5962   /* PREFIX_VEX_0F3878 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5967   },
5968
5969   /* PREFIX_VEX_0F3879 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5974   },
5975
5976   /* PREFIX_VEX_0F388C */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5981   },
5982
5983   /* PREFIX_VEX_0F388E */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5988   },
5989
5990   /* PREFIX_VEX_0F3890 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5995   },
5996
5997   /* PREFIX_VEX_0F3891 */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F3892 */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F3893 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F3896 */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F3897 */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F3898 */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F3899 */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F389A */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F389B */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F389C */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F389D */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F389E */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6079   },
6080
6081   /* PREFIX_VEX_0F389F */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F38A6 */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6093     { Bad_Opcode },
6094   },
6095
6096   /* PREFIX_VEX_0F38A7 */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6101   },
6102
6103   /* PREFIX_VEX_0F38A8 */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6108   },
6109
6110   /* PREFIX_VEX_0F38A9 */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6115   },
6116
6117   /* PREFIX_VEX_0F38AA */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F38AB */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38AC */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38AD */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38AE */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38AF */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38B6 */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38B7 */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38B8 */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6178   },
6179
6180   /* PREFIX_VEX_0F38B9 */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6185   },
6186
6187   /* PREFIX_VEX_0F38BA */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6192   },
6193
6194   /* PREFIX_VEX_0F38BB */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6199   },
6200
6201   /* PREFIX_VEX_0F38BC */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6206   },
6207
6208   /* PREFIX_VEX_0F38BD */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6213   },
6214
6215   /* PREFIX_VEX_0F38BE */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6220   },
6221
6222   /* PREFIX_VEX_0F38BF */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6227   },
6228
6229   /* PREFIX_VEX_0F38CF */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6234   },
6235
6236   /* PREFIX_VEX_0F38DB */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6241   },
6242
6243   /* PREFIX_VEX_0F38DC */
6244   {
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { "vaesenc",        { XM, Vex, EXx }, 0 },
6248   },
6249
6250   /* PREFIX_VEX_0F38DD */
6251   {
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6255   },
6256
6257   /* PREFIX_VEX_0F38DE */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { "vaesdec",        { XM, Vex, EXx }, 0 },
6262   },
6263
6264   /* PREFIX_VEX_0F38DF */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6269   },
6270
6271   /* PREFIX_VEX_0F38F2 */
6272   {
6273     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6274   },
6275
6276   /* PREFIX_VEX_0F38F3_REG_1 */
6277   {
6278     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6279   },
6280
6281   /* PREFIX_VEX_0F38F3_REG_2 */
6282   {
6283     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6284   },
6285
6286   /* PREFIX_VEX_0F38F3_REG_3 */
6287   {
6288     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6289   },
6290
6291   /* PREFIX_VEX_0F38F5 */
6292   {
6293     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6295     { Bad_Opcode },
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6297   },
6298
6299   /* PREFIX_VEX_0F38F6 */
6300   {
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6305   },
6306
6307   /* PREFIX_VEX_0F38F7 */
6308   {
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6310     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6313   },
6314
6315   /* PREFIX_VEX_0F3A00 */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6320   },
6321
6322   /* PREFIX_VEX_0F3A01 */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6327   },
6328
6329   /* PREFIX_VEX_0F3A02 */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A04 */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6341   },
6342
6343   /* PREFIX_VEX_0F3A05 */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6348   },
6349
6350   /* PREFIX_VEX_0F3A06 */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A08 */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { "vroundps",       { XM, EXx, Ib }, 0 },
6362   },
6363
6364   /* PREFIX_VEX_0F3A09 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { "vroundpd",       { XM, EXx, Ib }, 0 },
6369   },
6370
6371   /* PREFIX_VEX_0F3A0A */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6376   },
6377
6378   /* PREFIX_VEX_0F3A0B */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6383   },
6384
6385   /* PREFIX_VEX_0F3A0C */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6390   },
6391
6392   /* PREFIX_VEX_0F3A0D */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6397   },
6398
6399   /* PREFIX_VEX_0F3A0E */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6404   },
6405
6406   /* PREFIX_VEX_0F3A0F */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6411   },
6412
6413   /* PREFIX_VEX_0F3A14 */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A15 */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A16 */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A17 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A18 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A19 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A1D */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6460   },
6461
6462   /* PREFIX_VEX_0F3A20 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A21 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A22 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A30 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A31 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A32 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A33 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A38 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A39 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A40 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6530   },
6531
6532   /* PREFIX_VEX_0F3A41 */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A42 */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6544   },
6545
6546   /* PREFIX_VEX_0F3A44 */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6551   },
6552
6553   /* PREFIX_VEX_0F3A46 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A48 */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6565   },
6566
6567   /* PREFIX_VEX_0F3A49 */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A4A */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A4B */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6586   },
6587
6588   /* PREFIX_VEX_0F3A4C */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6593   },
6594
6595   /* PREFIX_VEX_0F3A5C */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6600   },
6601
6602   /* PREFIX_VEX_0F3A5D */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6607   },
6608
6609   /* PREFIX_VEX_0F3A5E */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6614   },
6615
6616   /* PREFIX_VEX_0F3A5F */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6621   },
6622
6623   /* PREFIX_VEX_0F3A60 */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6628     { Bad_Opcode },
6629   },
6630
6631   /* PREFIX_VEX_0F3A61 */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6636   },
6637
6638   /* PREFIX_VEX_0F3A62 */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6643   },
6644
6645   /* PREFIX_VEX_0F3A63 */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6650   },
6651
6652   /* PREFIX_VEX_0F3A68 */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6657   },
6658
6659   /* PREFIX_VEX_0F3A69 */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6664   },
6665
6666   /* PREFIX_VEX_0F3A6A */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6671   },
6672
6673   /* PREFIX_VEX_0F3A6B */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6678   },
6679
6680   /* PREFIX_VEX_0F3A6C */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6685   },
6686
6687   /* PREFIX_VEX_0F3A6D */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6692   },
6693
6694   /* PREFIX_VEX_0F3A6E */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6699   },
6700
6701   /* PREFIX_VEX_0F3A6F */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6706   },
6707
6708   /* PREFIX_VEX_0F3A78 */
6709   {
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6713   },
6714
6715   /* PREFIX_VEX_0F3A79 */
6716   {
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6720   },
6721
6722   /* PREFIX_VEX_0F3A7A */
6723   {
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6727   },
6728
6729   /* PREFIX_VEX_0F3A7B */
6730   {
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6734   },
6735
6736   /* PREFIX_VEX_0F3A7C */
6737   {
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6741     { Bad_Opcode },
6742   },
6743
6744   /* PREFIX_VEX_0F3A7D */
6745   {
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6749   },
6750
6751   /* PREFIX_VEX_0F3A7E */
6752   {
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6756   },
6757
6758   /* PREFIX_VEX_0F3A7F */
6759   {
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6763   },
6764
6765   /* PREFIX_VEX_0F3ACE */
6766   {
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6770   },
6771
6772   /* PREFIX_VEX_0F3ACF */
6773   {
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6777   },
6778
6779   /* PREFIX_VEX_0F3ADF */
6780   {
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6784   },
6785
6786   /* PREFIX_VEX_0F3AF0 */
6787   {
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6792   },
6793
6794 #include "i386-dis-evex-prefix.h"
6795 };
6796
6797 static const struct dis386 x86_64_table[][2] = {
6798   /* X86_64_06 */
6799   {
6800     { "pushP", { es }, 0 },
6801   },
6802
6803   /* X86_64_07 */
6804   {
6805     { "popP", { es }, 0 },
6806   },
6807
6808   /* X86_64_0D */
6809   {
6810     { "pushP", { cs }, 0 },
6811   },
6812
6813   /* X86_64_16 */
6814   {
6815     { "pushP", { ss }, 0 },
6816   },
6817
6818   /* X86_64_17 */
6819   {
6820     { "popP", { ss }, 0 },
6821   },
6822
6823   /* X86_64_1E */
6824   {
6825     { "pushP", { ds }, 0 },
6826   },
6827
6828   /* X86_64_1F */
6829   {
6830     { "popP", { ds }, 0 },
6831   },
6832
6833   /* X86_64_27 */
6834   {
6835     { "daa", { XX }, 0 },
6836   },
6837
6838   /* X86_64_2F */
6839   {
6840     { "das", { XX }, 0 },
6841   },
6842
6843   /* X86_64_37 */
6844   {
6845     { "aaa", { XX }, 0 },
6846   },
6847
6848   /* X86_64_3F */
6849   {
6850     { "aas", { XX }, 0 },
6851   },
6852
6853   /* X86_64_60 */
6854   {
6855     { "pushaP", { XX }, 0 },
6856   },
6857
6858   /* X86_64_61 */
6859   {
6860     { "popaP", { XX }, 0 },
6861   },
6862
6863   /* X86_64_62 */
6864   {
6865     { MOD_TABLE (MOD_62_32BIT) },
6866     { EVEX_TABLE (EVEX_0F) },
6867   },
6868
6869   /* X86_64_63 */
6870   {
6871     { "arpl", { Ew, Gw }, 0 },
6872     { "movs{lq|xd}", { Gv, Ed }, 0 },
6873   },
6874
6875   /* X86_64_6D */
6876   {
6877     { "ins{R|}", { Yzr, indirDX }, 0 },
6878     { "ins{G|}", { Yzr, indirDX }, 0 },
6879   },
6880
6881   /* X86_64_6F */
6882   {
6883     { "outs{R|}", { indirDXr, Xz }, 0 },
6884     { "outs{G|}", { indirDXr, Xz }, 0 },
6885   },
6886
6887   /* X86_64_82 */
6888   {
6889     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6890     { REG_TABLE (REG_80) },
6891   },
6892
6893   /* X86_64_9A */
6894   {
6895     { "Jcall{T|}", { Ap }, 0 },
6896   },
6897
6898   /* X86_64_C4 */
6899   {
6900     { MOD_TABLE (MOD_C4_32BIT) },
6901     { VEX_C4_TABLE (VEX_0F) },
6902   },
6903
6904   /* X86_64_C5 */
6905   {
6906     { MOD_TABLE (MOD_C5_32BIT) },
6907     { VEX_C5_TABLE (VEX_0F) },
6908   },
6909
6910   /* X86_64_CE */
6911   {
6912     { "into", { XX }, 0 },
6913   },
6914
6915   /* X86_64_D4 */
6916   {
6917     { "aam", { Ib }, 0 },
6918   },
6919
6920   /* X86_64_D5 */
6921   {
6922     { "aad", { Ib }, 0 },
6923   },
6924
6925   /* X86_64_E8 */
6926   {
6927     { "callP",          { Jv, BND }, 0 },
6928     { "call@",          { Jv, BND }, 0 }
6929   },
6930
6931   /* X86_64_E9 */
6932   {
6933     { "jmpP",           { Jv, BND }, 0 },
6934     { "jmp@",           { Jv, BND }, 0 }
6935   },
6936
6937   /* X86_64_EA */
6938   {
6939     { "Jjmp{T|}", { Ap }, 0 },
6940   },
6941
6942   /* X86_64_0F01_REG_0 */
6943   {
6944     { "sgdt{Q|IQ}", { M }, 0 },
6945     { "sgdt", { M }, 0 },
6946   },
6947
6948   /* X86_64_0F01_REG_1 */
6949   {
6950     { "sidt{Q|IQ}", { M }, 0 },
6951     { "sidt", { M }, 0 },
6952   },
6953
6954   /* X86_64_0F01_REG_2 */
6955   {
6956     { "lgdt{Q|Q}", { M }, 0 },
6957     { "lgdt", { M }, 0 },
6958   },
6959
6960   /* X86_64_0F01_REG_3 */
6961   {
6962     { "lidt{Q|Q}", { M }, 0 },
6963     { "lidt", { M }, 0 },
6964   },
6965 };
6966
6967 static const struct dis386 three_byte_table[][256] = {
6968
6969   /* THREE_BYTE_0F38 */
6970   {
6971     /* 00 */
6972     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6973     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6974     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6975     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6976     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6977     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6978     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6979     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6980     /* 08 */
6981     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6982     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6983     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6984     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     /* 10 */
6990     { PREFIX_TABLE (PREFIX_0F3810) },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { PREFIX_TABLE (PREFIX_0F3814) },
6995     { PREFIX_TABLE (PREFIX_0F3815) },
6996     { Bad_Opcode },
6997     { PREFIX_TABLE (PREFIX_0F3817) },
6998     /* 18 */
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7004     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7005     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7006     { Bad_Opcode },
7007     /* 20 */
7008     { PREFIX_TABLE (PREFIX_0F3820) },
7009     { PREFIX_TABLE (PREFIX_0F3821) },
7010     { PREFIX_TABLE (PREFIX_0F3822) },
7011     { PREFIX_TABLE (PREFIX_0F3823) },
7012     { PREFIX_TABLE (PREFIX_0F3824) },
7013     { PREFIX_TABLE (PREFIX_0F3825) },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     /* 28 */
7017     { PREFIX_TABLE (PREFIX_0F3828) },
7018     { PREFIX_TABLE (PREFIX_0F3829) },
7019     { PREFIX_TABLE (PREFIX_0F382A) },
7020     { PREFIX_TABLE (PREFIX_0F382B) },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     /* 30 */
7026     { PREFIX_TABLE (PREFIX_0F3830) },
7027     { PREFIX_TABLE (PREFIX_0F3831) },
7028     { PREFIX_TABLE (PREFIX_0F3832) },
7029     { PREFIX_TABLE (PREFIX_0F3833) },
7030     { PREFIX_TABLE (PREFIX_0F3834) },
7031     { PREFIX_TABLE (PREFIX_0F3835) },
7032     { Bad_Opcode },
7033     { PREFIX_TABLE (PREFIX_0F3837) },
7034     /* 38 */
7035     { PREFIX_TABLE (PREFIX_0F3838) },
7036     { PREFIX_TABLE (PREFIX_0F3839) },
7037     { PREFIX_TABLE (PREFIX_0F383A) },
7038     { PREFIX_TABLE (PREFIX_0F383B) },
7039     { PREFIX_TABLE (PREFIX_0F383C) },
7040     { PREFIX_TABLE (PREFIX_0F383D) },
7041     { PREFIX_TABLE (PREFIX_0F383E) },
7042     { PREFIX_TABLE (PREFIX_0F383F) },
7043     /* 40 */
7044     { PREFIX_TABLE (PREFIX_0F3840) },
7045     { PREFIX_TABLE (PREFIX_0F3841) },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* 48 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* 50 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* 58 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* 60 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* 68 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* 70 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* 78 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* 80 */
7116     { PREFIX_TABLE (PREFIX_0F3880) },
7117     { PREFIX_TABLE (PREFIX_0F3881) },
7118     { PREFIX_TABLE (PREFIX_0F3882) },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* 88 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* 90 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     /* 98 */
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     /* a0 */
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     /* a8 */
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     /* b0 */
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     /* b8 */
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     /* c0 */
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     /* c8 */
7197     { PREFIX_TABLE (PREFIX_0F38C8) },
7198     { PREFIX_TABLE (PREFIX_0F38C9) },
7199     { PREFIX_TABLE (PREFIX_0F38CA) },
7200     { PREFIX_TABLE (PREFIX_0F38CB) },
7201     { PREFIX_TABLE (PREFIX_0F38CC) },
7202     { PREFIX_TABLE (PREFIX_0F38CD) },
7203     { Bad_Opcode },
7204     { PREFIX_TABLE (PREFIX_0F38CF) },
7205     /* d0 */
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     /* d8 */
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { PREFIX_TABLE (PREFIX_0F38DB) },
7219     { PREFIX_TABLE (PREFIX_0F38DC) },
7220     { PREFIX_TABLE (PREFIX_0F38DD) },
7221     { PREFIX_TABLE (PREFIX_0F38DE) },
7222     { PREFIX_TABLE (PREFIX_0F38DF) },
7223     /* e0 */
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     /* e8 */
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* f0 */
7242     { PREFIX_TABLE (PREFIX_0F38F0) },
7243     { PREFIX_TABLE (PREFIX_0F38F1) },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { PREFIX_TABLE (PREFIX_0F38F5) },
7248     { PREFIX_TABLE (PREFIX_0F38F6) },
7249     { Bad_Opcode },
7250     /* f8 */
7251     { PREFIX_TABLE (PREFIX_0F38F8) },
7252     { PREFIX_TABLE (PREFIX_0F38F9) },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259   },
7260   /* THREE_BYTE_0F3A */
7261   {
7262     /* 00 */
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     /* 08 */
7272     { PREFIX_TABLE (PREFIX_0F3A08) },
7273     { PREFIX_TABLE (PREFIX_0F3A09) },
7274     { PREFIX_TABLE (PREFIX_0F3A0A) },
7275     { PREFIX_TABLE (PREFIX_0F3A0B) },
7276     { PREFIX_TABLE (PREFIX_0F3A0C) },
7277     { PREFIX_TABLE (PREFIX_0F3A0D) },
7278     { PREFIX_TABLE (PREFIX_0F3A0E) },
7279     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7280     /* 10 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { PREFIX_TABLE (PREFIX_0F3A14) },
7286     { PREFIX_TABLE (PREFIX_0F3A15) },
7287     { PREFIX_TABLE (PREFIX_0F3A16) },
7288     { PREFIX_TABLE (PREFIX_0F3A17) },
7289     /* 18 */
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 20 */
7299     { PREFIX_TABLE (PREFIX_0F3A20) },
7300     { PREFIX_TABLE (PREFIX_0F3A21) },
7301     { PREFIX_TABLE (PREFIX_0F3A22) },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* 28 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* 30 */
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     /* 38 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* 40 */
7335     { PREFIX_TABLE (PREFIX_0F3A40) },
7336     { PREFIX_TABLE (PREFIX_0F3A41) },
7337     { PREFIX_TABLE (PREFIX_0F3A42) },
7338     { Bad_Opcode },
7339     { PREFIX_TABLE (PREFIX_0F3A44) },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* 48 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* 50 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* 58 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* 60 */
7371     { PREFIX_TABLE (PREFIX_0F3A60) },
7372     { PREFIX_TABLE (PREFIX_0F3A61) },
7373     { PREFIX_TABLE (PREFIX_0F3A62) },
7374     { PREFIX_TABLE (PREFIX_0F3A63) },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* 68 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* 70 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* 78 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* 80 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* 88 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* 90 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* 98 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* a0 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* a8 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* b0 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* b8 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* c0 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* c8 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { PREFIX_TABLE (PREFIX_0F3ACC) },
7493     { Bad_Opcode },
7494     { PREFIX_TABLE (PREFIX_0F3ACE) },
7495     { PREFIX_TABLE (PREFIX_0F3ACF) },
7496     /* d0 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* d8 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { PREFIX_TABLE (PREFIX_0F3ADF) },
7514     /* e0 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* e8 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* f0 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* f8 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550   },
7551 };
7552
7553 static const struct dis386 xop_table[][256] = {
7554   /* XOP_08 */
7555   {
7556     /* 00 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* 08 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* 10 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 18 */
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* 20 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* 28 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* 30 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* 38 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* 40 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* 48 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* 50 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     /* 58 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     /* 60 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     /* 68 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     /* 70 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* 78 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* 80 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7707     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7708     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709     /* 88 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7717     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7718     /* 90 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7725     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7726     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7727     /* 98 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7735     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7736     /* a0 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7744     { Bad_Opcode },
7745     /* a8 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* b0 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7762     { Bad_Opcode },
7763     /* b8 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     /* c0 */
7773     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7774     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7775     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7776     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     /* c8 */
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7787     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7790     /* d0 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     /* d8 */
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     /* e0 */
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     /* e8 */
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7823     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7824     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7825     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7826     /* f0 */
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     /* f8 */
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844   },
7845   /* XOP_09 */
7846   {
7847     /* 00 */
7848     { Bad_Opcode },
7849     { REG_TABLE (REG_XOP_TBM_01) },
7850     { REG_TABLE (REG_XOP_TBM_02) },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     /* 08 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     /* 10 */
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { REG_TABLE (REG_XOP_LWPCB) },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     /* 18 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     /* 20 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     /* 28 */
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     /* 30 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     /* 38 */
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     /* 40 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     /* 48 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     /* 50 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* 58 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* 60 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* 68 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* 70 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* 78 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* 80 */
7992     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7993     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7994     { "vfrczss",        { XM, EXd }, 0 },
7995     { "vfrczsd",        { XM, EXq }, 0 },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* 88 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     /* 90 */
8010     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8011     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8012     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     /* 98 */
8019     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     /* a0 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     /* a8 */
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     /* b0 */
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     /* b8 */
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     /* c0 */
8064     { Bad_Opcode },
8065     { "vphaddbw",       { XM, EXxmm }, 0 },
8066     { "vphaddbd",       { XM, EXxmm }, 0 },
8067     { "vphaddbq",       { XM, EXxmm }, 0 },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { "vphaddwd",       { XM, EXxmm }, 0 },
8071     { "vphaddwq",       { XM, EXxmm }, 0 },
8072     /* c8 */
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { "vphadddq",       { XM, EXxmm }, 0 },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     /* d0 */
8082     { Bad_Opcode },
8083     { "vphaddubw",      { XM, EXxmm }, 0 },
8084     { "vphaddubd",      { XM, EXxmm }, 0 },
8085     { "vphaddubq",      { XM, EXxmm }, 0 },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { "vphadduwd",      { XM, EXxmm }, 0 },
8089     { "vphadduwq",      { XM, EXxmm }, 0 },
8090     /* d8 */
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { "vphaddudq",      { XM, EXxmm }, 0 },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     /* e0 */
8100     { Bad_Opcode },
8101     { "vphsubbw",       { XM, EXxmm }, 0 },
8102     { "vphsubwd",       { XM, EXxmm }, 0 },
8103     { "vphsubdq",       { XM, EXxmm }, 0 },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     /* e8 */
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     /* f0 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* f8 */
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135   },
8136   /* XOP_0A */
8137   {
8138     /* 00 */
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     /* 08 */
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     /* 10 */
8157     { "bextrS", { Gdq, Edq, Id }, 0 },
8158     { Bad_Opcode },
8159     { REG_TABLE (REG_XOP_LWP) },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     /* 18 */
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     /* 20 */
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     /* 28 */
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     /* 30 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* 38 */
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     /* 40 */
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* 48 */
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* 50 */
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     /* 58 */
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* 60 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     /* 68 */
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     /* 70 */
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     /* 78 */
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     /* 80 */
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     /* 88 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* 90 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* 98 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* a0 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* a8 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* b0 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* b8 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* c0 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* c8 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* d0 */
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* d8 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* e0 */
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     /* e8 */
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     /* f0 */
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     /* f8 */
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426   },
8427 };
8428
8429 static const struct dis386 vex_table[][256] = {
8430   /* VEX_0F */
8431   {
8432     /* 00 */
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     /* 08 */
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     /* 10 */
8451     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8454     { MOD_TABLE (MOD_VEX_0F13) },
8455     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8456     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8457     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8458     { MOD_TABLE (MOD_VEX_0F17) },
8459     /* 18 */
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     /* 20 */
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     /* 28 */
8478     { "vmovapX",        { XM, EXx }, 0 },
8479     { "vmovapX",        { EXxS, XM }, 0 },
8480     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8481     { MOD_TABLE (MOD_VEX_0F2B) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8486     /* 30 */
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     /* 38 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* 40 */
8505     { Bad_Opcode },
8506     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8508     { Bad_Opcode },
8509     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8510     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8513     /* 48 */
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     /* 50 */
8523     { MOD_TABLE (MOD_VEX_0F50) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8527     { "vandpX",         { XM, Vex, EXx }, 0 },
8528     { "vandnpX",        { XM, Vex, EXx }, 0 },
8529     { "vorpX",          { XM, Vex, EXx }, 0 },
8530     { "vxorpX",         { XM, Vex, EXx }, 0 },
8531     /* 58 */
8532     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8540     /* 60 */
8541     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8549     /* 68 */
8550     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8558     /* 70 */
8559     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8560     { REG_TABLE (REG_VEX_0F71) },
8561     { REG_TABLE (REG_VEX_0F72) },
8562     { REG_TABLE (REG_VEX_0F73) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8567     /* 78 */
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8576     /* 80 */
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     /* 88 */
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     /* 90 */
8595     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     /* 98 */
8604     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     /* a0 */
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     /* a8 */
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { REG_TABLE (REG_VEX_0FAE) },
8629     { Bad_Opcode },
8630     /* b0 */
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     /* b8 */
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     /* c0 */
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8652     { Bad_Opcode },
8653     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8654     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8655     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8656     { Bad_Opcode },
8657     /* c8 */
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     /* d0 */
8667     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8675     /* d8 */
8676     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8684     /* e0 */
8685     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8693     /* e8 */
8694     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8702     /* f0 */
8703     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8711     /* f8 */
8712     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8719     { Bad_Opcode },
8720   },
8721   /* VEX_0F38 */
8722   {
8723     /* 00 */
8724     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8732     /* 08 */
8733     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8741     /* 10 */
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8750     /* 18 */
8751     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8754     { Bad_Opcode },
8755     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8758     { Bad_Opcode },
8759     /* 20 */
8760     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     /* 28 */
8769     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8777     /* 30 */
8778     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8786     /* 38 */
8787     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8795     /* 40 */
8796     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8804     /* 48 */
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     /* 50 */
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     /* 58 */
8823     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     /* 60 */
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     /* 68 */
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     /* 70 */
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     /* 78 */
8859     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     /* 80 */
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     /* 88 */
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8882     { Bad_Opcode },
8883     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8884     { Bad_Opcode },
8885     /* 90 */
8886     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8894     /* 98 */
8895     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8903     /* a0 */
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8912     /* a8 */
8913     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8921     /* b0 */
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8930     /* b8 */
8931     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8939     /* c0 */
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     /* c8 */
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8957     /* d0 */
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     /* d8 */
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8975     /* e0 */
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     /* e8 */
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     /* f0 */
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8997     { REG_TABLE (REG_VEX_0F38F3) },
8998     { Bad_Opcode },
8999     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9002     /* f8 */
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011   },
9012   /* VEX_0F3A */
9013   {
9014     /* 00 */
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9018     { Bad_Opcode },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9022     { Bad_Opcode },
9023     /* 08 */
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9032     /* 10 */
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9041     /* 18 */
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     /* 20 */
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     /* 28 */
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     /* 30 */
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     /* 38 */
9078     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     /* 40 */
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9090     { Bad_Opcode },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9092     { Bad_Opcode },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9094     { Bad_Opcode },
9095     /* 48 */
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     /* 50 */
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     /* 58 */
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9122     /* 60 */
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     /* 68 */
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9140     /* 70 */
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     /* 78 */
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9158     /* 80 */
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     /* 88 */
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     /* 90 */
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     /* 98 */
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     /* a0 */
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     /* a8 */
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     /* b0 */
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     /* b8 */
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     /* c0 */
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     /* c8 */
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9247     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9248     /* d0 */
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     /* d8 */
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9266     /* e0 */
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     /* e8 */
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     /* f0 */
9285     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     /* f8 */
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302   },
9303 };
9304
9305 #include "i386-dis-evex.h"
9306
9307 static const struct dis386 vex_len_table[][2] = {
9308   /* VEX_LEN_0F12_P_0_M_0 */
9309   {
9310     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9311   },
9312
9313   /* VEX_LEN_0F12_P_0_M_1 */
9314   {
9315     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9316   },
9317
9318   /* VEX_LEN_0F12_P_2 */
9319   {
9320     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9321   },
9322
9323   /* VEX_LEN_0F13_M_0 */
9324   {
9325     { "vmovlpX",        { EXq, XM }, 0 },
9326   },
9327
9328   /* VEX_LEN_0F16_P_0_M_0 */
9329   {
9330     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9331   },
9332
9333   /* VEX_LEN_0F16_P_0_M_1 */
9334   {
9335     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9336   },
9337
9338   /* VEX_LEN_0F16_P_2 */
9339   {
9340     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9341   },
9342
9343   /* VEX_LEN_0F17_M_0 */
9344   {
9345     { "vmovhpX",        { EXq, XM }, 0 },
9346   },
9347
9348   /* VEX_LEN_0F41_P_0 */
9349   {
9350     { Bad_Opcode },
9351     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9352   },
9353   /* VEX_LEN_0F41_P_2 */
9354   {
9355     { Bad_Opcode },
9356     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9357   },
9358   /* VEX_LEN_0F42_P_0 */
9359   {
9360     { Bad_Opcode },
9361     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9362   },
9363   /* VEX_LEN_0F42_P_2 */
9364   {
9365     { Bad_Opcode },
9366     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9367   },
9368   /* VEX_LEN_0F44_P_0 */
9369   {
9370     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9371   },
9372   /* VEX_LEN_0F44_P_2 */
9373   {
9374     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9375   },
9376   /* VEX_LEN_0F45_P_0 */
9377   {
9378     { Bad_Opcode },
9379     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9380   },
9381   /* VEX_LEN_0F45_P_2 */
9382   {
9383     { Bad_Opcode },
9384     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9385   },
9386   /* VEX_LEN_0F46_P_0 */
9387   {
9388     { Bad_Opcode },
9389     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9390   },
9391   /* VEX_LEN_0F46_P_2 */
9392   {
9393     { Bad_Opcode },
9394     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9395   },
9396   /* VEX_LEN_0F47_P_0 */
9397   {
9398     { Bad_Opcode },
9399     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9400   },
9401   /* VEX_LEN_0F47_P_2 */
9402   {
9403     { Bad_Opcode },
9404     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9405   },
9406   /* VEX_LEN_0F4A_P_0 */
9407   {
9408     { Bad_Opcode },
9409     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9410   },
9411   /* VEX_LEN_0F4A_P_2 */
9412   {
9413     { Bad_Opcode },
9414     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9415   },
9416   /* VEX_LEN_0F4B_P_0 */
9417   {
9418     { Bad_Opcode },
9419     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9420   },
9421   /* VEX_LEN_0F4B_P_2 */
9422   {
9423     { Bad_Opcode },
9424     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9425   },
9426
9427   /* VEX_LEN_0F6E_P_2 */
9428   {
9429     { "vmovK",          { XMScalar, Edq }, 0 },
9430   },
9431
9432   /* VEX_LEN_0F77_P_1 */
9433   {
9434     { "vzeroupper",     { XX }, 0 },
9435     { "vzeroall",       { XX }, 0 },
9436   },
9437
9438   /* VEX_LEN_0F7E_P_1 */
9439   {
9440     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9441   },
9442
9443   /* VEX_LEN_0F7E_P_2 */
9444   {
9445     { "vmovK",          { Edq, XMScalar }, 0 },
9446   },
9447
9448   /* VEX_LEN_0F90_P_0 */
9449   {
9450     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9451   },
9452
9453   /* VEX_LEN_0F90_P_2 */
9454   {
9455     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9456   },
9457
9458   /* VEX_LEN_0F91_P_0 */
9459   {
9460     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9461   },
9462
9463   /* VEX_LEN_0F91_P_2 */
9464   {
9465     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9466   },
9467
9468   /* VEX_LEN_0F92_P_0 */
9469   {
9470     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9471   },
9472
9473   /* VEX_LEN_0F92_P_2 */
9474   {
9475     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9476   },
9477
9478   /* VEX_LEN_0F92_P_3 */
9479   {
9480     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9481   },
9482
9483   /* VEX_LEN_0F93_P_0 */
9484   {
9485     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9486   },
9487
9488   /* VEX_LEN_0F93_P_2 */
9489   {
9490     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9491   },
9492
9493   /* VEX_LEN_0F93_P_3 */
9494   {
9495     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9496   },
9497
9498   /* VEX_LEN_0F98_P_0 */
9499   {
9500     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9501   },
9502
9503   /* VEX_LEN_0F98_P_2 */
9504   {
9505     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9506   },
9507
9508   /* VEX_LEN_0F99_P_0 */
9509   {
9510     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9511   },
9512
9513   /* VEX_LEN_0F99_P_2 */
9514   {
9515     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9516   },
9517
9518   /* VEX_LEN_0FAE_R_2_M_0 */
9519   {
9520     { "vldmxcsr",       { Md }, 0 },
9521   },
9522
9523   /* VEX_LEN_0FAE_R_3_M_0 */
9524   {
9525     { "vstmxcsr",       { Md }, 0 },
9526   },
9527
9528   /* VEX_LEN_0FC4_P_2 */
9529   {
9530     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9531   },
9532
9533   /* VEX_LEN_0FC5_P_2 */
9534   {
9535     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9536   },
9537
9538   /* VEX_LEN_0FD6_P_2 */
9539   {
9540     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9541   },
9542
9543   /* VEX_LEN_0FF7_P_2 */
9544   {
9545     { "vmaskmovdqu",    { XM, XS }, 0 },
9546   },
9547
9548   /* VEX_LEN_0F3816_P_2 */
9549   {
9550     { Bad_Opcode },
9551     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9552   },
9553
9554   /* VEX_LEN_0F3819_P_2 */
9555   {
9556     { Bad_Opcode },
9557     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9558   },
9559
9560   /* VEX_LEN_0F381A_P_2_M_0 */
9561   {
9562     { Bad_Opcode },
9563     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9564   },
9565
9566   /* VEX_LEN_0F3836_P_2 */
9567   {
9568     { Bad_Opcode },
9569     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9570   },
9571
9572   /* VEX_LEN_0F3841_P_2 */
9573   {
9574     { "vphminposuw",    { XM, EXx }, 0 },
9575   },
9576
9577   /* VEX_LEN_0F385A_P_2_M_0 */
9578   {
9579     { Bad_Opcode },
9580     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9581   },
9582
9583   /* VEX_LEN_0F38DB_P_2 */
9584   {
9585     { "vaesimc",        { XM, EXx }, 0 },
9586   },
9587
9588   /* VEX_LEN_0F38F2_P_0 */
9589   {
9590     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9591   },
9592
9593   /* VEX_LEN_0F38F3_R_1_P_0 */
9594   {
9595     { "blsrS",          { VexGdq, Edq }, 0 },
9596   },
9597
9598   /* VEX_LEN_0F38F3_R_2_P_0 */
9599   {
9600     { "blsmskS",        { VexGdq, Edq }, 0 },
9601   },
9602
9603   /* VEX_LEN_0F38F3_R_3_P_0 */
9604   {
9605     { "blsiS",          { VexGdq, Edq }, 0 },
9606   },
9607
9608   /* VEX_LEN_0F38F5_P_0 */
9609   {
9610     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9611   },
9612
9613   /* VEX_LEN_0F38F5_P_1 */
9614   {
9615     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F38F5_P_3 */
9619   {
9620     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9621   },
9622
9623   /* VEX_LEN_0F38F6_P_3 */
9624   {
9625     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9626   },
9627
9628   /* VEX_LEN_0F38F7_P_0 */
9629   {
9630     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9631   },
9632
9633   /* VEX_LEN_0F38F7_P_1 */
9634   {
9635     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9636   },
9637
9638   /* VEX_LEN_0F38F7_P_2 */
9639   {
9640     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9641   },
9642
9643   /* VEX_LEN_0F38F7_P_3 */
9644   {
9645     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9646   },
9647
9648   /* VEX_LEN_0F3A00_P_2 */
9649   {
9650     { Bad_Opcode },
9651     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9652   },
9653
9654   /* VEX_LEN_0F3A01_P_2 */
9655   {
9656     { Bad_Opcode },
9657     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9658   },
9659
9660   /* VEX_LEN_0F3A06_P_2 */
9661   {
9662     { Bad_Opcode },
9663     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9664   },
9665
9666   /* VEX_LEN_0F3A14_P_2 */
9667   {
9668     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9669   },
9670
9671   /* VEX_LEN_0F3A15_P_2 */
9672   {
9673     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9674   },
9675
9676   /* VEX_LEN_0F3A16_P_2  */
9677   {
9678     { "vpextrK",        { Edq, XM, Ib }, 0 },
9679   },
9680
9681   /* VEX_LEN_0F3A17_P_2 */
9682   {
9683     { "vextractps",     { Edqd, XM, Ib }, 0 },
9684   },
9685
9686   /* VEX_LEN_0F3A18_P_2 */
9687   {
9688     { Bad_Opcode },
9689     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9690   },
9691
9692   /* VEX_LEN_0F3A19_P_2 */
9693   {
9694     { Bad_Opcode },
9695     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9696   },
9697
9698   /* VEX_LEN_0F3A20_P_2 */
9699   {
9700     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9701   },
9702
9703   /* VEX_LEN_0F3A21_P_2 */
9704   {
9705     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9706   },
9707
9708   /* VEX_LEN_0F3A22_P_2 */
9709   {
9710     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9711   },
9712
9713   /* VEX_LEN_0F3A30_P_2 */
9714   {
9715     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9716   },
9717
9718   /* VEX_LEN_0F3A31_P_2 */
9719   {
9720     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9721   },
9722
9723   /* VEX_LEN_0F3A32_P_2 */
9724   {
9725     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9726   },
9727
9728   /* VEX_LEN_0F3A33_P_2 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9731   },
9732
9733   /* VEX_LEN_0F3A38_P_2 */
9734   {
9735     { Bad_Opcode },
9736     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9737   },
9738
9739   /* VEX_LEN_0F3A39_P_2 */
9740   {
9741     { Bad_Opcode },
9742     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9743   },
9744
9745   /* VEX_LEN_0F3A41_P_2 */
9746   {
9747     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9748   },
9749
9750   /* VEX_LEN_0F3A46_P_2 */
9751   {
9752     { Bad_Opcode },
9753     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9754   },
9755
9756   /* VEX_LEN_0F3A60_P_2 */
9757   {
9758     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9759   },
9760
9761   /* VEX_LEN_0F3A61_P_2 */
9762   {
9763     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9764   },
9765
9766   /* VEX_LEN_0F3A62_P_2 */
9767   {
9768     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9769   },
9770
9771   /* VEX_LEN_0F3A63_P_2 */
9772   {
9773     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9774   },
9775
9776   /* VEX_LEN_0F3A6A_P_2 */
9777   {
9778     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9779   },
9780
9781   /* VEX_LEN_0F3A6B_P_2 */
9782   {
9783     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9784   },
9785
9786   /* VEX_LEN_0F3A6E_P_2 */
9787   {
9788     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9789   },
9790
9791   /* VEX_LEN_0F3A6F_P_2 */
9792   {
9793     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9794   },
9795
9796   /* VEX_LEN_0F3A7A_P_2 */
9797   {
9798     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9799   },
9800
9801   /* VEX_LEN_0F3A7B_P_2 */
9802   {
9803     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9804   },
9805
9806   /* VEX_LEN_0F3A7E_P_2 */
9807   {
9808     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9809   },
9810
9811   /* VEX_LEN_0F3A7F_P_2 */
9812   {
9813     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9814   },
9815
9816   /* VEX_LEN_0F3ADF_P_2 */
9817   {
9818     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9819   },
9820
9821   /* VEX_LEN_0F3AF0_P_3 */
9822   {
9823     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9824   },
9825
9826   /* VEX_LEN_0FXOP_08_CC */
9827   {
9828      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9829   },
9830
9831   /* VEX_LEN_0FXOP_08_CD */
9832   {
9833      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9834   },
9835
9836   /* VEX_LEN_0FXOP_08_CE */
9837   {
9838      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9839   },
9840
9841   /* VEX_LEN_0FXOP_08_CF */
9842   {
9843      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9844   },
9845
9846   /* VEX_LEN_0FXOP_08_EC */
9847   {
9848      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9849   },
9850
9851   /* VEX_LEN_0FXOP_08_ED */
9852   {
9853      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9854   },
9855
9856   /* VEX_LEN_0FXOP_08_EE */
9857   {
9858      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9859   },
9860
9861   /* VEX_LEN_0FXOP_08_EF */
9862   {
9863      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9864   },
9865
9866   /* VEX_LEN_0FXOP_09_80 */
9867   {
9868     { "vfrczps",        { XM, EXxmm }, 0 },
9869     { "vfrczps",        { XM, EXymmq }, 0 },
9870   },
9871
9872   /* VEX_LEN_0FXOP_09_81 */
9873   {
9874     { "vfrczpd",        { XM, EXxmm }, 0 },
9875     { "vfrczpd",        { XM, EXymmq }, 0 },
9876   },
9877 };
9878
9879 #include "i386-dis-evex-len.h"
9880
9881 static const struct dis386 vex_w_table[][2] = {
9882   {
9883     /* VEX_W_0F41_P_0_LEN_1 */
9884     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9885     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9886   },
9887   {
9888     /* VEX_W_0F41_P_2_LEN_1 */
9889     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9890     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9891   },
9892   {
9893     /* VEX_W_0F42_P_0_LEN_1 */
9894     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9895     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9896   },
9897   {
9898     /* VEX_W_0F42_P_2_LEN_1 */
9899     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9900     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9901   },
9902   {
9903     /* VEX_W_0F44_P_0_LEN_0 */
9904     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9905     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9906   },
9907   {
9908     /* VEX_W_0F44_P_2_LEN_0 */
9909     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9910     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9911   },
9912   {
9913     /* VEX_W_0F45_P_0_LEN_1 */
9914     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9915     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9916   },
9917   {
9918     /* VEX_W_0F45_P_2_LEN_1 */
9919     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9920     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9921   },
9922   {
9923     /* VEX_W_0F46_P_0_LEN_1 */
9924     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9925     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9926   },
9927   {
9928     /* VEX_W_0F46_P_2_LEN_1 */
9929     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9930     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9931   },
9932   {
9933     /* VEX_W_0F47_P_0_LEN_1 */
9934     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9935     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9936   },
9937   {
9938     /* VEX_W_0F47_P_2_LEN_1 */
9939     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9940     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9941   },
9942   {
9943     /* VEX_W_0F4A_P_0_LEN_1 */
9944     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9945     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9946   },
9947   {
9948     /* VEX_W_0F4A_P_2_LEN_1 */
9949     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9950     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9951   },
9952   {
9953     /* VEX_W_0F4B_P_0_LEN_1 */
9954     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9955     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9956   },
9957   {
9958     /* VEX_W_0F4B_P_2_LEN_1 */
9959     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9960   },
9961   {
9962     /* VEX_W_0F90_P_0_LEN_0 */
9963     { "kmovw",          { MaskG, MaskE }, 0 },
9964     { "kmovq",          { MaskG, MaskE }, 0 },
9965   },
9966   {
9967     /* VEX_W_0F90_P_2_LEN_0 */
9968     { "kmovb",          { MaskG, MaskBDE }, 0 },
9969     { "kmovd",          { MaskG, MaskBDE }, 0 },
9970   },
9971   {
9972     /* VEX_W_0F91_P_0_LEN_0 */
9973     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9974     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9975   },
9976   {
9977     /* VEX_W_0F91_P_2_LEN_0 */
9978     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9979     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9980   },
9981   {
9982     /* VEX_W_0F92_P_0_LEN_0 */
9983     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9984   },
9985   {
9986     /* VEX_W_0F92_P_2_LEN_0 */
9987     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9988   },
9989   {
9990     /* VEX_W_0F93_P_0_LEN_0 */
9991     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9992   },
9993   {
9994     /* VEX_W_0F93_P_2_LEN_0 */
9995     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9996   },
9997   {
9998     /* VEX_W_0F98_P_0_LEN_0 */
9999     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10000     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10001   },
10002   {
10003     /* VEX_W_0F98_P_2_LEN_0 */
10004     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10005     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10006   },
10007   {
10008     /* VEX_W_0F99_P_0_LEN_0 */
10009     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10010     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10011   },
10012   {
10013     /* VEX_W_0F99_P_2_LEN_0 */
10014     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10015     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10016   },
10017   {
10018     /* VEX_W_0F380C_P_2  */
10019     { "vpermilps",      { XM, Vex, EXx }, 0 },
10020   },
10021   {
10022     /* VEX_W_0F380D_P_2  */
10023     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10024   },
10025   {
10026     /* VEX_W_0F380E_P_2  */
10027     { "vtestps",        { XM, EXx }, 0 },
10028   },
10029   {
10030     /* VEX_W_0F380F_P_2  */
10031     { "vtestpd",        { XM, EXx }, 0 },
10032   },
10033   {
10034     /* VEX_W_0F3816_P_2  */
10035     { "vpermps",        { XM, Vex, EXx }, 0 },
10036   },
10037   {
10038     /* VEX_W_0F3818_P_2 */
10039     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10040   },
10041   {
10042     /* VEX_W_0F3819_P_2 */
10043     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10044   },
10045   {
10046     /* VEX_W_0F381A_P_2_M_0 */
10047     { "vbroadcastf128", { XM, Mxmm }, 0 },
10048   },
10049   {
10050     /* VEX_W_0F382C_P_2_M_0 */
10051     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10052   },
10053   {
10054     /* VEX_W_0F382D_P_2_M_0 */
10055     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10056   },
10057   {
10058     /* VEX_W_0F382E_P_2_M_0 */
10059     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10060   },
10061   {
10062     /* VEX_W_0F382F_P_2_M_0 */
10063     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10064   },
10065   {
10066     /* VEX_W_0F3836_P_2  */
10067     { "vpermd",         { XM, Vex, EXx }, 0 },
10068   },
10069   {
10070     /* VEX_W_0F3846_P_2 */
10071     { "vpsravd",        { XM, Vex, EXx }, 0 },
10072   },
10073   {
10074     /* VEX_W_0F3858_P_2 */
10075     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10076   },
10077   {
10078     /* VEX_W_0F3859_P_2 */
10079     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10080   },
10081   {
10082     /* VEX_W_0F385A_P_2_M_0 */
10083     { "vbroadcasti128", { XM, Mxmm }, 0 },
10084   },
10085   {
10086     /* VEX_W_0F3878_P_2 */
10087     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10088   },
10089   {
10090     /* VEX_W_0F3879_P_2 */
10091     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10092   },
10093   {
10094     /* VEX_W_0F38CF_P_2 */
10095     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10096   },
10097   {
10098     /* VEX_W_0F3A00_P_2 */
10099     { Bad_Opcode },
10100     { "vpermq",         { XM, EXx, Ib }, 0 },
10101   },
10102   {
10103     /* VEX_W_0F3A01_P_2 */
10104     { Bad_Opcode },
10105     { "vpermpd",        { XM, EXx, Ib }, 0 },
10106   },
10107   {
10108     /* VEX_W_0F3A02_P_2 */
10109     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10110   },
10111   {
10112     /* VEX_W_0F3A04_P_2 */
10113     { "vpermilps",      { XM, EXx, Ib }, 0 },
10114   },
10115   {
10116     /* VEX_W_0F3A05_P_2 */
10117     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10118   },
10119   {
10120     /* VEX_W_0F3A06_P_2 */
10121     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10122   },
10123   {
10124     /* VEX_W_0F3A18_P_2 */
10125     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10126   },
10127   {
10128     /* VEX_W_0F3A19_P_2 */
10129     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10130   },
10131   {
10132     /* VEX_W_0F3A30_P_2_LEN_0 */
10133     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10134     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10135   },
10136   {
10137     /* VEX_W_0F3A31_P_2_LEN_0 */
10138     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10139     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10140   },
10141   {
10142     /* VEX_W_0F3A32_P_2_LEN_0 */
10143     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10144     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10145   },
10146   {
10147     /* VEX_W_0F3A33_P_2_LEN_0 */
10148     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10149     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10150   },
10151   {
10152     /* VEX_W_0F3A38_P_2 */
10153     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10154   },
10155   {
10156     /* VEX_W_0F3A39_P_2 */
10157     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10158   },
10159   {
10160     /* VEX_W_0F3A46_P_2 */
10161     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10162   },
10163   {
10164     /* VEX_W_0F3A48_P_2 */
10165     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10166     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10167   },
10168   {
10169     /* VEX_W_0F3A49_P_2 */
10170     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10171     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10172   },
10173   {
10174     /* VEX_W_0F3A4A_P_2 */
10175     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10176   },
10177   {
10178     /* VEX_W_0F3A4B_P_2 */
10179     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10180   },
10181   {
10182     /* VEX_W_0F3A4C_P_2 */
10183     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10184   },
10185   {
10186     /* VEX_W_0F3ACE_P_2 */
10187     { Bad_Opcode },
10188     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10189   },
10190   {
10191     /* VEX_W_0F3ACF_P_2 */
10192     { Bad_Opcode },
10193     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10194   },
10195
10196 #include "i386-dis-evex-w.h"
10197 };
10198
10199 static const struct dis386 mod_table[][2] = {
10200   {
10201     /* MOD_8D */
10202     { "leaS",           { Gv, M }, 0 },
10203   },
10204   {
10205     /* MOD_C6_REG_7 */
10206     { Bad_Opcode },
10207     { RM_TABLE (RM_C6_REG_7) },
10208   },
10209   {
10210     /* MOD_C7_REG_7 */
10211     { Bad_Opcode },
10212     { RM_TABLE (RM_C7_REG_7) },
10213   },
10214   {
10215     /* MOD_FF_REG_3 */
10216     { "Jcall^", { indirEp }, 0 },
10217   },
10218   {
10219     /* MOD_FF_REG_5 */
10220     { "Jjmp^", { indirEp }, 0 },
10221   },
10222   {
10223     /* MOD_0F01_REG_0 */
10224     { X86_64_TABLE (X86_64_0F01_REG_0) },
10225     { RM_TABLE (RM_0F01_REG_0) },
10226   },
10227   {
10228     /* MOD_0F01_REG_1 */
10229     { X86_64_TABLE (X86_64_0F01_REG_1) },
10230     { RM_TABLE (RM_0F01_REG_1) },
10231   },
10232   {
10233     /* MOD_0F01_REG_2 */
10234     { X86_64_TABLE (X86_64_0F01_REG_2) },
10235     { RM_TABLE (RM_0F01_REG_2) },
10236   },
10237   {
10238     /* MOD_0F01_REG_3 */
10239     { X86_64_TABLE (X86_64_0F01_REG_3) },
10240     { RM_TABLE (RM_0F01_REG_3) },
10241   },
10242   {
10243     /* MOD_0F01_REG_5 */
10244     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10245     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10246   },
10247   {
10248     /* MOD_0F01_REG_7 */
10249     { "invlpg",         { Mb }, 0 },
10250     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10251   },
10252   {
10253     /* MOD_0F12_PREFIX_0 */
10254     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10255     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10256   },
10257   {
10258     /* MOD_0F13 */
10259     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10260   },
10261   {
10262     /* MOD_0F16_PREFIX_0 */
10263     { "movhps",         { XM, EXq }, 0 },
10264     { "movlhps",        { XM, EXq }, 0 },
10265   },
10266   {
10267     /* MOD_0F17 */
10268     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10269   },
10270   {
10271     /* MOD_0F18_REG_0 */
10272     { "prefetchnta",    { Mb }, 0 },
10273   },
10274   {
10275     /* MOD_0F18_REG_1 */
10276     { "prefetcht0",     { Mb }, 0 },
10277   },
10278   {
10279     /* MOD_0F18_REG_2 */
10280     { "prefetcht1",     { Mb }, 0 },
10281   },
10282   {
10283     /* MOD_0F18_REG_3 */
10284     { "prefetcht2",     { Mb }, 0 },
10285   },
10286   {
10287     /* MOD_0F18_REG_4 */
10288     { "nop/reserved",   { Mb }, 0 },
10289   },
10290   {
10291     /* MOD_0F18_REG_5 */
10292     { "nop/reserved",   { Mb }, 0 },
10293   },
10294   {
10295     /* MOD_0F18_REG_6 */
10296     { "nop/reserved",   { Mb }, 0 },
10297   },
10298   {
10299     /* MOD_0F18_REG_7 */
10300     { "nop/reserved",   { Mb }, 0 },
10301   },
10302   {
10303     /* MOD_0F1A_PREFIX_0 */
10304     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10305     { "nopQ",           { Ev }, 0 },
10306   },
10307   {
10308     /* MOD_0F1B_PREFIX_0 */
10309     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10310     { "nopQ",           { Ev }, 0 },
10311   },
10312   {
10313     /* MOD_0F1B_PREFIX_1 */
10314     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10315     { "nopQ",           { Ev }, 0 },
10316   },
10317   {
10318     /* MOD_0F1C_PREFIX_0 */
10319     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10320     { "nopQ",           { Ev }, 0 },
10321   },
10322   {
10323     /* MOD_0F1E_PREFIX_1 */
10324     { "nopQ",           { Ev }, 0 },
10325     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10326   },
10327   {
10328     /* MOD_0F24 */
10329     { Bad_Opcode },
10330     { "movL",           { Rd, Td }, 0 },
10331   },
10332   {
10333     /* MOD_0F26 */
10334     { Bad_Opcode },
10335     { "movL",           { Td, Rd }, 0 },
10336   },
10337   {
10338     /* MOD_0F2B_PREFIX_0 */
10339     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10340   },
10341   {
10342     /* MOD_0F2B_PREFIX_1 */
10343     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10344   },
10345   {
10346     /* MOD_0F2B_PREFIX_2 */
10347     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10348   },
10349   {
10350     /* MOD_0F2B_PREFIX_3 */
10351     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10352   },
10353   {
10354     /* MOD_0F51 */
10355     { Bad_Opcode },
10356     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10357   },
10358   {
10359     /* MOD_0F71_REG_2 */
10360     { Bad_Opcode },
10361     { "psrlw",          { MS, Ib }, 0 },
10362   },
10363   {
10364     /* MOD_0F71_REG_4 */
10365     { Bad_Opcode },
10366     { "psraw",          { MS, Ib }, 0 },
10367   },
10368   {
10369     /* MOD_0F71_REG_6 */
10370     { Bad_Opcode },
10371     { "psllw",          { MS, Ib }, 0 },
10372   },
10373   {
10374     /* MOD_0F72_REG_2 */
10375     { Bad_Opcode },
10376     { "psrld",          { MS, Ib }, 0 },
10377   },
10378   {
10379     /* MOD_0F72_REG_4 */
10380     { Bad_Opcode },
10381     { "psrad",          { MS, Ib }, 0 },
10382   },
10383   {
10384     /* MOD_0F72_REG_6 */
10385     { Bad_Opcode },
10386     { "pslld",          { MS, Ib }, 0 },
10387   },
10388   {
10389     /* MOD_0F73_REG_2 */
10390     { Bad_Opcode },
10391     { "psrlq",          { MS, Ib }, 0 },
10392   },
10393   {
10394     /* MOD_0F73_REG_3 */
10395     { Bad_Opcode },
10396     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10397   },
10398   {
10399     /* MOD_0F73_REG_6 */
10400     { Bad_Opcode },
10401     { "psllq",          { MS, Ib }, 0 },
10402   },
10403   {
10404     /* MOD_0F73_REG_7 */
10405     { Bad_Opcode },
10406     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10407   },
10408   {
10409     /* MOD_0FAE_REG_0 */
10410     { "fxsave",         { FXSAVE }, 0 },
10411     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10412   },
10413   {
10414     /* MOD_0FAE_REG_1 */
10415     { "fxrstor",        { FXSAVE }, 0 },
10416     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10417   },
10418   {
10419     /* MOD_0FAE_REG_2 */
10420     { "ldmxcsr",        { Md }, 0 },
10421     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10422   },
10423   {
10424     /* MOD_0FAE_REG_3 */
10425     { "stmxcsr",        { Md }, 0 },
10426     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10427   },
10428   {
10429     /* MOD_0FAE_REG_4 */
10430     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10431     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10432   },
10433   {
10434     /* MOD_0FAE_REG_5 */
10435     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10436     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10437   },
10438   {
10439     /* MOD_0FAE_REG_6 */
10440     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10441     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10442   },
10443   {
10444     /* MOD_0FAE_REG_7 */
10445     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10446     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10447   },
10448   {
10449     /* MOD_0FB2 */
10450     { "lssS",           { Gv, Mp }, 0 },
10451   },
10452   {
10453     /* MOD_0FB4 */
10454     { "lfsS",           { Gv, Mp }, 0 },
10455   },
10456   {
10457     /* MOD_0FB5 */
10458     { "lgsS",           { Gv, Mp }, 0 },
10459   },
10460   {
10461     /* MOD_0FC3 */
10462     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10463   },
10464   {
10465     /* MOD_0FC7_REG_3 */
10466     { "xrstors",        { FXSAVE }, 0 },
10467   },
10468   {
10469     /* MOD_0FC7_REG_4 */
10470     { "xsavec",         { FXSAVE }, 0 },
10471   },
10472   {
10473     /* MOD_0FC7_REG_5 */
10474     { "xsaves",         { FXSAVE }, 0 },
10475   },
10476   {
10477     /* MOD_0FC7_REG_6 */
10478     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10479     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10480   },
10481   {
10482     /* MOD_0FC7_REG_7 */
10483     { "vmptrst",        { Mq }, 0 },
10484     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10485   },
10486   {
10487     /* MOD_0FD7 */
10488     { Bad_Opcode },
10489     { "pmovmskb",       { Gdq, MS }, 0 },
10490   },
10491   {
10492     /* MOD_0FE7_PREFIX_2 */
10493     { "movntdq",        { Mx, XM }, 0 },
10494   },
10495   {
10496     /* MOD_0FF0_PREFIX_3 */
10497     { "lddqu",          { XM, M }, 0 },
10498   },
10499   {
10500     /* MOD_0F382A_PREFIX_2 */
10501     { "movntdqa",       { XM, Mx }, 0 },
10502   },
10503   {
10504     /* MOD_0F38F5_PREFIX_2 */
10505     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10506   },
10507   {
10508     /* MOD_0F38F6_PREFIX_0 */
10509     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10510   },
10511   {
10512     /* MOD_0F38F8_PREFIX_1 */
10513     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10514   },
10515   {
10516     /* MOD_0F38F8_PREFIX_2 */
10517     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10518   },
10519   {
10520     /* MOD_0F38F8_PREFIX_3 */
10521     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10522   },
10523   {
10524     /* MOD_0F38F9_PREFIX_0 */
10525     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10526   },
10527   {
10528     /* MOD_62_32BIT */
10529     { "bound{S|}",      { Gv, Ma }, 0 },
10530     { EVEX_TABLE (EVEX_0F) },
10531   },
10532   {
10533     /* MOD_C4_32BIT */
10534     { "lesS",           { Gv, Mp }, 0 },
10535     { VEX_C4_TABLE (VEX_0F) },
10536   },
10537   {
10538     /* MOD_C5_32BIT */
10539     { "ldsS",           { Gv, Mp }, 0 },
10540     { VEX_C5_TABLE (VEX_0F) },
10541   },
10542   {
10543     /* MOD_VEX_0F12_PREFIX_0 */
10544     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10545     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10546   },
10547   {
10548     /* MOD_VEX_0F13 */
10549     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10550   },
10551   {
10552     /* MOD_VEX_0F16_PREFIX_0 */
10553     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10554     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10555   },
10556   {
10557     /* MOD_VEX_0F17 */
10558     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10559   },
10560   {
10561     /* MOD_VEX_0F2B */
10562     { "vmovntpX",       { Mx, XM }, 0 },
10563   },
10564   {
10565     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10566     { Bad_Opcode },
10567     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10568   },
10569   {
10570     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10571     { Bad_Opcode },
10572     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10573   },
10574   {
10575     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10576     { Bad_Opcode },
10577     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10578   },
10579   {
10580     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10581     { Bad_Opcode },
10582     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10583   },
10584   {
10585     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10586     { Bad_Opcode },
10587     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10588   },
10589   {
10590     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10591     { Bad_Opcode },
10592     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10593   },
10594   {
10595     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10596     { Bad_Opcode },
10597     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10598   },
10599   {
10600     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10601     { Bad_Opcode },
10602     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10603   },
10604   {
10605     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10606     { Bad_Opcode },
10607     { "knotw",          { MaskG, MaskR }, 0 },
10608   },
10609   {
10610     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10611     { Bad_Opcode },
10612     { "knotq",          { MaskG, MaskR }, 0 },
10613   },
10614   {
10615     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10616     { Bad_Opcode },
10617     { "knotb",          { MaskG, MaskR }, 0 },
10618   },
10619   {
10620     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10621     { Bad_Opcode },
10622     { "knotd",          { MaskG, MaskR }, 0 },
10623   },
10624   {
10625     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10626     { Bad_Opcode },
10627     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10628   },
10629   {
10630     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10631     { Bad_Opcode },
10632     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10633   },
10634   {
10635     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10636     { Bad_Opcode },
10637     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10638   },
10639   {
10640     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10641     { Bad_Opcode },
10642     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10643   },
10644  {
10645     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10646     { Bad_Opcode },
10647     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10648   },
10649   {
10650     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10651     { Bad_Opcode },
10652     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10653   },
10654   {
10655     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10656     { Bad_Opcode },
10657     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10658   },
10659   {
10660     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10661     { Bad_Opcode },
10662     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10663   },
10664   {
10665     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10666     { Bad_Opcode },
10667     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10668   },
10669   {
10670     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10671     { Bad_Opcode },
10672     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10673   },
10674   {
10675     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10676     { Bad_Opcode },
10677     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10678   },
10679   {
10680     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10681     { Bad_Opcode },
10682     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10683   },
10684   {
10685     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10686     { Bad_Opcode },
10687     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10688   },
10689   {
10690     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10691     { Bad_Opcode },
10692     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10693   },
10694   {
10695     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10696     { Bad_Opcode },
10697     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10698   },
10699   {
10700     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10701     { Bad_Opcode },
10702     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10703   },
10704   {
10705     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10706     { Bad_Opcode },
10707     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10708   },
10709   {
10710     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10711     { Bad_Opcode },
10712     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10713   },
10714   {
10715     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10716     { Bad_Opcode },
10717     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10718   },
10719   {
10720     /* MOD_VEX_0F50 */
10721     { Bad_Opcode },
10722     { "vmovmskpX",      { Gdq, XS }, 0 },
10723   },
10724   {
10725     /* MOD_VEX_0F71_REG_2 */
10726     { Bad_Opcode },
10727     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10728   },
10729   {
10730     /* MOD_VEX_0F71_REG_4 */
10731     { Bad_Opcode },
10732     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10733   },
10734   {
10735     /* MOD_VEX_0F71_REG_6 */
10736     { Bad_Opcode },
10737     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10738   },
10739   {
10740     /* MOD_VEX_0F72_REG_2 */
10741     { Bad_Opcode },
10742     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10743   },
10744   {
10745     /* MOD_VEX_0F72_REG_4 */
10746     { Bad_Opcode },
10747     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10748   },
10749   {
10750     /* MOD_VEX_0F72_REG_6 */
10751     { Bad_Opcode },
10752     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10753   },
10754   {
10755     /* MOD_VEX_0F73_REG_2 */
10756     { Bad_Opcode },
10757     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10758   },
10759   {
10760     /* MOD_VEX_0F73_REG_3 */
10761     { Bad_Opcode },
10762     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10763   },
10764   {
10765     /* MOD_VEX_0F73_REG_6 */
10766     { Bad_Opcode },
10767     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10768   },
10769   {
10770     /* MOD_VEX_0F73_REG_7 */
10771     { Bad_Opcode },
10772     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10773   },
10774   {
10775     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10776     { "kmovw",          { Ew, MaskG }, 0 },
10777     { Bad_Opcode },
10778   },
10779   {
10780     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10781     { "kmovq",          { Eq, MaskG }, 0 },
10782     { Bad_Opcode },
10783   },
10784   {
10785     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10786     { "kmovb",          { Eb, MaskG }, 0 },
10787     { Bad_Opcode },
10788   },
10789   {
10790     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10791     { "kmovd",          { Ed, MaskG }, 0 },
10792     { Bad_Opcode },
10793   },
10794   {
10795     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10796     { Bad_Opcode },
10797     { "kmovw",          { MaskG, Rdq }, 0 },
10798   },
10799   {
10800     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10801     { Bad_Opcode },
10802     { "kmovb",          { MaskG, Rdq }, 0 },
10803   },
10804   {
10805     /* MOD_VEX_0F92_P_3_LEN_0 */
10806     { Bad_Opcode },
10807     { "kmovK",          { MaskG, Rdq }, 0 },
10808   },
10809   {
10810     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10811     { Bad_Opcode },
10812     { "kmovw",          { Gdq, MaskR }, 0 },
10813   },
10814   {
10815     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10816     { Bad_Opcode },
10817     { "kmovb",          { Gdq, MaskR }, 0 },
10818   },
10819   {
10820     /* MOD_VEX_0F93_P_3_LEN_0 */
10821     { Bad_Opcode },
10822     { "kmovK",          { Gdq, MaskR }, 0 },
10823   },
10824   {
10825     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10826     { Bad_Opcode },
10827     { "kortestw", { MaskG, MaskR }, 0 },
10828   },
10829   {
10830     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10831     { Bad_Opcode },
10832     { "kortestq", { MaskG, MaskR }, 0 },
10833   },
10834   {
10835     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10836     { Bad_Opcode },
10837     { "kortestb", { MaskG, MaskR }, 0 },
10838   },
10839   {
10840     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10841     { Bad_Opcode },
10842     { "kortestd", { MaskG, MaskR }, 0 },
10843   },
10844   {
10845     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10846     { Bad_Opcode },
10847     { "ktestw", { MaskG, MaskR }, 0 },
10848   },
10849   {
10850     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10851     { Bad_Opcode },
10852     { "ktestq", { MaskG, MaskR }, 0 },
10853   },
10854   {
10855     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10856     { Bad_Opcode },
10857     { "ktestb", { MaskG, MaskR }, 0 },
10858   },
10859   {
10860     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10861     { Bad_Opcode },
10862     { "ktestd", { MaskG, MaskR }, 0 },
10863   },
10864   {
10865     /* MOD_VEX_0FAE_REG_2 */
10866     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10867   },
10868   {
10869     /* MOD_VEX_0FAE_REG_3 */
10870     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10871   },
10872   {
10873     /* MOD_VEX_0FD7_PREFIX_2 */
10874     { Bad_Opcode },
10875     { "vpmovmskb",      { Gdq, XS }, 0 },
10876   },
10877   {
10878     /* MOD_VEX_0FE7_PREFIX_2 */
10879     { "vmovntdq",       { Mx, XM }, 0 },
10880   },
10881   {
10882     /* MOD_VEX_0FF0_PREFIX_3 */
10883     { "vlddqu",         { XM, M }, 0 },
10884   },
10885   {
10886     /* MOD_VEX_0F381A_PREFIX_2 */
10887     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10888   },
10889   {
10890     /* MOD_VEX_0F382A_PREFIX_2 */
10891     { "vmovntdqa",      { XM, Mx }, 0 },
10892   },
10893   {
10894     /* MOD_VEX_0F382C_PREFIX_2 */
10895     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10896   },
10897   {
10898     /* MOD_VEX_0F382D_PREFIX_2 */
10899     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10900   },
10901   {
10902     /* MOD_VEX_0F382E_PREFIX_2 */
10903     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10904   },
10905   {
10906     /* MOD_VEX_0F382F_PREFIX_2 */
10907     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10908   },
10909   {
10910     /* MOD_VEX_0F385A_PREFIX_2 */
10911     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10912   },
10913   {
10914     /* MOD_VEX_0F388C_PREFIX_2 */
10915     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10916   },
10917   {
10918     /* MOD_VEX_0F388E_PREFIX_2 */
10919     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10920   },
10921   {
10922     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10923     { Bad_Opcode },
10924     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10925   },
10926   {
10927     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10928     { Bad_Opcode },
10929     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10930   },
10931   {
10932     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10933     { Bad_Opcode },
10934     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10935   },
10936   {
10937     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10938     { Bad_Opcode },
10939     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10940   },
10941   {
10942     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10943     { Bad_Opcode },
10944     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10945   },
10946   {
10947     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10948     { Bad_Opcode },
10949     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10950   },
10951   {
10952     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10953     { Bad_Opcode },
10954     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10955   },
10956   {
10957     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10958     { Bad_Opcode },
10959     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10960   },
10961
10962 #include "i386-dis-evex-mod.h"
10963 };
10964
10965 static const struct dis386 rm_table[][8] = {
10966   {
10967     /* RM_C6_REG_7 */
10968     { "xabort",         { Skip_MODRM, Ib }, 0 },
10969   },
10970   {
10971     /* RM_C7_REG_7 */
10972     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10973   },
10974   {
10975     /* RM_0F01_REG_0 */
10976     { "enclv",          { Skip_MODRM }, 0 },
10977     { "vmcall",         { Skip_MODRM }, 0 },
10978     { "vmlaunch",       { Skip_MODRM }, 0 },
10979     { "vmresume",       { Skip_MODRM }, 0 },
10980     { "vmxoff",         { Skip_MODRM }, 0 },
10981     { "pconfig",        { Skip_MODRM }, 0 },
10982   },
10983   {
10984     /* RM_0F01_REG_1 */
10985     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10986     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10987     { "clac",           { Skip_MODRM }, 0 },
10988     { "stac",           { Skip_MODRM }, 0 },
10989     { Bad_Opcode },
10990     { Bad_Opcode },
10991     { Bad_Opcode },
10992     { "encls",          { Skip_MODRM }, 0 },
10993   },
10994   {
10995     /* RM_0F01_REG_2 */
10996     { "xgetbv",         { Skip_MODRM }, 0 },
10997     { "xsetbv",         { Skip_MODRM }, 0 },
10998     { Bad_Opcode },
10999     { Bad_Opcode },
11000     { "vmfunc",         { Skip_MODRM }, 0 },
11001     { "xend",           { Skip_MODRM }, 0 },
11002     { "xtest",          { Skip_MODRM }, 0 },
11003     { "enclu",          { Skip_MODRM }, 0 },
11004   },
11005   {
11006     /* RM_0F01_REG_3 */
11007     { "vmrun",          { Skip_MODRM }, 0 },
11008     { "vmmcall",        { Skip_MODRM }, 0 },
11009     { "vmload",         { Skip_MODRM }, 0 },
11010     { "vmsave",         { Skip_MODRM }, 0 },
11011     { "stgi",           { Skip_MODRM }, 0 },
11012     { "clgi",           { Skip_MODRM }, 0 },
11013     { "skinit",         { Skip_MODRM }, 0 },
11014     { "invlpga",        { Skip_MODRM }, 0 },
11015   },
11016   {
11017     /* RM_0F01_REG_5_MOD_3 */
11018     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11019     { Bad_Opcode },
11020     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11021     { Bad_Opcode },
11022     { Bad_Opcode },
11023     { Bad_Opcode },
11024     { "rdpkru",         { Skip_MODRM }, 0 },
11025     { "wrpkru",         { Skip_MODRM }, 0 },
11026   },
11027   {
11028     /* RM_0F01_REG_7_MOD_3 */
11029     { "swapgs",         { Skip_MODRM }, 0  },
11030     { "rdtscp",         { Skip_MODRM }, 0  },
11031     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11032     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11033     { "clzero",         { Skip_MODRM }, 0  },
11034     { "rdpru",          { Skip_MODRM }, 0  },
11035   },
11036   {
11037     /* RM_0F1E_P_1_MOD_3_REG_7 */
11038     { "nopQ",           { Ev }, 0 },
11039     { "nopQ",           { Ev }, 0 },
11040     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11041     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11042     { "nopQ",           { Ev }, 0 },
11043     { "nopQ",           { Ev }, 0 },
11044     { "nopQ",           { Ev }, 0 },
11045     { "nopQ",           { Ev }, 0 },
11046   },
11047   {
11048     /* RM_0FAE_REG_6_MOD_3 */
11049     { "mfence",         { Skip_MODRM }, 0 },
11050   },
11051   {
11052     /* RM_0FAE_REG_7_MOD_3 */
11053     { "sfence",         { Skip_MODRM }, 0 },
11054
11055   },
11056 };
11057
11058 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11059
11060 /* We use the high bit to indicate different name for the same
11061    prefix.  */
11062 #define REP_PREFIX      (0xf3 | 0x100)
11063 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11064 #define XRELEASE_PREFIX (0xf3 | 0x400)
11065 #define BND_PREFIX      (0xf2 | 0x400)
11066 #define NOTRACK_PREFIX  (0x3e | 0x100)
11067
11068 static int
11069 ckprefix (void)
11070 {
11071   int newrex, i, length;
11072   rex = 0;
11073   rex_ignored = 0;
11074   prefixes = 0;
11075   used_prefixes = 0;
11076   rex_used = 0;
11077   last_lock_prefix = -1;
11078   last_repz_prefix = -1;
11079   last_repnz_prefix = -1;
11080   last_data_prefix = -1;
11081   last_addr_prefix = -1;
11082   last_rex_prefix = -1;
11083   last_seg_prefix = -1;
11084   fwait_prefix = -1;
11085   active_seg_prefix = 0;
11086   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11087     all_prefixes[i] = 0;
11088   i = 0;
11089   length = 0;
11090   /* The maximum instruction length is 15bytes.  */
11091   while (length < MAX_CODE_LENGTH - 1)
11092     {
11093       FETCH_DATA (the_info, codep + 1);
11094       newrex = 0;
11095       switch (*codep)
11096         {
11097         /* REX prefixes family.  */
11098         case 0x40:
11099         case 0x41:
11100         case 0x42:
11101         case 0x43:
11102         case 0x44:
11103         case 0x45:
11104         case 0x46:
11105         case 0x47:
11106         case 0x48:
11107         case 0x49:
11108         case 0x4a:
11109         case 0x4b:
11110         case 0x4c:
11111         case 0x4d:
11112         case 0x4e:
11113         case 0x4f:
11114           if (address_mode == mode_64bit)
11115             newrex = *codep;
11116           else
11117             return 1;
11118           last_rex_prefix = i;
11119           break;
11120         case 0xf3:
11121           prefixes |= PREFIX_REPZ;
11122           last_repz_prefix = i;
11123           break;
11124         case 0xf2:
11125           prefixes |= PREFIX_REPNZ;
11126           last_repnz_prefix = i;
11127           break;
11128         case 0xf0:
11129           prefixes |= PREFIX_LOCK;
11130           last_lock_prefix = i;
11131           break;
11132         case 0x2e:
11133           prefixes |= PREFIX_CS;
11134           last_seg_prefix = i;
11135           active_seg_prefix = PREFIX_CS;
11136           break;
11137         case 0x36:
11138           prefixes |= PREFIX_SS;
11139           last_seg_prefix = i;
11140           active_seg_prefix = PREFIX_SS;
11141           break;
11142         case 0x3e:
11143           prefixes |= PREFIX_DS;
11144           last_seg_prefix = i;
11145           active_seg_prefix = PREFIX_DS;
11146           break;
11147         case 0x26:
11148           prefixes |= PREFIX_ES;
11149           last_seg_prefix = i;
11150           active_seg_prefix = PREFIX_ES;
11151           break;
11152         case 0x64:
11153           prefixes |= PREFIX_FS;
11154           last_seg_prefix = i;
11155           active_seg_prefix = PREFIX_FS;
11156           break;
11157         case 0x65:
11158           prefixes |= PREFIX_GS;
11159           last_seg_prefix = i;
11160           active_seg_prefix = PREFIX_GS;
11161           break;
11162         case 0x66:
11163           prefixes |= PREFIX_DATA;
11164           last_data_prefix = i;
11165           break;
11166         case 0x67:
11167           prefixes |= PREFIX_ADDR;
11168           last_addr_prefix = i;
11169           break;
11170         case FWAIT_OPCODE:
11171           /* fwait is really an instruction.  If there are prefixes
11172              before the fwait, they belong to the fwait, *not* to the
11173              following instruction.  */
11174           fwait_prefix = i;
11175           if (prefixes || rex)
11176             {
11177               prefixes |= PREFIX_FWAIT;
11178               codep++;
11179               /* This ensures that the previous REX prefixes are noticed
11180                  as unused prefixes, as in the return case below.  */
11181               rex_used = rex;
11182               return 1;
11183             }
11184           prefixes = PREFIX_FWAIT;
11185           break;
11186         default:
11187           return 1;
11188         }
11189       /* Rex is ignored when followed by another prefix.  */
11190       if (rex)
11191         {
11192           rex_used = rex;
11193           return 1;
11194         }
11195       if (*codep != FWAIT_OPCODE)
11196         all_prefixes[i++] = *codep;
11197       rex = newrex;
11198       codep++;
11199       length++;
11200     }
11201   return 0;
11202 }
11203
11204 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11205    prefix byte.  */
11206
11207 static const char *
11208 prefix_name (int pref, int sizeflag)
11209 {
11210   static const char *rexes [16] =
11211     {
11212       "rex",            /* 0x40 */
11213       "rex.B",          /* 0x41 */
11214       "rex.X",          /* 0x42 */
11215       "rex.XB",         /* 0x43 */
11216       "rex.R",          /* 0x44 */
11217       "rex.RB",         /* 0x45 */
11218       "rex.RX",         /* 0x46 */
11219       "rex.RXB",        /* 0x47 */
11220       "rex.W",          /* 0x48 */
11221       "rex.WB",         /* 0x49 */
11222       "rex.WX",         /* 0x4a */
11223       "rex.WXB",        /* 0x4b */
11224       "rex.WR",         /* 0x4c */
11225       "rex.WRB",        /* 0x4d */
11226       "rex.WRX",        /* 0x4e */
11227       "rex.WRXB",       /* 0x4f */
11228     };
11229
11230   switch (pref)
11231     {
11232     /* REX prefixes family.  */
11233     case 0x40:
11234     case 0x41:
11235     case 0x42:
11236     case 0x43:
11237     case 0x44:
11238     case 0x45:
11239     case 0x46:
11240     case 0x47:
11241     case 0x48:
11242     case 0x49:
11243     case 0x4a:
11244     case 0x4b:
11245     case 0x4c:
11246     case 0x4d:
11247     case 0x4e:
11248     case 0x4f:
11249       return rexes [pref - 0x40];
11250     case 0xf3:
11251       return "repz";
11252     case 0xf2:
11253       return "repnz";
11254     case 0xf0:
11255       return "lock";
11256     case 0x2e:
11257       return "cs";
11258     case 0x36:
11259       return "ss";
11260     case 0x3e:
11261       return "ds";
11262     case 0x26:
11263       return "es";
11264     case 0x64:
11265       return "fs";
11266     case 0x65:
11267       return "gs";
11268     case 0x66:
11269       return (sizeflag & DFLAG) ? "data16" : "data32";
11270     case 0x67:
11271       if (address_mode == mode_64bit)
11272         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11273       else
11274         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11275     case FWAIT_OPCODE:
11276       return "fwait";
11277     case REP_PREFIX:
11278       return "rep";
11279     case XACQUIRE_PREFIX:
11280       return "xacquire";
11281     case XRELEASE_PREFIX:
11282       return "xrelease";
11283     case BND_PREFIX:
11284       return "bnd";
11285     case NOTRACK_PREFIX:
11286       return "notrack";
11287     default:
11288       return NULL;
11289     }
11290 }
11291
11292 static char op_out[MAX_OPERANDS][100];
11293 static int op_ad, op_index[MAX_OPERANDS];
11294 static int two_source_ops;
11295 static bfd_vma op_address[MAX_OPERANDS];
11296 static bfd_vma op_riprel[MAX_OPERANDS];
11297 static bfd_vma start_pc;
11298
11299 /*
11300  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11301  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11302  *   section of the "Virtual 8086 Mode" chapter.)
11303  * 'pc' should be the address of this instruction, it will
11304  *   be used to print the target address if this is a relative jump or call
11305  * The function returns the length of this instruction in bytes.
11306  */
11307
11308 static char intel_syntax;
11309 static char intel_mnemonic = !SYSV386_COMPAT;
11310 static char open_char;
11311 static char close_char;
11312 static char separator_char;
11313 static char scale_char;
11314
11315 enum x86_64_isa
11316 {
11317   amd64 = 0,
11318   intel64
11319 };
11320
11321 static enum x86_64_isa isa64;
11322
11323 /* Here for backwards compatibility.  When gdb stops using
11324    print_insn_i386_att and print_insn_i386_intel these functions can
11325    disappear, and print_insn_i386 be merged into print_insn.  */
11326 int
11327 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11328 {
11329   intel_syntax = 0;
11330
11331   return print_insn (pc, info);
11332 }
11333
11334 int
11335 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11336 {
11337   intel_syntax = 1;
11338
11339   return print_insn (pc, info);
11340 }
11341
11342 int
11343 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11344 {
11345   intel_syntax = -1;
11346
11347   return print_insn (pc, info);
11348 }
11349
11350 void
11351 print_i386_disassembler_options (FILE *stream)
11352 {
11353   fprintf (stream, _("\n\
11354 The following i386/x86-64 specific disassembler options are supported for use\n\
11355 with the -M switch (multiple options should be separated by commas):\n"));
11356
11357   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11358   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11359   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11360   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11361   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11362   fprintf (stream, _("  att-mnemonic\n"
11363                      "              Display instruction in AT&T mnemonic\n"));
11364   fprintf (stream, _("  intel-mnemonic\n"
11365                      "              Display instruction in Intel mnemonic\n"));
11366   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11367   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11368   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11369   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11370   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11371   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11372   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11373   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11374 }
11375
11376 /* Bad opcode.  */
11377 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11378
11379 /* Get a pointer to struct dis386 with a valid name.  */
11380
11381 static const struct dis386 *
11382 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11383 {
11384   int vindex, vex_table_index;
11385
11386   if (dp->name != NULL)
11387     return dp;
11388
11389   switch (dp->op[0].bytemode)
11390     {
11391     case USE_REG_TABLE:
11392       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11393       break;
11394
11395     case USE_MOD_TABLE:
11396       vindex = modrm.mod == 0x3 ? 1 : 0;
11397       dp = &mod_table[dp->op[1].bytemode][vindex];
11398       break;
11399
11400     case USE_RM_TABLE:
11401       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11402       break;
11403
11404     case USE_PREFIX_TABLE:
11405       if (need_vex)
11406         {
11407           /* The prefix in VEX is implicit.  */
11408           switch (vex.prefix)
11409             {
11410             case 0:
11411               vindex = 0;
11412               break;
11413             case REPE_PREFIX_OPCODE:
11414               vindex = 1;
11415               break;
11416             case DATA_PREFIX_OPCODE:
11417               vindex = 2;
11418               break;
11419             case REPNE_PREFIX_OPCODE:
11420               vindex = 3;
11421               break;
11422             default:
11423               abort ();
11424               break;
11425             }
11426         }
11427       else
11428         {
11429           int last_prefix = -1;
11430           int prefix = 0;
11431           vindex = 0;
11432           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11433              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11434              last one wins.  */
11435           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11436             {
11437               if (last_repz_prefix > last_repnz_prefix)
11438                 {
11439                   vindex = 1;
11440                   prefix = PREFIX_REPZ;
11441                   last_prefix = last_repz_prefix;
11442                 }
11443               else
11444                 {
11445                   vindex = 3;
11446                   prefix = PREFIX_REPNZ;
11447                   last_prefix = last_repnz_prefix;
11448                 }
11449
11450               /* Check if prefix should be ignored.  */
11451               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11452                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11453                    & prefix) != 0)
11454                 vindex = 0;
11455             }
11456
11457           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11458             {
11459               vindex = 2;
11460               prefix = PREFIX_DATA;
11461               last_prefix = last_data_prefix;
11462             }
11463
11464           if (vindex != 0)
11465             {
11466               used_prefixes |= prefix;
11467               all_prefixes[last_prefix] = 0;
11468             }
11469         }
11470       dp = &prefix_table[dp->op[1].bytemode][vindex];
11471       break;
11472
11473     case USE_X86_64_TABLE:
11474       vindex = address_mode == mode_64bit ? 1 : 0;
11475       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11476       break;
11477
11478     case USE_3BYTE_TABLE:
11479       FETCH_DATA (info, codep + 2);
11480       vindex = *codep++;
11481       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11482       end_codep = codep;
11483       modrm.mod = (*codep >> 6) & 3;
11484       modrm.reg = (*codep >> 3) & 7;
11485       modrm.rm = *codep & 7;
11486       break;
11487
11488     case USE_VEX_LEN_TABLE:
11489       if (!need_vex)
11490         abort ();
11491
11492       switch (vex.length)
11493         {
11494         case 128:
11495           vindex = 0;
11496           break;
11497         case 256:
11498           vindex = 1;
11499           break;
11500         default:
11501           abort ();
11502           break;
11503         }
11504
11505       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11506       break;
11507
11508     case USE_EVEX_LEN_TABLE:
11509       if (!vex.evex)
11510         abort ();
11511
11512       switch (vex.length)
11513         {
11514         case 128:
11515           vindex = 0;
11516           break;
11517         case 256:
11518           vindex = 1;
11519           break;
11520         case 512:
11521           vindex = 2;
11522           break;
11523         default:
11524           abort ();
11525           break;
11526         }
11527
11528       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11529       break;
11530
11531     case USE_XOP_8F_TABLE:
11532       FETCH_DATA (info, codep + 3);
11533       /* All bits in the REX prefix are ignored.  */
11534       rex_ignored = rex;
11535       rex = ~(*codep >> 5) & 0x7;
11536
11537       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11538       switch ((*codep & 0x1f))
11539         {
11540         default:
11541           dp = &bad_opcode;
11542           return dp;
11543         case 0x8:
11544           vex_table_index = XOP_08;
11545           break;
11546         case 0x9:
11547           vex_table_index = XOP_09;
11548           break;
11549         case 0xa:
11550           vex_table_index = XOP_0A;
11551           break;
11552         }
11553       codep++;
11554       vex.w = *codep & 0x80;
11555       if (vex.w && address_mode == mode_64bit)
11556         rex |= REX_W;
11557
11558       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11559       if (address_mode != mode_64bit)
11560         {
11561           /* In 16/32-bit mode REX_B is silently ignored.  */
11562           rex &= ~REX_B;
11563         }
11564
11565       vex.length = (*codep & 0x4) ? 256 : 128;
11566       switch ((*codep & 0x3))
11567         {
11568         case 0:
11569           break;
11570         case 1:
11571           vex.prefix = DATA_PREFIX_OPCODE;
11572           break;
11573         case 2:
11574           vex.prefix = REPE_PREFIX_OPCODE;
11575           break;
11576         case 3:
11577           vex.prefix = REPNE_PREFIX_OPCODE;
11578           break;
11579         }
11580       need_vex = 1;
11581       need_vex_reg = 1;
11582       codep++;
11583       vindex = *codep++;
11584       dp = &xop_table[vex_table_index][vindex];
11585
11586       end_codep = codep;
11587       FETCH_DATA (info, codep + 1);
11588       modrm.mod = (*codep >> 6) & 3;
11589       modrm.reg = (*codep >> 3) & 7;
11590       modrm.rm = *codep & 7;
11591       break;
11592
11593     case USE_VEX_C4_TABLE:
11594       /* VEX prefix.  */
11595       FETCH_DATA (info, codep + 3);
11596       /* All bits in the REX prefix are ignored.  */
11597       rex_ignored = rex;
11598       rex = ~(*codep >> 5) & 0x7;
11599       switch ((*codep & 0x1f))
11600         {
11601         default:
11602           dp = &bad_opcode;
11603           return dp;
11604         case 0x1:
11605           vex_table_index = VEX_0F;
11606           break;
11607         case 0x2:
11608           vex_table_index = VEX_0F38;
11609           break;
11610         case 0x3:
11611           vex_table_index = VEX_0F3A;
11612           break;
11613         }
11614       codep++;
11615       vex.w = *codep & 0x80;
11616       if (address_mode == mode_64bit)
11617         {
11618           if (vex.w)
11619             rex |= REX_W;
11620         }
11621       else
11622         {
11623           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11624              is ignored, other REX bits are 0 and the highest bit in
11625              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11626           rex = 0;
11627         }
11628       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11629       vex.length = (*codep & 0x4) ? 256 : 128;
11630       switch ((*codep & 0x3))
11631         {
11632         case 0:
11633           break;
11634         case 1:
11635           vex.prefix = DATA_PREFIX_OPCODE;
11636           break;
11637         case 2:
11638           vex.prefix = REPE_PREFIX_OPCODE;
11639           break;
11640         case 3:
11641           vex.prefix = REPNE_PREFIX_OPCODE;
11642           break;
11643         }
11644       need_vex = 1;
11645       need_vex_reg = 1;
11646       codep++;
11647       vindex = *codep++;
11648       dp = &vex_table[vex_table_index][vindex];
11649       end_codep = codep;
11650       /* There is no MODRM byte for VEX0F 77.  */
11651       if (vex_table_index != VEX_0F || vindex != 0x77)
11652         {
11653           FETCH_DATA (info, codep + 1);
11654           modrm.mod = (*codep >> 6) & 3;
11655           modrm.reg = (*codep >> 3) & 7;
11656           modrm.rm = *codep & 7;
11657         }
11658       break;
11659
11660     case USE_VEX_C5_TABLE:
11661       /* VEX prefix.  */
11662       FETCH_DATA (info, codep + 2);
11663       /* All bits in the REX prefix are ignored.  */
11664       rex_ignored = rex;
11665       rex = (*codep & 0x80) ? 0 : REX_R;
11666
11667       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11668          VEX.vvvv is 1.  */
11669       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11670       vex.length = (*codep & 0x4) ? 256 : 128;
11671       switch ((*codep & 0x3))
11672         {
11673         case 0:
11674           break;
11675         case 1:
11676           vex.prefix = DATA_PREFIX_OPCODE;
11677           break;
11678         case 2:
11679           vex.prefix = REPE_PREFIX_OPCODE;
11680           break;
11681         case 3:
11682           vex.prefix = REPNE_PREFIX_OPCODE;
11683           break;
11684         }
11685       need_vex = 1;
11686       need_vex_reg = 1;
11687       codep++;
11688       vindex = *codep++;
11689       dp = &vex_table[dp->op[1].bytemode][vindex];
11690       end_codep = codep;
11691       /* There is no MODRM byte for VEX 77.  */
11692       if (vindex != 0x77)
11693         {
11694           FETCH_DATA (info, codep + 1);
11695           modrm.mod = (*codep >> 6) & 3;
11696           modrm.reg = (*codep >> 3) & 7;
11697           modrm.rm = *codep & 7;
11698         }
11699       break;
11700
11701     case USE_VEX_W_TABLE:
11702       if (!need_vex)
11703         abort ();
11704
11705       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11706       break;
11707
11708     case USE_EVEX_TABLE:
11709       two_source_ops = 0;
11710       /* EVEX prefix.  */
11711       vex.evex = 1;
11712       FETCH_DATA (info, codep + 4);
11713       /* All bits in the REX prefix are ignored.  */
11714       rex_ignored = rex;
11715       /* The first byte after 0x62.  */
11716       rex = ~(*codep >> 5) & 0x7;
11717       vex.r = *codep & 0x10;
11718       switch ((*codep & 0xf))
11719         {
11720         default:
11721           return &bad_opcode;
11722         case 0x1:
11723           vex_table_index = EVEX_0F;
11724           break;
11725         case 0x2:
11726           vex_table_index = EVEX_0F38;
11727           break;
11728         case 0x3:
11729           vex_table_index = EVEX_0F3A;
11730           break;
11731         }
11732
11733       /* The second byte after 0x62.  */
11734       codep++;
11735       vex.w = *codep & 0x80;
11736       if (vex.w && address_mode == mode_64bit)
11737         rex |= REX_W;
11738
11739       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11740
11741       /* The U bit.  */
11742       if (!(*codep & 0x4))
11743         return &bad_opcode;
11744
11745       switch ((*codep & 0x3))
11746         {
11747         case 0:
11748           break;
11749         case 1:
11750           vex.prefix = DATA_PREFIX_OPCODE;
11751           break;
11752         case 2:
11753           vex.prefix = REPE_PREFIX_OPCODE;
11754           break;
11755         case 3:
11756           vex.prefix = REPNE_PREFIX_OPCODE;
11757           break;
11758         }
11759
11760       /* The third byte after 0x62.  */
11761       codep++;
11762
11763       /* Remember the static rounding bits.  */
11764       vex.ll = (*codep >> 5) & 3;
11765       vex.b = (*codep & 0x10) != 0;
11766
11767       vex.v = *codep & 0x8;
11768       vex.mask_register_specifier = *codep & 0x7;
11769       vex.zeroing = *codep & 0x80;
11770
11771       if (address_mode != mode_64bit)
11772         {
11773           /* In 16/32-bit mode silently ignore following bits.  */
11774           rex &= ~REX_B;
11775           vex.r = 1;
11776           vex.v = 1;
11777         }
11778
11779       need_vex = 1;
11780       need_vex_reg = 1;
11781       codep++;
11782       vindex = *codep++;
11783       dp = &evex_table[vex_table_index][vindex];
11784       end_codep = codep;
11785       FETCH_DATA (info, codep + 1);
11786       modrm.mod = (*codep >> 6) & 3;
11787       modrm.reg = (*codep >> 3) & 7;
11788       modrm.rm = *codep & 7;
11789
11790       /* Set vector length.  */
11791       if (modrm.mod == 3 && vex.b)
11792         vex.length = 512;
11793       else
11794         {
11795           switch (vex.ll)
11796             {
11797             case 0x0:
11798               vex.length = 128;
11799               break;
11800             case 0x1:
11801               vex.length = 256;
11802               break;
11803             case 0x2:
11804               vex.length = 512;
11805               break;
11806             default:
11807               return &bad_opcode;
11808             }
11809         }
11810       break;
11811
11812     case 0:
11813       dp = &bad_opcode;
11814       break;
11815
11816     default:
11817       abort ();
11818     }
11819
11820   if (dp->name != NULL)
11821     return dp;
11822   else
11823     return get_valid_dis386 (dp, info);
11824 }
11825
11826 static void
11827 get_sib (disassemble_info *info, int sizeflag)
11828 {
11829   /* If modrm.mod == 3, operand must be register.  */
11830   if (need_modrm
11831       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11832       && modrm.mod != 3
11833       && modrm.rm == 4)
11834     {
11835       FETCH_DATA (info, codep + 2);
11836       sib.index = (codep [1] >> 3) & 7;
11837       sib.scale = (codep [1] >> 6) & 3;
11838       sib.base = codep [1] & 7;
11839     }
11840 }
11841
11842 static int
11843 print_insn (bfd_vma pc, disassemble_info *info)
11844 {
11845   const struct dis386 *dp;
11846   int i;
11847   char *op_txt[MAX_OPERANDS];
11848   int needcomma;
11849   int sizeflag, orig_sizeflag;
11850   const char *p;
11851   struct dis_private priv;
11852   int prefix_length;
11853
11854   priv.orig_sizeflag = AFLAG | DFLAG;
11855   if ((info->mach & bfd_mach_i386_i386) != 0)
11856     address_mode = mode_32bit;
11857   else if (info->mach == bfd_mach_i386_i8086)
11858     {
11859       address_mode = mode_16bit;
11860       priv.orig_sizeflag = 0;
11861     }
11862   else
11863     address_mode = mode_64bit;
11864
11865   if (intel_syntax == (char) -1)
11866     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11867
11868   for (p = info->disassembler_options; p != NULL; )
11869     {
11870       if (CONST_STRNEQ (p, "amd64"))
11871         isa64 = amd64;
11872       else if (CONST_STRNEQ (p, "intel64"))
11873         isa64 = intel64;
11874       else if (CONST_STRNEQ (p, "x86-64"))
11875         {
11876           address_mode = mode_64bit;
11877           priv.orig_sizeflag = AFLAG | DFLAG;
11878         }
11879       else if (CONST_STRNEQ (p, "i386"))
11880         {
11881           address_mode = mode_32bit;
11882           priv.orig_sizeflag = AFLAG | DFLAG;
11883         }
11884       else if (CONST_STRNEQ (p, "i8086"))
11885         {
11886           address_mode = mode_16bit;
11887           priv.orig_sizeflag = 0;
11888         }
11889       else if (CONST_STRNEQ (p, "intel"))
11890         {
11891           intel_syntax = 1;
11892           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11893             intel_mnemonic = 1;
11894         }
11895       else if (CONST_STRNEQ (p, "att"))
11896         {
11897           intel_syntax = 0;
11898           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11899             intel_mnemonic = 0;
11900         }
11901       else if (CONST_STRNEQ (p, "addr"))
11902         {
11903           if (address_mode == mode_64bit)
11904             {
11905               if (p[4] == '3' && p[5] == '2')
11906                 priv.orig_sizeflag &= ~AFLAG;
11907               else if (p[4] == '6' && p[5] == '4')
11908                 priv.orig_sizeflag |= AFLAG;
11909             }
11910           else
11911             {
11912               if (p[4] == '1' && p[5] == '6')
11913                 priv.orig_sizeflag &= ~AFLAG;
11914               else if (p[4] == '3' && p[5] == '2')
11915                 priv.orig_sizeflag |= AFLAG;
11916             }
11917         }
11918       else if (CONST_STRNEQ (p, "data"))
11919         {
11920           if (p[4] == '1' && p[5] == '6')
11921             priv.orig_sizeflag &= ~DFLAG;
11922           else if (p[4] == '3' && p[5] == '2')
11923             priv.orig_sizeflag |= DFLAG;
11924         }
11925       else if (CONST_STRNEQ (p, "suffix"))
11926         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11927
11928       p = strchr (p, ',');
11929       if (p != NULL)
11930         p++;
11931     }
11932
11933   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11934     {
11935       (*info->fprintf_func) (info->stream,
11936                              _("64-bit address is disabled"));
11937       return -1;
11938     }
11939
11940   if (intel_syntax)
11941     {
11942       names64 = intel_names64;
11943       names32 = intel_names32;
11944       names16 = intel_names16;
11945       names8 = intel_names8;
11946       names8rex = intel_names8rex;
11947       names_seg = intel_names_seg;
11948       names_mm = intel_names_mm;
11949       names_bnd = intel_names_bnd;
11950       names_xmm = intel_names_xmm;
11951       names_ymm = intel_names_ymm;
11952       names_zmm = intel_names_zmm;
11953       index64 = intel_index64;
11954       index32 = intel_index32;
11955       names_mask = intel_names_mask;
11956       index16 = intel_index16;
11957       open_char = '[';
11958       close_char = ']';
11959       separator_char = '+';
11960       scale_char = '*';
11961     }
11962   else
11963     {
11964       names64 = att_names64;
11965       names32 = att_names32;
11966       names16 = att_names16;
11967       names8 = att_names8;
11968       names8rex = att_names8rex;
11969       names_seg = att_names_seg;
11970       names_mm = att_names_mm;
11971       names_bnd = att_names_bnd;
11972       names_xmm = att_names_xmm;
11973       names_ymm = att_names_ymm;
11974       names_zmm = att_names_zmm;
11975       index64 = att_index64;
11976       index32 = att_index32;
11977       names_mask = att_names_mask;
11978       index16 = att_index16;
11979       open_char = '(';
11980       close_char =  ')';
11981       separator_char = ',';
11982       scale_char = ',';
11983     }
11984
11985   /* The output looks better if we put 7 bytes on a line, since that
11986      puts most long word instructions on a single line.  Use 8 bytes
11987      for Intel L1OM.  */
11988   if ((info->mach & bfd_mach_l1om) != 0)
11989     info->bytes_per_line = 8;
11990   else
11991     info->bytes_per_line = 7;
11992
11993   info->private_data = &priv;
11994   priv.max_fetched = priv.the_buffer;
11995   priv.insn_start = pc;
11996
11997   obuf[0] = 0;
11998   for (i = 0; i < MAX_OPERANDS; ++i)
11999     {
12000       op_out[i][0] = 0;
12001       op_index[i] = -1;
12002     }
12003
12004   the_info = info;
12005   start_pc = pc;
12006   start_codep = priv.the_buffer;
12007   codep = priv.the_buffer;
12008
12009   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12010     {
12011       const char *name;
12012
12013       /* Getting here means we tried for data but didn't get it.  That
12014          means we have an incomplete instruction of some sort.  Just
12015          print the first byte as a prefix or a .byte pseudo-op.  */
12016       if (codep > priv.the_buffer)
12017         {
12018           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12019           if (name != NULL)
12020             (*info->fprintf_func) (info->stream, "%s", name);
12021           else
12022             {
12023               /* Just print the first byte as a .byte instruction.  */
12024               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12025                                      (unsigned int) priv.the_buffer[0]);
12026             }
12027
12028           return 1;
12029         }
12030
12031       return -1;
12032     }
12033
12034   obufp = obuf;
12035   sizeflag = priv.orig_sizeflag;
12036
12037   if (!ckprefix () || rex_used)
12038     {
12039       /* Too many prefixes or unused REX prefixes.  */
12040       for (i = 0;
12041            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12042            i++)
12043         (*info->fprintf_func) (info->stream, "%s%s",
12044                                i == 0 ? "" : " ",
12045                                prefix_name (all_prefixes[i], sizeflag));
12046       return i;
12047     }
12048
12049   insn_codep = codep;
12050
12051   FETCH_DATA (info, codep + 1);
12052   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12053
12054   if (((prefixes & PREFIX_FWAIT)
12055        && ((*codep < 0xd8) || (*codep > 0xdf))))
12056     {
12057       /* Handle prefixes before fwait.  */
12058       for (i = 0; i < fwait_prefix && all_prefixes[i];
12059            i++)
12060         (*info->fprintf_func) (info->stream, "%s ",
12061                                prefix_name (all_prefixes[i], sizeflag));
12062       (*info->fprintf_func) (info->stream, "fwait");
12063       return i + 1;
12064     }
12065
12066   if (*codep == 0x0f)
12067     {
12068       unsigned char threebyte;
12069
12070       codep++;
12071       FETCH_DATA (info, codep + 1);
12072       threebyte = *codep;
12073       dp = &dis386_twobyte[threebyte];
12074       need_modrm = twobyte_has_modrm[*codep];
12075       codep++;
12076     }
12077   else
12078     {
12079       dp = &dis386[*codep];
12080       need_modrm = onebyte_has_modrm[*codep];
12081       codep++;
12082     }
12083
12084   /* Save sizeflag for printing the extra prefixes later before updating
12085      it for mnemonic and operand processing.  The prefix names depend
12086      only on the address mode.  */
12087   orig_sizeflag = sizeflag;
12088   if (prefixes & PREFIX_ADDR)
12089     sizeflag ^= AFLAG;
12090   if ((prefixes & PREFIX_DATA))
12091     sizeflag ^= DFLAG;
12092
12093   end_codep = codep;
12094   if (need_modrm)
12095     {
12096       FETCH_DATA (info, codep + 1);
12097       modrm.mod = (*codep >> 6) & 3;
12098       modrm.reg = (*codep >> 3) & 7;
12099       modrm.rm = *codep & 7;
12100     }
12101
12102   need_vex = 0;
12103   need_vex_reg = 0;
12104   vex_w_done = 0;
12105   memset (&vex, 0, sizeof (vex));
12106
12107   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12108     {
12109       get_sib (info, sizeflag);
12110       dofloat (sizeflag);
12111     }
12112   else
12113     {
12114       dp = get_valid_dis386 (dp, info);
12115       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12116         {
12117           get_sib (info, sizeflag);
12118           for (i = 0; i < MAX_OPERANDS; ++i)
12119             {
12120               obufp = op_out[i];
12121               op_ad = MAX_OPERANDS - 1 - i;
12122               if (dp->op[i].rtn)
12123                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12124               /* For EVEX instruction after the last operand masking
12125                  should be printed.  */
12126               if (i == 0 && vex.evex)
12127                 {
12128                   /* Don't print {%k0}.  */
12129                   if (vex.mask_register_specifier)
12130                     {
12131                       oappend ("{");
12132                       oappend (names_mask[vex.mask_register_specifier]);
12133                       oappend ("}");
12134                     }
12135                   if (vex.zeroing)
12136                     oappend ("{z}");
12137                 }
12138             }
12139         }
12140     }
12141
12142   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12143      are all 0s in inverted form.  */
12144   if (need_vex && vex.register_specifier != 0)
12145     {
12146       (*info->fprintf_func) (info->stream, "(bad)");
12147       return end_codep - priv.the_buffer;
12148     }
12149
12150   /* Check if the REX prefix is used.  */
12151   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12152     all_prefixes[last_rex_prefix] = 0;
12153
12154   /* Check if the SEG prefix is used.  */
12155   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12156                    | PREFIX_FS | PREFIX_GS)) != 0
12157       && (used_prefixes & active_seg_prefix) != 0)
12158     all_prefixes[last_seg_prefix] = 0;
12159
12160   /* Check if the ADDR prefix is used.  */
12161   if ((prefixes & PREFIX_ADDR) != 0
12162       && (used_prefixes & PREFIX_ADDR) != 0)
12163     all_prefixes[last_addr_prefix] = 0;
12164
12165   /* Check if the DATA prefix is used.  */
12166   if ((prefixes & PREFIX_DATA) != 0
12167       && (used_prefixes & PREFIX_DATA) != 0)
12168     all_prefixes[last_data_prefix] = 0;
12169
12170   /* Print the extra prefixes.  */
12171   prefix_length = 0;
12172   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12173     if (all_prefixes[i])
12174       {
12175         const char *name;
12176         name = prefix_name (all_prefixes[i], orig_sizeflag);
12177         if (name == NULL)
12178           abort ();
12179         prefix_length += strlen (name) + 1;
12180         (*info->fprintf_func) (info->stream, "%s ", name);
12181       }
12182
12183   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12184      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12185      used by putop and MMX/SSE operand and may be overriden by the
12186      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12187      separately.  */
12188   if (dp->prefix_requirement == PREFIX_OPCODE
12189       && dp != &bad_opcode
12190       && (((prefixes
12191             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12192            && (used_prefixes
12193                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12194           || ((((prefixes
12195                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12196                 == PREFIX_DATA)
12197                && (used_prefixes & PREFIX_DATA) == 0))))
12198     {
12199       (*info->fprintf_func) (info->stream, "(bad)");
12200       return end_codep - priv.the_buffer;
12201     }
12202
12203   /* Check maximum code length.  */
12204   if ((codep - start_codep) > MAX_CODE_LENGTH)
12205     {
12206       (*info->fprintf_func) (info->stream, "(bad)");
12207       return MAX_CODE_LENGTH;
12208     }
12209
12210   obufp = mnemonicendp;
12211   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12212     oappend (" ");
12213   oappend (" ");
12214   (*info->fprintf_func) (info->stream, "%s", obuf);
12215
12216   /* The enter and bound instructions are printed with operands in the same
12217      order as the intel book; everything else is printed in reverse order.  */
12218   if (intel_syntax || two_source_ops)
12219     {
12220       bfd_vma riprel;
12221
12222       for (i = 0; i < MAX_OPERANDS; ++i)
12223         op_txt[i] = op_out[i];
12224
12225       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12226           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12227         {
12228           op_txt[2] = op_out[3];
12229           op_txt[3] = op_out[2];
12230         }
12231
12232       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12233         {
12234           op_ad = op_index[i];
12235           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12236           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12237           riprel = op_riprel[i];
12238           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12239           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12240         }
12241     }
12242   else
12243     {
12244       for (i = 0; i < MAX_OPERANDS; ++i)
12245         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12246     }
12247
12248   needcomma = 0;
12249   for (i = 0; i < MAX_OPERANDS; ++i)
12250     if (*op_txt[i])
12251       {
12252         if (needcomma)
12253           (*info->fprintf_func) (info->stream, ",");
12254         if (op_index[i] != -1 && !op_riprel[i])
12255           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12256         else
12257           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12258         needcomma = 1;
12259       }
12260
12261   for (i = 0; i < MAX_OPERANDS; i++)
12262     if (op_index[i] != -1 && op_riprel[i])
12263       {
12264         (*info->fprintf_func) (info->stream, "        # ");
12265         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12266                                                 + op_address[op_index[i]]), info);
12267         break;
12268       }
12269   return codep - priv.the_buffer;
12270 }
12271
12272 static const char *float_mem[] = {
12273   /* d8 */
12274   "fadd{s|}",
12275   "fmul{s|}",
12276   "fcom{s|}",
12277   "fcomp{s|}",
12278   "fsub{s|}",
12279   "fsubr{s|}",
12280   "fdiv{s|}",
12281   "fdivr{s|}",
12282   /* d9 */
12283   "fld{s|}",
12284   "(bad)",
12285   "fst{s|}",
12286   "fstp{s|}",
12287   "fldenvIC",
12288   "fldcw",
12289   "fNstenvIC",
12290   "fNstcw",
12291   /* da */
12292   "fiadd{l|}",
12293   "fimul{l|}",
12294   "ficom{l|}",
12295   "ficomp{l|}",
12296   "fisub{l|}",
12297   "fisubr{l|}",
12298   "fidiv{l|}",
12299   "fidivr{l|}",
12300   /* db */
12301   "fild{l|}",
12302   "fisttp{l|}",
12303   "fist{l|}",
12304   "fistp{l|}",
12305   "(bad)",
12306   "fld{t||t|}",
12307   "(bad)",
12308   "fstp{t||t|}",
12309   /* dc */
12310   "fadd{l|}",
12311   "fmul{l|}",
12312   "fcom{l|}",
12313   "fcomp{l|}",
12314   "fsub{l|}",
12315   "fsubr{l|}",
12316   "fdiv{l|}",
12317   "fdivr{l|}",
12318   /* dd */
12319   "fld{l|}",
12320   "fisttp{ll|}",
12321   "fst{l||}",
12322   "fstp{l|}",
12323   "frstorIC",
12324   "(bad)",
12325   "fNsaveIC",
12326   "fNstsw",
12327   /* de */
12328   "fiadd{s|}",
12329   "fimul{s|}",
12330   "ficom{s|}",
12331   "ficomp{s|}",
12332   "fisub{s|}",
12333   "fisubr{s|}",
12334   "fidiv{s|}",
12335   "fidivr{s|}",
12336   /* df */
12337   "fild{s|}",
12338   "fisttp{s|}",
12339   "fist{s|}",
12340   "fistp{s|}",
12341   "fbld",
12342   "fild{ll|}",
12343   "fbstp",
12344   "fistp{ll|}",
12345 };
12346
12347 static const unsigned char float_mem_mode[] = {
12348   /* d8 */
12349   d_mode,
12350   d_mode,
12351   d_mode,
12352   d_mode,
12353   d_mode,
12354   d_mode,
12355   d_mode,
12356   d_mode,
12357   /* d9 */
12358   d_mode,
12359   0,
12360   d_mode,
12361   d_mode,
12362   0,
12363   w_mode,
12364   0,
12365   w_mode,
12366   /* da */
12367   d_mode,
12368   d_mode,
12369   d_mode,
12370   d_mode,
12371   d_mode,
12372   d_mode,
12373   d_mode,
12374   d_mode,
12375   /* db */
12376   d_mode,
12377   d_mode,
12378   d_mode,
12379   d_mode,
12380   0,
12381   t_mode,
12382   0,
12383   t_mode,
12384   /* dc */
12385   q_mode,
12386   q_mode,
12387   q_mode,
12388   q_mode,
12389   q_mode,
12390   q_mode,
12391   q_mode,
12392   q_mode,
12393   /* dd */
12394   q_mode,
12395   q_mode,
12396   q_mode,
12397   q_mode,
12398   0,
12399   0,
12400   0,
12401   w_mode,
12402   /* de */
12403   w_mode,
12404   w_mode,
12405   w_mode,
12406   w_mode,
12407   w_mode,
12408   w_mode,
12409   w_mode,
12410   w_mode,
12411   /* df */
12412   w_mode,
12413   w_mode,
12414   w_mode,
12415   w_mode,
12416   t_mode,
12417   q_mode,
12418   t_mode,
12419   q_mode
12420 };
12421
12422 #define ST { OP_ST, 0 }
12423 #define STi { OP_STi, 0 }
12424
12425 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12426 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12427 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12428 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12429 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12430 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12431 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12432 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12433 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12434
12435 static const struct dis386 float_reg[][8] = {
12436   /* d8 */
12437   {
12438     { "fadd",   { ST, STi }, 0 },
12439     { "fmul",   { ST, STi }, 0 },
12440     { "fcom",   { STi }, 0 },
12441     { "fcomp",  { STi }, 0 },
12442     { "fsub",   { ST, STi }, 0 },
12443     { "fsubr",  { ST, STi }, 0 },
12444     { "fdiv",   { ST, STi }, 0 },
12445     { "fdivr",  { ST, STi }, 0 },
12446   },
12447   /* d9 */
12448   {
12449     { "fld",    { STi }, 0 },
12450     { "fxch",   { STi }, 0 },
12451     { FGRPd9_2 },
12452     { Bad_Opcode },
12453     { FGRPd9_4 },
12454     { FGRPd9_5 },
12455     { FGRPd9_6 },
12456     { FGRPd9_7 },
12457   },
12458   /* da */
12459   {
12460     { "fcmovb", { ST, STi }, 0 },
12461     { "fcmove", { ST, STi }, 0 },
12462     { "fcmovbe",{ ST, STi }, 0 },
12463     { "fcmovu", { ST, STi }, 0 },
12464     { Bad_Opcode },
12465     { FGRPda_5 },
12466     { Bad_Opcode },
12467     { Bad_Opcode },
12468   },
12469   /* db */
12470   {
12471     { "fcmovnb",{ ST, STi }, 0 },
12472     { "fcmovne",{ ST, STi }, 0 },
12473     { "fcmovnbe",{ ST, STi }, 0 },
12474     { "fcmovnu",{ ST, STi }, 0 },
12475     { FGRPdb_4 },
12476     { "fucomi", { ST, STi }, 0 },
12477     { "fcomi",  { ST, STi }, 0 },
12478     { Bad_Opcode },
12479   },
12480   /* dc */
12481   {
12482     { "fadd",   { STi, ST }, 0 },
12483     { "fmul",   { STi, ST }, 0 },
12484     { Bad_Opcode },
12485     { Bad_Opcode },
12486     { "fsub{!M|r}",     { STi, ST }, 0 },
12487     { "fsub{M|}",       { STi, ST }, 0 },
12488     { "fdiv{!M|r}",     { STi, ST }, 0 },
12489     { "fdiv{M|}",       { STi, ST }, 0 },
12490   },
12491   /* dd */
12492   {
12493     { "ffree",  { STi }, 0 },
12494     { Bad_Opcode },
12495     { "fst",    { STi }, 0 },
12496     { "fstp",   { STi }, 0 },
12497     { "fucom",  { STi }, 0 },
12498     { "fucomp", { STi }, 0 },
12499     { Bad_Opcode },
12500     { Bad_Opcode },
12501   },
12502   /* de */
12503   {
12504     { "faddp",  { STi, ST }, 0 },
12505     { "fmulp",  { STi, ST }, 0 },
12506     { Bad_Opcode },
12507     { FGRPde_3 },
12508     { "fsub{!M|r}p",    { STi, ST }, 0 },
12509     { "fsub{M|}p",      { STi, ST }, 0 },
12510     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12511     { "fdiv{M|}p",      { STi, ST }, 0 },
12512   },
12513   /* df */
12514   {
12515     { "ffreep", { STi }, 0 },
12516     { Bad_Opcode },
12517     { Bad_Opcode },
12518     { Bad_Opcode },
12519     { FGRPdf_4 },
12520     { "fucomip", { ST, STi }, 0 },
12521     { "fcomip", { ST, STi }, 0 },
12522     { Bad_Opcode },
12523   },
12524 };
12525
12526 static char *fgrps[][8] = {
12527   /* Bad opcode 0 */
12528   {
12529     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12530   },
12531
12532   /* d9_2  1 */
12533   {
12534     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12535   },
12536
12537   /* d9_4  2 */
12538   {
12539     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12540   },
12541
12542   /* d9_5  3 */
12543   {
12544     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12545   },
12546
12547   /* d9_6  4 */
12548   {
12549     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12550   },
12551
12552   /* d9_7  5 */
12553   {
12554     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12555   },
12556
12557   /* da_5  6 */
12558   {
12559     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12560   },
12561
12562   /* db_4  7 */
12563   {
12564     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12565     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12566   },
12567
12568   /* de_3  8 */
12569   {
12570     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12571   },
12572
12573   /* df_4  9 */
12574   {
12575     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12576   },
12577 };
12578
12579 static void
12580 swap_operand (void)
12581 {
12582   mnemonicendp[0] = '.';
12583   mnemonicendp[1] = 's';
12584   mnemonicendp += 2;
12585 }
12586
12587 static void
12588 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12589                int sizeflag ATTRIBUTE_UNUSED)
12590 {
12591   /* Skip mod/rm byte.  */
12592   MODRM_CHECK;
12593   codep++;
12594 }
12595
12596 static void
12597 dofloat (int sizeflag)
12598 {
12599   const struct dis386 *dp;
12600   unsigned char floatop;
12601
12602   floatop = codep[-1];
12603
12604   if (modrm.mod != 3)
12605     {
12606       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12607
12608       putop (float_mem[fp_indx], sizeflag);
12609       obufp = op_out[0];
12610       op_ad = 2;
12611       OP_E (float_mem_mode[fp_indx], sizeflag);
12612       return;
12613     }
12614   /* Skip mod/rm byte.  */
12615   MODRM_CHECK;
12616   codep++;
12617
12618   dp = &float_reg[floatop - 0xd8][modrm.reg];
12619   if (dp->name == NULL)
12620     {
12621       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12622
12623       /* Instruction fnstsw is only one with strange arg.  */
12624       if (floatop == 0xdf && codep[-1] == 0xe0)
12625         strcpy (op_out[0], names16[0]);
12626     }
12627   else
12628     {
12629       putop (dp->name, sizeflag);
12630
12631       obufp = op_out[0];
12632       op_ad = 2;
12633       if (dp->op[0].rtn)
12634         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12635
12636       obufp = op_out[1];
12637       op_ad = 1;
12638       if (dp->op[1].rtn)
12639         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12640     }
12641 }
12642
12643 /* Like oappend (below), but S is a string starting with '%'.
12644    In Intel syntax, the '%' is elided.  */
12645 static void
12646 oappend_maybe_intel (const char *s)
12647 {
12648   oappend (s + intel_syntax);
12649 }
12650
12651 static void
12652 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12653 {
12654   oappend_maybe_intel ("%st");
12655 }
12656
12657 static void
12658 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12659 {
12660   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12661   oappend_maybe_intel (scratchbuf);
12662 }
12663
12664 /* Capital letters in template are macros.  */
12665 static int
12666 putop (const char *in_template, int sizeflag)
12667 {
12668   const char *p;
12669   int alt = 0;
12670   int cond = 1;
12671   unsigned int l = 0, len = 1;
12672   char last[4];
12673
12674 #define SAVE_LAST(c)                    \
12675   if (l < len && l < sizeof (last))     \
12676     last[l++] = c;                      \
12677   else                                  \
12678     abort ();
12679
12680   for (p = in_template; *p; p++)
12681     {
12682       switch (*p)
12683         {
12684         default:
12685           *obufp++ = *p;
12686           break;
12687         case '%':
12688           len++;
12689           break;
12690         case '!':
12691           cond = 0;
12692           break;
12693         case '{':
12694           if (intel_syntax)
12695             {
12696               while (*++p != '|')
12697                 if (*p == '}' || *p == '\0')
12698                   abort ();
12699             }
12700           /* Fall through.  */
12701         case 'I':
12702           alt = 1;
12703           continue;
12704         case '|':
12705           while (*++p != '}')
12706             {
12707               if (*p == '\0')
12708                 abort ();
12709             }
12710           break;
12711         case '}':
12712           break;
12713         case 'A':
12714           if (intel_syntax)
12715             break;
12716           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12717             *obufp++ = 'b';
12718           break;
12719         case 'B':
12720           if (l == 0 && len == 1)
12721             {
12722 case_B:
12723               if (intel_syntax)
12724                 break;
12725               if (sizeflag & SUFFIX_ALWAYS)
12726                 *obufp++ = 'b';
12727             }
12728           else
12729             {
12730               if (l != 1
12731                   || len != 2
12732                   || last[0] != 'L')
12733                 {
12734                   SAVE_LAST (*p);
12735                   break;
12736                 }
12737
12738               if (address_mode == mode_64bit
12739                   && !(prefixes & PREFIX_ADDR))
12740                 {
12741                   *obufp++ = 'a';
12742                   *obufp++ = 'b';
12743                   *obufp++ = 's';
12744                 }
12745
12746               goto case_B;
12747             }
12748           break;
12749         case 'C':
12750           if (intel_syntax && !alt)
12751             break;
12752           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12753             {
12754               if (sizeflag & DFLAG)
12755                 *obufp++ = intel_syntax ? 'd' : 'l';
12756               else
12757                 *obufp++ = intel_syntax ? 'w' : 's';
12758               used_prefixes |= (prefixes & PREFIX_DATA);
12759             }
12760           break;
12761         case 'D':
12762           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12763             break;
12764           USED_REX (REX_W);
12765           if (modrm.mod == 3)
12766             {
12767               if (rex & REX_W)
12768                 *obufp++ = 'q';
12769               else
12770                 {
12771                   if (sizeflag & DFLAG)
12772                     *obufp++ = intel_syntax ? 'd' : 'l';
12773                   else
12774                     *obufp++ = 'w';
12775                   used_prefixes |= (prefixes & PREFIX_DATA);
12776                 }
12777             }
12778           else
12779             *obufp++ = 'w';
12780           break;
12781         case 'E':               /* For jcxz/jecxz */
12782           if (address_mode == mode_64bit)
12783             {
12784               if (sizeflag & AFLAG)
12785                 *obufp++ = 'r';
12786               else
12787                 *obufp++ = 'e';
12788             }
12789           else
12790             if (sizeflag & AFLAG)
12791               *obufp++ = 'e';
12792           used_prefixes |= (prefixes & PREFIX_ADDR);
12793           break;
12794         case 'F':
12795           if (intel_syntax)
12796             break;
12797           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12798             {
12799               if (sizeflag & AFLAG)
12800                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12801               else
12802                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12803               used_prefixes |= (prefixes & PREFIX_ADDR);
12804             }
12805           break;
12806         case 'G':
12807           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12808             break;
12809           if ((rex & REX_W) || (sizeflag & DFLAG))
12810             *obufp++ = 'l';
12811           else
12812             *obufp++ = 'w';
12813           if (!(rex & REX_W))
12814             used_prefixes |= (prefixes & PREFIX_DATA);
12815           break;
12816         case 'H':
12817           if (intel_syntax)
12818             break;
12819           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12820               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12821             {
12822               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12823               *obufp++ = ',';
12824               *obufp++ = 'p';
12825               if (prefixes & PREFIX_DS)
12826                 *obufp++ = 't';
12827               else
12828                 *obufp++ = 'n';
12829             }
12830           break;
12831         case 'J':
12832           if (intel_syntax)
12833             break;
12834           *obufp++ = 'l';
12835           break;
12836         case 'K':
12837           USED_REX (REX_W);
12838           if (rex & REX_W)
12839             *obufp++ = 'q';
12840           else
12841             *obufp++ = 'd';
12842           break;
12843         case 'Z':
12844           if (l != 0 || len != 1)
12845             {
12846               if (l != 1 || len != 2 || last[0] != 'X')
12847                 {
12848                   SAVE_LAST (*p);
12849                   break;
12850                 }
12851               if (!need_vex || !vex.evex)
12852                 abort ();
12853               if (intel_syntax
12854                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12855                 break;
12856               switch (vex.length)
12857                 {
12858                 case 128:
12859                   *obufp++ = 'x';
12860                   break;
12861                 case 256:
12862                   *obufp++ = 'y';
12863                   break;
12864                 case 512:
12865                   *obufp++ = 'z';
12866                   break;
12867                 default:
12868                   abort ();
12869                 }
12870               break;
12871             }
12872           if (intel_syntax)
12873             break;
12874           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12875             {
12876               *obufp++ = 'q';
12877               break;
12878             }
12879           /* Fall through.  */
12880           goto case_L;
12881         case 'L':
12882           if (l != 0 || len != 1)
12883             {
12884               SAVE_LAST (*p);
12885               break;
12886             }
12887 case_L:
12888           if (intel_syntax)
12889             break;
12890           if (sizeflag & SUFFIX_ALWAYS)
12891             *obufp++ = 'l';
12892           break;
12893         case 'M':
12894           if (intel_mnemonic != cond)
12895             *obufp++ = 'r';
12896           break;
12897         case 'N':
12898           if ((prefixes & PREFIX_FWAIT) == 0)
12899             *obufp++ = 'n';
12900           else
12901             used_prefixes |= PREFIX_FWAIT;
12902           break;
12903         case 'O':
12904           USED_REX (REX_W);
12905           if (rex & REX_W)
12906             *obufp++ = 'o';
12907           else if (intel_syntax && (sizeflag & DFLAG))
12908             *obufp++ = 'q';
12909           else
12910             *obufp++ = 'd';
12911           if (!(rex & REX_W))
12912             used_prefixes |= (prefixes & PREFIX_DATA);
12913           break;
12914         case '&':
12915           if (!intel_syntax
12916               && address_mode == mode_64bit
12917               && isa64 == intel64)
12918             {
12919               *obufp++ = 'q';
12920               break;
12921             }
12922           /* Fall through.  */
12923         case 'T':
12924           if (!intel_syntax
12925               && address_mode == mode_64bit
12926               && ((sizeflag & DFLAG) || (rex & REX_W)))
12927             {
12928               *obufp++ = 'q';
12929               break;
12930             }
12931           /* Fall through.  */
12932           goto case_P;
12933         case 'P':
12934           if (l == 0 && len == 1)
12935             {
12936 case_P:
12937               if (intel_syntax)
12938                 {
12939                   if ((rex & REX_W) == 0
12940                       && (prefixes & PREFIX_DATA))
12941                     {
12942                       if ((sizeflag & DFLAG) == 0)
12943                         *obufp++ = 'w';
12944                       used_prefixes |= (prefixes & PREFIX_DATA);
12945                     }
12946                   break;
12947                 }
12948               if ((prefixes & PREFIX_DATA)
12949                   || (rex & REX_W)
12950                   || (sizeflag & SUFFIX_ALWAYS))
12951                 {
12952                   USED_REX (REX_W);
12953                   if (rex & REX_W)
12954                     *obufp++ = 'q';
12955                   else
12956                     {
12957                       if (sizeflag & DFLAG)
12958                         *obufp++ = 'l';
12959                       else
12960                         *obufp++ = 'w';
12961                       used_prefixes |= (prefixes & PREFIX_DATA);
12962                     }
12963                 }
12964             }
12965           else
12966             {
12967               if (l != 1 || len != 2 || last[0] != 'L')
12968                 {
12969                   SAVE_LAST (*p);
12970                   break;
12971                 }
12972
12973               if ((prefixes & PREFIX_DATA)
12974                   || (rex & REX_W)
12975                   || (sizeflag & SUFFIX_ALWAYS))
12976                 {
12977                   USED_REX (REX_W);
12978                   if (rex & REX_W)
12979                     *obufp++ = 'q';
12980                   else
12981                     {
12982                       if (sizeflag & DFLAG)
12983                         *obufp++ = intel_syntax ? 'd' : 'l';
12984                       else
12985                         *obufp++ = 'w';
12986                       used_prefixes |= (prefixes & PREFIX_DATA);
12987                     }
12988                 }
12989             }
12990           break;
12991         case 'U':
12992           if (intel_syntax)
12993             break;
12994           if (address_mode == mode_64bit
12995               && ((sizeflag & DFLAG) || (rex & REX_W)))
12996             {
12997               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12998                 *obufp++ = 'q';
12999               break;
13000             }
13001           /* Fall through.  */
13002           goto case_Q;
13003         case 'Q':
13004           if (l == 0 && len == 1)
13005             {
13006 case_Q:
13007               if (intel_syntax && !alt)
13008                 break;
13009               USED_REX (REX_W);
13010               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13011                 {
13012                   if (rex & REX_W)
13013                     *obufp++ = 'q';
13014                   else
13015                     {
13016                       if (sizeflag & DFLAG)
13017                         *obufp++ = intel_syntax ? 'd' : 'l';
13018                       else
13019                         *obufp++ = 'w';
13020                       used_prefixes |= (prefixes & PREFIX_DATA);
13021                     }
13022                 }
13023             }
13024           else
13025             {
13026               if (l != 1 || len != 2 || last[0] != 'L')
13027                 {
13028                   SAVE_LAST (*p);
13029                   break;
13030                 }
13031               if (intel_syntax
13032                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13033                 break;
13034               if ((rex & REX_W))
13035                 {
13036                   USED_REX (REX_W);
13037                   *obufp++ = 'q';
13038                 }
13039               else
13040                 *obufp++ = 'l';
13041             }
13042           break;
13043         case 'R':
13044           USED_REX (REX_W);
13045           if (rex & REX_W)
13046             *obufp++ = 'q';
13047           else if (sizeflag & DFLAG)
13048             {
13049               if (intel_syntax)
13050                   *obufp++ = 'd';
13051               else
13052                   *obufp++ = 'l';
13053             }
13054           else
13055             *obufp++ = 'w';
13056           if (intel_syntax && !p[1]
13057               && ((rex & REX_W) || (sizeflag & DFLAG)))
13058             *obufp++ = 'e';
13059           if (!(rex & REX_W))
13060             used_prefixes |= (prefixes & PREFIX_DATA);
13061           break;
13062         case 'V':
13063           if (l == 0 && len == 1)
13064             {
13065               if (intel_syntax)
13066                 break;
13067               if (address_mode == mode_64bit
13068                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13069                 {
13070                   if (sizeflag & SUFFIX_ALWAYS)
13071                     *obufp++ = 'q';
13072                   break;
13073                 }
13074             }
13075           else
13076             {
13077               if (l != 1
13078                   || len != 2
13079                   || last[0] != 'L')
13080                 {
13081                   SAVE_LAST (*p);
13082                   break;
13083                 }
13084
13085               if (rex & REX_W)
13086                 {
13087                   *obufp++ = 'a';
13088                   *obufp++ = 'b';
13089                   *obufp++ = 's';
13090                 }
13091             }
13092           /* Fall through.  */
13093           goto case_S;
13094         case 'S':
13095           if (l == 0 && len == 1)
13096             {
13097 case_S:
13098               if (intel_syntax)
13099                 break;
13100               if (sizeflag & SUFFIX_ALWAYS)
13101                 {
13102                   if (rex & REX_W)
13103                     *obufp++ = 'q';
13104                   else
13105                     {
13106                       if (sizeflag & DFLAG)
13107                         *obufp++ = 'l';
13108                       else
13109                         *obufp++ = 'w';
13110                       used_prefixes |= (prefixes & PREFIX_DATA);
13111                     }
13112                 }
13113             }
13114           else
13115             {
13116               if (l != 1
13117                   || len != 2
13118                   || last[0] != 'L')
13119                 {
13120                   SAVE_LAST (*p);
13121                   break;
13122                 }
13123
13124               if (address_mode == mode_64bit
13125                   && !(prefixes & PREFIX_ADDR))
13126                 {
13127                   *obufp++ = 'a';
13128                   *obufp++ = 'b';
13129                   *obufp++ = 's';
13130                 }
13131
13132               goto case_S;
13133             }
13134           break;
13135         case 'X':
13136           if (l != 0 || len != 1)
13137             {
13138               SAVE_LAST (*p);
13139               break;
13140             }
13141           if (need_vex && vex.prefix)
13142             {
13143               if (vex.prefix == DATA_PREFIX_OPCODE)
13144                 *obufp++ = 'd';
13145               else
13146                 *obufp++ = 's';
13147             }
13148           else
13149             {
13150               if (prefixes & PREFIX_DATA)
13151                 *obufp++ = 'd';
13152               else
13153                 *obufp++ = 's';
13154               used_prefixes |= (prefixes & PREFIX_DATA);
13155             }
13156           break;
13157         case 'Y':
13158           if (l == 0 && len == 1)
13159             abort ();
13160           else
13161             {
13162               if (l != 1 || len != 2 || last[0] != 'X')
13163                 {
13164                   SAVE_LAST (*p);
13165                   break;
13166                 }
13167               if (!need_vex)
13168                 abort ();
13169               if (intel_syntax
13170                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13171                 break;
13172               switch (vex.length)
13173                 {
13174                 case 128:
13175                   *obufp++ = 'x';
13176                   break;
13177                 case 256:
13178                   *obufp++ = 'y';
13179                   break;
13180                 case 512:
13181                   if (!vex.evex)
13182                 default:
13183                     abort ();
13184                 }
13185             }
13186           break;
13187         case 'W':
13188           if (l == 0 && len == 1)
13189             {
13190               /* operand size flag for cwtl, cbtw */
13191               USED_REX (REX_W);
13192               if (rex & REX_W)
13193                 {
13194                   if (intel_syntax)
13195                     *obufp++ = 'd';
13196                   else
13197                     *obufp++ = 'l';
13198                 }
13199               else if (sizeflag & DFLAG)
13200                 *obufp++ = 'w';
13201               else
13202                 *obufp++ = 'b';
13203               if (!(rex & REX_W))
13204                 used_prefixes |= (prefixes & PREFIX_DATA);
13205             }
13206           else
13207             {
13208               if (l != 1
13209                   || len != 2
13210                   || (last[0] != 'X'
13211                       && last[0] != 'L'))
13212                 {
13213                   SAVE_LAST (*p);
13214                   break;
13215                 }
13216               if (!need_vex)
13217                 abort ();
13218               if (last[0] == 'X')
13219                 *obufp++ = vex.w ? 'd': 's';
13220               else
13221                 *obufp++ = vex.w ? 'q': 'd';
13222             }
13223           break;
13224         case '^':
13225           if (intel_syntax)
13226             break;
13227           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13228             {
13229               if (sizeflag & DFLAG)
13230                 *obufp++ = 'l';
13231               else
13232                 *obufp++ = 'w';
13233               used_prefixes |= (prefixes & PREFIX_DATA);
13234             }
13235           break;
13236         case '@':
13237           if (intel_syntax)
13238             break;
13239           if (address_mode == mode_64bit
13240               && (isa64 == intel64
13241                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13242               *obufp++ = 'q';
13243           else if ((prefixes & PREFIX_DATA))
13244             {
13245               if (!(sizeflag & DFLAG))
13246                 *obufp++ = 'w';
13247               used_prefixes |= (prefixes & PREFIX_DATA);
13248             }
13249           break;
13250         }
13251       alt = 0;
13252     }
13253   *obufp = 0;
13254   mnemonicendp = obufp;
13255   return 0;
13256 }
13257
13258 static void
13259 oappend (const char *s)
13260 {
13261   obufp = stpcpy (obufp, s);
13262 }
13263
13264 static void
13265 append_seg (void)
13266 {
13267   /* Only print the active segment register.  */
13268   if (!active_seg_prefix)
13269     return;
13270
13271   used_prefixes |= active_seg_prefix;
13272   switch (active_seg_prefix)
13273     {
13274     case PREFIX_CS:
13275       oappend_maybe_intel ("%cs:");
13276       break;
13277     case PREFIX_DS:
13278       oappend_maybe_intel ("%ds:");
13279       break;
13280     case PREFIX_SS:
13281       oappend_maybe_intel ("%ss:");
13282       break;
13283     case PREFIX_ES:
13284       oappend_maybe_intel ("%es:");
13285       break;
13286     case PREFIX_FS:
13287       oappend_maybe_intel ("%fs:");
13288       break;
13289     case PREFIX_GS:
13290       oappend_maybe_intel ("%gs:");
13291       break;
13292     default:
13293       break;
13294     }
13295 }
13296
13297 static void
13298 OP_indirE (int bytemode, int sizeflag)
13299 {
13300   if (!intel_syntax)
13301     oappend ("*");
13302   OP_E (bytemode, sizeflag);
13303 }
13304
13305 static void
13306 print_operand_value (char *buf, int hex, bfd_vma disp)
13307 {
13308   if (address_mode == mode_64bit)
13309     {
13310       if (hex)
13311         {
13312           char tmp[30];
13313           int i;
13314           buf[0] = '0';
13315           buf[1] = 'x';
13316           sprintf_vma (tmp, disp);
13317           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13318           strcpy (buf + 2, tmp + i);
13319         }
13320       else
13321         {
13322           bfd_signed_vma v = disp;
13323           char tmp[30];
13324           int i;
13325           if (v < 0)
13326             {
13327               *(buf++) = '-';
13328               v = -disp;
13329               /* Check for possible overflow on 0x8000000000000000.  */
13330               if (v < 0)
13331                 {
13332                   strcpy (buf, "9223372036854775808");
13333                   return;
13334                 }
13335             }
13336           if (!v)
13337             {
13338               strcpy (buf, "0");
13339               return;
13340             }
13341
13342           i = 0;
13343           tmp[29] = 0;
13344           while (v)
13345             {
13346               tmp[28 - i] = (v % 10) + '0';
13347               v /= 10;
13348               i++;
13349             }
13350           strcpy (buf, tmp + 29 - i);
13351         }
13352     }
13353   else
13354     {
13355       if (hex)
13356         sprintf (buf, "0x%x", (unsigned int) disp);
13357       else
13358         sprintf (buf, "%d", (int) disp);
13359     }
13360 }
13361
13362 /* Put DISP in BUF as signed hex number.  */
13363
13364 static void
13365 print_displacement (char *buf, bfd_vma disp)
13366 {
13367   bfd_signed_vma val = disp;
13368   char tmp[30];
13369   int i, j = 0;
13370
13371   if (val < 0)
13372     {
13373       buf[j++] = '-';
13374       val = -disp;
13375
13376       /* Check for possible overflow.  */
13377       if (val < 0)
13378         {
13379           switch (address_mode)
13380             {
13381             case mode_64bit:
13382               strcpy (buf + j, "0x8000000000000000");
13383               break;
13384             case mode_32bit:
13385               strcpy (buf + j, "0x80000000");
13386               break;
13387             case mode_16bit:
13388               strcpy (buf + j, "0x8000");
13389               break;
13390             }
13391           return;
13392         }
13393     }
13394
13395   buf[j++] = '0';
13396   buf[j++] = 'x';
13397
13398   sprintf_vma (tmp, (bfd_vma) val);
13399   for (i = 0; tmp[i] == '0'; i++)
13400     continue;
13401   if (tmp[i] == '\0')
13402     i--;
13403   strcpy (buf + j, tmp + i);
13404 }
13405
13406 static void
13407 intel_operand_size (int bytemode, int sizeflag)
13408 {
13409   if (vex.evex
13410       && vex.b
13411       && (bytemode == x_mode
13412           || bytemode == evex_half_bcst_xmmq_mode))
13413     {
13414       if (vex.w)
13415         oappend ("QWORD PTR ");
13416       else
13417         oappend ("DWORD PTR ");
13418       return;
13419     }
13420   switch (bytemode)
13421     {
13422     case b_mode:
13423     case b_swap_mode:
13424     case dqb_mode:
13425     case db_mode:
13426       oappend ("BYTE PTR ");
13427       break;
13428     case w_mode:
13429     case dw_mode:
13430     case dqw_mode:
13431       oappend ("WORD PTR ");
13432       break;
13433     case indir_v_mode:
13434       if (address_mode == mode_64bit && isa64 == intel64)
13435         {
13436           oappend ("QWORD PTR ");
13437           break;
13438         }
13439       /* Fall through.  */
13440     case stack_v_mode:
13441       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13442         {
13443           oappend ("QWORD PTR ");
13444           break;
13445         }
13446       /* Fall through.  */
13447     case v_mode:
13448     case v_swap_mode:
13449     case dq_mode:
13450       USED_REX (REX_W);
13451       if (rex & REX_W)
13452         oappend ("QWORD PTR ");
13453       else
13454         {
13455           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13456             oappend ("DWORD PTR ");
13457           else
13458             oappend ("WORD PTR ");
13459           used_prefixes |= (prefixes & PREFIX_DATA);
13460         }
13461       break;
13462     case z_mode:
13463       if ((rex & REX_W) || (sizeflag & DFLAG))
13464         *obufp++ = 'D';
13465       oappend ("WORD PTR ");
13466       if (!(rex & REX_W))
13467         used_prefixes |= (prefixes & PREFIX_DATA);
13468       break;
13469     case a_mode:
13470       if (sizeflag & DFLAG)
13471         oappend ("QWORD PTR ");
13472       else
13473         oappend ("DWORD PTR ");
13474       used_prefixes |= (prefixes & PREFIX_DATA);
13475       break;
13476     case d_mode:
13477     case d_scalar_mode:
13478     case d_scalar_swap_mode:
13479     case d_swap_mode:
13480     case dqd_mode:
13481       oappend ("DWORD PTR ");
13482       break;
13483     case q_mode:
13484     case q_scalar_mode:
13485     case q_scalar_swap_mode:
13486     case q_swap_mode:
13487       oappend ("QWORD PTR ");
13488       break;
13489     case m_mode:
13490       if (address_mode == mode_64bit)
13491         oappend ("QWORD PTR ");
13492       else
13493         oappend ("DWORD PTR ");
13494       break;
13495     case f_mode:
13496       if (sizeflag & DFLAG)
13497         oappend ("FWORD PTR ");
13498       else
13499         oappend ("DWORD PTR ");
13500       used_prefixes |= (prefixes & PREFIX_DATA);
13501       break;
13502     case t_mode:
13503       oappend ("TBYTE PTR ");
13504       break;
13505     case x_mode:
13506     case x_swap_mode:
13507     case evex_x_gscat_mode:
13508     case evex_x_nobcst_mode:
13509     case b_scalar_mode:
13510     case w_scalar_mode:
13511       if (need_vex)
13512         {
13513           switch (vex.length)
13514             {
13515             case 128:
13516               oappend ("XMMWORD PTR ");
13517               break;
13518             case 256:
13519               oappend ("YMMWORD PTR ");
13520               break;
13521             case 512:
13522               oappend ("ZMMWORD PTR ");
13523               break;
13524             default:
13525               abort ();
13526             }
13527         }
13528       else
13529         oappend ("XMMWORD PTR ");
13530       break;
13531     case xmm_mode:
13532       oappend ("XMMWORD PTR ");
13533       break;
13534     case ymm_mode:
13535       oappend ("YMMWORD PTR ");
13536       break;
13537     case xmmq_mode:
13538     case evex_half_bcst_xmmq_mode:
13539       if (!need_vex)
13540         abort ();
13541
13542       switch (vex.length)
13543         {
13544         case 128:
13545           oappend ("QWORD PTR ");
13546           break;
13547         case 256:
13548           oappend ("XMMWORD PTR ");
13549           break;
13550         case 512:
13551           oappend ("YMMWORD PTR ");
13552           break;
13553         default:
13554           abort ();
13555         }
13556       break;
13557     case xmm_mb_mode:
13558       if (!need_vex)
13559         abort ();
13560
13561       switch (vex.length)
13562         {
13563         case 128:
13564         case 256:
13565         case 512:
13566           oappend ("BYTE PTR ");
13567           break;
13568         default:
13569           abort ();
13570         }
13571       break;
13572     case xmm_mw_mode:
13573       if (!need_vex)
13574         abort ();
13575
13576       switch (vex.length)
13577         {
13578         case 128:
13579         case 256:
13580         case 512:
13581           oappend ("WORD PTR ");
13582           break;
13583         default:
13584           abort ();
13585         }
13586       break;
13587     case xmm_md_mode:
13588       if (!need_vex)
13589         abort ();
13590
13591       switch (vex.length)
13592         {
13593         case 128:
13594         case 256:
13595         case 512:
13596           oappend ("DWORD PTR ");
13597           break;
13598         default:
13599           abort ();
13600         }
13601       break;
13602     case xmm_mq_mode:
13603       if (!need_vex)
13604         abort ();
13605
13606       switch (vex.length)
13607         {
13608         case 128:
13609         case 256:
13610         case 512:
13611           oappend ("QWORD PTR ");
13612           break;
13613         default:
13614           abort ();
13615         }
13616       break;
13617     case xmmdw_mode:
13618       if (!need_vex)
13619         abort ();
13620
13621       switch (vex.length)
13622         {
13623         case 128:
13624           oappend ("WORD PTR ");
13625           break;
13626         case 256:
13627           oappend ("DWORD PTR ");
13628           break;
13629         case 512:
13630           oappend ("QWORD PTR ");
13631           break;
13632         default:
13633           abort ();
13634         }
13635       break;
13636     case xmmqd_mode:
13637       if (!need_vex)
13638         abort ();
13639
13640       switch (vex.length)
13641         {
13642         case 128:
13643           oappend ("DWORD PTR ");
13644           break;
13645         case 256:
13646           oappend ("QWORD PTR ");
13647           break;
13648         case 512:
13649           oappend ("XMMWORD PTR ");
13650           break;
13651         default:
13652           abort ();
13653         }
13654       break;
13655     case ymmq_mode:
13656       if (!need_vex)
13657         abort ();
13658
13659       switch (vex.length)
13660         {
13661         case 128:
13662           oappend ("QWORD PTR ");
13663           break;
13664         case 256:
13665           oappend ("YMMWORD PTR ");
13666           break;
13667         case 512:
13668           oappend ("ZMMWORD PTR ");
13669           break;
13670         default:
13671           abort ();
13672         }
13673       break;
13674     case ymmxmm_mode:
13675       if (!need_vex)
13676         abort ();
13677
13678       switch (vex.length)
13679         {
13680         case 128:
13681         case 256:
13682           oappend ("XMMWORD PTR ");
13683           break;
13684         default:
13685           abort ();
13686         }
13687       break;
13688     case o_mode:
13689       oappend ("OWORD PTR ");
13690       break;
13691     case xmm_mdq_mode:
13692     case vex_w_dq_mode:
13693     case vex_scalar_w_dq_mode:
13694       if (!need_vex)
13695         abort ();
13696
13697       if (vex.w)
13698         oappend ("QWORD PTR ");
13699       else
13700         oappend ("DWORD PTR ");
13701       break;
13702     case vex_vsib_d_w_dq_mode:
13703     case vex_vsib_q_w_dq_mode:
13704       if (!need_vex)
13705         abort ();
13706
13707       if (!vex.evex)
13708         {
13709           if (vex.w)
13710             oappend ("QWORD PTR ");
13711           else
13712             oappend ("DWORD PTR ");
13713         }
13714       else
13715         {
13716           switch (vex.length)
13717             {
13718             case 128:
13719               oappend ("XMMWORD PTR ");
13720               break;
13721             case 256:
13722               oappend ("YMMWORD PTR ");
13723               break;
13724             case 512:
13725               oappend ("ZMMWORD PTR ");
13726               break;
13727             default:
13728               abort ();
13729             }
13730         }
13731       break;
13732     case vex_vsib_q_w_d_mode:
13733     case vex_vsib_d_w_d_mode:
13734       if (!need_vex || !vex.evex)
13735         abort ();
13736
13737       switch (vex.length)
13738         {
13739         case 128:
13740           oappend ("QWORD PTR ");
13741           break;
13742         case 256:
13743           oappend ("XMMWORD PTR ");
13744           break;
13745         case 512:
13746           oappend ("YMMWORD PTR ");
13747           break;
13748         default:
13749           abort ();
13750         }
13751
13752       break;
13753     case mask_bd_mode:
13754       if (!need_vex || vex.length != 128)
13755         abort ();
13756       if (vex.w)
13757         oappend ("DWORD PTR ");
13758       else
13759         oappend ("BYTE PTR ");
13760       break;
13761     case mask_mode:
13762       if (!need_vex)
13763         abort ();
13764       if (vex.w)
13765         oappend ("QWORD PTR ");
13766       else
13767         oappend ("WORD PTR ");
13768       break;
13769     case v_bnd_mode:
13770     case v_bndmk_mode:
13771     default:
13772       break;
13773     }
13774 }
13775
13776 static void
13777 OP_E_register (int bytemode, int sizeflag)
13778 {
13779   int reg = modrm.rm;
13780   const char **names;
13781
13782   USED_REX (REX_B);
13783   if ((rex & REX_B))
13784     reg += 8;
13785
13786   if ((sizeflag & SUFFIX_ALWAYS)
13787       && (bytemode == b_swap_mode
13788           || bytemode == bnd_swap_mode
13789           || bytemode == v_swap_mode))
13790     swap_operand ();
13791
13792   switch (bytemode)
13793     {
13794     case b_mode:
13795     case b_swap_mode:
13796       USED_REX (0);
13797       if (rex)
13798         names = names8rex;
13799       else
13800         names = names8;
13801       break;
13802     case w_mode:
13803       names = names16;
13804       break;
13805     case d_mode:
13806     case dw_mode:
13807     case db_mode:
13808       names = names32;
13809       break;
13810     case q_mode:
13811       names = names64;
13812       break;
13813     case m_mode:
13814     case v_bnd_mode:
13815       names = address_mode == mode_64bit ? names64 : names32;
13816       break;
13817     case bnd_mode:
13818     case bnd_swap_mode:
13819       if (reg > 0x3)
13820         {
13821           oappend ("(bad)");
13822           return;
13823         }
13824       names = names_bnd;
13825       break;
13826     case indir_v_mode:
13827       if (address_mode == mode_64bit && isa64 == intel64)
13828         {
13829           names = names64;
13830           break;
13831         }
13832       /* Fall through.  */
13833     case stack_v_mode:
13834       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13835         {
13836           names = names64;
13837           break;
13838         }
13839       bytemode = v_mode;
13840       /* Fall through.  */
13841     case v_mode:
13842     case v_swap_mode:
13843     case dq_mode:
13844     case dqb_mode:
13845     case dqd_mode:
13846     case dqw_mode:
13847       USED_REX (REX_W);
13848       if (rex & REX_W)
13849         names = names64;
13850       else
13851         {
13852           if ((sizeflag & DFLAG)
13853               || (bytemode != v_mode
13854                   && bytemode != v_swap_mode))
13855             names = names32;
13856           else
13857             names = names16;
13858           used_prefixes |= (prefixes & PREFIX_DATA);
13859         }
13860       break;
13861     case va_mode:
13862       names = (address_mode == mode_64bit
13863                ? names64 : names32);
13864       if (!(prefixes & PREFIX_ADDR))
13865         names = (address_mode == mode_16bit
13866                      ? names16 : names);
13867       else
13868         {
13869           /* Remove "addr16/addr32".  */
13870           all_prefixes[last_addr_prefix] = 0;
13871           names = (address_mode != mode_32bit
13872                        ? names32 : names16);
13873           used_prefixes |= PREFIX_ADDR;
13874         }
13875       break;
13876     case mask_bd_mode:
13877     case mask_mode:
13878       if (reg > 0x7)
13879         {
13880           oappend ("(bad)");
13881           return;
13882         }
13883       names = names_mask;
13884       break;
13885     case 0:
13886       return;
13887     default:
13888       oappend (INTERNAL_DISASSEMBLER_ERROR);
13889       return;
13890     }
13891   oappend (names[reg]);
13892 }
13893
13894 static void
13895 OP_E_memory (int bytemode, int sizeflag)
13896 {
13897   bfd_vma disp = 0;
13898   int add = (rex & REX_B) ? 8 : 0;
13899   int riprel = 0;
13900   int shift;
13901
13902   if (vex.evex)
13903     {
13904       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13905       if (vex.b
13906           && bytemode != x_mode
13907           && bytemode != xmmq_mode
13908           && bytemode != evex_half_bcst_xmmq_mode)
13909         {
13910           BadOp ();
13911           return;
13912         }
13913       switch (bytemode)
13914         {
13915         case dqw_mode:
13916         case dw_mode:
13917           shift = 1;
13918           break;
13919         case dqb_mode:
13920         case db_mode:
13921           shift = 0;
13922           break;
13923         case dq_mode:
13924           if (address_mode != mode_64bit)
13925             {
13926               shift = 2;
13927               break;
13928             }
13929             /* fall through */
13930         case vex_vsib_d_w_dq_mode:
13931         case vex_vsib_d_w_d_mode:
13932         case vex_vsib_q_w_dq_mode:
13933         case vex_vsib_q_w_d_mode:
13934         case evex_x_gscat_mode:
13935         case xmm_mdq_mode:
13936           shift = vex.w ? 3 : 2;
13937           break;
13938         case x_mode:
13939         case evex_half_bcst_xmmq_mode:
13940         case xmmq_mode:
13941           if (vex.b)
13942             {
13943               shift = vex.w ? 3 : 2;
13944               break;
13945             }
13946           /* Fall through.  */
13947         case xmmqd_mode:
13948         case xmmdw_mode:
13949         case ymmq_mode:
13950         case evex_x_nobcst_mode:
13951         case x_swap_mode:
13952           switch (vex.length)
13953             {
13954             case 128:
13955               shift = 4;
13956               break;
13957             case 256:
13958               shift = 5;
13959               break;
13960             case 512:
13961               shift = 6;
13962               break;
13963             default:
13964               abort ();
13965             }
13966           break;
13967         case ymm_mode:
13968           shift = 5;
13969           break;
13970         case xmm_mode:
13971           shift = 4;
13972           break;
13973         case xmm_mq_mode:
13974         case q_mode:
13975         case q_scalar_mode:
13976         case q_swap_mode:
13977         case q_scalar_swap_mode:
13978           shift = 3;
13979           break;
13980         case dqd_mode:
13981         case xmm_md_mode:
13982         case d_mode:
13983         case d_scalar_mode:
13984         case d_swap_mode:
13985         case d_scalar_swap_mode:
13986           shift = 2;
13987           break;
13988         case w_scalar_mode:
13989         case xmm_mw_mode:
13990           shift = 1;
13991           break;
13992         case b_scalar_mode:
13993         case xmm_mb_mode:
13994           shift = 0;
13995           break;
13996         default:
13997           abort ();
13998         }
13999       /* Make necessary corrections to shift for modes that need it.
14000          For these modes we currently have shift 4, 5 or 6 depending on
14001          vex.length (it corresponds to xmmword, ymmword or zmmword
14002          operand).  We might want to make it 3, 4 or 5 (e.g. for
14003          xmmq_mode).  In case of broadcast enabled the corrections
14004          aren't needed, as element size is always 32 or 64 bits.  */
14005       if (!vex.b
14006           && (bytemode == xmmq_mode
14007               || bytemode == evex_half_bcst_xmmq_mode))
14008         shift -= 1;
14009       else if (bytemode == xmmqd_mode)
14010         shift -= 2;
14011       else if (bytemode == xmmdw_mode)
14012         shift -= 3;
14013       else if (bytemode == ymmq_mode && vex.length == 128)
14014         shift -= 1;
14015     }
14016   else
14017     shift = 0;
14018
14019   USED_REX (REX_B);
14020   if (intel_syntax)
14021     intel_operand_size (bytemode, sizeflag);
14022   append_seg ();
14023
14024   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14025     {
14026       /* 32/64 bit address mode */
14027       int havedisp;
14028       int havesib;
14029       int havebase;
14030       int haveindex;
14031       int needindex;
14032       int needaddr32;
14033       int base, rbase;
14034       int vindex = 0;
14035       int scale = 0;
14036       int addr32flag = !((sizeflag & AFLAG)
14037                          || bytemode == v_bnd_mode
14038                          || bytemode == v_bndmk_mode
14039                          || bytemode == bnd_mode
14040                          || bytemode == bnd_swap_mode);
14041       const char **indexes64 = names64;
14042       const char **indexes32 = names32;
14043
14044       havesib = 0;
14045       havebase = 1;
14046       haveindex = 0;
14047       base = modrm.rm;
14048
14049       if (base == 4)
14050         {
14051           havesib = 1;
14052           vindex = sib.index;
14053           USED_REX (REX_X);
14054           if (rex & REX_X)
14055             vindex += 8;
14056           switch (bytemode)
14057             {
14058             case vex_vsib_d_w_dq_mode:
14059             case vex_vsib_d_w_d_mode:
14060             case vex_vsib_q_w_dq_mode:
14061             case vex_vsib_q_w_d_mode:
14062               if (!need_vex)
14063                 abort ();
14064               if (vex.evex)
14065                 {
14066                   if (!vex.v)
14067                     vindex += 16;
14068                 }
14069
14070               haveindex = 1;
14071               switch (vex.length)
14072                 {
14073                 case 128:
14074                   indexes64 = indexes32 = names_xmm;
14075                   break;
14076                 case 256:
14077                   if (!vex.w
14078                       || bytemode == vex_vsib_q_w_dq_mode
14079                       || bytemode == vex_vsib_q_w_d_mode)
14080                     indexes64 = indexes32 = names_ymm;
14081                   else
14082                     indexes64 = indexes32 = names_xmm;
14083                   break;
14084                 case 512:
14085                   if (!vex.w
14086                       || bytemode == vex_vsib_q_w_dq_mode
14087                       || bytemode == vex_vsib_q_w_d_mode)
14088                     indexes64 = indexes32 = names_zmm;
14089                   else
14090                     indexes64 = indexes32 = names_ymm;
14091                   break;
14092                 default:
14093                   abort ();
14094                 }
14095               break;
14096             default:
14097               haveindex = vindex != 4;
14098               break;
14099             }
14100           scale = sib.scale;
14101           base = sib.base;
14102           codep++;
14103         }
14104       rbase = base + add;
14105
14106       switch (modrm.mod)
14107         {
14108         case 0:
14109           if (base == 5)
14110             {
14111               havebase = 0;
14112               if (address_mode == mode_64bit && !havesib)
14113                 riprel = 1;
14114               disp = get32s ();
14115               if (riprel && bytemode == v_bndmk_mode)
14116                 {
14117                   oappend ("(bad)");
14118                   return;
14119                 }
14120             }
14121           break;
14122         case 1:
14123           FETCH_DATA (the_info, codep + 1);
14124           disp = *codep++;
14125           if ((disp & 0x80) != 0)
14126             disp -= 0x100;
14127           if (vex.evex && shift > 0)
14128             disp <<= shift;
14129           break;
14130         case 2:
14131           disp = get32s ();
14132           break;
14133         }
14134
14135       needindex = 0;
14136       needaddr32 = 0;
14137       if (havesib
14138           && !havebase
14139           && !haveindex
14140           && address_mode != mode_16bit)
14141         {
14142           if (address_mode == mode_64bit)
14143             {
14144               /* Display eiz instead of addr32.  */
14145               needindex = addr32flag;
14146               needaddr32 = 1;
14147             }
14148           else
14149             {
14150               /* In 32-bit mode, we need index register to tell [offset]
14151                  from [eiz*1 + offset].  */
14152               needindex = 1;
14153             }
14154         }
14155
14156       havedisp = (havebase
14157                   || needindex
14158                   || (havesib && (haveindex || scale != 0)));
14159
14160       if (!intel_syntax)
14161         if (modrm.mod != 0 || base == 5)
14162           {
14163             if (havedisp || riprel)
14164               print_displacement (scratchbuf, disp);
14165             else
14166               print_operand_value (scratchbuf, 1, disp);
14167             oappend (scratchbuf);
14168             if (riprel)
14169               {
14170                 set_op (disp, 1);
14171                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14172               }
14173           }
14174
14175       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14176           && (bytemode != v_bnd_mode)
14177           && (bytemode != v_bndmk_mode)
14178           && (bytemode != bnd_mode)
14179           && (bytemode != bnd_swap_mode))
14180         used_prefixes |= PREFIX_ADDR;
14181
14182       if (havedisp || (intel_syntax && riprel))
14183         {
14184           *obufp++ = open_char;
14185           if (intel_syntax && riprel)
14186             {
14187               set_op (disp, 1);
14188               oappend (!addr32flag ? "rip" : "eip");
14189             }
14190           *obufp = '\0';
14191           if (havebase)
14192             oappend (address_mode == mode_64bit && !addr32flag
14193                      ? names64[rbase] : names32[rbase]);
14194           if (havesib)
14195             {
14196               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14197                  print index to tell base + index from base.  */
14198               if (scale != 0
14199                   || needindex
14200                   || haveindex
14201                   || (havebase && base != ESP_REG_NUM))
14202                 {
14203                   if (!intel_syntax || havebase)
14204                     {
14205                       *obufp++ = separator_char;
14206                       *obufp = '\0';
14207                     }
14208                   if (haveindex)
14209                     oappend (address_mode == mode_64bit && !addr32flag
14210                              ? indexes64[vindex] : indexes32[vindex]);
14211                   else
14212                     oappend (address_mode == mode_64bit && !addr32flag
14213                              ? index64 : index32);
14214
14215                   *obufp++ = scale_char;
14216                   *obufp = '\0';
14217                   sprintf (scratchbuf, "%d", 1 << scale);
14218                   oappend (scratchbuf);
14219                 }
14220             }
14221           if (intel_syntax
14222               && (disp || modrm.mod != 0 || base == 5))
14223             {
14224               if (!havedisp || (bfd_signed_vma) disp >= 0)
14225                 {
14226                   *obufp++ = '+';
14227                   *obufp = '\0';
14228                 }
14229               else if (modrm.mod != 1 && disp != -disp)
14230                 {
14231                   *obufp++ = '-';
14232                   *obufp = '\0';
14233                   disp = - (bfd_signed_vma) disp;
14234                 }
14235
14236               if (havedisp)
14237                 print_displacement (scratchbuf, disp);
14238               else
14239                 print_operand_value (scratchbuf, 1, disp);
14240               oappend (scratchbuf);
14241             }
14242
14243           *obufp++ = close_char;
14244           *obufp = '\0';
14245         }
14246       else if (intel_syntax)
14247         {
14248           if (modrm.mod != 0 || base == 5)
14249             {
14250               if (!active_seg_prefix)
14251                 {
14252                   oappend (names_seg[ds_reg - es_reg]);
14253                   oappend (":");
14254                 }
14255               print_operand_value (scratchbuf, 1, disp);
14256               oappend (scratchbuf);
14257             }
14258         }
14259     }
14260   else
14261     {
14262       /* 16 bit address mode */
14263       used_prefixes |= prefixes & PREFIX_ADDR;
14264       switch (modrm.mod)
14265         {
14266         case 0:
14267           if (modrm.rm == 6)
14268             {
14269               disp = get16 ();
14270               if ((disp & 0x8000) != 0)
14271                 disp -= 0x10000;
14272             }
14273           break;
14274         case 1:
14275           FETCH_DATA (the_info, codep + 1);
14276           disp = *codep++;
14277           if ((disp & 0x80) != 0)
14278             disp -= 0x100;
14279           if (vex.evex && shift > 0)
14280             disp <<= shift;
14281           break;
14282         case 2:
14283           disp = get16 ();
14284           if ((disp & 0x8000) != 0)
14285             disp -= 0x10000;
14286           break;
14287         }
14288
14289       if (!intel_syntax)
14290         if (modrm.mod != 0 || modrm.rm == 6)
14291           {
14292             print_displacement (scratchbuf, disp);
14293             oappend (scratchbuf);
14294           }
14295
14296       if (modrm.mod != 0 || modrm.rm != 6)
14297         {
14298           *obufp++ = open_char;
14299           *obufp = '\0';
14300           oappend (index16[modrm.rm]);
14301           if (intel_syntax
14302               && (disp || modrm.mod != 0 || modrm.rm == 6))
14303             {
14304               if ((bfd_signed_vma) disp >= 0)
14305                 {
14306                   *obufp++ = '+';
14307                   *obufp = '\0';
14308                 }
14309               else if (modrm.mod != 1)
14310                 {
14311                   *obufp++ = '-';
14312                   *obufp = '\0';
14313                   disp = - (bfd_signed_vma) disp;
14314                 }
14315
14316               print_displacement (scratchbuf, disp);
14317               oappend (scratchbuf);
14318             }
14319
14320           *obufp++ = close_char;
14321           *obufp = '\0';
14322         }
14323       else if (intel_syntax)
14324         {
14325           if (!active_seg_prefix)
14326             {
14327               oappend (names_seg[ds_reg - es_reg]);
14328               oappend (":");
14329             }
14330           print_operand_value (scratchbuf, 1, disp & 0xffff);
14331           oappend (scratchbuf);
14332         }
14333     }
14334   if (vex.evex && vex.b
14335       && (bytemode == x_mode
14336           || bytemode == xmmq_mode
14337           || bytemode == evex_half_bcst_xmmq_mode))
14338     {
14339       if (vex.w
14340           || bytemode == xmmq_mode
14341           || bytemode == evex_half_bcst_xmmq_mode)
14342         {
14343           switch (vex.length)
14344             {
14345             case 128:
14346               oappend ("{1to2}");
14347               break;
14348             case 256:
14349               oappend ("{1to4}");
14350               break;
14351             case 512:
14352               oappend ("{1to8}");
14353               break;
14354             default:
14355               abort ();
14356             }
14357         }
14358       else
14359         {
14360           switch (vex.length)
14361             {
14362             case 128:
14363               oappend ("{1to4}");
14364               break;
14365             case 256:
14366               oappend ("{1to8}");
14367               break;
14368             case 512:
14369               oappend ("{1to16}");
14370               break;
14371             default:
14372               abort ();
14373             }
14374         }
14375     }
14376 }
14377
14378 static void
14379 OP_E (int bytemode, int sizeflag)
14380 {
14381   /* Skip mod/rm byte.  */
14382   MODRM_CHECK;
14383   codep++;
14384
14385   if (modrm.mod == 3)
14386     OP_E_register (bytemode, sizeflag);
14387   else
14388     OP_E_memory (bytemode, sizeflag);
14389 }
14390
14391 static void
14392 OP_G (int bytemode, int sizeflag)
14393 {
14394   int add = 0;
14395   const char **names;
14396   USED_REX (REX_R);
14397   if (rex & REX_R)
14398     add += 8;
14399   switch (bytemode)
14400     {
14401     case b_mode:
14402       USED_REX (0);
14403       if (rex)
14404         oappend (names8rex[modrm.reg + add]);
14405       else
14406         oappend (names8[modrm.reg + add]);
14407       break;
14408     case w_mode:
14409       oappend (names16[modrm.reg + add]);
14410       break;
14411     case d_mode:
14412     case db_mode:
14413     case dw_mode:
14414       oappend (names32[modrm.reg + add]);
14415       break;
14416     case q_mode:
14417       oappend (names64[modrm.reg + add]);
14418       break;
14419     case bnd_mode:
14420       if (modrm.reg > 0x3)
14421         {
14422           oappend ("(bad)");
14423           return;
14424         }
14425       oappend (names_bnd[modrm.reg]);
14426       break;
14427     case v_mode:
14428     case dq_mode:
14429     case dqb_mode:
14430     case dqd_mode:
14431     case dqw_mode:
14432       USED_REX (REX_W);
14433       if (rex & REX_W)
14434         oappend (names64[modrm.reg + add]);
14435       else
14436         {
14437           if ((sizeflag & DFLAG) || bytemode != v_mode)
14438             oappend (names32[modrm.reg + add]);
14439           else
14440             oappend (names16[modrm.reg + add]);
14441           used_prefixes |= (prefixes & PREFIX_DATA);
14442         }
14443       break;
14444     case va_mode:
14445       names = (address_mode == mode_64bit
14446                ? names64 : names32);
14447       if (!(prefixes & PREFIX_ADDR))
14448         {
14449           if (address_mode == mode_16bit)
14450             names = names16;
14451         }
14452       else
14453         {
14454           /* Remove "addr16/addr32".  */
14455           all_prefixes[last_addr_prefix] = 0;
14456           names = (address_mode != mode_32bit
14457                        ? names32 : names16);
14458           used_prefixes |= PREFIX_ADDR;
14459         }
14460       oappend (names[modrm.reg + add]);
14461       break;
14462     case m_mode:
14463       if (address_mode == mode_64bit)
14464         oappend (names64[modrm.reg + add]);
14465       else
14466         oappend (names32[modrm.reg + add]);
14467       break;
14468     case mask_bd_mode:
14469     case mask_mode:
14470       if ((modrm.reg + add) > 0x7)
14471         {
14472           oappend ("(bad)");
14473           return;
14474         }
14475       oappend (names_mask[modrm.reg + add]);
14476       break;
14477     default:
14478       oappend (INTERNAL_DISASSEMBLER_ERROR);
14479       break;
14480     }
14481 }
14482
14483 static bfd_vma
14484 get64 (void)
14485 {
14486   bfd_vma x;
14487 #ifdef BFD64
14488   unsigned int a;
14489   unsigned int b;
14490
14491   FETCH_DATA (the_info, codep + 8);
14492   a = *codep++ & 0xff;
14493   a |= (*codep++ & 0xff) << 8;
14494   a |= (*codep++ & 0xff) << 16;
14495   a |= (*codep++ & 0xffu) << 24;
14496   b = *codep++ & 0xff;
14497   b |= (*codep++ & 0xff) << 8;
14498   b |= (*codep++ & 0xff) << 16;
14499   b |= (*codep++ & 0xffu) << 24;
14500   x = a + ((bfd_vma) b << 32);
14501 #else
14502   abort ();
14503   x = 0;
14504 #endif
14505   return x;
14506 }
14507
14508 static bfd_signed_vma
14509 get32 (void)
14510 {
14511   bfd_signed_vma x = 0;
14512
14513   FETCH_DATA (the_info, codep + 4);
14514   x = *codep++ & (bfd_signed_vma) 0xff;
14515   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14516   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14517   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14518   return x;
14519 }
14520
14521 static bfd_signed_vma
14522 get32s (void)
14523 {
14524   bfd_signed_vma x = 0;
14525
14526   FETCH_DATA (the_info, codep + 4);
14527   x = *codep++ & (bfd_signed_vma) 0xff;
14528   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14529   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14530   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14531
14532   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14533
14534   return x;
14535 }
14536
14537 static int
14538 get16 (void)
14539 {
14540   int x = 0;
14541
14542   FETCH_DATA (the_info, codep + 2);
14543   x = *codep++ & 0xff;
14544   x |= (*codep++ & 0xff) << 8;
14545   return x;
14546 }
14547
14548 static void
14549 set_op (bfd_vma op, int riprel)
14550 {
14551   op_index[op_ad] = op_ad;
14552   if (address_mode == mode_64bit)
14553     {
14554       op_address[op_ad] = op;
14555       op_riprel[op_ad] = riprel;
14556     }
14557   else
14558     {
14559       /* Mask to get a 32-bit address.  */
14560       op_address[op_ad] = op & 0xffffffff;
14561       op_riprel[op_ad] = riprel & 0xffffffff;
14562     }
14563 }
14564
14565 static void
14566 OP_REG (int code, int sizeflag)
14567 {
14568   const char *s;
14569   int add;
14570
14571   switch (code)
14572     {
14573     case es_reg: case ss_reg: case cs_reg:
14574     case ds_reg: case fs_reg: case gs_reg:
14575       oappend (names_seg[code - es_reg]);
14576       return;
14577     }
14578
14579   USED_REX (REX_B);
14580   if (rex & REX_B)
14581     add = 8;
14582   else
14583     add = 0;
14584
14585   switch (code)
14586     {
14587     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14588     case sp_reg: case bp_reg: case si_reg: case di_reg:
14589       s = names16[code - ax_reg + add];
14590       break;
14591     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14592     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14593       USED_REX (0);
14594       if (rex)
14595         s = names8rex[code - al_reg + add];
14596       else
14597         s = names8[code - al_reg];
14598       break;
14599     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14600     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14601       if (address_mode == mode_64bit
14602           && ((sizeflag & DFLAG) || (rex & REX_W)))
14603         {
14604           s = names64[code - rAX_reg + add];
14605           break;
14606         }
14607       code += eAX_reg - rAX_reg;
14608       /* Fall through.  */
14609     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14610     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14611       USED_REX (REX_W);
14612       if (rex & REX_W)
14613         s = names64[code - eAX_reg + add];
14614       else
14615         {
14616           if (sizeflag & DFLAG)
14617             s = names32[code - eAX_reg + add];
14618           else
14619             s = names16[code - eAX_reg + add];
14620           used_prefixes |= (prefixes & PREFIX_DATA);
14621         }
14622       break;
14623     default:
14624       s = INTERNAL_DISASSEMBLER_ERROR;
14625       break;
14626     }
14627   oappend (s);
14628 }
14629
14630 static void
14631 OP_IMREG (int code, int sizeflag)
14632 {
14633   const char *s;
14634
14635   switch (code)
14636     {
14637     case indir_dx_reg:
14638       if (intel_syntax)
14639         s = "dx";
14640       else
14641         s = "(%dx)";
14642       break;
14643     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14644     case sp_reg: case bp_reg: case si_reg: case di_reg:
14645       s = names16[code - ax_reg];
14646       break;
14647     case es_reg: case ss_reg: case cs_reg:
14648     case ds_reg: case fs_reg: case gs_reg:
14649       s = names_seg[code - es_reg];
14650       break;
14651     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14652     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14653       USED_REX (0);
14654       if (rex)
14655         s = names8rex[code - al_reg];
14656       else
14657         s = names8[code - al_reg];
14658       break;
14659     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14660     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14661       USED_REX (REX_W);
14662       if (rex & REX_W)
14663         s = names64[code - eAX_reg];
14664       else
14665         {
14666           if (sizeflag & DFLAG)
14667             s = names32[code - eAX_reg];
14668           else
14669             s = names16[code - eAX_reg];
14670           used_prefixes |= (prefixes & PREFIX_DATA);
14671         }
14672       break;
14673     case z_mode_ax_reg:
14674       if ((rex & REX_W) || (sizeflag & DFLAG))
14675         s = *names32;
14676       else
14677         s = *names16;
14678       if (!(rex & REX_W))
14679         used_prefixes |= (prefixes & PREFIX_DATA);
14680       break;
14681     default:
14682       s = INTERNAL_DISASSEMBLER_ERROR;
14683       break;
14684     }
14685   oappend (s);
14686 }
14687
14688 static void
14689 OP_I (int bytemode, int sizeflag)
14690 {
14691   bfd_signed_vma op;
14692   bfd_signed_vma mask = -1;
14693
14694   switch (bytemode)
14695     {
14696     case b_mode:
14697       FETCH_DATA (the_info, codep + 1);
14698       op = *codep++;
14699       mask = 0xff;
14700       break;
14701     case v_mode:
14702       USED_REX (REX_W);
14703       if (rex & REX_W)
14704         op = get32s ();
14705       else
14706         {
14707           if (sizeflag & DFLAG)
14708             {
14709               op = get32 ();
14710               mask = 0xffffffff;
14711             }
14712           else
14713             {
14714               op = get16 ();
14715               mask = 0xfffff;
14716             }
14717           used_prefixes |= (prefixes & PREFIX_DATA);
14718         }
14719       break;
14720     case d_mode:
14721       mask = 0xffffffff;
14722       op = get32 ();
14723       break;
14724     case w_mode:
14725       mask = 0xfffff;
14726       op = get16 ();
14727       break;
14728     case const_1_mode:
14729       if (intel_syntax)
14730         oappend ("1");
14731       return;
14732     default:
14733       oappend (INTERNAL_DISASSEMBLER_ERROR);
14734       return;
14735     }
14736
14737   op &= mask;
14738   scratchbuf[0] = '$';
14739   print_operand_value (scratchbuf + 1, 1, op);
14740   oappend_maybe_intel (scratchbuf);
14741   scratchbuf[0] = '\0';
14742 }
14743
14744 static void
14745 OP_I64 (int bytemode, int sizeflag)
14746 {
14747   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14748     {
14749       OP_I (bytemode, sizeflag);
14750       return;
14751     }
14752
14753   USED_REX (REX_W);
14754
14755   scratchbuf[0] = '$';
14756   print_operand_value (scratchbuf + 1, 1, get64 ());
14757   oappend_maybe_intel (scratchbuf);
14758   scratchbuf[0] = '\0';
14759 }
14760
14761 static void
14762 OP_sI (int bytemode, int sizeflag)
14763 {
14764   bfd_signed_vma op;
14765
14766   switch (bytemode)
14767     {
14768     case b_mode:
14769     case b_T_mode:
14770       FETCH_DATA (the_info, codep + 1);
14771       op = *codep++;
14772       if ((op & 0x80) != 0)
14773         op -= 0x100;
14774       if (bytemode == b_T_mode)
14775         {
14776           if (address_mode != mode_64bit
14777               || !((sizeflag & DFLAG) || (rex & REX_W)))
14778             {
14779               /* The operand-size prefix is overridden by a REX prefix.  */
14780               if ((sizeflag & DFLAG) || (rex & REX_W))
14781                 op &= 0xffffffff;
14782               else
14783                 op &= 0xffff;
14784           }
14785         }
14786       else
14787         {
14788           if (!(rex & REX_W))
14789             {
14790               if (sizeflag & DFLAG)
14791                 op &= 0xffffffff;
14792               else
14793                 op &= 0xffff;
14794             }
14795         }
14796       break;
14797     case v_mode:
14798       /* The operand-size prefix is overridden by a REX prefix.  */
14799       if ((sizeflag & DFLAG) || (rex & REX_W))
14800         op = get32s ();
14801       else
14802         op = get16 ();
14803       break;
14804     default:
14805       oappend (INTERNAL_DISASSEMBLER_ERROR);
14806       return;
14807     }
14808
14809   scratchbuf[0] = '$';
14810   print_operand_value (scratchbuf + 1, 1, op);
14811   oappend_maybe_intel (scratchbuf);
14812 }
14813
14814 static void
14815 OP_J (int bytemode, int sizeflag)
14816 {
14817   bfd_vma disp;
14818   bfd_vma mask = -1;
14819   bfd_vma segment = 0;
14820
14821   switch (bytemode)
14822     {
14823     case b_mode:
14824       FETCH_DATA (the_info, codep + 1);
14825       disp = *codep++;
14826       if ((disp & 0x80) != 0)
14827         disp -= 0x100;
14828       break;
14829     case v_mode:
14830       if (isa64 == amd64)
14831         USED_REX (REX_W);
14832       if ((sizeflag & DFLAG)
14833           || (address_mode == mode_64bit
14834               && (isa64 != amd64 || (rex & REX_W))))
14835         disp = get32s ();
14836       else
14837         {
14838           disp = get16 ();
14839           if ((disp & 0x8000) != 0)
14840             disp -= 0x10000;
14841           /* In 16bit mode, address is wrapped around at 64k within
14842              the same segment.  Otherwise, a data16 prefix on a jump
14843              instruction means that the pc is masked to 16 bits after
14844              the displacement is added!  */
14845           mask = 0xffff;
14846           if ((prefixes & PREFIX_DATA) == 0)
14847             segment = ((start_pc + (codep - start_codep))
14848                        & ~((bfd_vma) 0xffff));
14849         }
14850       if (address_mode != mode_64bit
14851           || (isa64 == amd64 && !(rex & REX_W)))
14852         used_prefixes |= (prefixes & PREFIX_DATA);
14853       break;
14854     default:
14855       oappend (INTERNAL_DISASSEMBLER_ERROR);
14856       return;
14857     }
14858   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14859   set_op (disp, 0);
14860   print_operand_value (scratchbuf, 1, disp);
14861   oappend (scratchbuf);
14862 }
14863
14864 static void
14865 OP_SEG (int bytemode, int sizeflag)
14866 {
14867   if (bytemode == w_mode)
14868     oappend (names_seg[modrm.reg]);
14869   else
14870     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14871 }
14872
14873 static void
14874 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14875 {
14876   int seg, offset;
14877
14878   if (sizeflag & DFLAG)
14879     {
14880       offset = get32 ();
14881       seg = get16 ();
14882     }
14883   else
14884     {
14885       offset = get16 ();
14886       seg = get16 ();
14887     }
14888   used_prefixes |= (prefixes & PREFIX_DATA);
14889   if (intel_syntax)
14890     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14891   else
14892     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14893   oappend (scratchbuf);
14894 }
14895
14896 static void
14897 OP_OFF (int bytemode, int sizeflag)
14898 {
14899   bfd_vma off;
14900
14901   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14902     intel_operand_size (bytemode, sizeflag);
14903   append_seg ();
14904
14905   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14906     off = get32 ();
14907   else
14908     off = get16 ();
14909
14910   if (intel_syntax)
14911     {
14912       if (!active_seg_prefix)
14913         {
14914           oappend (names_seg[ds_reg - es_reg]);
14915           oappend (":");
14916         }
14917     }
14918   print_operand_value (scratchbuf, 1, off);
14919   oappend (scratchbuf);
14920 }
14921
14922 static void
14923 OP_OFF64 (int bytemode, int sizeflag)
14924 {
14925   bfd_vma off;
14926
14927   if (address_mode != mode_64bit
14928       || (prefixes & PREFIX_ADDR))
14929     {
14930       OP_OFF (bytemode, sizeflag);
14931       return;
14932     }
14933
14934   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14935     intel_operand_size (bytemode, sizeflag);
14936   append_seg ();
14937
14938   off = get64 ();
14939
14940   if (intel_syntax)
14941     {
14942       if (!active_seg_prefix)
14943         {
14944           oappend (names_seg[ds_reg - es_reg]);
14945           oappend (":");
14946         }
14947     }
14948   print_operand_value (scratchbuf, 1, off);
14949   oappend (scratchbuf);
14950 }
14951
14952 static void
14953 ptr_reg (int code, int sizeflag)
14954 {
14955   const char *s;
14956
14957   *obufp++ = open_char;
14958   used_prefixes |= (prefixes & PREFIX_ADDR);
14959   if (address_mode == mode_64bit)
14960     {
14961       if (!(sizeflag & AFLAG))
14962         s = names32[code - eAX_reg];
14963       else
14964         s = names64[code - eAX_reg];
14965     }
14966   else if (sizeflag & AFLAG)
14967     s = names32[code - eAX_reg];
14968   else
14969     s = names16[code - eAX_reg];
14970   oappend (s);
14971   *obufp++ = close_char;
14972   *obufp = 0;
14973 }
14974
14975 static void
14976 OP_ESreg (int code, int sizeflag)
14977 {
14978   if (intel_syntax)
14979     {
14980       switch (codep[-1])
14981         {
14982         case 0x6d:      /* insw/insl */
14983           intel_operand_size (z_mode, sizeflag);
14984           break;
14985         case 0xa5:      /* movsw/movsl/movsq */
14986         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14987         case 0xab:      /* stosw/stosl */
14988         case 0xaf:      /* scasw/scasl */
14989           intel_operand_size (v_mode, sizeflag);
14990           break;
14991         default:
14992           intel_operand_size (b_mode, sizeflag);
14993         }
14994     }
14995   oappend_maybe_intel ("%es:");
14996   ptr_reg (code, sizeflag);
14997 }
14998
14999 static void
15000 OP_DSreg (int code, int sizeflag)
15001 {
15002   if (intel_syntax)
15003     {
15004       switch (codep[-1])
15005         {
15006         case 0x6f:      /* outsw/outsl */
15007           intel_operand_size (z_mode, sizeflag);
15008           break;
15009         case 0xa5:      /* movsw/movsl/movsq */
15010         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15011         case 0xad:      /* lodsw/lodsl/lodsq */
15012           intel_operand_size (v_mode, sizeflag);
15013           break;
15014         default:
15015           intel_operand_size (b_mode, sizeflag);
15016         }
15017     }
15018   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15019      default segment register DS is printed.  */
15020   if (!active_seg_prefix)
15021     active_seg_prefix = PREFIX_DS;
15022   append_seg ();
15023   ptr_reg (code, sizeflag);
15024 }
15025
15026 static void
15027 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15028 {
15029   int add;
15030   if (rex & REX_R)
15031     {
15032       USED_REX (REX_R);
15033       add = 8;
15034     }
15035   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15036     {
15037       all_prefixes[last_lock_prefix] = 0;
15038       used_prefixes |= PREFIX_LOCK;
15039       add = 8;
15040     }
15041   else
15042     add = 0;
15043   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15044   oappend_maybe_intel (scratchbuf);
15045 }
15046
15047 static void
15048 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15049 {
15050   int add;
15051   USED_REX (REX_R);
15052   if (rex & REX_R)
15053     add = 8;
15054   else
15055     add = 0;
15056   if (intel_syntax)
15057     sprintf (scratchbuf, "db%d", modrm.reg + add);
15058   else
15059     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15060   oappend (scratchbuf);
15061 }
15062
15063 static void
15064 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15065 {
15066   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15067   oappend_maybe_intel (scratchbuf);
15068 }
15069
15070 static void
15071 OP_R (int bytemode, int sizeflag)
15072 {
15073   /* Skip mod/rm byte.  */
15074   MODRM_CHECK;
15075   codep++;
15076   OP_E_register (bytemode, sizeflag);
15077 }
15078
15079 static void
15080 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15081 {
15082   int reg = modrm.reg;
15083   const char **names;
15084
15085   used_prefixes |= (prefixes & PREFIX_DATA);
15086   if (prefixes & PREFIX_DATA)
15087     {
15088       names = names_xmm;
15089       USED_REX (REX_R);
15090       if (rex & REX_R)
15091         reg += 8;
15092     }
15093   else
15094     names = names_mm;
15095   oappend (names[reg]);
15096 }
15097
15098 static void
15099 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15100 {
15101   int reg = modrm.reg;
15102   const char **names;
15103
15104   USED_REX (REX_R);
15105   if (rex & REX_R)
15106     reg += 8;
15107   if (vex.evex)
15108     {
15109       if (!vex.r)
15110         reg += 16;
15111     }
15112
15113   if (need_vex
15114       && bytemode != xmm_mode
15115       && bytemode != xmmq_mode
15116       && bytemode != evex_half_bcst_xmmq_mode
15117       && bytemode != ymm_mode
15118       && bytemode != scalar_mode)
15119     {
15120       switch (vex.length)
15121         {
15122         case 128:
15123           names = names_xmm;
15124           break;
15125         case 256:
15126           if (vex.w
15127               || (bytemode != vex_vsib_q_w_dq_mode
15128                   && bytemode != vex_vsib_q_w_d_mode))
15129             names = names_ymm;
15130           else
15131             names = names_xmm;
15132           break;
15133         case 512:
15134           names = names_zmm;
15135           break;
15136         default:
15137           abort ();
15138         }
15139     }
15140   else if (bytemode == xmmq_mode
15141            || bytemode == evex_half_bcst_xmmq_mode)
15142     {
15143       switch (vex.length)
15144         {
15145         case 128:
15146         case 256:
15147           names = names_xmm;
15148           break;
15149         case 512:
15150           names = names_ymm;
15151           break;
15152         default:
15153           abort ();
15154         }
15155     }
15156   else if (bytemode == ymm_mode)
15157     names = names_ymm;
15158   else
15159     names = names_xmm;
15160   oappend (names[reg]);
15161 }
15162
15163 static void
15164 OP_EM (int bytemode, int sizeflag)
15165 {
15166   int reg;
15167   const char **names;
15168
15169   if (modrm.mod != 3)
15170     {
15171       if (intel_syntax
15172           && (bytemode == v_mode || bytemode == v_swap_mode))
15173         {
15174           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15175           used_prefixes |= (prefixes & PREFIX_DATA);
15176         }
15177       OP_E (bytemode, sizeflag);
15178       return;
15179     }
15180
15181   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15182     swap_operand ();
15183
15184   /* Skip mod/rm byte.  */
15185   MODRM_CHECK;
15186   codep++;
15187   used_prefixes |= (prefixes & PREFIX_DATA);
15188   reg = modrm.rm;
15189   if (prefixes & PREFIX_DATA)
15190     {
15191       names = names_xmm;
15192       USED_REX (REX_B);
15193       if (rex & REX_B)
15194         reg += 8;
15195     }
15196   else
15197     names = names_mm;
15198   oappend (names[reg]);
15199 }
15200
15201 /* cvt* are the only instructions in sse2 which have
15202    both SSE and MMX operands and also have 0x66 prefix
15203    in their opcode. 0x66 was originally used to differentiate
15204    between SSE and MMX instruction(operands). So we have to handle the
15205    cvt* separately using OP_EMC and OP_MXC */
15206 static void
15207 OP_EMC (int bytemode, int sizeflag)
15208 {
15209   if (modrm.mod != 3)
15210     {
15211       if (intel_syntax && bytemode == v_mode)
15212         {
15213           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15214           used_prefixes |= (prefixes & PREFIX_DATA);
15215         }
15216       OP_E (bytemode, sizeflag);
15217       return;
15218     }
15219
15220   /* Skip mod/rm byte.  */
15221   MODRM_CHECK;
15222   codep++;
15223   used_prefixes |= (prefixes & PREFIX_DATA);
15224   oappend (names_mm[modrm.rm]);
15225 }
15226
15227 static void
15228 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15229 {
15230   used_prefixes |= (prefixes & PREFIX_DATA);
15231   oappend (names_mm[modrm.reg]);
15232 }
15233
15234 static void
15235 OP_EX (int bytemode, int sizeflag)
15236 {
15237   int reg;
15238   const char **names;
15239
15240   /* Skip mod/rm byte.  */
15241   MODRM_CHECK;
15242   codep++;
15243
15244   if (modrm.mod != 3)
15245     {
15246       OP_E_memory (bytemode, sizeflag);
15247       return;
15248     }
15249
15250   reg = modrm.rm;
15251   USED_REX (REX_B);
15252   if (rex & REX_B)
15253     reg += 8;
15254   if (vex.evex)
15255     {
15256       USED_REX (REX_X);
15257       if ((rex & REX_X))
15258         reg += 16;
15259     }
15260
15261   if ((sizeflag & SUFFIX_ALWAYS)
15262       && (bytemode == x_swap_mode
15263           || bytemode == d_swap_mode
15264           || bytemode == d_scalar_swap_mode
15265           || bytemode == q_swap_mode
15266           || bytemode == q_scalar_swap_mode))
15267     swap_operand ();
15268
15269   if (need_vex
15270       && bytemode != xmm_mode
15271       && bytemode != xmmdw_mode
15272       && bytemode != xmmqd_mode
15273       && bytemode != xmm_mb_mode
15274       && bytemode != xmm_mw_mode
15275       && bytemode != xmm_md_mode
15276       && bytemode != xmm_mq_mode
15277       && bytemode != xmm_mdq_mode
15278       && bytemode != xmmq_mode
15279       && bytemode != evex_half_bcst_xmmq_mode
15280       && bytemode != ymm_mode
15281       && bytemode != d_scalar_mode
15282       && bytemode != d_scalar_swap_mode
15283       && bytemode != q_scalar_mode
15284       && bytemode != q_scalar_swap_mode
15285       && bytemode != vex_scalar_w_dq_mode)
15286     {
15287       switch (vex.length)
15288         {
15289         case 128:
15290           names = names_xmm;
15291           break;
15292         case 256:
15293           names = names_ymm;
15294           break;
15295         case 512:
15296           names = names_zmm;
15297           break;
15298         default:
15299           abort ();
15300         }
15301     }
15302   else if (bytemode == xmmq_mode
15303            || bytemode == evex_half_bcst_xmmq_mode)
15304     {
15305       switch (vex.length)
15306         {
15307         case 128:
15308         case 256:
15309           names = names_xmm;
15310           break;
15311         case 512:
15312           names = names_ymm;
15313           break;
15314         default:
15315           abort ();
15316         }
15317     }
15318   else if (bytemode == ymm_mode)
15319     names = names_ymm;
15320   else
15321     names = names_xmm;
15322   oappend (names[reg]);
15323 }
15324
15325 static void
15326 OP_MS (int bytemode, int sizeflag)
15327 {
15328   if (modrm.mod == 3)
15329     OP_EM (bytemode, sizeflag);
15330   else
15331     BadOp ();
15332 }
15333
15334 static void
15335 OP_XS (int bytemode, int sizeflag)
15336 {
15337   if (modrm.mod == 3)
15338     OP_EX (bytemode, sizeflag);
15339   else
15340     BadOp ();
15341 }
15342
15343 static void
15344 OP_M (int bytemode, int sizeflag)
15345 {
15346   if (modrm.mod == 3)
15347     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15348     BadOp ();
15349   else
15350     OP_E (bytemode, sizeflag);
15351 }
15352
15353 static void
15354 OP_0f07 (int bytemode, int sizeflag)
15355 {
15356   if (modrm.mod != 3 || modrm.rm != 0)
15357     BadOp ();
15358   else
15359     OP_E (bytemode, sizeflag);
15360 }
15361
15362 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15363    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15364
15365 static void
15366 NOP_Fixup1 (int bytemode, int sizeflag)
15367 {
15368   if ((prefixes & PREFIX_DATA) != 0
15369       || (rex != 0
15370           && rex != 0x48
15371           && address_mode == mode_64bit))
15372     OP_REG (bytemode, sizeflag);
15373   else
15374     strcpy (obuf, "nop");
15375 }
15376
15377 static void
15378 NOP_Fixup2 (int bytemode, int sizeflag)
15379 {
15380   if ((prefixes & PREFIX_DATA) != 0
15381       || (rex != 0
15382           && rex != 0x48
15383           && address_mode == mode_64bit))
15384     OP_IMREG (bytemode, sizeflag);
15385 }
15386
15387 static const char *const Suffix3DNow[] = {
15388 /* 00 */        NULL,           NULL,           NULL,           NULL,
15389 /* 04 */        NULL,           NULL,           NULL,           NULL,
15390 /* 08 */        NULL,           NULL,           NULL,           NULL,
15391 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15392 /* 10 */        NULL,           NULL,           NULL,           NULL,
15393 /* 14 */        NULL,           NULL,           NULL,           NULL,
15394 /* 18 */        NULL,           NULL,           NULL,           NULL,
15395 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15396 /* 20 */        NULL,           NULL,           NULL,           NULL,
15397 /* 24 */        NULL,           NULL,           NULL,           NULL,
15398 /* 28 */        NULL,           NULL,           NULL,           NULL,
15399 /* 2C */        NULL,           NULL,           NULL,           NULL,
15400 /* 30 */        NULL,           NULL,           NULL,           NULL,
15401 /* 34 */        NULL,           NULL,           NULL,           NULL,
15402 /* 38 */        NULL,           NULL,           NULL,           NULL,
15403 /* 3C */        NULL,           NULL,           NULL,           NULL,
15404 /* 40 */        NULL,           NULL,           NULL,           NULL,
15405 /* 44 */        NULL,           NULL,           NULL,           NULL,
15406 /* 48 */        NULL,           NULL,           NULL,           NULL,
15407 /* 4C */        NULL,           NULL,           NULL,           NULL,
15408 /* 50 */        NULL,           NULL,           NULL,           NULL,
15409 /* 54 */        NULL,           NULL,           NULL,           NULL,
15410 /* 58 */        NULL,           NULL,           NULL,           NULL,
15411 /* 5C */        NULL,           NULL,           NULL,           NULL,
15412 /* 60 */        NULL,           NULL,           NULL,           NULL,
15413 /* 64 */        NULL,           NULL,           NULL,           NULL,
15414 /* 68 */        NULL,           NULL,           NULL,           NULL,
15415 /* 6C */        NULL,           NULL,           NULL,           NULL,
15416 /* 70 */        NULL,           NULL,           NULL,           NULL,
15417 /* 74 */        NULL,           NULL,           NULL,           NULL,
15418 /* 78 */        NULL,           NULL,           NULL,           NULL,
15419 /* 7C */        NULL,           NULL,           NULL,           NULL,
15420 /* 80 */        NULL,           NULL,           NULL,           NULL,
15421 /* 84 */        NULL,           NULL,           NULL,           NULL,
15422 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15423 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15424 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15425 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15426 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15427 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15428 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15429 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15430 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15431 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15432 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15433 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15434 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15435 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15436 /* C0 */        NULL,           NULL,           NULL,           NULL,
15437 /* C4 */        NULL,           NULL,           NULL,           NULL,
15438 /* C8 */        NULL,           NULL,           NULL,           NULL,
15439 /* CC */        NULL,           NULL,           NULL,           NULL,
15440 /* D0 */        NULL,           NULL,           NULL,           NULL,
15441 /* D4 */        NULL,           NULL,           NULL,           NULL,
15442 /* D8 */        NULL,           NULL,           NULL,           NULL,
15443 /* DC */        NULL,           NULL,           NULL,           NULL,
15444 /* E0 */        NULL,           NULL,           NULL,           NULL,
15445 /* E4 */        NULL,           NULL,           NULL,           NULL,
15446 /* E8 */        NULL,           NULL,           NULL,           NULL,
15447 /* EC */        NULL,           NULL,           NULL,           NULL,
15448 /* F0 */        NULL,           NULL,           NULL,           NULL,
15449 /* F4 */        NULL,           NULL,           NULL,           NULL,
15450 /* F8 */        NULL,           NULL,           NULL,           NULL,
15451 /* FC */        NULL,           NULL,           NULL,           NULL,
15452 };
15453
15454 static void
15455 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15456 {
15457   const char *mnemonic;
15458
15459   FETCH_DATA (the_info, codep + 1);
15460   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15461      place where an 8-bit immediate would normally go.  ie. the last
15462      byte of the instruction.  */
15463   obufp = mnemonicendp;
15464   mnemonic = Suffix3DNow[*codep++ & 0xff];
15465   if (mnemonic)
15466     oappend (mnemonic);
15467   else
15468     {
15469       /* Since a variable sized modrm/sib chunk is between the start
15470          of the opcode (0x0f0f) and the opcode suffix, we need to do
15471          all the modrm processing first, and don't know until now that
15472          we have a bad opcode.  This necessitates some cleaning up.  */
15473       op_out[0][0] = '\0';
15474       op_out[1][0] = '\0';
15475       BadOp ();
15476     }
15477   mnemonicendp = obufp;
15478 }
15479
15480 static struct op simd_cmp_op[] =
15481 {
15482   { STRING_COMMA_LEN ("eq") },
15483   { STRING_COMMA_LEN ("lt") },
15484   { STRING_COMMA_LEN ("le") },
15485   { STRING_COMMA_LEN ("unord") },
15486   { STRING_COMMA_LEN ("neq") },
15487   { STRING_COMMA_LEN ("nlt") },
15488   { STRING_COMMA_LEN ("nle") },
15489   { STRING_COMMA_LEN ("ord") }
15490 };
15491
15492 static void
15493 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15494 {
15495   unsigned int cmp_type;
15496
15497   FETCH_DATA (the_info, codep + 1);
15498   cmp_type = *codep++ & 0xff;
15499   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15500     {
15501       char suffix [3];
15502       char *p = mnemonicendp - 2;
15503       suffix[0] = p[0];
15504       suffix[1] = p[1];
15505       suffix[2] = '\0';
15506       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15507       mnemonicendp += simd_cmp_op[cmp_type].len;
15508     }
15509   else
15510     {
15511       /* We have a reserved extension byte.  Output it directly.  */
15512       scratchbuf[0] = '$';
15513       print_operand_value (scratchbuf + 1, 1, cmp_type);
15514       oappend_maybe_intel (scratchbuf);
15515       scratchbuf[0] = '\0';
15516     }
15517 }
15518
15519 static void
15520 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15521 {
15522   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15523   if (!intel_syntax)
15524     {
15525       strcpy (op_out[0], names32[0]);
15526       strcpy (op_out[1], names32[1]);
15527       if (bytemode == eBX_reg)
15528         strcpy (op_out[2], names32[3]);
15529       two_source_ops = 1;
15530     }
15531   /* Skip mod/rm byte.  */
15532   MODRM_CHECK;
15533   codep++;
15534 }
15535
15536 static void
15537 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15538             int sizeflag ATTRIBUTE_UNUSED)
15539 {
15540   /* monitor %{e,r,}ax,%ecx,%edx"  */
15541   if (!intel_syntax)
15542     {
15543       const char **names = (address_mode == mode_64bit
15544                             ? names64 : names32);
15545
15546       if (prefixes & PREFIX_ADDR)
15547         {
15548           /* Remove "addr16/addr32".  */
15549           all_prefixes[last_addr_prefix] = 0;
15550           names = (address_mode != mode_32bit
15551                    ? names32 : names16);
15552           used_prefixes |= PREFIX_ADDR;
15553         }
15554       else if (address_mode == mode_16bit)
15555         names = names16;
15556       strcpy (op_out[0], names[0]);
15557       strcpy (op_out[1], names32[1]);
15558       strcpy (op_out[2], names32[2]);
15559       two_source_ops = 1;
15560     }
15561   /* Skip mod/rm byte.  */
15562   MODRM_CHECK;
15563   codep++;
15564 }
15565
15566 static void
15567 BadOp (void)
15568 {
15569   /* Throw away prefixes and 1st. opcode byte.  */
15570   codep = insn_codep + 1;
15571   oappend ("(bad)");
15572 }
15573
15574 static void
15575 REP_Fixup (int bytemode, int sizeflag)
15576 {
15577   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15578      lods and stos.  */
15579   if (prefixes & PREFIX_REPZ)
15580     all_prefixes[last_repz_prefix] = REP_PREFIX;
15581
15582   switch (bytemode)
15583     {
15584     case al_reg:
15585     case eAX_reg:
15586     case indir_dx_reg:
15587       OP_IMREG (bytemode, sizeflag);
15588       break;
15589     case eDI_reg:
15590       OP_ESreg (bytemode, sizeflag);
15591       break;
15592     case eSI_reg:
15593       OP_DSreg (bytemode, sizeflag);
15594       break;
15595     default:
15596       abort ();
15597       break;
15598     }
15599 }
15600
15601 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15602    "bnd".  */
15603
15604 static void
15605 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15606 {
15607   if (prefixes & PREFIX_REPNZ)
15608     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15609 }
15610
15611 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15612    "notrack".  */
15613
15614 static void
15615 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15616                int sizeflag ATTRIBUTE_UNUSED)
15617 {
15618   if (active_seg_prefix == PREFIX_DS
15619       && (address_mode != mode_64bit || last_data_prefix < 0))
15620     {
15621       /* NOTRACK prefix is only valid on indirect branch instructions.
15622          NB: DATA prefix is unsupported for Intel64.  */
15623       active_seg_prefix = 0;
15624       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15625     }
15626 }
15627
15628 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15629    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15630  */
15631
15632 static void
15633 HLE_Fixup1 (int bytemode, int sizeflag)
15634 {
15635   if (modrm.mod != 3
15636       && (prefixes & PREFIX_LOCK) != 0)
15637     {
15638       if (prefixes & PREFIX_REPZ)
15639         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15640       if (prefixes & PREFIX_REPNZ)
15641         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15642     }
15643
15644   OP_E (bytemode, sizeflag);
15645 }
15646
15647 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15648    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15649  */
15650
15651 static void
15652 HLE_Fixup2 (int bytemode, int sizeflag)
15653 {
15654   if (modrm.mod != 3)
15655     {
15656       if (prefixes & PREFIX_REPZ)
15657         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15658       if (prefixes & PREFIX_REPNZ)
15659         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15660     }
15661
15662   OP_E (bytemode, sizeflag);
15663 }
15664
15665 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15666    "xrelease" for memory operand.  No check for LOCK prefix.   */
15667
15668 static void
15669 HLE_Fixup3 (int bytemode, int sizeflag)
15670 {
15671   if (modrm.mod != 3
15672       && last_repz_prefix > last_repnz_prefix
15673       && (prefixes & PREFIX_REPZ) != 0)
15674     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15675
15676   OP_E (bytemode, sizeflag);
15677 }
15678
15679 static void
15680 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15681 {
15682   USED_REX (REX_W);
15683   if (rex & REX_W)
15684     {
15685       /* Change cmpxchg8b to cmpxchg16b.  */
15686       char *p = mnemonicendp - 2;
15687       mnemonicendp = stpcpy (p, "16b");
15688       bytemode = o_mode;
15689     }
15690   else if ((prefixes & PREFIX_LOCK) != 0)
15691     {
15692       if (prefixes & PREFIX_REPZ)
15693         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15694       if (prefixes & PREFIX_REPNZ)
15695         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15696     }
15697
15698   OP_M (bytemode, sizeflag);
15699 }
15700
15701 static void
15702 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15703 {
15704   const char **names;
15705
15706   if (need_vex)
15707     {
15708       switch (vex.length)
15709         {
15710         case 128:
15711           names = names_xmm;
15712           break;
15713         case 256:
15714           names = names_ymm;
15715           break;
15716         default:
15717           abort ();
15718         }
15719     }
15720   else
15721     names = names_xmm;
15722   oappend (names[reg]);
15723 }
15724
15725 static void
15726 CRC32_Fixup (int bytemode, int sizeflag)
15727 {
15728   /* Add proper suffix to "crc32".  */
15729   char *p = mnemonicendp;
15730
15731   switch (bytemode)
15732     {
15733     case b_mode:
15734       if (intel_syntax)
15735         goto skip;
15736
15737       *p++ = 'b';
15738       break;
15739     case v_mode:
15740       if (intel_syntax)
15741         goto skip;
15742
15743       USED_REX (REX_W);
15744       if (rex & REX_W)
15745         *p++ = 'q';
15746       else
15747         {
15748           if (sizeflag & DFLAG)
15749             *p++ = 'l';
15750           else
15751             *p++ = 'w';
15752           used_prefixes |= (prefixes & PREFIX_DATA);
15753         }
15754       break;
15755     default:
15756       oappend (INTERNAL_DISASSEMBLER_ERROR);
15757       break;
15758     }
15759   mnemonicendp = p;
15760   *p = '\0';
15761
15762 skip:
15763   if (modrm.mod == 3)
15764     {
15765       int add;
15766
15767       /* Skip mod/rm byte.  */
15768       MODRM_CHECK;
15769       codep++;
15770
15771       USED_REX (REX_B);
15772       add = (rex & REX_B) ? 8 : 0;
15773       if (bytemode == b_mode)
15774         {
15775           USED_REX (0);
15776           if (rex)
15777             oappend (names8rex[modrm.rm + add]);
15778           else
15779             oappend (names8[modrm.rm + add]);
15780         }
15781       else
15782         {
15783           USED_REX (REX_W);
15784           if (rex & REX_W)
15785             oappend (names64[modrm.rm + add]);
15786           else if ((prefixes & PREFIX_DATA))
15787             oappend (names16[modrm.rm + add]);
15788           else
15789             oappend (names32[modrm.rm + add]);
15790         }
15791     }
15792   else
15793     OP_E (bytemode, sizeflag);
15794 }
15795
15796 static void
15797 FXSAVE_Fixup (int bytemode, int sizeflag)
15798 {
15799   /* Add proper suffix to "fxsave" and "fxrstor".  */
15800   USED_REX (REX_W);
15801   if (rex & REX_W)
15802     {
15803       char *p = mnemonicendp;
15804       *p++ = '6';
15805       *p++ = '4';
15806       *p = '\0';
15807       mnemonicendp = p;
15808     }
15809   OP_M (bytemode, sizeflag);
15810 }
15811
15812 static void
15813 PCMPESTR_Fixup (int bytemode, int sizeflag)
15814 {
15815   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15816   if (!intel_syntax)
15817     {
15818       char *p = mnemonicendp;
15819
15820       USED_REX (REX_W);
15821       if (rex & REX_W)
15822         *p++ = 'q';
15823       else if (sizeflag & SUFFIX_ALWAYS)
15824         *p++ = 'l';
15825
15826       *p = '\0';
15827       mnemonicendp = p;
15828     }
15829
15830   OP_EX (bytemode, sizeflag);
15831 }
15832
15833 /* Display the destination register operand for instructions with
15834    VEX. */
15835
15836 static void
15837 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15838 {
15839   int reg;
15840   const char **names;
15841
15842   if (!need_vex)
15843     abort ();
15844
15845   if (!need_vex_reg)
15846     return;
15847
15848   reg = vex.register_specifier;
15849   vex.register_specifier = 0;
15850   if (address_mode != mode_64bit)
15851     reg &= 7;
15852   else if (vex.evex && !vex.v)
15853     reg += 16;
15854
15855   if (bytemode == vex_scalar_mode)
15856     {
15857       oappend (names_xmm[reg]);
15858       return;
15859     }
15860
15861   switch (vex.length)
15862     {
15863     case 128:
15864       switch (bytemode)
15865         {
15866         case vex_mode:
15867         case vex128_mode:
15868         case vex_vsib_q_w_dq_mode:
15869         case vex_vsib_q_w_d_mode:
15870           names = names_xmm;
15871           break;
15872         case dq_mode:
15873           if (rex & REX_W)
15874             names = names64;
15875           else
15876             names = names32;
15877           break;
15878         case mask_bd_mode:
15879         case mask_mode:
15880           if (reg > 0x7)
15881             {
15882               oappend ("(bad)");
15883               return;
15884             }
15885           names = names_mask;
15886           break;
15887         default:
15888           abort ();
15889           return;
15890         }
15891       break;
15892     case 256:
15893       switch (bytemode)
15894         {
15895         case vex_mode:
15896         case vex256_mode:
15897           names = names_ymm;
15898           break;
15899         case vex_vsib_q_w_dq_mode:
15900         case vex_vsib_q_w_d_mode:
15901           names = vex.w ? names_ymm : names_xmm;
15902           break;
15903         case mask_bd_mode:
15904         case mask_mode:
15905           if (reg > 0x7)
15906             {
15907               oappend ("(bad)");
15908               return;
15909             }
15910           names = names_mask;
15911           break;
15912         default:
15913           /* See PR binutils/20893 for a reproducer.  */
15914           oappend ("(bad)");
15915           return;
15916         }
15917       break;
15918     case 512:
15919       names = names_zmm;
15920       break;
15921     default:
15922       abort ();
15923       break;
15924     }
15925   oappend (names[reg]);
15926 }
15927
15928 /* Get the VEX immediate byte without moving codep.  */
15929
15930 static unsigned char
15931 get_vex_imm8 (int sizeflag, int opnum)
15932 {
15933   int bytes_before_imm = 0;
15934
15935   if (modrm.mod != 3)
15936     {
15937       /* There are SIB/displacement bytes.  */
15938       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15939         {
15940           /* 32/64 bit address mode */
15941           int base = modrm.rm;
15942
15943           /* Check SIB byte.  */
15944           if (base == 4)
15945             {
15946               FETCH_DATA (the_info, codep + 1);
15947               base = *codep & 7;
15948               /* When decoding the third source, don't increase
15949                  bytes_before_imm as this has already been incremented
15950                  by one in OP_E_memory while decoding the second
15951                  source operand.  */
15952               if (opnum == 0)
15953                 bytes_before_imm++;
15954             }
15955
15956           /* Don't increase bytes_before_imm when decoding the third source,
15957              it has already been incremented by OP_E_memory while decoding
15958              the second source operand.  */
15959           if (opnum == 0)
15960             {
15961               switch (modrm.mod)
15962                 {
15963                   case 0:
15964                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15965                        SIB == 5, there is a 4 byte displacement.  */
15966                     if (base != 5)
15967                       /* No displacement. */
15968                       break;
15969                     /* Fall through.  */
15970                   case 2:
15971                     /* 4 byte displacement.  */
15972                     bytes_before_imm += 4;
15973                     break;
15974                   case 1:
15975                     /* 1 byte displacement.  */
15976                     bytes_before_imm++;
15977                     break;
15978                 }
15979             }
15980         }
15981       else
15982         {
15983           /* 16 bit address mode */
15984           /* Don't increase bytes_before_imm when decoding the third source,
15985              it has already been incremented by OP_E_memory while decoding
15986              the second source operand.  */
15987           if (opnum == 0)
15988             {
15989               switch (modrm.mod)
15990                 {
15991                 case 0:
15992                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
15993                   if (modrm.rm != 6)
15994                     /* No displacement. */
15995                     break;
15996                   /* Fall through.  */
15997                 case 2:
15998                   /* 2 byte displacement.  */
15999                   bytes_before_imm += 2;
16000                   break;
16001                 case 1:
16002                   /* 1 byte displacement: when decoding the third source,
16003                      don't increase bytes_before_imm as this has already
16004                      been incremented by one in OP_E_memory while decoding
16005                      the second source operand.  */
16006                   if (opnum == 0)
16007                     bytes_before_imm++;
16008
16009                   break;
16010                 }
16011             }
16012         }
16013     }
16014
16015   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16016   return codep [bytes_before_imm];
16017 }
16018
16019 static void
16020 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16021 {
16022   const char **names;
16023
16024   if (reg == -1 && modrm.mod != 3)
16025     {
16026       OP_E_memory (bytemode, sizeflag);
16027       return;
16028     }
16029   else
16030     {
16031       if (reg == -1)
16032         {
16033           reg = modrm.rm;
16034           USED_REX (REX_B);
16035           if (rex & REX_B)
16036             reg += 8;
16037         }
16038       if (address_mode != mode_64bit)
16039         reg &= 7;
16040     }
16041
16042   switch (vex.length)
16043     {
16044     case 128:
16045       names = names_xmm;
16046       break;
16047     case 256:
16048       names = names_ymm;
16049       break;
16050     default:
16051       abort ();
16052     }
16053   oappend (names[reg]);
16054 }
16055
16056 static void
16057 OP_EX_VexImmW (int bytemode, int sizeflag)
16058 {
16059   int reg = -1;
16060   static unsigned char vex_imm8;
16061
16062   if (vex_w_done == 0)
16063     {
16064       vex_w_done = 1;
16065
16066       /* Skip mod/rm byte.  */
16067       MODRM_CHECK;
16068       codep++;
16069
16070       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16071
16072       if (vex.w)
16073           reg = vex_imm8 >> 4;
16074
16075       OP_EX_VexReg (bytemode, sizeflag, reg);
16076     }
16077   else if (vex_w_done == 1)
16078     {
16079       vex_w_done = 2;
16080
16081       if (!vex.w)
16082           reg = vex_imm8 >> 4;
16083
16084       OP_EX_VexReg (bytemode, sizeflag, reg);
16085     }
16086   else
16087     {
16088       /* Output the imm8 directly.  */
16089       scratchbuf[0] = '$';
16090       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16091       oappend_maybe_intel (scratchbuf);
16092       scratchbuf[0] = '\0';
16093       codep++;
16094     }
16095 }
16096
16097 static void
16098 OP_Vex_2src (int bytemode, int sizeflag)
16099 {
16100   if (modrm.mod == 3)
16101     {
16102       int reg = modrm.rm;
16103       USED_REX (REX_B);
16104       if (rex & REX_B)
16105         reg += 8;
16106       oappend (names_xmm[reg]);
16107     }
16108   else
16109     {
16110       if (intel_syntax
16111           && (bytemode == v_mode || bytemode == v_swap_mode))
16112         {
16113           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16114           used_prefixes |= (prefixes & PREFIX_DATA);
16115         }
16116       OP_E (bytemode, sizeflag);
16117     }
16118 }
16119
16120 static void
16121 OP_Vex_2src_1 (int bytemode, int sizeflag)
16122 {
16123   if (modrm.mod == 3)
16124     {
16125       /* Skip mod/rm byte.   */
16126       MODRM_CHECK;
16127       codep++;
16128     }
16129
16130   if (vex.w)
16131     {
16132       unsigned int reg = vex.register_specifier;
16133       vex.register_specifier = 0;
16134
16135       if (address_mode != mode_64bit)
16136         reg &= 7;
16137       oappend (names_xmm[reg]);
16138     }
16139   else
16140     OP_Vex_2src (bytemode, sizeflag);
16141 }
16142
16143 static void
16144 OP_Vex_2src_2 (int bytemode, int sizeflag)
16145 {
16146   if (vex.w)
16147     OP_Vex_2src (bytemode, sizeflag);
16148   else
16149     {
16150       unsigned int reg = vex.register_specifier;
16151       vex.register_specifier = 0;
16152
16153       if (address_mode != mode_64bit)
16154         reg &= 7;
16155       oappend (names_xmm[reg]);
16156     }
16157 }
16158
16159 static void
16160 OP_EX_VexW (int bytemode, int sizeflag)
16161 {
16162   int reg = -1;
16163
16164   if (!vex_w_done)
16165     {
16166       /* Skip mod/rm byte.  */
16167       MODRM_CHECK;
16168       codep++;
16169
16170       if (vex.w)
16171         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16172     }
16173   else
16174     {
16175       if (!vex.w)
16176         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16177     }
16178
16179   OP_EX_VexReg (bytemode, sizeflag, reg);
16180
16181   if (vex_w_done)
16182     codep++;
16183   vex_w_done = 1;
16184 }
16185
16186 static void
16187 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16188 {
16189   int reg;
16190   const char **names;
16191
16192   FETCH_DATA (the_info, codep + 1);
16193   reg = *codep++;
16194
16195   if (bytemode != x_mode)
16196     abort ();
16197
16198   reg >>= 4;
16199   if (address_mode != mode_64bit)
16200     reg &= 7;
16201
16202   switch (vex.length)
16203     {
16204     case 128:
16205       names = names_xmm;
16206       break;
16207     case 256:
16208       names = names_ymm;
16209       break;
16210     default:
16211       abort ();
16212     }
16213   oappend (names[reg]);
16214 }
16215
16216 static void
16217 OP_XMM_VexW (int bytemode, int sizeflag)
16218 {
16219   /* Turn off the REX.W bit since it is used for swapping operands
16220      now.  */
16221   rex &= ~REX_W;
16222   OP_XMM (bytemode, sizeflag);
16223 }
16224
16225 static void
16226 OP_EX_Vex (int bytemode, int sizeflag)
16227 {
16228   if (modrm.mod != 3)
16229     need_vex_reg = 0;
16230   OP_EX (bytemode, sizeflag);
16231 }
16232
16233 static void
16234 OP_XMM_Vex (int bytemode, int sizeflag)
16235 {
16236   if (modrm.mod != 3)
16237     need_vex_reg = 0;
16238   OP_XMM (bytemode, sizeflag);
16239 }
16240
16241 static struct op vex_cmp_op[] =
16242 {
16243   { STRING_COMMA_LEN ("eq") },
16244   { STRING_COMMA_LEN ("lt") },
16245   { STRING_COMMA_LEN ("le") },
16246   { STRING_COMMA_LEN ("unord") },
16247   { STRING_COMMA_LEN ("neq") },
16248   { STRING_COMMA_LEN ("nlt") },
16249   { STRING_COMMA_LEN ("nle") },
16250   { STRING_COMMA_LEN ("ord") },
16251   { STRING_COMMA_LEN ("eq_uq") },
16252   { STRING_COMMA_LEN ("nge") },
16253   { STRING_COMMA_LEN ("ngt") },
16254   { STRING_COMMA_LEN ("false") },
16255   { STRING_COMMA_LEN ("neq_oq") },
16256   { STRING_COMMA_LEN ("ge") },
16257   { STRING_COMMA_LEN ("gt") },
16258   { STRING_COMMA_LEN ("true") },
16259   { STRING_COMMA_LEN ("eq_os") },
16260   { STRING_COMMA_LEN ("lt_oq") },
16261   { STRING_COMMA_LEN ("le_oq") },
16262   { STRING_COMMA_LEN ("unord_s") },
16263   { STRING_COMMA_LEN ("neq_us") },
16264   { STRING_COMMA_LEN ("nlt_uq") },
16265   { STRING_COMMA_LEN ("nle_uq") },
16266   { STRING_COMMA_LEN ("ord_s") },
16267   { STRING_COMMA_LEN ("eq_us") },
16268   { STRING_COMMA_LEN ("nge_uq") },
16269   { STRING_COMMA_LEN ("ngt_uq") },
16270   { STRING_COMMA_LEN ("false_os") },
16271   { STRING_COMMA_LEN ("neq_os") },
16272   { STRING_COMMA_LEN ("ge_oq") },
16273   { STRING_COMMA_LEN ("gt_oq") },
16274   { STRING_COMMA_LEN ("true_us") },
16275 };
16276
16277 static void
16278 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16279 {
16280   unsigned int cmp_type;
16281
16282   FETCH_DATA (the_info, codep + 1);
16283   cmp_type = *codep++ & 0xff;
16284   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16285     {
16286       char suffix [3];
16287       char *p = mnemonicendp - 2;
16288       suffix[0] = p[0];
16289       suffix[1] = p[1];
16290       suffix[2] = '\0';
16291       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16292       mnemonicendp += vex_cmp_op[cmp_type].len;
16293     }
16294   else
16295     {
16296       /* We have a reserved extension byte.  Output it directly.  */
16297       scratchbuf[0] = '$';
16298       print_operand_value (scratchbuf + 1, 1, cmp_type);
16299       oappend_maybe_intel (scratchbuf);
16300       scratchbuf[0] = '\0';
16301     }
16302 }
16303
16304 static void
16305 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16306              int sizeflag ATTRIBUTE_UNUSED)
16307 {
16308   unsigned int cmp_type;
16309
16310   if (!vex.evex)
16311     abort ();
16312
16313   FETCH_DATA (the_info, codep + 1);
16314   cmp_type = *codep++ & 0xff;
16315   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16316      If it's the case, print suffix, otherwise - print the immediate.  */
16317   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16318       && cmp_type != 3
16319       && cmp_type != 7)
16320     {
16321       char suffix [3];
16322       char *p = mnemonicendp - 2;
16323
16324       /* vpcmp* can have both one- and two-lettered suffix.  */
16325       if (p[0] == 'p')
16326         {
16327           p++;
16328           suffix[0] = p[0];
16329           suffix[1] = '\0';
16330         }
16331       else
16332         {
16333           suffix[0] = p[0];
16334           suffix[1] = p[1];
16335           suffix[2] = '\0';
16336         }
16337
16338       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16339       mnemonicendp += simd_cmp_op[cmp_type].len;
16340     }
16341   else
16342     {
16343       /* We have a reserved extension byte.  Output it directly.  */
16344       scratchbuf[0] = '$';
16345       print_operand_value (scratchbuf + 1, 1, cmp_type);
16346       oappend_maybe_intel (scratchbuf);
16347       scratchbuf[0] = '\0';
16348     }
16349 }
16350
16351 static const struct op xop_cmp_op[] =
16352 {
16353   { STRING_COMMA_LEN ("lt") },
16354   { STRING_COMMA_LEN ("le") },
16355   { STRING_COMMA_LEN ("gt") },
16356   { STRING_COMMA_LEN ("ge") },
16357   { STRING_COMMA_LEN ("eq") },
16358   { STRING_COMMA_LEN ("neq") },
16359   { STRING_COMMA_LEN ("false") },
16360   { STRING_COMMA_LEN ("true") }
16361 };
16362
16363 static void
16364 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16365              int sizeflag ATTRIBUTE_UNUSED)
16366 {
16367   unsigned int cmp_type;
16368
16369   FETCH_DATA (the_info, codep + 1);
16370   cmp_type = *codep++ & 0xff;
16371   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16372     {
16373       char suffix[3];
16374       char *p = mnemonicendp - 2;
16375
16376       /* vpcom* can have both one- and two-lettered suffix.  */
16377       if (p[0] == 'm')
16378         {
16379           p++;
16380           suffix[0] = p[0];
16381           suffix[1] = '\0';
16382         }
16383       else
16384         {
16385           suffix[0] = p[0];
16386           suffix[1] = p[1];
16387           suffix[2] = '\0';
16388         }
16389
16390       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16391       mnemonicendp += xop_cmp_op[cmp_type].len;
16392     }
16393   else
16394     {
16395       /* We have a reserved extension byte.  Output it directly.  */
16396       scratchbuf[0] = '$';
16397       print_operand_value (scratchbuf + 1, 1, cmp_type);
16398       oappend_maybe_intel (scratchbuf);
16399       scratchbuf[0] = '\0';
16400     }
16401 }
16402
16403 static const struct op pclmul_op[] =
16404 {
16405   { STRING_COMMA_LEN ("lql") },
16406   { STRING_COMMA_LEN ("hql") },
16407   { STRING_COMMA_LEN ("lqh") },
16408   { STRING_COMMA_LEN ("hqh") }
16409 };
16410
16411 static void
16412 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16413               int sizeflag ATTRIBUTE_UNUSED)
16414 {
16415   unsigned int pclmul_type;
16416
16417   FETCH_DATA (the_info, codep + 1);
16418   pclmul_type = *codep++ & 0xff;
16419   switch (pclmul_type)
16420     {
16421     case 0x10:
16422       pclmul_type = 2;
16423       break;
16424     case 0x11:
16425       pclmul_type = 3;
16426       break;
16427     default:
16428       break;
16429     }
16430   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16431     {
16432       char suffix [4];
16433       char *p = mnemonicendp - 3;
16434       suffix[0] = p[0];
16435       suffix[1] = p[1];
16436       suffix[2] = p[2];
16437       suffix[3] = '\0';
16438       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16439       mnemonicendp += pclmul_op[pclmul_type].len;
16440     }
16441   else
16442     {
16443       /* We have a reserved extension byte.  Output it directly.  */
16444       scratchbuf[0] = '$';
16445       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16446       oappend_maybe_intel (scratchbuf);
16447       scratchbuf[0] = '\0';
16448     }
16449 }
16450
16451 static void
16452 MOVBE_Fixup (int bytemode, int sizeflag)
16453 {
16454   /* Add proper suffix to "movbe".  */
16455   char *p = mnemonicendp;
16456
16457   switch (bytemode)
16458     {
16459     case v_mode:
16460       if (intel_syntax)
16461         goto skip;
16462
16463       USED_REX (REX_W);
16464       if (sizeflag & SUFFIX_ALWAYS)
16465         {
16466           if (rex & REX_W)
16467             *p++ = 'q';
16468           else
16469             {
16470               if (sizeflag & DFLAG)
16471                 *p++ = 'l';
16472               else
16473                 *p++ = 'w';
16474               used_prefixes |= (prefixes & PREFIX_DATA);
16475             }
16476         }
16477       break;
16478     default:
16479       oappend (INTERNAL_DISASSEMBLER_ERROR);
16480       break;
16481     }
16482   mnemonicendp = p;
16483   *p = '\0';
16484
16485 skip:
16486   OP_M (bytemode, sizeflag);
16487 }
16488
16489 static void
16490 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16491 {
16492   int reg;
16493   const char **names;
16494
16495   /* Skip mod/rm byte.  */
16496   MODRM_CHECK;
16497   codep++;
16498
16499   if (rex & REX_W)
16500     names = names64;
16501   else
16502     names = names32;
16503
16504   reg = modrm.rm;
16505   USED_REX (REX_B);
16506   if (rex & REX_B)
16507     reg += 8;
16508
16509   oappend (names[reg]);
16510 }
16511
16512 static void
16513 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16514 {
16515   const char **names;
16516   unsigned int reg = vex.register_specifier;
16517   vex.register_specifier = 0;
16518
16519   if (rex & REX_W)
16520     names = names64;
16521   else
16522     names = names32;
16523
16524   if (address_mode != mode_64bit)
16525     reg &= 7;
16526   oappend (names[reg]);
16527 }
16528
16529 static void
16530 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16531 {
16532   if (!vex.evex
16533       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16534     abort ();
16535
16536   USED_REX (REX_R);
16537   if ((rex & REX_R) != 0 || !vex.r)
16538     {
16539       BadOp ();
16540       return;
16541     }
16542
16543   oappend (names_mask [modrm.reg]);
16544 }
16545
16546 static void
16547 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16548 {
16549   if (!vex.evex
16550       || (bytemode != evex_rounding_mode
16551           && bytemode != evex_rounding_64_mode
16552           && bytemode != evex_sae_mode))
16553     abort ();
16554   if (modrm.mod == 3 && vex.b)
16555     switch (bytemode)
16556       {
16557       case evex_rounding_64_mode:
16558         if (address_mode != mode_64bit)
16559           {
16560             oappend ("(bad)");
16561             break;
16562           }
16563         /* Fall through.  */
16564       case evex_rounding_mode:
16565         oappend (names_rounding[vex.ll]);
16566         break;
16567       case evex_sae_mode:
16568         oappend ("{sae}");
16569         break;
16570       default:
16571         break;
16572       }
16573 }