opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_Rounding (int, int);
  95 static void OP_REG_VexI4 (int, int);
  96 static void OP_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125 static void MOVSXD_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* Mark parts used in the REX prefix.  When we are testing for
 155    empty prefix (for 8bit register REX extension), just mask it
 156    out.  Otherwise test for REX bit is excuse for existence of REX
 157    only in case value is nonzero.  */
 158 #define USED_REX(value)                                 \
 159   {                                                     \
 160     if (value)                                          \
 161       {                                                 \
 162         if ((rex & value))                              \
 163           rex_used |= (value) | REX_OPCODE;             \
 164       }                                                 \
 165     else                                                \
 166       rex_used |= REX_OPCODE;                           \
 167   }
 168
 169 /* Flags for prefixes which we somehow handled when printing the
 170    current instruction.  */
 171 static int used_prefixes;
 172
 173 /* Flags stored in PREFIXES.  */
 174 #define PREFIX_REPZ 1
 175 #define PREFIX_REPNZ 2
 176 #define PREFIX_LOCK 4
 177 #define PREFIX_CS 8
 178 #define PREFIX_SS 0x10
 179 #define PREFIX_DS 0x20
 180 #define PREFIX_ES 0x40
 181 #define PREFIX_FS 0x80
 182 #define PREFIX_GS 0x100
 183 #define PREFIX_DATA 0x200
 184 #define PREFIX_ADDR 0x400
 185 #define PREFIX_FWAIT 0x800
 186
 187 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 188    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 189    on error.  */
 190 #define FETCH_DATA(info, addr) \
 191   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 192    ? 1 : fetch_data ((info), (addr)))
 193
 194 static int
 195 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 196 {
 197   int status;
 198   struct dis_private *priv = (struct dis_private *) info->private_data;
 199   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 200
 201   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 202     status = (*info->read_memory_func) (start,
 203                                         priv->max_fetched,
 204                                         addr - priv->max_fetched,
 205                                         info);
 206   else
 207     status = -1;
 208   if (status != 0)
 209     {
 210       /* If we did manage to read at least one byte, then
 211          print_insn_i386 will do something sensible.  Otherwise, print
 212          an error.  We do that here because this is where we know
 213          STATUS.  */
 214       if (priv->max_fetched == priv->the_buffer)
 215         (*info->memory_error_func) (status, start, info);
 216       OPCODES_SIGLONGJMP (priv->bailout, 1);
 217     }
 218   else
 219     priv->max_fetched = addr;
 220   return 1;
 221 }
 222
 223 /* Possible values for prefix requirement.  */
 224 #define PREFIX_IGNORED_SHIFT    16
 225 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 226 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 227 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 230
 231 /* Opcode prefixes.  */
 232 #define PREFIX_OPCODE           (PREFIX_REPZ \
 233                                  | PREFIX_REPNZ \
 234                                  | PREFIX_DATA)
 235
 236 /* Prefixes ignored.  */
 237 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 238                                  | PREFIX_IGNORED_REPNZ \
 239                                  | PREFIX_IGNORED_DATA)
 240
 241 #define XX { NULL, 0 }
 242 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 243
 244 #define Eb { OP_E, b_mode }
 245 #define Ebnd { OP_E, bnd_mode }
 246 #define EbS { OP_E, b_swap_mode }
 247 #define EbndS { OP_E, bnd_swap_mode }
 248 #define Ev { OP_E, v_mode }
 249 #define Eva { OP_E, va_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define Edqb { OP_E, dqb_mode }
 256 #define Edb { OP_E, db_mode }
 257 #define Edw { OP_E, dw_mode }
 258 #define Edqd { OP_E, dqd_mode }
 259 #define Eq { OP_E, q_mode }
 260 #define indirEv { OP_indirE, indir_v_mode }
 261 #define indirEp { OP_indirE, f_mode }
 262 #define stackEv { OP_E, stack_v_mode }
 263 #define Em { OP_E, m_mode }
 264 #define Ew { OP_E, w_mode }
 265 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 266 #define Ma { OP_M, a_mode }
 267 #define Mb { OP_M, b_mode }
 268 #define Md { OP_M, d_mode }
 269 #define Mo { OP_M, o_mode }
 270 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 271 #define Mq { OP_M, q_mode }
 272 #define Mv_bnd { OP_M, v_bndmk_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gva { OP_G, va_mode }
 282 #define Gw { OP_G, w_mode }
 283 #define Rd { OP_R, d_mode }
 284 #define Rdq { OP_R, dq_mode }
 285 #define Rm { OP_R, m_mode }
 286 #define Ib { OP_I, b_mode }
 287 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 289 #define Iv { OP_I, v_mode }
 290 #define sIv { OP_sI, v_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Id { OP_I, d_mode }
 293 #define Iw { OP_I, w_mode }
 294 #define I1 { OP_I, const_1_mode }
 295 #define Jb { OP_J, b_mode }
 296 #define Jv { OP_J, v_mode }
 297 #define Jdqw { OP_J, dqw_mode }
 298 #define Cm { OP_C, m_mode }
 299 #define Dm { OP_D, m_mode }
 300 #define Td { OP_T, d_mode }
 301 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 302
 303 #define RMeAX { OP_REG, eAX_reg }
 304 #define RMeBX { OP_REG, eBX_reg }
 305 #define RMeCX { OP_REG, eCX_reg }
 306 #define RMeDX { OP_REG, eDX_reg }
 307 #define RMeSP { OP_REG, eSP_reg }
 308 #define RMeBP { OP_REG, eBP_reg }
 309 #define RMeSI { OP_REG, eSI_reg }
 310 #define RMeDI { OP_REG, eDI_reg }
 311 #define RMrAX { OP_REG, rAX_reg }
 312 #define RMrBX { OP_REG, rBX_reg }
 313 #define RMrCX { OP_REG, rCX_reg }
 314 #define RMrDX { OP_REG, rDX_reg }
 315 #define RMrSP { OP_REG, rSP_reg }
 316 #define RMrBP { OP_REG, rBP_reg }
 317 #define RMrSI { OP_REG, rSI_reg }
 318 #define RMrDI { OP_REG, rDI_reg }
 319 #define RMAL { OP_REG, al_reg }
 320 #define RMCL { OP_REG, cl_reg }
 321 #define RMDL { OP_REG, dl_reg }
 322 #define RMBL { OP_REG, bl_reg }
 323 #define RMAH { OP_REG, ah_reg }
 324 #define RMCH { OP_REG, ch_reg }
 325 #define RMDH { OP_REG, dh_reg }
 326 #define RMBH { OP_REG, bh_reg }
 327 #define RMAX { OP_REG, ax_reg }
 328 #define RMDX { OP_REG, dx_reg }
 329
 330 #define eAX { OP_IMREG, eAX_reg }
 331 #define eBX { OP_IMREG, eBX_reg }
 332 #define eCX { OP_IMREG, eCX_reg }
 333 #define eDX { OP_IMREG, eDX_reg }
 334 #define eSP { OP_IMREG, eSP_reg }
 335 #define eBP { OP_IMREG, eBP_reg }
 336 #define eSI { OP_IMREG, eSI_reg }
 337 #define eDI { OP_IMREG, eDI_reg }
 338 #define AL { OP_IMREG, al_reg }
 339 #define CL { OP_IMREG, cl_reg }
 340 #define DL { OP_IMREG, dl_reg }
 341 #define BL { OP_IMREG, bl_reg }
 342 #define AH { OP_IMREG, ah_reg }
 343 #define CH { OP_IMREG, ch_reg }
 344 #define DH { OP_IMREG, dh_reg }
 345 #define BH { OP_IMREG, bh_reg }
 346 #define AX { OP_IMREG, ax_reg }
 347 #define DX { OP_IMREG, dx_reg }
 348 #define zAX { OP_IMREG, z_mode_ax_reg }
 349 #define indirDX { OP_IMREG, indir_dx_reg }
 350
 351 #define Sw { OP_SEG, w_mode }
 352 #define Sv { OP_SEG, v_mode }
 353 #define Ap { OP_DIR, 0 }
 354 #define Ob { OP_OFF64, b_mode }
 355 #define Ov { OP_OFF64, v_mode }
 356 #define Xb { OP_DSreg, eSI_reg }
 357 #define Xv { OP_DSreg, eSI_reg }
 358 #define Xz { OP_DSreg, eSI_reg }
 359 #define Yb { OP_ESreg, eDI_reg }
 360 #define Yv { OP_ESreg, eDI_reg }
 361 #define DSBX { OP_DSreg, eBX_reg }
 362
 363 #define es { OP_REG, es_reg }
 364 #define ss { OP_REG, ss_reg }
 365 #define cs { OP_REG, cs_reg }
 366 #define ds { OP_REG, ds_reg }
 367 #define fs { OP_REG, fs_reg }
 368 #define gs { OP_REG, gs_reg }
 369
 370 #define MX { OP_MMX, 0 }
 371 #define XM { OP_XMM, 0 }
 372 #define XMScalar { OP_XMM, scalar_mode }
 373 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 374 #define XMM { OP_XMM, xmm_mode }
 375 #define XMxmmq { OP_XMM, xmmq_mode }
 376 #define EM { OP_EM, v_mode }
 377 #define EMS { OP_EM, v_swap_mode }
 378 #define EMd { OP_EM, d_mode }
 379 #define EMx { OP_EM, x_mode }
 380 #define EXbScalar { OP_EX, b_scalar_mode }
 381 #define EXw { OP_EX, w_mode }
 382 #define EXwScalar { OP_EX, w_scalar_mode }
 383 #define EXd { OP_EX, d_mode }
 384 #define EXdS { OP_EX, d_swap_mode }
 385 #define EXq { OP_EX, q_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmmdw { OP_EX, xmmdw_mode }
 398 #define EXxmmqd { OP_EX, xmmqd_mode }
 399 #define EXymmq { OP_EX, ymmq_mode }
 400 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 401 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 402 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 403 #define MS { OP_MS, v_mode }
 404 #define XS { OP_XS, v_mode }
 405 #define EMCq { OP_EMC, q_mode }
 406 #define MXC { OP_MXC, 0 }
 407 #define OPSUF { OP_3DNowSuffix, 0 }
 408 #define SEP { SEP_Fixup, 0 }
 409 #define CMP { CMP_Fixup, 0 }
 410 #define XMM0 { XMM_Fixup, 0 }
 411 #define FXSAVE { FXSAVE_Fixup, 0 }
 412
 413 #define Vex { OP_VEX, vex_mode }
 414 #define VexW { OP_VexW, vex_mode }
 415 #define VexScalar { OP_VEX, vex_scalar_mode }
 416 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 417 #define Vex128 { OP_VEX, vex128_mode }
 418 #define Vex256 { OP_VEX, vex256_mode }
 419 #define VexGdq { OP_VEX, dq_mode }
 420 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 421 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 422 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 423 #define XMVexI4 { OP_REG_VexI4, x_mode }
 424 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 425 #define VexI4 { OP_VexI4, 0 }
 426 #define PCLMUL { PCLMUL_Fixup, 0 }
 427 #define VCMP { VCMP_Fixup, 0 }
 428 #define VPCMP { VPCMP_Fixup, 0 }
 429 #define VPCOM { VPCOM_Fixup, 0 }
 430
 431 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 432 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 433 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 434
 435 #define XMask { OP_Mask, mask_mode }
 436 #define MaskG { OP_G, mask_mode }
 437 #define MaskE { OP_E, mask_mode }
 438 #define MaskBDE { OP_E, mask_bd_mode }
 439 #define MaskR { OP_R, mask_mode }
 440 #define MaskVex { OP_VEX, mask_mode }
 441
 442 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 443 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 444 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 445 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 446
 447 /* Used handle "rep" prefix for string instructions.  */
 448 #define Xbr { REP_Fixup, eSI_reg }
 449 #define Xvr { REP_Fixup, eSI_reg }
 450 #define Ybr { REP_Fixup, eDI_reg }
 451 #define Yvr { REP_Fixup, eDI_reg }
 452 #define Yzr { REP_Fixup, eDI_reg }
 453 #define indirDXr { REP_Fixup, indir_dx_reg }
 454 #define ALr { REP_Fixup, al_reg }
 455 #define eAXr { REP_Fixup, eAX_reg }
 456
 457 /* Used handle HLE prefix for lockable instructions.  */
 458 #define Ebh1 { HLE_Fixup1, b_mode }
 459 #define Evh1 { HLE_Fixup1, v_mode }
 460 #define Ebh2 { HLE_Fixup2, b_mode }
 461 #define Evh2 { HLE_Fixup2, v_mode }
 462 #define Ebh3 { HLE_Fixup3, b_mode }
 463 #define Evh3 { HLE_Fixup3, v_mode }
 464
 465 #define BND { BND_Fixup, 0 }
 466 #define NOTRACK { NOTRACK_Fixup, 0 }
 467
 468 #define cond_jump_flag { NULL, cond_jump_mode }
 469 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 470
 471 /* bits in sizeflag */
 472 #define SUFFIX_ALWAYS 4
 473 #define AFLAG 2
 474 #define DFLAG 1
 475
 476 enum
 477 {
 478   /* byte operand */
 479   b_mode = 1,
 480   /* byte operand with operand swapped */
 481   b_swap_mode,
 482   /* byte operand, sign extend like 'T' suffix */
 483   b_T_mode,
 484   /* operand size depends on prefixes */
 485   v_mode,
 486   /* operand size depends on prefixes with operand swapped */
 487   v_swap_mode,
 488   /* operand size depends on address prefix */
 489   va_mode,
 490   /* word operand */
 491   w_mode,
 492   /* double word operand  */
 493   d_mode,
 494   /* double word operand with operand swapped */
 495   d_swap_mode,
 496   /* quad word operand */
 497   q_mode,
 498   /* quad word operand with operand swapped */
 499   q_swap_mode,
 500   /* ten-byte operand */
 501   t_mode,
 502   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 503      broadcast enabled.  */
 504   x_mode,
 505   /* Similar to x_mode, but with different EVEX mem shifts.  */
 506   evex_x_gscat_mode,
 507   /* Similar to x_mode, but with disabled broadcast.  */
 508   evex_x_nobcst_mode,
 509   /* Similar to x_mode, but with operands swapped and disabled broadcast
 510      in EVEX.  */
 511   x_swap_mode,
 512   /* 16-byte XMM operand */
 513   xmm_mode,
 514   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 515      memory operand (depending on vector length).  Broadcast isn't
 516      allowed.  */
 517   xmmq_mode,
 518   /* Same as xmmq_mode, but broadcast is allowed.  */
 519   evex_half_bcst_xmmq_mode,
 520   /* XMM register or byte memory operand */
 521   xmm_mb_mode,
 522   /* XMM register or word memory operand */
 523   xmm_mw_mode,
 524   /* XMM register or double word memory operand */
 525   xmm_md_mode,
 526   /* XMM register or quad word memory operand */
 527   xmm_mq_mode,
 528   /* 16-byte XMM, word, double word or quad word operand.  */
 529   xmmdw_mode,
 530   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 531   xmmqd_mode,
 532   /* 32-byte YMM operand */
 533   ymm_mode,
 534   /* quad word, ymmword or zmmword memory operand.  */
 535   ymmq_mode,
 536   /* 32-byte YMM or 16-byte word operand */
 537   ymmxmm_mode,
 538   /* d_mode in 32bit, q_mode in 64bit mode.  */
 539   m_mode,
 540   /* pair of v_mode operands */
 541   a_mode,
 542   cond_jump_mode,
 543   loop_jcxz_mode,
 544   movsxd_mode,
 545   v_bnd_mode,
 546   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 547   v_bndmk_mode,
 548   /* operand size depends on REX prefixes.  */
 549   dq_mode,
 550   /* registers like dq_mode, memory like w_mode, displacements like
 551      v_mode without considering Intel64 ISA.  */
 552   dqw_mode,
 553   /* bounds operand */
 554   bnd_mode,
 555   /* bounds operand with operand swapped */
 556   bnd_swap_mode,
 557   /* 4- or 6-byte pointer operand */
 558   f_mode,
 559   const_1_mode,
 560   /* v_mode for indirect branch opcodes.  */
 561   indir_v_mode,
 562   /* v_mode for stack-related opcodes.  */
 563   stack_v_mode,
 564   /* non-quad operand size depends on prefixes */
 565   z_mode,
 566   /* 16-byte operand */
 567   o_mode,
 568   /* registers like dq_mode, memory like b_mode.  */
 569   dqb_mode,
 570   /* registers like d_mode, memory like b_mode.  */
 571   db_mode,
 572   /* registers like d_mode, memory like w_mode.  */
 573   dw_mode,
 574   /* registers like dq_mode, memory like d_mode.  */
 575   dqd_mode,
 576   /* normal vex mode */
 577   vex_mode,
 578   /* 128bit vex mode */
 579   vex128_mode,
 580   /* 256bit vex mode */
 581   vex256_mode,
 582
 583   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 584   vex_vsib_d_w_dq_mode,
 585   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 586   vex_vsib_d_w_d_mode,
 587   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 588   vex_vsib_q_w_dq_mode,
 589   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 590   vex_vsib_q_w_d_mode,
 591
 592   /* scalar, ignore vector length.  */
 593   scalar_mode,
 594   /* like b_mode, ignore vector length.  */
 595   b_scalar_mode,
 596   /* like w_mode, ignore vector length.  */
 597   w_scalar_mode,
 598   /* like d_swap_mode, ignore vector length.  */
 599   d_scalar_swap_mode,
 600   /* like q_swap_mode, ignore vector length.  */
 601   q_scalar_swap_mode,
 602   /* like vex_mode, ignore vector length.  */
 603   vex_scalar_mode,
 604   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 605   vex_scalar_w_dq_mode,
 606
 607   /* Static rounding.  */
 608   evex_rounding_mode,
 609   /* Static rounding, 64-bit mode only.  */
 610   evex_rounding_64_mode,
 611   /* Supress all exceptions.  */
 612   evex_sae_mode,
 613
 614   /* Mask register operand.  */
 615   mask_mode,
 616   /* Mask register operand.  */
 617   mask_bd_mode,
 618
 619   es_reg,
 620   cs_reg,
 621   ss_reg,
 622   ds_reg,
 623   fs_reg,
 624   gs_reg,
 625
 626   eAX_reg,
 627   eCX_reg,
 628   eDX_reg,
 629   eBX_reg,
 630   eSP_reg,
 631   eBP_reg,
 632   eSI_reg,
 633   eDI_reg,
 634
 635   al_reg,
 636   cl_reg,
 637   dl_reg,
 638   bl_reg,
 639   ah_reg,
 640   ch_reg,
 641   dh_reg,
 642   bh_reg,
 643
 644   ax_reg,
 645   cx_reg,
 646   dx_reg,
 647   bx_reg,
 648   sp_reg,
 649   bp_reg,
 650   si_reg,
 651   di_reg,
 652
 653   rAX_reg,
 654   rCX_reg,
 655   rDX_reg,
 656   rBX_reg,
 657   rSP_reg,
 658   rBP_reg,
 659   rSI_reg,
 660   rDI_reg,
 661
 662   z_mode_ax_reg,
 663   indir_dx_reg
 664 };
 665
 666 enum
 667 {
 668   FLOATCODE = 1,
 669   USE_REG_TABLE,
 670   USE_MOD_TABLE,
 671   USE_RM_TABLE,
 672   USE_PREFIX_TABLE,
 673   USE_X86_64_TABLE,
 674   USE_3BYTE_TABLE,
 675   USE_XOP_8F_TABLE,
 676   USE_VEX_C4_TABLE,
 677   USE_VEX_C5_TABLE,
 678   USE_VEX_LEN_TABLE,
 679   USE_VEX_W_TABLE,
 680   USE_EVEX_TABLE,
 681   USE_EVEX_LEN_TABLE
 682 };
 683
 684 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 685
 686 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 687 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 688 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 689 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 690 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 691 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 692 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 693 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 694 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 695 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 696 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 697 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 698 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 699 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 700 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 701 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 702
 703 enum
 704 {
 705   REG_80 = 0,
 706   REG_81,
 707   REG_83,
 708   REG_8F,
 709   REG_C0,
 710   REG_C1,
 711   REG_C6,
 712   REG_C7,
 713   REG_D0,
 714   REG_D1,
 715   REG_D2,
 716   REG_D3,
 717   REG_F6,
 718   REG_F7,
 719   REG_FE,
 720   REG_FF,
 721   REG_0F00,
 722   REG_0F01,
 723   REG_0F0D,
 724   REG_0F18,
 725   REG_0F1C_P_0_MOD_0,
 726   REG_0F1E_P_1_MOD_3,
 727   REG_0F71,
 728   REG_0F72,
 729   REG_0F73,
 730   REG_0FA6,
 731   REG_0FA7,
 732   REG_0FAE,
 733   REG_0FBA,
 734   REG_0FC7,
 735   REG_VEX_0F71,
 736   REG_VEX_0F72,
 737   REG_VEX_0F73,
 738   REG_VEX_0FAE,
 739   REG_VEX_0F38F3,
 740   REG_XOP_LWPCB,
 741   REG_XOP_LWP,
 742   REG_XOP_TBM_01,
 743   REG_XOP_TBM_02,
 744
 745   REG_EVEX_0F71,
 746   REG_EVEX_0F72,
 747   REG_EVEX_0F73,
 748   REG_EVEX_0F38C6,
 749   REG_EVEX_0F38C7
 750 };
 751
 752 enum
 753 {
 754   MOD_8D = 0,
 755   MOD_C6_REG_7,
 756   MOD_C7_REG_7,
 757   MOD_FF_REG_3,
 758   MOD_FF_REG_5,
 759   MOD_0F01_REG_0,
 760   MOD_0F01_REG_1,
 761   MOD_0F01_REG_2,
 762   MOD_0F01_REG_3,
 763   MOD_0F01_REG_5,
 764   MOD_0F01_REG_7,
 765   MOD_0F12_PREFIX_0,
 766   MOD_0F12_PREFIX_2,
 767   MOD_0F13,
 768   MOD_0F16_PREFIX_0,
 769   MOD_0F16_PREFIX_2,
 770   MOD_0F17,
 771   MOD_0F18_REG_0,
 772   MOD_0F18_REG_1,
 773   MOD_0F18_REG_2,
 774   MOD_0F18_REG_3,
 775   MOD_0F18_REG_4,
 776   MOD_0F18_REG_5,
 777   MOD_0F18_REG_6,
 778   MOD_0F18_REG_7,
 779   MOD_0F1A_PREFIX_0,
 780   MOD_0F1B_PREFIX_0,
 781   MOD_0F1B_PREFIX_1,
 782   MOD_0F1C_PREFIX_0,
 783   MOD_0F1E_PREFIX_1,
 784   MOD_0F24,
 785   MOD_0F26,
 786   MOD_0F2B_PREFIX_0,
 787   MOD_0F2B_PREFIX_1,
 788   MOD_0F2B_PREFIX_2,
 789   MOD_0F2B_PREFIX_3,
 790   MOD_0F50,
 791   MOD_0F71_REG_2,
 792   MOD_0F71_REG_4,
 793   MOD_0F71_REG_6,
 794   MOD_0F72_REG_2,
 795   MOD_0F72_REG_4,
 796   MOD_0F72_REG_6,
 797   MOD_0F73_REG_2,
 798   MOD_0F73_REG_3,
 799   MOD_0F73_REG_6,
 800   MOD_0F73_REG_7,
 801   MOD_0FAE_REG_0,
 802   MOD_0FAE_REG_1,
 803   MOD_0FAE_REG_2,
 804   MOD_0FAE_REG_3,
 805   MOD_0FAE_REG_4,
 806   MOD_0FAE_REG_5,
 807   MOD_0FAE_REG_6,
 808   MOD_0FAE_REG_7,
 809   MOD_0FB2,
 810   MOD_0FB4,
 811   MOD_0FB5,
 812   MOD_0FC3,
 813   MOD_0FC7_REG_3,
 814   MOD_0FC7_REG_4,
 815   MOD_0FC7_REG_5,
 816   MOD_0FC7_REG_6,
 817   MOD_0FC7_REG_7,
 818   MOD_0FD7,
 819   MOD_0FE7_PREFIX_2,
 820   MOD_0FF0_PREFIX_3,
 821   MOD_0F382A_PREFIX_2,
 822   MOD_0F38F5_PREFIX_2,
 823   MOD_0F38F6_PREFIX_0,
 824   MOD_0F38F8_PREFIX_1,
 825   MOD_0F38F8_PREFIX_2,
 826   MOD_0F38F8_PREFIX_3,
 827   MOD_0F38F9_PREFIX_0,
 828   MOD_62_32BIT,
 829   MOD_C4_32BIT,
 830   MOD_C5_32BIT,
 831   MOD_VEX_0F12_PREFIX_0,
 832   MOD_VEX_0F12_PREFIX_2,
 833   MOD_VEX_0F13,
 834   MOD_VEX_0F16_PREFIX_0,
 835   MOD_VEX_0F16_PREFIX_2,
 836   MOD_VEX_0F17,
 837   MOD_VEX_0F2B,
 838   MOD_VEX_W_0_0F41_P_0_LEN_1,
 839   MOD_VEX_W_1_0F41_P_0_LEN_1,
 840   MOD_VEX_W_0_0F41_P_2_LEN_1,
 841   MOD_VEX_W_1_0F41_P_2_LEN_1,
 842   MOD_VEX_W_0_0F42_P_0_LEN_1,
 843   MOD_VEX_W_1_0F42_P_0_LEN_1,
 844   MOD_VEX_W_0_0F42_P_2_LEN_1,
 845   MOD_VEX_W_1_0F42_P_2_LEN_1,
 846   MOD_VEX_W_0_0F44_P_0_LEN_1,
 847   MOD_VEX_W_1_0F44_P_0_LEN_1,
 848   MOD_VEX_W_0_0F44_P_2_LEN_1,
 849   MOD_VEX_W_1_0F44_P_2_LEN_1,
 850   MOD_VEX_W_0_0F45_P_0_LEN_1,
 851   MOD_VEX_W_1_0F45_P_0_LEN_1,
 852   MOD_VEX_W_0_0F45_P_2_LEN_1,
 853   MOD_VEX_W_1_0F45_P_2_LEN_1,
 854   MOD_VEX_W_0_0F46_P_0_LEN_1,
 855   MOD_VEX_W_1_0F46_P_0_LEN_1,
 856   MOD_VEX_W_0_0F46_P_2_LEN_1,
 857   MOD_VEX_W_1_0F46_P_2_LEN_1,
 858   MOD_VEX_W_0_0F47_P_0_LEN_1,
 859   MOD_VEX_W_1_0F47_P_0_LEN_1,
 860   MOD_VEX_W_0_0F47_P_2_LEN_1,
 861   MOD_VEX_W_1_0F47_P_2_LEN_1,
 862   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 863   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 864   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 865   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 866   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 867   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 868   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 869   MOD_VEX_0F50,
 870   MOD_VEX_0F71_REG_2,
 871   MOD_VEX_0F71_REG_4,
 872   MOD_VEX_0F71_REG_6,
 873   MOD_VEX_0F72_REG_2,
 874   MOD_VEX_0F72_REG_4,
 875   MOD_VEX_0F72_REG_6,
 876   MOD_VEX_0F73_REG_2,
 877   MOD_VEX_0F73_REG_3,
 878   MOD_VEX_0F73_REG_6,
 879   MOD_VEX_0F73_REG_7,
 880   MOD_VEX_W_0_0F91_P_0_LEN_0,
 881   MOD_VEX_W_1_0F91_P_0_LEN_0,
 882   MOD_VEX_W_0_0F91_P_2_LEN_0,
 883   MOD_VEX_W_1_0F91_P_2_LEN_0,
 884   MOD_VEX_W_0_0F92_P_0_LEN_0,
 885   MOD_VEX_W_0_0F92_P_2_LEN_0,
 886   MOD_VEX_0F92_P_3_LEN_0,
 887   MOD_VEX_W_0_0F93_P_0_LEN_0,
 888   MOD_VEX_W_0_0F93_P_2_LEN_0,
 889   MOD_VEX_0F93_P_3_LEN_0,
 890   MOD_VEX_W_0_0F98_P_0_LEN_0,
 891   MOD_VEX_W_1_0F98_P_0_LEN_0,
 892   MOD_VEX_W_0_0F98_P_2_LEN_0,
 893   MOD_VEX_W_1_0F98_P_2_LEN_0,
 894   MOD_VEX_W_0_0F99_P_0_LEN_0,
 895   MOD_VEX_W_1_0F99_P_0_LEN_0,
 896   MOD_VEX_W_0_0F99_P_2_LEN_0,
 897   MOD_VEX_W_1_0F99_P_2_LEN_0,
 898   MOD_VEX_0FAE_REG_2,
 899   MOD_VEX_0FAE_REG_3,
 900   MOD_VEX_0FD7_PREFIX_2,
 901   MOD_VEX_0FE7_PREFIX_2,
 902   MOD_VEX_0FF0_PREFIX_3,
 903   MOD_VEX_0F381A_PREFIX_2,
 904   MOD_VEX_0F382A_PREFIX_2,
 905   MOD_VEX_0F382C_PREFIX_2,
 906   MOD_VEX_0F382D_PREFIX_2,
 907   MOD_VEX_0F382E_PREFIX_2,
 908   MOD_VEX_0F382F_PREFIX_2,
 909   MOD_VEX_0F385A_PREFIX_2,
 910   MOD_VEX_0F388C_PREFIX_2,
 911   MOD_VEX_0F388E_PREFIX_2,
 912   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 913   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 914   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 915   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 916   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 917   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 918   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 919   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 920
 921   MOD_EVEX_0F12_PREFIX_0,
 922   MOD_EVEX_0F12_PREFIX_2,
 923   MOD_EVEX_0F13,
 924   MOD_EVEX_0F16_PREFIX_0,
 925   MOD_EVEX_0F16_PREFIX_2,
 926   MOD_EVEX_0F17,
 927   MOD_EVEX_0F2B,
 928   MOD_EVEX_0F381A_P_2_W_0,
 929   MOD_EVEX_0F381A_P_2_W_1,
 930   MOD_EVEX_0F381B_P_2_W_0,
 931   MOD_EVEX_0F381B_P_2_W_1,
 932   MOD_EVEX_0F385A_P_2_W_0,
 933   MOD_EVEX_0F385A_P_2_W_1,
 934   MOD_EVEX_0F385B_P_2_W_0,
 935   MOD_EVEX_0F385B_P_2_W_1,
 936   MOD_EVEX_0F38C6_REG_1,
 937   MOD_EVEX_0F38C6_REG_2,
 938   MOD_EVEX_0F38C6_REG_5,
 939   MOD_EVEX_0F38C6_REG_6,
 940   MOD_EVEX_0F38C7_REG_1,
 941   MOD_EVEX_0F38C7_REG_2,
 942   MOD_EVEX_0F38C7_REG_5,
 943   MOD_EVEX_0F38C7_REG_6
 944 };
 945
 946 enum
 947 {
 948   RM_C6_REG_7 = 0,
 949   RM_C7_REG_7,
 950   RM_0F01_REG_0,
 951   RM_0F01_REG_1,
 952   RM_0F01_REG_2,
 953   RM_0F01_REG_3,
 954   RM_0F01_REG_5_MOD_3,
 955   RM_0F01_REG_7_MOD_3,
 956   RM_0F1E_P_1_MOD_3_REG_7,
 957   RM_0FAE_REG_6_MOD_3_P_0,
 958   RM_0FAE_REG_7_MOD_3,
 959 };
 960
 961 enum
 962 {
 963   PREFIX_90 = 0,
 964   PREFIX_0F01_REG_3_RM_1,
 965   PREFIX_0F01_REG_5_MOD_0,
 966   PREFIX_0F01_REG_5_MOD_3_RM_0,
 967   PREFIX_0F01_REG_5_MOD_3_RM_1,
 968   PREFIX_0F01_REG_5_MOD_3_RM_2,
 969   PREFIX_0F01_REG_7_MOD_3_RM_2,
 970   PREFIX_0F01_REG_7_MOD_3_RM_3,
 971   PREFIX_0F09,
 972   PREFIX_0F10,
 973   PREFIX_0F11,
 974   PREFIX_0F12,
 975   PREFIX_0F16,
 976   PREFIX_0F1A,
 977   PREFIX_0F1B,
 978   PREFIX_0F1C,
 979   PREFIX_0F1E,
 980   PREFIX_0F2A,
 981   PREFIX_0F2B,
 982   PREFIX_0F2C,
 983   PREFIX_0F2D,
 984   PREFIX_0F2E,
 985   PREFIX_0F2F,
 986   PREFIX_0F51,
 987   PREFIX_0F52,
 988   PREFIX_0F53,
 989   PREFIX_0F58,
 990   PREFIX_0F59,
 991   PREFIX_0F5A,
 992   PREFIX_0F5B,
 993   PREFIX_0F5C,
 994   PREFIX_0F5D,
 995   PREFIX_0F5E,
 996   PREFIX_0F5F,
 997   PREFIX_0F60,
 998   PREFIX_0F61,
 999   PREFIX_0F62,
1000   PREFIX_0F6C,
1001   PREFIX_0F6D,
1002   PREFIX_0F6F,
1003   PREFIX_0F70,
1004   PREFIX_0F73_REG_3,
1005   PREFIX_0F73_REG_7,
1006   PREFIX_0F78,
1007   PREFIX_0F79,
1008   PREFIX_0F7C,
1009   PREFIX_0F7D,
1010   PREFIX_0F7E,
1011   PREFIX_0F7F,
1012   PREFIX_0FAE_REG_0_MOD_3,
1013   PREFIX_0FAE_REG_1_MOD_3,
1014   PREFIX_0FAE_REG_2_MOD_3,
1015   PREFIX_0FAE_REG_3_MOD_3,
1016   PREFIX_0FAE_REG_4_MOD_0,
1017   PREFIX_0FAE_REG_4_MOD_3,
1018   PREFIX_0FAE_REG_5_MOD_0,
1019   PREFIX_0FAE_REG_5_MOD_3,
1020   PREFIX_0FAE_REG_6_MOD_0,
1021   PREFIX_0FAE_REG_6_MOD_3,
1022   PREFIX_0FAE_REG_7_MOD_0,
1023   PREFIX_0FB8,
1024   PREFIX_0FBC,
1025   PREFIX_0FBD,
1026   PREFIX_0FC2,
1027   PREFIX_0FC3_MOD_0,
1028   PREFIX_0FC7_REG_6_MOD_0,
1029   PREFIX_0FC7_REG_6_MOD_3,
1030   PREFIX_0FC7_REG_7_MOD_3,
1031   PREFIX_0FD0,
1032   PREFIX_0FD6,
1033   PREFIX_0FE6,
1034   PREFIX_0FE7,
1035   PREFIX_0FF0,
1036   PREFIX_0FF7,
1037   PREFIX_0F3810,
1038   PREFIX_0F3814,
1039   PREFIX_0F3815,
1040   PREFIX_0F3817,
1041   PREFIX_0F3820,
1042   PREFIX_0F3821,
1043   PREFIX_0F3822,
1044   PREFIX_0F3823,
1045   PREFIX_0F3824,
1046   PREFIX_0F3825,
1047   PREFIX_0F3828,
1048   PREFIX_0F3829,
1049   PREFIX_0F382A,
1050   PREFIX_0F382B,
1051   PREFIX_0F3830,
1052   PREFIX_0F3831,
1053   PREFIX_0F3832,
1054   PREFIX_0F3833,
1055   PREFIX_0F3834,
1056   PREFIX_0F3835,
1057   PREFIX_0F3837,
1058   PREFIX_0F3838,
1059   PREFIX_0F3839,
1060   PREFIX_0F383A,
1061   PREFIX_0F383B,
1062   PREFIX_0F383C,
1063   PREFIX_0F383D,
1064   PREFIX_0F383E,
1065   PREFIX_0F383F,
1066   PREFIX_0F3840,
1067   PREFIX_0F3841,
1068   PREFIX_0F3880,
1069   PREFIX_0F3881,
1070   PREFIX_0F3882,
1071   PREFIX_0F38C8,
1072   PREFIX_0F38C9,
1073   PREFIX_0F38CA,
1074   PREFIX_0F38CB,
1075   PREFIX_0F38CC,
1076   PREFIX_0F38CD,
1077   PREFIX_0F38CF,
1078   PREFIX_0F38DB,
1079   PREFIX_0F38DC,
1080   PREFIX_0F38DD,
1081   PREFIX_0F38DE,
1082   PREFIX_0F38DF,
1083   PREFIX_0F38F0,
1084   PREFIX_0F38F1,
1085   PREFIX_0F38F5,
1086   PREFIX_0F38F6,
1087   PREFIX_0F38F8,
1088   PREFIX_0F38F9,
1089   PREFIX_0F3A08,
1090   PREFIX_0F3A09,
1091   PREFIX_0F3A0A,
1092   PREFIX_0F3A0B,
1093   PREFIX_0F3A0C,
1094   PREFIX_0F3A0D,
1095   PREFIX_0F3A0E,
1096   PREFIX_0F3A14,
1097   PREFIX_0F3A15,
1098   PREFIX_0F3A16,
1099   PREFIX_0F3A17,
1100   PREFIX_0F3A20,
1101   PREFIX_0F3A21,
1102   PREFIX_0F3A22,
1103   PREFIX_0F3A40,
1104   PREFIX_0F3A41,
1105   PREFIX_0F3A42,
1106   PREFIX_0F3A44,
1107   PREFIX_0F3A60,
1108   PREFIX_0F3A61,
1109   PREFIX_0F3A62,
1110   PREFIX_0F3A63,
1111   PREFIX_0F3ACC,
1112   PREFIX_0F3ACE,
1113   PREFIX_0F3ACF,
1114   PREFIX_0F3ADF,
1115   PREFIX_VEX_0F10,
1116   PREFIX_VEX_0F11,
1117   PREFIX_VEX_0F12,
1118   PREFIX_VEX_0F16,
1119   PREFIX_VEX_0F2A,
1120   PREFIX_VEX_0F2C,
1121   PREFIX_VEX_0F2D,
1122   PREFIX_VEX_0F2E,
1123   PREFIX_VEX_0F2F,
1124   PREFIX_VEX_0F41,
1125   PREFIX_VEX_0F42,
1126   PREFIX_VEX_0F44,
1127   PREFIX_VEX_0F45,
1128   PREFIX_VEX_0F46,
1129   PREFIX_VEX_0F47,
1130   PREFIX_VEX_0F4A,
1131   PREFIX_VEX_0F4B,
1132   PREFIX_VEX_0F51,
1133   PREFIX_VEX_0F52,
1134   PREFIX_VEX_0F53,
1135   PREFIX_VEX_0F58,
1136   PREFIX_VEX_0F59,
1137   PREFIX_VEX_0F5A,
1138   PREFIX_VEX_0F5B,
1139   PREFIX_VEX_0F5C,
1140   PREFIX_VEX_0F5D,
1141   PREFIX_VEX_0F5E,
1142   PREFIX_VEX_0F5F,
1143   PREFIX_VEX_0F60,
1144   PREFIX_VEX_0F61,
1145   PREFIX_VEX_0F62,
1146   PREFIX_VEX_0F63,
1147   PREFIX_VEX_0F64,
1148   PREFIX_VEX_0F65,
1149   PREFIX_VEX_0F66,
1150   PREFIX_VEX_0F67,
1151   PREFIX_VEX_0F68,
1152   PREFIX_VEX_0F69,
1153   PREFIX_VEX_0F6A,
1154   PREFIX_VEX_0F6B,
1155   PREFIX_VEX_0F6C,
1156   PREFIX_VEX_0F6D,
1157   PREFIX_VEX_0F6E,
1158   PREFIX_VEX_0F6F,
1159   PREFIX_VEX_0F70,
1160   PREFIX_VEX_0F71_REG_2,
1161   PREFIX_VEX_0F71_REG_4,
1162   PREFIX_VEX_0F71_REG_6,
1163   PREFIX_VEX_0F72_REG_2,
1164   PREFIX_VEX_0F72_REG_4,
1165   PREFIX_VEX_0F72_REG_6,
1166   PREFIX_VEX_0F73_REG_2,
1167   PREFIX_VEX_0F73_REG_3,
1168   PREFIX_VEX_0F73_REG_6,
1169   PREFIX_VEX_0F73_REG_7,
1170   PREFIX_VEX_0F74,
1171   PREFIX_VEX_0F75,
1172   PREFIX_VEX_0F76,
1173   PREFIX_VEX_0F77,
1174   PREFIX_VEX_0F7C,
1175   PREFIX_VEX_0F7D,
1176   PREFIX_VEX_0F7E,
1177   PREFIX_VEX_0F7F,
1178   PREFIX_VEX_0F90,
1179   PREFIX_VEX_0F91,
1180   PREFIX_VEX_0F92,
1181   PREFIX_VEX_0F93,
1182   PREFIX_VEX_0F98,
1183   PREFIX_VEX_0F99,
1184   PREFIX_VEX_0FC2,
1185   PREFIX_VEX_0FC4,
1186   PREFIX_VEX_0FC5,
1187   PREFIX_VEX_0FD0,
1188   PREFIX_VEX_0FD1,
1189   PREFIX_VEX_0FD2,
1190   PREFIX_VEX_0FD3,
1191   PREFIX_VEX_0FD4,
1192   PREFIX_VEX_0FD5,
1193   PREFIX_VEX_0FD6,
1194   PREFIX_VEX_0FD7,
1195   PREFIX_VEX_0FD8,
1196   PREFIX_VEX_0FD9,
1197   PREFIX_VEX_0FDA,
1198   PREFIX_VEX_0FDB,
1199   PREFIX_VEX_0FDC,
1200   PREFIX_VEX_0FDD,
1201   PREFIX_VEX_0FDE,
1202   PREFIX_VEX_0FDF,
1203   PREFIX_VEX_0FE0,
1204   PREFIX_VEX_0FE1,
1205   PREFIX_VEX_0FE2,
1206   PREFIX_VEX_0FE3,
1207   PREFIX_VEX_0FE4,
1208   PREFIX_VEX_0FE5,
1209   PREFIX_VEX_0FE6,
1210   PREFIX_VEX_0FE7,
1211   PREFIX_VEX_0FE8,
1212   PREFIX_VEX_0FE9,
1213   PREFIX_VEX_0FEA,
1214   PREFIX_VEX_0FEB,
1215   PREFIX_VEX_0FEC,
1216   PREFIX_VEX_0FED,
1217   PREFIX_VEX_0FEE,
1218   PREFIX_VEX_0FEF,
1219   PREFIX_VEX_0FF0,
1220   PREFIX_VEX_0FF1,
1221   PREFIX_VEX_0FF2,
1222   PREFIX_VEX_0FF3,
1223   PREFIX_VEX_0FF4,
1224   PREFIX_VEX_0FF5,
1225   PREFIX_VEX_0FF6,
1226   PREFIX_VEX_0FF7,
1227   PREFIX_VEX_0FF8,
1228   PREFIX_VEX_0FF9,
1229   PREFIX_VEX_0FFA,
1230   PREFIX_VEX_0FFB,
1231   PREFIX_VEX_0FFC,
1232   PREFIX_VEX_0FFD,
1233   PREFIX_VEX_0FFE,
1234   PREFIX_VEX_0F3800,
1235   PREFIX_VEX_0F3801,
1236   PREFIX_VEX_0F3802,
1237   PREFIX_VEX_0F3803,
1238   PREFIX_VEX_0F3804,
1239   PREFIX_VEX_0F3805,
1240   PREFIX_VEX_0F3806,
1241   PREFIX_VEX_0F3807,
1242   PREFIX_VEX_0F3808,
1243   PREFIX_VEX_0F3809,
1244   PREFIX_VEX_0F380A,
1245   PREFIX_VEX_0F380B,
1246   PREFIX_VEX_0F380C,
1247   PREFIX_VEX_0F380D,
1248   PREFIX_VEX_0F380E,
1249   PREFIX_VEX_0F380F,
1250   PREFIX_VEX_0F3813,
1251   PREFIX_VEX_0F3816,
1252   PREFIX_VEX_0F3817,
1253   PREFIX_VEX_0F3818,
1254   PREFIX_VEX_0F3819,
1255   PREFIX_VEX_0F381A,
1256   PREFIX_VEX_0F381C,
1257   PREFIX_VEX_0F381D,
1258   PREFIX_VEX_0F381E,
1259   PREFIX_VEX_0F3820,
1260   PREFIX_VEX_0F3821,
1261   PREFIX_VEX_0F3822,
1262   PREFIX_VEX_0F3823,
1263   PREFIX_VEX_0F3824,
1264   PREFIX_VEX_0F3825,
1265   PREFIX_VEX_0F3828,
1266   PREFIX_VEX_0F3829,
1267   PREFIX_VEX_0F382A,
1268   PREFIX_VEX_0F382B,
1269   PREFIX_VEX_0F382C,
1270   PREFIX_VEX_0F382D,
1271   PREFIX_VEX_0F382E,
1272   PREFIX_VEX_0F382F,
1273   PREFIX_VEX_0F3830,
1274   PREFIX_VEX_0F3831,
1275   PREFIX_VEX_0F3832,
1276   PREFIX_VEX_0F3833,
1277   PREFIX_VEX_0F3834,
1278   PREFIX_VEX_0F3835,
1279   PREFIX_VEX_0F3836,
1280   PREFIX_VEX_0F3837,
1281   PREFIX_VEX_0F3838,
1282   PREFIX_VEX_0F3839,
1283   PREFIX_VEX_0F383A,
1284   PREFIX_VEX_0F383B,
1285   PREFIX_VEX_0F383C,
1286   PREFIX_VEX_0F383D,
1287   PREFIX_VEX_0F383E,
1288   PREFIX_VEX_0F383F,
1289   PREFIX_VEX_0F3840,
1290   PREFIX_VEX_0F3841,
1291   PREFIX_VEX_0F3845,
1292   PREFIX_VEX_0F3846,
1293   PREFIX_VEX_0F3847,
1294   PREFIX_VEX_0F3858,
1295   PREFIX_VEX_0F3859,
1296   PREFIX_VEX_0F385A,
1297   PREFIX_VEX_0F3878,
1298   PREFIX_VEX_0F3879,
1299   PREFIX_VEX_0F388C,
1300   PREFIX_VEX_0F388E,
1301   PREFIX_VEX_0F3890,
1302   PREFIX_VEX_0F3891,
1303   PREFIX_VEX_0F3892,
1304   PREFIX_VEX_0F3893,
1305   PREFIX_VEX_0F3896,
1306   PREFIX_VEX_0F3897,
1307   PREFIX_VEX_0F3898,
1308   PREFIX_VEX_0F3899,
1309   PREFIX_VEX_0F389A,
1310   PREFIX_VEX_0F389B,
1311   PREFIX_VEX_0F389C,
1312   PREFIX_VEX_0F389D,
1313   PREFIX_VEX_0F389E,
1314   PREFIX_VEX_0F389F,
1315   PREFIX_VEX_0F38A6,
1316   PREFIX_VEX_0F38A7,
1317   PREFIX_VEX_0F38A8,
1318   PREFIX_VEX_0F38A9,
1319   PREFIX_VEX_0F38AA,
1320   PREFIX_VEX_0F38AB,
1321   PREFIX_VEX_0F38AC,
1322   PREFIX_VEX_0F38AD,
1323   PREFIX_VEX_0F38AE,
1324   PREFIX_VEX_0F38AF,
1325   PREFIX_VEX_0F38B6,
1326   PREFIX_VEX_0F38B7,
1327   PREFIX_VEX_0F38B8,
1328   PREFIX_VEX_0F38B9,
1329   PREFIX_VEX_0F38BA,
1330   PREFIX_VEX_0F38BB,
1331   PREFIX_VEX_0F38BC,
1332   PREFIX_VEX_0F38BD,
1333   PREFIX_VEX_0F38BE,
1334   PREFIX_VEX_0F38BF,
1335   PREFIX_VEX_0F38CF,
1336   PREFIX_VEX_0F38DB,
1337   PREFIX_VEX_0F38DC,
1338   PREFIX_VEX_0F38DD,
1339   PREFIX_VEX_0F38DE,
1340   PREFIX_VEX_0F38DF,
1341   PREFIX_VEX_0F38F2,
1342   PREFIX_VEX_0F38F3_REG_1,
1343   PREFIX_VEX_0F38F3_REG_2,
1344   PREFIX_VEX_0F38F3_REG_3,
1345   PREFIX_VEX_0F38F5,
1346   PREFIX_VEX_0F38F6,
1347   PREFIX_VEX_0F38F7,
1348   PREFIX_VEX_0F3A00,
1349   PREFIX_VEX_0F3A01,
1350   PREFIX_VEX_0F3A02,
1351   PREFIX_VEX_0F3A04,
1352   PREFIX_VEX_0F3A05,
1353   PREFIX_VEX_0F3A06,
1354   PREFIX_VEX_0F3A08,
1355   PREFIX_VEX_0F3A09,
1356   PREFIX_VEX_0F3A0A,
1357   PREFIX_VEX_0F3A0B,
1358   PREFIX_VEX_0F3A0C,
1359   PREFIX_VEX_0F3A0D,
1360   PREFIX_VEX_0F3A0E,
1361   PREFIX_VEX_0F3A0F,
1362   PREFIX_VEX_0F3A14,
1363   PREFIX_VEX_0F3A15,
1364   PREFIX_VEX_0F3A16,
1365   PREFIX_VEX_0F3A17,
1366   PREFIX_VEX_0F3A18,
1367   PREFIX_VEX_0F3A19,
1368   PREFIX_VEX_0F3A1D,
1369   PREFIX_VEX_0F3A20,
1370   PREFIX_VEX_0F3A21,
1371   PREFIX_VEX_0F3A22,
1372   PREFIX_VEX_0F3A30,
1373   PREFIX_VEX_0F3A31,
1374   PREFIX_VEX_0F3A32,
1375   PREFIX_VEX_0F3A33,
1376   PREFIX_VEX_0F3A38,
1377   PREFIX_VEX_0F3A39,
1378   PREFIX_VEX_0F3A40,
1379   PREFIX_VEX_0F3A41,
1380   PREFIX_VEX_0F3A42,
1381   PREFIX_VEX_0F3A44,
1382   PREFIX_VEX_0F3A46,
1383   PREFIX_VEX_0F3A48,
1384   PREFIX_VEX_0F3A49,
1385   PREFIX_VEX_0F3A4A,
1386   PREFIX_VEX_0F3A4B,
1387   PREFIX_VEX_0F3A4C,
1388   PREFIX_VEX_0F3A5C,
1389   PREFIX_VEX_0F3A5D,
1390   PREFIX_VEX_0F3A5E,
1391   PREFIX_VEX_0F3A5F,
1392   PREFIX_VEX_0F3A60,
1393   PREFIX_VEX_0F3A61,
1394   PREFIX_VEX_0F3A62,
1395   PREFIX_VEX_0F3A63,
1396   PREFIX_VEX_0F3A68,
1397   PREFIX_VEX_0F3A69,
1398   PREFIX_VEX_0F3A6A,
1399   PREFIX_VEX_0F3A6B,
1400   PREFIX_VEX_0F3A6C,
1401   PREFIX_VEX_0F3A6D,
1402   PREFIX_VEX_0F3A6E,
1403   PREFIX_VEX_0F3A6F,
1404   PREFIX_VEX_0F3A78,
1405   PREFIX_VEX_0F3A79,
1406   PREFIX_VEX_0F3A7A,
1407   PREFIX_VEX_0F3A7B,
1408   PREFIX_VEX_0F3A7C,
1409   PREFIX_VEX_0F3A7D,
1410   PREFIX_VEX_0F3A7E,
1411   PREFIX_VEX_0F3A7F,
1412   PREFIX_VEX_0F3ACE,
1413   PREFIX_VEX_0F3ACF,
1414   PREFIX_VEX_0F3ADF,
1415   PREFIX_VEX_0F3AF0,
1416
1417   PREFIX_EVEX_0F10,
1418   PREFIX_EVEX_0F11,
1419   PREFIX_EVEX_0F12,
1420   PREFIX_EVEX_0F16,
1421   PREFIX_EVEX_0F2A,
1422   PREFIX_EVEX_0F2C,
1423   PREFIX_EVEX_0F2D,
1424   PREFIX_EVEX_0F2E,
1425   PREFIX_EVEX_0F2F,
1426   PREFIX_EVEX_0F51,
1427   PREFIX_EVEX_0F58,
1428   PREFIX_EVEX_0F59,
1429   PREFIX_EVEX_0F5A,
1430   PREFIX_EVEX_0F5B,
1431   PREFIX_EVEX_0F5C,
1432   PREFIX_EVEX_0F5D,
1433   PREFIX_EVEX_0F5E,
1434   PREFIX_EVEX_0F5F,
1435   PREFIX_EVEX_0F64,
1436   PREFIX_EVEX_0F65,
1437   PREFIX_EVEX_0F66,
1438   PREFIX_EVEX_0F6E,
1439   PREFIX_EVEX_0F6F,
1440   PREFIX_EVEX_0F70,
1441   PREFIX_EVEX_0F71_REG_2,
1442   PREFIX_EVEX_0F71_REG_4,
1443   PREFIX_EVEX_0F71_REG_6,
1444   PREFIX_EVEX_0F72_REG_0,
1445   PREFIX_EVEX_0F72_REG_1,
1446   PREFIX_EVEX_0F72_REG_2,
1447   PREFIX_EVEX_0F72_REG_4,
1448   PREFIX_EVEX_0F72_REG_6,
1449   PREFIX_EVEX_0F73_REG_2,
1450   PREFIX_EVEX_0F73_REG_3,
1451   PREFIX_EVEX_0F73_REG_6,
1452   PREFIX_EVEX_0F73_REG_7,
1453   PREFIX_EVEX_0F74,
1454   PREFIX_EVEX_0F75,
1455   PREFIX_EVEX_0F76,
1456   PREFIX_EVEX_0F78,
1457   PREFIX_EVEX_0F79,
1458   PREFIX_EVEX_0F7A,
1459   PREFIX_EVEX_0F7B,
1460   PREFIX_EVEX_0F7E,
1461   PREFIX_EVEX_0F7F,
1462   PREFIX_EVEX_0FC2,
1463   PREFIX_EVEX_0FC4,
1464   PREFIX_EVEX_0FC5,
1465   PREFIX_EVEX_0FD6,
1466   PREFIX_EVEX_0FDB,
1467   PREFIX_EVEX_0FDF,
1468   PREFIX_EVEX_0FE2,
1469   PREFIX_EVEX_0FE6,
1470   PREFIX_EVEX_0FE7,
1471   PREFIX_EVEX_0FEB,
1472   PREFIX_EVEX_0FEF,
1473   PREFIX_EVEX_0F380D,
1474   PREFIX_EVEX_0F3810,
1475   PREFIX_EVEX_0F3811,
1476   PREFIX_EVEX_0F3812,
1477   PREFIX_EVEX_0F3813,
1478   PREFIX_EVEX_0F3814,
1479   PREFIX_EVEX_0F3815,
1480   PREFIX_EVEX_0F3816,
1481   PREFIX_EVEX_0F3819,
1482   PREFIX_EVEX_0F381A,
1483   PREFIX_EVEX_0F381B,
1484   PREFIX_EVEX_0F381E,
1485   PREFIX_EVEX_0F381F,
1486   PREFIX_EVEX_0F3820,
1487   PREFIX_EVEX_0F3821,
1488   PREFIX_EVEX_0F3822,
1489   PREFIX_EVEX_0F3823,
1490   PREFIX_EVEX_0F3824,
1491   PREFIX_EVEX_0F3825,
1492   PREFIX_EVEX_0F3826,
1493   PREFIX_EVEX_0F3827,
1494   PREFIX_EVEX_0F3828,
1495   PREFIX_EVEX_0F3829,
1496   PREFIX_EVEX_0F382A,
1497   PREFIX_EVEX_0F382C,
1498   PREFIX_EVEX_0F382D,
1499   PREFIX_EVEX_0F3830,
1500   PREFIX_EVEX_0F3831,
1501   PREFIX_EVEX_0F3832,
1502   PREFIX_EVEX_0F3833,
1503   PREFIX_EVEX_0F3834,
1504   PREFIX_EVEX_0F3835,
1505   PREFIX_EVEX_0F3836,
1506   PREFIX_EVEX_0F3837,
1507   PREFIX_EVEX_0F3838,
1508   PREFIX_EVEX_0F3839,
1509   PREFIX_EVEX_0F383A,
1510   PREFIX_EVEX_0F383B,
1511   PREFIX_EVEX_0F383D,
1512   PREFIX_EVEX_0F383F,
1513   PREFIX_EVEX_0F3840,
1514   PREFIX_EVEX_0F3842,
1515   PREFIX_EVEX_0F3843,
1516   PREFIX_EVEX_0F3844,
1517   PREFIX_EVEX_0F3845,
1518   PREFIX_EVEX_0F3846,
1519   PREFIX_EVEX_0F3847,
1520   PREFIX_EVEX_0F384C,
1521   PREFIX_EVEX_0F384D,
1522   PREFIX_EVEX_0F384E,
1523   PREFIX_EVEX_0F384F,
1524   PREFIX_EVEX_0F3850,
1525   PREFIX_EVEX_0F3851,
1526   PREFIX_EVEX_0F3852,
1527   PREFIX_EVEX_0F3853,
1528   PREFIX_EVEX_0F3854,
1529   PREFIX_EVEX_0F3855,
1530   PREFIX_EVEX_0F3859,
1531   PREFIX_EVEX_0F385A,
1532   PREFIX_EVEX_0F385B,
1533   PREFIX_EVEX_0F3862,
1534   PREFIX_EVEX_0F3863,
1535   PREFIX_EVEX_0F3864,
1536   PREFIX_EVEX_0F3865,
1537   PREFIX_EVEX_0F3866,
1538   PREFIX_EVEX_0F3868,
1539   PREFIX_EVEX_0F3870,
1540   PREFIX_EVEX_0F3871,
1541   PREFIX_EVEX_0F3872,
1542   PREFIX_EVEX_0F3873,
1543   PREFIX_EVEX_0F3875,
1544   PREFIX_EVEX_0F3876,
1545   PREFIX_EVEX_0F3877,
1546   PREFIX_EVEX_0F387A,
1547   PREFIX_EVEX_0F387B,
1548   PREFIX_EVEX_0F387C,
1549   PREFIX_EVEX_0F387D,
1550   PREFIX_EVEX_0F387E,
1551   PREFIX_EVEX_0F387F,
1552   PREFIX_EVEX_0F3883,
1553   PREFIX_EVEX_0F3888,
1554   PREFIX_EVEX_0F3889,
1555   PREFIX_EVEX_0F388A,
1556   PREFIX_EVEX_0F388B,
1557   PREFIX_EVEX_0F388D,
1558   PREFIX_EVEX_0F388F,
1559   PREFIX_EVEX_0F3890,
1560   PREFIX_EVEX_0F3891,
1561   PREFIX_EVEX_0F3892,
1562   PREFIX_EVEX_0F3893,
1563   PREFIX_EVEX_0F389A,
1564   PREFIX_EVEX_0F389B,
1565   PREFIX_EVEX_0F38A0,
1566   PREFIX_EVEX_0F38A1,
1567   PREFIX_EVEX_0F38A2,
1568   PREFIX_EVEX_0F38A3,
1569   PREFIX_EVEX_0F38AA,
1570   PREFIX_EVEX_0F38AB,
1571   PREFIX_EVEX_0F38B4,
1572   PREFIX_EVEX_0F38B5,
1573   PREFIX_EVEX_0F38C4,
1574   PREFIX_EVEX_0F38C6_REG_1,
1575   PREFIX_EVEX_0F38C6_REG_2,
1576   PREFIX_EVEX_0F38C6_REG_5,
1577   PREFIX_EVEX_0F38C6_REG_6,
1578   PREFIX_EVEX_0F38C7_REG_1,
1579   PREFIX_EVEX_0F38C7_REG_2,
1580   PREFIX_EVEX_0F38C7_REG_5,
1581   PREFIX_EVEX_0F38C7_REG_6,
1582   PREFIX_EVEX_0F38C8,
1583   PREFIX_EVEX_0F38CA,
1584   PREFIX_EVEX_0F38CB,
1585   PREFIX_EVEX_0F38CC,
1586   PREFIX_EVEX_0F38CD,
1587
1588   PREFIX_EVEX_0F3A00,
1589   PREFIX_EVEX_0F3A01,
1590   PREFIX_EVEX_0F3A03,
1591   PREFIX_EVEX_0F3A05,
1592   PREFIX_EVEX_0F3A08,
1593   PREFIX_EVEX_0F3A09,
1594   PREFIX_EVEX_0F3A0A,
1595   PREFIX_EVEX_0F3A0B,
1596   PREFIX_EVEX_0F3A14,
1597   PREFIX_EVEX_0F3A15,
1598   PREFIX_EVEX_0F3A16,
1599   PREFIX_EVEX_0F3A17,
1600   PREFIX_EVEX_0F3A18,
1601   PREFIX_EVEX_0F3A19,
1602   PREFIX_EVEX_0F3A1A,
1603   PREFIX_EVEX_0F3A1B,
1604   PREFIX_EVEX_0F3A1E,
1605   PREFIX_EVEX_0F3A1F,
1606   PREFIX_EVEX_0F3A20,
1607   PREFIX_EVEX_0F3A21,
1608   PREFIX_EVEX_0F3A22,
1609   PREFIX_EVEX_0F3A23,
1610   PREFIX_EVEX_0F3A25,
1611   PREFIX_EVEX_0F3A26,
1612   PREFIX_EVEX_0F3A27,
1613   PREFIX_EVEX_0F3A38,
1614   PREFIX_EVEX_0F3A39,
1615   PREFIX_EVEX_0F3A3A,
1616   PREFIX_EVEX_0F3A3B,
1617   PREFIX_EVEX_0F3A3E,
1618   PREFIX_EVEX_0F3A3F,
1619   PREFIX_EVEX_0F3A42,
1620   PREFIX_EVEX_0F3A43,
1621   PREFIX_EVEX_0F3A50,
1622   PREFIX_EVEX_0F3A51,
1623   PREFIX_EVEX_0F3A54,
1624   PREFIX_EVEX_0F3A55,
1625   PREFIX_EVEX_0F3A56,
1626   PREFIX_EVEX_0F3A57,
1627   PREFIX_EVEX_0F3A66,
1628   PREFIX_EVEX_0F3A67,
1629   PREFIX_EVEX_0F3A70,
1630   PREFIX_EVEX_0F3A71,
1631   PREFIX_EVEX_0F3A72,
1632   PREFIX_EVEX_0F3A73,
1633 };
1634
1635 enum
1636 {
1637   X86_64_06 = 0,
1638   X86_64_07,
1639   X86_64_0E,
1640   X86_64_16,
1641   X86_64_17,
1642   X86_64_1E,
1643   X86_64_1F,
1644   X86_64_27,
1645   X86_64_2F,
1646   X86_64_37,
1647   X86_64_3F,
1648   X86_64_60,
1649   X86_64_61,
1650   X86_64_62,
1651   X86_64_63,
1652   X86_64_6D,
1653   X86_64_6F,
1654   X86_64_82,
1655   X86_64_9A,
1656   X86_64_C2,
1657   X86_64_C3,
1658   X86_64_C4,
1659   X86_64_C5,
1660   X86_64_CE,
1661   X86_64_D4,
1662   X86_64_D5,
1663   X86_64_E8,
1664   X86_64_E9,
1665   X86_64_EA,
1666   X86_64_0F01_REG_0,
1667   X86_64_0F01_REG_1,
1668   X86_64_0F01_REG_2,
1669   X86_64_0F01_REG_3
1670 };
1671
1672 enum
1673 {
1674   THREE_BYTE_0F38 = 0,
1675   THREE_BYTE_0F3A
1676 };
1677
1678 enum
1679 {
1680   XOP_08 = 0,
1681   XOP_09,
1682   XOP_0A
1683 };
1684
1685 enum
1686 {
1687   VEX_0F = 0,
1688   VEX_0F38,
1689   VEX_0F3A
1690 };
1691
1692 enum
1693 {
1694   EVEX_0F = 0,
1695   EVEX_0F38,
1696   EVEX_0F3A
1697 };
1698
1699 enum
1700 {
1701   VEX_LEN_0F12_P_0_M_0 = 0,
1702   VEX_LEN_0F12_P_0_M_1,
1703 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1704   VEX_LEN_0F13_M_0,
1705   VEX_LEN_0F16_P_0_M_0,
1706   VEX_LEN_0F16_P_0_M_1,
1707 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1708   VEX_LEN_0F17_M_0,
1709   VEX_LEN_0F41_P_0,
1710   VEX_LEN_0F41_P_2,
1711   VEX_LEN_0F42_P_0,
1712   VEX_LEN_0F42_P_2,
1713   VEX_LEN_0F44_P_0,
1714   VEX_LEN_0F44_P_2,
1715   VEX_LEN_0F45_P_0,
1716   VEX_LEN_0F45_P_2,
1717   VEX_LEN_0F46_P_0,
1718   VEX_LEN_0F46_P_2,
1719   VEX_LEN_0F47_P_0,
1720   VEX_LEN_0F47_P_2,
1721   VEX_LEN_0F4A_P_0,
1722   VEX_LEN_0F4A_P_2,
1723   VEX_LEN_0F4B_P_0,
1724   VEX_LEN_0F4B_P_2,
1725   VEX_LEN_0F6E_P_2,
1726   VEX_LEN_0F77_P_0,
1727   VEX_LEN_0F7E_P_1,
1728   VEX_LEN_0F7E_P_2,
1729   VEX_LEN_0F90_P_0,
1730   VEX_LEN_0F90_P_2,
1731   VEX_LEN_0F91_P_0,
1732   VEX_LEN_0F91_P_2,
1733   VEX_LEN_0F92_P_0,
1734   VEX_LEN_0F92_P_2,
1735   VEX_LEN_0F92_P_3,
1736   VEX_LEN_0F93_P_0,
1737   VEX_LEN_0F93_P_2,
1738   VEX_LEN_0F93_P_3,
1739   VEX_LEN_0F98_P_0,
1740   VEX_LEN_0F98_P_2,
1741   VEX_LEN_0F99_P_0,
1742   VEX_LEN_0F99_P_2,
1743   VEX_LEN_0FAE_R_2_M_0,
1744   VEX_LEN_0FAE_R_3_M_0,
1745   VEX_LEN_0FC4_P_2,
1746   VEX_LEN_0FC5_P_2,
1747   VEX_LEN_0FD6_P_2,
1748   VEX_LEN_0FF7_P_2,
1749   VEX_LEN_0F3816_P_2,
1750   VEX_LEN_0F3819_P_2,
1751   VEX_LEN_0F381A_P_2_M_0,
1752   VEX_LEN_0F3836_P_2,
1753   VEX_LEN_0F3841_P_2,
1754   VEX_LEN_0F385A_P_2_M_0,
1755   VEX_LEN_0F38DB_P_2,
1756   VEX_LEN_0F38F2_P_0,
1757   VEX_LEN_0F38F3_R_1_P_0,
1758   VEX_LEN_0F38F3_R_2_P_0,
1759   VEX_LEN_0F38F3_R_3_P_0,
1760   VEX_LEN_0F38F5_P_0,
1761   VEX_LEN_0F38F5_P_1,
1762   VEX_LEN_0F38F5_P_3,
1763   VEX_LEN_0F38F6_P_3,
1764   VEX_LEN_0F38F7_P_0,
1765   VEX_LEN_0F38F7_P_1,
1766   VEX_LEN_0F38F7_P_2,
1767   VEX_LEN_0F38F7_P_3,
1768   VEX_LEN_0F3A00_P_2,
1769   VEX_LEN_0F3A01_P_2,
1770   VEX_LEN_0F3A06_P_2,
1771   VEX_LEN_0F3A14_P_2,
1772   VEX_LEN_0F3A15_P_2,
1773   VEX_LEN_0F3A16_P_2,
1774   VEX_LEN_0F3A17_P_2,
1775   VEX_LEN_0F3A18_P_2,
1776   VEX_LEN_0F3A19_P_2,
1777   VEX_LEN_0F3A20_P_2,
1778   VEX_LEN_0F3A21_P_2,
1779   VEX_LEN_0F3A22_P_2,
1780   VEX_LEN_0F3A30_P_2,
1781   VEX_LEN_0F3A31_P_2,
1782   VEX_LEN_0F3A32_P_2,
1783   VEX_LEN_0F3A33_P_2,
1784   VEX_LEN_0F3A38_P_2,
1785   VEX_LEN_0F3A39_P_2,
1786   VEX_LEN_0F3A41_P_2,
1787   VEX_LEN_0F3A46_P_2,
1788   VEX_LEN_0F3A60_P_2,
1789   VEX_LEN_0F3A61_P_2,
1790   VEX_LEN_0F3A62_P_2,
1791   VEX_LEN_0F3A63_P_2,
1792   VEX_LEN_0F3ADF_P_2,
1793   VEX_LEN_0F3AF0_P_3,
1794   VEX_LEN_0FXOP_08_CC,
1795   VEX_LEN_0FXOP_08_CD,
1796   VEX_LEN_0FXOP_08_CE,
1797   VEX_LEN_0FXOP_08_CF,
1798   VEX_LEN_0FXOP_08_EC,
1799   VEX_LEN_0FXOP_08_ED,
1800   VEX_LEN_0FXOP_08_EE,
1801   VEX_LEN_0FXOP_08_EF,
1802   VEX_LEN_0FXOP_09_82_W_0,
1803   VEX_LEN_0FXOP_09_83_W_0,
1804 };
1805
1806 enum
1807 {
1808   EVEX_LEN_0F6E_P_2 = 0,
1809   EVEX_LEN_0F7E_P_1,
1810   EVEX_LEN_0F7E_P_2,
1811   EVEX_LEN_0FC4_P_2,
1812   EVEX_LEN_0FC5_P_2,
1813   EVEX_LEN_0FD6_P_2,
1814   EVEX_LEN_0F3816_P_2,
1815   EVEX_LEN_0F3819_P_2_W_0,
1816   EVEX_LEN_0F3819_P_2_W_1,
1817   EVEX_LEN_0F381A_P_2_W_0_M_0,
1818   EVEX_LEN_0F381A_P_2_W_1_M_0,
1819   EVEX_LEN_0F381B_P_2_W_0_M_0,
1820   EVEX_LEN_0F381B_P_2_W_1_M_0,
1821   EVEX_LEN_0F3836_P_2,
1822   EVEX_LEN_0F385A_P_2_W_0_M_0,
1823   EVEX_LEN_0F385A_P_2_W_1_M_0,
1824   EVEX_LEN_0F385B_P_2_W_0_M_0,
1825   EVEX_LEN_0F385B_P_2_W_1_M_0,
1826   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1827   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1828   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1829   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1830   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1831   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1832   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1833   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1834   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1835   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1836   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1837   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1838   EVEX_LEN_0F3A00_P_2_W_1,
1839   EVEX_LEN_0F3A01_P_2_W_1,
1840   EVEX_LEN_0F3A14_P_2,
1841   EVEX_LEN_0F3A15_P_2,
1842   EVEX_LEN_0F3A16_P_2,
1843   EVEX_LEN_0F3A17_P_2,
1844   EVEX_LEN_0F3A18_P_2_W_0,
1845   EVEX_LEN_0F3A18_P_2_W_1,
1846   EVEX_LEN_0F3A19_P_2_W_0,
1847   EVEX_LEN_0F3A19_P_2_W_1,
1848   EVEX_LEN_0F3A1A_P_2_W_0,
1849   EVEX_LEN_0F3A1A_P_2_W_1,
1850   EVEX_LEN_0F3A1B_P_2_W_0,
1851   EVEX_LEN_0F3A1B_P_2_W_1,
1852   EVEX_LEN_0F3A20_P_2,
1853   EVEX_LEN_0F3A21_P_2_W_0,
1854   EVEX_LEN_0F3A22_P_2,
1855   EVEX_LEN_0F3A23_P_2_W_0,
1856   EVEX_LEN_0F3A23_P_2_W_1,
1857   EVEX_LEN_0F3A38_P_2_W_0,
1858   EVEX_LEN_0F3A38_P_2_W_1,
1859   EVEX_LEN_0F3A39_P_2_W_0,
1860   EVEX_LEN_0F3A39_P_2_W_1,
1861   EVEX_LEN_0F3A3A_P_2_W_0,
1862   EVEX_LEN_0F3A3A_P_2_W_1,
1863   EVEX_LEN_0F3A3B_P_2_W_0,
1864   EVEX_LEN_0F3A3B_P_2_W_1,
1865   EVEX_LEN_0F3A43_P_2_W_0,
1866   EVEX_LEN_0F3A43_P_2_W_1
1867 };
1868
1869 enum
1870 {
1871   VEX_W_0F41_P_0_LEN_1 = 0,
1872   VEX_W_0F41_P_2_LEN_1,
1873   VEX_W_0F42_P_0_LEN_1,
1874   VEX_W_0F42_P_2_LEN_1,
1875   VEX_W_0F44_P_0_LEN_0,
1876   VEX_W_0F44_P_2_LEN_0,
1877   VEX_W_0F45_P_0_LEN_1,
1878   VEX_W_0F45_P_2_LEN_1,
1879   VEX_W_0F46_P_0_LEN_1,
1880   VEX_W_0F46_P_2_LEN_1,
1881   VEX_W_0F47_P_0_LEN_1,
1882   VEX_W_0F47_P_2_LEN_1,
1883   VEX_W_0F4A_P_0_LEN_1,
1884   VEX_W_0F4A_P_2_LEN_1,
1885   VEX_W_0F4B_P_0_LEN_1,
1886   VEX_W_0F4B_P_2_LEN_1,
1887   VEX_W_0F90_P_0_LEN_0,
1888   VEX_W_0F90_P_2_LEN_0,
1889   VEX_W_0F91_P_0_LEN_0,
1890   VEX_W_0F91_P_2_LEN_0,
1891   VEX_W_0F92_P_0_LEN_0,
1892   VEX_W_0F92_P_2_LEN_0,
1893   VEX_W_0F93_P_0_LEN_0,
1894   VEX_W_0F93_P_2_LEN_0,
1895   VEX_W_0F98_P_0_LEN_0,
1896   VEX_W_0F98_P_2_LEN_0,
1897   VEX_W_0F99_P_0_LEN_0,
1898   VEX_W_0F99_P_2_LEN_0,
1899   VEX_W_0F380C_P_2,
1900   VEX_W_0F380D_P_2,
1901   VEX_W_0F380E_P_2,
1902   VEX_W_0F380F_P_2,
1903   VEX_W_0F3813_P_2,
1904   VEX_W_0F3816_P_2,
1905   VEX_W_0F3818_P_2,
1906   VEX_W_0F3819_P_2,
1907   VEX_W_0F381A_P_2_M_0,
1908   VEX_W_0F382C_P_2_M_0,
1909   VEX_W_0F382D_P_2_M_0,
1910   VEX_W_0F382E_P_2_M_0,
1911   VEX_W_0F382F_P_2_M_0,
1912   VEX_W_0F3836_P_2,
1913   VEX_W_0F3846_P_2,
1914   VEX_W_0F3858_P_2,
1915   VEX_W_0F3859_P_2,
1916   VEX_W_0F385A_P_2_M_0,
1917   VEX_W_0F3878_P_2,
1918   VEX_W_0F3879_P_2,
1919   VEX_W_0F38CF_P_2,
1920   VEX_W_0F3A00_P_2,
1921   VEX_W_0F3A01_P_2,
1922   VEX_W_0F3A02_P_2,
1923   VEX_W_0F3A04_P_2,
1924   VEX_W_0F3A05_P_2,
1925   VEX_W_0F3A06_P_2,
1926   VEX_W_0F3A18_P_2,
1927   VEX_W_0F3A19_P_2,
1928   VEX_W_0F3A1D_P_2,
1929   VEX_W_0F3A30_P_2_LEN_0,
1930   VEX_W_0F3A31_P_2_LEN_0,
1931   VEX_W_0F3A32_P_2_LEN_0,
1932   VEX_W_0F3A33_P_2_LEN_0,
1933   VEX_W_0F3A38_P_2,
1934   VEX_W_0F3A39_P_2,
1935   VEX_W_0F3A46_P_2,
1936   VEX_W_0F3A4A_P_2,
1937   VEX_W_0F3A4B_P_2,
1938   VEX_W_0F3A4C_P_2,
1939   VEX_W_0F3ACE_P_2,
1940   VEX_W_0F3ACF_P_2,
1941
1942   VEX_W_0FXOP_09_80,
1943   VEX_W_0FXOP_09_81,
1944   VEX_W_0FXOP_09_82,
1945   VEX_W_0FXOP_09_83,
1946
1947   EVEX_W_0F10_P_1,
1948   EVEX_W_0F10_P_3,
1949   EVEX_W_0F11_P_1,
1950   EVEX_W_0F11_P_3,
1951   EVEX_W_0F12_P_0_M_1,
1952   EVEX_W_0F12_P_1,
1953   EVEX_W_0F12_P_3,
1954   EVEX_W_0F16_P_0_M_1,
1955   EVEX_W_0F16_P_1,
1956   EVEX_W_0F2A_P_3,
1957   EVEX_W_0F51_P_1,
1958   EVEX_W_0F51_P_3,
1959   EVEX_W_0F58_P_1,
1960   EVEX_W_0F58_P_3,
1961   EVEX_W_0F59_P_1,
1962   EVEX_W_0F59_P_3,
1963   EVEX_W_0F5A_P_0,
1964   EVEX_W_0F5A_P_1,
1965   EVEX_W_0F5A_P_2,
1966   EVEX_W_0F5A_P_3,
1967   EVEX_W_0F5B_P_0,
1968   EVEX_W_0F5B_P_1,
1969   EVEX_W_0F5B_P_2,
1970   EVEX_W_0F5C_P_1,
1971   EVEX_W_0F5C_P_3,
1972   EVEX_W_0F5D_P_1,
1973   EVEX_W_0F5D_P_3,
1974   EVEX_W_0F5E_P_1,
1975   EVEX_W_0F5E_P_3,
1976   EVEX_W_0F5F_P_1,
1977   EVEX_W_0F5F_P_3,
1978   EVEX_W_0F62,
1979   EVEX_W_0F66_P_2,
1980   EVEX_W_0F6A,
1981   EVEX_W_0F6B,
1982   EVEX_W_0F6C,
1983   EVEX_W_0F6D,
1984   EVEX_W_0F6F_P_1,
1985   EVEX_W_0F6F_P_2,
1986   EVEX_W_0F6F_P_3,
1987   EVEX_W_0F70_P_2,
1988   EVEX_W_0F72_R_2_P_2,
1989   EVEX_W_0F72_R_6_P_2,
1990   EVEX_W_0F73_R_2_P_2,
1991   EVEX_W_0F73_R_6_P_2,
1992   EVEX_W_0F76_P_2,
1993   EVEX_W_0F78_P_0,
1994   EVEX_W_0F78_P_2,
1995   EVEX_W_0F79_P_0,
1996   EVEX_W_0F79_P_2,
1997   EVEX_W_0F7A_P_1,
1998   EVEX_W_0F7A_P_2,
1999   EVEX_W_0F7A_P_3,
2000   EVEX_W_0F7B_P_2,
2001   EVEX_W_0F7B_P_3,
2002   EVEX_W_0F7E_P_1,
2003   EVEX_W_0F7F_P_1,
2004   EVEX_W_0F7F_P_2,
2005   EVEX_W_0F7F_P_3,
2006   EVEX_W_0FC2_P_1,
2007   EVEX_W_0FC2_P_3,
2008   EVEX_W_0FD2,
2009   EVEX_W_0FD3,
2010   EVEX_W_0FD4,
2011   EVEX_W_0FD6_P_2,
2012   EVEX_W_0FE6_P_1,
2013   EVEX_W_0FE6_P_2,
2014   EVEX_W_0FE6_P_3,
2015   EVEX_W_0FE7_P_2,
2016   EVEX_W_0FF2,
2017   EVEX_W_0FF3,
2018   EVEX_W_0FF4,
2019   EVEX_W_0FFA,
2020   EVEX_W_0FFB,
2021   EVEX_W_0FFE,
2022   EVEX_W_0F380D_P_2,
2023   EVEX_W_0F3810_P_1,
2024   EVEX_W_0F3810_P_2,
2025   EVEX_W_0F3811_P_1,
2026   EVEX_W_0F3811_P_2,
2027   EVEX_W_0F3812_P_1,
2028   EVEX_W_0F3812_P_2,
2029   EVEX_W_0F3813_P_1,
2030   EVEX_W_0F3813_P_2,
2031   EVEX_W_0F3814_P_1,
2032   EVEX_W_0F3815_P_1,
2033   EVEX_W_0F3819_P_2,
2034   EVEX_W_0F381A_P_2,
2035   EVEX_W_0F381B_P_2,
2036   EVEX_W_0F381E_P_2,
2037   EVEX_W_0F381F_P_2,
2038   EVEX_W_0F3820_P_1,
2039   EVEX_W_0F3821_P_1,
2040   EVEX_W_0F3822_P_1,
2041   EVEX_W_0F3823_P_1,
2042   EVEX_W_0F3824_P_1,
2043   EVEX_W_0F3825_P_1,
2044   EVEX_W_0F3825_P_2,
2045   EVEX_W_0F3828_P_2,
2046   EVEX_W_0F3829_P_2,
2047   EVEX_W_0F382A_P_1,
2048   EVEX_W_0F382A_P_2,
2049   EVEX_W_0F382B,
2050   EVEX_W_0F3830_P_1,
2051   EVEX_W_0F3831_P_1,
2052   EVEX_W_0F3832_P_1,
2053   EVEX_W_0F3833_P_1,
2054   EVEX_W_0F3834_P_1,
2055   EVEX_W_0F3835_P_1,
2056   EVEX_W_0F3835_P_2,
2057   EVEX_W_0F3837_P_2,
2058   EVEX_W_0F383A_P_1,
2059   EVEX_W_0F3852_P_1,
2060   EVEX_W_0F3859_P_2,
2061   EVEX_W_0F385A_P_2,
2062   EVEX_W_0F385B_P_2,
2063   EVEX_W_0F3862_P_2,
2064   EVEX_W_0F3863_P_2,
2065   EVEX_W_0F3870_P_2,
2066   EVEX_W_0F3872_P_1,
2067   EVEX_W_0F3872_P_2,
2068   EVEX_W_0F3872_P_3,
2069   EVEX_W_0F387A_P_2,
2070   EVEX_W_0F387B_P_2,
2071   EVEX_W_0F3883_P_2,
2072   EVEX_W_0F3891_P_2,
2073   EVEX_W_0F3893_P_2,
2074   EVEX_W_0F38A1_P_2,
2075   EVEX_W_0F38A3_P_2,
2076   EVEX_W_0F38C7_R_1_P_2,
2077   EVEX_W_0F38C7_R_2_P_2,
2078   EVEX_W_0F38C7_R_5_P_2,
2079   EVEX_W_0F38C7_R_6_P_2,
2080
2081   EVEX_W_0F3A00_P_2,
2082   EVEX_W_0F3A01_P_2,
2083   EVEX_W_0F3A05_P_2,
2084   EVEX_W_0F3A08_P_2,
2085   EVEX_W_0F3A09_P_2,
2086   EVEX_W_0F3A0A_P_2,
2087   EVEX_W_0F3A0B_P_2,
2088   EVEX_W_0F3A18_P_2,
2089   EVEX_W_0F3A19_P_2,
2090   EVEX_W_0F3A1A_P_2,
2091   EVEX_W_0F3A1B_P_2,
2092   EVEX_W_0F3A21_P_2,
2093   EVEX_W_0F3A23_P_2,
2094   EVEX_W_0F3A38_P_2,
2095   EVEX_W_0F3A39_P_2,
2096   EVEX_W_0F3A3A_P_2,
2097   EVEX_W_0F3A3B_P_2,
2098   EVEX_W_0F3A42_P_2,
2099   EVEX_W_0F3A43_P_2,
2100   EVEX_W_0F3A70_P_2,
2101   EVEX_W_0F3A72_P_2,
2102 };
2103
2104 typedef void (*op_rtn) (int bytemode, int sizeflag);
2105
2106 struct dis386 {
2107   const char *name;
2108   struct
2109     {
2110       op_rtn rtn;
2111       int bytemode;
2112     } op[MAX_OPERANDS];
2113   unsigned int prefix_requirement;
2114 };
2115
2116 /* Upper case letters in the instruction names here are macros.
2117    'A' => print 'b' if no register operands or suffix_always is true
2118    'B' => print 'b' if suffix_always is true
2119    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2120           size prefix
2121    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2122           suffix_always is true
2123    'E' => print 'e' if 32-bit form of jcxz
2124    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2125    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2126    'H' => print ",pt" or ",pn" branch hint
2127    'I' unused.
2128    'J' unused.
2129    'K' => print 'd' or 'q' if rex prefix is present.
2130    'L' => print 'l' if suffix_always is true
2131    'M' => print 'r' if intel_mnemonic is false.
2132    'N' => print 'n' if instruction has no wait "prefix"
2133    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2134    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2135           or suffix_always is true.  print 'q' if rex prefix is present.
2136    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2137           is true
2138    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2139    'S' => print 'w', 'l' or 'q' if suffix_always is true
2140    'T' => print 'q' in 64bit mode if instruction has no operand size
2141           prefix and behave as 'P' otherwise
2142    'U' => print 'q' in 64bit mode if instruction has no operand size
2143           prefix and behave as 'Q' otherwise
2144    'V' => print 'q' in 64bit mode if instruction has no operand size
2145           prefix and behave as 'S' otherwise
2146    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2147    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2148    'Y' unused.
2149    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2150    '!' => change condition from true to false or from false to true.
2151    '%' => add 1 upper case letter to the macro.
2152    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2153           prefix or suffix_always is true (lcall/ljmp).
2154    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2155           on operand size prefix.
2156    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2157           has no operand size prefix for AMD64 ISA, behave as 'P'
2158           otherwise
2159
2160    2 upper case letter macros:
2161    "XY" => print 'x' or 'y' if suffix_always is true or no register
2162            operands and no broadcast.
2163    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2164            register operands and no broadcast.
2165    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2166    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2167            operand or no operand at all in 64bit mode, or if suffix_always
2168            is true.
2169    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2170    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2171    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2172    "LW" => print 'd', 'q' depending on the VEX.W bit
2173    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2174    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2175            an operand size prefix, or suffix_always is true.  print
2176            'q' if rex prefix is present.
2177
2178    Many of the above letters print nothing in Intel mode.  See "putop"
2179    for the details.
2180
2181    Braces '{' and '}', and vertical bars '|', indicate alternative
2182    mnemonic strings for AT&T and Intel.  */
2183
2184 static const struct dis386 dis386[] = {
2185   /* 00 */
2186   { "addB",             { Ebh1, Gb }, 0 },
2187   { "addS",             { Evh1, Gv }, 0 },
2188   { "addB",             { Gb, EbS }, 0 },
2189   { "addS",             { Gv, EvS }, 0 },
2190   { "addB",             { AL, Ib }, 0 },
2191   { "addS",             { eAX, Iv }, 0 },
2192   { X86_64_TABLE (X86_64_06) },
2193   { X86_64_TABLE (X86_64_07) },
2194   /* 08 */
2195   { "orB",              { Ebh1, Gb }, 0 },
2196   { "orS",              { Evh1, Gv }, 0 },
2197   { "orB",              { Gb, EbS }, 0 },
2198   { "orS",              { Gv, EvS }, 0 },
2199   { "orB",              { AL, Ib }, 0 },
2200   { "orS",              { eAX, Iv }, 0 },
2201   { X86_64_TABLE (X86_64_0E) },
2202   { Bad_Opcode },       /* 0x0f extended opcode escape */
2203   /* 10 */
2204   { "adcB",             { Ebh1, Gb }, 0 },
2205   { "adcS",             { Evh1, Gv }, 0 },
2206   { "adcB",             { Gb, EbS }, 0 },
2207   { "adcS",             { Gv, EvS }, 0 },
2208   { "adcB",             { AL, Ib }, 0 },
2209   { "adcS",             { eAX, Iv }, 0 },
2210   { X86_64_TABLE (X86_64_16) },
2211   { X86_64_TABLE (X86_64_17) },
2212   /* 18 */
2213   { "sbbB",             { Ebh1, Gb }, 0 },
2214   { "sbbS",             { Evh1, Gv }, 0 },
2215   { "sbbB",             { Gb, EbS }, 0 },
2216   { "sbbS",             { Gv, EvS }, 0 },
2217   { "sbbB",             { AL, Ib }, 0 },
2218   { "sbbS",             { eAX, Iv }, 0 },
2219   { X86_64_TABLE (X86_64_1E) },
2220   { X86_64_TABLE (X86_64_1F) },
2221   /* 20 */
2222   { "andB",             { Ebh1, Gb }, 0 },
2223   { "andS",             { Evh1, Gv }, 0 },
2224   { "andB",             { Gb, EbS }, 0 },
2225   { "andS",             { Gv, EvS }, 0 },
2226   { "andB",             { AL, Ib }, 0 },
2227   { "andS",             { eAX, Iv }, 0 },
2228   { Bad_Opcode },       /* SEG ES prefix */
2229   { X86_64_TABLE (X86_64_27) },
2230   /* 28 */
2231   { "subB",             { Ebh1, Gb }, 0 },
2232   { "subS",             { Evh1, Gv }, 0 },
2233   { "subB",             { Gb, EbS }, 0 },
2234   { "subS",             { Gv, EvS }, 0 },
2235   { "subB",             { AL, Ib }, 0 },
2236   { "subS",             { eAX, Iv }, 0 },
2237   { Bad_Opcode },       /* SEG CS prefix */
2238   { X86_64_TABLE (X86_64_2F) },
2239   /* 30 */
2240   { "xorB",             { Ebh1, Gb }, 0 },
2241   { "xorS",             { Evh1, Gv }, 0 },
2242   { "xorB",             { Gb, EbS }, 0 },
2243   { "xorS",             { Gv, EvS }, 0 },
2244   { "xorB",             { AL, Ib }, 0 },
2245   { "xorS",             { eAX, Iv }, 0 },
2246   { Bad_Opcode },       /* SEG SS prefix */
2247   { X86_64_TABLE (X86_64_37) },
2248   /* 38 */
2249   { "cmpB",             { Eb, Gb }, 0 },
2250   { "cmpS",             { Ev, Gv }, 0 },
2251   { "cmpB",             { Gb, EbS }, 0 },
2252   { "cmpS",             { Gv, EvS }, 0 },
2253   { "cmpB",             { AL, Ib }, 0 },
2254   { "cmpS",             { eAX, Iv }, 0 },
2255   { Bad_Opcode },       /* SEG DS prefix */
2256   { X86_64_TABLE (X86_64_3F) },
2257   /* 40 */
2258   { "inc{S|}",          { RMeAX }, 0 },
2259   { "inc{S|}",          { RMeCX }, 0 },
2260   { "inc{S|}",          { RMeDX }, 0 },
2261   { "inc{S|}",          { RMeBX }, 0 },
2262   { "inc{S|}",          { RMeSP }, 0 },
2263   { "inc{S|}",          { RMeBP }, 0 },
2264   { "inc{S|}",          { RMeSI }, 0 },
2265   { "inc{S|}",          { RMeDI }, 0 },
2266   /* 48 */
2267   { "dec{S|}",          { RMeAX }, 0 },
2268   { "dec{S|}",          { RMeCX }, 0 },
2269   { "dec{S|}",          { RMeDX }, 0 },
2270   { "dec{S|}",          { RMeBX }, 0 },
2271   { "dec{S|}",          { RMeSP }, 0 },
2272   { "dec{S|}",          { RMeBP }, 0 },
2273   { "dec{S|}",          { RMeSI }, 0 },
2274   { "dec{S|}",          { RMeDI }, 0 },
2275   /* 50 */
2276   { "pushV",            { RMrAX }, 0 },
2277   { "pushV",            { RMrCX }, 0 },
2278   { "pushV",            { RMrDX }, 0 },
2279   { "pushV",            { RMrBX }, 0 },
2280   { "pushV",            { RMrSP }, 0 },
2281   { "pushV",            { RMrBP }, 0 },
2282   { "pushV",            { RMrSI }, 0 },
2283   { "pushV",            { RMrDI }, 0 },
2284   /* 58 */
2285   { "popV",             { RMrAX }, 0 },
2286   { "popV",             { RMrCX }, 0 },
2287   { "popV",             { RMrDX }, 0 },
2288   { "popV",             { RMrBX }, 0 },
2289   { "popV",             { RMrSP }, 0 },
2290   { "popV",             { RMrBP }, 0 },
2291   { "popV",             { RMrSI }, 0 },
2292   { "popV",             { RMrDI }, 0 },
2293   /* 60 */
2294   { X86_64_TABLE (X86_64_60) },
2295   { X86_64_TABLE (X86_64_61) },
2296   { X86_64_TABLE (X86_64_62) },
2297   { X86_64_TABLE (X86_64_63) },
2298   { Bad_Opcode },       /* seg fs */
2299   { Bad_Opcode },       /* seg gs */
2300   { Bad_Opcode },       /* op size prefix */
2301   { Bad_Opcode },       /* adr size prefix */
2302   /* 68 */
2303   { "pushT",            { sIv }, 0 },
2304   { "imulS",            { Gv, Ev, Iv }, 0 },
2305   { "pushT",            { sIbT }, 0 },
2306   { "imulS",            { Gv, Ev, sIb }, 0 },
2307   { "ins{b|}",          { Ybr, indirDX }, 0 },
2308   { X86_64_TABLE (X86_64_6D) },
2309   { "outs{b|}",         { indirDXr, Xb }, 0 },
2310   { X86_64_TABLE (X86_64_6F) },
2311   /* 70 */
2312   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2313   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2314   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2315   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2316   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2317   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2318   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2319   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2320   /* 78 */
2321   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2322   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2323   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2324   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2325   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2326   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2327   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2328   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2329   /* 80 */
2330   { REG_TABLE (REG_80) },
2331   { REG_TABLE (REG_81) },
2332   { X86_64_TABLE (X86_64_82) },
2333   { REG_TABLE (REG_83) },
2334   { "testB",            { Eb, Gb }, 0 },
2335   { "testS",            { Ev, Gv }, 0 },
2336   { "xchgB",            { Ebh2, Gb }, 0 },
2337   { "xchgS",            { Evh2, Gv }, 0 },
2338   /* 88 */
2339   { "movB",             { Ebh3, Gb }, 0 },
2340   { "movS",             { Evh3, Gv }, 0 },
2341   { "movB",             { Gb, EbS }, 0 },
2342   { "movS",             { Gv, EvS }, 0 },
2343   { "movD",             { Sv, Sw }, 0 },
2344   { MOD_TABLE (MOD_8D) },
2345   { "movD",             { Sw, Sv }, 0 },
2346   { REG_TABLE (REG_8F) },
2347   /* 90 */
2348   { PREFIX_TABLE (PREFIX_90) },
2349   { "xchgS",            { RMeCX, eAX }, 0 },
2350   { "xchgS",            { RMeDX, eAX }, 0 },
2351   { "xchgS",            { RMeBX, eAX }, 0 },
2352   { "xchgS",            { RMeSP, eAX }, 0 },
2353   { "xchgS",            { RMeBP, eAX }, 0 },
2354   { "xchgS",            { RMeSI, eAX }, 0 },
2355   { "xchgS",            { RMeDI, eAX }, 0 },
2356   /* 98 */
2357   { "cW{t|}R",          { XX }, 0 },
2358   { "cR{t|}O",          { XX }, 0 },
2359   { X86_64_TABLE (X86_64_9A) },
2360   { Bad_Opcode },       /* fwait */
2361   { "pushfT",           { XX }, 0 },
2362   { "popfT",            { XX }, 0 },
2363   { "sahf",             { XX }, 0 },
2364   { "lahf",             { XX }, 0 },
2365   /* a0 */
2366   { "mov%LB",           { AL, Ob }, 0 },
2367   { "mov%LS",           { eAX, Ov }, 0 },
2368   { "mov%LB",           { Ob, AL }, 0 },
2369   { "mov%LS",           { Ov, eAX }, 0 },
2370   { "movs{b|}",         { Ybr, Xb }, 0 },
2371   { "movs{R|}",         { Yvr, Xv }, 0 },
2372   { "cmps{b|}",         { Xb, Yb }, 0 },
2373   { "cmps{R|}",         { Xv, Yv }, 0 },
2374   /* a8 */
2375   { "testB",            { AL, Ib }, 0 },
2376   { "testS",            { eAX, Iv }, 0 },
2377   { "stosB",            { Ybr, AL }, 0 },
2378   { "stosS",            { Yvr, eAX }, 0 },
2379   { "lodsB",            { ALr, Xb }, 0 },
2380   { "lodsS",            { eAXr, Xv }, 0 },
2381   { "scasB",            { AL, Yb }, 0 },
2382   { "scasS",            { eAX, Yv }, 0 },
2383   /* b0 */
2384   { "movB",             { RMAL, Ib }, 0 },
2385   { "movB",             { RMCL, Ib }, 0 },
2386   { "movB",             { RMDL, Ib }, 0 },
2387   { "movB",             { RMBL, Ib }, 0 },
2388   { "movB",             { RMAH, Ib }, 0 },
2389   { "movB",             { RMCH, Ib }, 0 },
2390   { "movB",             { RMDH, Ib }, 0 },
2391   { "movB",             { RMBH, Ib }, 0 },
2392   /* b8 */
2393   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2394   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2395   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2396   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2397   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2398   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2399   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2400   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2401   /* c0 */
2402   { REG_TABLE (REG_C0) },
2403   { REG_TABLE (REG_C1) },
2404   { X86_64_TABLE (X86_64_C2) },
2405   { X86_64_TABLE (X86_64_C3) },
2406   { X86_64_TABLE (X86_64_C4) },
2407   { X86_64_TABLE (X86_64_C5) },
2408   { REG_TABLE (REG_C6) },
2409   { REG_TABLE (REG_C7) },
2410   /* c8 */
2411   { "enterT",           { Iw, Ib }, 0 },
2412   { "leaveT",           { XX }, 0 },
2413   { "{l|}ret{|f}P",     { Iw }, 0 },
2414   { "{l|}ret{|f}P",     { XX }, 0 },
2415   { "int3",             { XX }, 0 },
2416   { "int",              { Ib }, 0 },
2417   { X86_64_TABLE (X86_64_CE) },
2418   { "iret%LP",          { XX }, 0 },
2419   /* d0 */
2420   { REG_TABLE (REG_D0) },
2421   { REG_TABLE (REG_D1) },
2422   { REG_TABLE (REG_D2) },
2423   { REG_TABLE (REG_D3) },
2424   { X86_64_TABLE (X86_64_D4) },
2425   { X86_64_TABLE (X86_64_D5) },
2426   { Bad_Opcode },
2427   { "xlat",             { DSBX }, 0 },
2428   /* d8 */
2429   { FLOAT },
2430   { FLOAT },
2431   { FLOAT },
2432   { FLOAT },
2433   { FLOAT },
2434   { FLOAT },
2435   { FLOAT },
2436   { FLOAT },
2437   /* e0 */
2438   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2439   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2440   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2441   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2442   { "inB",              { AL, Ib }, 0 },
2443   { "inG",              { zAX, Ib }, 0 },
2444   { "outB",             { Ib, AL }, 0 },
2445   { "outG",             { Ib, zAX }, 0 },
2446   /* e8 */
2447   { X86_64_TABLE (X86_64_E8) },
2448   { X86_64_TABLE (X86_64_E9) },
2449   { X86_64_TABLE (X86_64_EA) },
2450   { "jmp",              { Jb, BND }, 0 },
2451   { "inB",              { AL, indirDX }, 0 },
2452   { "inG",              { zAX, indirDX }, 0 },
2453   { "outB",             { indirDX, AL }, 0 },
2454   { "outG",             { indirDX, zAX }, 0 },
2455   /* f0 */
2456   { Bad_Opcode },       /* lock prefix */
2457   { "icebp",            { XX }, 0 },
2458   { Bad_Opcode },       /* repne */
2459   { Bad_Opcode },       /* repz */
2460   { "hlt",              { XX }, 0 },
2461   { "cmc",              { XX }, 0 },
2462   { REG_TABLE (REG_F6) },
2463   { REG_TABLE (REG_F7) },
2464   /* f8 */
2465   { "clc",              { XX }, 0 },
2466   { "stc",              { XX }, 0 },
2467   { "cli",              { XX }, 0 },
2468   { "sti",              { XX }, 0 },
2469   { "cld",              { XX }, 0 },
2470   { "std",              { XX }, 0 },
2471   { REG_TABLE (REG_FE) },
2472   { REG_TABLE (REG_FF) },
2473 };
2474
2475 static const struct dis386 dis386_twobyte[] = {
2476   /* 00 */
2477   { REG_TABLE (REG_0F00 ) },
2478   { REG_TABLE (REG_0F01 ) },
2479   { "larS",             { Gv, Ew }, 0 },
2480   { "lslS",             { Gv, Ew }, 0 },
2481   { Bad_Opcode },
2482   { "syscall",          { XX }, 0 },
2483   { "clts",             { XX }, 0 },
2484   { "sysret%LQ",                { XX }, 0 },
2485   /* 08 */
2486   { "invd",             { XX }, 0 },
2487   { PREFIX_TABLE (PREFIX_0F09) },
2488   { Bad_Opcode },
2489   { "ud2",              { XX }, 0 },
2490   { Bad_Opcode },
2491   { REG_TABLE (REG_0F0D) },
2492   { "femms",            { XX }, 0 },
2493   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2494   /* 10 */
2495   { PREFIX_TABLE (PREFIX_0F10) },
2496   { PREFIX_TABLE (PREFIX_0F11) },
2497   { PREFIX_TABLE (PREFIX_0F12) },
2498   { MOD_TABLE (MOD_0F13) },
2499   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2500   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2501   { PREFIX_TABLE (PREFIX_0F16) },
2502   { MOD_TABLE (MOD_0F17) },
2503   /* 18 */
2504   { REG_TABLE (REG_0F18) },
2505   { "nopQ",             { Ev }, 0 },
2506   { PREFIX_TABLE (PREFIX_0F1A) },
2507   { PREFIX_TABLE (PREFIX_0F1B) },
2508   { PREFIX_TABLE (PREFIX_0F1C) },
2509   { "nopQ",             { Ev }, 0 },
2510   { PREFIX_TABLE (PREFIX_0F1E) },
2511   { "nopQ",             { Ev }, 0 },
2512   /* 20 */
2513   { "movZ",             { Rm, Cm }, 0 },
2514   { "movZ",             { Rm, Dm }, 0 },
2515   { "movZ",             { Cm, Rm }, 0 },
2516   { "movZ",             { Dm, Rm }, 0 },
2517   { MOD_TABLE (MOD_0F24) },
2518   { Bad_Opcode },
2519   { MOD_TABLE (MOD_0F26) },
2520   { Bad_Opcode },
2521   /* 28 */
2522   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2523   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2524   { PREFIX_TABLE (PREFIX_0F2A) },
2525   { PREFIX_TABLE (PREFIX_0F2B) },
2526   { PREFIX_TABLE (PREFIX_0F2C) },
2527   { PREFIX_TABLE (PREFIX_0F2D) },
2528   { PREFIX_TABLE (PREFIX_0F2E) },
2529   { PREFIX_TABLE (PREFIX_0F2F) },
2530   /* 30 */
2531   { "wrmsr",            { XX }, 0 },
2532   { "rdtsc",            { XX }, 0 },
2533   { "rdmsr",            { XX }, 0 },
2534   { "rdpmc",            { XX }, 0 },
2535   { "sysenter",         { SEP }, 0 },
2536   { "sysexit",          { SEP }, 0 },
2537   { Bad_Opcode },
2538   { "getsec",           { XX }, 0 },
2539   /* 38 */
2540   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2541   { Bad_Opcode },
2542   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2543   { Bad_Opcode },
2544   { Bad_Opcode },
2545   { Bad_Opcode },
2546   { Bad_Opcode },
2547   { Bad_Opcode },
2548   /* 40 */
2549   { "cmovoS",           { Gv, Ev }, 0 },
2550   { "cmovnoS",          { Gv, Ev }, 0 },
2551   { "cmovbS",           { Gv, Ev }, 0 },
2552   { "cmovaeS",          { Gv, Ev }, 0 },
2553   { "cmoveS",           { Gv, Ev }, 0 },
2554   { "cmovneS",          { Gv, Ev }, 0 },
2555   { "cmovbeS",          { Gv, Ev }, 0 },
2556   { "cmovaS",           { Gv, Ev }, 0 },
2557   /* 48 */
2558   { "cmovsS",           { Gv, Ev }, 0 },
2559   { "cmovnsS",          { Gv, Ev }, 0 },
2560   { "cmovpS",           { Gv, Ev }, 0 },
2561   { "cmovnpS",          { Gv, Ev }, 0 },
2562   { "cmovlS",           { Gv, Ev }, 0 },
2563   { "cmovgeS",          { Gv, Ev }, 0 },
2564   { "cmovleS",          { Gv, Ev }, 0 },
2565   { "cmovgS",           { Gv, Ev }, 0 },
2566   /* 50 */
2567   { MOD_TABLE (MOD_0F50) },
2568   { PREFIX_TABLE (PREFIX_0F51) },
2569   { PREFIX_TABLE (PREFIX_0F52) },
2570   { PREFIX_TABLE (PREFIX_0F53) },
2571   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2572   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2573   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2574   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2575   /* 58 */
2576   { PREFIX_TABLE (PREFIX_0F58) },
2577   { PREFIX_TABLE (PREFIX_0F59) },
2578   { PREFIX_TABLE (PREFIX_0F5A) },
2579   { PREFIX_TABLE (PREFIX_0F5B) },
2580   { PREFIX_TABLE (PREFIX_0F5C) },
2581   { PREFIX_TABLE (PREFIX_0F5D) },
2582   { PREFIX_TABLE (PREFIX_0F5E) },
2583   { PREFIX_TABLE (PREFIX_0F5F) },
2584   /* 60 */
2585   { PREFIX_TABLE (PREFIX_0F60) },
2586   { PREFIX_TABLE (PREFIX_0F61) },
2587   { PREFIX_TABLE (PREFIX_0F62) },
2588   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2589   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2590   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2591   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2592   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2593   /* 68 */
2594   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2595   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2596   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2597   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2598   { PREFIX_TABLE (PREFIX_0F6C) },
2599   { PREFIX_TABLE (PREFIX_0F6D) },
2600   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2601   { PREFIX_TABLE (PREFIX_0F6F) },
2602   /* 70 */
2603   { PREFIX_TABLE (PREFIX_0F70) },
2604   { REG_TABLE (REG_0F71) },
2605   { REG_TABLE (REG_0F72) },
2606   { REG_TABLE (REG_0F73) },
2607   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2608   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2609   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2610   { "emms",             { XX }, PREFIX_OPCODE },
2611   /* 78 */
2612   { PREFIX_TABLE (PREFIX_0F78) },
2613   { PREFIX_TABLE (PREFIX_0F79) },
2614   { Bad_Opcode },
2615   { Bad_Opcode },
2616   { PREFIX_TABLE (PREFIX_0F7C) },
2617   { PREFIX_TABLE (PREFIX_0F7D) },
2618   { PREFIX_TABLE (PREFIX_0F7E) },
2619   { PREFIX_TABLE (PREFIX_0F7F) },
2620   /* 80 */
2621   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2622   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2623   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2624   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2625   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2626   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2627   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2628   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2629   /* 88 */
2630   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2631   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2632   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2633   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2634   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2635   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2636   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2637   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2638   /* 90 */
2639   { "seto",             { Eb }, 0 },
2640   { "setno",            { Eb }, 0 },
2641   { "setb",             { Eb }, 0 },
2642   { "setae",            { Eb }, 0 },
2643   { "sete",             { Eb }, 0 },
2644   { "setne",            { Eb }, 0 },
2645   { "setbe",            { Eb }, 0 },
2646   { "seta",             { Eb }, 0 },
2647   /* 98 */
2648   { "sets",             { Eb }, 0 },
2649   { "setns",            { Eb }, 0 },
2650   { "setp",             { Eb }, 0 },
2651   { "setnp",            { Eb }, 0 },
2652   { "setl",             { Eb }, 0 },
2653   { "setge",            { Eb }, 0 },
2654   { "setle",            { Eb }, 0 },
2655   { "setg",             { Eb }, 0 },
2656   /* a0 */
2657   { "pushT",            { fs }, 0 },
2658   { "popT",             { fs }, 0 },
2659   { "cpuid",            { XX }, 0 },
2660   { "btS",              { Ev, Gv }, 0 },
2661   { "shldS",            { Ev, Gv, Ib }, 0 },
2662   { "shldS",            { Ev, Gv, CL }, 0 },
2663   { REG_TABLE (REG_0FA6) },
2664   { REG_TABLE (REG_0FA7) },
2665   /* a8 */
2666   { "pushT",            { gs }, 0 },
2667   { "popT",             { gs }, 0 },
2668   { "rsm",              { XX }, 0 },
2669   { "btsS",             { Evh1, Gv }, 0 },
2670   { "shrdS",            { Ev, Gv, Ib }, 0 },
2671   { "shrdS",            { Ev, Gv, CL }, 0 },
2672   { REG_TABLE (REG_0FAE) },
2673   { "imulS",            { Gv, Ev }, 0 },
2674   /* b0 */
2675   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2676   { "cmpxchgS",         { Evh1, Gv }, 0 },
2677   { MOD_TABLE (MOD_0FB2) },
2678   { "btrS",             { Evh1, Gv }, 0 },
2679   { MOD_TABLE (MOD_0FB4) },
2680   { MOD_TABLE (MOD_0FB5) },
2681   { "movz{bR|x}",       { Gv, Eb }, 0 },
2682   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2683   /* b8 */
2684   { PREFIX_TABLE (PREFIX_0FB8) },
2685   { "ud1S",             { Gv, Ev }, 0 },
2686   { REG_TABLE (REG_0FBA) },
2687   { "btcS",             { Evh1, Gv }, 0 },
2688   { PREFIX_TABLE (PREFIX_0FBC) },
2689   { PREFIX_TABLE (PREFIX_0FBD) },
2690   { "movs{bR|x}",       { Gv, Eb }, 0 },
2691   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2692   /* c0 */
2693   { "xaddB",            { Ebh1, Gb }, 0 },
2694   { "xaddS",            { Evh1, Gv }, 0 },
2695   { PREFIX_TABLE (PREFIX_0FC2) },
2696   { MOD_TABLE (MOD_0FC3) },
2697   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2698   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2699   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2700   { REG_TABLE (REG_0FC7) },
2701   /* c8 */
2702   { "bswap",            { RMeAX }, 0 },
2703   { "bswap",            { RMeCX }, 0 },
2704   { "bswap",            { RMeDX }, 0 },
2705   { "bswap",            { RMeBX }, 0 },
2706   { "bswap",            { RMeSP }, 0 },
2707   { "bswap",            { RMeBP }, 0 },
2708   { "bswap",            { RMeSI }, 0 },
2709   { "bswap",            { RMeDI }, 0 },
2710   /* d0 */
2711   { PREFIX_TABLE (PREFIX_0FD0) },
2712   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2713   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2714   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2715   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2716   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2717   { PREFIX_TABLE (PREFIX_0FD6) },
2718   { MOD_TABLE (MOD_0FD7) },
2719   /* d8 */
2720   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2721   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2722   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2723   { "pand",             { MX, EM }, PREFIX_OPCODE },
2724   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2725   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2726   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2727   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2728   /* e0 */
2729   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2730   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2731   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2732   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2733   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2734   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2735   { PREFIX_TABLE (PREFIX_0FE6) },
2736   { PREFIX_TABLE (PREFIX_0FE7) },
2737   /* e8 */
2738   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2739   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2740   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2741   { "por",              { MX, EM }, PREFIX_OPCODE },
2742   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2743   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2744   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2745   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2746   /* f0 */
2747   { PREFIX_TABLE (PREFIX_0FF0) },
2748   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2749   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2750   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2751   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2752   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2753   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2754   { PREFIX_TABLE (PREFIX_0FF7) },
2755   /* f8 */
2756   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2757   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2758   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2759   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2760   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2761   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2762   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2763   { "ud0S",             { Gv, Ev }, 0 },
2764 };
2765
2766 static const unsigned char onebyte_has_modrm[256] = {
2767   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2768   /*       -------------------------------        */
2769   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2770   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2771   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2772   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2773   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2774   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2775   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2776   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2777   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2778   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2779   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2780   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2781   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2782   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2783   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2784   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2785   /*       -------------------------------        */
2786   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2787 };
2788
2789 static const unsigned char twobyte_has_modrm[256] = {
2790   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2791   /*       -------------------------------        */
2792   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2793   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2794   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2795   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2796   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2797   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2798   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2799   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2800   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2801   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2802   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2803   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2804   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2805   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2806   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2807   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2808   /*       -------------------------------        */
2809   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2810 };
2811
2812 static char obuf[100];
2813 static char *obufp;
2814 static char *mnemonicendp;
2815 static char scratchbuf[100];
2816 static unsigned char *start_codep;
2817 static unsigned char *insn_codep;
2818 static unsigned char *codep;
2819 static unsigned char *end_codep;
2820 static int last_lock_prefix;
2821 static int last_repz_prefix;
2822 static int last_repnz_prefix;
2823 static int last_data_prefix;
2824 static int last_addr_prefix;
2825 static int last_rex_prefix;
2826 static int last_seg_prefix;
2827 static int fwait_prefix;
2828 /* The active segment register prefix.  */
2829 static int active_seg_prefix;
2830 #define MAX_CODE_LENGTH 15
2831 /* We can up to 14 prefixes since the maximum instruction length is
2832    15bytes.  */
2833 static int all_prefixes[MAX_CODE_LENGTH - 1];
2834 static disassemble_info *the_info;
2835 static struct
2836   {
2837     int mod;
2838     int reg;
2839     int rm;
2840   }
2841 modrm;
2842 static unsigned char need_modrm;
2843 static struct
2844   {
2845     int scale;
2846     int index;
2847     int base;
2848   }
2849 sib;
2850 static struct
2851   {
2852     int register_specifier;
2853     int length;
2854     int prefix;
2855     int w;
2856     int evex;
2857     int r;
2858     int v;
2859     int mask_register_specifier;
2860     int zeroing;
2861     int ll;
2862     int b;
2863   }
2864 vex;
2865 static unsigned char need_vex;
2866 static unsigned char need_vex_reg;
2867
2868 struct op
2869   {
2870     const char *name;
2871     unsigned int len;
2872   };
2873
2874 /* If we are accessing mod/rm/reg without need_modrm set, then the
2875    values are stale.  Hitting this abort likely indicates that you
2876    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2877 #define MODRM_CHECK  if (!need_modrm) abort ()
2878
2879 static const char **names64;
2880 static const char **names32;
2881 static const char **names16;
2882 static const char **names8;
2883 static const char **names8rex;
2884 static const char **names_seg;
2885 static const char *index64;
2886 static const char *index32;
2887 static const char **index16;
2888 static const char **names_bnd;
2889
2890 static const char *intel_names64[] = {
2891   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2892   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2893 };
2894 static const char *intel_names32[] = {
2895   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2896   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2897 };
2898 static const char *intel_names16[] = {
2899   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2900   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2901 };
2902 static const char *intel_names8[] = {
2903   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2904 };
2905 static const char *intel_names8rex[] = {
2906   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2907   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2908 };
2909 static const char *intel_names_seg[] = {
2910   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2911 };
2912 static const char *intel_index64 = "riz";
2913 static const char *intel_index32 = "eiz";
2914 static const char *intel_index16[] = {
2915   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2916 };
2917
2918 static const char *att_names64[] = {
2919   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2920   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2921 };
2922 static const char *att_names32[] = {
2923   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2924   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2925 };
2926 static const char *att_names16[] = {
2927   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2928   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2929 };
2930 static const char *att_names8[] = {
2931   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2932 };
2933 static const char *att_names8rex[] = {
2934   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2935   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2936 };
2937 static const char *att_names_seg[] = {
2938   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2939 };
2940 static const char *att_index64 = "%riz";
2941 static const char *att_index32 = "%eiz";
2942 static const char *att_index16[] = {
2943   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2944 };
2945
2946 static const char **names_mm;
2947 static const char *intel_names_mm[] = {
2948   "mm0", "mm1", "mm2", "mm3",
2949   "mm4", "mm5", "mm6", "mm7"
2950 };
2951 static const char *att_names_mm[] = {
2952   "%mm0", "%mm1", "%mm2", "%mm3",
2953   "%mm4", "%mm5", "%mm6", "%mm7"
2954 };
2955
2956 static const char *intel_names_bnd[] = {
2957   "bnd0", "bnd1", "bnd2", "bnd3"
2958 };
2959
2960 static const char *att_names_bnd[] = {
2961   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2962 };
2963
2964 static const char **names_xmm;
2965 static const char *intel_names_xmm[] = {
2966   "xmm0", "xmm1", "xmm2", "xmm3",
2967   "xmm4", "xmm5", "xmm6", "xmm7",
2968   "xmm8", "xmm9", "xmm10", "xmm11",
2969   "xmm12", "xmm13", "xmm14", "xmm15",
2970   "xmm16", "xmm17", "xmm18", "xmm19",
2971   "xmm20", "xmm21", "xmm22", "xmm23",
2972   "xmm24", "xmm25", "xmm26", "xmm27",
2973   "xmm28", "xmm29", "xmm30", "xmm31"
2974 };
2975 static const char *att_names_xmm[] = {
2976   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2977   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2978   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2979   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2980   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2981   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2982   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2983   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2984 };
2985
2986 static const char **names_ymm;
2987 static const char *intel_names_ymm[] = {
2988   "ymm0", "ymm1", "ymm2", "ymm3",
2989   "ymm4", "ymm5", "ymm6", "ymm7",
2990   "ymm8", "ymm9", "ymm10", "ymm11",
2991   "ymm12", "ymm13", "ymm14", "ymm15",
2992   "ymm16", "ymm17", "ymm18", "ymm19",
2993   "ymm20", "ymm21", "ymm22", "ymm23",
2994   "ymm24", "ymm25", "ymm26", "ymm27",
2995   "ymm28", "ymm29", "ymm30", "ymm31"
2996 };
2997 static const char *att_names_ymm[] = {
2998   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2999   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3000   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3001   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3002   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3003   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3004   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3005   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3006 };
3007
3008 static const char **names_zmm;
3009 static const char *intel_names_zmm[] = {
3010   "zmm0", "zmm1", "zmm2", "zmm3",
3011   "zmm4", "zmm5", "zmm6", "zmm7",
3012   "zmm8", "zmm9", "zmm10", "zmm11",
3013   "zmm12", "zmm13", "zmm14", "zmm15",
3014   "zmm16", "zmm17", "zmm18", "zmm19",
3015   "zmm20", "zmm21", "zmm22", "zmm23",
3016   "zmm24", "zmm25", "zmm26", "zmm27",
3017   "zmm28", "zmm29", "zmm30", "zmm31"
3018 };
3019 static const char *att_names_zmm[] = {
3020   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3021   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3022   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3023   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3024   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3025   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3026   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3027   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3028 };
3029
3030 static const char **names_mask;
3031 static const char *intel_names_mask[] = {
3032   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3033 };
3034 static const char *att_names_mask[] = {
3035   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3036 };
3037
3038 static const char *names_rounding[] =
3039 {
3040   "{rn-sae}",
3041   "{rd-sae}",
3042   "{ru-sae}",
3043   "{rz-sae}"
3044 };
3045
3046 static const struct dis386 reg_table[][8] = {
3047   /* REG_80 */
3048   {
3049     { "addA",   { Ebh1, Ib }, 0 },
3050     { "orA",    { Ebh1, Ib }, 0 },
3051     { "adcA",   { Ebh1, Ib }, 0 },
3052     { "sbbA",   { Ebh1, Ib }, 0 },
3053     { "andA",   { Ebh1, Ib }, 0 },
3054     { "subA",   { Ebh1, Ib }, 0 },
3055     { "xorA",   { Ebh1, Ib }, 0 },
3056     { "cmpA",   { Eb, Ib }, 0 },
3057   },
3058   /* REG_81 */
3059   {
3060     { "addQ",   { Evh1, Iv }, 0 },
3061     { "orQ",    { Evh1, Iv }, 0 },
3062     { "adcQ",   { Evh1, Iv }, 0 },
3063     { "sbbQ",   { Evh1, Iv }, 0 },
3064     { "andQ",   { Evh1, Iv }, 0 },
3065     { "subQ",   { Evh1, Iv }, 0 },
3066     { "xorQ",   { Evh1, Iv }, 0 },
3067     { "cmpQ",   { Ev, Iv }, 0 },
3068   },
3069   /* REG_83 */
3070   {
3071     { "addQ",   { Evh1, sIb }, 0 },
3072     { "orQ",    { Evh1, sIb }, 0 },
3073     { "adcQ",   { Evh1, sIb }, 0 },
3074     { "sbbQ",   { Evh1, sIb }, 0 },
3075     { "andQ",   { Evh1, sIb }, 0 },
3076     { "subQ",   { Evh1, sIb }, 0 },
3077     { "xorQ",   { Evh1, sIb }, 0 },
3078     { "cmpQ",   { Ev, sIb }, 0 },
3079   },
3080   /* REG_8F */
3081   {
3082     { "popU",   { stackEv }, 0 },
3083     { XOP_8F_TABLE (XOP_09) },
3084     { Bad_Opcode },
3085     { Bad_Opcode },
3086     { Bad_Opcode },
3087     { XOP_8F_TABLE (XOP_09) },
3088   },
3089   /* REG_C0 */
3090   {
3091     { "rolA",   { Eb, Ib }, 0 },
3092     { "rorA",   { Eb, Ib }, 0 },
3093     { "rclA",   { Eb, Ib }, 0 },
3094     { "rcrA",   { Eb, Ib }, 0 },
3095     { "shlA",   { Eb, Ib }, 0 },
3096     { "shrA",   { Eb, Ib }, 0 },
3097     { "shlA",   { Eb, Ib }, 0 },
3098     { "sarA",   { Eb, Ib }, 0 },
3099   },
3100   /* REG_C1 */
3101   {
3102     { "rolQ",   { Ev, Ib }, 0 },
3103     { "rorQ",   { Ev, Ib }, 0 },
3104     { "rclQ",   { Ev, Ib }, 0 },
3105     { "rcrQ",   { Ev, Ib }, 0 },
3106     { "shlQ",   { Ev, Ib }, 0 },
3107     { "shrQ",   { Ev, Ib }, 0 },
3108     { "shlQ",   { Ev, Ib }, 0 },
3109     { "sarQ",   { Ev, Ib }, 0 },
3110   },
3111   /* REG_C6 */
3112   {
3113     { "movA",   { Ebh3, Ib }, 0 },
3114     { Bad_Opcode },
3115     { Bad_Opcode },
3116     { Bad_Opcode },
3117     { Bad_Opcode },
3118     { Bad_Opcode },
3119     { Bad_Opcode },
3120     { MOD_TABLE (MOD_C6_REG_7) },
3121   },
3122   /* REG_C7 */
3123   {
3124     { "movQ",   { Evh3, Iv }, 0 },
3125     { Bad_Opcode },
3126     { Bad_Opcode },
3127     { Bad_Opcode },
3128     { Bad_Opcode },
3129     { Bad_Opcode },
3130     { Bad_Opcode },
3131     { MOD_TABLE (MOD_C7_REG_7) },
3132   },
3133   /* REG_D0 */
3134   {
3135     { "rolA",   { Eb, I1 }, 0 },
3136     { "rorA",   { Eb, I1 }, 0 },
3137     { "rclA",   { Eb, I1 }, 0 },
3138     { "rcrA",   { Eb, I1 }, 0 },
3139     { "shlA",   { Eb, I1 }, 0 },
3140     { "shrA",   { Eb, I1 }, 0 },
3141     { "shlA",   { Eb, I1 }, 0 },
3142     { "sarA",   { Eb, I1 }, 0 },
3143   },
3144   /* REG_D1 */
3145   {
3146     { "rolQ",   { Ev, I1 }, 0 },
3147     { "rorQ",   { Ev, I1 }, 0 },
3148     { "rclQ",   { Ev, I1 }, 0 },
3149     { "rcrQ",   { Ev, I1 }, 0 },
3150     { "shlQ",   { Ev, I1 }, 0 },
3151     { "shrQ",   { Ev, I1 }, 0 },
3152     { "shlQ",   { Ev, I1 }, 0 },
3153     { "sarQ",   { Ev, I1 }, 0 },
3154   },
3155   /* REG_D2 */
3156   {
3157     { "rolA",   { Eb, CL }, 0 },
3158     { "rorA",   { Eb, CL }, 0 },
3159     { "rclA",   { Eb, CL }, 0 },
3160     { "rcrA",   { Eb, CL }, 0 },
3161     { "shlA",   { Eb, CL }, 0 },
3162     { "shrA",   { Eb, CL }, 0 },
3163     { "shlA",   { Eb, CL }, 0 },
3164     { "sarA",   { Eb, CL }, 0 },
3165   },
3166   /* REG_D3 */
3167   {
3168     { "rolQ",   { Ev, CL }, 0 },
3169     { "rorQ",   { Ev, CL }, 0 },
3170     { "rclQ",   { Ev, CL }, 0 },
3171     { "rcrQ",   { Ev, CL }, 0 },
3172     { "shlQ",   { Ev, CL }, 0 },
3173     { "shrQ",   { Ev, CL }, 0 },
3174     { "shlQ",   { Ev, CL }, 0 },
3175     { "sarQ",   { Ev, CL }, 0 },
3176   },
3177   /* REG_F6 */
3178   {
3179     { "testA",  { Eb, Ib }, 0 },
3180     { "testA",  { Eb, Ib }, 0 },
3181     { "notA",   { Ebh1 }, 0 },
3182     { "negA",   { Ebh1 }, 0 },
3183     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3184     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3185     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3186     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3187   },
3188   /* REG_F7 */
3189   {
3190     { "testQ",  { Ev, Iv }, 0 },
3191     { "testQ",  { Ev, Iv }, 0 },
3192     { "notQ",   { Evh1 }, 0 },
3193     { "negQ",   { Evh1 }, 0 },
3194     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3195     { "imulQ",  { Ev }, 0 },
3196     { "divQ",   { Ev }, 0 },
3197     { "idivQ",  { Ev }, 0 },
3198   },
3199   /* REG_FE */
3200   {
3201     { "incA",   { Ebh1 }, 0 },
3202     { "decA",   { Ebh1 }, 0 },
3203   },
3204   /* REG_FF */
3205   {
3206     { "incQ",   { Evh1 }, 0 },
3207     { "decQ",   { Evh1 }, 0 },
3208     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3209     { MOD_TABLE (MOD_FF_REG_3) },
3210     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3211     { MOD_TABLE (MOD_FF_REG_5) },
3212     { "pushU",  { stackEv }, 0 },
3213     { Bad_Opcode },
3214   },
3215   /* REG_0F00 */
3216   {
3217     { "sldtD",  { Sv }, 0 },
3218     { "strD",   { Sv }, 0 },
3219     { "lldt",   { Ew }, 0 },
3220     { "ltr",    { Ew }, 0 },
3221     { "verr",   { Ew }, 0 },
3222     { "verw",   { Ew }, 0 },
3223     { Bad_Opcode },
3224     { Bad_Opcode },
3225   },
3226   /* REG_0F01 */
3227   {
3228     { MOD_TABLE (MOD_0F01_REG_0) },
3229     { MOD_TABLE (MOD_0F01_REG_1) },
3230     { MOD_TABLE (MOD_0F01_REG_2) },
3231     { MOD_TABLE (MOD_0F01_REG_3) },
3232     { "smswD",  { Sv }, 0 },
3233     { MOD_TABLE (MOD_0F01_REG_5) },
3234     { "lmsw",   { Ew }, 0 },
3235     { MOD_TABLE (MOD_0F01_REG_7) },
3236   },
3237   /* REG_0F0D */
3238   {
3239     { "prefetch",       { Mb }, 0 },
3240     { "prefetchw",      { Mb }, 0 },
3241     { "prefetchwt1",    { Mb }, 0 },
3242     { "prefetch",       { Mb }, 0 },
3243     { "prefetch",       { Mb }, 0 },
3244     { "prefetch",       { Mb }, 0 },
3245     { "prefetch",       { Mb }, 0 },
3246     { "prefetch",       { Mb }, 0 },
3247   },
3248   /* REG_0F18 */
3249   {
3250     { MOD_TABLE (MOD_0F18_REG_0) },
3251     { MOD_TABLE (MOD_0F18_REG_1) },
3252     { MOD_TABLE (MOD_0F18_REG_2) },
3253     { MOD_TABLE (MOD_0F18_REG_3) },
3254     { MOD_TABLE (MOD_0F18_REG_4) },
3255     { MOD_TABLE (MOD_0F18_REG_5) },
3256     { MOD_TABLE (MOD_0F18_REG_6) },
3257     { MOD_TABLE (MOD_0F18_REG_7) },
3258   },
3259   /* REG_0F1C_P_0_MOD_0 */
3260   {
3261     { "cldemote",       { Mb }, 0 },
3262     { "nopQ",           { Ev }, 0 },
3263     { "nopQ",           { Ev }, 0 },
3264     { "nopQ",           { Ev }, 0 },
3265     { "nopQ",           { Ev }, 0 },
3266     { "nopQ",           { Ev }, 0 },
3267     { "nopQ",           { Ev }, 0 },
3268     { "nopQ",           { Ev }, 0 },
3269   },
3270   /* REG_0F1E_P_1_MOD_3 */
3271   {
3272     { "nopQ",           { Ev }, 0 },
3273     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3274     { "nopQ",           { Ev }, 0 },
3275     { "nopQ",           { Ev }, 0 },
3276     { "nopQ",           { Ev }, 0 },
3277     { "nopQ",           { Ev }, 0 },
3278     { "nopQ",           { Ev }, 0 },
3279     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3280   },
3281   /* REG_0F71 */
3282   {
3283     { Bad_Opcode },
3284     { Bad_Opcode },
3285     { MOD_TABLE (MOD_0F71_REG_2) },
3286     { Bad_Opcode },
3287     { MOD_TABLE (MOD_0F71_REG_4) },
3288     { Bad_Opcode },
3289     { MOD_TABLE (MOD_0F71_REG_6) },
3290   },
3291   /* REG_0F72 */
3292   {
3293     { Bad_Opcode },
3294     { Bad_Opcode },
3295     { MOD_TABLE (MOD_0F72_REG_2) },
3296     { Bad_Opcode },
3297     { MOD_TABLE (MOD_0F72_REG_4) },
3298     { Bad_Opcode },
3299     { MOD_TABLE (MOD_0F72_REG_6) },
3300   },
3301   /* REG_0F73 */
3302   {
3303     { Bad_Opcode },
3304     { Bad_Opcode },
3305     { MOD_TABLE (MOD_0F73_REG_2) },
3306     { MOD_TABLE (MOD_0F73_REG_3) },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { MOD_TABLE (MOD_0F73_REG_6) },
3310     { MOD_TABLE (MOD_0F73_REG_7) },
3311   },
3312   /* REG_0FA6 */
3313   {
3314     { "montmul",        { { OP_0f07, 0 } }, 0 },
3315     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3316     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3317   },
3318   /* REG_0FA7 */
3319   {
3320     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3321     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3322     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3323     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3324     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3325     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3326   },
3327   /* REG_0FAE */
3328   {
3329     { MOD_TABLE (MOD_0FAE_REG_0) },
3330     { MOD_TABLE (MOD_0FAE_REG_1) },
3331     { MOD_TABLE (MOD_0FAE_REG_2) },
3332     { MOD_TABLE (MOD_0FAE_REG_3) },
3333     { MOD_TABLE (MOD_0FAE_REG_4) },
3334     { MOD_TABLE (MOD_0FAE_REG_5) },
3335     { MOD_TABLE (MOD_0FAE_REG_6) },
3336     { MOD_TABLE (MOD_0FAE_REG_7) },
3337   },
3338   /* REG_0FBA */
3339   {
3340     { Bad_Opcode },
3341     { Bad_Opcode },
3342     { Bad_Opcode },
3343     { Bad_Opcode },
3344     { "btQ",    { Ev, Ib }, 0 },
3345     { "btsQ",   { Evh1, Ib }, 0 },
3346     { "btrQ",   { Evh1, Ib }, 0 },
3347     { "btcQ",   { Evh1, Ib }, 0 },
3348   },
3349   /* REG_0FC7 */
3350   {
3351     { Bad_Opcode },
3352     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3353     { Bad_Opcode },
3354     { MOD_TABLE (MOD_0FC7_REG_3) },
3355     { MOD_TABLE (MOD_0FC7_REG_4) },
3356     { MOD_TABLE (MOD_0FC7_REG_5) },
3357     { MOD_TABLE (MOD_0FC7_REG_6) },
3358     { MOD_TABLE (MOD_0FC7_REG_7) },
3359   },
3360   /* REG_VEX_0F71 */
3361   {
3362     { Bad_Opcode },
3363     { Bad_Opcode },
3364     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3365     { Bad_Opcode },
3366     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3367     { Bad_Opcode },
3368     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3369   },
3370   /* REG_VEX_0F72 */
3371   {
3372     { Bad_Opcode },
3373     { Bad_Opcode },
3374     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3375     { Bad_Opcode },
3376     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3377     { Bad_Opcode },
3378     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3379   },
3380   /* REG_VEX_0F73 */
3381   {
3382     { Bad_Opcode },
3383     { Bad_Opcode },
3384     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3385     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3386     { Bad_Opcode },
3387     { Bad_Opcode },
3388     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3389     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3390   },
3391   /* REG_VEX_0FAE */
3392   {
3393     { Bad_Opcode },
3394     { Bad_Opcode },
3395     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3396     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3397   },
3398   /* REG_VEX_0F38F3 */
3399   {
3400     { Bad_Opcode },
3401     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3402     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3403     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3404   },
3405   /* REG_XOP_LWPCB */
3406   {
3407     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3408     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3409   },
3410   /* REG_XOP_LWP */
3411   {
3412     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3413     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3414   },
3415   /* REG_XOP_TBM_01 */
3416   {
3417     { Bad_Opcode },
3418     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3419     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3420     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3421     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3422     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3423     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3424     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3425   },
3426   /* REG_XOP_TBM_02 */
3427   {
3428     { Bad_Opcode },
3429     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3430     { Bad_Opcode },
3431     { Bad_Opcode },
3432     { Bad_Opcode },
3433     { Bad_Opcode },
3434     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3435   },
3436
3437 #include "i386-dis-evex-reg.h"
3438 };
3439
3440 static const struct dis386 prefix_table[][4] = {
3441   /* PREFIX_90 */
3442   {
3443     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3444     { "pause", { XX }, 0 },
3445     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3446     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3447   },
3448
3449   /* PREFIX_0F01_REG_3_RM_1 */
3450   {
3451     { "vmmcall",        { Skip_MODRM }, 0 },
3452     { "vmgexit",        { Skip_MODRM }, 0 },
3453     { Bad_Opcode },
3454     { "vmgexit",        { Skip_MODRM }, 0 },
3455   },
3456
3457   /* PREFIX_0F01_REG_5_MOD_0 */
3458   {
3459     { Bad_Opcode },
3460     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3461   },
3462
3463   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3464   {
3465     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3466     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3467     { Bad_Opcode },
3468     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3469   },
3470
3471   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3472   {
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475     { Bad_Opcode },
3476     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3477   },
3478
3479   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3480   {
3481     { Bad_Opcode },
3482     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3483   },
3484
3485   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3486   {
3487     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3488     { "mcommit",        { Skip_MODRM }, 0 },
3489   },
3490
3491   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3492   {
3493     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3494   },
3495
3496   /* PREFIX_0F09 */
3497   {
3498     { "wbinvd",   { XX }, 0 },
3499     { "wbnoinvd", { XX }, 0 },
3500   },
3501
3502   /* PREFIX_0F10 */
3503   {
3504     { "movups", { XM, EXx }, PREFIX_OPCODE },
3505     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3506     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3507     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3508   },
3509
3510   /* PREFIX_0F11 */
3511   {
3512     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3513     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3514     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3515     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3516   },
3517
3518   /* PREFIX_0F12 */
3519   {
3520     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3521     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3522     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3523     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3524   },
3525
3526   /* PREFIX_0F16 */
3527   {
3528     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3529     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3530     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3531   },
3532
3533   /* PREFIX_0F1A */
3534   {
3535     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3536     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3537     { "bndmov", { Gbnd, Ebnd }, 0 },
3538     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3539   },
3540
3541   /* PREFIX_0F1B */
3542   {
3543     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3544     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3545     { "bndmov", { EbndS, Gbnd }, 0 },
3546     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3547   },
3548
3549   /* PREFIX_0F1C */
3550   {
3551     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3552     { "nopQ",   { Ev }, PREFIX_OPCODE },
3553     { "nopQ",   { Ev }, PREFIX_OPCODE },
3554     { "nopQ",   { Ev }, PREFIX_OPCODE },
3555   },
3556
3557   /* PREFIX_0F1E */
3558   {
3559     { "nopQ",   { Ev }, PREFIX_OPCODE },
3560     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3561     { "nopQ",   { Ev }, PREFIX_OPCODE },
3562     { "nopQ",   { Ev }, PREFIX_OPCODE },
3563   },
3564
3565   /* PREFIX_0F2A */
3566   {
3567     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3568     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3569     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3570     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3571   },
3572
3573   /* PREFIX_0F2B */
3574   {
3575     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3576     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3577     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3578     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3579   },
3580
3581   /* PREFIX_0F2C */
3582   {
3583     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3584     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3585     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3586     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3587   },
3588
3589   /* PREFIX_0F2D */
3590   {
3591     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3592     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3593     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3594     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3595   },
3596
3597   /* PREFIX_0F2E */
3598   {
3599     { "ucomiss",{ XM, EXd }, 0 },
3600     { Bad_Opcode },
3601     { "ucomisd",{ XM, EXq }, 0 },
3602   },
3603
3604   /* PREFIX_0F2F */
3605   {
3606     { "comiss", { XM, EXd }, 0 },
3607     { Bad_Opcode },
3608     { "comisd", { XM, EXq }, 0 },
3609   },
3610
3611   /* PREFIX_0F51 */
3612   {
3613     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3614     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3615     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3616     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3617   },
3618
3619   /* PREFIX_0F52 */
3620   {
3621     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3622     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3623   },
3624
3625   /* PREFIX_0F53 */
3626   {
3627     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3628     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3629   },
3630
3631   /* PREFIX_0F58 */
3632   {
3633     { "addps", { XM, EXx }, PREFIX_OPCODE },
3634     { "addss", { XM, EXd }, PREFIX_OPCODE },
3635     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3636     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3637   },
3638
3639   /* PREFIX_0F59 */
3640   {
3641     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3642     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3643     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3644     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3645   },
3646
3647   /* PREFIX_0F5A */
3648   {
3649     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3650     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3651     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3652     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3653   },
3654
3655   /* PREFIX_0F5B */
3656   {
3657     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3658     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3659     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3660   },
3661
3662   /* PREFIX_0F5C */
3663   {
3664     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3665     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3666     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3667     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3668   },
3669
3670   /* PREFIX_0F5D */
3671   {
3672     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3673     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3674     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3675     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3676   },
3677
3678   /* PREFIX_0F5E */
3679   {
3680     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3681     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3682     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3683     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3684   },
3685
3686   /* PREFIX_0F5F */
3687   {
3688     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3689     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3690     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3691     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3692   },
3693
3694   /* PREFIX_0F60 */
3695   {
3696     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3697     { Bad_Opcode },
3698     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3699   },
3700
3701   /* PREFIX_0F61 */
3702   {
3703     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3704     { Bad_Opcode },
3705     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3706   },
3707
3708   /* PREFIX_0F62 */
3709   {
3710     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3711     { Bad_Opcode },
3712     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3713   },
3714
3715   /* PREFIX_0F6C */
3716   {
3717     { Bad_Opcode },
3718     { Bad_Opcode },
3719     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3720   },
3721
3722   /* PREFIX_0F6D */
3723   {
3724     { Bad_Opcode },
3725     { Bad_Opcode },
3726     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3727   },
3728
3729   /* PREFIX_0F6F */
3730   {
3731     { "movq",   { MX, EM }, PREFIX_OPCODE },
3732     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3733     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3734   },
3735
3736   /* PREFIX_0F70 */
3737   {
3738     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3739     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3740     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3741     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3742   },
3743
3744   /* PREFIX_0F73_REG_3 */
3745   {
3746     { Bad_Opcode },
3747     { Bad_Opcode },
3748     { "psrldq", { XS, Ib }, 0 },
3749   },
3750
3751   /* PREFIX_0F73_REG_7 */
3752   {
3753     { Bad_Opcode },
3754     { Bad_Opcode },
3755     { "pslldq", { XS, Ib }, 0 },
3756   },
3757
3758   /* PREFIX_0F78 */
3759   {
3760     {"vmread",  { Em, Gm }, 0 },
3761     { Bad_Opcode },
3762     {"extrq",   { XS, Ib, Ib }, 0 },
3763     {"insertq", { XM, XS, Ib, Ib }, 0 },
3764   },
3765
3766   /* PREFIX_0F79 */
3767   {
3768     {"vmwrite", { Gm, Em }, 0 },
3769     { Bad_Opcode },
3770     {"extrq",   { XM, XS }, 0 },
3771     {"insertq", { XM, XS }, 0 },
3772   },
3773
3774   /* PREFIX_0F7C */
3775   {
3776     { Bad_Opcode },
3777     { Bad_Opcode },
3778     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3779     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3780   },
3781
3782   /* PREFIX_0F7D */
3783   {
3784     { Bad_Opcode },
3785     { Bad_Opcode },
3786     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3787     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3788   },
3789
3790   /* PREFIX_0F7E */
3791   {
3792     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3793     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3794     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_0F7F */
3798   {
3799     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3800     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3801     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3802   },
3803
3804   /* PREFIX_0FAE_REG_0_MOD_3 */
3805   {
3806     { Bad_Opcode },
3807     { "rdfsbase", { Ev }, 0 },
3808   },
3809
3810   /* PREFIX_0FAE_REG_1_MOD_3 */
3811   {
3812     { Bad_Opcode },
3813     { "rdgsbase", { Ev }, 0 },
3814   },
3815
3816   /* PREFIX_0FAE_REG_2_MOD_3 */
3817   {
3818     { Bad_Opcode },
3819     { "wrfsbase", { Ev }, 0 },
3820   },
3821
3822   /* PREFIX_0FAE_REG_3_MOD_3 */
3823   {
3824     { Bad_Opcode },
3825     { "wrgsbase", { Ev }, 0 },
3826   },
3827
3828   /* PREFIX_0FAE_REG_4_MOD_0 */
3829   {
3830     { "xsave",  { FXSAVE }, 0 },
3831     { "ptwrite%LQ", { Edq }, 0 },
3832   },
3833
3834   /* PREFIX_0FAE_REG_4_MOD_3 */
3835   {
3836     { Bad_Opcode },
3837     { "ptwrite%LQ", { Edq }, 0 },
3838   },
3839
3840   /* PREFIX_0FAE_REG_5_MOD_0 */
3841   {
3842     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3843   },
3844
3845   /* PREFIX_0FAE_REG_5_MOD_3 */
3846   {
3847     { "lfence",         { Skip_MODRM }, 0 },
3848     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3849   },
3850
3851   /* PREFIX_0FAE_REG_6_MOD_0 */
3852   {
3853     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3854     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3855     { "clwb",   { Mb }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0FAE_REG_6_MOD_3 */
3859   {
3860     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3861     { "umonitor",       { Eva }, PREFIX_OPCODE },
3862     { "tpause", { Edq }, PREFIX_OPCODE },
3863     { "umwait", { Edq }, PREFIX_OPCODE },
3864   },
3865
3866   /* PREFIX_0FAE_REG_7_MOD_0 */
3867   {
3868     { "clflush",        { Mb }, 0 },
3869     { Bad_Opcode },
3870     { "clflushopt",     { Mb }, 0 },
3871   },
3872
3873   /* PREFIX_0FB8 */
3874   {
3875     { Bad_Opcode },
3876     { "popcntS", { Gv, Ev }, 0 },
3877   },
3878
3879   /* PREFIX_0FBC */
3880   {
3881     { "bsfS",   { Gv, Ev }, 0 },
3882     { "tzcntS", { Gv, Ev }, 0 },
3883     { "bsfS",   { Gv, Ev }, 0 },
3884   },
3885
3886   /* PREFIX_0FBD */
3887   {
3888     { "bsrS",   { Gv, Ev }, 0 },
3889     { "lzcntS", { Gv, Ev }, 0 },
3890     { "bsrS",   { Gv, Ev }, 0 },
3891   },
3892
3893   /* PREFIX_0FC2 */
3894   {
3895     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3896     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3897     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3898     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3899   },
3900
3901   /* PREFIX_0FC3_MOD_0 */
3902   {
3903     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3904   },
3905
3906   /* PREFIX_0FC7_REG_6_MOD_0 */
3907   {
3908     { "vmptrld",{ Mq }, 0 },
3909     { "vmxon",  { Mq }, 0 },
3910     { "vmclear",{ Mq }, 0 },
3911   },
3912
3913   /* PREFIX_0FC7_REG_6_MOD_3 */
3914   {
3915     { "rdrand", { Ev }, 0 },
3916     { Bad_Opcode },
3917     { "rdrand", { Ev }, 0 }
3918   },
3919
3920   /* PREFIX_0FC7_REG_7_MOD_3 */
3921   {
3922     { "rdseed", { Ev }, 0 },
3923     { "rdpid",  { Em }, 0 },
3924     { "rdseed", { Ev }, 0 },
3925   },
3926
3927   /* PREFIX_0FD0 */
3928   {
3929     { Bad_Opcode },
3930     { Bad_Opcode },
3931     { "addsubpd", { XM, EXx }, 0 },
3932     { "addsubps", { XM, EXx }, 0 },
3933   },
3934
3935   /* PREFIX_0FD6 */
3936   {
3937     { Bad_Opcode },
3938     { "movq2dq",{ XM, MS }, 0 },
3939     { "movq",   { EXqS, XM }, 0 },
3940     { "movdq2q",{ MX, XS }, 0 },
3941   },
3942
3943   /* PREFIX_0FE6 */
3944   {
3945     { Bad_Opcode },
3946     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3947     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3948     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3949   },
3950
3951   /* PREFIX_0FE7 */
3952   {
3953     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3954     { Bad_Opcode },
3955     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3956   },
3957
3958   /* PREFIX_0FF0 */
3959   {
3960     { Bad_Opcode },
3961     { Bad_Opcode },
3962     { Bad_Opcode },
3963     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3964   },
3965
3966   /* PREFIX_0FF7 */
3967   {
3968     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3969     { Bad_Opcode },
3970     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3971   },
3972
3973   /* PREFIX_0F3810 */
3974   {
3975     { Bad_Opcode },
3976     { Bad_Opcode },
3977     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_0F3814 */
3981   {
3982     { Bad_Opcode },
3983     { Bad_Opcode },
3984     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_0F3815 */
3988   {
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
3992   },
3993
3994   /* PREFIX_0F3817 */
3995   {
3996     { Bad_Opcode },
3997     { Bad_Opcode },
3998     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
3999   },
4000
4001   /* PREFIX_0F3820 */
4002   {
4003     { Bad_Opcode },
4004     { Bad_Opcode },
4005     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0F3821 */
4009   {
4010     { Bad_Opcode },
4011     { Bad_Opcode },
4012     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4013   },
4014
4015   /* PREFIX_0F3822 */
4016   {
4017     { Bad_Opcode },
4018     { Bad_Opcode },
4019     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4020   },
4021
4022   /* PREFIX_0F3823 */
4023   {
4024     { Bad_Opcode },
4025     { Bad_Opcode },
4026     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4027   },
4028
4029   /* PREFIX_0F3824 */
4030   {
4031     { Bad_Opcode },
4032     { Bad_Opcode },
4033     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4034   },
4035
4036   /* PREFIX_0F3825 */
4037   {
4038     { Bad_Opcode },
4039     { Bad_Opcode },
4040     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4041   },
4042
4043   /* PREFIX_0F3828 */
4044   {
4045     { Bad_Opcode },
4046     { Bad_Opcode },
4047     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4048   },
4049
4050   /* PREFIX_0F3829 */
4051   {
4052     { Bad_Opcode },
4053     { Bad_Opcode },
4054     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4055   },
4056
4057   /* PREFIX_0F382A */
4058   {
4059     { Bad_Opcode },
4060     { Bad_Opcode },
4061     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4062   },
4063
4064   /* PREFIX_0F382B */
4065   {
4066     { Bad_Opcode },
4067     { Bad_Opcode },
4068     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4069   },
4070
4071   /* PREFIX_0F3830 */
4072   {
4073     { Bad_Opcode },
4074     { Bad_Opcode },
4075     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4076   },
4077
4078   /* PREFIX_0F3831 */
4079   {
4080     { Bad_Opcode },
4081     { Bad_Opcode },
4082     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4083   },
4084
4085   /* PREFIX_0F3832 */
4086   {
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4090   },
4091
4092   /* PREFIX_0F3833 */
4093   {
4094     { Bad_Opcode },
4095     { Bad_Opcode },
4096     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4097   },
4098
4099   /* PREFIX_0F3834 */
4100   {
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4104   },
4105
4106   /* PREFIX_0F3835 */
4107   {
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0F3837 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4118   },
4119
4120   /* PREFIX_0F3838 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_0F3839 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F383A */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F383B */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0F383C */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4153   },
4154
4155   /* PREFIX_0F383D */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F383E */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4167   },
4168
4169   /* PREFIX_0F383F */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0F3840 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F3841 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4188   },
4189
4190   /* PREFIX_0F3880 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F3881 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4202   },
4203
4204   /* PREFIX_0F3882 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F38C8 */
4212   {
4213     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4214   },
4215
4216   /* PREFIX_0F38C9 */
4217   {
4218     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4219   },
4220
4221   /* PREFIX_0F38CA */
4222   {
4223     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4224   },
4225
4226   /* PREFIX_0F38CB */
4227   {
4228     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4229   },
4230
4231   /* PREFIX_0F38CC */
4232   {
4233     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4234   },
4235
4236   /* PREFIX_0F38CD */
4237   {
4238     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F38CF */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F38DB */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F38DC */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F38DD */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F38DE */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F38DF */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F38F0 */
4284   {
4285     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4286     { Bad_Opcode },
4287     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4288     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4289   },
4290
4291   /* PREFIX_0F38F1 */
4292   {
4293     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4294     { Bad_Opcode },
4295     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4296     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4297   },
4298
4299   /* PREFIX_0F38F5 */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4304   },
4305
4306   /* PREFIX_0F38F6 */
4307   {
4308     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4309     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4310     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4311     { Bad_Opcode },
4312   },
4313
4314   /* PREFIX_0F38F8 */
4315   {
4316     { Bad_Opcode },
4317     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4318     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4319     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4320   },
4321
4322   /* PREFIX_0F38F9 */
4323   {
4324     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4325   },
4326
4327   /* PREFIX_0F3A08 */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4332   },
4333
4334   /* PREFIX_0F3A09 */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4339   },
4340
4341   /* PREFIX_0F3A0A */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4346   },
4347
4348   /* PREFIX_0F3A0B */
4349   {
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4353   },
4354
4355   /* PREFIX_0F3A0C */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F3A0D */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4367   },
4368
4369   /* PREFIX_0F3A0E */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F3A14 */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F3A15 */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F3A16 */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4395   },
4396
4397   /* PREFIX_0F3A17 */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4402   },
4403
4404   /* PREFIX_0F3A20 */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4409   },
4410
4411   /* PREFIX_0F3A21 */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4416   },
4417
4418   /* PREFIX_0F3A22 */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4423   },
4424
4425   /* PREFIX_0F3A40 */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4430   },
4431
4432   /* PREFIX_0F3A41 */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F3A42 */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4444   },
4445
4446   /* PREFIX_0F3A44 */
4447   {
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4451   },
4452
4453   /* PREFIX_0F3A60 */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4458   },
4459
4460   /* PREFIX_0F3A61 */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4465   },
4466
4467   /* PREFIX_0F3A62 */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4472   },
4473
4474   /* PREFIX_0F3A63 */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4479   },
4480
4481   /* PREFIX_0F3ACC */
4482   {
4483     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4484   },
4485
4486   /* PREFIX_0F3ACE */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F3ACF */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F3ADF */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_VEX_0F10 */
4508   {
4509     { "vmovups",        { XM, EXx }, 0 },
4510     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4511     { "vmovupd",        { XM, EXx }, 0 },
4512     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4513   },
4514
4515   /* PREFIX_VEX_0F11 */
4516   {
4517     { "vmovups",        { EXxS, XM }, 0 },
4518     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4519     { "vmovupd",        { EXxS, XM }, 0 },
4520     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4521   },
4522
4523   /* PREFIX_VEX_0F12 */
4524   {
4525     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4526     { "vmovsldup",      { XM, EXx }, 0 },
4527     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4528     { "vmovddup",       { XM, EXymmq }, 0 },
4529   },
4530
4531   /* PREFIX_VEX_0F16 */
4532   {
4533     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4534     { "vmovshdup",      { XM, EXx }, 0 },
4535     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4536   },
4537
4538   /* PREFIX_VEX_0F2A */
4539   {
4540     { Bad_Opcode },
4541     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4542     { Bad_Opcode },
4543     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4544   },
4545
4546   /* PREFIX_VEX_0F2C */
4547   {
4548     { Bad_Opcode },
4549     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4550     { Bad_Opcode },
4551     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4552   },
4553
4554   /* PREFIX_VEX_0F2D */
4555   {
4556     { Bad_Opcode },
4557     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4558     { Bad_Opcode },
4559     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4560   },
4561
4562   /* PREFIX_VEX_0F2E */
4563   {
4564     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4565     { Bad_Opcode },
4566     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4567   },
4568
4569   /* PREFIX_VEX_0F2F */
4570   {
4571     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4572     { Bad_Opcode },
4573     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4574   },
4575
4576   /* PREFIX_VEX_0F41 */
4577   {
4578     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4579     { Bad_Opcode },
4580     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4581   },
4582
4583   /* PREFIX_VEX_0F42 */
4584   {
4585     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4586     { Bad_Opcode },
4587     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4588   },
4589
4590   /* PREFIX_VEX_0F44 */
4591   {
4592     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4593     { Bad_Opcode },
4594     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4595   },
4596
4597   /* PREFIX_VEX_0F45 */
4598   {
4599     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4600     { Bad_Opcode },
4601     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4602   },
4603
4604   /* PREFIX_VEX_0F46 */
4605   {
4606     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4607     { Bad_Opcode },
4608     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4609   },
4610
4611   /* PREFIX_VEX_0F47 */
4612   {
4613     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4614     { Bad_Opcode },
4615     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4616   },
4617
4618   /* PREFIX_VEX_0F4A */
4619   {
4620     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4621     { Bad_Opcode },
4622     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4623   },
4624
4625   /* PREFIX_VEX_0F4B */
4626   {
4627     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4628     { Bad_Opcode },
4629     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4630   },
4631
4632   /* PREFIX_VEX_0F51 */
4633   {
4634     { "vsqrtps",        { XM, EXx }, 0 },
4635     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4636     { "vsqrtpd",        { XM, EXx }, 0 },
4637     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4638   },
4639
4640   /* PREFIX_VEX_0F52 */
4641   {
4642     { "vrsqrtps",       { XM, EXx }, 0 },
4643     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4644   },
4645
4646   /* PREFIX_VEX_0F53 */
4647   {
4648     { "vrcpps",         { XM, EXx }, 0 },
4649     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4650   },
4651
4652   /* PREFIX_VEX_0F58 */
4653   {
4654     { "vaddps",         { XM, Vex, EXx }, 0 },
4655     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4656     { "vaddpd",         { XM, Vex, EXx }, 0 },
4657     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4658   },
4659
4660   /* PREFIX_VEX_0F59 */
4661   {
4662     { "vmulps",         { XM, Vex, EXx }, 0 },
4663     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4664     { "vmulpd",         { XM, Vex, EXx }, 0 },
4665     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4666   },
4667
4668   /* PREFIX_VEX_0F5A */
4669   {
4670     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4671     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4672     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4673     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4674   },
4675
4676   /* PREFIX_VEX_0F5B */
4677   {
4678     { "vcvtdq2ps",      { XM, EXx }, 0 },
4679     { "vcvttps2dq",     { XM, EXx }, 0 },
4680     { "vcvtps2dq",      { XM, EXx }, 0 },
4681   },
4682
4683   /* PREFIX_VEX_0F5C */
4684   {
4685     { "vsubps",         { XM, Vex, EXx }, 0 },
4686     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4687     { "vsubpd",         { XM, Vex, EXx }, 0 },
4688     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4689   },
4690
4691   /* PREFIX_VEX_0F5D */
4692   {
4693     { "vminps",         { XM, Vex, EXx }, 0 },
4694     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4695     { "vminpd",         { XM, Vex, EXx }, 0 },
4696     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4697   },
4698
4699   /* PREFIX_VEX_0F5E */
4700   {
4701     { "vdivps",         { XM, Vex, EXx }, 0 },
4702     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4703     { "vdivpd",         { XM, Vex, EXx }, 0 },
4704     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4705   },
4706
4707   /* PREFIX_VEX_0F5F */
4708   {
4709     { "vmaxps",         { XM, Vex, EXx }, 0 },
4710     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4711     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4712     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4713   },
4714
4715   /* PREFIX_VEX_0F60 */
4716   {
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4720   },
4721
4722   /* PREFIX_VEX_0F61 */
4723   {
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4727   },
4728
4729   /* PREFIX_VEX_0F62 */
4730   {
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4734   },
4735
4736   /* PREFIX_VEX_0F63 */
4737   {
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4741   },
4742
4743   /* PREFIX_VEX_0F64 */
4744   {
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4748   },
4749
4750   /* PREFIX_VEX_0F65 */
4751   {
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4755   },
4756
4757   /* PREFIX_VEX_0F66 */
4758   {
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4762   },
4763
4764   /* PREFIX_VEX_0F67 */
4765   {
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4769   },
4770
4771   /* PREFIX_VEX_0F68 */
4772   {
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4776   },
4777
4778   /* PREFIX_VEX_0F69 */
4779   {
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4783   },
4784
4785   /* PREFIX_VEX_0F6A */
4786   {
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4790   },
4791
4792   /* PREFIX_VEX_0F6B */
4793   {
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4797   },
4798
4799   /* PREFIX_VEX_0F6C */
4800   {
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4804   },
4805
4806   /* PREFIX_VEX_0F6D */
4807   {
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4811   },
4812
4813   /* PREFIX_VEX_0F6E */
4814   {
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4818   },
4819
4820   /* PREFIX_VEX_0F6F */
4821   {
4822     { Bad_Opcode },
4823     { "vmovdqu",        { XM, EXx }, 0 },
4824     { "vmovdqa",        { XM, EXx }, 0 },
4825   },
4826
4827   /* PREFIX_VEX_0F70 */
4828   {
4829     { Bad_Opcode },
4830     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4831     { "vpshufd",        { XM, EXx, Ib }, 0 },
4832     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4833   },
4834
4835   /* PREFIX_VEX_0F71_REG_2 */
4836   {
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4840   },
4841
4842   /* PREFIX_VEX_0F71_REG_4 */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { "vpsraw",         { Vex, XS, Ib }, 0 },
4847   },
4848
4849   /* PREFIX_VEX_0F71_REG_6 */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { "vpsllw",         { Vex, XS, Ib }, 0 },
4854   },
4855
4856   /* PREFIX_VEX_0F72_REG_2 */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { "vpsrld",         { Vex, XS, Ib }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F72_REG_4 */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { "vpsrad",         { Vex, XS, Ib }, 0 },
4868   },
4869
4870   /* PREFIX_VEX_0F72_REG_6 */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { "vpslld",         { Vex, XS, Ib }, 0 },
4875   },
4876
4877   /* PREFIX_VEX_0F73_REG_2 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4882   },
4883
4884   /* PREFIX_VEX_0F73_REG_3 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { "vpsrldq",        { Vex, XS, Ib }, 0 },
4889   },
4890
4891   /* PREFIX_VEX_0F73_REG_6 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { "vpsllq",         { Vex, XS, Ib }, 0 },
4896   },
4897
4898   /* PREFIX_VEX_0F73_REG_7 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "vpslldq",        { Vex, XS, Ib }, 0 },
4903   },
4904
4905   /* PREFIX_VEX_0F74 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
4910   },
4911
4912   /* PREFIX_VEX_0F75 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
4917   },
4918
4919   /* PREFIX_VEX_0F76 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
4924   },
4925
4926   /* PREFIX_VEX_0F77 */
4927   {
4928     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
4929   },
4930
4931   /* PREFIX_VEX_0F7C */
4932   {
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { "vhaddpd",        { XM, Vex, EXx }, 0 },
4936     { "vhaddps",        { XM, Vex, EXx }, 0 },
4937   },
4938
4939   /* PREFIX_VEX_0F7D */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { "vhsubpd",        { XM, Vex, EXx }, 0 },
4944     { "vhsubps",        { XM, Vex, EXx }, 0 },
4945   },
4946
4947   /* PREFIX_VEX_0F7E */
4948   {
4949     { Bad_Opcode },
4950     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4951     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4952   },
4953
4954   /* PREFIX_VEX_0F7F */
4955   {
4956     { Bad_Opcode },
4957     { "vmovdqu",        { EXxS, XM }, 0 },
4958     { "vmovdqa",        { EXxS, XM }, 0 },
4959   },
4960
4961   /* PREFIX_VEX_0F90 */
4962   {
4963     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4964     { Bad_Opcode },
4965     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
4966   },
4967
4968   /* PREFIX_VEX_0F91 */
4969   {
4970     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4971     { Bad_Opcode },
4972     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
4973   },
4974
4975   /* PREFIX_VEX_0F92 */
4976   {
4977     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4978     { Bad_Opcode },
4979     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
4980     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
4981   },
4982
4983   /* PREFIX_VEX_0F93 */
4984   {
4985     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4986     { Bad_Opcode },
4987     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
4988     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
4989   },
4990
4991   /* PREFIX_VEX_0F98 */
4992   {
4993     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4994     { Bad_Opcode },
4995     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
4996   },
4997
4998   /* PREFIX_VEX_0F99 */
4999   {
5000     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5001     { Bad_Opcode },
5002     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5003   },
5004
5005   /* PREFIX_VEX_0FC2 */
5006   {
5007     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5008     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5009     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5010     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5011   },
5012
5013   /* PREFIX_VEX_0FC4 */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5018   },
5019
5020   /* PREFIX_VEX_0FC5 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5025   },
5026
5027   /* PREFIX_VEX_0FD0 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5032     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5033   },
5034
5035   /* PREFIX_VEX_0FD1 */
5036   {
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5040   },
5041
5042   /* PREFIX_VEX_0FD2 */
5043   {
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5047   },
5048
5049   /* PREFIX_VEX_0FD3 */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5054   },
5055
5056   /* PREFIX_VEX_0FD4 */
5057   {
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { "vpaddq",         { XM, Vex, EXx }, 0 },
5061   },
5062
5063   /* PREFIX_VEX_0FD5 */
5064   {
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { "vpmullw",        { XM, Vex, EXx }, 0 },
5068   },
5069
5070   /* PREFIX_VEX_0FD6 */
5071   {
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5075   },
5076
5077   /* PREFIX_VEX_0FD7 */
5078   {
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5082   },
5083
5084   /* PREFIX_VEX_0FD8 */
5085   {
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5089   },
5090
5091   /* PREFIX_VEX_0FD9 */
5092   {
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5096   },
5097
5098   /* PREFIX_VEX_0FDA */
5099   {
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { "vpminub",        { XM, Vex, EXx }, 0 },
5103   },
5104
5105   /* PREFIX_VEX_0FDB */
5106   {
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { "vpand",          { XM, Vex, EXx }, 0 },
5110   },
5111
5112   /* PREFIX_VEX_0FDC */
5113   {
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5117   },
5118
5119   /* PREFIX_VEX_0FDD */
5120   {
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5124   },
5125
5126   /* PREFIX_VEX_0FDE */
5127   {
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5131   },
5132
5133   /* PREFIX_VEX_0FDF */
5134   {
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { "vpandn",         { XM, Vex, EXx }, 0 },
5138   },
5139
5140   /* PREFIX_VEX_0FE0 */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { "vpavgb",         { XM, Vex, EXx }, 0 },
5145   },
5146
5147   /* PREFIX_VEX_0FE1 */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5152   },
5153
5154   /* PREFIX_VEX_0FE2 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5159   },
5160
5161   /* PREFIX_VEX_0FE3 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { "vpavgw",         { XM, Vex, EXx }, 0 },
5166   },
5167
5168   /* PREFIX_VEX_0FE4 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5173   },
5174
5175   /* PREFIX_VEX_0FE5 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5180   },
5181
5182   /* PREFIX_VEX_0FE6 */
5183   {
5184     { Bad_Opcode },
5185     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5186     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5187     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5188   },
5189
5190   /* PREFIX_VEX_0FE7 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5195   },
5196
5197   /* PREFIX_VEX_0FE8 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5202   },
5203
5204   /* PREFIX_VEX_0FE9 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5209   },
5210
5211   /* PREFIX_VEX_0FEA */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { "vpminsw",        { XM, Vex, EXx }, 0 },
5216   },
5217
5218   /* PREFIX_VEX_0FEB */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { "vpor",           { XM, Vex, EXx }, 0 },
5223   },
5224
5225   /* PREFIX_VEX_0FEC */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5230   },
5231
5232   /* PREFIX_VEX_0FED */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5237   },
5238
5239   /* PREFIX_VEX_0FEE */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5244   },
5245
5246   /* PREFIX_VEX_0FEF */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vpxor",          { XM, Vex, EXx }, 0 },
5251   },
5252
5253   /* PREFIX_VEX_0FF0 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5259   },
5260
5261   /* PREFIX_VEX_0FF1 */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5266   },
5267
5268   /* PREFIX_VEX_0FF2 */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5273   },
5274
5275   /* PREFIX_VEX_0FF3 */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5280   },
5281
5282   /* PREFIX_VEX_0FF4 */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5287   },
5288
5289   /* PREFIX_VEX_0FF5 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FF6 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5301   },
5302
5303   /* PREFIX_VEX_0FF7 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0FF8 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { "vpsubb",         { XM, Vex, EXx }, 0 },
5315   },
5316
5317   /* PREFIX_VEX_0FF9 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { "vpsubw",         { XM, Vex, EXx }, 0 },
5322   },
5323
5324   /* PREFIX_VEX_0FFA */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { "vpsubd",         { XM, Vex, EXx }, 0 },
5329   },
5330
5331   /* PREFIX_VEX_0FFB */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { "vpsubq",         { XM, Vex, EXx }, 0 },
5336   },
5337
5338   /* PREFIX_VEX_0FFC */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { "vpaddb",         { XM, Vex, EXx }, 0 },
5343   },
5344
5345   /* PREFIX_VEX_0FFD */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { "vpaddw",         { XM, Vex, EXx }, 0 },
5350   },
5351
5352   /* PREFIX_VEX_0FFE */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { "vpaddd",         { XM, Vex, EXx }, 0 },
5357   },
5358
5359   /* PREFIX_VEX_0F3800 */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { "vpshufb",        { XM, Vex, EXx }, 0 },
5364   },
5365
5366   /* PREFIX_VEX_0F3801 */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { "vphaddw",        { XM, Vex, EXx }, 0 },
5371   },
5372
5373   /* PREFIX_VEX_0F3802 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { "vphaddd",        { XM, Vex, EXx }, 0 },
5378   },
5379
5380   /* PREFIX_VEX_0F3803 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5385   },
5386
5387   /* PREFIX_VEX_0F3804 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5392   },
5393
5394   /* PREFIX_VEX_0F3805 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { "vphsubw",        { XM, Vex, EXx }, 0 },
5399   },
5400
5401   /* PREFIX_VEX_0F3806 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { "vphsubd",        { XM, Vex, EXx }, 0 },
5406   },
5407
5408   /* PREFIX_VEX_0F3807 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5413   },
5414
5415   /* PREFIX_VEX_0F3808 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { "vpsignb",        { XM, Vex, EXx }, 0 },
5420   },
5421
5422   /* PREFIX_VEX_0F3809 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { "vpsignw",        { XM, Vex, EXx }, 0 },
5427   },
5428
5429   /* PREFIX_VEX_0F380A */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { "vpsignd",        { XM, Vex, EXx }, 0 },
5434   },
5435
5436   /* PREFIX_VEX_0F380B */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5441   },
5442
5443   /* PREFIX_VEX_0F380C */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5448   },
5449
5450   /* PREFIX_VEX_0F380D */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5455   },
5456
5457   /* PREFIX_VEX_0F380E */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5462   },
5463
5464   /* PREFIX_VEX_0F380F */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5469   },
5470
5471   /* PREFIX_VEX_0F3813 */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5476   },
5477
5478   /* PREFIX_VEX_0F3816 */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5483   },
5484
5485   /* PREFIX_VEX_0F3817 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { "vptest",         { XM, EXx }, 0 },
5490   },
5491
5492   /* PREFIX_VEX_0F3818 */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5497   },
5498
5499   /* PREFIX_VEX_0F3819 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5504   },
5505
5506   /* PREFIX_VEX_0F381A */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5511   },
5512
5513   /* PREFIX_VEX_0F381C */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { "vpabsb",         { XM, EXx }, 0 },
5518   },
5519
5520   /* PREFIX_VEX_0F381D */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { "vpabsw",         { XM, EXx }, 0 },
5525   },
5526
5527   /* PREFIX_VEX_0F381E */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { "vpabsd",         { XM, EXx }, 0 },
5532   },
5533
5534   /* PREFIX_VEX_0F3820 */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5539   },
5540
5541   /* PREFIX_VEX_0F3821 */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5546   },
5547
5548   /* PREFIX_VEX_0F3822 */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5553   },
5554
5555   /* PREFIX_VEX_0F3823 */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5560   },
5561
5562   /* PREFIX_VEX_0F3824 */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5567   },
5568
5569   /* PREFIX_VEX_0F3825 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5574   },
5575
5576   /* PREFIX_VEX_0F3828 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5581   },
5582
5583   /* PREFIX_VEX_0F3829 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5588   },
5589
5590   /* PREFIX_VEX_0F382A */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5595   },
5596
5597   /* PREFIX_VEX_0F382B */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5602   },
5603
5604   /* PREFIX_VEX_0F382C */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F382D */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5616   },
5617
5618   /* PREFIX_VEX_0F382E */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F382F */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F3830 */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5637   },
5638
5639   /* PREFIX_VEX_0F3831 */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5644   },
5645
5646   /* PREFIX_VEX_0F3832 */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5651   },
5652
5653   /* PREFIX_VEX_0F3833 */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5658   },
5659
5660   /* PREFIX_VEX_0F3834 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5665   },
5666
5667   /* PREFIX_VEX_0F3835 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5672   },
5673
5674   /* PREFIX_VEX_0F3836 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5679   },
5680
5681   /* PREFIX_VEX_0F3837 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5686   },
5687
5688   /* PREFIX_VEX_0F3838 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { "vpminsb",        { XM, Vex, EXx }, 0 },
5693   },
5694
5695   /* PREFIX_VEX_0F3839 */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { "vpminsd",        { XM, Vex, EXx }, 0 },
5700   },
5701
5702   /* PREFIX_VEX_0F383A */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { "vpminuw",        { XM, Vex, EXx }, 0 },
5707   },
5708
5709   /* PREFIX_VEX_0F383B */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { "vpminud",        { XM, Vex, EXx }, 0 },
5714   },
5715
5716   /* PREFIX_VEX_0F383C */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5721   },
5722
5723   /* PREFIX_VEX_0F383D */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5728   },
5729
5730   /* PREFIX_VEX_0F383E */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5735   },
5736
5737   /* PREFIX_VEX_0F383F */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5742   },
5743
5744   /* PREFIX_VEX_0F3840 */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { "vpmulld",        { XM, Vex, EXx }, 0 },
5749   },
5750
5751   /* PREFIX_VEX_0F3841 */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F3845 */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5763   },
5764
5765   /* PREFIX_VEX_0F3846 */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5770   },
5771
5772   /* PREFIX_VEX_0F3847 */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5777   },
5778
5779   /* PREFIX_VEX_0F3858 */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5784   },
5785
5786   /* PREFIX_VEX_0F3859 */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5791   },
5792
5793   /* PREFIX_VEX_0F385A */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5798   },
5799
5800   /* PREFIX_VEX_0F3878 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5805   },
5806
5807   /* PREFIX_VEX_0F3879 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5812   },
5813
5814   /* PREFIX_VEX_0F388C */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5819   },
5820
5821   /* PREFIX_VEX_0F388E */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5826   },
5827
5828   /* PREFIX_VEX_0F3890 */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5833   },
5834
5835   /* PREFIX_VEX_0F3891 */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5840   },
5841
5842   /* PREFIX_VEX_0F3892 */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5847   },
5848
5849   /* PREFIX_VEX_0F3893 */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5854   },
5855
5856   /* PREFIX_VEX_0F3896 */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5861   },
5862
5863   /* PREFIX_VEX_0F3897 */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5868   },
5869
5870   /* PREFIX_VEX_0F3898 */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5875   },
5876
5877   /* PREFIX_VEX_0F3899 */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5882   },
5883
5884   /* PREFIX_VEX_0F389A */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5889   },
5890
5891   /* PREFIX_VEX_0F389B */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5896   },
5897
5898   /* PREFIX_VEX_0F389C */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5903   },
5904
5905   /* PREFIX_VEX_0F389D */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5910   },
5911
5912   /* PREFIX_VEX_0F389E */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5917   },
5918
5919   /* PREFIX_VEX_0F389F */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5924   },
5925
5926   /* PREFIX_VEX_0F38A6 */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5931     { Bad_Opcode },
5932   },
5933
5934   /* PREFIX_VEX_0F38A7 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5939   },
5940
5941   /* PREFIX_VEX_0F38A8 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5946   },
5947
5948   /* PREFIX_VEX_0F38A9 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5953   },
5954
5955   /* PREFIX_VEX_0F38AA */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
5960   },
5961
5962   /* PREFIX_VEX_0F38AB */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5967   },
5968
5969   /* PREFIX_VEX_0F38AC */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5974   },
5975
5976   /* PREFIX_VEX_0F38AD */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5981   },
5982
5983   /* PREFIX_VEX_0F38AE */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5988   },
5989
5990   /* PREFIX_VEX_0F38AF */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5995   },
5996
5997   /* PREFIX_VEX_0F38B6 */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F38B7 */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F38B8 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F38B9 */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F38BA */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F38BB */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F38BC */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F38BD */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F38BE */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F38BF */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F38CF */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6072   },
6073
6074   /* PREFIX_VEX_0F38DB */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6079   },
6080
6081   /* PREFIX_VEX_0F38DC */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vaesenc",        { XM, Vex, EXx }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F38DD */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6093   },
6094
6095   /* PREFIX_VEX_0F38DE */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vaesdec",        { XM, Vex, EXx }, 0 },
6100   },
6101
6102   /* PREFIX_VEX_0F38DF */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6107   },
6108
6109   /* PREFIX_VEX_0F38F2 */
6110   {
6111     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6112   },
6113
6114   /* PREFIX_VEX_0F38F3_REG_1 */
6115   {
6116     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6117   },
6118
6119   /* PREFIX_VEX_0F38F3_REG_2 */
6120   {
6121     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6122   },
6123
6124   /* PREFIX_VEX_0F38F3_REG_3 */
6125   {
6126     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6127   },
6128
6129   /* PREFIX_VEX_0F38F5 */
6130   {
6131     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6132     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6133     { Bad_Opcode },
6134     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6135   },
6136
6137   /* PREFIX_VEX_0F38F6 */
6138   {
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6143   },
6144
6145   /* PREFIX_VEX_0F38F7 */
6146   {
6147     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6148     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6149     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6150     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6151   },
6152
6153   /* PREFIX_VEX_0F3A00 */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6158   },
6159
6160   /* PREFIX_VEX_0F3A01 */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6165   },
6166
6167   /* PREFIX_VEX_0F3A02 */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6172   },
6173
6174   /* PREFIX_VEX_0F3A04 */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6179   },
6180
6181   /* PREFIX_VEX_0F3A05 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6186   },
6187
6188   /* PREFIX_VEX_0F3A06 */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6193   },
6194
6195   /* PREFIX_VEX_0F3A08 */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { "vroundps",       { XM, EXx, Ib }, 0 },
6200   },
6201
6202   /* PREFIX_VEX_0F3A09 */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vroundpd",       { XM, EXx, Ib }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F3A0A */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F3A0B */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F3A0C */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F3A0D */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6235   },
6236
6237   /* PREFIX_VEX_0F3A0E */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6242   },
6243
6244   /* PREFIX_VEX_0F3A0F */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6249   },
6250
6251   /* PREFIX_VEX_0F3A14 */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6256   },
6257
6258   /* PREFIX_VEX_0F3A15 */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6263   },
6264
6265   /* PREFIX_VEX_0F3A16 */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6270   },
6271
6272   /* PREFIX_VEX_0F3A17 */
6273   {
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6277   },
6278
6279   /* PREFIX_VEX_0F3A18 */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6284   },
6285
6286   /* PREFIX_VEX_0F3A19 */
6287   {
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6291   },
6292
6293   /* PREFIX_VEX_0F3A1D */
6294   {
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6298   },
6299
6300   /* PREFIX_VEX_0F3A20 */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6305   },
6306
6307   /* PREFIX_VEX_0F3A21 */
6308   {
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6312   },
6313
6314   /* PREFIX_VEX_0F3A22 */
6315   {
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6319   },
6320
6321   /* PREFIX_VEX_0F3A30 */
6322   {
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6326   },
6327
6328   /* PREFIX_VEX_0F3A31 */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6333   },
6334
6335   /* PREFIX_VEX_0F3A32 */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6340   },
6341
6342   /* PREFIX_VEX_0F3A33 */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6347   },
6348
6349   /* PREFIX_VEX_0F3A38 */
6350   {
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6354   },
6355
6356   /* PREFIX_VEX_0F3A39 */
6357   {
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6361   },
6362
6363   /* PREFIX_VEX_0F3A40 */
6364   {
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6368   },
6369
6370   /* PREFIX_VEX_0F3A41 */
6371   {
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6375   },
6376
6377   /* PREFIX_VEX_0F3A42 */
6378   {
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6382   },
6383
6384   /* PREFIX_VEX_0F3A44 */
6385   {
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6389   },
6390
6391   /* PREFIX_VEX_0F3A46 */
6392   {
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6396   },
6397
6398   /* PREFIX_VEX_0F3A48 */
6399   {
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6403   },
6404
6405   /* PREFIX_VEX_0F3A49 */
6406   {
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6410   },
6411
6412   /* PREFIX_VEX_0F3A4A */
6413   {
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6417   },
6418
6419   /* PREFIX_VEX_0F3A4B */
6420   {
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6424   },
6425
6426   /* PREFIX_VEX_0F3A4C */
6427   {
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6431   },
6432
6433   /* PREFIX_VEX_0F3A5C */
6434   {
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6438   },
6439
6440   /* PREFIX_VEX_0F3A5D */
6441   {
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6445   },
6446
6447   /* PREFIX_VEX_0F3A5E */
6448   {
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6452   },
6453
6454   /* PREFIX_VEX_0F3A5F */
6455   {
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6459   },
6460
6461   /* PREFIX_VEX_0F3A60 */
6462   {
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6466     { Bad_Opcode },
6467   },
6468
6469   /* PREFIX_VEX_0F3A61 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A62 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A63 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A68 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6495   },
6496
6497   /* PREFIX_VEX_0F3A69 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6502   },
6503
6504   /* PREFIX_VEX_0F3A6A */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6509   },
6510
6511   /* PREFIX_VEX_0F3A6B */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6516   },
6517
6518   /* PREFIX_VEX_0F3A6C */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6523   },
6524
6525   /* PREFIX_VEX_0F3A6D */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6530   },
6531
6532   /* PREFIX_VEX_0F3A6E */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6537   },
6538
6539   /* PREFIX_VEX_0F3A6F */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6544   },
6545
6546   /* PREFIX_VEX_0F3A78 */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6551   },
6552
6553   /* PREFIX_VEX_0F3A79 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6558   },
6559
6560   /* PREFIX_VEX_0F3A7A */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6565   },
6566
6567   /* PREFIX_VEX_0F3A7B */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6572   },
6573
6574   /* PREFIX_VEX_0F3A7C */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6579     { Bad_Opcode },
6580   },
6581
6582   /* PREFIX_VEX_0F3A7D */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6587   },
6588
6589   /* PREFIX_VEX_0F3A7E */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6594   },
6595
6596   /* PREFIX_VEX_0F3A7F */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6601   },
6602
6603   /* PREFIX_VEX_0F3ACE */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6608   },
6609
6610   /* PREFIX_VEX_0F3ACF */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6615   },
6616
6617   /* PREFIX_VEX_0F3ADF */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6622   },
6623
6624   /* PREFIX_VEX_0F3AF0 */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6630   },
6631
6632 #include "i386-dis-evex-prefix.h"
6633 };
6634
6635 static const struct dis386 x86_64_table[][2] = {
6636   /* X86_64_06 */
6637   {
6638     { "pushP", { es }, 0 },
6639   },
6640
6641   /* X86_64_07 */
6642   {
6643     { "popP", { es }, 0 },
6644   },
6645
6646   /* X86_64_0E */
6647   {
6648     { "pushP", { cs }, 0 },
6649   },
6650
6651   /* X86_64_16 */
6652   {
6653     { "pushP", { ss }, 0 },
6654   },
6655
6656   /* X86_64_17 */
6657   {
6658     { "popP", { ss }, 0 },
6659   },
6660
6661   /* X86_64_1E */
6662   {
6663     { "pushP", { ds }, 0 },
6664   },
6665
6666   /* X86_64_1F */
6667   {
6668     { "popP", { ds }, 0 },
6669   },
6670
6671   /* X86_64_27 */
6672   {
6673     { "daa", { XX }, 0 },
6674   },
6675
6676   /* X86_64_2F */
6677   {
6678     { "das", { XX }, 0 },
6679   },
6680
6681   /* X86_64_37 */
6682   {
6683     { "aaa", { XX }, 0 },
6684   },
6685
6686   /* X86_64_3F */
6687   {
6688     { "aas", { XX }, 0 },
6689   },
6690
6691   /* X86_64_60 */
6692   {
6693     { "pushaP", { XX }, 0 },
6694   },
6695
6696   /* X86_64_61 */
6697   {
6698     { "popaP", { XX }, 0 },
6699   },
6700
6701   /* X86_64_62 */
6702   {
6703     { MOD_TABLE (MOD_62_32BIT) },
6704     { EVEX_TABLE (EVEX_0F) },
6705   },
6706
6707   /* X86_64_63 */
6708   {
6709     { "arpl", { Ew, Gw }, 0 },
6710     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6711   },
6712
6713   /* X86_64_6D */
6714   {
6715     { "ins{R|}", { Yzr, indirDX }, 0 },
6716     { "ins{G|}", { Yzr, indirDX }, 0 },
6717   },
6718
6719   /* X86_64_6F */
6720   {
6721     { "outs{R|}", { indirDXr, Xz }, 0 },
6722     { "outs{G|}", { indirDXr, Xz }, 0 },
6723   },
6724
6725   /* X86_64_82 */
6726   {
6727     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6728     { REG_TABLE (REG_80) },
6729   },
6730
6731   /* X86_64_9A */
6732   {
6733     { "{l|}call{T|}", { Ap }, 0 },
6734   },
6735
6736   /* X86_64_C2 */
6737   {
6738     { "retP",           { Iw, BND }, 0 },
6739     { "ret@",           { Iw, BND }, 0 },
6740   },
6741
6742   /* X86_64_C3 */
6743   {
6744     { "retP",           { BND }, 0 },
6745     { "ret@",           { BND }, 0 },
6746   },
6747
6748   /* X86_64_C4 */
6749   {
6750     { MOD_TABLE (MOD_C4_32BIT) },
6751     { VEX_C4_TABLE (VEX_0F) },
6752   },
6753
6754   /* X86_64_C5 */
6755   {
6756     { MOD_TABLE (MOD_C5_32BIT) },
6757     { VEX_C5_TABLE (VEX_0F) },
6758   },
6759
6760   /* X86_64_CE */
6761   {
6762     { "into", { XX }, 0 },
6763   },
6764
6765   /* X86_64_D4 */
6766   {
6767     { "aam", { Ib }, 0 },
6768   },
6769
6770   /* X86_64_D5 */
6771   {
6772     { "aad", { Ib }, 0 },
6773   },
6774
6775   /* X86_64_E8 */
6776   {
6777     { "callP",          { Jv, BND }, 0 },
6778     { "call@",          { Jv, BND }, 0 }
6779   },
6780
6781   /* X86_64_E9 */
6782   {
6783     { "jmpP",           { Jv, BND }, 0 },
6784     { "jmp@",           { Jv, BND }, 0 }
6785   },
6786
6787   /* X86_64_EA */
6788   {
6789     { "{l|}jmp{T|}", { Ap }, 0 },
6790   },
6791
6792   /* X86_64_0F01_REG_0 */
6793   {
6794     { "sgdt{Q|Q}", { M }, 0 },
6795     { "sgdt", { M }, 0 },
6796   },
6797
6798   /* X86_64_0F01_REG_1 */
6799   {
6800     { "sidt{Q|Q}", { M }, 0 },
6801     { "sidt", { M }, 0 },
6802   },
6803
6804   /* X86_64_0F01_REG_2 */
6805   {
6806     { "lgdt{Q|Q}", { M }, 0 },
6807     { "lgdt", { M }, 0 },
6808   },
6809
6810   /* X86_64_0F01_REG_3 */
6811   {
6812     { "lidt{Q|Q}", { M }, 0 },
6813     { "lidt", { M }, 0 },
6814   },
6815 };
6816
6817 static const struct dis386 three_byte_table[][256] = {
6818
6819   /* THREE_BYTE_0F38 */
6820   {
6821     /* 00 */
6822     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6823     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6824     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6825     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6826     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6827     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6828     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6829     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6830     /* 08 */
6831     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6832     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6833     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6834     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     /* 10 */
6840     { PREFIX_TABLE (PREFIX_0F3810) },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { PREFIX_TABLE (PREFIX_0F3814) },
6845     { PREFIX_TABLE (PREFIX_0F3815) },
6846     { Bad_Opcode },
6847     { PREFIX_TABLE (PREFIX_0F3817) },
6848     /* 18 */
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6854     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6855     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6856     { Bad_Opcode },
6857     /* 20 */
6858     { PREFIX_TABLE (PREFIX_0F3820) },
6859     { PREFIX_TABLE (PREFIX_0F3821) },
6860     { PREFIX_TABLE (PREFIX_0F3822) },
6861     { PREFIX_TABLE (PREFIX_0F3823) },
6862     { PREFIX_TABLE (PREFIX_0F3824) },
6863     { PREFIX_TABLE (PREFIX_0F3825) },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     /* 28 */
6867     { PREFIX_TABLE (PREFIX_0F3828) },
6868     { PREFIX_TABLE (PREFIX_0F3829) },
6869     { PREFIX_TABLE (PREFIX_0F382A) },
6870     { PREFIX_TABLE (PREFIX_0F382B) },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     /* 30 */
6876     { PREFIX_TABLE (PREFIX_0F3830) },
6877     { PREFIX_TABLE (PREFIX_0F3831) },
6878     { PREFIX_TABLE (PREFIX_0F3832) },
6879     { PREFIX_TABLE (PREFIX_0F3833) },
6880     { PREFIX_TABLE (PREFIX_0F3834) },
6881     { PREFIX_TABLE (PREFIX_0F3835) },
6882     { Bad_Opcode },
6883     { PREFIX_TABLE (PREFIX_0F3837) },
6884     /* 38 */
6885     { PREFIX_TABLE (PREFIX_0F3838) },
6886     { PREFIX_TABLE (PREFIX_0F3839) },
6887     { PREFIX_TABLE (PREFIX_0F383A) },
6888     { PREFIX_TABLE (PREFIX_0F383B) },
6889     { PREFIX_TABLE (PREFIX_0F383C) },
6890     { PREFIX_TABLE (PREFIX_0F383D) },
6891     { PREFIX_TABLE (PREFIX_0F383E) },
6892     { PREFIX_TABLE (PREFIX_0F383F) },
6893     /* 40 */
6894     { PREFIX_TABLE (PREFIX_0F3840) },
6895     { PREFIX_TABLE (PREFIX_0F3841) },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     /* 48 */
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     /* 50 */
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     /* 58 */
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     /* 60 */
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     /* 68 */
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     /* 70 */
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     /* 78 */
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     /* 80 */
6966     { PREFIX_TABLE (PREFIX_0F3880) },
6967     { PREFIX_TABLE (PREFIX_0F3881) },
6968     { PREFIX_TABLE (PREFIX_0F3882) },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     /* 88 */
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     /* 90 */
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     /* 98 */
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     /* a0 */
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     /* a8 */
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     /* b0 */
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     /* b8 */
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     /* c0 */
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     /* c8 */
7047     { PREFIX_TABLE (PREFIX_0F38C8) },
7048     { PREFIX_TABLE (PREFIX_0F38C9) },
7049     { PREFIX_TABLE (PREFIX_0F38CA) },
7050     { PREFIX_TABLE (PREFIX_0F38CB) },
7051     { PREFIX_TABLE (PREFIX_0F38CC) },
7052     { PREFIX_TABLE (PREFIX_0F38CD) },
7053     { Bad_Opcode },
7054     { PREFIX_TABLE (PREFIX_0F38CF) },
7055     /* d0 */
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     /* d8 */
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { PREFIX_TABLE (PREFIX_0F38DB) },
7069     { PREFIX_TABLE (PREFIX_0F38DC) },
7070     { PREFIX_TABLE (PREFIX_0F38DD) },
7071     { PREFIX_TABLE (PREFIX_0F38DE) },
7072     { PREFIX_TABLE (PREFIX_0F38DF) },
7073     /* e0 */
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* e8 */
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     /* f0 */
7092     { PREFIX_TABLE (PREFIX_0F38F0) },
7093     { PREFIX_TABLE (PREFIX_0F38F1) },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { PREFIX_TABLE (PREFIX_0F38F5) },
7098     { PREFIX_TABLE (PREFIX_0F38F6) },
7099     { Bad_Opcode },
7100     /* f8 */
7101     { PREFIX_TABLE (PREFIX_0F38F8) },
7102     { PREFIX_TABLE (PREFIX_0F38F9) },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109   },
7110   /* THREE_BYTE_0F3A */
7111   {
7112     /* 00 */
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     /* 08 */
7122     { PREFIX_TABLE (PREFIX_0F3A08) },
7123     { PREFIX_TABLE (PREFIX_0F3A09) },
7124     { PREFIX_TABLE (PREFIX_0F3A0A) },
7125     { PREFIX_TABLE (PREFIX_0F3A0B) },
7126     { PREFIX_TABLE (PREFIX_0F3A0C) },
7127     { PREFIX_TABLE (PREFIX_0F3A0D) },
7128     { PREFIX_TABLE (PREFIX_0F3A0E) },
7129     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7130     /* 10 */
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { PREFIX_TABLE (PREFIX_0F3A14) },
7136     { PREFIX_TABLE (PREFIX_0F3A15) },
7137     { PREFIX_TABLE (PREFIX_0F3A16) },
7138     { PREFIX_TABLE (PREFIX_0F3A17) },
7139     /* 18 */
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     /* 20 */
7149     { PREFIX_TABLE (PREFIX_0F3A20) },
7150     { PREFIX_TABLE (PREFIX_0F3A21) },
7151     { PREFIX_TABLE (PREFIX_0F3A22) },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     /* 28 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* 30 */
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* 38 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* 40 */
7185     { PREFIX_TABLE (PREFIX_0F3A40) },
7186     { PREFIX_TABLE (PREFIX_0F3A41) },
7187     { PREFIX_TABLE (PREFIX_0F3A42) },
7188     { Bad_Opcode },
7189     { PREFIX_TABLE (PREFIX_0F3A44) },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* 48 */
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* 50 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 58 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 60 */
7221     { PREFIX_TABLE (PREFIX_0F3A60) },
7222     { PREFIX_TABLE (PREFIX_0F3A61) },
7223     { PREFIX_TABLE (PREFIX_0F3A62) },
7224     { PREFIX_TABLE (PREFIX_0F3A63) },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* 68 */
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 70 */
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* 78 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* 80 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* 88 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 90 */
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* 98 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* a0 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* a8 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* b0 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* b8 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* c0 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* c8 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { PREFIX_TABLE (PREFIX_0F3ACC) },
7343     { Bad_Opcode },
7344     { PREFIX_TABLE (PREFIX_0F3ACE) },
7345     { PREFIX_TABLE (PREFIX_0F3ACF) },
7346     /* d0 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* d8 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { PREFIX_TABLE (PREFIX_0F3ADF) },
7364     /* e0 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* e8 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* f0 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* f8 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400   },
7401 };
7402
7403 static const struct dis386 xop_table[][256] = {
7404   /* XOP_08 */
7405   {
7406     /* 00 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* 08 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* 10 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* 18 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* 20 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* 28 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* 30 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* 38 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* 40 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* 48 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     /* 50 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* 58 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* 60 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* 68 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* 70 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* 78 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* 80 */
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7557     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7558     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7559     /* 88 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7567     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7568     /* 90 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7575     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7576     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7577     /* 98 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7585     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7586     /* a0 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
7590     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7594     { Bad_Opcode },
7595     /* a8 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     /* b0 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7612     { Bad_Opcode },
7613     /* b8 */
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     /* c0 */
7623     { "vprotb",         { XM, EXx, Ib }, 0 },
7624     { "vprotw",         { XM, EXx, Ib }, 0 },
7625     { "vprotd",         { XM, EXx, Ib }, 0 },
7626     { "vprotq",         { XM, EXx, Ib }, 0 },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     /* c8 */
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7637     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7638     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7639     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7640     /* d0 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     /* d8 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     /* e0 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* e8 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7673     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7674     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7675     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7676     /* f0 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* f8 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694   },
7695   /* XOP_09 */
7696   {
7697     /* 00 */
7698     { Bad_Opcode },
7699     { REG_TABLE (REG_XOP_TBM_01) },
7700     { REG_TABLE (REG_XOP_TBM_02) },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     /* 08 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     /* 10 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { REG_TABLE (REG_XOP_LWPCB) },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     /* 18 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     /* 20 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* 28 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* 30 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* 38 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* 40 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* 48 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* 50 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* 58 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* 60 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* 68 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     /* 70 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* 78 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 80 */
7842     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
7843     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
7844     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
7845     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 88 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 90 */
7860     { "vprotb",         { XM, EXx, VexW }, 0 },
7861     { "vprotw",         { XM, EXx, VexW }, 0 },
7862     { "vprotd",         { XM, EXx, VexW }, 0 },
7863     { "vprotq",         { XM, EXx, VexW }, 0 },
7864     { "vpshlb",         { XM, EXx, VexW }, 0 },
7865     { "vpshlw",         { XM, EXx, VexW }, 0 },
7866     { "vpshld",         { XM, EXx, VexW }, 0 },
7867     { "vpshlq",         { XM, EXx, VexW }, 0 },
7868     /* 98 */
7869     { "vpshab",         { XM, EXx, VexW }, 0 },
7870     { "vpshaw",         { XM, EXx, VexW }, 0 },
7871     { "vpshad",         { XM, EXx, VexW }, 0 },
7872     { "vpshaq",         { XM, EXx, VexW }, 0 },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     /* a0 */
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* a8 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* b0 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* b8 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* c0 */
7914     { Bad_Opcode },
7915     { "vphaddbw",       { XM, EXxmm }, 0 },
7916     { "vphaddbd",       { XM, EXxmm }, 0 },
7917     { "vphaddbq",       { XM, EXxmm }, 0 },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { "vphaddwd",       { XM, EXxmm }, 0 },
7921     { "vphaddwq",       { XM, EXxmm }, 0 },
7922     /* c8 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { "vphadddq",       { XM, EXxmm }, 0 },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* d0 */
7932     { Bad_Opcode },
7933     { "vphaddubw",      { XM, EXxmm }, 0 },
7934     { "vphaddubd",      { XM, EXxmm }, 0 },
7935     { "vphaddubq",      { XM, EXxmm }, 0 },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { "vphadduwd",      { XM, EXxmm }, 0 },
7939     { "vphadduwq",      { XM, EXxmm }, 0 },
7940     /* d8 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { "vphaddudq",      { XM, EXxmm }, 0 },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     /* e0 */
7950     { Bad_Opcode },
7951     { "vphsubbw",       { XM, EXxmm }, 0 },
7952     { "vphsubwd",       { XM, EXxmm }, 0 },
7953     { "vphsubdq",       { XM, EXxmm }, 0 },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     /* e8 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* f0 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* f8 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985   },
7986   /* XOP_0A */
7987   {
7988     /* 00 */
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     /* 08 */
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     /* 10 */
8007     { "bextrS", { Gdq, Edq, Id }, 0 },
8008     { Bad_Opcode },
8009     { REG_TABLE (REG_XOP_LWP) },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* 18 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* 20 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* 28 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* 30 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* 38 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* 40 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* 48 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* 50 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* 58 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* 60 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* 68 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* 70 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* 78 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 80 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 88 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 90 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 98 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* a0 */
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* a8 */
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* b0 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* b8 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* c0 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* c8 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* d0 */
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     /* d8 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* e0 */
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* e8 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* f0 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* f8 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276   },
8277 };
8278
8279 static const struct dis386 vex_table[][256] = {
8280   /* VEX_0F */
8281   {
8282     /* 00 */
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     /* 08 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* 10 */
8301     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8302     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8303     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8304     { MOD_TABLE (MOD_VEX_0F13) },
8305     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8306     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8307     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8308     { MOD_TABLE (MOD_VEX_0F17) },
8309     /* 18 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* 20 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* 28 */
8328     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8329     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8330     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8331     { MOD_TABLE (MOD_VEX_0F2B) },
8332     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8333     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8334     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8335     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8336     /* 30 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* 38 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* 40 */
8355     { Bad_Opcode },
8356     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8357     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8358     { Bad_Opcode },
8359     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8360     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8361     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8362     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8363     /* 48 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8367     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* 50 */
8373     { MOD_TABLE (MOD_VEX_0F50) },
8374     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8375     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8376     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8377     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8378     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8379     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8380     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8381     /* 58 */
8382     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8383     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8384     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8385     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8386     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8387     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8388     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8389     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8390     /* 60 */
8391     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8392     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8393     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8394     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8395     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8396     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8397     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8398     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8399     /* 68 */
8400     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8401     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8402     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8403     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8404     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8405     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8406     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8407     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8408     /* 70 */
8409     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8410     { REG_TABLE (REG_VEX_0F71) },
8411     { REG_TABLE (REG_VEX_0F72) },
8412     { REG_TABLE (REG_VEX_0F73) },
8413     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8414     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8415     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8416     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8417     /* 78 */
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8426     /* 80 */
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     /* 88 */
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     /* 90 */
8445     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8446     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8447     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     /* 98 */
8454     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     /* a0 */
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     /* a8 */
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { REG_TABLE (REG_VEX_0FAE) },
8479     { Bad_Opcode },
8480     /* b0 */
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     /* b8 */
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     /* c0 */
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8502     { Bad_Opcode },
8503     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8504     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8505     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8506     { Bad_Opcode },
8507     /* c8 */
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     /* d0 */
8517     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8518     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8519     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8520     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8521     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8522     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8523     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8524     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8525     /* d8 */
8526     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8527     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8528     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8529     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8530     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8531     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8532     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8533     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8534     /* e0 */
8535     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8536     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8537     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8538     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8539     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8540     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8541     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8542     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8543     /* e8 */
8544     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8545     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8546     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8547     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8548     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8549     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8550     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8551     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8552     /* f0 */
8553     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8557     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8558     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8559     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8560     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8561     /* f8 */
8562     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8566     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8569     { Bad_Opcode },
8570   },
8571   /* VEX_0F38 */
8572   {
8573     /* 00 */
8574     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8581     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8582     /* 08 */
8583     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8589     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8590     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8591     /* 10 */
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8600     /* 18 */
8601     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8604     { Bad_Opcode },
8605     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8608     { Bad_Opcode },
8609     /* 20 */
8610     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     /* 28 */
8619     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8623     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8627     /* 30 */
8628     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8633     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8636     /* 38 */
8637     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8645     /* 40 */
8646     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8654     /* 48 */
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     /* 50 */
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     /* 58 */
8673     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     /* 60 */
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     /* 68 */
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     /* 70 */
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     /* 78 */
8709     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     /* 80 */
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     /* 88 */
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8732     { Bad_Opcode },
8733     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8734     { Bad_Opcode },
8735     /* 90 */
8736     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8744     /* 98 */
8745     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8753     /* a0 */
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8762     /* a8 */
8763     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8771     /* b0 */
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8780     /* b8 */
8781     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8789     /* c0 */
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     /* c8 */
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8807     /* d0 */
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     /* d8 */
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8825     /* e0 */
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     /* e8 */
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     /* f0 */
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8847     { REG_TABLE (REG_VEX_0F38F3) },
8848     { Bad_Opcode },
8849     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8852     /* f8 */
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861   },
8862   /* VEX_0F3A */
8863   {
8864     /* 00 */
8865     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8868     { Bad_Opcode },
8869     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8872     { Bad_Opcode },
8873     /* 08 */
8874     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8882     /* 10 */
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8891     /* 18 */
8892     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     /* 20 */
8901     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     /* 28 */
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     /* 30 */
8919     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     /* 38 */
8928     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     /* 40 */
8937     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8940     { Bad_Opcode },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8942     { Bad_Opcode },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8944     { Bad_Opcode },
8945     /* 48 */
8946     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     /* 50 */
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     /* 58 */
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8972     /* 60 */
8973     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     /* 68 */
8982     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8990     /* 70 */
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     /* 78 */
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9008     /* 80 */
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     /* 88 */
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     /* 90 */
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     /* 98 */
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     /* a0 */
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     /* a8 */
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     /* b0 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     /* b8 */
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     /* c0 */
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     /* c8 */
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9097     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9098     /* d0 */
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     /* d8 */
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9116     /* e0 */
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     /* e8 */
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     /* f0 */
9135     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     /* f8 */
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152   },
9153 };
9154
9155 #include "i386-dis-evex.h"
9156
9157 static const struct dis386 vex_len_table[][2] = {
9158   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9159   {
9160     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9161   },
9162
9163   /* VEX_LEN_0F12_P_0_M_1 */
9164   {
9165     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9166   },
9167
9168   /* VEX_LEN_0F13_M_0 */
9169   {
9170     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9171   },
9172
9173   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9174   {
9175     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9176   },
9177
9178   /* VEX_LEN_0F16_P_0_M_1 */
9179   {
9180     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9181   },
9182
9183   /* VEX_LEN_0F17_M_0 */
9184   {
9185     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9186   },
9187
9188   /* VEX_LEN_0F41_P_0 */
9189   {
9190     { Bad_Opcode },
9191     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9192   },
9193   /* VEX_LEN_0F41_P_2 */
9194   {
9195     { Bad_Opcode },
9196     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9197   },
9198   /* VEX_LEN_0F42_P_0 */
9199   {
9200     { Bad_Opcode },
9201     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9202   },
9203   /* VEX_LEN_0F42_P_2 */
9204   {
9205     { Bad_Opcode },
9206     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9207   },
9208   /* VEX_LEN_0F44_P_0 */
9209   {
9210     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9211   },
9212   /* VEX_LEN_0F44_P_2 */
9213   {
9214     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9215   },
9216   /* VEX_LEN_0F45_P_0 */
9217   {
9218     { Bad_Opcode },
9219     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9220   },
9221   /* VEX_LEN_0F45_P_2 */
9222   {
9223     { Bad_Opcode },
9224     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9225   },
9226   /* VEX_LEN_0F46_P_0 */
9227   {
9228     { Bad_Opcode },
9229     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9230   },
9231   /* VEX_LEN_0F46_P_2 */
9232   {
9233     { Bad_Opcode },
9234     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9235   },
9236   /* VEX_LEN_0F47_P_0 */
9237   {
9238     { Bad_Opcode },
9239     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9240   },
9241   /* VEX_LEN_0F47_P_2 */
9242   {
9243     { Bad_Opcode },
9244     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9245   },
9246   /* VEX_LEN_0F4A_P_0 */
9247   {
9248     { Bad_Opcode },
9249     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9250   },
9251   /* VEX_LEN_0F4A_P_2 */
9252   {
9253     { Bad_Opcode },
9254     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9255   },
9256   /* VEX_LEN_0F4B_P_0 */
9257   {
9258     { Bad_Opcode },
9259     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9260   },
9261   /* VEX_LEN_0F4B_P_2 */
9262   {
9263     { Bad_Opcode },
9264     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9265   },
9266
9267   /* VEX_LEN_0F6E_P_2 */
9268   {
9269     { "vmovK",          { XMScalar, Edq }, 0 },
9270   },
9271
9272   /* VEX_LEN_0F77_P_1 */
9273   {
9274     { "vzeroupper",     { XX }, 0 },
9275     { "vzeroall",       { XX }, 0 },
9276   },
9277
9278   /* VEX_LEN_0F7E_P_1 */
9279   {
9280     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9281   },
9282
9283   /* VEX_LEN_0F7E_P_2 */
9284   {
9285     { "vmovK",          { Edq, XMScalar }, 0 },
9286   },
9287
9288   /* VEX_LEN_0F90_P_0 */
9289   {
9290     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9291   },
9292
9293   /* VEX_LEN_0F90_P_2 */
9294   {
9295     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9296   },
9297
9298   /* VEX_LEN_0F91_P_0 */
9299   {
9300     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9301   },
9302
9303   /* VEX_LEN_0F91_P_2 */
9304   {
9305     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9306   },
9307
9308   /* VEX_LEN_0F92_P_0 */
9309   {
9310     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9311   },
9312
9313   /* VEX_LEN_0F92_P_2 */
9314   {
9315     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9316   },
9317
9318   /* VEX_LEN_0F92_P_3 */
9319   {
9320     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9321   },
9322
9323   /* VEX_LEN_0F93_P_0 */
9324   {
9325     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9326   },
9327
9328   /* VEX_LEN_0F93_P_2 */
9329   {
9330     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9331   },
9332
9333   /* VEX_LEN_0F93_P_3 */
9334   {
9335     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9336   },
9337
9338   /* VEX_LEN_0F98_P_0 */
9339   {
9340     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9341   },
9342
9343   /* VEX_LEN_0F98_P_2 */
9344   {
9345     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9346   },
9347
9348   /* VEX_LEN_0F99_P_0 */
9349   {
9350     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9351   },
9352
9353   /* VEX_LEN_0F99_P_2 */
9354   {
9355     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9356   },
9357
9358   /* VEX_LEN_0FAE_R_2_M_0 */
9359   {
9360     { "vldmxcsr",       { Md }, 0 },
9361   },
9362
9363   /* VEX_LEN_0FAE_R_3_M_0 */
9364   {
9365     { "vstmxcsr",       { Md }, 0 },
9366   },
9367
9368   /* VEX_LEN_0FC4_P_2 */
9369   {
9370     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9371   },
9372
9373   /* VEX_LEN_0FC5_P_2 */
9374   {
9375     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9376   },
9377
9378   /* VEX_LEN_0FD6_P_2 */
9379   {
9380     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9381   },
9382
9383   /* VEX_LEN_0FF7_P_2 */
9384   {
9385     { "vmaskmovdqu",    { XM, XS }, 0 },
9386   },
9387
9388   /* VEX_LEN_0F3816_P_2 */
9389   {
9390     { Bad_Opcode },
9391     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9392   },
9393
9394   /* VEX_LEN_0F3819_P_2 */
9395   {
9396     { Bad_Opcode },
9397     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9398   },
9399
9400   /* VEX_LEN_0F381A_P_2_M_0 */
9401   {
9402     { Bad_Opcode },
9403     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9404   },
9405
9406   /* VEX_LEN_0F3836_P_2 */
9407   {
9408     { Bad_Opcode },
9409     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9410   },
9411
9412   /* VEX_LEN_0F3841_P_2 */
9413   {
9414     { "vphminposuw",    { XM, EXx }, 0 },
9415   },
9416
9417   /* VEX_LEN_0F385A_P_2_M_0 */
9418   {
9419     { Bad_Opcode },
9420     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9421   },
9422
9423   /* VEX_LEN_0F38DB_P_2 */
9424   {
9425     { "vaesimc",        { XM, EXx }, 0 },
9426   },
9427
9428   /* VEX_LEN_0F38F2_P_0 */
9429   {
9430     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9431   },
9432
9433   /* VEX_LEN_0F38F3_R_1_P_0 */
9434   {
9435     { "blsrS",          { VexGdq, Edq }, 0 },
9436   },
9437
9438   /* VEX_LEN_0F38F3_R_2_P_0 */
9439   {
9440     { "blsmskS",        { VexGdq, Edq }, 0 },
9441   },
9442
9443   /* VEX_LEN_0F38F3_R_3_P_0 */
9444   {
9445     { "blsiS",          { VexGdq, Edq }, 0 },
9446   },
9447
9448   /* VEX_LEN_0F38F5_P_0 */
9449   {
9450     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9451   },
9452
9453   /* VEX_LEN_0F38F5_P_1 */
9454   {
9455     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9456   },
9457
9458   /* VEX_LEN_0F38F5_P_3 */
9459   {
9460     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9461   },
9462
9463   /* VEX_LEN_0F38F6_P_3 */
9464   {
9465     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9466   },
9467
9468   /* VEX_LEN_0F38F7_P_0 */
9469   {
9470     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9471   },
9472
9473   /* VEX_LEN_0F38F7_P_1 */
9474   {
9475     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9476   },
9477
9478   /* VEX_LEN_0F38F7_P_2 */
9479   {
9480     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9481   },
9482
9483   /* VEX_LEN_0F38F7_P_3 */
9484   {
9485     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9486   },
9487
9488   /* VEX_LEN_0F3A00_P_2 */
9489   {
9490     { Bad_Opcode },
9491     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9492   },
9493
9494   /* VEX_LEN_0F3A01_P_2 */
9495   {
9496     { Bad_Opcode },
9497     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9498   },
9499
9500   /* VEX_LEN_0F3A06_P_2 */
9501   {
9502     { Bad_Opcode },
9503     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9504   },
9505
9506   /* VEX_LEN_0F3A14_P_2 */
9507   {
9508     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9509   },
9510
9511   /* VEX_LEN_0F3A15_P_2 */
9512   {
9513     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9514   },
9515
9516   /* VEX_LEN_0F3A16_P_2  */
9517   {
9518     { "vpextrK",        { Edq, XM, Ib }, 0 },
9519   },
9520
9521   /* VEX_LEN_0F3A17_P_2 */
9522   {
9523     { "vextractps",     { Edqd, XM, Ib }, 0 },
9524   },
9525
9526   /* VEX_LEN_0F3A18_P_2 */
9527   {
9528     { Bad_Opcode },
9529     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9530   },
9531
9532   /* VEX_LEN_0F3A19_P_2 */
9533   {
9534     { Bad_Opcode },
9535     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9536   },
9537
9538   /* VEX_LEN_0F3A20_P_2 */
9539   {
9540     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9541   },
9542
9543   /* VEX_LEN_0F3A21_P_2 */
9544   {
9545     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9546   },
9547
9548   /* VEX_LEN_0F3A22_P_2 */
9549   {
9550     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9551   },
9552
9553   /* VEX_LEN_0F3A30_P_2 */
9554   {
9555     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9556   },
9557
9558   /* VEX_LEN_0F3A31_P_2 */
9559   {
9560     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9561   },
9562
9563   /* VEX_LEN_0F3A32_P_2 */
9564   {
9565     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9566   },
9567
9568   /* VEX_LEN_0F3A33_P_2 */
9569   {
9570     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9571   },
9572
9573   /* VEX_LEN_0F3A38_P_2 */
9574   {
9575     { Bad_Opcode },
9576     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9577   },
9578
9579   /* VEX_LEN_0F3A39_P_2 */
9580   {
9581     { Bad_Opcode },
9582     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9583   },
9584
9585   /* VEX_LEN_0F3A41_P_2 */
9586   {
9587     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9588   },
9589
9590   /* VEX_LEN_0F3A46_P_2 */
9591   {
9592     { Bad_Opcode },
9593     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9594   },
9595
9596   /* VEX_LEN_0F3A60_P_2 */
9597   {
9598     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9599   },
9600
9601   /* VEX_LEN_0F3A61_P_2 */
9602   {
9603     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9604   },
9605
9606   /* VEX_LEN_0F3A62_P_2 */
9607   {
9608     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9609   },
9610
9611   /* VEX_LEN_0F3A63_P_2 */
9612   {
9613     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9614   },
9615
9616   /* VEX_LEN_0F3ADF_P_2 */
9617   {
9618     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9619   },
9620
9621   /* VEX_LEN_0F3AF0_P_3 */
9622   {
9623     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9624   },
9625
9626   /* VEX_LEN_0FXOP_08_CC */
9627   {
9628      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9629   },
9630
9631   /* VEX_LEN_0FXOP_08_CD */
9632   {
9633      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9634   },
9635
9636   /* VEX_LEN_0FXOP_08_CE */
9637   {
9638      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9639   },
9640
9641   /* VEX_LEN_0FXOP_08_CF */
9642   {
9643      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9644   },
9645
9646   /* VEX_LEN_0FXOP_08_EC */
9647   {
9648      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9649   },
9650
9651   /* VEX_LEN_0FXOP_08_ED */
9652   {
9653      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9654   },
9655
9656   /* VEX_LEN_0FXOP_08_EE */
9657   {
9658      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9659   },
9660
9661   /* VEX_LEN_0FXOP_08_EF */
9662   {
9663      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9664   },
9665
9666   /* VEX_LEN_0FXOP_09_82_W_0 */
9667   {
9668     { "vfrczss",        { XM, EXd }, 0 },
9669   },
9670
9671   /* VEX_LEN_0FXOP_09_83_W_0 */
9672   {
9673     { "vfrczsd",        { XM, EXq }, 0 },
9674   },
9675 };
9676
9677 #include "i386-dis-evex-len.h"
9678
9679 static const struct dis386 vex_w_table[][2] = {
9680   {
9681     /* VEX_W_0F41_P_0_LEN_1 */
9682     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9683     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9684   },
9685   {
9686     /* VEX_W_0F41_P_2_LEN_1 */
9687     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9688     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9689   },
9690   {
9691     /* VEX_W_0F42_P_0_LEN_1 */
9692     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9693     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9694   },
9695   {
9696     /* VEX_W_0F42_P_2_LEN_1 */
9697     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9698     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9699   },
9700   {
9701     /* VEX_W_0F44_P_0_LEN_0 */
9702     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9703     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9704   },
9705   {
9706     /* VEX_W_0F44_P_2_LEN_0 */
9707     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9708     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9709   },
9710   {
9711     /* VEX_W_0F45_P_0_LEN_1 */
9712     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9713     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9714   },
9715   {
9716     /* VEX_W_0F45_P_2_LEN_1 */
9717     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9718     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9719   },
9720   {
9721     /* VEX_W_0F46_P_0_LEN_1 */
9722     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9723     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9724   },
9725   {
9726     /* VEX_W_0F46_P_2_LEN_1 */
9727     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9728     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9729   },
9730   {
9731     /* VEX_W_0F47_P_0_LEN_1 */
9732     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9733     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9734   },
9735   {
9736     /* VEX_W_0F47_P_2_LEN_1 */
9737     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9738     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9739   },
9740   {
9741     /* VEX_W_0F4A_P_0_LEN_1 */
9742     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9743     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9744   },
9745   {
9746     /* VEX_W_0F4A_P_2_LEN_1 */
9747     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9748     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9749   },
9750   {
9751     /* VEX_W_0F4B_P_0_LEN_1 */
9752     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9753     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9754   },
9755   {
9756     /* VEX_W_0F4B_P_2_LEN_1 */
9757     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9758   },
9759   {
9760     /* VEX_W_0F90_P_0_LEN_0 */
9761     { "kmovw",          { MaskG, MaskE }, 0 },
9762     { "kmovq",          { MaskG, MaskE }, 0 },
9763   },
9764   {
9765     /* VEX_W_0F90_P_2_LEN_0 */
9766     { "kmovb",          { MaskG, MaskBDE }, 0 },
9767     { "kmovd",          { MaskG, MaskBDE }, 0 },
9768   },
9769   {
9770     /* VEX_W_0F91_P_0_LEN_0 */
9771     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9772     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9773   },
9774   {
9775     /* VEX_W_0F91_P_2_LEN_0 */
9776     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9777     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9778   },
9779   {
9780     /* VEX_W_0F92_P_0_LEN_0 */
9781     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9782   },
9783   {
9784     /* VEX_W_0F92_P_2_LEN_0 */
9785     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9786   },
9787   {
9788     /* VEX_W_0F93_P_0_LEN_0 */
9789     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9790   },
9791   {
9792     /* VEX_W_0F93_P_2_LEN_0 */
9793     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9794   },
9795   {
9796     /* VEX_W_0F98_P_0_LEN_0 */
9797     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9798     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9799   },
9800   {
9801     /* VEX_W_0F98_P_2_LEN_0 */
9802     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9803     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9804   },
9805   {
9806     /* VEX_W_0F99_P_0_LEN_0 */
9807     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9808     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9809   },
9810   {
9811     /* VEX_W_0F99_P_2_LEN_0 */
9812     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9813     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9814   },
9815   {
9816     /* VEX_W_0F380C_P_2  */
9817     { "vpermilps",      { XM, Vex, EXx }, 0 },
9818   },
9819   {
9820     /* VEX_W_0F380D_P_2  */
9821     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9822   },
9823   {
9824     /* VEX_W_0F380E_P_2  */
9825     { "vtestps",        { XM, EXx }, 0 },
9826   },
9827   {
9828     /* VEX_W_0F380F_P_2  */
9829     { "vtestpd",        { XM, EXx }, 0 },
9830   },
9831   {
9832     /* VEX_W_0F3813_P_2 */
9833     { "vcvtph2ps", { XM, EXxmmq }, 0 },
9834   },
9835   {
9836     /* VEX_W_0F3816_P_2  */
9837     { "vpermps",        { XM, Vex, EXx }, 0 },
9838   },
9839   {
9840     /* VEX_W_0F3818_P_2 */
9841     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
9842   },
9843   {
9844     /* VEX_W_0F3819_P_2 */
9845     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
9846   },
9847   {
9848     /* VEX_W_0F381A_P_2_M_0 */
9849     { "vbroadcastf128", { XM, Mxmm }, 0 },
9850   },
9851   {
9852     /* VEX_W_0F382C_P_2_M_0 */
9853     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
9854   },
9855   {
9856     /* VEX_W_0F382D_P_2_M_0 */
9857     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
9858   },
9859   {
9860     /* VEX_W_0F382E_P_2_M_0 */
9861     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
9862   },
9863   {
9864     /* VEX_W_0F382F_P_2_M_0 */
9865     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
9866   },
9867   {
9868     /* VEX_W_0F3836_P_2  */
9869     { "vpermd",         { XM, Vex, EXx }, 0 },
9870   },
9871   {
9872     /* VEX_W_0F3846_P_2 */
9873     { "vpsravd",        { XM, Vex, EXx }, 0 },
9874   },
9875   {
9876     /* VEX_W_0F3858_P_2 */
9877     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
9878   },
9879   {
9880     /* VEX_W_0F3859_P_2 */
9881     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
9882   },
9883   {
9884     /* VEX_W_0F385A_P_2_M_0 */
9885     { "vbroadcasti128", { XM, Mxmm }, 0 },
9886   },
9887   {
9888     /* VEX_W_0F3878_P_2 */
9889     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
9890   },
9891   {
9892     /* VEX_W_0F3879_P_2 */
9893     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
9894   },
9895   {
9896     /* VEX_W_0F38CF_P_2 */
9897     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
9898   },
9899   {
9900     /* VEX_W_0F3A00_P_2 */
9901     { Bad_Opcode },
9902     { "vpermq",         { XM, EXx, Ib }, 0 },
9903   },
9904   {
9905     /* VEX_W_0F3A01_P_2 */
9906     { Bad_Opcode },
9907     { "vpermpd",        { XM, EXx, Ib }, 0 },
9908   },
9909   {
9910     /* VEX_W_0F3A02_P_2 */
9911     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
9912   },
9913   {
9914     /* VEX_W_0F3A04_P_2 */
9915     { "vpermilps",      { XM, EXx, Ib }, 0 },
9916   },
9917   {
9918     /* VEX_W_0F3A05_P_2 */
9919     { "vpermilpd",      { XM, EXx, Ib }, 0 },
9920   },
9921   {
9922     /* VEX_W_0F3A06_P_2 */
9923     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
9924   },
9925   {
9926     /* VEX_W_0F3A18_P_2 */
9927     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
9928   },
9929   {
9930     /* VEX_W_0F3A19_P_2 */
9931     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
9932   },
9933   {
9934     /* VEX_W_0F3A1D_P_2 */
9935     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
9936   },
9937   {
9938     /* VEX_W_0F3A30_P_2_LEN_0 */
9939     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
9940     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
9941   },
9942   {
9943     /* VEX_W_0F3A31_P_2_LEN_0 */
9944     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
9945     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
9946   },
9947   {
9948     /* VEX_W_0F3A32_P_2_LEN_0 */
9949     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
9950     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
9951   },
9952   {
9953     /* VEX_W_0F3A33_P_2_LEN_0 */
9954     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
9955     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
9956   },
9957   {
9958     /* VEX_W_0F3A38_P_2 */
9959     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
9960   },
9961   {
9962     /* VEX_W_0F3A39_P_2 */
9963     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
9964   },
9965   {
9966     /* VEX_W_0F3A46_P_2 */
9967     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
9968   },
9969   {
9970     /* VEX_W_0F3A4A_P_2 */
9971     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
9972   },
9973   {
9974     /* VEX_W_0F3A4B_P_2 */
9975     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
9976   },
9977   {
9978     /* VEX_W_0F3A4C_P_2 */
9979     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
9980   },
9981   {
9982     /* VEX_W_0F3ACE_P_2 */
9983     { Bad_Opcode },
9984     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
9985   },
9986   {
9987     /* VEX_W_0F3ACF_P_2 */
9988     { Bad_Opcode },
9989     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
9990   },
9991   /* VEX_W_0FXOP_09_80 */
9992   {
9993     { "vfrczps",        { XM, EXx }, 0 },
9994   },
9995   /* VEX_W_0FXOP_09_81 */
9996   {
9997     { "vfrczpd",        { XM, EXx }, 0 },
9998   },
9999   /* VEX_W_0FXOP_09_82 */
10000   {
10001     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10002   },
10003   /* VEX_W_0FXOP_09_83 */
10004   {
10005     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10006   },
10007
10008 #include "i386-dis-evex-w.h"
10009 };
10010
10011 static const struct dis386 mod_table[][2] = {
10012   {
10013     /* MOD_8D */
10014     { "leaS",           { Gv, M }, 0 },
10015   },
10016   {
10017     /* MOD_C6_REG_7 */
10018     { Bad_Opcode },
10019     { RM_TABLE (RM_C6_REG_7) },
10020   },
10021   {
10022     /* MOD_C7_REG_7 */
10023     { Bad_Opcode },
10024     { RM_TABLE (RM_C7_REG_7) },
10025   },
10026   {
10027     /* MOD_FF_REG_3 */
10028     { "{l|}call^", { indirEp }, 0 },
10029   },
10030   {
10031     /* MOD_FF_REG_5 */
10032     { "{l|}jmp^", { indirEp }, 0 },
10033   },
10034   {
10035     /* MOD_0F01_REG_0 */
10036     { X86_64_TABLE (X86_64_0F01_REG_0) },
10037     { RM_TABLE (RM_0F01_REG_0) },
10038   },
10039   {
10040     /* MOD_0F01_REG_1 */
10041     { X86_64_TABLE (X86_64_0F01_REG_1) },
10042     { RM_TABLE (RM_0F01_REG_1) },
10043   },
10044   {
10045     /* MOD_0F01_REG_2 */
10046     { X86_64_TABLE (X86_64_0F01_REG_2) },
10047     { RM_TABLE (RM_0F01_REG_2) },
10048   },
10049   {
10050     /* MOD_0F01_REG_3 */
10051     { X86_64_TABLE (X86_64_0F01_REG_3) },
10052     { RM_TABLE (RM_0F01_REG_3) },
10053   },
10054   {
10055     /* MOD_0F01_REG_5 */
10056     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10057     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10058   },
10059   {
10060     /* MOD_0F01_REG_7 */
10061     { "invlpg",         { Mb }, 0 },
10062     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10063   },
10064   {
10065     /* MOD_0F12_PREFIX_0 */
10066     { "movlpX",         { XM, EXq }, 0 },
10067     { "movhlps",        { XM, EXq }, 0 },
10068   },
10069   {
10070     /* MOD_0F12_PREFIX_2 */
10071     { "movlpX", { XM, EXq }, 0 },
10072   },
10073   {
10074     /* MOD_0F13 */
10075     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10076   },
10077   {
10078     /* MOD_0F16_PREFIX_0 */
10079     { "movhpX",         { XM, EXq }, 0 },
10080     { "movlhps",        { XM, EXq }, 0 },
10081   },
10082   {
10083     /* MOD_0F16_PREFIX_2 */
10084     { "movhpX", { XM, EXq }, 0 },
10085   },
10086   {
10087     /* MOD_0F17 */
10088     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10089   },
10090   {
10091     /* MOD_0F18_REG_0 */
10092     { "prefetchnta",    { Mb }, 0 },
10093   },
10094   {
10095     /* MOD_0F18_REG_1 */
10096     { "prefetcht0",     { Mb }, 0 },
10097   },
10098   {
10099     /* MOD_0F18_REG_2 */
10100     { "prefetcht1",     { Mb }, 0 },
10101   },
10102   {
10103     /* MOD_0F18_REG_3 */
10104     { "prefetcht2",     { Mb }, 0 },
10105   },
10106   {
10107     /* MOD_0F18_REG_4 */
10108     { "nop/reserved",   { Mb }, 0 },
10109   },
10110   {
10111     /* MOD_0F18_REG_5 */
10112     { "nop/reserved",   { Mb }, 0 },
10113   },
10114   {
10115     /* MOD_0F18_REG_6 */
10116     { "nop/reserved",   { Mb }, 0 },
10117   },
10118   {
10119     /* MOD_0F18_REG_7 */
10120     { "nop/reserved",   { Mb }, 0 },
10121   },
10122   {
10123     /* MOD_0F1A_PREFIX_0 */
10124     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10125     { "nopQ",           { Ev }, 0 },
10126   },
10127   {
10128     /* MOD_0F1B_PREFIX_0 */
10129     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10130     { "nopQ",           { Ev }, 0 },
10131   },
10132   {
10133     /* MOD_0F1B_PREFIX_1 */
10134     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10135     { "nopQ",           { Ev }, 0 },
10136   },
10137   {
10138     /* MOD_0F1C_PREFIX_0 */
10139     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10140     { "nopQ",           { Ev }, 0 },
10141   },
10142   {
10143     /* MOD_0F1E_PREFIX_1 */
10144     { "nopQ",           { Ev }, 0 },
10145     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10146   },
10147   {
10148     /* MOD_0F24 */
10149     { Bad_Opcode },
10150     { "movL",           { Rd, Td }, 0 },
10151   },
10152   {
10153     /* MOD_0F26 */
10154     { Bad_Opcode },
10155     { "movL",           { Td, Rd }, 0 },
10156   },
10157   {
10158     /* MOD_0F2B_PREFIX_0 */
10159     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10160   },
10161   {
10162     /* MOD_0F2B_PREFIX_1 */
10163     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10164   },
10165   {
10166     /* MOD_0F2B_PREFIX_2 */
10167     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10168   },
10169   {
10170     /* MOD_0F2B_PREFIX_3 */
10171     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10172   },
10173   {
10174     /* MOD_0F50 */
10175     { Bad_Opcode },
10176     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10177   },
10178   {
10179     /* MOD_0F71_REG_2 */
10180     { Bad_Opcode },
10181     { "psrlw",          { MS, Ib }, 0 },
10182   },
10183   {
10184     /* MOD_0F71_REG_4 */
10185     { Bad_Opcode },
10186     { "psraw",          { MS, Ib }, 0 },
10187   },
10188   {
10189     /* MOD_0F71_REG_6 */
10190     { Bad_Opcode },
10191     { "psllw",          { MS, Ib }, 0 },
10192   },
10193   {
10194     /* MOD_0F72_REG_2 */
10195     { Bad_Opcode },
10196     { "psrld",          { MS, Ib }, 0 },
10197   },
10198   {
10199     /* MOD_0F72_REG_4 */
10200     { Bad_Opcode },
10201     { "psrad",          { MS, Ib }, 0 },
10202   },
10203   {
10204     /* MOD_0F72_REG_6 */
10205     { Bad_Opcode },
10206     { "pslld",          { MS, Ib }, 0 },
10207   },
10208   {
10209     /* MOD_0F73_REG_2 */
10210     { Bad_Opcode },
10211     { "psrlq",          { MS, Ib }, 0 },
10212   },
10213   {
10214     /* MOD_0F73_REG_3 */
10215     { Bad_Opcode },
10216     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10217   },
10218   {
10219     /* MOD_0F73_REG_6 */
10220     { Bad_Opcode },
10221     { "psllq",          { MS, Ib }, 0 },
10222   },
10223   {
10224     /* MOD_0F73_REG_7 */
10225     { Bad_Opcode },
10226     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10227   },
10228   {
10229     /* MOD_0FAE_REG_0 */
10230     { "fxsave",         { FXSAVE }, 0 },
10231     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10232   },
10233   {
10234     /* MOD_0FAE_REG_1 */
10235     { "fxrstor",        { FXSAVE }, 0 },
10236     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10237   },
10238   {
10239     /* MOD_0FAE_REG_2 */
10240     { "ldmxcsr",        { Md }, 0 },
10241     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10242   },
10243   {
10244     /* MOD_0FAE_REG_3 */
10245     { "stmxcsr",        { Md }, 0 },
10246     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10247   },
10248   {
10249     /* MOD_0FAE_REG_4 */
10250     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10251     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10252   },
10253   {
10254     /* MOD_0FAE_REG_5 */
10255     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10256     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10257   },
10258   {
10259     /* MOD_0FAE_REG_6 */
10260     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10261     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10262   },
10263   {
10264     /* MOD_0FAE_REG_7 */
10265     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10266     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10267   },
10268   {
10269     /* MOD_0FB2 */
10270     { "lssS",           { Gv, Mp }, 0 },
10271   },
10272   {
10273     /* MOD_0FB4 */
10274     { "lfsS",           { Gv, Mp }, 0 },
10275   },
10276   {
10277     /* MOD_0FB5 */
10278     { "lgsS",           { Gv, Mp }, 0 },
10279   },
10280   {
10281     /* MOD_0FC3 */
10282     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10283   },
10284   {
10285     /* MOD_0FC7_REG_3 */
10286     { "xrstors",        { FXSAVE }, 0 },
10287   },
10288   {
10289     /* MOD_0FC7_REG_4 */
10290     { "xsavec",         { FXSAVE }, 0 },
10291   },
10292   {
10293     /* MOD_0FC7_REG_5 */
10294     { "xsaves",         { FXSAVE }, 0 },
10295   },
10296   {
10297     /* MOD_0FC7_REG_6 */
10298     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10299     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10300   },
10301   {
10302     /* MOD_0FC7_REG_7 */
10303     { "vmptrst",        { Mq }, 0 },
10304     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10305   },
10306   {
10307     /* MOD_0FD7 */
10308     { Bad_Opcode },
10309     { "pmovmskb",       { Gdq, MS }, 0 },
10310   },
10311   {
10312     /* MOD_0FE7_PREFIX_2 */
10313     { "movntdq",        { Mx, XM }, 0 },
10314   },
10315   {
10316     /* MOD_0FF0_PREFIX_3 */
10317     { "lddqu",          { XM, M }, 0 },
10318   },
10319   {
10320     /* MOD_0F382A_PREFIX_2 */
10321     { "movntdqa",       { XM, Mx }, 0 },
10322   },
10323   {
10324     /* MOD_0F38F5_PREFIX_2 */
10325     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10326   },
10327   {
10328     /* MOD_0F38F6_PREFIX_0 */
10329     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10330   },
10331   {
10332     /* MOD_0F38F8_PREFIX_1 */
10333     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10334   },
10335   {
10336     /* MOD_0F38F8_PREFIX_2 */
10337     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10338   },
10339   {
10340     /* MOD_0F38F8_PREFIX_3 */
10341     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10342   },
10343   {
10344     /* MOD_0F38F9_PREFIX_0 */
10345     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10346   },
10347   {
10348     /* MOD_62_32BIT */
10349     { "bound{S|}",      { Gv, Ma }, 0 },
10350     { EVEX_TABLE (EVEX_0F) },
10351   },
10352   {
10353     /* MOD_C4_32BIT */
10354     { "lesS",           { Gv, Mp }, 0 },
10355     { VEX_C4_TABLE (VEX_0F) },
10356   },
10357   {
10358     /* MOD_C5_32BIT */
10359     { "ldsS",           { Gv, Mp }, 0 },
10360     { VEX_C5_TABLE (VEX_0F) },
10361   },
10362   {
10363     /* MOD_VEX_0F12_PREFIX_0 */
10364     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10365     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10366   },
10367   {
10368     /* MOD_VEX_0F12_PREFIX_2 */
10369     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10370   },
10371   {
10372     /* MOD_VEX_0F13 */
10373     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10374   },
10375   {
10376     /* MOD_VEX_0F16_PREFIX_0 */
10377     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10378     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10379   },
10380   {
10381     /* MOD_VEX_0F16_PREFIX_2 */
10382     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10383   },
10384   {
10385     /* MOD_VEX_0F17 */
10386     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10387   },
10388   {
10389     /* MOD_VEX_0F2B */
10390     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10391   },
10392   {
10393     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10394     { Bad_Opcode },
10395     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10396   },
10397   {
10398     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10399     { Bad_Opcode },
10400     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10401   },
10402   {
10403     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10404     { Bad_Opcode },
10405     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10406   },
10407   {
10408     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10409     { Bad_Opcode },
10410     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10411   },
10412   {
10413     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10414     { Bad_Opcode },
10415     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10416   },
10417   {
10418     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10419     { Bad_Opcode },
10420     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10421   },
10422   {
10423     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10424     { Bad_Opcode },
10425     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10426   },
10427   {
10428     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10429     { Bad_Opcode },
10430     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10431   },
10432   {
10433     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10434     { Bad_Opcode },
10435     { "knotw",          { MaskG, MaskR }, 0 },
10436   },
10437   {
10438     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10439     { Bad_Opcode },
10440     { "knotq",          { MaskG, MaskR }, 0 },
10441   },
10442   {
10443     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10444     { Bad_Opcode },
10445     { "knotb",          { MaskG, MaskR }, 0 },
10446   },
10447   {
10448     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10449     { Bad_Opcode },
10450     { "knotd",          { MaskG, MaskR }, 0 },
10451   },
10452   {
10453     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10454     { Bad_Opcode },
10455     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10456   },
10457   {
10458     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10459     { Bad_Opcode },
10460     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10461   },
10462   {
10463     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10464     { Bad_Opcode },
10465     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10466   },
10467   {
10468     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10469     { Bad_Opcode },
10470     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10471   },
10472  {
10473     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10474     { Bad_Opcode },
10475     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10476   },
10477   {
10478     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10479     { Bad_Opcode },
10480     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10481   },
10482   {
10483     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10484     { Bad_Opcode },
10485     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10486   },
10487   {
10488     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10489     { Bad_Opcode },
10490     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10491   },
10492   {
10493     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10494     { Bad_Opcode },
10495     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10496   },
10497   {
10498     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10499     { Bad_Opcode },
10500     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10501   },
10502   {
10503     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10504     { Bad_Opcode },
10505     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10506   },
10507   {
10508     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10509     { Bad_Opcode },
10510     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10511   },
10512   {
10513     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10514     { Bad_Opcode },
10515     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10516   },
10517   {
10518     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10519     { Bad_Opcode },
10520     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10521   },
10522   {
10523     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10524     { Bad_Opcode },
10525     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10526   },
10527   {
10528     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10529     { Bad_Opcode },
10530     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10531   },
10532   {
10533     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10534     { Bad_Opcode },
10535     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10536   },
10537   {
10538     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10539     { Bad_Opcode },
10540     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10541   },
10542   {
10543     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10544     { Bad_Opcode },
10545     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10546   },
10547   {
10548     /* MOD_VEX_0F50 */
10549     { Bad_Opcode },
10550     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10551   },
10552   {
10553     /* MOD_VEX_0F71_REG_2 */
10554     { Bad_Opcode },
10555     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10556   },
10557   {
10558     /* MOD_VEX_0F71_REG_4 */
10559     { Bad_Opcode },
10560     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10561   },
10562   {
10563     /* MOD_VEX_0F71_REG_6 */
10564     { Bad_Opcode },
10565     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10566   },
10567   {
10568     /* MOD_VEX_0F72_REG_2 */
10569     { Bad_Opcode },
10570     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10571   },
10572   {
10573     /* MOD_VEX_0F72_REG_4 */
10574     { Bad_Opcode },
10575     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10576   },
10577   {
10578     /* MOD_VEX_0F72_REG_6 */
10579     { Bad_Opcode },
10580     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10581   },
10582   {
10583     /* MOD_VEX_0F73_REG_2 */
10584     { Bad_Opcode },
10585     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10586   },
10587   {
10588     /* MOD_VEX_0F73_REG_3 */
10589     { Bad_Opcode },
10590     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10591   },
10592   {
10593     /* MOD_VEX_0F73_REG_6 */
10594     { Bad_Opcode },
10595     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10596   },
10597   {
10598     /* MOD_VEX_0F73_REG_7 */
10599     { Bad_Opcode },
10600     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10601   },
10602   {
10603     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10604     { "kmovw",          { Ew, MaskG }, 0 },
10605     { Bad_Opcode },
10606   },
10607   {
10608     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10609     { "kmovq",          { Eq, MaskG }, 0 },
10610     { Bad_Opcode },
10611   },
10612   {
10613     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10614     { "kmovb",          { Eb, MaskG }, 0 },
10615     { Bad_Opcode },
10616   },
10617   {
10618     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10619     { "kmovd",          { Ed, MaskG }, 0 },
10620     { Bad_Opcode },
10621   },
10622   {
10623     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10624     { Bad_Opcode },
10625     { "kmovw",          { MaskG, Rdq }, 0 },
10626   },
10627   {
10628     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10629     { Bad_Opcode },
10630     { "kmovb",          { MaskG, Rdq }, 0 },
10631   },
10632   {
10633     /* MOD_VEX_0F92_P_3_LEN_0 */
10634     { Bad_Opcode },
10635     { "kmovK",          { MaskG, Rdq }, 0 },
10636   },
10637   {
10638     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10639     { Bad_Opcode },
10640     { "kmovw",          { Gdq, MaskR }, 0 },
10641   },
10642   {
10643     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10644     { Bad_Opcode },
10645     { "kmovb",          { Gdq, MaskR }, 0 },
10646   },
10647   {
10648     /* MOD_VEX_0F93_P_3_LEN_0 */
10649     { Bad_Opcode },
10650     { "kmovK",          { Gdq, MaskR }, 0 },
10651   },
10652   {
10653     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10654     { Bad_Opcode },
10655     { "kortestw", { MaskG, MaskR }, 0 },
10656   },
10657   {
10658     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10659     { Bad_Opcode },
10660     { "kortestq", { MaskG, MaskR }, 0 },
10661   },
10662   {
10663     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10664     { Bad_Opcode },
10665     { "kortestb", { MaskG, MaskR }, 0 },
10666   },
10667   {
10668     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10669     { Bad_Opcode },
10670     { "kortestd", { MaskG, MaskR }, 0 },
10671   },
10672   {
10673     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10674     { Bad_Opcode },
10675     { "ktestw", { MaskG, MaskR }, 0 },
10676   },
10677   {
10678     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10679     { Bad_Opcode },
10680     { "ktestq", { MaskG, MaskR }, 0 },
10681   },
10682   {
10683     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10684     { Bad_Opcode },
10685     { "ktestb", { MaskG, MaskR }, 0 },
10686   },
10687   {
10688     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10689     { Bad_Opcode },
10690     { "ktestd", { MaskG, MaskR }, 0 },
10691   },
10692   {
10693     /* MOD_VEX_0FAE_REG_2 */
10694     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10695   },
10696   {
10697     /* MOD_VEX_0FAE_REG_3 */
10698     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10699   },
10700   {
10701     /* MOD_VEX_0FD7_PREFIX_2 */
10702     { Bad_Opcode },
10703     { "vpmovmskb",      { Gdq, XS }, 0 },
10704   },
10705   {
10706     /* MOD_VEX_0FE7_PREFIX_2 */
10707     { "vmovntdq",       { Mx, XM }, 0 },
10708   },
10709   {
10710     /* MOD_VEX_0FF0_PREFIX_3 */
10711     { "vlddqu",         { XM, M }, 0 },
10712   },
10713   {
10714     /* MOD_VEX_0F381A_PREFIX_2 */
10715     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10716   },
10717   {
10718     /* MOD_VEX_0F382A_PREFIX_2 */
10719     { "vmovntdqa",      { XM, Mx }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_0F382C_PREFIX_2 */
10723     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10724   },
10725   {
10726     /* MOD_VEX_0F382D_PREFIX_2 */
10727     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10728   },
10729   {
10730     /* MOD_VEX_0F382E_PREFIX_2 */
10731     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10732   },
10733   {
10734     /* MOD_VEX_0F382F_PREFIX_2 */
10735     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10736   },
10737   {
10738     /* MOD_VEX_0F385A_PREFIX_2 */
10739     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10740   },
10741   {
10742     /* MOD_VEX_0F388C_PREFIX_2 */
10743     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10744   },
10745   {
10746     /* MOD_VEX_0F388E_PREFIX_2 */
10747     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10748   },
10749   {
10750     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10751     { Bad_Opcode },
10752     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10753   },
10754   {
10755     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10756     { Bad_Opcode },
10757     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10758   },
10759   {
10760     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10761     { Bad_Opcode },
10762     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10763   },
10764   {
10765     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10766     { Bad_Opcode },
10767     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10768   },
10769   {
10770     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10771     { Bad_Opcode },
10772     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10773   },
10774   {
10775     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10776     { Bad_Opcode },
10777     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10778   },
10779   {
10780     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10781     { Bad_Opcode },
10782     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10783   },
10784   {
10785     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10786     { Bad_Opcode },
10787     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10788   },
10789
10790 #include "i386-dis-evex-mod.h"
10791 };
10792
10793 static const struct dis386 rm_table[][8] = {
10794   {
10795     /* RM_C6_REG_7 */
10796     { "xabort",         { Skip_MODRM, Ib }, 0 },
10797   },
10798   {
10799     /* RM_C7_REG_7 */
10800     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10801   },
10802   {
10803     /* RM_0F01_REG_0 */
10804     { "enclv",          { Skip_MODRM }, 0 },
10805     { "vmcall",         { Skip_MODRM }, 0 },
10806     { "vmlaunch",       { Skip_MODRM }, 0 },
10807     { "vmresume",       { Skip_MODRM }, 0 },
10808     { "vmxoff",         { Skip_MODRM }, 0 },
10809     { "pconfig",        { Skip_MODRM }, 0 },
10810   },
10811   {
10812     /* RM_0F01_REG_1 */
10813     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10814     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10815     { "clac",           { Skip_MODRM }, 0 },
10816     { "stac",           { Skip_MODRM }, 0 },
10817     { Bad_Opcode },
10818     { Bad_Opcode },
10819     { Bad_Opcode },
10820     { "encls",          { Skip_MODRM }, 0 },
10821   },
10822   {
10823     /* RM_0F01_REG_2 */
10824     { "xgetbv",         { Skip_MODRM }, 0 },
10825     { "xsetbv",         { Skip_MODRM }, 0 },
10826     { Bad_Opcode },
10827     { Bad_Opcode },
10828     { "vmfunc",         { Skip_MODRM }, 0 },
10829     { "xend",           { Skip_MODRM }, 0 },
10830     { "xtest",          { Skip_MODRM }, 0 },
10831     { "enclu",          { Skip_MODRM }, 0 },
10832   },
10833   {
10834     /* RM_0F01_REG_3 */
10835     { "vmrun",          { Skip_MODRM }, 0 },
10836     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10837     { "vmload",         { Skip_MODRM }, 0 },
10838     { "vmsave",         { Skip_MODRM }, 0 },
10839     { "stgi",           { Skip_MODRM }, 0 },
10840     { "clgi",           { Skip_MODRM }, 0 },
10841     { "skinit",         { Skip_MODRM }, 0 },
10842     { "invlpga",        { Skip_MODRM }, 0 },
10843   },
10844   {
10845     /* RM_0F01_REG_5_MOD_3 */
10846     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10847     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10848     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10849     { Bad_Opcode },
10850     { Bad_Opcode },
10851     { Bad_Opcode },
10852     { "rdpkru",         { Skip_MODRM }, 0 },
10853     { "wrpkru",         { Skip_MODRM }, 0 },
10854   },
10855   {
10856     /* RM_0F01_REG_7_MOD_3 */
10857     { "swapgs",         { Skip_MODRM }, 0  },
10858     { "rdtscp",         { Skip_MODRM }, 0  },
10859     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
10860     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
10861     { "clzero",         { Skip_MODRM }, 0  },
10862     { "rdpru",          { Skip_MODRM }, 0  },
10863   },
10864   {
10865     /* RM_0F1E_P_1_MOD_3_REG_7 */
10866     { "nopQ",           { Ev }, 0 },
10867     { "nopQ",           { Ev }, 0 },
10868     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
10869     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
10870     { "nopQ",           { Ev }, 0 },
10871     { "nopQ",           { Ev }, 0 },
10872     { "nopQ",           { Ev }, 0 },
10873     { "nopQ",           { Ev }, 0 },
10874   },
10875   {
10876     /* RM_0FAE_REG_6_MOD_3 */
10877     { "mfence",         { Skip_MODRM }, 0 },
10878   },
10879   {
10880     /* RM_0FAE_REG_7_MOD_3 */
10881     { "sfence",         { Skip_MODRM }, 0 },
10882
10883   },
10884 };
10885
10886 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10887
10888 /* We use the high bit to indicate different name for the same
10889    prefix.  */
10890 #define REP_PREFIX      (0xf3 | 0x100)
10891 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10892 #define XRELEASE_PREFIX (0xf3 | 0x400)
10893 #define BND_PREFIX      (0xf2 | 0x400)
10894 #define NOTRACK_PREFIX  (0x3e | 0x100)
10895
10896 /* Remember if the current op is a jump instruction.  */
10897 static bfd_boolean op_is_jump = FALSE;
10898
10899 static int
10900 ckprefix (void)
10901 {
10902   int newrex, i, length;
10903   rex = 0;
10904   prefixes = 0;
10905   used_prefixes = 0;
10906   rex_used = 0;
10907   last_lock_prefix = -1;
10908   last_repz_prefix = -1;
10909   last_repnz_prefix = -1;
10910   last_data_prefix = -1;
10911   last_addr_prefix = -1;
10912   last_rex_prefix = -1;
10913   last_seg_prefix = -1;
10914   fwait_prefix = -1;
10915   active_seg_prefix = 0;
10916   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10917     all_prefixes[i] = 0;
10918   i = 0;
10919   length = 0;
10920   /* The maximum instruction length is 15bytes.  */
10921   while (length < MAX_CODE_LENGTH - 1)
10922     {
10923       FETCH_DATA (the_info, codep + 1);
10924       newrex = 0;
10925       switch (*codep)
10926         {
10927         /* REX prefixes family.  */
10928         case 0x40:
10929         case 0x41:
10930         case 0x42:
10931         case 0x43:
10932         case 0x44:
10933         case 0x45:
10934         case 0x46:
10935         case 0x47:
10936         case 0x48:
10937         case 0x49:
10938         case 0x4a:
10939         case 0x4b:
10940         case 0x4c:
10941         case 0x4d:
10942         case 0x4e:
10943         case 0x4f:
10944           if (address_mode == mode_64bit)
10945             newrex = *codep;
10946           else
10947             return 1;
10948           last_rex_prefix = i;
10949           break;
10950         case 0xf3:
10951           prefixes |= PREFIX_REPZ;
10952           last_repz_prefix = i;
10953           break;
10954         case 0xf2:
10955           prefixes |= PREFIX_REPNZ;
10956           last_repnz_prefix = i;
10957           break;
10958         case 0xf0:
10959           prefixes |= PREFIX_LOCK;
10960           last_lock_prefix = i;
10961           break;
10962         case 0x2e:
10963           prefixes |= PREFIX_CS;
10964           last_seg_prefix = i;
10965           active_seg_prefix = PREFIX_CS;
10966           break;
10967         case 0x36:
10968           prefixes |= PREFIX_SS;
10969           last_seg_prefix = i;
10970           active_seg_prefix = PREFIX_SS;
10971           break;
10972         case 0x3e:
10973           prefixes |= PREFIX_DS;
10974           last_seg_prefix = i;
10975           active_seg_prefix = PREFIX_DS;
10976           break;
10977         case 0x26:
10978           prefixes |= PREFIX_ES;
10979           last_seg_prefix = i;
10980           active_seg_prefix = PREFIX_ES;
10981           break;
10982         case 0x64:
10983           prefixes |= PREFIX_FS;
10984           last_seg_prefix = i;
10985           active_seg_prefix = PREFIX_FS;
10986           break;
10987         case 0x65:
10988           prefixes |= PREFIX_GS;
10989           last_seg_prefix = i;
10990           active_seg_prefix = PREFIX_GS;
10991           break;
10992         case 0x66:
10993           prefixes |= PREFIX_DATA;
10994           last_data_prefix = i;
10995           break;
10996         case 0x67:
10997           prefixes |= PREFIX_ADDR;
10998           last_addr_prefix = i;
10999           break;
11000         case FWAIT_OPCODE:
11001           /* fwait is really an instruction.  If there are prefixes
11002              before the fwait, they belong to the fwait, *not* to the
11003              following instruction.  */
11004           fwait_prefix = i;
11005           if (prefixes || rex)
11006             {
11007               prefixes |= PREFIX_FWAIT;
11008               codep++;
11009               /* This ensures that the previous REX prefixes are noticed
11010                  as unused prefixes, as in the return case below.  */
11011               rex_used = rex;
11012               return 1;
11013             }
11014           prefixes = PREFIX_FWAIT;
11015           break;
11016         default:
11017           return 1;
11018         }
11019       /* Rex is ignored when followed by another prefix.  */
11020       if (rex)
11021         {
11022           rex_used = rex;
11023           return 1;
11024         }
11025       if (*codep != FWAIT_OPCODE)
11026         all_prefixes[i++] = *codep;
11027       rex = newrex;
11028       codep++;
11029       length++;
11030     }
11031   return 0;
11032 }
11033
11034 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11035    prefix byte.  */
11036
11037 static const char *
11038 prefix_name (int pref, int sizeflag)
11039 {
11040   static const char *rexes [16] =
11041     {
11042       "rex",            /* 0x40 */
11043       "rex.B",          /* 0x41 */
11044       "rex.X",          /* 0x42 */
11045       "rex.XB",         /* 0x43 */
11046       "rex.R",          /* 0x44 */
11047       "rex.RB",         /* 0x45 */
11048       "rex.RX",         /* 0x46 */
11049       "rex.RXB",        /* 0x47 */
11050       "rex.W",          /* 0x48 */
11051       "rex.WB",         /* 0x49 */
11052       "rex.WX",         /* 0x4a */
11053       "rex.WXB",        /* 0x4b */
11054       "rex.WR",         /* 0x4c */
11055       "rex.WRB",        /* 0x4d */
11056       "rex.WRX",        /* 0x4e */
11057       "rex.WRXB",       /* 0x4f */
11058     };
11059
11060   switch (pref)
11061     {
11062     /* REX prefixes family.  */
11063     case 0x40:
11064     case 0x41:
11065     case 0x42:
11066     case 0x43:
11067     case 0x44:
11068     case 0x45:
11069     case 0x46:
11070     case 0x47:
11071     case 0x48:
11072     case 0x49:
11073     case 0x4a:
11074     case 0x4b:
11075     case 0x4c:
11076     case 0x4d:
11077     case 0x4e:
11078     case 0x4f:
11079       return rexes [pref - 0x40];
11080     case 0xf3:
11081       return "repz";
11082     case 0xf2:
11083       return "repnz";
11084     case 0xf0:
11085       return "lock";
11086     case 0x2e:
11087       return "cs";
11088     case 0x36:
11089       return "ss";
11090     case 0x3e:
11091       return "ds";
11092     case 0x26:
11093       return "es";
11094     case 0x64:
11095       return "fs";
11096     case 0x65:
11097       return "gs";
11098     case 0x66:
11099       return (sizeflag & DFLAG) ? "data16" : "data32";
11100     case 0x67:
11101       if (address_mode == mode_64bit)
11102         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11103       else
11104         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11105     case FWAIT_OPCODE:
11106       return "fwait";
11107     case REP_PREFIX:
11108       return "rep";
11109     case XACQUIRE_PREFIX:
11110       return "xacquire";
11111     case XRELEASE_PREFIX:
11112       return "xrelease";
11113     case BND_PREFIX:
11114       return "bnd";
11115     case NOTRACK_PREFIX:
11116       return "notrack";
11117     default:
11118       return NULL;
11119     }
11120 }
11121
11122 static char op_out[MAX_OPERANDS][100];
11123 static int op_ad, op_index[MAX_OPERANDS];
11124 static int two_source_ops;
11125 static bfd_vma op_address[MAX_OPERANDS];
11126 static bfd_vma op_riprel[MAX_OPERANDS];
11127 static bfd_vma start_pc;
11128
11129 /*
11130  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11131  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11132  *   section of the "Virtual 8086 Mode" chapter.)
11133  * 'pc' should be the address of this instruction, it will
11134  *   be used to print the target address if this is a relative jump or call
11135  * The function returns the length of this instruction in bytes.
11136  */
11137
11138 static char intel_syntax;
11139 static char intel_mnemonic = !SYSV386_COMPAT;
11140 static char open_char;
11141 static char close_char;
11142 static char separator_char;
11143 static char scale_char;
11144
11145 enum x86_64_isa
11146 {
11147   amd64 = 1,
11148   intel64
11149 };
11150
11151 static enum x86_64_isa isa64;
11152
11153 /* Here for backwards compatibility.  When gdb stops using
11154    print_insn_i386_att and print_insn_i386_intel these functions can
11155    disappear, and print_insn_i386 be merged into print_insn.  */
11156 int
11157 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11158 {
11159   intel_syntax = 0;
11160
11161   return print_insn (pc, info);
11162 }
11163
11164 int
11165 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11166 {
11167   intel_syntax = 1;
11168
11169   return print_insn (pc, info);
11170 }
11171
11172 int
11173 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11174 {
11175   intel_syntax = -1;
11176
11177   return print_insn (pc, info);
11178 }
11179
11180 void
11181 print_i386_disassembler_options (FILE *stream)
11182 {
11183   fprintf (stream, _("\n\
11184 The following i386/x86-64 specific disassembler options are supported for use\n\
11185 with the -M switch (multiple options should be separated by commas):\n"));
11186
11187   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11188   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11189   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11190   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11191   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11192   fprintf (stream, _("  att-mnemonic\n"
11193                      "              Display instruction in AT&T mnemonic\n"));
11194   fprintf (stream, _("  intel-mnemonic\n"
11195                      "              Display instruction in Intel mnemonic\n"));
11196   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11197   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11198   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11199   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11200   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11201   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11202   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11203   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11204 }
11205
11206 /* Bad opcode.  */
11207 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11208
11209 /* Get a pointer to struct dis386 with a valid name.  */
11210
11211 static const struct dis386 *
11212 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11213 {
11214   int vindex, vex_table_index;
11215
11216   if (dp->name != NULL)
11217     return dp;
11218
11219   switch (dp->op[0].bytemode)
11220     {
11221     case USE_REG_TABLE:
11222       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11223       break;
11224
11225     case USE_MOD_TABLE:
11226       vindex = modrm.mod == 0x3 ? 1 : 0;
11227       dp = &mod_table[dp->op[1].bytemode][vindex];
11228       break;
11229
11230     case USE_RM_TABLE:
11231       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11232       break;
11233
11234     case USE_PREFIX_TABLE:
11235       if (need_vex)
11236         {
11237           /* The prefix in VEX is implicit.  */
11238           switch (vex.prefix)
11239             {
11240             case 0:
11241               vindex = 0;
11242               break;
11243             case REPE_PREFIX_OPCODE:
11244               vindex = 1;
11245               break;
11246             case DATA_PREFIX_OPCODE:
11247               vindex = 2;
11248               break;
11249             case REPNE_PREFIX_OPCODE:
11250               vindex = 3;
11251               break;
11252             default:
11253               abort ();
11254               break;
11255             }
11256         }
11257       else
11258         {
11259           int last_prefix = -1;
11260           int prefix = 0;
11261           vindex = 0;
11262           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11263              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11264              last one wins.  */
11265           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11266             {
11267               if (last_repz_prefix > last_repnz_prefix)
11268                 {
11269                   vindex = 1;
11270                   prefix = PREFIX_REPZ;
11271                   last_prefix = last_repz_prefix;
11272                 }
11273               else
11274                 {
11275                   vindex = 3;
11276                   prefix = PREFIX_REPNZ;
11277                   last_prefix = last_repnz_prefix;
11278                 }
11279
11280               /* Check if prefix should be ignored.  */
11281               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11282                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11283                    & prefix) != 0)
11284                 vindex = 0;
11285             }
11286
11287           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11288             {
11289               vindex = 2;
11290               prefix = PREFIX_DATA;
11291               last_prefix = last_data_prefix;
11292             }
11293
11294           if (vindex != 0)
11295             {
11296               used_prefixes |= prefix;
11297               all_prefixes[last_prefix] = 0;
11298             }
11299         }
11300       dp = &prefix_table[dp->op[1].bytemode][vindex];
11301       break;
11302
11303     case USE_X86_64_TABLE:
11304       vindex = address_mode == mode_64bit ? 1 : 0;
11305       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11306       break;
11307
11308     case USE_3BYTE_TABLE:
11309       FETCH_DATA (info, codep + 2);
11310       vindex = *codep++;
11311       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11312       end_codep = codep;
11313       modrm.mod = (*codep >> 6) & 3;
11314       modrm.reg = (*codep >> 3) & 7;
11315       modrm.rm = *codep & 7;
11316       break;
11317
11318     case USE_VEX_LEN_TABLE:
11319       if (!need_vex)
11320         abort ();
11321
11322       switch (vex.length)
11323         {
11324         case 128:
11325           vindex = 0;
11326           break;
11327         case 256:
11328           vindex = 1;
11329           break;
11330         default:
11331           abort ();
11332           break;
11333         }
11334
11335       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11336       break;
11337
11338     case USE_EVEX_LEN_TABLE:
11339       if (!vex.evex)
11340         abort ();
11341
11342       switch (vex.length)
11343         {
11344         case 128:
11345           vindex = 0;
11346           break;
11347         case 256:
11348           vindex = 1;
11349           break;
11350         case 512:
11351           vindex = 2;
11352           break;
11353         default:
11354           abort ();
11355           break;
11356         }
11357
11358       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11359       break;
11360
11361     case USE_XOP_8F_TABLE:
11362       FETCH_DATA (info, codep + 3);
11363       rex = ~(*codep >> 5) & 0x7;
11364
11365       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11366       switch ((*codep & 0x1f))
11367         {
11368         default:
11369           dp = &bad_opcode;
11370           return dp;
11371         case 0x8:
11372           vex_table_index = XOP_08;
11373           break;
11374         case 0x9:
11375           vex_table_index = XOP_09;
11376           break;
11377         case 0xa:
11378           vex_table_index = XOP_0A;
11379           break;
11380         }
11381       codep++;
11382       vex.w = *codep & 0x80;
11383       if (vex.w && address_mode == mode_64bit)
11384         rex |= REX_W;
11385
11386       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11387       if (address_mode != mode_64bit)
11388         {
11389           /* In 16/32-bit mode REX_B is silently ignored.  */
11390           rex &= ~REX_B;
11391         }
11392
11393       vex.length = (*codep & 0x4) ? 256 : 128;
11394       switch ((*codep & 0x3))
11395         {
11396         case 0:
11397           break;
11398         case 1:
11399           vex.prefix = DATA_PREFIX_OPCODE;
11400           break;
11401         case 2:
11402           vex.prefix = REPE_PREFIX_OPCODE;
11403           break;
11404         case 3:
11405           vex.prefix = REPNE_PREFIX_OPCODE;
11406           break;
11407         }
11408       need_vex = 1;
11409       need_vex_reg = 1;
11410       codep++;
11411       vindex = *codep++;
11412       dp = &xop_table[vex_table_index][vindex];
11413
11414       end_codep = codep;
11415       FETCH_DATA (info, codep + 1);
11416       modrm.mod = (*codep >> 6) & 3;
11417       modrm.reg = (*codep >> 3) & 7;
11418       modrm.rm = *codep & 7;
11419
11420       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
11421          having to decode the bits for every otherwise valid encoding.  */
11422       if (vex.prefix)
11423         return &bad_opcode;
11424       break;
11425
11426     case USE_VEX_C4_TABLE:
11427       /* VEX prefix.  */
11428       FETCH_DATA (info, codep + 3);
11429       rex = ~(*codep >> 5) & 0x7;
11430       switch ((*codep & 0x1f))
11431         {
11432         default:
11433           dp = &bad_opcode;
11434           return dp;
11435         case 0x1:
11436           vex_table_index = VEX_0F;
11437           break;
11438         case 0x2:
11439           vex_table_index = VEX_0F38;
11440           break;
11441         case 0x3:
11442           vex_table_index = VEX_0F3A;
11443           break;
11444         }
11445       codep++;
11446       vex.w = *codep & 0x80;
11447       if (address_mode == mode_64bit)
11448         {
11449           if (vex.w)
11450             rex |= REX_W;
11451         }
11452       else
11453         {
11454           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11455              is ignored, other REX bits are 0 and the highest bit in
11456              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11457           rex = 0;
11458         }
11459       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11460       vex.length = (*codep & 0x4) ? 256 : 128;
11461       switch ((*codep & 0x3))
11462         {
11463         case 0:
11464           break;
11465         case 1:
11466           vex.prefix = DATA_PREFIX_OPCODE;
11467           break;
11468         case 2:
11469           vex.prefix = REPE_PREFIX_OPCODE;
11470           break;
11471         case 3:
11472           vex.prefix = REPNE_PREFIX_OPCODE;
11473           break;
11474         }
11475       need_vex = 1;
11476       need_vex_reg = 1;
11477       codep++;
11478       vindex = *codep++;
11479       dp = &vex_table[vex_table_index][vindex];
11480       end_codep = codep;
11481       /* There is no MODRM byte for VEX0F 77.  */
11482       if (vex_table_index != VEX_0F || vindex != 0x77)
11483         {
11484           FETCH_DATA (info, codep + 1);
11485           modrm.mod = (*codep >> 6) & 3;
11486           modrm.reg = (*codep >> 3) & 7;
11487           modrm.rm = *codep & 7;
11488         }
11489       break;
11490
11491     case USE_VEX_C5_TABLE:
11492       /* VEX prefix.  */
11493       FETCH_DATA (info, codep + 2);
11494       rex = (*codep & 0x80) ? 0 : REX_R;
11495
11496       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11497          VEX.vvvv is 1.  */
11498       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11499       vex.length = (*codep & 0x4) ? 256 : 128;
11500       switch ((*codep & 0x3))
11501         {
11502         case 0:
11503           break;
11504         case 1:
11505           vex.prefix = DATA_PREFIX_OPCODE;
11506           break;
11507         case 2:
11508           vex.prefix = REPE_PREFIX_OPCODE;
11509           break;
11510         case 3:
11511           vex.prefix = REPNE_PREFIX_OPCODE;
11512           break;
11513         }
11514       need_vex = 1;
11515       need_vex_reg = 1;
11516       codep++;
11517       vindex = *codep++;
11518       dp = &vex_table[dp->op[1].bytemode][vindex];
11519       end_codep = codep;
11520       /* There is no MODRM byte for VEX 77.  */
11521       if (vindex != 0x77)
11522         {
11523           FETCH_DATA (info, codep + 1);
11524           modrm.mod = (*codep >> 6) & 3;
11525           modrm.reg = (*codep >> 3) & 7;
11526           modrm.rm = *codep & 7;
11527         }
11528       break;
11529
11530     case USE_VEX_W_TABLE:
11531       if (!need_vex)
11532         abort ();
11533
11534       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11535       break;
11536
11537     case USE_EVEX_TABLE:
11538       two_source_ops = 0;
11539       /* EVEX prefix.  */
11540       vex.evex = 1;
11541       FETCH_DATA (info, codep + 4);
11542       /* The first byte after 0x62.  */
11543       rex = ~(*codep >> 5) & 0x7;
11544       vex.r = *codep & 0x10;
11545       switch ((*codep & 0xf))
11546         {
11547         default:
11548           return &bad_opcode;
11549         case 0x1:
11550           vex_table_index = EVEX_0F;
11551           break;
11552         case 0x2:
11553           vex_table_index = EVEX_0F38;
11554           break;
11555         case 0x3:
11556           vex_table_index = EVEX_0F3A;
11557           break;
11558         }
11559
11560       /* The second byte after 0x62.  */
11561       codep++;
11562       vex.w = *codep & 0x80;
11563       if (vex.w && address_mode == mode_64bit)
11564         rex |= REX_W;
11565
11566       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11567
11568       /* The U bit.  */
11569       if (!(*codep & 0x4))
11570         return &bad_opcode;
11571
11572       switch ((*codep & 0x3))
11573         {
11574         case 0:
11575           break;
11576         case 1:
11577           vex.prefix = DATA_PREFIX_OPCODE;
11578           break;
11579         case 2:
11580           vex.prefix = REPE_PREFIX_OPCODE;
11581           break;
11582         case 3:
11583           vex.prefix = REPNE_PREFIX_OPCODE;
11584           break;
11585         }
11586
11587       /* The third byte after 0x62.  */
11588       codep++;
11589
11590       /* Remember the static rounding bits.  */
11591       vex.ll = (*codep >> 5) & 3;
11592       vex.b = (*codep & 0x10) != 0;
11593
11594       vex.v = *codep & 0x8;
11595       vex.mask_register_specifier = *codep & 0x7;
11596       vex.zeroing = *codep & 0x80;
11597
11598       if (address_mode != mode_64bit)
11599         {
11600           /* In 16/32-bit mode silently ignore following bits.  */
11601           rex &= ~REX_B;
11602           vex.r = 1;
11603           vex.v = 1;
11604         }
11605
11606       need_vex = 1;
11607       need_vex_reg = 1;
11608       codep++;
11609       vindex = *codep++;
11610       dp = &evex_table[vex_table_index][vindex];
11611       end_codep = codep;
11612       FETCH_DATA (info, codep + 1);
11613       modrm.mod = (*codep >> 6) & 3;
11614       modrm.reg = (*codep >> 3) & 7;
11615       modrm.rm = *codep & 7;
11616
11617       /* Set vector length.  */
11618       if (modrm.mod == 3 && vex.b)
11619         vex.length = 512;
11620       else
11621         {
11622           switch (vex.ll)
11623             {
11624             case 0x0:
11625               vex.length = 128;
11626               break;
11627             case 0x1:
11628               vex.length = 256;
11629               break;
11630             case 0x2:
11631               vex.length = 512;
11632               break;
11633             default:
11634               return &bad_opcode;
11635             }
11636         }
11637       break;
11638
11639     case 0:
11640       dp = &bad_opcode;
11641       break;
11642
11643     default:
11644       abort ();
11645     }
11646
11647   if (dp->name != NULL)
11648     return dp;
11649   else
11650     return get_valid_dis386 (dp, info);
11651 }
11652
11653 static void
11654 get_sib (disassemble_info *info, int sizeflag)
11655 {
11656   /* If modrm.mod == 3, operand must be register.  */
11657   if (need_modrm
11658       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11659       && modrm.mod != 3
11660       && modrm.rm == 4)
11661     {
11662       FETCH_DATA (info, codep + 2);
11663       sib.index = (codep [1] >> 3) & 7;
11664       sib.scale = (codep [1] >> 6) & 3;
11665       sib.base = codep [1] & 7;
11666     }
11667 }
11668
11669 static int
11670 print_insn (bfd_vma pc, disassemble_info *info)
11671 {
11672   const struct dis386 *dp;
11673   int i;
11674   char *op_txt[MAX_OPERANDS];
11675   int needcomma;
11676   int sizeflag, orig_sizeflag;
11677   const char *p;
11678   struct dis_private priv;
11679   int prefix_length;
11680
11681   priv.orig_sizeflag = AFLAG | DFLAG;
11682   if ((info->mach & bfd_mach_i386_i386) != 0)
11683     address_mode = mode_32bit;
11684   else if (info->mach == bfd_mach_i386_i8086)
11685     {
11686       address_mode = mode_16bit;
11687       priv.orig_sizeflag = 0;
11688     }
11689   else
11690     address_mode = mode_64bit;
11691
11692   if (intel_syntax == (char) -1)
11693     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11694
11695   for (p = info->disassembler_options; p != NULL; )
11696     {
11697       if (CONST_STRNEQ (p, "amd64"))
11698         isa64 = amd64;
11699       else if (CONST_STRNEQ (p, "intel64"))
11700         isa64 = intel64;
11701       else if (CONST_STRNEQ (p, "x86-64"))
11702         {
11703           address_mode = mode_64bit;
11704           priv.orig_sizeflag |= AFLAG | DFLAG;
11705         }
11706       else if (CONST_STRNEQ (p, "i386"))
11707         {
11708           address_mode = mode_32bit;
11709           priv.orig_sizeflag |= AFLAG | DFLAG;
11710         }
11711       else if (CONST_STRNEQ (p, "i8086"))
11712         {
11713           address_mode = mode_16bit;
11714           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11715         }
11716       else if (CONST_STRNEQ (p, "intel"))
11717         {
11718           intel_syntax = 1;
11719           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11720             intel_mnemonic = 1;
11721         }
11722       else if (CONST_STRNEQ (p, "att"))
11723         {
11724           intel_syntax = 0;
11725           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11726             intel_mnemonic = 0;
11727         }
11728       else if (CONST_STRNEQ (p, "addr"))
11729         {
11730           if (address_mode == mode_64bit)
11731             {
11732               if (p[4] == '3' && p[5] == '2')
11733                 priv.orig_sizeflag &= ~AFLAG;
11734               else if (p[4] == '6' && p[5] == '4')
11735                 priv.orig_sizeflag |= AFLAG;
11736             }
11737           else
11738             {
11739               if (p[4] == '1' && p[5] == '6')
11740                 priv.orig_sizeflag &= ~AFLAG;
11741               else if (p[4] == '3' && p[5] == '2')
11742                 priv.orig_sizeflag |= AFLAG;
11743             }
11744         }
11745       else if (CONST_STRNEQ (p, "data"))
11746         {
11747           if (p[4] == '1' && p[5] == '6')
11748             priv.orig_sizeflag &= ~DFLAG;
11749           else if (p[4] == '3' && p[5] == '2')
11750             priv.orig_sizeflag |= DFLAG;
11751         }
11752       else if (CONST_STRNEQ (p, "suffix"))
11753         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11754
11755       p = strchr (p, ',');
11756       if (p != NULL)
11757         p++;
11758     }
11759
11760   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11761     {
11762       (*info->fprintf_func) (info->stream,
11763                              _("64-bit address is disabled"));
11764       return -1;
11765     }
11766
11767   if (intel_syntax)
11768     {
11769       names64 = intel_names64;
11770       names32 = intel_names32;
11771       names16 = intel_names16;
11772       names8 = intel_names8;
11773       names8rex = intel_names8rex;
11774       names_seg = intel_names_seg;
11775       names_mm = intel_names_mm;
11776       names_bnd = intel_names_bnd;
11777       names_xmm = intel_names_xmm;
11778       names_ymm = intel_names_ymm;
11779       names_zmm = intel_names_zmm;
11780       index64 = intel_index64;
11781       index32 = intel_index32;
11782       names_mask = intel_names_mask;
11783       index16 = intel_index16;
11784       open_char = '[';
11785       close_char = ']';
11786       separator_char = '+';
11787       scale_char = '*';
11788     }
11789   else
11790     {
11791       names64 = att_names64;
11792       names32 = att_names32;
11793       names16 = att_names16;
11794       names8 = att_names8;
11795       names8rex = att_names8rex;
11796       names_seg = att_names_seg;
11797       names_mm = att_names_mm;
11798       names_bnd = att_names_bnd;
11799       names_xmm = att_names_xmm;
11800       names_ymm = att_names_ymm;
11801       names_zmm = att_names_zmm;
11802       index64 = att_index64;
11803       index32 = att_index32;
11804       names_mask = att_names_mask;
11805       index16 = att_index16;
11806       open_char = '(';
11807       close_char =  ')';
11808       separator_char = ',';
11809       scale_char = ',';
11810     }
11811
11812   /* The output looks better if we put 7 bytes on a line, since that
11813      puts most long word instructions on a single line.  Use 8 bytes
11814      for Intel L1OM.  */
11815   if ((info->mach & bfd_mach_l1om) != 0)
11816     info->bytes_per_line = 8;
11817   else
11818     info->bytes_per_line = 7;
11819
11820   info->private_data = &priv;
11821   priv.max_fetched = priv.the_buffer;
11822   priv.insn_start = pc;
11823
11824   obuf[0] = 0;
11825   for (i = 0; i < MAX_OPERANDS; ++i)
11826     {
11827       op_out[i][0] = 0;
11828       op_index[i] = -1;
11829     }
11830
11831   the_info = info;
11832   start_pc = pc;
11833   start_codep = priv.the_buffer;
11834   codep = priv.the_buffer;
11835
11836   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11837     {
11838       const char *name;
11839
11840       /* Getting here means we tried for data but didn't get it.  That
11841          means we have an incomplete instruction of some sort.  Just
11842          print the first byte as a prefix or a .byte pseudo-op.  */
11843       if (codep > priv.the_buffer)
11844         {
11845           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11846           if (name != NULL)
11847             (*info->fprintf_func) (info->stream, "%s", name);
11848           else
11849             {
11850               /* Just print the first byte as a .byte instruction.  */
11851               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11852                                      (unsigned int) priv.the_buffer[0]);
11853             }
11854
11855           return 1;
11856         }
11857
11858       return -1;
11859     }
11860
11861   obufp = obuf;
11862   sizeflag = priv.orig_sizeflag;
11863
11864   if (!ckprefix () || rex_used)
11865     {
11866       /* Too many prefixes or unused REX prefixes.  */
11867       for (i = 0;
11868            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11869            i++)
11870         (*info->fprintf_func) (info->stream, "%s%s",
11871                                i == 0 ? "" : " ",
11872                                prefix_name (all_prefixes[i], sizeflag));
11873       return i;
11874     }
11875
11876   insn_codep = codep;
11877
11878   FETCH_DATA (info, codep + 1);
11879   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11880
11881   if (((prefixes & PREFIX_FWAIT)
11882        && ((*codep < 0xd8) || (*codep > 0xdf))))
11883     {
11884       /* Handle prefixes before fwait.  */
11885       for (i = 0; i < fwait_prefix && all_prefixes[i];
11886            i++)
11887         (*info->fprintf_func) (info->stream, "%s ",
11888                                prefix_name (all_prefixes[i], sizeflag));
11889       (*info->fprintf_func) (info->stream, "fwait");
11890       return i + 1;
11891     }
11892
11893   if (*codep == 0x0f)
11894     {
11895       unsigned char threebyte;
11896
11897       codep++;
11898       FETCH_DATA (info, codep + 1);
11899       threebyte = *codep;
11900       dp = &dis386_twobyte[threebyte];
11901       need_modrm = twobyte_has_modrm[*codep];
11902       codep++;
11903     }
11904   else
11905     {
11906       dp = &dis386[*codep];
11907       need_modrm = onebyte_has_modrm[*codep];
11908       codep++;
11909     }
11910
11911   /* Save sizeflag for printing the extra prefixes later before updating
11912      it for mnemonic and operand processing.  The prefix names depend
11913      only on the address mode.  */
11914   orig_sizeflag = sizeflag;
11915   if (prefixes & PREFIX_ADDR)
11916     sizeflag ^= AFLAG;
11917   if ((prefixes & PREFIX_DATA))
11918     sizeflag ^= DFLAG;
11919
11920   end_codep = codep;
11921   if (need_modrm)
11922     {
11923       FETCH_DATA (info, codep + 1);
11924       modrm.mod = (*codep >> 6) & 3;
11925       modrm.reg = (*codep >> 3) & 7;
11926       modrm.rm = *codep & 7;
11927     }
11928
11929   need_vex = 0;
11930   need_vex_reg = 0;
11931   memset (&vex, 0, sizeof (vex));
11932
11933   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11934     {
11935       get_sib (info, sizeflag);
11936       dofloat (sizeflag);
11937     }
11938   else
11939     {
11940       dp = get_valid_dis386 (dp, info);
11941       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11942         {
11943           get_sib (info, sizeflag);
11944           for (i = 0; i < MAX_OPERANDS; ++i)
11945             {
11946               obufp = op_out[i];
11947               op_ad = MAX_OPERANDS - 1 - i;
11948               if (dp->op[i].rtn)
11949                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11950               /* For EVEX instruction after the last operand masking
11951                  should be printed.  */
11952               if (i == 0 && vex.evex)
11953                 {
11954                   /* Don't print {%k0}.  */
11955                   if (vex.mask_register_specifier)
11956                     {
11957                       oappend ("{");
11958                       oappend (names_mask[vex.mask_register_specifier]);
11959                       oappend ("}");
11960                     }
11961                   if (vex.zeroing)
11962                     oappend ("{z}");
11963                 }
11964             }
11965         }
11966     }
11967
11968   /* Clear instruction information.  */
11969   if (the_info)
11970     {
11971       the_info->insn_info_valid = 0;
11972       the_info->branch_delay_insns = 0;
11973       the_info->data_size = 0;
11974       the_info->insn_type = dis_noninsn;
11975       the_info->target = 0;
11976       the_info->target2 = 0;
11977     }
11978
11979   /* Reset jump operation indicator.  */
11980   op_is_jump = FALSE;
11981
11982   {
11983     int jump_detection = 0;
11984
11985     /* Extract flags.  */
11986     for (i = 0; i < MAX_OPERANDS; ++i)
11987       {
11988         if ((dp->op[i].rtn == OP_J)
11989             || (dp->op[i].rtn == OP_indirE))
11990           jump_detection |= 1;
11991         else if ((dp->op[i].rtn == BND_Fixup)
11992                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
11993           jump_detection |= 2;
11994         else if ((dp->op[i].bytemode == cond_jump_mode)
11995                  || (dp->op[i].bytemode == loop_jcxz_mode))
11996           jump_detection |= 4;
11997       }
11998
11999     /* Determine if this is a jump or branch.  */
12000     if ((jump_detection & 0x3) == 0x3)
12001       {
12002         op_is_jump = TRUE;
12003         if (jump_detection & 0x4)
12004           the_info->insn_type = dis_condbranch;
12005         else
12006           the_info->insn_type =
12007             (dp->name && !strncmp(dp->name, "call", 4))
12008             ? dis_jsr : dis_branch;
12009       }
12010   }
12011
12012   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12013      are all 0s in inverted form.  */
12014   if (need_vex && vex.register_specifier != 0)
12015     {
12016       (*info->fprintf_func) (info->stream, "(bad)");
12017       return end_codep - priv.the_buffer;
12018     }
12019
12020   /* Check if the REX prefix is used.  */
12021   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12022     all_prefixes[last_rex_prefix] = 0;
12023
12024   /* Check if the SEG prefix is used.  */
12025   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12026                    | PREFIX_FS | PREFIX_GS)) != 0
12027       && (used_prefixes & active_seg_prefix) != 0)
12028     all_prefixes[last_seg_prefix] = 0;
12029
12030   /* Check if the ADDR prefix is used.  */
12031   if ((prefixes & PREFIX_ADDR) != 0
12032       && (used_prefixes & PREFIX_ADDR) != 0)
12033     all_prefixes[last_addr_prefix] = 0;
12034
12035   /* Check if the DATA prefix is used.  */
12036   if ((prefixes & PREFIX_DATA) != 0
12037       && (used_prefixes & PREFIX_DATA) != 0
12038       && !need_vex)
12039     all_prefixes[last_data_prefix] = 0;
12040
12041   /* Print the extra prefixes.  */
12042   prefix_length = 0;
12043   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12044     if (all_prefixes[i])
12045       {
12046         const char *name;
12047         name = prefix_name (all_prefixes[i], orig_sizeflag);
12048         if (name == NULL)
12049           abort ();
12050         prefix_length += strlen (name) + 1;
12051         (*info->fprintf_func) (info->stream, "%s ", name);
12052       }
12053
12054   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12055      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12056      used by putop and MMX/SSE operand and may be overriden by the
12057      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12058      separately.  */
12059   if (dp->prefix_requirement == PREFIX_OPCODE
12060       && (((need_vex
12061             ? vex.prefix == REPE_PREFIX_OPCODE
12062               || vex.prefix == REPNE_PREFIX_OPCODE
12063             : (prefixes
12064                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12065            && (used_prefixes
12066                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12067           || (((need_vex
12068                 ? vex.prefix == DATA_PREFIX_OPCODE
12069                 : ((prefixes
12070                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12071                    == PREFIX_DATA))
12072                && (used_prefixes & PREFIX_DATA) == 0))
12073           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12074     {
12075       (*info->fprintf_func) (info->stream, "(bad)");
12076       return end_codep - priv.the_buffer;
12077     }
12078
12079   /* Check maximum code length.  */
12080   if ((codep - start_codep) > MAX_CODE_LENGTH)
12081     {
12082       (*info->fprintf_func) (info->stream, "(bad)");
12083       return MAX_CODE_LENGTH;
12084     }
12085
12086   obufp = mnemonicendp;
12087   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12088     oappend (" ");
12089   oappend (" ");
12090   (*info->fprintf_func) (info->stream, "%s", obuf);
12091
12092   /* The enter and bound instructions are printed with operands in the same
12093      order as the intel book; everything else is printed in reverse order.  */
12094   if (intel_syntax || two_source_ops)
12095     {
12096       bfd_vma riprel;
12097
12098       for (i = 0; i < MAX_OPERANDS; ++i)
12099         op_txt[i] = op_out[i];
12100
12101       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12102           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12103         {
12104           op_txt[2] = op_out[3];
12105           op_txt[3] = op_out[2];
12106         }
12107
12108       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12109         {
12110           op_ad = op_index[i];
12111           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12112           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12113           riprel = op_riprel[i];
12114           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12115           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12116         }
12117     }
12118   else
12119     {
12120       for (i = 0; i < MAX_OPERANDS; ++i)
12121         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12122     }
12123
12124   needcomma = 0;
12125   for (i = 0; i < MAX_OPERANDS; ++i)
12126     if (*op_txt[i])
12127       {
12128         if (needcomma)
12129           (*info->fprintf_func) (info->stream, ",");
12130         if (op_index[i] != -1 && !op_riprel[i])
12131           {
12132             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12133
12134             if (the_info && op_is_jump)
12135               {
12136                 the_info->insn_info_valid = 1;
12137                 the_info->branch_delay_insns = 0;
12138                 the_info->data_size = 0;
12139                 the_info->target = target;
12140                 the_info->target2 = 0;
12141               }
12142             (*info->print_address_func) (target, info);
12143           }
12144         else
12145           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12146         needcomma = 1;
12147       }
12148
12149   for (i = 0; i < MAX_OPERANDS; i++)
12150     if (op_index[i] != -1 && op_riprel[i])
12151       {
12152         (*info->fprintf_func) (info->stream, "        # ");
12153         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12154                                                 + op_address[op_index[i]]), info);
12155         break;
12156       }
12157   return codep - priv.the_buffer;
12158 }
12159
12160 static const char *float_mem[] = {
12161   /* d8 */
12162   "fadd{s|}",
12163   "fmul{s|}",
12164   "fcom{s|}",
12165   "fcomp{s|}",
12166   "fsub{s|}",
12167   "fsubr{s|}",
12168   "fdiv{s|}",
12169   "fdivr{s|}",
12170   /* d9 */
12171   "fld{s|}",
12172   "(bad)",
12173   "fst{s|}",
12174   "fstp{s|}",
12175   "fldenv{C|C}",
12176   "fldcw",
12177   "fNstenv{C|C}",
12178   "fNstcw",
12179   /* da */
12180   "fiadd{l|}",
12181   "fimul{l|}",
12182   "ficom{l|}",
12183   "ficomp{l|}",
12184   "fisub{l|}",
12185   "fisubr{l|}",
12186   "fidiv{l|}",
12187   "fidivr{l|}",
12188   /* db */
12189   "fild{l|}",
12190   "fisttp{l|}",
12191   "fist{l|}",
12192   "fistp{l|}",
12193   "(bad)",
12194   "fld{t|}",
12195   "(bad)",
12196   "fstp{t|}",
12197   /* dc */
12198   "fadd{l|}",
12199   "fmul{l|}",
12200   "fcom{l|}",
12201   "fcomp{l|}",
12202   "fsub{l|}",
12203   "fsubr{l|}",
12204   "fdiv{l|}",
12205   "fdivr{l|}",
12206   /* dd */
12207   "fld{l|}",
12208   "fisttp{ll|}",
12209   "fst{l||}",
12210   "fstp{l|}",
12211   "frstor{C|C}",
12212   "(bad)",
12213   "fNsave{C|C}",
12214   "fNstsw",
12215   /* de */
12216   "fiadd{s|}",
12217   "fimul{s|}",
12218   "ficom{s|}",
12219   "ficomp{s|}",
12220   "fisub{s|}",
12221   "fisubr{s|}",
12222   "fidiv{s|}",
12223   "fidivr{s|}",
12224   /* df */
12225   "fild{s|}",
12226   "fisttp{s|}",
12227   "fist{s|}",
12228   "fistp{s|}",
12229   "fbld",
12230   "fild{ll|}",
12231   "fbstp",
12232   "fistp{ll|}",
12233 };
12234
12235 static const unsigned char float_mem_mode[] = {
12236   /* d8 */
12237   d_mode,
12238   d_mode,
12239   d_mode,
12240   d_mode,
12241   d_mode,
12242   d_mode,
12243   d_mode,
12244   d_mode,
12245   /* d9 */
12246   d_mode,
12247   0,
12248   d_mode,
12249   d_mode,
12250   0,
12251   w_mode,
12252   0,
12253   w_mode,
12254   /* da */
12255   d_mode,
12256   d_mode,
12257   d_mode,
12258   d_mode,
12259   d_mode,
12260   d_mode,
12261   d_mode,
12262   d_mode,
12263   /* db */
12264   d_mode,
12265   d_mode,
12266   d_mode,
12267   d_mode,
12268   0,
12269   t_mode,
12270   0,
12271   t_mode,
12272   /* dc */
12273   q_mode,
12274   q_mode,
12275   q_mode,
12276   q_mode,
12277   q_mode,
12278   q_mode,
12279   q_mode,
12280   q_mode,
12281   /* dd */
12282   q_mode,
12283   q_mode,
12284   q_mode,
12285   q_mode,
12286   0,
12287   0,
12288   0,
12289   w_mode,
12290   /* de */
12291   w_mode,
12292   w_mode,
12293   w_mode,
12294   w_mode,
12295   w_mode,
12296   w_mode,
12297   w_mode,
12298   w_mode,
12299   /* df */
12300   w_mode,
12301   w_mode,
12302   w_mode,
12303   w_mode,
12304   t_mode,
12305   q_mode,
12306   t_mode,
12307   q_mode
12308 };
12309
12310 #define ST { OP_ST, 0 }
12311 #define STi { OP_STi, 0 }
12312
12313 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12314 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12315 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12316 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12317 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12318 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12319 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12320 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12321 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12322
12323 static const struct dis386 float_reg[][8] = {
12324   /* d8 */
12325   {
12326     { "fadd",   { ST, STi }, 0 },
12327     { "fmul",   { ST, STi }, 0 },
12328     { "fcom",   { STi }, 0 },
12329     { "fcomp",  { STi }, 0 },
12330     { "fsub",   { ST, STi }, 0 },
12331     { "fsubr",  { ST, STi }, 0 },
12332     { "fdiv",   { ST, STi }, 0 },
12333     { "fdivr",  { ST, STi }, 0 },
12334   },
12335   /* d9 */
12336   {
12337     { "fld",    { STi }, 0 },
12338     { "fxch",   { STi }, 0 },
12339     { FGRPd9_2 },
12340     { Bad_Opcode },
12341     { FGRPd9_4 },
12342     { FGRPd9_5 },
12343     { FGRPd9_6 },
12344     { FGRPd9_7 },
12345   },
12346   /* da */
12347   {
12348     { "fcmovb", { ST, STi }, 0 },
12349     { "fcmove", { ST, STi }, 0 },
12350     { "fcmovbe",{ ST, STi }, 0 },
12351     { "fcmovu", { ST, STi }, 0 },
12352     { Bad_Opcode },
12353     { FGRPda_5 },
12354     { Bad_Opcode },
12355     { Bad_Opcode },
12356   },
12357   /* db */
12358   {
12359     { "fcmovnb",{ ST, STi }, 0 },
12360     { "fcmovne",{ ST, STi }, 0 },
12361     { "fcmovnbe",{ ST, STi }, 0 },
12362     { "fcmovnu",{ ST, STi }, 0 },
12363     { FGRPdb_4 },
12364     { "fucomi", { ST, STi }, 0 },
12365     { "fcomi",  { ST, STi }, 0 },
12366     { Bad_Opcode },
12367   },
12368   /* dc */
12369   {
12370     { "fadd",   { STi, ST }, 0 },
12371     { "fmul",   { STi, ST }, 0 },
12372     { Bad_Opcode },
12373     { Bad_Opcode },
12374     { "fsub{!M|r}",     { STi, ST }, 0 },
12375     { "fsub{M|}",       { STi, ST }, 0 },
12376     { "fdiv{!M|r}",     { STi, ST }, 0 },
12377     { "fdiv{M|}",       { STi, ST }, 0 },
12378   },
12379   /* dd */
12380   {
12381     { "ffree",  { STi }, 0 },
12382     { Bad_Opcode },
12383     { "fst",    { STi }, 0 },
12384     { "fstp",   { STi }, 0 },
12385     { "fucom",  { STi }, 0 },
12386     { "fucomp", { STi }, 0 },
12387     { Bad_Opcode },
12388     { Bad_Opcode },
12389   },
12390   /* de */
12391   {
12392     { "faddp",  { STi, ST }, 0 },
12393     { "fmulp",  { STi, ST }, 0 },
12394     { Bad_Opcode },
12395     { FGRPde_3 },
12396     { "fsub{!M|r}p",    { STi, ST }, 0 },
12397     { "fsub{M|}p",      { STi, ST }, 0 },
12398     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12399     { "fdiv{M|}p",      { STi, ST }, 0 },
12400   },
12401   /* df */
12402   {
12403     { "ffreep", { STi }, 0 },
12404     { Bad_Opcode },
12405     { Bad_Opcode },
12406     { Bad_Opcode },
12407     { FGRPdf_4 },
12408     { "fucomip", { ST, STi }, 0 },
12409     { "fcomip", { ST, STi }, 0 },
12410     { Bad_Opcode },
12411   },
12412 };
12413
12414 static char *fgrps[][8] = {
12415   /* Bad opcode 0 */
12416   {
12417     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12418   },
12419
12420   /* d9_2  1 */
12421   {
12422     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12423   },
12424
12425   /* d9_4  2 */
12426   {
12427     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12428   },
12429
12430   /* d9_5  3 */
12431   {
12432     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12433   },
12434
12435   /* d9_6  4 */
12436   {
12437     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12438   },
12439
12440   /* d9_7  5 */
12441   {
12442     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12443   },
12444
12445   /* da_5  6 */
12446   {
12447     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12448   },
12449
12450   /* db_4  7 */
12451   {
12452     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12453     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12454   },
12455
12456   /* de_3  8 */
12457   {
12458     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12459   },
12460
12461   /* df_4  9 */
12462   {
12463     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12464   },
12465 };
12466
12467 static void
12468 swap_operand (void)
12469 {
12470   mnemonicendp[0] = '.';
12471   mnemonicendp[1] = 's';
12472   mnemonicendp += 2;
12473 }
12474
12475 static void
12476 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12477                int sizeflag ATTRIBUTE_UNUSED)
12478 {
12479   /* Skip mod/rm byte.  */
12480   MODRM_CHECK;
12481   codep++;
12482 }
12483
12484 static void
12485 dofloat (int sizeflag)
12486 {
12487   const struct dis386 *dp;
12488   unsigned char floatop;
12489
12490   floatop = codep[-1];
12491
12492   if (modrm.mod != 3)
12493     {
12494       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12495
12496       putop (float_mem[fp_indx], sizeflag);
12497       obufp = op_out[0];
12498       op_ad = 2;
12499       OP_E (float_mem_mode[fp_indx], sizeflag);
12500       return;
12501     }
12502   /* Skip mod/rm byte.  */
12503   MODRM_CHECK;
12504   codep++;
12505
12506   dp = &float_reg[floatop - 0xd8][modrm.reg];
12507   if (dp->name == NULL)
12508     {
12509       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12510
12511       /* Instruction fnstsw is only one with strange arg.  */
12512       if (floatop == 0xdf && codep[-1] == 0xe0)
12513         strcpy (op_out[0], names16[0]);
12514     }
12515   else
12516     {
12517       putop (dp->name, sizeflag);
12518
12519       obufp = op_out[0];
12520       op_ad = 2;
12521       if (dp->op[0].rtn)
12522         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12523
12524       obufp = op_out[1];
12525       op_ad = 1;
12526       if (dp->op[1].rtn)
12527         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12528     }
12529 }
12530
12531 /* Like oappend (below), but S is a string starting with '%'.
12532    In Intel syntax, the '%' is elided.  */
12533 static void
12534 oappend_maybe_intel (const char *s)
12535 {
12536   oappend (s + intel_syntax);
12537 }
12538
12539 static void
12540 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12541 {
12542   oappend_maybe_intel ("%st");
12543 }
12544
12545 static void
12546 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12547 {
12548   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12549   oappend_maybe_intel (scratchbuf);
12550 }
12551
12552 /* Capital letters in template are macros.  */
12553 static int
12554 putop (const char *in_template, int sizeflag)
12555 {
12556   const char *p;
12557   int alt = 0;
12558   int cond = 1;
12559   unsigned int l = 0, len = 0;
12560   char last[4];
12561
12562   for (p = in_template; *p; p++)
12563     {
12564       if (len > l)
12565         {
12566           if (l >= sizeof (last) || !ISUPPER (*p))
12567             abort ();
12568           last[l++] = *p;
12569           continue;
12570         }
12571       switch (*p)
12572         {
12573         default:
12574           *obufp++ = *p;
12575           break;
12576         case '%':
12577           len++;
12578           break;
12579         case '!':
12580           cond = 0;
12581           break;
12582         case '{':
12583           if (intel_syntax)
12584             {
12585               while (*++p != '|')
12586                 if (*p == '}' || *p == '\0')
12587                   abort ();
12588               alt = 1;
12589             }
12590           break;
12591         case '|':
12592           while (*++p != '}')
12593             {
12594               if (*p == '\0')
12595                 abort ();
12596             }
12597           break;
12598         case '}':
12599           alt = 0;
12600           break;
12601         case 'A':
12602           if (intel_syntax)
12603             break;
12604           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12605             *obufp++ = 'b';
12606           break;
12607         case 'B':
12608           if (l == 0)
12609             {
12610             case_B:
12611               if (intel_syntax)
12612                 break;
12613               if (sizeflag & SUFFIX_ALWAYS)
12614                 *obufp++ = 'b';
12615             }
12616           else if (l == 1 && last[0] == 'L')
12617             {
12618               if (address_mode == mode_64bit
12619                   && !(prefixes & PREFIX_ADDR))
12620                 {
12621                   *obufp++ = 'a';
12622                   *obufp++ = 'b';
12623                   *obufp++ = 's';
12624                 }
12625
12626               goto case_B;
12627             }
12628           else
12629             abort ();
12630           break;
12631         case 'C':
12632           if (intel_syntax && !alt)
12633             break;
12634           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12635             {
12636               if (sizeflag & DFLAG)
12637                 *obufp++ = intel_syntax ? 'd' : 'l';
12638               else
12639                 *obufp++ = intel_syntax ? 'w' : 's';
12640               used_prefixes |= (prefixes & PREFIX_DATA);
12641             }
12642           break;
12643         case 'D':
12644           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12645             break;
12646           USED_REX (REX_W);
12647           if (modrm.mod == 3)
12648             {
12649               if (rex & REX_W)
12650                 *obufp++ = 'q';
12651               else
12652                 {
12653                   if (sizeflag & DFLAG)
12654                     *obufp++ = intel_syntax ? 'd' : 'l';
12655                   else
12656                     *obufp++ = 'w';
12657                   used_prefixes |= (prefixes & PREFIX_DATA);
12658                 }
12659             }
12660           else
12661             *obufp++ = 'w';
12662           break;
12663         case 'E':               /* For jcxz/jecxz */
12664           if (address_mode == mode_64bit)
12665             {
12666               if (sizeflag & AFLAG)
12667                 *obufp++ = 'r';
12668               else
12669                 *obufp++ = 'e';
12670             }
12671           else
12672             if (sizeflag & AFLAG)
12673               *obufp++ = 'e';
12674           used_prefixes |= (prefixes & PREFIX_ADDR);
12675           break;
12676         case 'F':
12677           if (intel_syntax)
12678             break;
12679           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12680             {
12681               if (sizeflag & AFLAG)
12682                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12683               else
12684                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12685               used_prefixes |= (prefixes & PREFIX_ADDR);
12686             }
12687           break;
12688         case 'G':
12689           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12690             break;
12691           if ((rex & REX_W) || (sizeflag & DFLAG))
12692             *obufp++ = 'l';
12693           else
12694             *obufp++ = 'w';
12695           if (!(rex & REX_W))
12696             used_prefixes |= (prefixes & PREFIX_DATA);
12697           break;
12698         case 'H':
12699           if (intel_syntax)
12700             break;
12701           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12702               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12703             {
12704               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12705               *obufp++ = ',';
12706               *obufp++ = 'p';
12707               if (prefixes & PREFIX_DS)
12708                 *obufp++ = 't';
12709               else
12710                 *obufp++ = 'n';
12711             }
12712           break;
12713         case 'K':
12714           USED_REX (REX_W);
12715           if (rex & REX_W)
12716             *obufp++ = 'q';
12717           else
12718             *obufp++ = 'd';
12719           break;
12720         case 'Z':
12721           if (l != 0)
12722             {
12723               if (l != 1 || last[0] != 'X')
12724                 abort ();
12725               if (!need_vex || !vex.evex)
12726                 abort ();
12727               if (intel_syntax
12728                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12729                 break;
12730               switch (vex.length)
12731                 {
12732                 case 128:
12733                   *obufp++ = 'x';
12734                   break;
12735                 case 256:
12736                   *obufp++ = 'y';
12737                   break;
12738                 case 512:
12739                   *obufp++ = 'z';
12740                   break;
12741                 default:
12742                   abort ();
12743                 }
12744               break;
12745             }
12746           if (intel_syntax)
12747             break;
12748           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12749             {
12750               *obufp++ = 'q';
12751               break;
12752             }
12753           /* Fall through.  */
12754           goto case_L;
12755         case 'L':
12756           if (l != 0)
12757             abort ();
12758         case_L:
12759           if (intel_syntax)
12760             break;
12761           if (sizeflag & SUFFIX_ALWAYS)
12762             *obufp++ = 'l';
12763           break;
12764         case 'M':
12765           if (intel_mnemonic != cond)
12766             *obufp++ = 'r';
12767           break;
12768         case 'N':
12769           if ((prefixes & PREFIX_FWAIT) == 0)
12770             *obufp++ = 'n';
12771           else
12772             used_prefixes |= PREFIX_FWAIT;
12773           break;
12774         case 'O':
12775           USED_REX (REX_W);
12776           if (rex & REX_W)
12777             *obufp++ = 'o';
12778           else if (intel_syntax && (sizeflag & DFLAG))
12779             *obufp++ = 'q';
12780           else
12781             *obufp++ = 'd';
12782           if (!(rex & REX_W))
12783             used_prefixes |= (prefixes & PREFIX_DATA);
12784           break;
12785         case '&':
12786           if (!intel_syntax
12787               && address_mode == mode_64bit
12788               && isa64 == intel64)
12789             {
12790               *obufp++ = 'q';
12791               break;
12792             }
12793           /* Fall through.  */
12794         case 'T':
12795           if (!intel_syntax
12796               && address_mode == mode_64bit
12797               && ((sizeflag & DFLAG) || (rex & REX_W)))
12798             {
12799               *obufp++ = 'q';
12800               break;
12801             }
12802           /* Fall through.  */
12803           goto case_P;
12804         case 'P':
12805           if (l == 0)
12806             {
12807             case_P:
12808               if (intel_syntax)
12809                 {
12810                   if ((rex & REX_W) == 0
12811                       && (prefixes & PREFIX_DATA))
12812                     {
12813                       if ((sizeflag & DFLAG) == 0)
12814                         *obufp++ = 'w';
12815                       used_prefixes |= (prefixes & PREFIX_DATA);
12816                     }
12817                   break;
12818                 }
12819               if ((prefixes & PREFIX_DATA)
12820                   || (rex & REX_W)
12821                   || (sizeflag & SUFFIX_ALWAYS))
12822                 {
12823                   USED_REX (REX_W);
12824                   if (rex & REX_W)
12825                     *obufp++ = 'q';
12826                   else
12827                     {
12828                       if (sizeflag & DFLAG)
12829                         *obufp++ = 'l';
12830                       else
12831                         *obufp++ = 'w';
12832                       used_prefixes |= (prefixes & PREFIX_DATA);
12833                     }
12834                 }
12835             }
12836           else if (l == 1 && last[0] == 'L')
12837             {
12838               if ((prefixes & PREFIX_DATA)
12839                   || (rex & REX_W)
12840                   || (sizeflag & SUFFIX_ALWAYS))
12841                 {
12842                   USED_REX (REX_W);
12843                   if (rex & REX_W)
12844                     *obufp++ = 'q';
12845                   else
12846                     {
12847                       if (sizeflag & DFLAG)
12848                         *obufp++ = intel_syntax ? 'd' : 'l';
12849                       else
12850                         *obufp++ = 'w';
12851                       used_prefixes |= (prefixes & PREFIX_DATA);
12852                     }
12853                 }
12854             }
12855           else
12856             abort ();
12857           break;
12858         case 'U':
12859           if (intel_syntax)
12860             break;
12861           if (address_mode == mode_64bit
12862               && ((sizeflag & DFLAG) || (rex & REX_W)))
12863             {
12864               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12865                 *obufp++ = 'q';
12866               break;
12867             }
12868           /* Fall through.  */
12869           goto case_Q;
12870         case 'Q':
12871           if (l == 0)
12872             {
12873             case_Q:
12874               if (intel_syntax && !alt)
12875                 break;
12876               USED_REX (REX_W);
12877               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12878                 {
12879                   if (rex & REX_W)
12880                     *obufp++ = 'q';
12881                   else
12882                     {
12883                       if (sizeflag & DFLAG)
12884                         *obufp++ = intel_syntax ? 'd' : 'l';
12885                       else
12886                         *obufp++ = 'w';
12887                       used_prefixes |= (prefixes & PREFIX_DATA);
12888                     }
12889                 }
12890             }
12891           else if (l == 1 && last[0] == 'L')
12892             {
12893               if ((intel_syntax && need_modrm)
12894                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12895                 break;
12896               if ((rex & REX_W))
12897                 {
12898                   USED_REX (REX_W);
12899                   *obufp++ = 'q';
12900                 }
12901               else if((address_mode == mode_64bit && need_modrm)
12902                       || (sizeflag & SUFFIX_ALWAYS))
12903                 *obufp++ = intel_syntax? 'd' : 'l';
12904             }
12905           else
12906             abort ();
12907           break;
12908         case 'R':
12909           USED_REX (REX_W);
12910           if (rex & REX_W)
12911             *obufp++ = 'q';
12912           else if (sizeflag & DFLAG)
12913             {
12914               if (intel_syntax)
12915                   *obufp++ = 'd';
12916               else
12917                   *obufp++ = 'l';
12918             }
12919           else
12920             *obufp++ = 'w';
12921           if (intel_syntax && !p[1]
12922               && ((rex & REX_W) || (sizeflag & DFLAG)))
12923             *obufp++ = 'e';
12924           if (!(rex & REX_W))
12925             used_prefixes |= (prefixes & PREFIX_DATA);
12926           break;
12927         case 'V':
12928           if (l == 0)
12929             {
12930               if (intel_syntax)
12931                 break;
12932               if (address_mode == mode_64bit
12933                   && ((sizeflag & DFLAG) || (rex & REX_W)))
12934                 {
12935                   if (sizeflag & SUFFIX_ALWAYS)
12936                     *obufp++ = 'q';
12937                   break;
12938                 }
12939             }
12940           else if (l == 1 && last[0] == 'L')
12941             {
12942               if (rex & REX_W)
12943                 {
12944                   *obufp++ = 'a';
12945                   *obufp++ = 'b';
12946                   *obufp++ = 's';
12947                 }
12948             }
12949           else
12950             abort ();
12951           /* Fall through.  */
12952           goto case_S;
12953         case 'S':
12954           if (l == 0)
12955             {
12956             case_S:
12957               if (intel_syntax)
12958                 break;
12959               if (sizeflag & SUFFIX_ALWAYS)
12960                 {
12961                   if (rex & REX_W)
12962                     *obufp++ = 'q';
12963                   else
12964                     {
12965                       if (sizeflag & DFLAG)
12966                         *obufp++ = 'l';
12967                       else
12968                         *obufp++ = 'w';
12969                       used_prefixes |= (prefixes & PREFIX_DATA);
12970                     }
12971                 }
12972             }
12973           else if (l == 1 && last[0] == 'L')
12974             {
12975               if (address_mode == mode_64bit
12976                   && !(prefixes & PREFIX_ADDR))
12977                 {
12978                   *obufp++ = 'a';
12979                   *obufp++ = 'b';
12980                   *obufp++ = 's';
12981                 }
12982
12983               goto case_S;
12984             }
12985           else
12986             abort ();
12987           break;
12988         case 'X':
12989           if (l != 0)
12990             abort ();
12991           if (need_vex
12992               ? vex.prefix == DATA_PREFIX_OPCODE
12993               : prefixes & PREFIX_DATA)
12994             {
12995               *obufp++ = 'd';
12996               used_prefixes |= PREFIX_DATA;
12997             }
12998           else
12999             *obufp++ = 's';
13000           break;
13001         case 'Y':
13002           if (l == 1 && last[0] == 'X')
13003             {
13004               if (!need_vex)
13005                 abort ();
13006               if (intel_syntax
13007                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13008                 break;
13009               switch (vex.length)
13010                 {
13011                 case 128:
13012                   *obufp++ = 'x';
13013                   break;
13014                 case 256:
13015                   *obufp++ = 'y';
13016                   break;
13017                 case 512:
13018                   if (!vex.evex)
13019                 default:
13020                     abort ();
13021                 }
13022             }
13023           else
13024             abort ();
13025           break;
13026         case 'W':
13027           if (l == 0)
13028             {
13029               /* operand size flag for cwtl, cbtw */
13030               USED_REX (REX_W);
13031               if (rex & REX_W)
13032                 {
13033                   if (intel_syntax)
13034                     *obufp++ = 'd';
13035                   else
13036                     *obufp++ = 'l';
13037                 }
13038               else if (sizeflag & DFLAG)
13039                 *obufp++ = 'w';
13040               else
13041                 *obufp++ = 'b';
13042               if (!(rex & REX_W))
13043                 used_prefixes |= (prefixes & PREFIX_DATA);
13044             }
13045           else if (l == 1)
13046             {
13047               if (!need_vex)
13048                 abort ();
13049               if (last[0] == 'X')
13050                 *obufp++ = vex.w ? 'd': 's';
13051               else if (last[0] == 'L')
13052                 *obufp++ = vex.w ? 'q': 'd';
13053               else if (last[0] == 'B')
13054                 *obufp++ = vex.w ? 'w': 'b';
13055               else
13056                 abort ();
13057             }
13058           else
13059             abort ();
13060           break;
13061         case '^':
13062           if (intel_syntax)
13063             break;
13064           if (isa64 == intel64 && (rex & REX_W))
13065             {
13066               USED_REX (REX_W);
13067               *obufp++ = 'q';
13068               break;
13069             }
13070           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13071             {
13072               if (sizeflag & DFLAG)
13073                 *obufp++ = 'l';
13074               else
13075                 *obufp++ = 'w';
13076               used_prefixes |= (prefixes & PREFIX_DATA);
13077             }
13078           break;
13079         case '@':
13080           if (intel_syntax)
13081             break;
13082           if (address_mode == mode_64bit
13083               && (isa64 == intel64
13084                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13085               *obufp++ = 'q';
13086           else if ((prefixes & PREFIX_DATA))
13087             {
13088               if (!(sizeflag & DFLAG))
13089                 *obufp++ = 'w';
13090               used_prefixes |= (prefixes & PREFIX_DATA);
13091             }
13092           break;
13093         }
13094
13095       if (len == l)
13096         len = l = 0;
13097     }
13098   *obufp = 0;
13099   mnemonicendp = obufp;
13100   return 0;
13101 }
13102
13103 static void
13104 oappend (const char *s)
13105 {
13106   obufp = stpcpy (obufp, s);
13107 }
13108
13109 static void
13110 append_seg (void)
13111 {
13112   /* Only print the active segment register.  */
13113   if (!active_seg_prefix)
13114     return;
13115
13116   used_prefixes |= active_seg_prefix;
13117   switch (active_seg_prefix)
13118     {
13119     case PREFIX_CS:
13120       oappend_maybe_intel ("%cs:");
13121       break;
13122     case PREFIX_DS:
13123       oappend_maybe_intel ("%ds:");
13124       break;
13125     case PREFIX_SS:
13126       oappend_maybe_intel ("%ss:");
13127       break;
13128     case PREFIX_ES:
13129       oappend_maybe_intel ("%es:");
13130       break;
13131     case PREFIX_FS:
13132       oappend_maybe_intel ("%fs:");
13133       break;
13134     case PREFIX_GS:
13135       oappend_maybe_intel ("%gs:");
13136       break;
13137     default:
13138       break;
13139     }
13140 }
13141
13142 static void
13143 OP_indirE (int bytemode, int sizeflag)
13144 {
13145   if (!intel_syntax)
13146     oappend ("*");
13147   OP_E (bytemode, sizeflag);
13148 }
13149
13150 static void
13151 print_operand_value (char *buf, int hex, bfd_vma disp)
13152 {
13153   if (address_mode == mode_64bit)
13154     {
13155       if (hex)
13156         {
13157           char tmp[30];
13158           int i;
13159           buf[0] = '0';
13160           buf[1] = 'x';
13161           sprintf_vma (tmp, disp);
13162           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13163           strcpy (buf + 2, tmp + i);
13164         }
13165       else
13166         {
13167           bfd_signed_vma v = disp;
13168           char tmp[30];
13169           int i;
13170           if (v < 0)
13171             {
13172               *(buf++) = '-';
13173               v = -disp;
13174               /* Check for possible overflow on 0x8000000000000000.  */
13175               if (v < 0)
13176                 {
13177                   strcpy (buf, "9223372036854775808");
13178                   return;
13179                 }
13180             }
13181           if (!v)
13182             {
13183               strcpy (buf, "0");
13184               return;
13185             }
13186
13187           i = 0;
13188           tmp[29] = 0;
13189           while (v)
13190             {
13191               tmp[28 - i] = (v % 10) + '0';
13192               v /= 10;
13193               i++;
13194             }
13195           strcpy (buf, tmp + 29 - i);
13196         }
13197     }
13198   else
13199     {
13200       if (hex)
13201         sprintf (buf, "0x%x", (unsigned int) disp);
13202       else
13203         sprintf (buf, "%d", (int) disp);
13204     }
13205 }
13206
13207 /* Put DISP in BUF as signed hex number.  */
13208
13209 static void
13210 print_displacement (char *buf, bfd_vma disp)
13211 {
13212   bfd_signed_vma val = disp;
13213   char tmp[30];
13214   int i, j = 0;
13215
13216   if (val < 0)
13217     {
13218       buf[j++] = '-';
13219       val = -disp;
13220
13221       /* Check for possible overflow.  */
13222       if (val < 0)
13223         {
13224           switch (address_mode)
13225             {
13226             case mode_64bit:
13227               strcpy (buf + j, "0x8000000000000000");
13228               break;
13229             case mode_32bit:
13230               strcpy (buf + j, "0x80000000");
13231               break;
13232             case mode_16bit:
13233               strcpy (buf + j, "0x8000");
13234               break;
13235             }
13236           return;
13237         }
13238     }
13239
13240   buf[j++] = '0';
13241   buf[j++] = 'x';
13242
13243   sprintf_vma (tmp, (bfd_vma) val);
13244   for (i = 0; tmp[i] == '0'; i++)
13245     continue;
13246   if (tmp[i] == '\0')
13247     i--;
13248   strcpy (buf + j, tmp + i);
13249 }
13250
13251 static void
13252 intel_operand_size (int bytemode, int sizeflag)
13253 {
13254   if (vex.evex
13255       && vex.b
13256       && (bytemode == x_mode
13257           || bytemode == evex_half_bcst_xmmq_mode))
13258     {
13259       if (vex.w)
13260         oappend ("QWORD PTR ");
13261       else
13262         oappend ("DWORD PTR ");
13263       return;
13264     }
13265   switch (bytemode)
13266     {
13267     case b_mode:
13268     case b_swap_mode:
13269     case dqb_mode:
13270     case db_mode:
13271       oappend ("BYTE PTR ");
13272       break;
13273     case w_mode:
13274     case dw_mode:
13275     case dqw_mode:
13276       oappend ("WORD PTR ");
13277       break;
13278     case indir_v_mode:
13279       if (address_mode == mode_64bit && isa64 == intel64)
13280         {
13281           oappend ("QWORD PTR ");
13282           break;
13283         }
13284       /* Fall through.  */
13285     case stack_v_mode:
13286       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13287         {
13288           oappend ("QWORD PTR ");
13289           break;
13290         }
13291       /* Fall through.  */
13292     case v_mode:
13293     case v_swap_mode:
13294     case dq_mode:
13295       USED_REX (REX_W);
13296       if (rex & REX_W)
13297         oappend ("QWORD PTR ");
13298       else
13299         {
13300           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13301             oappend ("DWORD PTR ");
13302           else
13303             oappend ("WORD PTR ");
13304           used_prefixes |= (prefixes & PREFIX_DATA);
13305         }
13306       break;
13307     case z_mode:
13308       if ((rex & REX_W) || (sizeflag & DFLAG))
13309         *obufp++ = 'D';
13310       oappend ("WORD PTR ");
13311       if (!(rex & REX_W))
13312         used_prefixes |= (prefixes & PREFIX_DATA);
13313       break;
13314     case a_mode:
13315       if (sizeflag & DFLAG)
13316         oappend ("QWORD PTR ");
13317       else
13318         oappend ("DWORD PTR ");
13319       used_prefixes |= (prefixes & PREFIX_DATA);
13320       break;
13321     case movsxd_mode:
13322       if (!(sizeflag & DFLAG) && isa64 == intel64)
13323         oappend ("WORD PTR ");
13324       else
13325         oappend ("DWORD PTR ");
13326       used_prefixes |= (prefixes & PREFIX_DATA);
13327       break;
13328     case d_mode:
13329     case d_scalar_swap_mode:
13330     case d_swap_mode:
13331     case dqd_mode:
13332       oappend ("DWORD PTR ");
13333       break;
13334     case q_mode:
13335     case q_scalar_swap_mode:
13336     case q_swap_mode:
13337       oappend ("QWORD PTR ");
13338       break;
13339     case m_mode:
13340       if (address_mode == mode_64bit)
13341         oappend ("QWORD PTR ");
13342       else
13343         oappend ("DWORD PTR ");
13344       break;
13345     case f_mode:
13346       if (sizeflag & DFLAG)
13347         oappend ("FWORD PTR ");
13348       else
13349         oappend ("DWORD PTR ");
13350       used_prefixes |= (prefixes & PREFIX_DATA);
13351       break;
13352     case t_mode:
13353       oappend ("TBYTE PTR ");
13354       break;
13355     case x_mode:
13356     case x_swap_mode:
13357     case evex_x_gscat_mode:
13358     case evex_x_nobcst_mode:
13359     case b_scalar_mode:
13360     case w_scalar_mode:
13361       if (need_vex)
13362         {
13363           switch (vex.length)
13364             {
13365             case 128:
13366               oappend ("XMMWORD PTR ");
13367               break;
13368             case 256:
13369               oappend ("YMMWORD PTR ");
13370               break;
13371             case 512:
13372               oappend ("ZMMWORD PTR ");
13373               break;
13374             default:
13375               abort ();
13376             }
13377         }
13378       else
13379         oappend ("XMMWORD PTR ");
13380       break;
13381     case xmm_mode:
13382       oappend ("XMMWORD PTR ");
13383       break;
13384     case ymm_mode:
13385       oappend ("YMMWORD PTR ");
13386       break;
13387     case xmmq_mode:
13388     case evex_half_bcst_xmmq_mode:
13389       if (!need_vex)
13390         abort ();
13391
13392       switch (vex.length)
13393         {
13394         case 128:
13395           oappend ("QWORD PTR ");
13396           break;
13397         case 256:
13398           oappend ("XMMWORD PTR ");
13399           break;
13400         case 512:
13401           oappend ("YMMWORD PTR ");
13402           break;
13403         default:
13404           abort ();
13405         }
13406       break;
13407     case xmm_mb_mode:
13408       if (!need_vex)
13409         abort ();
13410
13411       switch (vex.length)
13412         {
13413         case 128:
13414         case 256:
13415         case 512:
13416           oappend ("BYTE PTR ");
13417           break;
13418         default:
13419           abort ();
13420         }
13421       break;
13422     case xmm_mw_mode:
13423       if (!need_vex)
13424         abort ();
13425
13426       switch (vex.length)
13427         {
13428         case 128:
13429         case 256:
13430         case 512:
13431           oappend ("WORD PTR ");
13432           break;
13433         default:
13434           abort ();
13435         }
13436       break;
13437     case xmm_md_mode:
13438       if (!need_vex)
13439         abort ();
13440
13441       switch (vex.length)
13442         {
13443         case 128:
13444         case 256:
13445         case 512:
13446           oappend ("DWORD PTR ");
13447           break;
13448         default:
13449           abort ();
13450         }
13451       break;
13452     case xmm_mq_mode:
13453       if (!need_vex)
13454         abort ();
13455
13456       switch (vex.length)
13457         {
13458         case 128:
13459         case 256:
13460         case 512:
13461           oappend ("QWORD PTR ");
13462           break;
13463         default:
13464           abort ();
13465         }
13466       break;
13467     case xmmdw_mode:
13468       if (!need_vex)
13469         abort ();
13470
13471       switch (vex.length)
13472         {
13473         case 128:
13474           oappend ("WORD PTR ");
13475           break;
13476         case 256:
13477           oappend ("DWORD PTR ");
13478           break;
13479         case 512:
13480           oappend ("QWORD PTR ");
13481           break;
13482         default:
13483           abort ();
13484         }
13485       break;
13486     case xmmqd_mode:
13487       if (!need_vex)
13488         abort ();
13489
13490       switch (vex.length)
13491         {
13492         case 128:
13493           oappend ("DWORD PTR ");
13494           break;
13495         case 256:
13496           oappend ("QWORD PTR ");
13497           break;
13498         case 512:
13499           oappend ("XMMWORD PTR ");
13500           break;
13501         default:
13502           abort ();
13503         }
13504       break;
13505     case ymmq_mode:
13506       if (!need_vex)
13507         abort ();
13508
13509       switch (vex.length)
13510         {
13511         case 128:
13512           oappend ("QWORD PTR ");
13513           break;
13514         case 256:
13515           oappend ("YMMWORD PTR ");
13516           break;
13517         case 512:
13518           oappend ("ZMMWORD PTR ");
13519           break;
13520         default:
13521           abort ();
13522         }
13523       break;
13524     case ymmxmm_mode:
13525       if (!need_vex)
13526         abort ();
13527
13528       switch (vex.length)
13529         {
13530         case 128:
13531         case 256:
13532           oappend ("XMMWORD PTR ");
13533           break;
13534         default:
13535           abort ();
13536         }
13537       break;
13538     case o_mode:
13539       oappend ("OWORD PTR ");
13540       break;
13541     case vex_scalar_w_dq_mode:
13542       if (!need_vex)
13543         abort ();
13544
13545       if (vex.w)
13546         oappend ("QWORD PTR ");
13547       else
13548         oappend ("DWORD PTR ");
13549       break;
13550     case vex_vsib_d_w_dq_mode:
13551     case vex_vsib_q_w_dq_mode:
13552       if (!need_vex)
13553         abort ();
13554
13555       if (!vex.evex)
13556         {
13557           if (vex.w)
13558             oappend ("QWORD PTR ");
13559           else
13560             oappend ("DWORD PTR ");
13561         }
13562       else
13563         {
13564           switch (vex.length)
13565             {
13566             case 128:
13567               oappend ("XMMWORD PTR ");
13568               break;
13569             case 256:
13570               oappend ("YMMWORD PTR ");
13571               break;
13572             case 512:
13573               oappend ("ZMMWORD PTR ");
13574               break;
13575             default:
13576               abort ();
13577             }
13578         }
13579       break;
13580     case vex_vsib_q_w_d_mode:
13581     case vex_vsib_d_w_d_mode:
13582       if (!need_vex || !vex.evex)
13583         abort ();
13584
13585       switch (vex.length)
13586         {
13587         case 128:
13588           oappend ("QWORD PTR ");
13589           break;
13590         case 256:
13591           oappend ("XMMWORD PTR ");
13592           break;
13593         case 512:
13594           oappend ("YMMWORD PTR ");
13595           break;
13596         default:
13597           abort ();
13598         }
13599
13600       break;
13601     case mask_bd_mode:
13602       if (!need_vex || vex.length != 128)
13603         abort ();
13604       if (vex.w)
13605         oappend ("DWORD PTR ");
13606       else
13607         oappend ("BYTE PTR ");
13608       break;
13609     case mask_mode:
13610       if (!need_vex)
13611         abort ();
13612       if (vex.w)
13613         oappend ("QWORD PTR ");
13614       else
13615         oappend ("WORD PTR ");
13616       break;
13617     case v_bnd_mode:
13618     case v_bndmk_mode:
13619     default:
13620       break;
13621     }
13622 }
13623
13624 static void
13625 OP_E_register (int bytemode, int sizeflag)
13626 {
13627   int reg = modrm.rm;
13628   const char **names;
13629
13630   USED_REX (REX_B);
13631   if ((rex & REX_B))
13632     reg += 8;
13633
13634   if ((sizeflag & SUFFIX_ALWAYS)
13635       && (bytemode == b_swap_mode
13636           || bytemode == bnd_swap_mode
13637           || bytemode == v_swap_mode))
13638     swap_operand ();
13639
13640   switch (bytemode)
13641     {
13642     case b_mode:
13643     case b_swap_mode:
13644       USED_REX (0);
13645       if (rex)
13646         names = names8rex;
13647       else
13648         names = names8;
13649       break;
13650     case w_mode:
13651       names = names16;
13652       break;
13653     case d_mode:
13654     case dw_mode:
13655     case db_mode:
13656       names = names32;
13657       break;
13658     case q_mode:
13659       names = names64;
13660       break;
13661     case m_mode:
13662     case v_bnd_mode:
13663       names = address_mode == mode_64bit ? names64 : names32;
13664       break;
13665     case bnd_mode:
13666     case bnd_swap_mode:
13667       if (reg > 0x3)
13668         {
13669           oappend ("(bad)");
13670           return;
13671         }
13672       names = names_bnd;
13673       break;
13674     case indir_v_mode:
13675       if (address_mode == mode_64bit && isa64 == intel64)
13676         {
13677           names = names64;
13678           break;
13679         }
13680       /* Fall through.  */
13681     case stack_v_mode:
13682       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13683         {
13684           names = names64;
13685           break;
13686         }
13687       bytemode = v_mode;
13688       /* Fall through.  */
13689     case v_mode:
13690     case v_swap_mode:
13691     case dq_mode:
13692     case dqb_mode:
13693     case dqd_mode:
13694     case dqw_mode:
13695       USED_REX (REX_W);
13696       if (rex & REX_W)
13697         names = names64;
13698       else
13699         {
13700           if ((sizeflag & DFLAG)
13701               || (bytemode != v_mode
13702                   && bytemode != v_swap_mode))
13703             names = names32;
13704           else
13705             names = names16;
13706           used_prefixes |= (prefixes & PREFIX_DATA);
13707         }
13708       break;
13709     case movsxd_mode:
13710       if (!(sizeflag & DFLAG) && isa64 == intel64)
13711         names = names16;
13712       else
13713         names = names32;
13714       used_prefixes |= (prefixes & PREFIX_DATA);
13715       break;
13716     case va_mode:
13717       names = (address_mode == mode_64bit
13718                ? names64 : names32);
13719       if (!(prefixes & PREFIX_ADDR))
13720         names = (address_mode == mode_16bit
13721                      ? names16 : names);
13722       else
13723         {
13724           /* Remove "addr16/addr32".  */
13725           all_prefixes[last_addr_prefix] = 0;
13726           names = (address_mode != mode_32bit
13727                        ? names32 : names16);
13728           used_prefixes |= PREFIX_ADDR;
13729         }
13730       break;
13731     case mask_bd_mode:
13732     case mask_mode:
13733       if (reg > 0x7)
13734         {
13735           oappend ("(bad)");
13736           return;
13737         }
13738       names = names_mask;
13739       break;
13740     case 0:
13741       return;
13742     default:
13743       oappend (INTERNAL_DISASSEMBLER_ERROR);
13744       return;
13745     }
13746   oappend (names[reg]);
13747 }
13748
13749 static void
13750 OP_E_memory (int bytemode, int sizeflag)
13751 {
13752   bfd_vma disp = 0;
13753   int add = (rex & REX_B) ? 8 : 0;
13754   int riprel = 0;
13755   int shift;
13756
13757   if (vex.evex)
13758     {
13759       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13760       if (vex.b
13761           && bytemode != x_mode
13762           && bytemode != xmmq_mode
13763           && bytemode != evex_half_bcst_xmmq_mode)
13764         {
13765           BadOp ();
13766           return;
13767         }
13768       switch (bytemode)
13769         {
13770         case dqw_mode:
13771         case dw_mode:
13772           shift = 1;
13773           break;
13774         case dqb_mode:
13775         case db_mode:
13776           shift = 0;
13777           break;
13778         case dq_mode:
13779           if (address_mode != mode_64bit)
13780             {
13781               shift = 2;
13782               break;
13783             }
13784             /* fall through */
13785         case vex_scalar_w_dq_mode:
13786         case vex_vsib_d_w_dq_mode:
13787         case vex_vsib_d_w_d_mode:
13788         case vex_vsib_q_w_dq_mode:
13789         case vex_vsib_q_w_d_mode:
13790         case evex_x_gscat_mode:
13791           shift = vex.w ? 3 : 2;
13792           break;
13793         case x_mode:
13794         case evex_half_bcst_xmmq_mode:
13795         case xmmq_mode:
13796           if (vex.b)
13797             {
13798               shift = vex.w ? 3 : 2;
13799               break;
13800             }
13801           /* Fall through.  */
13802         case xmmqd_mode:
13803         case xmmdw_mode:
13804         case ymmq_mode:
13805         case evex_x_nobcst_mode:
13806         case x_swap_mode:
13807           switch (vex.length)
13808             {
13809             case 128:
13810               shift = 4;
13811               break;
13812             case 256:
13813               shift = 5;
13814               break;
13815             case 512:
13816               shift = 6;
13817               break;
13818             default:
13819               abort ();
13820             }
13821           break;
13822         case ymm_mode:
13823           shift = 5;
13824           break;
13825         case xmm_mode:
13826           shift = 4;
13827           break;
13828         case xmm_mq_mode:
13829         case q_mode:
13830         case q_swap_mode:
13831         case q_scalar_swap_mode:
13832           shift = 3;
13833           break;
13834         case dqd_mode:
13835         case xmm_md_mode:
13836         case d_mode:
13837         case d_swap_mode:
13838         case d_scalar_swap_mode:
13839           shift = 2;
13840           break;
13841         case w_scalar_mode:
13842         case xmm_mw_mode:
13843           shift = 1;
13844           break;
13845         case b_scalar_mode:
13846         case xmm_mb_mode:
13847           shift = 0;
13848           break;
13849         default:
13850           abort ();
13851         }
13852       /* Make necessary corrections to shift for modes that need it.
13853          For these modes we currently have shift 4, 5 or 6 depending on
13854          vex.length (it corresponds to xmmword, ymmword or zmmword
13855          operand).  We might want to make it 3, 4 or 5 (e.g. for
13856          xmmq_mode).  In case of broadcast enabled the corrections
13857          aren't needed, as element size is always 32 or 64 bits.  */
13858       if (!vex.b
13859           && (bytemode == xmmq_mode
13860               || bytemode == evex_half_bcst_xmmq_mode))
13861         shift -= 1;
13862       else if (bytemode == xmmqd_mode)
13863         shift -= 2;
13864       else if (bytemode == xmmdw_mode)
13865         shift -= 3;
13866       else if (bytemode == ymmq_mode && vex.length == 128)
13867         shift -= 1;
13868     }
13869   else
13870     shift = 0;
13871
13872   USED_REX (REX_B);
13873   if (intel_syntax)
13874     intel_operand_size (bytemode, sizeflag);
13875   append_seg ();
13876
13877   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13878     {
13879       /* 32/64 bit address mode */
13880       int havedisp;
13881       int havesib;
13882       int havebase;
13883       int haveindex;
13884       int needindex;
13885       int needaddr32;
13886       int base, rbase;
13887       int vindex = 0;
13888       int scale = 0;
13889       int addr32flag = !((sizeflag & AFLAG)
13890                          || bytemode == v_bnd_mode
13891                          || bytemode == v_bndmk_mode
13892                          || bytemode == bnd_mode
13893                          || bytemode == bnd_swap_mode);
13894       const char **indexes64 = names64;
13895       const char **indexes32 = names32;
13896
13897       havesib = 0;
13898       havebase = 1;
13899       haveindex = 0;
13900       base = modrm.rm;
13901
13902       if (base == 4)
13903         {
13904           havesib = 1;
13905           vindex = sib.index;
13906           USED_REX (REX_X);
13907           if (rex & REX_X)
13908             vindex += 8;
13909           switch (bytemode)
13910             {
13911             case vex_vsib_d_w_dq_mode:
13912             case vex_vsib_d_w_d_mode:
13913             case vex_vsib_q_w_dq_mode:
13914             case vex_vsib_q_w_d_mode:
13915               if (!need_vex)
13916                 abort ();
13917               if (vex.evex)
13918                 {
13919                   if (!vex.v)
13920                     vindex += 16;
13921                 }
13922
13923               haveindex = 1;
13924               switch (vex.length)
13925                 {
13926                 case 128:
13927                   indexes64 = indexes32 = names_xmm;
13928                   break;
13929                 case 256:
13930                   if (!vex.w
13931                       || bytemode == vex_vsib_q_w_dq_mode
13932                       || bytemode == vex_vsib_q_w_d_mode)
13933                     indexes64 = indexes32 = names_ymm;
13934                   else
13935                     indexes64 = indexes32 = names_xmm;
13936                   break;
13937                 case 512:
13938                   if (!vex.w
13939                       || bytemode == vex_vsib_q_w_dq_mode
13940                       || bytemode == vex_vsib_q_w_d_mode)
13941                     indexes64 = indexes32 = names_zmm;
13942                   else
13943                     indexes64 = indexes32 = names_ymm;
13944                   break;
13945                 default:
13946                   abort ();
13947                 }
13948               break;
13949             default:
13950               haveindex = vindex != 4;
13951               break;
13952             }
13953           scale = sib.scale;
13954           base = sib.base;
13955           codep++;
13956         }
13957       rbase = base + add;
13958
13959       switch (modrm.mod)
13960         {
13961         case 0:
13962           if (base == 5)
13963             {
13964               havebase = 0;
13965               if (address_mode == mode_64bit && !havesib)
13966                 riprel = 1;
13967               disp = get32s ();
13968               if (riprel && bytemode == v_bndmk_mode)
13969                 {
13970                   oappend ("(bad)");
13971                   return;
13972                 }
13973             }
13974           break;
13975         case 1:
13976           FETCH_DATA (the_info, codep + 1);
13977           disp = *codep++;
13978           if ((disp & 0x80) != 0)
13979             disp -= 0x100;
13980           if (vex.evex && shift > 0)
13981             disp <<= shift;
13982           break;
13983         case 2:
13984           disp = get32s ();
13985           break;
13986         }
13987
13988       needindex = 0;
13989       needaddr32 = 0;
13990       if (havesib
13991           && !havebase
13992           && !haveindex
13993           && address_mode != mode_16bit)
13994         {
13995           if (address_mode == mode_64bit)
13996             {
13997               /* Display eiz instead of addr32.  */
13998               needindex = addr32flag;
13999               needaddr32 = 1;
14000             }
14001           else
14002             {
14003               /* In 32-bit mode, we need index register to tell [offset]
14004                  from [eiz*1 + offset].  */
14005               needindex = 1;
14006             }
14007         }
14008
14009       havedisp = (havebase
14010                   || needindex
14011                   || (havesib && (haveindex || scale != 0)));
14012
14013       if (!intel_syntax)
14014         if (modrm.mod != 0 || base == 5)
14015           {
14016             if (havedisp || riprel)
14017               print_displacement (scratchbuf, disp);
14018             else
14019               print_operand_value (scratchbuf, 1, disp);
14020             oappend (scratchbuf);
14021             if (riprel)
14022               {
14023                 set_op (disp, 1);
14024                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14025               }
14026           }
14027
14028       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14029           && (address_mode != mode_64bit
14030               || ((bytemode != v_bnd_mode)
14031                   && (bytemode != v_bndmk_mode)
14032                   && (bytemode != bnd_mode)
14033                   && (bytemode != bnd_swap_mode))))
14034         used_prefixes |= PREFIX_ADDR;
14035
14036       if (havedisp || (intel_syntax && riprel))
14037         {
14038           *obufp++ = open_char;
14039           if (intel_syntax && riprel)
14040             {
14041               set_op (disp, 1);
14042               oappend (!addr32flag ? "rip" : "eip");
14043             }
14044           *obufp = '\0';
14045           if (havebase)
14046             oappend (address_mode == mode_64bit && !addr32flag
14047                      ? names64[rbase] : names32[rbase]);
14048           if (havesib)
14049             {
14050               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14051                  print index to tell base + index from base.  */
14052               if (scale != 0
14053                   || needindex
14054                   || haveindex
14055                   || (havebase && base != ESP_REG_NUM))
14056                 {
14057                   if (!intel_syntax || havebase)
14058                     {
14059                       *obufp++ = separator_char;
14060                       *obufp = '\0';
14061                     }
14062                   if (haveindex)
14063                     oappend (address_mode == mode_64bit && !addr32flag
14064                              ? indexes64[vindex] : indexes32[vindex]);
14065                   else
14066                     oappend (address_mode == mode_64bit && !addr32flag
14067                              ? index64 : index32);
14068
14069                   *obufp++ = scale_char;
14070                   *obufp = '\0';
14071                   sprintf (scratchbuf, "%d", 1 << scale);
14072                   oappend (scratchbuf);
14073                 }
14074             }
14075           if (intel_syntax
14076               && (disp || modrm.mod != 0 || base == 5))
14077             {
14078               if (!havedisp || (bfd_signed_vma) disp >= 0)
14079                 {
14080                   *obufp++ = '+';
14081                   *obufp = '\0';
14082                 }
14083               else if (modrm.mod != 1 && disp != -disp)
14084                 {
14085                   *obufp++ = '-';
14086                   *obufp = '\0';
14087                   disp = - (bfd_signed_vma) disp;
14088                 }
14089
14090               if (havedisp)
14091                 print_displacement (scratchbuf, disp);
14092               else
14093                 print_operand_value (scratchbuf, 1, disp);
14094               oappend (scratchbuf);
14095             }
14096
14097           *obufp++ = close_char;
14098           *obufp = '\0';
14099         }
14100       else if (intel_syntax)
14101         {
14102           if (modrm.mod != 0 || base == 5)
14103             {
14104               if (!active_seg_prefix)
14105                 {
14106                   oappend (names_seg[ds_reg - es_reg]);
14107                   oappend (":");
14108                 }
14109               print_operand_value (scratchbuf, 1, disp);
14110               oappend (scratchbuf);
14111             }
14112         }
14113     }
14114   else if (bytemode == v_bnd_mode
14115            || bytemode == v_bndmk_mode
14116            || bytemode == bnd_mode
14117            || bytemode == bnd_swap_mode)
14118     {
14119       oappend ("(bad)");
14120       return;
14121     }
14122   else
14123     {
14124       /* 16 bit address mode */
14125       used_prefixes |= prefixes & PREFIX_ADDR;
14126       switch (modrm.mod)
14127         {
14128         case 0:
14129           if (modrm.rm == 6)
14130             {
14131               disp = get16 ();
14132               if ((disp & 0x8000) != 0)
14133                 disp -= 0x10000;
14134             }
14135           break;
14136         case 1:
14137           FETCH_DATA (the_info, codep + 1);
14138           disp = *codep++;
14139           if ((disp & 0x80) != 0)
14140             disp -= 0x100;
14141           if (vex.evex && shift > 0)
14142             disp <<= shift;
14143           break;
14144         case 2:
14145           disp = get16 ();
14146           if ((disp & 0x8000) != 0)
14147             disp -= 0x10000;
14148           break;
14149         }
14150
14151       if (!intel_syntax)
14152         if (modrm.mod != 0 || modrm.rm == 6)
14153           {
14154             print_displacement (scratchbuf, disp);
14155             oappend (scratchbuf);
14156           }
14157
14158       if (modrm.mod != 0 || modrm.rm != 6)
14159         {
14160           *obufp++ = open_char;
14161           *obufp = '\0';
14162           oappend (index16[modrm.rm]);
14163           if (intel_syntax
14164               && (disp || modrm.mod != 0 || modrm.rm == 6))
14165             {
14166               if ((bfd_signed_vma) disp >= 0)
14167                 {
14168                   *obufp++ = '+';
14169                   *obufp = '\0';
14170                 }
14171               else if (modrm.mod != 1)
14172                 {
14173                   *obufp++ = '-';
14174                   *obufp = '\0';
14175                   disp = - (bfd_signed_vma) disp;
14176                 }
14177
14178               print_displacement (scratchbuf, disp);
14179               oappend (scratchbuf);
14180             }
14181
14182           *obufp++ = close_char;
14183           *obufp = '\0';
14184         }
14185       else if (intel_syntax)
14186         {
14187           if (!active_seg_prefix)
14188             {
14189               oappend (names_seg[ds_reg - es_reg]);
14190               oappend (":");
14191             }
14192           print_operand_value (scratchbuf, 1, disp & 0xffff);
14193           oappend (scratchbuf);
14194         }
14195     }
14196   if (vex.evex && vex.b
14197       && (bytemode == x_mode
14198           || bytemode == xmmq_mode
14199           || bytemode == evex_half_bcst_xmmq_mode))
14200     {
14201       if (vex.w
14202           || bytemode == xmmq_mode
14203           || bytemode == evex_half_bcst_xmmq_mode)
14204         {
14205           switch (vex.length)
14206             {
14207             case 128:
14208               oappend ("{1to2}");
14209               break;
14210             case 256:
14211               oappend ("{1to4}");
14212               break;
14213             case 512:
14214               oappend ("{1to8}");
14215               break;
14216             default:
14217               abort ();
14218             }
14219         }
14220       else
14221         {
14222           switch (vex.length)
14223             {
14224             case 128:
14225               oappend ("{1to4}");
14226               break;
14227             case 256:
14228               oappend ("{1to8}");
14229               break;
14230             case 512:
14231               oappend ("{1to16}");
14232               break;
14233             default:
14234               abort ();
14235             }
14236         }
14237     }
14238 }
14239
14240 static void
14241 OP_E (int bytemode, int sizeflag)
14242 {
14243   /* Skip mod/rm byte.  */
14244   MODRM_CHECK;
14245   codep++;
14246
14247   if (modrm.mod == 3)
14248     OP_E_register (bytemode, sizeflag);
14249   else
14250     OP_E_memory (bytemode, sizeflag);
14251 }
14252
14253 static void
14254 OP_G (int bytemode, int sizeflag)
14255 {
14256   int add = 0;
14257   const char **names;
14258   USED_REX (REX_R);
14259   if (rex & REX_R)
14260     add += 8;
14261   switch (bytemode)
14262     {
14263     case b_mode:
14264       USED_REX (0);
14265       if (rex)
14266         oappend (names8rex[modrm.reg + add]);
14267       else
14268         oappend (names8[modrm.reg + add]);
14269       break;
14270     case w_mode:
14271       oappend (names16[modrm.reg + add]);
14272       break;
14273     case d_mode:
14274     case db_mode:
14275     case dw_mode:
14276       oappend (names32[modrm.reg + add]);
14277       break;
14278     case q_mode:
14279       oappend (names64[modrm.reg + add]);
14280       break;
14281     case bnd_mode:
14282       if (modrm.reg > 0x3)
14283         {
14284           oappend ("(bad)");
14285           return;
14286         }
14287       oappend (names_bnd[modrm.reg]);
14288       break;
14289     case v_mode:
14290     case dq_mode:
14291     case dqb_mode:
14292     case dqd_mode:
14293     case dqw_mode:
14294     case movsxd_mode:
14295       USED_REX (REX_W);
14296       if (rex & REX_W)
14297         oappend (names64[modrm.reg + add]);
14298       else
14299         {
14300           if ((sizeflag & DFLAG)
14301               || (bytemode != v_mode && bytemode != movsxd_mode))
14302             oappend (names32[modrm.reg + add]);
14303           else
14304             oappend (names16[modrm.reg + add]);
14305           used_prefixes |= (prefixes & PREFIX_DATA);
14306         }
14307       break;
14308     case va_mode:
14309       names = (address_mode == mode_64bit
14310                ? names64 : names32);
14311       if (!(prefixes & PREFIX_ADDR))
14312         {
14313           if (address_mode == mode_16bit)
14314             names = names16;
14315         }
14316       else
14317         {
14318           /* Remove "addr16/addr32".  */
14319           all_prefixes[last_addr_prefix] = 0;
14320           names = (address_mode != mode_32bit
14321                        ? names32 : names16);
14322           used_prefixes |= PREFIX_ADDR;
14323         }
14324       oappend (names[modrm.reg + add]);
14325       break;
14326     case m_mode:
14327       if (address_mode == mode_64bit)
14328         oappend (names64[modrm.reg + add]);
14329       else
14330         oappend (names32[modrm.reg + add]);
14331       break;
14332     case mask_bd_mode:
14333     case mask_mode:
14334       if ((modrm.reg + add) > 0x7)
14335         {
14336           oappend ("(bad)");
14337           return;
14338         }
14339       oappend (names_mask[modrm.reg + add]);
14340       break;
14341     default:
14342       oappend (INTERNAL_DISASSEMBLER_ERROR);
14343       break;
14344     }
14345 }
14346
14347 static bfd_vma
14348 get64 (void)
14349 {
14350   bfd_vma x;
14351 #ifdef BFD64
14352   unsigned int a;
14353   unsigned int b;
14354
14355   FETCH_DATA (the_info, codep + 8);
14356   a = *codep++ & 0xff;
14357   a |= (*codep++ & 0xff) << 8;
14358   a |= (*codep++ & 0xff) << 16;
14359   a |= (*codep++ & 0xffu) << 24;
14360   b = *codep++ & 0xff;
14361   b |= (*codep++ & 0xff) << 8;
14362   b |= (*codep++ & 0xff) << 16;
14363   b |= (*codep++ & 0xffu) << 24;
14364   x = a + ((bfd_vma) b << 32);
14365 #else
14366   abort ();
14367   x = 0;
14368 #endif
14369   return x;
14370 }
14371
14372 static bfd_signed_vma
14373 get32 (void)
14374 {
14375   bfd_signed_vma x = 0;
14376
14377   FETCH_DATA (the_info, codep + 4);
14378   x = *codep++ & (bfd_signed_vma) 0xff;
14379   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14380   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14381   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14382   return x;
14383 }
14384
14385 static bfd_signed_vma
14386 get32s (void)
14387 {
14388   bfd_signed_vma x = 0;
14389
14390   FETCH_DATA (the_info, codep + 4);
14391   x = *codep++ & (bfd_signed_vma) 0xff;
14392   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14393   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14394   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14395
14396   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14397
14398   return x;
14399 }
14400
14401 static int
14402 get16 (void)
14403 {
14404   int x = 0;
14405
14406   FETCH_DATA (the_info, codep + 2);
14407   x = *codep++ & 0xff;
14408   x |= (*codep++ & 0xff) << 8;
14409   return x;
14410 }
14411
14412 static void
14413 set_op (bfd_vma op, int riprel)
14414 {
14415   op_index[op_ad] = op_ad;
14416   if (address_mode == mode_64bit)
14417     {
14418       op_address[op_ad] = op;
14419       op_riprel[op_ad] = riprel;
14420     }
14421   else
14422     {
14423       /* Mask to get a 32-bit address.  */
14424       op_address[op_ad] = op & 0xffffffff;
14425       op_riprel[op_ad] = riprel & 0xffffffff;
14426     }
14427 }
14428
14429 static void
14430 OP_REG (int code, int sizeflag)
14431 {
14432   const char *s;
14433   int add;
14434
14435   switch (code)
14436     {
14437     case es_reg: case ss_reg: case cs_reg:
14438     case ds_reg: case fs_reg: case gs_reg:
14439       oappend (names_seg[code - es_reg]);
14440       return;
14441     }
14442
14443   USED_REX (REX_B);
14444   if (rex & REX_B)
14445     add = 8;
14446   else
14447     add = 0;
14448
14449   switch (code)
14450     {
14451     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14452     case sp_reg: case bp_reg: case si_reg: case di_reg:
14453       s = names16[code - ax_reg + add];
14454       break;
14455     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14456     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14457       USED_REX (0);
14458       if (rex)
14459         s = names8rex[code - al_reg + add];
14460       else
14461         s = names8[code - al_reg];
14462       break;
14463     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14464     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14465       if (address_mode == mode_64bit
14466           && ((sizeflag & DFLAG) || (rex & REX_W)))
14467         {
14468           s = names64[code - rAX_reg + add];
14469           break;
14470         }
14471       code += eAX_reg - rAX_reg;
14472       /* Fall through.  */
14473     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14474     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14475       USED_REX (REX_W);
14476       if (rex & REX_W)
14477         s = names64[code - eAX_reg + add];
14478       else
14479         {
14480           if (sizeflag & DFLAG)
14481             s = names32[code - eAX_reg + add];
14482           else
14483             s = names16[code - eAX_reg + add];
14484           used_prefixes |= (prefixes & PREFIX_DATA);
14485         }
14486       break;
14487     default:
14488       s = INTERNAL_DISASSEMBLER_ERROR;
14489       break;
14490     }
14491   oappend (s);
14492 }
14493
14494 static void
14495 OP_IMREG (int code, int sizeflag)
14496 {
14497   const char *s;
14498
14499   switch (code)
14500     {
14501     case indir_dx_reg:
14502       if (intel_syntax)
14503         s = "dx";
14504       else
14505         s = "(%dx)";
14506       break;
14507     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14508     case sp_reg: case bp_reg: case si_reg: case di_reg:
14509       s = names16[code - ax_reg];
14510       break;
14511     case es_reg: case ss_reg: case cs_reg:
14512     case ds_reg: case fs_reg: case gs_reg:
14513       s = names_seg[code - es_reg];
14514       break;
14515     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14516     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14517       USED_REX (0);
14518       if (rex)
14519         s = names8rex[code - al_reg];
14520       else
14521         s = names8[code - al_reg];
14522       break;
14523     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14524     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14525       USED_REX (REX_W);
14526       if (rex & REX_W)
14527         s = names64[code - eAX_reg];
14528       else
14529         {
14530           if (sizeflag & DFLAG)
14531             s = names32[code - eAX_reg];
14532           else
14533             s = names16[code - eAX_reg];
14534           used_prefixes |= (prefixes & PREFIX_DATA);
14535         }
14536       break;
14537     case z_mode_ax_reg:
14538       if ((rex & REX_W) || (sizeflag & DFLAG))
14539         s = *names32;
14540       else
14541         s = *names16;
14542       if (!(rex & REX_W))
14543         used_prefixes |= (prefixes & PREFIX_DATA);
14544       break;
14545     default:
14546       s = INTERNAL_DISASSEMBLER_ERROR;
14547       break;
14548     }
14549   oappend (s);
14550 }
14551
14552 static void
14553 OP_I (int bytemode, int sizeflag)
14554 {
14555   bfd_signed_vma op;
14556   bfd_signed_vma mask = -1;
14557
14558   switch (bytemode)
14559     {
14560     case b_mode:
14561       FETCH_DATA (the_info, codep + 1);
14562       op = *codep++;
14563       mask = 0xff;
14564       break;
14565     case v_mode:
14566       USED_REX (REX_W);
14567       if (rex & REX_W)
14568         op = get32s ();
14569       else
14570         {
14571           if (sizeflag & DFLAG)
14572             {
14573               op = get32 ();
14574               mask = 0xffffffff;
14575             }
14576           else
14577             {
14578               op = get16 ();
14579               mask = 0xfffff;
14580             }
14581           used_prefixes |= (prefixes & PREFIX_DATA);
14582         }
14583       break;
14584     case d_mode:
14585       mask = 0xffffffff;
14586       op = get32 ();
14587       break;
14588     case w_mode:
14589       mask = 0xfffff;
14590       op = get16 ();
14591       break;
14592     case const_1_mode:
14593       if (intel_syntax)
14594         oappend ("1");
14595       return;
14596     default:
14597       oappend (INTERNAL_DISASSEMBLER_ERROR);
14598       return;
14599     }
14600
14601   op &= mask;
14602   scratchbuf[0] = '$';
14603   print_operand_value (scratchbuf + 1, 1, op);
14604   oappend_maybe_intel (scratchbuf);
14605   scratchbuf[0] = '\0';
14606 }
14607
14608 static void
14609 OP_I64 (int bytemode, int sizeflag)
14610 {
14611   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14612     {
14613       OP_I (bytemode, sizeflag);
14614       return;
14615     }
14616
14617   USED_REX (REX_W);
14618
14619   scratchbuf[0] = '$';
14620   print_operand_value (scratchbuf + 1, 1, get64 ());
14621   oappend_maybe_intel (scratchbuf);
14622   scratchbuf[0] = '\0';
14623 }
14624
14625 static void
14626 OP_sI (int bytemode, int sizeflag)
14627 {
14628   bfd_signed_vma op;
14629
14630   switch (bytemode)
14631     {
14632     case b_mode:
14633     case b_T_mode:
14634       FETCH_DATA (the_info, codep + 1);
14635       op = *codep++;
14636       if ((op & 0x80) != 0)
14637         op -= 0x100;
14638       if (bytemode == b_T_mode)
14639         {
14640           if (address_mode != mode_64bit
14641               || !((sizeflag & DFLAG) || (rex & REX_W)))
14642             {
14643               /* The operand-size prefix is overridden by a REX prefix.  */
14644               if ((sizeflag & DFLAG) || (rex & REX_W))
14645                 op &= 0xffffffff;
14646               else
14647                 op &= 0xffff;
14648           }
14649         }
14650       else
14651         {
14652           if (!(rex & REX_W))
14653             {
14654               if (sizeflag & DFLAG)
14655                 op &= 0xffffffff;
14656               else
14657                 op &= 0xffff;
14658             }
14659         }
14660       break;
14661     case v_mode:
14662       /* The operand-size prefix is overridden by a REX prefix.  */
14663       if ((sizeflag & DFLAG) || (rex & REX_W))
14664         op = get32s ();
14665       else
14666         op = get16 ();
14667       break;
14668     default:
14669       oappend (INTERNAL_DISASSEMBLER_ERROR);
14670       return;
14671     }
14672
14673   scratchbuf[0] = '$';
14674   print_operand_value (scratchbuf + 1, 1, op);
14675   oappend_maybe_intel (scratchbuf);
14676 }
14677
14678 static void
14679 OP_J (int bytemode, int sizeflag)
14680 {
14681   bfd_vma disp;
14682   bfd_vma mask = -1;
14683   bfd_vma segment = 0;
14684
14685   switch (bytemode)
14686     {
14687     case b_mode:
14688       FETCH_DATA (the_info, codep + 1);
14689       disp = *codep++;
14690       if ((disp & 0x80) != 0)
14691         disp -= 0x100;
14692       break;
14693     case v_mode:
14694       if (isa64 != intel64)
14695     case dqw_mode:
14696         USED_REX (REX_W);
14697       if ((sizeflag & DFLAG)
14698           || (address_mode == mode_64bit
14699               && ((isa64 == intel64 && bytemode != dqw_mode)
14700                   || (rex & REX_W))))
14701         disp = get32s ();
14702       else
14703         {
14704           disp = get16 ();
14705           if ((disp & 0x8000) != 0)
14706             disp -= 0x10000;
14707           /* In 16bit mode, address is wrapped around at 64k within
14708              the same segment.  Otherwise, a data16 prefix on a jump
14709              instruction means that the pc is masked to 16 bits after
14710              the displacement is added!  */
14711           mask = 0xffff;
14712           if ((prefixes & PREFIX_DATA) == 0)
14713             segment = ((start_pc + (codep - start_codep))
14714                        & ~((bfd_vma) 0xffff));
14715         }
14716       if (address_mode != mode_64bit
14717           || (isa64 != intel64 && !(rex & REX_W)))
14718         used_prefixes |= (prefixes & PREFIX_DATA);
14719       break;
14720     default:
14721       oappend (INTERNAL_DISASSEMBLER_ERROR);
14722       return;
14723     }
14724   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14725   set_op (disp, 0);
14726   print_operand_value (scratchbuf, 1, disp);
14727   oappend (scratchbuf);
14728 }
14729
14730 static void
14731 OP_SEG (int bytemode, int sizeflag)
14732 {
14733   if (bytemode == w_mode)
14734     oappend (names_seg[modrm.reg]);
14735   else
14736     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14737 }
14738
14739 static void
14740 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14741 {
14742   int seg, offset;
14743
14744   if (sizeflag & DFLAG)
14745     {
14746       offset = get32 ();
14747       seg = get16 ();
14748     }
14749   else
14750     {
14751       offset = get16 ();
14752       seg = get16 ();
14753     }
14754   used_prefixes |= (prefixes & PREFIX_DATA);
14755   if (intel_syntax)
14756     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14757   else
14758     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14759   oappend (scratchbuf);
14760 }
14761
14762 static void
14763 OP_OFF (int bytemode, int sizeflag)
14764 {
14765   bfd_vma off;
14766
14767   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14768     intel_operand_size (bytemode, sizeflag);
14769   append_seg ();
14770
14771   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14772     off = get32 ();
14773   else
14774     off = get16 ();
14775
14776   if (intel_syntax)
14777     {
14778       if (!active_seg_prefix)
14779         {
14780           oappend (names_seg[ds_reg - es_reg]);
14781           oappend (":");
14782         }
14783     }
14784   print_operand_value (scratchbuf, 1, off);
14785   oappend (scratchbuf);
14786 }
14787
14788 static void
14789 OP_OFF64 (int bytemode, int sizeflag)
14790 {
14791   bfd_vma off;
14792
14793   if (address_mode != mode_64bit
14794       || (prefixes & PREFIX_ADDR))
14795     {
14796       OP_OFF (bytemode, sizeflag);
14797       return;
14798     }
14799
14800   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14801     intel_operand_size (bytemode, sizeflag);
14802   append_seg ();
14803
14804   off = get64 ();
14805
14806   if (intel_syntax)
14807     {
14808       if (!active_seg_prefix)
14809         {
14810           oappend (names_seg[ds_reg - es_reg]);
14811           oappend (":");
14812         }
14813     }
14814   print_operand_value (scratchbuf, 1, off);
14815   oappend (scratchbuf);
14816 }
14817
14818 static void
14819 ptr_reg (int code, int sizeflag)
14820 {
14821   const char *s;
14822
14823   *obufp++ = open_char;
14824   used_prefixes |= (prefixes & PREFIX_ADDR);
14825   if (address_mode == mode_64bit)
14826     {
14827       if (!(sizeflag & AFLAG))
14828         s = names32[code - eAX_reg];
14829       else
14830         s = names64[code - eAX_reg];
14831     }
14832   else if (sizeflag & AFLAG)
14833     s = names32[code - eAX_reg];
14834   else
14835     s = names16[code - eAX_reg];
14836   oappend (s);
14837   *obufp++ = close_char;
14838   *obufp = 0;
14839 }
14840
14841 static void
14842 OP_ESreg (int code, int sizeflag)
14843 {
14844   if (intel_syntax)
14845     {
14846       switch (codep[-1])
14847         {
14848         case 0x6d:      /* insw/insl */
14849           intel_operand_size (z_mode, sizeflag);
14850           break;
14851         case 0xa5:      /* movsw/movsl/movsq */
14852         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14853         case 0xab:      /* stosw/stosl */
14854         case 0xaf:      /* scasw/scasl */
14855           intel_operand_size (v_mode, sizeflag);
14856           break;
14857         default:
14858           intel_operand_size (b_mode, sizeflag);
14859         }
14860     }
14861   oappend_maybe_intel ("%es:");
14862   ptr_reg (code, sizeflag);
14863 }
14864
14865 static void
14866 OP_DSreg (int code, int sizeflag)
14867 {
14868   if (intel_syntax)
14869     {
14870       switch (codep[-1])
14871         {
14872         case 0x6f:      /* outsw/outsl */
14873           intel_operand_size (z_mode, sizeflag);
14874           break;
14875         case 0xa5:      /* movsw/movsl/movsq */
14876         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14877         case 0xad:      /* lodsw/lodsl/lodsq */
14878           intel_operand_size (v_mode, sizeflag);
14879           break;
14880         default:
14881           intel_operand_size (b_mode, sizeflag);
14882         }
14883     }
14884   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14885      default segment register DS is printed.  */
14886   if (!active_seg_prefix)
14887     active_seg_prefix = PREFIX_DS;
14888   append_seg ();
14889   ptr_reg (code, sizeflag);
14890 }
14891
14892 static void
14893 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14894 {
14895   int add;
14896   if (rex & REX_R)
14897     {
14898       USED_REX (REX_R);
14899       add = 8;
14900     }
14901   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
14902     {
14903       all_prefixes[last_lock_prefix] = 0;
14904       used_prefixes |= PREFIX_LOCK;
14905       add = 8;
14906     }
14907   else
14908     add = 0;
14909   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
14910   oappend_maybe_intel (scratchbuf);
14911 }
14912
14913 static void
14914 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14915 {
14916   int add;
14917   USED_REX (REX_R);
14918   if (rex & REX_R)
14919     add = 8;
14920   else
14921     add = 0;
14922   if (intel_syntax)
14923     sprintf (scratchbuf, "db%d", modrm.reg + add);
14924   else
14925     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
14926   oappend (scratchbuf);
14927 }
14928
14929 static void
14930 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14931 {
14932   sprintf (scratchbuf, "%%tr%d", modrm.reg);
14933   oappend_maybe_intel (scratchbuf);
14934 }
14935
14936 static void
14937 OP_R (int bytemode, int sizeflag)
14938 {
14939   /* Skip mod/rm byte.  */
14940   MODRM_CHECK;
14941   codep++;
14942   OP_E_register (bytemode, sizeflag);
14943 }
14944
14945 static void
14946 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14947 {
14948   int reg = modrm.reg;
14949   const char **names;
14950
14951   used_prefixes |= (prefixes & PREFIX_DATA);
14952   if (prefixes & PREFIX_DATA)
14953     {
14954       names = names_xmm;
14955       USED_REX (REX_R);
14956       if (rex & REX_R)
14957         reg += 8;
14958     }
14959   else
14960     names = names_mm;
14961   oappend (names[reg]);
14962 }
14963
14964 static void
14965 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14966 {
14967   int reg = modrm.reg;
14968   const char **names;
14969
14970   USED_REX (REX_R);
14971   if (rex & REX_R)
14972     reg += 8;
14973   if (vex.evex)
14974     {
14975       if (!vex.r)
14976         reg += 16;
14977     }
14978
14979   if (need_vex
14980       && bytemode != xmm_mode
14981       && bytemode != xmmq_mode
14982       && bytemode != evex_half_bcst_xmmq_mode
14983       && bytemode != ymm_mode
14984       && bytemode != scalar_mode)
14985     {
14986       switch (vex.length)
14987         {
14988         case 128:
14989           names = names_xmm;
14990           break;
14991         case 256:
14992           if (vex.w
14993               || (bytemode != vex_vsib_q_w_dq_mode
14994                   && bytemode != vex_vsib_q_w_d_mode))
14995             names = names_ymm;
14996           else
14997             names = names_xmm;
14998           break;
14999         case 512:
15000           names = names_zmm;
15001           break;
15002         default:
15003           abort ();
15004         }
15005     }
15006   else if (bytemode == xmmq_mode
15007            || bytemode == evex_half_bcst_xmmq_mode)
15008     {
15009       switch (vex.length)
15010         {
15011         case 128:
15012         case 256:
15013           names = names_xmm;
15014           break;
15015         case 512:
15016           names = names_ymm;
15017           break;
15018         default:
15019           abort ();
15020         }
15021     }
15022   else if (bytemode == ymm_mode)
15023     names = names_ymm;
15024   else
15025     names = names_xmm;
15026   oappend (names[reg]);
15027 }
15028
15029 static void
15030 OP_EM (int bytemode, int sizeflag)
15031 {
15032   int reg;
15033   const char **names;
15034
15035   if (modrm.mod != 3)
15036     {
15037       if (intel_syntax
15038           && (bytemode == v_mode || bytemode == v_swap_mode))
15039         {
15040           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15041           used_prefixes |= (prefixes & PREFIX_DATA);
15042         }
15043       OP_E (bytemode, sizeflag);
15044       return;
15045     }
15046
15047   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15048     swap_operand ();
15049
15050   /* Skip mod/rm byte.  */
15051   MODRM_CHECK;
15052   codep++;
15053   used_prefixes |= (prefixes & PREFIX_DATA);
15054   reg = modrm.rm;
15055   if (prefixes & PREFIX_DATA)
15056     {
15057       names = names_xmm;
15058       USED_REX (REX_B);
15059       if (rex & REX_B)
15060         reg += 8;
15061     }
15062   else
15063     names = names_mm;
15064   oappend (names[reg]);
15065 }
15066
15067 /* cvt* are the only instructions in sse2 which have
15068    both SSE and MMX operands and also have 0x66 prefix
15069    in their opcode. 0x66 was originally used to differentiate
15070    between SSE and MMX instruction(operands). So we have to handle the
15071    cvt* separately using OP_EMC and OP_MXC */
15072 static void
15073 OP_EMC (int bytemode, int sizeflag)
15074 {
15075   if (modrm.mod != 3)
15076     {
15077       if (intel_syntax && bytemode == v_mode)
15078         {
15079           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15080           used_prefixes |= (prefixes & PREFIX_DATA);
15081         }
15082       OP_E (bytemode, sizeflag);
15083       return;
15084     }
15085
15086   /* Skip mod/rm byte.  */
15087   MODRM_CHECK;
15088   codep++;
15089   used_prefixes |= (prefixes & PREFIX_DATA);
15090   oappend (names_mm[modrm.rm]);
15091 }
15092
15093 static void
15094 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15095 {
15096   used_prefixes |= (prefixes & PREFIX_DATA);
15097   oappend (names_mm[modrm.reg]);
15098 }
15099
15100 static void
15101 OP_EX (int bytemode, int sizeflag)
15102 {
15103   int reg;
15104   const char **names;
15105
15106   /* Skip mod/rm byte.  */
15107   MODRM_CHECK;
15108   codep++;
15109
15110   if (modrm.mod != 3)
15111     {
15112       OP_E_memory (bytemode, sizeflag);
15113       return;
15114     }
15115
15116   reg = modrm.rm;
15117   USED_REX (REX_B);
15118   if (rex & REX_B)
15119     reg += 8;
15120   if (vex.evex)
15121     {
15122       USED_REX (REX_X);
15123       if ((rex & REX_X))
15124         reg += 16;
15125     }
15126
15127   if ((sizeflag & SUFFIX_ALWAYS)
15128       && (bytemode == x_swap_mode
15129           || bytemode == d_swap_mode
15130           || bytemode == d_scalar_swap_mode
15131           || bytemode == q_swap_mode
15132           || bytemode == q_scalar_swap_mode))
15133     swap_operand ();
15134
15135   if (need_vex
15136       && bytemode != xmm_mode
15137       && bytemode != xmmdw_mode
15138       && bytemode != xmmqd_mode
15139       && bytemode != xmm_mb_mode
15140       && bytemode != xmm_mw_mode
15141       && bytemode != xmm_md_mode
15142       && bytemode != xmm_mq_mode
15143       && bytemode != xmmq_mode
15144       && bytemode != evex_half_bcst_xmmq_mode
15145       && bytemode != ymm_mode
15146       && bytemode != d_scalar_swap_mode
15147       && bytemode != q_scalar_swap_mode
15148       && bytemode != vex_scalar_w_dq_mode)
15149     {
15150       switch (vex.length)
15151         {
15152         case 128:
15153           names = names_xmm;
15154           break;
15155         case 256:
15156           names = names_ymm;
15157           break;
15158         case 512:
15159           names = names_zmm;
15160           break;
15161         default:
15162           abort ();
15163         }
15164     }
15165   else if (bytemode == xmmq_mode
15166            || bytemode == evex_half_bcst_xmmq_mode)
15167     {
15168       switch (vex.length)
15169         {
15170         case 128:
15171         case 256:
15172           names = names_xmm;
15173           break;
15174         case 512:
15175           names = names_ymm;
15176           break;
15177         default:
15178           abort ();
15179         }
15180     }
15181   else if (bytemode == ymm_mode)
15182     names = names_ymm;
15183   else
15184     names = names_xmm;
15185   oappend (names[reg]);
15186 }
15187
15188 static void
15189 OP_MS (int bytemode, int sizeflag)
15190 {
15191   if (modrm.mod == 3)
15192     OP_EM (bytemode, sizeflag);
15193   else
15194     BadOp ();
15195 }
15196
15197 static void
15198 OP_XS (int bytemode, int sizeflag)
15199 {
15200   if (modrm.mod == 3)
15201     OP_EX (bytemode, sizeflag);
15202   else
15203     BadOp ();
15204 }
15205
15206 static void
15207 OP_M (int bytemode, int sizeflag)
15208 {
15209   if (modrm.mod == 3)
15210     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15211     BadOp ();
15212   else
15213     OP_E (bytemode, sizeflag);
15214 }
15215
15216 static void
15217 OP_0f07 (int bytemode, int sizeflag)
15218 {
15219   if (modrm.mod != 3 || modrm.rm != 0)
15220     BadOp ();
15221   else
15222     OP_E (bytemode, sizeflag);
15223 }
15224
15225 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15226    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15227
15228 static void
15229 NOP_Fixup1 (int bytemode, int sizeflag)
15230 {
15231   if ((prefixes & PREFIX_DATA) != 0
15232       || (rex != 0
15233           && rex != 0x48
15234           && address_mode == mode_64bit))
15235     OP_REG (bytemode, sizeflag);
15236   else
15237     strcpy (obuf, "nop");
15238 }
15239
15240 static void
15241 NOP_Fixup2 (int bytemode, int sizeflag)
15242 {
15243   if ((prefixes & PREFIX_DATA) != 0
15244       || (rex != 0
15245           && rex != 0x48
15246           && address_mode == mode_64bit))
15247     OP_IMREG (bytemode, sizeflag);
15248 }
15249
15250 static const char *const Suffix3DNow[] = {
15251 /* 00 */        NULL,           NULL,           NULL,           NULL,
15252 /* 04 */        NULL,           NULL,           NULL,           NULL,
15253 /* 08 */        NULL,           NULL,           NULL,           NULL,
15254 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15255 /* 10 */        NULL,           NULL,           NULL,           NULL,
15256 /* 14 */        NULL,           NULL,           NULL,           NULL,
15257 /* 18 */        NULL,           NULL,           NULL,           NULL,
15258 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15259 /* 20 */        NULL,           NULL,           NULL,           NULL,
15260 /* 24 */        NULL,           NULL,           NULL,           NULL,
15261 /* 28 */        NULL,           NULL,           NULL,           NULL,
15262 /* 2C */        NULL,           NULL,           NULL,           NULL,
15263 /* 30 */        NULL,           NULL,           NULL,           NULL,
15264 /* 34 */        NULL,           NULL,           NULL,           NULL,
15265 /* 38 */        NULL,           NULL,           NULL,           NULL,
15266 /* 3C */        NULL,           NULL,           NULL,           NULL,
15267 /* 40 */        NULL,           NULL,           NULL,           NULL,
15268 /* 44 */        NULL,           NULL,           NULL,           NULL,
15269 /* 48 */        NULL,           NULL,           NULL,           NULL,
15270 /* 4C */        NULL,           NULL,           NULL,           NULL,
15271 /* 50 */        NULL,           NULL,           NULL,           NULL,
15272 /* 54 */        NULL,           NULL,           NULL,           NULL,
15273 /* 58 */        NULL,           NULL,           NULL,           NULL,
15274 /* 5C */        NULL,           NULL,           NULL,           NULL,
15275 /* 60 */        NULL,           NULL,           NULL,           NULL,
15276 /* 64 */        NULL,           NULL,           NULL,           NULL,
15277 /* 68 */        NULL,           NULL,           NULL,           NULL,
15278 /* 6C */        NULL,           NULL,           NULL,           NULL,
15279 /* 70 */        NULL,           NULL,           NULL,           NULL,
15280 /* 74 */        NULL,           NULL,           NULL,           NULL,
15281 /* 78 */        NULL,           NULL,           NULL,           NULL,
15282 /* 7C */        NULL,           NULL,           NULL,           NULL,
15283 /* 80 */        NULL,           NULL,           NULL,           NULL,
15284 /* 84 */        NULL,           NULL,           NULL,           NULL,
15285 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15286 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15287 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15288 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15289 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15290 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15291 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15292 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15293 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15294 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15295 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15296 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15297 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15298 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15299 /* C0 */        NULL,           NULL,           NULL,           NULL,
15300 /* C4 */        NULL,           NULL,           NULL,           NULL,
15301 /* C8 */        NULL,           NULL,           NULL,           NULL,
15302 /* CC */        NULL,           NULL,           NULL,           NULL,
15303 /* D0 */        NULL,           NULL,           NULL,           NULL,
15304 /* D4 */        NULL,           NULL,           NULL,           NULL,
15305 /* D8 */        NULL,           NULL,           NULL,           NULL,
15306 /* DC */        NULL,           NULL,           NULL,           NULL,
15307 /* E0 */        NULL,           NULL,           NULL,           NULL,
15308 /* E4 */        NULL,           NULL,           NULL,           NULL,
15309 /* E8 */        NULL,           NULL,           NULL,           NULL,
15310 /* EC */        NULL,           NULL,           NULL,           NULL,
15311 /* F0 */        NULL,           NULL,           NULL,           NULL,
15312 /* F4 */        NULL,           NULL,           NULL,           NULL,
15313 /* F8 */        NULL,           NULL,           NULL,           NULL,
15314 /* FC */        NULL,           NULL,           NULL,           NULL,
15315 };
15316
15317 static void
15318 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15319 {
15320   const char *mnemonic;
15321
15322   FETCH_DATA (the_info, codep + 1);
15323   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15324      place where an 8-bit immediate would normally go.  ie. the last
15325      byte of the instruction.  */
15326   obufp = mnemonicendp;
15327   mnemonic = Suffix3DNow[*codep++ & 0xff];
15328   if (mnemonic)
15329     oappend (mnemonic);
15330   else
15331     {
15332       /* Since a variable sized modrm/sib chunk is between the start
15333          of the opcode (0x0f0f) and the opcode suffix, we need to do
15334          all the modrm processing first, and don't know until now that
15335          we have a bad opcode.  This necessitates some cleaning up.  */
15336       op_out[0][0] = '\0';
15337       op_out[1][0] = '\0';
15338       BadOp ();
15339     }
15340   mnemonicendp = obufp;
15341 }
15342
15343 static struct op simd_cmp_op[] =
15344 {
15345   { STRING_COMMA_LEN ("eq") },
15346   { STRING_COMMA_LEN ("lt") },
15347   { STRING_COMMA_LEN ("le") },
15348   { STRING_COMMA_LEN ("unord") },
15349   { STRING_COMMA_LEN ("neq") },
15350   { STRING_COMMA_LEN ("nlt") },
15351   { STRING_COMMA_LEN ("nle") },
15352   { STRING_COMMA_LEN ("ord") }
15353 };
15354
15355 static void
15356 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15357 {
15358   unsigned int cmp_type;
15359
15360   FETCH_DATA (the_info, codep + 1);
15361   cmp_type = *codep++ & 0xff;
15362   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15363     {
15364       char suffix [3];
15365       char *p = mnemonicendp - 2;
15366       suffix[0] = p[0];
15367       suffix[1] = p[1];
15368       suffix[2] = '\0';
15369       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15370       mnemonicendp += simd_cmp_op[cmp_type].len;
15371     }
15372   else
15373     {
15374       /* We have a reserved extension byte.  Output it directly.  */
15375       scratchbuf[0] = '$';
15376       print_operand_value (scratchbuf + 1, 1, cmp_type);
15377       oappend_maybe_intel (scratchbuf);
15378       scratchbuf[0] = '\0';
15379     }
15380 }
15381
15382 static void
15383 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15384 {
15385   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15386   if (!intel_syntax)
15387     {
15388       strcpy (op_out[0], names32[0]);
15389       strcpy (op_out[1], names32[1]);
15390       if (bytemode == eBX_reg)
15391         strcpy (op_out[2], names32[3]);
15392       two_source_ops = 1;
15393     }
15394   /* Skip mod/rm byte.  */
15395   MODRM_CHECK;
15396   codep++;
15397 }
15398
15399 static void
15400 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15401             int sizeflag ATTRIBUTE_UNUSED)
15402 {
15403   /* monitor %{e,r,}ax,%ecx,%edx"  */
15404   if (!intel_syntax)
15405     {
15406       const char **names = (address_mode == mode_64bit
15407                             ? names64 : names32);
15408
15409       if (prefixes & PREFIX_ADDR)
15410         {
15411           /* Remove "addr16/addr32".  */
15412           all_prefixes[last_addr_prefix] = 0;
15413           names = (address_mode != mode_32bit
15414                    ? names32 : names16);
15415           used_prefixes |= PREFIX_ADDR;
15416         }
15417       else if (address_mode == mode_16bit)
15418         names = names16;
15419       strcpy (op_out[0], names[0]);
15420       strcpy (op_out[1], names32[1]);
15421       strcpy (op_out[2], names32[2]);
15422       two_source_ops = 1;
15423     }
15424   /* Skip mod/rm byte.  */
15425   MODRM_CHECK;
15426   codep++;
15427 }
15428
15429 static void
15430 BadOp (void)
15431 {
15432   /* Throw away prefixes and 1st. opcode byte.  */
15433   codep = insn_codep + 1;
15434   oappend ("(bad)");
15435 }
15436
15437 static void
15438 REP_Fixup (int bytemode, int sizeflag)
15439 {
15440   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15441      lods and stos.  */
15442   if (prefixes & PREFIX_REPZ)
15443     all_prefixes[last_repz_prefix] = REP_PREFIX;
15444
15445   switch (bytemode)
15446     {
15447     case al_reg:
15448     case eAX_reg:
15449     case indir_dx_reg:
15450       OP_IMREG (bytemode, sizeflag);
15451       break;
15452     case eDI_reg:
15453       OP_ESreg (bytemode, sizeflag);
15454       break;
15455     case eSI_reg:
15456       OP_DSreg (bytemode, sizeflag);
15457       break;
15458     default:
15459       abort ();
15460       break;
15461     }
15462 }
15463
15464 static void
15465 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15466 {
15467   if ( isa64 != amd64 )
15468     return;
15469
15470   obufp = obuf;
15471   BadOp ();
15472   mnemonicendp = obufp;
15473   ++codep;
15474 }
15475
15476 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15477    "bnd".  */
15478
15479 static void
15480 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15481 {
15482   if (prefixes & PREFIX_REPNZ)
15483     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15484 }
15485
15486 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15487    "notrack".  */
15488
15489 static void
15490 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15491                int sizeflag ATTRIBUTE_UNUSED)
15492 {
15493   if (active_seg_prefix == PREFIX_DS
15494       && (address_mode != mode_64bit || last_data_prefix < 0))
15495     {
15496       /* NOTRACK prefix is only valid on indirect branch instructions.
15497          NB: DATA prefix is unsupported for Intel64.  */
15498       active_seg_prefix = 0;
15499       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15500     }
15501 }
15502
15503 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15504    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15505  */
15506
15507 static void
15508 HLE_Fixup1 (int bytemode, int sizeflag)
15509 {
15510   if (modrm.mod != 3
15511       && (prefixes & PREFIX_LOCK) != 0)
15512     {
15513       if (prefixes & PREFIX_REPZ)
15514         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15515       if (prefixes & PREFIX_REPNZ)
15516         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15517     }
15518
15519   OP_E (bytemode, sizeflag);
15520 }
15521
15522 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15523    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15524  */
15525
15526 static void
15527 HLE_Fixup2 (int bytemode, int sizeflag)
15528 {
15529   if (modrm.mod != 3)
15530     {
15531       if (prefixes & PREFIX_REPZ)
15532         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15533       if (prefixes & PREFIX_REPNZ)
15534         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15535     }
15536
15537   OP_E (bytemode, sizeflag);
15538 }
15539
15540 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15541    "xrelease" for memory operand.  No check for LOCK prefix.   */
15542
15543 static void
15544 HLE_Fixup3 (int bytemode, int sizeflag)
15545 {
15546   if (modrm.mod != 3
15547       && last_repz_prefix > last_repnz_prefix
15548       && (prefixes & PREFIX_REPZ) != 0)
15549     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15550
15551   OP_E (bytemode, sizeflag);
15552 }
15553
15554 static void
15555 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15556 {
15557   USED_REX (REX_W);
15558   if (rex & REX_W)
15559     {
15560       /* Change cmpxchg8b to cmpxchg16b.  */
15561       char *p = mnemonicendp - 2;
15562       mnemonicendp = stpcpy (p, "16b");
15563       bytemode = o_mode;
15564     }
15565   else if ((prefixes & PREFIX_LOCK) != 0)
15566     {
15567       if (prefixes & PREFIX_REPZ)
15568         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15569       if (prefixes & PREFIX_REPNZ)
15570         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15571     }
15572
15573   OP_M (bytemode, sizeflag);
15574 }
15575
15576 static void
15577 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15578 {
15579   const char **names;
15580
15581   if (need_vex)
15582     {
15583       switch (vex.length)
15584         {
15585         case 128:
15586           names = names_xmm;
15587           break;
15588         case 256:
15589           names = names_ymm;
15590           break;
15591         default:
15592           abort ();
15593         }
15594     }
15595   else
15596     names = names_xmm;
15597   oappend (names[reg]);
15598 }
15599
15600 static void
15601 CRC32_Fixup (int bytemode, int sizeflag)
15602 {
15603   /* Add proper suffix to "crc32".  */
15604   char *p = mnemonicendp;
15605
15606   switch (bytemode)
15607     {
15608     case b_mode:
15609       if (intel_syntax)
15610         goto skip;
15611
15612       *p++ = 'b';
15613       break;
15614     case v_mode:
15615       if (intel_syntax)
15616         goto skip;
15617
15618       USED_REX (REX_W);
15619       if (rex & REX_W)
15620         *p++ = 'q';
15621       else
15622         {
15623           if (sizeflag & DFLAG)
15624             *p++ = 'l';
15625           else
15626             *p++ = 'w';
15627           used_prefixes |= (prefixes & PREFIX_DATA);
15628         }
15629       break;
15630     default:
15631       oappend (INTERNAL_DISASSEMBLER_ERROR);
15632       break;
15633     }
15634   mnemonicendp = p;
15635   *p = '\0';
15636
15637  skip:
15638   if (modrm.mod == 3)
15639     {
15640       int add;
15641
15642       /* Skip mod/rm byte.  */
15643       MODRM_CHECK;
15644       codep++;
15645
15646       USED_REX (REX_B);
15647       add = (rex & REX_B) ? 8 : 0;
15648       if (bytemode == b_mode)
15649         {
15650           USED_REX (0);
15651           if (rex)
15652             oappend (names8rex[modrm.rm + add]);
15653           else
15654             oappend (names8[modrm.rm + add]);
15655         }
15656       else
15657         {
15658           USED_REX (REX_W);
15659           if (rex & REX_W)
15660             oappend (names64[modrm.rm + add]);
15661           else if ((prefixes & PREFIX_DATA))
15662             oappend (names16[modrm.rm + add]);
15663           else
15664             oappend (names32[modrm.rm + add]);
15665         }
15666     }
15667   else
15668     OP_E (bytemode, sizeflag);
15669 }
15670
15671 static void
15672 FXSAVE_Fixup (int bytemode, int sizeflag)
15673 {
15674   /* Add proper suffix to "fxsave" and "fxrstor".  */
15675   USED_REX (REX_W);
15676   if (rex & REX_W)
15677     {
15678       char *p = mnemonicendp;
15679       *p++ = '6';
15680       *p++ = '4';
15681       *p = '\0';
15682       mnemonicendp = p;
15683     }
15684   OP_M (bytemode, sizeflag);
15685 }
15686
15687 static void
15688 PCMPESTR_Fixup (int bytemode, int sizeflag)
15689 {
15690   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15691   if (!intel_syntax)
15692     {
15693       char *p = mnemonicendp;
15694
15695       USED_REX (REX_W);
15696       if (rex & REX_W)
15697         *p++ = 'q';
15698       else if (sizeflag & SUFFIX_ALWAYS)
15699         *p++ = 'l';
15700
15701       *p = '\0';
15702       mnemonicendp = p;
15703     }
15704
15705   OP_EX (bytemode, sizeflag);
15706 }
15707
15708 /* Display the destination register operand for instructions with
15709    VEX. */
15710
15711 static void
15712 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15713 {
15714   int reg;
15715   const char **names;
15716
15717   if (!need_vex)
15718     abort ();
15719
15720   if (!need_vex_reg)
15721     return;
15722
15723   reg = vex.register_specifier;
15724   vex.register_specifier = 0;
15725   if (address_mode != mode_64bit)
15726     reg &= 7;
15727   else if (vex.evex && !vex.v)
15728     reg += 16;
15729
15730   if (bytemode == vex_scalar_mode)
15731     {
15732       oappend (names_xmm[reg]);
15733       return;
15734     }
15735
15736   switch (vex.length)
15737     {
15738     case 128:
15739       switch (bytemode)
15740         {
15741         case vex_mode:
15742         case vex128_mode:
15743         case vex_vsib_q_w_dq_mode:
15744         case vex_vsib_q_w_d_mode:
15745           names = names_xmm;
15746           break;
15747         case dq_mode:
15748           if (rex & REX_W)
15749             names = names64;
15750           else
15751             names = names32;
15752           break;
15753         case mask_bd_mode:
15754         case mask_mode:
15755           if (reg > 0x7)
15756             {
15757               oappend ("(bad)");
15758               return;
15759             }
15760           names = names_mask;
15761           break;
15762         default:
15763           abort ();
15764           return;
15765         }
15766       break;
15767     case 256:
15768       switch (bytemode)
15769         {
15770         case vex_mode:
15771         case vex256_mode:
15772           names = names_ymm;
15773           break;
15774         case vex_vsib_q_w_dq_mode:
15775         case vex_vsib_q_w_d_mode:
15776           names = vex.w ? names_ymm : names_xmm;
15777           break;
15778         case mask_bd_mode:
15779         case mask_mode:
15780           if (reg > 0x7)
15781             {
15782               oappend ("(bad)");
15783               return;
15784             }
15785           names = names_mask;
15786           break;
15787         default:
15788           /* See PR binutils/20893 for a reproducer.  */
15789           oappend ("(bad)");
15790           return;
15791         }
15792       break;
15793     case 512:
15794       names = names_zmm;
15795       break;
15796     default:
15797       abort ();
15798       break;
15799     }
15800   oappend (names[reg]);
15801 }
15802
15803 static void
15804 OP_VexW (int bytemode, int sizeflag)
15805 {
15806   OP_VEX (bytemode, sizeflag);
15807
15808   if (vex.w)
15809     {
15810       /* Swap 2nd and 3rd operands.  */
15811       strcpy (scratchbuf, op_out[2]);
15812       strcpy (op_out[2], op_out[1]);
15813       strcpy (op_out[1], scratchbuf);
15814     }
15815 }
15816
15817 static void
15818 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15819 {
15820   int reg;
15821   const char **names = names_xmm;
15822
15823   FETCH_DATA (the_info, codep + 1);
15824   reg = *codep++;
15825
15826   if (bytemode != x_mode && bytemode != scalar_mode)
15827     abort ();
15828
15829   reg >>= 4;
15830   if (address_mode != mode_64bit)
15831     reg &= 7;
15832
15833   if (bytemode == x_mode && vex.length == 256)
15834     names = names_ymm;
15835
15836   oappend (names[reg]);
15837
15838   if (vex.w)
15839     {
15840       /* Swap 3rd and 4th operands.  */
15841       strcpy (scratchbuf, op_out[3]);
15842       strcpy (op_out[3], op_out[2]);
15843       strcpy (op_out[2], scratchbuf);
15844     }
15845 }
15846
15847 static void
15848 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
15849           int sizeflag ATTRIBUTE_UNUSED)
15850 {
15851   scratchbuf[0] = '$';
15852   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
15853   oappend_maybe_intel (scratchbuf);
15854 }
15855
15856 static void
15857 OP_EX_Vex (int bytemode, int sizeflag)
15858 {
15859   if (modrm.mod != 3)
15860     need_vex_reg = 0;
15861   OP_EX (bytemode, sizeflag);
15862 }
15863
15864 static void
15865 OP_XMM_Vex (int bytemode, int sizeflag)
15866 {
15867   if (modrm.mod != 3)
15868     need_vex_reg = 0;
15869   OP_XMM (bytemode, sizeflag);
15870 }
15871
15872 static struct op vex_cmp_op[] =
15873 {
15874   { STRING_COMMA_LEN ("eq") },
15875   { STRING_COMMA_LEN ("lt") },
15876   { STRING_COMMA_LEN ("le") },
15877   { STRING_COMMA_LEN ("unord") },
15878   { STRING_COMMA_LEN ("neq") },
15879   { STRING_COMMA_LEN ("nlt") },
15880   { STRING_COMMA_LEN ("nle") },
15881   { STRING_COMMA_LEN ("ord") },
15882   { STRING_COMMA_LEN ("eq_uq") },
15883   { STRING_COMMA_LEN ("nge") },
15884   { STRING_COMMA_LEN ("ngt") },
15885   { STRING_COMMA_LEN ("false") },
15886   { STRING_COMMA_LEN ("neq_oq") },
15887   { STRING_COMMA_LEN ("ge") },
15888   { STRING_COMMA_LEN ("gt") },
15889   { STRING_COMMA_LEN ("true") },
15890   { STRING_COMMA_LEN ("eq_os") },
15891   { STRING_COMMA_LEN ("lt_oq") },
15892   { STRING_COMMA_LEN ("le_oq") },
15893   { STRING_COMMA_LEN ("unord_s") },
15894   { STRING_COMMA_LEN ("neq_us") },
15895   { STRING_COMMA_LEN ("nlt_uq") },
15896   { STRING_COMMA_LEN ("nle_uq") },
15897   { STRING_COMMA_LEN ("ord_s") },
15898   { STRING_COMMA_LEN ("eq_us") },
15899   { STRING_COMMA_LEN ("nge_uq") },
15900   { STRING_COMMA_LEN ("ngt_uq") },
15901   { STRING_COMMA_LEN ("false_os") },
15902   { STRING_COMMA_LEN ("neq_os") },
15903   { STRING_COMMA_LEN ("ge_oq") },
15904   { STRING_COMMA_LEN ("gt_oq") },
15905   { STRING_COMMA_LEN ("true_us") },
15906 };
15907
15908 static void
15909 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15910 {
15911   unsigned int cmp_type;
15912
15913   FETCH_DATA (the_info, codep + 1);
15914   cmp_type = *codep++ & 0xff;
15915   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15916     {
15917       char suffix [3];
15918       char *p = mnemonicendp - 2;
15919       suffix[0] = p[0];
15920       suffix[1] = p[1];
15921       suffix[2] = '\0';
15922       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15923       mnemonicendp += vex_cmp_op[cmp_type].len;
15924     }
15925   else
15926     {
15927       /* We have a reserved extension byte.  Output it directly.  */
15928       scratchbuf[0] = '$';
15929       print_operand_value (scratchbuf + 1, 1, cmp_type);
15930       oappend_maybe_intel (scratchbuf);
15931       scratchbuf[0] = '\0';
15932     }
15933 }
15934
15935 static void
15936 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
15937              int sizeflag ATTRIBUTE_UNUSED)
15938 {
15939   unsigned int cmp_type;
15940
15941   if (!vex.evex)
15942     abort ();
15943
15944   FETCH_DATA (the_info, codep + 1);
15945   cmp_type = *codep++ & 0xff;
15946   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
15947      If it's the case, print suffix, otherwise - print the immediate.  */
15948   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
15949       && cmp_type != 3
15950       && cmp_type != 7)
15951     {
15952       char suffix [3];
15953       char *p = mnemonicendp - 2;
15954
15955       /* vpcmp* can have both one- and two-lettered suffix.  */
15956       if (p[0] == 'p')
15957         {
15958           p++;
15959           suffix[0] = p[0];
15960           suffix[1] = '\0';
15961         }
15962       else
15963         {
15964           suffix[0] = p[0];
15965           suffix[1] = p[1];
15966           suffix[2] = '\0';
15967         }
15968
15969       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15970       mnemonicendp += simd_cmp_op[cmp_type].len;
15971     }
15972   else
15973     {
15974       /* We have a reserved extension byte.  Output it directly.  */
15975       scratchbuf[0] = '$';
15976       print_operand_value (scratchbuf + 1, 1, cmp_type);
15977       oappend_maybe_intel (scratchbuf);
15978       scratchbuf[0] = '\0';
15979     }
15980 }
15981
15982 static const struct op xop_cmp_op[] =
15983 {
15984   { STRING_COMMA_LEN ("lt") },
15985   { STRING_COMMA_LEN ("le") },
15986   { STRING_COMMA_LEN ("gt") },
15987   { STRING_COMMA_LEN ("ge") },
15988   { STRING_COMMA_LEN ("eq") },
15989   { STRING_COMMA_LEN ("neq") },
15990   { STRING_COMMA_LEN ("false") },
15991   { STRING_COMMA_LEN ("true") }
15992 };
15993
15994 static void
15995 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
15996              int sizeflag ATTRIBUTE_UNUSED)
15997 {
15998   unsigned int cmp_type;
15999
16000   FETCH_DATA (the_info, codep + 1);
16001   cmp_type = *codep++ & 0xff;
16002   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16003     {
16004       char suffix[3];
16005       char *p = mnemonicendp - 2;
16006
16007       /* vpcom* can have both one- and two-lettered suffix.  */
16008       if (p[0] == 'm')
16009         {
16010           p++;
16011           suffix[0] = p[0];
16012           suffix[1] = '\0';
16013         }
16014       else
16015         {
16016           suffix[0] = p[0];
16017           suffix[1] = p[1];
16018           suffix[2] = '\0';
16019         }
16020
16021       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16022       mnemonicendp += xop_cmp_op[cmp_type].len;
16023     }
16024   else
16025     {
16026       /* We have a reserved extension byte.  Output it directly.  */
16027       scratchbuf[0] = '$';
16028       print_operand_value (scratchbuf + 1, 1, cmp_type);
16029       oappend_maybe_intel (scratchbuf);
16030       scratchbuf[0] = '\0';
16031     }
16032 }
16033
16034 static const struct op pclmul_op[] =
16035 {
16036   { STRING_COMMA_LEN ("lql") },
16037   { STRING_COMMA_LEN ("hql") },
16038   { STRING_COMMA_LEN ("lqh") },
16039   { STRING_COMMA_LEN ("hqh") }
16040 };
16041
16042 static void
16043 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16044               int sizeflag ATTRIBUTE_UNUSED)
16045 {
16046   unsigned int pclmul_type;
16047
16048   FETCH_DATA (the_info, codep + 1);
16049   pclmul_type = *codep++ & 0xff;
16050   switch (pclmul_type)
16051     {
16052     case 0x10:
16053       pclmul_type = 2;
16054       break;
16055     case 0x11:
16056       pclmul_type = 3;
16057       break;
16058     default:
16059       break;
16060     }
16061   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16062     {
16063       char suffix [4];
16064       char *p = mnemonicendp - 3;
16065       suffix[0] = p[0];
16066       suffix[1] = p[1];
16067       suffix[2] = p[2];
16068       suffix[3] = '\0';
16069       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16070       mnemonicendp += pclmul_op[pclmul_type].len;
16071     }
16072   else
16073     {
16074       /* We have a reserved extension byte.  Output it directly.  */
16075       scratchbuf[0] = '$';
16076       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16077       oappend_maybe_intel (scratchbuf);
16078       scratchbuf[0] = '\0';
16079     }
16080 }
16081
16082 static void
16083 MOVBE_Fixup (int bytemode, int sizeflag)
16084 {
16085   /* Add proper suffix to "movbe".  */
16086   char *p = mnemonicendp;
16087
16088   switch (bytemode)
16089     {
16090     case v_mode:
16091       if (intel_syntax)
16092         goto skip;
16093
16094       USED_REX (REX_W);
16095       if (sizeflag & SUFFIX_ALWAYS)
16096         {
16097           if (rex & REX_W)
16098             *p++ = 'q';
16099           else
16100             {
16101               if (sizeflag & DFLAG)
16102                 *p++ = 'l';
16103               else
16104                 *p++ = 'w';
16105               used_prefixes |= (prefixes & PREFIX_DATA);
16106             }
16107         }
16108       break;
16109     default:
16110       oappend (INTERNAL_DISASSEMBLER_ERROR);
16111       break;
16112     }
16113   mnemonicendp = p;
16114   *p = '\0';
16115
16116  skip:
16117   OP_M (bytemode, sizeflag);
16118 }
16119
16120 static void
16121 MOVSXD_Fixup (int bytemode, int sizeflag)
16122 {
16123   /* Add proper suffix to "movsxd".  */
16124   char *p = mnemonicendp;
16125
16126   switch (bytemode)
16127     {
16128     case movsxd_mode:
16129       if (intel_syntax)
16130         {
16131           *p++ = 'x';
16132           *p++ = 'd';
16133           goto skip;
16134         }
16135
16136       USED_REX (REX_W);
16137       if (rex & REX_W)
16138         {
16139           *p++ = 'l';
16140           *p++ = 'q';
16141         }
16142       else
16143         {
16144           *p++ = 'x';
16145           *p++ = 'd';
16146         }
16147       break;
16148     default:
16149       oappend (INTERNAL_DISASSEMBLER_ERROR);
16150       break;
16151     }
16152
16153  skip:
16154   mnemonicendp = p;
16155   *p = '\0';
16156   OP_E (bytemode, sizeflag);
16157 }
16158
16159 static void
16160 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16161 {
16162   int reg;
16163   const char **names;
16164
16165   /* Skip mod/rm byte.  */
16166   MODRM_CHECK;
16167   codep++;
16168
16169   if (rex & REX_W)
16170     names = names64;
16171   else
16172     names = names32;
16173
16174   reg = modrm.rm;
16175   USED_REX (REX_B);
16176   if (rex & REX_B)
16177     reg += 8;
16178
16179   oappend (names[reg]);
16180 }
16181
16182 static void
16183 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16184 {
16185   const char **names;
16186   unsigned int reg = vex.register_specifier;
16187   vex.register_specifier = 0;
16188
16189   if (rex & REX_W)
16190     names = names64;
16191   else
16192     names = names32;
16193
16194   if (address_mode != mode_64bit)
16195     reg &= 7;
16196   oappend (names[reg]);
16197 }
16198
16199 static void
16200 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16201 {
16202   if (!vex.evex
16203       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16204     abort ();
16205
16206   USED_REX (REX_R);
16207   if ((rex & REX_R) != 0 || !vex.r)
16208     {
16209       BadOp ();
16210       return;
16211     }
16212
16213   oappend (names_mask [modrm.reg]);
16214 }
16215
16216 static void
16217 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16218 {
16219   if (modrm.mod == 3 && vex.b)
16220     switch (bytemode)
16221       {
16222       case evex_rounding_64_mode:
16223         if (address_mode != mode_64bit)
16224           {
16225             oappend ("(bad)");
16226             break;
16227           }
16228         /* Fall through.  */
16229       case evex_rounding_mode:
16230         oappend (names_rounding[vex.ll]);
16231         break;
16232       case evex_sae_mode:
16233         oappend ("{sae}");
16234         break;
16235       default:
16236         abort ();
16237         break;
16238       }
16239 }