opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127 static void MOVSXD_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Eva { OP_E, va_mode }
 254 #define Ev_bnd { OP_E, v_bnd_mode }
 255 #define EvS { OP_E, v_swap_mode }
 256 #define Ed { OP_E, d_mode }
 257 #define Edq { OP_E, dq_mode }
 258 #define Edqw { OP_E, dqw_mode }
 259 #define Edqb { OP_E, dqb_mode }
 260 #define Edb { OP_E, db_mode }
 261 #define Edw { OP_E, dw_mode }
 262 #define Edqd { OP_E, dqd_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iv64 { OP_I64, v_mode }
 296 #define Id { OP_I, d_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Jdqw { OP_J, dqw_mode }
 302 #define Cm { OP_C, m_mode }
 303 #define Dm { OP_D, m_mode }
 304 #define Td { OP_T, d_mode }
 305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 306
 307 #define RMeAX { OP_REG, eAX_reg }
 308 #define RMeBX { OP_REG, eBX_reg }
 309 #define RMeCX { OP_REG, eCX_reg }
 310 #define RMeDX { OP_REG, eDX_reg }
 311 #define RMeSP { OP_REG, eSP_reg }
 312 #define RMeBP { OP_REG, eBP_reg }
 313 #define RMeSI { OP_REG, eSI_reg }
 314 #define RMeDI { OP_REG, eDI_reg }
 315 #define RMrAX { OP_REG, rAX_reg }
 316 #define RMrBX { OP_REG, rBX_reg }
 317 #define RMrCX { OP_REG, rCX_reg }
 318 #define RMrDX { OP_REG, rDX_reg }
 319 #define RMrSP { OP_REG, rSP_reg }
 320 #define RMrBP { OP_REG, rBP_reg }
 321 #define RMrSI { OP_REG, rSI_reg }
 322 #define RMrDI { OP_REG, rDI_reg }
 323 #define RMAL { OP_REG, al_reg }
 324 #define RMCL { OP_REG, cl_reg }
 325 #define RMDL { OP_REG, dl_reg }
 326 #define RMBL { OP_REG, bl_reg }
 327 #define RMAH { OP_REG, ah_reg }
 328 #define RMCH { OP_REG, ch_reg }
 329 #define RMDH { OP_REG, dh_reg }
 330 #define RMBH { OP_REG, bh_reg }
 331 #define RMAX { OP_REG, ax_reg }
 332 #define RMDX { OP_REG, dx_reg }
 333
 334 #define eAX { OP_IMREG, eAX_reg }
 335 #define eBX { OP_IMREG, eBX_reg }
 336 #define eCX { OP_IMREG, eCX_reg }
 337 #define eDX { OP_IMREG, eDX_reg }
 338 #define eSP { OP_IMREG, eSP_reg }
 339 #define eBP { OP_IMREG, eBP_reg }
 340 #define eSI { OP_IMREG, eSI_reg }
 341 #define eDI { OP_IMREG, eDI_reg }
 342 #define AL { OP_IMREG, al_reg }
 343 #define CL { OP_IMREG, cl_reg }
 344 #define DL { OP_IMREG, dl_reg }
 345 #define BL { OP_IMREG, bl_reg }
 346 #define AH { OP_IMREG, ah_reg }
 347 #define CH { OP_IMREG, ch_reg }
 348 #define DH { OP_IMREG, dh_reg }
 349 #define BH { OP_IMREG, bh_reg }
 350 #define AX { OP_IMREG, ax_reg }
 351 #define DX { OP_IMREG, dx_reg }
 352 #define zAX { OP_IMREG, z_mode_ax_reg }
 353 #define indirDX { OP_IMREG, indir_dx_reg }
 354
 355 #define Sw { OP_SEG, w_mode }
 356 #define Sv { OP_SEG, v_mode }
 357 #define Ap { OP_DIR, 0 }
 358 #define Ob { OP_OFF64, b_mode }
 359 #define Ov { OP_OFF64, v_mode }
 360 #define Xb { OP_DSreg, eSI_reg }
 361 #define Xv { OP_DSreg, eSI_reg }
 362 #define Xz { OP_DSreg, eSI_reg }
 363 #define Yb { OP_ESreg, eDI_reg }
 364 #define Yv { OP_ESreg, eDI_reg }
 365 #define DSBX { OP_DSreg, eBX_reg }
 366
 367 #define es { OP_REG, es_reg }
 368 #define ss { OP_REG, ss_reg }
 369 #define cs { OP_REG, cs_reg }
 370 #define ds { OP_REG, ds_reg }
 371 #define fs { OP_REG, fs_reg }
 372 #define gs { OP_REG, gs_reg }
 373
 374 #define MX { OP_MMX, 0 }
 375 #define XM { OP_XMM, 0 }
 376 #define XMScalar { OP_XMM, scalar_mode }
 377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 378 #define XMM { OP_XMM, xmm_mode }
 379 #define XMxmmq { OP_XMM, xmmq_mode }
 380 #define EM { OP_EM, v_mode }
 381 #define EMS { OP_EM, v_swap_mode }
 382 #define EMd { OP_EM, d_mode }
 383 #define EMx { OP_EM, x_mode }
 384 #define EXbScalar { OP_EX, b_scalar_mode }
 385 #define EXw { OP_EX, w_mode }
 386 #define EXwScalar { OP_EX, w_scalar_mode }
 387 #define EXd { OP_EX, d_mode }
 388 #define EXdScalar { OP_EX, d_scalar_mode }
 389 #define EXdS { OP_EX, d_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmmdw { OP_EX, xmmdw_mode }
 405 #define EXxmmqd { OP_EX, xmmqd_mode }
 406 #define EXymmq { OP_EX, ymmq_mode }
 407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 410 #define MS { OP_MS, v_mode }
 411 #define XS { OP_XS, v_mode }
 412 #define EMCq { OP_EMC, q_mode }
 413 #define MXC { OP_MXC, 0 }
 414 #define OPSUF { OP_3DNowSuffix, 0 }
 415 #define SEP { SEP_Fixup, 0 }
 416 #define CMP { CMP_Fixup, 0 }
 417 #define XMM0 { XMM_Fixup, 0 }
 418 #define FXSAVE { FXSAVE_Fixup, 0 }
 419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 421
 422 #define Vex { OP_VEX, vex_mode }
 423 #define VexScalar { OP_VEX, vex_scalar_mode }
 424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 425 #define Vex128 { OP_VEX, vex128_mode }
 426 #define Vex256 { OP_VEX, vex256_mode }
 427 #define VexGdq { OP_VEX, dq_mode }
 428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 430 #define EXVexW { OP_EX_VexW, x_mode }
 431 #define EXdVexW { OP_EX_VexW, d_mode }
 432 #define EXqVexW { OP_EX_VexW, q_mode }
 433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440 #define VPCOM { VPCOM_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 445
 446 #define XMask { OP_Mask, mask_mode }
 447 #define MaskG { OP_G, mask_mode }
 448 #define MaskE { OP_E, mask_mode }
 449 #define MaskBDE { OP_E, mask_bd_mode }
 450 #define MaskR { OP_R, mask_mode }
 451 #define MaskVex { OP_VEX, mask_mode }
 452
 453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 457
 458 /* Used handle "rep" prefix for string instructions.  */
 459 #define Xbr { REP_Fixup, eSI_reg }
 460 #define Xvr { REP_Fixup, eSI_reg }
 461 #define Ybr { REP_Fixup, eDI_reg }
 462 #define Yvr { REP_Fixup, eDI_reg }
 463 #define Yzr { REP_Fixup, eDI_reg }
 464 #define indirDXr { REP_Fixup, indir_dx_reg }
 465 #define ALr { REP_Fixup, al_reg }
 466 #define eAXr { REP_Fixup, eAX_reg }
 467
 468 /* Used handle HLE prefix for lockable instructions.  */
 469 #define Ebh1 { HLE_Fixup1, b_mode }
 470 #define Evh1 { HLE_Fixup1, v_mode }
 471 #define Ebh2 { HLE_Fixup2, b_mode }
 472 #define Evh2 { HLE_Fixup2, v_mode }
 473 #define Ebh3 { HLE_Fixup3, b_mode }
 474 #define Evh3 { HLE_Fixup3, v_mode }
 475
 476 #define BND { BND_Fixup, 0 }
 477 #define NOTRACK { NOTRACK_Fixup, 0 }
 478
 479 #define cond_jump_flag { NULL, cond_jump_mode }
 480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 481
 482 /* bits in sizeflag */
 483 #define SUFFIX_ALWAYS 4
 484 #define AFLAG 2
 485 #define DFLAG 1
 486
 487 enum
 488 {
 489   /* byte operand */
 490   b_mode = 1,
 491   /* byte operand with operand swapped */
 492   b_swap_mode,
 493   /* byte operand, sign extend like 'T' suffix */
 494   b_T_mode,
 495   /* operand size depends on prefixes */
 496   v_mode,
 497   /* operand size depends on prefixes with operand swapped */
 498   v_swap_mode,
 499   /* operand size depends on address prefix */
 500   va_mode,
 501   /* word operand */
 502   w_mode,
 503   /* double word operand  */
 504   d_mode,
 505   /* double word operand with operand swapped */
 506   d_swap_mode,
 507   /* quad word operand */
 508   q_mode,
 509   /* quad word operand with operand swapped */
 510   q_swap_mode,
 511   /* ten-byte operand */
 512   t_mode,
 513   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 514      broadcast enabled.  */
 515   x_mode,
 516   /* Similar to x_mode, but with different EVEX mem shifts.  */
 517   evex_x_gscat_mode,
 518   /* Similar to x_mode, but with disabled broadcast.  */
 519   evex_x_nobcst_mode,
 520   /* Similar to x_mode, but with operands swapped and disabled broadcast
 521      in EVEX.  */
 522   x_swap_mode,
 523   /* 16-byte XMM operand */
 524   xmm_mode,
 525   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 526      memory operand (depending on vector length).  Broadcast isn't
 527      allowed.  */
 528   xmmq_mode,
 529   /* Same as xmmq_mode, but broadcast is allowed.  */
 530   evex_half_bcst_xmmq_mode,
 531   /* XMM register or byte memory operand */
 532   xmm_mb_mode,
 533   /* XMM register or word memory operand */
 534   xmm_mw_mode,
 535   /* XMM register or double word memory operand */
 536   xmm_md_mode,
 537   /* XMM register or quad word memory operand */
 538   xmm_mq_mode,
 539   /* 16-byte XMM, word, double word or quad word operand.  */
 540   xmmdw_mode,
 541   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 542   xmmqd_mode,
 543   /* 32-byte YMM operand */
 544   ymm_mode,
 545   /* quad word, ymmword or zmmword memory operand.  */
 546   ymmq_mode,
 547   /* 32-byte YMM or 16-byte word operand */
 548   ymmxmm_mode,
 549   /* d_mode in 32bit, q_mode in 64bit mode.  */
 550   m_mode,
 551   /* pair of v_mode operands */
 552   a_mode,
 553   cond_jump_mode,
 554   loop_jcxz_mode,
 555   movsxd_mode,
 556   v_bnd_mode,
 557   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 558   v_bndmk_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode, displacements like
 562      v_mode without considering Intel64 ISA.  */
 563   dqw_mode,
 564   /* bounds operand */
 565   bnd_mode,
 566   /* bounds operand with operand swapped */
 567   bnd_swap_mode,
 568   /* 4- or 6-byte pointer operand */
 569   f_mode,
 570   const_1_mode,
 571   /* v_mode for indirect branch opcodes.  */
 572   indir_v_mode,
 573   /* v_mode for stack-related opcodes.  */
 574   stack_v_mode,
 575   /* non-quad operand size depends on prefixes */
 576   z_mode,
 577   /* 16-byte operand */
 578   o_mode,
 579   /* registers like dq_mode, memory like b_mode.  */
 580   dqb_mode,
 581   /* registers like d_mode, memory like b_mode.  */
 582   db_mode,
 583   /* registers like d_mode, memory like w_mode.  */
 584   dw_mode,
 585   /* registers like dq_mode, memory like d_mode.  */
 586   dqd_mode,
 587   /* normal vex mode */
 588   vex_mode,
 589   /* 128bit vex mode */
 590   vex128_mode,
 591   /* 256bit vex mode */
 592   vex256_mode,
 593
 594   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 595   vex_vsib_d_w_dq_mode,
 596   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 597   vex_vsib_d_w_d_mode,
 598   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 599   vex_vsib_q_w_dq_mode,
 600   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 601   vex_vsib_q_w_d_mode,
 602
 603   /* scalar, ignore vector length.  */
 604   scalar_mode,
 605   /* like b_mode, ignore vector length.  */
 606   b_scalar_mode,
 607   /* like w_mode, ignore vector length.  */
 608   w_scalar_mode,
 609   /* like d_mode, ignore vector length.  */
 610   d_scalar_mode,
 611   /* like d_swap_mode, ignore vector length.  */
 612   d_scalar_swap_mode,
 613   /* like q_mode, ignore vector length.  */
 614   q_scalar_mode,
 615   /* like q_swap_mode, ignore vector length.  */
 616   q_scalar_swap_mode,
 617   /* like vex_mode, ignore vector length.  */
 618   vex_scalar_mode,
 619   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 620   vex_scalar_w_dq_mode,
 621
 622   /* Static rounding.  */
 623   evex_rounding_mode,
 624   /* Static rounding, 64-bit mode only.  */
 625   evex_rounding_64_mode,
 626   /* Supress all exceptions.  */
 627   evex_sae_mode,
 628
 629   /* Mask register operand.  */
 630   mask_mode,
 631   /* Mask register operand.  */
 632   mask_bd_mode,
 633
 634   es_reg,
 635   cs_reg,
 636   ss_reg,
 637   ds_reg,
 638   fs_reg,
 639   gs_reg,
 640
 641   eAX_reg,
 642   eCX_reg,
 643   eDX_reg,
 644   eBX_reg,
 645   eSP_reg,
 646   eBP_reg,
 647   eSI_reg,
 648   eDI_reg,
 649
 650   al_reg,
 651   cl_reg,
 652   dl_reg,
 653   bl_reg,
 654   ah_reg,
 655   ch_reg,
 656   dh_reg,
 657   bh_reg,
 658
 659   ax_reg,
 660   cx_reg,
 661   dx_reg,
 662   bx_reg,
 663   sp_reg,
 664   bp_reg,
 665   si_reg,
 666   di_reg,
 667
 668   rAX_reg,
 669   rCX_reg,
 670   rDX_reg,
 671   rBX_reg,
 672   rSP_reg,
 673   rBP_reg,
 674   rSI_reg,
 675   rDI_reg,
 676
 677   z_mode_ax_reg,
 678   indir_dx_reg
 679 };
 680
 681 enum
 682 {
 683   FLOATCODE = 1,
 684   USE_REG_TABLE,
 685   USE_MOD_TABLE,
 686   USE_RM_TABLE,
 687   USE_PREFIX_TABLE,
 688   USE_X86_64_TABLE,
 689   USE_3BYTE_TABLE,
 690   USE_XOP_8F_TABLE,
 691   USE_VEX_C4_TABLE,
 692   USE_VEX_C5_TABLE,
 693   USE_VEX_LEN_TABLE,
 694   USE_VEX_W_TABLE,
 695   USE_EVEX_TABLE,
 696   USE_EVEX_LEN_TABLE
 697 };
 698
 699 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 700
 701 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 702 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 703 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 704 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 705 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 706 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 707 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 708 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 709 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 710 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 711 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 712 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 713 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 714 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 715 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 716 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 717
 718 enum
 719 {
 720   REG_80 = 0,
 721   REG_81,
 722   REG_83,
 723   REG_8F,
 724   REG_C0,
 725   REG_C1,
 726   REG_C6,
 727   REG_C7,
 728   REG_D0,
 729   REG_D1,
 730   REG_D2,
 731   REG_D3,
 732   REG_F6,
 733   REG_F7,
 734   REG_FE,
 735   REG_FF,
 736   REG_0F00,
 737   REG_0F01,
 738   REG_0F0D,
 739   REG_0F18,
 740   REG_0F1C_P_0_MOD_0,
 741   REG_0F1E_P_1_MOD_3,
 742   REG_0F71,
 743   REG_0F72,
 744   REG_0F73,
 745   REG_0FA6,
 746   REG_0FA7,
 747   REG_0FAE,
 748   REG_0FBA,
 749   REG_0FC7,
 750   REG_VEX_0F71,
 751   REG_VEX_0F72,
 752   REG_VEX_0F73,
 753   REG_VEX_0FAE,
 754   REG_VEX_0F38F3,
 755   REG_XOP_LWPCB,
 756   REG_XOP_LWP,
 757   REG_XOP_TBM_01,
 758   REG_XOP_TBM_02,
 759
 760   REG_EVEX_0F71,
 761   REG_EVEX_0F72,
 762   REG_EVEX_0F73,
 763   REG_EVEX_0F38C6,
 764   REG_EVEX_0F38C7
 765 };
 766
 767 enum
 768 {
 769   MOD_8D = 0,
 770   MOD_C6_REG_7,
 771   MOD_C7_REG_7,
 772   MOD_FF_REG_3,
 773   MOD_FF_REG_5,
 774   MOD_0F01_REG_0,
 775   MOD_0F01_REG_1,
 776   MOD_0F01_REG_2,
 777   MOD_0F01_REG_3,
 778   MOD_0F01_REG_5,
 779   MOD_0F01_REG_7,
 780   MOD_0F12_PREFIX_0,
 781   MOD_0F13,
 782   MOD_0F16_PREFIX_0,
 783   MOD_0F17,
 784   MOD_0F18_REG_0,
 785   MOD_0F18_REG_1,
 786   MOD_0F18_REG_2,
 787   MOD_0F18_REG_3,
 788   MOD_0F18_REG_4,
 789   MOD_0F18_REG_5,
 790   MOD_0F18_REG_6,
 791   MOD_0F18_REG_7,
 792   MOD_0F1A_PREFIX_0,
 793   MOD_0F1B_PREFIX_0,
 794   MOD_0F1B_PREFIX_1,
 795   MOD_0F1C_PREFIX_0,
 796   MOD_0F1E_PREFIX_1,
 797   MOD_0F24,
 798   MOD_0F26,
 799   MOD_0F2B_PREFIX_0,
 800   MOD_0F2B_PREFIX_1,
 801   MOD_0F2B_PREFIX_2,
 802   MOD_0F2B_PREFIX_3,
 803   MOD_0F51,
 804   MOD_0F71_REG_2,
 805   MOD_0F71_REG_4,
 806   MOD_0F71_REG_6,
 807   MOD_0F72_REG_2,
 808   MOD_0F72_REG_4,
 809   MOD_0F72_REG_6,
 810   MOD_0F73_REG_2,
 811   MOD_0F73_REG_3,
 812   MOD_0F73_REG_6,
 813   MOD_0F73_REG_7,
 814   MOD_0FAE_REG_0,
 815   MOD_0FAE_REG_1,
 816   MOD_0FAE_REG_2,
 817   MOD_0FAE_REG_3,
 818   MOD_0FAE_REG_4,
 819   MOD_0FAE_REG_5,
 820   MOD_0FAE_REG_6,
 821   MOD_0FAE_REG_7,
 822   MOD_0FB2,
 823   MOD_0FB4,
 824   MOD_0FB5,
 825   MOD_0FC3,
 826   MOD_0FC7_REG_3,
 827   MOD_0FC7_REG_4,
 828   MOD_0FC7_REG_5,
 829   MOD_0FC7_REG_6,
 830   MOD_0FC7_REG_7,
 831   MOD_0FD7,
 832   MOD_0FE7_PREFIX_2,
 833   MOD_0FF0_PREFIX_3,
 834   MOD_0F382A_PREFIX_2,
 835   MOD_0F38F5_PREFIX_2,
 836   MOD_0F38F6_PREFIX_0,
 837   MOD_0F38F8_PREFIX_1,
 838   MOD_0F38F8_PREFIX_2,
 839   MOD_0F38F8_PREFIX_3,
 840   MOD_0F38F9_PREFIX_0,
 841   MOD_62_32BIT,
 842   MOD_C4_32BIT,
 843   MOD_C5_32BIT,
 844   MOD_VEX_0F12_PREFIX_0,
 845   MOD_VEX_0F13,
 846   MOD_VEX_0F16_PREFIX_0,
 847   MOD_VEX_0F17,
 848   MOD_VEX_0F2B,
 849   MOD_VEX_W_0_0F41_P_0_LEN_1,
 850   MOD_VEX_W_1_0F41_P_0_LEN_1,
 851   MOD_VEX_W_0_0F41_P_2_LEN_1,
 852   MOD_VEX_W_1_0F41_P_2_LEN_1,
 853   MOD_VEX_W_0_0F42_P_0_LEN_1,
 854   MOD_VEX_W_1_0F42_P_0_LEN_1,
 855   MOD_VEX_W_0_0F42_P_2_LEN_1,
 856   MOD_VEX_W_1_0F42_P_2_LEN_1,
 857   MOD_VEX_W_0_0F44_P_0_LEN_1,
 858   MOD_VEX_W_1_0F44_P_0_LEN_1,
 859   MOD_VEX_W_0_0F44_P_2_LEN_1,
 860   MOD_VEX_W_1_0F44_P_2_LEN_1,
 861   MOD_VEX_W_0_0F45_P_0_LEN_1,
 862   MOD_VEX_W_1_0F45_P_0_LEN_1,
 863   MOD_VEX_W_0_0F45_P_2_LEN_1,
 864   MOD_VEX_W_1_0F45_P_2_LEN_1,
 865   MOD_VEX_W_0_0F46_P_0_LEN_1,
 866   MOD_VEX_W_1_0F46_P_0_LEN_1,
 867   MOD_VEX_W_0_0F46_P_2_LEN_1,
 868   MOD_VEX_W_1_0F46_P_2_LEN_1,
 869   MOD_VEX_W_0_0F47_P_0_LEN_1,
 870   MOD_VEX_W_1_0F47_P_0_LEN_1,
 871   MOD_VEX_W_0_0F47_P_2_LEN_1,
 872   MOD_VEX_W_1_0F47_P_2_LEN_1,
 873   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 874   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 875   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 876   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 877   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 878   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 879   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 880   MOD_VEX_0F50,
 881   MOD_VEX_0F71_REG_2,
 882   MOD_VEX_0F71_REG_4,
 883   MOD_VEX_0F71_REG_6,
 884   MOD_VEX_0F72_REG_2,
 885   MOD_VEX_0F72_REG_4,
 886   MOD_VEX_0F72_REG_6,
 887   MOD_VEX_0F73_REG_2,
 888   MOD_VEX_0F73_REG_3,
 889   MOD_VEX_0F73_REG_6,
 890   MOD_VEX_0F73_REG_7,
 891   MOD_VEX_W_0_0F91_P_0_LEN_0,
 892   MOD_VEX_W_1_0F91_P_0_LEN_0,
 893   MOD_VEX_W_0_0F91_P_2_LEN_0,
 894   MOD_VEX_W_1_0F91_P_2_LEN_0,
 895   MOD_VEX_W_0_0F92_P_0_LEN_0,
 896   MOD_VEX_W_0_0F92_P_2_LEN_0,
 897   MOD_VEX_0F92_P_3_LEN_0,
 898   MOD_VEX_W_0_0F93_P_0_LEN_0,
 899   MOD_VEX_W_0_0F93_P_2_LEN_0,
 900   MOD_VEX_0F93_P_3_LEN_0,
 901   MOD_VEX_W_0_0F98_P_0_LEN_0,
 902   MOD_VEX_W_1_0F98_P_0_LEN_0,
 903   MOD_VEX_W_0_0F98_P_2_LEN_0,
 904   MOD_VEX_W_1_0F98_P_2_LEN_0,
 905   MOD_VEX_W_0_0F99_P_0_LEN_0,
 906   MOD_VEX_W_1_0F99_P_0_LEN_0,
 907   MOD_VEX_W_0_0F99_P_2_LEN_0,
 908   MOD_VEX_W_1_0F99_P_2_LEN_0,
 909   MOD_VEX_0FAE_REG_2,
 910   MOD_VEX_0FAE_REG_3,
 911   MOD_VEX_0FD7_PREFIX_2,
 912   MOD_VEX_0FE7_PREFIX_2,
 913   MOD_VEX_0FF0_PREFIX_3,
 914   MOD_VEX_0F381A_PREFIX_2,
 915   MOD_VEX_0F382A_PREFIX_2,
 916   MOD_VEX_0F382C_PREFIX_2,
 917   MOD_VEX_0F382D_PREFIX_2,
 918   MOD_VEX_0F382E_PREFIX_2,
 919   MOD_VEX_0F382F_PREFIX_2,
 920   MOD_VEX_0F385A_PREFIX_2,
 921   MOD_VEX_0F388C_PREFIX_2,
 922   MOD_VEX_0F388E_PREFIX_2,
 923   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 925   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 927   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 928   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 929   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 930   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 931
 932   MOD_EVEX_0F12_PREFIX_0,
 933   MOD_EVEX_0F16_PREFIX_0,
 934   MOD_EVEX_0F38C6_REG_1,
 935   MOD_EVEX_0F38C6_REG_2,
 936   MOD_EVEX_0F38C6_REG_5,
 937   MOD_EVEX_0F38C6_REG_6,
 938   MOD_EVEX_0F38C7_REG_1,
 939   MOD_EVEX_0F38C7_REG_2,
 940   MOD_EVEX_0F38C7_REG_5,
 941   MOD_EVEX_0F38C7_REG_6
 942 };
 943
 944 enum
 945 {
 946   RM_C6_REG_7 = 0,
 947   RM_C7_REG_7,
 948   RM_0F01_REG_0,
 949   RM_0F01_REG_1,
 950   RM_0F01_REG_2,
 951   RM_0F01_REG_3,
 952   RM_0F01_REG_5_MOD_3,
 953   RM_0F01_REG_7_MOD_3,
 954   RM_0F1E_P_1_MOD_3_REG_7,
 955   RM_0FAE_REG_6_MOD_3_P_0,
 956   RM_0FAE_REG_7_MOD_3,
 957 };
 958
 959 enum
 960 {
 961   PREFIX_90 = 0,
 962   PREFIX_0F01_REG_3_RM_1,
 963   PREFIX_0F01_REG_5_MOD_0,
 964   PREFIX_0F01_REG_5_MOD_3_RM_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_2,
 966   PREFIX_0F01_REG_7_MOD_3_RM_2,
 967   PREFIX_0F01_REG_7_MOD_3_RM_3,
 968   PREFIX_0F09,
 969   PREFIX_0F10,
 970   PREFIX_0F11,
 971   PREFIX_0F12,
 972   PREFIX_0F16,
 973   PREFIX_0F1A,
 974   PREFIX_0F1B,
 975   PREFIX_0F1C,
 976   PREFIX_0F1E,
 977   PREFIX_0F2A,
 978   PREFIX_0F2B,
 979   PREFIX_0F2C,
 980   PREFIX_0F2D,
 981   PREFIX_0F2E,
 982   PREFIX_0F2F,
 983   PREFIX_0F51,
 984   PREFIX_0F52,
 985   PREFIX_0F53,
 986   PREFIX_0F58,
 987   PREFIX_0F59,
 988   PREFIX_0F5A,
 989   PREFIX_0F5B,
 990   PREFIX_0F5C,
 991   PREFIX_0F5D,
 992   PREFIX_0F5E,
 993   PREFIX_0F5F,
 994   PREFIX_0F60,
 995   PREFIX_0F61,
 996   PREFIX_0F62,
 997   PREFIX_0F6C,
 998   PREFIX_0F6D,
 999   PREFIX_0F6F,
1000   PREFIX_0F70,
1001   PREFIX_0F73_REG_3,
1002   PREFIX_0F73_REG_7,
1003   PREFIX_0F78,
1004   PREFIX_0F79,
1005   PREFIX_0F7C,
1006   PREFIX_0F7D,
1007   PREFIX_0F7E,
1008   PREFIX_0F7F,
1009   PREFIX_0FAE_REG_0_MOD_3,
1010   PREFIX_0FAE_REG_1_MOD_3,
1011   PREFIX_0FAE_REG_2_MOD_3,
1012   PREFIX_0FAE_REG_3_MOD_3,
1013   PREFIX_0FAE_REG_4_MOD_0,
1014   PREFIX_0FAE_REG_4_MOD_3,
1015   PREFIX_0FAE_REG_5_MOD_0,
1016   PREFIX_0FAE_REG_5_MOD_3,
1017   PREFIX_0FAE_REG_6_MOD_0,
1018   PREFIX_0FAE_REG_6_MOD_3,
1019   PREFIX_0FAE_REG_7_MOD_0,
1020   PREFIX_0FB8,
1021   PREFIX_0FBC,
1022   PREFIX_0FBD,
1023   PREFIX_0FC2,
1024   PREFIX_0FC3_MOD_0,
1025   PREFIX_0FC7_REG_6_MOD_0,
1026   PREFIX_0FC7_REG_6_MOD_3,
1027   PREFIX_0FC7_REG_7_MOD_3,
1028   PREFIX_0FD0,
1029   PREFIX_0FD6,
1030   PREFIX_0FE6,
1031   PREFIX_0FE7,
1032   PREFIX_0FF0,
1033   PREFIX_0FF7,
1034   PREFIX_0F3810,
1035   PREFIX_0F3814,
1036   PREFIX_0F3815,
1037   PREFIX_0F3817,
1038   PREFIX_0F3820,
1039   PREFIX_0F3821,
1040   PREFIX_0F3822,
1041   PREFIX_0F3823,
1042   PREFIX_0F3824,
1043   PREFIX_0F3825,
1044   PREFIX_0F3828,
1045   PREFIX_0F3829,
1046   PREFIX_0F382A,
1047   PREFIX_0F382B,
1048   PREFIX_0F3830,
1049   PREFIX_0F3831,
1050   PREFIX_0F3832,
1051   PREFIX_0F3833,
1052   PREFIX_0F3834,
1053   PREFIX_0F3835,
1054   PREFIX_0F3837,
1055   PREFIX_0F3838,
1056   PREFIX_0F3839,
1057   PREFIX_0F383A,
1058   PREFIX_0F383B,
1059   PREFIX_0F383C,
1060   PREFIX_0F383D,
1061   PREFIX_0F383E,
1062   PREFIX_0F383F,
1063   PREFIX_0F3840,
1064   PREFIX_0F3841,
1065   PREFIX_0F3880,
1066   PREFIX_0F3881,
1067   PREFIX_0F3882,
1068   PREFIX_0F38C8,
1069   PREFIX_0F38C9,
1070   PREFIX_0F38CA,
1071   PREFIX_0F38CB,
1072   PREFIX_0F38CC,
1073   PREFIX_0F38CD,
1074   PREFIX_0F38CF,
1075   PREFIX_0F38DB,
1076   PREFIX_0F38DC,
1077   PREFIX_0F38DD,
1078   PREFIX_0F38DE,
1079   PREFIX_0F38DF,
1080   PREFIX_0F38F0,
1081   PREFIX_0F38F1,
1082   PREFIX_0F38F5,
1083   PREFIX_0F38F6,
1084   PREFIX_0F38F8,
1085   PREFIX_0F38F9,
1086   PREFIX_0F3A08,
1087   PREFIX_0F3A09,
1088   PREFIX_0F3A0A,
1089   PREFIX_0F3A0B,
1090   PREFIX_0F3A0C,
1091   PREFIX_0F3A0D,
1092   PREFIX_0F3A0E,
1093   PREFIX_0F3A14,
1094   PREFIX_0F3A15,
1095   PREFIX_0F3A16,
1096   PREFIX_0F3A17,
1097   PREFIX_0F3A20,
1098   PREFIX_0F3A21,
1099   PREFIX_0F3A22,
1100   PREFIX_0F3A40,
1101   PREFIX_0F3A41,
1102   PREFIX_0F3A42,
1103   PREFIX_0F3A44,
1104   PREFIX_0F3A60,
1105   PREFIX_0F3A61,
1106   PREFIX_0F3A62,
1107   PREFIX_0F3A63,
1108   PREFIX_0F3ACC,
1109   PREFIX_0F3ACE,
1110   PREFIX_0F3ACF,
1111   PREFIX_0F3ADF,
1112   PREFIX_VEX_0F10,
1113   PREFIX_VEX_0F11,
1114   PREFIX_VEX_0F12,
1115   PREFIX_VEX_0F16,
1116   PREFIX_VEX_0F2A,
1117   PREFIX_VEX_0F2C,
1118   PREFIX_VEX_0F2D,
1119   PREFIX_VEX_0F2E,
1120   PREFIX_VEX_0F2F,
1121   PREFIX_VEX_0F41,
1122   PREFIX_VEX_0F42,
1123   PREFIX_VEX_0F44,
1124   PREFIX_VEX_0F45,
1125   PREFIX_VEX_0F46,
1126   PREFIX_VEX_0F47,
1127   PREFIX_VEX_0F4A,
1128   PREFIX_VEX_0F4B,
1129   PREFIX_VEX_0F51,
1130   PREFIX_VEX_0F52,
1131   PREFIX_VEX_0F53,
1132   PREFIX_VEX_0F58,
1133   PREFIX_VEX_0F59,
1134   PREFIX_VEX_0F5A,
1135   PREFIX_VEX_0F5B,
1136   PREFIX_VEX_0F5C,
1137   PREFIX_VEX_0F5D,
1138   PREFIX_VEX_0F5E,
1139   PREFIX_VEX_0F5F,
1140   PREFIX_VEX_0F60,
1141   PREFIX_VEX_0F61,
1142   PREFIX_VEX_0F62,
1143   PREFIX_VEX_0F63,
1144   PREFIX_VEX_0F64,
1145   PREFIX_VEX_0F65,
1146   PREFIX_VEX_0F66,
1147   PREFIX_VEX_0F67,
1148   PREFIX_VEX_0F68,
1149   PREFIX_VEX_0F69,
1150   PREFIX_VEX_0F6A,
1151   PREFIX_VEX_0F6B,
1152   PREFIX_VEX_0F6C,
1153   PREFIX_VEX_0F6D,
1154   PREFIX_VEX_0F6E,
1155   PREFIX_VEX_0F6F,
1156   PREFIX_VEX_0F70,
1157   PREFIX_VEX_0F71_REG_2,
1158   PREFIX_VEX_0F71_REG_4,
1159   PREFIX_VEX_0F71_REG_6,
1160   PREFIX_VEX_0F72_REG_2,
1161   PREFIX_VEX_0F72_REG_4,
1162   PREFIX_VEX_0F72_REG_6,
1163   PREFIX_VEX_0F73_REG_2,
1164   PREFIX_VEX_0F73_REG_3,
1165   PREFIX_VEX_0F73_REG_6,
1166   PREFIX_VEX_0F73_REG_7,
1167   PREFIX_VEX_0F74,
1168   PREFIX_VEX_0F75,
1169   PREFIX_VEX_0F76,
1170   PREFIX_VEX_0F77,
1171   PREFIX_VEX_0F7C,
1172   PREFIX_VEX_0F7D,
1173   PREFIX_VEX_0F7E,
1174   PREFIX_VEX_0F7F,
1175   PREFIX_VEX_0F90,
1176   PREFIX_VEX_0F91,
1177   PREFIX_VEX_0F92,
1178   PREFIX_VEX_0F93,
1179   PREFIX_VEX_0F98,
1180   PREFIX_VEX_0F99,
1181   PREFIX_VEX_0FC2,
1182   PREFIX_VEX_0FC4,
1183   PREFIX_VEX_0FC5,
1184   PREFIX_VEX_0FD0,
1185   PREFIX_VEX_0FD1,
1186   PREFIX_VEX_0FD2,
1187   PREFIX_VEX_0FD3,
1188   PREFIX_VEX_0FD4,
1189   PREFIX_VEX_0FD5,
1190   PREFIX_VEX_0FD6,
1191   PREFIX_VEX_0FD7,
1192   PREFIX_VEX_0FD8,
1193   PREFIX_VEX_0FD9,
1194   PREFIX_VEX_0FDA,
1195   PREFIX_VEX_0FDB,
1196   PREFIX_VEX_0FDC,
1197   PREFIX_VEX_0FDD,
1198   PREFIX_VEX_0FDE,
1199   PREFIX_VEX_0FDF,
1200   PREFIX_VEX_0FE0,
1201   PREFIX_VEX_0FE1,
1202   PREFIX_VEX_0FE2,
1203   PREFIX_VEX_0FE3,
1204   PREFIX_VEX_0FE4,
1205   PREFIX_VEX_0FE5,
1206   PREFIX_VEX_0FE6,
1207   PREFIX_VEX_0FE7,
1208   PREFIX_VEX_0FE8,
1209   PREFIX_VEX_0FE9,
1210   PREFIX_VEX_0FEA,
1211   PREFIX_VEX_0FEB,
1212   PREFIX_VEX_0FEC,
1213   PREFIX_VEX_0FED,
1214   PREFIX_VEX_0FEE,
1215   PREFIX_VEX_0FEF,
1216   PREFIX_VEX_0FF0,
1217   PREFIX_VEX_0FF1,
1218   PREFIX_VEX_0FF2,
1219   PREFIX_VEX_0FF3,
1220   PREFIX_VEX_0FF4,
1221   PREFIX_VEX_0FF5,
1222   PREFIX_VEX_0FF6,
1223   PREFIX_VEX_0FF7,
1224   PREFIX_VEX_0FF8,
1225   PREFIX_VEX_0FF9,
1226   PREFIX_VEX_0FFA,
1227   PREFIX_VEX_0FFB,
1228   PREFIX_VEX_0FFC,
1229   PREFIX_VEX_0FFD,
1230   PREFIX_VEX_0FFE,
1231   PREFIX_VEX_0F3800,
1232   PREFIX_VEX_0F3801,
1233   PREFIX_VEX_0F3802,
1234   PREFIX_VEX_0F3803,
1235   PREFIX_VEX_0F3804,
1236   PREFIX_VEX_0F3805,
1237   PREFIX_VEX_0F3806,
1238   PREFIX_VEX_0F3807,
1239   PREFIX_VEX_0F3808,
1240   PREFIX_VEX_0F3809,
1241   PREFIX_VEX_0F380A,
1242   PREFIX_VEX_0F380B,
1243   PREFIX_VEX_0F380C,
1244   PREFIX_VEX_0F380D,
1245   PREFIX_VEX_0F380E,
1246   PREFIX_VEX_0F380F,
1247   PREFIX_VEX_0F3813,
1248   PREFIX_VEX_0F3816,
1249   PREFIX_VEX_0F3817,
1250   PREFIX_VEX_0F3818,
1251   PREFIX_VEX_0F3819,
1252   PREFIX_VEX_0F381A,
1253   PREFIX_VEX_0F381C,
1254   PREFIX_VEX_0F381D,
1255   PREFIX_VEX_0F381E,
1256   PREFIX_VEX_0F3820,
1257   PREFIX_VEX_0F3821,
1258   PREFIX_VEX_0F3822,
1259   PREFIX_VEX_0F3823,
1260   PREFIX_VEX_0F3824,
1261   PREFIX_VEX_0F3825,
1262   PREFIX_VEX_0F3828,
1263   PREFIX_VEX_0F3829,
1264   PREFIX_VEX_0F382A,
1265   PREFIX_VEX_0F382B,
1266   PREFIX_VEX_0F382C,
1267   PREFIX_VEX_0F382D,
1268   PREFIX_VEX_0F382E,
1269   PREFIX_VEX_0F382F,
1270   PREFIX_VEX_0F3830,
1271   PREFIX_VEX_0F3831,
1272   PREFIX_VEX_0F3832,
1273   PREFIX_VEX_0F3833,
1274   PREFIX_VEX_0F3834,
1275   PREFIX_VEX_0F3835,
1276   PREFIX_VEX_0F3836,
1277   PREFIX_VEX_0F3837,
1278   PREFIX_VEX_0F3838,
1279   PREFIX_VEX_0F3839,
1280   PREFIX_VEX_0F383A,
1281   PREFIX_VEX_0F383B,
1282   PREFIX_VEX_0F383C,
1283   PREFIX_VEX_0F383D,
1284   PREFIX_VEX_0F383E,
1285   PREFIX_VEX_0F383F,
1286   PREFIX_VEX_0F3840,
1287   PREFIX_VEX_0F3841,
1288   PREFIX_VEX_0F3845,
1289   PREFIX_VEX_0F3846,
1290   PREFIX_VEX_0F3847,
1291   PREFIX_VEX_0F3858,
1292   PREFIX_VEX_0F3859,
1293   PREFIX_VEX_0F385A,
1294   PREFIX_VEX_0F3878,
1295   PREFIX_VEX_0F3879,
1296   PREFIX_VEX_0F388C,
1297   PREFIX_VEX_0F388E,
1298   PREFIX_VEX_0F3890,
1299   PREFIX_VEX_0F3891,
1300   PREFIX_VEX_0F3892,
1301   PREFIX_VEX_0F3893,
1302   PREFIX_VEX_0F3896,
1303   PREFIX_VEX_0F3897,
1304   PREFIX_VEX_0F3898,
1305   PREFIX_VEX_0F3899,
1306   PREFIX_VEX_0F389A,
1307   PREFIX_VEX_0F389B,
1308   PREFIX_VEX_0F389C,
1309   PREFIX_VEX_0F389D,
1310   PREFIX_VEX_0F389E,
1311   PREFIX_VEX_0F389F,
1312   PREFIX_VEX_0F38A6,
1313   PREFIX_VEX_0F38A7,
1314   PREFIX_VEX_0F38A8,
1315   PREFIX_VEX_0F38A9,
1316   PREFIX_VEX_0F38AA,
1317   PREFIX_VEX_0F38AB,
1318   PREFIX_VEX_0F38AC,
1319   PREFIX_VEX_0F38AD,
1320   PREFIX_VEX_0F38AE,
1321   PREFIX_VEX_0F38AF,
1322   PREFIX_VEX_0F38B6,
1323   PREFIX_VEX_0F38B7,
1324   PREFIX_VEX_0F38B8,
1325   PREFIX_VEX_0F38B9,
1326   PREFIX_VEX_0F38BA,
1327   PREFIX_VEX_0F38BB,
1328   PREFIX_VEX_0F38BC,
1329   PREFIX_VEX_0F38BD,
1330   PREFIX_VEX_0F38BE,
1331   PREFIX_VEX_0F38BF,
1332   PREFIX_VEX_0F38CF,
1333   PREFIX_VEX_0F38DB,
1334   PREFIX_VEX_0F38DC,
1335   PREFIX_VEX_0F38DD,
1336   PREFIX_VEX_0F38DE,
1337   PREFIX_VEX_0F38DF,
1338   PREFIX_VEX_0F38F2,
1339   PREFIX_VEX_0F38F3_REG_1,
1340   PREFIX_VEX_0F38F3_REG_2,
1341   PREFIX_VEX_0F38F3_REG_3,
1342   PREFIX_VEX_0F38F5,
1343   PREFIX_VEX_0F38F6,
1344   PREFIX_VEX_0F38F7,
1345   PREFIX_VEX_0F3A00,
1346   PREFIX_VEX_0F3A01,
1347   PREFIX_VEX_0F3A02,
1348   PREFIX_VEX_0F3A04,
1349   PREFIX_VEX_0F3A05,
1350   PREFIX_VEX_0F3A06,
1351   PREFIX_VEX_0F3A08,
1352   PREFIX_VEX_0F3A09,
1353   PREFIX_VEX_0F3A0A,
1354   PREFIX_VEX_0F3A0B,
1355   PREFIX_VEX_0F3A0C,
1356   PREFIX_VEX_0F3A0D,
1357   PREFIX_VEX_0F3A0E,
1358   PREFIX_VEX_0F3A0F,
1359   PREFIX_VEX_0F3A14,
1360   PREFIX_VEX_0F3A15,
1361   PREFIX_VEX_0F3A16,
1362   PREFIX_VEX_0F3A17,
1363   PREFIX_VEX_0F3A18,
1364   PREFIX_VEX_0F3A19,
1365   PREFIX_VEX_0F3A1D,
1366   PREFIX_VEX_0F3A20,
1367   PREFIX_VEX_0F3A21,
1368   PREFIX_VEX_0F3A22,
1369   PREFIX_VEX_0F3A30,
1370   PREFIX_VEX_0F3A31,
1371   PREFIX_VEX_0F3A32,
1372   PREFIX_VEX_0F3A33,
1373   PREFIX_VEX_0F3A38,
1374   PREFIX_VEX_0F3A39,
1375   PREFIX_VEX_0F3A40,
1376   PREFIX_VEX_0F3A41,
1377   PREFIX_VEX_0F3A42,
1378   PREFIX_VEX_0F3A44,
1379   PREFIX_VEX_0F3A46,
1380   PREFIX_VEX_0F3A48,
1381   PREFIX_VEX_0F3A49,
1382   PREFIX_VEX_0F3A4A,
1383   PREFIX_VEX_0F3A4B,
1384   PREFIX_VEX_0F3A4C,
1385   PREFIX_VEX_0F3A5C,
1386   PREFIX_VEX_0F3A5D,
1387   PREFIX_VEX_0F3A5E,
1388   PREFIX_VEX_0F3A5F,
1389   PREFIX_VEX_0F3A60,
1390   PREFIX_VEX_0F3A61,
1391   PREFIX_VEX_0F3A62,
1392   PREFIX_VEX_0F3A63,
1393   PREFIX_VEX_0F3A68,
1394   PREFIX_VEX_0F3A69,
1395   PREFIX_VEX_0F3A6A,
1396   PREFIX_VEX_0F3A6B,
1397   PREFIX_VEX_0F3A6C,
1398   PREFIX_VEX_0F3A6D,
1399   PREFIX_VEX_0F3A6E,
1400   PREFIX_VEX_0F3A6F,
1401   PREFIX_VEX_0F3A78,
1402   PREFIX_VEX_0F3A79,
1403   PREFIX_VEX_0F3A7A,
1404   PREFIX_VEX_0F3A7B,
1405   PREFIX_VEX_0F3A7C,
1406   PREFIX_VEX_0F3A7D,
1407   PREFIX_VEX_0F3A7E,
1408   PREFIX_VEX_0F3A7F,
1409   PREFIX_VEX_0F3ACE,
1410   PREFIX_VEX_0F3ACF,
1411   PREFIX_VEX_0F3ADF,
1412   PREFIX_VEX_0F3AF0,
1413
1414   PREFIX_EVEX_0F10,
1415   PREFIX_EVEX_0F11,
1416   PREFIX_EVEX_0F12,
1417   PREFIX_EVEX_0F13,
1418   PREFIX_EVEX_0F14,
1419   PREFIX_EVEX_0F15,
1420   PREFIX_EVEX_0F16,
1421   PREFIX_EVEX_0F17,
1422   PREFIX_EVEX_0F28,
1423   PREFIX_EVEX_0F29,
1424   PREFIX_EVEX_0F2A,
1425   PREFIX_EVEX_0F2B,
1426   PREFIX_EVEX_0F2C,
1427   PREFIX_EVEX_0F2D,
1428   PREFIX_EVEX_0F2E,
1429   PREFIX_EVEX_0F2F,
1430   PREFIX_EVEX_0F51,
1431   PREFIX_EVEX_0F54,
1432   PREFIX_EVEX_0F55,
1433   PREFIX_EVEX_0F56,
1434   PREFIX_EVEX_0F57,
1435   PREFIX_EVEX_0F58,
1436   PREFIX_EVEX_0F59,
1437   PREFIX_EVEX_0F5A,
1438   PREFIX_EVEX_0F5B,
1439   PREFIX_EVEX_0F5C,
1440   PREFIX_EVEX_0F5D,
1441   PREFIX_EVEX_0F5E,
1442   PREFIX_EVEX_0F5F,
1443   PREFIX_EVEX_0F60,
1444   PREFIX_EVEX_0F61,
1445   PREFIX_EVEX_0F62,
1446   PREFIX_EVEX_0F63,
1447   PREFIX_EVEX_0F64,
1448   PREFIX_EVEX_0F65,
1449   PREFIX_EVEX_0F66,
1450   PREFIX_EVEX_0F67,
1451   PREFIX_EVEX_0F68,
1452   PREFIX_EVEX_0F69,
1453   PREFIX_EVEX_0F6A,
1454   PREFIX_EVEX_0F6B,
1455   PREFIX_EVEX_0F6C,
1456   PREFIX_EVEX_0F6D,
1457   PREFIX_EVEX_0F6E,
1458   PREFIX_EVEX_0F6F,
1459   PREFIX_EVEX_0F70,
1460   PREFIX_EVEX_0F71_REG_2,
1461   PREFIX_EVEX_0F71_REG_4,
1462   PREFIX_EVEX_0F71_REG_6,
1463   PREFIX_EVEX_0F72_REG_0,
1464   PREFIX_EVEX_0F72_REG_1,
1465   PREFIX_EVEX_0F72_REG_2,
1466   PREFIX_EVEX_0F72_REG_4,
1467   PREFIX_EVEX_0F72_REG_6,
1468   PREFIX_EVEX_0F73_REG_2,
1469   PREFIX_EVEX_0F73_REG_3,
1470   PREFIX_EVEX_0F73_REG_6,
1471   PREFIX_EVEX_0F73_REG_7,
1472   PREFIX_EVEX_0F74,
1473   PREFIX_EVEX_0F75,
1474   PREFIX_EVEX_0F76,
1475   PREFIX_EVEX_0F78,
1476   PREFIX_EVEX_0F79,
1477   PREFIX_EVEX_0F7A,
1478   PREFIX_EVEX_0F7B,
1479   PREFIX_EVEX_0F7E,
1480   PREFIX_EVEX_0F7F,
1481   PREFIX_EVEX_0FC2,
1482   PREFIX_EVEX_0FC4,
1483   PREFIX_EVEX_0FC5,
1484   PREFIX_EVEX_0FC6,
1485   PREFIX_EVEX_0FD1,
1486   PREFIX_EVEX_0FD2,
1487   PREFIX_EVEX_0FD3,
1488   PREFIX_EVEX_0FD4,
1489   PREFIX_EVEX_0FD5,
1490   PREFIX_EVEX_0FD6,
1491   PREFIX_EVEX_0FD8,
1492   PREFIX_EVEX_0FD9,
1493   PREFIX_EVEX_0FDA,
1494   PREFIX_EVEX_0FDB,
1495   PREFIX_EVEX_0FDC,
1496   PREFIX_EVEX_0FDD,
1497   PREFIX_EVEX_0FDE,
1498   PREFIX_EVEX_0FDF,
1499   PREFIX_EVEX_0FE0,
1500   PREFIX_EVEX_0FE1,
1501   PREFIX_EVEX_0FE2,
1502   PREFIX_EVEX_0FE3,
1503   PREFIX_EVEX_0FE4,
1504   PREFIX_EVEX_0FE5,
1505   PREFIX_EVEX_0FE6,
1506   PREFIX_EVEX_0FE7,
1507   PREFIX_EVEX_0FE8,
1508   PREFIX_EVEX_0FE9,
1509   PREFIX_EVEX_0FEA,
1510   PREFIX_EVEX_0FEB,
1511   PREFIX_EVEX_0FEC,
1512   PREFIX_EVEX_0FED,
1513   PREFIX_EVEX_0FEE,
1514   PREFIX_EVEX_0FEF,
1515   PREFIX_EVEX_0FF1,
1516   PREFIX_EVEX_0FF2,
1517   PREFIX_EVEX_0FF3,
1518   PREFIX_EVEX_0FF4,
1519   PREFIX_EVEX_0FF5,
1520   PREFIX_EVEX_0FF6,
1521   PREFIX_EVEX_0FF8,
1522   PREFIX_EVEX_0FF9,
1523   PREFIX_EVEX_0FFA,
1524   PREFIX_EVEX_0FFB,
1525   PREFIX_EVEX_0FFC,
1526   PREFIX_EVEX_0FFD,
1527   PREFIX_EVEX_0FFE,
1528   PREFIX_EVEX_0F3800,
1529   PREFIX_EVEX_0F3804,
1530   PREFIX_EVEX_0F380B,
1531   PREFIX_EVEX_0F380C,
1532   PREFIX_EVEX_0F380D,
1533   PREFIX_EVEX_0F3810,
1534   PREFIX_EVEX_0F3811,
1535   PREFIX_EVEX_0F3812,
1536   PREFIX_EVEX_0F3813,
1537   PREFIX_EVEX_0F3814,
1538   PREFIX_EVEX_0F3815,
1539   PREFIX_EVEX_0F3816,
1540   PREFIX_EVEX_0F3818,
1541   PREFIX_EVEX_0F3819,
1542   PREFIX_EVEX_0F381A,
1543   PREFIX_EVEX_0F381B,
1544   PREFIX_EVEX_0F381C,
1545   PREFIX_EVEX_0F381D,
1546   PREFIX_EVEX_0F381E,
1547   PREFIX_EVEX_0F381F,
1548   PREFIX_EVEX_0F3820,
1549   PREFIX_EVEX_0F3821,
1550   PREFIX_EVEX_0F3822,
1551   PREFIX_EVEX_0F3823,
1552   PREFIX_EVEX_0F3824,
1553   PREFIX_EVEX_0F3825,
1554   PREFIX_EVEX_0F3826,
1555   PREFIX_EVEX_0F3827,
1556   PREFIX_EVEX_0F3828,
1557   PREFIX_EVEX_0F3829,
1558   PREFIX_EVEX_0F382A,
1559   PREFIX_EVEX_0F382B,
1560   PREFIX_EVEX_0F382C,
1561   PREFIX_EVEX_0F382D,
1562   PREFIX_EVEX_0F3830,
1563   PREFIX_EVEX_0F3831,
1564   PREFIX_EVEX_0F3832,
1565   PREFIX_EVEX_0F3833,
1566   PREFIX_EVEX_0F3834,
1567   PREFIX_EVEX_0F3835,
1568   PREFIX_EVEX_0F3836,
1569   PREFIX_EVEX_0F3837,
1570   PREFIX_EVEX_0F3838,
1571   PREFIX_EVEX_0F3839,
1572   PREFIX_EVEX_0F383A,
1573   PREFIX_EVEX_0F383B,
1574   PREFIX_EVEX_0F383C,
1575   PREFIX_EVEX_0F383D,
1576   PREFIX_EVEX_0F383E,
1577   PREFIX_EVEX_0F383F,
1578   PREFIX_EVEX_0F3840,
1579   PREFIX_EVEX_0F3842,
1580   PREFIX_EVEX_0F3843,
1581   PREFIX_EVEX_0F3844,
1582   PREFIX_EVEX_0F3845,
1583   PREFIX_EVEX_0F3846,
1584   PREFIX_EVEX_0F3847,
1585   PREFIX_EVEX_0F384C,
1586   PREFIX_EVEX_0F384D,
1587   PREFIX_EVEX_0F384E,
1588   PREFIX_EVEX_0F384F,
1589   PREFIX_EVEX_0F3850,
1590   PREFIX_EVEX_0F3851,
1591   PREFIX_EVEX_0F3852,
1592   PREFIX_EVEX_0F3853,
1593   PREFIX_EVEX_0F3854,
1594   PREFIX_EVEX_0F3855,
1595   PREFIX_EVEX_0F3858,
1596   PREFIX_EVEX_0F3859,
1597   PREFIX_EVEX_0F385A,
1598   PREFIX_EVEX_0F385B,
1599   PREFIX_EVEX_0F3862,
1600   PREFIX_EVEX_0F3863,
1601   PREFIX_EVEX_0F3864,
1602   PREFIX_EVEX_0F3865,
1603   PREFIX_EVEX_0F3866,
1604   PREFIX_EVEX_0F3868,
1605   PREFIX_EVEX_0F3870,
1606   PREFIX_EVEX_0F3871,
1607   PREFIX_EVEX_0F3872,
1608   PREFIX_EVEX_0F3873,
1609   PREFIX_EVEX_0F3875,
1610   PREFIX_EVEX_0F3876,
1611   PREFIX_EVEX_0F3877,
1612   PREFIX_EVEX_0F3878,
1613   PREFIX_EVEX_0F3879,
1614   PREFIX_EVEX_0F387A,
1615   PREFIX_EVEX_0F387B,
1616   PREFIX_EVEX_0F387C,
1617   PREFIX_EVEX_0F387D,
1618   PREFIX_EVEX_0F387E,
1619   PREFIX_EVEX_0F387F,
1620   PREFIX_EVEX_0F3883,
1621   PREFIX_EVEX_0F3888,
1622   PREFIX_EVEX_0F3889,
1623   PREFIX_EVEX_0F388A,
1624   PREFIX_EVEX_0F388B,
1625   PREFIX_EVEX_0F388D,
1626   PREFIX_EVEX_0F388F,
1627   PREFIX_EVEX_0F3890,
1628   PREFIX_EVEX_0F3891,
1629   PREFIX_EVEX_0F3892,
1630   PREFIX_EVEX_0F3893,
1631   PREFIX_EVEX_0F3896,
1632   PREFIX_EVEX_0F3897,
1633   PREFIX_EVEX_0F3898,
1634   PREFIX_EVEX_0F3899,
1635   PREFIX_EVEX_0F389A,
1636   PREFIX_EVEX_0F389B,
1637   PREFIX_EVEX_0F389C,
1638   PREFIX_EVEX_0F389D,
1639   PREFIX_EVEX_0F389E,
1640   PREFIX_EVEX_0F389F,
1641   PREFIX_EVEX_0F38A0,
1642   PREFIX_EVEX_0F38A1,
1643   PREFIX_EVEX_0F38A2,
1644   PREFIX_EVEX_0F38A3,
1645   PREFIX_EVEX_0F38A6,
1646   PREFIX_EVEX_0F38A7,
1647   PREFIX_EVEX_0F38A8,
1648   PREFIX_EVEX_0F38A9,
1649   PREFIX_EVEX_0F38AA,
1650   PREFIX_EVEX_0F38AB,
1651   PREFIX_EVEX_0F38AC,
1652   PREFIX_EVEX_0F38AD,
1653   PREFIX_EVEX_0F38AE,
1654   PREFIX_EVEX_0F38AF,
1655   PREFIX_EVEX_0F38B4,
1656   PREFIX_EVEX_0F38B5,
1657   PREFIX_EVEX_0F38B6,
1658   PREFIX_EVEX_0F38B7,
1659   PREFIX_EVEX_0F38B8,
1660   PREFIX_EVEX_0F38B9,
1661   PREFIX_EVEX_0F38BA,
1662   PREFIX_EVEX_0F38BB,
1663   PREFIX_EVEX_0F38BC,
1664   PREFIX_EVEX_0F38BD,
1665   PREFIX_EVEX_0F38BE,
1666   PREFIX_EVEX_0F38BF,
1667   PREFIX_EVEX_0F38C4,
1668   PREFIX_EVEX_0F38C6_REG_1,
1669   PREFIX_EVEX_0F38C6_REG_2,
1670   PREFIX_EVEX_0F38C6_REG_5,
1671   PREFIX_EVEX_0F38C6_REG_6,
1672   PREFIX_EVEX_0F38C7_REG_1,
1673   PREFIX_EVEX_0F38C7_REG_2,
1674   PREFIX_EVEX_0F38C7_REG_5,
1675   PREFIX_EVEX_0F38C7_REG_6,
1676   PREFIX_EVEX_0F38C8,
1677   PREFIX_EVEX_0F38CA,
1678   PREFIX_EVEX_0F38CB,
1679   PREFIX_EVEX_0F38CC,
1680   PREFIX_EVEX_0F38CD,
1681   PREFIX_EVEX_0F38CF,
1682   PREFIX_EVEX_0F38DC,
1683   PREFIX_EVEX_0F38DD,
1684   PREFIX_EVEX_0F38DE,
1685   PREFIX_EVEX_0F38DF,
1686
1687   PREFIX_EVEX_0F3A00,
1688   PREFIX_EVEX_0F3A01,
1689   PREFIX_EVEX_0F3A03,
1690   PREFIX_EVEX_0F3A04,
1691   PREFIX_EVEX_0F3A05,
1692   PREFIX_EVEX_0F3A08,
1693   PREFIX_EVEX_0F3A09,
1694   PREFIX_EVEX_0F3A0A,
1695   PREFIX_EVEX_0F3A0B,
1696   PREFIX_EVEX_0F3A0F,
1697   PREFIX_EVEX_0F3A14,
1698   PREFIX_EVEX_0F3A15,
1699   PREFIX_EVEX_0F3A16,
1700   PREFIX_EVEX_0F3A17,
1701   PREFIX_EVEX_0F3A18,
1702   PREFIX_EVEX_0F3A19,
1703   PREFIX_EVEX_0F3A1A,
1704   PREFIX_EVEX_0F3A1B,
1705   PREFIX_EVEX_0F3A1D,
1706   PREFIX_EVEX_0F3A1E,
1707   PREFIX_EVEX_0F3A1F,
1708   PREFIX_EVEX_0F3A20,
1709   PREFIX_EVEX_0F3A21,
1710   PREFIX_EVEX_0F3A22,
1711   PREFIX_EVEX_0F3A23,
1712   PREFIX_EVEX_0F3A25,
1713   PREFIX_EVEX_0F3A26,
1714   PREFIX_EVEX_0F3A27,
1715   PREFIX_EVEX_0F3A38,
1716   PREFIX_EVEX_0F3A39,
1717   PREFIX_EVEX_0F3A3A,
1718   PREFIX_EVEX_0F3A3B,
1719   PREFIX_EVEX_0F3A3E,
1720   PREFIX_EVEX_0F3A3F,
1721   PREFIX_EVEX_0F3A42,
1722   PREFIX_EVEX_0F3A43,
1723   PREFIX_EVEX_0F3A44,
1724   PREFIX_EVEX_0F3A50,
1725   PREFIX_EVEX_0F3A51,
1726   PREFIX_EVEX_0F3A54,
1727   PREFIX_EVEX_0F3A55,
1728   PREFIX_EVEX_0F3A56,
1729   PREFIX_EVEX_0F3A57,
1730   PREFIX_EVEX_0F3A66,
1731   PREFIX_EVEX_0F3A67,
1732   PREFIX_EVEX_0F3A70,
1733   PREFIX_EVEX_0F3A71,
1734   PREFIX_EVEX_0F3A72,
1735   PREFIX_EVEX_0F3A73,
1736   PREFIX_EVEX_0F3ACE,
1737   PREFIX_EVEX_0F3ACF
1738 };
1739
1740 enum
1741 {
1742   X86_64_06 = 0,
1743   X86_64_07,
1744   X86_64_0E,
1745   X86_64_16,
1746   X86_64_17,
1747   X86_64_1E,
1748   X86_64_1F,
1749   X86_64_27,
1750   X86_64_2F,
1751   X86_64_37,
1752   X86_64_3F,
1753   X86_64_60,
1754   X86_64_61,
1755   X86_64_62,
1756   X86_64_63,
1757   X86_64_6D,
1758   X86_64_6F,
1759   X86_64_82,
1760   X86_64_9A,
1761   X86_64_C2,
1762   X86_64_C3,
1763   X86_64_C4,
1764   X86_64_C5,
1765   X86_64_CE,
1766   X86_64_D4,
1767   X86_64_D5,
1768   X86_64_E8,
1769   X86_64_E9,
1770   X86_64_EA,
1771   X86_64_0F01_REG_0,
1772   X86_64_0F01_REG_1,
1773   X86_64_0F01_REG_2,
1774   X86_64_0F01_REG_3
1775 };
1776
1777 enum
1778 {
1779   THREE_BYTE_0F38 = 0,
1780   THREE_BYTE_0F3A
1781 };
1782
1783 enum
1784 {
1785   XOP_08 = 0,
1786   XOP_09,
1787   XOP_0A
1788 };
1789
1790 enum
1791 {
1792   VEX_0F = 0,
1793   VEX_0F38,
1794   VEX_0F3A
1795 };
1796
1797 enum
1798 {
1799   EVEX_0F = 0,
1800   EVEX_0F38,
1801   EVEX_0F3A
1802 };
1803
1804 enum
1805 {
1806   VEX_LEN_0F12_P_0_M_0 = 0,
1807   VEX_LEN_0F12_P_0_M_1,
1808   VEX_LEN_0F12_P_2,
1809   VEX_LEN_0F13_M_0,
1810   VEX_LEN_0F16_P_0_M_0,
1811   VEX_LEN_0F16_P_0_M_1,
1812   VEX_LEN_0F16_P_2,
1813   VEX_LEN_0F17_M_0,
1814   VEX_LEN_0F41_P_0,
1815   VEX_LEN_0F41_P_2,
1816   VEX_LEN_0F42_P_0,
1817   VEX_LEN_0F42_P_2,
1818   VEX_LEN_0F44_P_0,
1819   VEX_LEN_0F44_P_2,
1820   VEX_LEN_0F45_P_0,
1821   VEX_LEN_0F45_P_2,
1822   VEX_LEN_0F46_P_0,
1823   VEX_LEN_0F46_P_2,
1824   VEX_LEN_0F47_P_0,
1825   VEX_LEN_0F47_P_2,
1826   VEX_LEN_0F4A_P_0,
1827   VEX_LEN_0F4A_P_2,
1828   VEX_LEN_0F4B_P_0,
1829   VEX_LEN_0F4B_P_2,
1830   VEX_LEN_0F6E_P_2,
1831   VEX_LEN_0F77_P_0,
1832   VEX_LEN_0F7E_P_1,
1833   VEX_LEN_0F7E_P_2,
1834   VEX_LEN_0F90_P_0,
1835   VEX_LEN_0F90_P_2,
1836   VEX_LEN_0F91_P_0,
1837   VEX_LEN_0F91_P_2,
1838   VEX_LEN_0F92_P_0,
1839   VEX_LEN_0F92_P_2,
1840   VEX_LEN_0F92_P_3,
1841   VEX_LEN_0F93_P_0,
1842   VEX_LEN_0F93_P_2,
1843   VEX_LEN_0F93_P_3,
1844   VEX_LEN_0F98_P_0,
1845   VEX_LEN_0F98_P_2,
1846   VEX_LEN_0F99_P_0,
1847   VEX_LEN_0F99_P_2,
1848   VEX_LEN_0FAE_R_2_M_0,
1849   VEX_LEN_0FAE_R_3_M_0,
1850   VEX_LEN_0FC4_P_2,
1851   VEX_LEN_0FC5_P_2,
1852   VEX_LEN_0FD6_P_2,
1853   VEX_LEN_0FF7_P_2,
1854   VEX_LEN_0F3816_P_2,
1855   VEX_LEN_0F3819_P_2,
1856   VEX_LEN_0F381A_P_2_M_0,
1857   VEX_LEN_0F3836_P_2,
1858   VEX_LEN_0F3841_P_2,
1859   VEX_LEN_0F385A_P_2_M_0,
1860   VEX_LEN_0F38DB_P_2,
1861   VEX_LEN_0F38F2_P_0,
1862   VEX_LEN_0F38F3_R_1_P_0,
1863   VEX_LEN_0F38F3_R_2_P_0,
1864   VEX_LEN_0F38F3_R_3_P_0,
1865   VEX_LEN_0F38F5_P_0,
1866   VEX_LEN_0F38F5_P_1,
1867   VEX_LEN_0F38F5_P_3,
1868   VEX_LEN_0F38F6_P_3,
1869   VEX_LEN_0F38F7_P_0,
1870   VEX_LEN_0F38F7_P_1,
1871   VEX_LEN_0F38F7_P_2,
1872   VEX_LEN_0F38F7_P_3,
1873   VEX_LEN_0F3A00_P_2,
1874   VEX_LEN_0F3A01_P_2,
1875   VEX_LEN_0F3A06_P_2,
1876   VEX_LEN_0F3A14_P_2,
1877   VEX_LEN_0F3A15_P_2,
1878   VEX_LEN_0F3A16_P_2,
1879   VEX_LEN_0F3A17_P_2,
1880   VEX_LEN_0F3A18_P_2,
1881   VEX_LEN_0F3A19_P_2,
1882   VEX_LEN_0F3A20_P_2,
1883   VEX_LEN_0F3A21_P_2,
1884   VEX_LEN_0F3A22_P_2,
1885   VEX_LEN_0F3A30_P_2,
1886   VEX_LEN_0F3A31_P_2,
1887   VEX_LEN_0F3A32_P_2,
1888   VEX_LEN_0F3A33_P_2,
1889   VEX_LEN_0F3A38_P_2,
1890   VEX_LEN_0F3A39_P_2,
1891   VEX_LEN_0F3A41_P_2,
1892   VEX_LEN_0F3A46_P_2,
1893   VEX_LEN_0F3A60_P_2,
1894   VEX_LEN_0F3A61_P_2,
1895   VEX_LEN_0F3A62_P_2,
1896   VEX_LEN_0F3A63_P_2,
1897   VEX_LEN_0F3A6A_P_2,
1898   VEX_LEN_0F3A6B_P_2,
1899   VEX_LEN_0F3A6E_P_2,
1900   VEX_LEN_0F3A6F_P_2,
1901   VEX_LEN_0F3A7A_P_2,
1902   VEX_LEN_0F3A7B_P_2,
1903   VEX_LEN_0F3A7E_P_2,
1904   VEX_LEN_0F3A7F_P_2,
1905   VEX_LEN_0F3ADF_P_2,
1906   VEX_LEN_0F3AF0_P_3,
1907   VEX_LEN_0FXOP_08_CC,
1908   VEX_LEN_0FXOP_08_CD,
1909   VEX_LEN_0FXOP_08_CE,
1910   VEX_LEN_0FXOP_08_CF,
1911   VEX_LEN_0FXOP_08_EC,
1912   VEX_LEN_0FXOP_08_ED,
1913   VEX_LEN_0FXOP_08_EE,
1914   VEX_LEN_0FXOP_08_EF,
1915   VEX_LEN_0FXOP_09_80,
1916   VEX_LEN_0FXOP_09_81
1917 };
1918
1919 enum
1920 {
1921   EVEX_LEN_0F6E_P_2 = 0,
1922   EVEX_LEN_0F7E_P_1,
1923   EVEX_LEN_0F7E_P_2,
1924   EVEX_LEN_0FD6_P_2,
1925   EVEX_LEN_0F3819_P_2_W_0,
1926   EVEX_LEN_0F3819_P_2_W_1,
1927   EVEX_LEN_0F381A_P_2_W_0,
1928   EVEX_LEN_0F381A_P_2_W_1,
1929   EVEX_LEN_0F381B_P_2_W_0,
1930   EVEX_LEN_0F381B_P_2_W_1,
1931   EVEX_LEN_0F385A_P_2_W_0,
1932   EVEX_LEN_0F385A_P_2_W_1,
1933   EVEX_LEN_0F385B_P_2_W_0,
1934   EVEX_LEN_0F385B_P_2_W_1,
1935   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1936   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1937   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1938   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1939   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1940   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1941   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1942   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1943   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1944   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1945   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1946   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1947   EVEX_LEN_0F3A18_P_2_W_0,
1948   EVEX_LEN_0F3A18_P_2_W_1,
1949   EVEX_LEN_0F3A19_P_2_W_0,
1950   EVEX_LEN_0F3A19_P_2_W_1,
1951   EVEX_LEN_0F3A1A_P_2_W_0,
1952   EVEX_LEN_0F3A1A_P_2_W_1,
1953   EVEX_LEN_0F3A1B_P_2_W_0,
1954   EVEX_LEN_0F3A1B_P_2_W_1,
1955   EVEX_LEN_0F3A23_P_2_W_0,
1956   EVEX_LEN_0F3A23_P_2_W_1,
1957   EVEX_LEN_0F3A38_P_2_W_0,
1958   EVEX_LEN_0F3A38_P_2_W_1,
1959   EVEX_LEN_0F3A39_P_2_W_0,
1960   EVEX_LEN_0F3A39_P_2_W_1,
1961   EVEX_LEN_0F3A3A_P_2_W_0,
1962   EVEX_LEN_0F3A3A_P_2_W_1,
1963   EVEX_LEN_0F3A3B_P_2_W_0,
1964   EVEX_LEN_0F3A3B_P_2_W_1,
1965   EVEX_LEN_0F3A43_P_2_W_0,
1966   EVEX_LEN_0F3A43_P_2_W_1
1967 };
1968
1969 enum
1970 {
1971   VEX_W_0F41_P_0_LEN_1 = 0,
1972   VEX_W_0F41_P_2_LEN_1,
1973   VEX_W_0F42_P_0_LEN_1,
1974   VEX_W_0F42_P_2_LEN_1,
1975   VEX_W_0F44_P_0_LEN_0,
1976   VEX_W_0F44_P_2_LEN_0,
1977   VEX_W_0F45_P_0_LEN_1,
1978   VEX_W_0F45_P_2_LEN_1,
1979   VEX_W_0F46_P_0_LEN_1,
1980   VEX_W_0F46_P_2_LEN_1,
1981   VEX_W_0F47_P_0_LEN_1,
1982   VEX_W_0F47_P_2_LEN_1,
1983   VEX_W_0F4A_P_0_LEN_1,
1984   VEX_W_0F4A_P_2_LEN_1,
1985   VEX_W_0F4B_P_0_LEN_1,
1986   VEX_W_0F4B_P_2_LEN_1,
1987   VEX_W_0F90_P_0_LEN_0,
1988   VEX_W_0F90_P_2_LEN_0,
1989   VEX_W_0F91_P_0_LEN_0,
1990   VEX_W_0F91_P_2_LEN_0,
1991   VEX_W_0F92_P_0_LEN_0,
1992   VEX_W_0F92_P_2_LEN_0,
1993   VEX_W_0F93_P_0_LEN_0,
1994   VEX_W_0F93_P_2_LEN_0,
1995   VEX_W_0F98_P_0_LEN_0,
1996   VEX_W_0F98_P_2_LEN_0,
1997   VEX_W_0F99_P_0_LEN_0,
1998   VEX_W_0F99_P_2_LEN_0,
1999   VEX_W_0F380C_P_2,
2000   VEX_W_0F380D_P_2,
2001   VEX_W_0F380E_P_2,
2002   VEX_W_0F380F_P_2,
2003   VEX_W_0F3816_P_2,
2004   VEX_W_0F3818_P_2,
2005   VEX_W_0F3819_P_2,
2006   VEX_W_0F381A_P_2_M_0,
2007   VEX_W_0F382C_P_2_M_0,
2008   VEX_W_0F382D_P_2_M_0,
2009   VEX_W_0F382E_P_2_M_0,
2010   VEX_W_0F382F_P_2_M_0,
2011   VEX_W_0F3836_P_2,
2012   VEX_W_0F3846_P_2,
2013   VEX_W_0F3858_P_2,
2014   VEX_W_0F3859_P_2,
2015   VEX_W_0F385A_P_2_M_0,
2016   VEX_W_0F3878_P_2,
2017   VEX_W_0F3879_P_2,
2018   VEX_W_0F38CF_P_2,
2019   VEX_W_0F3A00_P_2,
2020   VEX_W_0F3A01_P_2,
2021   VEX_W_0F3A02_P_2,
2022   VEX_W_0F3A04_P_2,
2023   VEX_W_0F3A05_P_2,
2024   VEX_W_0F3A06_P_2,
2025   VEX_W_0F3A18_P_2,
2026   VEX_W_0F3A19_P_2,
2027   VEX_W_0F3A30_P_2_LEN_0,
2028   VEX_W_0F3A31_P_2_LEN_0,
2029   VEX_W_0F3A32_P_2_LEN_0,
2030   VEX_W_0F3A33_P_2_LEN_0,
2031   VEX_W_0F3A38_P_2,
2032   VEX_W_0F3A39_P_2,
2033   VEX_W_0F3A46_P_2,
2034   VEX_W_0F3A48_P_2,
2035   VEX_W_0F3A49_P_2,
2036   VEX_W_0F3A4A_P_2,
2037   VEX_W_0F3A4B_P_2,
2038   VEX_W_0F3A4C_P_2,
2039   VEX_W_0F3ACE_P_2,
2040   VEX_W_0F3ACF_P_2,
2041
2042   EVEX_W_0F10_P_0,
2043   EVEX_W_0F10_P_1,
2044   EVEX_W_0F10_P_2,
2045   EVEX_W_0F10_P_3,
2046   EVEX_W_0F11_P_0,
2047   EVEX_W_0F11_P_1,
2048   EVEX_W_0F11_P_2,
2049   EVEX_W_0F11_P_3,
2050   EVEX_W_0F12_P_0_M_0,
2051   EVEX_W_0F12_P_0_M_1,
2052   EVEX_W_0F12_P_1,
2053   EVEX_W_0F12_P_2,
2054   EVEX_W_0F12_P_3,
2055   EVEX_W_0F13_P_0,
2056   EVEX_W_0F13_P_2,
2057   EVEX_W_0F14_P_0,
2058   EVEX_W_0F14_P_2,
2059   EVEX_W_0F15_P_0,
2060   EVEX_W_0F15_P_2,
2061   EVEX_W_0F16_P_0_M_0,
2062   EVEX_W_0F16_P_0_M_1,
2063   EVEX_W_0F16_P_1,
2064   EVEX_W_0F16_P_2,
2065   EVEX_W_0F17_P_0,
2066   EVEX_W_0F17_P_2,
2067   EVEX_W_0F28_P_0,
2068   EVEX_W_0F28_P_2,
2069   EVEX_W_0F29_P_0,
2070   EVEX_W_0F29_P_2,
2071   EVEX_W_0F2A_P_3,
2072   EVEX_W_0F2B_P_0,
2073   EVEX_W_0F2B_P_2,
2074   EVEX_W_0F2E_P_0,
2075   EVEX_W_0F2E_P_2,
2076   EVEX_W_0F2F_P_0,
2077   EVEX_W_0F2F_P_2,
2078   EVEX_W_0F51_P_0,
2079   EVEX_W_0F51_P_1,
2080   EVEX_W_0F51_P_2,
2081   EVEX_W_0F51_P_3,
2082   EVEX_W_0F54_P_0,
2083   EVEX_W_0F54_P_2,
2084   EVEX_W_0F55_P_0,
2085   EVEX_W_0F55_P_2,
2086   EVEX_W_0F56_P_0,
2087   EVEX_W_0F56_P_2,
2088   EVEX_W_0F57_P_0,
2089   EVEX_W_0F57_P_2,
2090   EVEX_W_0F58_P_0,
2091   EVEX_W_0F58_P_1,
2092   EVEX_W_0F58_P_2,
2093   EVEX_W_0F58_P_3,
2094   EVEX_W_0F59_P_0,
2095   EVEX_W_0F59_P_1,
2096   EVEX_W_0F59_P_2,
2097   EVEX_W_0F59_P_3,
2098   EVEX_W_0F5A_P_0,
2099   EVEX_W_0F5A_P_1,
2100   EVEX_W_0F5A_P_2,
2101   EVEX_W_0F5A_P_3,
2102   EVEX_W_0F5B_P_0,
2103   EVEX_W_0F5B_P_1,
2104   EVEX_W_0F5B_P_2,
2105   EVEX_W_0F5C_P_0,
2106   EVEX_W_0F5C_P_1,
2107   EVEX_W_0F5C_P_2,
2108   EVEX_W_0F5C_P_3,
2109   EVEX_W_0F5D_P_0,
2110   EVEX_W_0F5D_P_1,
2111   EVEX_W_0F5D_P_2,
2112   EVEX_W_0F5D_P_3,
2113   EVEX_W_0F5E_P_0,
2114   EVEX_W_0F5E_P_1,
2115   EVEX_W_0F5E_P_2,
2116   EVEX_W_0F5E_P_3,
2117   EVEX_W_0F5F_P_0,
2118   EVEX_W_0F5F_P_1,
2119   EVEX_W_0F5F_P_2,
2120   EVEX_W_0F5F_P_3,
2121   EVEX_W_0F62_P_2,
2122   EVEX_W_0F66_P_2,
2123   EVEX_W_0F6A_P_2,
2124   EVEX_W_0F6B_P_2,
2125   EVEX_W_0F6C_P_2,
2126   EVEX_W_0F6D_P_2,
2127   EVEX_W_0F6F_P_1,
2128   EVEX_W_0F6F_P_2,
2129   EVEX_W_0F6F_P_3,
2130   EVEX_W_0F70_P_2,
2131   EVEX_W_0F72_R_2_P_2,
2132   EVEX_W_0F72_R_6_P_2,
2133   EVEX_W_0F73_R_2_P_2,
2134   EVEX_W_0F73_R_6_P_2,
2135   EVEX_W_0F76_P_2,
2136   EVEX_W_0F78_P_0,
2137   EVEX_W_0F78_P_2,
2138   EVEX_W_0F79_P_0,
2139   EVEX_W_0F79_P_2,
2140   EVEX_W_0F7A_P_1,
2141   EVEX_W_0F7A_P_2,
2142   EVEX_W_0F7A_P_3,
2143   EVEX_W_0F7B_P_2,
2144   EVEX_W_0F7B_P_3,
2145   EVEX_W_0F7E_P_1,
2146   EVEX_W_0F7F_P_1,
2147   EVEX_W_0F7F_P_2,
2148   EVEX_W_0F7F_P_3,
2149   EVEX_W_0FC2_P_0,
2150   EVEX_W_0FC2_P_1,
2151   EVEX_W_0FC2_P_2,
2152   EVEX_W_0FC2_P_3,
2153   EVEX_W_0FC6_P_0,
2154   EVEX_W_0FC6_P_2,
2155   EVEX_W_0FD2_P_2,
2156   EVEX_W_0FD3_P_2,
2157   EVEX_W_0FD4_P_2,
2158   EVEX_W_0FD6_P_2,
2159   EVEX_W_0FE6_P_1,
2160   EVEX_W_0FE6_P_2,
2161   EVEX_W_0FE6_P_3,
2162   EVEX_W_0FE7_P_2,
2163   EVEX_W_0FF2_P_2,
2164   EVEX_W_0FF3_P_2,
2165   EVEX_W_0FF4_P_2,
2166   EVEX_W_0FFA_P_2,
2167   EVEX_W_0FFB_P_2,
2168   EVEX_W_0FFE_P_2,
2169   EVEX_W_0F380C_P_2,
2170   EVEX_W_0F380D_P_2,
2171   EVEX_W_0F3810_P_1,
2172   EVEX_W_0F3810_P_2,
2173   EVEX_W_0F3811_P_1,
2174   EVEX_W_0F3811_P_2,
2175   EVEX_W_0F3812_P_1,
2176   EVEX_W_0F3812_P_2,
2177   EVEX_W_0F3813_P_1,
2178   EVEX_W_0F3813_P_2,
2179   EVEX_W_0F3814_P_1,
2180   EVEX_W_0F3815_P_1,
2181   EVEX_W_0F3818_P_2,
2182   EVEX_W_0F3819_P_2,
2183   EVEX_W_0F381A_P_2,
2184   EVEX_W_0F381B_P_2,
2185   EVEX_W_0F381E_P_2,
2186   EVEX_W_0F381F_P_2,
2187   EVEX_W_0F3820_P_1,
2188   EVEX_W_0F3821_P_1,
2189   EVEX_W_0F3822_P_1,
2190   EVEX_W_0F3823_P_1,
2191   EVEX_W_0F3824_P_1,
2192   EVEX_W_0F3825_P_1,
2193   EVEX_W_0F3825_P_2,
2194   EVEX_W_0F3826_P_1,
2195   EVEX_W_0F3826_P_2,
2196   EVEX_W_0F3828_P_1,
2197   EVEX_W_0F3828_P_2,
2198   EVEX_W_0F3829_P_1,
2199   EVEX_W_0F3829_P_2,
2200   EVEX_W_0F382A_P_1,
2201   EVEX_W_0F382A_P_2,
2202   EVEX_W_0F382B_P_2,
2203   EVEX_W_0F3830_P_1,
2204   EVEX_W_0F3831_P_1,
2205   EVEX_W_0F3832_P_1,
2206   EVEX_W_0F3833_P_1,
2207   EVEX_W_0F3834_P_1,
2208   EVEX_W_0F3835_P_1,
2209   EVEX_W_0F3835_P_2,
2210   EVEX_W_0F3837_P_2,
2211   EVEX_W_0F3838_P_1,
2212   EVEX_W_0F3839_P_1,
2213   EVEX_W_0F383A_P_1,
2214   EVEX_W_0F3840_P_2,
2215   EVEX_W_0F3852_P_1,
2216   EVEX_W_0F3854_P_2,
2217   EVEX_W_0F3855_P_2,
2218   EVEX_W_0F3858_P_2,
2219   EVEX_W_0F3859_P_2,
2220   EVEX_W_0F385A_P_2,
2221   EVEX_W_0F385B_P_2,
2222   EVEX_W_0F3862_P_2,
2223   EVEX_W_0F3863_P_2,
2224   EVEX_W_0F3866_P_2,
2225   EVEX_W_0F3868_P_3,
2226   EVEX_W_0F3870_P_2,
2227   EVEX_W_0F3871_P_2,
2228   EVEX_W_0F3872_P_1,
2229   EVEX_W_0F3872_P_2,
2230   EVEX_W_0F3872_P_3,
2231   EVEX_W_0F3873_P_2,
2232   EVEX_W_0F3875_P_2,
2233   EVEX_W_0F3878_P_2,
2234   EVEX_W_0F3879_P_2,
2235   EVEX_W_0F387A_P_2,
2236   EVEX_W_0F387B_P_2,
2237   EVEX_W_0F387D_P_2,
2238   EVEX_W_0F3883_P_2,
2239   EVEX_W_0F388D_P_2,
2240   EVEX_W_0F3891_P_2,
2241   EVEX_W_0F3893_P_2,
2242   EVEX_W_0F38A1_P_2,
2243   EVEX_W_0F38A3_P_2,
2244   EVEX_W_0F38C7_R_1_P_2,
2245   EVEX_W_0F38C7_R_2_P_2,
2246   EVEX_W_0F38C7_R_5_P_2,
2247   EVEX_W_0F38C7_R_6_P_2,
2248
2249   EVEX_W_0F3A00_P_2,
2250   EVEX_W_0F3A01_P_2,
2251   EVEX_W_0F3A04_P_2,
2252   EVEX_W_0F3A05_P_2,
2253   EVEX_W_0F3A08_P_2,
2254   EVEX_W_0F3A09_P_2,
2255   EVEX_W_0F3A0A_P_2,
2256   EVEX_W_0F3A0B_P_2,
2257   EVEX_W_0F3A18_P_2,
2258   EVEX_W_0F3A19_P_2,
2259   EVEX_W_0F3A1A_P_2,
2260   EVEX_W_0F3A1B_P_2,
2261   EVEX_W_0F3A1D_P_2,
2262   EVEX_W_0F3A21_P_2,
2263   EVEX_W_0F3A23_P_2,
2264   EVEX_W_0F3A38_P_2,
2265   EVEX_W_0F3A39_P_2,
2266   EVEX_W_0F3A3A_P_2,
2267   EVEX_W_0F3A3B_P_2,
2268   EVEX_W_0F3A3E_P_2,
2269   EVEX_W_0F3A3F_P_2,
2270   EVEX_W_0F3A42_P_2,
2271   EVEX_W_0F3A43_P_2,
2272   EVEX_W_0F3A50_P_2,
2273   EVEX_W_0F3A51_P_2,
2274   EVEX_W_0F3A56_P_2,
2275   EVEX_W_0F3A57_P_2,
2276   EVEX_W_0F3A66_P_2,
2277   EVEX_W_0F3A67_P_2,
2278   EVEX_W_0F3A70_P_2,
2279   EVEX_W_0F3A71_P_2,
2280   EVEX_W_0F3A72_P_2,
2281   EVEX_W_0F3A73_P_2,
2282   EVEX_W_0F3ACE_P_2,
2283   EVEX_W_0F3ACF_P_2
2284 };
2285
2286 typedef void (*op_rtn) (int bytemode, int sizeflag);
2287
2288 struct dis386 {
2289   const char *name;
2290   struct
2291     {
2292       op_rtn rtn;
2293       int bytemode;
2294     } op[MAX_OPERANDS];
2295   unsigned int prefix_requirement;
2296 };
2297
2298 /* Upper case letters in the instruction names here are macros.
2299    'A' => print 'b' if no register operands or suffix_always is true
2300    'B' => print 'b' if suffix_always is true
2301    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2302           size prefix
2303    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2304           suffix_always is true
2305    'E' => print 'e' if 32-bit form of jcxz
2306    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2307    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2308    'H' => print ",pt" or ",pn" branch hint
2309    'I' => honor following macro letter even in Intel mode (implemented only
2310           for some of the macro letters)
2311    'J' => print 'l'
2312    'K' => print 'd' or 'q' if rex prefix is present.
2313    'L' => print 'l' if suffix_always is true
2314    'M' => print 'r' if intel_mnemonic is false.
2315    'N' => print 'n' if instruction has no wait "prefix"
2316    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2317    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2318           or suffix_always is true.  print 'q' if rex prefix is present.
2319    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2320           is true
2321    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2322    'S' => print 'w', 'l' or 'q' if suffix_always is true
2323    'T' => print 'q' in 64bit mode if instruction has no operand size
2324           prefix and behave as 'P' otherwise
2325    'U' => print 'q' in 64bit mode if instruction has no operand size
2326           prefix and behave as 'Q' otherwise
2327    'V' => print 'q' in 64bit mode if instruction has no operand size
2328           prefix and behave as 'S' otherwise
2329    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2330    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2331    'Y' unused.
2332    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2333    '!' => change condition from true to false or from false to true.
2334    '%' => add 1 upper case letter to the macro.
2335    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2336           prefix or suffix_always is true (lcall/ljmp).
2337    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2338           on operand size prefix.
2339    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2340           has no operand size prefix for AMD64 ISA, behave as 'P'
2341           otherwise
2342
2343    2 upper case letter macros:
2344    "XY" => print 'x' or 'y' if suffix_always is true or no register
2345            operands and no broadcast.
2346    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2347            register operands and no broadcast.
2348    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2349    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2350            or suffix_always is true
2351    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2352    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2353    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2354    "LW" => print 'd', 'q' depending on the VEX.W bit
2355    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2356            an operand size prefix, or suffix_always is true.  print
2357            'q' if rex prefix is present.
2358
2359    Many of the above letters print nothing in Intel mode.  See "putop"
2360    for the details.
2361
2362    Braces '{' and '}', and vertical bars '|', indicate alternative
2363    mnemonic strings for AT&T and Intel.  */
2364
2365 static const struct dis386 dis386[] = {
2366   /* 00 */
2367   { "addB",             { Ebh1, Gb }, 0 },
2368   { "addS",             { Evh1, Gv }, 0 },
2369   { "addB",             { Gb, EbS }, 0 },
2370   { "addS",             { Gv, EvS }, 0 },
2371   { "addB",             { AL, Ib }, 0 },
2372   { "addS",             { eAX, Iv }, 0 },
2373   { X86_64_TABLE (X86_64_06) },
2374   { X86_64_TABLE (X86_64_07) },
2375   /* 08 */
2376   { "orB",              { Ebh1, Gb }, 0 },
2377   { "orS",              { Evh1, Gv }, 0 },
2378   { "orB",              { Gb, EbS }, 0 },
2379   { "orS",              { Gv, EvS }, 0 },
2380   { "orB",              { AL, Ib }, 0 },
2381   { "orS",              { eAX, Iv }, 0 },
2382   { X86_64_TABLE (X86_64_0E) },
2383   { Bad_Opcode },       /* 0x0f extended opcode escape */
2384   /* 10 */
2385   { "adcB",             { Ebh1, Gb }, 0 },
2386   { "adcS",             { Evh1, Gv }, 0 },
2387   { "adcB",             { Gb, EbS }, 0 },
2388   { "adcS",             { Gv, EvS }, 0 },
2389   { "adcB",             { AL, Ib }, 0 },
2390   { "adcS",             { eAX, Iv }, 0 },
2391   { X86_64_TABLE (X86_64_16) },
2392   { X86_64_TABLE (X86_64_17) },
2393   /* 18 */
2394   { "sbbB",             { Ebh1, Gb }, 0 },
2395   { "sbbS",             { Evh1, Gv }, 0 },
2396   { "sbbB",             { Gb, EbS }, 0 },
2397   { "sbbS",             { Gv, EvS }, 0 },
2398   { "sbbB",             { AL, Ib }, 0 },
2399   { "sbbS",             { eAX, Iv }, 0 },
2400   { X86_64_TABLE (X86_64_1E) },
2401   { X86_64_TABLE (X86_64_1F) },
2402   /* 20 */
2403   { "andB",             { Ebh1, Gb }, 0 },
2404   { "andS",             { Evh1, Gv }, 0 },
2405   { "andB",             { Gb, EbS }, 0 },
2406   { "andS",             { Gv, EvS }, 0 },
2407   { "andB",             { AL, Ib }, 0 },
2408   { "andS",             { eAX, Iv }, 0 },
2409   { Bad_Opcode },       /* SEG ES prefix */
2410   { X86_64_TABLE (X86_64_27) },
2411   /* 28 */
2412   { "subB",             { Ebh1, Gb }, 0 },
2413   { "subS",             { Evh1, Gv }, 0 },
2414   { "subB",             { Gb, EbS }, 0 },
2415   { "subS",             { Gv, EvS }, 0 },
2416   { "subB",             { AL, Ib }, 0 },
2417   { "subS",             { eAX, Iv }, 0 },
2418   { Bad_Opcode },       /* SEG CS prefix */
2419   { X86_64_TABLE (X86_64_2F) },
2420   /* 30 */
2421   { "xorB",             { Ebh1, Gb }, 0 },
2422   { "xorS",             { Evh1, Gv }, 0 },
2423   { "xorB",             { Gb, EbS }, 0 },
2424   { "xorS",             { Gv, EvS }, 0 },
2425   { "xorB",             { AL, Ib }, 0 },
2426   { "xorS",             { eAX, Iv }, 0 },
2427   { Bad_Opcode },       /* SEG SS prefix */
2428   { X86_64_TABLE (X86_64_37) },
2429   /* 38 */
2430   { "cmpB",             { Eb, Gb }, 0 },
2431   { "cmpS",             { Ev, Gv }, 0 },
2432   { "cmpB",             { Gb, EbS }, 0 },
2433   { "cmpS",             { Gv, EvS }, 0 },
2434   { "cmpB",             { AL, Ib }, 0 },
2435   { "cmpS",             { eAX, Iv }, 0 },
2436   { Bad_Opcode },       /* SEG DS prefix */
2437   { X86_64_TABLE (X86_64_3F) },
2438   /* 40 */
2439   { "inc{S|}",          { RMeAX }, 0 },
2440   { "inc{S|}",          { RMeCX }, 0 },
2441   { "inc{S|}",          { RMeDX }, 0 },
2442   { "inc{S|}",          { RMeBX }, 0 },
2443   { "inc{S|}",          { RMeSP }, 0 },
2444   { "inc{S|}",          { RMeBP }, 0 },
2445   { "inc{S|}",          { RMeSI }, 0 },
2446   { "inc{S|}",          { RMeDI }, 0 },
2447   /* 48 */
2448   { "dec{S|}",          { RMeAX }, 0 },
2449   { "dec{S|}",          { RMeCX }, 0 },
2450   { "dec{S|}",          { RMeDX }, 0 },
2451   { "dec{S|}",          { RMeBX }, 0 },
2452   { "dec{S|}",          { RMeSP }, 0 },
2453   { "dec{S|}",          { RMeBP }, 0 },
2454   { "dec{S|}",          { RMeSI }, 0 },
2455   { "dec{S|}",          { RMeDI }, 0 },
2456   /* 50 */
2457   { "pushV",            { RMrAX }, 0 },
2458   { "pushV",            { RMrCX }, 0 },
2459   { "pushV",            { RMrDX }, 0 },
2460   { "pushV",            { RMrBX }, 0 },
2461   { "pushV",            { RMrSP }, 0 },
2462   { "pushV",            { RMrBP }, 0 },
2463   { "pushV",            { RMrSI }, 0 },
2464   { "pushV",            { RMrDI }, 0 },
2465   /* 58 */
2466   { "popV",             { RMrAX }, 0 },
2467   { "popV",             { RMrCX }, 0 },
2468   { "popV",             { RMrDX }, 0 },
2469   { "popV",             { RMrBX }, 0 },
2470   { "popV",             { RMrSP }, 0 },
2471   { "popV",             { RMrBP }, 0 },
2472   { "popV",             { RMrSI }, 0 },
2473   { "popV",             { RMrDI }, 0 },
2474   /* 60 */
2475   { X86_64_TABLE (X86_64_60) },
2476   { X86_64_TABLE (X86_64_61) },
2477   { X86_64_TABLE (X86_64_62) },
2478   { X86_64_TABLE (X86_64_63) },
2479   { Bad_Opcode },       /* seg fs */
2480   { Bad_Opcode },       /* seg gs */
2481   { Bad_Opcode },       /* op size prefix */
2482   { Bad_Opcode },       /* adr size prefix */
2483   /* 68 */
2484   { "pushT",            { sIv }, 0 },
2485   { "imulS",            { Gv, Ev, Iv }, 0 },
2486   { "pushT",            { sIbT }, 0 },
2487   { "imulS",            { Gv, Ev, sIb }, 0 },
2488   { "ins{b|}",          { Ybr, indirDX }, 0 },
2489   { X86_64_TABLE (X86_64_6D) },
2490   { "outs{b|}",         { indirDXr, Xb }, 0 },
2491   { X86_64_TABLE (X86_64_6F) },
2492   /* 70 */
2493   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2494   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2495   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2496   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2497   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2498   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2499   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2500   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2501   /* 78 */
2502   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2503   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2504   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2505   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2506   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2507   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2508   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2509   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2510   /* 80 */
2511   { REG_TABLE (REG_80) },
2512   { REG_TABLE (REG_81) },
2513   { X86_64_TABLE (X86_64_82) },
2514   { REG_TABLE (REG_83) },
2515   { "testB",            { Eb, Gb }, 0 },
2516   { "testS",            { Ev, Gv }, 0 },
2517   { "xchgB",            { Ebh2, Gb }, 0 },
2518   { "xchgS",            { Evh2, Gv }, 0 },
2519   /* 88 */
2520   { "movB",             { Ebh3, Gb }, 0 },
2521   { "movS",             { Evh3, Gv }, 0 },
2522   { "movB",             { Gb, EbS }, 0 },
2523   { "movS",             { Gv, EvS }, 0 },
2524   { "movD",             { Sv, Sw }, 0 },
2525   { MOD_TABLE (MOD_8D) },
2526   { "movD",             { Sw, Sv }, 0 },
2527   { REG_TABLE (REG_8F) },
2528   /* 90 */
2529   { PREFIX_TABLE (PREFIX_90) },
2530   { "xchgS",            { RMeCX, eAX }, 0 },
2531   { "xchgS",            { RMeDX, eAX }, 0 },
2532   { "xchgS",            { RMeBX, eAX }, 0 },
2533   { "xchgS",            { RMeSP, eAX }, 0 },
2534   { "xchgS",            { RMeBP, eAX }, 0 },
2535   { "xchgS",            { RMeSI, eAX }, 0 },
2536   { "xchgS",            { RMeDI, eAX }, 0 },
2537   /* 98 */
2538   { "cW{t|}R",          { XX }, 0 },
2539   { "cR{t|}O",          { XX }, 0 },
2540   { X86_64_TABLE (X86_64_9A) },
2541   { Bad_Opcode },       /* fwait */
2542   { "pushfT",           { XX }, 0 },
2543   { "popfT",            { XX }, 0 },
2544   { "sahf",             { XX }, 0 },
2545   { "lahf",             { XX }, 0 },
2546   /* a0 */
2547   { "mov%LB",           { AL, Ob }, 0 },
2548   { "mov%LS",           { eAX, Ov }, 0 },
2549   { "mov%LB",           { Ob, AL }, 0 },
2550   { "mov%LS",           { Ov, eAX }, 0 },
2551   { "movs{b|}",         { Ybr, Xb }, 0 },
2552   { "movs{R|}",         { Yvr, Xv }, 0 },
2553   { "cmps{b|}",         { Xb, Yb }, 0 },
2554   { "cmps{R|}",         { Xv, Yv }, 0 },
2555   /* a8 */
2556   { "testB",            { AL, Ib }, 0 },
2557   { "testS",            { eAX, Iv }, 0 },
2558   { "stosB",            { Ybr, AL }, 0 },
2559   { "stosS",            { Yvr, eAX }, 0 },
2560   { "lodsB",            { ALr, Xb }, 0 },
2561   { "lodsS",            { eAXr, Xv }, 0 },
2562   { "scasB",            { AL, Yb }, 0 },
2563   { "scasS",            { eAX, Yv }, 0 },
2564   /* b0 */
2565   { "movB",             { RMAL, Ib }, 0 },
2566   { "movB",             { RMCL, Ib }, 0 },
2567   { "movB",             { RMDL, Ib }, 0 },
2568   { "movB",             { RMBL, Ib }, 0 },
2569   { "movB",             { RMAH, Ib }, 0 },
2570   { "movB",             { RMCH, Ib }, 0 },
2571   { "movB",             { RMDH, Ib }, 0 },
2572   { "movB",             { RMBH, Ib }, 0 },
2573   /* b8 */
2574   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2575   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2576   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2577   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2578   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2579   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2580   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2581   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2582   /* c0 */
2583   { REG_TABLE (REG_C0) },
2584   { REG_TABLE (REG_C1) },
2585   { X86_64_TABLE (X86_64_C2) },
2586   { X86_64_TABLE (X86_64_C3) },
2587   { X86_64_TABLE (X86_64_C4) },
2588   { X86_64_TABLE (X86_64_C5) },
2589   { REG_TABLE (REG_C6) },
2590   { REG_TABLE (REG_C7) },
2591   /* c8 */
2592   { "enterT",           { Iw, Ib }, 0 },
2593   { "leaveT",           { XX }, 0 },
2594   { "Jret{|f}P",        { Iw }, 0 },
2595   { "Jret{|f}P",        { XX }, 0 },
2596   { "int3",             { XX }, 0 },
2597   { "int",              { Ib }, 0 },
2598   { X86_64_TABLE (X86_64_CE) },
2599   { "iret%LP",          { XX }, 0 },
2600   /* d0 */
2601   { REG_TABLE (REG_D0) },
2602   { REG_TABLE (REG_D1) },
2603   { REG_TABLE (REG_D2) },
2604   { REG_TABLE (REG_D3) },
2605   { X86_64_TABLE (X86_64_D4) },
2606   { X86_64_TABLE (X86_64_D5) },
2607   { Bad_Opcode },
2608   { "xlat",             { DSBX }, 0 },
2609   /* d8 */
2610   { FLOAT },
2611   { FLOAT },
2612   { FLOAT },
2613   { FLOAT },
2614   { FLOAT },
2615   { FLOAT },
2616   { FLOAT },
2617   { FLOAT },
2618   /* e0 */
2619   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2620   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2621   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2622   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2623   { "inB",              { AL, Ib }, 0 },
2624   { "inG",              { zAX, Ib }, 0 },
2625   { "outB",             { Ib, AL }, 0 },
2626   { "outG",             { Ib, zAX }, 0 },
2627   /* e8 */
2628   { X86_64_TABLE (X86_64_E8) },
2629   { X86_64_TABLE (X86_64_E9) },
2630   { X86_64_TABLE (X86_64_EA) },
2631   { "jmp",              { Jb, BND }, 0 },
2632   { "inB",              { AL, indirDX }, 0 },
2633   { "inG",              { zAX, indirDX }, 0 },
2634   { "outB",             { indirDX, AL }, 0 },
2635   { "outG",             { indirDX, zAX }, 0 },
2636   /* f0 */
2637   { Bad_Opcode },       /* lock prefix */
2638   { "icebp",            { XX }, 0 },
2639   { Bad_Opcode },       /* repne */
2640   { Bad_Opcode },       /* repz */
2641   { "hlt",              { XX }, 0 },
2642   { "cmc",              { XX }, 0 },
2643   { REG_TABLE (REG_F6) },
2644   { REG_TABLE (REG_F7) },
2645   /* f8 */
2646   { "clc",              { XX }, 0 },
2647   { "stc",              { XX }, 0 },
2648   { "cli",              { XX }, 0 },
2649   { "sti",              { XX }, 0 },
2650   { "cld",              { XX }, 0 },
2651   { "std",              { XX }, 0 },
2652   { REG_TABLE (REG_FE) },
2653   { REG_TABLE (REG_FF) },
2654 };
2655
2656 static const struct dis386 dis386_twobyte[] = {
2657   /* 00 */
2658   { REG_TABLE (REG_0F00 ) },
2659   { REG_TABLE (REG_0F01 ) },
2660   { "larS",             { Gv, Ew }, 0 },
2661   { "lslS",             { Gv, Ew }, 0 },
2662   { Bad_Opcode },
2663   { "syscall",          { XX }, 0 },
2664   { "clts",             { XX }, 0 },
2665   { "sysret%LP",                { XX }, 0 },
2666   /* 08 */
2667   { "invd",             { XX }, 0 },
2668   { PREFIX_TABLE (PREFIX_0F09) },
2669   { Bad_Opcode },
2670   { "ud2",              { XX }, 0 },
2671   { Bad_Opcode },
2672   { REG_TABLE (REG_0F0D) },
2673   { "femms",            { XX }, 0 },
2674   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2675   /* 10 */
2676   { PREFIX_TABLE (PREFIX_0F10) },
2677   { PREFIX_TABLE (PREFIX_0F11) },
2678   { PREFIX_TABLE (PREFIX_0F12) },
2679   { MOD_TABLE (MOD_0F13) },
2680   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2681   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2682   { PREFIX_TABLE (PREFIX_0F16) },
2683   { MOD_TABLE (MOD_0F17) },
2684   /* 18 */
2685   { REG_TABLE (REG_0F18) },
2686   { "nopQ",             { Ev }, 0 },
2687   { PREFIX_TABLE (PREFIX_0F1A) },
2688   { PREFIX_TABLE (PREFIX_0F1B) },
2689   { PREFIX_TABLE (PREFIX_0F1C) },
2690   { "nopQ",             { Ev }, 0 },
2691   { PREFIX_TABLE (PREFIX_0F1E) },
2692   { "nopQ",             { Ev }, 0 },
2693   /* 20 */
2694   { "movZ",             { Rm, Cm }, 0 },
2695   { "movZ",             { Rm, Dm }, 0 },
2696   { "movZ",             { Cm, Rm }, 0 },
2697   { "movZ",             { Dm, Rm }, 0 },
2698   { MOD_TABLE (MOD_0F24) },
2699   { Bad_Opcode },
2700   { MOD_TABLE (MOD_0F26) },
2701   { Bad_Opcode },
2702   /* 28 */
2703   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2704   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2705   { PREFIX_TABLE (PREFIX_0F2A) },
2706   { PREFIX_TABLE (PREFIX_0F2B) },
2707   { PREFIX_TABLE (PREFIX_0F2C) },
2708   { PREFIX_TABLE (PREFIX_0F2D) },
2709   { PREFIX_TABLE (PREFIX_0F2E) },
2710   { PREFIX_TABLE (PREFIX_0F2F) },
2711   /* 30 */
2712   { "wrmsr",            { XX }, 0 },
2713   { "rdtsc",            { XX }, 0 },
2714   { "rdmsr",            { XX }, 0 },
2715   { "rdpmc",            { XX }, 0 },
2716   { "sysenter",         { SEP }, 0 },
2717   { "sysexit",          { SEP }, 0 },
2718   { Bad_Opcode },
2719   { "getsec",           { XX }, 0 },
2720   /* 38 */
2721   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2722   { Bad_Opcode },
2723   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2724   { Bad_Opcode },
2725   { Bad_Opcode },
2726   { Bad_Opcode },
2727   { Bad_Opcode },
2728   { Bad_Opcode },
2729   /* 40 */
2730   { "cmovoS",           { Gv, Ev }, 0 },
2731   { "cmovnoS",          { Gv, Ev }, 0 },
2732   { "cmovbS",           { Gv, Ev }, 0 },
2733   { "cmovaeS",          { Gv, Ev }, 0 },
2734   { "cmoveS",           { Gv, Ev }, 0 },
2735   { "cmovneS",          { Gv, Ev }, 0 },
2736   { "cmovbeS",          { Gv, Ev }, 0 },
2737   { "cmovaS",           { Gv, Ev }, 0 },
2738   /* 48 */
2739   { "cmovsS",           { Gv, Ev }, 0 },
2740   { "cmovnsS",          { Gv, Ev }, 0 },
2741   { "cmovpS",           { Gv, Ev }, 0 },
2742   { "cmovnpS",          { Gv, Ev }, 0 },
2743   { "cmovlS",           { Gv, Ev }, 0 },
2744   { "cmovgeS",          { Gv, Ev }, 0 },
2745   { "cmovleS",          { Gv, Ev }, 0 },
2746   { "cmovgS",           { Gv, Ev }, 0 },
2747   /* 50 */
2748   { MOD_TABLE (MOD_0F51) },
2749   { PREFIX_TABLE (PREFIX_0F51) },
2750   { PREFIX_TABLE (PREFIX_0F52) },
2751   { PREFIX_TABLE (PREFIX_0F53) },
2752   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2753   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2754   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2755   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2756   /* 58 */
2757   { PREFIX_TABLE (PREFIX_0F58) },
2758   { PREFIX_TABLE (PREFIX_0F59) },
2759   { PREFIX_TABLE (PREFIX_0F5A) },
2760   { PREFIX_TABLE (PREFIX_0F5B) },
2761   { PREFIX_TABLE (PREFIX_0F5C) },
2762   { PREFIX_TABLE (PREFIX_0F5D) },
2763   { PREFIX_TABLE (PREFIX_0F5E) },
2764   { PREFIX_TABLE (PREFIX_0F5F) },
2765   /* 60 */
2766   { PREFIX_TABLE (PREFIX_0F60) },
2767   { PREFIX_TABLE (PREFIX_0F61) },
2768   { PREFIX_TABLE (PREFIX_0F62) },
2769   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2770   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2771   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2772   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2773   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2774   /* 68 */
2775   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2776   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2777   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2778   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2779   { PREFIX_TABLE (PREFIX_0F6C) },
2780   { PREFIX_TABLE (PREFIX_0F6D) },
2781   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2782   { PREFIX_TABLE (PREFIX_0F6F) },
2783   /* 70 */
2784   { PREFIX_TABLE (PREFIX_0F70) },
2785   { REG_TABLE (REG_0F71) },
2786   { REG_TABLE (REG_0F72) },
2787   { REG_TABLE (REG_0F73) },
2788   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2789   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2790   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2791   { "emms",             { XX }, PREFIX_OPCODE },
2792   /* 78 */
2793   { PREFIX_TABLE (PREFIX_0F78) },
2794   { PREFIX_TABLE (PREFIX_0F79) },
2795   { Bad_Opcode },
2796   { Bad_Opcode },
2797   { PREFIX_TABLE (PREFIX_0F7C) },
2798   { PREFIX_TABLE (PREFIX_0F7D) },
2799   { PREFIX_TABLE (PREFIX_0F7E) },
2800   { PREFIX_TABLE (PREFIX_0F7F) },
2801   /* 80 */
2802   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2803   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2804   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2805   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2806   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2807   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2808   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2809   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2810   /* 88 */
2811   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2812   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2813   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2814   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2815   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2816   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2817   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2818   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2819   /* 90 */
2820   { "seto",             { Eb }, 0 },
2821   { "setno",            { Eb }, 0 },
2822   { "setb",             { Eb }, 0 },
2823   { "setae",            { Eb }, 0 },
2824   { "sete",             { Eb }, 0 },
2825   { "setne",            { Eb }, 0 },
2826   { "setbe",            { Eb }, 0 },
2827   { "seta",             { Eb }, 0 },
2828   /* 98 */
2829   { "sets",             { Eb }, 0 },
2830   { "setns",            { Eb }, 0 },
2831   { "setp",             { Eb }, 0 },
2832   { "setnp",            { Eb }, 0 },
2833   { "setl",             { Eb }, 0 },
2834   { "setge",            { Eb }, 0 },
2835   { "setle",            { Eb }, 0 },
2836   { "setg",             { Eb }, 0 },
2837   /* a0 */
2838   { "pushT",            { fs }, 0 },
2839   { "popT",             { fs }, 0 },
2840   { "cpuid",            { XX }, 0 },
2841   { "btS",              { Ev, Gv }, 0 },
2842   { "shldS",            { Ev, Gv, Ib }, 0 },
2843   { "shldS",            { Ev, Gv, CL }, 0 },
2844   { REG_TABLE (REG_0FA6) },
2845   { REG_TABLE (REG_0FA7) },
2846   /* a8 */
2847   { "pushT",            { gs }, 0 },
2848   { "popT",             { gs }, 0 },
2849   { "rsm",              { XX }, 0 },
2850   { "btsS",             { Evh1, Gv }, 0 },
2851   { "shrdS",            { Ev, Gv, Ib }, 0 },
2852   { "shrdS",            { Ev, Gv, CL }, 0 },
2853   { REG_TABLE (REG_0FAE) },
2854   { "imulS",            { Gv, Ev }, 0 },
2855   /* b0 */
2856   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2857   { "cmpxchgS",         { Evh1, Gv }, 0 },
2858   { MOD_TABLE (MOD_0FB2) },
2859   { "btrS",             { Evh1, Gv }, 0 },
2860   { MOD_TABLE (MOD_0FB4) },
2861   { MOD_TABLE (MOD_0FB5) },
2862   { "movz{bR|x}",       { Gv, Eb }, 0 },
2863   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2864   /* b8 */
2865   { PREFIX_TABLE (PREFIX_0FB8) },
2866   { "ud1S",             { Gv, Ev }, 0 },
2867   { REG_TABLE (REG_0FBA) },
2868   { "btcS",             { Evh1, Gv }, 0 },
2869   { PREFIX_TABLE (PREFIX_0FBC) },
2870   { PREFIX_TABLE (PREFIX_0FBD) },
2871   { "movs{bR|x}",       { Gv, Eb }, 0 },
2872   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2873   /* c0 */
2874   { "xaddB",            { Ebh1, Gb }, 0 },
2875   { "xaddS",            { Evh1, Gv }, 0 },
2876   { PREFIX_TABLE (PREFIX_0FC2) },
2877   { MOD_TABLE (MOD_0FC3) },
2878   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2879   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2880   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2881   { REG_TABLE (REG_0FC7) },
2882   /* c8 */
2883   { "bswap",            { RMeAX }, 0 },
2884   { "bswap",            { RMeCX }, 0 },
2885   { "bswap",            { RMeDX }, 0 },
2886   { "bswap",            { RMeBX }, 0 },
2887   { "bswap",            { RMeSP }, 0 },
2888   { "bswap",            { RMeBP }, 0 },
2889   { "bswap",            { RMeSI }, 0 },
2890   { "bswap",            { RMeDI }, 0 },
2891   /* d0 */
2892   { PREFIX_TABLE (PREFIX_0FD0) },
2893   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2894   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2895   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2896   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2897   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2898   { PREFIX_TABLE (PREFIX_0FD6) },
2899   { MOD_TABLE (MOD_0FD7) },
2900   /* d8 */
2901   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2902   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2903   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2904   { "pand",             { MX, EM }, PREFIX_OPCODE },
2905   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2906   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2907   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2908   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2909   /* e0 */
2910   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2911   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2912   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2913   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2914   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2915   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2916   { PREFIX_TABLE (PREFIX_0FE6) },
2917   { PREFIX_TABLE (PREFIX_0FE7) },
2918   /* e8 */
2919   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2920   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2921   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2922   { "por",              { MX, EM }, PREFIX_OPCODE },
2923   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2924   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2925   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2926   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2927   /* f0 */
2928   { PREFIX_TABLE (PREFIX_0FF0) },
2929   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2930   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2931   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2932   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2933   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2934   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2935   { PREFIX_TABLE (PREFIX_0FF7) },
2936   /* f8 */
2937   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2938   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2939   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2940   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2941   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2942   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2943   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2944   { "ud0S",             { Gv, Ev }, 0 },
2945 };
2946
2947 static const unsigned char onebyte_has_modrm[256] = {
2948   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2949   /*       -------------------------------        */
2950   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2951   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2952   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2953   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2954   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2955   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2956   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2957   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2958   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2959   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2960   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2961   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2962   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2963   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2964   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2965   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2966   /*       -------------------------------        */
2967   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2968 };
2969
2970 static const unsigned char twobyte_has_modrm[256] = {
2971   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2972   /*       -------------------------------        */
2973   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2974   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2975   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2976   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2977   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2978   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2979   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2980   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2981   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2982   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2983   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2984   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2985   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2986   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2987   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2988   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2989   /*       -------------------------------        */
2990   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2991 };
2992
2993 static char obuf[100];
2994 static char *obufp;
2995 static char *mnemonicendp;
2996 static char scratchbuf[100];
2997 static unsigned char *start_codep;
2998 static unsigned char *insn_codep;
2999 static unsigned char *codep;
3000 static unsigned char *end_codep;
3001 static int last_lock_prefix;
3002 static int last_repz_prefix;
3003 static int last_repnz_prefix;
3004 static int last_data_prefix;
3005 static int last_addr_prefix;
3006 static int last_rex_prefix;
3007 static int last_seg_prefix;
3008 static int fwait_prefix;
3009 /* The active segment register prefix.  */
3010 static int active_seg_prefix;
3011 #define MAX_CODE_LENGTH 15
3012 /* We can up to 14 prefixes since the maximum instruction length is
3013    15bytes.  */
3014 static int all_prefixes[MAX_CODE_LENGTH - 1];
3015 static disassemble_info *the_info;
3016 static struct
3017   {
3018     int mod;
3019     int reg;
3020     int rm;
3021   }
3022 modrm;
3023 static unsigned char need_modrm;
3024 static struct
3025   {
3026     int scale;
3027     int index;
3028     int base;
3029   }
3030 sib;
3031 static struct
3032   {
3033     int register_specifier;
3034     int length;
3035     int prefix;
3036     int w;
3037     int evex;
3038     int r;
3039     int v;
3040     int mask_register_specifier;
3041     int zeroing;
3042     int ll;
3043     int b;
3044   }
3045 vex;
3046 static unsigned char need_vex;
3047 static unsigned char need_vex_reg;
3048 static unsigned char vex_w_done;
3049
3050 struct op
3051   {
3052     const char *name;
3053     unsigned int len;
3054   };
3055
3056 /* If we are accessing mod/rm/reg without need_modrm set, then the
3057    values are stale.  Hitting this abort likely indicates that you
3058    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3059 #define MODRM_CHECK  if (!need_modrm) abort ()
3060
3061 static const char **names64;
3062 static const char **names32;
3063 static const char **names16;
3064 static const char **names8;
3065 static const char **names8rex;
3066 static const char **names_seg;
3067 static const char *index64;
3068 static const char *index32;
3069 static const char **index16;
3070 static const char **names_bnd;
3071
3072 static const char *intel_names64[] = {
3073   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3074   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3075 };
3076 static const char *intel_names32[] = {
3077   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3078   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3079 };
3080 static const char *intel_names16[] = {
3081   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3082   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3083 };
3084 static const char *intel_names8[] = {
3085   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3086 };
3087 static const char *intel_names8rex[] = {
3088   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3089   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3090 };
3091 static const char *intel_names_seg[] = {
3092   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3093 };
3094 static const char *intel_index64 = "riz";
3095 static const char *intel_index32 = "eiz";
3096 static const char *intel_index16[] = {
3097   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3098 };
3099
3100 static const char *att_names64[] = {
3101   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3102   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3103 };
3104 static const char *att_names32[] = {
3105   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3106   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3107 };
3108 static const char *att_names16[] = {
3109   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3110   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3111 };
3112 static const char *att_names8[] = {
3113   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3114 };
3115 static const char *att_names8rex[] = {
3116   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3117   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3118 };
3119 static const char *att_names_seg[] = {
3120   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3121 };
3122 static const char *att_index64 = "%riz";
3123 static const char *att_index32 = "%eiz";
3124 static const char *att_index16[] = {
3125   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3126 };
3127
3128 static const char **names_mm;
3129 static const char *intel_names_mm[] = {
3130   "mm0", "mm1", "mm2", "mm3",
3131   "mm4", "mm5", "mm6", "mm7"
3132 };
3133 static const char *att_names_mm[] = {
3134   "%mm0", "%mm1", "%mm2", "%mm3",
3135   "%mm4", "%mm5", "%mm6", "%mm7"
3136 };
3137
3138 static const char *intel_names_bnd[] = {
3139   "bnd0", "bnd1", "bnd2", "bnd3"
3140 };
3141
3142 static const char *att_names_bnd[] = {
3143   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3144 };
3145
3146 static const char **names_xmm;
3147 static const char *intel_names_xmm[] = {
3148   "xmm0", "xmm1", "xmm2", "xmm3",
3149   "xmm4", "xmm5", "xmm6", "xmm7",
3150   "xmm8", "xmm9", "xmm10", "xmm11",
3151   "xmm12", "xmm13", "xmm14", "xmm15",
3152   "xmm16", "xmm17", "xmm18", "xmm19",
3153   "xmm20", "xmm21", "xmm22", "xmm23",
3154   "xmm24", "xmm25", "xmm26", "xmm27",
3155   "xmm28", "xmm29", "xmm30", "xmm31"
3156 };
3157 static const char *att_names_xmm[] = {
3158   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3159   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3160   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3161   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3162   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3163   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3164   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3165   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3166 };
3167
3168 static const char **names_ymm;
3169 static const char *intel_names_ymm[] = {
3170   "ymm0", "ymm1", "ymm2", "ymm3",
3171   "ymm4", "ymm5", "ymm6", "ymm7",
3172   "ymm8", "ymm9", "ymm10", "ymm11",
3173   "ymm12", "ymm13", "ymm14", "ymm15",
3174   "ymm16", "ymm17", "ymm18", "ymm19",
3175   "ymm20", "ymm21", "ymm22", "ymm23",
3176   "ymm24", "ymm25", "ymm26", "ymm27",
3177   "ymm28", "ymm29", "ymm30", "ymm31"
3178 };
3179 static const char *att_names_ymm[] = {
3180   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3181   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3182   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3183   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3184   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3185   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3186   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3187   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3188 };
3189
3190 static const char **names_zmm;
3191 static const char *intel_names_zmm[] = {
3192   "zmm0", "zmm1", "zmm2", "zmm3",
3193   "zmm4", "zmm5", "zmm6", "zmm7",
3194   "zmm8", "zmm9", "zmm10", "zmm11",
3195   "zmm12", "zmm13", "zmm14", "zmm15",
3196   "zmm16", "zmm17", "zmm18", "zmm19",
3197   "zmm20", "zmm21", "zmm22", "zmm23",
3198   "zmm24", "zmm25", "zmm26", "zmm27",
3199   "zmm28", "zmm29", "zmm30", "zmm31"
3200 };
3201 static const char *att_names_zmm[] = {
3202   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3203   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3204   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3205   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3206   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3207   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3208   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3209   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3210 };
3211
3212 static const char **names_mask;
3213 static const char *intel_names_mask[] = {
3214   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3215 };
3216 static const char *att_names_mask[] = {
3217   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3218 };
3219
3220 static const char *names_rounding[] =
3221 {
3222   "{rn-sae}",
3223   "{rd-sae}",
3224   "{ru-sae}",
3225   "{rz-sae}"
3226 };
3227
3228 static const struct dis386 reg_table[][8] = {
3229   /* REG_80 */
3230   {
3231     { "addA",   { Ebh1, Ib }, 0 },
3232     { "orA",    { Ebh1, Ib }, 0 },
3233     { "adcA",   { Ebh1, Ib }, 0 },
3234     { "sbbA",   { Ebh1, Ib }, 0 },
3235     { "andA",   { Ebh1, Ib }, 0 },
3236     { "subA",   { Ebh1, Ib }, 0 },
3237     { "xorA",   { Ebh1, Ib }, 0 },
3238     { "cmpA",   { Eb, Ib }, 0 },
3239   },
3240   /* REG_81 */
3241   {
3242     { "addQ",   { Evh1, Iv }, 0 },
3243     { "orQ",    { Evh1, Iv }, 0 },
3244     { "adcQ",   { Evh1, Iv }, 0 },
3245     { "sbbQ",   { Evh1, Iv }, 0 },
3246     { "andQ",   { Evh1, Iv }, 0 },
3247     { "subQ",   { Evh1, Iv }, 0 },
3248     { "xorQ",   { Evh1, Iv }, 0 },
3249     { "cmpQ",   { Ev, Iv }, 0 },
3250   },
3251   /* REG_83 */
3252   {
3253     { "addQ",   { Evh1, sIb }, 0 },
3254     { "orQ",    { Evh1, sIb }, 0 },
3255     { "adcQ",   { Evh1, sIb }, 0 },
3256     { "sbbQ",   { Evh1, sIb }, 0 },
3257     { "andQ",   { Evh1, sIb }, 0 },
3258     { "subQ",   { Evh1, sIb }, 0 },
3259     { "xorQ",   { Evh1, sIb }, 0 },
3260     { "cmpQ",   { Ev, sIb }, 0 },
3261   },
3262   /* REG_8F */
3263   {
3264     { "popU",   { stackEv }, 0 },
3265     { XOP_8F_TABLE (XOP_09) },
3266     { Bad_Opcode },
3267     { Bad_Opcode },
3268     { Bad_Opcode },
3269     { XOP_8F_TABLE (XOP_09) },
3270   },
3271   /* REG_C0 */
3272   {
3273     { "rolA",   { Eb, Ib }, 0 },
3274     { "rorA",   { Eb, Ib }, 0 },
3275     { "rclA",   { Eb, Ib }, 0 },
3276     { "rcrA",   { Eb, Ib }, 0 },
3277     { "shlA",   { Eb, Ib }, 0 },
3278     { "shrA",   { Eb, Ib }, 0 },
3279     { "shlA",   { Eb, Ib }, 0 },
3280     { "sarA",   { Eb, Ib }, 0 },
3281   },
3282   /* REG_C1 */
3283   {
3284     { "rolQ",   { Ev, Ib }, 0 },
3285     { "rorQ",   { Ev, Ib }, 0 },
3286     { "rclQ",   { Ev, Ib }, 0 },
3287     { "rcrQ",   { Ev, Ib }, 0 },
3288     { "shlQ",   { Ev, Ib }, 0 },
3289     { "shrQ",   { Ev, Ib }, 0 },
3290     { "shlQ",   { Ev, Ib }, 0 },
3291     { "sarQ",   { Ev, Ib }, 0 },
3292   },
3293   /* REG_C6 */
3294   {
3295     { "movA",   { Ebh3, Ib }, 0 },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { MOD_TABLE (MOD_C6_REG_7) },
3303   },
3304   /* REG_C7 */
3305   {
3306     { "movQ",   { Evh3, Iv }, 0 },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { Bad_Opcode },
3313     { MOD_TABLE (MOD_C7_REG_7) },
3314   },
3315   /* REG_D0 */
3316   {
3317     { "rolA",   { Eb, I1 }, 0 },
3318     { "rorA",   { Eb, I1 }, 0 },
3319     { "rclA",   { Eb, I1 }, 0 },
3320     { "rcrA",   { Eb, I1 }, 0 },
3321     { "shlA",   { Eb, I1 }, 0 },
3322     { "shrA",   { Eb, I1 }, 0 },
3323     { "shlA",   { Eb, I1 }, 0 },
3324     { "sarA",   { Eb, I1 }, 0 },
3325   },
3326   /* REG_D1 */
3327   {
3328     { "rolQ",   { Ev, I1 }, 0 },
3329     { "rorQ",   { Ev, I1 }, 0 },
3330     { "rclQ",   { Ev, I1 }, 0 },
3331     { "rcrQ",   { Ev, I1 }, 0 },
3332     { "shlQ",   { Ev, I1 }, 0 },
3333     { "shrQ",   { Ev, I1 }, 0 },
3334     { "shlQ",   { Ev, I1 }, 0 },
3335     { "sarQ",   { Ev, I1 }, 0 },
3336   },
3337   /* REG_D2 */
3338   {
3339     { "rolA",   { Eb, CL }, 0 },
3340     { "rorA",   { Eb, CL }, 0 },
3341     { "rclA",   { Eb, CL }, 0 },
3342     { "rcrA",   { Eb, CL }, 0 },
3343     { "shlA",   { Eb, CL }, 0 },
3344     { "shrA",   { Eb, CL }, 0 },
3345     { "shlA",   { Eb, CL }, 0 },
3346     { "sarA",   { Eb, CL }, 0 },
3347   },
3348   /* REG_D3 */
3349   {
3350     { "rolQ",   { Ev, CL }, 0 },
3351     { "rorQ",   { Ev, CL }, 0 },
3352     { "rclQ",   { Ev, CL }, 0 },
3353     { "rcrQ",   { Ev, CL }, 0 },
3354     { "shlQ",   { Ev, CL }, 0 },
3355     { "shrQ",   { Ev, CL }, 0 },
3356     { "shlQ",   { Ev, CL }, 0 },
3357     { "sarQ",   { Ev, CL }, 0 },
3358   },
3359   /* REG_F6 */
3360   {
3361     { "testA",  { Eb, Ib }, 0 },
3362     { "testA",  { Eb, Ib }, 0 },
3363     { "notA",   { Ebh1 }, 0 },
3364     { "negA",   { Ebh1 }, 0 },
3365     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3366     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3367     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3368     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3369   },
3370   /* REG_F7 */
3371   {
3372     { "testQ",  { Ev, Iv }, 0 },
3373     { "testQ",  { Ev, Iv }, 0 },
3374     { "notQ",   { Evh1 }, 0 },
3375     { "negQ",   { Evh1 }, 0 },
3376     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3377     { "imulQ",  { Ev }, 0 },
3378     { "divQ",   { Ev }, 0 },
3379     { "idivQ",  { Ev }, 0 },
3380   },
3381   /* REG_FE */
3382   {
3383     { "incA",   { Ebh1 }, 0 },
3384     { "decA",   { Ebh1 }, 0 },
3385   },
3386   /* REG_FF */
3387   {
3388     { "incQ",   { Evh1 }, 0 },
3389     { "decQ",   { Evh1 }, 0 },
3390     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3391     { MOD_TABLE (MOD_FF_REG_3) },
3392     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3393     { MOD_TABLE (MOD_FF_REG_5) },
3394     { "pushU",  { stackEv }, 0 },
3395     { Bad_Opcode },
3396   },
3397   /* REG_0F00 */
3398   {
3399     { "sldtD",  { Sv }, 0 },
3400     { "strD",   { Sv }, 0 },
3401     { "lldt",   { Ew }, 0 },
3402     { "ltr",    { Ew }, 0 },
3403     { "verr",   { Ew }, 0 },
3404     { "verw",   { Ew }, 0 },
3405     { Bad_Opcode },
3406     { Bad_Opcode },
3407   },
3408   /* REG_0F01 */
3409   {
3410     { MOD_TABLE (MOD_0F01_REG_0) },
3411     { MOD_TABLE (MOD_0F01_REG_1) },
3412     { MOD_TABLE (MOD_0F01_REG_2) },
3413     { MOD_TABLE (MOD_0F01_REG_3) },
3414     { "smswD",  { Sv }, 0 },
3415     { MOD_TABLE (MOD_0F01_REG_5) },
3416     { "lmsw",   { Ew }, 0 },
3417     { MOD_TABLE (MOD_0F01_REG_7) },
3418   },
3419   /* REG_0F0D */
3420   {
3421     { "prefetch",       { Mb }, 0 },
3422     { "prefetchw",      { Mb }, 0 },
3423     { "prefetchwt1",    { Mb }, 0 },
3424     { "prefetch",       { Mb }, 0 },
3425     { "prefetch",       { Mb }, 0 },
3426     { "prefetch",       { Mb }, 0 },
3427     { "prefetch",       { Mb }, 0 },
3428     { "prefetch",       { Mb }, 0 },
3429   },
3430   /* REG_0F18 */
3431   {
3432     { MOD_TABLE (MOD_0F18_REG_0) },
3433     { MOD_TABLE (MOD_0F18_REG_1) },
3434     { MOD_TABLE (MOD_0F18_REG_2) },
3435     { MOD_TABLE (MOD_0F18_REG_3) },
3436     { MOD_TABLE (MOD_0F18_REG_4) },
3437     { MOD_TABLE (MOD_0F18_REG_5) },
3438     { MOD_TABLE (MOD_0F18_REG_6) },
3439     { MOD_TABLE (MOD_0F18_REG_7) },
3440   },
3441   /* REG_0F1C_P_0_MOD_0 */
3442   {
3443     { "cldemote",       { Mb }, 0 },
3444     { "nopQ",           { Ev }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449     { "nopQ",           { Ev }, 0 },
3450     { "nopQ",           { Ev }, 0 },
3451   },
3452   /* REG_0F1E_P_1_MOD_3 */
3453   {
3454     { "nopQ",           { Ev }, 0 },
3455     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { "nopQ",           { Ev }, 0 },
3460     { "nopQ",           { Ev }, 0 },
3461     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3462   },
3463   /* REG_0F71 */
3464   {
3465     { Bad_Opcode },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_0F71_REG_2) },
3468     { Bad_Opcode },
3469     { MOD_TABLE (MOD_0F71_REG_4) },
3470     { Bad_Opcode },
3471     { MOD_TABLE (MOD_0F71_REG_6) },
3472   },
3473   /* REG_0F72 */
3474   {
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_0F72_REG_2) },
3478     { Bad_Opcode },
3479     { MOD_TABLE (MOD_0F72_REG_4) },
3480     { Bad_Opcode },
3481     { MOD_TABLE (MOD_0F72_REG_6) },
3482   },
3483   /* REG_0F73 */
3484   {
3485     { Bad_Opcode },
3486     { Bad_Opcode },
3487     { MOD_TABLE (MOD_0F73_REG_2) },
3488     { MOD_TABLE (MOD_0F73_REG_3) },
3489     { Bad_Opcode },
3490     { Bad_Opcode },
3491     { MOD_TABLE (MOD_0F73_REG_6) },
3492     { MOD_TABLE (MOD_0F73_REG_7) },
3493   },
3494   /* REG_0FA6 */
3495   {
3496     { "montmul",        { { OP_0f07, 0 } }, 0 },
3497     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3498     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3499   },
3500   /* REG_0FA7 */
3501   {
3502     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3503     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3504     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3505     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3506     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3507     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3508   },
3509   /* REG_0FAE */
3510   {
3511     { MOD_TABLE (MOD_0FAE_REG_0) },
3512     { MOD_TABLE (MOD_0FAE_REG_1) },
3513     { MOD_TABLE (MOD_0FAE_REG_2) },
3514     { MOD_TABLE (MOD_0FAE_REG_3) },
3515     { MOD_TABLE (MOD_0FAE_REG_4) },
3516     { MOD_TABLE (MOD_0FAE_REG_5) },
3517     { MOD_TABLE (MOD_0FAE_REG_6) },
3518     { MOD_TABLE (MOD_0FAE_REG_7) },
3519   },
3520   /* REG_0FBA */
3521   {
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { "btQ",    { Ev, Ib }, 0 },
3527     { "btsQ",   { Evh1, Ib }, 0 },
3528     { "btrQ",   { Evh1, Ib }, 0 },
3529     { "btcQ",   { Evh1, Ib }, 0 },
3530   },
3531   /* REG_0FC7 */
3532   {
3533     { Bad_Opcode },
3534     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_0FC7_REG_3) },
3537     { MOD_TABLE (MOD_0FC7_REG_4) },
3538     { MOD_TABLE (MOD_0FC7_REG_5) },
3539     { MOD_TABLE (MOD_0FC7_REG_6) },
3540     { MOD_TABLE (MOD_0FC7_REG_7) },
3541   },
3542   /* REG_VEX_0F71 */
3543   {
3544     { Bad_Opcode },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3547     { Bad_Opcode },
3548     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3549     { Bad_Opcode },
3550     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3551   },
3552   /* REG_VEX_0F72 */
3553   {
3554     { Bad_Opcode },
3555     { Bad_Opcode },
3556     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3557     { Bad_Opcode },
3558     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3559     { Bad_Opcode },
3560     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3561   },
3562   /* REG_VEX_0F73 */
3563   {
3564     { Bad_Opcode },
3565     { Bad_Opcode },
3566     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3567     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3568     { Bad_Opcode },
3569     { Bad_Opcode },
3570     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3571     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3572   },
3573   /* REG_VEX_0FAE */
3574   {
3575     { Bad_Opcode },
3576     { Bad_Opcode },
3577     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3578     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3579   },
3580   /* REG_VEX_0F38F3 */
3581   {
3582     { Bad_Opcode },
3583     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3584     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3585     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3586   },
3587   /* REG_XOP_LWPCB */
3588   {
3589     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3590     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3591   },
3592   /* REG_XOP_LWP */
3593   {
3594     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3595     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3596   },
3597   /* REG_XOP_TBM_01 */
3598   {
3599     { Bad_Opcode },
3600     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3601     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3602     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3603     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3604     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3605     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3606     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3607   },
3608   /* REG_XOP_TBM_02 */
3609   {
3610     { Bad_Opcode },
3611     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3617   },
3618
3619 #include "i386-dis-evex-reg.h"
3620 };
3621
3622 static const struct dis386 prefix_table[][4] = {
3623   /* PREFIX_90 */
3624   {
3625     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3626     { "pause", { XX }, 0 },
3627     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3628     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3629   },
3630
3631   /* PREFIX_0F01_REG_3_MOD_1 */
3632   {
3633     { "vmmcall",        { Skip_MODRM }, 0 },
3634     { "vmgexit",        { Skip_MODRM }, 0 },
3635     { Bad_Opcode },
3636     { "vmgexit",        { Skip_MODRM }, 0 },
3637   },
3638
3639   /* PREFIX_0F01_REG_5_MOD_0 */
3640   {
3641     { Bad_Opcode },
3642     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3643   },
3644
3645   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3646   {
3647     { Bad_Opcode },
3648     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3649   },
3650
3651   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3652   {
3653     { Bad_Opcode },
3654     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3655   },
3656
3657   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3658   {
3659     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3660     { "mcommit",        { Skip_MODRM }, 0 },
3661   },
3662
3663   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3664   {
3665     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3666   },
3667
3668   /* PREFIX_0F09 */
3669   {
3670     { "wbinvd",   { XX }, 0 },
3671     { "wbnoinvd", { XX }, 0 },
3672   },
3673
3674   /* PREFIX_0F10 */
3675   {
3676     { "movups", { XM, EXx }, PREFIX_OPCODE },
3677     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3678     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3679     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3680   },
3681
3682   /* PREFIX_0F11 */
3683   {
3684     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3685     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3686     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3687     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3688   },
3689
3690   /* PREFIX_0F12 */
3691   {
3692     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3693     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3694     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3695     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3696   },
3697
3698   /* PREFIX_0F16 */
3699   {
3700     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3701     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3702     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3703   },
3704
3705   /* PREFIX_0F1A */
3706   {
3707     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3708     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3709     { "bndmov", { Gbnd, Ebnd }, 0 },
3710     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3711   },
3712
3713   /* PREFIX_0F1B */
3714   {
3715     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3716     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3717     { "bndmov", { EbndS, Gbnd }, 0 },
3718     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3719   },
3720
3721   /* PREFIX_0F1C */
3722   {
3723     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3724     { "nopQ",   { Ev }, PREFIX_OPCODE },
3725     { "nopQ",   { Ev }, PREFIX_OPCODE },
3726     { "nopQ",   { Ev }, PREFIX_OPCODE },
3727   },
3728
3729   /* PREFIX_0F1E */
3730   {
3731     { "nopQ",   { Ev }, PREFIX_OPCODE },
3732     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3733     { "nopQ",   { Ev }, PREFIX_OPCODE },
3734     { "nopQ",   { Ev }, PREFIX_OPCODE },
3735   },
3736
3737   /* PREFIX_0F2A */
3738   {
3739     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3740     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3741     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3742     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3743   },
3744
3745   /* PREFIX_0F2B */
3746   {
3747     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3748     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3749     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3750     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3751   },
3752
3753   /* PREFIX_0F2C */
3754   {
3755     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3756     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3757     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3758     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3759   },
3760
3761   /* PREFIX_0F2D */
3762   {
3763     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3764     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3765     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3766     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3767   },
3768
3769   /* PREFIX_0F2E */
3770   {
3771     { "ucomiss",{ XM, EXd }, 0 },
3772     { Bad_Opcode },
3773     { "ucomisd",{ XM, EXq }, 0 },
3774   },
3775
3776   /* PREFIX_0F2F */
3777   {
3778     { "comiss", { XM, EXd }, 0 },
3779     { Bad_Opcode },
3780     { "comisd", { XM, EXq }, 0 },
3781   },
3782
3783   /* PREFIX_0F51 */
3784   {
3785     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3786     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3787     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3788     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3789   },
3790
3791   /* PREFIX_0F52 */
3792   {
3793     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3794     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_0F53 */
3798   {
3799     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3800     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3801   },
3802
3803   /* PREFIX_0F58 */
3804   {
3805     { "addps", { XM, EXx }, PREFIX_OPCODE },
3806     { "addss", { XM, EXd }, PREFIX_OPCODE },
3807     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3808     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3809   },
3810
3811   /* PREFIX_0F59 */
3812   {
3813     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3814     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3815     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3816     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3817   },
3818
3819   /* PREFIX_0F5A */
3820   {
3821     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3822     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3823     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3824     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3825   },
3826
3827   /* PREFIX_0F5B */
3828   {
3829     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3830     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3831     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F5C */
3835   {
3836     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3837     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3838     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3839     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F5D */
3843   {
3844     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3845     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3846     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3847     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3848   },
3849
3850   /* PREFIX_0F5E */
3851   {
3852     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3853     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3854     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3855     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F5F */
3859   {
3860     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3861     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3862     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3863     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3864   },
3865
3866   /* PREFIX_0F60 */
3867   {
3868     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3869     { Bad_Opcode },
3870     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3871   },
3872
3873   /* PREFIX_0F61 */
3874   {
3875     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3876     { Bad_Opcode },
3877     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3878   },
3879
3880   /* PREFIX_0F62 */
3881   {
3882     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3883     { Bad_Opcode },
3884     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3885   },
3886
3887   /* PREFIX_0F6C */
3888   {
3889     { Bad_Opcode },
3890     { Bad_Opcode },
3891     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3892   },
3893
3894   /* PREFIX_0F6D */
3895   {
3896     { Bad_Opcode },
3897     { Bad_Opcode },
3898     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3899   },
3900
3901   /* PREFIX_0F6F */
3902   {
3903     { "movq",   { MX, EM }, PREFIX_OPCODE },
3904     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3905     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3906   },
3907
3908   /* PREFIX_0F70 */
3909   {
3910     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3911     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3912     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3913     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3914   },
3915
3916   /* PREFIX_0F73_REG_3 */
3917   {
3918     { Bad_Opcode },
3919     { Bad_Opcode },
3920     { "psrldq", { XS, Ib }, 0 },
3921   },
3922
3923   /* PREFIX_0F73_REG_7 */
3924   {
3925     { Bad_Opcode },
3926     { Bad_Opcode },
3927     { "pslldq", { XS, Ib }, 0 },
3928   },
3929
3930   /* PREFIX_0F78 */
3931   {
3932     {"vmread",  { Em, Gm }, 0 },
3933     { Bad_Opcode },
3934     {"extrq",   { XS, Ib, Ib }, 0 },
3935     {"insertq", { XM, XS, Ib, Ib }, 0 },
3936   },
3937
3938   /* PREFIX_0F79 */
3939   {
3940     {"vmwrite", { Gm, Em }, 0 },
3941     { Bad_Opcode },
3942     {"extrq",   { XM, XS }, 0 },
3943     {"insertq", { XM, XS }, 0 },
3944   },
3945
3946   /* PREFIX_0F7C */
3947   {
3948     { Bad_Opcode },
3949     { Bad_Opcode },
3950     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3951     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3952   },
3953
3954   /* PREFIX_0F7D */
3955   {
3956     { Bad_Opcode },
3957     { Bad_Opcode },
3958     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3959     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3960   },
3961
3962   /* PREFIX_0F7E */
3963   {
3964     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3965     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3966     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3967   },
3968
3969   /* PREFIX_0F7F */
3970   {
3971     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3972     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3973     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3974   },
3975
3976   /* PREFIX_0FAE_REG_0_MOD_3 */
3977   {
3978     { Bad_Opcode },
3979     { "rdfsbase", { Ev }, 0 },
3980   },
3981
3982   /* PREFIX_0FAE_REG_1_MOD_3 */
3983   {
3984     { Bad_Opcode },
3985     { "rdgsbase", { Ev }, 0 },
3986   },
3987
3988   /* PREFIX_0FAE_REG_2_MOD_3 */
3989   {
3990     { Bad_Opcode },
3991     { "wrfsbase", { Ev }, 0 },
3992   },
3993
3994   /* PREFIX_0FAE_REG_3_MOD_3 */
3995   {
3996     { Bad_Opcode },
3997     { "wrgsbase", { Ev }, 0 },
3998   },
3999
4000   /* PREFIX_0FAE_REG_4_MOD_0 */
4001   {
4002     { "xsave",  { FXSAVE }, 0 },
4003     { "ptwrite%LQ", { Edq }, 0 },
4004   },
4005
4006   /* PREFIX_0FAE_REG_4_MOD_3 */
4007   {
4008     { Bad_Opcode },
4009     { "ptwrite%LQ", { Edq }, 0 },
4010   },
4011
4012   /* PREFIX_0FAE_REG_5_MOD_0 */
4013   {
4014     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4015   },
4016
4017   /* PREFIX_0FAE_REG_5_MOD_3 */
4018   {
4019     { "lfence",         { Skip_MODRM }, 0 },
4020     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4021   },
4022
4023   /* PREFIX_0FAE_REG_6_MOD_0 */
4024   {
4025     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4026     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4027     { "clwb",   { Mb }, PREFIX_OPCODE },
4028   },
4029
4030   /* PREFIX_0FAE_REG_6_MOD_3 */
4031   {
4032     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4033     { "umonitor",       { Eva }, PREFIX_OPCODE },
4034     { "tpause", { Edq }, PREFIX_OPCODE },
4035     { "umwait", { Edq }, PREFIX_OPCODE },
4036   },
4037
4038   /* PREFIX_0FAE_REG_7_MOD_0 */
4039   {
4040     { "clflush",        { Mb }, 0 },
4041     { Bad_Opcode },
4042     { "clflushopt",     { Mb }, 0 },
4043   },
4044
4045   /* PREFIX_0FB8 */
4046   {
4047     { Bad_Opcode },
4048     { "popcntS", { Gv, Ev }, 0 },
4049   },
4050
4051   /* PREFIX_0FBC */
4052   {
4053     { "bsfS",   { Gv, Ev }, 0 },
4054     { "tzcntS", { Gv, Ev }, 0 },
4055     { "bsfS",   { Gv, Ev }, 0 },
4056   },
4057
4058   /* PREFIX_0FBD */
4059   {
4060     { "bsrS",   { Gv, Ev }, 0 },
4061     { "lzcntS", { Gv, Ev }, 0 },
4062     { "bsrS",   { Gv, Ev }, 0 },
4063   },
4064
4065   /* PREFIX_0FC2 */
4066   {
4067     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4068     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4069     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4070     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4071   },
4072
4073   /* PREFIX_0FC3_MOD_0 */
4074   {
4075     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4076   },
4077
4078   /* PREFIX_0FC7_REG_6_MOD_0 */
4079   {
4080     { "vmptrld",{ Mq }, 0 },
4081     { "vmxon",  { Mq }, 0 },
4082     { "vmclear",{ Mq }, 0 },
4083   },
4084
4085   /* PREFIX_0FC7_REG_6_MOD_3 */
4086   {
4087     { "rdrand", { Ev }, 0 },
4088     { Bad_Opcode },
4089     { "rdrand", { Ev }, 0 }
4090   },
4091
4092   /* PREFIX_0FC7_REG_7_MOD_3 */
4093   {
4094     { "rdseed", { Ev }, 0 },
4095     { "rdpid",  { Em }, 0 },
4096     { "rdseed", { Ev }, 0 },
4097   },
4098
4099   /* PREFIX_0FD0 */
4100   {
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { "addsubpd", { XM, EXx }, 0 },
4104     { "addsubps", { XM, EXx }, 0 },
4105   },
4106
4107   /* PREFIX_0FD6 */
4108   {
4109     { Bad_Opcode },
4110     { "movq2dq",{ XM, MS }, 0 },
4111     { "movq",   { EXqS, XM }, 0 },
4112     { "movdq2q",{ MX, XS }, 0 },
4113   },
4114
4115   /* PREFIX_0FE6 */
4116   {
4117     { Bad_Opcode },
4118     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4119     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4120     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4121   },
4122
4123   /* PREFIX_0FE7 */
4124   {
4125     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4126     { Bad_Opcode },
4127     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4128   },
4129
4130   /* PREFIX_0FF0 */
4131   {
4132     { Bad_Opcode },
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4136   },
4137
4138   /* PREFIX_0FF7 */
4139   {
4140     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4141     { Bad_Opcode },
4142     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4143   },
4144
4145   /* PREFIX_0F3810 */
4146   {
4147     { Bad_Opcode },
4148     { Bad_Opcode },
4149     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4150   },
4151
4152   /* PREFIX_0F3814 */
4153   {
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4157   },
4158
4159   /* PREFIX_0F3815 */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4164   },
4165
4166   /* PREFIX_0F3817 */
4167   {
4168     { Bad_Opcode },
4169     { Bad_Opcode },
4170     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4171   },
4172
4173   /* PREFIX_0F3820 */
4174   {
4175     { Bad_Opcode },
4176     { Bad_Opcode },
4177     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4178   },
4179
4180   /* PREFIX_0F3821 */
4181   {
4182     { Bad_Opcode },
4183     { Bad_Opcode },
4184     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_0F3822 */
4188   {
4189     { Bad_Opcode },
4190     { Bad_Opcode },
4191     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4192   },
4193
4194   /* PREFIX_0F3823 */
4195   {
4196     { Bad_Opcode },
4197     { Bad_Opcode },
4198     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4199   },
4200
4201   /* PREFIX_0F3824 */
4202   {
4203     { Bad_Opcode },
4204     { Bad_Opcode },
4205     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4206   },
4207
4208   /* PREFIX_0F3825 */
4209   {
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4213   },
4214
4215   /* PREFIX_0F3828 */
4216   {
4217     { Bad_Opcode },
4218     { Bad_Opcode },
4219     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4220   },
4221
4222   /* PREFIX_0F3829 */
4223   {
4224     { Bad_Opcode },
4225     { Bad_Opcode },
4226     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4227   },
4228
4229   /* PREFIX_0F382A */
4230   {
4231     { Bad_Opcode },
4232     { Bad_Opcode },
4233     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4234   },
4235
4236   /* PREFIX_0F382B */
4237   {
4238     { Bad_Opcode },
4239     { Bad_Opcode },
4240     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4241   },
4242
4243   /* PREFIX_0F3830 */
4244   {
4245     { Bad_Opcode },
4246     { Bad_Opcode },
4247     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4248   },
4249
4250   /* PREFIX_0F3831 */
4251   {
4252     { Bad_Opcode },
4253     { Bad_Opcode },
4254     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4255   },
4256
4257   /* PREFIX_0F3832 */
4258   {
4259     { Bad_Opcode },
4260     { Bad_Opcode },
4261     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4262   },
4263
4264   /* PREFIX_0F3833 */
4265   {
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4269   },
4270
4271   /* PREFIX_0F3834 */
4272   {
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4276   },
4277
4278   /* PREFIX_0F3835 */
4279   {
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4283   },
4284
4285   /* PREFIX_0F3837 */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4290   },
4291
4292   /* PREFIX_0F3838 */
4293   {
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4297   },
4298
4299   /* PREFIX_0F3839 */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4304   },
4305
4306   /* PREFIX_0F383A */
4307   {
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4311   },
4312
4313   /* PREFIX_0F383B */
4314   {
4315     { Bad_Opcode },
4316     { Bad_Opcode },
4317     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4318   },
4319
4320   /* PREFIX_0F383C */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4325   },
4326
4327   /* PREFIX_0F383D */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4332   },
4333
4334   /* PREFIX_0F383E */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4339   },
4340
4341   /* PREFIX_0F383F */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4346   },
4347
4348   /* PREFIX_0F3840 */
4349   {
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4353   },
4354
4355   /* PREFIX_0F3841 */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F3880 */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4367   },
4368
4369   /* PREFIX_0F3881 */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F3882 */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F38C8 */
4384   {
4385     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38C9 */
4389   {
4390     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F38CA */
4394   {
4395     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F38CB */
4399   {
4400     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F38CC */
4404   {
4405     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4406   },
4407
4408   /* PREFIX_0F38CD */
4409   {
4410     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F38CF */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F38DB */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F38DC */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4432   },
4433
4434   /* PREFIX_0F38DD */
4435   {
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F38DE */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4446   },
4447
4448   /* PREFIX_0F38DF */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F38F0 */
4456   {
4457     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4458     { Bad_Opcode },
4459     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4460     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4461   },
4462
4463   /* PREFIX_0F38F1 */
4464   {
4465     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4466     { Bad_Opcode },
4467     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4468     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4469   },
4470
4471   /* PREFIX_0F38F5 */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4476   },
4477
4478   /* PREFIX_0F38F6 */
4479   {
4480     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4481     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4482     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4483     { Bad_Opcode },
4484   },
4485
4486   /* PREFIX_0F38F8 */
4487   {
4488     { Bad_Opcode },
4489     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4490     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4491     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4492   },
4493
4494   /* PREFIX_0F38F9 */
4495   {
4496     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4497   },
4498
4499   /* PREFIX_0F3A08 */
4500   {
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4504   },
4505
4506   /* PREFIX_0F3A09 */
4507   {
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4511   },
4512
4513   /* PREFIX_0F3A0A */
4514   {
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4518   },
4519
4520   /* PREFIX_0F3A0B */
4521   {
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4525   },
4526
4527   /* PREFIX_0F3A0C */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4532   },
4533
4534   /* PREFIX_0F3A0D */
4535   {
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4539   },
4540
4541   /* PREFIX_0F3A0E */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4546   },
4547
4548   /* PREFIX_0F3A14 */
4549   {
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4553   },
4554
4555   /* PREFIX_0F3A15 */
4556   {
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4560   },
4561
4562   /* PREFIX_0F3A16 */
4563   {
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4567   },
4568
4569   /* PREFIX_0F3A17 */
4570   {
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4574   },
4575
4576   /* PREFIX_0F3A20 */
4577   {
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4581   },
4582
4583   /* PREFIX_0F3A21 */
4584   {
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4588   },
4589
4590   /* PREFIX_0F3A22 */
4591   {
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4595   },
4596
4597   /* PREFIX_0F3A40 */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4602   },
4603
4604   /* PREFIX_0F3A41 */
4605   {
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4609   },
4610
4611   /* PREFIX_0F3A42 */
4612   {
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4616   },
4617
4618   /* PREFIX_0F3A44 */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4623   },
4624
4625   /* PREFIX_0F3A60 */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4630   },
4631
4632   /* PREFIX_0F3A61 */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4637   },
4638
4639   /* PREFIX_0F3A62 */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4644   },
4645
4646   /* PREFIX_0F3A63 */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4651   },
4652
4653   /* PREFIX_0F3ACC */
4654   {
4655     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4656   },
4657
4658   /* PREFIX_0F3ACE */
4659   {
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4663   },
4664
4665   /* PREFIX_0F3ACF */
4666   {
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4670   },
4671
4672   /* PREFIX_0F3ADF */
4673   {
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4677   },
4678
4679   /* PREFIX_VEX_0F10 */
4680   {
4681     { "vmovups",        { XM, EXx }, 0 },
4682     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4683     { "vmovupd",        { XM, EXx }, 0 },
4684     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4685   },
4686
4687   /* PREFIX_VEX_0F11 */
4688   {
4689     { "vmovups",        { EXxS, XM }, 0 },
4690     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4691     { "vmovupd",        { EXxS, XM }, 0 },
4692     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4693   },
4694
4695   /* PREFIX_VEX_0F12 */
4696   {
4697     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4698     { "vmovsldup",      { XM, EXx }, 0 },
4699     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4700     { "vmovddup",       { XM, EXymmq }, 0 },
4701   },
4702
4703   /* PREFIX_VEX_0F16 */
4704   {
4705     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4706     { "vmovshdup",      { XM, EXx }, 0 },
4707     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4708   },
4709
4710   /* PREFIX_VEX_0F2A */
4711   {
4712     { Bad_Opcode },
4713     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4714     { Bad_Opcode },
4715     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4716   },
4717
4718   /* PREFIX_VEX_0F2C */
4719   {
4720     { Bad_Opcode },
4721     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4722     { Bad_Opcode },
4723     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4724   },
4725
4726   /* PREFIX_VEX_0F2D */
4727   {
4728     { Bad_Opcode },
4729     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4730     { Bad_Opcode },
4731     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4732   },
4733
4734   /* PREFIX_VEX_0F2E */
4735   {
4736     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4737     { Bad_Opcode },
4738     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4739   },
4740
4741   /* PREFIX_VEX_0F2F */
4742   {
4743     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4744     { Bad_Opcode },
4745     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4746   },
4747
4748   /* PREFIX_VEX_0F41 */
4749   {
4750     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4751     { Bad_Opcode },
4752     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4753   },
4754
4755   /* PREFIX_VEX_0F42 */
4756   {
4757     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4758     { Bad_Opcode },
4759     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4760   },
4761
4762   /* PREFIX_VEX_0F44 */
4763   {
4764     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4765     { Bad_Opcode },
4766     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4767   },
4768
4769   /* PREFIX_VEX_0F45 */
4770   {
4771     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4772     { Bad_Opcode },
4773     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4774   },
4775
4776   /* PREFIX_VEX_0F46 */
4777   {
4778     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4779     { Bad_Opcode },
4780     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4781   },
4782
4783   /* PREFIX_VEX_0F47 */
4784   {
4785     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4786     { Bad_Opcode },
4787     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4788   },
4789
4790   /* PREFIX_VEX_0F4A */
4791   {
4792     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4793     { Bad_Opcode },
4794     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4795   },
4796
4797   /* PREFIX_VEX_0F4B */
4798   {
4799     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4800     { Bad_Opcode },
4801     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4802   },
4803
4804   /* PREFIX_VEX_0F51 */
4805   {
4806     { "vsqrtps",        { XM, EXx }, 0 },
4807     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4808     { "vsqrtpd",        { XM, EXx }, 0 },
4809     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4810   },
4811
4812   /* PREFIX_VEX_0F52 */
4813   {
4814     { "vrsqrtps",       { XM, EXx }, 0 },
4815     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4816   },
4817
4818   /* PREFIX_VEX_0F53 */
4819   {
4820     { "vrcpps",         { XM, EXx }, 0 },
4821     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4822   },
4823
4824   /* PREFIX_VEX_0F58 */
4825   {
4826     { "vaddps",         { XM, Vex, EXx }, 0 },
4827     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4828     { "vaddpd",         { XM, Vex, EXx }, 0 },
4829     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4830   },
4831
4832   /* PREFIX_VEX_0F59 */
4833   {
4834     { "vmulps",         { XM, Vex, EXx }, 0 },
4835     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4836     { "vmulpd",         { XM, Vex, EXx }, 0 },
4837     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4838   },
4839
4840   /* PREFIX_VEX_0F5A */
4841   {
4842     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4843     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4844     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4845     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4846   },
4847
4848   /* PREFIX_VEX_0F5B */
4849   {
4850     { "vcvtdq2ps",      { XM, EXx }, 0 },
4851     { "vcvttps2dq",     { XM, EXx }, 0 },
4852     { "vcvtps2dq",      { XM, EXx }, 0 },
4853   },
4854
4855   /* PREFIX_VEX_0F5C */
4856   {
4857     { "vsubps",         { XM, Vex, EXx }, 0 },
4858     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4859     { "vsubpd",         { XM, Vex, EXx }, 0 },
4860     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F5D */
4864   {
4865     { "vminps",         { XM, Vex, EXx }, 0 },
4866     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4867     { "vminpd",         { XM, Vex, EXx }, 0 },
4868     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4869   },
4870
4871   /* PREFIX_VEX_0F5E */
4872   {
4873     { "vdivps",         { XM, Vex, EXx }, 0 },
4874     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4875     { "vdivpd",         { XM, Vex, EXx }, 0 },
4876     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4877   },
4878
4879   /* PREFIX_VEX_0F5F */
4880   {
4881     { "vmaxps",         { XM, Vex, EXx }, 0 },
4882     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4883     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4884     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4885   },
4886
4887   /* PREFIX_VEX_0F60 */
4888   {
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4892   },
4893
4894   /* PREFIX_VEX_0F61 */
4895   {
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4899   },
4900
4901   /* PREFIX_VEX_0F62 */
4902   {
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4906   },
4907
4908   /* PREFIX_VEX_0F63 */
4909   {
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4913   },
4914
4915   /* PREFIX_VEX_0F64 */
4916   {
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4920   },
4921
4922   /* PREFIX_VEX_0F65 */
4923   {
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4927   },
4928
4929   /* PREFIX_VEX_0F66 */
4930   {
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4934   },
4935
4936   /* PREFIX_VEX_0F67 */
4937   {
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4941   },
4942
4943   /* PREFIX_VEX_0F68 */
4944   {
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4948   },
4949
4950   /* PREFIX_VEX_0F69 */
4951   {
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4955   },
4956
4957   /* PREFIX_VEX_0F6A */
4958   {
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4962   },
4963
4964   /* PREFIX_VEX_0F6B */
4965   {
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4969   },
4970
4971   /* PREFIX_VEX_0F6C */
4972   {
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4976   },
4977
4978   /* PREFIX_VEX_0F6D */
4979   {
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4983   },
4984
4985   /* PREFIX_VEX_0F6E */
4986   {
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4990   },
4991
4992   /* PREFIX_VEX_0F6F */
4993   {
4994     { Bad_Opcode },
4995     { "vmovdqu",        { XM, EXx }, 0 },
4996     { "vmovdqa",        { XM, EXx }, 0 },
4997   },
4998
4999   /* PREFIX_VEX_0F70 */
5000   {
5001     { Bad_Opcode },
5002     { "vpshufhw",       { XM, EXx, Ib }, 0 },
5003     { "vpshufd",        { XM, EXx, Ib }, 0 },
5004     { "vpshuflw",       { XM, EXx, Ib }, 0 },
5005   },
5006
5007   /* PREFIX_VEX_0F71_REG_2 */
5008   {
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5012   },
5013
5014   /* PREFIX_VEX_0F71_REG_4 */
5015   {
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { "vpsraw",         { Vex, XS, Ib }, 0 },
5019   },
5020
5021   /* PREFIX_VEX_0F71_REG_6 */
5022   {
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { "vpsllw",         { Vex, XS, Ib }, 0 },
5026   },
5027
5028   /* PREFIX_VEX_0F72_REG_2 */
5029   {
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { "vpsrld",         { Vex, XS, Ib }, 0 },
5033   },
5034
5035   /* PREFIX_VEX_0F72_REG_4 */
5036   {
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { "vpsrad",         { Vex, XS, Ib }, 0 },
5040   },
5041
5042   /* PREFIX_VEX_0F72_REG_6 */
5043   {
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { "vpslld",         { Vex, XS, Ib }, 0 },
5047   },
5048
5049   /* PREFIX_VEX_0F73_REG_2 */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5054   },
5055
5056   /* PREFIX_VEX_0F73_REG_3 */
5057   {
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5061   },
5062
5063   /* PREFIX_VEX_0F73_REG_6 */
5064   {
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { "vpsllq",         { Vex, XS, Ib }, 0 },
5068   },
5069
5070   /* PREFIX_VEX_0F73_REG_7 */
5071   {
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { "vpslldq",        { Vex, XS, Ib }, 0 },
5075   },
5076
5077   /* PREFIX_VEX_0F74 */
5078   {
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5082   },
5083
5084   /* PREFIX_VEX_0F75 */
5085   {
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5089   },
5090
5091   /* PREFIX_VEX_0F76 */
5092   {
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5096   },
5097
5098   /* PREFIX_VEX_0F77 */
5099   {
5100     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5101   },
5102
5103   /* PREFIX_VEX_0F7C */
5104   {
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5108     { "vhaddps",        { XM, Vex, EXx }, 0 },
5109   },
5110
5111   /* PREFIX_VEX_0F7D */
5112   {
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5116     { "vhsubps",        { XM, Vex, EXx }, 0 },
5117   },
5118
5119   /* PREFIX_VEX_0F7E */
5120   {
5121     { Bad_Opcode },
5122     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5123     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5124   },
5125
5126   /* PREFIX_VEX_0F7F */
5127   {
5128     { Bad_Opcode },
5129     { "vmovdqu",        { EXxS, XM }, 0 },
5130     { "vmovdqa",        { EXxS, XM }, 0 },
5131   },
5132
5133   /* PREFIX_VEX_0F90 */
5134   {
5135     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5136     { Bad_Opcode },
5137     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5138   },
5139
5140   /* PREFIX_VEX_0F91 */
5141   {
5142     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5143     { Bad_Opcode },
5144     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5145   },
5146
5147   /* PREFIX_VEX_0F92 */
5148   {
5149     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5150     { Bad_Opcode },
5151     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5152     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5153   },
5154
5155   /* PREFIX_VEX_0F93 */
5156   {
5157     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5158     { Bad_Opcode },
5159     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5160     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5161   },
5162
5163   /* PREFIX_VEX_0F98 */
5164   {
5165     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5166     { Bad_Opcode },
5167     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5168   },
5169
5170   /* PREFIX_VEX_0F99 */
5171   {
5172     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5173     { Bad_Opcode },
5174     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5175   },
5176
5177   /* PREFIX_VEX_0FC2 */
5178   {
5179     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5180     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5181     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5182     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5183   },
5184
5185   /* PREFIX_VEX_0FC4 */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5190   },
5191
5192   /* PREFIX_VEX_0FC5 */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5197   },
5198
5199   /* PREFIX_VEX_0FD0 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5204     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5205   },
5206
5207   /* PREFIX_VEX_0FD1 */
5208   {
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5212   },
5213
5214   /* PREFIX_VEX_0FD2 */
5215   {
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5219   },
5220
5221   /* PREFIX_VEX_0FD3 */
5222   {
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5226   },
5227
5228   /* PREFIX_VEX_0FD4 */
5229   {
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { "vpaddq",         { XM, Vex, EXx }, 0 },
5233   },
5234
5235   /* PREFIX_VEX_0FD5 */
5236   {
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { "vpmullw",        { XM, Vex, EXx }, 0 },
5240   },
5241
5242   /* PREFIX_VEX_0FD6 */
5243   {
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5247   },
5248
5249   /* PREFIX_VEX_0FD7 */
5250   {
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5254   },
5255
5256   /* PREFIX_VEX_0FD8 */
5257   {
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5261   },
5262
5263   /* PREFIX_VEX_0FD9 */
5264   {
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5268   },
5269
5270   /* PREFIX_VEX_0FDA */
5271   {
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { "vpminub",        { XM, Vex, EXx }, 0 },
5275   },
5276
5277   /* PREFIX_VEX_0FDB */
5278   {
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { "vpand",          { XM, Vex, EXx }, 0 },
5282   },
5283
5284   /* PREFIX_VEX_0FDC */
5285   {
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5289   },
5290
5291   /* PREFIX_VEX_0FDD */
5292   {
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5296   },
5297
5298   /* PREFIX_VEX_0FDE */
5299   {
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5303   },
5304
5305   /* PREFIX_VEX_0FDF */
5306   {
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { "vpandn",         { XM, Vex, EXx }, 0 },
5310   },
5311
5312   /* PREFIX_VEX_0FE0 */
5313   {
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { "vpavgb",         { XM, Vex, EXx }, 0 },
5317   },
5318
5319   /* PREFIX_VEX_0FE1 */
5320   {
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5324   },
5325
5326   /* PREFIX_VEX_0FE2 */
5327   {
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5331   },
5332
5333   /* PREFIX_VEX_0FE3 */
5334   {
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { "vpavgw",         { XM, Vex, EXx }, 0 },
5338   },
5339
5340   /* PREFIX_VEX_0FE4 */
5341   {
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5345   },
5346
5347   /* PREFIX_VEX_0FE5 */
5348   {
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5352   },
5353
5354   /* PREFIX_VEX_0FE6 */
5355   {
5356     { Bad_Opcode },
5357     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5358     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5359     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5360   },
5361
5362   /* PREFIX_VEX_0FE7 */
5363   {
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5367   },
5368
5369   /* PREFIX_VEX_0FE8 */
5370   {
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5374   },
5375
5376   /* PREFIX_VEX_0FE9 */
5377   {
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5381   },
5382
5383   /* PREFIX_VEX_0FEA */
5384   {
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { "vpminsw",        { XM, Vex, EXx }, 0 },
5388   },
5389
5390   /* PREFIX_VEX_0FEB */
5391   {
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { "vpor",           { XM, Vex, EXx }, 0 },
5395   },
5396
5397   /* PREFIX_VEX_0FEC */
5398   {
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5402   },
5403
5404   /* PREFIX_VEX_0FED */
5405   {
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5409   },
5410
5411   /* PREFIX_VEX_0FEE */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5416   },
5417
5418   /* PREFIX_VEX_0FEF */
5419   {
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { "vpxor",          { XM, Vex, EXx }, 0 },
5423   },
5424
5425   /* PREFIX_VEX_0FF0 */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5431   },
5432
5433   /* PREFIX_VEX_0FF1 */
5434   {
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5438   },
5439
5440   /* PREFIX_VEX_0FF2 */
5441   {
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5445   },
5446
5447   /* PREFIX_VEX_0FF3 */
5448   {
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5452   },
5453
5454   /* PREFIX_VEX_0FF4 */
5455   {
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5459   },
5460
5461   /* PREFIX_VEX_0FF5 */
5462   {
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5466   },
5467
5468   /* PREFIX_VEX_0FF6 */
5469   {
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5473   },
5474
5475   /* PREFIX_VEX_0FF7 */
5476   {
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5480   },
5481
5482   /* PREFIX_VEX_0FF8 */
5483   {
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { "vpsubb",         { XM, Vex, EXx }, 0 },
5487   },
5488
5489   /* PREFIX_VEX_0FF9 */
5490   {
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { "vpsubw",         { XM, Vex, EXx }, 0 },
5494   },
5495
5496   /* PREFIX_VEX_0FFA */
5497   {
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { "vpsubd",         { XM, Vex, EXx }, 0 },
5501   },
5502
5503   /* PREFIX_VEX_0FFB */
5504   {
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { "vpsubq",         { XM, Vex, EXx }, 0 },
5508   },
5509
5510   /* PREFIX_VEX_0FFC */
5511   {
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { "vpaddb",         { XM, Vex, EXx }, 0 },
5515   },
5516
5517   /* PREFIX_VEX_0FFD */
5518   {
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { "vpaddw",         { XM, Vex, EXx }, 0 },
5522   },
5523
5524   /* PREFIX_VEX_0FFE */
5525   {
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { "vpaddd",         { XM, Vex, EXx }, 0 },
5529   },
5530
5531   /* PREFIX_VEX_0F3800 */
5532   {
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { "vpshufb",        { XM, Vex, EXx }, 0 },
5536   },
5537
5538   /* PREFIX_VEX_0F3801 */
5539   {
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { "vphaddw",        { XM, Vex, EXx }, 0 },
5543   },
5544
5545   /* PREFIX_VEX_0F3802 */
5546   {
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { "vphaddd",        { XM, Vex, EXx }, 0 },
5550   },
5551
5552   /* PREFIX_VEX_0F3803 */
5553   {
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5557   },
5558
5559   /* PREFIX_VEX_0F3804 */
5560   {
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5564   },
5565
5566   /* PREFIX_VEX_0F3805 */
5567   {
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { "vphsubw",        { XM, Vex, EXx }, 0 },
5571   },
5572
5573   /* PREFIX_VEX_0F3806 */
5574   {
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { "vphsubd",        { XM, Vex, EXx }, 0 },
5578   },
5579
5580   /* PREFIX_VEX_0F3807 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5585   },
5586
5587   /* PREFIX_VEX_0F3808 */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { "vpsignb",        { XM, Vex, EXx }, 0 },
5592   },
5593
5594   /* PREFIX_VEX_0F3809 */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { "vpsignw",        { XM, Vex, EXx }, 0 },
5599   },
5600
5601   /* PREFIX_VEX_0F380A */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { "vpsignd",        { XM, Vex, EXx }, 0 },
5606   },
5607
5608   /* PREFIX_VEX_0F380B */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5613   },
5614
5615   /* PREFIX_VEX_0F380C */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5620   },
5621
5622   /* PREFIX_VEX_0F380D */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5627   },
5628
5629   /* PREFIX_VEX_0F380E */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5634   },
5635
5636   /* PREFIX_VEX_0F380F */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5641   },
5642
5643   /* PREFIX_VEX_0F3813 */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5648   },
5649
5650   /* PREFIX_VEX_0F3816 */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5655   },
5656
5657   /* PREFIX_VEX_0F3817 */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { "vptest",         { XM, EXx }, 0 },
5662   },
5663
5664   /* PREFIX_VEX_0F3818 */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5669   },
5670
5671   /* PREFIX_VEX_0F3819 */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5676   },
5677
5678   /* PREFIX_VEX_0F381A */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5683   },
5684
5685   /* PREFIX_VEX_0F381C */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { "vpabsb",         { XM, EXx }, 0 },
5690   },
5691
5692   /* PREFIX_VEX_0F381D */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { "vpabsw",         { XM, EXx }, 0 },
5697   },
5698
5699   /* PREFIX_VEX_0F381E */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { "vpabsd",         { XM, EXx }, 0 },
5704   },
5705
5706   /* PREFIX_VEX_0F3820 */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5711   },
5712
5713   /* PREFIX_VEX_0F3821 */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5718   },
5719
5720   /* PREFIX_VEX_0F3822 */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5725   },
5726
5727   /* PREFIX_VEX_0F3823 */
5728   {
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5732   },
5733
5734   /* PREFIX_VEX_0F3824 */
5735   {
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5739   },
5740
5741   /* PREFIX_VEX_0F3825 */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5746   },
5747
5748   /* PREFIX_VEX_0F3828 */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5753   },
5754
5755   /* PREFIX_VEX_0F3829 */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5760   },
5761
5762   /* PREFIX_VEX_0F382A */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5767   },
5768
5769   /* PREFIX_VEX_0F382B */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5774   },
5775
5776   /* PREFIX_VEX_0F382C */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5781   },
5782
5783   /* PREFIX_VEX_0F382D */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5788   },
5789
5790   /* PREFIX_VEX_0F382E */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5795   },
5796
5797   /* PREFIX_VEX_0F382F */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5802   },
5803
5804   /* PREFIX_VEX_0F3830 */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5809   },
5810
5811   /* PREFIX_VEX_0F3831 */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5816   },
5817
5818   /* PREFIX_VEX_0F3832 */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5823   },
5824
5825   /* PREFIX_VEX_0F3833 */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5830   },
5831
5832   /* PREFIX_VEX_0F3834 */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5837   },
5838
5839   /* PREFIX_VEX_0F3835 */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5844   },
5845
5846   /* PREFIX_VEX_0F3836 */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5851   },
5852
5853   /* PREFIX_VEX_0F3837 */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5858   },
5859
5860   /* PREFIX_VEX_0F3838 */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { "vpminsb",        { XM, Vex, EXx }, 0 },
5865   },
5866
5867   /* PREFIX_VEX_0F3839 */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { "vpminsd",        { XM, Vex, EXx }, 0 },
5872   },
5873
5874   /* PREFIX_VEX_0F383A */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { "vpminuw",        { XM, Vex, EXx }, 0 },
5879   },
5880
5881   /* PREFIX_VEX_0F383B */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { "vpminud",        { XM, Vex, EXx }, 0 },
5886   },
5887
5888   /* PREFIX_VEX_0F383C */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5893   },
5894
5895   /* PREFIX_VEX_0F383D */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5900   },
5901
5902   /* PREFIX_VEX_0F383E */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5907   },
5908
5909   /* PREFIX_VEX_0F383F */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5914   },
5915
5916   /* PREFIX_VEX_0F3840 */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { "vpmulld",        { XM, Vex, EXx }, 0 },
5921   },
5922
5923   /* PREFIX_VEX_0F3841 */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5928   },
5929
5930   /* PREFIX_VEX_0F3845 */
5931   {
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5935   },
5936
5937   /* PREFIX_VEX_0F3846 */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5942   },
5943
5944   /* PREFIX_VEX_0F3847 */
5945   {
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5949   },
5950
5951   /* PREFIX_VEX_0F3858 */
5952   {
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5956   },
5957
5958   /* PREFIX_VEX_0F3859 */
5959   {
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5963   },
5964
5965   /* PREFIX_VEX_0F385A */
5966   {
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5970   },
5971
5972   /* PREFIX_VEX_0F3878 */
5973   {
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5977   },
5978
5979   /* PREFIX_VEX_0F3879 */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5984   },
5985
5986   /* PREFIX_VEX_0F388C */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5991   },
5992
5993   /* PREFIX_VEX_0F388E */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5998   },
5999
6000   /* PREFIX_VEX_0F3890 */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6005   },
6006
6007   /* PREFIX_VEX_0F3891 */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6012   },
6013
6014   /* PREFIX_VEX_0F3892 */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6019   },
6020
6021   /* PREFIX_VEX_0F3893 */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6026   },
6027
6028   /* PREFIX_VEX_0F3896 */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6033   },
6034
6035   /* PREFIX_VEX_0F3897 */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6040   },
6041
6042   /* PREFIX_VEX_0F3898 */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6047   },
6048
6049   /* PREFIX_VEX_0F3899 */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6054   },
6055
6056   /* PREFIX_VEX_0F389A */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6061   },
6062
6063   /* PREFIX_VEX_0F389B */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6068   },
6069
6070   /* PREFIX_VEX_0F389C */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6075   },
6076
6077   /* PREFIX_VEX_0F389D */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6082   },
6083
6084   /* PREFIX_VEX_0F389E */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6089   },
6090
6091   /* PREFIX_VEX_0F389F */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6096   },
6097
6098   /* PREFIX_VEX_0F38A6 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6103     { Bad_Opcode },
6104   },
6105
6106   /* PREFIX_VEX_0F38A7 */
6107   {
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6111   },
6112
6113   /* PREFIX_VEX_0F38A8 */
6114   {
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6118   },
6119
6120   /* PREFIX_VEX_0F38A9 */
6121   {
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6125   },
6126
6127   /* PREFIX_VEX_0F38AA */
6128   {
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6132   },
6133
6134   /* PREFIX_VEX_0F38AB */
6135   {
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6139   },
6140
6141   /* PREFIX_VEX_0F38AC */
6142   {
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6146   },
6147
6148   /* PREFIX_VEX_0F38AD */
6149   {
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6153   },
6154
6155   /* PREFIX_VEX_0F38AE */
6156   {
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6160   },
6161
6162   /* PREFIX_VEX_0F38AF */
6163   {
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6167   },
6168
6169   /* PREFIX_VEX_0F38B6 */
6170   {
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6174   },
6175
6176   /* PREFIX_VEX_0F38B7 */
6177   {
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6181   },
6182
6183   /* PREFIX_VEX_0F38B8 */
6184   {
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6188   },
6189
6190   /* PREFIX_VEX_0F38B9 */
6191   {
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6195   },
6196
6197   /* PREFIX_VEX_0F38BA */
6198   {
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6202   },
6203
6204   /* PREFIX_VEX_0F38BB */
6205   {
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6209   },
6210
6211   /* PREFIX_VEX_0F38BC */
6212   {
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6216   },
6217
6218   /* PREFIX_VEX_0F38BD */
6219   {
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6223   },
6224
6225   /* PREFIX_VEX_0F38BE */
6226   {
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6230   },
6231
6232   /* PREFIX_VEX_0F38BF */
6233   {
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6237   },
6238
6239   /* PREFIX_VEX_0F38CF */
6240   {
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6244   },
6245
6246   /* PREFIX_VEX_0F38DB */
6247   {
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6251   },
6252
6253   /* PREFIX_VEX_0F38DC */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vaesenc",        { XM, Vex, EXx }, 0 },
6258   },
6259
6260   /* PREFIX_VEX_0F38DD */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6265   },
6266
6267   /* PREFIX_VEX_0F38DE */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { "vaesdec",        { XM, Vex, EXx }, 0 },
6272   },
6273
6274   /* PREFIX_VEX_0F38DF */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6279   },
6280
6281   /* PREFIX_VEX_0F38F2 */
6282   {
6283     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6284   },
6285
6286   /* PREFIX_VEX_0F38F3_REG_1 */
6287   {
6288     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6289   },
6290
6291   /* PREFIX_VEX_0F38F3_REG_2 */
6292   {
6293     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6294   },
6295
6296   /* PREFIX_VEX_0F38F3_REG_3 */
6297   {
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6299   },
6300
6301   /* PREFIX_VEX_0F38F5 */
6302   {
6303     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6304     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6305     { Bad_Opcode },
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6307   },
6308
6309   /* PREFIX_VEX_0F38F6 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6315   },
6316
6317   /* PREFIX_VEX_0F38F7 */
6318   {
6319     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6320     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6321     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6322     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6323   },
6324
6325   /* PREFIX_VEX_0F3A00 */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6330   },
6331
6332   /* PREFIX_VEX_0F3A01 */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6337   },
6338
6339   /* PREFIX_VEX_0F3A02 */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6344   },
6345
6346   /* PREFIX_VEX_0F3A04 */
6347   {
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6351   },
6352
6353   /* PREFIX_VEX_0F3A05 */
6354   {
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6358   },
6359
6360   /* PREFIX_VEX_0F3A06 */
6361   {
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6365   },
6366
6367   /* PREFIX_VEX_0F3A08 */
6368   {
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { "vroundps",       { XM, EXx, Ib }, 0 },
6372   },
6373
6374   /* PREFIX_VEX_0F3A09 */
6375   {
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { "vroundpd",       { XM, EXx, Ib }, 0 },
6379   },
6380
6381   /* PREFIX_VEX_0F3A0A */
6382   {
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6386   },
6387
6388   /* PREFIX_VEX_0F3A0B */
6389   {
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6393   },
6394
6395   /* PREFIX_VEX_0F3A0C */
6396   {
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6400   },
6401
6402   /* PREFIX_VEX_0F3A0D */
6403   {
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6407   },
6408
6409   /* PREFIX_VEX_0F3A0E */
6410   {
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6414   },
6415
6416   /* PREFIX_VEX_0F3A0F */
6417   {
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6421   },
6422
6423   /* PREFIX_VEX_0F3A14 */
6424   {
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6428   },
6429
6430   /* PREFIX_VEX_0F3A15 */
6431   {
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6435   },
6436
6437   /* PREFIX_VEX_0F3A16 */
6438   {
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6442   },
6443
6444   /* PREFIX_VEX_0F3A17 */
6445   {
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6449   },
6450
6451   /* PREFIX_VEX_0F3A18 */
6452   {
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6456   },
6457
6458   /* PREFIX_VEX_0F3A19 */
6459   {
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6463   },
6464
6465   /* PREFIX_VEX_0F3A1D */
6466   {
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6470   },
6471
6472   /* PREFIX_VEX_0F3A20 */
6473   {
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6477   },
6478
6479   /* PREFIX_VEX_0F3A21 */
6480   {
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6484   },
6485
6486   /* PREFIX_VEX_0F3A22 */
6487   {
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6491   },
6492
6493   /* PREFIX_VEX_0F3A30 */
6494   {
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6498   },
6499
6500   /* PREFIX_VEX_0F3A31 */
6501   {
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6505   },
6506
6507   /* PREFIX_VEX_0F3A32 */
6508   {
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6512   },
6513
6514   /* PREFIX_VEX_0F3A33 */
6515   {
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6519   },
6520
6521   /* PREFIX_VEX_0F3A38 */
6522   {
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6526   },
6527
6528   /* PREFIX_VEX_0F3A39 */
6529   {
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6533   },
6534
6535   /* PREFIX_VEX_0F3A40 */
6536   {
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6540   },
6541
6542   /* PREFIX_VEX_0F3A41 */
6543   {
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6547   },
6548
6549   /* PREFIX_VEX_0F3A42 */
6550   {
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6554   },
6555
6556   /* PREFIX_VEX_0F3A44 */
6557   {
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6561   },
6562
6563   /* PREFIX_VEX_0F3A46 */
6564   {
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6568   },
6569
6570   /* PREFIX_VEX_0F3A48 */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6575   },
6576
6577   /* PREFIX_VEX_0F3A49 */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6582   },
6583
6584   /* PREFIX_VEX_0F3A4A */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A4B */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6596   },
6597
6598   /* PREFIX_VEX_0F3A4C */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6603   },
6604
6605   /* PREFIX_VEX_0F3A5C */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6610   },
6611
6612   /* PREFIX_VEX_0F3A5D */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6617   },
6618
6619   /* PREFIX_VEX_0F3A5E */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6624   },
6625
6626   /* PREFIX_VEX_0F3A5F */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6631   },
6632
6633   /* PREFIX_VEX_0F3A60 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6638     { Bad_Opcode },
6639   },
6640
6641   /* PREFIX_VEX_0F3A61 */
6642   {
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6646   },
6647
6648   /* PREFIX_VEX_0F3A62 */
6649   {
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6653   },
6654
6655   /* PREFIX_VEX_0F3A63 */
6656   {
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6660   },
6661
6662   /* PREFIX_VEX_0F3A68 */
6663   {
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6667   },
6668
6669   /* PREFIX_VEX_0F3A69 */
6670   {
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6674   },
6675
6676   /* PREFIX_VEX_0F3A6A */
6677   {
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6681   },
6682
6683   /* PREFIX_VEX_0F3A6B */
6684   {
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6688   },
6689
6690   /* PREFIX_VEX_0F3A6C */
6691   {
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6695   },
6696
6697   /* PREFIX_VEX_0F3A6D */
6698   {
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6702   },
6703
6704   /* PREFIX_VEX_0F3A6E */
6705   {
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6709   },
6710
6711   /* PREFIX_VEX_0F3A6F */
6712   {
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6716   },
6717
6718   /* PREFIX_VEX_0F3A78 */
6719   {
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6723   },
6724
6725   /* PREFIX_VEX_0F3A79 */
6726   {
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6730   },
6731
6732   /* PREFIX_VEX_0F3A7A */
6733   {
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6737   },
6738
6739   /* PREFIX_VEX_0F3A7B */
6740   {
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6744   },
6745
6746   /* PREFIX_VEX_0F3A7C */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6751     { Bad_Opcode },
6752   },
6753
6754   /* PREFIX_VEX_0F3A7D */
6755   {
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6759   },
6760
6761   /* PREFIX_VEX_0F3A7E */
6762   {
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6766   },
6767
6768   /* PREFIX_VEX_0F3A7F */
6769   {
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6773   },
6774
6775   /* PREFIX_VEX_0F3ACE */
6776   {
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6780   },
6781
6782   /* PREFIX_VEX_0F3ACF */
6783   {
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6787   },
6788
6789   /* PREFIX_VEX_0F3ADF */
6790   {
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6794   },
6795
6796   /* PREFIX_VEX_0F3AF0 */
6797   {
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6802   },
6803
6804 #include "i386-dis-evex-prefix.h"
6805 };
6806
6807 static const struct dis386 x86_64_table[][2] = {
6808   /* X86_64_06 */
6809   {
6810     { "pushP", { es }, 0 },
6811   },
6812
6813   /* X86_64_07 */
6814   {
6815     { "popP", { es }, 0 },
6816   },
6817
6818   /* X86_64_0E */
6819   {
6820     { "pushP", { cs }, 0 },
6821   },
6822
6823   /* X86_64_16 */
6824   {
6825     { "pushP", { ss }, 0 },
6826   },
6827
6828   /* X86_64_17 */
6829   {
6830     { "popP", { ss }, 0 },
6831   },
6832
6833   /* X86_64_1E */
6834   {
6835     { "pushP", { ds }, 0 },
6836   },
6837
6838   /* X86_64_1F */
6839   {
6840     { "popP", { ds }, 0 },
6841   },
6842
6843   /* X86_64_27 */
6844   {
6845     { "daa", { XX }, 0 },
6846   },
6847
6848   /* X86_64_2F */
6849   {
6850     { "das", { XX }, 0 },
6851   },
6852
6853   /* X86_64_37 */
6854   {
6855     { "aaa", { XX }, 0 },
6856   },
6857
6858   /* X86_64_3F */
6859   {
6860     { "aas", { XX }, 0 },
6861   },
6862
6863   /* X86_64_60 */
6864   {
6865     { "pushaP", { XX }, 0 },
6866   },
6867
6868   /* X86_64_61 */
6869   {
6870     { "popaP", { XX }, 0 },
6871   },
6872
6873   /* X86_64_62 */
6874   {
6875     { MOD_TABLE (MOD_62_32BIT) },
6876     { EVEX_TABLE (EVEX_0F) },
6877   },
6878
6879   /* X86_64_63 */
6880   {
6881     { "arpl", { Ew, Gw }, 0 },
6882     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6883   },
6884
6885   /* X86_64_6D */
6886   {
6887     { "ins{R|}", { Yzr, indirDX }, 0 },
6888     { "ins{G|}", { Yzr, indirDX }, 0 },
6889   },
6890
6891   /* X86_64_6F */
6892   {
6893     { "outs{R|}", { indirDXr, Xz }, 0 },
6894     { "outs{G|}", { indirDXr, Xz }, 0 },
6895   },
6896
6897   /* X86_64_82 */
6898   {
6899     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6900     { REG_TABLE (REG_80) },
6901   },
6902
6903   /* X86_64_9A */
6904   {
6905     { "Jcall{T|}", { Ap }, 0 },
6906   },
6907
6908   /* X86_64_C2 */
6909   {
6910     { "retP",           { Iw, BND }, 0 },
6911     { "ret@",           { Iw, BND }, 0 },
6912   },
6913
6914   /* X86_64_C3 */
6915   {
6916     { "retP",           { BND }, 0 },
6917     { "ret@",           { BND }, 0 },
6918   },
6919
6920   /* X86_64_C4 */
6921   {
6922     { MOD_TABLE (MOD_C4_32BIT) },
6923     { VEX_C4_TABLE (VEX_0F) },
6924   },
6925
6926   /* X86_64_C5 */
6927   {
6928     { MOD_TABLE (MOD_C5_32BIT) },
6929     { VEX_C5_TABLE (VEX_0F) },
6930   },
6931
6932   /* X86_64_CE */
6933   {
6934     { "into", { XX }, 0 },
6935   },
6936
6937   /* X86_64_D4 */
6938   {
6939     { "aam", { Ib }, 0 },
6940   },
6941
6942   /* X86_64_D5 */
6943   {
6944     { "aad", { Ib }, 0 },
6945   },
6946
6947   /* X86_64_E8 */
6948   {
6949     { "callP",          { Jv, BND }, 0 },
6950     { "call@",          { Jv, BND }, 0 }
6951   },
6952
6953   /* X86_64_E9 */
6954   {
6955     { "jmpP",           { Jv, BND }, 0 },
6956     { "jmp@",           { Jv, BND }, 0 }
6957   },
6958
6959   /* X86_64_EA */
6960   {
6961     { "Jjmp{T|}", { Ap }, 0 },
6962   },
6963
6964   /* X86_64_0F01_REG_0 */
6965   {
6966     { "sgdt{Q|IQ}", { M }, 0 },
6967     { "sgdt", { M }, 0 },
6968   },
6969
6970   /* X86_64_0F01_REG_1 */
6971   {
6972     { "sidt{Q|IQ}", { M }, 0 },
6973     { "sidt", { M }, 0 },
6974   },
6975
6976   /* X86_64_0F01_REG_2 */
6977   {
6978     { "lgdt{Q|Q}", { M }, 0 },
6979     { "lgdt", { M }, 0 },
6980   },
6981
6982   /* X86_64_0F01_REG_3 */
6983   {
6984     { "lidt{Q|Q}", { M }, 0 },
6985     { "lidt", { M }, 0 },
6986   },
6987 };
6988
6989 static const struct dis386 three_byte_table[][256] = {
6990
6991   /* THREE_BYTE_0F38 */
6992   {
6993     /* 00 */
6994     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6995     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6996     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6997     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6998     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6999     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7000     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7001     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7002     /* 08 */
7003     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7004     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7005     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7006     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     /* 10 */
7012     { PREFIX_TABLE (PREFIX_0F3810) },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { PREFIX_TABLE (PREFIX_0F3814) },
7017     { PREFIX_TABLE (PREFIX_0F3815) },
7018     { Bad_Opcode },
7019     { PREFIX_TABLE (PREFIX_0F3817) },
7020     /* 18 */
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7026     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7027     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7028     { Bad_Opcode },
7029     /* 20 */
7030     { PREFIX_TABLE (PREFIX_0F3820) },
7031     { PREFIX_TABLE (PREFIX_0F3821) },
7032     { PREFIX_TABLE (PREFIX_0F3822) },
7033     { PREFIX_TABLE (PREFIX_0F3823) },
7034     { PREFIX_TABLE (PREFIX_0F3824) },
7035     { PREFIX_TABLE (PREFIX_0F3825) },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     /* 28 */
7039     { PREFIX_TABLE (PREFIX_0F3828) },
7040     { PREFIX_TABLE (PREFIX_0F3829) },
7041     { PREFIX_TABLE (PREFIX_0F382A) },
7042     { PREFIX_TABLE (PREFIX_0F382B) },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     /* 30 */
7048     { PREFIX_TABLE (PREFIX_0F3830) },
7049     { PREFIX_TABLE (PREFIX_0F3831) },
7050     { PREFIX_TABLE (PREFIX_0F3832) },
7051     { PREFIX_TABLE (PREFIX_0F3833) },
7052     { PREFIX_TABLE (PREFIX_0F3834) },
7053     { PREFIX_TABLE (PREFIX_0F3835) },
7054     { Bad_Opcode },
7055     { PREFIX_TABLE (PREFIX_0F3837) },
7056     /* 38 */
7057     { PREFIX_TABLE (PREFIX_0F3838) },
7058     { PREFIX_TABLE (PREFIX_0F3839) },
7059     { PREFIX_TABLE (PREFIX_0F383A) },
7060     { PREFIX_TABLE (PREFIX_0F383B) },
7061     { PREFIX_TABLE (PREFIX_0F383C) },
7062     { PREFIX_TABLE (PREFIX_0F383D) },
7063     { PREFIX_TABLE (PREFIX_0F383E) },
7064     { PREFIX_TABLE (PREFIX_0F383F) },
7065     /* 40 */
7066     { PREFIX_TABLE (PREFIX_0F3840) },
7067     { PREFIX_TABLE (PREFIX_0F3841) },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* 48 */
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* 50 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* 58 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* 60 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* 68 */
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* 70 */
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* 78 */
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* 80 */
7138     { PREFIX_TABLE (PREFIX_0F3880) },
7139     { PREFIX_TABLE (PREFIX_0F3881) },
7140     { PREFIX_TABLE (PREFIX_0F3882) },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* 88 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* 90 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* 98 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* a0 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* a8 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* b0 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* b8 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* c0 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* c8 */
7219     { PREFIX_TABLE (PREFIX_0F38C8) },
7220     { PREFIX_TABLE (PREFIX_0F38C9) },
7221     { PREFIX_TABLE (PREFIX_0F38CA) },
7222     { PREFIX_TABLE (PREFIX_0F38CB) },
7223     { PREFIX_TABLE (PREFIX_0F38CC) },
7224     { PREFIX_TABLE (PREFIX_0F38CD) },
7225     { Bad_Opcode },
7226     { PREFIX_TABLE (PREFIX_0F38CF) },
7227     /* d0 */
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     /* d8 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { PREFIX_TABLE (PREFIX_0F38DB) },
7241     { PREFIX_TABLE (PREFIX_0F38DC) },
7242     { PREFIX_TABLE (PREFIX_0F38DD) },
7243     { PREFIX_TABLE (PREFIX_0F38DE) },
7244     { PREFIX_TABLE (PREFIX_0F38DF) },
7245     /* e0 */
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     /* e8 */
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     /* f0 */
7264     { PREFIX_TABLE (PREFIX_0F38F0) },
7265     { PREFIX_TABLE (PREFIX_0F38F1) },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { PREFIX_TABLE (PREFIX_0F38F5) },
7270     { PREFIX_TABLE (PREFIX_0F38F6) },
7271     { Bad_Opcode },
7272     /* f8 */
7273     { PREFIX_TABLE (PREFIX_0F38F8) },
7274     { PREFIX_TABLE (PREFIX_0F38F9) },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281   },
7282   /* THREE_BYTE_0F3A */
7283   {
7284     /* 00 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     /* 08 */
7294     { PREFIX_TABLE (PREFIX_0F3A08) },
7295     { PREFIX_TABLE (PREFIX_0F3A09) },
7296     { PREFIX_TABLE (PREFIX_0F3A0A) },
7297     { PREFIX_TABLE (PREFIX_0F3A0B) },
7298     { PREFIX_TABLE (PREFIX_0F3A0C) },
7299     { PREFIX_TABLE (PREFIX_0F3A0D) },
7300     { PREFIX_TABLE (PREFIX_0F3A0E) },
7301     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7302     /* 10 */
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { PREFIX_TABLE (PREFIX_0F3A14) },
7308     { PREFIX_TABLE (PREFIX_0F3A15) },
7309     { PREFIX_TABLE (PREFIX_0F3A16) },
7310     { PREFIX_TABLE (PREFIX_0F3A17) },
7311     /* 18 */
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 20 */
7321     { PREFIX_TABLE (PREFIX_0F3A20) },
7322     { PREFIX_TABLE (PREFIX_0F3A21) },
7323     { PREFIX_TABLE (PREFIX_0F3A22) },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 28 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 30 */
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 38 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 40 */
7357     { PREFIX_TABLE (PREFIX_0F3A40) },
7358     { PREFIX_TABLE (PREFIX_0F3A41) },
7359     { PREFIX_TABLE (PREFIX_0F3A42) },
7360     { Bad_Opcode },
7361     { PREFIX_TABLE (PREFIX_0F3A44) },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 48 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* 50 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* 58 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* 60 */
7393     { PREFIX_TABLE (PREFIX_0F3A60) },
7394     { PREFIX_TABLE (PREFIX_0F3A61) },
7395     { PREFIX_TABLE (PREFIX_0F3A62) },
7396     { PREFIX_TABLE (PREFIX_0F3A63) },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* 68 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* 70 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* 78 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* 80 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* 88 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* 90 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* 98 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* a0 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* a8 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* b0 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* b8 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* c0 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* c8 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { PREFIX_TABLE (PREFIX_0F3ACC) },
7515     { Bad_Opcode },
7516     { PREFIX_TABLE (PREFIX_0F3ACE) },
7517     { PREFIX_TABLE (PREFIX_0F3ACF) },
7518     /* d0 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* d8 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { PREFIX_TABLE (PREFIX_0F3ADF) },
7536     /* e0 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* e8 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     /* f0 */
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     /* f8 */
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572   },
7573 };
7574
7575 static const struct dis386 xop_table[][256] = {
7576   /* XOP_08 */
7577   {
7578     /* 00 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* 08 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* 10 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     /* 18 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* 20 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* 28 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* 30 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* 38 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     /* 40 */
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     /* 48 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     /* 50 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     /* 58 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     /* 60 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     /* 68 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     /* 70 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     /* 78 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     /* 80 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7729     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7730     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7731     /* 88 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7739     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740     /* 90 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7747     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7748     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7749     /* 98 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7757     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7758     /* a0 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7762     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7766     { Bad_Opcode },
7767     /* a8 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* b0 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7784     { Bad_Opcode },
7785     /* b8 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* c0 */
7795     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7796     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7797     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7798     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* c8 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7809     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7810     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7811     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7812     /* d0 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* d8 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* e0 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* e8 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7845     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7846     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7847     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7848     /* f0 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* f8 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866   },
7867   /* XOP_09 */
7868   {
7869     /* 00 */
7870     { Bad_Opcode },
7871     { REG_TABLE (REG_XOP_TBM_01) },
7872     { REG_TABLE (REG_XOP_TBM_02) },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* 08 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 10 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { REG_TABLE (REG_XOP_LWPCB) },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     /* 18 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     /* 20 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     /* 28 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     /* 30 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* 38 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* 40 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* 48 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* 50 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* 58 */
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* 60 */
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     /* 68 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* 70 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* 78 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* 80 */
8014     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8015     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8016     { "vfrczss",        { XM, EXd }, 0 },
8017     { "vfrczsd",        { XM, EXq }, 0 },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* 88 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* 90 */
8032     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8033     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8034     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8035     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8036     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8037     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8038     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8039     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8040     /* 98 */
8041     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8042     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8043     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8044     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* a0 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* a8 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* b0 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* b8 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* c0 */
8086     { Bad_Opcode },
8087     { "vphaddbw",       { XM, EXxmm }, 0 },
8088     { "vphaddbd",       { XM, EXxmm }, 0 },
8089     { "vphaddbq",       { XM, EXxmm }, 0 },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { "vphaddwd",       { XM, EXxmm }, 0 },
8093     { "vphaddwq",       { XM, EXxmm }, 0 },
8094     /* c8 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { "vphadddq",       { XM, EXxmm }, 0 },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* d0 */
8104     { Bad_Opcode },
8105     { "vphaddubw",      { XM, EXxmm }, 0 },
8106     { "vphaddubd",      { XM, EXxmm }, 0 },
8107     { "vphaddubq",      { XM, EXxmm }, 0 },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { "vphadduwd",      { XM, EXxmm }, 0 },
8111     { "vphadduwq",      { XM, EXxmm }, 0 },
8112     /* d8 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { "vphaddudq",      { XM, EXxmm }, 0 },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* e0 */
8122     { Bad_Opcode },
8123     { "vphsubbw",       { XM, EXxmm }, 0 },
8124     { "vphsubwd",       { XM, EXxmm }, 0 },
8125     { "vphsubdq",       { XM, EXxmm }, 0 },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* e8 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* f0 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* f8 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157   },
8158   /* XOP_0A */
8159   {
8160     /* 00 */
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 08 */
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 10 */
8179     { "bextrS", { Gdq, Edq, Id }, 0 },
8180     { Bad_Opcode },
8181     { REG_TABLE (REG_XOP_LWP) },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 18 */
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 20 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 28 */
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     /* 30 */
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* 38 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* 40 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* 48 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* 50 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* 58 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* 60 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* 68 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* 70 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* 78 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* 80 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* 88 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* 90 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* 98 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* a0 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* a8 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* b0 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* b8 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* c0 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* c8 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* d0 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* d8 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* e0 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* e8 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     /* f0 */
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     /* f8 */
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448   },
8449 };
8450
8451 static const struct dis386 vex_table[][256] = {
8452   /* VEX_0F */
8453   {
8454     /* 00 */
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     /* 08 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     /* 10 */
8473     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8474     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8475     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8476     { MOD_TABLE (MOD_VEX_0F13) },
8477     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8478     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8479     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8480     { MOD_TABLE (MOD_VEX_0F17) },
8481     /* 18 */
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     /* 20 */
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     /* 28 */
8500     { "vmovapX",        { XM, EXx }, 0 },
8501     { "vmovapX",        { EXxS, XM }, 0 },
8502     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8503     { MOD_TABLE (MOD_VEX_0F2B) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8506     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8508     /* 30 */
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     /* 38 */
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     /* 40 */
8527     { Bad_Opcode },
8528     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8530     { Bad_Opcode },
8531     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8535     /* 48 */
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     /* 50 */
8545     { MOD_TABLE (MOD_VEX_0F50) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8549     { "vandpX",         { XM, Vex, EXx }, 0 },
8550     { "vandnpX",        { XM, Vex, EXx }, 0 },
8551     { "vorpX",          { XM, Vex, EXx }, 0 },
8552     { "vxorpX",         { XM, Vex, EXx }, 0 },
8553     /* 58 */
8554     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8560     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8562     /* 60 */
8563     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8571     /* 68 */
8572     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8580     /* 70 */
8581     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8582     { REG_TABLE (REG_VEX_0F71) },
8583     { REG_TABLE (REG_VEX_0F72) },
8584     { REG_TABLE (REG_VEX_0F73) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8589     /* 78 */
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8598     /* 80 */
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     /* 88 */
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     /* 90 */
8617     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     /* 98 */
8626     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     /* a0 */
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     /* a8 */
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { REG_TABLE (REG_VEX_0FAE) },
8651     { Bad_Opcode },
8652     /* b0 */
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     /* b8 */
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     /* c0 */
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8674     { Bad_Opcode },
8675     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8677     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8678     { Bad_Opcode },
8679     /* c8 */
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     /* d0 */
8689     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8697     /* d8 */
8698     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8706     /* e0 */
8707     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8715     /* e8 */
8716     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8721     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8722     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8723     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8724     /* f0 */
8725     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8726     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8727     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8728     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8729     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8730     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8731     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8732     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8733     /* f8 */
8734     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8735     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8736     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8738     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8739     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8740     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8741     { Bad_Opcode },
8742   },
8743   /* VEX_0F38 */
8744   {
8745     /* 00 */
8746     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8754     /* 08 */
8755     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8763     /* 10 */
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8772     /* 18 */
8773     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8776     { Bad_Opcode },
8777     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8780     { Bad_Opcode },
8781     /* 20 */
8782     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     /* 28 */
8791     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8799     /* 30 */
8800     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8808     /* 38 */
8809     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8817     /* 40 */
8818     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8826     /* 48 */
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     /* 50 */
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* 58 */
8845     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     /* 60 */
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     /* 68 */
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     /* 70 */
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     /* 78 */
8881     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     /* 80 */
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     /* 88 */
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8904     { Bad_Opcode },
8905     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8906     { Bad_Opcode },
8907     /* 90 */
8908     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8916     /* 98 */
8917     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8925     /* a0 */
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8934     /* a8 */
8935     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8943     /* b0 */
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8952     /* b8 */
8953     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8961     /* c0 */
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     /* c8 */
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8979     /* d0 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* d8 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8997     /* e0 */
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     /* e8 */
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     /* f0 */
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9019     { REG_TABLE (REG_VEX_0F38F3) },
9020     { Bad_Opcode },
9021     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9024     /* f8 */
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033   },
9034   /* VEX_0F3A */
9035   {
9036     /* 00 */
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9040     { Bad_Opcode },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9044     { Bad_Opcode },
9045     /* 08 */
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9054     /* 10 */
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9063     /* 18 */
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     /* 20 */
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     /* 28 */
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     /* 30 */
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     /* 38 */
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     /* 40 */
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9112     { Bad_Opcode },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9114     { Bad_Opcode },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9116     { Bad_Opcode },
9117     /* 48 */
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     /* 50 */
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     /* 58 */
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9144     /* 60 */
9145     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     /* 68 */
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9161     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9162     /* 70 */
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     /* 78 */
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9177     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9180     /* 80 */
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     /* 88 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     /* 90 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     /* 98 */
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     /* a0 */
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     /* a8 */
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     /* b0 */
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     /* b8 */
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     /* c0 */
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* c8 */
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9269     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9270     /* d0 */
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     /* d8 */
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9288     /* e0 */
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     /* e8 */
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     /* f0 */
9307     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     /* f8 */
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324   },
9325 };
9326
9327 #include "i386-dis-evex.h"
9328
9329 static const struct dis386 vex_len_table[][2] = {
9330   /* VEX_LEN_0F12_P_0_M_0 */
9331   {
9332     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9333   },
9334
9335   /* VEX_LEN_0F12_P_0_M_1 */
9336   {
9337     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9338   },
9339
9340   /* VEX_LEN_0F12_P_2 */
9341   {
9342     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9343   },
9344
9345   /* VEX_LEN_0F13_M_0 */
9346   {
9347     { "vmovlpX",        { EXq, XM }, 0 },
9348   },
9349
9350   /* VEX_LEN_0F16_P_0_M_0 */
9351   {
9352     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9353   },
9354
9355   /* VEX_LEN_0F16_P_0_M_1 */
9356   {
9357     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9358   },
9359
9360   /* VEX_LEN_0F16_P_2 */
9361   {
9362     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9363   },
9364
9365   /* VEX_LEN_0F17_M_0 */
9366   {
9367     { "vmovhpX",        { EXq, XM }, 0 },
9368   },
9369
9370   /* VEX_LEN_0F41_P_0 */
9371   {
9372     { Bad_Opcode },
9373     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9374   },
9375   /* VEX_LEN_0F41_P_2 */
9376   {
9377     { Bad_Opcode },
9378     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9379   },
9380   /* VEX_LEN_0F42_P_0 */
9381   {
9382     { Bad_Opcode },
9383     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9384   },
9385   /* VEX_LEN_0F42_P_2 */
9386   {
9387     { Bad_Opcode },
9388     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9389   },
9390   /* VEX_LEN_0F44_P_0 */
9391   {
9392     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9393   },
9394   /* VEX_LEN_0F44_P_2 */
9395   {
9396     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9397   },
9398   /* VEX_LEN_0F45_P_0 */
9399   {
9400     { Bad_Opcode },
9401     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9402   },
9403   /* VEX_LEN_0F45_P_2 */
9404   {
9405     { Bad_Opcode },
9406     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9407   },
9408   /* VEX_LEN_0F46_P_0 */
9409   {
9410     { Bad_Opcode },
9411     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9412   },
9413   /* VEX_LEN_0F46_P_2 */
9414   {
9415     { Bad_Opcode },
9416     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9417   },
9418   /* VEX_LEN_0F47_P_0 */
9419   {
9420     { Bad_Opcode },
9421     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9422   },
9423   /* VEX_LEN_0F47_P_2 */
9424   {
9425     { Bad_Opcode },
9426     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9427   },
9428   /* VEX_LEN_0F4A_P_0 */
9429   {
9430     { Bad_Opcode },
9431     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9432   },
9433   /* VEX_LEN_0F4A_P_2 */
9434   {
9435     { Bad_Opcode },
9436     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9437   },
9438   /* VEX_LEN_0F4B_P_0 */
9439   {
9440     { Bad_Opcode },
9441     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9442   },
9443   /* VEX_LEN_0F4B_P_2 */
9444   {
9445     { Bad_Opcode },
9446     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9447   },
9448
9449   /* VEX_LEN_0F6E_P_2 */
9450   {
9451     { "vmovK",          { XMScalar, Edq }, 0 },
9452   },
9453
9454   /* VEX_LEN_0F77_P_1 */
9455   {
9456     { "vzeroupper",     { XX }, 0 },
9457     { "vzeroall",       { XX }, 0 },
9458   },
9459
9460   /* VEX_LEN_0F7E_P_1 */
9461   {
9462     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9463   },
9464
9465   /* VEX_LEN_0F7E_P_2 */
9466   {
9467     { "vmovK",          { Edq, XMScalar }, 0 },
9468   },
9469
9470   /* VEX_LEN_0F90_P_0 */
9471   {
9472     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9473   },
9474
9475   /* VEX_LEN_0F90_P_2 */
9476   {
9477     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9478   },
9479
9480   /* VEX_LEN_0F91_P_0 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9483   },
9484
9485   /* VEX_LEN_0F91_P_2 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9488   },
9489
9490   /* VEX_LEN_0F92_P_0 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9493   },
9494
9495   /* VEX_LEN_0F92_P_2 */
9496   {
9497     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9498   },
9499
9500   /* VEX_LEN_0F92_P_3 */
9501   {
9502     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9503   },
9504
9505   /* VEX_LEN_0F93_P_0 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9508   },
9509
9510   /* VEX_LEN_0F93_P_2 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9513   },
9514
9515   /* VEX_LEN_0F93_P_3 */
9516   {
9517     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9518   },
9519
9520   /* VEX_LEN_0F98_P_0 */
9521   {
9522     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9523   },
9524
9525   /* VEX_LEN_0F98_P_2 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9528   },
9529
9530   /* VEX_LEN_0F99_P_0 */
9531   {
9532     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9533   },
9534
9535   /* VEX_LEN_0F99_P_2 */
9536   {
9537     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9538   },
9539
9540   /* VEX_LEN_0FAE_R_2_M_0 */
9541   {
9542     { "vldmxcsr",       { Md }, 0 },
9543   },
9544
9545   /* VEX_LEN_0FAE_R_3_M_0 */
9546   {
9547     { "vstmxcsr",       { Md }, 0 },
9548   },
9549
9550   /* VEX_LEN_0FC4_P_2 */
9551   {
9552     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9553   },
9554
9555   /* VEX_LEN_0FC5_P_2 */
9556   {
9557     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9558   },
9559
9560   /* VEX_LEN_0FD6_P_2 */
9561   {
9562     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9563   },
9564
9565   /* VEX_LEN_0FF7_P_2 */
9566   {
9567     { "vmaskmovdqu",    { XM, XS }, 0 },
9568   },
9569
9570   /* VEX_LEN_0F3816_P_2 */
9571   {
9572     { Bad_Opcode },
9573     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9574   },
9575
9576   /* VEX_LEN_0F3819_P_2 */
9577   {
9578     { Bad_Opcode },
9579     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9580   },
9581
9582   /* VEX_LEN_0F381A_P_2_M_0 */
9583   {
9584     { Bad_Opcode },
9585     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9586   },
9587
9588   /* VEX_LEN_0F3836_P_2 */
9589   {
9590     { Bad_Opcode },
9591     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9592   },
9593
9594   /* VEX_LEN_0F3841_P_2 */
9595   {
9596     { "vphminposuw",    { XM, EXx }, 0 },
9597   },
9598
9599   /* VEX_LEN_0F385A_P_2_M_0 */
9600   {
9601     { Bad_Opcode },
9602     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9603   },
9604
9605   /* VEX_LEN_0F38DB_P_2 */
9606   {
9607     { "vaesimc",        { XM, EXx }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F38F2_P_0 */
9611   {
9612     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9613   },
9614
9615   /* VEX_LEN_0F38F3_R_1_P_0 */
9616   {
9617     { "blsrS",          { VexGdq, Edq }, 0 },
9618   },
9619
9620   /* VEX_LEN_0F38F3_R_2_P_0 */
9621   {
9622     { "blsmskS",        { VexGdq, Edq }, 0 },
9623   },
9624
9625   /* VEX_LEN_0F38F3_R_3_P_0 */
9626   {
9627     { "blsiS",          { VexGdq, Edq }, 0 },
9628   },
9629
9630   /* VEX_LEN_0F38F5_P_0 */
9631   {
9632     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9633   },
9634
9635   /* VEX_LEN_0F38F5_P_1 */
9636   {
9637     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9638   },
9639
9640   /* VEX_LEN_0F38F5_P_3 */
9641   {
9642     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9643   },
9644
9645   /* VEX_LEN_0F38F6_P_3 */
9646   {
9647     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9648   },
9649
9650   /* VEX_LEN_0F38F7_P_0 */
9651   {
9652     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9653   },
9654
9655   /* VEX_LEN_0F38F7_P_1 */
9656   {
9657     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9658   },
9659
9660   /* VEX_LEN_0F38F7_P_2 */
9661   {
9662     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9663   },
9664
9665   /* VEX_LEN_0F38F7_P_3 */
9666   {
9667     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9668   },
9669
9670   /* VEX_LEN_0F3A00_P_2 */
9671   {
9672     { Bad_Opcode },
9673     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9674   },
9675
9676   /* VEX_LEN_0F3A01_P_2 */
9677   {
9678     { Bad_Opcode },
9679     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9680   },
9681
9682   /* VEX_LEN_0F3A06_P_2 */
9683   {
9684     { Bad_Opcode },
9685     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9686   },
9687
9688   /* VEX_LEN_0F3A14_P_2 */
9689   {
9690     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9691   },
9692
9693   /* VEX_LEN_0F3A15_P_2 */
9694   {
9695     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9696   },
9697
9698   /* VEX_LEN_0F3A16_P_2  */
9699   {
9700     { "vpextrK",        { Edq, XM, Ib }, 0 },
9701   },
9702
9703   /* VEX_LEN_0F3A17_P_2 */
9704   {
9705     { "vextractps",     { Edqd, XM, Ib }, 0 },
9706   },
9707
9708   /* VEX_LEN_0F3A18_P_2 */
9709   {
9710     { Bad_Opcode },
9711     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9712   },
9713
9714   /* VEX_LEN_0F3A19_P_2 */
9715   {
9716     { Bad_Opcode },
9717     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9718   },
9719
9720   /* VEX_LEN_0F3A20_P_2 */
9721   {
9722     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9723   },
9724
9725   /* VEX_LEN_0F3A21_P_2 */
9726   {
9727     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9728   },
9729
9730   /* VEX_LEN_0F3A22_P_2 */
9731   {
9732     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9733   },
9734
9735   /* VEX_LEN_0F3A30_P_2 */
9736   {
9737     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9738   },
9739
9740   /* VEX_LEN_0F3A31_P_2 */
9741   {
9742     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9743   },
9744
9745   /* VEX_LEN_0F3A32_P_2 */
9746   {
9747     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9748   },
9749
9750   /* VEX_LEN_0F3A33_P_2 */
9751   {
9752     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9753   },
9754
9755   /* VEX_LEN_0F3A38_P_2 */
9756   {
9757     { Bad_Opcode },
9758     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9759   },
9760
9761   /* VEX_LEN_0F3A39_P_2 */
9762   {
9763     { Bad_Opcode },
9764     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9765   },
9766
9767   /* VEX_LEN_0F3A41_P_2 */
9768   {
9769     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9770   },
9771
9772   /* VEX_LEN_0F3A46_P_2 */
9773   {
9774     { Bad_Opcode },
9775     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9776   },
9777
9778   /* VEX_LEN_0F3A60_P_2 */
9779   {
9780     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9781   },
9782
9783   /* VEX_LEN_0F3A61_P_2 */
9784   {
9785     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9786   },
9787
9788   /* VEX_LEN_0F3A62_P_2 */
9789   {
9790     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9791   },
9792
9793   /* VEX_LEN_0F3A63_P_2 */
9794   {
9795     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9796   },
9797
9798   /* VEX_LEN_0F3A6A_P_2 */
9799   {
9800     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9801   },
9802
9803   /* VEX_LEN_0F3A6B_P_2 */
9804   {
9805     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9806   },
9807
9808   /* VEX_LEN_0F3A6E_P_2 */
9809   {
9810     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9811   },
9812
9813   /* VEX_LEN_0F3A6F_P_2 */
9814   {
9815     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9816   },
9817
9818   /* VEX_LEN_0F3A7A_P_2 */
9819   {
9820     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9821   },
9822
9823   /* VEX_LEN_0F3A7B_P_2 */
9824   {
9825     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9826   },
9827
9828   /* VEX_LEN_0F3A7E_P_2 */
9829   {
9830     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9831   },
9832
9833   /* VEX_LEN_0F3A7F_P_2 */
9834   {
9835     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9836   },
9837
9838   /* VEX_LEN_0F3ADF_P_2 */
9839   {
9840     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9841   },
9842
9843   /* VEX_LEN_0F3AF0_P_3 */
9844   {
9845     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9846   },
9847
9848   /* VEX_LEN_0FXOP_08_CC */
9849   {
9850      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9851   },
9852
9853   /* VEX_LEN_0FXOP_08_CD */
9854   {
9855      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9856   },
9857
9858   /* VEX_LEN_0FXOP_08_CE */
9859   {
9860      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9861   },
9862
9863   /* VEX_LEN_0FXOP_08_CF */
9864   {
9865      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9866   },
9867
9868   /* VEX_LEN_0FXOP_08_EC */
9869   {
9870      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9871   },
9872
9873   /* VEX_LEN_0FXOP_08_ED */
9874   {
9875      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9876   },
9877
9878   /* VEX_LEN_0FXOP_08_EE */
9879   {
9880      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9881   },
9882
9883   /* VEX_LEN_0FXOP_08_EF */
9884   {
9885      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9886   },
9887
9888   /* VEX_LEN_0FXOP_09_80 */
9889   {
9890     { "vfrczps",        { XM, EXxmm }, 0 },
9891     { "vfrczps",        { XM, EXymmq }, 0 },
9892   },
9893
9894   /* VEX_LEN_0FXOP_09_81 */
9895   {
9896     { "vfrczpd",        { XM, EXxmm }, 0 },
9897     { "vfrczpd",        { XM, EXymmq }, 0 },
9898   },
9899 };
9900
9901 #include "i386-dis-evex-len.h"
9902
9903 static const struct dis386 vex_w_table[][2] = {
9904   {
9905     /* VEX_W_0F41_P_0_LEN_1 */
9906     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9907     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9908   },
9909   {
9910     /* VEX_W_0F41_P_2_LEN_1 */
9911     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9912     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9913   },
9914   {
9915     /* VEX_W_0F42_P_0_LEN_1 */
9916     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9917     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9918   },
9919   {
9920     /* VEX_W_0F42_P_2_LEN_1 */
9921     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9922     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9923   },
9924   {
9925     /* VEX_W_0F44_P_0_LEN_0 */
9926     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9927     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9928   },
9929   {
9930     /* VEX_W_0F44_P_2_LEN_0 */
9931     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9932     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9933   },
9934   {
9935     /* VEX_W_0F45_P_0_LEN_1 */
9936     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9937     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9938   },
9939   {
9940     /* VEX_W_0F45_P_2_LEN_1 */
9941     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9942     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9943   },
9944   {
9945     /* VEX_W_0F46_P_0_LEN_1 */
9946     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9947     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9948   },
9949   {
9950     /* VEX_W_0F46_P_2_LEN_1 */
9951     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9952     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9953   },
9954   {
9955     /* VEX_W_0F47_P_0_LEN_1 */
9956     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9957     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9958   },
9959   {
9960     /* VEX_W_0F47_P_2_LEN_1 */
9961     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9962     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9963   },
9964   {
9965     /* VEX_W_0F4A_P_0_LEN_1 */
9966     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9967     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9968   },
9969   {
9970     /* VEX_W_0F4A_P_2_LEN_1 */
9971     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9972     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9973   },
9974   {
9975     /* VEX_W_0F4B_P_0_LEN_1 */
9976     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9977     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9978   },
9979   {
9980     /* VEX_W_0F4B_P_2_LEN_1 */
9981     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9982   },
9983   {
9984     /* VEX_W_0F90_P_0_LEN_0 */
9985     { "kmovw",          { MaskG, MaskE }, 0 },
9986     { "kmovq",          { MaskG, MaskE }, 0 },
9987   },
9988   {
9989     /* VEX_W_0F90_P_2_LEN_0 */
9990     { "kmovb",          { MaskG, MaskBDE }, 0 },
9991     { "kmovd",          { MaskG, MaskBDE }, 0 },
9992   },
9993   {
9994     /* VEX_W_0F91_P_0_LEN_0 */
9995     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9996     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9997   },
9998   {
9999     /* VEX_W_0F91_P_2_LEN_0 */
10000     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10001     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10002   },
10003   {
10004     /* VEX_W_0F92_P_0_LEN_0 */
10005     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10006   },
10007   {
10008     /* VEX_W_0F92_P_2_LEN_0 */
10009     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10010   },
10011   {
10012     /* VEX_W_0F93_P_0_LEN_0 */
10013     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10014   },
10015   {
10016     /* VEX_W_0F93_P_2_LEN_0 */
10017     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10018   },
10019   {
10020     /* VEX_W_0F98_P_0_LEN_0 */
10021     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10022     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10023   },
10024   {
10025     /* VEX_W_0F98_P_2_LEN_0 */
10026     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10027     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10028   },
10029   {
10030     /* VEX_W_0F99_P_0_LEN_0 */
10031     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10032     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10033   },
10034   {
10035     /* VEX_W_0F99_P_2_LEN_0 */
10036     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10037     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10038   },
10039   {
10040     /* VEX_W_0F380C_P_2  */
10041     { "vpermilps",      { XM, Vex, EXx }, 0 },
10042   },
10043   {
10044     /* VEX_W_0F380D_P_2  */
10045     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10046   },
10047   {
10048     /* VEX_W_0F380E_P_2  */
10049     { "vtestps",        { XM, EXx }, 0 },
10050   },
10051   {
10052     /* VEX_W_0F380F_P_2  */
10053     { "vtestpd",        { XM, EXx }, 0 },
10054   },
10055   {
10056     /* VEX_W_0F3816_P_2  */
10057     { "vpermps",        { XM, Vex, EXx }, 0 },
10058   },
10059   {
10060     /* VEX_W_0F3818_P_2 */
10061     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10062   },
10063   {
10064     /* VEX_W_0F3819_P_2 */
10065     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10066   },
10067   {
10068     /* VEX_W_0F381A_P_2_M_0 */
10069     { "vbroadcastf128", { XM, Mxmm }, 0 },
10070   },
10071   {
10072     /* VEX_W_0F382C_P_2_M_0 */
10073     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10074   },
10075   {
10076     /* VEX_W_0F382D_P_2_M_0 */
10077     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10078   },
10079   {
10080     /* VEX_W_0F382E_P_2_M_0 */
10081     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10082   },
10083   {
10084     /* VEX_W_0F382F_P_2_M_0 */
10085     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10086   },
10087   {
10088     /* VEX_W_0F3836_P_2  */
10089     { "vpermd",         { XM, Vex, EXx }, 0 },
10090   },
10091   {
10092     /* VEX_W_0F3846_P_2 */
10093     { "vpsravd",        { XM, Vex, EXx }, 0 },
10094   },
10095   {
10096     /* VEX_W_0F3858_P_2 */
10097     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10098   },
10099   {
10100     /* VEX_W_0F3859_P_2 */
10101     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10102   },
10103   {
10104     /* VEX_W_0F385A_P_2_M_0 */
10105     { "vbroadcasti128", { XM, Mxmm }, 0 },
10106   },
10107   {
10108     /* VEX_W_0F3878_P_2 */
10109     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10110   },
10111   {
10112     /* VEX_W_0F3879_P_2 */
10113     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10114   },
10115   {
10116     /* VEX_W_0F38CF_P_2 */
10117     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10118   },
10119   {
10120     /* VEX_W_0F3A00_P_2 */
10121     { Bad_Opcode },
10122     { "vpermq",         { XM, EXx, Ib }, 0 },
10123   },
10124   {
10125     /* VEX_W_0F3A01_P_2 */
10126     { Bad_Opcode },
10127     { "vpermpd",        { XM, EXx, Ib }, 0 },
10128   },
10129   {
10130     /* VEX_W_0F3A02_P_2 */
10131     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10132   },
10133   {
10134     /* VEX_W_0F3A04_P_2 */
10135     { "vpermilps",      { XM, EXx, Ib }, 0 },
10136   },
10137   {
10138     /* VEX_W_0F3A05_P_2 */
10139     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10140   },
10141   {
10142     /* VEX_W_0F3A06_P_2 */
10143     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10144   },
10145   {
10146     /* VEX_W_0F3A18_P_2 */
10147     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10148   },
10149   {
10150     /* VEX_W_0F3A19_P_2 */
10151     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10152   },
10153   {
10154     /* VEX_W_0F3A30_P_2_LEN_0 */
10155     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10156     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10157   },
10158   {
10159     /* VEX_W_0F3A31_P_2_LEN_0 */
10160     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10161     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10162   },
10163   {
10164     /* VEX_W_0F3A32_P_2_LEN_0 */
10165     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10166     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10167   },
10168   {
10169     /* VEX_W_0F3A33_P_2_LEN_0 */
10170     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10171     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10172   },
10173   {
10174     /* VEX_W_0F3A38_P_2 */
10175     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10176   },
10177   {
10178     /* VEX_W_0F3A39_P_2 */
10179     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10180   },
10181   {
10182     /* VEX_W_0F3A46_P_2 */
10183     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10184   },
10185   {
10186     /* VEX_W_0F3A48_P_2 */
10187     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10188     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10189   },
10190   {
10191     /* VEX_W_0F3A49_P_2 */
10192     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10193     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10194   },
10195   {
10196     /* VEX_W_0F3A4A_P_2 */
10197     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10198   },
10199   {
10200     /* VEX_W_0F3A4B_P_2 */
10201     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10202   },
10203   {
10204     /* VEX_W_0F3A4C_P_2 */
10205     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10206   },
10207   {
10208     /* VEX_W_0F3ACE_P_2 */
10209     { Bad_Opcode },
10210     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10211   },
10212   {
10213     /* VEX_W_0F3ACF_P_2 */
10214     { Bad_Opcode },
10215     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10216   },
10217
10218 #include "i386-dis-evex-w.h"
10219 };
10220
10221 static const struct dis386 mod_table[][2] = {
10222   {
10223     /* MOD_8D */
10224     { "leaS",           { Gv, M }, 0 },
10225   },
10226   {
10227     /* MOD_C6_REG_7 */
10228     { Bad_Opcode },
10229     { RM_TABLE (RM_C6_REG_7) },
10230   },
10231   {
10232     /* MOD_C7_REG_7 */
10233     { Bad_Opcode },
10234     { RM_TABLE (RM_C7_REG_7) },
10235   },
10236   {
10237     /* MOD_FF_REG_3 */
10238     { "Jcall^", { indirEp }, 0 },
10239   },
10240   {
10241     /* MOD_FF_REG_5 */
10242     { "Jjmp^", { indirEp }, 0 },
10243   },
10244   {
10245     /* MOD_0F01_REG_0 */
10246     { X86_64_TABLE (X86_64_0F01_REG_0) },
10247     { RM_TABLE (RM_0F01_REG_0) },
10248   },
10249   {
10250     /* MOD_0F01_REG_1 */
10251     { X86_64_TABLE (X86_64_0F01_REG_1) },
10252     { RM_TABLE (RM_0F01_REG_1) },
10253   },
10254   {
10255     /* MOD_0F01_REG_2 */
10256     { X86_64_TABLE (X86_64_0F01_REG_2) },
10257     { RM_TABLE (RM_0F01_REG_2) },
10258   },
10259   {
10260     /* MOD_0F01_REG_3 */
10261     { X86_64_TABLE (X86_64_0F01_REG_3) },
10262     { RM_TABLE (RM_0F01_REG_3) },
10263   },
10264   {
10265     /* MOD_0F01_REG_5 */
10266     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10267     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10268   },
10269   {
10270     /* MOD_0F01_REG_7 */
10271     { "invlpg",         { Mb }, 0 },
10272     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10273   },
10274   {
10275     /* MOD_0F12_PREFIX_0 */
10276     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10277     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10278   },
10279   {
10280     /* MOD_0F13 */
10281     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10282   },
10283   {
10284     /* MOD_0F16_PREFIX_0 */
10285     { "movhps",         { XM, EXq }, 0 },
10286     { "movlhps",        { XM, EXq }, 0 },
10287   },
10288   {
10289     /* MOD_0F17 */
10290     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10291   },
10292   {
10293     /* MOD_0F18_REG_0 */
10294     { "prefetchnta",    { Mb }, 0 },
10295   },
10296   {
10297     /* MOD_0F18_REG_1 */
10298     { "prefetcht0",     { Mb }, 0 },
10299   },
10300   {
10301     /* MOD_0F18_REG_2 */
10302     { "prefetcht1",     { Mb }, 0 },
10303   },
10304   {
10305     /* MOD_0F18_REG_3 */
10306     { "prefetcht2",     { Mb }, 0 },
10307   },
10308   {
10309     /* MOD_0F18_REG_4 */
10310     { "nop/reserved",   { Mb }, 0 },
10311   },
10312   {
10313     /* MOD_0F18_REG_5 */
10314     { "nop/reserved",   { Mb }, 0 },
10315   },
10316   {
10317     /* MOD_0F18_REG_6 */
10318     { "nop/reserved",   { Mb }, 0 },
10319   },
10320   {
10321     /* MOD_0F18_REG_7 */
10322     { "nop/reserved",   { Mb }, 0 },
10323   },
10324   {
10325     /* MOD_0F1A_PREFIX_0 */
10326     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10327     { "nopQ",           { Ev }, 0 },
10328   },
10329   {
10330     /* MOD_0F1B_PREFIX_0 */
10331     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10332     { "nopQ",           { Ev }, 0 },
10333   },
10334   {
10335     /* MOD_0F1B_PREFIX_1 */
10336     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10337     { "nopQ",           { Ev }, 0 },
10338   },
10339   {
10340     /* MOD_0F1C_PREFIX_0 */
10341     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10342     { "nopQ",           { Ev }, 0 },
10343   },
10344   {
10345     /* MOD_0F1E_PREFIX_1 */
10346     { "nopQ",           { Ev }, 0 },
10347     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10348   },
10349   {
10350     /* MOD_0F24 */
10351     { Bad_Opcode },
10352     { "movL",           { Rd, Td }, 0 },
10353   },
10354   {
10355     /* MOD_0F26 */
10356     { Bad_Opcode },
10357     { "movL",           { Td, Rd }, 0 },
10358   },
10359   {
10360     /* MOD_0F2B_PREFIX_0 */
10361     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10362   },
10363   {
10364     /* MOD_0F2B_PREFIX_1 */
10365     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10366   },
10367   {
10368     /* MOD_0F2B_PREFIX_2 */
10369     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10370   },
10371   {
10372     /* MOD_0F2B_PREFIX_3 */
10373     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10374   },
10375   {
10376     /* MOD_0F51 */
10377     { Bad_Opcode },
10378     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10379   },
10380   {
10381     /* MOD_0F71_REG_2 */
10382     { Bad_Opcode },
10383     { "psrlw",          { MS, Ib }, 0 },
10384   },
10385   {
10386     /* MOD_0F71_REG_4 */
10387     { Bad_Opcode },
10388     { "psraw",          { MS, Ib }, 0 },
10389   },
10390   {
10391     /* MOD_0F71_REG_6 */
10392     { Bad_Opcode },
10393     { "psllw",          { MS, Ib }, 0 },
10394   },
10395   {
10396     /* MOD_0F72_REG_2 */
10397     { Bad_Opcode },
10398     { "psrld",          { MS, Ib }, 0 },
10399   },
10400   {
10401     /* MOD_0F72_REG_4 */
10402     { Bad_Opcode },
10403     { "psrad",          { MS, Ib }, 0 },
10404   },
10405   {
10406     /* MOD_0F72_REG_6 */
10407     { Bad_Opcode },
10408     { "pslld",          { MS, Ib }, 0 },
10409   },
10410   {
10411     /* MOD_0F73_REG_2 */
10412     { Bad_Opcode },
10413     { "psrlq",          { MS, Ib }, 0 },
10414   },
10415   {
10416     /* MOD_0F73_REG_3 */
10417     { Bad_Opcode },
10418     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10419   },
10420   {
10421     /* MOD_0F73_REG_6 */
10422     { Bad_Opcode },
10423     { "psllq",          { MS, Ib }, 0 },
10424   },
10425   {
10426     /* MOD_0F73_REG_7 */
10427     { Bad_Opcode },
10428     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10429   },
10430   {
10431     /* MOD_0FAE_REG_0 */
10432     { "fxsave",         { FXSAVE }, 0 },
10433     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10434   },
10435   {
10436     /* MOD_0FAE_REG_1 */
10437     { "fxrstor",        { FXSAVE }, 0 },
10438     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10439   },
10440   {
10441     /* MOD_0FAE_REG_2 */
10442     { "ldmxcsr",        { Md }, 0 },
10443     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10444   },
10445   {
10446     /* MOD_0FAE_REG_3 */
10447     { "stmxcsr",        { Md }, 0 },
10448     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10449   },
10450   {
10451     /* MOD_0FAE_REG_4 */
10452     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10453     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10454   },
10455   {
10456     /* MOD_0FAE_REG_5 */
10457     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10458     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10459   },
10460   {
10461     /* MOD_0FAE_REG_6 */
10462     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10463     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10464   },
10465   {
10466     /* MOD_0FAE_REG_7 */
10467     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10468     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10469   },
10470   {
10471     /* MOD_0FB2 */
10472     { "lssS",           { Gv, Mp }, 0 },
10473   },
10474   {
10475     /* MOD_0FB4 */
10476     { "lfsS",           { Gv, Mp }, 0 },
10477   },
10478   {
10479     /* MOD_0FB5 */
10480     { "lgsS",           { Gv, Mp }, 0 },
10481   },
10482   {
10483     /* MOD_0FC3 */
10484     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10485   },
10486   {
10487     /* MOD_0FC7_REG_3 */
10488     { "xrstors",        { FXSAVE }, 0 },
10489   },
10490   {
10491     /* MOD_0FC7_REG_4 */
10492     { "xsavec",         { FXSAVE }, 0 },
10493   },
10494   {
10495     /* MOD_0FC7_REG_5 */
10496     { "xsaves",         { FXSAVE }, 0 },
10497   },
10498   {
10499     /* MOD_0FC7_REG_6 */
10500     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10501     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10502   },
10503   {
10504     /* MOD_0FC7_REG_7 */
10505     { "vmptrst",        { Mq }, 0 },
10506     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10507   },
10508   {
10509     /* MOD_0FD7 */
10510     { Bad_Opcode },
10511     { "pmovmskb",       { Gdq, MS }, 0 },
10512   },
10513   {
10514     /* MOD_0FE7_PREFIX_2 */
10515     { "movntdq",        { Mx, XM }, 0 },
10516   },
10517   {
10518     /* MOD_0FF0_PREFIX_3 */
10519     { "lddqu",          { XM, M }, 0 },
10520   },
10521   {
10522     /* MOD_0F382A_PREFIX_2 */
10523     { "movntdqa",       { XM, Mx }, 0 },
10524   },
10525   {
10526     /* MOD_0F38F5_PREFIX_2 */
10527     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10528   },
10529   {
10530     /* MOD_0F38F6_PREFIX_0 */
10531     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10532   },
10533   {
10534     /* MOD_0F38F8_PREFIX_1 */
10535     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10536   },
10537   {
10538     /* MOD_0F38F8_PREFIX_2 */
10539     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10540   },
10541   {
10542     /* MOD_0F38F8_PREFIX_3 */
10543     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10544   },
10545   {
10546     /* MOD_0F38F9_PREFIX_0 */
10547     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10548   },
10549   {
10550     /* MOD_62_32BIT */
10551     { "bound{S|}",      { Gv, Ma }, 0 },
10552     { EVEX_TABLE (EVEX_0F) },
10553   },
10554   {
10555     /* MOD_C4_32BIT */
10556     { "lesS",           { Gv, Mp }, 0 },
10557     { VEX_C4_TABLE (VEX_0F) },
10558   },
10559   {
10560     /* MOD_C5_32BIT */
10561     { "ldsS",           { Gv, Mp }, 0 },
10562     { VEX_C5_TABLE (VEX_0F) },
10563   },
10564   {
10565     /* MOD_VEX_0F12_PREFIX_0 */
10566     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10567     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10568   },
10569   {
10570     /* MOD_VEX_0F13 */
10571     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10572   },
10573   {
10574     /* MOD_VEX_0F16_PREFIX_0 */
10575     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10576     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10577   },
10578   {
10579     /* MOD_VEX_0F17 */
10580     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10581   },
10582   {
10583     /* MOD_VEX_0F2B */
10584     { "vmovntpX",       { Mx, XM }, 0 },
10585   },
10586   {
10587     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10588     { Bad_Opcode },
10589     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10590   },
10591   {
10592     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10593     { Bad_Opcode },
10594     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10598     { Bad_Opcode },
10599     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10603     { Bad_Opcode },
10604     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10608     { Bad_Opcode },
10609     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10610   },
10611   {
10612     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10613     { Bad_Opcode },
10614     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10615   },
10616   {
10617     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10618     { Bad_Opcode },
10619     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10620   },
10621   {
10622     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10623     { Bad_Opcode },
10624     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10625   },
10626   {
10627     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10628     { Bad_Opcode },
10629     { "knotw",          { MaskG, MaskR }, 0 },
10630   },
10631   {
10632     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10633     { Bad_Opcode },
10634     { "knotq",          { MaskG, MaskR }, 0 },
10635   },
10636   {
10637     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10638     { Bad_Opcode },
10639     { "knotb",          { MaskG, MaskR }, 0 },
10640   },
10641   {
10642     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10643     { Bad_Opcode },
10644     { "knotd",          { MaskG, MaskR }, 0 },
10645   },
10646   {
10647     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10648     { Bad_Opcode },
10649     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10650   },
10651   {
10652     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10653     { Bad_Opcode },
10654     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10655   },
10656   {
10657     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10658     { Bad_Opcode },
10659     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10660   },
10661   {
10662     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10663     { Bad_Opcode },
10664     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10665   },
10666  {
10667     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10668     { Bad_Opcode },
10669     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10670   },
10671   {
10672     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10673     { Bad_Opcode },
10674     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10675   },
10676   {
10677     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10678     { Bad_Opcode },
10679     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10680   },
10681   {
10682     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10683     { Bad_Opcode },
10684     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10688     { Bad_Opcode },
10689     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10693     { Bad_Opcode },
10694     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10698     { Bad_Opcode },
10699     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10703     { Bad_Opcode },
10704     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10708     { Bad_Opcode },
10709     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10713     { Bad_Opcode },
10714     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10718     { Bad_Opcode },
10719     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10723     { Bad_Opcode },
10724     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10725   },
10726   {
10727     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10728     { Bad_Opcode },
10729     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10730   },
10731   {
10732     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10733     { Bad_Opcode },
10734     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10735   },
10736   {
10737     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10738     { Bad_Opcode },
10739     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10740   },
10741   {
10742     /* MOD_VEX_0F50 */
10743     { Bad_Opcode },
10744     { "vmovmskpX",      { Gdq, XS }, 0 },
10745   },
10746   {
10747     /* MOD_VEX_0F71_REG_2 */
10748     { Bad_Opcode },
10749     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10750   },
10751   {
10752     /* MOD_VEX_0F71_REG_4 */
10753     { Bad_Opcode },
10754     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10755   },
10756   {
10757     /* MOD_VEX_0F71_REG_6 */
10758     { Bad_Opcode },
10759     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10760   },
10761   {
10762     /* MOD_VEX_0F72_REG_2 */
10763     { Bad_Opcode },
10764     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10765   },
10766   {
10767     /* MOD_VEX_0F72_REG_4 */
10768     { Bad_Opcode },
10769     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10770   },
10771   {
10772     /* MOD_VEX_0F72_REG_6 */
10773     { Bad_Opcode },
10774     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10775   },
10776   {
10777     /* MOD_VEX_0F73_REG_2 */
10778     { Bad_Opcode },
10779     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10780   },
10781   {
10782     /* MOD_VEX_0F73_REG_3 */
10783     { Bad_Opcode },
10784     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10785   },
10786   {
10787     /* MOD_VEX_0F73_REG_6 */
10788     { Bad_Opcode },
10789     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10790   },
10791   {
10792     /* MOD_VEX_0F73_REG_7 */
10793     { Bad_Opcode },
10794     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10795   },
10796   {
10797     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10798     { "kmovw",          { Ew, MaskG }, 0 },
10799     { Bad_Opcode },
10800   },
10801   {
10802     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10803     { "kmovq",          { Eq, MaskG }, 0 },
10804     { Bad_Opcode },
10805   },
10806   {
10807     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10808     { "kmovb",          { Eb, MaskG }, 0 },
10809     { Bad_Opcode },
10810   },
10811   {
10812     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10813     { "kmovd",          { Ed, MaskG }, 0 },
10814     { Bad_Opcode },
10815   },
10816   {
10817     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10818     { Bad_Opcode },
10819     { "kmovw",          { MaskG, Rdq }, 0 },
10820   },
10821   {
10822     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10823     { Bad_Opcode },
10824     { "kmovb",          { MaskG, Rdq }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_0F92_P_3_LEN_0 */
10828     { Bad_Opcode },
10829     { "kmovK",          { MaskG, Rdq }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10833     { Bad_Opcode },
10834     { "kmovw",          { Gdq, MaskR }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10838     { Bad_Opcode },
10839     { "kmovb",          { Gdq, MaskR }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_0F93_P_3_LEN_0 */
10843     { Bad_Opcode },
10844     { "kmovK",          { Gdq, MaskR }, 0 },
10845   },
10846   {
10847     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10848     { Bad_Opcode },
10849     { "kortestw", { MaskG, MaskR }, 0 },
10850   },
10851   {
10852     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10853     { Bad_Opcode },
10854     { "kortestq", { MaskG, MaskR }, 0 },
10855   },
10856   {
10857     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10858     { Bad_Opcode },
10859     { "kortestb", { MaskG, MaskR }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10863     { Bad_Opcode },
10864     { "kortestd", { MaskG, MaskR }, 0 },
10865   },
10866   {
10867     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10868     { Bad_Opcode },
10869     { "ktestw", { MaskG, MaskR }, 0 },
10870   },
10871   {
10872     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10873     { Bad_Opcode },
10874     { "ktestq", { MaskG, MaskR }, 0 },
10875   },
10876   {
10877     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10878     { Bad_Opcode },
10879     { "ktestb", { MaskG, MaskR }, 0 },
10880   },
10881   {
10882     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10883     { Bad_Opcode },
10884     { "ktestd", { MaskG, MaskR }, 0 },
10885   },
10886   {
10887     /* MOD_VEX_0FAE_REG_2 */
10888     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10889   },
10890   {
10891     /* MOD_VEX_0FAE_REG_3 */
10892     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10893   },
10894   {
10895     /* MOD_VEX_0FD7_PREFIX_2 */
10896     { Bad_Opcode },
10897     { "vpmovmskb",      { Gdq, XS }, 0 },
10898   },
10899   {
10900     /* MOD_VEX_0FE7_PREFIX_2 */
10901     { "vmovntdq",       { Mx, XM }, 0 },
10902   },
10903   {
10904     /* MOD_VEX_0FF0_PREFIX_3 */
10905     { "vlddqu",         { XM, M }, 0 },
10906   },
10907   {
10908     /* MOD_VEX_0F381A_PREFIX_2 */
10909     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10910   },
10911   {
10912     /* MOD_VEX_0F382A_PREFIX_2 */
10913     { "vmovntdqa",      { XM, Mx }, 0 },
10914   },
10915   {
10916     /* MOD_VEX_0F382C_PREFIX_2 */
10917     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10918   },
10919   {
10920     /* MOD_VEX_0F382D_PREFIX_2 */
10921     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10922   },
10923   {
10924     /* MOD_VEX_0F382E_PREFIX_2 */
10925     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10926   },
10927   {
10928     /* MOD_VEX_0F382F_PREFIX_2 */
10929     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10930   },
10931   {
10932     /* MOD_VEX_0F385A_PREFIX_2 */
10933     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10934   },
10935   {
10936     /* MOD_VEX_0F388C_PREFIX_2 */
10937     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10938   },
10939   {
10940     /* MOD_VEX_0F388E_PREFIX_2 */
10941     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10942   },
10943   {
10944     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10945     { Bad_Opcode },
10946     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10947   },
10948   {
10949     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10950     { Bad_Opcode },
10951     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10952   },
10953   {
10954     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10955     { Bad_Opcode },
10956     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10957   },
10958   {
10959     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10960     { Bad_Opcode },
10961     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10962   },
10963   {
10964     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10965     { Bad_Opcode },
10966     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10967   },
10968   {
10969     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10970     { Bad_Opcode },
10971     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10972   },
10973   {
10974     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10975     { Bad_Opcode },
10976     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10977   },
10978   {
10979     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10980     { Bad_Opcode },
10981     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10982   },
10983
10984 #include "i386-dis-evex-mod.h"
10985 };
10986
10987 static const struct dis386 rm_table[][8] = {
10988   {
10989     /* RM_C6_REG_7 */
10990     { "xabort",         { Skip_MODRM, Ib }, 0 },
10991   },
10992   {
10993     /* RM_C7_REG_7 */
10994     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10995   },
10996   {
10997     /* RM_0F01_REG_0 */
10998     { "enclv",          { Skip_MODRM }, 0 },
10999     { "vmcall",         { Skip_MODRM }, 0 },
11000     { "vmlaunch",       { Skip_MODRM }, 0 },
11001     { "vmresume",       { Skip_MODRM }, 0 },
11002     { "vmxoff",         { Skip_MODRM }, 0 },
11003     { "pconfig",        { Skip_MODRM }, 0 },
11004   },
11005   {
11006     /* RM_0F01_REG_1 */
11007     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11008     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11009     { "clac",           { Skip_MODRM }, 0 },
11010     { "stac",           { Skip_MODRM }, 0 },
11011     { Bad_Opcode },
11012     { Bad_Opcode },
11013     { Bad_Opcode },
11014     { "encls",          { Skip_MODRM }, 0 },
11015   },
11016   {
11017     /* RM_0F01_REG_2 */
11018     { "xgetbv",         { Skip_MODRM }, 0 },
11019     { "xsetbv",         { Skip_MODRM }, 0 },
11020     { Bad_Opcode },
11021     { Bad_Opcode },
11022     { "vmfunc",         { Skip_MODRM }, 0 },
11023     { "xend",           { Skip_MODRM }, 0 },
11024     { "xtest",          { Skip_MODRM }, 0 },
11025     { "enclu",          { Skip_MODRM }, 0 },
11026   },
11027   {
11028     /* RM_0F01_REG_3 */
11029     { "vmrun",          { Skip_MODRM }, 0 },
11030     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
11031     { "vmload",         { Skip_MODRM }, 0 },
11032     { "vmsave",         { Skip_MODRM }, 0 },
11033     { "stgi",           { Skip_MODRM }, 0 },
11034     { "clgi",           { Skip_MODRM }, 0 },
11035     { "skinit",         { Skip_MODRM }, 0 },
11036     { "invlpga",        { Skip_MODRM }, 0 },
11037   },
11038   {
11039     /* RM_0F01_REG_5_MOD_3 */
11040     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11041     { Bad_Opcode },
11042     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11043     { Bad_Opcode },
11044     { Bad_Opcode },
11045     { Bad_Opcode },
11046     { "rdpkru",         { Skip_MODRM }, 0 },
11047     { "wrpkru",         { Skip_MODRM }, 0 },
11048   },
11049   {
11050     /* RM_0F01_REG_7_MOD_3 */
11051     { "swapgs",         { Skip_MODRM }, 0  },
11052     { "rdtscp",         { Skip_MODRM }, 0  },
11053     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11054     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11055     { "clzero",         { Skip_MODRM }, 0  },
11056     { "rdpru",          { Skip_MODRM }, 0  },
11057   },
11058   {
11059     /* RM_0F1E_P_1_MOD_3_REG_7 */
11060     { "nopQ",           { Ev }, 0 },
11061     { "nopQ",           { Ev }, 0 },
11062     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11063     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11064     { "nopQ",           { Ev }, 0 },
11065     { "nopQ",           { Ev }, 0 },
11066     { "nopQ",           { Ev }, 0 },
11067     { "nopQ",           { Ev }, 0 },
11068   },
11069   {
11070     /* RM_0FAE_REG_6_MOD_3 */
11071     { "mfence",         { Skip_MODRM }, 0 },
11072   },
11073   {
11074     /* RM_0FAE_REG_7_MOD_3 */
11075     { "sfence",         { Skip_MODRM }, 0 },
11076
11077   },
11078 };
11079
11080 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11081
11082 /* We use the high bit to indicate different name for the same
11083    prefix.  */
11084 #define REP_PREFIX      (0xf3 | 0x100)
11085 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11086 #define XRELEASE_PREFIX (0xf3 | 0x400)
11087 #define BND_PREFIX      (0xf2 | 0x400)
11088 #define NOTRACK_PREFIX  (0x3e | 0x100)
11089
11090 /* Remember if the current op is a jump instruction.  */
11091 static bfd_boolean op_is_jump = FALSE;
11092
11093 static int
11094 ckprefix (void)
11095 {
11096   int newrex, i, length;
11097   rex = 0;
11098   rex_ignored = 0;
11099   prefixes = 0;
11100   used_prefixes = 0;
11101   rex_used = 0;
11102   last_lock_prefix = -1;
11103   last_repz_prefix = -1;
11104   last_repnz_prefix = -1;
11105   last_data_prefix = -1;
11106   last_addr_prefix = -1;
11107   last_rex_prefix = -1;
11108   last_seg_prefix = -1;
11109   fwait_prefix = -1;
11110   active_seg_prefix = 0;
11111   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11112     all_prefixes[i] = 0;
11113   i = 0;
11114   length = 0;
11115   /* The maximum instruction length is 15bytes.  */
11116   while (length < MAX_CODE_LENGTH - 1)
11117     {
11118       FETCH_DATA (the_info, codep + 1);
11119       newrex = 0;
11120       switch (*codep)
11121         {
11122         /* REX prefixes family.  */
11123         case 0x40:
11124         case 0x41:
11125         case 0x42:
11126         case 0x43:
11127         case 0x44:
11128         case 0x45:
11129         case 0x46:
11130         case 0x47:
11131         case 0x48:
11132         case 0x49:
11133         case 0x4a:
11134         case 0x4b:
11135         case 0x4c:
11136         case 0x4d:
11137         case 0x4e:
11138         case 0x4f:
11139           if (address_mode == mode_64bit)
11140             newrex = *codep;
11141           else
11142             return 1;
11143           last_rex_prefix = i;
11144           break;
11145         case 0xf3:
11146           prefixes |= PREFIX_REPZ;
11147           last_repz_prefix = i;
11148           break;
11149         case 0xf2:
11150           prefixes |= PREFIX_REPNZ;
11151           last_repnz_prefix = i;
11152           break;
11153         case 0xf0:
11154           prefixes |= PREFIX_LOCK;
11155           last_lock_prefix = i;
11156           break;
11157         case 0x2e:
11158           prefixes |= PREFIX_CS;
11159           last_seg_prefix = i;
11160           active_seg_prefix = PREFIX_CS;
11161           break;
11162         case 0x36:
11163           prefixes |= PREFIX_SS;
11164           last_seg_prefix = i;
11165           active_seg_prefix = PREFIX_SS;
11166           break;
11167         case 0x3e:
11168           prefixes |= PREFIX_DS;
11169           last_seg_prefix = i;
11170           active_seg_prefix = PREFIX_DS;
11171           break;
11172         case 0x26:
11173           prefixes |= PREFIX_ES;
11174           last_seg_prefix = i;
11175           active_seg_prefix = PREFIX_ES;
11176           break;
11177         case 0x64:
11178           prefixes |= PREFIX_FS;
11179           last_seg_prefix = i;
11180           active_seg_prefix = PREFIX_FS;
11181           break;
11182         case 0x65:
11183           prefixes |= PREFIX_GS;
11184           last_seg_prefix = i;
11185           active_seg_prefix = PREFIX_GS;
11186           break;
11187         case 0x66:
11188           prefixes |= PREFIX_DATA;
11189           last_data_prefix = i;
11190           break;
11191         case 0x67:
11192           prefixes |= PREFIX_ADDR;
11193           last_addr_prefix = i;
11194           break;
11195         case FWAIT_OPCODE:
11196           /* fwait is really an instruction.  If there are prefixes
11197              before the fwait, they belong to the fwait, *not* to the
11198              following instruction.  */
11199           fwait_prefix = i;
11200           if (prefixes || rex)
11201             {
11202               prefixes |= PREFIX_FWAIT;
11203               codep++;
11204               /* This ensures that the previous REX prefixes are noticed
11205                  as unused prefixes, as in the return case below.  */
11206               rex_used = rex;
11207               return 1;
11208             }
11209           prefixes = PREFIX_FWAIT;
11210           break;
11211         default:
11212           return 1;
11213         }
11214       /* Rex is ignored when followed by another prefix.  */
11215       if (rex)
11216         {
11217           rex_used = rex;
11218           return 1;
11219         }
11220       if (*codep != FWAIT_OPCODE)
11221         all_prefixes[i++] = *codep;
11222       rex = newrex;
11223       codep++;
11224       length++;
11225     }
11226   return 0;
11227 }
11228
11229 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11230    prefix byte.  */
11231
11232 static const char *
11233 prefix_name (int pref, int sizeflag)
11234 {
11235   static const char *rexes [16] =
11236     {
11237       "rex",            /* 0x40 */
11238       "rex.B",          /* 0x41 */
11239       "rex.X",          /* 0x42 */
11240       "rex.XB",         /* 0x43 */
11241       "rex.R",          /* 0x44 */
11242       "rex.RB",         /* 0x45 */
11243       "rex.RX",         /* 0x46 */
11244       "rex.RXB",        /* 0x47 */
11245       "rex.W",          /* 0x48 */
11246       "rex.WB",         /* 0x49 */
11247       "rex.WX",         /* 0x4a */
11248       "rex.WXB",        /* 0x4b */
11249       "rex.WR",         /* 0x4c */
11250       "rex.WRB",        /* 0x4d */
11251       "rex.WRX",        /* 0x4e */
11252       "rex.WRXB",       /* 0x4f */
11253     };
11254
11255   switch (pref)
11256     {
11257     /* REX prefixes family.  */
11258     case 0x40:
11259     case 0x41:
11260     case 0x42:
11261     case 0x43:
11262     case 0x44:
11263     case 0x45:
11264     case 0x46:
11265     case 0x47:
11266     case 0x48:
11267     case 0x49:
11268     case 0x4a:
11269     case 0x4b:
11270     case 0x4c:
11271     case 0x4d:
11272     case 0x4e:
11273     case 0x4f:
11274       return rexes [pref - 0x40];
11275     case 0xf3:
11276       return "repz";
11277     case 0xf2:
11278       return "repnz";
11279     case 0xf0:
11280       return "lock";
11281     case 0x2e:
11282       return "cs";
11283     case 0x36:
11284       return "ss";
11285     case 0x3e:
11286       return "ds";
11287     case 0x26:
11288       return "es";
11289     case 0x64:
11290       return "fs";
11291     case 0x65:
11292       return "gs";
11293     case 0x66:
11294       return (sizeflag & DFLAG) ? "data16" : "data32";
11295     case 0x67:
11296       if (address_mode == mode_64bit)
11297         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11298       else
11299         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11300     case FWAIT_OPCODE:
11301       return "fwait";
11302     case REP_PREFIX:
11303       return "rep";
11304     case XACQUIRE_PREFIX:
11305       return "xacquire";
11306     case XRELEASE_PREFIX:
11307       return "xrelease";
11308     case BND_PREFIX:
11309       return "bnd";
11310     case NOTRACK_PREFIX:
11311       return "notrack";
11312     default:
11313       return NULL;
11314     }
11315 }
11316
11317 static char op_out[MAX_OPERANDS][100];
11318 static int op_ad, op_index[MAX_OPERANDS];
11319 static int two_source_ops;
11320 static bfd_vma op_address[MAX_OPERANDS];
11321 static bfd_vma op_riprel[MAX_OPERANDS];
11322 static bfd_vma start_pc;
11323
11324 /*
11325  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11326  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11327  *   section of the "Virtual 8086 Mode" chapter.)
11328  * 'pc' should be the address of this instruction, it will
11329  *   be used to print the target address if this is a relative jump or call
11330  * The function returns the length of this instruction in bytes.
11331  */
11332
11333 static char intel_syntax;
11334 static char intel_mnemonic = !SYSV386_COMPAT;
11335 static char open_char;
11336 static char close_char;
11337 static char separator_char;
11338 static char scale_char;
11339
11340 enum x86_64_isa
11341 {
11342   amd64 = 1,
11343   intel64
11344 };
11345
11346 static enum x86_64_isa isa64;
11347
11348 /* Here for backwards compatibility.  When gdb stops using
11349    print_insn_i386_att and print_insn_i386_intel these functions can
11350    disappear, and print_insn_i386 be merged into print_insn.  */
11351 int
11352 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11353 {
11354   intel_syntax = 0;
11355
11356   return print_insn (pc, info);
11357 }
11358
11359 int
11360 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11361 {
11362   intel_syntax = 1;
11363
11364   return print_insn (pc, info);
11365 }
11366
11367 int
11368 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11369 {
11370   intel_syntax = -1;
11371
11372   return print_insn (pc, info);
11373 }
11374
11375 void
11376 print_i386_disassembler_options (FILE *stream)
11377 {
11378   fprintf (stream, _("\n\
11379 The following i386/x86-64 specific disassembler options are supported for use\n\
11380 with the -M switch (multiple options should be separated by commas):\n"));
11381
11382   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11383   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11384   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11385   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11386   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11387   fprintf (stream, _("  att-mnemonic\n"
11388                      "              Display instruction in AT&T mnemonic\n"));
11389   fprintf (stream, _("  intel-mnemonic\n"
11390                      "              Display instruction in Intel mnemonic\n"));
11391   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11392   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11393   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11394   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11395   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11396   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11397   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11398   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11399 }
11400
11401 /* Bad opcode.  */
11402 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11403
11404 /* Get a pointer to struct dis386 with a valid name.  */
11405
11406 static const struct dis386 *
11407 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11408 {
11409   int vindex, vex_table_index;
11410
11411   if (dp->name != NULL)
11412     return dp;
11413
11414   switch (dp->op[0].bytemode)
11415     {
11416     case USE_REG_TABLE:
11417       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11418       break;
11419
11420     case USE_MOD_TABLE:
11421       vindex = modrm.mod == 0x3 ? 1 : 0;
11422       dp = &mod_table[dp->op[1].bytemode][vindex];
11423       break;
11424
11425     case USE_RM_TABLE:
11426       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11427       break;
11428
11429     case USE_PREFIX_TABLE:
11430       if (need_vex)
11431         {
11432           /* The prefix in VEX is implicit.  */
11433           switch (vex.prefix)
11434             {
11435             case 0:
11436               vindex = 0;
11437               break;
11438             case REPE_PREFIX_OPCODE:
11439               vindex = 1;
11440               break;
11441             case DATA_PREFIX_OPCODE:
11442               vindex = 2;
11443               break;
11444             case REPNE_PREFIX_OPCODE:
11445               vindex = 3;
11446               break;
11447             default:
11448               abort ();
11449               break;
11450             }
11451         }
11452       else
11453         {
11454           int last_prefix = -1;
11455           int prefix = 0;
11456           vindex = 0;
11457           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11458              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11459              last one wins.  */
11460           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11461             {
11462               if (last_repz_prefix > last_repnz_prefix)
11463                 {
11464                   vindex = 1;
11465                   prefix = PREFIX_REPZ;
11466                   last_prefix = last_repz_prefix;
11467                 }
11468               else
11469                 {
11470                   vindex = 3;
11471                   prefix = PREFIX_REPNZ;
11472                   last_prefix = last_repnz_prefix;
11473                 }
11474
11475               /* Check if prefix should be ignored.  */
11476               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11477                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11478                    & prefix) != 0)
11479                 vindex = 0;
11480             }
11481
11482           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11483             {
11484               vindex = 2;
11485               prefix = PREFIX_DATA;
11486               last_prefix = last_data_prefix;
11487             }
11488
11489           if (vindex != 0)
11490             {
11491               used_prefixes |= prefix;
11492               all_prefixes[last_prefix] = 0;
11493             }
11494         }
11495       dp = &prefix_table[dp->op[1].bytemode][vindex];
11496       break;
11497
11498     case USE_X86_64_TABLE:
11499       vindex = address_mode == mode_64bit ? 1 : 0;
11500       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11501       break;
11502
11503     case USE_3BYTE_TABLE:
11504       FETCH_DATA (info, codep + 2);
11505       vindex = *codep++;
11506       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11507       end_codep = codep;
11508       modrm.mod = (*codep >> 6) & 3;
11509       modrm.reg = (*codep >> 3) & 7;
11510       modrm.rm = *codep & 7;
11511       break;
11512
11513     case USE_VEX_LEN_TABLE:
11514       if (!need_vex)
11515         abort ();
11516
11517       switch (vex.length)
11518         {
11519         case 128:
11520           vindex = 0;
11521           break;
11522         case 256:
11523           vindex = 1;
11524           break;
11525         default:
11526           abort ();
11527           break;
11528         }
11529
11530       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11531       break;
11532
11533     case USE_EVEX_LEN_TABLE:
11534       if (!vex.evex)
11535         abort ();
11536
11537       switch (vex.length)
11538         {
11539         case 128:
11540           vindex = 0;
11541           break;
11542         case 256:
11543           vindex = 1;
11544           break;
11545         case 512:
11546           vindex = 2;
11547           break;
11548         default:
11549           abort ();
11550           break;
11551         }
11552
11553       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11554       break;
11555
11556     case USE_XOP_8F_TABLE:
11557       FETCH_DATA (info, codep + 3);
11558       /* All bits in the REX prefix are ignored.  */
11559       rex_ignored = rex;
11560       rex = ~(*codep >> 5) & 0x7;
11561
11562       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11563       switch ((*codep & 0x1f))
11564         {
11565         default:
11566           dp = &bad_opcode;
11567           return dp;
11568         case 0x8:
11569           vex_table_index = XOP_08;
11570           break;
11571         case 0x9:
11572           vex_table_index = XOP_09;
11573           break;
11574         case 0xa:
11575           vex_table_index = XOP_0A;
11576           break;
11577         }
11578       codep++;
11579       vex.w = *codep & 0x80;
11580       if (vex.w && address_mode == mode_64bit)
11581         rex |= REX_W;
11582
11583       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11584       if (address_mode != mode_64bit)
11585         {
11586           /* In 16/32-bit mode REX_B is silently ignored.  */
11587           rex &= ~REX_B;
11588         }
11589
11590       vex.length = (*codep & 0x4) ? 256 : 128;
11591       switch ((*codep & 0x3))
11592         {
11593         case 0:
11594           break;
11595         case 1:
11596           vex.prefix = DATA_PREFIX_OPCODE;
11597           break;
11598         case 2:
11599           vex.prefix = REPE_PREFIX_OPCODE;
11600           break;
11601         case 3:
11602           vex.prefix = REPNE_PREFIX_OPCODE;
11603           break;
11604         }
11605       need_vex = 1;
11606       need_vex_reg = 1;
11607       codep++;
11608       vindex = *codep++;
11609       dp = &xop_table[vex_table_index][vindex];
11610
11611       end_codep = codep;
11612       FETCH_DATA (info, codep + 1);
11613       modrm.mod = (*codep >> 6) & 3;
11614       modrm.reg = (*codep >> 3) & 7;
11615       modrm.rm = *codep & 7;
11616       break;
11617
11618     case USE_VEX_C4_TABLE:
11619       /* VEX prefix.  */
11620       FETCH_DATA (info, codep + 3);
11621       /* All bits in the REX prefix are ignored.  */
11622       rex_ignored = rex;
11623       rex = ~(*codep >> 5) & 0x7;
11624       switch ((*codep & 0x1f))
11625         {
11626         default:
11627           dp = &bad_opcode;
11628           return dp;
11629         case 0x1:
11630           vex_table_index = VEX_0F;
11631           break;
11632         case 0x2:
11633           vex_table_index = VEX_0F38;
11634           break;
11635         case 0x3:
11636           vex_table_index = VEX_0F3A;
11637           break;
11638         }
11639       codep++;
11640       vex.w = *codep & 0x80;
11641       if (address_mode == mode_64bit)
11642         {
11643           if (vex.w)
11644             rex |= REX_W;
11645         }
11646       else
11647         {
11648           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11649              is ignored, other REX bits are 0 and the highest bit in
11650              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11651           rex = 0;
11652         }
11653       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11654       vex.length = (*codep & 0x4) ? 256 : 128;
11655       switch ((*codep & 0x3))
11656         {
11657         case 0:
11658           break;
11659         case 1:
11660           vex.prefix = DATA_PREFIX_OPCODE;
11661           break;
11662         case 2:
11663           vex.prefix = REPE_PREFIX_OPCODE;
11664           break;
11665         case 3:
11666           vex.prefix = REPNE_PREFIX_OPCODE;
11667           break;
11668         }
11669       need_vex = 1;
11670       need_vex_reg = 1;
11671       codep++;
11672       vindex = *codep++;
11673       dp = &vex_table[vex_table_index][vindex];
11674       end_codep = codep;
11675       /* There is no MODRM byte for VEX0F 77.  */
11676       if (vex_table_index != VEX_0F || vindex != 0x77)
11677         {
11678           FETCH_DATA (info, codep + 1);
11679           modrm.mod = (*codep >> 6) & 3;
11680           modrm.reg = (*codep >> 3) & 7;
11681           modrm.rm = *codep & 7;
11682         }
11683       break;
11684
11685     case USE_VEX_C5_TABLE:
11686       /* VEX prefix.  */
11687       FETCH_DATA (info, codep + 2);
11688       /* All bits in the REX prefix are ignored.  */
11689       rex_ignored = rex;
11690       rex = (*codep & 0x80) ? 0 : REX_R;
11691
11692       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11693          VEX.vvvv is 1.  */
11694       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11695       vex.length = (*codep & 0x4) ? 256 : 128;
11696       switch ((*codep & 0x3))
11697         {
11698         case 0:
11699           break;
11700         case 1:
11701           vex.prefix = DATA_PREFIX_OPCODE;
11702           break;
11703         case 2:
11704           vex.prefix = REPE_PREFIX_OPCODE;
11705           break;
11706         case 3:
11707           vex.prefix = REPNE_PREFIX_OPCODE;
11708           break;
11709         }
11710       need_vex = 1;
11711       need_vex_reg = 1;
11712       codep++;
11713       vindex = *codep++;
11714       dp = &vex_table[dp->op[1].bytemode][vindex];
11715       end_codep = codep;
11716       /* There is no MODRM byte for VEX 77.  */
11717       if (vindex != 0x77)
11718         {
11719           FETCH_DATA (info, codep + 1);
11720           modrm.mod = (*codep >> 6) & 3;
11721           modrm.reg = (*codep >> 3) & 7;
11722           modrm.rm = *codep & 7;
11723         }
11724       break;
11725
11726     case USE_VEX_W_TABLE:
11727       if (!need_vex)
11728         abort ();
11729
11730       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11731       break;
11732
11733     case USE_EVEX_TABLE:
11734       two_source_ops = 0;
11735       /* EVEX prefix.  */
11736       vex.evex = 1;
11737       FETCH_DATA (info, codep + 4);
11738       /* All bits in the REX prefix are ignored.  */
11739       rex_ignored = rex;
11740       /* The first byte after 0x62.  */
11741       rex = ~(*codep >> 5) & 0x7;
11742       vex.r = *codep & 0x10;
11743       switch ((*codep & 0xf))
11744         {
11745         default:
11746           return &bad_opcode;
11747         case 0x1:
11748           vex_table_index = EVEX_0F;
11749           break;
11750         case 0x2:
11751           vex_table_index = EVEX_0F38;
11752           break;
11753         case 0x3:
11754           vex_table_index = EVEX_0F3A;
11755           break;
11756         }
11757
11758       /* The second byte after 0x62.  */
11759       codep++;
11760       vex.w = *codep & 0x80;
11761       if (vex.w && address_mode == mode_64bit)
11762         rex |= REX_W;
11763
11764       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11765
11766       /* The U bit.  */
11767       if (!(*codep & 0x4))
11768         return &bad_opcode;
11769
11770       switch ((*codep & 0x3))
11771         {
11772         case 0:
11773           break;
11774         case 1:
11775           vex.prefix = DATA_PREFIX_OPCODE;
11776           break;
11777         case 2:
11778           vex.prefix = REPE_PREFIX_OPCODE;
11779           break;
11780         case 3:
11781           vex.prefix = REPNE_PREFIX_OPCODE;
11782           break;
11783         }
11784
11785       /* The third byte after 0x62.  */
11786       codep++;
11787
11788       /* Remember the static rounding bits.  */
11789       vex.ll = (*codep >> 5) & 3;
11790       vex.b = (*codep & 0x10) != 0;
11791
11792       vex.v = *codep & 0x8;
11793       vex.mask_register_specifier = *codep & 0x7;
11794       vex.zeroing = *codep & 0x80;
11795
11796       if (address_mode != mode_64bit)
11797         {
11798           /* In 16/32-bit mode silently ignore following bits.  */
11799           rex &= ~REX_B;
11800           vex.r = 1;
11801           vex.v = 1;
11802         }
11803
11804       need_vex = 1;
11805       need_vex_reg = 1;
11806       codep++;
11807       vindex = *codep++;
11808       dp = &evex_table[vex_table_index][vindex];
11809       end_codep = codep;
11810       FETCH_DATA (info, codep + 1);
11811       modrm.mod = (*codep >> 6) & 3;
11812       modrm.reg = (*codep >> 3) & 7;
11813       modrm.rm = *codep & 7;
11814
11815       /* Set vector length.  */
11816       if (modrm.mod == 3 && vex.b)
11817         vex.length = 512;
11818       else
11819         {
11820           switch (vex.ll)
11821             {
11822             case 0x0:
11823               vex.length = 128;
11824               break;
11825             case 0x1:
11826               vex.length = 256;
11827               break;
11828             case 0x2:
11829               vex.length = 512;
11830               break;
11831             default:
11832               return &bad_opcode;
11833             }
11834         }
11835       break;
11836
11837     case 0:
11838       dp = &bad_opcode;
11839       break;
11840
11841     default:
11842       abort ();
11843     }
11844
11845   if (dp->name != NULL)
11846     return dp;
11847   else
11848     return get_valid_dis386 (dp, info);
11849 }
11850
11851 static void
11852 get_sib (disassemble_info *info, int sizeflag)
11853 {
11854   /* If modrm.mod == 3, operand must be register.  */
11855   if (need_modrm
11856       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11857       && modrm.mod != 3
11858       && modrm.rm == 4)
11859     {
11860       FETCH_DATA (info, codep + 2);
11861       sib.index = (codep [1] >> 3) & 7;
11862       sib.scale = (codep [1] >> 6) & 3;
11863       sib.base = codep [1] & 7;
11864     }
11865 }
11866
11867 static int
11868 print_insn (bfd_vma pc, disassemble_info *info)
11869 {
11870   const struct dis386 *dp;
11871   int i;
11872   char *op_txt[MAX_OPERANDS];
11873   int needcomma;
11874   int sizeflag, orig_sizeflag;
11875   const char *p;
11876   struct dis_private priv;
11877   int prefix_length;
11878
11879   priv.orig_sizeflag = AFLAG | DFLAG;
11880   if ((info->mach & bfd_mach_i386_i386) != 0)
11881     address_mode = mode_32bit;
11882   else if (info->mach == bfd_mach_i386_i8086)
11883     {
11884       address_mode = mode_16bit;
11885       priv.orig_sizeflag = 0;
11886     }
11887   else
11888     address_mode = mode_64bit;
11889
11890   if (intel_syntax == (char) -1)
11891     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11892
11893   for (p = info->disassembler_options; p != NULL; )
11894     {
11895       if (CONST_STRNEQ (p, "amd64"))
11896         isa64 = amd64;
11897       else if (CONST_STRNEQ (p, "intel64"))
11898         isa64 = intel64;
11899       else if (CONST_STRNEQ (p, "x86-64"))
11900         {
11901           address_mode = mode_64bit;
11902           priv.orig_sizeflag = AFLAG | DFLAG;
11903         }
11904       else if (CONST_STRNEQ (p, "i386"))
11905         {
11906           address_mode = mode_32bit;
11907           priv.orig_sizeflag = AFLAG | DFLAG;
11908         }
11909       else if (CONST_STRNEQ (p, "i8086"))
11910         {
11911           address_mode = mode_16bit;
11912           priv.orig_sizeflag = 0;
11913         }
11914       else if (CONST_STRNEQ (p, "intel"))
11915         {
11916           intel_syntax = 1;
11917           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11918             intel_mnemonic = 1;
11919         }
11920       else if (CONST_STRNEQ (p, "att"))
11921         {
11922           intel_syntax = 0;
11923           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11924             intel_mnemonic = 0;
11925         }
11926       else if (CONST_STRNEQ (p, "addr"))
11927         {
11928           if (address_mode == mode_64bit)
11929             {
11930               if (p[4] == '3' && p[5] == '2')
11931                 priv.orig_sizeflag &= ~AFLAG;
11932               else if (p[4] == '6' && p[5] == '4')
11933                 priv.orig_sizeflag |= AFLAG;
11934             }
11935           else
11936             {
11937               if (p[4] == '1' && p[5] == '6')
11938                 priv.orig_sizeflag &= ~AFLAG;
11939               else if (p[4] == '3' && p[5] == '2')
11940                 priv.orig_sizeflag |= AFLAG;
11941             }
11942         }
11943       else if (CONST_STRNEQ (p, "data"))
11944         {
11945           if (p[4] == '1' && p[5] == '6')
11946             priv.orig_sizeflag &= ~DFLAG;
11947           else if (p[4] == '3' && p[5] == '2')
11948             priv.orig_sizeflag |= DFLAG;
11949         }
11950       else if (CONST_STRNEQ (p, "suffix"))
11951         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11952
11953       p = strchr (p, ',');
11954       if (p != NULL)
11955         p++;
11956     }
11957
11958   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11959     {
11960       (*info->fprintf_func) (info->stream,
11961                              _("64-bit address is disabled"));
11962       return -1;
11963     }
11964
11965   if (intel_syntax)
11966     {
11967       names64 = intel_names64;
11968       names32 = intel_names32;
11969       names16 = intel_names16;
11970       names8 = intel_names8;
11971       names8rex = intel_names8rex;
11972       names_seg = intel_names_seg;
11973       names_mm = intel_names_mm;
11974       names_bnd = intel_names_bnd;
11975       names_xmm = intel_names_xmm;
11976       names_ymm = intel_names_ymm;
11977       names_zmm = intel_names_zmm;
11978       index64 = intel_index64;
11979       index32 = intel_index32;
11980       names_mask = intel_names_mask;
11981       index16 = intel_index16;
11982       open_char = '[';
11983       close_char = ']';
11984       separator_char = '+';
11985       scale_char = '*';
11986     }
11987   else
11988     {
11989       names64 = att_names64;
11990       names32 = att_names32;
11991       names16 = att_names16;
11992       names8 = att_names8;
11993       names8rex = att_names8rex;
11994       names_seg = att_names_seg;
11995       names_mm = att_names_mm;
11996       names_bnd = att_names_bnd;
11997       names_xmm = att_names_xmm;
11998       names_ymm = att_names_ymm;
11999       names_zmm = att_names_zmm;
12000       index64 = att_index64;
12001       index32 = att_index32;
12002       names_mask = att_names_mask;
12003       index16 = att_index16;
12004       open_char = '(';
12005       close_char =  ')';
12006       separator_char = ',';
12007       scale_char = ',';
12008     }
12009
12010   /* The output looks better if we put 7 bytes on a line, since that
12011      puts most long word instructions on a single line.  Use 8 bytes
12012      for Intel L1OM.  */
12013   if ((info->mach & bfd_mach_l1om) != 0)
12014     info->bytes_per_line = 8;
12015   else
12016     info->bytes_per_line = 7;
12017
12018   info->private_data = &priv;
12019   priv.max_fetched = priv.the_buffer;
12020   priv.insn_start = pc;
12021
12022   obuf[0] = 0;
12023   for (i = 0; i < MAX_OPERANDS; ++i)
12024     {
12025       op_out[i][0] = 0;
12026       op_index[i] = -1;
12027     }
12028
12029   the_info = info;
12030   start_pc = pc;
12031   start_codep = priv.the_buffer;
12032   codep = priv.the_buffer;
12033
12034   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12035     {
12036       const char *name;
12037
12038       /* Getting here means we tried for data but didn't get it.  That
12039          means we have an incomplete instruction of some sort.  Just
12040          print the first byte as a prefix or a .byte pseudo-op.  */
12041       if (codep > priv.the_buffer)
12042         {
12043           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12044           if (name != NULL)
12045             (*info->fprintf_func) (info->stream, "%s", name);
12046           else
12047             {
12048               /* Just print the first byte as a .byte instruction.  */
12049               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12050                                      (unsigned int) priv.the_buffer[0]);
12051             }
12052
12053           return 1;
12054         }
12055
12056       return -1;
12057     }
12058
12059   obufp = obuf;
12060   sizeflag = priv.orig_sizeflag;
12061
12062   if (!ckprefix () || rex_used)
12063     {
12064       /* Too many prefixes or unused REX prefixes.  */
12065       for (i = 0;
12066            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12067            i++)
12068         (*info->fprintf_func) (info->stream, "%s%s",
12069                                i == 0 ? "" : " ",
12070                                prefix_name (all_prefixes[i], sizeflag));
12071       return i;
12072     }
12073
12074   insn_codep = codep;
12075
12076   FETCH_DATA (info, codep + 1);
12077   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12078
12079   if (((prefixes & PREFIX_FWAIT)
12080        && ((*codep < 0xd8) || (*codep > 0xdf))))
12081     {
12082       /* Handle prefixes before fwait.  */
12083       for (i = 0; i < fwait_prefix && all_prefixes[i];
12084            i++)
12085         (*info->fprintf_func) (info->stream, "%s ",
12086                                prefix_name (all_prefixes[i], sizeflag));
12087       (*info->fprintf_func) (info->stream, "fwait");
12088       return i + 1;
12089     }
12090
12091   if (*codep == 0x0f)
12092     {
12093       unsigned char threebyte;
12094
12095       codep++;
12096       FETCH_DATA (info, codep + 1);
12097       threebyte = *codep;
12098       dp = &dis386_twobyte[threebyte];
12099       need_modrm = twobyte_has_modrm[*codep];
12100       codep++;
12101     }
12102   else
12103     {
12104       dp = &dis386[*codep];
12105       need_modrm = onebyte_has_modrm[*codep];
12106       codep++;
12107     }
12108
12109   /* Save sizeflag for printing the extra prefixes later before updating
12110      it for mnemonic and operand processing.  The prefix names depend
12111      only on the address mode.  */
12112   orig_sizeflag = sizeflag;
12113   if (prefixes & PREFIX_ADDR)
12114     sizeflag ^= AFLAG;
12115   if ((prefixes & PREFIX_DATA))
12116     sizeflag ^= DFLAG;
12117
12118   end_codep = codep;
12119   if (need_modrm)
12120     {
12121       FETCH_DATA (info, codep + 1);
12122       modrm.mod = (*codep >> 6) & 3;
12123       modrm.reg = (*codep >> 3) & 7;
12124       modrm.rm = *codep & 7;
12125     }
12126
12127   need_vex = 0;
12128   need_vex_reg = 0;
12129   vex_w_done = 0;
12130   memset (&vex, 0, sizeof (vex));
12131
12132   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12133     {
12134       get_sib (info, sizeflag);
12135       dofloat (sizeflag);
12136     }
12137   else
12138     {
12139       dp = get_valid_dis386 (dp, info);
12140       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12141         {
12142           get_sib (info, sizeflag);
12143           for (i = 0; i < MAX_OPERANDS; ++i)
12144             {
12145               obufp = op_out[i];
12146               op_ad = MAX_OPERANDS - 1 - i;
12147               if (dp->op[i].rtn)
12148                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12149               /* For EVEX instruction after the last operand masking
12150                  should be printed.  */
12151               if (i == 0 && vex.evex)
12152                 {
12153                   /* Don't print {%k0}.  */
12154                   if (vex.mask_register_specifier)
12155                     {
12156                       oappend ("{");
12157                       oappend (names_mask[vex.mask_register_specifier]);
12158                       oappend ("}");
12159                     }
12160                   if (vex.zeroing)
12161                     oappend ("{z}");
12162                 }
12163             }
12164         }
12165     }
12166
12167   /* Clear instruction information.  */
12168   if (the_info)
12169     {
12170       the_info->insn_info_valid = 0;
12171       the_info->branch_delay_insns = 0;
12172       the_info->data_size = 0;
12173       the_info->insn_type = dis_noninsn;
12174       the_info->target = 0;
12175       the_info->target2 = 0;
12176     }
12177
12178   /* Reset jump operation indicator.  */
12179   op_is_jump = FALSE;
12180
12181   {
12182     int jump_detection = 0;
12183
12184     /* Extract flags.  */
12185     for (i = 0; i < MAX_OPERANDS; ++i)
12186       {
12187         if ((dp->op[i].rtn == OP_J)
12188             || (dp->op[i].rtn == OP_indirE))
12189           jump_detection |= 1;
12190         else if ((dp->op[i].rtn == BND_Fixup)
12191                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12192           jump_detection |= 2;
12193         else if ((dp->op[i].bytemode == cond_jump_mode)
12194                  || (dp->op[i].bytemode == loop_jcxz_mode))
12195           jump_detection |= 4;
12196       }
12197
12198     /* Determine if this is a jump or branch.  */
12199     if ((jump_detection & 0x3) == 0x3)
12200       {
12201         op_is_jump = TRUE;
12202         if (jump_detection & 0x4)
12203           the_info->insn_type = dis_condbranch;
12204         else
12205           the_info->insn_type =
12206             (dp->name && !strncmp(dp->name, "call", 4))
12207             ? dis_jsr : dis_branch;
12208       }
12209   }
12210
12211   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12212      are all 0s in inverted form.  */
12213   if (need_vex && vex.register_specifier != 0)
12214     {
12215       (*info->fprintf_func) (info->stream, "(bad)");
12216       return end_codep - priv.the_buffer;
12217     }
12218
12219   /* Check if the REX prefix is used.  */
12220   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12221     all_prefixes[last_rex_prefix] = 0;
12222
12223   /* Check if the SEG prefix is used.  */
12224   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12225                    | PREFIX_FS | PREFIX_GS)) != 0
12226       && (used_prefixes & active_seg_prefix) != 0)
12227     all_prefixes[last_seg_prefix] = 0;
12228
12229   /* Check if the ADDR prefix is used.  */
12230   if ((prefixes & PREFIX_ADDR) != 0
12231       && (used_prefixes & PREFIX_ADDR) != 0)
12232     all_prefixes[last_addr_prefix] = 0;
12233
12234   /* Check if the DATA prefix is used.  */
12235   if ((prefixes & PREFIX_DATA) != 0
12236       && (used_prefixes & PREFIX_DATA) != 0)
12237     all_prefixes[last_data_prefix] = 0;
12238
12239   /* Print the extra prefixes.  */
12240   prefix_length = 0;
12241   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12242     if (all_prefixes[i])
12243       {
12244         const char *name;
12245         name = prefix_name (all_prefixes[i], orig_sizeflag);
12246         if (name == NULL)
12247           abort ();
12248         prefix_length += strlen (name) + 1;
12249         (*info->fprintf_func) (info->stream, "%s ", name);
12250       }
12251
12252   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12253      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12254      used by putop and MMX/SSE operand and may be overriden by the
12255      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12256      separately.  */
12257   if (dp->prefix_requirement == PREFIX_OPCODE
12258       && dp != &bad_opcode
12259       && (((prefixes
12260             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12261            && (used_prefixes
12262                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12263           || ((((prefixes
12264                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12265                 == PREFIX_DATA)
12266                && (used_prefixes & PREFIX_DATA) == 0))))
12267     {
12268       (*info->fprintf_func) (info->stream, "(bad)");
12269       return end_codep - priv.the_buffer;
12270     }
12271
12272   /* Check maximum code length.  */
12273   if ((codep - start_codep) > MAX_CODE_LENGTH)
12274     {
12275       (*info->fprintf_func) (info->stream, "(bad)");
12276       return MAX_CODE_LENGTH;
12277     }
12278
12279   obufp = mnemonicendp;
12280   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12281     oappend (" ");
12282   oappend (" ");
12283   (*info->fprintf_func) (info->stream, "%s", obuf);
12284
12285   /* The enter and bound instructions are printed with operands in the same
12286      order as the intel book; everything else is printed in reverse order.  */
12287   if (intel_syntax || two_source_ops)
12288     {
12289       bfd_vma riprel;
12290
12291       for (i = 0; i < MAX_OPERANDS; ++i)
12292         op_txt[i] = op_out[i];
12293
12294       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12295           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12296         {
12297           op_txt[2] = op_out[3];
12298           op_txt[3] = op_out[2];
12299         }
12300
12301       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12302         {
12303           op_ad = op_index[i];
12304           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12305           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12306           riprel = op_riprel[i];
12307           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12308           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12309         }
12310     }
12311   else
12312     {
12313       for (i = 0; i < MAX_OPERANDS; ++i)
12314         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12315     }
12316
12317   needcomma = 0;
12318   for (i = 0; i < MAX_OPERANDS; ++i)
12319     if (*op_txt[i])
12320       {
12321         if (needcomma)
12322           (*info->fprintf_func) (info->stream, ",");
12323         if (op_index[i] != -1 && !op_riprel[i])
12324           {
12325             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12326
12327             if (the_info && op_is_jump)
12328               {
12329                 the_info->insn_info_valid = 1;
12330                 the_info->branch_delay_insns = 0;
12331                 the_info->data_size = 0;
12332                 the_info->target = target;
12333                 the_info->target2 = 0;
12334               }
12335             (*info->print_address_func) (target, info);
12336           }
12337         else
12338           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12339         needcomma = 1;
12340       }
12341
12342   for (i = 0; i < MAX_OPERANDS; i++)
12343     if (op_index[i] != -1 && op_riprel[i])
12344       {
12345         (*info->fprintf_func) (info->stream, "        # ");
12346         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12347                                                 + op_address[op_index[i]]), info);
12348         break;
12349       }
12350   return codep - priv.the_buffer;
12351 }
12352
12353 static const char *float_mem[] = {
12354   /* d8 */
12355   "fadd{s|}",
12356   "fmul{s|}",
12357   "fcom{s|}",
12358   "fcomp{s|}",
12359   "fsub{s|}",
12360   "fsubr{s|}",
12361   "fdiv{s|}",
12362   "fdivr{s|}",
12363   /* d9 */
12364   "fld{s|}",
12365   "(bad)",
12366   "fst{s|}",
12367   "fstp{s|}",
12368   "fldenvIC",
12369   "fldcw",
12370   "fNstenvIC",
12371   "fNstcw",
12372   /* da */
12373   "fiadd{l|}",
12374   "fimul{l|}",
12375   "ficom{l|}",
12376   "ficomp{l|}",
12377   "fisub{l|}",
12378   "fisubr{l|}",
12379   "fidiv{l|}",
12380   "fidivr{l|}",
12381   /* db */
12382   "fild{l|}",
12383   "fisttp{l|}",
12384   "fist{l|}",
12385   "fistp{l|}",
12386   "(bad)",
12387   "fld{t||t|}",
12388   "(bad)",
12389   "fstp{t||t|}",
12390   /* dc */
12391   "fadd{l|}",
12392   "fmul{l|}",
12393   "fcom{l|}",
12394   "fcomp{l|}",
12395   "fsub{l|}",
12396   "fsubr{l|}",
12397   "fdiv{l|}",
12398   "fdivr{l|}",
12399   /* dd */
12400   "fld{l|}",
12401   "fisttp{ll|}",
12402   "fst{l||}",
12403   "fstp{l|}",
12404   "frstorIC",
12405   "(bad)",
12406   "fNsaveIC",
12407   "fNstsw",
12408   /* de */
12409   "fiadd{s|}",
12410   "fimul{s|}",
12411   "ficom{s|}",
12412   "ficomp{s|}",
12413   "fisub{s|}",
12414   "fisubr{s|}",
12415   "fidiv{s|}",
12416   "fidivr{s|}",
12417   /* df */
12418   "fild{s|}",
12419   "fisttp{s|}",
12420   "fist{s|}",
12421   "fistp{s|}",
12422   "fbld",
12423   "fild{ll|}",
12424   "fbstp",
12425   "fistp{ll|}",
12426 };
12427
12428 static const unsigned char float_mem_mode[] = {
12429   /* d8 */
12430   d_mode,
12431   d_mode,
12432   d_mode,
12433   d_mode,
12434   d_mode,
12435   d_mode,
12436   d_mode,
12437   d_mode,
12438   /* d9 */
12439   d_mode,
12440   0,
12441   d_mode,
12442   d_mode,
12443   0,
12444   w_mode,
12445   0,
12446   w_mode,
12447   /* da */
12448   d_mode,
12449   d_mode,
12450   d_mode,
12451   d_mode,
12452   d_mode,
12453   d_mode,
12454   d_mode,
12455   d_mode,
12456   /* db */
12457   d_mode,
12458   d_mode,
12459   d_mode,
12460   d_mode,
12461   0,
12462   t_mode,
12463   0,
12464   t_mode,
12465   /* dc */
12466   q_mode,
12467   q_mode,
12468   q_mode,
12469   q_mode,
12470   q_mode,
12471   q_mode,
12472   q_mode,
12473   q_mode,
12474   /* dd */
12475   q_mode,
12476   q_mode,
12477   q_mode,
12478   q_mode,
12479   0,
12480   0,
12481   0,
12482   w_mode,
12483   /* de */
12484   w_mode,
12485   w_mode,
12486   w_mode,
12487   w_mode,
12488   w_mode,
12489   w_mode,
12490   w_mode,
12491   w_mode,
12492   /* df */
12493   w_mode,
12494   w_mode,
12495   w_mode,
12496   w_mode,
12497   t_mode,
12498   q_mode,
12499   t_mode,
12500   q_mode
12501 };
12502
12503 #define ST { OP_ST, 0 }
12504 #define STi { OP_STi, 0 }
12505
12506 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12507 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12508 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12509 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12510 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12511 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12512 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12513 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12514 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12515
12516 static const struct dis386 float_reg[][8] = {
12517   /* d8 */
12518   {
12519     { "fadd",   { ST, STi }, 0 },
12520     { "fmul",   { ST, STi }, 0 },
12521     { "fcom",   { STi }, 0 },
12522     { "fcomp",  { STi }, 0 },
12523     { "fsub",   { ST, STi }, 0 },
12524     { "fsubr",  { ST, STi }, 0 },
12525     { "fdiv",   { ST, STi }, 0 },
12526     { "fdivr",  { ST, STi }, 0 },
12527   },
12528   /* d9 */
12529   {
12530     { "fld",    { STi }, 0 },
12531     { "fxch",   { STi }, 0 },
12532     { FGRPd9_2 },
12533     { Bad_Opcode },
12534     { FGRPd9_4 },
12535     { FGRPd9_5 },
12536     { FGRPd9_6 },
12537     { FGRPd9_7 },
12538   },
12539   /* da */
12540   {
12541     { "fcmovb", { ST, STi }, 0 },
12542     { "fcmove", { ST, STi }, 0 },
12543     { "fcmovbe",{ ST, STi }, 0 },
12544     { "fcmovu", { ST, STi }, 0 },
12545     { Bad_Opcode },
12546     { FGRPda_5 },
12547     { Bad_Opcode },
12548     { Bad_Opcode },
12549   },
12550   /* db */
12551   {
12552     { "fcmovnb",{ ST, STi }, 0 },
12553     { "fcmovne",{ ST, STi }, 0 },
12554     { "fcmovnbe",{ ST, STi }, 0 },
12555     { "fcmovnu",{ ST, STi }, 0 },
12556     { FGRPdb_4 },
12557     { "fucomi", { ST, STi }, 0 },
12558     { "fcomi",  { ST, STi }, 0 },
12559     { Bad_Opcode },
12560   },
12561   /* dc */
12562   {
12563     { "fadd",   { STi, ST }, 0 },
12564     { "fmul",   { STi, ST }, 0 },
12565     { Bad_Opcode },
12566     { Bad_Opcode },
12567     { "fsub{!M|r}",     { STi, ST }, 0 },
12568     { "fsub{M|}",       { STi, ST }, 0 },
12569     { "fdiv{!M|r}",     { STi, ST }, 0 },
12570     { "fdiv{M|}",       { STi, ST }, 0 },
12571   },
12572   /* dd */
12573   {
12574     { "ffree",  { STi }, 0 },
12575     { Bad_Opcode },
12576     { "fst",    { STi }, 0 },
12577     { "fstp",   { STi }, 0 },
12578     { "fucom",  { STi }, 0 },
12579     { "fucomp", { STi }, 0 },
12580     { Bad_Opcode },
12581     { Bad_Opcode },
12582   },
12583   /* de */
12584   {
12585     { "faddp",  { STi, ST }, 0 },
12586     { "fmulp",  { STi, ST }, 0 },
12587     { Bad_Opcode },
12588     { FGRPde_3 },
12589     { "fsub{!M|r}p",    { STi, ST }, 0 },
12590     { "fsub{M|}p",      { STi, ST }, 0 },
12591     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12592     { "fdiv{M|}p",      { STi, ST }, 0 },
12593   },
12594   /* df */
12595   {
12596     { "ffreep", { STi }, 0 },
12597     { Bad_Opcode },
12598     { Bad_Opcode },
12599     { Bad_Opcode },
12600     { FGRPdf_4 },
12601     { "fucomip", { ST, STi }, 0 },
12602     { "fcomip", { ST, STi }, 0 },
12603     { Bad_Opcode },
12604   },
12605 };
12606
12607 static char *fgrps[][8] = {
12608   /* Bad opcode 0 */
12609   {
12610     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12611   },
12612
12613   /* d9_2  1 */
12614   {
12615     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12616   },
12617
12618   /* d9_4  2 */
12619   {
12620     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12621   },
12622
12623   /* d9_5  3 */
12624   {
12625     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12626   },
12627
12628   /* d9_6  4 */
12629   {
12630     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12631   },
12632
12633   /* d9_7  5 */
12634   {
12635     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12636   },
12637
12638   /* da_5  6 */
12639   {
12640     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12641   },
12642
12643   /* db_4  7 */
12644   {
12645     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12646     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12647   },
12648
12649   /* de_3  8 */
12650   {
12651     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12652   },
12653
12654   /* df_4  9 */
12655   {
12656     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12657   },
12658 };
12659
12660 static void
12661 swap_operand (void)
12662 {
12663   mnemonicendp[0] = '.';
12664   mnemonicendp[1] = 's';
12665   mnemonicendp += 2;
12666 }
12667
12668 static void
12669 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12670                int sizeflag ATTRIBUTE_UNUSED)
12671 {
12672   /* Skip mod/rm byte.  */
12673   MODRM_CHECK;
12674   codep++;
12675 }
12676
12677 static void
12678 dofloat (int sizeflag)
12679 {
12680   const struct dis386 *dp;
12681   unsigned char floatop;
12682
12683   floatop = codep[-1];
12684
12685   if (modrm.mod != 3)
12686     {
12687       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12688
12689       putop (float_mem[fp_indx], sizeflag);
12690       obufp = op_out[0];
12691       op_ad = 2;
12692       OP_E (float_mem_mode[fp_indx], sizeflag);
12693       return;
12694     }
12695   /* Skip mod/rm byte.  */
12696   MODRM_CHECK;
12697   codep++;
12698
12699   dp = &float_reg[floatop - 0xd8][modrm.reg];
12700   if (dp->name == NULL)
12701     {
12702       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12703
12704       /* Instruction fnstsw is only one with strange arg.  */
12705       if (floatop == 0xdf && codep[-1] == 0xe0)
12706         strcpy (op_out[0], names16[0]);
12707     }
12708   else
12709     {
12710       putop (dp->name, sizeflag);
12711
12712       obufp = op_out[0];
12713       op_ad = 2;
12714       if (dp->op[0].rtn)
12715         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12716
12717       obufp = op_out[1];
12718       op_ad = 1;
12719       if (dp->op[1].rtn)
12720         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12721     }
12722 }
12723
12724 /* Like oappend (below), but S is a string starting with '%'.
12725    In Intel syntax, the '%' is elided.  */
12726 static void
12727 oappend_maybe_intel (const char *s)
12728 {
12729   oappend (s + intel_syntax);
12730 }
12731
12732 static void
12733 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12734 {
12735   oappend_maybe_intel ("%st");
12736 }
12737
12738 static void
12739 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12740 {
12741   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12742   oappend_maybe_intel (scratchbuf);
12743 }
12744
12745 /* Capital letters in template are macros.  */
12746 static int
12747 putop (const char *in_template, int sizeflag)
12748 {
12749   const char *p;
12750   int alt = 0;
12751   int cond = 1;
12752   unsigned int l = 0, len = 1;
12753   char last[4];
12754
12755 #define SAVE_LAST(c)                    \
12756   if (l < len && l < sizeof (last))     \
12757     last[l++] = c;                      \
12758   else                                  \
12759     abort ();
12760
12761   for (p = in_template; *p; p++)
12762     {
12763       switch (*p)
12764         {
12765         default:
12766           *obufp++ = *p;
12767           break;
12768         case '%':
12769           len++;
12770           break;
12771         case '!':
12772           cond = 0;
12773           break;
12774         case '{':
12775           if (intel_syntax)
12776             {
12777               while (*++p != '|')
12778                 if (*p == '}' || *p == '\0')
12779                   abort ();
12780             }
12781           /* Fall through.  */
12782         case 'I':
12783           alt = 1;
12784           continue;
12785         case '|':
12786           while (*++p != '}')
12787             {
12788               if (*p == '\0')
12789                 abort ();
12790             }
12791           break;
12792         case '}':
12793           break;
12794         case 'A':
12795           if (intel_syntax)
12796             break;
12797           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12798             *obufp++ = 'b';
12799           break;
12800         case 'B':
12801           if (l == 0 && len == 1)
12802             {
12803             case_B:
12804               if (intel_syntax)
12805                 break;
12806               if (sizeflag & SUFFIX_ALWAYS)
12807                 *obufp++ = 'b';
12808             }
12809           else
12810             {
12811               if (l != 1
12812                   || len != 2
12813                   || last[0] != 'L')
12814                 {
12815                   SAVE_LAST (*p);
12816                   break;
12817                 }
12818
12819               if (address_mode == mode_64bit
12820                   && !(prefixes & PREFIX_ADDR))
12821                 {
12822                   *obufp++ = 'a';
12823                   *obufp++ = 'b';
12824                   *obufp++ = 's';
12825                 }
12826
12827               goto case_B;
12828             }
12829           break;
12830         case 'C':
12831           if (intel_syntax && !alt)
12832             break;
12833           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12834             {
12835               if (sizeflag & DFLAG)
12836                 *obufp++ = intel_syntax ? 'd' : 'l';
12837               else
12838                 *obufp++ = intel_syntax ? 'w' : 's';
12839               used_prefixes |= (prefixes & PREFIX_DATA);
12840             }
12841           break;
12842         case 'D':
12843           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12844             break;
12845           USED_REX (REX_W);
12846           if (modrm.mod == 3)
12847             {
12848               if (rex & REX_W)
12849                 *obufp++ = 'q';
12850               else
12851                 {
12852                   if (sizeflag & DFLAG)
12853                     *obufp++ = intel_syntax ? 'd' : 'l';
12854                   else
12855                     *obufp++ = 'w';
12856                   used_prefixes |= (prefixes & PREFIX_DATA);
12857                 }
12858             }
12859           else
12860             *obufp++ = 'w';
12861           break;
12862         case 'E':               /* For jcxz/jecxz */
12863           if (address_mode == mode_64bit)
12864             {
12865               if (sizeflag & AFLAG)
12866                 *obufp++ = 'r';
12867               else
12868                 *obufp++ = 'e';
12869             }
12870           else
12871             if (sizeflag & AFLAG)
12872               *obufp++ = 'e';
12873           used_prefixes |= (prefixes & PREFIX_ADDR);
12874           break;
12875         case 'F':
12876           if (intel_syntax)
12877             break;
12878           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12879             {
12880               if (sizeflag & AFLAG)
12881                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12882               else
12883                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12884               used_prefixes |= (prefixes & PREFIX_ADDR);
12885             }
12886           break;
12887         case 'G':
12888           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12889             break;
12890           if ((rex & REX_W) || (sizeflag & DFLAG))
12891             *obufp++ = 'l';
12892           else
12893             *obufp++ = 'w';
12894           if (!(rex & REX_W))
12895             used_prefixes |= (prefixes & PREFIX_DATA);
12896           break;
12897         case 'H':
12898           if (intel_syntax)
12899             break;
12900           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12901               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12902             {
12903               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12904               *obufp++ = ',';
12905               *obufp++ = 'p';
12906               if (prefixes & PREFIX_DS)
12907                 *obufp++ = 't';
12908               else
12909                 *obufp++ = 'n';
12910             }
12911           break;
12912         case 'J':
12913           if (intel_syntax)
12914             break;
12915           *obufp++ = 'l';
12916           break;
12917         case 'K':
12918           USED_REX (REX_W);
12919           if (rex & REX_W)
12920             *obufp++ = 'q';
12921           else
12922             *obufp++ = 'd';
12923           break;
12924         case 'Z':
12925           if (l != 0 || len != 1)
12926             {
12927               if (l != 1 || len != 2 || last[0] != 'X')
12928                 {
12929                   SAVE_LAST (*p);
12930                   break;
12931                 }
12932               if (!need_vex || !vex.evex)
12933                 abort ();
12934               if (intel_syntax
12935                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12936                 break;
12937               switch (vex.length)
12938                 {
12939                 case 128:
12940                   *obufp++ = 'x';
12941                   break;
12942                 case 256:
12943                   *obufp++ = 'y';
12944                   break;
12945                 case 512:
12946                   *obufp++ = 'z';
12947                   break;
12948                 default:
12949                   abort ();
12950                 }
12951               break;
12952             }
12953           if (intel_syntax)
12954             break;
12955           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12956             {
12957               *obufp++ = 'q';
12958               break;
12959             }
12960           /* Fall through.  */
12961           goto case_L;
12962         case 'L':
12963           if (l != 0 || len != 1)
12964             {
12965               SAVE_LAST (*p);
12966               break;
12967             }
12968         case_L:
12969           if (intel_syntax)
12970             break;
12971           if (sizeflag & SUFFIX_ALWAYS)
12972             *obufp++ = 'l';
12973           break;
12974         case 'M':
12975           if (intel_mnemonic != cond)
12976             *obufp++ = 'r';
12977           break;
12978         case 'N':
12979           if ((prefixes & PREFIX_FWAIT) == 0)
12980             *obufp++ = 'n';
12981           else
12982             used_prefixes |= PREFIX_FWAIT;
12983           break;
12984         case 'O':
12985           USED_REX (REX_W);
12986           if (rex & REX_W)
12987             *obufp++ = 'o';
12988           else if (intel_syntax && (sizeflag & DFLAG))
12989             *obufp++ = 'q';
12990           else
12991             *obufp++ = 'd';
12992           if (!(rex & REX_W))
12993             used_prefixes |= (prefixes & PREFIX_DATA);
12994           break;
12995         case '&':
12996           if (!intel_syntax
12997               && address_mode == mode_64bit
12998               && isa64 == intel64)
12999             {
13000               *obufp++ = 'q';
13001               break;
13002             }
13003           /* Fall through.  */
13004         case 'T':
13005           if (!intel_syntax
13006               && address_mode == mode_64bit
13007               && ((sizeflag & DFLAG) || (rex & REX_W)))
13008             {
13009               *obufp++ = 'q';
13010               break;
13011             }
13012           /* Fall through.  */
13013           goto case_P;
13014         case 'P':
13015           if (l == 0 && len == 1)
13016             {
13017             case_P:
13018               if (intel_syntax)
13019                 {
13020                   if ((rex & REX_W) == 0
13021                       && (prefixes & PREFIX_DATA))
13022                     {
13023                       if ((sizeflag & DFLAG) == 0)
13024                         *obufp++ = 'w';
13025                       used_prefixes |= (prefixes & PREFIX_DATA);
13026                     }
13027                   break;
13028                 }
13029               if ((prefixes & PREFIX_DATA)
13030                   || (rex & REX_W)
13031                   || (sizeflag & SUFFIX_ALWAYS))
13032                 {
13033                   USED_REX (REX_W);
13034                   if (rex & REX_W)
13035                     *obufp++ = 'q';
13036                   else
13037                     {
13038                       if (sizeflag & DFLAG)
13039                         *obufp++ = 'l';
13040                       else
13041                         *obufp++ = 'w';
13042                       used_prefixes |= (prefixes & PREFIX_DATA);
13043                     }
13044                 }
13045             }
13046           else
13047             {
13048               if (l != 1 || len != 2 || last[0] != 'L')
13049                 {
13050                   SAVE_LAST (*p);
13051                   break;
13052                 }
13053
13054               if ((prefixes & PREFIX_DATA)
13055                   || (rex & REX_W)
13056                   || (sizeflag & SUFFIX_ALWAYS))
13057                 {
13058                   USED_REX (REX_W);
13059                   if (rex & REX_W)
13060                     *obufp++ = 'q';
13061                   else
13062                     {
13063                       if (sizeflag & DFLAG)
13064                         *obufp++ = intel_syntax ? 'd' : 'l';
13065                       else
13066                         *obufp++ = 'w';
13067                       used_prefixes |= (prefixes & PREFIX_DATA);
13068                     }
13069                 }
13070             }
13071           break;
13072         case 'U':
13073           if (intel_syntax)
13074             break;
13075           if (address_mode == mode_64bit
13076               && ((sizeflag & DFLAG) || (rex & REX_W)))
13077             {
13078               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13079                 *obufp++ = 'q';
13080               break;
13081             }
13082           /* Fall through.  */
13083           goto case_Q;
13084         case 'Q':
13085           if (l == 0 && len == 1)
13086             {
13087             case_Q:
13088               if (intel_syntax && !alt)
13089                 break;
13090               USED_REX (REX_W);
13091               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13092                 {
13093                   if (rex & REX_W)
13094                     *obufp++ = 'q';
13095                   else
13096                     {
13097                       if (sizeflag & DFLAG)
13098                         *obufp++ = intel_syntax ? 'd' : 'l';
13099                       else
13100                         *obufp++ = 'w';
13101                       used_prefixes |= (prefixes & PREFIX_DATA);
13102                     }
13103                 }
13104             }
13105           else
13106             {
13107               if (l != 1 || len != 2 || last[0] != 'L')
13108                 {
13109                   SAVE_LAST (*p);
13110                   break;
13111                 }
13112               if (intel_syntax
13113                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13114                 break;
13115               if ((rex & REX_W))
13116                 {
13117                   USED_REX (REX_W);
13118                   *obufp++ = 'q';
13119                 }
13120               else
13121                 *obufp++ = 'l';
13122             }
13123           break;
13124         case 'R':
13125           USED_REX (REX_W);
13126           if (rex & REX_W)
13127             *obufp++ = 'q';
13128           else if (sizeflag & DFLAG)
13129             {
13130               if (intel_syntax)
13131                   *obufp++ = 'd';
13132               else
13133                   *obufp++ = 'l';
13134             }
13135           else
13136             *obufp++ = 'w';
13137           if (intel_syntax && !p[1]
13138               && ((rex & REX_W) || (sizeflag & DFLAG)))
13139             *obufp++ = 'e';
13140           if (!(rex & REX_W))
13141             used_prefixes |= (prefixes & PREFIX_DATA);
13142           break;
13143         case 'V':
13144           if (l == 0 && len == 1)
13145             {
13146               if (intel_syntax)
13147                 break;
13148               if (address_mode == mode_64bit
13149                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13150                 {
13151                   if (sizeflag & SUFFIX_ALWAYS)
13152                     *obufp++ = 'q';
13153                   break;
13154                 }
13155             }
13156           else
13157             {
13158               if (l != 1
13159                   || len != 2
13160                   || last[0] != 'L')
13161                 {
13162                   SAVE_LAST (*p);
13163                   break;
13164                 }
13165
13166               if (rex & REX_W)
13167                 {
13168                   *obufp++ = 'a';
13169                   *obufp++ = 'b';
13170                   *obufp++ = 's';
13171                 }
13172             }
13173           /* Fall through.  */
13174           goto case_S;
13175         case 'S':
13176           if (l == 0 && len == 1)
13177             {
13178             case_S:
13179               if (intel_syntax)
13180                 break;
13181               if (sizeflag & SUFFIX_ALWAYS)
13182                 {
13183                   if (rex & REX_W)
13184                     *obufp++ = 'q';
13185                   else
13186                     {
13187                       if (sizeflag & DFLAG)
13188                         *obufp++ = 'l';
13189                       else
13190                         *obufp++ = 'w';
13191                       used_prefixes |= (prefixes & PREFIX_DATA);
13192                     }
13193                 }
13194             }
13195           else
13196             {
13197               if (l != 1
13198                   || len != 2
13199                   || last[0] != 'L')
13200                 {
13201                   SAVE_LAST (*p);
13202                   break;
13203                 }
13204
13205               if (address_mode == mode_64bit
13206                   && !(prefixes & PREFIX_ADDR))
13207                 {
13208                   *obufp++ = 'a';
13209                   *obufp++ = 'b';
13210                   *obufp++ = 's';
13211                 }
13212
13213               goto case_S;
13214             }
13215           break;
13216         case 'X':
13217           if (l != 0 || len != 1)
13218             {
13219               SAVE_LAST (*p);
13220               break;
13221             }
13222           if (need_vex && vex.prefix)
13223             {
13224               if (vex.prefix == DATA_PREFIX_OPCODE)
13225                 *obufp++ = 'd';
13226               else
13227                 *obufp++ = 's';
13228             }
13229           else
13230             {
13231               if (prefixes & PREFIX_DATA)
13232                 *obufp++ = 'd';
13233               else
13234                 *obufp++ = 's';
13235               used_prefixes |= (prefixes & PREFIX_DATA);
13236             }
13237           break;
13238         case 'Y':
13239           if (l == 0 && len == 1)
13240             abort ();
13241           else
13242             {
13243               if (l != 1 || len != 2 || last[0] != 'X')
13244                 {
13245                   SAVE_LAST (*p);
13246                   break;
13247                 }
13248               if (!need_vex)
13249                 abort ();
13250               if (intel_syntax
13251                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13252                 break;
13253               switch (vex.length)
13254                 {
13255                 case 128:
13256                   *obufp++ = 'x';
13257                   break;
13258                 case 256:
13259                   *obufp++ = 'y';
13260                   break;
13261                 case 512:
13262                   if (!vex.evex)
13263                 default:
13264                     abort ();
13265                 }
13266             }
13267           break;
13268         case 'W':
13269           if (l == 0 && len == 1)
13270             {
13271               /* operand size flag for cwtl, cbtw */
13272               USED_REX (REX_W);
13273               if (rex & REX_W)
13274                 {
13275                   if (intel_syntax)
13276                     *obufp++ = 'd';
13277                   else
13278                     *obufp++ = 'l';
13279                 }
13280               else if (sizeflag & DFLAG)
13281                 *obufp++ = 'w';
13282               else
13283                 *obufp++ = 'b';
13284               if (!(rex & REX_W))
13285                 used_prefixes |= (prefixes & PREFIX_DATA);
13286             }
13287           else
13288             {
13289               if (l != 1
13290                   || len != 2
13291                   || (last[0] != 'X'
13292                       && last[0] != 'L'))
13293                 {
13294                   SAVE_LAST (*p);
13295                   break;
13296                 }
13297               if (!need_vex)
13298                 abort ();
13299               if (last[0] == 'X')
13300                 *obufp++ = vex.w ? 'd': 's';
13301               else
13302                 *obufp++ = vex.w ? 'q': 'd';
13303             }
13304           break;
13305         case '^':
13306           if (intel_syntax)
13307             break;
13308           if (isa64 == intel64 && (rex & REX_W))
13309             {
13310               USED_REX (REX_W);
13311               *obufp++ = 'q';
13312               break;
13313             }
13314           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13315             {
13316               if (sizeflag & DFLAG)
13317                 *obufp++ = 'l';
13318               else
13319                 *obufp++ = 'w';
13320               used_prefixes |= (prefixes & PREFIX_DATA);
13321             }
13322           break;
13323         case '@':
13324           if (intel_syntax)
13325             break;
13326           if (address_mode == mode_64bit
13327               && (isa64 == intel64
13328                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13329               *obufp++ = 'q';
13330           else if ((prefixes & PREFIX_DATA))
13331             {
13332               if (!(sizeflag & DFLAG))
13333                 *obufp++ = 'w';
13334               used_prefixes |= (prefixes & PREFIX_DATA);
13335             }
13336           break;
13337         }
13338       alt = 0;
13339     }
13340   *obufp = 0;
13341   mnemonicendp = obufp;
13342   return 0;
13343 }
13344
13345 static void
13346 oappend (const char *s)
13347 {
13348   obufp = stpcpy (obufp, s);
13349 }
13350
13351 static void
13352 append_seg (void)
13353 {
13354   /* Only print the active segment register.  */
13355   if (!active_seg_prefix)
13356     return;
13357
13358   used_prefixes |= active_seg_prefix;
13359   switch (active_seg_prefix)
13360     {
13361     case PREFIX_CS:
13362       oappend_maybe_intel ("%cs:");
13363       break;
13364     case PREFIX_DS:
13365       oappend_maybe_intel ("%ds:");
13366       break;
13367     case PREFIX_SS:
13368       oappend_maybe_intel ("%ss:");
13369       break;
13370     case PREFIX_ES:
13371       oappend_maybe_intel ("%es:");
13372       break;
13373     case PREFIX_FS:
13374       oappend_maybe_intel ("%fs:");
13375       break;
13376     case PREFIX_GS:
13377       oappend_maybe_intel ("%gs:");
13378       break;
13379     default:
13380       break;
13381     }
13382 }
13383
13384 static void
13385 OP_indirE (int bytemode, int sizeflag)
13386 {
13387   if (!intel_syntax)
13388     oappend ("*");
13389   OP_E (bytemode, sizeflag);
13390 }
13391
13392 static void
13393 print_operand_value (char *buf, int hex, bfd_vma disp)
13394 {
13395   if (address_mode == mode_64bit)
13396     {
13397       if (hex)
13398         {
13399           char tmp[30];
13400           int i;
13401           buf[0] = '0';
13402           buf[1] = 'x';
13403           sprintf_vma (tmp, disp);
13404           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13405           strcpy (buf + 2, tmp + i);
13406         }
13407       else
13408         {
13409           bfd_signed_vma v = disp;
13410           char tmp[30];
13411           int i;
13412           if (v < 0)
13413             {
13414               *(buf++) = '-';
13415               v = -disp;
13416               /* Check for possible overflow on 0x8000000000000000.  */
13417               if (v < 0)
13418                 {
13419                   strcpy (buf, "9223372036854775808");
13420                   return;
13421                 }
13422             }
13423           if (!v)
13424             {
13425               strcpy (buf, "0");
13426               return;
13427             }
13428
13429           i = 0;
13430           tmp[29] = 0;
13431           while (v)
13432             {
13433               tmp[28 - i] = (v % 10) + '0';
13434               v /= 10;
13435               i++;
13436             }
13437           strcpy (buf, tmp + 29 - i);
13438         }
13439     }
13440   else
13441     {
13442       if (hex)
13443         sprintf (buf, "0x%x", (unsigned int) disp);
13444       else
13445         sprintf (buf, "%d", (int) disp);
13446     }
13447 }
13448
13449 /* Put DISP in BUF as signed hex number.  */
13450
13451 static void
13452 print_displacement (char *buf, bfd_vma disp)
13453 {
13454   bfd_signed_vma val = disp;
13455   char tmp[30];
13456   int i, j = 0;
13457
13458   if (val < 0)
13459     {
13460       buf[j++] = '-';
13461       val = -disp;
13462
13463       /* Check for possible overflow.  */
13464       if (val < 0)
13465         {
13466           switch (address_mode)
13467             {
13468             case mode_64bit:
13469               strcpy (buf + j, "0x8000000000000000");
13470               break;
13471             case mode_32bit:
13472               strcpy (buf + j, "0x80000000");
13473               break;
13474             case mode_16bit:
13475               strcpy (buf + j, "0x8000");
13476               break;
13477             }
13478           return;
13479         }
13480     }
13481
13482   buf[j++] = '0';
13483   buf[j++] = 'x';
13484
13485   sprintf_vma (tmp, (bfd_vma) val);
13486   for (i = 0; tmp[i] == '0'; i++)
13487     continue;
13488   if (tmp[i] == '\0')
13489     i--;
13490   strcpy (buf + j, tmp + i);
13491 }
13492
13493 static void
13494 intel_operand_size (int bytemode, int sizeflag)
13495 {
13496   if (vex.evex
13497       && vex.b
13498       && (bytemode == x_mode
13499           || bytemode == evex_half_bcst_xmmq_mode))
13500     {
13501       if (vex.w)
13502         oappend ("QWORD PTR ");
13503       else
13504         oappend ("DWORD PTR ");
13505       return;
13506     }
13507   switch (bytemode)
13508     {
13509     case b_mode:
13510     case b_swap_mode:
13511     case dqb_mode:
13512     case db_mode:
13513       oappend ("BYTE PTR ");
13514       break;
13515     case w_mode:
13516     case dw_mode:
13517     case dqw_mode:
13518       oappend ("WORD PTR ");
13519       break;
13520     case indir_v_mode:
13521       if (address_mode == mode_64bit && isa64 == intel64)
13522         {
13523           oappend ("QWORD PTR ");
13524           break;
13525         }
13526       /* Fall through.  */
13527     case stack_v_mode:
13528       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13529         {
13530           oappend ("QWORD PTR ");
13531           break;
13532         }
13533       /* Fall through.  */
13534     case v_mode:
13535     case v_swap_mode:
13536     case dq_mode:
13537       USED_REX (REX_W);
13538       if (rex & REX_W)
13539         oappend ("QWORD PTR ");
13540       else
13541         {
13542           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13543             oappend ("DWORD PTR ");
13544           else
13545             oappend ("WORD PTR ");
13546           used_prefixes |= (prefixes & PREFIX_DATA);
13547         }
13548       break;
13549     case z_mode:
13550       if ((rex & REX_W) || (sizeflag & DFLAG))
13551         *obufp++ = 'D';
13552       oappend ("WORD PTR ");
13553       if (!(rex & REX_W))
13554         used_prefixes |= (prefixes & PREFIX_DATA);
13555       break;
13556     case a_mode:
13557       if (sizeflag & DFLAG)
13558         oappend ("QWORD PTR ");
13559       else
13560         oappend ("DWORD PTR ");
13561       used_prefixes |= (prefixes & PREFIX_DATA);
13562       break;
13563     case movsxd_mode:
13564       if (!(sizeflag & DFLAG) && isa64 == intel64)
13565         oappend ("WORD PTR ");
13566       else
13567         oappend ("DWORD PTR ");
13568       used_prefixes |= (prefixes & PREFIX_DATA);
13569       break;
13570     case d_mode:
13571     case d_scalar_mode:
13572     case d_scalar_swap_mode:
13573     case d_swap_mode:
13574     case dqd_mode:
13575       oappend ("DWORD PTR ");
13576       break;
13577     case q_mode:
13578     case q_scalar_mode:
13579     case q_scalar_swap_mode:
13580     case q_swap_mode:
13581       oappend ("QWORD PTR ");
13582       break;
13583     case m_mode:
13584       if (address_mode == mode_64bit)
13585         oappend ("QWORD PTR ");
13586       else
13587         oappend ("DWORD PTR ");
13588       break;
13589     case f_mode:
13590       if (sizeflag & DFLAG)
13591         oappend ("FWORD PTR ");
13592       else
13593         oappend ("DWORD PTR ");
13594       used_prefixes |= (prefixes & PREFIX_DATA);
13595       break;
13596     case t_mode:
13597       oappend ("TBYTE PTR ");
13598       break;
13599     case x_mode:
13600     case x_swap_mode:
13601     case evex_x_gscat_mode:
13602     case evex_x_nobcst_mode:
13603     case b_scalar_mode:
13604     case w_scalar_mode:
13605       if (need_vex)
13606         {
13607           switch (vex.length)
13608             {
13609             case 128:
13610               oappend ("XMMWORD PTR ");
13611               break;
13612             case 256:
13613               oappend ("YMMWORD PTR ");
13614               break;
13615             case 512:
13616               oappend ("ZMMWORD PTR ");
13617               break;
13618             default:
13619               abort ();
13620             }
13621         }
13622       else
13623         oappend ("XMMWORD PTR ");
13624       break;
13625     case xmm_mode:
13626       oappend ("XMMWORD PTR ");
13627       break;
13628     case ymm_mode:
13629       oappend ("YMMWORD PTR ");
13630       break;
13631     case xmmq_mode:
13632     case evex_half_bcst_xmmq_mode:
13633       if (!need_vex)
13634         abort ();
13635
13636       switch (vex.length)
13637         {
13638         case 128:
13639           oappend ("QWORD PTR ");
13640           break;
13641         case 256:
13642           oappend ("XMMWORD PTR ");
13643           break;
13644         case 512:
13645           oappend ("YMMWORD PTR ");
13646           break;
13647         default:
13648           abort ();
13649         }
13650       break;
13651     case xmm_mb_mode:
13652       if (!need_vex)
13653         abort ();
13654
13655       switch (vex.length)
13656         {
13657         case 128:
13658         case 256:
13659         case 512:
13660           oappend ("BYTE PTR ");
13661           break;
13662         default:
13663           abort ();
13664         }
13665       break;
13666     case xmm_mw_mode:
13667       if (!need_vex)
13668         abort ();
13669
13670       switch (vex.length)
13671         {
13672         case 128:
13673         case 256:
13674         case 512:
13675           oappend ("WORD PTR ");
13676           break;
13677         default:
13678           abort ();
13679         }
13680       break;
13681     case xmm_md_mode:
13682       if (!need_vex)
13683         abort ();
13684
13685       switch (vex.length)
13686         {
13687         case 128:
13688         case 256:
13689         case 512:
13690           oappend ("DWORD PTR ");
13691           break;
13692         default:
13693           abort ();
13694         }
13695       break;
13696     case xmm_mq_mode:
13697       if (!need_vex)
13698         abort ();
13699
13700       switch (vex.length)
13701         {
13702         case 128:
13703         case 256:
13704         case 512:
13705           oappend ("QWORD PTR ");
13706           break;
13707         default:
13708           abort ();
13709         }
13710       break;
13711     case xmmdw_mode:
13712       if (!need_vex)
13713         abort ();
13714
13715       switch (vex.length)
13716         {
13717         case 128:
13718           oappend ("WORD PTR ");
13719           break;
13720         case 256:
13721           oappend ("DWORD PTR ");
13722           break;
13723         case 512:
13724           oappend ("QWORD PTR ");
13725           break;
13726         default:
13727           abort ();
13728         }
13729       break;
13730     case xmmqd_mode:
13731       if (!need_vex)
13732         abort ();
13733
13734       switch (vex.length)
13735         {
13736         case 128:
13737           oappend ("DWORD PTR ");
13738           break;
13739         case 256:
13740           oappend ("QWORD PTR ");
13741           break;
13742         case 512:
13743           oappend ("XMMWORD PTR ");
13744           break;
13745         default:
13746           abort ();
13747         }
13748       break;
13749     case ymmq_mode:
13750       if (!need_vex)
13751         abort ();
13752
13753       switch (vex.length)
13754         {
13755         case 128:
13756           oappend ("QWORD PTR ");
13757           break;
13758         case 256:
13759           oappend ("YMMWORD PTR ");
13760           break;
13761         case 512:
13762           oappend ("ZMMWORD PTR ");
13763           break;
13764         default:
13765           abort ();
13766         }
13767       break;
13768     case ymmxmm_mode:
13769       if (!need_vex)
13770         abort ();
13771
13772       switch (vex.length)
13773         {
13774         case 128:
13775         case 256:
13776           oappend ("XMMWORD PTR ");
13777           break;
13778         default:
13779           abort ();
13780         }
13781       break;
13782     case o_mode:
13783       oappend ("OWORD PTR ");
13784       break;
13785     case vex_scalar_w_dq_mode:
13786       if (!need_vex)
13787         abort ();
13788
13789       if (vex.w)
13790         oappend ("QWORD PTR ");
13791       else
13792         oappend ("DWORD PTR ");
13793       break;
13794     case vex_vsib_d_w_dq_mode:
13795     case vex_vsib_q_w_dq_mode:
13796       if (!need_vex)
13797         abort ();
13798
13799       if (!vex.evex)
13800         {
13801           if (vex.w)
13802             oappend ("QWORD PTR ");
13803           else
13804             oappend ("DWORD PTR ");
13805         }
13806       else
13807         {
13808           switch (vex.length)
13809             {
13810             case 128:
13811               oappend ("XMMWORD PTR ");
13812               break;
13813             case 256:
13814               oappend ("YMMWORD PTR ");
13815               break;
13816             case 512:
13817               oappend ("ZMMWORD PTR ");
13818               break;
13819             default:
13820               abort ();
13821             }
13822         }
13823       break;
13824     case vex_vsib_q_w_d_mode:
13825     case vex_vsib_d_w_d_mode:
13826       if (!need_vex || !vex.evex)
13827         abort ();
13828
13829       switch (vex.length)
13830         {
13831         case 128:
13832           oappend ("QWORD PTR ");
13833           break;
13834         case 256:
13835           oappend ("XMMWORD PTR ");
13836           break;
13837         case 512:
13838           oappend ("YMMWORD PTR ");
13839           break;
13840         default:
13841           abort ();
13842         }
13843
13844       break;
13845     case mask_bd_mode:
13846       if (!need_vex || vex.length != 128)
13847         abort ();
13848       if (vex.w)
13849         oappend ("DWORD PTR ");
13850       else
13851         oappend ("BYTE PTR ");
13852       break;
13853     case mask_mode:
13854       if (!need_vex)
13855         abort ();
13856       if (vex.w)
13857         oappend ("QWORD PTR ");
13858       else
13859         oappend ("WORD PTR ");
13860       break;
13861     case v_bnd_mode:
13862     case v_bndmk_mode:
13863     default:
13864       break;
13865     }
13866 }
13867
13868 static void
13869 OP_E_register (int bytemode, int sizeflag)
13870 {
13871   int reg = modrm.rm;
13872   const char **names;
13873
13874   USED_REX (REX_B);
13875   if ((rex & REX_B))
13876     reg += 8;
13877
13878   if ((sizeflag & SUFFIX_ALWAYS)
13879       && (bytemode == b_swap_mode
13880           || bytemode == bnd_swap_mode
13881           || bytemode == v_swap_mode))
13882     swap_operand ();
13883
13884   switch (bytemode)
13885     {
13886     case b_mode:
13887     case b_swap_mode:
13888       USED_REX (0);
13889       if (rex)
13890         names = names8rex;
13891       else
13892         names = names8;
13893       break;
13894     case w_mode:
13895       names = names16;
13896       break;
13897     case d_mode:
13898     case dw_mode:
13899     case db_mode:
13900       names = names32;
13901       break;
13902     case q_mode:
13903       names = names64;
13904       break;
13905     case m_mode:
13906     case v_bnd_mode:
13907       names = address_mode == mode_64bit ? names64 : names32;
13908       break;
13909     case bnd_mode:
13910     case bnd_swap_mode:
13911       if (reg > 0x3)
13912         {
13913           oappend ("(bad)");
13914           return;
13915         }
13916       names = names_bnd;
13917       break;
13918     case indir_v_mode:
13919       if (address_mode == mode_64bit && isa64 == intel64)
13920         {
13921           names = names64;
13922           break;
13923         }
13924       /* Fall through.  */
13925     case stack_v_mode:
13926       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13927         {
13928           names = names64;
13929           break;
13930         }
13931       bytemode = v_mode;
13932       /* Fall through.  */
13933     case v_mode:
13934     case v_swap_mode:
13935     case dq_mode:
13936     case dqb_mode:
13937     case dqd_mode:
13938     case dqw_mode:
13939       USED_REX (REX_W);
13940       if (rex & REX_W)
13941         names = names64;
13942       else
13943         {
13944           if ((sizeflag & DFLAG)
13945               || (bytemode != v_mode
13946                   && bytemode != v_swap_mode))
13947             names = names32;
13948           else
13949             names = names16;
13950           used_prefixes |= (prefixes & PREFIX_DATA);
13951         }
13952       break;
13953     case movsxd_mode:
13954       if (!(sizeflag & DFLAG) && isa64 == intel64)
13955         names = names16;
13956       else
13957         names = names32;
13958       used_prefixes |= (prefixes & PREFIX_DATA);
13959       break;
13960     case va_mode:
13961       names = (address_mode == mode_64bit
13962                ? names64 : names32);
13963       if (!(prefixes & PREFIX_ADDR))
13964         names = (address_mode == mode_16bit
13965                      ? names16 : names);
13966       else
13967         {
13968           /* Remove "addr16/addr32".  */
13969           all_prefixes[last_addr_prefix] = 0;
13970           names = (address_mode != mode_32bit
13971                        ? names32 : names16);
13972           used_prefixes |= PREFIX_ADDR;
13973         }
13974       break;
13975     case mask_bd_mode:
13976     case mask_mode:
13977       if (reg > 0x7)
13978         {
13979           oappend ("(bad)");
13980           return;
13981         }
13982       names = names_mask;
13983       break;
13984     case 0:
13985       return;
13986     default:
13987       oappend (INTERNAL_DISASSEMBLER_ERROR);
13988       return;
13989     }
13990   oappend (names[reg]);
13991 }
13992
13993 static void
13994 OP_E_memory (int bytemode, int sizeflag)
13995 {
13996   bfd_vma disp = 0;
13997   int add = (rex & REX_B) ? 8 : 0;
13998   int riprel = 0;
13999   int shift;
14000
14001   if (vex.evex)
14002     {
14003       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14004       if (vex.b
14005           && bytemode != x_mode
14006           && bytemode != xmmq_mode
14007           && bytemode != evex_half_bcst_xmmq_mode)
14008         {
14009           BadOp ();
14010           return;
14011         }
14012       switch (bytemode)
14013         {
14014         case dqw_mode:
14015         case dw_mode:
14016           shift = 1;
14017           break;
14018         case dqb_mode:
14019         case db_mode:
14020           shift = 0;
14021           break;
14022         case dq_mode:
14023           if (address_mode != mode_64bit)
14024             {
14025               shift = 2;
14026               break;
14027             }
14028             /* fall through */
14029         case vex_scalar_w_dq_mode:
14030         case vex_vsib_d_w_dq_mode:
14031         case vex_vsib_d_w_d_mode:
14032         case vex_vsib_q_w_dq_mode:
14033         case vex_vsib_q_w_d_mode:
14034         case evex_x_gscat_mode:
14035           shift = vex.w ? 3 : 2;
14036           break;
14037         case x_mode:
14038         case evex_half_bcst_xmmq_mode:
14039         case xmmq_mode:
14040           if (vex.b)
14041             {
14042               shift = vex.w ? 3 : 2;
14043               break;
14044             }
14045           /* Fall through.  */
14046         case xmmqd_mode:
14047         case xmmdw_mode:
14048         case ymmq_mode:
14049         case evex_x_nobcst_mode:
14050         case x_swap_mode:
14051           switch (vex.length)
14052             {
14053             case 128:
14054               shift = 4;
14055               break;
14056             case 256:
14057               shift = 5;
14058               break;
14059             case 512:
14060               shift = 6;
14061               break;
14062             default:
14063               abort ();
14064             }
14065           break;
14066         case ymm_mode:
14067           shift = 5;
14068           break;
14069         case xmm_mode:
14070           shift = 4;
14071           break;
14072         case xmm_mq_mode:
14073         case q_mode:
14074         case q_scalar_mode:
14075         case q_swap_mode:
14076         case q_scalar_swap_mode:
14077           shift = 3;
14078           break;
14079         case dqd_mode:
14080         case xmm_md_mode:
14081         case d_mode:
14082         case d_scalar_mode:
14083         case d_swap_mode:
14084         case d_scalar_swap_mode:
14085           shift = 2;
14086           break;
14087         case w_scalar_mode:
14088         case xmm_mw_mode:
14089           shift = 1;
14090           break;
14091         case b_scalar_mode:
14092         case xmm_mb_mode:
14093           shift = 0;
14094           break;
14095         default:
14096           abort ();
14097         }
14098       /* Make necessary corrections to shift for modes that need it.
14099          For these modes we currently have shift 4, 5 or 6 depending on
14100          vex.length (it corresponds to xmmword, ymmword or zmmword
14101          operand).  We might want to make it 3, 4 or 5 (e.g. for
14102          xmmq_mode).  In case of broadcast enabled the corrections
14103          aren't needed, as element size is always 32 or 64 bits.  */
14104       if (!vex.b
14105           && (bytemode == xmmq_mode
14106               || bytemode == evex_half_bcst_xmmq_mode))
14107         shift -= 1;
14108       else if (bytemode == xmmqd_mode)
14109         shift -= 2;
14110       else if (bytemode == xmmdw_mode)
14111         shift -= 3;
14112       else if (bytemode == ymmq_mode && vex.length == 128)
14113         shift -= 1;
14114     }
14115   else
14116     shift = 0;
14117
14118   USED_REX (REX_B);
14119   if (intel_syntax)
14120     intel_operand_size (bytemode, sizeflag);
14121   append_seg ();
14122
14123   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14124     {
14125       /* 32/64 bit address mode */
14126       int havedisp;
14127       int havesib;
14128       int havebase;
14129       int haveindex;
14130       int needindex;
14131       int needaddr32;
14132       int base, rbase;
14133       int vindex = 0;
14134       int scale = 0;
14135       int addr32flag = !((sizeflag & AFLAG)
14136                          || bytemode == v_bnd_mode
14137                          || bytemode == v_bndmk_mode
14138                          || bytemode == bnd_mode
14139                          || bytemode == bnd_swap_mode);
14140       const char **indexes64 = names64;
14141       const char **indexes32 = names32;
14142
14143       havesib = 0;
14144       havebase = 1;
14145       haveindex = 0;
14146       base = modrm.rm;
14147
14148       if (base == 4)
14149         {
14150           havesib = 1;
14151           vindex = sib.index;
14152           USED_REX (REX_X);
14153           if (rex & REX_X)
14154             vindex += 8;
14155           switch (bytemode)
14156             {
14157             case vex_vsib_d_w_dq_mode:
14158             case vex_vsib_d_w_d_mode:
14159             case vex_vsib_q_w_dq_mode:
14160             case vex_vsib_q_w_d_mode:
14161               if (!need_vex)
14162                 abort ();
14163               if (vex.evex)
14164                 {
14165                   if (!vex.v)
14166                     vindex += 16;
14167                 }
14168
14169               haveindex = 1;
14170               switch (vex.length)
14171                 {
14172                 case 128:
14173                   indexes64 = indexes32 = names_xmm;
14174                   break;
14175                 case 256:
14176                   if (!vex.w
14177                       || bytemode == vex_vsib_q_w_dq_mode
14178                       || bytemode == vex_vsib_q_w_d_mode)
14179                     indexes64 = indexes32 = names_ymm;
14180                   else
14181                     indexes64 = indexes32 = names_xmm;
14182                   break;
14183                 case 512:
14184                   if (!vex.w
14185                       || bytemode == vex_vsib_q_w_dq_mode
14186                       || bytemode == vex_vsib_q_w_d_mode)
14187                     indexes64 = indexes32 = names_zmm;
14188                   else
14189                     indexes64 = indexes32 = names_ymm;
14190                   break;
14191                 default:
14192                   abort ();
14193                 }
14194               break;
14195             default:
14196               haveindex = vindex != 4;
14197               break;
14198             }
14199           scale = sib.scale;
14200           base = sib.base;
14201           codep++;
14202         }
14203       rbase = base + add;
14204
14205       switch (modrm.mod)
14206         {
14207         case 0:
14208           if (base == 5)
14209             {
14210               havebase = 0;
14211               if (address_mode == mode_64bit && !havesib)
14212                 riprel = 1;
14213               disp = get32s ();
14214               if (riprel && bytemode == v_bndmk_mode)
14215                 {
14216                   oappend ("(bad)");
14217                   return;
14218                 }
14219             }
14220           break;
14221         case 1:
14222           FETCH_DATA (the_info, codep + 1);
14223           disp = *codep++;
14224           if ((disp & 0x80) != 0)
14225             disp -= 0x100;
14226           if (vex.evex && shift > 0)
14227             disp <<= shift;
14228           break;
14229         case 2:
14230           disp = get32s ();
14231           break;
14232         }
14233
14234       needindex = 0;
14235       needaddr32 = 0;
14236       if (havesib
14237           && !havebase
14238           && !haveindex
14239           && address_mode != mode_16bit)
14240         {
14241           if (address_mode == mode_64bit)
14242             {
14243               /* Display eiz instead of addr32.  */
14244               needindex = addr32flag;
14245               needaddr32 = 1;
14246             }
14247           else
14248             {
14249               /* In 32-bit mode, we need index register to tell [offset]
14250                  from [eiz*1 + offset].  */
14251               needindex = 1;
14252             }
14253         }
14254
14255       havedisp = (havebase
14256                   || needindex
14257                   || (havesib && (haveindex || scale != 0)));
14258
14259       if (!intel_syntax)
14260         if (modrm.mod != 0 || base == 5)
14261           {
14262             if (havedisp || riprel)
14263               print_displacement (scratchbuf, disp);
14264             else
14265               print_operand_value (scratchbuf, 1, disp);
14266             oappend (scratchbuf);
14267             if (riprel)
14268               {
14269                 set_op (disp, 1);
14270                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14271               }
14272           }
14273
14274       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14275           && (address_mode != mode_64bit
14276               || ((bytemode != v_bnd_mode)
14277                   && (bytemode != v_bndmk_mode)
14278                   && (bytemode != bnd_mode)
14279                   && (bytemode != bnd_swap_mode))))
14280         used_prefixes |= PREFIX_ADDR;
14281
14282       if (havedisp || (intel_syntax && riprel))
14283         {
14284           *obufp++ = open_char;
14285           if (intel_syntax && riprel)
14286             {
14287               set_op (disp, 1);
14288               oappend (!addr32flag ? "rip" : "eip");
14289             }
14290           *obufp = '\0';
14291           if (havebase)
14292             oappend (address_mode == mode_64bit && !addr32flag
14293                      ? names64[rbase] : names32[rbase]);
14294           if (havesib)
14295             {
14296               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14297                  print index to tell base + index from base.  */
14298               if (scale != 0
14299                   || needindex
14300                   || haveindex
14301                   || (havebase && base != ESP_REG_NUM))
14302                 {
14303                   if (!intel_syntax || havebase)
14304                     {
14305                       *obufp++ = separator_char;
14306                       *obufp = '\0';
14307                     }
14308                   if (haveindex)
14309                     oappend (address_mode == mode_64bit && !addr32flag
14310                              ? indexes64[vindex] : indexes32[vindex]);
14311                   else
14312                     oappend (address_mode == mode_64bit && !addr32flag
14313                              ? index64 : index32);
14314
14315                   *obufp++ = scale_char;
14316                   *obufp = '\0';
14317                   sprintf (scratchbuf, "%d", 1 << scale);
14318                   oappend (scratchbuf);
14319                 }
14320             }
14321           if (intel_syntax
14322               && (disp || modrm.mod != 0 || base == 5))
14323             {
14324               if (!havedisp || (bfd_signed_vma) disp >= 0)
14325                 {
14326                   *obufp++ = '+';
14327                   *obufp = '\0';
14328                 }
14329               else if (modrm.mod != 1 && disp != -disp)
14330                 {
14331                   *obufp++ = '-';
14332                   *obufp = '\0';
14333                   disp = - (bfd_signed_vma) disp;
14334                 }
14335
14336               if (havedisp)
14337                 print_displacement (scratchbuf, disp);
14338               else
14339                 print_operand_value (scratchbuf, 1, disp);
14340               oappend (scratchbuf);
14341             }
14342
14343           *obufp++ = close_char;
14344           *obufp = '\0';
14345         }
14346       else if (intel_syntax)
14347         {
14348           if (modrm.mod != 0 || base == 5)
14349             {
14350               if (!active_seg_prefix)
14351                 {
14352                   oappend (names_seg[ds_reg - es_reg]);
14353                   oappend (":");
14354                 }
14355               print_operand_value (scratchbuf, 1, disp);
14356               oappend (scratchbuf);
14357             }
14358         }
14359     }
14360   else if (bytemode == v_bnd_mode
14361            || bytemode == v_bndmk_mode
14362            || bytemode == bnd_mode
14363            || bytemode == bnd_swap_mode)
14364     {
14365       oappend ("(bad)");
14366       return;
14367     }
14368   else
14369     {
14370       /* 16 bit address mode */
14371       used_prefixes |= prefixes & PREFIX_ADDR;
14372       switch (modrm.mod)
14373         {
14374         case 0:
14375           if (modrm.rm == 6)
14376             {
14377               disp = get16 ();
14378               if ((disp & 0x8000) != 0)
14379                 disp -= 0x10000;
14380             }
14381           break;
14382         case 1:
14383           FETCH_DATA (the_info, codep + 1);
14384           disp = *codep++;
14385           if ((disp & 0x80) != 0)
14386             disp -= 0x100;
14387           if (vex.evex && shift > 0)
14388             disp <<= shift;
14389           break;
14390         case 2:
14391           disp = get16 ();
14392           if ((disp & 0x8000) != 0)
14393             disp -= 0x10000;
14394           break;
14395         }
14396
14397       if (!intel_syntax)
14398         if (modrm.mod != 0 || modrm.rm == 6)
14399           {
14400             print_displacement (scratchbuf, disp);
14401             oappend (scratchbuf);
14402           }
14403
14404       if (modrm.mod != 0 || modrm.rm != 6)
14405         {
14406           *obufp++ = open_char;
14407           *obufp = '\0';
14408           oappend (index16[modrm.rm]);
14409           if (intel_syntax
14410               && (disp || modrm.mod != 0 || modrm.rm == 6))
14411             {
14412               if ((bfd_signed_vma) disp >= 0)
14413                 {
14414                   *obufp++ = '+';
14415                   *obufp = '\0';
14416                 }
14417               else if (modrm.mod != 1)
14418                 {
14419                   *obufp++ = '-';
14420                   *obufp = '\0';
14421                   disp = - (bfd_signed_vma) disp;
14422                 }
14423
14424               print_displacement (scratchbuf, disp);
14425               oappend (scratchbuf);
14426             }
14427
14428           *obufp++ = close_char;
14429           *obufp = '\0';
14430         }
14431       else if (intel_syntax)
14432         {
14433           if (!active_seg_prefix)
14434             {
14435               oappend (names_seg[ds_reg - es_reg]);
14436               oappend (":");
14437             }
14438           print_operand_value (scratchbuf, 1, disp & 0xffff);
14439           oappend (scratchbuf);
14440         }
14441     }
14442   if (vex.evex && vex.b
14443       && (bytemode == x_mode
14444           || bytemode == xmmq_mode
14445           || bytemode == evex_half_bcst_xmmq_mode))
14446     {
14447       if (vex.w
14448           || bytemode == xmmq_mode
14449           || bytemode == evex_half_bcst_xmmq_mode)
14450         {
14451           switch (vex.length)
14452             {
14453             case 128:
14454               oappend ("{1to2}");
14455               break;
14456             case 256:
14457               oappend ("{1to4}");
14458               break;
14459             case 512:
14460               oappend ("{1to8}");
14461               break;
14462             default:
14463               abort ();
14464             }
14465         }
14466       else
14467         {
14468           switch (vex.length)
14469             {
14470             case 128:
14471               oappend ("{1to4}");
14472               break;
14473             case 256:
14474               oappend ("{1to8}");
14475               break;
14476             case 512:
14477               oappend ("{1to16}");
14478               break;
14479             default:
14480               abort ();
14481             }
14482         }
14483     }
14484 }
14485
14486 static void
14487 OP_E (int bytemode, int sizeflag)
14488 {
14489   /* Skip mod/rm byte.  */
14490   MODRM_CHECK;
14491   codep++;
14492
14493   if (modrm.mod == 3)
14494     OP_E_register (bytemode, sizeflag);
14495   else
14496     OP_E_memory (bytemode, sizeflag);
14497 }
14498
14499 static void
14500 OP_G (int bytemode, int sizeflag)
14501 {
14502   int add = 0;
14503   const char **names;
14504   USED_REX (REX_R);
14505   if (rex & REX_R)
14506     add += 8;
14507   switch (bytemode)
14508     {
14509     case b_mode:
14510       USED_REX (0);
14511       if (rex)
14512         oappend (names8rex[modrm.reg + add]);
14513       else
14514         oappend (names8[modrm.reg + add]);
14515       break;
14516     case w_mode:
14517       oappend (names16[modrm.reg + add]);
14518       break;
14519     case d_mode:
14520     case db_mode:
14521     case dw_mode:
14522       oappend (names32[modrm.reg + add]);
14523       break;
14524     case q_mode:
14525       oappend (names64[modrm.reg + add]);
14526       break;
14527     case bnd_mode:
14528       if (modrm.reg > 0x3)
14529         {
14530           oappend ("(bad)");
14531           return;
14532         }
14533       oappend (names_bnd[modrm.reg]);
14534       break;
14535     case v_mode:
14536     case dq_mode:
14537     case dqb_mode:
14538     case dqd_mode:
14539     case dqw_mode:
14540     case movsxd_mode:
14541       USED_REX (REX_W);
14542       if (rex & REX_W)
14543         oappend (names64[modrm.reg + add]);
14544       else
14545         {
14546           if ((sizeflag & DFLAG)
14547               || (bytemode != v_mode && bytemode != movsxd_mode))
14548             oappend (names32[modrm.reg + add]);
14549           else
14550             oappend (names16[modrm.reg + add]);
14551           used_prefixes |= (prefixes & PREFIX_DATA);
14552         }
14553       break;
14554     case va_mode:
14555       names = (address_mode == mode_64bit
14556                ? names64 : names32);
14557       if (!(prefixes & PREFIX_ADDR))
14558         {
14559           if (address_mode == mode_16bit)
14560             names = names16;
14561         }
14562       else
14563         {
14564           /* Remove "addr16/addr32".  */
14565           all_prefixes[last_addr_prefix] = 0;
14566           names = (address_mode != mode_32bit
14567                        ? names32 : names16);
14568           used_prefixes |= PREFIX_ADDR;
14569         }
14570       oappend (names[modrm.reg + add]);
14571       break;
14572     case m_mode:
14573       if (address_mode == mode_64bit)
14574         oappend (names64[modrm.reg + add]);
14575       else
14576         oappend (names32[modrm.reg + add]);
14577       break;
14578     case mask_bd_mode:
14579     case mask_mode:
14580       if ((modrm.reg + add) > 0x7)
14581         {
14582           oappend ("(bad)");
14583           return;
14584         }
14585       oappend (names_mask[modrm.reg + add]);
14586       break;
14587     default:
14588       oappend (INTERNAL_DISASSEMBLER_ERROR);
14589       break;
14590     }
14591 }
14592
14593 static bfd_vma
14594 get64 (void)
14595 {
14596   bfd_vma x;
14597 #ifdef BFD64
14598   unsigned int a;
14599   unsigned int b;
14600
14601   FETCH_DATA (the_info, codep + 8);
14602   a = *codep++ & 0xff;
14603   a |= (*codep++ & 0xff) << 8;
14604   a |= (*codep++ & 0xff) << 16;
14605   a |= (*codep++ & 0xffu) << 24;
14606   b = *codep++ & 0xff;
14607   b |= (*codep++ & 0xff) << 8;
14608   b |= (*codep++ & 0xff) << 16;
14609   b |= (*codep++ & 0xffu) << 24;
14610   x = a + ((bfd_vma) b << 32);
14611 #else
14612   abort ();
14613   x = 0;
14614 #endif
14615   return x;
14616 }
14617
14618 static bfd_signed_vma
14619 get32 (void)
14620 {
14621   bfd_signed_vma x = 0;
14622
14623   FETCH_DATA (the_info, codep + 4);
14624   x = *codep++ & (bfd_signed_vma) 0xff;
14625   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14626   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14627   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14628   return x;
14629 }
14630
14631 static bfd_signed_vma
14632 get32s (void)
14633 {
14634   bfd_signed_vma x = 0;
14635
14636   FETCH_DATA (the_info, codep + 4);
14637   x = *codep++ & (bfd_signed_vma) 0xff;
14638   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14639   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14640   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14641
14642   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14643
14644   return x;
14645 }
14646
14647 static int
14648 get16 (void)
14649 {
14650   int x = 0;
14651
14652   FETCH_DATA (the_info, codep + 2);
14653   x = *codep++ & 0xff;
14654   x |= (*codep++ & 0xff) << 8;
14655   return x;
14656 }
14657
14658 static void
14659 set_op (bfd_vma op, int riprel)
14660 {
14661   op_index[op_ad] = op_ad;
14662   if (address_mode == mode_64bit)
14663     {
14664       op_address[op_ad] = op;
14665       op_riprel[op_ad] = riprel;
14666     }
14667   else
14668     {
14669       /* Mask to get a 32-bit address.  */
14670       op_address[op_ad] = op & 0xffffffff;
14671       op_riprel[op_ad] = riprel & 0xffffffff;
14672     }
14673 }
14674
14675 static void
14676 OP_REG (int code, int sizeflag)
14677 {
14678   const char *s;
14679   int add;
14680
14681   switch (code)
14682     {
14683     case es_reg: case ss_reg: case cs_reg:
14684     case ds_reg: case fs_reg: case gs_reg:
14685       oappend (names_seg[code - es_reg]);
14686       return;
14687     }
14688
14689   USED_REX (REX_B);
14690   if (rex & REX_B)
14691     add = 8;
14692   else
14693     add = 0;
14694
14695   switch (code)
14696     {
14697     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14698     case sp_reg: case bp_reg: case si_reg: case di_reg:
14699       s = names16[code - ax_reg + add];
14700       break;
14701     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14702     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14703       USED_REX (0);
14704       if (rex)
14705         s = names8rex[code - al_reg + add];
14706       else
14707         s = names8[code - al_reg];
14708       break;
14709     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14710     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14711       if (address_mode == mode_64bit
14712           && ((sizeflag & DFLAG) || (rex & REX_W)))
14713         {
14714           s = names64[code - rAX_reg + add];
14715           break;
14716         }
14717       code += eAX_reg - rAX_reg;
14718       /* Fall through.  */
14719     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14720     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14721       USED_REX (REX_W);
14722       if (rex & REX_W)
14723         s = names64[code - eAX_reg + add];
14724       else
14725         {
14726           if (sizeflag & DFLAG)
14727             s = names32[code - eAX_reg + add];
14728           else
14729             s = names16[code - eAX_reg + add];
14730           used_prefixes |= (prefixes & PREFIX_DATA);
14731         }
14732       break;
14733     default:
14734       s = INTERNAL_DISASSEMBLER_ERROR;
14735       break;
14736     }
14737   oappend (s);
14738 }
14739
14740 static void
14741 OP_IMREG (int code, int sizeflag)
14742 {
14743   const char *s;
14744
14745   switch (code)
14746     {
14747     case indir_dx_reg:
14748       if (intel_syntax)
14749         s = "dx";
14750       else
14751         s = "(%dx)";
14752       break;
14753     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14754     case sp_reg: case bp_reg: case si_reg: case di_reg:
14755       s = names16[code - ax_reg];
14756       break;
14757     case es_reg: case ss_reg: case cs_reg:
14758     case ds_reg: case fs_reg: case gs_reg:
14759       s = names_seg[code - es_reg];
14760       break;
14761     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14762     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14763       USED_REX (0);
14764       if (rex)
14765         s = names8rex[code - al_reg];
14766       else
14767         s = names8[code - al_reg];
14768       break;
14769     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14770     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14771       USED_REX (REX_W);
14772       if (rex & REX_W)
14773         s = names64[code - eAX_reg];
14774       else
14775         {
14776           if (sizeflag & DFLAG)
14777             s = names32[code - eAX_reg];
14778           else
14779             s = names16[code - eAX_reg];
14780           used_prefixes |= (prefixes & PREFIX_DATA);
14781         }
14782       break;
14783     case z_mode_ax_reg:
14784       if ((rex & REX_W) || (sizeflag & DFLAG))
14785         s = *names32;
14786       else
14787         s = *names16;
14788       if (!(rex & REX_W))
14789         used_prefixes |= (prefixes & PREFIX_DATA);
14790       break;
14791     default:
14792       s = INTERNAL_DISASSEMBLER_ERROR;
14793       break;
14794     }
14795   oappend (s);
14796 }
14797
14798 static void
14799 OP_I (int bytemode, int sizeflag)
14800 {
14801   bfd_signed_vma op;
14802   bfd_signed_vma mask = -1;
14803
14804   switch (bytemode)
14805     {
14806     case b_mode:
14807       FETCH_DATA (the_info, codep + 1);
14808       op = *codep++;
14809       mask = 0xff;
14810       break;
14811     case v_mode:
14812       USED_REX (REX_W);
14813       if (rex & REX_W)
14814         op = get32s ();
14815       else
14816         {
14817           if (sizeflag & DFLAG)
14818             {
14819               op = get32 ();
14820               mask = 0xffffffff;
14821             }
14822           else
14823             {
14824               op = get16 ();
14825               mask = 0xfffff;
14826             }
14827           used_prefixes |= (prefixes & PREFIX_DATA);
14828         }
14829       break;
14830     case d_mode:
14831       mask = 0xffffffff;
14832       op = get32 ();
14833       break;
14834     case w_mode:
14835       mask = 0xfffff;
14836       op = get16 ();
14837       break;
14838     case const_1_mode:
14839       if (intel_syntax)
14840         oappend ("1");
14841       return;
14842     default:
14843       oappend (INTERNAL_DISASSEMBLER_ERROR);
14844       return;
14845     }
14846
14847   op &= mask;
14848   scratchbuf[0] = '$';
14849   print_operand_value (scratchbuf + 1, 1, op);
14850   oappend_maybe_intel (scratchbuf);
14851   scratchbuf[0] = '\0';
14852 }
14853
14854 static void
14855 OP_I64 (int bytemode, int sizeflag)
14856 {
14857   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14858     {
14859       OP_I (bytemode, sizeflag);
14860       return;
14861     }
14862
14863   USED_REX (REX_W);
14864
14865   scratchbuf[0] = '$';
14866   print_operand_value (scratchbuf + 1, 1, get64 ());
14867   oappend_maybe_intel (scratchbuf);
14868   scratchbuf[0] = '\0';
14869 }
14870
14871 static void
14872 OP_sI (int bytemode, int sizeflag)
14873 {
14874   bfd_signed_vma op;
14875
14876   switch (bytemode)
14877     {
14878     case b_mode:
14879     case b_T_mode:
14880       FETCH_DATA (the_info, codep + 1);
14881       op = *codep++;
14882       if ((op & 0x80) != 0)
14883         op -= 0x100;
14884       if (bytemode == b_T_mode)
14885         {
14886           if (address_mode != mode_64bit
14887               || !((sizeflag & DFLAG) || (rex & REX_W)))
14888             {
14889               /* The operand-size prefix is overridden by a REX prefix.  */
14890               if ((sizeflag & DFLAG) || (rex & REX_W))
14891                 op &= 0xffffffff;
14892               else
14893                 op &= 0xffff;
14894           }
14895         }
14896       else
14897         {
14898           if (!(rex & REX_W))
14899             {
14900               if (sizeflag & DFLAG)
14901                 op &= 0xffffffff;
14902               else
14903                 op &= 0xffff;
14904             }
14905         }
14906       break;
14907     case v_mode:
14908       /* The operand-size prefix is overridden by a REX prefix.  */
14909       if ((sizeflag & DFLAG) || (rex & REX_W))
14910         op = get32s ();
14911       else
14912         op = get16 ();
14913       break;
14914     default:
14915       oappend (INTERNAL_DISASSEMBLER_ERROR);
14916       return;
14917     }
14918
14919   scratchbuf[0] = '$';
14920   print_operand_value (scratchbuf + 1, 1, op);
14921   oappend_maybe_intel (scratchbuf);
14922 }
14923
14924 static void
14925 OP_J (int bytemode, int sizeflag)
14926 {
14927   bfd_vma disp;
14928   bfd_vma mask = -1;
14929   bfd_vma segment = 0;
14930
14931   switch (bytemode)
14932     {
14933     case b_mode:
14934       FETCH_DATA (the_info, codep + 1);
14935       disp = *codep++;
14936       if ((disp & 0x80) != 0)
14937         disp -= 0x100;
14938       break;
14939     case v_mode:
14940       if (isa64 != intel64)
14941     case dqw_mode:
14942         USED_REX (REX_W);
14943       if ((sizeflag & DFLAG)
14944           || (address_mode == mode_64bit
14945               && ((isa64 == intel64 && bytemode != dqw_mode)
14946                   || (rex & REX_W))))
14947         disp = get32s ();
14948       else
14949         {
14950           disp = get16 ();
14951           if ((disp & 0x8000) != 0)
14952             disp -= 0x10000;
14953           /* In 16bit mode, address is wrapped around at 64k within
14954              the same segment.  Otherwise, a data16 prefix on a jump
14955              instruction means that the pc is masked to 16 bits after
14956              the displacement is added!  */
14957           mask = 0xffff;
14958           if ((prefixes & PREFIX_DATA) == 0)
14959             segment = ((start_pc + (codep - start_codep))
14960                        & ~((bfd_vma) 0xffff));
14961         }
14962       if (address_mode != mode_64bit
14963           || (isa64 != intel64 && !(rex & REX_W)))
14964         used_prefixes |= (prefixes & PREFIX_DATA);
14965       break;
14966     default:
14967       oappend (INTERNAL_DISASSEMBLER_ERROR);
14968       return;
14969     }
14970   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14971   set_op (disp, 0);
14972   print_operand_value (scratchbuf, 1, disp);
14973   oappend (scratchbuf);
14974 }
14975
14976 static void
14977 OP_SEG (int bytemode, int sizeflag)
14978 {
14979   if (bytemode == w_mode)
14980     oappend (names_seg[modrm.reg]);
14981   else
14982     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14983 }
14984
14985 static void
14986 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14987 {
14988   int seg, offset;
14989
14990   if (sizeflag & DFLAG)
14991     {
14992       offset = get32 ();
14993       seg = get16 ();
14994     }
14995   else
14996     {
14997       offset = get16 ();
14998       seg = get16 ();
14999     }
15000   used_prefixes |= (prefixes & PREFIX_DATA);
15001   if (intel_syntax)
15002     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15003   else
15004     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15005   oappend (scratchbuf);
15006 }
15007
15008 static void
15009 OP_OFF (int bytemode, int sizeflag)
15010 {
15011   bfd_vma off;
15012
15013   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15014     intel_operand_size (bytemode, sizeflag);
15015   append_seg ();
15016
15017   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15018     off = get32 ();
15019   else
15020     off = get16 ();
15021
15022   if (intel_syntax)
15023     {
15024       if (!active_seg_prefix)
15025         {
15026           oappend (names_seg[ds_reg - es_reg]);
15027           oappend (":");
15028         }
15029     }
15030   print_operand_value (scratchbuf, 1, off);
15031   oappend (scratchbuf);
15032 }
15033
15034 static void
15035 OP_OFF64 (int bytemode, int sizeflag)
15036 {
15037   bfd_vma off;
15038
15039   if (address_mode != mode_64bit
15040       || (prefixes & PREFIX_ADDR))
15041     {
15042       OP_OFF (bytemode, sizeflag);
15043       return;
15044     }
15045
15046   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15047     intel_operand_size (bytemode, sizeflag);
15048   append_seg ();
15049
15050   off = get64 ();
15051
15052   if (intel_syntax)
15053     {
15054       if (!active_seg_prefix)
15055         {
15056           oappend (names_seg[ds_reg - es_reg]);
15057           oappend (":");
15058         }
15059     }
15060   print_operand_value (scratchbuf, 1, off);
15061   oappend (scratchbuf);
15062 }
15063
15064 static void
15065 ptr_reg (int code, int sizeflag)
15066 {
15067   const char *s;
15068
15069   *obufp++ = open_char;
15070   used_prefixes |= (prefixes & PREFIX_ADDR);
15071   if (address_mode == mode_64bit)
15072     {
15073       if (!(sizeflag & AFLAG))
15074         s = names32[code - eAX_reg];
15075       else
15076         s = names64[code - eAX_reg];
15077     }
15078   else if (sizeflag & AFLAG)
15079     s = names32[code - eAX_reg];
15080   else
15081     s = names16[code - eAX_reg];
15082   oappend (s);
15083   *obufp++ = close_char;
15084   *obufp = 0;
15085 }
15086
15087 static void
15088 OP_ESreg (int code, int sizeflag)
15089 {
15090   if (intel_syntax)
15091     {
15092       switch (codep[-1])
15093         {
15094         case 0x6d:      /* insw/insl */
15095           intel_operand_size (z_mode, sizeflag);
15096           break;
15097         case 0xa5:      /* movsw/movsl/movsq */
15098         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15099         case 0xab:      /* stosw/stosl */
15100         case 0xaf:      /* scasw/scasl */
15101           intel_operand_size (v_mode, sizeflag);
15102           break;
15103         default:
15104           intel_operand_size (b_mode, sizeflag);
15105         }
15106     }
15107   oappend_maybe_intel ("%es:");
15108   ptr_reg (code, sizeflag);
15109 }
15110
15111 static void
15112 OP_DSreg (int code, int sizeflag)
15113 {
15114   if (intel_syntax)
15115     {
15116       switch (codep[-1])
15117         {
15118         case 0x6f:      /* outsw/outsl */
15119           intel_operand_size (z_mode, sizeflag);
15120           break;
15121         case 0xa5:      /* movsw/movsl/movsq */
15122         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15123         case 0xad:      /* lodsw/lodsl/lodsq */
15124           intel_operand_size (v_mode, sizeflag);
15125           break;
15126         default:
15127           intel_operand_size (b_mode, sizeflag);
15128         }
15129     }
15130   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15131      default segment register DS is printed.  */
15132   if (!active_seg_prefix)
15133     active_seg_prefix = PREFIX_DS;
15134   append_seg ();
15135   ptr_reg (code, sizeflag);
15136 }
15137
15138 static void
15139 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15140 {
15141   int add;
15142   if (rex & REX_R)
15143     {
15144       USED_REX (REX_R);
15145       add = 8;
15146     }
15147   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15148     {
15149       all_prefixes[last_lock_prefix] = 0;
15150       used_prefixes |= PREFIX_LOCK;
15151       add = 8;
15152     }
15153   else
15154     add = 0;
15155   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15156   oappend_maybe_intel (scratchbuf);
15157 }
15158
15159 static void
15160 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15161 {
15162   int add;
15163   USED_REX (REX_R);
15164   if (rex & REX_R)
15165     add = 8;
15166   else
15167     add = 0;
15168   if (intel_syntax)
15169     sprintf (scratchbuf, "db%d", modrm.reg + add);
15170   else
15171     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15172   oappend (scratchbuf);
15173 }
15174
15175 static void
15176 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15177 {
15178   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15179   oappend_maybe_intel (scratchbuf);
15180 }
15181
15182 static void
15183 OP_R (int bytemode, int sizeflag)
15184 {
15185   /* Skip mod/rm byte.  */
15186   MODRM_CHECK;
15187   codep++;
15188   OP_E_register (bytemode, sizeflag);
15189 }
15190
15191 static void
15192 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15193 {
15194   int reg = modrm.reg;
15195   const char **names;
15196
15197   used_prefixes |= (prefixes & PREFIX_DATA);
15198   if (prefixes & PREFIX_DATA)
15199     {
15200       names = names_xmm;
15201       USED_REX (REX_R);
15202       if (rex & REX_R)
15203         reg += 8;
15204     }
15205   else
15206     names = names_mm;
15207   oappend (names[reg]);
15208 }
15209
15210 static void
15211 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15212 {
15213   int reg = modrm.reg;
15214   const char **names;
15215
15216   USED_REX (REX_R);
15217   if (rex & REX_R)
15218     reg += 8;
15219   if (vex.evex)
15220     {
15221       if (!vex.r)
15222         reg += 16;
15223     }
15224
15225   if (need_vex
15226       && bytemode != xmm_mode
15227       && bytemode != xmmq_mode
15228       && bytemode != evex_half_bcst_xmmq_mode
15229       && bytemode != ymm_mode
15230       && bytemode != scalar_mode)
15231     {
15232       switch (vex.length)
15233         {
15234         case 128:
15235           names = names_xmm;
15236           break;
15237         case 256:
15238           if (vex.w
15239               || (bytemode != vex_vsib_q_w_dq_mode
15240                   && bytemode != vex_vsib_q_w_d_mode))
15241             names = names_ymm;
15242           else
15243             names = names_xmm;
15244           break;
15245         case 512:
15246           names = names_zmm;
15247           break;
15248         default:
15249           abort ();
15250         }
15251     }
15252   else if (bytemode == xmmq_mode
15253            || bytemode == evex_half_bcst_xmmq_mode)
15254     {
15255       switch (vex.length)
15256         {
15257         case 128:
15258         case 256:
15259           names = names_xmm;
15260           break;
15261         case 512:
15262           names = names_ymm;
15263           break;
15264         default:
15265           abort ();
15266         }
15267     }
15268   else if (bytemode == ymm_mode)
15269     names = names_ymm;
15270   else
15271     names = names_xmm;
15272   oappend (names[reg]);
15273 }
15274
15275 static void
15276 OP_EM (int bytemode, int sizeflag)
15277 {
15278   int reg;
15279   const char **names;
15280
15281   if (modrm.mod != 3)
15282     {
15283       if (intel_syntax
15284           && (bytemode == v_mode || bytemode == v_swap_mode))
15285         {
15286           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15287           used_prefixes |= (prefixes & PREFIX_DATA);
15288         }
15289       OP_E (bytemode, sizeflag);
15290       return;
15291     }
15292
15293   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15294     swap_operand ();
15295
15296   /* Skip mod/rm byte.  */
15297   MODRM_CHECK;
15298   codep++;
15299   used_prefixes |= (prefixes & PREFIX_DATA);
15300   reg = modrm.rm;
15301   if (prefixes & PREFIX_DATA)
15302     {
15303       names = names_xmm;
15304       USED_REX (REX_B);
15305       if (rex & REX_B)
15306         reg += 8;
15307     }
15308   else
15309     names = names_mm;
15310   oappend (names[reg]);
15311 }
15312
15313 /* cvt* are the only instructions in sse2 which have
15314    both SSE and MMX operands and also have 0x66 prefix
15315    in their opcode. 0x66 was originally used to differentiate
15316    between SSE and MMX instruction(operands). So we have to handle the
15317    cvt* separately using OP_EMC and OP_MXC */
15318 static void
15319 OP_EMC (int bytemode, int sizeflag)
15320 {
15321   if (modrm.mod != 3)
15322     {
15323       if (intel_syntax && bytemode == v_mode)
15324         {
15325           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15326           used_prefixes |= (prefixes & PREFIX_DATA);
15327         }
15328       OP_E (bytemode, sizeflag);
15329       return;
15330     }
15331
15332   /* Skip mod/rm byte.  */
15333   MODRM_CHECK;
15334   codep++;
15335   used_prefixes |= (prefixes & PREFIX_DATA);
15336   oappend (names_mm[modrm.rm]);
15337 }
15338
15339 static void
15340 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15341 {
15342   used_prefixes |= (prefixes & PREFIX_DATA);
15343   oappend (names_mm[modrm.reg]);
15344 }
15345
15346 static void
15347 OP_EX (int bytemode, int sizeflag)
15348 {
15349   int reg;
15350   const char **names;
15351
15352   /* Skip mod/rm byte.  */
15353   MODRM_CHECK;
15354   codep++;
15355
15356   if (modrm.mod != 3)
15357     {
15358       OP_E_memory (bytemode, sizeflag);
15359       return;
15360     }
15361
15362   reg = modrm.rm;
15363   USED_REX (REX_B);
15364   if (rex & REX_B)
15365     reg += 8;
15366   if (vex.evex)
15367     {
15368       USED_REX (REX_X);
15369       if ((rex & REX_X))
15370         reg += 16;
15371     }
15372
15373   if ((sizeflag & SUFFIX_ALWAYS)
15374       && (bytemode == x_swap_mode
15375           || bytemode == d_swap_mode
15376           || bytemode == d_scalar_swap_mode
15377           || bytemode == q_swap_mode
15378           || bytemode == q_scalar_swap_mode))
15379     swap_operand ();
15380
15381   if (need_vex
15382       && bytemode != xmm_mode
15383       && bytemode != xmmdw_mode
15384       && bytemode != xmmqd_mode
15385       && bytemode != xmm_mb_mode
15386       && bytemode != xmm_mw_mode
15387       && bytemode != xmm_md_mode
15388       && bytemode != xmm_mq_mode
15389       && bytemode != xmmq_mode
15390       && bytemode != evex_half_bcst_xmmq_mode
15391       && bytemode != ymm_mode
15392       && bytemode != d_scalar_mode
15393       && bytemode != d_scalar_swap_mode
15394       && bytemode != q_scalar_mode
15395       && bytemode != q_scalar_swap_mode
15396       && bytemode != vex_scalar_w_dq_mode)
15397     {
15398       switch (vex.length)
15399         {
15400         case 128:
15401           names = names_xmm;
15402           break;
15403         case 256:
15404           names = names_ymm;
15405           break;
15406         case 512:
15407           names = names_zmm;
15408           break;
15409         default:
15410           abort ();
15411         }
15412     }
15413   else if (bytemode == xmmq_mode
15414            || bytemode == evex_half_bcst_xmmq_mode)
15415     {
15416       switch (vex.length)
15417         {
15418         case 128:
15419         case 256:
15420           names = names_xmm;
15421           break;
15422         case 512:
15423           names = names_ymm;
15424           break;
15425         default:
15426           abort ();
15427         }
15428     }
15429   else if (bytemode == ymm_mode)
15430     names = names_ymm;
15431   else
15432     names = names_xmm;
15433   oappend (names[reg]);
15434 }
15435
15436 static void
15437 OP_MS (int bytemode, int sizeflag)
15438 {
15439   if (modrm.mod == 3)
15440     OP_EM (bytemode, sizeflag);
15441   else
15442     BadOp ();
15443 }
15444
15445 static void
15446 OP_XS (int bytemode, int sizeflag)
15447 {
15448   if (modrm.mod == 3)
15449     OP_EX (bytemode, sizeflag);
15450   else
15451     BadOp ();
15452 }
15453
15454 static void
15455 OP_M (int bytemode, int sizeflag)
15456 {
15457   if (modrm.mod == 3)
15458     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15459     BadOp ();
15460   else
15461     OP_E (bytemode, sizeflag);
15462 }
15463
15464 static void
15465 OP_0f07 (int bytemode, int sizeflag)
15466 {
15467   if (modrm.mod != 3 || modrm.rm != 0)
15468     BadOp ();
15469   else
15470     OP_E (bytemode, sizeflag);
15471 }
15472
15473 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15474    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15475
15476 static void
15477 NOP_Fixup1 (int bytemode, int sizeflag)
15478 {
15479   if ((prefixes & PREFIX_DATA) != 0
15480       || (rex != 0
15481           && rex != 0x48
15482           && address_mode == mode_64bit))
15483     OP_REG (bytemode, sizeflag);
15484   else
15485     strcpy (obuf, "nop");
15486 }
15487
15488 static void
15489 NOP_Fixup2 (int bytemode, int sizeflag)
15490 {
15491   if ((prefixes & PREFIX_DATA) != 0
15492       || (rex != 0
15493           && rex != 0x48
15494           && address_mode == mode_64bit))
15495     OP_IMREG (bytemode, sizeflag);
15496 }
15497
15498 static const char *const Suffix3DNow[] = {
15499 /* 00 */        NULL,           NULL,           NULL,           NULL,
15500 /* 04 */        NULL,           NULL,           NULL,           NULL,
15501 /* 08 */        NULL,           NULL,           NULL,           NULL,
15502 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15503 /* 10 */        NULL,           NULL,           NULL,           NULL,
15504 /* 14 */        NULL,           NULL,           NULL,           NULL,
15505 /* 18 */        NULL,           NULL,           NULL,           NULL,
15506 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15507 /* 20 */        NULL,           NULL,           NULL,           NULL,
15508 /* 24 */        NULL,           NULL,           NULL,           NULL,
15509 /* 28 */        NULL,           NULL,           NULL,           NULL,
15510 /* 2C */        NULL,           NULL,           NULL,           NULL,
15511 /* 30 */        NULL,           NULL,           NULL,           NULL,
15512 /* 34 */        NULL,           NULL,           NULL,           NULL,
15513 /* 38 */        NULL,           NULL,           NULL,           NULL,
15514 /* 3C */        NULL,           NULL,           NULL,           NULL,
15515 /* 40 */        NULL,           NULL,           NULL,           NULL,
15516 /* 44 */        NULL,           NULL,           NULL,           NULL,
15517 /* 48 */        NULL,           NULL,           NULL,           NULL,
15518 /* 4C */        NULL,           NULL,           NULL,           NULL,
15519 /* 50 */        NULL,           NULL,           NULL,           NULL,
15520 /* 54 */        NULL,           NULL,           NULL,           NULL,
15521 /* 58 */        NULL,           NULL,           NULL,           NULL,
15522 /* 5C */        NULL,           NULL,           NULL,           NULL,
15523 /* 60 */        NULL,           NULL,           NULL,           NULL,
15524 /* 64 */        NULL,           NULL,           NULL,           NULL,
15525 /* 68 */        NULL,           NULL,           NULL,           NULL,
15526 /* 6C */        NULL,           NULL,           NULL,           NULL,
15527 /* 70 */        NULL,           NULL,           NULL,           NULL,
15528 /* 74 */        NULL,           NULL,           NULL,           NULL,
15529 /* 78 */        NULL,           NULL,           NULL,           NULL,
15530 /* 7C */        NULL,           NULL,           NULL,           NULL,
15531 /* 80 */        NULL,           NULL,           NULL,           NULL,
15532 /* 84 */        NULL,           NULL,           NULL,           NULL,
15533 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15534 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15535 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15536 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15537 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15538 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15539 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15540 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15541 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15542 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15543 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15544 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15545 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15546 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15547 /* C0 */        NULL,           NULL,           NULL,           NULL,
15548 /* C4 */        NULL,           NULL,           NULL,           NULL,
15549 /* C8 */        NULL,           NULL,           NULL,           NULL,
15550 /* CC */        NULL,           NULL,           NULL,           NULL,
15551 /* D0 */        NULL,           NULL,           NULL,           NULL,
15552 /* D4 */        NULL,           NULL,           NULL,           NULL,
15553 /* D8 */        NULL,           NULL,           NULL,           NULL,
15554 /* DC */        NULL,           NULL,           NULL,           NULL,
15555 /* E0 */        NULL,           NULL,           NULL,           NULL,
15556 /* E4 */        NULL,           NULL,           NULL,           NULL,
15557 /* E8 */        NULL,           NULL,           NULL,           NULL,
15558 /* EC */        NULL,           NULL,           NULL,           NULL,
15559 /* F0 */        NULL,           NULL,           NULL,           NULL,
15560 /* F4 */        NULL,           NULL,           NULL,           NULL,
15561 /* F8 */        NULL,           NULL,           NULL,           NULL,
15562 /* FC */        NULL,           NULL,           NULL,           NULL,
15563 };
15564
15565 static void
15566 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15567 {
15568   const char *mnemonic;
15569
15570   FETCH_DATA (the_info, codep + 1);
15571   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15572      place where an 8-bit immediate would normally go.  ie. the last
15573      byte of the instruction.  */
15574   obufp = mnemonicendp;
15575   mnemonic = Suffix3DNow[*codep++ & 0xff];
15576   if (mnemonic)
15577     oappend (mnemonic);
15578   else
15579     {
15580       /* Since a variable sized modrm/sib chunk is between the start
15581          of the opcode (0x0f0f) and the opcode suffix, we need to do
15582          all the modrm processing first, and don't know until now that
15583          we have a bad opcode.  This necessitates some cleaning up.  */
15584       op_out[0][0] = '\0';
15585       op_out[1][0] = '\0';
15586       BadOp ();
15587     }
15588   mnemonicendp = obufp;
15589 }
15590
15591 static struct op simd_cmp_op[] =
15592 {
15593   { STRING_COMMA_LEN ("eq") },
15594   { STRING_COMMA_LEN ("lt") },
15595   { STRING_COMMA_LEN ("le") },
15596   { STRING_COMMA_LEN ("unord") },
15597   { STRING_COMMA_LEN ("neq") },
15598   { STRING_COMMA_LEN ("nlt") },
15599   { STRING_COMMA_LEN ("nle") },
15600   { STRING_COMMA_LEN ("ord") }
15601 };
15602
15603 static void
15604 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15605 {
15606   unsigned int cmp_type;
15607
15608   FETCH_DATA (the_info, codep + 1);
15609   cmp_type = *codep++ & 0xff;
15610   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15611     {
15612       char suffix [3];
15613       char *p = mnemonicendp - 2;
15614       suffix[0] = p[0];
15615       suffix[1] = p[1];
15616       suffix[2] = '\0';
15617       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15618       mnemonicendp += simd_cmp_op[cmp_type].len;
15619     }
15620   else
15621     {
15622       /* We have a reserved extension byte.  Output it directly.  */
15623       scratchbuf[0] = '$';
15624       print_operand_value (scratchbuf + 1, 1, cmp_type);
15625       oappend_maybe_intel (scratchbuf);
15626       scratchbuf[0] = '\0';
15627     }
15628 }
15629
15630 static void
15631 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15632 {
15633   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15634   if (!intel_syntax)
15635     {
15636       strcpy (op_out[0], names32[0]);
15637       strcpy (op_out[1], names32[1]);
15638       if (bytemode == eBX_reg)
15639         strcpy (op_out[2], names32[3]);
15640       two_source_ops = 1;
15641     }
15642   /* Skip mod/rm byte.  */
15643   MODRM_CHECK;
15644   codep++;
15645 }
15646
15647 static void
15648 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15649             int sizeflag ATTRIBUTE_UNUSED)
15650 {
15651   /* monitor %{e,r,}ax,%ecx,%edx"  */
15652   if (!intel_syntax)
15653     {
15654       const char **names = (address_mode == mode_64bit
15655                             ? names64 : names32);
15656
15657       if (prefixes & PREFIX_ADDR)
15658         {
15659           /* Remove "addr16/addr32".  */
15660           all_prefixes[last_addr_prefix] = 0;
15661           names = (address_mode != mode_32bit
15662                    ? names32 : names16);
15663           used_prefixes |= PREFIX_ADDR;
15664         }
15665       else if (address_mode == mode_16bit)
15666         names = names16;
15667       strcpy (op_out[0], names[0]);
15668       strcpy (op_out[1], names32[1]);
15669       strcpy (op_out[2], names32[2]);
15670       two_source_ops = 1;
15671     }
15672   /* Skip mod/rm byte.  */
15673   MODRM_CHECK;
15674   codep++;
15675 }
15676
15677 static void
15678 BadOp (void)
15679 {
15680   /* Throw away prefixes and 1st. opcode byte.  */
15681   codep = insn_codep + 1;
15682   oappend ("(bad)");
15683 }
15684
15685 static void
15686 REP_Fixup (int bytemode, int sizeflag)
15687 {
15688   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15689      lods and stos.  */
15690   if (prefixes & PREFIX_REPZ)
15691     all_prefixes[last_repz_prefix] = REP_PREFIX;
15692
15693   switch (bytemode)
15694     {
15695     case al_reg:
15696     case eAX_reg:
15697     case indir_dx_reg:
15698       OP_IMREG (bytemode, sizeflag);
15699       break;
15700     case eDI_reg:
15701       OP_ESreg (bytemode, sizeflag);
15702       break;
15703     case eSI_reg:
15704       OP_DSreg (bytemode, sizeflag);
15705       break;
15706     default:
15707       abort ();
15708       break;
15709     }
15710 }
15711
15712 static void
15713 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15714 {
15715   if ( isa64 != amd64 )
15716     return;
15717
15718   obufp = obuf;
15719   BadOp ();
15720   mnemonicendp = obufp;
15721   ++codep;
15722 }
15723
15724 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15725    "bnd".  */
15726
15727 static void
15728 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15729 {
15730   if (prefixes & PREFIX_REPNZ)
15731     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15732 }
15733
15734 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15735    "notrack".  */
15736
15737 static void
15738 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15739                int sizeflag ATTRIBUTE_UNUSED)
15740 {
15741   if (active_seg_prefix == PREFIX_DS
15742       && (address_mode != mode_64bit || last_data_prefix < 0))
15743     {
15744       /* NOTRACK prefix is only valid on indirect branch instructions.
15745          NB: DATA prefix is unsupported for Intel64.  */
15746       active_seg_prefix = 0;
15747       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15748     }
15749 }
15750
15751 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15752    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15753  */
15754
15755 static void
15756 HLE_Fixup1 (int bytemode, int sizeflag)
15757 {
15758   if (modrm.mod != 3
15759       && (prefixes & PREFIX_LOCK) != 0)
15760     {
15761       if (prefixes & PREFIX_REPZ)
15762         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15763       if (prefixes & PREFIX_REPNZ)
15764         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15765     }
15766
15767   OP_E (bytemode, sizeflag);
15768 }
15769
15770 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15771    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15772  */
15773
15774 static void
15775 HLE_Fixup2 (int bytemode, int sizeflag)
15776 {
15777   if (modrm.mod != 3)
15778     {
15779       if (prefixes & PREFIX_REPZ)
15780         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15781       if (prefixes & PREFIX_REPNZ)
15782         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15783     }
15784
15785   OP_E (bytemode, sizeflag);
15786 }
15787
15788 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15789    "xrelease" for memory operand.  No check for LOCK prefix.   */
15790
15791 static void
15792 HLE_Fixup3 (int bytemode, int sizeflag)
15793 {
15794   if (modrm.mod != 3
15795       && last_repz_prefix > last_repnz_prefix
15796       && (prefixes & PREFIX_REPZ) != 0)
15797     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15798
15799   OP_E (bytemode, sizeflag);
15800 }
15801
15802 static void
15803 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15804 {
15805   USED_REX (REX_W);
15806   if (rex & REX_W)
15807     {
15808       /* Change cmpxchg8b to cmpxchg16b.  */
15809       char *p = mnemonicendp - 2;
15810       mnemonicendp = stpcpy (p, "16b");
15811       bytemode = o_mode;
15812     }
15813   else if ((prefixes & PREFIX_LOCK) != 0)
15814     {
15815       if (prefixes & PREFIX_REPZ)
15816         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15817       if (prefixes & PREFIX_REPNZ)
15818         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15819     }
15820
15821   OP_M (bytemode, sizeflag);
15822 }
15823
15824 static void
15825 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15826 {
15827   const char **names;
15828
15829   if (need_vex)
15830     {
15831       switch (vex.length)
15832         {
15833         case 128:
15834           names = names_xmm;
15835           break;
15836         case 256:
15837           names = names_ymm;
15838           break;
15839         default:
15840           abort ();
15841         }
15842     }
15843   else
15844     names = names_xmm;
15845   oappend (names[reg]);
15846 }
15847
15848 static void
15849 CRC32_Fixup (int bytemode, int sizeflag)
15850 {
15851   /* Add proper suffix to "crc32".  */
15852   char *p = mnemonicendp;
15853
15854   switch (bytemode)
15855     {
15856     case b_mode:
15857       if (intel_syntax)
15858         goto skip;
15859
15860       *p++ = 'b';
15861       break;
15862     case v_mode:
15863       if (intel_syntax)
15864         goto skip;
15865
15866       USED_REX (REX_W);
15867       if (rex & REX_W)
15868         *p++ = 'q';
15869       else
15870         {
15871           if (sizeflag & DFLAG)
15872             *p++ = 'l';
15873           else
15874             *p++ = 'w';
15875           used_prefixes |= (prefixes & PREFIX_DATA);
15876         }
15877       break;
15878     default:
15879       oappend (INTERNAL_DISASSEMBLER_ERROR);
15880       break;
15881     }
15882   mnemonicendp = p;
15883   *p = '\0';
15884
15885  skip:
15886   if (modrm.mod == 3)
15887     {
15888       int add;
15889
15890       /* Skip mod/rm byte.  */
15891       MODRM_CHECK;
15892       codep++;
15893
15894       USED_REX (REX_B);
15895       add = (rex & REX_B) ? 8 : 0;
15896       if (bytemode == b_mode)
15897         {
15898           USED_REX (0);
15899           if (rex)
15900             oappend (names8rex[modrm.rm + add]);
15901           else
15902             oappend (names8[modrm.rm + add]);
15903         }
15904       else
15905         {
15906           USED_REX (REX_W);
15907           if (rex & REX_W)
15908             oappend (names64[modrm.rm + add]);
15909           else if ((prefixes & PREFIX_DATA))
15910             oappend (names16[modrm.rm + add]);
15911           else
15912             oappend (names32[modrm.rm + add]);
15913         }
15914     }
15915   else
15916     OP_E (bytemode, sizeflag);
15917 }
15918
15919 static void
15920 FXSAVE_Fixup (int bytemode, int sizeflag)
15921 {
15922   /* Add proper suffix to "fxsave" and "fxrstor".  */
15923   USED_REX (REX_W);
15924   if (rex & REX_W)
15925     {
15926       char *p = mnemonicendp;
15927       *p++ = '6';
15928       *p++ = '4';
15929       *p = '\0';
15930       mnemonicendp = p;
15931     }
15932   OP_M (bytemode, sizeflag);
15933 }
15934
15935 static void
15936 PCMPESTR_Fixup (int bytemode, int sizeflag)
15937 {
15938   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15939   if (!intel_syntax)
15940     {
15941       char *p = mnemonicendp;
15942
15943       USED_REX (REX_W);
15944       if (rex & REX_W)
15945         *p++ = 'q';
15946       else if (sizeflag & SUFFIX_ALWAYS)
15947         *p++ = 'l';
15948
15949       *p = '\0';
15950       mnemonicendp = p;
15951     }
15952
15953   OP_EX (bytemode, sizeflag);
15954 }
15955
15956 /* Display the destination register operand for instructions with
15957    VEX. */
15958
15959 static void
15960 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15961 {
15962   int reg;
15963   const char **names;
15964
15965   if (!need_vex)
15966     abort ();
15967
15968   if (!need_vex_reg)
15969     return;
15970
15971   reg = vex.register_specifier;
15972   vex.register_specifier = 0;
15973   if (address_mode != mode_64bit)
15974     reg &= 7;
15975   else if (vex.evex && !vex.v)
15976     reg += 16;
15977
15978   if (bytemode == vex_scalar_mode)
15979     {
15980       oappend (names_xmm[reg]);
15981       return;
15982     }
15983
15984   switch (vex.length)
15985     {
15986     case 128:
15987       switch (bytemode)
15988         {
15989         case vex_mode:
15990         case vex128_mode:
15991         case vex_vsib_q_w_dq_mode:
15992         case vex_vsib_q_w_d_mode:
15993           names = names_xmm;
15994           break;
15995         case dq_mode:
15996           if (rex & REX_W)
15997             names = names64;
15998           else
15999             names = names32;
16000           break;
16001         case mask_bd_mode:
16002         case mask_mode:
16003           if (reg > 0x7)
16004             {
16005               oappend ("(bad)");
16006               return;
16007             }
16008           names = names_mask;
16009           break;
16010         default:
16011           abort ();
16012           return;
16013         }
16014       break;
16015     case 256:
16016       switch (bytemode)
16017         {
16018         case vex_mode:
16019         case vex256_mode:
16020           names = names_ymm;
16021           break;
16022         case vex_vsib_q_w_dq_mode:
16023         case vex_vsib_q_w_d_mode:
16024           names = vex.w ? names_ymm : names_xmm;
16025           break;
16026         case mask_bd_mode:
16027         case mask_mode:
16028           if (reg > 0x7)
16029             {
16030               oappend ("(bad)");
16031               return;
16032             }
16033           names = names_mask;
16034           break;
16035         default:
16036           /* See PR binutils/20893 for a reproducer.  */
16037           oappend ("(bad)");
16038           return;
16039         }
16040       break;
16041     case 512:
16042       names = names_zmm;
16043       break;
16044     default:
16045       abort ();
16046       break;
16047     }
16048   oappend (names[reg]);
16049 }
16050
16051 /* Get the VEX immediate byte without moving codep.  */
16052
16053 static unsigned char
16054 get_vex_imm8 (int sizeflag, int opnum)
16055 {
16056   int bytes_before_imm = 0;
16057
16058   if (modrm.mod != 3)
16059     {
16060       /* There are SIB/displacement bytes.  */
16061       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16062         {
16063           /* 32/64 bit address mode */
16064           int base = modrm.rm;
16065
16066           /* Check SIB byte.  */
16067           if (base == 4)
16068             {
16069               FETCH_DATA (the_info, codep + 1);
16070               base = *codep & 7;
16071               /* When decoding the third source, don't increase
16072                  bytes_before_imm as this has already been incremented
16073                  by one in OP_E_memory while decoding the second
16074                  source operand.  */
16075               if (opnum == 0)
16076                 bytes_before_imm++;
16077             }
16078
16079           /* Don't increase bytes_before_imm when decoding the third source,
16080              it has already been incremented by OP_E_memory while decoding
16081              the second source operand.  */
16082           if (opnum == 0)
16083             {
16084               switch (modrm.mod)
16085                 {
16086                   case 0:
16087                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16088                        SIB == 5, there is a 4 byte displacement.  */
16089                     if (base != 5)
16090                       /* No displacement. */
16091                       break;
16092                     /* Fall through.  */
16093                   case 2:
16094                     /* 4 byte displacement.  */
16095                     bytes_before_imm += 4;
16096                     break;
16097                   case 1:
16098                     /* 1 byte displacement.  */
16099                     bytes_before_imm++;
16100                     break;
16101                 }
16102             }
16103         }
16104       else
16105         {
16106           /* 16 bit address mode */
16107           /* Don't increase bytes_before_imm when decoding the third source,
16108              it has already been incremented by OP_E_memory while decoding
16109              the second source operand.  */
16110           if (opnum == 0)
16111             {
16112               switch (modrm.mod)
16113                 {
16114                 case 0:
16115                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16116                   if (modrm.rm != 6)
16117                     /* No displacement. */
16118                     break;
16119                   /* Fall through.  */
16120                 case 2:
16121                   /* 2 byte displacement.  */
16122                   bytes_before_imm += 2;
16123                   break;
16124                 case 1:
16125                   /* 1 byte displacement: when decoding the third source,
16126                      don't increase bytes_before_imm as this has already
16127                      been incremented by one in OP_E_memory while decoding
16128                      the second source operand.  */
16129                   if (opnum == 0)
16130                     bytes_before_imm++;
16131
16132                   break;
16133                 }
16134             }
16135         }
16136     }
16137
16138   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16139   return codep [bytes_before_imm];
16140 }
16141
16142 static void
16143 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16144 {
16145   const char **names;
16146
16147   if (reg == -1 && modrm.mod != 3)
16148     {
16149       OP_E_memory (bytemode, sizeflag);
16150       return;
16151     }
16152   else
16153     {
16154       if (reg == -1)
16155         {
16156           reg = modrm.rm;
16157           USED_REX (REX_B);
16158           if (rex & REX_B)
16159             reg += 8;
16160         }
16161       if (address_mode != mode_64bit)
16162         reg &= 7;
16163     }
16164
16165   switch (vex.length)
16166     {
16167     case 128:
16168       names = names_xmm;
16169       break;
16170     case 256:
16171       names = names_ymm;
16172       break;
16173     default:
16174       abort ();
16175     }
16176   oappend (names[reg]);
16177 }
16178
16179 static void
16180 OP_EX_VexImmW (int bytemode, int sizeflag)
16181 {
16182   int reg = -1;
16183   static unsigned char vex_imm8;
16184
16185   if (vex_w_done == 0)
16186     {
16187       vex_w_done = 1;
16188
16189       /* Skip mod/rm byte.  */
16190       MODRM_CHECK;
16191       codep++;
16192
16193       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16194
16195       if (vex.w)
16196           reg = vex_imm8 >> 4;
16197
16198       OP_EX_VexReg (bytemode, sizeflag, reg);
16199     }
16200   else if (vex_w_done == 1)
16201     {
16202       vex_w_done = 2;
16203
16204       if (!vex.w)
16205           reg = vex_imm8 >> 4;
16206
16207       OP_EX_VexReg (bytemode, sizeflag, reg);
16208     }
16209   else
16210     {
16211       /* Output the imm8 directly.  */
16212       scratchbuf[0] = '$';
16213       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16214       oappend_maybe_intel (scratchbuf);
16215       scratchbuf[0] = '\0';
16216       codep++;
16217     }
16218 }
16219
16220 static void
16221 OP_Vex_2src (int bytemode, int sizeflag)
16222 {
16223   if (modrm.mod == 3)
16224     {
16225       int reg = modrm.rm;
16226       USED_REX (REX_B);
16227       if (rex & REX_B)
16228         reg += 8;
16229       oappend (names_xmm[reg]);
16230     }
16231   else
16232     {
16233       if (intel_syntax
16234           && (bytemode == v_mode || bytemode == v_swap_mode))
16235         {
16236           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16237           used_prefixes |= (prefixes & PREFIX_DATA);
16238         }
16239       OP_E (bytemode, sizeflag);
16240     }
16241 }
16242
16243 static void
16244 OP_Vex_2src_1 (int bytemode, int sizeflag)
16245 {
16246   if (modrm.mod == 3)
16247     {
16248       /* Skip mod/rm byte.   */
16249       MODRM_CHECK;
16250       codep++;
16251     }
16252
16253   if (vex.w)
16254     {
16255       unsigned int reg = vex.register_specifier;
16256       vex.register_specifier = 0;
16257
16258       if (address_mode != mode_64bit)
16259         reg &= 7;
16260       oappend (names_xmm[reg]);
16261     }
16262   else
16263     OP_Vex_2src (bytemode, sizeflag);
16264 }
16265
16266 static void
16267 OP_Vex_2src_2 (int bytemode, int sizeflag)
16268 {
16269   if (vex.w)
16270     OP_Vex_2src (bytemode, sizeflag);
16271   else
16272     {
16273       unsigned int reg = vex.register_specifier;
16274       vex.register_specifier = 0;
16275
16276       if (address_mode != mode_64bit)
16277         reg &= 7;
16278       oappend (names_xmm[reg]);
16279     }
16280 }
16281
16282 static void
16283 OP_EX_VexW (int bytemode, int sizeflag)
16284 {
16285   int reg = -1;
16286
16287   if (!vex_w_done)
16288     {
16289       /* Skip mod/rm byte.  */
16290       MODRM_CHECK;
16291       codep++;
16292
16293       if (vex.w)
16294         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16295     }
16296   else
16297     {
16298       if (!vex.w)
16299         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16300     }
16301
16302   OP_EX_VexReg (bytemode, sizeflag, reg);
16303
16304   if (vex_w_done)
16305     codep++;
16306   vex_w_done = 1;
16307 }
16308
16309 static void
16310 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16311 {
16312   int reg;
16313   const char **names;
16314
16315   FETCH_DATA (the_info, codep + 1);
16316   reg = *codep++;
16317
16318   if (bytemode != x_mode)
16319     abort ();
16320
16321   reg >>= 4;
16322   if (address_mode != mode_64bit)
16323     reg &= 7;
16324
16325   switch (vex.length)
16326     {
16327     case 128:
16328       names = names_xmm;
16329       break;
16330     case 256:
16331       names = names_ymm;
16332       break;
16333     default:
16334       abort ();
16335     }
16336   oappend (names[reg]);
16337 }
16338
16339 static void
16340 OP_XMM_VexW (int bytemode, int sizeflag)
16341 {
16342   /* Turn off the REX.W bit since it is used for swapping operands
16343      now.  */
16344   rex &= ~REX_W;
16345   OP_XMM (bytemode, sizeflag);
16346 }
16347
16348 static void
16349 OP_EX_Vex (int bytemode, int sizeflag)
16350 {
16351   if (modrm.mod != 3)
16352     need_vex_reg = 0;
16353   OP_EX (bytemode, sizeflag);
16354 }
16355
16356 static void
16357 OP_XMM_Vex (int bytemode, int sizeflag)
16358 {
16359   if (modrm.mod != 3)
16360     need_vex_reg = 0;
16361   OP_XMM (bytemode, sizeflag);
16362 }
16363
16364 static struct op vex_cmp_op[] =
16365 {
16366   { STRING_COMMA_LEN ("eq") },
16367   { STRING_COMMA_LEN ("lt") },
16368   { STRING_COMMA_LEN ("le") },
16369   { STRING_COMMA_LEN ("unord") },
16370   { STRING_COMMA_LEN ("neq") },
16371   { STRING_COMMA_LEN ("nlt") },
16372   { STRING_COMMA_LEN ("nle") },
16373   { STRING_COMMA_LEN ("ord") },
16374   { STRING_COMMA_LEN ("eq_uq") },
16375   { STRING_COMMA_LEN ("nge") },
16376   { STRING_COMMA_LEN ("ngt") },
16377   { STRING_COMMA_LEN ("false") },
16378   { STRING_COMMA_LEN ("neq_oq") },
16379   { STRING_COMMA_LEN ("ge") },
16380   { STRING_COMMA_LEN ("gt") },
16381   { STRING_COMMA_LEN ("true") },
16382   { STRING_COMMA_LEN ("eq_os") },
16383   { STRING_COMMA_LEN ("lt_oq") },
16384   { STRING_COMMA_LEN ("le_oq") },
16385   { STRING_COMMA_LEN ("unord_s") },
16386   { STRING_COMMA_LEN ("neq_us") },
16387   { STRING_COMMA_LEN ("nlt_uq") },
16388   { STRING_COMMA_LEN ("nle_uq") },
16389   { STRING_COMMA_LEN ("ord_s") },
16390   { STRING_COMMA_LEN ("eq_us") },
16391   { STRING_COMMA_LEN ("nge_uq") },
16392   { STRING_COMMA_LEN ("ngt_uq") },
16393   { STRING_COMMA_LEN ("false_os") },
16394   { STRING_COMMA_LEN ("neq_os") },
16395   { STRING_COMMA_LEN ("ge_oq") },
16396   { STRING_COMMA_LEN ("gt_oq") },
16397   { STRING_COMMA_LEN ("true_us") },
16398 };
16399
16400 static void
16401 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16402 {
16403   unsigned int cmp_type;
16404
16405   FETCH_DATA (the_info, codep + 1);
16406   cmp_type = *codep++ & 0xff;
16407   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16408     {
16409       char suffix [3];
16410       char *p = mnemonicendp - 2;
16411       suffix[0] = p[0];
16412       suffix[1] = p[1];
16413       suffix[2] = '\0';
16414       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16415       mnemonicendp += vex_cmp_op[cmp_type].len;
16416     }
16417   else
16418     {
16419       /* We have a reserved extension byte.  Output it directly.  */
16420       scratchbuf[0] = '$';
16421       print_operand_value (scratchbuf + 1, 1, cmp_type);
16422       oappend_maybe_intel (scratchbuf);
16423       scratchbuf[0] = '\0';
16424     }
16425 }
16426
16427 static void
16428 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16429              int sizeflag ATTRIBUTE_UNUSED)
16430 {
16431   unsigned int cmp_type;
16432
16433   if (!vex.evex)
16434     abort ();
16435
16436   FETCH_DATA (the_info, codep + 1);
16437   cmp_type = *codep++ & 0xff;
16438   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16439      If it's the case, print suffix, otherwise - print the immediate.  */
16440   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16441       && cmp_type != 3
16442       && cmp_type != 7)
16443     {
16444       char suffix [3];
16445       char *p = mnemonicendp - 2;
16446
16447       /* vpcmp* can have both one- and two-lettered suffix.  */
16448       if (p[0] == 'p')
16449         {
16450           p++;
16451           suffix[0] = p[0];
16452           suffix[1] = '\0';
16453         }
16454       else
16455         {
16456           suffix[0] = p[0];
16457           suffix[1] = p[1];
16458           suffix[2] = '\0';
16459         }
16460
16461       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16462       mnemonicendp += simd_cmp_op[cmp_type].len;
16463     }
16464   else
16465     {
16466       /* We have a reserved extension byte.  Output it directly.  */
16467       scratchbuf[0] = '$';
16468       print_operand_value (scratchbuf + 1, 1, cmp_type);
16469       oappend_maybe_intel (scratchbuf);
16470       scratchbuf[0] = '\0';
16471     }
16472 }
16473
16474 static const struct op xop_cmp_op[] =
16475 {
16476   { STRING_COMMA_LEN ("lt") },
16477   { STRING_COMMA_LEN ("le") },
16478   { STRING_COMMA_LEN ("gt") },
16479   { STRING_COMMA_LEN ("ge") },
16480   { STRING_COMMA_LEN ("eq") },
16481   { STRING_COMMA_LEN ("neq") },
16482   { STRING_COMMA_LEN ("false") },
16483   { STRING_COMMA_LEN ("true") }
16484 };
16485
16486 static void
16487 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16488              int sizeflag ATTRIBUTE_UNUSED)
16489 {
16490   unsigned int cmp_type;
16491
16492   FETCH_DATA (the_info, codep + 1);
16493   cmp_type = *codep++ & 0xff;
16494   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16495     {
16496       char suffix[3];
16497       char *p = mnemonicendp - 2;
16498
16499       /* vpcom* can have both one- and two-lettered suffix.  */
16500       if (p[0] == 'm')
16501         {
16502           p++;
16503           suffix[0] = p[0];
16504           suffix[1] = '\0';
16505         }
16506       else
16507         {
16508           suffix[0] = p[0];
16509           suffix[1] = p[1];
16510           suffix[2] = '\0';
16511         }
16512
16513       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16514       mnemonicendp += xop_cmp_op[cmp_type].len;
16515     }
16516   else
16517     {
16518       /* We have a reserved extension byte.  Output it directly.  */
16519       scratchbuf[0] = '$';
16520       print_operand_value (scratchbuf + 1, 1, cmp_type);
16521       oappend_maybe_intel (scratchbuf);
16522       scratchbuf[0] = '\0';
16523     }
16524 }
16525
16526 static const struct op pclmul_op[] =
16527 {
16528   { STRING_COMMA_LEN ("lql") },
16529   { STRING_COMMA_LEN ("hql") },
16530   { STRING_COMMA_LEN ("lqh") },
16531   { STRING_COMMA_LEN ("hqh") }
16532 };
16533
16534 static void
16535 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16536               int sizeflag ATTRIBUTE_UNUSED)
16537 {
16538   unsigned int pclmul_type;
16539
16540   FETCH_DATA (the_info, codep + 1);
16541   pclmul_type = *codep++ & 0xff;
16542   switch (pclmul_type)
16543     {
16544     case 0x10:
16545       pclmul_type = 2;
16546       break;
16547     case 0x11:
16548       pclmul_type = 3;
16549       break;
16550     default:
16551       break;
16552     }
16553   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16554     {
16555       char suffix [4];
16556       char *p = mnemonicendp - 3;
16557       suffix[0] = p[0];
16558       suffix[1] = p[1];
16559       suffix[2] = p[2];
16560       suffix[3] = '\0';
16561       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16562       mnemonicendp += pclmul_op[pclmul_type].len;
16563     }
16564   else
16565     {
16566       /* We have a reserved extension byte.  Output it directly.  */
16567       scratchbuf[0] = '$';
16568       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16569       oappend_maybe_intel (scratchbuf);
16570       scratchbuf[0] = '\0';
16571     }
16572 }
16573
16574 static void
16575 MOVBE_Fixup (int bytemode, int sizeflag)
16576 {
16577   /* Add proper suffix to "movbe".  */
16578   char *p = mnemonicendp;
16579
16580   switch (bytemode)
16581     {
16582     case v_mode:
16583       if (intel_syntax)
16584         goto skip;
16585
16586       USED_REX (REX_W);
16587       if (sizeflag & SUFFIX_ALWAYS)
16588         {
16589           if (rex & REX_W)
16590             *p++ = 'q';
16591           else
16592             {
16593               if (sizeflag & DFLAG)
16594                 *p++ = 'l';
16595               else
16596                 *p++ = 'w';
16597               used_prefixes |= (prefixes & PREFIX_DATA);
16598             }
16599         }
16600       break;
16601     default:
16602       oappend (INTERNAL_DISASSEMBLER_ERROR);
16603       break;
16604     }
16605   mnemonicendp = p;
16606   *p = '\0';
16607
16608  skip:
16609   OP_M (bytemode, sizeflag);
16610 }
16611
16612 static void
16613 MOVSXD_Fixup (int bytemode, int sizeflag)
16614 {
16615   /* Add proper suffix to "movsxd".  */
16616   char *p = mnemonicendp;
16617
16618   switch (bytemode)
16619     {
16620     case movsxd_mode:
16621       if (intel_syntax)
16622         {
16623           *p++ = 'x';
16624           *p++ = 'd';
16625           goto skip;
16626         }
16627
16628       USED_REX (REX_W);
16629       if (rex & REX_W)
16630         {
16631           *p++ = 'l';
16632           *p++ = 'q';
16633         }
16634       else
16635         {
16636           *p++ = 'x';
16637           *p++ = 'd';
16638         }
16639       break;
16640     default:
16641       oappend (INTERNAL_DISASSEMBLER_ERROR);
16642       break;
16643     }
16644
16645  skip:
16646   mnemonicendp = p;
16647   *p = '\0';
16648   OP_E (bytemode, sizeflag);
16649 }
16650
16651 static void
16652 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16653 {
16654   int reg;
16655   const char **names;
16656
16657   /* Skip mod/rm byte.  */
16658   MODRM_CHECK;
16659   codep++;
16660
16661   if (rex & REX_W)
16662     names = names64;
16663   else
16664     names = names32;
16665
16666   reg = modrm.rm;
16667   USED_REX (REX_B);
16668   if (rex & REX_B)
16669     reg += 8;
16670
16671   oappend (names[reg]);
16672 }
16673
16674 static void
16675 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16676 {
16677   const char **names;
16678   unsigned int reg = vex.register_specifier;
16679   vex.register_specifier = 0;
16680
16681   if (rex & REX_W)
16682     names = names64;
16683   else
16684     names = names32;
16685
16686   if (address_mode != mode_64bit)
16687     reg &= 7;
16688   oappend (names[reg]);
16689 }
16690
16691 static void
16692 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16693 {
16694   if (!vex.evex
16695       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16696     abort ();
16697
16698   USED_REX (REX_R);
16699   if ((rex & REX_R) != 0 || !vex.r)
16700     {
16701       BadOp ();
16702       return;
16703     }
16704
16705   oappend (names_mask [modrm.reg]);
16706 }
16707
16708 static void
16709 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16710 {
16711   if (!vex.evex
16712       || (bytemode != evex_rounding_mode
16713           && bytemode != evex_rounding_64_mode
16714           && bytemode != evex_sae_mode))
16715     abort ();
16716   if (modrm.mod == 3 && vex.b)
16717     switch (bytemode)
16718       {
16719       case evex_rounding_64_mode:
16720         if (address_mode != mode_64bit)
16721           {
16722             oappend ("(bad)");
16723             break;
16724           }
16725         /* Fall through.  */
16726       case evex_rounding_mode:
16727         oappend (names_rounding[vex.ll]);
16728         break;
16729       case evex_sae_mode:
16730         oappend ("{sae}");
16731         break;
16732       default:
16733         break;
16734       }
16735 }