opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_EX_Vex (int, int);
  92 static void OP_EX_VexW (int, int);
  93 static void OP_EX_VexImmW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_Rounding (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void SEP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128 static void MOVSXD_Fixup (int, int);
 129
 130 static void OP_Mask (int, int);
 131
 132 struct dis_private {
 133   /* Points to first byte not fetched.  */
 134   bfd_byte *max_fetched;
 135   bfd_byte the_buffer[MAX_MNEM_SIZE];
 136   bfd_vma insn_start;
 137   int orig_sizeflag;
 138   OPCODES_SIGJMP_BUF bailout;
 139 };
 140
 141 enum address_mode
 142 {
 143   mode_16bit,
 144   mode_32bit,
 145   mode_64bit
 146 };
 147
 148 enum address_mode address_mode;
 149
 150 /* Flags for the prefixes for the current instruction.  See below.  */
 151 static int prefixes;
 152
 153 /* REX prefix the current instruction.  See below.  */
 154 static int rex;
 155 /* Bits of REX we've already used.  */
 156 static int rex_used;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Jdqw { OP_J, dqw_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmmdw { OP_EX, xmmdw_mode }
 401 #define EXxmmqd { OP_EX, xmmqd_mode }
 402 #define EXymmq { OP_EX, ymmq_mode }
 403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 406 #define MS { OP_MS, v_mode }
 407 #define XS { OP_XS, v_mode }
 408 #define EMCq { OP_EMC, q_mode }
 409 #define MXC { OP_MXC, 0 }
 410 #define OPSUF { OP_3DNowSuffix, 0 }
 411 #define SEP { SEP_Fixup, 0 }
 412 #define CMP { CMP_Fixup, 0 }
 413 #define XMM0 { XMM_Fixup, 0 }
 414 #define FXSAVE { FXSAVE_Fixup, 0 }
 415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 417
 418 #define Vex { OP_VEX, vex_mode }
 419 #define VexScalar { OP_VEX, vex_scalar_mode }
 420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 421 #define Vex128 { OP_VEX, vex128_mode }
 422 #define Vex256 { OP_VEX, vex256_mode }
 423 #define VexGdq { OP_VEX, dq_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 426 #define EXVexW { OP_EX_VexW, x_mode }
 427 #define EXdVexW { OP_EX_VexW, d_mode }
 428 #define EXqVexW { OP_EX_VexW, q_mode }
 429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 431 #define XMVexW { OP_XMM_VexW, 0 }
 432 #define XMVexI4 { OP_REG_VexI4, x_mode }
 433 #define PCLMUL { PCLMUL_Fixup, 0 }
 434 #define VCMP { VCMP_Fixup, 0 }
 435 #define VPCMP { VPCMP_Fixup, 0 }
 436 #define VPCOM { VPCOM_Fixup, 0 }
 437
 438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 441
 442 #define XMask { OP_Mask, mask_mode }
 443 #define MaskG { OP_G, mask_mode }
 444 #define MaskE { OP_E, mask_mode }
 445 #define MaskBDE { OP_E, mask_bd_mode }
 446 #define MaskR { OP_R, mask_mode }
 447 #define MaskVex { OP_VEX, mask_mode }
 448
 449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 453
 454 /* Used handle "rep" prefix for string instructions.  */
 455 #define Xbr { REP_Fixup, eSI_reg }
 456 #define Xvr { REP_Fixup, eSI_reg }
 457 #define Ybr { REP_Fixup, eDI_reg }
 458 #define Yvr { REP_Fixup, eDI_reg }
 459 #define Yzr { REP_Fixup, eDI_reg }
 460 #define indirDXr { REP_Fixup, indir_dx_reg }
 461 #define ALr { REP_Fixup, al_reg }
 462 #define eAXr { REP_Fixup, eAX_reg }
 463
 464 /* Used handle HLE prefix for lockable instructions.  */
 465 #define Ebh1 { HLE_Fixup1, b_mode }
 466 #define Evh1 { HLE_Fixup1, v_mode }
 467 #define Ebh2 { HLE_Fixup2, b_mode }
 468 #define Evh2 { HLE_Fixup2, v_mode }
 469 #define Ebh3 { HLE_Fixup3, b_mode }
 470 #define Evh3 { HLE_Fixup3, v_mode }
 471
 472 #define BND { BND_Fixup, 0 }
 473 #define NOTRACK { NOTRACK_Fixup, 0 }
 474
 475 #define cond_jump_flag { NULL, cond_jump_mode }
 476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 477
 478 /* bits in sizeflag */
 479 #define SUFFIX_ALWAYS 4
 480 #define AFLAG 2
 481 #define DFLAG 1
 482
 483 enum
 484 {
 485   /* byte operand */
 486   b_mode = 1,
 487   /* byte operand with operand swapped */
 488   b_swap_mode,
 489   /* byte operand, sign extend like 'T' suffix */
 490   b_T_mode,
 491   /* operand size depends on prefixes */
 492   v_mode,
 493   /* operand size depends on prefixes with operand swapped */
 494   v_swap_mode,
 495   /* operand size depends on address prefix */
 496   va_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* 16-byte XMM, word, double word or quad word operand.  */
 536   xmmdw_mode,
 537   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 538   xmmqd_mode,
 539   /* 32-byte YMM operand */
 540   ymm_mode,
 541   /* quad word, ymmword or zmmword memory operand.  */
 542   ymmq_mode,
 543   /* 32-byte YMM or 16-byte word operand */
 544   ymmxmm_mode,
 545   /* d_mode in 32bit, q_mode in 64bit mode.  */
 546   m_mode,
 547   /* pair of v_mode operands */
 548   a_mode,
 549   cond_jump_mode,
 550   loop_jcxz_mode,
 551   movsxd_mode,
 552   v_bnd_mode,
 553   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 554   v_bndmk_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode, displacements like
 558      v_mode without considering Intel64 ISA.  */
 559   dqw_mode,
 560   /* bounds operand */
 561   bnd_mode,
 562   /* bounds operand with operand swapped */
 563   bnd_swap_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589
 590   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 591   vex_vsib_d_w_dq_mode,
 592   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 593   vex_vsib_d_w_d_mode,
 594   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 595   vex_vsib_q_w_dq_mode,
 596   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 597   vex_vsib_q_w_d_mode,
 598
 599   /* scalar, ignore vector length.  */
 600   scalar_mode,
 601   /* like b_mode, ignore vector length.  */
 602   b_scalar_mode,
 603   /* like w_mode, ignore vector length.  */
 604   w_scalar_mode,
 605   /* like d_swap_mode, ignore vector length.  */
 606   d_scalar_swap_mode,
 607   /* like q_swap_mode, ignore vector length.  */
 608   q_scalar_swap_mode,
 609   /* like vex_mode, ignore vector length.  */
 610   vex_scalar_mode,
 611   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 612   vex_scalar_w_dq_mode,
 613
 614   /* Static rounding.  */
 615   evex_rounding_mode,
 616   /* Static rounding, 64-bit mode only.  */
 617   evex_rounding_64_mode,
 618   /* Supress all exceptions.  */
 619   evex_sae_mode,
 620
 621   /* Mask register operand.  */
 622   mask_mode,
 623   /* Mask register operand.  */
 624   mask_bd_mode,
 625
 626   es_reg,
 627   cs_reg,
 628   ss_reg,
 629   ds_reg,
 630   fs_reg,
 631   gs_reg,
 632
 633   eAX_reg,
 634   eCX_reg,
 635   eDX_reg,
 636   eBX_reg,
 637   eSP_reg,
 638   eBP_reg,
 639   eSI_reg,
 640   eDI_reg,
 641
 642   al_reg,
 643   cl_reg,
 644   dl_reg,
 645   bl_reg,
 646   ah_reg,
 647   ch_reg,
 648   dh_reg,
 649   bh_reg,
 650
 651   ax_reg,
 652   cx_reg,
 653   dx_reg,
 654   bx_reg,
 655   sp_reg,
 656   bp_reg,
 657   si_reg,
 658   di_reg,
 659
 660   rAX_reg,
 661   rCX_reg,
 662   rDX_reg,
 663   rBX_reg,
 664   rSP_reg,
 665   rBP_reg,
 666   rSI_reg,
 667   rDI_reg,
 668
 669   z_mode_ax_reg,
 670   indir_dx_reg
 671 };
 672
 673 enum
 674 {
 675   FLOATCODE = 1,
 676   USE_REG_TABLE,
 677   USE_MOD_TABLE,
 678   USE_RM_TABLE,
 679   USE_PREFIX_TABLE,
 680   USE_X86_64_TABLE,
 681   USE_3BYTE_TABLE,
 682   USE_XOP_8F_TABLE,
 683   USE_VEX_C4_TABLE,
 684   USE_VEX_C5_TABLE,
 685   USE_VEX_LEN_TABLE,
 686   USE_VEX_W_TABLE,
 687   USE_EVEX_TABLE,
 688   USE_EVEX_LEN_TABLE
 689 };
 690
 691 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 692
 693 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 694 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 695 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 696 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 697 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 698 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 699 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 700 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 701 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 702 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 703 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 704 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 705 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 706 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 707 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 708 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 709
 710 enum
 711 {
 712   REG_80 = 0,
 713   REG_81,
 714   REG_83,
 715   REG_8F,
 716   REG_C0,
 717   REG_C1,
 718   REG_C6,
 719   REG_C7,
 720   REG_D0,
 721   REG_D1,
 722   REG_D2,
 723   REG_D3,
 724   REG_F6,
 725   REG_F7,
 726   REG_FE,
 727   REG_FF,
 728   REG_0F00,
 729   REG_0F01,
 730   REG_0F0D,
 731   REG_0F18,
 732   REG_0F1C_P_0_MOD_0,
 733   REG_0F1E_P_1_MOD_3,
 734   REG_0F71,
 735   REG_0F72,
 736   REG_0F73,
 737   REG_0FA6,
 738   REG_0FA7,
 739   REG_0FAE,
 740   REG_0FBA,
 741   REG_0FC7,
 742   REG_VEX_0F71,
 743   REG_VEX_0F72,
 744   REG_VEX_0F73,
 745   REG_VEX_0FAE,
 746   REG_VEX_0F38F3,
 747   REG_XOP_LWPCB,
 748   REG_XOP_LWP,
 749   REG_XOP_TBM_01,
 750   REG_XOP_TBM_02,
 751
 752   REG_EVEX_0F71,
 753   REG_EVEX_0F72,
 754   REG_EVEX_0F73,
 755   REG_EVEX_0F38C6,
 756   REG_EVEX_0F38C7
 757 };
 758
 759 enum
 760 {
 761   MOD_8D = 0,
 762   MOD_C6_REG_7,
 763   MOD_C7_REG_7,
 764   MOD_FF_REG_3,
 765   MOD_FF_REG_5,
 766   MOD_0F01_REG_0,
 767   MOD_0F01_REG_1,
 768   MOD_0F01_REG_2,
 769   MOD_0F01_REG_3,
 770   MOD_0F01_REG_5,
 771   MOD_0F01_REG_7,
 772   MOD_0F12_PREFIX_0,
 773   MOD_0F12_PREFIX_2,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F16_PREFIX_2,
 777   MOD_0F17,
 778   MOD_0F18_REG_0,
 779   MOD_0F18_REG_1,
 780   MOD_0F18_REG_2,
 781   MOD_0F18_REG_3,
 782   MOD_0F18_REG_4,
 783   MOD_0F18_REG_5,
 784   MOD_0F18_REG_6,
 785   MOD_0F18_REG_7,
 786   MOD_0F1A_PREFIX_0,
 787   MOD_0F1B_PREFIX_0,
 788   MOD_0F1B_PREFIX_1,
 789   MOD_0F1C_PREFIX_0,
 790   MOD_0F1E_PREFIX_1,
 791   MOD_0F24,
 792   MOD_0F26,
 793   MOD_0F2B_PREFIX_0,
 794   MOD_0F2B_PREFIX_1,
 795   MOD_0F2B_PREFIX_2,
 796   MOD_0F2B_PREFIX_3,
 797   MOD_0F50,
 798   MOD_0F71_REG_2,
 799   MOD_0F71_REG_4,
 800   MOD_0F71_REG_6,
 801   MOD_0F72_REG_2,
 802   MOD_0F72_REG_4,
 803   MOD_0F72_REG_6,
 804   MOD_0F73_REG_2,
 805   MOD_0F73_REG_3,
 806   MOD_0F73_REG_6,
 807   MOD_0F73_REG_7,
 808   MOD_0FAE_REG_0,
 809   MOD_0FAE_REG_1,
 810   MOD_0FAE_REG_2,
 811   MOD_0FAE_REG_3,
 812   MOD_0FAE_REG_4,
 813   MOD_0FAE_REG_5,
 814   MOD_0FAE_REG_6,
 815   MOD_0FAE_REG_7,
 816   MOD_0FB2,
 817   MOD_0FB4,
 818   MOD_0FB5,
 819   MOD_0FC3,
 820   MOD_0FC7_REG_3,
 821   MOD_0FC7_REG_4,
 822   MOD_0FC7_REG_5,
 823   MOD_0FC7_REG_6,
 824   MOD_0FC7_REG_7,
 825   MOD_0FD7,
 826   MOD_0FE7_PREFIX_2,
 827   MOD_0FF0_PREFIX_3,
 828   MOD_0F382A_PREFIX_2,
 829   MOD_0F38F5_PREFIX_2,
 830   MOD_0F38F6_PREFIX_0,
 831   MOD_0F38F8_PREFIX_1,
 832   MOD_0F38F8_PREFIX_2,
 833   MOD_0F38F8_PREFIX_3,
 834   MOD_0F38F9_PREFIX_0,
 835   MOD_62_32BIT,
 836   MOD_C4_32BIT,
 837   MOD_C5_32BIT,
 838   MOD_VEX_0F12_PREFIX_0,
 839   MOD_VEX_0F12_PREFIX_2,
 840   MOD_VEX_0F13,
 841   MOD_VEX_0F16_PREFIX_0,
 842   MOD_VEX_0F16_PREFIX_2,
 843   MOD_VEX_0F17,
 844   MOD_VEX_0F2B,
 845   MOD_VEX_W_0_0F41_P_0_LEN_1,
 846   MOD_VEX_W_1_0F41_P_0_LEN_1,
 847   MOD_VEX_W_0_0F41_P_2_LEN_1,
 848   MOD_VEX_W_1_0F41_P_2_LEN_1,
 849   MOD_VEX_W_0_0F42_P_0_LEN_1,
 850   MOD_VEX_W_1_0F42_P_0_LEN_1,
 851   MOD_VEX_W_0_0F42_P_2_LEN_1,
 852   MOD_VEX_W_1_0F42_P_2_LEN_1,
 853   MOD_VEX_W_0_0F44_P_0_LEN_1,
 854   MOD_VEX_W_1_0F44_P_0_LEN_1,
 855   MOD_VEX_W_0_0F44_P_2_LEN_1,
 856   MOD_VEX_W_1_0F44_P_2_LEN_1,
 857   MOD_VEX_W_0_0F45_P_0_LEN_1,
 858   MOD_VEX_W_1_0F45_P_0_LEN_1,
 859   MOD_VEX_W_0_0F45_P_2_LEN_1,
 860   MOD_VEX_W_1_0F45_P_2_LEN_1,
 861   MOD_VEX_W_0_0F46_P_0_LEN_1,
 862   MOD_VEX_W_1_0F46_P_0_LEN_1,
 863   MOD_VEX_W_0_0F46_P_2_LEN_1,
 864   MOD_VEX_W_1_0F46_P_2_LEN_1,
 865   MOD_VEX_W_0_0F47_P_0_LEN_1,
 866   MOD_VEX_W_1_0F47_P_0_LEN_1,
 867   MOD_VEX_W_0_0F47_P_2_LEN_1,
 868   MOD_VEX_W_1_0F47_P_2_LEN_1,
 869   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 870   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 871   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 872   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 873   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 874   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 875   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 876   MOD_VEX_0F50,
 877   MOD_VEX_0F71_REG_2,
 878   MOD_VEX_0F71_REG_4,
 879   MOD_VEX_0F71_REG_6,
 880   MOD_VEX_0F72_REG_2,
 881   MOD_VEX_0F72_REG_4,
 882   MOD_VEX_0F72_REG_6,
 883   MOD_VEX_0F73_REG_2,
 884   MOD_VEX_0F73_REG_3,
 885   MOD_VEX_0F73_REG_6,
 886   MOD_VEX_0F73_REG_7,
 887   MOD_VEX_W_0_0F91_P_0_LEN_0,
 888   MOD_VEX_W_1_0F91_P_0_LEN_0,
 889   MOD_VEX_W_0_0F91_P_2_LEN_0,
 890   MOD_VEX_W_1_0F91_P_2_LEN_0,
 891   MOD_VEX_W_0_0F92_P_0_LEN_0,
 892   MOD_VEX_W_0_0F92_P_2_LEN_0,
 893   MOD_VEX_0F92_P_3_LEN_0,
 894   MOD_VEX_W_0_0F93_P_0_LEN_0,
 895   MOD_VEX_W_0_0F93_P_2_LEN_0,
 896   MOD_VEX_0F93_P_3_LEN_0,
 897   MOD_VEX_W_0_0F98_P_0_LEN_0,
 898   MOD_VEX_W_1_0F98_P_0_LEN_0,
 899   MOD_VEX_W_0_0F98_P_2_LEN_0,
 900   MOD_VEX_W_1_0F98_P_2_LEN_0,
 901   MOD_VEX_W_0_0F99_P_0_LEN_0,
 902   MOD_VEX_W_1_0F99_P_0_LEN_0,
 903   MOD_VEX_W_0_0F99_P_2_LEN_0,
 904   MOD_VEX_W_1_0F99_P_2_LEN_0,
 905   MOD_VEX_0FAE_REG_2,
 906   MOD_VEX_0FAE_REG_3,
 907   MOD_VEX_0FD7_PREFIX_2,
 908   MOD_VEX_0FE7_PREFIX_2,
 909   MOD_VEX_0FF0_PREFIX_3,
 910   MOD_VEX_0F381A_PREFIX_2,
 911   MOD_VEX_0F382A_PREFIX_2,
 912   MOD_VEX_0F382C_PREFIX_2,
 913   MOD_VEX_0F382D_PREFIX_2,
 914   MOD_VEX_0F382E_PREFIX_2,
 915   MOD_VEX_0F382F_PREFIX_2,
 916   MOD_VEX_0F385A_PREFIX_2,
 917   MOD_VEX_0F388C_PREFIX_2,
 918   MOD_VEX_0F388E_PREFIX_2,
 919   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 923   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 925   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 927
 928   MOD_EVEX_0F12_PREFIX_0,
 929   MOD_EVEX_0F12_PREFIX_2,
 930   MOD_EVEX_0F13,
 931   MOD_EVEX_0F16_PREFIX_0,
 932   MOD_EVEX_0F16_PREFIX_2,
 933   MOD_EVEX_0F17,
 934   MOD_EVEX_0F2B,
 935   MOD_EVEX_0F381A_P_2_W_0,
 936   MOD_EVEX_0F381A_P_2_W_1,
 937   MOD_EVEX_0F381B_P_2_W_0,
 938   MOD_EVEX_0F381B_P_2_W_1,
 939   MOD_EVEX_0F385A_P_2_W_0,
 940   MOD_EVEX_0F385A_P_2_W_1,
 941   MOD_EVEX_0F385B_P_2_W_0,
 942   MOD_EVEX_0F385B_P_2_W_1,
 943   MOD_EVEX_0F38C6_REG_1,
 944   MOD_EVEX_0F38C6_REG_2,
 945   MOD_EVEX_0F38C6_REG_5,
 946   MOD_EVEX_0F38C6_REG_6,
 947   MOD_EVEX_0F38C7_REG_1,
 948   MOD_EVEX_0F38C7_REG_2,
 949   MOD_EVEX_0F38C7_REG_5,
 950   MOD_EVEX_0F38C7_REG_6
 951 };
 952
 953 enum
 954 {
 955   RM_C6_REG_7 = 0,
 956   RM_C7_REG_7,
 957   RM_0F01_REG_0,
 958   RM_0F01_REG_1,
 959   RM_0F01_REG_2,
 960   RM_0F01_REG_3,
 961   RM_0F01_REG_5_MOD_3,
 962   RM_0F01_REG_7_MOD_3,
 963   RM_0F1E_P_1_MOD_3_REG_7,
 964   RM_0FAE_REG_6_MOD_3_P_0,
 965   RM_0FAE_REG_7_MOD_3,
 966 };
 967
 968 enum
 969 {
 970   PREFIX_90 = 0,
 971   PREFIX_0F01_REG_3_RM_1,
 972   PREFIX_0F01_REG_5_MOD_0,
 973   PREFIX_0F01_REG_5_MOD_3_RM_0,
 974   PREFIX_0F01_REG_5_MOD_3_RM_1,
 975   PREFIX_0F01_REG_5_MOD_3_RM_2,
 976   PREFIX_0F01_REG_7_MOD_3_RM_2,
 977   PREFIX_0F01_REG_7_MOD_3_RM_3,
 978   PREFIX_0F09,
 979   PREFIX_0F10,
 980   PREFIX_0F11,
 981   PREFIX_0F12,
 982   PREFIX_0F16,
 983   PREFIX_0F1A,
 984   PREFIX_0F1B,
 985   PREFIX_0F1C,
 986   PREFIX_0F1E,
 987   PREFIX_0F2A,
 988   PREFIX_0F2B,
 989   PREFIX_0F2C,
 990   PREFIX_0F2D,
 991   PREFIX_0F2E,
 992   PREFIX_0F2F,
 993   PREFIX_0F51,
 994   PREFIX_0F52,
 995   PREFIX_0F53,
 996   PREFIX_0F58,
 997   PREFIX_0F59,
 998   PREFIX_0F5A,
 999   PREFIX_0F5B,
1000   PREFIX_0F5C,
1001   PREFIX_0F5D,
1002   PREFIX_0F5E,
1003   PREFIX_0F5F,
1004   PREFIX_0F60,
1005   PREFIX_0F61,
1006   PREFIX_0F62,
1007   PREFIX_0F6C,
1008   PREFIX_0F6D,
1009   PREFIX_0F6F,
1010   PREFIX_0F70,
1011   PREFIX_0F73_REG_3,
1012   PREFIX_0F73_REG_7,
1013   PREFIX_0F78,
1014   PREFIX_0F79,
1015   PREFIX_0F7C,
1016   PREFIX_0F7D,
1017   PREFIX_0F7E,
1018   PREFIX_0F7F,
1019   PREFIX_0FAE_REG_0_MOD_3,
1020   PREFIX_0FAE_REG_1_MOD_3,
1021   PREFIX_0FAE_REG_2_MOD_3,
1022   PREFIX_0FAE_REG_3_MOD_3,
1023   PREFIX_0FAE_REG_4_MOD_0,
1024   PREFIX_0FAE_REG_4_MOD_3,
1025   PREFIX_0FAE_REG_5_MOD_0,
1026   PREFIX_0FAE_REG_5_MOD_3,
1027   PREFIX_0FAE_REG_6_MOD_0,
1028   PREFIX_0FAE_REG_6_MOD_3,
1029   PREFIX_0FAE_REG_7_MOD_0,
1030   PREFIX_0FB8,
1031   PREFIX_0FBC,
1032   PREFIX_0FBD,
1033   PREFIX_0FC2,
1034   PREFIX_0FC3_MOD_0,
1035   PREFIX_0FC7_REG_6_MOD_0,
1036   PREFIX_0FC7_REG_6_MOD_3,
1037   PREFIX_0FC7_REG_7_MOD_3,
1038   PREFIX_0FD0,
1039   PREFIX_0FD6,
1040   PREFIX_0FE6,
1041   PREFIX_0FE7,
1042   PREFIX_0FF0,
1043   PREFIX_0FF7,
1044   PREFIX_0F3810,
1045   PREFIX_0F3814,
1046   PREFIX_0F3815,
1047   PREFIX_0F3817,
1048   PREFIX_0F3820,
1049   PREFIX_0F3821,
1050   PREFIX_0F3822,
1051   PREFIX_0F3823,
1052   PREFIX_0F3824,
1053   PREFIX_0F3825,
1054   PREFIX_0F3828,
1055   PREFIX_0F3829,
1056   PREFIX_0F382A,
1057   PREFIX_0F382B,
1058   PREFIX_0F3830,
1059   PREFIX_0F3831,
1060   PREFIX_0F3832,
1061   PREFIX_0F3833,
1062   PREFIX_0F3834,
1063   PREFIX_0F3835,
1064   PREFIX_0F3837,
1065   PREFIX_0F3838,
1066   PREFIX_0F3839,
1067   PREFIX_0F383A,
1068   PREFIX_0F383B,
1069   PREFIX_0F383C,
1070   PREFIX_0F383D,
1071   PREFIX_0F383E,
1072   PREFIX_0F383F,
1073   PREFIX_0F3840,
1074   PREFIX_0F3841,
1075   PREFIX_0F3880,
1076   PREFIX_0F3881,
1077   PREFIX_0F3882,
1078   PREFIX_0F38C8,
1079   PREFIX_0F38C9,
1080   PREFIX_0F38CA,
1081   PREFIX_0F38CB,
1082   PREFIX_0F38CC,
1083   PREFIX_0F38CD,
1084   PREFIX_0F38CF,
1085   PREFIX_0F38DB,
1086   PREFIX_0F38DC,
1087   PREFIX_0F38DD,
1088   PREFIX_0F38DE,
1089   PREFIX_0F38DF,
1090   PREFIX_0F38F0,
1091   PREFIX_0F38F1,
1092   PREFIX_0F38F5,
1093   PREFIX_0F38F6,
1094   PREFIX_0F38F8,
1095   PREFIX_0F38F9,
1096   PREFIX_0F3A08,
1097   PREFIX_0F3A09,
1098   PREFIX_0F3A0A,
1099   PREFIX_0F3A0B,
1100   PREFIX_0F3A0C,
1101   PREFIX_0F3A0D,
1102   PREFIX_0F3A0E,
1103   PREFIX_0F3A14,
1104   PREFIX_0F3A15,
1105   PREFIX_0F3A16,
1106   PREFIX_0F3A17,
1107   PREFIX_0F3A20,
1108   PREFIX_0F3A21,
1109   PREFIX_0F3A22,
1110   PREFIX_0F3A40,
1111   PREFIX_0F3A41,
1112   PREFIX_0F3A42,
1113   PREFIX_0F3A44,
1114   PREFIX_0F3A60,
1115   PREFIX_0F3A61,
1116   PREFIX_0F3A62,
1117   PREFIX_0F3A63,
1118   PREFIX_0F3ACC,
1119   PREFIX_0F3ACE,
1120   PREFIX_0F3ACF,
1121   PREFIX_0F3ADF,
1122   PREFIX_VEX_0F10,
1123   PREFIX_VEX_0F11,
1124   PREFIX_VEX_0F12,
1125   PREFIX_VEX_0F16,
1126   PREFIX_VEX_0F2A,
1127   PREFIX_VEX_0F2C,
1128   PREFIX_VEX_0F2D,
1129   PREFIX_VEX_0F2E,
1130   PREFIX_VEX_0F2F,
1131   PREFIX_VEX_0F41,
1132   PREFIX_VEX_0F42,
1133   PREFIX_VEX_0F44,
1134   PREFIX_VEX_0F45,
1135   PREFIX_VEX_0F46,
1136   PREFIX_VEX_0F47,
1137   PREFIX_VEX_0F4A,
1138   PREFIX_VEX_0F4B,
1139   PREFIX_VEX_0F51,
1140   PREFIX_VEX_0F52,
1141   PREFIX_VEX_0F53,
1142   PREFIX_VEX_0F58,
1143   PREFIX_VEX_0F59,
1144   PREFIX_VEX_0F5A,
1145   PREFIX_VEX_0F5B,
1146   PREFIX_VEX_0F5C,
1147   PREFIX_VEX_0F5D,
1148   PREFIX_VEX_0F5E,
1149   PREFIX_VEX_0F5F,
1150   PREFIX_VEX_0F60,
1151   PREFIX_VEX_0F61,
1152   PREFIX_VEX_0F62,
1153   PREFIX_VEX_0F63,
1154   PREFIX_VEX_0F64,
1155   PREFIX_VEX_0F65,
1156   PREFIX_VEX_0F66,
1157   PREFIX_VEX_0F67,
1158   PREFIX_VEX_0F68,
1159   PREFIX_VEX_0F69,
1160   PREFIX_VEX_0F6A,
1161   PREFIX_VEX_0F6B,
1162   PREFIX_VEX_0F6C,
1163   PREFIX_VEX_0F6D,
1164   PREFIX_VEX_0F6E,
1165   PREFIX_VEX_0F6F,
1166   PREFIX_VEX_0F70,
1167   PREFIX_VEX_0F71_REG_2,
1168   PREFIX_VEX_0F71_REG_4,
1169   PREFIX_VEX_0F71_REG_6,
1170   PREFIX_VEX_0F72_REG_2,
1171   PREFIX_VEX_0F72_REG_4,
1172   PREFIX_VEX_0F72_REG_6,
1173   PREFIX_VEX_0F73_REG_2,
1174   PREFIX_VEX_0F73_REG_3,
1175   PREFIX_VEX_0F73_REG_6,
1176   PREFIX_VEX_0F73_REG_7,
1177   PREFIX_VEX_0F74,
1178   PREFIX_VEX_0F75,
1179   PREFIX_VEX_0F76,
1180   PREFIX_VEX_0F77,
1181   PREFIX_VEX_0F7C,
1182   PREFIX_VEX_0F7D,
1183   PREFIX_VEX_0F7E,
1184   PREFIX_VEX_0F7F,
1185   PREFIX_VEX_0F90,
1186   PREFIX_VEX_0F91,
1187   PREFIX_VEX_0F92,
1188   PREFIX_VEX_0F93,
1189   PREFIX_VEX_0F98,
1190   PREFIX_VEX_0F99,
1191   PREFIX_VEX_0FC2,
1192   PREFIX_VEX_0FC4,
1193   PREFIX_VEX_0FC5,
1194   PREFIX_VEX_0FD0,
1195   PREFIX_VEX_0FD1,
1196   PREFIX_VEX_0FD2,
1197   PREFIX_VEX_0FD3,
1198   PREFIX_VEX_0FD4,
1199   PREFIX_VEX_0FD5,
1200   PREFIX_VEX_0FD6,
1201   PREFIX_VEX_0FD7,
1202   PREFIX_VEX_0FD8,
1203   PREFIX_VEX_0FD9,
1204   PREFIX_VEX_0FDA,
1205   PREFIX_VEX_0FDB,
1206   PREFIX_VEX_0FDC,
1207   PREFIX_VEX_0FDD,
1208   PREFIX_VEX_0FDE,
1209   PREFIX_VEX_0FDF,
1210   PREFIX_VEX_0FE0,
1211   PREFIX_VEX_0FE1,
1212   PREFIX_VEX_0FE2,
1213   PREFIX_VEX_0FE3,
1214   PREFIX_VEX_0FE4,
1215   PREFIX_VEX_0FE5,
1216   PREFIX_VEX_0FE6,
1217   PREFIX_VEX_0FE7,
1218   PREFIX_VEX_0FE8,
1219   PREFIX_VEX_0FE9,
1220   PREFIX_VEX_0FEA,
1221   PREFIX_VEX_0FEB,
1222   PREFIX_VEX_0FEC,
1223   PREFIX_VEX_0FED,
1224   PREFIX_VEX_0FEE,
1225   PREFIX_VEX_0FEF,
1226   PREFIX_VEX_0FF0,
1227   PREFIX_VEX_0FF1,
1228   PREFIX_VEX_0FF2,
1229   PREFIX_VEX_0FF3,
1230   PREFIX_VEX_0FF4,
1231   PREFIX_VEX_0FF5,
1232   PREFIX_VEX_0FF6,
1233   PREFIX_VEX_0FF7,
1234   PREFIX_VEX_0FF8,
1235   PREFIX_VEX_0FF9,
1236   PREFIX_VEX_0FFA,
1237   PREFIX_VEX_0FFB,
1238   PREFIX_VEX_0FFC,
1239   PREFIX_VEX_0FFD,
1240   PREFIX_VEX_0FFE,
1241   PREFIX_VEX_0F3800,
1242   PREFIX_VEX_0F3801,
1243   PREFIX_VEX_0F3802,
1244   PREFIX_VEX_0F3803,
1245   PREFIX_VEX_0F3804,
1246   PREFIX_VEX_0F3805,
1247   PREFIX_VEX_0F3806,
1248   PREFIX_VEX_0F3807,
1249   PREFIX_VEX_0F3808,
1250   PREFIX_VEX_0F3809,
1251   PREFIX_VEX_0F380A,
1252   PREFIX_VEX_0F380B,
1253   PREFIX_VEX_0F380C,
1254   PREFIX_VEX_0F380D,
1255   PREFIX_VEX_0F380E,
1256   PREFIX_VEX_0F380F,
1257   PREFIX_VEX_0F3813,
1258   PREFIX_VEX_0F3816,
1259   PREFIX_VEX_0F3817,
1260   PREFIX_VEX_0F3818,
1261   PREFIX_VEX_0F3819,
1262   PREFIX_VEX_0F381A,
1263   PREFIX_VEX_0F381C,
1264   PREFIX_VEX_0F381D,
1265   PREFIX_VEX_0F381E,
1266   PREFIX_VEX_0F3820,
1267   PREFIX_VEX_0F3821,
1268   PREFIX_VEX_0F3822,
1269   PREFIX_VEX_0F3823,
1270   PREFIX_VEX_0F3824,
1271   PREFIX_VEX_0F3825,
1272   PREFIX_VEX_0F3828,
1273   PREFIX_VEX_0F3829,
1274   PREFIX_VEX_0F382A,
1275   PREFIX_VEX_0F382B,
1276   PREFIX_VEX_0F382C,
1277   PREFIX_VEX_0F382D,
1278   PREFIX_VEX_0F382E,
1279   PREFIX_VEX_0F382F,
1280   PREFIX_VEX_0F3830,
1281   PREFIX_VEX_0F3831,
1282   PREFIX_VEX_0F3832,
1283   PREFIX_VEX_0F3833,
1284   PREFIX_VEX_0F3834,
1285   PREFIX_VEX_0F3835,
1286   PREFIX_VEX_0F3836,
1287   PREFIX_VEX_0F3837,
1288   PREFIX_VEX_0F3838,
1289   PREFIX_VEX_0F3839,
1290   PREFIX_VEX_0F383A,
1291   PREFIX_VEX_0F383B,
1292   PREFIX_VEX_0F383C,
1293   PREFIX_VEX_0F383D,
1294   PREFIX_VEX_0F383E,
1295   PREFIX_VEX_0F383F,
1296   PREFIX_VEX_0F3840,
1297   PREFIX_VEX_0F3841,
1298   PREFIX_VEX_0F3845,
1299   PREFIX_VEX_0F3846,
1300   PREFIX_VEX_0F3847,
1301   PREFIX_VEX_0F3858,
1302   PREFIX_VEX_0F3859,
1303   PREFIX_VEX_0F385A,
1304   PREFIX_VEX_0F3878,
1305   PREFIX_VEX_0F3879,
1306   PREFIX_VEX_0F388C,
1307   PREFIX_VEX_0F388E,
1308   PREFIX_VEX_0F3890,
1309   PREFIX_VEX_0F3891,
1310   PREFIX_VEX_0F3892,
1311   PREFIX_VEX_0F3893,
1312   PREFIX_VEX_0F3896,
1313   PREFIX_VEX_0F3897,
1314   PREFIX_VEX_0F3898,
1315   PREFIX_VEX_0F3899,
1316   PREFIX_VEX_0F389A,
1317   PREFIX_VEX_0F389B,
1318   PREFIX_VEX_0F389C,
1319   PREFIX_VEX_0F389D,
1320   PREFIX_VEX_0F389E,
1321   PREFIX_VEX_0F389F,
1322   PREFIX_VEX_0F38A6,
1323   PREFIX_VEX_0F38A7,
1324   PREFIX_VEX_0F38A8,
1325   PREFIX_VEX_0F38A9,
1326   PREFIX_VEX_0F38AA,
1327   PREFIX_VEX_0F38AB,
1328   PREFIX_VEX_0F38AC,
1329   PREFIX_VEX_0F38AD,
1330   PREFIX_VEX_0F38AE,
1331   PREFIX_VEX_0F38AF,
1332   PREFIX_VEX_0F38B6,
1333   PREFIX_VEX_0F38B7,
1334   PREFIX_VEX_0F38B8,
1335   PREFIX_VEX_0F38B9,
1336   PREFIX_VEX_0F38BA,
1337   PREFIX_VEX_0F38BB,
1338   PREFIX_VEX_0F38BC,
1339   PREFIX_VEX_0F38BD,
1340   PREFIX_VEX_0F38BE,
1341   PREFIX_VEX_0F38BF,
1342   PREFIX_VEX_0F38CF,
1343   PREFIX_VEX_0F38DB,
1344   PREFIX_VEX_0F38DC,
1345   PREFIX_VEX_0F38DD,
1346   PREFIX_VEX_0F38DE,
1347   PREFIX_VEX_0F38DF,
1348   PREFIX_VEX_0F38F2,
1349   PREFIX_VEX_0F38F3_REG_1,
1350   PREFIX_VEX_0F38F3_REG_2,
1351   PREFIX_VEX_0F38F3_REG_3,
1352   PREFIX_VEX_0F38F5,
1353   PREFIX_VEX_0F38F6,
1354   PREFIX_VEX_0F38F7,
1355   PREFIX_VEX_0F3A00,
1356   PREFIX_VEX_0F3A01,
1357   PREFIX_VEX_0F3A02,
1358   PREFIX_VEX_0F3A04,
1359   PREFIX_VEX_0F3A05,
1360   PREFIX_VEX_0F3A06,
1361   PREFIX_VEX_0F3A08,
1362   PREFIX_VEX_0F3A09,
1363   PREFIX_VEX_0F3A0A,
1364   PREFIX_VEX_0F3A0B,
1365   PREFIX_VEX_0F3A0C,
1366   PREFIX_VEX_0F3A0D,
1367   PREFIX_VEX_0F3A0E,
1368   PREFIX_VEX_0F3A0F,
1369   PREFIX_VEX_0F3A14,
1370   PREFIX_VEX_0F3A15,
1371   PREFIX_VEX_0F3A16,
1372   PREFIX_VEX_0F3A17,
1373   PREFIX_VEX_0F3A18,
1374   PREFIX_VEX_0F3A19,
1375   PREFIX_VEX_0F3A1D,
1376   PREFIX_VEX_0F3A20,
1377   PREFIX_VEX_0F3A21,
1378   PREFIX_VEX_0F3A22,
1379   PREFIX_VEX_0F3A30,
1380   PREFIX_VEX_0F3A31,
1381   PREFIX_VEX_0F3A32,
1382   PREFIX_VEX_0F3A33,
1383   PREFIX_VEX_0F3A38,
1384   PREFIX_VEX_0F3A39,
1385   PREFIX_VEX_0F3A40,
1386   PREFIX_VEX_0F3A41,
1387   PREFIX_VEX_0F3A42,
1388   PREFIX_VEX_0F3A44,
1389   PREFIX_VEX_0F3A46,
1390   PREFIX_VEX_0F3A48,
1391   PREFIX_VEX_0F3A49,
1392   PREFIX_VEX_0F3A4A,
1393   PREFIX_VEX_0F3A4B,
1394   PREFIX_VEX_0F3A4C,
1395   PREFIX_VEX_0F3A5C,
1396   PREFIX_VEX_0F3A5D,
1397   PREFIX_VEX_0F3A5E,
1398   PREFIX_VEX_0F3A5F,
1399   PREFIX_VEX_0F3A60,
1400   PREFIX_VEX_0F3A61,
1401   PREFIX_VEX_0F3A62,
1402   PREFIX_VEX_0F3A63,
1403   PREFIX_VEX_0F3A68,
1404   PREFIX_VEX_0F3A69,
1405   PREFIX_VEX_0F3A6A,
1406   PREFIX_VEX_0F3A6B,
1407   PREFIX_VEX_0F3A6C,
1408   PREFIX_VEX_0F3A6D,
1409   PREFIX_VEX_0F3A6E,
1410   PREFIX_VEX_0F3A6F,
1411   PREFIX_VEX_0F3A78,
1412   PREFIX_VEX_0F3A79,
1413   PREFIX_VEX_0F3A7A,
1414   PREFIX_VEX_0F3A7B,
1415   PREFIX_VEX_0F3A7C,
1416   PREFIX_VEX_0F3A7D,
1417   PREFIX_VEX_0F3A7E,
1418   PREFIX_VEX_0F3A7F,
1419   PREFIX_VEX_0F3ACE,
1420   PREFIX_VEX_0F3ACF,
1421   PREFIX_VEX_0F3ADF,
1422   PREFIX_VEX_0F3AF0,
1423
1424   PREFIX_EVEX_0F10,
1425   PREFIX_EVEX_0F11,
1426   PREFIX_EVEX_0F12,
1427   PREFIX_EVEX_0F16,
1428   PREFIX_EVEX_0F2A,
1429   PREFIX_EVEX_0F2C,
1430   PREFIX_EVEX_0F2D,
1431   PREFIX_EVEX_0F2E,
1432   PREFIX_EVEX_0F2F,
1433   PREFIX_EVEX_0F51,
1434   PREFIX_EVEX_0F58,
1435   PREFIX_EVEX_0F59,
1436   PREFIX_EVEX_0F5A,
1437   PREFIX_EVEX_0F5B,
1438   PREFIX_EVEX_0F5C,
1439   PREFIX_EVEX_0F5D,
1440   PREFIX_EVEX_0F5E,
1441   PREFIX_EVEX_0F5F,
1442   PREFIX_EVEX_0F64,
1443   PREFIX_EVEX_0F65,
1444   PREFIX_EVEX_0F66,
1445   PREFIX_EVEX_0F6E,
1446   PREFIX_EVEX_0F6F,
1447   PREFIX_EVEX_0F70,
1448   PREFIX_EVEX_0F71_REG_2,
1449   PREFIX_EVEX_0F71_REG_4,
1450   PREFIX_EVEX_0F71_REG_6,
1451   PREFIX_EVEX_0F72_REG_0,
1452   PREFIX_EVEX_0F72_REG_1,
1453   PREFIX_EVEX_0F72_REG_2,
1454   PREFIX_EVEX_0F72_REG_4,
1455   PREFIX_EVEX_0F72_REG_6,
1456   PREFIX_EVEX_0F73_REG_2,
1457   PREFIX_EVEX_0F73_REG_3,
1458   PREFIX_EVEX_0F73_REG_6,
1459   PREFIX_EVEX_0F73_REG_7,
1460   PREFIX_EVEX_0F74,
1461   PREFIX_EVEX_0F75,
1462   PREFIX_EVEX_0F76,
1463   PREFIX_EVEX_0F78,
1464   PREFIX_EVEX_0F79,
1465   PREFIX_EVEX_0F7A,
1466   PREFIX_EVEX_0F7B,
1467   PREFIX_EVEX_0F7E,
1468   PREFIX_EVEX_0F7F,
1469   PREFIX_EVEX_0FC2,
1470   PREFIX_EVEX_0FC4,
1471   PREFIX_EVEX_0FC5,
1472   PREFIX_EVEX_0FD6,
1473   PREFIX_EVEX_0FDB,
1474   PREFIX_EVEX_0FDF,
1475   PREFIX_EVEX_0FE2,
1476   PREFIX_EVEX_0FE6,
1477   PREFIX_EVEX_0FE7,
1478   PREFIX_EVEX_0FEB,
1479   PREFIX_EVEX_0FEF,
1480   PREFIX_EVEX_0F380D,
1481   PREFIX_EVEX_0F3810,
1482   PREFIX_EVEX_0F3811,
1483   PREFIX_EVEX_0F3812,
1484   PREFIX_EVEX_0F3813,
1485   PREFIX_EVEX_0F3814,
1486   PREFIX_EVEX_0F3815,
1487   PREFIX_EVEX_0F3816,
1488   PREFIX_EVEX_0F3819,
1489   PREFIX_EVEX_0F381A,
1490   PREFIX_EVEX_0F381B,
1491   PREFIX_EVEX_0F381E,
1492   PREFIX_EVEX_0F381F,
1493   PREFIX_EVEX_0F3820,
1494   PREFIX_EVEX_0F3821,
1495   PREFIX_EVEX_0F3822,
1496   PREFIX_EVEX_0F3823,
1497   PREFIX_EVEX_0F3824,
1498   PREFIX_EVEX_0F3825,
1499   PREFIX_EVEX_0F3826,
1500   PREFIX_EVEX_0F3827,
1501   PREFIX_EVEX_0F3828,
1502   PREFIX_EVEX_0F3829,
1503   PREFIX_EVEX_0F382A,
1504   PREFIX_EVEX_0F382C,
1505   PREFIX_EVEX_0F382D,
1506   PREFIX_EVEX_0F3830,
1507   PREFIX_EVEX_0F3831,
1508   PREFIX_EVEX_0F3832,
1509   PREFIX_EVEX_0F3833,
1510   PREFIX_EVEX_0F3834,
1511   PREFIX_EVEX_0F3835,
1512   PREFIX_EVEX_0F3836,
1513   PREFIX_EVEX_0F3837,
1514   PREFIX_EVEX_0F3838,
1515   PREFIX_EVEX_0F3839,
1516   PREFIX_EVEX_0F383A,
1517   PREFIX_EVEX_0F383B,
1518   PREFIX_EVEX_0F383D,
1519   PREFIX_EVEX_0F383F,
1520   PREFIX_EVEX_0F3840,
1521   PREFIX_EVEX_0F3842,
1522   PREFIX_EVEX_0F3843,
1523   PREFIX_EVEX_0F3844,
1524   PREFIX_EVEX_0F3845,
1525   PREFIX_EVEX_0F3846,
1526   PREFIX_EVEX_0F3847,
1527   PREFIX_EVEX_0F384C,
1528   PREFIX_EVEX_0F384D,
1529   PREFIX_EVEX_0F384E,
1530   PREFIX_EVEX_0F384F,
1531   PREFIX_EVEX_0F3850,
1532   PREFIX_EVEX_0F3851,
1533   PREFIX_EVEX_0F3852,
1534   PREFIX_EVEX_0F3853,
1535   PREFIX_EVEX_0F3854,
1536   PREFIX_EVEX_0F3855,
1537   PREFIX_EVEX_0F3859,
1538   PREFIX_EVEX_0F385A,
1539   PREFIX_EVEX_0F385B,
1540   PREFIX_EVEX_0F3862,
1541   PREFIX_EVEX_0F3863,
1542   PREFIX_EVEX_0F3864,
1543   PREFIX_EVEX_0F3865,
1544   PREFIX_EVEX_0F3866,
1545   PREFIX_EVEX_0F3868,
1546   PREFIX_EVEX_0F3870,
1547   PREFIX_EVEX_0F3871,
1548   PREFIX_EVEX_0F3872,
1549   PREFIX_EVEX_0F3873,
1550   PREFIX_EVEX_0F3875,
1551   PREFIX_EVEX_0F3876,
1552   PREFIX_EVEX_0F3877,
1553   PREFIX_EVEX_0F387A,
1554   PREFIX_EVEX_0F387B,
1555   PREFIX_EVEX_0F387C,
1556   PREFIX_EVEX_0F387D,
1557   PREFIX_EVEX_0F387E,
1558   PREFIX_EVEX_0F387F,
1559   PREFIX_EVEX_0F3883,
1560   PREFIX_EVEX_0F3888,
1561   PREFIX_EVEX_0F3889,
1562   PREFIX_EVEX_0F388A,
1563   PREFIX_EVEX_0F388B,
1564   PREFIX_EVEX_0F388D,
1565   PREFIX_EVEX_0F388F,
1566   PREFIX_EVEX_0F3890,
1567   PREFIX_EVEX_0F3891,
1568   PREFIX_EVEX_0F3892,
1569   PREFIX_EVEX_0F3893,
1570   PREFIX_EVEX_0F389A,
1571   PREFIX_EVEX_0F389B,
1572   PREFIX_EVEX_0F38A0,
1573   PREFIX_EVEX_0F38A1,
1574   PREFIX_EVEX_0F38A2,
1575   PREFIX_EVEX_0F38A3,
1576   PREFIX_EVEX_0F38AA,
1577   PREFIX_EVEX_0F38AB,
1578   PREFIX_EVEX_0F38B4,
1579   PREFIX_EVEX_0F38B5,
1580   PREFIX_EVEX_0F38C4,
1581   PREFIX_EVEX_0F38C6_REG_1,
1582   PREFIX_EVEX_0F38C6_REG_2,
1583   PREFIX_EVEX_0F38C6_REG_5,
1584   PREFIX_EVEX_0F38C6_REG_6,
1585   PREFIX_EVEX_0F38C7_REG_1,
1586   PREFIX_EVEX_0F38C7_REG_2,
1587   PREFIX_EVEX_0F38C7_REG_5,
1588   PREFIX_EVEX_0F38C7_REG_6,
1589   PREFIX_EVEX_0F38C8,
1590   PREFIX_EVEX_0F38CA,
1591   PREFIX_EVEX_0F38CB,
1592   PREFIX_EVEX_0F38CC,
1593   PREFIX_EVEX_0F38CD,
1594
1595   PREFIX_EVEX_0F3A00,
1596   PREFIX_EVEX_0F3A01,
1597   PREFIX_EVEX_0F3A03,
1598   PREFIX_EVEX_0F3A05,
1599   PREFIX_EVEX_0F3A08,
1600   PREFIX_EVEX_0F3A09,
1601   PREFIX_EVEX_0F3A0A,
1602   PREFIX_EVEX_0F3A0B,
1603   PREFIX_EVEX_0F3A14,
1604   PREFIX_EVEX_0F3A15,
1605   PREFIX_EVEX_0F3A16,
1606   PREFIX_EVEX_0F3A17,
1607   PREFIX_EVEX_0F3A18,
1608   PREFIX_EVEX_0F3A19,
1609   PREFIX_EVEX_0F3A1A,
1610   PREFIX_EVEX_0F3A1B,
1611   PREFIX_EVEX_0F3A1E,
1612   PREFIX_EVEX_0F3A1F,
1613   PREFIX_EVEX_0F3A20,
1614   PREFIX_EVEX_0F3A21,
1615   PREFIX_EVEX_0F3A22,
1616   PREFIX_EVEX_0F3A23,
1617   PREFIX_EVEX_0F3A25,
1618   PREFIX_EVEX_0F3A26,
1619   PREFIX_EVEX_0F3A27,
1620   PREFIX_EVEX_0F3A38,
1621   PREFIX_EVEX_0F3A39,
1622   PREFIX_EVEX_0F3A3A,
1623   PREFIX_EVEX_0F3A3B,
1624   PREFIX_EVEX_0F3A3E,
1625   PREFIX_EVEX_0F3A3F,
1626   PREFIX_EVEX_0F3A42,
1627   PREFIX_EVEX_0F3A43,
1628   PREFIX_EVEX_0F3A50,
1629   PREFIX_EVEX_0F3A51,
1630   PREFIX_EVEX_0F3A54,
1631   PREFIX_EVEX_0F3A55,
1632   PREFIX_EVEX_0F3A56,
1633   PREFIX_EVEX_0F3A57,
1634   PREFIX_EVEX_0F3A66,
1635   PREFIX_EVEX_0F3A67,
1636   PREFIX_EVEX_0F3A70,
1637   PREFIX_EVEX_0F3A71,
1638   PREFIX_EVEX_0F3A72,
1639   PREFIX_EVEX_0F3A73,
1640 };
1641
1642 enum
1643 {
1644   X86_64_06 = 0,
1645   X86_64_07,
1646   X86_64_0E,
1647   X86_64_16,
1648   X86_64_17,
1649   X86_64_1E,
1650   X86_64_1F,
1651   X86_64_27,
1652   X86_64_2F,
1653   X86_64_37,
1654   X86_64_3F,
1655   X86_64_60,
1656   X86_64_61,
1657   X86_64_62,
1658   X86_64_63,
1659   X86_64_6D,
1660   X86_64_6F,
1661   X86_64_82,
1662   X86_64_9A,
1663   X86_64_C2,
1664   X86_64_C3,
1665   X86_64_C4,
1666   X86_64_C5,
1667   X86_64_CE,
1668   X86_64_D4,
1669   X86_64_D5,
1670   X86_64_E8,
1671   X86_64_E9,
1672   X86_64_EA,
1673   X86_64_0F01_REG_0,
1674   X86_64_0F01_REG_1,
1675   X86_64_0F01_REG_2,
1676   X86_64_0F01_REG_3
1677 };
1678
1679 enum
1680 {
1681   THREE_BYTE_0F38 = 0,
1682   THREE_BYTE_0F3A
1683 };
1684
1685 enum
1686 {
1687   XOP_08 = 0,
1688   XOP_09,
1689   XOP_0A
1690 };
1691
1692 enum
1693 {
1694   VEX_0F = 0,
1695   VEX_0F38,
1696   VEX_0F3A
1697 };
1698
1699 enum
1700 {
1701   EVEX_0F = 0,
1702   EVEX_0F38,
1703   EVEX_0F3A
1704 };
1705
1706 enum
1707 {
1708   VEX_LEN_0F12_P_0_M_0 = 0,
1709   VEX_LEN_0F12_P_0_M_1,
1710 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1711   VEX_LEN_0F13_M_0,
1712   VEX_LEN_0F16_P_0_M_0,
1713   VEX_LEN_0F16_P_0_M_1,
1714 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1715   VEX_LEN_0F17_M_0,
1716   VEX_LEN_0F41_P_0,
1717   VEX_LEN_0F41_P_2,
1718   VEX_LEN_0F42_P_0,
1719   VEX_LEN_0F42_P_2,
1720   VEX_LEN_0F44_P_0,
1721   VEX_LEN_0F44_P_2,
1722   VEX_LEN_0F45_P_0,
1723   VEX_LEN_0F45_P_2,
1724   VEX_LEN_0F46_P_0,
1725   VEX_LEN_0F46_P_2,
1726   VEX_LEN_0F47_P_0,
1727   VEX_LEN_0F47_P_2,
1728   VEX_LEN_0F4A_P_0,
1729   VEX_LEN_0F4A_P_2,
1730   VEX_LEN_0F4B_P_0,
1731   VEX_LEN_0F4B_P_2,
1732   VEX_LEN_0F6E_P_2,
1733   VEX_LEN_0F77_P_0,
1734   VEX_LEN_0F7E_P_1,
1735   VEX_LEN_0F7E_P_2,
1736   VEX_LEN_0F90_P_0,
1737   VEX_LEN_0F90_P_2,
1738   VEX_LEN_0F91_P_0,
1739   VEX_LEN_0F91_P_2,
1740   VEX_LEN_0F92_P_0,
1741   VEX_LEN_0F92_P_2,
1742   VEX_LEN_0F92_P_3,
1743   VEX_LEN_0F93_P_0,
1744   VEX_LEN_0F93_P_2,
1745   VEX_LEN_0F93_P_3,
1746   VEX_LEN_0F98_P_0,
1747   VEX_LEN_0F98_P_2,
1748   VEX_LEN_0F99_P_0,
1749   VEX_LEN_0F99_P_2,
1750   VEX_LEN_0FAE_R_2_M_0,
1751   VEX_LEN_0FAE_R_3_M_0,
1752   VEX_LEN_0FC4_P_2,
1753   VEX_LEN_0FC5_P_2,
1754   VEX_LEN_0FD6_P_2,
1755   VEX_LEN_0FF7_P_2,
1756   VEX_LEN_0F3816_P_2,
1757   VEX_LEN_0F3819_P_2,
1758   VEX_LEN_0F381A_P_2_M_0,
1759   VEX_LEN_0F3836_P_2,
1760   VEX_LEN_0F3841_P_2,
1761   VEX_LEN_0F385A_P_2_M_0,
1762   VEX_LEN_0F38DB_P_2,
1763   VEX_LEN_0F38F2_P_0,
1764   VEX_LEN_0F38F3_R_1_P_0,
1765   VEX_LEN_0F38F3_R_2_P_0,
1766   VEX_LEN_0F38F3_R_3_P_0,
1767   VEX_LEN_0F38F5_P_0,
1768   VEX_LEN_0F38F5_P_1,
1769   VEX_LEN_0F38F5_P_3,
1770   VEX_LEN_0F38F6_P_3,
1771   VEX_LEN_0F38F7_P_0,
1772   VEX_LEN_0F38F7_P_1,
1773   VEX_LEN_0F38F7_P_2,
1774   VEX_LEN_0F38F7_P_3,
1775   VEX_LEN_0F3A00_P_2,
1776   VEX_LEN_0F3A01_P_2,
1777   VEX_LEN_0F3A06_P_2,
1778   VEX_LEN_0F3A14_P_2,
1779   VEX_LEN_0F3A15_P_2,
1780   VEX_LEN_0F3A16_P_2,
1781   VEX_LEN_0F3A17_P_2,
1782   VEX_LEN_0F3A18_P_2,
1783   VEX_LEN_0F3A19_P_2,
1784   VEX_LEN_0F3A20_P_2,
1785   VEX_LEN_0F3A21_P_2,
1786   VEX_LEN_0F3A22_P_2,
1787   VEX_LEN_0F3A30_P_2,
1788   VEX_LEN_0F3A31_P_2,
1789   VEX_LEN_0F3A32_P_2,
1790   VEX_LEN_0F3A33_P_2,
1791   VEX_LEN_0F3A38_P_2,
1792   VEX_LEN_0F3A39_P_2,
1793   VEX_LEN_0F3A41_P_2,
1794   VEX_LEN_0F3A46_P_2,
1795   VEX_LEN_0F3A60_P_2,
1796   VEX_LEN_0F3A61_P_2,
1797   VEX_LEN_0F3A62_P_2,
1798   VEX_LEN_0F3A63_P_2,
1799   VEX_LEN_0F3A6A_P_2,
1800   VEX_LEN_0F3A6B_P_2,
1801   VEX_LEN_0F3A6E_P_2,
1802   VEX_LEN_0F3A6F_P_2,
1803   VEX_LEN_0F3A7A_P_2,
1804   VEX_LEN_0F3A7B_P_2,
1805   VEX_LEN_0F3A7E_P_2,
1806   VEX_LEN_0F3A7F_P_2,
1807   VEX_LEN_0F3ADF_P_2,
1808   VEX_LEN_0F3AF0_P_3,
1809   VEX_LEN_0FXOP_08_CC,
1810   VEX_LEN_0FXOP_08_CD,
1811   VEX_LEN_0FXOP_08_CE,
1812   VEX_LEN_0FXOP_08_CF,
1813   VEX_LEN_0FXOP_08_EC,
1814   VEX_LEN_0FXOP_08_ED,
1815   VEX_LEN_0FXOP_08_EE,
1816   VEX_LEN_0FXOP_08_EF,
1817   VEX_LEN_0FXOP_09_82_W_0,
1818   VEX_LEN_0FXOP_09_83_W_0,
1819 };
1820
1821 enum
1822 {
1823   EVEX_LEN_0F6E_P_2 = 0,
1824   EVEX_LEN_0F7E_P_1,
1825   EVEX_LEN_0F7E_P_2,
1826   EVEX_LEN_0FC4_P_2,
1827   EVEX_LEN_0FC5_P_2,
1828   EVEX_LEN_0FD6_P_2,
1829   EVEX_LEN_0F3816_P_2,
1830   EVEX_LEN_0F3819_P_2_W_0,
1831   EVEX_LEN_0F3819_P_2_W_1,
1832   EVEX_LEN_0F381A_P_2_W_0_M_0,
1833   EVEX_LEN_0F381A_P_2_W_1_M_0,
1834   EVEX_LEN_0F381B_P_2_W_0_M_0,
1835   EVEX_LEN_0F381B_P_2_W_1_M_0,
1836   EVEX_LEN_0F3836_P_2,
1837   EVEX_LEN_0F385A_P_2_W_0_M_0,
1838   EVEX_LEN_0F385A_P_2_W_1_M_0,
1839   EVEX_LEN_0F385B_P_2_W_0_M_0,
1840   EVEX_LEN_0F385B_P_2_W_1_M_0,
1841   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1842   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1843   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1844   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1845   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1846   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1847   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1848   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1849   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1850   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1851   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1852   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1853   EVEX_LEN_0F3A00_P_2_W_1,
1854   EVEX_LEN_0F3A01_P_2_W_1,
1855   EVEX_LEN_0F3A14_P_2,
1856   EVEX_LEN_0F3A15_P_2,
1857   EVEX_LEN_0F3A16_P_2,
1858   EVEX_LEN_0F3A17_P_2,
1859   EVEX_LEN_0F3A18_P_2_W_0,
1860   EVEX_LEN_0F3A18_P_2_W_1,
1861   EVEX_LEN_0F3A19_P_2_W_0,
1862   EVEX_LEN_0F3A19_P_2_W_1,
1863   EVEX_LEN_0F3A1A_P_2_W_0,
1864   EVEX_LEN_0F3A1A_P_2_W_1,
1865   EVEX_LEN_0F3A1B_P_2_W_0,
1866   EVEX_LEN_0F3A1B_P_2_W_1,
1867   EVEX_LEN_0F3A20_P_2,
1868   EVEX_LEN_0F3A21_P_2_W_0,
1869   EVEX_LEN_0F3A22_P_2,
1870   EVEX_LEN_0F3A23_P_2_W_0,
1871   EVEX_LEN_0F3A23_P_2_W_1,
1872   EVEX_LEN_0F3A38_P_2_W_0,
1873   EVEX_LEN_0F3A38_P_2_W_1,
1874   EVEX_LEN_0F3A39_P_2_W_0,
1875   EVEX_LEN_0F3A39_P_2_W_1,
1876   EVEX_LEN_0F3A3A_P_2_W_0,
1877   EVEX_LEN_0F3A3A_P_2_W_1,
1878   EVEX_LEN_0F3A3B_P_2_W_0,
1879   EVEX_LEN_0F3A3B_P_2_W_1,
1880   EVEX_LEN_0F3A43_P_2_W_0,
1881   EVEX_LEN_0F3A43_P_2_W_1
1882 };
1883
1884 enum
1885 {
1886   VEX_W_0F41_P_0_LEN_1 = 0,
1887   VEX_W_0F41_P_2_LEN_1,
1888   VEX_W_0F42_P_0_LEN_1,
1889   VEX_W_0F42_P_2_LEN_1,
1890   VEX_W_0F44_P_0_LEN_0,
1891   VEX_W_0F44_P_2_LEN_0,
1892   VEX_W_0F45_P_0_LEN_1,
1893   VEX_W_0F45_P_2_LEN_1,
1894   VEX_W_0F46_P_0_LEN_1,
1895   VEX_W_0F46_P_2_LEN_1,
1896   VEX_W_0F47_P_0_LEN_1,
1897   VEX_W_0F47_P_2_LEN_1,
1898   VEX_W_0F4A_P_0_LEN_1,
1899   VEX_W_0F4A_P_2_LEN_1,
1900   VEX_W_0F4B_P_0_LEN_1,
1901   VEX_W_0F4B_P_2_LEN_1,
1902   VEX_W_0F90_P_0_LEN_0,
1903   VEX_W_0F90_P_2_LEN_0,
1904   VEX_W_0F91_P_0_LEN_0,
1905   VEX_W_0F91_P_2_LEN_0,
1906   VEX_W_0F92_P_0_LEN_0,
1907   VEX_W_0F92_P_2_LEN_0,
1908   VEX_W_0F93_P_0_LEN_0,
1909   VEX_W_0F93_P_2_LEN_0,
1910   VEX_W_0F98_P_0_LEN_0,
1911   VEX_W_0F98_P_2_LEN_0,
1912   VEX_W_0F99_P_0_LEN_0,
1913   VEX_W_0F99_P_2_LEN_0,
1914   VEX_W_0F380C_P_2,
1915   VEX_W_0F380D_P_2,
1916   VEX_W_0F380E_P_2,
1917   VEX_W_0F380F_P_2,
1918   VEX_W_0F3813_P_2,
1919   VEX_W_0F3816_P_2,
1920   VEX_W_0F3818_P_2,
1921   VEX_W_0F3819_P_2,
1922   VEX_W_0F381A_P_2_M_0,
1923   VEX_W_0F382C_P_2_M_0,
1924   VEX_W_0F382D_P_2_M_0,
1925   VEX_W_0F382E_P_2_M_0,
1926   VEX_W_0F382F_P_2_M_0,
1927   VEX_W_0F3836_P_2,
1928   VEX_W_0F3846_P_2,
1929   VEX_W_0F3858_P_2,
1930   VEX_W_0F3859_P_2,
1931   VEX_W_0F385A_P_2_M_0,
1932   VEX_W_0F3878_P_2,
1933   VEX_W_0F3879_P_2,
1934   VEX_W_0F38CF_P_2,
1935   VEX_W_0F3A00_P_2,
1936   VEX_W_0F3A01_P_2,
1937   VEX_W_0F3A02_P_2,
1938   VEX_W_0F3A04_P_2,
1939   VEX_W_0F3A05_P_2,
1940   VEX_W_0F3A06_P_2,
1941   VEX_W_0F3A18_P_2,
1942   VEX_W_0F3A19_P_2,
1943   VEX_W_0F3A1D_P_2,
1944   VEX_W_0F3A30_P_2_LEN_0,
1945   VEX_W_0F3A31_P_2_LEN_0,
1946   VEX_W_0F3A32_P_2_LEN_0,
1947   VEX_W_0F3A33_P_2_LEN_0,
1948   VEX_W_0F3A38_P_2,
1949   VEX_W_0F3A39_P_2,
1950   VEX_W_0F3A46_P_2,
1951   VEX_W_0F3A48_P_2,
1952   VEX_W_0F3A49_P_2,
1953   VEX_W_0F3A4A_P_2,
1954   VEX_W_0F3A4B_P_2,
1955   VEX_W_0F3A4C_P_2,
1956   VEX_W_0F3ACE_P_2,
1957   VEX_W_0F3ACF_P_2,
1958
1959   VEX_W_0FXOP_09_80,
1960   VEX_W_0FXOP_09_81,
1961   VEX_W_0FXOP_09_82,
1962   VEX_W_0FXOP_09_83,
1963
1964   EVEX_W_0F10_P_1,
1965   EVEX_W_0F10_P_3,
1966   EVEX_W_0F11_P_1,
1967   EVEX_W_0F11_P_3,
1968   EVEX_W_0F12_P_0_M_1,
1969   EVEX_W_0F12_P_1,
1970   EVEX_W_0F12_P_3,
1971   EVEX_W_0F16_P_0_M_1,
1972   EVEX_W_0F16_P_1,
1973   EVEX_W_0F2A_P_3,
1974   EVEX_W_0F51_P_1,
1975   EVEX_W_0F51_P_3,
1976   EVEX_W_0F58_P_1,
1977   EVEX_W_0F58_P_3,
1978   EVEX_W_0F59_P_1,
1979   EVEX_W_0F59_P_3,
1980   EVEX_W_0F5A_P_0,
1981   EVEX_W_0F5A_P_1,
1982   EVEX_W_0F5A_P_2,
1983   EVEX_W_0F5A_P_3,
1984   EVEX_W_0F5B_P_0,
1985   EVEX_W_0F5B_P_1,
1986   EVEX_W_0F5B_P_2,
1987   EVEX_W_0F5C_P_1,
1988   EVEX_W_0F5C_P_3,
1989   EVEX_W_0F5D_P_1,
1990   EVEX_W_0F5D_P_3,
1991   EVEX_W_0F5E_P_1,
1992   EVEX_W_0F5E_P_3,
1993   EVEX_W_0F5F_P_1,
1994   EVEX_W_0F5F_P_3,
1995   EVEX_W_0F62,
1996   EVEX_W_0F66_P_2,
1997   EVEX_W_0F6A,
1998   EVEX_W_0F6B,
1999   EVEX_W_0F6C,
2000   EVEX_W_0F6D,
2001   EVEX_W_0F6F_P_1,
2002   EVEX_W_0F6F_P_2,
2003   EVEX_W_0F6F_P_3,
2004   EVEX_W_0F70_P_2,
2005   EVEX_W_0F72_R_2_P_2,
2006   EVEX_W_0F72_R_6_P_2,
2007   EVEX_W_0F73_R_2_P_2,
2008   EVEX_W_0F73_R_6_P_2,
2009   EVEX_W_0F76_P_2,
2010   EVEX_W_0F78_P_0,
2011   EVEX_W_0F78_P_2,
2012   EVEX_W_0F79_P_0,
2013   EVEX_W_0F79_P_2,
2014   EVEX_W_0F7A_P_1,
2015   EVEX_W_0F7A_P_2,
2016   EVEX_W_0F7A_P_3,
2017   EVEX_W_0F7B_P_2,
2018   EVEX_W_0F7B_P_3,
2019   EVEX_W_0F7E_P_1,
2020   EVEX_W_0F7F_P_1,
2021   EVEX_W_0F7F_P_2,
2022   EVEX_W_0F7F_P_3,
2023   EVEX_W_0FC2_P_1,
2024   EVEX_W_0FC2_P_3,
2025   EVEX_W_0FD2,
2026   EVEX_W_0FD3,
2027   EVEX_W_0FD4,
2028   EVEX_W_0FD6_P_2,
2029   EVEX_W_0FE6_P_1,
2030   EVEX_W_0FE6_P_2,
2031   EVEX_W_0FE6_P_3,
2032   EVEX_W_0FE7_P_2,
2033   EVEX_W_0FF2,
2034   EVEX_W_0FF3,
2035   EVEX_W_0FF4,
2036   EVEX_W_0FFA,
2037   EVEX_W_0FFB,
2038   EVEX_W_0FFE,
2039   EVEX_W_0F380D_P_2,
2040   EVEX_W_0F3810_P_1,
2041   EVEX_W_0F3810_P_2,
2042   EVEX_W_0F3811_P_1,
2043   EVEX_W_0F3811_P_2,
2044   EVEX_W_0F3812_P_1,
2045   EVEX_W_0F3812_P_2,
2046   EVEX_W_0F3813_P_1,
2047   EVEX_W_0F3813_P_2,
2048   EVEX_W_0F3814_P_1,
2049   EVEX_W_0F3815_P_1,
2050   EVEX_W_0F3819_P_2,
2051   EVEX_W_0F381A_P_2,
2052   EVEX_W_0F381B_P_2,
2053   EVEX_W_0F381E_P_2,
2054   EVEX_W_0F381F_P_2,
2055   EVEX_W_0F3820_P_1,
2056   EVEX_W_0F3821_P_1,
2057   EVEX_W_0F3822_P_1,
2058   EVEX_W_0F3823_P_1,
2059   EVEX_W_0F3824_P_1,
2060   EVEX_W_0F3825_P_1,
2061   EVEX_W_0F3825_P_2,
2062   EVEX_W_0F3826_P_1,
2063   EVEX_W_0F3826_P_2,
2064   EVEX_W_0F3828_P_1,
2065   EVEX_W_0F3828_P_2,
2066   EVEX_W_0F3829_P_1,
2067   EVEX_W_0F3829_P_2,
2068   EVEX_W_0F382A_P_1,
2069   EVEX_W_0F382A_P_2,
2070   EVEX_W_0F382B,
2071   EVEX_W_0F3830_P_1,
2072   EVEX_W_0F3831_P_1,
2073   EVEX_W_0F3832_P_1,
2074   EVEX_W_0F3833_P_1,
2075   EVEX_W_0F3834_P_1,
2076   EVEX_W_0F3835_P_1,
2077   EVEX_W_0F3835_P_2,
2078   EVEX_W_0F3837_P_2,
2079   EVEX_W_0F383A_P_1,
2080   EVEX_W_0F3852_P_1,
2081   EVEX_W_0F3854_P_2,
2082   EVEX_W_0F3859_P_2,
2083   EVEX_W_0F385A_P_2,
2084   EVEX_W_0F385B_P_2,
2085   EVEX_W_0F3862_P_2,
2086   EVEX_W_0F3863_P_2,
2087   EVEX_W_0F3866_P_2,
2088   EVEX_W_0F3870_P_2,
2089   EVEX_W_0F3872_P_1,
2090   EVEX_W_0F3872_P_2,
2091   EVEX_W_0F3872_P_3,
2092   EVEX_W_0F3875_P_2,
2093   EVEX_W_0F387A_P_2,
2094   EVEX_W_0F387B_P_2,
2095   EVEX_W_0F387D_P_2,
2096   EVEX_W_0F3883_P_2,
2097   EVEX_W_0F388D_P_2,
2098   EVEX_W_0F3891_P_2,
2099   EVEX_W_0F3893_P_2,
2100   EVEX_W_0F38A1_P_2,
2101   EVEX_W_0F38A3_P_2,
2102   EVEX_W_0F38C7_R_1_P_2,
2103   EVEX_W_0F38C7_R_2_P_2,
2104   EVEX_W_0F38C7_R_5_P_2,
2105   EVEX_W_0F38C7_R_6_P_2,
2106
2107   EVEX_W_0F3A00_P_2,
2108   EVEX_W_0F3A01_P_2,
2109   EVEX_W_0F3A05_P_2,
2110   EVEX_W_0F3A08_P_2,
2111   EVEX_W_0F3A09_P_2,
2112   EVEX_W_0F3A0A_P_2,
2113   EVEX_W_0F3A0B_P_2,
2114   EVEX_W_0F3A18_P_2,
2115   EVEX_W_0F3A19_P_2,
2116   EVEX_W_0F3A1A_P_2,
2117   EVEX_W_0F3A1B_P_2,
2118   EVEX_W_0F3A21_P_2,
2119   EVEX_W_0F3A23_P_2,
2120   EVEX_W_0F3A38_P_2,
2121   EVEX_W_0F3A39_P_2,
2122   EVEX_W_0F3A3A_P_2,
2123   EVEX_W_0F3A3B_P_2,
2124   EVEX_W_0F3A3E_P_2,
2125   EVEX_W_0F3A3F_P_2,
2126   EVEX_W_0F3A42_P_2,
2127   EVEX_W_0F3A43_P_2,
2128   EVEX_W_0F3A70_P_2,
2129   EVEX_W_0F3A72_P_2,
2130 };
2131
2132 typedef void (*op_rtn) (int bytemode, int sizeflag);
2133
2134 struct dis386 {
2135   const char *name;
2136   struct
2137     {
2138       op_rtn rtn;
2139       int bytemode;
2140     } op[MAX_OPERANDS];
2141   unsigned int prefix_requirement;
2142 };
2143
2144 /* Upper case letters in the instruction names here are macros.
2145    'A' => print 'b' if no register operands or suffix_always is true
2146    'B' => print 'b' if suffix_always is true
2147    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2148           size prefix
2149    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2150           suffix_always is true
2151    'E' => print 'e' if 32-bit form of jcxz
2152    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2153    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2154    'H' => print ",pt" or ",pn" branch hint
2155    'I' unused.
2156    'J' unused.
2157    'K' => print 'd' or 'q' if rex prefix is present.
2158    'L' => print 'l' if suffix_always is true
2159    'M' => print 'r' if intel_mnemonic is false.
2160    'N' => print 'n' if instruction has no wait "prefix"
2161    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2162    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2163           or suffix_always is true.  print 'q' if rex prefix is present.
2164    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2165           is true
2166    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2167    'S' => print 'w', 'l' or 'q' if suffix_always is true
2168    'T' => print 'q' in 64bit mode if instruction has no operand size
2169           prefix and behave as 'P' otherwise
2170    'U' => print 'q' in 64bit mode if instruction has no operand size
2171           prefix and behave as 'Q' otherwise
2172    'V' => print 'q' in 64bit mode if instruction has no operand size
2173           prefix and behave as 'S' otherwise
2174    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2175    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2176    'Y' unused.
2177    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2178    '!' => change condition from true to false or from false to true.
2179    '%' => add 1 upper case letter to the macro.
2180    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2181           prefix or suffix_always is true (lcall/ljmp).
2182    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2183           on operand size prefix.
2184    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2185           has no operand size prefix for AMD64 ISA, behave as 'P'
2186           otherwise
2187
2188    2 upper case letter macros:
2189    "XY" => print 'x' or 'y' if suffix_always is true or no register
2190            operands and no broadcast.
2191    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2192            register operands and no broadcast.
2193    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2194    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2195            operand or no operand at all in 64bit mode, or if suffix_always
2196            is true.
2197    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2198    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2199    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2200    "LW" => print 'd', 'q' depending on the VEX.W bit
2201    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2202            an operand size prefix, or suffix_always is true.  print
2203            'q' if rex prefix is present.
2204
2205    Many of the above letters print nothing in Intel mode.  See "putop"
2206    for the details.
2207
2208    Braces '{' and '}', and vertical bars '|', indicate alternative
2209    mnemonic strings for AT&T and Intel.  */
2210
2211 static const struct dis386 dis386[] = {
2212   /* 00 */
2213   { "addB",             { Ebh1, Gb }, 0 },
2214   { "addS",             { Evh1, Gv }, 0 },
2215   { "addB",             { Gb, EbS }, 0 },
2216   { "addS",             { Gv, EvS }, 0 },
2217   { "addB",             { AL, Ib }, 0 },
2218   { "addS",             { eAX, Iv }, 0 },
2219   { X86_64_TABLE (X86_64_06) },
2220   { X86_64_TABLE (X86_64_07) },
2221   /* 08 */
2222   { "orB",              { Ebh1, Gb }, 0 },
2223   { "orS",              { Evh1, Gv }, 0 },
2224   { "orB",              { Gb, EbS }, 0 },
2225   { "orS",              { Gv, EvS }, 0 },
2226   { "orB",              { AL, Ib }, 0 },
2227   { "orS",              { eAX, Iv }, 0 },
2228   { X86_64_TABLE (X86_64_0E) },
2229   { Bad_Opcode },       /* 0x0f extended opcode escape */
2230   /* 10 */
2231   { "adcB",             { Ebh1, Gb }, 0 },
2232   { "adcS",             { Evh1, Gv }, 0 },
2233   { "adcB",             { Gb, EbS }, 0 },
2234   { "adcS",             { Gv, EvS }, 0 },
2235   { "adcB",             { AL, Ib }, 0 },
2236   { "adcS",             { eAX, Iv }, 0 },
2237   { X86_64_TABLE (X86_64_16) },
2238   { X86_64_TABLE (X86_64_17) },
2239   /* 18 */
2240   { "sbbB",             { Ebh1, Gb }, 0 },
2241   { "sbbS",             { Evh1, Gv }, 0 },
2242   { "sbbB",             { Gb, EbS }, 0 },
2243   { "sbbS",             { Gv, EvS }, 0 },
2244   { "sbbB",             { AL, Ib }, 0 },
2245   { "sbbS",             { eAX, Iv }, 0 },
2246   { X86_64_TABLE (X86_64_1E) },
2247   { X86_64_TABLE (X86_64_1F) },
2248   /* 20 */
2249   { "andB",             { Ebh1, Gb }, 0 },
2250   { "andS",             { Evh1, Gv }, 0 },
2251   { "andB",             { Gb, EbS }, 0 },
2252   { "andS",             { Gv, EvS }, 0 },
2253   { "andB",             { AL, Ib }, 0 },
2254   { "andS",             { eAX, Iv }, 0 },
2255   { Bad_Opcode },       /* SEG ES prefix */
2256   { X86_64_TABLE (X86_64_27) },
2257   /* 28 */
2258   { "subB",             { Ebh1, Gb }, 0 },
2259   { "subS",             { Evh1, Gv }, 0 },
2260   { "subB",             { Gb, EbS }, 0 },
2261   { "subS",             { Gv, EvS }, 0 },
2262   { "subB",             { AL, Ib }, 0 },
2263   { "subS",             { eAX, Iv }, 0 },
2264   { Bad_Opcode },       /* SEG CS prefix */
2265   { X86_64_TABLE (X86_64_2F) },
2266   /* 30 */
2267   { "xorB",             { Ebh1, Gb }, 0 },
2268   { "xorS",             { Evh1, Gv }, 0 },
2269   { "xorB",             { Gb, EbS }, 0 },
2270   { "xorS",             { Gv, EvS }, 0 },
2271   { "xorB",             { AL, Ib }, 0 },
2272   { "xorS",             { eAX, Iv }, 0 },
2273   { Bad_Opcode },       /* SEG SS prefix */
2274   { X86_64_TABLE (X86_64_37) },
2275   /* 38 */
2276   { "cmpB",             { Eb, Gb }, 0 },
2277   { "cmpS",             { Ev, Gv }, 0 },
2278   { "cmpB",             { Gb, EbS }, 0 },
2279   { "cmpS",             { Gv, EvS }, 0 },
2280   { "cmpB",             { AL, Ib }, 0 },
2281   { "cmpS",             { eAX, Iv }, 0 },
2282   { Bad_Opcode },       /* SEG DS prefix */
2283   { X86_64_TABLE (X86_64_3F) },
2284   /* 40 */
2285   { "inc{S|}",          { RMeAX }, 0 },
2286   { "inc{S|}",          { RMeCX }, 0 },
2287   { "inc{S|}",          { RMeDX }, 0 },
2288   { "inc{S|}",          { RMeBX }, 0 },
2289   { "inc{S|}",          { RMeSP }, 0 },
2290   { "inc{S|}",          { RMeBP }, 0 },
2291   { "inc{S|}",          { RMeSI }, 0 },
2292   { "inc{S|}",          { RMeDI }, 0 },
2293   /* 48 */
2294   { "dec{S|}",          { RMeAX }, 0 },
2295   { "dec{S|}",          { RMeCX }, 0 },
2296   { "dec{S|}",          { RMeDX }, 0 },
2297   { "dec{S|}",          { RMeBX }, 0 },
2298   { "dec{S|}",          { RMeSP }, 0 },
2299   { "dec{S|}",          { RMeBP }, 0 },
2300   { "dec{S|}",          { RMeSI }, 0 },
2301   { "dec{S|}",          { RMeDI }, 0 },
2302   /* 50 */
2303   { "pushV",            { RMrAX }, 0 },
2304   { "pushV",            { RMrCX }, 0 },
2305   { "pushV",            { RMrDX }, 0 },
2306   { "pushV",            { RMrBX }, 0 },
2307   { "pushV",            { RMrSP }, 0 },
2308   { "pushV",            { RMrBP }, 0 },
2309   { "pushV",            { RMrSI }, 0 },
2310   { "pushV",            { RMrDI }, 0 },
2311   /* 58 */
2312   { "popV",             { RMrAX }, 0 },
2313   { "popV",             { RMrCX }, 0 },
2314   { "popV",             { RMrDX }, 0 },
2315   { "popV",             { RMrBX }, 0 },
2316   { "popV",             { RMrSP }, 0 },
2317   { "popV",             { RMrBP }, 0 },
2318   { "popV",             { RMrSI }, 0 },
2319   { "popV",             { RMrDI }, 0 },
2320   /* 60 */
2321   { X86_64_TABLE (X86_64_60) },
2322   { X86_64_TABLE (X86_64_61) },
2323   { X86_64_TABLE (X86_64_62) },
2324   { X86_64_TABLE (X86_64_63) },
2325   { Bad_Opcode },       /* seg fs */
2326   { Bad_Opcode },       /* seg gs */
2327   { Bad_Opcode },       /* op size prefix */
2328   { Bad_Opcode },       /* adr size prefix */
2329   /* 68 */
2330   { "pushT",            { sIv }, 0 },
2331   { "imulS",            { Gv, Ev, Iv }, 0 },
2332   { "pushT",            { sIbT }, 0 },
2333   { "imulS",            { Gv, Ev, sIb }, 0 },
2334   { "ins{b|}",          { Ybr, indirDX }, 0 },
2335   { X86_64_TABLE (X86_64_6D) },
2336   { "outs{b|}",         { indirDXr, Xb }, 0 },
2337   { X86_64_TABLE (X86_64_6F) },
2338   /* 70 */
2339   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2340   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2341   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2342   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2343   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2344   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2345   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2346   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2347   /* 78 */
2348   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2349   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2350   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2351   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2352   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2353   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2354   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2355   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2356   /* 80 */
2357   { REG_TABLE (REG_80) },
2358   { REG_TABLE (REG_81) },
2359   { X86_64_TABLE (X86_64_82) },
2360   { REG_TABLE (REG_83) },
2361   { "testB",            { Eb, Gb }, 0 },
2362   { "testS",            { Ev, Gv }, 0 },
2363   { "xchgB",            { Ebh2, Gb }, 0 },
2364   { "xchgS",            { Evh2, Gv }, 0 },
2365   /* 88 */
2366   { "movB",             { Ebh3, Gb }, 0 },
2367   { "movS",             { Evh3, Gv }, 0 },
2368   { "movB",             { Gb, EbS }, 0 },
2369   { "movS",             { Gv, EvS }, 0 },
2370   { "movD",             { Sv, Sw }, 0 },
2371   { MOD_TABLE (MOD_8D) },
2372   { "movD",             { Sw, Sv }, 0 },
2373   { REG_TABLE (REG_8F) },
2374   /* 90 */
2375   { PREFIX_TABLE (PREFIX_90) },
2376   { "xchgS",            { RMeCX, eAX }, 0 },
2377   { "xchgS",            { RMeDX, eAX }, 0 },
2378   { "xchgS",            { RMeBX, eAX }, 0 },
2379   { "xchgS",            { RMeSP, eAX }, 0 },
2380   { "xchgS",            { RMeBP, eAX }, 0 },
2381   { "xchgS",            { RMeSI, eAX }, 0 },
2382   { "xchgS",            { RMeDI, eAX }, 0 },
2383   /* 98 */
2384   { "cW{t|}R",          { XX }, 0 },
2385   { "cR{t|}O",          { XX }, 0 },
2386   { X86_64_TABLE (X86_64_9A) },
2387   { Bad_Opcode },       /* fwait */
2388   { "pushfT",           { XX }, 0 },
2389   { "popfT",            { XX }, 0 },
2390   { "sahf",             { XX }, 0 },
2391   { "lahf",             { XX }, 0 },
2392   /* a0 */
2393   { "mov%LB",           { AL, Ob }, 0 },
2394   { "mov%LS",           { eAX, Ov }, 0 },
2395   { "mov%LB",           { Ob, AL }, 0 },
2396   { "mov%LS",           { Ov, eAX }, 0 },
2397   { "movs{b|}",         { Ybr, Xb }, 0 },
2398   { "movs{R|}",         { Yvr, Xv }, 0 },
2399   { "cmps{b|}",         { Xb, Yb }, 0 },
2400   { "cmps{R|}",         { Xv, Yv }, 0 },
2401   /* a8 */
2402   { "testB",            { AL, Ib }, 0 },
2403   { "testS",            { eAX, Iv }, 0 },
2404   { "stosB",            { Ybr, AL }, 0 },
2405   { "stosS",            { Yvr, eAX }, 0 },
2406   { "lodsB",            { ALr, Xb }, 0 },
2407   { "lodsS",            { eAXr, Xv }, 0 },
2408   { "scasB",            { AL, Yb }, 0 },
2409   { "scasS",            { eAX, Yv }, 0 },
2410   /* b0 */
2411   { "movB",             { RMAL, Ib }, 0 },
2412   { "movB",             { RMCL, Ib }, 0 },
2413   { "movB",             { RMDL, Ib }, 0 },
2414   { "movB",             { RMBL, Ib }, 0 },
2415   { "movB",             { RMAH, Ib }, 0 },
2416   { "movB",             { RMCH, Ib }, 0 },
2417   { "movB",             { RMDH, Ib }, 0 },
2418   { "movB",             { RMBH, Ib }, 0 },
2419   /* b8 */
2420   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2421   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2422   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2423   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2424   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2425   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2426   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2427   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2428   /* c0 */
2429   { REG_TABLE (REG_C0) },
2430   { REG_TABLE (REG_C1) },
2431   { X86_64_TABLE (X86_64_C2) },
2432   { X86_64_TABLE (X86_64_C3) },
2433   { X86_64_TABLE (X86_64_C4) },
2434   { X86_64_TABLE (X86_64_C5) },
2435   { REG_TABLE (REG_C6) },
2436   { REG_TABLE (REG_C7) },
2437   /* c8 */
2438   { "enterT",           { Iw, Ib }, 0 },
2439   { "leaveT",           { XX }, 0 },
2440   { "{l|}ret{|f}P",     { Iw }, 0 },
2441   { "{l|}ret{|f}P",     { XX }, 0 },
2442   { "int3",             { XX }, 0 },
2443   { "int",              { Ib }, 0 },
2444   { X86_64_TABLE (X86_64_CE) },
2445   { "iret%LP",          { XX }, 0 },
2446   /* d0 */
2447   { REG_TABLE (REG_D0) },
2448   { REG_TABLE (REG_D1) },
2449   { REG_TABLE (REG_D2) },
2450   { REG_TABLE (REG_D3) },
2451   { X86_64_TABLE (X86_64_D4) },
2452   { X86_64_TABLE (X86_64_D5) },
2453   { Bad_Opcode },
2454   { "xlat",             { DSBX }, 0 },
2455   /* d8 */
2456   { FLOAT },
2457   { FLOAT },
2458   { FLOAT },
2459   { FLOAT },
2460   { FLOAT },
2461   { FLOAT },
2462   { FLOAT },
2463   { FLOAT },
2464   /* e0 */
2465   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2466   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2467   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2468   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2469   { "inB",              { AL, Ib }, 0 },
2470   { "inG",              { zAX, Ib }, 0 },
2471   { "outB",             { Ib, AL }, 0 },
2472   { "outG",             { Ib, zAX }, 0 },
2473   /* e8 */
2474   { X86_64_TABLE (X86_64_E8) },
2475   { X86_64_TABLE (X86_64_E9) },
2476   { X86_64_TABLE (X86_64_EA) },
2477   { "jmp",              { Jb, BND }, 0 },
2478   { "inB",              { AL, indirDX }, 0 },
2479   { "inG",              { zAX, indirDX }, 0 },
2480   { "outB",             { indirDX, AL }, 0 },
2481   { "outG",             { indirDX, zAX }, 0 },
2482   /* f0 */
2483   { Bad_Opcode },       /* lock prefix */
2484   { "icebp",            { XX }, 0 },
2485   { Bad_Opcode },       /* repne */
2486   { Bad_Opcode },       /* repz */
2487   { "hlt",              { XX }, 0 },
2488   { "cmc",              { XX }, 0 },
2489   { REG_TABLE (REG_F6) },
2490   { REG_TABLE (REG_F7) },
2491   /* f8 */
2492   { "clc",              { XX }, 0 },
2493   { "stc",              { XX }, 0 },
2494   { "cli",              { XX }, 0 },
2495   { "sti",              { XX }, 0 },
2496   { "cld",              { XX }, 0 },
2497   { "std",              { XX }, 0 },
2498   { REG_TABLE (REG_FE) },
2499   { REG_TABLE (REG_FF) },
2500 };
2501
2502 static const struct dis386 dis386_twobyte[] = {
2503   /* 00 */
2504   { REG_TABLE (REG_0F00 ) },
2505   { REG_TABLE (REG_0F01 ) },
2506   { "larS",             { Gv, Ew }, 0 },
2507   { "lslS",             { Gv, Ew }, 0 },
2508   { Bad_Opcode },
2509   { "syscall",          { XX }, 0 },
2510   { "clts",             { XX }, 0 },
2511   { "sysret%LQ",                { XX }, 0 },
2512   /* 08 */
2513   { "invd",             { XX }, 0 },
2514   { PREFIX_TABLE (PREFIX_0F09) },
2515   { Bad_Opcode },
2516   { "ud2",              { XX }, 0 },
2517   { Bad_Opcode },
2518   { REG_TABLE (REG_0F0D) },
2519   { "femms",            { XX }, 0 },
2520   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2521   /* 10 */
2522   { PREFIX_TABLE (PREFIX_0F10) },
2523   { PREFIX_TABLE (PREFIX_0F11) },
2524   { PREFIX_TABLE (PREFIX_0F12) },
2525   { MOD_TABLE (MOD_0F13) },
2526   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2527   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2528   { PREFIX_TABLE (PREFIX_0F16) },
2529   { MOD_TABLE (MOD_0F17) },
2530   /* 18 */
2531   { REG_TABLE (REG_0F18) },
2532   { "nopQ",             { Ev }, 0 },
2533   { PREFIX_TABLE (PREFIX_0F1A) },
2534   { PREFIX_TABLE (PREFIX_0F1B) },
2535   { PREFIX_TABLE (PREFIX_0F1C) },
2536   { "nopQ",             { Ev }, 0 },
2537   { PREFIX_TABLE (PREFIX_0F1E) },
2538   { "nopQ",             { Ev }, 0 },
2539   /* 20 */
2540   { "movZ",             { Rm, Cm }, 0 },
2541   { "movZ",             { Rm, Dm }, 0 },
2542   { "movZ",             { Cm, Rm }, 0 },
2543   { "movZ",             { Dm, Rm }, 0 },
2544   { MOD_TABLE (MOD_0F24) },
2545   { Bad_Opcode },
2546   { MOD_TABLE (MOD_0F26) },
2547   { Bad_Opcode },
2548   /* 28 */
2549   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2550   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2551   { PREFIX_TABLE (PREFIX_0F2A) },
2552   { PREFIX_TABLE (PREFIX_0F2B) },
2553   { PREFIX_TABLE (PREFIX_0F2C) },
2554   { PREFIX_TABLE (PREFIX_0F2D) },
2555   { PREFIX_TABLE (PREFIX_0F2E) },
2556   { PREFIX_TABLE (PREFIX_0F2F) },
2557   /* 30 */
2558   { "wrmsr",            { XX }, 0 },
2559   { "rdtsc",            { XX }, 0 },
2560   { "rdmsr",            { XX }, 0 },
2561   { "rdpmc",            { XX }, 0 },
2562   { "sysenter",         { SEP }, 0 },
2563   { "sysexit",          { SEP }, 0 },
2564   { Bad_Opcode },
2565   { "getsec",           { XX }, 0 },
2566   /* 38 */
2567   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2568   { Bad_Opcode },
2569   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2570   { Bad_Opcode },
2571   { Bad_Opcode },
2572   { Bad_Opcode },
2573   { Bad_Opcode },
2574   { Bad_Opcode },
2575   /* 40 */
2576   { "cmovoS",           { Gv, Ev }, 0 },
2577   { "cmovnoS",          { Gv, Ev }, 0 },
2578   { "cmovbS",           { Gv, Ev }, 0 },
2579   { "cmovaeS",          { Gv, Ev }, 0 },
2580   { "cmoveS",           { Gv, Ev }, 0 },
2581   { "cmovneS",          { Gv, Ev }, 0 },
2582   { "cmovbeS",          { Gv, Ev }, 0 },
2583   { "cmovaS",           { Gv, Ev }, 0 },
2584   /* 48 */
2585   { "cmovsS",           { Gv, Ev }, 0 },
2586   { "cmovnsS",          { Gv, Ev }, 0 },
2587   { "cmovpS",           { Gv, Ev }, 0 },
2588   { "cmovnpS",          { Gv, Ev }, 0 },
2589   { "cmovlS",           { Gv, Ev }, 0 },
2590   { "cmovgeS",          { Gv, Ev }, 0 },
2591   { "cmovleS",          { Gv, Ev }, 0 },
2592   { "cmovgS",           { Gv, Ev }, 0 },
2593   /* 50 */
2594   { MOD_TABLE (MOD_0F50) },
2595   { PREFIX_TABLE (PREFIX_0F51) },
2596   { PREFIX_TABLE (PREFIX_0F52) },
2597   { PREFIX_TABLE (PREFIX_0F53) },
2598   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2599   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2600   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2601   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2602   /* 58 */
2603   { PREFIX_TABLE (PREFIX_0F58) },
2604   { PREFIX_TABLE (PREFIX_0F59) },
2605   { PREFIX_TABLE (PREFIX_0F5A) },
2606   { PREFIX_TABLE (PREFIX_0F5B) },
2607   { PREFIX_TABLE (PREFIX_0F5C) },
2608   { PREFIX_TABLE (PREFIX_0F5D) },
2609   { PREFIX_TABLE (PREFIX_0F5E) },
2610   { PREFIX_TABLE (PREFIX_0F5F) },
2611   /* 60 */
2612   { PREFIX_TABLE (PREFIX_0F60) },
2613   { PREFIX_TABLE (PREFIX_0F61) },
2614   { PREFIX_TABLE (PREFIX_0F62) },
2615   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2616   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2617   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2618   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2619   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2620   /* 68 */
2621   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2622   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2623   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2624   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2625   { PREFIX_TABLE (PREFIX_0F6C) },
2626   { PREFIX_TABLE (PREFIX_0F6D) },
2627   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2628   { PREFIX_TABLE (PREFIX_0F6F) },
2629   /* 70 */
2630   { PREFIX_TABLE (PREFIX_0F70) },
2631   { REG_TABLE (REG_0F71) },
2632   { REG_TABLE (REG_0F72) },
2633   { REG_TABLE (REG_0F73) },
2634   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2635   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2636   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2637   { "emms",             { XX }, PREFIX_OPCODE },
2638   /* 78 */
2639   { PREFIX_TABLE (PREFIX_0F78) },
2640   { PREFIX_TABLE (PREFIX_0F79) },
2641   { Bad_Opcode },
2642   { Bad_Opcode },
2643   { PREFIX_TABLE (PREFIX_0F7C) },
2644   { PREFIX_TABLE (PREFIX_0F7D) },
2645   { PREFIX_TABLE (PREFIX_0F7E) },
2646   { PREFIX_TABLE (PREFIX_0F7F) },
2647   /* 80 */
2648   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2649   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2650   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2651   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2652   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2653   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2654   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2655   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2656   /* 88 */
2657   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2658   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2659   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2660   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2661   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2662   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2663   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2664   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2665   /* 90 */
2666   { "seto",             { Eb }, 0 },
2667   { "setno",            { Eb }, 0 },
2668   { "setb",             { Eb }, 0 },
2669   { "setae",            { Eb }, 0 },
2670   { "sete",             { Eb }, 0 },
2671   { "setne",            { Eb }, 0 },
2672   { "setbe",            { Eb }, 0 },
2673   { "seta",             { Eb }, 0 },
2674   /* 98 */
2675   { "sets",             { Eb }, 0 },
2676   { "setns",            { Eb }, 0 },
2677   { "setp",             { Eb }, 0 },
2678   { "setnp",            { Eb }, 0 },
2679   { "setl",             { Eb }, 0 },
2680   { "setge",            { Eb }, 0 },
2681   { "setle",            { Eb }, 0 },
2682   { "setg",             { Eb }, 0 },
2683   /* a0 */
2684   { "pushT",            { fs }, 0 },
2685   { "popT",             { fs }, 0 },
2686   { "cpuid",            { XX }, 0 },
2687   { "btS",              { Ev, Gv }, 0 },
2688   { "shldS",            { Ev, Gv, Ib }, 0 },
2689   { "shldS",            { Ev, Gv, CL }, 0 },
2690   { REG_TABLE (REG_0FA6) },
2691   { REG_TABLE (REG_0FA7) },
2692   /* a8 */
2693   { "pushT",            { gs }, 0 },
2694   { "popT",             { gs }, 0 },
2695   { "rsm",              { XX }, 0 },
2696   { "btsS",             { Evh1, Gv }, 0 },
2697   { "shrdS",            { Ev, Gv, Ib }, 0 },
2698   { "shrdS",            { Ev, Gv, CL }, 0 },
2699   { REG_TABLE (REG_0FAE) },
2700   { "imulS",            { Gv, Ev }, 0 },
2701   /* b0 */
2702   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2703   { "cmpxchgS",         { Evh1, Gv }, 0 },
2704   { MOD_TABLE (MOD_0FB2) },
2705   { "btrS",             { Evh1, Gv }, 0 },
2706   { MOD_TABLE (MOD_0FB4) },
2707   { MOD_TABLE (MOD_0FB5) },
2708   { "movz{bR|x}",       { Gv, Eb }, 0 },
2709   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2710   /* b8 */
2711   { PREFIX_TABLE (PREFIX_0FB8) },
2712   { "ud1S",             { Gv, Ev }, 0 },
2713   { REG_TABLE (REG_0FBA) },
2714   { "btcS",             { Evh1, Gv }, 0 },
2715   { PREFIX_TABLE (PREFIX_0FBC) },
2716   { PREFIX_TABLE (PREFIX_0FBD) },
2717   { "movs{bR|x}",       { Gv, Eb }, 0 },
2718   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2719   /* c0 */
2720   { "xaddB",            { Ebh1, Gb }, 0 },
2721   { "xaddS",            { Evh1, Gv }, 0 },
2722   { PREFIX_TABLE (PREFIX_0FC2) },
2723   { MOD_TABLE (MOD_0FC3) },
2724   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2725   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2726   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2727   { REG_TABLE (REG_0FC7) },
2728   /* c8 */
2729   { "bswap",            { RMeAX }, 0 },
2730   { "bswap",            { RMeCX }, 0 },
2731   { "bswap",            { RMeDX }, 0 },
2732   { "bswap",            { RMeBX }, 0 },
2733   { "bswap",            { RMeSP }, 0 },
2734   { "bswap",            { RMeBP }, 0 },
2735   { "bswap",            { RMeSI }, 0 },
2736   { "bswap",            { RMeDI }, 0 },
2737   /* d0 */
2738   { PREFIX_TABLE (PREFIX_0FD0) },
2739   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2740   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2741   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2742   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2743   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2744   { PREFIX_TABLE (PREFIX_0FD6) },
2745   { MOD_TABLE (MOD_0FD7) },
2746   /* d8 */
2747   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2748   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2749   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2750   { "pand",             { MX, EM }, PREFIX_OPCODE },
2751   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2752   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2753   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2754   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2755   /* e0 */
2756   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2757   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2758   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2759   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2760   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2761   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2762   { PREFIX_TABLE (PREFIX_0FE6) },
2763   { PREFIX_TABLE (PREFIX_0FE7) },
2764   /* e8 */
2765   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2766   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2767   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2768   { "por",              { MX, EM }, PREFIX_OPCODE },
2769   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2770   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2771   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2772   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2773   /* f0 */
2774   { PREFIX_TABLE (PREFIX_0FF0) },
2775   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2776   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2777   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2778   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2779   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2780   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2781   { PREFIX_TABLE (PREFIX_0FF7) },
2782   /* f8 */
2783   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2784   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2785   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2786   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2787   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2788   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2789   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2790   { "ud0S",             { Gv, Ev }, 0 },
2791 };
2792
2793 static const unsigned char onebyte_has_modrm[256] = {
2794   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2795   /*       -------------------------------        */
2796   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2797   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2798   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2799   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2800   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2801   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2802   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2803   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2804   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2805   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2806   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2807   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2808   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2809   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2810   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2811   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2812   /*       -------------------------------        */
2813   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2814 };
2815
2816 static const unsigned char twobyte_has_modrm[256] = {
2817   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2818   /*       -------------------------------        */
2819   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2820   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2821   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2822   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2823   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2824   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2825   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2826   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2827   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2828   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2829   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2830   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2831   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2832   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2833   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2834   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2835   /*       -------------------------------        */
2836   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2837 };
2838
2839 static char obuf[100];
2840 static char *obufp;
2841 static char *mnemonicendp;
2842 static char scratchbuf[100];
2843 static unsigned char *start_codep;
2844 static unsigned char *insn_codep;
2845 static unsigned char *codep;
2846 static unsigned char *end_codep;
2847 static int last_lock_prefix;
2848 static int last_repz_prefix;
2849 static int last_repnz_prefix;
2850 static int last_data_prefix;
2851 static int last_addr_prefix;
2852 static int last_rex_prefix;
2853 static int last_seg_prefix;
2854 static int fwait_prefix;
2855 /* The active segment register prefix.  */
2856 static int active_seg_prefix;
2857 #define MAX_CODE_LENGTH 15
2858 /* We can up to 14 prefixes since the maximum instruction length is
2859    15bytes.  */
2860 static int all_prefixes[MAX_CODE_LENGTH - 1];
2861 static disassemble_info *the_info;
2862 static struct
2863   {
2864     int mod;
2865     int reg;
2866     int rm;
2867   }
2868 modrm;
2869 static unsigned char need_modrm;
2870 static struct
2871   {
2872     int scale;
2873     int index;
2874     int base;
2875   }
2876 sib;
2877 static struct
2878   {
2879     int register_specifier;
2880     int length;
2881     int prefix;
2882     int w;
2883     int evex;
2884     int r;
2885     int v;
2886     int mask_register_specifier;
2887     int zeroing;
2888     int ll;
2889     int b;
2890   }
2891 vex;
2892 static unsigned char need_vex;
2893 static unsigned char need_vex_reg;
2894 static unsigned char vex_w_done;
2895
2896 struct op
2897   {
2898     const char *name;
2899     unsigned int len;
2900   };
2901
2902 /* If we are accessing mod/rm/reg without need_modrm set, then the
2903    values are stale.  Hitting this abort likely indicates that you
2904    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2905 #define MODRM_CHECK  if (!need_modrm) abort ()
2906
2907 static const char **names64;
2908 static const char **names32;
2909 static const char **names16;
2910 static const char **names8;
2911 static const char **names8rex;
2912 static const char **names_seg;
2913 static const char *index64;
2914 static const char *index32;
2915 static const char **index16;
2916 static const char **names_bnd;
2917
2918 static const char *intel_names64[] = {
2919   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2920   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2921 };
2922 static const char *intel_names32[] = {
2923   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2924   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2925 };
2926 static const char *intel_names16[] = {
2927   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2928   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2929 };
2930 static const char *intel_names8[] = {
2931   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2932 };
2933 static const char *intel_names8rex[] = {
2934   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2935   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2936 };
2937 static const char *intel_names_seg[] = {
2938   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2939 };
2940 static const char *intel_index64 = "riz";
2941 static const char *intel_index32 = "eiz";
2942 static const char *intel_index16[] = {
2943   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2944 };
2945
2946 static const char *att_names64[] = {
2947   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2948   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2949 };
2950 static const char *att_names32[] = {
2951   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2952   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2953 };
2954 static const char *att_names16[] = {
2955   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2956   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2957 };
2958 static const char *att_names8[] = {
2959   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2960 };
2961 static const char *att_names8rex[] = {
2962   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2963   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2964 };
2965 static const char *att_names_seg[] = {
2966   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2967 };
2968 static const char *att_index64 = "%riz";
2969 static const char *att_index32 = "%eiz";
2970 static const char *att_index16[] = {
2971   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2972 };
2973
2974 static const char **names_mm;
2975 static const char *intel_names_mm[] = {
2976   "mm0", "mm1", "mm2", "mm3",
2977   "mm4", "mm5", "mm6", "mm7"
2978 };
2979 static const char *att_names_mm[] = {
2980   "%mm0", "%mm1", "%mm2", "%mm3",
2981   "%mm4", "%mm5", "%mm6", "%mm7"
2982 };
2983
2984 static const char *intel_names_bnd[] = {
2985   "bnd0", "bnd1", "bnd2", "bnd3"
2986 };
2987
2988 static const char *att_names_bnd[] = {
2989   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2990 };
2991
2992 static const char **names_xmm;
2993 static const char *intel_names_xmm[] = {
2994   "xmm0", "xmm1", "xmm2", "xmm3",
2995   "xmm4", "xmm5", "xmm6", "xmm7",
2996   "xmm8", "xmm9", "xmm10", "xmm11",
2997   "xmm12", "xmm13", "xmm14", "xmm15",
2998   "xmm16", "xmm17", "xmm18", "xmm19",
2999   "xmm20", "xmm21", "xmm22", "xmm23",
3000   "xmm24", "xmm25", "xmm26", "xmm27",
3001   "xmm28", "xmm29", "xmm30", "xmm31"
3002 };
3003 static const char *att_names_xmm[] = {
3004   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3005   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3006   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3007   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3008   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3009   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3010   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3011   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3012 };
3013
3014 static const char **names_ymm;
3015 static const char *intel_names_ymm[] = {
3016   "ymm0", "ymm1", "ymm2", "ymm3",
3017   "ymm4", "ymm5", "ymm6", "ymm7",
3018   "ymm8", "ymm9", "ymm10", "ymm11",
3019   "ymm12", "ymm13", "ymm14", "ymm15",
3020   "ymm16", "ymm17", "ymm18", "ymm19",
3021   "ymm20", "ymm21", "ymm22", "ymm23",
3022   "ymm24", "ymm25", "ymm26", "ymm27",
3023   "ymm28", "ymm29", "ymm30", "ymm31"
3024 };
3025 static const char *att_names_ymm[] = {
3026   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3027   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3028   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3029   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3030   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3031   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3032   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3033   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3034 };
3035
3036 static const char **names_zmm;
3037 static const char *intel_names_zmm[] = {
3038   "zmm0", "zmm1", "zmm2", "zmm3",
3039   "zmm4", "zmm5", "zmm6", "zmm7",
3040   "zmm8", "zmm9", "zmm10", "zmm11",
3041   "zmm12", "zmm13", "zmm14", "zmm15",
3042   "zmm16", "zmm17", "zmm18", "zmm19",
3043   "zmm20", "zmm21", "zmm22", "zmm23",
3044   "zmm24", "zmm25", "zmm26", "zmm27",
3045   "zmm28", "zmm29", "zmm30", "zmm31"
3046 };
3047 static const char *att_names_zmm[] = {
3048   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3049   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3050   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3051   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3052   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3053   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3054   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3055   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3056 };
3057
3058 static const char **names_mask;
3059 static const char *intel_names_mask[] = {
3060   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3061 };
3062 static const char *att_names_mask[] = {
3063   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3064 };
3065
3066 static const char *names_rounding[] =
3067 {
3068   "{rn-sae}",
3069   "{rd-sae}",
3070   "{ru-sae}",
3071   "{rz-sae}"
3072 };
3073
3074 static const struct dis386 reg_table[][8] = {
3075   /* REG_80 */
3076   {
3077     { "addA",   { Ebh1, Ib }, 0 },
3078     { "orA",    { Ebh1, Ib }, 0 },
3079     { "adcA",   { Ebh1, Ib }, 0 },
3080     { "sbbA",   { Ebh1, Ib }, 0 },
3081     { "andA",   { Ebh1, Ib }, 0 },
3082     { "subA",   { Ebh1, Ib }, 0 },
3083     { "xorA",   { Ebh1, Ib }, 0 },
3084     { "cmpA",   { Eb, Ib }, 0 },
3085   },
3086   /* REG_81 */
3087   {
3088     { "addQ",   { Evh1, Iv }, 0 },
3089     { "orQ",    { Evh1, Iv }, 0 },
3090     { "adcQ",   { Evh1, Iv }, 0 },
3091     { "sbbQ",   { Evh1, Iv }, 0 },
3092     { "andQ",   { Evh1, Iv }, 0 },
3093     { "subQ",   { Evh1, Iv }, 0 },
3094     { "xorQ",   { Evh1, Iv }, 0 },
3095     { "cmpQ",   { Ev, Iv }, 0 },
3096   },
3097   /* REG_83 */
3098   {
3099     { "addQ",   { Evh1, sIb }, 0 },
3100     { "orQ",    { Evh1, sIb }, 0 },
3101     { "adcQ",   { Evh1, sIb }, 0 },
3102     { "sbbQ",   { Evh1, sIb }, 0 },
3103     { "andQ",   { Evh1, sIb }, 0 },
3104     { "subQ",   { Evh1, sIb }, 0 },
3105     { "xorQ",   { Evh1, sIb }, 0 },
3106     { "cmpQ",   { Ev, sIb }, 0 },
3107   },
3108   /* REG_8F */
3109   {
3110     { "popU",   { stackEv }, 0 },
3111     { XOP_8F_TABLE (XOP_09) },
3112     { Bad_Opcode },
3113     { Bad_Opcode },
3114     { Bad_Opcode },
3115     { XOP_8F_TABLE (XOP_09) },
3116   },
3117   /* REG_C0 */
3118   {
3119     { "rolA",   { Eb, Ib }, 0 },
3120     { "rorA",   { Eb, Ib }, 0 },
3121     { "rclA",   { Eb, Ib }, 0 },
3122     { "rcrA",   { Eb, Ib }, 0 },
3123     { "shlA",   { Eb, Ib }, 0 },
3124     { "shrA",   { Eb, Ib }, 0 },
3125     { "shlA",   { Eb, Ib }, 0 },
3126     { "sarA",   { Eb, Ib }, 0 },
3127   },
3128   /* REG_C1 */
3129   {
3130     { "rolQ",   { Ev, Ib }, 0 },
3131     { "rorQ",   { Ev, Ib }, 0 },
3132     { "rclQ",   { Ev, Ib }, 0 },
3133     { "rcrQ",   { Ev, Ib }, 0 },
3134     { "shlQ",   { Ev, Ib }, 0 },
3135     { "shrQ",   { Ev, Ib }, 0 },
3136     { "shlQ",   { Ev, Ib }, 0 },
3137     { "sarQ",   { Ev, Ib }, 0 },
3138   },
3139   /* REG_C6 */
3140   {
3141     { "movA",   { Ebh3, Ib }, 0 },
3142     { Bad_Opcode },
3143     { Bad_Opcode },
3144     { Bad_Opcode },
3145     { Bad_Opcode },
3146     { Bad_Opcode },
3147     { Bad_Opcode },
3148     { MOD_TABLE (MOD_C6_REG_7) },
3149   },
3150   /* REG_C7 */
3151   {
3152     { "movQ",   { Evh3, Iv }, 0 },
3153     { Bad_Opcode },
3154     { Bad_Opcode },
3155     { Bad_Opcode },
3156     { Bad_Opcode },
3157     { Bad_Opcode },
3158     { Bad_Opcode },
3159     { MOD_TABLE (MOD_C7_REG_7) },
3160   },
3161   /* REG_D0 */
3162   {
3163     { "rolA",   { Eb, I1 }, 0 },
3164     { "rorA",   { Eb, I1 }, 0 },
3165     { "rclA",   { Eb, I1 }, 0 },
3166     { "rcrA",   { Eb, I1 }, 0 },
3167     { "shlA",   { Eb, I1 }, 0 },
3168     { "shrA",   { Eb, I1 }, 0 },
3169     { "shlA",   { Eb, I1 }, 0 },
3170     { "sarA",   { Eb, I1 }, 0 },
3171   },
3172   /* REG_D1 */
3173   {
3174     { "rolQ",   { Ev, I1 }, 0 },
3175     { "rorQ",   { Ev, I1 }, 0 },
3176     { "rclQ",   { Ev, I1 }, 0 },
3177     { "rcrQ",   { Ev, I1 }, 0 },
3178     { "shlQ",   { Ev, I1 }, 0 },
3179     { "shrQ",   { Ev, I1 }, 0 },
3180     { "shlQ",   { Ev, I1 }, 0 },
3181     { "sarQ",   { Ev, I1 }, 0 },
3182   },
3183   /* REG_D2 */
3184   {
3185     { "rolA",   { Eb, CL }, 0 },
3186     { "rorA",   { Eb, CL }, 0 },
3187     { "rclA",   { Eb, CL }, 0 },
3188     { "rcrA",   { Eb, CL }, 0 },
3189     { "shlA",   { Eb, CL }, 0 },
3190     { "shrA",   { Eb, CL }, 0 },
3191     { "shlA",   { Eb, CL }, 0 },
3192     { "sarA",   { Eb, CL }, 0 },
3193   },
3194   /* REG_D3 */
3195   {
3196     { "rolQ",   { Ev, CL }, 0 },
3197     { "rorQ",   { Ev, CL }, 0 },
3198     { "rclQ",   { Ev, CL }, 0 },
3199     { "rcrQ",   { Ev, CL }, 0 },
3200     { "shlQ",   { Ev, CL }, 0 },
3201     { "shrQ",   { Ev, CL }, 0 },
3202     { "shlQ",   { Ev, CL }, 0 },
3203     { "sarQ",   { Ev, CL }, 0 },
3204   },
3205   /* REG_F6 */
3206   {
3207     { "testA",  { Eb, Ib }, 0 },
3208     { "testA",  { Eb, Ib }, 0 },
3209     { "notA",   { Ebh1 }, 0 },
3210     { "negA",   { Ebh1 }, 0 },
3211     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3212     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3213     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3214     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3215   },
3216   /* REG_F7 */
3217   {
3218     { "testQ",  { Ev, Iv }, 0 },
3219     { "testQ",  { Ev, Iv }, 0 },
3220     { "notQ",   { Evh1 }, 0 },
3221     { "negQ",   { Evh1 }, 0 },
3222     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3223     { "imulQ",  { Ev }, 0 },
3224     { "divQ",   { Ev }, 0 },
3225     { "idivQ",  { Ev }, 0 },
3226   },
3227   /* REG_FE */
3228   {
3229     { "incA",   { Ebh1 }, 0 },
3230     { "decA",   { Ebh1 }, 0 },
3231   },
3232   /* REG_FF */
3233   {
3234     { "incQ",   { Evh1 }, 0 },
3235     { "decQ",   { Evh1 }, 0 },
3236     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3237     { MOD_TABLE (MOD_FF_REG_3) },
3238     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3239     { MOD_TABLE (MOD_FF_REG_5) },
3240     { "pushU",  { stackEv }, 0 },
3241     { Bad_Opcode },
3242   },
3243   /* REG_0F00 */
3244   {
3245     { "sldtD",  { Sv }, 0 },
3246     { "strD",   { Sv }, 0 },
3247     { "lldt",   { Ew }, 0 },
3248     { "ltr",    { Ew }, 0 },
3249     { "verr",   { Ew }, 0 },
3250     { "verw",   { Ew }, 0 },
3251     { Bad_Opcode },
3252     { Bad_Opcode },
3253   },
3254   /* REG_0F01 */
3255   {
3256     { MOD_TABLE (MOD_0F01_REG_0) },
3257     { MOD_TABLE (MOD_0F01_REG_1) },
3258     { MOD_TABLE (MOD_0F01_REG_2) },
3259     { MOD_TABLE (MOD_0F01_REG_3) },
3260     { "smswD",  { Sv }, 0 },
3261     { MOD_TABLE (MOD_0F01_REG_5) },
3262     { "lmsw",   { Ew }, 0 },
3263     { MOD_TABLE (MOD_0F01_REG_7) },
3264   },
3265   /* REG_0F0D */
3266   {
3267     { "prefetch",       { Mb }, 0 },
3268     { "prefetchw",      { Mb }, 0 },
3269     { "prefetchwt1",    { Mb }, 0 },
3270     { "prefetch",       { Mb }, 0 },
3271     { "prefetch",       { Mb }, 0 },
3272     { "prefetch",       { Mb }, 0 },
3273     { "prefetch",       { Mb }, 0 },
3274     { "prefetch",       { Mb }, 0 },
3275   },
3276   /* REG_0F18 */
3277   {
3278     { MOD_TABLE (MOD_0F18_REG_0) },
3279     { MOD_TABLE (MOD_0F18_REG_1) },
3280     { MOD_TABLE (MOD_0F18_REG_2) },
3281     { MOD_TABLE (MOD_0F18_REG_3) },
3282     { MOD_TABLE (MOD_0F18_REG_4) },
3283     { MOD_TABLE (MOD_0F18_REG_5) },
3284     { MOD_TABLE (MOD_0F18_REG_6) },
3285     { MOD_TABLE (MOD_0F18_REG_7) },
3286   },
3287   /* REG_0F1C_P_0_MOD_0 */
3288   {
3289     { "cldemote",       { Mb }, 0 },
3290     { "nopQ",           { Ev }, 0 },
3291     { "nopQ",           { Ev }, 0 },
3292     { "nopQ",           { Ev }, 0 },
3293     { "nopQ",           { Ev }, 0 },
3294     { "nopQ",           { Ev }, 0 },
3295     { "nopQ",           { Ev }, 0 },
3296     { "nopQ",           { Ev }, 0 },
3297   },
3298   /* REG_0F1E_P_1_MOD_3 */
3299   {
3300     { "nopQ",           { Ev }, 0 },
3301     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3302     { "nopQ",           { Ev }, 0 },
3303     { "nopQ",           { Ev }, 0 },
3304     { "nopQ",           { Ev }, 0 },
3305     { "nopQ",           { Ev }, 0 },
3306     { "nopQ",           { Ev }, 0 },
3307     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3308   },
3309   /* REG_0F71 */
3310   {
3311     { Bad_Opcode },
3312     { Bad_Opcode },
3313     { MOD_TABLE (MOD_0F71_REG_2) },
3314     { Bad_Opcode },
3315     { MOD_TABLE (MOD_0F71_REG_4) },
3316     { Bad_Opcode },
3317     { MOD_TABLE (MOD_0F71_REG_6) },
3318   },
3319   /* REG_0F72 */
3320   {
3321     { Bad_Opcode },
3322     { Bad_Opcode },
3323     { MOD_TABLE (MOD_0F72_REG_2) },
3324     { Bad_Opcode },
3325     { MOD_TABLE (MOD_0F72_REG_4) },
3326     { Bad_Opcode },
3327     { MOD_TABLE (MOD_0F72_REG_6) },
3328   },
3329   /* REG_0F73 */
3330   {
3331     { Bad_Opcode },
3332     { Bad_Opcode },
3333     { MOD_TABLE (MOD_0F73_REG_2) },
3334     { MOD_TABLE (MOD_0F73_REG_3) },
3335     { Bad_Opcode },
3336     { Bad_Opcode },
3337     { MOD_TABLE (MOD_0F73_REG_6) },
3338     { MOD_TABLE (MOD_0F73_REG_7) },
3339   },
3340   /* REG_0FA6 */
3341   {
3342     { "montmul",        { { OP_0f07, 0 } }, 0 },
3343     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3344     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3345   },
3346   /* REG_0FA7 */
3347   {
3348     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3349     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3350     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3351     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3352     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3353     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3354   },
3355   /* REG_0FAE */
3356   {
3357     { MOD_TABLE (MOD_0FAE_REG_0) },
3358     { MOD_TABLE (MOD_0FAE_REG_1) },
3359     { MOD_TABLE (MOD_0FAE_REG_2) },
3360     { MOD_TABLE (MOD_0FAE_REG_3) },
3361     { MOD_TABLE (MOD_0FAE_REG_4) },
3362     { MOD_TABLE (MOD_0FAE_REG_5) },
3363     { MOD_TABLE (MOD_0FAE_REG_6) },
3364     { MOD_TABLE (MOD_0FAE_REG_7) },
3365   },
3366   /* REG_0FBA */
3367   {
3368     { Bad_Opcode },
3369     { Bad_Opcode },
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { "btQ",    { Ev, Ib }, 0 },
3373     { "btsQ",   { Evh1, Ib }, 0 },
3374     { "btrQ",   { Evh1, Ib }, 0 },
3375     { "btcQ",   { Evh1, Ib }, 0 },
3376   },
3377   /* REG_0FC7 */
3378   {
3379     { Bad_Opcode },
3380     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3381     { Bad_Opcode },
3382     { MOD_TABLE (MOD_0FC7_REG_3) },
3383     { MOD_TABLE (MOD_0FC7_REG_4) },
3384     { MOD_TABLE (MOD_0FC7_REG_5) },
3385     { MOD_TABLE (MOD_0FC7_REG_6) },
3386     { MOD_TABLE (MOD_0FC7_REG_7) },
3387   },
3388   /* REG_VEX_0F71 */
3389   {
3390     { Bad_Opcode },
3391     { Bad_Opcode },
3392     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3393     { Bad_Opcode },
3394     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3395     { Bad_Opcode },
3396     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3397   },
3398   /* REG_VEX_0F72 */
3399   {
3400     { Bad_Opcode },
3401     { Bad_Opcode },
3402     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3403     { Bad_Opcode },
3404     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3405     { Bad_Opcode },
3406     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3407   },
3408   /* REG_VEX_0F73 */
3409   {
3410     { Bad_Opcode },
3411     { Bad_Opcode },
3412     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3413     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3414     { Bad_Opcode },
3415     { Bad_Opcode },
3416     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3417     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3418   },
3419   /* REG_VEX_0FAE */
3420   {
3421     { Bad_Opcode },
3422     { Bad_Opcode },
3423     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3424     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3425   },
3426   /* REG_VEX_0F38F3 */
3427   {
3428     { Bad_Opcode },
3429     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3430     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3431     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3432   },
3433   /* REG_XOP_LWPCB */
3434   {
3435     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3436     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3437   },
3438   /* REG_XOP_LWP */
3439   {
3440     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3441     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3442   },
3443   /* REG_XOP_TBM_01 */
3444   {
3445     { Bad_Opcode },
3446     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3447     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3448     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3449     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3450     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3451     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3452     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3453   },
3454   /* REG_XOP_TBM_02 */
3455   {
3456     { Bad_Opcode },
3457     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3458     { Bad_Opcode },
3459     { Bad_Opcode },
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3463   },
3464
3465 #include "i386-dis-evex-reg.h"
3466 };
3467
3468 static const struct dis386 prefix_table[][4] = {
3469   /* PREFIX_90 */
3470   {
3471     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3472     { "pause", { XX }, 0 },
3473     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3474     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3475   },
3476
3477   /* PREFIX_0F01_REG_3_RM_1 */
3478   {
3479     { "vmmcall",        { Skip_MODRM }, 0 },
3480     { "vmgexit",        { Skip_MODRM }, 0 },
3481     { Bad_Opcode },
3482     { "vmgexit",        { Skip_MODRM }, 0 },
3483   },
3484
3485   /* PREFIX_0F01_REG_5_MOD_0 */
3486   {
3487     { Bad_Opcode },
3488     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3489   },
3490
3491   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3492   {
3493     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3494     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3495     { Bad_Opcode },
3496     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3497   },
3498
3499   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3500   {
3501     { Bad_Opcode },
3502     { Bad_Opcode },
3503     { Bad_Opcode },
3504     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3505   },
3506
3507   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3508   {
3509     { Bad_Opcode },
3510     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3511   },
3512
3513   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3514   {
3515     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3516     { "mcommit",        { Skip_MODRM }, 0 },
3517   },
3518
3519   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3520   {
3521     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3522   },
3523
3524   /* PREFIX_0F09 */
3525   {
3526     { "wbinvd",   { XX }, 0 },
3527     { "wbnoinvd", { XX }, 0 },
3528   },
3529
3530   /* PREFIX_0F10 */
3531   {
3532     { "movups", { XM, EXx }, PREFIX_OPCODE },
3533     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3534     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3535     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3536   },
3537
3538   /* PREFIX_0F11 */
3539   {
3540     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3541     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3542     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3543     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3544   },
3545
3546   /* PREFIX_0F12 */
3547   {
3548     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3549     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3550     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3551     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3552   },
3553
3554   /* PREFIX_0F16 */
3555   {
3556     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3557     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3558     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3559   },
3560
3561   /* PREFIX_0F1A */
3562   {
3563     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3564     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3565     { "bndmov", { Gbnd, Ebnd }, 0 },
3566     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3567   },
3568
3569   /* PREFIX_0F1B */
3570   {
3571     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3572     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3573     { "bndmov", { EbndS, Gbnd }, 0 },
3574     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3575   },
3576
3577   /* PREFIX_0F1C */
3578   {
3579     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3580     { "nopQ",   { Ev }, PREFIX_OPCODE },
3581     { "nopQ",   { Ev }, PREFIX_OPCODE },
3582     { "nopQ",   { Ev }, PREFIX_OPCODE },
3583   },
3584
3585   /* PREFIX_0F1E */
3586   {
3587     { "nopQ",   { Ev }, PREFIX_OPCODE },
3588     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3589     { "nopQ",   { Ev }, PREFIX_OPCODE },
3590     { "nopQ",   { Ev }, PREFIX_OPCODE },
3591   },
3592
3593   /* PREFIX_0F2A */
3594   {
3595     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3596     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3597     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3598     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3599   },
3600
3601   /* PREFIX_0F2B */
3602   {
3603     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3604     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3605     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3606     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3607   },
3608
3609   /* PREFIX_0F2C */
3610   {
3611     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3612     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3613     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3614     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3615   },
3616
3617   /* PREFIX_0F2D */
3618   {
3619     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3620     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3621     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3622     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3623   },
3624
3625   /* PREFIX_0F2E */
3626   {
3627     { "ucomiss",{ XM, EXd }, 0 },
3628     { Bad_Opcode },
3629     { "ucomisd",{ XM, EXq }, 0 },
3630   },
3631
3632   /* PREFIX_0F2F */
3633   {
3634     { "comiss", { XM, EXd }, 0 },
3635     { Bad_Opcode },
3636     { "comisd", { XM, EXq }, 0 },
3637   },
3638
3639   /* PREFIX_0F51 */
3640   {
3641     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3642     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3643     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3644     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3645   },
3646
3647   /* PREFIX_0F52 */
3648   {
3649     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3650     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3651   },
3652
3653   /* PREFIX_0F53 */
3654   {
3655     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3656     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3657   },
3658
3659   /* PREFIX_0F58 */
3660   {
3661     { "addps", { XM, EXx }, PREFIX_OPCODE },
3662     { "addss", { XM, EXd }, PREFIX_OPCODE },
3663     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3664     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3665   },
3666
3667   /* PREFIX_0F59 */
3668   {
3669     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3670     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3671     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3672     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3673   },
3674
3675   /* PREFIX_0F5A */
3676   {
3677     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3678     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3679     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3680     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3681   },
3682
3683   /* PREFIX_0F5B */
3684   {
3685     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3686     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3687     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3688   },
3689
3690   /* PREFIX_0F5C */
3691   {
3692     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3693     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3694     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3695     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3696   },
3697
3698   /* PREFIX_0F5D */
3699   {
3700     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3701     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3702     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3703     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3704   },
3705
3706   /* PREFIX_0F5E */
3707   {
3708     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3709     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3710     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3711     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3712   },
3713
3714   /* PREFIX_0F5F */
3715   {
3716     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3717     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3718     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3719     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3720   },
3721
3722   /* PREFIX_0F60 */
3723   {
3724     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3725     { Bad_Opcode },
3726     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3727   },
3728
3729   /* PREFIX_0F61 */
3730   {
3731     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3732     { Bad_Opcode },
3733     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3734   },
3735
3736   /* PREFIX_0F62 */
3737   {
3738     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3739     { Bad_Opcode },
3740     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3741   },
3742
3743   /* PREFIX_0F6C */
3744   {
3745     { Bad_Opcode },
3746     { Bad_Opcode },
3747     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3748   },
3749
3750   /* PREFIX_0F6D */
3751   {
3752     { Bad_Opcode },
3753     { Bad_Opcode },
3754     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3755   },
3756
3757   /* PREFIX_0F6F */
3758   {
3759     { "movq",   { MX, EM }, PREFIX_OPCODE },
3760     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3761     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3762   },
3763
3764   /* PREFIX_0F70 */
3765   {
3766     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3767     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3768     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3769     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3770   },
3771
3772   /* PREFIX_0F73_REG_3 */
3773   {
3774     { Bad_Opcode },
3775     { Bad_Opcode },
3776     { "psrldq", { XS, Ib }, 0 },
3777   },
3778
3779   /* PREFIX_0F73_REG_7 */
3780   {
3781     { Bad_Opcode },
3782     { Bad_Opcode },
3783     { "pslldq", { XS, Ib }, 0 },
3784   },
3785
3786   /* PREFIX_0F78 */
3787   {
3788     {"vmread",  { Em, Gm }, 0 },
3789     { Bad_Opcode },
3790     {"extrq",   { XS, Ib, Ib }, 0 },
3791     {"insertq", { XM, XS, Ib, Ib }, 0 },
3792   },
3793
3794   /* PREFIX_0F79 */
3795   {
3796     {"vmwrite", { Gm, Em }, 0 },
3797     { Bad_Opcode },
3798     {"extrq",   { XM, XS }, 0 },
3799     {"insertq", { XM, XS }, 0 },
3800   },
3801
3802   /* PREFIX_0F7C */
3803   {
3804     { Bad_Opcode },
3805     { Bad_Opcode },
3806     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3807     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3808   },
3809
3810   /* PREFIX_0F7D */
3811   {
3812     { Bad_Opcode },
3813     { Bad_Opcode },
3814     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3815     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3816   },
3817
3818   /* PREFIX_0F7E */
3819   {
3820     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3821     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3822     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3823   },
3824
3825   /* PREFIX_0F7F */
3826   {
3827     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3828     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3829     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_0FAE_REG_0_MOD_3 */
3833   {
3834     { Bad_Opcode },
3835     { "rdfsbase", { Ev }, 0 },
3836   },
3837
3838   /* PREFIX_0FAE_REG_1_MOD_3 */
3839   {
3840     { Bad_Opcode },
3841     { "rdgsbase", { Ev }, 0 },
3842   },
3843
3844   /* PREFIX_0FAE_REG_2_MOD_3 */
3845   {
3846     { Bad_Opcode },
3847     { "wrfsbase", { Ev }, 0 },
3848   },
3849
3850   /* PREFIX_0FAE_REG_3_MOD_3 */
3851   {
3852     { Bad_Opcode },
3853     { "wrgsbase", { Ev }, 0 },
3854   },
3855
3856   /* PREFIX_0FAE_REG_4_MOD_0 */
3857   {
3858     { "xsave",  { FXSAVE }, 0 },
3859     { "ptwrite%LQ", { Edq }, 0 },
3860   },
3861
3862   /* PREFIX_0FAE_REG_4_MOD_3 */
3863   {
3864     { Bad_Opcode },
3865     { "ptwrite%LQ", { Edq }, 0 },
3866   },
3867
3868   /* PREFIX_0FAE_REG_5_MOD_0 */
3869   {
3870     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3871   },
3872
3873   /* PREFIX_0FAE_REG_5_MOD_3 */
3874   {
3875     { "lfence",         { Skip_MODRM }, 0 },
3876     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3877   },
3878
3879   /* PREFIX_0FAE_REG_6_MOD_0 */
3880   {
3881     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3882     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3883     { "clwb",   { Mb }, PREFIX_OPCODE },
3884   },
3885
3886   /* PREFIX_0FAE_REG_6_MOD_3 */
3887   {
3888     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3889     { "umonitor",       { Eva }, PREFIX_OPCODE },
3890     { "tpause", { Edq }, PREFIX_OPCODE },
3891     { "umwait", { Edq }, PREFIX_OPCODE },
3892   },
3893
3894   /* PREFIX_0FAE_REG_7_MOD_0 */
3895   {
3896     { "clflush",        { Mb }, 0 },
3897     { Bad_Opcode },
3898     { "clflushopt",     { Mb }, 0 },
3899   },
3900
3901   /* PREFIX_0FB8 */
3902   {
3903     { Bad_Opcode },
3904     { "popcntS", { Gv, Ev }, 0 },
3905   },
3906
3907   /* PREFIX_0FBC */
3908   {
3909     { "bsfS",   { Gv, Ev }, 0 },
3910     { "tzcntS", { Gv, Ev }, 0 },
3911     { "bsfS",   { Gv, Ev }, 0 },
3912   },
3913
3914   /* PREFIX_0FBD */
3915   {
3916     { "bsrS",   { Gv, Ev }, 0 },
3917     { "lzcntS", { Gv, Ev }, 0 },
3918     { "bsrS",   { Gv, Ev }, 0 },
3919   },
3920
3921   /* PREFIX_0FC2 */
3922   {
3923     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3924     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3925     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3926     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3927   },
3928
3929   /* PREFIX_0FC3_MOD_0 */
3930   {
3931     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3932   },
3933
3934   /* PREFIX_0FC7_REG_6_MOD_0 */
3935   {
3936     { "vmptrld",{ Mq }, 0 },
3937     { "vmxon",  { Mq }, 0 },
3938     { "vmclear",{ Mq }, 0 },
3939   },
3940
3941   /* PREFIX_0FC7_REG_6_MOD_3 */
3942   {
3943     { "rdrand", { Ev }, 0 },
3944     { Bad_Opcode },
3945     { "rdrand", { Ev }, 0 }
3946   },
3947
3948   /* PREFIX_0FC7_REG_7_MOD_3 */
3949   {
3950     { "rdseed", { Ev }, 0 },
3951     { "rdpid",  { Em }, 0 },
3952     { "rdseed", { Ev }, 0 },
3953   },
3954
3955   /* PREFIX_0FD0 */
3956   {
3957     { Bad_Opcode },
3958     { Bad_Opcode },
3959     { "addsubpd", { XM, EXx }, 0 },
3960     { "addsubps", { XM, EXx }, 0 },
3961   },
3962
3963   /* PREFIX_0FD6 */
3964   {
3965     { Bad_Opcode },
3966     { "movq2dq",{ XM, MS }, 0 },
3967     { "movq",   { EXqS, XM }, 0 },
3968     { "movdq2q",{ MX, XS }, 0 },
3969   },
3970
3971   /* PREFIX_0FE6 */
3972   {
3973     { Bad_Opcode },
3974     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3975     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3976     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_0FE7 */
3980   {
3981     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3982     { Bad_Opcode },
3983     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3984   },
3985
3986   /* PREFIX_0FF0 */
3987   {
3988     { Bad_Opcode },
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3992   },
3993
3994   /* PREFIX_0FF7 */
3995   {
3996     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3997     { Bad_Opcode },
3998     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3999   },
4000
4001   /* PREFIX_0F3810 */
4002   {
4003     { Bad_Opcode },
4004     { Bad_Opcode },
4005     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0F3814 */
4009   {
4010     { Bad_Opcode },
4011     { Bad_Opcode },
4012     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4013   },
4014
4015   /* PREFIX_0F3815 */
4016   {
4017     { Bad_Opcode },
4018     { Bad_Opcode },
4019     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4020   },
4021
4022   /* PREFIX_0F3817 */
4023   {
4024     { Bad_Opcode },
4025     { Bad_Opcode },
4026     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4027   },
4028
4029   /* PREFIX_0F3820 */
4030   {
4031     { Bad_Opcode },
4032     { Bad_Opcode },
4033     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4034   },
4035
4036   /* PREFIX_0F3821 */
4037   {
4038     { Bad_Opcode },
4039     { Bad_Opcode },
4040     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4041   },
4042
4043   /* PREFIX_0F3822 */
4044   {
4045     { Bad_Opcode },
4046     { Bad_Opcode },
4047     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4048   },
4049
4050   /* PREFIX_0F3823 */
4051   {
4052     { Bad_Opcode },
4053     { Bad_Opcode },
4054     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4055   },
4056
4057   /* PREFIX_0F3824 */
4058   {
4059     { Bad_Opcode },
4060     { Bad_Opcode },
4061     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4062   },
4063
4064   /* PREFIX_0F3825 */
4065   {
4066     { Bad_Opcode },
4067     { Bad_Opcode },
4068     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4069   },
4070
4071   /* PREFIX_0F3828 */
4072   {
4073     { Bad_Opcode },
4074     { Bad_Opcode },
4075     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4076   },
4077
4078   /* PREFIX_0F3829 */
4079   {
4080     { Bad_Opcode },
4081     { Bad_Opcode },
4082     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4083   },
4084
4085   /* PREFIX_0F382A */
4086   {
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4090   },
4091
4092   /* PREFIX_0F382B */
4093   {
4094     { Bad_Opcode },
4095     { Bad_Opcode },
4096     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4097   },
4098
4099   /* PREFIX_0F3830 */
4100   {
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4104   },
4105
4106   /* PREFIX_0F3831 */
4107   {
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0F3832 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4118   },
4119
4120   /* PREFIX_0F3833 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_0F3834 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F3835 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F3837 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0F3838 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4153   },
4154
4155   /* PREFIX_0F3839 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F383A */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4167   },
4168
4169   /* PREFIX_0F383B */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0F383C */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F383D */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4188   },
4189
4190   /* PREFIX_0F383E */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F383F */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4202   },
4203
4204   /* PREFIX_0F3840 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3841 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3880 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3881 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3882 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F38C8 */
4240   {
4241     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4242   },
4243
4244   /* PREFIX_0F38C9 */
4245   {
4246     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4247   },
4248
4249   /* PREFIX_0F38CA */
4250   {
4251     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F38CB */
4255   {
4256     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4257   },
4258
4259   /* PREFIX_0F38CC */
4260   {
4261     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4262   },
4263
4264   /* PREFIX_0F38CD */
4265   {
4266     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F38CF */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F38DB */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F38DC */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F38DD */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F38DE */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F38DF */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F38F0 */
4312   {
4313     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4314     { Bad_Opcode },
4315     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4316     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4317   },
4318
4319   /* PREFIX_0F38F1 */
4320   {
4321     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4322     { Bad_Opcode },
4323     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4324     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4325   },
4326
4327   /* PREFIX_0F38F5 */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4332   },
4333
4334   /* PREFIX_0F38F6 */
4335   {
4336     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4337     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4338     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4339     { Bad_Opcode },
4340   },
4341
4342   /* PREFIX_0F38F8 */
4343   {
4344     { Bad_Opcode },
4345     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4346     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4347     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4348   },
4349
4350   /* PREFIX_0F38F9 */
4351   {
4352     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4353   },
4354
4355   /* PREFIX_0F3A08 */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F3A09 */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4367   },
4368
4369   /* PREFIX_0F3A0A */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F3A0B */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F3A0C */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F3A0D */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4395   },
4396
4397   /* PREFIX_0F3A0E */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4402   },
4403
4404   /* PREFIX_0F3A14 */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4409   },
4410
4411   /* PREFIX_0F3A15 */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4416   },
4417
4418   /* PREFIX_0F3A16 */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4423   },
4424
4425   /* PREFIX_0F3A17 */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4430   },
4431
4432   /* PREFIX_0F3A20 */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F3A21 */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4444   },
4445
4446   /* PREFIX_0F3A22 */
4447   {
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4451   },
4452
4453   /* PREFIX_0F3A40 */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4458   },
4459
4460   /* PREFIX_0F3A41 */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4465   },
4466
4467   /* PREFIX_0F3A42 */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4472   },
4473
4474   /* PREFIX_0F3A44 */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4479   },
4480
4481   /* PREFIX_0F3A60 */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4486   },
4487
4488   /* PREFIX_0F3A61 */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4493   },
4494
4495   /* PREFIX_0F3A62 */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F3A63 */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4507   },
4508
4509   /* PREFIX_0F3ACC */
4510   {
4511     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_0F3ACE */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4519   },
4520
4521   /* PREFIX_0F3ACF */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4526   },
4527
4528   /* PREFIX_0F3ADF */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4533   },
4534
4535   /* PREFIX_VEX_0F10 */
4536   {
4537     { "vmovups",        { XM, EXx }, 0 },
4538     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4539     { "vmovupd",        { XM, EXx }, 0 },
4540     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4541   },
4542
4543   /* PREFIX_VEX_0F11 */
4544   {
4545     { "vmovups",        { EXxS, XM }, 0 },
4546     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4547     { "vmovupd",        { EXxS, XM }, 0 },
4548     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4549   },
4550
4551   /* PREFIX_VEX_0F12 */
4552   {
4553     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4554     { "vmovsldup",      { XM, EXx }, 0 },
4555     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4556     { "vmovddup",       { XM, EXymmq }, 0 },
4557   },
4558
4559   /* PREFIX_VEX_0F16 */
4560   {
4561     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4562     { "vmovshdup",      { XM, EXx }, 0 },
4563     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4564   },
4565
4566   /* PREFIX_VEX_0F2A */
4567   {
4568     { Bad_Opcode },
4569     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4570     { Bad_Opcode },
4571     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4572   },
4573
4574   /* PREFIX_VEX_0F2C */
4575   {
4576     { Bad_Opcode },
4577     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4578     { Bad_Opcode },
4579     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4580   },
4581
4582   /* PREFIX_VEX_0F2D */
4583   {
4584     { Bad_Opcode },
4585     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4586     { Bad_Opcode },
4587     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4588   },
4589
4590   /* PREFIX_VEX_0F2E */
4591   {
4592     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4593     { Bad_Opcode },
4594     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4595   },
4596
4597   /* PREFIX_VEX_0F2F */
4598   {
4599     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4600     { Bad_Opcode },
4601     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4602   },
4603
4604   /* PREFIX_VEX_0F41 */
4605   {
4606     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4607     { Bad_Opcode },
4608     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4609   },
4610
4611   /* PREFIX_VEX_0F42 */
4612   {
4613     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4614     { Bad_Opcode },
4615     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4616   },
4617
4618   /* PREFIX_VEX_0F44 */
4619   {
4620     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4621     { Bad_Opcode },
4622     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4623   },
4624
4625   /* PREFIX_VEX_0F45 */
4626   {
4627     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4628     { Bad_Opcode },
4629     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4630   },
4631
4632   /* PREFIX_VEX_0F46 */
4633   {
4634     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4635     { Bad_Opcode },
4636     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4637   },
4638
4639   /* PREFIX_VEX_0F47 */
4640   {
4641     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4642     { Bad_Opcode },
4643     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4644   },
4645
4646   /* PREFIX_VEX_0F4A */
4647   {
4648     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4649     { Bad_Opcode },
4650     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4651   },
4652
4653   /* PREFIX_VEX_0F4B */
4654   {
4655     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4656     { Bad_Opcode },
4657     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4658   },
4659
4660   /* PREFIX_VEX_0F51 */
4661   {
4662     { "vsqrtps",        { XM, EXx }, 0 },
4663     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4664     { "vsqrtpd",        { XM, EXx }, 0 },
4665     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4666   },
4667
4668   /* PREFIX_VEX_0F52 */
4669   {
4670     { "vrsqrtps",       { XM, EXx }, 0 },
4671     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4672   },
4673
4674   /* PREFIX_VEX_0F53 */
4675   {
4676     { "vrcpps",         { XM, EXx }, 0 },
4677     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4678   },
4679
4680   /* PREFIX_VEX_0F58 */
4681   {
4682     { "vaddps",         { XM, Vex, EXx }, 0 },
4683     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4684     { "vaddpd",         { XM, Vex, EXx }, 0 },
4685     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4686   },
4687
4688   /* PREFIX_VEX_0F59 */
4689   {
4690     { "vmulps",         { XM, Vex, EXx }, 0 },
4691     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4692     { "vmulpd",         { XM, Vex, EXx }, 0 },
4693     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4694   },
4695
4696   /* PREFIX_VEX_0F5A */
4697   {
4698     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4699     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4700     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4701     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4702   },
4703
4704   /* PREFIX_VEX_0F5B */
4705   {
4706     { "vcvtdq2ps",      { XM, EXx }, 0 },
4707     { "vcvttps2dq",     { XM, EXx }, 0 },
4708     { "vcvtps2dq",      { XM, EXx }, 0 },
4709   },
4710
4711   /* PREFIX_VEX_0F5C */
4712   {
4713     { "vsubps",         { XM, Vex, EXx }, 0 },
4714     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4715     { "vsubpd",         { XM, Vex, EXx }, 0 },
4716     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4717   },
4718
4719   /* PREFIX_VEX_0F5D */
4720   {
4721     { "vminps",         { XM, Vex, EXx }, 0 },
4722     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4723     { "vminpd",         { XM, Vex, EXx }, 0 },
4724     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4725   },
4726
4727   /* PREFIX_VEX_0F5E */
4728   {
4729     { "vdivps",         { XM, Vex, EXx }, 0 },
4730     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4731     { "vdivpd",         { XM, Vex, EXx }, 0 },
4732     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4733   },
4734
4735   /* PREFIX_VEX_0F5F */
4736   {
4737     { "vmaxps",         { XM, Vex, EXx }, 0 },
4738     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4739     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4740     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4741   },
4742
4743   /* PREFIX_VEX_0F60 */
4744   {
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4748   },
4749
4750   /* PREFIX_VEX_0F61 */
4751   {
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4755   },
4756
4757   /* PREFIX_VEX_0F62 */
4758   {
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4762   },
4763
4764   /* PREFIX_VEX_0F63 */
4765   {
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4769   },
4770
4771   /* PREFIX_VEX_0F64 */
4772   {
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4776   },
4777
4778   /* PREFIX_VEX_0F65 */
4779   {
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4783   },
4784
4785   /* PREFIX_VEX_0F66 */
4786   {
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4790   },
4791
4792   /* PREFIX_VEX_0F67 */
4793   {
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4797   },
4798
4799   /* PREFIX_VEX_0F68 */
4800   {
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4804   },
4805
4806   /* PREFIX_VEX_0F69 */
4807   {
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4811   },
4812
4813   /* PREFIX_VEX_0F6A */
4814   {
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4818   },
4819
4820   /* PREFIX_VEX_0F6B */
4821   {
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4825   },
4826
4827   /* PREFIX_VEX_0F6C */
4828   {
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4832   },
4833
4834   /* PREFIX_VEX_0F6D */
4835   {
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4839   },
4840
4841   /* PREFIX_VEX_0F6E */
4842   {
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4846   },
4847
4848   /* PREFIX_VEX_0F6F */
4849   {
4850     { Bad_Opcode },
4851     { "vmovdqu",        { XM, EXx }, 0 },
4852     { "vmovdqa",        { XM, EXx }, 0 },
4853   },
4854
4855   /* PREFIX_VEX_0F70 */
4856   {
4857     { Bad_Opcode },
4858     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4859     { "vpshufd",        { XM, EXx, Ib }, 0 },
4860     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F71_REG_2 */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4868   },
4869
4870   /* PREFIX_VEX_0F71_REG_4 */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { "vpsraw",         { Vex, XS, Ib }, 0 },
4875   },
4876
4877   /* PREFIX_VEX_0F71_REG_6 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { "vpsllw",         { Vex, XS, Ib }, 0 },
4882   },
4883
4884   /* PREFIX_VEX_0F72_REG_2 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { "vpsrld",         { Vex, XS, Ib }, 0 },
4889   },
4890
4891   /* PREFIX_VEX_0F72_REG_4 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { "vpsrad",         { Vex, XS, Ib }, 0 },
4896   },
4897
4898   /* PREFIX_VEX_0F72_REG_6 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "vpslld",         { Vex, XS, Ib }, 0 },
4903   },
4904
4905   /* PREFIX_VEX_0F73_REG_2 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4910   },
4911
4912   /* PREFIX_VEX_0F73_REG_3 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { "vpsrldq",        { Vex, XS, Ib }, 0 },
4917   },
4918
4919   /* PREFIX_VEX_0F73_REG_6 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { "vpsllq",         { Vex, XS, Ib }, 0 },
4924   },
4925
4926   /* PREFIX_VEX_0F73_REG_7 */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { "vpslldq",        { Vex, XS, Ib }, 0 },
4931   },
4932
4933   /* PREFIX_VEX_0F74 */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
4938   },
4939
4940   /* PREFIX_VEX_0F75 */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
4945   },
4946
4947   /* PREFIX_VEX_0F76 */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
4952   },
4953
4954   /* PREFIX_VEX_0F77 */
4955   {
4956     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
4957   },
4958
4959   /* PREFIX_VEX_0F7C */
4960   {
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { "vhaddpd",        { XM, Vex, EXx }, 0 },
4964     { "vhaddps",        { XM, Vex, EXx }, 0 },
4965   },
4966
4967   /* PREFIX_VEX_0F7D */
4968   {
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { "vhsubpd",        { XM, Vex, EXx }, 0 },
4972     { "vhsubps",        { XM, Vex, EXx }, 0 },
4973   },
4974
4975   /* PREFIX_VEX_0F7E */
4976   {
4977     { Bad_Opcode },
4978     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4979     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_0F7F */
4983   {
4984     { Bad_Opcode },
4985     { "vmovdqu",        { EXxS, XM }, 0 },
4986     { "vmovdqa",        { EXxS, XM }, 0 },
4987   },
4988
4989   /* PREFIX_VEX_0F90 */
4990   {
4991     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4992     { Bad_Opcode },
4993     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
4994   },
4995
4996   /* PREFIX_VEX_0F91 */
4997   {
4998     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4999     { Bad_Opcode },
5000     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5001   },
5002
5003   /* PREFIX_VEX_0F92 */
5004   {
5005     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5006     { Bad_Opcode },
5007     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5008     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5009   },
5010
5011   /* PREFIX_VEX_0F93 */
5012   {
5013     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5014     { Bad_Opcode },
5015     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5016     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5017   },
5018
5019   /* PREFIX_VEX_0F98 */
5020   {
5021     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5022     { Bad_Opcode },
5023     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5024   },
5025
5026   /* PREFIX_VEX_0F99 */
5027   {
5028     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5029     { Bad_Opcode },
5030     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5031   },
5032
5033   /* PREFIX_VEX_0FC2 */
5034   {
5035     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5036     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5037     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5038     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5039   },
5040
5041   /* PREFIX_VEX_0FC4 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5046   },
5047
5048   /* PREFIX_VEX_0FC5 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5053   },
5054
5055   /* PREFIX_VEX_0FD0 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5060     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5061   },
5062
5063   /* PREFIX_VEX_0FD1 */
5064   {
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5068   },
5069
5070   /* PREFIX_VEX_0FD2 */
5071   {
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5075   },
5076
5077   /* PREFIX_VEX_0FD3 */
5078   {
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5082   },
5083
5084   /* PREFIX_VEX_0FD4 */
5085   {
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { "vpaddq",         { XM, Vex, EXx }, 0 },
5089   },
5090
5091   /* PREFIX_VEX_0FD5 */
5092   {
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { "vpmullw",        { XM, Vex, EXx }, 0 },
5096   },
5097
5098   /* PREFIX_VEX_0FD6 */
5099   {
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5103   },
5104
5105   /* PREFIX_VEX_0FD7 */
5106   {
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5110   },
5111
5112   /* PREFIX_VEX_0FD8 */
5113   {
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5117   },
5118
5119   /* PREFIX_VEX_0FD9 */
5120   {
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5124   },
5125
5126   /* PREFIX_VEX_0FDA */
5127   {
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { "vpminub",        { XM, Vex, EXx }, 0 },
5131   },
5132
5133   /* PREFIX_VEX_0FDB */
5134   {
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { "vpand",          { XM, Vex, EXx }, 0 },
5138   },
5139
5140   /* PREFIX_VEX_0FDC */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5145   },
5146
5147   /* PREFIX_VEX_0FDD */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5152   },
5153
5154   /* PREFIX_VEX_0FDE */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5159   },
5160
5161   /* PREFIX_VEX_0FDF */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { "vpandn",         { XM, Vex, EXx }, 0 },
5166   },
5167
5168   /* PREFIX_VEX_0FE0 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { "vpavgb",         { XM, Vex, EXx }, 0 },
5173   },
5174
5175   /* PREFIX_VEX_0FE1 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5180   },
5181
5182   /* PREFIX_VEX_0FE2 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5187   },
5188
5189   /* PREFIX_VEX_0FE3 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { "vpavgw",         { XM, Vex, EXx }, 0 },
5194   },
5195
5196   /* PREFIX_VEX_0FE4 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5201   },
5202
5203   /* PREFIX_VEX_0FE5 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5208   },
5209
5210   /* PREFIX_VEX_0FE6 */
5211   {
5212     { Bad_Opcode },
5213     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5214     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5215     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5216   },
5217
5218   /* PREFIX_VEX_0FE7 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5223   },
5224
5225   /* PREFIX_VEX_0FE8 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5230   },
5231
5232   /* PREFIX_VEX_0FE9 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5237   },
5238
5239   /* PREFIX_VEX_0FEA */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { "vpminsw",        { XM, Vex, EXx }, 0 },
5244   },
5245
5246   /* PREFIX_VEX_0FEB */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vpor",           { XM, Vex, EXx }, 0 },
5251   },
5252
5253   /* PREFIX_VEX_0FEC */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5258   },
5259
5260   /* PREFIX_VEX_0FED */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5265   },
5266
5267   /* PREFIX_VEX_0FEE */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5272   },
5273
5274   /* PREFIX_VEX_0FEF */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { "vpxor",          { XM, Vex, EXx }, 0 },
5279   },
5280
5281   /* PREFIX_VEX_0FF0 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5287   },
5288
5289   /* PREFIX_VEX_0FF1 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FF2 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5301   },
5302
5303   /* PREFIX_VEX_0FF3 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5308   },
5309
5310   /* PREFIX_VEX_0FF4 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5315   },
5316
5317   /* PREFIX_VEX_0FF5 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5322   },
5323
5324   /* PREFIX_VEX_0FF6 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5329   },
5330
5331   /* PREFIX_VEX_0FF7 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5336   },
5337
5338   /* PREFIX_VEX_0FF8 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { "vpsubb",         { XM, Vex, EXx }, 0 },
5343   },
5344
5345   /* PREFIX_VEX_0FF9 */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { "vpsubw",         { XM, Vex, EXx }, 0 },
5350   },
5351
5352   /* PREFIX_VEX_0FFA */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { "vpsubd",         { XM, Vex, EXx }, 0 },
5357   },
5358
5359   /* PREFIX_VEX_0FFB */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { "vpsubq",         { XM, Vex, EXx }, 0 },
5364   },
5365
5366   /* PREFIX_VEX_0FFC */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { "vpaddb",         { XM, Vex, EXx }, 0 },
5371   },
5372
5373   /* PREFIX_VEX_0FFD */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { "vpaddw",         { XM, Vex, EXx }, 0 },
5378   },
5379
5380   /* PREFIX_VEX_0FFE */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { "vpaddd",         { XM, Vex, EXx }, 0 },
5385   },
5386
5387   /* PREFIX_VEX_0F3800 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { "vpshufb",        { XM, Vex, EXx }, 0 },
5392   },
5393
5394   /* PREFIX_VEX_0F3801 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { "vphaddw",        { XM, Vex, EXx }, 0 },
5399   },
5400
5401   /* PREFIX_VEX_0F3802 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { "vphaddd",        { XM, Vex, EXx }, 0 },
5406   },
5407
5408   /* PREFIX_VEX_0F3803 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5413   },
5414
5415   /* PREFIX_VEX_0F3804 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5420   },
5421
5422   /* PREFIX_VEX_0F3805 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { "vphsubw",        { XM, Vex, EXx }, 0 },
5427   },
5428
5429   /* PREFIX_VEX_0F3806 */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { "vphsubd",        { XM, Vex, EXx }, 0 },
5434   },
5435
5436   /* PREFIX_VEX_0F3807 */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5441   },
5442
5443   /* PREFIX_VEX_0F3808 */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { "vpsignb",        { XM, Vex, EXx }, 0 },
5448   },
5449
5450   /* PREFIX_VEX_0F3809 */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { "vpsignw",        { XM, Vex, EXx }, 0 },
5455   },
5456
5457   /* PREFIX_VEX_0F380A */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { "vpsignd",        { XM, Vex, EXx }, 0 },
5462   },
5463
5464   /* PREFIX_VEX_0F380B */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5469   },
5470
5471   /* PREFIX_VEX_0F380C */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5476   },
5477
5478   /* PREFIX_VEX_0F380D */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5483   },
5484
5485   /* PREFIX_VEX_0F380E */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5490   },
5491
5492   /* PREFIX_VEX_0F380F */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5497   },
5498
5499   /* PREFIX_VEX_0F3813 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5504   },
5505
5506   /* PREFIX_VEX_0F3816 */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5511   },
5512
5513   /* PREFIX_VEX_0F3817 */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { "vptest",         { XM, EXx }, 0 },
5518   },
5519
5520   /* PREFIX_VEX_0F3818 */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5525   },
5526
5527   /* PREFIX_VEX_0F3819 */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5532   },
5533
5534   /* PREFIX_VEX_0F381A */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5539   },
5540
5541   /* PREFIX_VEX_0F381C */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { "vpabsb",         { XM, EXx }, 0 },
5546   },
5547
5548   /* PREFIX_VEX_0F381D */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { "vpabsw",         { XM, EXx }, 0 },
5553   },
5554
5555   /* PREFIX_VEX_0F381E */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { "vpabsd",         { XM, EXx }, 0 },
5560   },
5561
5562   /* PREFIX_VEX_0F3820 */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5567   },
5568
5569   /* PREFIX_VEX_0F3821 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5574   },
5575
5576   /* PREFIX_VEX_0F3822 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5581   },
5582
5583   /* PREFIX_VEX_0F3823 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5588   },
5589
5590   /* PREFIX_VEX_0F3824 */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5595   },
5596
5597   /* PREFIX_VEX_0F3825 */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5602   },
5603
5604   /* PREFIX_VEX_0F3828 */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5609   },
5610
5611   /* PREFIX_VEX_0F3829 */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5616   },
5617
5618   /* PREFIX_VEX_0F382A */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F382B */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5630   },
5631
5632   /* PREFIX_VEX_0F382C */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F382D */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5644   },
5645
5646   /* PREFIX_VEX_0F382E */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5651   },
5652
5653   /* PREFIX_VEX_0F382F */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5658   },
5659
5660   /* PREFIX_VEX_0F3830 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5665   },
5666
5667   /* PREFIX_VEX_0F3831 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5672   },
5673
5674   /* PREFIX_VEX_0F3832 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5679   },
5680
5681   /* PREFIX_VEX_0F3833 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5686   },
5687
5688   /* PREFIX_VEX_0F3834 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5693   },
5694
5695   /* PREFIX_VEX_0F3835 */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5700   },
5701
5702   /* PREFIX_VEX_0F3836 */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5707   },
5708
5709   /* PREFIX_VEX_0F3837 */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5714   },
5715
5716   /* PREFIX_VEX_0F3838 */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { "vpminsb",        { XM, Vex, EXx }, 0 },
5721   },
5722
5723   /* PREFIX_VEX_0F3839 */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { "vpminsd",        { XM, Vex, EXx }, 0 },
5728   },
5729
5730   /* PREFIX_VEX_0F383A */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { "vpminuw",        { XM, Vex, EXx }, 0 },
5735   },
5736
5737   /* PREFIX_VEX_0F383B */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { "vpminud",        { XM, Vex, EXx }, 0 },
5742   },
5743
5744   /* PREFIX_VEX_0F383C */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5749   },
5750
5751   /* PREFIX_VEX_0F383D */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5756   },
5757
5758   /* PREFIX_VEX_0F383E */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5763   },
5764
5765   /* PREFIX_VEX_0F383F */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5770   },
5771
5772   /* PREFIX_VEX_0F3840 */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { "vpmulld",        { XM, Vex, EXx }, 0 },
5777   },
5778
5779   /* PREFIX_VEX_0F3841 */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5784   },
5785
5786   /* PREFIX_VEX_0F3845 */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5791   },
5792
5793   /* PREFIX_VEX_0F3846 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5798   },
5799
5800   /* PREFIX_VEX_0F3847 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5805   },
5806
5807   /* PREFIX_VEX_0F3858 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5812   },
5813
5814   /* PREFIX_VEX_0F3859 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5819   },
5820
5821   /* PREFIX_VEX_0F385A */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5826   },
5827
5828   /* PREFIX_VEX_0F3878 */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5833   },
5834
5835   /* PREFIX_VEX_0F3879 */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5840   },
5841
5842   /* PREFIX_VEX_0F388C */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5847   },
5848
5849   /* PREFIX_VEX_0F388E */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5854   },
5855
5856   /* PREFIX_VEX_0F3890 */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5861   },
5862
5863   /* PREFIX_VEX_0F3891 */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5868   },
5869
5870   /* PREFIX_VEX_0F3892 */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5875   },
5876
5877   /* PREFIX_VEX_0F3893 */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5882   },
5883
5884   /* PREFIX_VEX_0F3896 */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5889   },
5890
5891   /* PREFIX_VEX_0F3897 */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5896   },
5897
5898   /* PREFIX_VEX_0F3898 */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5903   },
5904
5905   /* PREFIX_VEX_0F3899 */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5910   },
5911
5912   /* PREFIX_VEX_0F389A */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5917   },
5918
5919   /* PREFIX_VEX_0F389B */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5924   },
5925
5926   /* PREFIX_VEX_0F389C */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5931   },
5932
5933   /* PREFIX_VEX_0F389D */
5934   {
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5938   },
5939
5940   /* PREFIX_VEX_0F389E */
5941   {
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5945   },
5946
5947   /* PREFIX_VEX_0F389F */
5948   {
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5952   },
5953
5954   /* PREFIX_VEX_0F38A6 */
5955   {
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5959     { Bad_Opcode },
5960   },
5961
5962   /* PREFIX_VEX_0F38A7 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5967   },
5968
5969   /* PREFIX_VEX_0F38A8 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5974   },
5975
5976   /* PREFIX_VEX_0F38A9 */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5981   },
5982
5983   /* PREFIX_VEX_0F38AA */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
5988   },
5989
5990   /* PREFIX_VEX_0F38AB */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5995   },
5996
5997   /* PREFIX_VEX_0F38AC */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F38AD */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F38AE */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F38AF */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F38B6 */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F38B7 */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F38B8 */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F38B9 */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F38BA */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F38BB */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F38BC */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F38BD */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6079   },
6080
6081   /* PREFIX_VEX_0F38BE */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F38BF */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6093   },
6094
6095   /* PREFIX_VEX_0F38CF */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6100   },
6101
6102   /* PREFIX_VEX_0F38DB */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6107   },
6108
6109   /* PREFIX_VEX_0F38DC */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { "vaesenc",        { XM, Vex, EXx }, 0 },
6114   },
6115
6116   /* PREFIX_VEX_0F38DD */
6117   {
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6121   },
6122
6123   /* PREFIX_VEX_0F38DE */
6124   {
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { "vaesdec",        { XM, Vex, EXx }, 0 },
6128   },
6129
6130   /* PREFIX_VEX_0F38DF */
6131   {
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6135   },
6136
6137   /* PREFIX_VEX_0F38F2 */
6138   {
6139     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6140   },
6141
6142   /* PREFIX_VEX_0F38F3_REG_1 */
6143   {
6144     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6145   },
6146
6147   /* PREFIX_VEX_0F38F3_REG_2 */
6148   {
6149     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6150   },
6151
6152   /* PREFIX_VEX_0F38F3_REG_3 */
6153   {
6154     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6155   },
6156
6157   /* PREFIX_VEX_0F38F5 */
6158   {
6159     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6160     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6161     { Bad_Opcode },
6162     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6163   },
6164
6165   /* PREFIX_VEX_0F38F6 */
6166   {
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6171   },
6172
6173   /* PREFIX_VEX_0F38F7 */
6174   {
6175     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6176     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6177     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6178     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6179   },
6180
6181   /* PREFIX_VEX_0F3A00 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6186   },
6187
6188   /* PREFIX_VEX_0F3A01 */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6193   },
6194
6195   /* PREFIX_VEX_0F3A02 */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6200   },
6201
6202   /* PREFIX_VEX_0F3A04 */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6207   },
6208
6209   /* PREFIX_VEX_0F3A05 */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6214   },
6215
6216   /* PREFIX_VEX_0F3A06 */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6221   },
6222
6223   /* PREFIX_VEX_0F3A08 */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vroundps",       { XM, EXx, Ib }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F3A09 */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vroundpd",       { XM, EXx, Ib }, 0 },
6235   },
6236
6237   /* PREFIX_VEX_0F3A0A */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6242   },
6243
6244   /* PREFIX_VEX_0F3A0B */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6249   },
6250
6251   /* PREFIX_VEX_0F3A0C */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6256   },
6257
6258   /* PREFIX_VEX_0F3A0D */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6263   },
6264
6265   /* PREFIX_VEX_0F3A0E */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6270   },
6271
6272   /* PREFIX_VEX_0F3A0F */
6273   {
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6277   },
6278
6279   /* PREFIX_VEX_0F3A14 */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6284   },
6285
6286   /* PREFIX_VEX_0F3A15 */
6287   {
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6291   },
6292
6293   /* PREFIX_VEX_0F3A16 */
6294   {
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6298   },
6299
6300   /* PREFIX_VEX_0F3A17 */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6305   },
6306
6307   /* PREFIX_VEX_0F3A18 */
6308   {
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6312   },
6313
6314   /* PREFIX_VEX_0F3A19 */
6315   {
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6319   },
6320
6321   /* PREFIX_VEX_0F3A1D */
6322   {
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6326   },
6327
6328   /* PREFIX_VEX_0F3A20 */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6333   },
6334
6335   /* PREFIX_VEX_0F3A21 */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6340   },
6341
6342   /* PREFIX_VEX_0F3A22 */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6347   },
6348
6349   /* PREFIX_VEX_0F3A30 */
6350   {
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6354   },
6355
6356   /* PREFIX_VEX_0F3A31 */
6357   {
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6361   },
6362
6363   /* PREFIX_VEX_0F3A32 */
6364   {
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6368   },
6369
6370   /* PREFIX_VEX_0F3A33 */
6371   {
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6375   },
6376
6377   /* PREFIX_VEX_0F3A38 */
6378   {
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6382   },
6383
6384   /* PREFIX_VEX_0F3A39 */
6385   {
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6389   },
6390
6391   /* PREFIX_VEX_0F3A40 */
6392   {
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6396   },
6397
6398   /* PREFIX_VEX_0F3A41 */
6399   {
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6403   },
6404
6405   /* PREFIX_VEX_0F3A42 */
6406   {
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6410   },
6411
6412   /* PREFIX_VEX_0F3A44 */
6413   {
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6417   },
6418
6419   /* PREFIX_VEX_0F3A46 */
6420   {
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6424   },
6425
6426   /* PREFIX_VEX_0F3A48 */
6427   {
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6431   },
6432
6433   /* PREFIX_VEX_0F3A49 */
6434   {
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6438   },
6439
6440   /* PREFIX_VEX_0F3A4A */
6441   {
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6445   },
6446
6447   /* PREFIX_VEX_0F3A4B */
6448   {
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6452   },
6453
6454   /* PREFIX_VEX_0F3A4C */
6455   {
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6459   },
6460
6461   /* PREFIX_VEX_0F3A5C */
6462   {
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6466   },
6467
6468   /* PREFIX_VEX_0F3A5D */
6469   {
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6473   },
6474
6475   /* PREFIX_VEX_0F3A5E */
6476   {
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6480   },
6481
6482   /* PREFIX_VEX_0F3A5F */
6483   {
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6487   },
6488
6489   /* PREFIX_VEX_0F3A60 */
6490   {
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6494     { Bad_Opcode },
6495   },
6496
6497   /* PREFIX_VEX_0F3A61 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A62 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A63 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A68 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6523   },
6524
6525   /* PREFIX_VEX_0F3A69 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6530   },
6531
6532   /* PREFIX_VEX_0F3A6A */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A6B */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A6C */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6551   },
6552
6553   /* PREFIX_VEX_0F3A6D */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6558   },
6559
6560   /* PREFIX_VEX_0F3A6E */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6565   },
6566
6567   /* PREFIX_VEX_0F3A6F */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A78 */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6579   },
6580
6581   /* PREFIX_VEX_0F3A79 */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6586   },
6587
6588   /* PREFIX_VEX_0F3A7A */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6593   },
6594
6595   /* PREFIX_VEX_0F3A7B */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6600   },
6601
6602   /* PREFIX_VEX_0F3A7C */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6607     { Bad_Opcode },
6608   },
6609
6610   /* PREFIX_VEX_0F3A7D */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6615   },
6616
6617   /* PREFIX_VEX_0F3A7E */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6622   },
6623
6624   /* PREFIX_VEX_0F3A7F */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6629   },
6630
6631   /* PREFIX_VEX_0F3ACE */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6636   },
6637
6638   /* PREFIX_VEX_0F3ACF */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6643   },
6644
6645   /* PREFIX_VEX_0F3ADF */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6650   },
6651
6652   /* PREFIX_VEX_0F3AF0 */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6658   },
6659
6660 #include "i386-dis-evex-prefix.h"
6661 };
6662
6663 static const struct dis386 x86_64_table[][2] = {
6664   /* X86_64_06 */
6665   {
6666     { "pushP", { es }, 0 },
6667   },
6668
6669   /* X86_64_07 */
6670   {
6671     { "popP", { es }, 0 },
6672   },
6673
6674   /* X86_64_0E */
6675   {
6676     { "pushP", { cs }, 0 },
6677   },
6678
6679   /* X86_64_16 */
6680   {
6681     { "pushP", { ss }, 0 },
6682   },
6683
6684   /* X86_64_17 */
6685   {
6686     { "popP", { ss }, 0 },
6687   },
6688
6689   /* X86_64_1E */
6690   {
6691     { "pushP", { ds }, 0 },
6692   },
6693
6694   /* X86_64_1F */
6695   {
6696     { "popP", { ds }, 0 },
6697   },
6698
6699   /* X86_64_27 */
6700   {
6701     { "daa", { XX }, 0 },
6702   },
6703
6704   /* X86_64_2F */
6705   {
6706     { "das", { XX }, 0 },
6707   },
6708
6709   /* X86_64_37 */
6710   {
6711     { "aaa", { XX }, 0 },
6712   },
6713
6714   /* X86_64_3F */
6715   {
6716     { "aas", { XX }, 0 },
6717   },
6718
6719   /* X86_64_60 */
6720   {
6721     { "pushaP", { XX }, 0 },
6722   },
6723
6724   /* X86_64_61 */
6725   {
6726     { "popaP", { XX }, 0 },
6727   },
6728
6729   /* X86_64_62 */
6730   {
6731     { MOD_TABLE (MOD_62_32BIT) },
6732     { EVEX_TABLE (EVEX_0F) },
6733   },
6734
6735   /* X86_64_63 */
6736   {
6737     { "arpl", { Ew, Gw }, 0 },
6738     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6739   },
6740
6741   /* X86_64_6D */
6742   {
6743     { "ins{R|}", { Yzr, indirDX }, 0 },
6744     { "ins{G|}", { Yzr, indirDX }, 0 },
6745   },
6746
6747   /* X86_64_6F */
6748   {
6749     { "outs{R|}", { indirDXr, Xz }, 0 },
6750     { "outs{G|}", { indirDXr, Xz }, 0 },
6751   },
6752
6753   /* X86_64_82 */
6754   {
6755     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6756     { REG_TABLE (REG_80) },
6757   },
6758
6759   /* X86_64_9A */
6760   {
6761     { "{l|}call{T|}", { Ap }, 0 },
6762   },
6763
6764   /* X86_64_C2 */
6765   {
6766     { "retP",           { Iw, BND }, 0 },
6767     { "ret@",           { Iw, BND }, 0 },
6768   },
6769
6770   /* X86_64_C3 */
6771   {
6772     { "retP",           { BND }, 0 },
6773     { "ret@",           { BND }, 0 },
6774   },
6775
6776   /* X86_64_C4 */
6777   {
6778     { MOD_TABLE (MOD_C4_32BIT) },
6779     { VEX_C4_TABLE (VEX_0F) },
6780   },
6781
6782   /* X86_64_C5 */
6783   {
6784     { MOD_TABLE (MOD_C5_32BIT) },
6785     { VEX_C5_TABLE (VEX_0F) },
6786   },
6787
6788   /* X86_64_CE */
6789   {
6790     { "into", { XX }, 0 },
6791   },
6792
6793   /* X86_64_D4 */
6794   {
6795     { "aam", { Ib }, 0 },
6796   },
6797
6798   /* X86_64_D5 */
6799   {
6800     { "aad", { Ib }, 0 },
6801   },
6802
6803   /* X86_64_E8 */
6804   {
6805     { "callP",          { Jv, BND }, 0 },
6806     { "call@",          { Jv, BND }, 0 }
6807   },
6808
6809   /* X86_64_E9 */
6810   {
6811     { "jmpP",           { Jv, BND }, 0 },
6812     { "jmp@",           { Jv, BND }, 0 }
6813   },
6814
6815   /* X86_64_EA */
6816   {
6817     { "{l|}jmp{T|}", { Ap }, 0 },
6818   },
6819
6820   /* X86_64_0F01_REG_0 */
6821   {
6822     { "sgdt{Q|Q}", { M }, 0 },
6823     { "sgdt", { M }, 0 },
6824   },
6825
6826   /* X86_64_0F01_REG_1 */
6827   {
6828     { "sidt{Q|Q}", { M }, 0 },
6829     { "sidt", { M }, 0 },
6830   },
6831
6832   /* X86_64_0F01_REG_2 */
6833   {
6834     { "lgdt{Q|Q}", { M }, 0 },
6835     { "lgdt", { M }, 0 },
6836   },
6837
6838   /* X86_64_0F01_REG_3 */
6839   {
6840     { "lidt{Q|Q}", { M }, 0 },
6841     { "lidt", { M }, 0 },
6842   },
6843 };
6844
6845 static const struct dis386 three_byte_table[][256] = {
6846
6847   /* THREE_BYTE_0F38 */
6848   {
6849     /* 00 */
6850     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6851     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6852     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6853     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6854     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6855     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6856     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6857     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6858     /* 08 */
6859     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6860     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6861     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6862     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     /* 10 */
6868     { PREFIX_TABLE (PREFIX_0F3810) },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { PREFIX_TABLE (PREFIX_0F3814) },
6873     { PREFIX_TABLE (PREFIX_0F3815) },
6874     { Bad_Opcode },
6875     { PREFIX_TABLE (PREFIX_0F3817) },
6876     /* 18 */
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6882     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6883     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6884     { Bad_Opcode },
6885     /* 20 */
6886     { PREFIX_TABLE (PREFIX_0F3820) },
6887     { PREFIX_TABLE (PREFIX_0F3821) },
6888     { PREFIX_TABLE (PREFIX_0F3822) },
6889     { PREFIX_TABLE (PREFIX_0F3823) },
6890     { PREFIX_TABLE (PREFIX_0F3824) },
6891     { PREFIX_TABLE (PREFIX_0F3825) },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     /* 28 */
6895     { PREFIX_TABLE (PREFIX_0F3828) },
6896     { PREFIX_TABLE (PREFIX_0F3829) },
6897     { PREFIX_TABLE (PREFIX_0F382A) },
6898     { PREFIX_TABLE (PREFIX_0F382B) },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     /* 30 */
6904     { PREFIX_TABLE (PREFIX_0F3830) },
6905     { PREFIX_TABLE (PREFIX_0F3831) },
6906     { PREFIX_TABLE (PREFIX_0F3832) },
6907     { PREFIX_TABLE (PREFIX_0F3833) },
6908     { PREFIX_TABLE (PREFIX_0F3834) },
6909     { PREFIX_TABLE (PREFIX_0F3835) },
6910     { Bad_Opcode },
6911     { PREFIX_TABLE (PREFIX_0F3837) },
6912     /* 38 */
6913     { PREFIX_TABLE (PREFIX_0F3838) },
6914     { PREFIX_TABLE (PREFIX_0F3839) },
6915     { PREFIX_TABLE (PREFIX_0F383A) },
6916     { PREFIX_TABLE (PREFIX_0F383B) },
6917     { PREFIX_TABLE (PREFIX_0F383C) },
6918     { PREFIX_TABLE (PREFIX_0F383D) },
6919     { PREFIX_TABLE (PREFIX_0F383E) },
6920     { PREFIX_TABLE (PREFIX_0F383F) },
6921     /* 40 */
6922     { PREFIX_TABLE (PREFIX_0F3840) },
6923     { PREFIX_TABLE (PREFIX_0F3841) },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     /* 48 */
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     /* 50 */
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     /* 58 */
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     /* 60 */
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     /* 68 */
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     /* 70 */
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     /* 78 */
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     /* 80 */
6994     { PREFIX_TABLE (PREFIX_0F3880) },
6995     { PREFIX_TABLE (PREFIX_0F3881) },
6996     { PREFIX_TABLE (PREFIX_0F3882) },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     /* 88 */
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     /* 90 */
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     /* 98 */
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     /* a0 */
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     /* a8 */
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     /* b0 */
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     /* b8 */
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     /* c0 */
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* c8 */
7075     { PREFIX_TABLE (PREFIX_0F38C8) },
7076     { PREFIX_TABLE (PREFIX_0F38C9) },
7077     { PREFIX_TABLE (PREFIX_0F38CA) },
7078     { PREFIX_TABLE (PREFIX_0F38CB) },
7079     { PREFIX_TABLE (PREFIX_0F38CC) },
7080     { PREFIX_TABLE (PREFIX_0F38CD) },
7081     { Bad_Opcode },
7082     { PREFIX_TABLE (PREFIX_0F38CF) },
7083     /* d0 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* d8 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { PREFIX_TABLE (PREFIX_0F38DB) },
7097     { PREFIX_TABLE (PREFIX_0F38DC) },
7098     { PREFIX_TABLE (PREFIX_0F38DD) },
7099     { PREFIX_TABLE (PREFIX_0F38DE) },
7100     { PREFIX_TABLE (PREFIX_0F38DF) },
7101     /* e0 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* e8 */
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* f0 */
7120     { PREFIX_TABLE (PREFIX_0F38F0) },
7121     { PREFIX_TABLE (PREFIX_0F38F1) },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { PREFIX_TABLE (PREFIX_0F38F5) },
7126     { PREFIX_TABLE (PREFIX_0F38F6) },
7127     { Bad_Opcode },
7128     /* f8 */
7129     { PREFIX_TABLE (PREFIX_0F38F8) },
7130     { PREFIX_TABLE (PREFIX_0F38F9) },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137   },
7138   /* THREE_BYTE_0F3A */
7139   {
7140     /* 00 */
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     /* 08 */
7150     { PREFIX_TABLE (PREFIX_0F3A08) },
7151     { PREFIX_TABLE (PREFIX_0F3A09) },
7152     { PREFIX_TABLE (PREFIX_0F3A0A) },
7153     { PREFIX_TABLE (PREFIX_0F3A0B) },
7154     { PREFIX_TABLE (PREFIX_0F3A0C) },
7155     { PREFIX_TABLE (PREFIX_0F3A0D) },
7156     { PREFIX_TABLE (PREFIX_0F3A0E) },
7157     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7158     /* 10 */
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { PREFIX_TABLE (PREFIX_0F3A14) },
7164     { PREFIX_TABLE (PREFIX_0F3A15) },
7165     { PREFIX_TABLE (PREFIX_0F3A16) },
7166     { PREFIX_TABLE (PREFIX_0F3A17) },
7167     /* 18 */
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     /* 20 */
7177     { PREFIX_TABLE (PREFIX_0F3A20) },
7178     { PREFIX_TABLE (PREFIX_0F3A21) },
7179     { PREFIX_TABLE (PREFIX_0F3A22) },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     /* 28 */
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     /* 30 */
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     /* 38 */
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     /* 40 */
7213     { PREFIX_TABLE (PREFIX_0F3A40) },
7214     { PREFIX_TABLE (PREFIX_0F3A41) },
7215     { PREFIX_TABLE (PREFIX_0F3A42) },
7216     { Bad_Opcode },
7217     { PREFIX_TABLE (PREFIX_0F3A44) },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     /* 48 */
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     /* 50 */
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     /* 58 */
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     /* 60 */
7249     { PREFIX_TABLE (PREFIX_0F3A60) },
7250     { PREFIX_TABLE (PREFIX_0F3A61) },
7251     { PREFIX_TABLE (PREFIX_0F3A62) },
7252     { PREFIX_TABLE (PREFIX_0F3A63) },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     /* 68 */
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     /* 70 */
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* 78 */
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     /* 80 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     /* 88 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 90 */
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 98 */
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* a0 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* a8 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* b0 */
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* b8 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* c0 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* c8 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { PREFIX_TABLE (PREFIX_0F3ACC) },
7371     { Bad_Opcode },
7372     { PREFIX_TABLE (PREFIX_0F3ACE) },
7373     { PREFIX_TABLE (PREFIX_0F3ACF) },
7374     /* d0 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* d8 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { PREFIX_TABLE (PREFIX_0F3ADF) },
7392     /* e0 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* e8 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* f0 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* f8 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428   },
7429 };
7430
7431 static const struct dis386 xop_table[][256] = {
7432   /* XOP_08 */
7433   {
7434     /* 00 */
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     /* 08 */
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     /* 10 */
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     /* 18 */
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     /* 20 */
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     /* 28 */
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     /* 30 */
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     /* 38 */
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     /* 40 */
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     /* 48 */
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     /* 50 */
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     /* 58 */
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     /* 60 */
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     /* 68 */
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     /* 70 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* 78 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* 80 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7585     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7586     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7587     /* 88 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7595     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7596     /* 90 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7603     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7604     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7605     /* 98 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7613     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7614     /* a0 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7618     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7622     { Bad_Opcode },
7623     /* a8 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* b0 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7640     { Bad_Opcode },
7641     /* b8 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     /* c0 */
7651     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7652     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7653     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7654     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     /* c8 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7665     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7666     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7667     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7668     /* d0 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     /* d8 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     /* e0 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     /* e8 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7701     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7702     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7703     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7704     /* f0 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     /* f8 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722   },
7723   /* XOP_09 */
7724   {
7725     /* 00 */
7726     { Bad_Opcode },
7727     { REG_TABLE (REG_XOP_TBM_01) },
7728     { REG_TABLE (REG_XOP_TBM_02) },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     /* 08 */
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     /* 10 */
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { REG_TABLE (REG_XOP_LWPCB) },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     /* 18 */
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     /* 20 */
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     /* 28 */
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     /* 30 */
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     /* 38 */
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     /* 40 */
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     /* 48 */
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     /* 50 */
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     /* 58 */
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     /* 60 */
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     /* 68 */
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     /* 70 */
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     /* 78 */
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     /* 80 */
7870     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
7871     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
7872     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
7873     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* 88 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 90 */
7888     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7889     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7890     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7891     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7892     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7893     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7894     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7895     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7896     /* 98 */
7897     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7898     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7899     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7900     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     /* a0 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     /* a8 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     /* b0 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* b8 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* c0 */
7942     { Bad_Opcode },
7943     { "vphaddbw",       { XM, EXxmm }, 0 },
7944     { "vphaddbd",       { XM, EXxmm }, 0 },
7945     { "vphaddbq",       { XM, EXxmm }, 0 },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { "vphaddwd",       { XM, EXxmm }, 0 },
7949     { "vphaddwq",       { XM, EXxmm }, 0 },
7950     /* c8 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { "vphadddq",       { XM, EXxmm }, 0 },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* d0 */
7960     { Bad_Opcode },
7961     { "vphaddubw",      { XM, EXxmm }, 0 },
7962     { "vphaddubd",      { XM, EXxmm }, 0 },
7963     { "vphaddubq",      { XM, EXxmm }, 0 },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { "vphadduwd",      { XM, EXxmm }, 0 },
7967     { "vphadduwq",      { XM, EXxmm }, 0 },
7968     /* d8 */
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { "vphaddudq",      { XM, EXxmm }, 0 },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* e0 */
7978     { Bad_Opcode },
7979     { "vphsubbw",       { XM, EXxmm }, 0 },
7980     { "vphsubwd",       { XM, EXxmm }, 0 },
7981     { "vphsubdq",       { XM, EXxmm }, 0 },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     /* e8 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* f0 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* f8 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013   },
8014   /* XOP_0A */
8015   {
8016     /* 00 */
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     /* 08 */
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     /* 10 */
8035     { "bextrS", { Gdq, Edq, Id }, 0 },
8036     { Bad_Opcode },
8037     { REG_TABLE (REG_XOP_LWP) },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     /* 18 */
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     /* 20 */
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     /* 28 */
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     /* 30 */
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     /* 38 */
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     /* 40 */
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     /* 48 */
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     /* 50 */
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     /* 58 */
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     /* 60 */
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     /* 68 */
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     /* 70 */
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     /* 78 */
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     /* 80 */
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 88 */
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 90 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 98 */
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* a0 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* a8 */
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     /* b0 */
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* b8 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* c0 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* c8 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* d0 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* d8 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* e0 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* e8 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* f0 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* f8 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304   },
8305 };
8306
8307 static const struct dis386 vex_table[][256] = {
8308   /* VEX_0F */
8309   {
8310     /* 00 */
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* 08 */
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* 10 */
8329     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8330     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8331     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8332     { MOD_TABLE (MOD_VEX_0F13) },
8333     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8334     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8335     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8336     { MOD_TABLE (MOD_VEX_0F17) },
8337     /* 18 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     /* 20 */
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* 28 */
8356     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8357     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8358     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8359     { MOD_TABLE (MOD_VEX_0F2B) },
8360     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8361     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8362     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8363     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8364     /* 30 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* 38 */
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* 40 */
8383     { Bad_Opcode },
8384     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8385     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8386     { Bad_Opcode },
8387     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8388     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8389     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8390     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8391     /* 48 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8395     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     /* 50 */
8401     { MOD_TABLE (MOD_VEX_0F50) },
8402     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8403     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8404     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8405     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8406     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8407     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8408     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8409     /* 58 */
8410     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8411     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8412     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8413     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8414     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8415     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8416     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8417     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8418     /* 60 */
8419     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8427     /* 68 */
8428     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8433     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8434     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8435     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8436     /* 70 */
8437     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8438     { REG_TABLE (REG_VEX_0F71) },
8439     { REG_TABLE (REG_VEX_0F72) },
8440     { REG_TABLE (REG_VEX_0F73) },
8441     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8442     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8443     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8444     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8445     /* 78 */
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8451     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8454     /* 80 */
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     /* 88 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     /* 90 */
8473     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8474     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8475     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8476     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     /* 98 */
8482     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     /* a0 */
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     /* a8 */
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { REG_TABLE (REG_VEX_0FAE) },
8507     { Bad_Opcode },
8508     /* b0 */
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     /* b8 */
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     /* c0 */
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8530     { Bad_Opcode },
8531     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8532     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8533     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8534     { Bad_Opcode },
8535     /* c8 */
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     /* d0 */
8545     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8546     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8547     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8548     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8549     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8550     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8551     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8552     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8553     /* d8 */
8554     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8557     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8558     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8559     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8560     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8561     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8562     /* e0 */
8563     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8566     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8569     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8570     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8571     /* e8 */
8572     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8575     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8576     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8577     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8578     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8579     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8580     /* f0 */
8581     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8584     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8585     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8586     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8587     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8589     /* f8 */
8590     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8592     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8593     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8594     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8595     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8596     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8597     { Bad_Opcode },
8598   },
8599   /* VEX_0F38 */
8600   {
8601     /* 00 */
8602     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8610     /* 08 */
8611     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8619     /* 10 */
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8628     /* 18 */
8629     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8632     { Bad_Opcode },
8633     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8636     { Bad_Opcode },
8637     /* 20 */
8638     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     /* 28 */
8647     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8655     /* 30 */
8656     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8664     /* 38 */
8665     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8673     /* 40 */
8674     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8682     /* 48 */
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     /* 50 */
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     /* 58 */
8701     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     /* 60 */
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     /* 68 */
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     /* 70 */
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     /* 78 */
8737     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     /* 80 */
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     /* 88 */
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8760     { Bad_Opcode },
8761     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8762     { Bad_Opcode },
8763     /* 90 */
8764     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8772     /* 98 */
8773     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8781     /* a0 */
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8790     /* a8 */
8791     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8799     /* b0 */
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8808     /* b8 */
8809     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8817     /* c0 */
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     /* c8 */
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8835     /* d0 */
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* d8 */
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8852     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8853     /* e0 */
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     /* e8 */
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     /* f0 */
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8875     { REG_TABLE (REG_VEX_0F38F3) },
8876     { Bad_Opcode },
8877     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8880     /* f8 */
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889   },
8890   /* VEX_0F3A */
8891   {
8892     /* 00 */
8893     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8896     { Bad_Opcode },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8900     { Bad_Opcode },
8901     /* 08 */
8902     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8910     /* 10 */
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8919     /* 18 */
8920     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     /* 20 */
8929     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     /* 28 */
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     /* 30 */
8947     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     /* 38 */
8956     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     /* 40 */
8965     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8968     { Bad_Opcode },
8969     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8970     { Bad_Opcode },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8972     { Bad_Opcode },
8973     /* 48 */
8974     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     /* 50 */
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     /* 58 */
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9000     /* 60 */
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     /* 68 */
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9018     /* 70 */
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     /* 78 */
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9036     /* 80 */
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     /* 88 */
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     /* 90 */
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     /* 98 */
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     /* a0 */
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     /* a8 */
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     /* b0 */
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     /* b8 */
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     /* c0 */
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     /* c8 */
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9125     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9126     /* d0 */
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     /* d8 */
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9144     /* e0 */
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     /* e8 */
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     /* f0 */
9163     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     /* f8 */
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180   },
9181 };
9182
9183 #include "i386-dis-evex.h"
9184
9185 static const struct dis386 vex_len_table[][2] = {
9186   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9187   {
9188     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9189   },
9190
9191   /* VEX_LEN_0F12_P_0_M_1 */
9192   {
9193     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9194   },
9195
9196   /* VEX_LEN_0F13_M_0 */
9197   {
9198     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9199   },
9200
9201   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9202   {
9203     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9204   },
9205
9206   /* VEX_LEN_0F16_P_0_M_1 */
9207   {
9208     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9209   },
9210
9211   /* VEX_LEN_0F17_M_0 */
9212   {
9213     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9214   },
9215
9216   /* VEX_LEN_0F41_P_0 */
9217   {
9218     { Bad_Opcode },
9219     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9220   },
9221   /* VEX_LEN_0F41_P_2 */
9222   {
9223     { Bad_Opcode },
9224     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9225   },
9226   /* VEX_LEN_0F42_P_0 */
9227   {
9228     { Bad_Opcode },
9229     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9230   },
9231   /* VEX_LEN_0F42_P_2 */
9232   {
9233     { Bad_Opcode },
9234     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9235   },
9236   /* VEX_LEN_0F44_P_0 */
9237   {
9238     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9239   },
9240   /* VEX_LEN_0F44_P_2 */
9241   {
9242     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9243   },
9244   /* VEX_LEN_0F45_P_0 */
9245   {
9246     { Bad_Opcode },
9247     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9248   },
9249   /* VEX_LEN_0F45_P_2 */
9250   {
9251     { Bad_Opcode },
9252     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9253   },
9254   /* VEX_LEN_0F46_P_0 */
9255   {
9256     { Bad_Opcode },
9257     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9258   },
9259   /* VEX_LEN_0F46_P_2 */
9260   {
9261     { Bad_Opcode },
9262     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9263   },
9264   /* VEX_LEN_0F47_P_0 */
9265   {
9266     { Bad_Opcode },
9267     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9268   },
9269   /* VEX_LEN_0F47_P_2 */
9270   {
9271     { Bad_Opcode },
9272     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9273   },
9274   /* VEX_LEN_0F4A_P_0 */
9275   {
9276     { Bad_Opcode },
9277     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9278   },
9279   /* VEX_LEN_0F4A_P_2 */
9280   {
9281     { Bad_Opcode },
9282     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9283   },
9284   /* VEX_LEN_0F4B_P_0 */
9285   {
9286     { Bad_Opcode },
9287     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9288   },
9289   /* VEX_LEN_0F4B_P_2 */
9290   {
9291     { Bad_Opcode },
9292     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9293   },
9294
9295   /* VEX_LEN_0F6E_P_2 */
9296   {
9297     { "vmovK",          { XMScalar, Edq }, 0 },
9298   },
9299
9300   /* VEX_LEN_0F77_P_1 */
9301   {
9302     { "vzeroupper",     { XX }, 0 },
9303     { "vzeroall",       { XX }, 0 },
9304   },
9305
9306   /* VEX_LEN_0F7E_P_1 */
9307   {
9308     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9309   },
9310
9311   /* VEX_LEN_0F7E_P_2 */
9312   {
9313     { "vmovK",          { Edq, XMScalar }, 0 },
9314   },
9315
9316   /* VEX_LEN_0F90_P_0 */
9317   {
9318     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9319   },
9320
9321   /* VEX_LEN_0F90_P_2 */
9322   {
9323     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9324   },
9325
9326   /* VEX_LEN_0F91_P_0 */
9327   {
9328     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9329   },
9330
9331   /* VEX_LEN_0F91_P_2 */
9332   {
9333     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9334   },
9335
9336   /* VEX_LEN_0F92_P_0 */
9337   {
9338     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9339   },
9340
9341   /* VEX_LEN_0F92_P_2 */
9342   {
9343     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9344   },
9345
9346   /* VEX_LEN_0F92_P_3 */
9347   {
9348     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9349   },
9350
9351   /* VEX_LEN_0F93_P_0 */
9352   {
9353     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9354   },
9355
9356   /* VEX_LEN_0F93_P_2 */
9357   {
9358     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9359   },
9360
9361   /* VEX_LEN_0F93_P_3 */
9362   {
9363     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9364   },
9365
9366   /* VEX_LEN_0F98_P_0 */
9367   {
9368     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9369   },
9370
9371   /* VEX_LEN_0F98_P_2 */
9372   {
9373     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9374   },
9375
9376   /* VEX_LEN_0F99_P_0 */
9377   {
9378     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9379   },
9380
9381   /* VEX_LEN_0F99_P_2 */
9382   {
9383     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9384   },
9385
9386   /* VEX_LEN_0FAE_R_2_M_0 */
9387   {
9388     { "vldmxcsr",       { Md }, 0 },
9389   },
9390
9391   /* VEX_LEN_0FAE_R_3_M_0 */
9392   {
9393     { "vstmxcsr",       { Md }, 0 },
9394   },
9395
9396   /* VEX_LEN_0FC4_P_2 */
9397   {
9398     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9399   },
9400
9401   /* VEX_LEN_0FC5_P_2 */
9402   {
9403     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9404   },
9405
9406   /* VEX_LEN_0FD6_P_2 */
9407   {
9408     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9409   },
9410
9411   /* VEX_LEN_0FF7_P_2 */
9412   {
9413     { "vmaskmovdqu",    { XM, XS }, 0 },
9414   },
9415
9416   /* VEX_LEN_0F3816_P_2 */
9417   {
9418     { Bad_Opcode },
9419     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9420   },
9421
9422   /* VEX_LEN_0F3819_P_2 */
9423   {
9424     { Bad_Opcode },
9425     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9426   },
9427
9428   /* VEX_LEN_0F381A_P_2_M_0 */
9429   {
9430     { Bad_Opcode },
9431     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9432   },
9433
9434   /* VEX_LEN_0F3836_P_2 */
9435   {
9436     { Bad_Opcode },
9437     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9438   },
9439
9440   /* VEX_LEN_0F3841_P_2 */
9441   {
9442     { "vphminposuw",    { XM, EXx }, 0 },
9443   },
9444
9445   /* VEX_LEN_0F385A_P_2_M_0 */
9446   {
9447     { Bad_Opcode },
9448     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9449   },
9450
9451   /* VEX_LEN_0F38DB_P_2 */
9452   {
9453     { "vaesimc",        { XM, EXx }, 0 },
9454   },
9455
9456   /* VEX_LEN_0F38F2_P_0 */
9457   {
9458     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9459   },
9460
9461   /* VEX_LEN_0F38F3_R_1_P_0 */
9462   {
9463     { "blsrS",          { VexGdq, Edq }, 0 },
9464   },
9465
9466   /* VEX_LEN_0F38F3_R_2_P_0 */
9467   {
9468     { "blsmskS",        { VexGdq, Edq }, 0 },
9469   },
9470
9471   /* VEX_LEN_0F38F3_R_3_P_0 */
9472   {
9473     { "blsiS",          { VexGdq, Edq }, 0 },
9474   },
9475
9476   /* VEX_LEN_0F38F5_P_0 */
9477   {
9478     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9479   },
9480
9481   /* VEX_LEN_0F38F5_P_1 */
9482   {
9483     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9484   },
9485
9486   /* VEX_LEN_0F38F5_P_3 */
9487   {
9488     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9489   },
9490
9491   /* VEX_LEN_0F38F6_P_3 */
9492   {
9493     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9494   },
9495
9496   /* VEX_LEN_0F38F7_P_0 */
9497   {
9498     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9499   },
9500
9501   /* VEX_LEN_0F38F7_P_1 */
9502   {
9503     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9504   },
9505
9506   /* VEX_LEN_0F38F7_P_2 */
9507   {
9508     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9509   },
9510
9511   /* VEX_LEN_0F38F7_P_3 */
9512   {
9513     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9514   },
9515
9516   /* VEX_LEN_0F3A00_P_2 */
9517   {
9518     { Bad_Opcode },
9519     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9520   },
9521
9522   /* VEX_LEN_0F3A01_P_2 */
9523   {
9524     { Bad_Opcode },
9525     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9526   },
9527
9528   /* VEX_LEN_0F3A06_P_2 */
9529   {
9530     { Bad_Opcode },
9531     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9532   },
9533
9534   /* VEX_LEN_0F3A14_P_2 */
9535   {
9536     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9537   },
9538
9539   /* VEX_LEN_0F3A15_P_2 */
9540   {
9541     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9542   },
9543
9544   /* VEX_LEN_0F3A16_P_2  */
9545   {
9546     { "vpextrK",        { Edq, XM, Ib }, 0 },
9547   },
9548
9549   /* VEX_LEN_0F3A17_P_2 */
9550   {
9551     { "vextractps",     { Edqd, XM, Ib }, 0 },
9552   },
9553
9554   /* VEX_LEN_0F3A18_P_2 */
9555   {
9556     { Bad_Opcode },
9557     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9558   },
9559
9560   /* VEX_LEN_0F3A19_P_2 */
9561   {
9562     { Bad_Opcode },
9563     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9564   },
9565
9566   /* VEX_LEN_0F3A20_P_2 */
9567   {
9568     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9569   },
9570
9571   /* VEX_LEN_0F3A21_P_2 */
9572   {
9573     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9574   },
9575
9576   /* VEX_LEN_0F3A22_P_2 */
9577   {
9578     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9579   },
9580
9581   /* VEX_LEN_0F3A30_P_2 */
9582   {
9583     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9584   },
9585
9586   /* VEX_LEN_0F3A31_P_2 */
9587   {
9588     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9589   },
9590
9591   /* VEX_LEN_0F3A32_P_2 */
9592   {
9593     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9594   },
9595
9596   /* VEX_LEN_0F3A33_P_2 */
9597   {
9598     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9599   },
9600
9601   /* VEX_LEN_0F3A38_P_2 */
9602   {
9603     { Bad_Opcode },
9604     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9605   },
9606
9607   /* VEX_LEN_0F3A39_P_2 */
9608   {
9609     { Bad_Opcode },
9610     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9611   },
9612
9613   /* VEX_LEN_0F3A41_P_2 */
9614   {
9615     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F3A46_P_2 */
9619   {
9620     { Bad_Opcode },
9621     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9622   },
9623
9624   /* VEX_LEN_0F3A60_P_2 */
9625   {
9626     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9627   },
9628
9629   /* VEX_LEN_0F3A61_P_2 */
9630   {
9631     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9632   },
9633
9634   /* VEX_LEN_0F3A62_P_2 */
9635   {
9636     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9637   },
9638
9639   /* VEX_LEN_0F3A63_P_2 */
9640   {
9641     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9642   },
9643
9644   /* VEX_LEN_0F3A6A_P_2 */
9645   {
9646     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9647   },
9648
9649   /* VEX_LEN_0F3A6B_P_2 */
9650   {
9651     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9652   },
9653
9654   /* VEX_LEN_0F3A6E_P_2 */
9655   {
9656     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9657   },
9658
9659   /* VEX_LEN_0F3A6F_P_2 */
9660   {
9661     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9662   },
9663
9664   /* VEX_LEN_0F3A7A_P_2 */
9665   {
9666     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9667   },
9668
9669   /* VEX_LEN_0F3A7B_P_2 */
9670   {
9671     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9672   },
9673
9674   /* VEX_LEN_0F3A7E_P_2 */
9675   {
9676     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9677   },
9678
9679   /* VEX_LEN_0F3A7F_P_2 */
9680   {
9681     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9682   },
9683
9684   /* VEX_LEN_0F3ADF_P_2 */
9685   {
9686     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9687   },
9688
9689   /* VEX_LEN_0F3AF0_P_3 */
9690   {
9691     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9692   },
9693
9694   /* VEX_LEN_0FXOP_08_CC */
9695   {
9696      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9697   },
9698
9699   /* VEX_LEN_0FXOP_08_CD */
9700   {
9701      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9702   },
9703
9704   /* VEX_LEN_0FXOP_08_CE */
9705   {
9706      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9707   },
9708
9709   /* VEX_LEN_0FXOP_08_CF */
9710   {
9711      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9712   },
9713
9714   /* VEX_LEN_0FXOP_08_EC */
9715   {
9716      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9717   },
9718
9719   /* VEX_LEN_0FXOP_08_ED */
9720   {
9721      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9722   },
9723
9724   /* VEX_LEN_0FXOP_08_EE */
9725   {
9726      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9727   },
9728
9729   /* VEX_LEN_0FXOP_08_EF */
9730   {
9731      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9732   },
9733
9734   /* VEX_LEN_0FXOP_09_82_W_0 */
9735   {
9736     { "vfrczss",        { XM, EXd }, 0 },
9737   },
9738
9739   /* VEX_LEN_0FXOP_09_83_W_0 */
9740   {
9741     { "vfrczsd",        { XM, EXq }, 0 },
9742   },
9743 };
9744
9745 #include "i386-dis-evex-len.h"
9746
9747 static const struct dis386 vex_w_table[][2] = {
9748   {
9749     /* VEX_W_0F41_P_0_LEN_1 */
9750     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9751     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9752   },
9753   {
9754     /* VEX_W_0F41_P_2_LEN_1 */
9755     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9756     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9757   },
9758   {
9759     /* VEX_W_0F42_P_0_LEN_1 */
9760     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9761     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9762   },
9763   {
9764     /* VEX_W_0F42_P_2_LEN_1 */
9765     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9766     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9767   },
9768   {
9769     /* VEX_W_0F44_P_0_LEN_0 */
9770     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9771     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9772   },
9773   {
9774     /* VEX_W_0F44_P_2_LEN_0 */
9775     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9776     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9777   },
9778   {
9779     /* VEX_W_0F45_P_0_LEN_1 */
9780     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9781     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9782   },
9783   {
9784     /* VEX_W_0F45_P_2_LEN_1 */
9785     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9786     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9787   },
9788   {
9789     /* VEX_W_0F46_P_0_LEN_1 */
9790     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9791     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9792   },
9793   {
9794     /* VEX_W_0F46_P_2_LEN_1 */
9795     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9796     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9797   },
9798   {
9799     /* VEX_W_0F47_P_0_LEN_1 */
9800     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9801     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9802   },
9803   {
9804     /* VEX_W_0F47_P_2_LEN_1 */
9805     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9806     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9807   },
9808   {
9809     /* VEX_W_0F4A_P_0_LEN_1 */
9810     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9811     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9812   },
9813   {
9814     /* VEX_W_0F4A_P_2_LEN_1 */
9815     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9816     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9817   },
9818   {
9819     /* VEX_W_0F4B_P_0_LEN_1 */
9820     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9821     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9822   },
9823   {
9824     /* VEX_W_0F4B_P_2_LEN_1 */
9825     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9826   },
9827   {
9828     /* VEX_W_0F90_P_0_LEN_0 */
9829     { "kmovw",          { MaskG, MaskE }, 0 },
9830     { "kmovq",          { MaskG, MaskE }, 0 },
9831   },
9832   {
9833     /* VEX_W_0F90_P_2_LEN_0 */
9834     { "kmovb",          { MaskG, MaskBDE }, 0 },
9835     { "kmovd",          { MaskG, MaskBDE }, 0 },
9836   },
9837   {
9838     /* VEX_W_0F91_P_0_LEN_0 */
9839     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9840     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9841   },
9842   {
9843     /* VEX_W_0F91_P_2_LEN_0 */
9844     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9845     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9846   },
9847   {
9848     /* VEX_W_0F92_P_0_LEN_0 */
9849     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9850   },
9851   {
9852     /* VEX_W_0F92_P_2_LEN_0 */
9853     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9854   },
9855   {
9856     /* VEX_W_0F93_P_0_LEN_0 */
9857     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9858   },
9859   {
9860     /* VEX_W_0F93_P_2_LEN_0 */
9861     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9862   },
9863   {
9864     /* VEX_W_0F98_P_0_LEN_0 */
9865     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9866     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9867   },
9868   {
9869     /* VEX_W_0F98_P_2_LEN_0 */
9870     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9871     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9872   },
9873   {
9874     /* VEX_W_0F99_P_0_LEN_0 */
9875     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9876     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9877   },
9878   {
9879     /* VEX_W_0F99_P_2_LEN_0 */
9880     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9881     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9882   },
9883   {
9884     /* VEX_W_0F380C_P_2  */
9885     { "vpermilps",      { XM, Vex, EXx }, 0 },
9886   },
9887   {
9888     /* VEX_W_0F380D_P_2  */
9889     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9890   },
9891   {
9892     /* VEX_W_0F380E_P_2  */
9893     { "vtestps",        { XM, EXx }, 0 },
9894   },
9895   {
9896     /* VEX_W_0F380F_P_2  */
9897     { "vtestpd",        { XM, EXx }, 0 },
9898   },
9899   {
9900     /* VEX_W_0F3813_P_2 */
9901     { "vcvtph2ps", { XM, EXxmmq }, 0 },
9902   },
9903   {
9904     /* VEX_W_0F3816_P_2  */
9905     { "vpermps",        { XM, Vex, EXx }, 0 },
9906   },
9907   {
9908     /* VEX_W_0F3818_P_2 */
9909     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
9910   },
9911   {
9912     /* VEX_W_0F3819_P_2 */
9913     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
9914   },
9915   {
9916     /* VEX_W_0F381A_P_2_M_0 */
9917     { "vbroadcastf128", { XM, Mxmm }, 0 },
9918   },
9919   {
9920     /* VEX_W_0F382C_P_2_M_0 */
9921     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
9922   },
9923   {
9924     /* VEX_W_0F382D_P_2_M_0 */
9925     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
9926   },
9927   {
9928     /* VEX_W_0F382E_P_2_M_0 */
9929     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
9930   },
9931   {
9932     /* VEX_W_0F382F_P_2_M_0 */
9933     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
9934   },
9935   {
9936     /* VEX_W_0F3836_P_2  */
9937     { "vpermd",         { XM, Vex, EXx }, 0 },
9938   },
9939   {
9940     /* VEX_W_0F3846_P_2 */
9941     { "vpsravd",        { XM, Vex, EXx }, 0 },
9942   },
9943   {
9944     /* VEX_W_0F3858_P_2 */
9945     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
9946   },
9947   {
9948     /* VEX_W_0F3859_P_2 */
9949     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
9950   },
9951   {
9952     /* VEX_W_0F385A_P_2_M_0 */
9953     { "vbroadcasti128", { XM, Mxmm }, 0 },
9954   },
9955   {
9956     /* VEX_W_0F3878_P_2 */
9957     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
9958   },
9959   {
9960     /* VEX_W_0F3879_P_2 */
9961     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
9962   },
9963   {
9964     /* VEX_W_0F38CF_P_2 */
9965     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
9966   },
9967   {
9968     /* VEX_W_0F3A00_P_2 */
9969     { Bad_Opcode },
9970     { "vpermq",         { XM, EXx, Ib }, 0 },
9971   },
9972   {
9973     /* VEX_W_0F3A01_P_2 */
9974     { Bad_Opcode },
9975     { "vpermpd",        { XM, EXx, Ib }, 0 },
9976   },
9977   {
9978     /* VEX_W_0F3A02_P_2 */
9979     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
9980   },
9981   {
9982     /* VEX_W_0F3A04_P_2 */
9983     { "vpermilps",      { XM, EXx, Ib }, 0 },
9984   },
9985   {
9986     /* VEX_W_0F3A05_P_2 */
9987     { "vpermilpd",      { XM, EXx, Ib }, 0 },
9988   },
9989   {
9990     /* VEX_W_0F3A06_P_2 */
9991     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
9992   },
9993   {
9994     /* VEX_W_0F3A18_P_2 */
9995     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
9996   },
9997   {
9998     /* VEX_W_0F3A19_P_2 */
9999     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10000   },
10001   {
10002     /* VEX_W_0F3A1D_P_2 */
10003     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10004   },
10005   {
10006     /* VEX_W_0F3A30_P_2_LEN_0 */
10007     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10008     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10009   },
10010   {
10011     /* VEX_W_0F3A31_P_2_LEN_0 */
10012     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10013     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10014   },
10015   {
10016     /* VEX_W_0F3A32_P_2_LEN_0 */
10017     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10018     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10019   },
10020   {
10021     /* VEX_W_0F3A33_P_2_LEN_0 */
10022     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10023     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10024   },
10025   {
10026     /* VEX_W_0F3A38_P_2 */
10027     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10028   },
10029   {
10030     /* VEX_W_0F3A39_P_2 */
10031     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10032   },
10033   {
10034     /* VEX_W_0F3A46_P_2 */
10035     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10036   },
10037   {
10038     /* VEX_W_0F3A48_P_2 */
10039     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10040     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10041   },
10042   {
10043     /* VEX_W_0F3A49_P_2 */
10044     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10045     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10046   },
10047   {
10048     /* VEX_W_0F3A4A_P_2 */
10049     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10050   },
10051   {
10052     /* VEX_W_0F3A4B_P_2 */
10053     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10054   },
10055   {
10056     /* VEX_W_0F3A4C_P_2 */
10057     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10058   },
10059   {
10060     /* VEX_W_0F3ACE_P_2 */
10061     { Bad_Opcode },
10062     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10063   },
10064   {
10065     /* VEX_W_0F3ACF_P_2 */
10066     { Bad_Opcode },
10067     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10068   },
10069   /* VEX_W_0FXOP_09_80 */
10070   {
10071     { "vfrczps",        { XM, EXx }, 0 },
10072   },
10073   /* VEX_W_0FXOP_09_81 */
10074   {
10075     { "vfrczpd",        { XM, EXx }, 0 },
10076   },
10077   /* VEX_W_0FXOP_09_82 */
10078   {
10079     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10080   },
10081   /* VEX_W_0FXOP_09_83 */
10082   {
10083     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10084   },
10085
10086 #include "i386-dis-evex-w.h"
10087 };
10088
10089 static const struct dis386 mod_table[][2] = {
10090   {
10091     /* MOD_8D */
10092     { "leaS",           { Gv, M }, 0 },
10093   },
10094   {
10095     /* MOD_C6_REG_7 */
10096     { Bad_Opcode },
10097     { RM_TABLE (RM_C6_REG_7) },
10098   },
10099   {
10100     /* MOD_C7_REG_7 */
10101     { Bad_Opcode },
10102     { RM_TABLE (RM_C7_REG_7) },
10103   },
10104   {
10105     /* MOD_FF_REG_3 */
10106     { "{l|}call^", { indirEp }, 0 },
10107   },
10108   {
10109     /* MOD_FF_REG_5 */
10110     { "{l|}jmp^", { indirEp }, 0 },
10111   },
10112   {
10113     /* MOD_0F01_REG_0 */
10114     { X86_64_TABLE (X86_64_0F01_REG_0) },
10115     { RM_TABLE (RM_0F01_REG_0) },
10116   },
10117   {
10118     /* MOD_0F01_REG_1 */
10119     { X86_64_TABLE (X86_64_0F01_REG_1) },
10120     { RM_TABLE (RM_0F01_REG_1) },
10121   },
10122   {
10123     /* MOD_0F01_REG_2 */
10124     { X86_64_TABLE (X86_64_0F01_REG_2) },
10125     { RM_TABLE (RM_0F01_REG_2) },
10126   },
10127   {
10128     /* MOD_0F01_REG_3 */
10129     { X86_64_TABLE (X86_64_0F01_REG_3) },
10130     { RM_TABLE (RM_0F01_REG_3) },
10131   },
10132   {
10133     /* MOD_0F01_REG_5 */
10134     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10135     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10136   },
10137   {
10138     /* MOD_0F01_REG_7 */
10139     { "invlpg",         { Mb }, 0 },
10140     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10141   },
10142   {
10143     /* MOD_0F12_PREFIX_0 */
10144     { "movlpX",         { XM, EXq }, 0 },
10145     { "movhlps",        { XM, EXq }, 0 },
10146   },
10147   {
10148     /* MOD_0F12_PREFIX_2 */
10149     { "movlpX", { XM, EXq }, 0 },
10150   },
10151   {
10152     /* MOD_0F13 */
10153     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10154   },
10155   {
10156     /* MOD_0F16_PREFIX_0 */
10157     { "movhpX",         { XM, EXq }, 0 },
10158     { "movlhps",        { XM, EXq }, 0 },
10159   },
10160   {
10161     /* MOD_0F16_PREFIX_2 */
10162     { "movhpX", { XM, EXq }, 0 },
10163   },
10164   {
10165     /* MOD_0F17 */
10166     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10167   },
10168   {
10169     /* MOD_0F18_REG_0 */
10170     { "prefetchnta",    { Mb }, 0 },
10171   },
10172   {
10173     /* MOD_0F18_REG_1 */
10174     { "prefetcht0",     { Mb }, 0 },
10175   },
10176   {
10177     /* MOD_0F18_REG_2 */
10178     { "prefetcht1",     { Mb }, 0 },
10179   },
10180   {
10181     /* MOD_0F18_REG_3 */
10182     { "prefetcht2",     { Mb }, 0 },
10183   },
10184   {
10185     /* MOD_0F18_REG_4 */
10186     { "nop/reserved",   { Mb }, 0 },
10187   },
10188   {
10189     /* MOD_0F18_REG_5 */
10190     { "nop/reserved",   { Mb }, 0 },
10191   },
10192   {
10193     /* MOD_0F18_REG_6 */
10194     { "nop/reserved",   { Mb }, 0 },
10195   },
10196   {
10197     /* MOD_0F18_REG_7 */
10198     { "nop/reserved",   { Mb }, 0 },
10199   },
10200   {
10201     /* MOD_0F1A_PREFIX_0 */
10202     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10203     { "nopQ",           { Ev }, 0 },
10204   },
10205   {
10206     /* MOD_0F1B_PREFIX_0 */
10207     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10208     { "nopQ",           { Ev }, 0 },
10209   },
10210   {
10211     /* MOD_0F1B_PREFIX_1 */
10212     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10213     { "nopQ",           { Ev }, 0 },
10214   },
10215   {
10216     /* MOD_0F1C_PREFIX_0 */
10217     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10218     { "nopQ",           { Ev }, 0 },
10219   },
10220   {
10221     /* MOD_0F1E_PREFIX_1 */
10222     { "nopQ",           { Ev }, 0 },
10223     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10224   },
10225   {
10226     /* MOD_0F24 */
10227     { Bad_Opcode },
10228     { "movL",           { Rd, Td }, 0 },
10229   },
10230   {
10231     /* MOD_0F26 */
10232     { Bad_Opcode },
10233     { "movL",           { Td, Rd }, 0 },
10234   },
10235   {
10236     /* MOD_0F2B_PREFIX_0 */
10237     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10238   },
10239   {
10240     /* MOD_0F2B_PREFIX_1 */
10241     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10242   },
10243   {
10244     /* MOD_0F2B_PREFIX_2 */
10245     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10246   },
10247   {
10248     /* MOD_0F2B_PREFIX_3 */
10249     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10250   },
10251   {
10252     /* MOD_0F50 */
10253     { Bad_Opcode },
10254     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10255   },
10256   {
10257     /* MOD_0F71_REG_2 */
10258     { Bad_Opcode },
10259     { "psrlw",          { MS, Ib }, 0 },
10260   },
10261   {
10262     /* MOD_0F71_REG_4 */
10263     { Bad_Opcode },
10264     { "psraw",          { MS, Ib }, 0 },
10265   },
10266   {
10267     /* MOD_0F71_REG_6 */
10268     { Bad_Opcode },
10269     { "psllw",          { MS, Ib }, 0 },
10270   },
10271   {
10272     /* MOD_0F72_REG_2 */
10273     { Bad_Opcode },
10274     { "psrld",          { MS, Ib }, 0 },
10275   },
10276   {
10277     /* MOD_0F72_REG_4 */
10278     { Bad_Opcode },
10279     { "psrad",          { MS, Ib }, 0 },
10280   },
10281   {
10282     /* MOD_0F72_REG_6 */
10283     { Bad_Opcode },
10284     { "pslld",          { MS, Ib }, 0 },
10285   },
10286   {
10287     /* MOD_0F73_REG_2 */
10288     { Bad_Opcode },
10289     { "psrlq",          { MS, Ib }, 0 },
10290   },
10291   {
10292     /* MOD_0F73_REG_3 */
10293     { Bad_Opcode },
10294     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10295   },
10296   {
10297     /* MOD_0F73_REG_6 */
10298     { Bad_Opcode },
10299     { "psllq",          { MS, Ib }, 0 },
10300   },
10301   {
10302     /* MOD_0F73_REG_7 */
10303     { Bad_Opcode },
10304     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10305   },
10306   {
10307     /* MOD_0FAE_REG_0 */
10308     { "fxsave",         { FXSAVE }, 0 },
10309     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10310   },
10311   {
10312     /* MOD_0FAE_REG_1 */
10313     { "fxrstor",        { FXSAVE }, 0 },
10314     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10315   },
10316   {
10317     /* MOD_0FAE_REG_2 */
10318     { "ldmxcsr",        { Md }, 0 },
10319     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10320   },
10321   {
10322     /* MOD_0FAE_REG_3 */
10323     { "stmxcsr",        { Md }, 0 },
10324     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10325   },
10326   {
10327     /* MOD_0FAE_REG_4 */
10328     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10329     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10330   },
10331   {
10332     /* MOD_0FAE_REG_5 */
10333     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10334     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10335   },
10336   {
10337     /* MOD_0FAE_REG_6 */
10338     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10339     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10340   },
10341   {
10342     /* MOD_0FAE_REG_7 */
10343     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10344     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10345   },
10346   {
10347     /* MOD_0FB2 */
10348     { "lssS",           { Gv, Mp }, 0 },
10349   },
10350   {
10351     /* MOD_0FB4 */
10352     { "lfsS",           { Gv, Mp }, 0 },
10353   },
10354   {
10355     /* MOD_0FB5 */
10356     { "lgsS",           { Gv, Mp }, 0 },
10357   },
10358   {
10359     /* MOD_0FC3 */
10360     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10361   },
10362   {
10363     /* MOD_0FC7_REG_3 */
10364     { "xrstors",        { FXSAVE }, 0 },
10365   },
10366   {
10367     /* MOD_0FC7_REG_4 */
10368     { "xsavec",         { FXSAVE }, 0 },
10369   },
10370   {
10371     /* MOD_0FC7_REG_5 */
10372     { "xsaves",         { FXSAVE }, 0 },
10373   },
10374   {
10375     /* MOD_0FC7_REG_6 */
10376     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10377     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10378   },
10379   {
10380     /* MOD_0FC7_REG_7 */
10381     { "vmptrst",        { Mq }, 0 },
10382     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10383   },
10384   {
10385     /* MOD_0FD7 */
10386     { Bad_Opcode },
10387     { "pmovmskb",       { Gdq, MS }, 0 },
10388   },
10389   {
10390     /* MOD_0FE7_PREFIX_2 */
10391     { "movntdq",        { Mx, XM }, 0 },
10392   },
10393   {
10394     /* MOD_0FF0_PREFIX_3 */
10395     { "lddqu",          { XM, M }, 0 },
10396   },
10397   {
10398     /* MOD_0F382A_PREFIX_2 */
10399     { "movntdqa",       { XM, Mx }, 0 },
10400   },
10401   {
10402     /* MOD_0F38F5_PREFIX_2 */
10403     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10404   },
10405   {
10406     /* MOD_0F38F6_PREFIX_0 */
10407     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10408   },
10409   {
10410     /* MOD_0F38F8_PREFIX_1 */
10411     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10412   },
10413   {
10414     /* MOD_0F38F8_PREFIX_2 */
10415     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10416   },
10417   {
10418     /* MOD_0F38F8_PREFIX_3 */
10419     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10420   },
10421   {
10422     /* MOD_0F38F9_PREFIX_0 */
10423     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10424   },
10425   {
10426     /* MOD_62_32BIT */
10427     { "bound{S|}",      { Gv, Ma }, 0 },
10428     { EVEX_TABLE (EVEX_0F) },
10429   },
10430   {
10431     /* MOD_C4_32BIT */
10432     { "lesS",           { Gv, Mp }, 0 },
10433     { VEX_C4_TABLE (VEX_0F) },
10434   },
10435   {
10436     /* MOD_C5_32BIT */
10437     { "ldsS",           { Gv, Mp }, 0 },
10438     { VEX_C5_TABLE (VEX_0F) },
10439   },
10440   {
10441     /* MOD_VEX_0F12_PREFIX_0 */
10442     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10443     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10444   },
10445   {
10446     /* MOD_VEX_0F12_PREFIX_2 */
10447     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10448   },
10449   {
10450     /* MOD_VEX_0F13 */
10451     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10452   },
10453   {
10454     /* MOD_VEX_0F16_PREFIX_0 */
10455     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10456     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10457   },
10458   {
10459     /* MOD_VEX_0F16_PREFIX_2 */
10460     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10461   },
10462   {
10463     /* MOD_VEX_0F17 */
10464     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10465   },
10466   {
10467     /* MOD_VEX_0F2B */
10468     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10469   },
10470   {
10471     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10472     { Bad_Opcode },
10473     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10474   },
10475   {
10476     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10477     { Bad_Opcode },
10478     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10479   },
10480   {
10481     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10482     { Bad_Opcode },
10483     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10484   },
10485   {
10486     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10487     { Bad_Opcode },
10488     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10489   },
10490   {
10491     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10492     { Bad_Opcode },
10493     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10494   },
10495   {
10496     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10497     { Bad_Opcode },
10498     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10499   },
10500   {
10501     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10502     { Bad_Opcode },
10503     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10504   },
10505   {
10506     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10507     { Bad_Opcode },
10508     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10509   },
10510   {
10511     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10512     { Bad_Opcode },
10513     { "knotw",          { MaskG, MaskR }, 0 },
10514   },
10515   {
10516     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10517     { Bad_Opcode },
10518     { "knotq",          { MaskG, MaskR }, 0 },
10519   },
10520   {
10521     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10522     { Bad_Opcode },
10523     { "knotb",          { MaskG, MaskR }, 0 },
10524   },
10525   {
10526     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10527     { Bad_Opcode },
10528     { "knotd",          { MaskG, MaskR }, 0 },
10529   },
10530   {
10531     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10532     { Bad_Opcode },
10533     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10534   },
10535   {
10536     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10537     { Bad_Opcode },
10538     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10539   },
10540   {
10541     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10542     { Bad_Opcode },
10543     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10544   },
10545   {
10546     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10547     { Bad_Opcode },
10548     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10549   },
10550  {
10551     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10552     { Bad_Opcode },
10553     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10554   },
10555   {
10556     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10557     { Bad_Opcode },
10558     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10559   },
10560   {
10561     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10562     { Bad_Opcode },
10563     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10564   },
10565   {
10566     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10567     { Bad_Opcode },
10568     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10569   },
10570   {
10571     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10572     { Bad_Opcode },
10573     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10574   },
10575   {
10576     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10577     { Bad_Opcode },
10578     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10579   },
10580   {
10581     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10582     { Bad_Opcode },
10583     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10584   },
10585   {
10586     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10587     { Bad_Opcode },
10588     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10589   },
10590   {
10591     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10592     { Bad_Opcode },
10593     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10594   },
10595   {
10596     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10597     { Bad_Opcode },
10598     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10599   },
10600   {
10601     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10602     { Bad_Opcode },
10603     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10604   },
10605   {
10606     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10607     { Bad_Opcode },
10608     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10609   },
10610   {
10611     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10612     { Bad_Opcode },
10613     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10614   },
10615   {
10616     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10617     { Bad_Opcode },
10618     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10619   },
10620   {
10621     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10622     { Bad_Opcode },
10623     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10624   },
10625   {
10626     /* MOD_VEX_0F50 */
10627     { Bad_Opcode },
10628     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10629   },
10630   {
10631     /* MOD_VEX_0F71_REG_2 */
10632     { Bad_Opcode },
10633     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10634   },
10635   {
10636     /* MOD_VEX_0F71_REG_4 */
10637     { Bad_Opcode },
10638     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10639   },
10640   {
10641     /* MOD_VEX_0F71_REG_6 */
10642     { Bad_Opcode },
10643     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10644   },
10645   {
10646     /* MOD_VEX_0F72_REG_2 */
10647     { Bad_Opcode },
10648     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10649   },
10650   {
10651     /* MOD_VEX_0F72_REG_4 */
10652     { Bad_Opcode },
10653     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10654   },
10655   {
10656     /* MOD_VEX_0F72_REG_6 */
10657     { Bad_Opcode },
10658     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10659   },
10660   {
10661     /* MOD_VEX_0F73_REG_2 */
10662     { Bad_Opcode },
10663     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10664   },
10665   {
10666     /* MOD_VEX_0F73_REG_3 */
10667     { Bad_Opcode },
10668     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10669   },
10670   {
10671     /* MOD_VEX_0F73_REG_6 */
10672     { Bad_Opcode },
10673     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10674   },
10675   {
10676     /* MOD_VEX_0F73_REG_7 */
10677     { Bad_Opcode },
10678     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10679   },
10680   {
10681     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10682     { "kmovw",          { Ew, MaskG }, 0 },
10683     { Bad_Opcode },
10684   },
10685   {
10686     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10687     { "kmovq",          { Eq, MaskG }, 0 },
10688     { Bad_Opcode },
10689   },
10690   {
10691     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10692     { "kmovb",          { Eb, MaskG }, 0 },
10693     { Bad_Opcode },
10694   },
10695   {
10696     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10697     { "kmovd",          { Ed, MaskG }, 0 },
10698     { Bad_Opcode },
10699   },
10700   {
10701     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10702     { Bad_Opcode },
10703     { "kmovw",          { MaskG, Rdq }, 0 },
10704   },
10705   {
10706     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10707     { Bad_Opcode },
10708     { "kmovb",          { MaskG, Rdq }, 0 },
10709   },
10710   {
10711     /* MOD_VEX_0F92_P_3_LEN_0 */
10712     { Bad_Opcode },
10713     { "kmovK",          { MaskG, Rdq }, 0 },
10714   },
10715   {
10716     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10717     { Bad_Opcode },
10718     { "kmovw",          { Gdq, MaskR }, 0 },
10719   },
10720   {
10721     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10722     { Bad_Opcode },
10723     { "kmovb",          { Gdq, MaskR }, 0 },
10724   },
10725   {
10726     /* MOD_VEX_0F93_P_3_LEN_0 */
10727     { Bad_Opcode },
10728     { "kmovK",          { Gdq, MaskR }, 0 },
10729   },
10730   {
10731     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10732     { Bad_Opcode },
10733     { "kortestw", { MaskG, MaskR }, 0 },
10734   },
10735   {
10736     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10737     { Bad_Opcode },
10738     { "kortestq", { MaskG, MaskR }, 0 },
10739   },
10740   {
10741     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10742     { Bad_Opcode },
10743     { "kortestb", { MaskG, MaskR }, 0 },
10744   },
10745   {
10746     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10747     { Bad_Opcode },
10748     { "kortestd", { MaskG, MaskR }, 0 },
10749   },
10750   {
10751     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10752     { Bad_Opcode },
10753     { "ktestw", { MaskG, MaskR }, 0 },
10754   },
10755   {
10756     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10757     { Bad_Opcode },
10758     { "ktestq", { MaskG, MaskR }, 0 },
10759   },
10760   {
10761     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10762     { Bad_Opcode },
10763     { "ktestb", { MaskG, MaskR }, 0 },
10764   },
10765   {
10766     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10767     { Bad_Opcode },
10768     { "ktestd", { MaskG, MaskR }, 0 },
10769   },
10770   {
10771     /* MOD_VEX_0FAE_REG_2 */
10772     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10773   },
10774   {
10775     /* MOD_VEX_0FAE_REG_3 */
10776     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10777   },
10778   {
10779     /* MOD_VEX_0FD7_PREFIX_2 */
10780     { Bad_Opcode },
10781     { "vpmovmskb",      { Gdq, XS }, 0 },
10782   },
10783   {
10784     /* MOD_VEX_0FE7_PREFIX_2 */
10785     { "vmovntdq",       { Mx, XM }, 0 },
10786   },
10787   {
10788     /* MOD_VEX_0FF0_PREFIX_3 */
10789     { "vlddqu",         { XM, M }, 0 },
10790   },
10791   {
10792     /* MOD_VEX_0F381A_PREFIX_2 */
10793     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10794   },
10795   {
10796     /* MOD_VEX_0F382A_PREFIX_2 */
10797     { "vmovntdqa",      { XM, Mx }, 0 },
10798   },
10799   {
10800     /* MOD_VEX_0F382C_PREFIX_2 */
10801     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10802   },
10803   {
10804     /* MOD_VEX_0F382D_PREFIX_2 */
10805     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10806   },
10807   {
10808     /* MOD_VEX_0F382E_PREFIX_2 */
10809     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10810   },
10811   {
10812     /* MOD_VEX_0F382F_PREFIX_2 */
10813     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10814   },
10815   {
10816     /* MOD_VEX_0F385A_PREFIX_2 */
10817     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10818   },
10819   {
10820     /* MOD_VEX_0F388C_PREFIX_2 */
10821     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10822   },
10823   {
10824     /* MOD_VEX_0F388E_PREFIX_2 */
10825     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10826   },
10827   {
10828     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10829     { Bad_Opcode },
10830     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10831   },
10832   {
10833     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10834     { Bad_Opcode },
10835     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10836   },
10837   {
10838     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10839     { Bad_Opcode },
10840     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10841   },
10842   {
10843     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10844     { Bad_Opcode },
10845     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10846   },
10847   {
10848     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10849     { Bad_Opcode },
10850     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10851   },
10852   {
10853     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10854     { Bad_Opcode },
10855     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10856   },
10857   {
10858     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10859     { Bad_Opcode },
10860     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10861   },
10862   {
10863     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10864     { Bad_Opcode },
10865     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10866   },
10867
10868 #include "i386-dis-evex-mod.h"
10869 };
10870
10871 static const struct dis386 rm_table[][8] = {
10872   {
10873     /* RM_C6_REG_7 */
10874     { "xabort",         { Skip_MODRM, Ib }, 0 },
10875   },
10876   {
10877     /* RM_C7_REG_7 */
10878     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10879   },
10880   {
10881     /* RM_0F01_REG_0 */
10882     { "enclv",          { Skip_MODRM }, 0 },
10883     { "vmcall",         { Skip_MODRM }, 0 },
10884     { "vmlaunch",       { Skip_MODRM }, 0 },
10885     { "vmresume",       { Skip_MODRM }, 0 },
10886     { "vmxoff",         { Skip_MODRM }, 0 },
10887     { "pconfig",        { Skip_MODRM }, 0 },
10888   },
10889   {
10890     /* RM_0F01_REG_1 */
10891     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10892     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10893     { "clac",           { Skip_MODRM }, 0 },
10894     { "stac",           { Skip_MODRM }, 0 },
10895     { Bad_Opcode },
10896     { Bad_Opcode },
10897     { Bad_Opcode },
10898     { "encls",          { Skip_MODRM }, 0 },
10899   },
10900   {
10901     /* RM_0F01_REG_2 */
10902     { "xgetbv",         { Skip_MODRM }, 0 },
10903     { "xsetbv",         { Skip_MODRM }, 0 },
10904     { Bad_Opcode },
10905     { Bad_Opcode },
10906     { "vmfunc",         { Skip_MODRM }, 0 },
10907     { "xend",           { Skip_MODRM }, 0 },
10908     { "xtest",          { Skip_MODRM }, 0 },
10909     { "enclu",          { Skip_MODRM }, 0 },
10910   },
10911   {
10912     /* RM_0F01_REG_3 */
10913     { "vmrun",          { Skip_MODRM }, 0 },
10914     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10915     { "vmload",         { Skip_MODRM }, 0 },
10916     { "vmsave",         { Skip_MODRM }, 0 },
10917     { "stgi",           { Skip_MODRM }, 0 },
10918     { "clgi",           { Skip_MODRM }, 0 },
10919     { "skinit",         { Skip_MODRM }, 0 },
10920     { "invlpga",        { Skip_MODRM }, 0 },
10921   },
10922   {
10923     /* RM_0F01_REG_5_MOD_3 */
10924     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10925     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10926     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10927     { Bad_Opcode },
10928     { Bad_Opcode },
10929     { Bad_Opcode },
10930     { "rdpkru",         { Skip_MODRM }, 0 },
10931     { "wrpkru",         { Skip_MODRM }, 0 },
10932   },
10933   {
10934     /* RM_0F01_REG_7_MOD_3 */
10935     { "swapgs",         { Skip_MODRM }, 0  },
10936     { "rdtscp",         { Skip_MODRM }, 0  },
10937     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
10938     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
10939     { "clzero",         { Skip_MODRM }, 0  },
10940     { "rdpru",          { Skip_MODRM }, 0  },
10941   },
10942   {
10943     /* RM_0F1E_P_1_MOD_3_REG_7 */
10944     { "nopQ",           { Ev }, 0 },
10945     { "nopQ",           { Ev }, 0 },
10946     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
10947     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
10948     { "nopQ",           { Ev }, 0 },
10949     { "nopQ",           { Ev }, 0 },
10950     { "nopQ",           { Ev }, 0 },
10951     { "nopQ",           { Ev }, 0 },
10952   },
10953   {
10954     /* RM_0FAE_REG_6_MOD_3 */
10955     { "mfence",         { Skip_MODRM }, 0 },
10956   },
10957   {
10958     /* RM_0FAE_REG_7_MOD_3 */
10959     { "sfence",         { Skip_MODRM }, 0 },
10960
10961   },
10962 };
10963
10964 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10965
10966 /* We use the high bit to indicate different name for the same
10967    prefix.  */
10968 #define REP_PREFIX      (0xf3 | 0x100)
10969 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10970 #define XRELEASE_PREFIX (0xf3 | 0x400)
10971 #define BND_PREFIX      (0xf2 | 0x400)
10972 #define NOTRACK_PREFIX  (0x3e | 0x100)
10973
10974 /* Remember if the current op is a jump instruction.  */
10975 static bfd_boolean op_is_jump = FALSE;
10976
10977 static int
10978 ckprefix (void)
10979 {
10980   int newrex, i, length;
10981   rex = 0;
10982   prefixes = 0;
10983   used_prefixes = 0;
10984   rex_used = 0;
10985   last_lock_prefix = -1;
10986   last_repz_prefix = -1;
10987   last_repnz_prefix = -1;
10988   last_data_prefix = -1;
10989   last_addr_prefix = -1;
10990   last_rex_prefix = -1;
10991   last_seg_prefix = -1;
10992   fwait_prefix = -1;
10993   active_seg_prefix = 0;
10994   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10995     all_prefixes[i] = 0;
10996   i = 0;
10997   length = 0;
10998   /* The maximum instruction length is 15bytes.  */
10999   while (length < MAX_CODE_LENGTH - 1)
11000     {
11001       FETCH_DATA (the_info, codep + 1);
11002       newrex = 0;
11003       switch (*codep)
11004         {
11005         /* REX prefixes family.  */
11006         case 0x40:
11007         case 0x41:
11008         case 0x42:
11009         case 0x43:
11010         case 0x44:
11011         case 0x45:
11012         case 0x46:
11013         case 0x47:
11014         case 0x48:
11015         case 0x49:
11016         case 0x4a:
11017         case 0x4b:
11018         case 0x4c:
11019         case 0x4d:
11020         case 0x4e:
11021         case 0x4f:
11022           if (address_mode == mode_64bit)
11023             newrex = *codep;
11024           else
11025             return 1;
11026           last_rex_prefix = i;
11027           break;
11028         case 0xf3:
11029           prefixes |= PREFIX_REPZ;
11030           last_repz_prefix = i;
11031           break;
11032         case 0xf2:
11033           prefixes |= PREFIX_REPNZ;
11034           last_repnz_prefix = i;
11035           break;
11036         case 0xf0:
11037           prefixes |= PREFIX_LOCK;
11038           last_lock_prefix = i;
11039           break;
11040         case 0x2e:
11041           prefixes |= PREFIX_CS;
11042           last_seg_prefix = i;
11043           active_seg_prefix = PREFIX_CS;
11044           break;
11045         case 0x36:
11046           prefixes |= PREFIX_SS;
11047           last_seg_prefix = i;
11048           active_seg_prefix = PREFIX_SS;
11049           break;
11050         case 0x3e:
11051           prefixes |= PREFIX_DS;
11052           last_seg_prefix = i;
11053           active_seg_prefix = PREFIX_DS;
11054           break;
11055         case 0x26:
11056           prefixes |= PREFIX_ES;
11057           last_seg_prefix = i;
11058           active_seg_prefix = PREFIX_ES;
11059           break;
11060         case 0x64:
11061           prefixes |= PREFIX_FS;
11062           last_seg_prefix = i;
11063           active_seg_prefix = PREFIX_FS;
11064           break;
11065         case 0x65:
11066           prefixes |= PREFIX_GS;
11067           last_seg_prefix = i;
11068           active_seg_prefix = PREFIX_GS;
11069           break;
11070         case 0x66:
11071           prefixes |= PREFIX_DATA;
11072           last_data_prefix = i;
11073           break;
11074         case 0x67:
11075           prefixes |= PREFIX_ADDR;
11076           last_addr_prefix = i;
11077           break;
11078         case FWAIT_OPCODE:
11079           /* fwait is really an instruction.  If there are prefixes
11080              before the fwait, they belong to the fwait, *not* to the
11081              following instruction.  */
11082           fwait_prefix = i;
11083           if (prefixes || rex)
11084             {
11085               prefixes |= PREFIX_FWAIT;
11086               codep++;
11087               /* This ensures that the previous REX prefixes are noticed
11088                  as unused prefixes, as in the return case below.  */
11089               rex_used = rex;
11090               return 1;
11091             }
11092           prefixes = PREFIX_FWAIT;
11093           break;
11094         default:
11095           return 1;
11096         }
11097       /* Rex is ignored when followed by another prefix.  */
11098       if (rex)
11099         {
11100           rex_used = rex;
11101           return 1;
11102         }
11103       if (*codep != FWAIT_OPCODE)
11104         all_prefixes[i++] = *codep;
11105       rex = newrex;
11106       codep++;
11107       length++;
11108     }
11109   return 0;
11110 }
11111
11112 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11113    prefix byte.  */
11114
11115 static const char *
11116 prefix_name (int pref, int sizeflag)
11117 {
11118   static const char *rexes [16] =
11119     {
11120       "rex",            /* 0x40 */
11121       "rex.B",          /* 0x41 */
11122       "rex.X",          /* 0x42 */
11123       "rex.XB",         /* 0x43 */
11124       "rex.R",          /* 0x44 */
11125       "rex.RB",         /* 0x45 */
11126       "rex.RX",         /* 0x46 */
11127       "rex.RXB",        /* 0x47 */
11128       "rex.W",          /* 0x48 */
11129       "rex.WB",         /* 0x49 */
11130       "rex.WX",         /* 0x4a */
11131       "rex.WXB",        /* 0x4b */
11132       "rex.WR",         /* 0x4c */
11133       "rex.WRB",        /* 0x4d */
11134       "rex.WRX",        /* 0x4e */
11135       "rex.WRXB",       /* 0x4f */
11136     };
11137
11138   switch (pref)
11139     {
11140     /* REX prefixes family.  */
11141     case 0x40:
11142     case 0x41:
11143     case 0x42:
11144     case 0x43:
11145     case 0x44:
11146     case 0x45:
11147     case 0x46:
11148     case 0x47:
11149     case 0x48:
11150     case 0x49:
11151     case 0x4a:
11152     case 0x4b:
11153     case 0x4c:
11154     case 0x4d:
11155     case 0x4e:
11156     case 0x4f:
11157       return rexes [pref - 0x40];
11158     case 0xf3:
11159       return "repz";
11160     case 0xf2:
11161       return "repnz";
11162     case 0xf0:
11163       return "lock";
11164     case 0x2e:
11165       return "cs";
11166     case 0x36:
11167       return "ss";
11168     case 0x3e:
11169       return "ds";
11170     case 0x26:
11171       return "es";
11172     case 0x64:
11173       return "fs";
11174     case 0x65:
11175       return "gs";
11176     case 0x66:
11177       return (sizeflag & DFLAG) ? "data16" : "data32";
11178     case 0x67:
11179       if (address_mode == mode_64bit)
11180         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11181       else
11182         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11183     case FWAIT_OPCODE:
11184       return "fwait";
11185     case REP_PREFIX:
11186       return "rep";
11187     case XACQUIRE_PREFIX:
11188       return "xacquire";
11189     case XRELEASE_PREFIX:
11190       return "xrelease";
11191     case BND_PREFIX:
11192       return "bnd";
11193     case NOTRACK_PREFIX:
11194       return "notrack";
11195     default:
11196       return NULL;
11197     }
11198 }
11199
11200 static char op_out[MAX_OPERANDS][100];
11201 static int op_ad, op_index[MAX_OPERANDS];
11202 static int two_source_ops;
11203 static bfd_vma op_address[MAX_OPERANDS];
11204 static bfd_vma op_riprel[MAX_OPERANDS];
11205 static bfd_vma start_pc;
11206
11207 /*
11208  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11209  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11210  *   section of the "Virtual 8086 Mode" chapter.)
11211  * 'pc' should be the address of this instruction, it will
11212  *   be used to print the target address if this is a relative jump or call
11213  * The function returns the length of this instruction in bytes.
11214  */
11215
11216 static char intel_syntax;
11217 static char intel_mnemonic = !SYSV386_COMPAT;
11218 static char open_char;
11219 static char close_char;
11220 static char separator_char;
11221 static char scale_char;
11222
11223 enum x86_64_isa
11224 {
11225   amd64 = 1,
11226   intel64
11227 };
11228
11229 static enum x86_64_isa isa64;
11230
11231 /* Here for backwards compatibility.  When gdb stops using
11232    print_insn_i386_att and print_insn_i386_intel these functions can
11233    disappear, and print_insn_i386 be merged into print_insn.  */
11234 int
11235 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11236 {
11237   intel_syntax = 0;
11238
11239   return print_insn (pc, info);
11240 }
11241
11242 int
11243 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11244 {
11245   intel_syntax = 1;
11246
11247   return print_insn (pc, info);
11248 }
11249
11250 int
11251 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11252 {
11253   intel_syntax = -1;
11254
11255   return print_insn (pc, info);
11256 }
11257
11258 void
11259 print_i386_disassembler_options (FILE *stream)
11260 {
11261   fprintf (stream, _("\n\
11262 The following i386/x86-64 specific disassembler options are supported for use\n\
11263 with the -M switch (multiple options should be separated by commas):\n"));
11264
11265   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11266   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11267   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11268   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11269   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11270   fprintf (stream, _("  att-mnemonic\n"
11271                      "              Display instruction in AT&T mnemonic\n"));
11272   fprintf (stream, _("  intel-mnemonic\n"
11273                      "              Display instruction in Intel mnemonic\n"));
11274   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11275   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11276   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11277   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11278   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11279   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11280   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11281   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11282 }
11283
11284 /* Bad opcode.  */
11285 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11286
11287 /* Get a pointer to struct dis386 with a valid name.  */
11288
11289 static const struct dis386 *
11290 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11291 {
11292   int vindex, vex_table_index;
11293
11294   if (dp->name != NULL)
11295     return dp;
11296
11297   switch (dp->op[0].bytemode)
11298     {
11299     case USE_REG_TABLE:
11300       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11301       break;
11302
11303     case USE_MOD_TABLE:
11304       vindex = modrm.mod == 0x3 ? 1 : 0;
11305       dp = &mod_table[dp->op[1].bytemode][vindex];
11306       break;
11307
11308     case USE_RM_TABLE:
11309       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11310       break;
11311
11312     case USE_PREFIX_TABLE:
11313       if (need_vex)
11314         {
11315           /* The prefix in VEX is implicit.  */
11316           switch (vex.prefix)
11317             {
11318             case 0:
11319               vindex = 0;
11320               break;
11321             case REPE_PREFIX_OPCODE:
11322               vindex = 1;
11323               break;
11324             case DATA_PREFIX_OPCODE:
11325               vindex = 2;
11326               break;
11327             case REPNE_PREFIX_OPCODE:
11328               vindex = 3;
11329               break;
11330             default:
11331               abort ();
11332               break;
11333             }
11334         }
11335       else
11336         {
11337           int last_prefix = -1;
11338           int prefix = 0;
11339           vindex = 0;
11340           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11341              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11342              last one wins.  */
11343           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11344             {
11345               if (last_repz_prefix > last_repnz_prefix)
11346                 {
11347                   vindex = 1;
11348                   prefix = PREFIX_REPZ;
11349                   last_prefix = last_repz_prefix;
11350                 }
11351               else
11352                 {
11353                   vindex = 3;
11354                   prefix = PREFIX_REPNZ;
11355                   last_prefix = last_repnz_prefix;
11356                 }
11357
11358               /* Check if prefix should be ignored.  */
11359               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11360                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11361                    & prefix) != 0)
11362                 vindex = 0;
11363             }
11364
11365           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11366             {
11367               vindex = 2;
11368               prefix = PREFIX_DATA;
11369               last_prefix = last_data_prefix;
11370             }
11371
11372           if (vindex != 0)
11373             {
11374               used_prefixes |= prefix;
11375               all_prefixes[last_prefix] = 0;
11376             }
11377         }
11378       dp = &prefix_table[dp->op[1].bytemode][vindex];
11379       break;
11380
11381     case USE_X86_64_TABLE:
11382       vindex = address_mode == mode_64bit ? 1 : 0;
11383       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11384       break;
11385
11386     case USE_3BYTE_TABLE:
11387       FETCH_DATA (info, codep + 2);
11388       vindex = *codep++;
11389       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11390       end_codep = codep;
11391       modrm.mod = (*codep >> 6) & 3;
11392       modrm.reg = (*codep >> 3) & 7;
11393       modrm.rm = *codep & 7;
11394       break;
11395
11396     case USE_VEX_LEN_TABLE:
11397       if (!need_vex)
11398         abort ();
11399
11400       switch (vex.length)
11401         {
11402         case 128:
11403           vindex = 0;
11404           break;
11405         case 256:
11406           vindex = 1;
11407           break;
11408         default:
11409           abort ();
11410           break;
11411         }
11412
11413       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11414       break;
11415
11416     case USE_EVEX_LEN_TABLE:
11417       if (!vex.evex)
11418         abort ();
11419
11420       switch (vex.length)
11421         {
11422         case 128:
11423           vindex = 0;
11424           break;
11425         case 256:
11426           vindex = 1;
11427           break;
11428         case 512:
11429           vindex = 2;
11430           break;
11431         default:
11432           abort ();
11433           break;
11434         }
11435
11436       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11437       break;
11438
11439     case USE_XOP_8F_TABLE:
11440       FETCH_DATA (info, codep + 3);
11441       rex = ~(*codep >> 5) & 0x7;
11442
11443       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11444       switch ((*codep & 0x1f))
11445         {
11446         default:
11447           dp = &bad_opcode;
11448           return dp;
11449         case 0x8:
11450           vex_table_index = XOP_08;
11451           break;
11452         case 0x9:
11453           vex_table_index = XOP_09;
11454           break;
11455         case 0xa:
11456           vex_table_index = XOP_0A;
11457           break;
11458         }
11459       codep++;
11460       vex.w = *codep & 0x80;
11461       if (vex.w && address_mode == mode_64bit)
11462         rex |= REX_W;
11463
11464       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11465       if (address_mode != mode_64bit)
11466         {
11467           /* In 16/32-bit mode REX_B is silently ignored.  */
11468           rex &= ~REX_B;
11469         }
11470
11471       vex.length = (*codep & 0x4) ? 256 : 128;
11472       switch ((*codep & 0x3))
11473         {
11474         case 0:
11475           break;
11476         case 1:
11477           vex.prefix = DATA_PREFIX_OPCODE;
11478           break;
11479         case 2:
11480           vex.prefix = REPE_PREFIX_OPCODE;
11481           break;
11482         case 3:
11483           vex.prefix = REPNE_PREFIX_OPCODE;
11484           break;
11485         }
11486       need_vex = 1;
11487       need_vex_reg = 1;
11488       codep++;
11489       vindex = *codep++;
11490       dp = &xop_table[vex_table_index][vindex];
11491
11492       end_codep = codep;
11493       FETCH_DATA (info, codep + 1);
11494       modrm.mod = (*codep >> 6) & 3;
11495       modrm.reg = (*codep >> 3) & 7;
11496       modrm.rm = *codep & 7;
11497
11498       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
11499          having to decode the bits for every otherwise valid encoding.  */
11500       if (vex.prefix)
11501         return &bad_opcode;
11502       break;
11503
11504     case USE_VEX_C4_TABLE:
11505       /* VEX prefix.  */
11506       FETCH_DATA (info, codep + 3);
11507       rex = ~(*codep >> 5) & 0x7;
11508       switch ((*codep & 0x1f))
11509         {
11510         default:
11511           dp = &bad_opcode;
11512           return dp;
11513         case 0x1:
11514           vex_table_index = VEX_0F;
11515           break;
11516         case 0x2:
11517           vex_table_index = VEX_0F38;
11518           break;
11519         case 0x3:
11520           vex_table_index = VEX_0F3A;
11521           break;
11522         }
11523       codep++;
11524       vex.w = *codep & 0x80;
11525       if (address_mode == mode_64bit)
11526         {
11527           if (vex.w)
11528             rex |= REX_W;
11529         }
11530       else
11531         {
11532           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11533              is ignored, other REX bits are 0 and the highest bit in
11534              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11535           rex = 0;
11536         }
11537       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11538       vex.length = (*codep & 0x4) ? 256 : 128;
11539       switch ((*codep & 0x3))
11540         {
11541         case 0:
11542           break;
11543         case 1:
11544           vex.prefix = DATA_PREFIX_OPCODE;
11545           break;
11546         case 2:
11547           vex.prefix = REPE_PREFIX_OPCODE;
11548           break;
11549         case 3:
11550           vex.prefix = REPNE_PREFIX_OPCODE;
11551           break;
11552         }
11553       need_vex = 1;
11554       need_vex_reg = 1;
11555       codep++;
11556       vindex = *codep++;
11557       dp = &vex_table[vex_table_index][vindex];
11558       end_codep = codep;
11559       /* There is no MODRM byte for VEX0F 77.  */
11560       if (vex_table_index != VEX_0F || vindex != 0x77)
11561         {
11562           FETCH_DATA (info, codep + 1);
11563           modrm.mod = (*codep >> 6) & 3;
11564           modrm.reg = (*codep >> 3) & 7;
11565           modrm.rm = *codep & 7;
11566         }
11567       break;
11568
11569     case USE_VEX_C5_TABLE:
11570       /* VEX prefix.  */
11571       FETCH_DATA (info, codep + 2);
11572       rex = (*codep & 0x80) ? 0 : REX_R;
11573
11574       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11575          VEX.vvvv is 1.  */
11576       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11577       vex.length = (*codep & 0x4) ? 256 : 128;
11578       switch ((*codep & 0x3))
11579         {
11580         case 0:
11581           break;
11582         case 1:
11583           vex.prefix = DATA_PREFIX_OPCODE;
11584           break;
11585         case 2:
11586           vex.prefix = REPE_PREFIX_OPCODE;
11587           break;
11588         case 3:
11589           vex.prefix = REPNE_PREFIX_OPCODE;
11590           break;
11591         }
11592       need_vex = 1;
11593       need_vex_reg = 1;
11594       codep++;
11595       vindex = *codep++;
11596       dp = &vex_table[dp->op[1].bytemode][vindex];
11597       end_codep = codep;
11598       /* There is no MODRM byte for VEX 77.  */
11599       if (vindex != 0x77)
11600         {
11601           FETCH_DATA (info, codep + 1);
11602           modrm.mod = (*codep >> 6) & 3;
11603           modrm.reg = (*codep >> 3) & 7;
11604           modrm.rm = *codep & 7;
11605         }
11606       break;
11607
11608     case USE_VEX_W_TABLE:
11609       if (!need_vex)
11610         abort ();
11611
11612       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11613       break;
11614
11615     case USE_EVEX_TABLE:
11616       two_source_ops = 0;
11617       /* EVEX prefix.  */
11618       vex.evex = 1;
11619       FETCH_DATA (info, codep + 4);
11620       /* The first byte after 0x62.  */
11621       rex = ~(*codep >> 5) & 0x7;
11622       vex.r = *codep & 0x10;
11623       switch ((*codep & 0xf))
11624         {
11625         default:
11626           return &bad_opcode;
11627         case 0x1:
11628           vex_table_index = EVEX_0F;
11629           break;
11630         case 0x2:
11631           vex_table_index = EVEX_0F38;
11632           break;
11633         case 0x3:
11634           vex_table_index = EVEX_0F3A;
11635           break;
11636         }
11637
11638       /* The second byte after 0x62.  */
11639       codep++;
11640       vex.w = *codep & 0x80;
11641       if (vex.w && address_mode == mode_64bit)
11642         rex |= REX_W;
11643
11644       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11645
11646       /* The U bit.  */
11647       if (!(*codep & 0x4))
11648         return &bad_opcode;
11649
11650       switch ((*codep & 0x3))
11651         {
11652         case 0:
11653           break;
11654         case 1:
11655           vex.prefix = DATA_PREFIX_OPCODE;
11656           break;
11657         case 2:
11658           vex.prefix = REPE_PREFIX_OPCODE;
11659           break;
11660         case 3:
11661           vex.prefix = REPNE_PREFIX_OPCODE;
11662           break;
11663         }
11664
11665       /* The third byte after 0x62.  */
11666       codep++;
11667
11668       /* Remember the static rounding bits.  */
11669       vex.ll = (*codep >> 5) & 3;
11670       vex.b = (*codep & 0x10) != 0;
11671
11672       vex.v = *codep & 0x8;
11673       vex.mask_register_specifier = *codep & 0x7;
11674       vex.zeroing = *codep & 0x80;
11675
11676       if (address_mode != mode_64bit)
11677         {
11678           /* In 16/32-bit mode silently ignore following bits.  */
11679           rex &= ~REX_B;
11680           vex.r = 1;
11681           vex.v = 1;
11682         }
11683
11684       need_vex = 1;
11685       need_vex_reg = 1;
11686       codep++;
11687       vindex = *codep++;
11688       dp = &evex_table[vex_table_index][vindex];
11689       end_codep = codep;
11690       FETCH_DATA (info, codep + 1);
11691       modrm.mod = (*codep >> 6) & 3;
11692       modrm.reg = (*codep >> 3) & 7;
11693       modrm.rm = *codep & 7;
11694
11695       /* Set vector length.  */
11696       if (modrm.mod == 3 && vex.b)
11697         vex.length = 512;
11698       else
11699         {
11700           switch (vex.ll)
11701             {
11702             case 0x0:
11703               vex.length = 128;
11704               break;
11705             case 0x1:
11706               vex.length = 256;
11707               break;
11708             case 0x2:
11709               vex.length = 512;
11710               break;
11711             default:
11712               return &bad_opcode;
11713             }
11714         }
11715       break;
11716
11717     case 0:
11718       dp = &bad_opcode;
11719       break;
11720
11721     default:
11722       abort ();
11723     }
11724
11725   if (dp->name != NULL)
11726     return dp;
11727   else
11728     return get_valid_dis386 (dp, info);
11729 }
11730
11731 static void
11732 get_sib (disassemble_info *info, int sizeflag)
11733 {
11734   /* If modrm.mod == 3, operand must be register.  */
11735   if (need_modrm
11736       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11737       && modrm.mod != 3
11738       && modrm.rm == 4)
11739     {
11740       FETCH_DATA (info, codep + 2);
11741       sib.index = (codep [1] >> 3) & 7;
11742       sib.scale = (codep [1] >> 6) & 3;
11743       sib.base = codep [1] & 7;
11744     }
11745 }
11746
11747 static int
11748 print_insn (bfd_vma pc, disassemble_info *info)
11749 {
11750   const struct dis386 *dp;
11751   int i;
11752   char *op_txt[MAX_OPERANDS];
11753   int needcomma;
11754   int sizeflag, orig_sizeflag;
11755   const char *p;
11756   struct dis_private priv;
11757   int prefix_length;
11758
11759   priv.orig_sizeflag = AFLAG | DFLAG;
11760   if ((info->mach & bfd_mach_i386_i386) != 0)
11761     address_mode = mode_32bit;
11762   else if (info->mach == bfd_mach_i386_i8086)
11763     {
11764       address_mode = mode_16bit;
11765       priv.orig_sizeflag = 0;
11766     }
11767   else
11768     address_mode = mode_64bit;
11769
11770   if (intel_syntax == (char) -1)
11771     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11772
11773   for (p = info->disassembler_options; p != NULL; )
11774     {
11775       if (CONST_STRNEQ (p, "amd64"))
11776         isa64 = amd64;
11777       else if (CONST_STRNEQ (p, "intel64"))
11778         isa64 = intel64;
11779       else if (CONST_STRNEQ (p, "x86-64"))
11780         {
11781           address_mode = mode_64bit;
11782           priv.orig_sizeflag |= AFLAG | DFLAG;
11783         }
11784       else if (CONST_STRNEQ (p, "i386"))
11785         {
11786           address_mode = mode_32bit;
11787           priv.orig_sizeflag |= AFLAG | DFLAG;
11788         }
11789       else if (CONST_STRNEQ (p, "i8086"))
11790         {
11791           address_mode = mode_16bit;
11792           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11793         }
11794       else if (CONST_STRNEQ (p, "intel"))
11795         {
11796           intel_syntax = 1;
11797           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11798             intel_mnemonic = 1;
11799         }
11800       else if (CONST_STRNEQ (p, "att"))
11801         {
11802           intel_syntax = 0;
11803           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11804             intel_mnemonic = 0;
11805         }
11806       else if (CONST_STRNEQ (p, "addr"))
11807         {
11808           if (address_mode == mode_64bit)
11809             {
11810               if (p[4] == '3' && p[5] == '2')
11811                 priv.orig_sizeflag &= ~AFLAG;
11812               else if (p[4] == '6' && p[5] == '4')
11813                 priv.orig_sizeflag |= AFLAG;
11814             }
11815           else
11816             {
11817               if (p[4] == '1' && p[5] == '6')
11818                 priv.orig_sizeflag &= ~AFLAG;
11819               else if (p[4] == '3' && p[5] == '2')
11820                 priv.orig_sizeflag |= AFLAG;
11821             }
11822         }
11823       else if (CONST_STRNEQ (p, "data"))
11824         {
11825           if (p[4] == '1' && p[5] == '6')
11826             priv.orig_sizeflag &= ~DFLAG;
11827           else if (p[4] == '3' && p[5] == '2')
11828             priv.orig_sizeflag |= DFLAG;
11829         }
11830       else if (CONST_STRNEQ (p, "suffix"))
11831         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11832
11833       p = strchr (p, ',');
11834       if (p != NULL)
11835         p++;
11836     }
11837
11838   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11839     {
11840       (*info->fprintf_func) (info->stream,
11841                              _("64-bit address is disabled"));
11842       return -1;
11843     }
11844
11845   if (intel_syntax)
11846     {
11847       names64 = intel_names64;
11848       names32 = intel_names32;
11849       names16 = intel_names16;
11850       names8 = intel_names8;
11851       names8rex = intel_names8rex;
11852       names_seg = intel_names_seg;
11853       names_mm = intel_names_mm;
11854       names_bnd = intel_names_bnd;
11855       names_xmm = intel_names_xmm;
11856       names_ymm = intel_names_ymm;
11857       names_zmm = intel_names_zmm;
11858       index64 = intel_index64;
11859       index32 = intel_index32;
11860       names_mask = intel_names_mask;
11861       index16 = intel_index16;
11862       open_char = '[';
11863       close_char = ']';
11864       separator_char = '+';
11865       scale_char = '*';
11866     }
11867   else
11868     {
11869       names64 = att_names64;
11870       names32 = att_names32;
11871       names16 = att_names16;
11872       names8 = att_names8;
11873       names8rex = att_names8rex;
11874       names_seg = att_names_seg;
11875       names_mm = att_names_mm;
11876       names_bnd = att_names_bnd;
11877       names_xmm = att_names_xmm;
11878       names_ymm = att_names_ymm;
11879       names_zmm = att_names_zmm;
11880       index64 = att_index64;
11881       index32 = att_index32;
11882       names_mask = att_names_mask;
11883       index16 = att_index16;
11884       open_char = '(';
11885       close_char =  ')';
11886       separator_char = ',';
11887       scale_char = ',';
11888     }
11889
11890   /* The output looks better if we put 7 bytes on a line, since that
11891      puts most long word instructions on a single line.  Use 8 bytes
11892      for Intel L1OM.  */
11893   if ((info->mach & bfd_mach_l1om) != 0)
11894     info->bytes_per_line = 8;
11895   else
11896     info->bytes_per_line = 7;
11897
11898   info->private_data = &priv;
11899   priv.max_fetched = priv.the_buffer;
11900   priv.insn_start = pc;
11901
11902   obuf[0] = 0;
11903   for (i = 0; i < MAX_OPERANDS; ++i)
11904     {
11905       op_out[i][0] = 0;
11906       op_index[i] = -1;
11907     }
11908
11909   the_info = info;
11910   start_pc = pc;
11911   start_codep = priv.the_buffer;
11912   codep = priv.the_buffer;
11913
11914   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11915     {
11916       const char *name;
11917
11918       /* Getting here means we tried for data but didn't get it.  That
11919          means we have an incomplete instruction of some sort.  Just
11920          print the first byte as a prefix or a .byte pseudo-op.  */
11921       if (codep > priv.the_buffer)
11922         {
11923           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11924           if (name != NULL)
11925             (*info->fprintf_func) (info->stream, "%s", name);
11926           else
11927             {
11928               /* Just print the first byte as a .byte instruction.  */
11929               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11930                                      (unsigned int) priv.the_buffer[0]);
11931             }
11932
11933           return 1;
11934         }
11935
11936       return -1;
11937     }
11938
11939   obufp = obuf;
11940   sizeflag = priv.orig_sizeflag;
11941
11942   if (!ckprefix () || rex_used)
11943     {
11944       /* Too many prefixes or unused REX prefixes.  */
11945       for (i = 0;
11946            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11947            i++)
11948         (*info->fprintf_func) (info->stream, "%s%s",
11949                                i == 0 ? "" : " ",
11950                                prefix_name (all_prefixes[i], sizeflag));
11951       return i;
11952     }
11953
11954   insn_codep = codep;
11955
11956   FETCH_DATA (info, codep + 1);
11957   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11958
11959   if (((prefixes & PREFIX_FWAIT)
11960        && ((*codep < 0xd8) || (*codep > 0xdf))))
11961     {
11962       /* Handle prefixes before fwait.  */
11963       for (i = 0; i < fwait_prefix && all_prefixes[i];
11964            i++)
11965         (*info->fprintf_func) (info->stream, "%s ",
11966                                prefix_name (all_prefixes[i], sizeflag));
11967       (*info->fprintf_func) (info->stream, "fwait");
11968       return i + 1;
11969     }
11970
11971   if (*codep == 0x0f)
11972     {
11973       unsigned char threebyte;
11974
11975       codep++;
11976       FETCH_DATA (info, codep + 1);
11977       threebyte = *codep;
11978       dp = &dis386_twobyte[threebyte];
11979       need_modrm = twobyte_has_modrm[*codep];
11980       codep++;
11981     }
11982   else
11983     {
11984       dp = &dis386[*codep];
11985       need_modrm = onebyte_has_modrm[*codep];
11986       codep++;
11987     }
11988
11989   /* Save sizeflag for printing the extra prefixes later before updating
11990      it for mnemonic and operand processing.  The prefix names depend
11991      only on the address mode.  */
11992   orig_sizeflag = sizeflag;
11993   if (prefixes & PREFIX_ADDR)
11994     sizeflag ^= AFLAG;
11995   if ((prefixes & PREFIX_DATA))
11996     sizeflag ^= DFLAG;
11997
11998   end_codep = codep;
11999   if (need_modrm)
12000     {
12001       FETCH_DATA (info, codep + 1);
12002       modrm.mod = (*codep >> 6) & 3;
12003       modrm.reg = (*codep >> 3) & 7;
12004       modrm.rm = *codep & 7;
12005     }
12006
12007   need_vex = 0;
12008   need_vex_reg = 0;
12009   vex_w_done = 0;
12010   memset (&vex, 0, sizeof (vex));
12011
12012   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12013     {
12014       get_sib (info, sizeflag);
12015       dofloat (sizeflag);
12016     }
12017   else
12018     {
12019       dp = get_valid_dis386 (dp, info);
12020       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12021         {
12022           get_sib (info, sizeflag);
12023           for (i = 0; i < MAX_OPERANDS; ++i)
12024             {
12025               obufp = op_out[i];
12026               op_ad = MAX_OPERANDS - 1 - i;
12027               if (dp->op[i].rtn)
12028                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12029               /* For EVEX instruction after the last operand masking
12030                  should be printed.  */
12031               if (i == 0 && vex.evex)
12032                 {
12033                   /* Don't print {%k0}.  */
12034                   if (vex.mask_register_specifier)
12035                     {
12036                       oappend ("{");
12037                       oappend (names_mask[vex.mask_register_specifier]);
12038                       oappend ("}");
12039                     }
12040                   if (vex.zeroing)
12041                     oappend ("{z}");
12042                 }
12043             }
12044         }
12045     }
12046
12047   /* Clear instruction information.  */
12048   if (the_info)
12049     {
12050       the_info->insn_info_valid = 0;
12051       the_info->branch_delay_insns = 0;
12052       the_info->data_size = 0;
12053       the_info->insn_type = dis_noninsn;
12054       the_info->target = 0;
12055       the_info->target2 = 0;
12056     }
12057
12058   /* Reset jump operation indicator.  */
12059   op_is_jump = FALSE;
12060
12061   {
12062     int jump_detection = 0;
12063
12064     /* Extract flags.  */
12065     for (i = 0; i < MAX_OPERANDS; ++i)
12066       {
12067         if ((dp->op[i].rtn == OP_J)
12068             || (dp->op[i].rtn == OP_indirE))
12069           jump_detection |= 1;
12070         else if ((dp->op[i].rtn == BND_Fixup)
12071                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12072           jump_detection |= 2;
12073         else if ((dp->op[i].bytemode == cond_jump_mode)
12074                  || (dp->op[i].bytemode == loop_jcxz_mode))
12075           jump_detection |= 4;
12076       }
12077
12078     /* Determine if this is a jump or branch.  */
12079     if ((jump_detection & 0x3) == 0x3)
12080       {
12081         op_is_jump = TRUE;
12082         if (jump_detection & 0x4)
12083           the_info->insn_type = dis_condbranch;
12084         else
12085           the_info->insn_type =
12086             (dp->name && !strncmp(dp->name, "call", 4))
12087             ? dis_jsr : dis_branch;
12088       }
12089   }
12090
12091   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12092      are all 0s in inverted form.  */
12093   if (need_vex && vex.register_specifier != 0)
12094     {
12095       (*info->fprintf_func) (info->stream, "(bad)");
12096       return end_codep - priv.the_buffer;
12097     }
12098
12099   /* Check if the REX prefix is used.  */
12100   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12101     all_prefixes[last_rex_prefix] = 0;
12102
12103   /* Check if the SEG prefix is used.  */
12104   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12105                    | PREFIX_FS | PREFIX_GS)) != 0
12106       && (used_prefixes & active_seg_prefix) != 0)
12107     all_prefixes[last_seg_prefix] = 0;
12108
12109   /* Check if the ADDR prefix is used.  */
12110   if ((prefixes & PREFIX_ADDR) != 0
12111       && (used_prefixes & PREFIX_ADDR) != 0)
12112     all_prefixes[last_addr_prefix] = 0;
12113
12114   /* Check if the DATA prefix is used.  */
12115   if ((prefixes & PREFIX_DATA) != 0
12116       && (used_prefixes & PREFIX_DATA) != 0
12117       && !need_vex)
12118     all_prefixes[last_data_prefix] = 0;
12119
12120   /* Print the extra prefixes.  */
12121   prefix_length = 0;
12122   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12123     if (all_prefixes[i])
12124       {
12125         const char *name;
12126         name = prefix_name (all_prefixes[i], orig_sizeflag);
12127         if (name == NULL)
12128           abort ();
12129         prefix_length += strlen (name) + 1;
12130         (*info->fprintf_func) (info->stream, "%s ", name);
12131       }
12132
12133   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12134      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12135      used by putop and MMX/SSE operand and may be overriden by the
12136      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12137      separately.  */
12138   if (dp->prefix_requirement == PREFIX_OPCODE
12139       && (((need_vex
12140             ? vex.prefix == REPE_PREFIX_OPCODE
12141               || vex.prefix == REPNE_PREFIX_OPCODE
12142             : (prefixes
12143                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12144            && (used_prefixes
12145                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12146           || (((need_vex
12147                 ? vex.prefix == DATA_PREFIX_OPCODE
12148                 : ((prefixes
12149                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12150                    == PREFIX_DATA))
12151                && (used_prefixes & PREFIX_DATA) == 0))
12152           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12153     {
12154       (*info->fprintf_func) (info->stream, "(bad)");
12155       return end_codep - priv.the_buffer;
12156     }
12157
12158   /* Check maximum code length.  */
12159   if ((codep - start_codep) > MAX_CODE_LENGTH)
12160     {
12161       (*info->fprintf_func) (info->stream, "(bad)");
12162       return MAX_CODE_LENGTH;
12163     }
12164
12165   obufp = mnemonicendp;
12166   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12167     oappend (" ");
12168   oappend (" ");
12169   (*info->fprintf_func) (info->stream, "%s", obuf);
12170
12171   /* The enter and bound instructions are printed with operands in the same
12172      order as the intel book; everything else is printed in reverse order.  */
12173   if (intel_syntax || two_source_ops)
12174     {
12175       bfd_vma riprel;
12176
12177       for (i = 0; i < MAX_OPERANDS; ++i)
12178         op_txt[i] = op_out[i];
12179
12180       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12181           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12182         {
12183           op_txt[2] = op_out[3];
12184           op_txt[3] = op_out[2];
12185         }
12186
12187       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12188         {
12189           op_ad = op_index[i];
12190           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12191           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12192           riprel = op_riprel[i];
12193           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12194           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12195         }
12196     }
12197   else
12198     {
12199       for (i = 0; i < MAX_OPERANDS; ++i)
12200         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12201     }
12202
12203   needcomma = 0;
12204   for (i = 0; i < MAX_OPERANDS; ++i)
12205     if (*op_txt[i])
12206       {
12207         if (needcomma)
12208           (*info->fprintf_func) (info->stream, ",");
12209         if (op_index[i] != -1 && !op_riprel[i])
12210           {
12211             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12212
12213             if (the_info && op_is_jump)
12214               {
12215                 the_info->insn_info_valid = 1;
12216                 the_info->branch_delay_insns = 0;
12217                 the_info->data_size = 0;
12218                 the_info->target = target;
12219                 the_info->target2 = 0;
12220               }
12221             (*info->print_address_func) (target, info);
12222           }
12223         else
12224           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12225         needcomma = 1;
12226       }
12227
12228   for (i = 0; i < MAX_OPERANDS; i++)
12229     if (op_index[i] != -1 && op_riprel[i])
12230       {
12231         (*info->fprintf_func) (info->stream, "        # ");
12232         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12233                                                 + op_address[op_index[i]]), info);
12234         break;
12235       }
12236   return codep - priv.the_buffer;
12237 }
12238
12239 static const char *float_mem[] = {
12240   /* d8 */
12241   "fadd{s|}",
12242   "fmul{s|}",
12243   "fcom{s|}",
12244   "fcomp{s|}",
12245   "fsub{s|}",
12246   "fsubr{s|}",
12247   "fdiv{s|}",
12248   "fdivr{s|}",
12249   /* d9 */
12250   "fld{s|}",
12251   "(bad)",
12252   "fst{s|}",
12253   "fstp{s|}",
12254   "fldenv{C|C}",
12255   "fldcw",
12256   "fNstenv{C|C}",
12257   "fNstcw",
12258   /* da */
12259   "fiadd{l|}",
12260   "fimul{l|}",
12261   "ficom{l|}",
12262   "ficomp{l|}",
12263   "fisub{l|}",
12264   "fisubr{l|}",
12265   "fidiv{l|}",
12266   "fidivr{l|}",
12267   /* db */
12268   "fild{l|}",
12269   "fisttp{l|}",
12270   "fist{l|}",
12271   "fistp{l|}",
12272   "(bad)",
12273   "fld{t|}",
12274   "(bad)",
12275   "fstp{t|}",
12276   /* dc */
12277   "fadd{l|}",
12278   "fmul{l|}",
12279   "fcom{l|}",
12280   "fcomp{l|}",
12281   "fsub{l|}",
12282   "fsubr{l|}",
12283   "fdiv{l|}",
12284   "fdivr{l|}",
12285   /* dd */
12286   "fld{l|}",
12287   "fisttp{ll|}",
12288   "fst{l||}",
12289   "fstp{l|}",
12290   "frstor{C|C}",
12291   "(bad)",
12292   "fNsave{C|C}",
12293   "fNstsw",
12294   /* de */
12295   "fiadd{s|}",
12296   "fimul{s|}",
12297   "ficom{s|}",
12298   "ficomp{s|}",
12299   "fisub{s|}",
12300   "fisubr{s|}",
12301   "fidiv{s|}",
12302   "fidivr{s|}",
12303   /* df */
12304   "fild{s|}",
12305   "fisttp{s|}",
12306   "fist{s|}",
12307   "fistp{s|}",
12308   "fbld",
12309   "fild{ll|}",
12310   "fbstp",
12311   "fistp{ll|}",
12312 };
12313
12314 static const unsigned char float_mem_mode[] = {
12315   /* d8 */
12316   d_mode,
12317   d_mode,
12318   d_mode,
12319   d_mode,
12320   d_mode,
12321   d_mode,
12322   d_mode,
12323   d_mode,
12324   /* d9 */
12325   d_mode,
12326   0,
12327   d_mode,
12328   d_mode,
12329   0,
12330   w_mode,
12331   0,
12332   w_mode,
12333   /* da */
12334   d_mode,
12335   d_mode,
12336   d_mode,
12337   d_mode,
12338   d_mode,
12339   d_mode,
12340   d_mode,
12341   d_mode,
12342   /* db */
12343   d_mode,
12344   d_mode,
12345   d_mode,
12346   d_mode,
12347   0,
12348   t_mode,
12349   0,
12350   t_mode,
12351   /* dc */
12352   q_mode,
12353   q_mode,
12354   q_mode,
12355   q_mode,
12356   q_mode,
12357   q_mode,
12358   q_mode,
12359   q_mode,
12360   /* dd */
12361   q_mode,
12362   q_mode,
12363   q_mode,
12364   q_mode,
12365   0,
12366   0,
12367   0,
12368   w_mode,
12369   /* de */
12370   w_mode,
12371   w_mode,
12372   w_mode,
12373   w_mode,
12374   w_mode,
12375   w_mode,
12376   w_mode,
12377   w_mode,
12378   /* df */
12379   w_mode,
12380   w_mode,
12381   w_mode,
12382   w_mode,
12383   t_mode,
12384   q_mode,
12385   t_mode,
12386   q_mode
12387 };
12388
12389 #define ST { OP_ST, 0 }
12390 #define STi { OP_STi, 0 }
12391
12392 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12393 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12394 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12395 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12396 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12397 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12398 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12399 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12400 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12401
12402 static const struct dis386 float_reg[][8] = {
12403   /* d8 */
12404   {
12405     { "fadd",   { ST, STi }, 0 },
12406     { "fmul",   { ST, STi }, 0 },
12407     { "fcom",   { STi }, 0 },
12408     { "fcomp",  { STi }, 0 },
12409     { "fsub",   { ST, STi }, 0 },
12410     { "fsubr",  { ST, STi }, 0 },
12411     { "fdiv",   { ST, STi }, 0 },
12412     { "fdivr",  { ST, STi }, 0 },
12413   },
12414   /* d9 */
12415   {
12416     { "fld",    { STi }, 0 },
12417     { "fxch",   { STi }, 0 },
12418     { FGRPd9_2 },
12419     { Bad_Opcode },
12420     { FGRPd9_4 },
12421     { FGRPd9_5 },
12422     { FGRPd9_6 },
12423     { FGRPd9_7 },
12424   },
12425   /* da */
12426   {
12427     { "fcmovb", { ST, STi }, 0 },
12428     { "fcmove", { ST, STi }, 0 },
12429     { "fcmovbe",{ ST, STi }, 0 },
12430     { "fcmovu", { ST, STi }, 0 },
12431     { Bad_Opcode },
12432     { FGRPda_5 },
12433     { Bad_Opcode },
12434     { Bad_Opcode },
12435   },
12436   /* db */
12437   {
12438     { "fcmovnb",{ ST, STi }, 0 },
12439     { "fcmovne",{ ST, STi }, 0 },
12440     { "fcmovnbe",{ ST, STi }, 0 },
12441     { "fcmovnu",{ ST, STi }, 0 },
12442     { FGRPdb_4 },
12443     { "fucomi", { ST, STi }, 0 },
12444     { "fcomi",  { ST, STi }, 0 },
12445     { Bad_Opcode },
12446   },
12447   /* dc */
12448   {
12449     { "fadd",   { STi, ST }, 0 },
12450     { "fmul",   { STi, ST }, 0 },
12451     { Bad_Opcode },
12452     { Bad_Opcode },
12453     { "fsub{!M|r}",     { STi, ST }, 0 },
12454     { "fsub{M|}",       { STi, ST }, 0 },
12455     { "fdiv{!M|r}",     { STi, ST }, 0 },
12456     { "fdiv{M|}",       { STi, ST }, 0 },
12457   },
12458   /* dd */
12459   {
12460     { "ffree",  { STi }, 0 },
12461     { Bad_Opcode },
12462     { "fst",    { STi }, 0 },
12463     { "fstp",   { STi }, 0 },
12464     { "fucom",  { STi }, 0 },
12465     { "fucomp", { STi }, 0 },
12466     { Bad_Opcode },
12467     { Bad_Opcode },
12468   },
12469   /* de */
12470   {
12471     { "faddp",  { STi, ST }, 0 },
12472     { "fmulp",  { STi, ST }, 0 },
12473     { Bad_Opcode },
12474     { FGRPde_3 },
12475     { "fsub{!M|r}p",    { STi, ST }, 0 },
12476     { "fsub{M|}p",      { STi, ST }, 0 },
12477     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12478     { "fdiv{M|}p",      { STi, ST }, 0 },
12479   },
12480   /* df */
12481   {
12482     { "ffreep", { STi }, 0 },
12483     { Bad_Opcode },
12484     { Bad_Opcode },
12485     { Bad_Opcode },
12486     { FGRPdf_4 },
12487     { "fucomip", { ST, STi }, 0 },
12488     { "fcomip", { ST, STi }, 0 },
12489     { Bad_Opcode },
12490   },
12491 };
12492
12493 static char *fgrps[][8] = {
12494   /* Bad opcode 0 */
12495   {
12496     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12497   },
12498
12499   /* d9_2  1 */
12500   {
12501     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12502   },
12503
12504   /* d9_4  2 */
12505   {
12506     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12507   },
12508
12509   /* d9_5  3 */
12510   {
12511     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12512   },
12513
12514   /* d9_6  4 */
12515   {
12516     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12517   },
12518
12519   /* d9_7  5 */
12520   {
12521     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12522   },
12523
12524   /* da_5  6 */
12525   {
12526     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12527   },
12528
12529   /* db_4  7 */
12530   {
12531     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12532     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12533   },
12534
12535   /* de_3  8 */
12536   {
12537     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12538   },
12539
12540   /* df_4  9 */
12541   {
12542     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12543   },
12544 };
12545
12546 static void
12547 swap_operand (void)
12548 {
12549   mnemonicendp[0] = '.';
12550   mnemonicendp[1] = 's';
12551   mnemonicendp += 2;
12552 }
12553
12554 static void
12555 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12556                int sizeflag ATTRIBUTE_UNUSED)
12557 {
12558   /* Skip mod/rm byte.  */
12559   MODRM_CHECK;
12560   codep++;
12561 }
12562
12563 static void
12564 dofloat (int sizeflag)
12565 {
12566   const struct dis386 *dp;
12567   unsigned char floatop;
12568
12569   floatop = codep[-1];
12570
12571   if (modrm.mod != 3)
12572     {
12573       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12574
12575       putop (float_mem[fp_indx], sizeflag);
12576       obufp = op_out[0];
12577       op_ad = 2;
12578       OP_E (float_mem_mode[fp_indx], sizeflag);
12579       return;
12580     }
12581   /* Skip mod/rm byte.  */
12582   MODRM_CHECK;
12583   codep++;
12584
12585   dp = &float_reg[floatop - 0xd8][modrm.reg];
12586   if (dp->name == NULL)
12587     {
12588       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12589
12590       /* Instruction fnstsw is only one with strange arg.  */
12591       if (floatop == 0xdf && codep[-1] == 0xe0)
12592         strcpy (op_out[0], names16[0]);
12593     }
12594   else
12595     {
12596       putop (dp->name, sizeflag);
12597
12598       obufp = op_out[0];
12599       op_ad = 2;
12600       if (dp->op[0].rtn)
12601         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12602
12603       obufp = op_out[1];
12604       op_ad = 1;
12605       if (dp->op[1].rtn)
12606         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12607     }
12608 }
12609
12610 /* Like oappend (below), but S is a string starting with '%'.
12611    In Intel syntax, the '%' is elided.  */
12612 static void
12613 oappend_maybe_intel (const char *s)
12614 {
12615   oappend (s + intel_syntax);
12616 }
12617
12618 static void
12619 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12620 {
12621   oappend_maybe_intel ("%st");
12622 }
12623
12624 static void
12625 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12626 {
12627   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12628   oappend_maybe_intel (scratchbuf);
12629 }
12630
12631 /* Capital letters in template are macros.  */
12632 static int
12633 putop (const char *in_template, int sizeflag)
12634 {
12635   const char *p;
12636   int alt = 0;
12637   int cond = 1;
12638   unsigned int l = 0, len = 0;
12639   char last[4];
12640
12641   for (p = in_template; *p; p++)
12642     {
12643       if (len > l)
12644         {
12645           if (l >= sizeof (last) || !ISUPPER (*p))
12646             abort ();
12647           last[l++] = *p;
12648           continue;
12649         }
12650       switch (*p)
12651         {
12652         default:
12653           *obufp++ = *p;
12654           break;
12655         case '%':
12656           len++;
12657           break;
12658         case '!':
12659           cond = 0;
12660           break;
12661         case '{':
12662           if (intel_syntax)
12663             {
12664               while (*++p != '|')
12665                 if (*p == '}' || *p == '\0')
12666                   abort ();
12667               alt = 1;
12668             }
12669           break;
12670         case '|':
12671           while (*++p != '}')
12672             {
12673               if (*p == '\0')
12674                 abort ();
12675             }
12676           break;
12677         case '}':
12678           alt = 0;
12679           break;
12680         case 'A':
12681           if (intel_syntax)
12682             break;
12683           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12684             *obufp++ = 'b';
12685           break;
12686         case 'B':
12687           if (l == 0)
12688             {
12689             case_B:
12690               if (intel_syntax)
12691                 break;
12692               if (sizeflag & SUFFIX_ALWAYS)
12693                 *obufp++ = 'b';
12694             }
12695           else if (l == 1 && last[0] == 'L')
12696             {
12697               if (address_mode == mode_64bit
12698                   && !(prefixes & PREFIX_ADDR))
12699                 {
12700                   *obufp++ = 'a';
12701                   *obufp++ = 'b';
12702                   *obufp++ = 's';
12703                 }
12704
12705               goto case_B;
12706             }
12707           else
12708             abort ();
12709           break;
12710         case 'C':
12711           if (intel_syntax && !alt)
12712             break;
12713           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12714             {
12715               if (sizeflag & DFLAG)
12716                 *obufp++ = intel_syntax ? 'd' : 'l';
12717               else
12718                 *obufp++ = intel_syntax ? 'w' : 's';
12719               used_prefixes |= (prefixes & PREFIX_DATA);
12720             }
12721           break;
12722         case 'D':
12723           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12724             break;
12725           USED_REX (REX_W);
12726           if (modrm.mod == 3)
12727             {
12728               if (rex & REX_W)
12729                 *obufp++ = 'q';
12730               else
12731                 {
12732                   if (sizeflag & DFLAG)
12733                     *obufp++ = intel_syntax ? 'd' : 'l';
12734                   else
12735                     *obufp++ = 'w';
12736                   used_prefixes |= (prefixes & PREFIX_DATA);
12737                 }
12738             }
12739           else
12740             *obufp++ = 'w';
12741           break;
12742         case 'E':               /* For jcxz/jecxz */
12743           if (address_mode == mode_64bit)
12744             {
12745               if (sizeflag & AFLAG)
12746                 *obufp++ = 'r';
12747               else
12748                 *obufp++ = 'e';
12749             }
12750           else
12751             if (sizeflag & AFLAG)
12752               *obufp++ = 'e';
12753           used_prefixes |= (prefixes & PREFIX_ADDR);
12754           break;
12755         case 'F':
12756           if (intel_syntax)
12757             break;
12758           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12759             {
12760               if (sizeflag & AFLAG)
12761                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12762               else
12763                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12764               used_prefixes |= (prefixes & PREFIX_ADDR);
12765             }
12766           break;
12767         case 'G':
12768           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12769             break;
12770           if ((rex & REX_W) || (sizeflag & DFLAG))
12771             *obufp++ = 'l';
12772           else
12773             *obufp++ = 'w';
12774           if (!(rex & REX_W))
12775             used_prefixes |= (prefixes & PREFIX_DATA);
12776           break;
12777         case 'H':
12778           if (intel_syntax)
12779             break;
12780           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12781               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12782             {
12783               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12784               *obufp++ = ',';
12785               *obufp++ = 'p';
12786               if (prefixes & PREFIX_DS)
12787                 *obufp++ = 't';
12788               else
12789                 *obufp++ = 'n';
12790             }
12791           break;
12792         case 'K':
12793           USED_REX (REX_W);
12794           if (rex & REX_W)
12795             *obufp++ = 'q';
12796           else
12797             *obufp++ = 'd';
12798           break;
12799         case 'Z':
12800           if (l != 0)
12801             {
12802               if (l != 1 || last[0] != 'X')
12803                 abort ();
12804               if (!need_vex || !vex.evex)
12805                 abort ();
12806               if (intel_syntax
12807                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12808                 break;
12809               switch (vex.length)
12810                 {
12811                 case 128:
12812                   *obufp++ = 'x';
12813                   break;
12814                 case 256:
12815                   *obufp++ = 'y';
12816                   break;
12817                 case 512:
12818                   *obufp++ = 'z';
12819                   break;
12820                 default:
12821                   abort ();
12822                 }
12823               break;
12824             }
12825           if (intel_syntax)
12826             break;
12827           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12828             {
12829               *obufp++ = 'q';
12830               break;
12831             }
12832           /* Fall through.  */
12833           goto case_L;
12834         case 'L':
12835           if (l != 0)
12836             abort ();
12837         case_L:
12838           if (intel_syntax)
12839             break;
12840           if (sizeflag & SUFFIX_ALWAYS)
12841             *obufp++ = 'l';
12842           break;
12843         case 'M':
12844           if (intel_mnemonic != cond)
12845             *obufp++ = 'r';
12846           break;
12847         case 'N':
12848           if ((prefixes & PREFIX_FWAIT) == 0)
12849             *obufp++ = 'n';
12850           else
12851             used_prefixes |= PREFIX_FWAIT;
12852           break;
12853         case 'O':
12854           USED_REX (REX_W);
12855           if (rex & REX_W)
12856             *obufp++ = 'o';
12857           else if (intel_syntax && (sizeflag & DFLAG))
12858             *obufp++ = 'q';
12859           else
12860             *obufp++ = 'd';
12861           if (!(rex & REX_W))
12862             used_prefixes |= (prefixes & PREFIX_DATA);
12863           break;
12864         case '&':
12865           if (!intel_syntax
12866               && address_mode == mode_64bit
12867               && isa64 == intel64)
12868             {
12869               *obufp++ = 'q';
12870               break;
12871             }
12872           /* Fall through.  */
12873         case 'T':
12874           if (!intel_syntax
12875               && address_mode == mode_64bit
12876               && ((sizeflag & DFLAG) || (rex & REX_W)))
12877             {
12878               *obufp++ = 'q';
12879               break;
12880             }
12881           /* Fall through.  */
12882           goto case_P;
12883         case 'P':
12884           if (l == 0)
12885             {
12886             case_P:
12887               if (intel_syntax)
12888                 {
12889                   if ((rex & REX_W) == 0
12890                       && (prefixes & PREFIX_DATA))
12891                     {
12892                       if ((sizeflag & DFLAG) == 0)
12893                         *obufp++ = 'w';
12894                       used_prefixes |= (prefixes & PREFIX_DATA);
12895                     }
12896                   break;
12897                 }
12898               if ((prefixes & PREFIX_DATA)
12899                   || (rex & REX_W)
12900                   || (sizeflag & SUFFIX_ALWAYS))
12901                 {
12902                   USED_REX (REX_W);
12903                   if (rex & REX_W)
12904                     *obufp++ = 'q';
12905                   else
12906                     {
12907                       if (sizeflag & DFLAG)
12908                         *obufp++ = 'l';
12909                       else
12910                         *obufp++ = 'w';
12911                       used_prefixes |= (prefixes & PREFIX_DATA);
12912                     }
12913                 }
12914             }
12915           else if (l == 1 && last[0] == 'L')
12916             {
12917               if ((prefixes & PREFIX_DATA)
12918                   || (rex & REX_W)
12919                   || (sizeflag & SUFFIX_ALWAYS))
12920                 {
12921                   USED_REX (REX_W);
12922                   if (rex & REX_W)
12923                     *obufp++ = 'q';
12924                   else
12925                     {
12926                       if (sizeflag & DFLAG)
12927                         *obufp++ = intel_syntax ? 'd' : 'l';
12928                       else
12929                         *obufp++ = 'w';
12930                       used_prefixes |= (prefixes & PREFIX_DATA);
12931                     }
12932                 }
12933             }
12934           else
12935             abort ();
12936           break;
12937         case 'U':
12938           if (intel_syntax)
12939             break;
12940           if (address_mode == mode_64bit
12941               && ((sizeflag & DFLAG) || (rex & REX_W)))
12942             {
12943               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12944                 *obufp++ = 'q';
12945               break;
12946             }
12947           /* Fall through.  */
12948           goto case_Q;
12949         case 'Q':
12950           if (l == 0)
12951             {
12952             case_Q:
12953               if (intel_syntax && !alt)
12954                 break;
12955               USED_REX (REX_W);
12956               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12957                 {
12958                   if (rex & REX_W)
12959                     *obufp++ = 'q';
12960                   else
12961                     {
12962                       if (sizeflag & DFLAG)
12963                         *obufp++ = intel_syntax ? 'd' : 'l';
12964                       else
12965                         *obufp++ = 'w';
12966                       used_prefixes |= (prefixes & PREFIX_DATA);
12967                     }
12968                 }
12969             }
12970           else if (l == 1 && last[0] == 'L')
12971             {
12972               if ((intel_syntax && need_modrm)
12973                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12974                 break;
12975               if ((rex & REX_W))
12976                 {
12977                   USED_REX (REX_W);
12978                   *obufp++ = 'q';
12979                 }
12980               else if((address_mode == mode_64bit && need_modrm)
12981                       || (sizeflag & SUFFIX_ALWAYS))
12982                 *obufp++ = intel_syntax? 'd' : 'l';
12983             }
12984           else
12985             abort ();
12986           break;
12987         case 'R':
12988           USED_REX (REX_W);
12989           if (rex & REX_W)
12990             *obufp++ = 'q';
12991           else if (sizeflag & DFLAG)
12992             {
12993               if (intel_syntax)
12994                   *obufp++ = 'd';
12995               else
12996                   *obufp++ = 'l';
12997             }
12998           else
12999             *obufp++ = 'w';
13000           if (intel_syntax && !p[1]
13001               && ((rex & REX_W) || (sizeflag & DFLAG)))
13002             *obufp++ = 'e';
13003           if (!(rex & REX_W))
13004             used_prefixes |= (prefixes & PREFIX_DATA);
13005           break;
13006         case 'V':
13007           if (l == 0)
13008             {
13009               if (intel_syntax)
13010                 break;
13011               if (address_mode == mode_64bit
13012                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13013                 {
13014                   if (sizeflag & SUFFIX_ALWAYS)
13015                     *obufp++ = 'q';
13016                   break;
13017                 }
13018             }
13019           else if (l == 1 && last[0] == 'L')
13020             {
13021               if (rex & REX_W)
13022                 {
13023                   *obufp++ = 'a';
13024                   *obufp++ = 'b';
13025                   *obufp++ = 's';
13026                 }
13027             }
13028           else
13029             abort ();
13030           /* Fall through.  */
13031           goto case_S;
13032         case 'S':
13033           if (l == 0)
13034             {
13035             case_S:
13036               if (intel_syntax)
13037                 break;
13038               if (sizeflag & SUFFIX_ALWAYS)
13039                 {
13040                   if (rex & REX_W)
13041                     *obufp++ = 'q';
13042                   else
13043                     {
13044                       if (sizeflag & DFLAG)
13045                         *obufp++ = 'l';
13046                       else
13047                         *obufp++ = 'w';
13048                       used_prefixes |= (prefixes & PREFIX_DATA);
13049                     }
13050                 }
13051             }
13052           else if (l == 1 && last[0] == 'L')
13053             {
13054               if (address_mode == mode_64bit
13055                   && !(prefixes & PREFIX_ADDR))
13056                 {
13057                   *obufp++ = 'a';
13058                   *obufp++ = 'b';
13059                   *obufp++ = 's';
13060                 }
13061
13062               goto case_S;
13063             }
13064           else
13065             abort ();
13066           break;
13067         case 'X':
13068           if (l != 0)
13069             abort ();
13070           if (need_vex
13071               ? vex.prefix == DATA_PREFIX_OPCODE
13072               : prefixes & PREFIX_DATA)
13073             {
13074               *obufp++ = 'd';
13075               used_prefixes |= PREFIX_DATA;
13076             }
13077           else
13078             *obufp++ = 's';
13079           break;
13080         case 'Y':
13081           if (l == 1 && last[0] == 'X')
13082             {
13083               if (!need_vex)
13084                 abort ();
13085               if (intel_syntax
13086                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13087                 break;
13088               switch (vex.length)
13089                 {
13090                 case 128:
13091                   *obufp++ = 'x';
13092                   break;
13093                 case 256:
13094                   *obufp++ = 'y';
13095                   break;
13096                 case 512:
13097                   if (!vex.evex)
13098                 default:
13099                     abort ();
13100                 }
13101             }
13102           else
13103             abort ();
13104           break;
13105         case 'W':
13106           if (l == 0)
13107             {
13108               /* operand size flag for cwtl, cbtw */
13109               USED_REX (REX_W);
13110               if (rex & REX_W)
13111                 {
13112                   if (intel_syntax)
13113                     *obufp++ = 'd';
13114                   else
13115                     *obufp++ = 'l';
13116                 }
13117               else if (sizeflag & DFLAG)
13118                 *obufp++ = 'w';
13119               else
13120                 *obufp++ = 'b';
13121               if (!(rex & REX_W))
13122                 used_prefixes |= (prefixes & PREFIX_DATA);
13123             }
13124           else if (l == 1)
13125             {
13126               if (!need_vex)
13127                 abort ();
13128               if (last[0] == 'X')
13129                 *obufp++ = vex.w ? 'd': 's';
13130               else if (last[0] == 'L')
13131                 *obufp++ = vex.w ? 'q': 'd';
13132               else
13133                 abort ();
13134             }
13135           else
13136             abort ();
13137           break;
13138         case '^':
13139           if (intel_syntax)
13140             break;
13141           if (isa64 == intel64 && (rex & REX_W))
13142             {
13143               USED_REX (REX_W);
13144               *obufp++ = 'q';
13145               break;
13146             }
13147           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13148             {
13149               if (sizeflag & DFLAG)
13150                 *obufp++ = 'l';
13151               else
13152                 *obufp++ = 'w';
13153               used_prefixes |= (prefixes & PREFIX_DATA);
13154             }
13155           break;
13156         case '@':
13157           if (intel_syntax)
13158             break;
13159           if (address_mode == mode_64bit
13160               && (isa64 == intel64
13161                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13162               *obufp++ = 'q';
13163           else if ((prefixes & PREFIX_DATA))
13164             {
13165               if (!(sizeflag & DFLAG))
13166                 *obufp++ = 'w';
13167               used_prefixes |= (prefixes & PREFIX_DATA);
13168             }
13169           break;
13170         }
13171
13172       if (len == l)
13173         len = l = 0;
13174     }
13175   *obufp = 0;
13176   mnemonicendp = obufp;
13177   return 0;
13178 }
13179
13180 static void
13181 oappend (const char *s)
13182 {
13183   obufp = stpcpy (obufp, s);
13184 }
13185
13186 static void
13187 append_seg (void)
13188 {
13189   /* Only print the active segment register.  */
13190   if (!active_seg_prefix)
13191     return;
13192
13193   used_prefixes |= active_seg_prefix;
13194   switch (active_seg_prefix)
13195     {
13196     case PREFIX_CS:
13197       oappend_maybe_intel ("%cs:");
13198       break;
13199     case PREFIX_DS:
13200       oappend_maybe_intel ("%ds:");
13201       break;
13202     case PREFIX_SS:
13203       oappend_maybe_intel ("%ss:");
13204       break;
13205     case PREFIX_ES:
13206       oappend_maybe_intel ("%es:");
13207       break;
13208     case PREFIX_FS:
13209       oappend_maybe_intel ("%fs:");
13210       break;
13211     case PREFIX_GS:
13212       oappend_maybe_intel ("%gs:");
13213       break;
13214     default:
13215       break;
13216     }
13217 }
13218
13219 static void
13220 OP_indirE (int bytemode, int sizeflag)
13221 {
13222   if (!intel_syntax)
13223     oappend ("*");
13224   OP_E (bytemode, sizeflag);
13225 }
13226
13227 static void
13228 print_operand_value (char *buf, int hex, bfd_vma disp)
13229 {
13230   if (address_mode == mode_64bit)
13231     {
13232       if (hex)
13233         {
13234           char tmp[30];
13235           int i;
13236           buf[0] = '0';
13237           buf[1] = 'x';
13238           sprintf_vma (tmp, disp);
13239           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13240           strcpy (buf + 2, tmp + i);
13241         }
13242       else
13243         {
13244           bfd_signed_vma v = disp;
13245           char tmp[30];
13246           int i;
13247           if (v < 0)
13248             {
13249               *(buf++) = '-';
13250               v = -disp;
13251               /* Check for possible overflow on 0x8000000000000000.  */
13252               if (v < 0)
13253                 {
13254                   strcpy (buf, "9223372036854775808");
13255                   return;
13256                 }
13257             }
13258           if (!v)
13259             {
13260               strcpy (buf, "0");
13261               return;
13262             }
13263
13264           i = 0;
13265           tmp[29] = 0;
13266           while (v)
13267             {
13268               tmp[28 - i] = (v % 10) + '0';
13269               v /= 10;
13270               i++;
13271             }
13272           strcpy (buf, tmp + 29 - i);
13273         }
13274     }
13275   else
13276     {
13277       if (hex)
13278         sprintf (buf, "0x%x", (unsigned int) disp);
13279       else
13280         sprintf (buf, "%d", (int) disp);
13281     }
13282 }
13283
13284 /* Put DISP in BUF as signed hex number.  */
13285
13286 static void
13287 print_displacement (char *buf, bfd_vma disp)
13288 {
13289   bfd_signed_vma val = disp;
13290   char tmp[30];
13291   int i, j = 0;
13292
13293   if (val < 0)
13294     {
13295       buf[j++] = '-';
13296       val = -disp;
13297
13298       /* Check for possible overflow.  */
13299       if (val < 0)
13300         {
13301           switch (address_mode)
13302             {
13303             case mode_64bit:
13304               strcpy (buf + j, "0x8000000000000000");
13305               break;
13306             case mode_32bit:
13307               strcpy (buf + j, "0x80000000");
13308               break;
13309             case mode_16bit:
13310               strcpy (buf + j, "0x8000");
13311               break;
13312             }
13313           return;
13314         }
13315     }
13316
13317   buf[j++] = '0';
13318   buf[j++] = 'x';
13319
13320   sprintf_vma (tmp, (bfd_vma) val);
13321   for (i = 0; tmp[i] == '0'; i++)
13322     continue;
13323   if (tmp[i] == '\0')
13324     i--;
13325   strcpy (buf + j, tmp + i);
13326 }
13327
13328 static void
13329 intel_operand_size (int bytemode, int sizeflag)
13330 {
13331   if (vex.evex
13332       && vex.b
13333       && (bytemode == x_mode
13334           || bytemode == evex_half_bcst_xmmq_mode))
13335     {
13336       if (vex.w)
13337         oappend ("QWORD PTR ");
13338       else
13339         oappend ("DWORD PTR ");
13340       return;
13341     }
13342   switch (bytemode)
13343     {
13344     case b_mode:
13345     case b_swap_mode:
13346     case dqb_mode:
13347     case db_mode:
13348       oappend ("BYTE PTR ");
13349       break;
13350     case w_mode:
13351     case dw_mode:
13352     case dqw_mode:
13353       oappend ("WORD PTR ");
13354       break;
13355     case indir_v_mode:
13356       if (address_mode == mode_64bit && isa64 == intel64)
13357         {
13358           oappend ("QWORD PTR ");
13359           break;
13360         }
13361       /* Fall through.  */
13362     case stack_v_mode:
13363       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13364         {
13365           oappend ("QWORD PTR ");
13366           break;
13367         }
13368       /* Fall through.  */
13369     case v_mode:
13370     case v_swap_mode:
13371     case dq_mode:
13372       USED_REX (REX_W);
13373       if (rex & REX_W)
13374         oappend ("QWORD PTR ");
13375       else
13376         {
13377           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13378             oappend ("DWORD PTR ");
13379           else
13380             oappend ("WORD PTR ");
13381           used_prefixes |= (prefixes & PREFIX_DATA);
13382         }
13383       break;
13384     case z_mode:
13385       if ((rex & REX_W) || (sizeflag & DFLAG))
13386         *obufp++ = 'D';
13387       oappend ("WORD PTR ");
13388       if (!(rex & REX_W))
13389         used_prefixes |= (prefixes & PREFIX_DATA);
13390       break;
13391     case a_mode:
13392       if (sizeflag & DFLAG)
13393         oappend ("QWORD PTR ");
13394       else
13395         oappend ("DWORD PTR ");
13396       used_prefixes |= (prefixes & PREFIX_DATA);
13397       break;
13398     case movsxd_mode:
13399       if (!(sizeflag & DFLAG) && isa64 == intel64)
13400         oappend ("WORD PTR ");
13401       else
13402         oappend ("DWORD PTR ");
13403       used_prefixes |= (prefixes & PREFIX_DATA);
13404       break;
13405     case d_mode:
13406     case d_scalar_swap_mode:
13407     case d_swap_mode:
13408     case dqd_mode:
13409       oappend ("DWORD PTR ");
13410       break;
13411     case q_mode:
13412     case q_scalar_swap_mode:
13413     case q_swap_mode:
13414       oappend ("QWORD PTR ");
13415       break;
13416     case m_mode:
13417       if (address_mode == mode_64bit)
13418         oappend ("QWORD PTR ");
13419       else
13420         oappend ("DWORD PTR ");
13421       break;
13422     case f_mode:
13423       if (sizeflag & DFLAG)
13424         oappend ("FWORD PTR ");
13425       else
13426         oappend ("DWORD PTR ");
13427       used_prefixes |= (prefixes & PREFIX_DATA);
13428       break;
13429     case t_mode:
13430       oappend ("TBYTE PTR ");
13431       break;
13432     case x_mode:
13433     case x_swap_mode:
13434     case evex_x_gscat_mode:
13435     case evex_x_nobcst_mode:
13436     case b_scalar_mode:
13437     case w_scalar_mode:
13438       if (need_vex)
13439         {
13440           switch (vex.length)
13441             {
13442             case 128:
13443               oappend ("XMMWORD PTR ");
13444               break;
13445             case 256:
13446               oappend ("YMMWORD PTR ");
13447               break;
13448             case 512:
13449               oappend ("ZMMWORD PTR ");
13450               break;
13451             default:
13452               abort ();
13453             }
13454         }
13455       else
13456         oappend ("XMMWORD PTR ");
13457       break;
13458     case xmm_mode:
13459       oappend ("XMMWORD PTR ");
13460       break;
13461     case ymm_mode:
13462       oappend ("YMMWORD PTR ");
13463       break;
13464     case xmmq_mode:
13465     case evex_half_bcst_xmmq_mode:
13466       if (!need_vex)
13467         abort ();
13468
13469       switch (vex.length)
13470         {
13471         case 128:
13472           oappend ("QWORD PTR ");
13473           break;
13474         case 256:
13475           oappend ("XMMWORD PTR ");
13476           break;
13477         case 512:
13478           oappend ("YMMWORD PTR ");
13479           break;
13480         default:
13481           abort ();
13482         }
13483       break;
13484     case xmm_mb_mode:
13485       if (!need_vex)
13486         abort ();
13487
13488       switch (vex.length)
13489         {
13490         case 128:
13491         case 256:
13492         case 512:
13493           oappend ("BYTE PTR ");
13494           break;
13495         default:
13496           abort ();
13497         }
13498       break;
13499     case xmm_mw_mode:
13500       if (!need_vex)
13501         abort ();
13502
13503       switch (vex.length)
13504         {
13505         case 128:
13506         case 256:
13507         case 512:
13508           oappend ("WORD PTR ");
13509           break;
13510         default:
13511           abort ();
13512         }
13513       break;
13514     case xmm_md_mode:
13515       if (!need_vex)
13516         abort ();
13517
13518       switch (vex.length)
13519         {
13520         case 128:
13521         case 256:
13522         case 512:
13523           oappend ("DWORD PTR ");
13524           break;
13525         default:
13526           abort ();
13527         }
13528       break;
13529     case xmm_mq_mode:
13530       if (!need_vex)
13531         abort ();
13532
13533       switch (vex.length)
13534         {
13535         case 128:
13536         case 256:
13537         case 512:
13538           oappend ("QWORD PTR ");
13539           break;
13540         default:
13541           abort ();
13542         }
13543       break;
13544     case xmmdw_mode:
13545       if (!need_vex)
13546         abort ();
13547
13548       switch (vex.length)
13549         {
13550         case 128:
13551           oappend ("WORD PTR ");
13552           break;
13553         case 256:
13554           oappend ("DWORD PTR ");
13555           break;
13556         case 512:
13557           oappend ("QWORD PTR ");
13558           break;
13559         default:
13560           abort ();
13561         }
13562       break;
13563     case xmmqd_mode:
13564       if (!need_vex)
13565         abort ();
13566
13567       switch (vex.length)
13568         {
13569         case 128:
13570           oappend ("DWORD PTR ");
13571           break;
13572         case 256:
13573           oappend ("QWORD PTR ");
13574           break;
13575         case 512:
13576           oappend ("XMMWORD PTR ");
13577           break;
13578         default:
13579           abort ();
13580         }
13581       break;
13582     case ymmq_mode:
13583       if (!need_vex)
13584         abort ();
13585
13586       switch (vex.length)
13587         {
13588         case 128:
13589           oappend ("QWORD PTR ");
13590           break;
13591         case 256:
13592           oappend ("YMMWORD PTR ");
13593           break;
13594         case 512:
13595           oappend ("ZMMWORD PTR ");
13596           break;
13597         default:
13598           abort ();
13599         }
13600       break;
13601     case ymmxmm_mode:
13602       if (!need_vex)
13603         abort ();
13604
13605       switch (vex.length)
13606         {
13607         case 128:
13608         case 256:
13609           oappend ("XMMWORD PTR ");
13610           break;
13611         default:
13612           abort ();
13613         }
13614       break;
13615     case o_mode:
13616       oappend ("OWORD PTR ");
13617       break;
13618     case vex_scalar_w_dq_mode:
13619       if (!need_vex)
13620         abort ();
13621
13622       if (vex.w)
13623         oappend ("QWORD PTR ");
13624       else
13625         oappend ("DWORD PTR ");
13626       break;
13627     case vex_vsib_d_w_dq_mode:
13628     case vex_vsib_q_w_dq_mode:
13629       if (!need_vex)
13630         abort ();
13631
13632       if (!vex.evex)
13633         {
13634           if (vex.w)
13635             oappend ("QWORD PTR ");
13636           else
13637             oappend ("DWORD PTR ");
13638         }
13639       else
13640         {
13641           switch (vex.length)
13642             {
13643             case 128:
13644               oappend ("XMMWORD PTR ");
13645               break;
13646             case 256:
13647               oappend ("YMMWORD PTR ");
13648               break;
13649             case 512:
13650               oappend ("ZMMWORD PTR ");
13651               break;
13652             default:
13653               abort ();
13654             }
13655         }
13656       break;
13657     case vex_vsib_q_w_d_mode:
13658     case vex_vsib_d_w_d_mode:
13659       if (!need_vex || !vex.evex)
13660         abort ();
13661
13662       switch (vex.length)
13663         {
13664         case 128:
13665           oappend ("QWORD PTR ");
13666           break;
13667         case 256:
13668           oappend ("XMMWORD PTR ");
13669           break;
13670         case 512:
13671           oappend ("YMMWORD PTR ");
13672           break;
13673         default:
13674           abort ();
13675         }
13676
13677       break;
13678     case mask_bd_mode:
13679       if (!need_vex || vex.length != 128)
13680         abort ();
13681       if (vex.w)
13682         oappend ("DWORD PTR ");
13683       else
13684         oappend ("BYTE PTR ");
13685       break;
13686     case mask_mode:
13687       if (!need_vex)
13688         abort ();
13689       if (vex.w)
13690         oappend ("QWORD PTR ");
13691       else
13692         oappend ("WORD PTR ");
13693       break;
13694     case v_bnd_mode:
13695     case v_bndmk_mode:
13696     default:
13697       break;
13698     }
13699 }
13700
13701 static void
13702 OP_E_register (int bytemode, int sizeflag)
13703 {
13704   int reg = modrm.rm;
13705   const char **names;
13706
13707   USED_REX (REX_B);
13708   if ((rex & REX_B))
13709     reg += 8;
13710
13711   if ((sizeflag & SUFFIX_ALWAYS)
13712       && (bytemode == b_swap_mode
13713           || bytemode == bnd_swap_mode
13714           || bytemode == v_swap_mode))
13715     swap_operand ();
13716
13717   switch (bytemode)
13718     {
13719     case b_mode:
13720     case b_swap_mode:
13721       USED_REX (0);
13722       if (rex)
13723         names = names8rex;
13724       else
13725         names = names8;
13726       break;
13727     case w_mode:
13728       names = names16;
13729       break;
13730     case d_mode:
13731     case dw_mode:
13732     case db_mode:
13733       names = names32;
13734       break;
13735     case q_mode:
13736       names = names64;
13737       break;
13738     case m_mode:
13739     case v_bnd_mode:
13740       names = address_mode == mode_64bit ? names64 : names32;
13741       break;
13742     case bnd_mode:
13743     case bnd_swap_mode:
13744       if (reg > 0x3)
13745         {
13746           oappend ("(bad)");
13747           return;
13748         }
13749       names = names_bnd;
13750       break;
13751     case indir_v_mode:
13752       if (address_mode == mode_64bit && isa64 == intel64)
13753         {
13754           names = names64;
13755           break;
13756         }
13757       /* Fall through.  */
13758     case stack_v_mode:
13759       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13760         {
13761           names = names64;
13762           break;
13763         }
13764       bytemode = v_mode;
13765       /* Fall through.  */
13766     case v_mode:
13767     case v_swap_mode:
13768     case dq_mode:
13769     case dqb_mode:
13770     case dqd_mode:
13771     case dqw_mode:
13772       USED_REX (REX_W);
13773       if (rex & REX_W)
13774         names = names64;
13775       else
13776         {
13777           if ((sizeflag & DFLAG)
13778               || (bytemode != v_mode
13779                   && bytemode != v_swap_mode))
13780             names = names32;
13781           else
13782             names = names16;
13783           used_prefixes |= (prefixes & PREFIX_DATA);
13784         }
13785       break;
13786     case movsxd_mode:
13787       if (!(sizeflag & DFLAG) && isa64 == intel64)
13788         names = names16;
13789       else
13790         names = names32;
13791       used_prefixes |= (prefixes & PREFIX_DATA);
13792       break;
13793     case va_mode:
13794       names = (address_mode == mode_64bit
13795                ? names64 : names32);
13796       if (!(prefixes & PREFIX_ADDR))
13797         names = (address_mode == mode_16bit
13798                      ? names16 : names);
13799       else
13800         {
13801           /* Remove "addr16/addr32".  */
13802           all_prefixes[last_addr_prefix] = 0;
13803           names = (address_mode != mode_32bit
13804                        ? names32 : names16);
13805           used_prefixes |= PREFIX_ADDR;
13806         }
13807       break;
13808     case mask_bd_mode:
13809     case mask_mode:
13810       if (reg > 0x7)
13811         {
13812           oappend ("(bad)");
13813           return;
13814         }
13815       names = names_mask;
13816       break;
13817     case 0:
13818       return;
13819     default:
13820       oappend (INTERNAL_DISASSEMBLER_ERROR);
13821       return;
13822     }
13823   oappend (names[reg]);
13824 }
13825
13826 static void
13827 OP_E_memory (int bytemode, int sizeflag)
13828 {
13829   bfd_vma disp = 0;
13830   int add = (rex & REX_B) ? 8 : 0;
13831   int riprel = 0;
13832   int shift;
13833
13834   if (vex.evex)
13835     {
13836       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13837       if (vex.b
13838           && bytemode != x_mode
13839           && bytemode != xmmq_mode
13840           && bytemode != evex_half_bcst_xmmq_mode)
13841         {
13842           BadOp ();
13843           return;
13844         }
13845       switch (bytemode)
13846         {
13847         case dqw_mode:
13848         case dw_mode:
13849           shift = 1;
13850           break;
13851         case dqb_mode:
13852         case db_mode:
13853           shift = 0;
13854           break;
13855         case dq_mode:
13856           if (address_mode != mode_64bit)
13857             {
13858               shift = 2;
13859               break;
13860             }
13861             /* fall through */
13862         case vex_scalar_w_dq_mode:
13863         case vex_vsib_d_w_dq_mode:
13864         case vex_vsib_d_w_d_mode:
13865         case vex_vsib_q_w_dq_mode:
13866         case vex_vsib_q_w_d_mode:
13867         case evex_x_gscat_mode:
13868           shift = vex.w ? 3 : 2;
13869           break;
13870         case x_mode:
13871         case evex_half_bcst_xmmq_mode:
13872         case xmmq_mode:
13873           if (vex.b)
13874             {
13875               shift = vex.w ? 3 : 2;
13876               break;
13877             }
13878           /* Fall through.  */
13879         case xmmqd_mode:
13880         case xmmdw_mode:
13881         case ymmq_mode:
13882         case evex_x_nobcst_mode:
13883         case x_swap_mode:
13884           switch (vex.length)
13885             {
13886             case 128:
13887               shift = 4;
13888               break;
13889             case 256:
13890               shift = 5;
13891               break;
13892             case 512:
13893               shift = 6;
13894               break;
13895             default:
13896               abort ();
13897             }
13898           break;
13899         case ymm_mode:
13900           shift = 5;
13901           break;
13902         case xmm_mode:
13903           shift = 4;
13904           break;
13905         case xmm_mq_mode:
13906         case q_mode:
13907         case q_swap_mode:
13908         case q_scalar_swap_mode:
13909           shift = 3;
13910           break;
13911         case dqd_mode:
13912         case xmm_md_mode:
13913         case d_mode:
13914         case d_swap_mode:
13915         case d_scalar_swap_mode:
13916           shift = 2;
13917           break;
13918         case w_scalar_mode:
13919         case xmm_mw_mode:
13920           shift = 1;
13921           break;
13922         case b_scalar_mode:
13923         case xmm_mb_mode:
13924           shift = 0;
13925           break;
13926         default:
13927           abort ();
13928         }
13929       /* Make necessary corrections to shift for modes that need it.
13930          For these modes we currently have shift 4, 5 or 6 depending on
13931          vex.length (it corresponds to xmmword, ymmword or zmmword
13932          operand).  We might want to make it 3, 4 or 5 (e.g. for
13933          xmmq_mode).  In case of broadcast enabled the corrections
13934          aren't needed, as element size is always 32 or 64 bits.  */
13935       if (!vex.b
13936           && (bytemode == xmmq_mode
13937               || bytemode == evex_half_bcst_xmmq_mode))
13938         shift -= 1;
13939       else if (bytemode == xmmqd_mode)
13940         shift -= 2;
13941       else if (bytemode == xmmdw_mode)
13942         shift -= 3;
13943       else if (bytemode == ymmq_mode && vex.length == 128)
13944         shift -= 1;
13945     }
13946   else
13947     shift = 0;
13948
13949   USED_REX (REX_B);
13950   if (intel_syntax)
13951     intel_operand_size (bytemode, sizeflag);
13952   append_seg ();
13953
13954   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13955     {
13956       /* 32/64 bit address mode */
13957       int havedisp;
13958       int havesib;
13959       int havebase;
13960       int haveindex;
13961       int needindex;
13962       int needaddr32;
13963       int base, rbase;
13964       int vindex = 0;
13965       int scale = 0;
13966       int addr32flag = !((sizeflag & AFLAG)
13967                          || bytemode == v_bnd_mode
13968                          || bytemode == v_bndmk_mode
13969                          || bytemode == bnd_mode
13970                          || bytemode == bnd_swap_mode);
13971       const char **indexes64 = names64;
13972       const char **indexes32 = names32;
13973
13974       havesib = 0;
13975       havebase = 1;
13976       haveindex = 0;
13977       base = modrm.rm;
13978
13979       if (base == 4)
13980         {
13981           havesib = 1;
13982           vindex = sib.index;
13983           USED_REX (REX_X);
13984           if (rex & REX_X)
13985             vindex += 8;
13986           switch (bytemode)
13987             {
13988             case vex_vsib_d_w_dq_mode:
13989             case vex_vsib_d_w_d_mode:
13990             case vex_vsib_q_w_dq_mode:
13991             case vex_vsib_q_w_d_mode:
13992               if (!need_vex)
13993                 abort ();
13994               if (vex.evex)
13995                 {
13996                   if (!vex.v)
13997                     vindex += 16;
13998                 }
13999
14000               haveindex = 1;
14001               switch (vex.length)
14002                 {
14003                 case 128:
14004                   indexes64 = indexes32 = names_xmm;
14005                   break;
14006                 case 256:
14007                   if (!vex.w
14008                       || bytemode == vex_vsib_q_w_dq_mode
14009                       || bytemode == vex_vsib_q_w_d_mode)
14010                     indexes64 = indexes32 = names_ymm;
14011                   else
14012                     indexes64 = indexes32 = names_xmm;
14013                   break;
14014                 case 512:
14015                   if (!vex.w
14016                       || bytemode == vex_vsib_q_w_dq_mode
14017                       || bytemode == vex_vsib_q_w_d_mode)
14018                     indexes64 = indexes32 = names_zmm;
14019                   else
14020                     indexes64 = indexes32 = names_ymm;
14021                   break;
14022                 default:
14023                   abort ();
14024                 }
14025               break;
14026             default:
14027               haveindex = vindex != 4;
14028               break;
14029             }
14030           scale = sib.scale;
14031           base = sib.base;
14032           codep++;
14033         }
14034       rbase = base + add;
14035
14036       switch (modrm.mod)
14037         {
14038         case 0:
14039           if (base == 5)
14040             {
14041               havebase = 0;
14042               if (address_mode == mode_64bit && !havesib)
14043                 riprel = 1;
14044               disp = get32s ();
14045               if (riprel && bytemode == v_bndmk_mode)
14046                 {
14047                   oappend ("(bad)");
14048                   return;
14049                 }
14050             }
14051           break;
14052         case 1:
14053           FETCH_DATA (the_info, codep + 1);
14054           disp = *codep++;
14055           if ((disp & 0x80) != 0)
14056             disp -= 0x100;
14057           if (vex.evex && shift > 0)
14058             disp <<= shift;
14059           break;
14060         case 2:
14061           disp = get32s ();
14062           break;
14063         }
14064
14065       needindex = 0;
14066       needaddr32 = 0;
14067       if (havesib
14068           && !havebase
14069           && !haveindex
14070           && address_mode != mode_16bit)
14071         {
14072           if (address_mode == mode_64bit)
14073             {
14074               /* Display eiz instead of addr32.  */
14075               needindex = addr32flag;
14076               needaddr32 = 1;
14077             }
14078           else
14079             {
14080               /* In 32-bit mode, we need index register to tell [offset]
14081                  from [eiz*1 + offset].  */
14082               needindex = 1;
14083             }
14084         }
14085
14086       havedisp = (havebase
14087                   || needindex
14088                   || (havesib && (haveindex || scale != 0)));
14089
14090       if (!intel_syntax)
14091         if (modrm.mod != 0 || base == 5)
14092           {
14093             if (havedisp || riprel)
14094               print_displacement (scratchbuf, disp);
14095             else
14096               print_operand_value (scratchbuf, 1, disp);
14097             oappend (scratchbuf);
14098             if (riprel)
14099               {
14100                 set_op (disp, 1);
14101                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14102               }
14103           }
14104
14105       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14106           && (address_mode != mode_64bit
14107               || ((bytemode != v_bnd_mode)
14108                   && (bytemode != v_bndmk_mode)
14109                   && (bytemode != bnd_mode)
14110                   && (bytemode != bnd_swap_mode))))
14111         used_prefixes |= PREFIX_ADDR;
14112
14113       if (havedisp || (intel_syntax && riprel))
14114         {
14115           *obufp++ = open_char;
14116           if (intel_syntax && riprel)
14117             {
14118               set_op (disp, 1);
14119               oappend (!addr32flag ? "rip" : "eip");
14120             }
14121           *obufp = '\0';
14122           if (havebase)
14123             oappend (address_mode == mode_64bit && !addr32flag
14124                      ? names64[rbase] : names32[rbase]);
14125           if (havesib)
14126             {
14127               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14128                  print index to tell base + index from base.  */
14129               if (scale != 0
14130                   || needindex
14131                   || haveindex
14132                   || (havebase && base != ESP_REG_NUM))
14133                 {
14134                   if (!intel_syntax || havebase)
14135                     {
14136                       *obufp++ = separator_char;
14137                       *obufp = '\0';
14138                     }
14139                   if (haveindex)
14140                     oappend (address_mode == mode_64bit && !addr32flag
14141                              ? indexes64[vindex] : indexes32[vindex]);
14142                   else
14143                     oappend (address_mode == mode_64bit && !addr32flag
14144                              ? index64 : index32);
14145
14146                   *obufp++ = scale_char;
14147                   *obufp = '\0';
14148                   sprintf (scratchbuf, "%d", 1 << scale);
14149                   oappend (scratchbuf);
14150                 }
14151             }
14152           if (intel_syntax
14153               && (disp || modrm.mod != 0 || base == 5))
14154             {
14155               if (!havedisp || (bfd_signed_vma) disp >= 0)
14156                 {
14157                   *obufp++ = '+';
14158                   *obufp = '\0';
14159                 }
14160               else if (modrm.mod != 1 && disp != -disp)
14161                 {
14162                   *obufp++ = '-';
14163                   *obufp = '\0';
14164                   disp = - (bfd_signed_vma) disp;
14165                 }
14166
14167               if (havedisp)
14168                 print_displacement (scratchbuf, disp);
14169               else
14170                 print_operand_value (scratchbuf, 1, disp);
14171               oappend (scratchbuf);
14172             }
14173
14174           *obufp++ = close_char;
14175           *obufp = '\0';
14176         }
14177       else if (intel_syntax)
14178         {
14179           if (modrm.mod != 0 || base == 5)
14180             {
14181               if (!active_seg_prefix)
14182                 {
14183                   oappend (names_seg[ds_reg - es_reg]);
14184                   oappend (":");
14185                 }
14186               print_operand_value (scratchbuf, 1, disp);
14187               oappend (scratchbuf);
14188             }
14189         }
14190     }
14191   else if (bytemode == v_bnd_mode
14192            || bytemode == v_bndmk_mode
14193            || bytemode == bnd_mode
14194            || bytemode == bnd_swap_mode)
14195     {
14196       oappend ("(bad)");
14197       return;
14198     }
14199   else
14200     {
14201       /* 16 bit address mode */
14202       used_prefixes |= prefixes & PREFIX_ADDR;
14203       switch (modrm.mod)
14204         {
14205         case 0:
14206           if (modrm.rm == 6)
14207             {
14208               disp = get16 ();
14209               if ((disp & 0x8000) != 0)
14210                 disp -= 0x10000;
14211             }
14212           break;
14213         case 1:
14214           FETCH_DATA (the_info, codep + 1);
14215           disp = *codep++;
14216           if ((disp & 0x80) != 0)
14217             disp -= 0x100;
14218           if (vex.evex && shift > 0)
14219             disp <<= shift;
14220           break;
14221         case 2:
14222           disp = get16 ();
14223           if ((disp & 0x8000) != 0)
14224             disp -= 0x10000;
14225           break;
14226         }
14227
14228       if (!intel_syntax)
14229         if (modrm.mod != 0 || modrm.rm == 6)
14230           {
14231             print_displacement (scratchbuf, disp);
14232             oappend (scratchbuf);
14233           }
14234
14235       if (modrm.mod != 0 || modrm.rm != 6)
14236         {
14237           *obufp++ = open_char;
14238           *obufp = '\0';
14239           oappend (index16[modrm.rm]);
14240           if (intel_syntax
14241               && (disp || modrm.mod != 0 || modrm.rm == 6))
14242             {
14243               if ((bfd_signed_vma) disp >= 0)
14244                 {
14245                   *obufp++ = '+';
14246                   *obufp = '\0';
14247                 }
14248               else if (modrm.mod != 1)
14249                 {
14250                   *obufp++ = '-';
14251                   *obufp = '\0';
14252                   disp = - (bfd_signed_vma) disp;
14253                 }
14254
14255               print_displacement (scratchbuf, disp);
14256               oappend (scratchbuf);
14257             }
14258
14259           *obufp++ = close_char;
14260           *obufp = '\0';
14261         }
14262       else if (intel_syntax)
14263         {
14264           if (!active_seg_prefix)
14265             {
14266               oappend (names_seg[ds_reg - es_reg]);
14267               oappend (":");
14268             }
14269           print_operand_value (scratchbuf, 1, disp & 0xffff);
14270           oappend (scratchbuf);
14271         }
14272     }
14273   if (vex.evex && vex.b
14274       && (bytemode == x_mode
14275           || bytemode == xmmq_mode
14276           || bytemode == evex_half_bcst_xmmq_mode))
14277     {
14278       if (vex.w
14279           || bytemode == xmmq_mode
14280           || bytemode == evex_half_bcst_xmmq_mode)
14281         {
14282           switch (vex.length)
14283             {
14284             case 128:
14285               oappend ("{1to2}");
14286               break;
14287             case 256:
14288               oappend ("{1to4}");
14289               break;
14290             case 512:
14291               oappend ("{1to8}");
14292               break;
14293             default:
14294               abort ();
14295             }
14296         }
14297       else
14298         {
14299           switch (vex.length)
14300             {
14301             case 128:
14302               oappend ("{1to4}");
14303               break;
14304             case 256:
14305               oappend ("{1to8}");
14306               break;
14307             case 512:
14308               oappend ("{1to16}");
14309               break;
14310             default:
14311               abort ();
14312             }
14313         }
14314     }
14315 }
14316
14317 static void
14318 OP_E (int bytemode, int sizeflag)
14319 {
14320   /* Skip mod/rm byte.  */
14321   MODRM_CHECK;
14322   codep++;
14323
14324   if (modrm.mod == 3)
14325     OP_E_register (bytemode, sizeflag);
14326   else
14327     OP_E_memory (bytemode, sizeflag);
14328 }
14329
14330 static void
14331 OP_G (int bytemode, int sizeflag)
14332 {
14333   int add = 0;
14334   const char **names;
14335   USED_REX (REX_R);
14336   if (rex & REX_R)
14337     add += 8;
14338   switch (bytemode)
14339     {
14340     case b_mode:
14341       USED_REX (0);
14342       if (rex)
14343         oappend (names8rex[modrm.reg + add]);
14344       else
14345         oappend (names8[modrm.reg + add]);
14346       break;
14347     case w_mode:
14348       oappend (names16[modrm.reg + add]);
14349       break;
14350     case d_mode:
14351     case db_mode:
14352     case dw_mode:
14353       oappend (names32[modrm.reg + add]);
14354       break;
14355     case q_mode:
14356       oappend (names64[modrm.reg + add]);
14357       break;
14358     case bnd_mode:
14359       if (modrm.reg > 0x3)
14360         {
14361           oappend ("(bad)");
14362           return;
14363         }
14364       oappend (names_bnd[modrm.reg]);
14365       break;
14366     case v_mode:
14367     case dq_mode:
14368     case dqb_mode:
14369     case dqd_mode:
14370     case dqw_mode:
14371     case movsxd_mode:
14372       USED_REX (REX_W);
14373       if (rex & REX_W)
14374         oappend (names64[modrm.reg + add]);
14375       else
14376         {
14377           if ((sizeflag & DFLAG)
14378               || (bytemode != v_mode && bytemode != movsxd_mode))
14379             oappend (names32[modrm.reg + add]);
14380           else
14381             oappend (names16[modrm.reg + add]);
14382           used_prefixes |= (prefixes & PREFIX_DATA);
14383         }
14384       break;
14385     case va_mode:
14386       names = (address_mode == mode_64bit
14387                ? names64 : names32);
14388       if (!(prefixes & PREFIX_ADDR))
14389         {
14390           if (address_mode == mode_16bit)
14391             names = names16;
14392         }
14393       else
14394         {
14395           /* Remove "addr16/addr32".  */
14396           all_prefixes[last_addr_prefix] = 0;
14397           names = (address_mode != mode_32bit
14398                        ? names32 : names16);
14399           used_prefixes |= PREFIX_ADDR;
14400         }
14401       oappend (names[modrm.reg + add]);
14402       break;
14403     case m_mode:
14404       if (address_mode == mode_64bit)
14405         oappend (names64[modrm.reg + add]);
14406       else
14407         oappend (names32[modrm.reg + add]);
14408       break;
14409     case mask_bd_mode:
14410     case mask_mode:
14411       if ((modrm.reg + add) > 0x7)
14412         {
14413           oappend ("(bad)");
14414           return;
14415         }
14416       oappend (names_mask[modrm.reg + add]);
14417       break;
14418     default:
14419       oappend (INTERNAL_DISASSEMBLER_ERROR);
14420       break;
14421     }
14422 }
14423
14424 static bfd_vma
14425 get64 (void)
14426 {
14427   bfd_vma x;
14428 #ifdef BFD64
14429   unsigned int a;
14430   unsigned int b;
14431
14432   FETCH_DATA (the_info, codep + 8);
14433   a = *codep++ & 0xff;
14434   a |= (*codep++ & 0xff) << 8;
14435   a |= (*codep++ & 0xff) << 16;
14436   a |= (*codep++ & 0xffu) << 24;
14437   b = *codep++ & 0xff;
14438   b |= (*codep++ & 0xff) << 8;
14439   b |= (*codep++ & 0xff) << 16;
14440   b |= (*codep++ & 0xffu) << 24;
14441   x = a + ((bfd_vma) b << 32);
14442 #else
14443   abort ();
14444   x = 0;
14445 #endif
14446   return x;
14447 }
14448
14449 static bfd_signed_vma
14450 get32 (void)
14451 {
14452   bfd_signed_vma x = 0;
14453
14454   FETCH_DATA (the_info, codep + 4);
14455   x = *codep++ & (bfd_signed_vma) 0xff;
14456   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14457   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14458   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14459   return x;
14460 }
14461
14462 static bfd_signed_vma
14463 get32s (void)
14464 {
14465   bfd_signed_vma x = 0;
14466
14467   FETCH_DATA (the_info, codep + 4);
14468   x = *codep++ & (bfd_signed_vma) 0xff;
14469   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14470   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14471   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14472
14473   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14474
14475   return x;
14476 }
14477
14478 static int
14479 get16 (void)
14480 {
14481   int x = 0;
14482
14483   FETCH_DATA (the_info, codep + 2);
14484   x = *codep++ & 0xff;
14485   x |= (*codep++ & 0xff) << 8;
14486   return x;
14487 }
14488
14489 static void
14490 set_op (bfd_vma op, int riprel)
14491 {
14492   op_index[op_ad] = op_ad;
14493   if (address_mode == mode_64bit)
14494     {
14495       op_address[op_ad] = op;
14496       op_riprel[op_ad] = riprel;
14497     }
14498   else
14499     {
14500       /* Mask to get a 32-bit address.  */
14501       op_address[op_ad] = op & 0xffffffff;
14502       op_riprel[op_ad] = riprel & 0xffffffff;
14503     }
14504 }
14505
14506 static void
14507 OP_REG (int code, int sizeflag)
14508 {
14509   const char *s;
14510   int add;
14511
14512   switch (code)
14513     {
14514     case es_reg: case ss_reg: case cs_reg:
14515     case ds_reg: case fs_reg: case gs_reg:
14516       oappend (names_seg[code - es_reg]);
14517       return;
14518     }
14519
14520   USED_REX (REX_B);
14521   if (rex & REX_B)
14522     add = 8;
14523   else
14524     add = 0;
14525
14526   switch (code)
14527     {
14528     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14529     case sp_reg: case bp_reg: case si_reg: case di_reg:
14530       s = names16[code - ax_reg + add];
14531       break;
14532     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14533     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14534       USED_REX (0);
14535       if (rex)
14536         s = names8rex[code - al_reg + add];
14537       else
14538         s = names8[code - al_reg];
14539       break;
14540     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14541     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14542       if (address_mode == mode_64bit
14543           && ((sizeflag & DFLAG) || (rex & REX_W)))
14544         {
14545           s = names64[code - rAX_reg + add];
14546           break;
14547         }
14548       code += eAX_reg - rAX_reg;
14549       /* Fall through.  */
14550     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14551     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14552       USED_REX (REX_W);
14553       if (rex & REX_W)
14554         s = names64[code - eAX_reg + add];
14555       else
14556         {
14557           if (sizeflag & DFLAG)
14558             s = names32[code - eAX_reg + add];
14559           else
14560             s = names16[code - eAX_reg + add];
14561           used_prefixes |= (prefixes & PREFIX_DATA);
14562         }
14563       break;
14564     default:
14565       s = INTERNAL_DISASSEMBLER_ERROR;
14566       break;
14567     }
14568   oappend (s);
14569 }
14570
14571 static void
14572 OP_IMREG (int code, int sizeflag)
14573 {
14574   const char *s;
14575
14576   switch (code)
14577     {
14578     case indir_dx_reg:
14579       if (intel_syntax)
14580         s = "dx";
14581       else
14582         s = "(%dx)";
14583       break;
14584     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14585     case sp_reg: case bp_reg: case si_reg: case di_reg:
14586       s = names16[code - ax_reg];
14587       break;
14588     case es_reg: case ss_reg: case cs_reg:
14589     case ds_reg: case fs_reg: case gs_reg:
14590       s = names_seg[code - es_reg];
14591       break;
14592     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14593     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14594       USED_REX (0);
14595       if (rex)
14596         s = names8rex[code - al_reg];
14597       else
14598         s = names8[code - al_reg];
14599       break;
14600     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14601     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14602       USED_REX (REX_W);
14603       if (rex & REX_W)
14604         s = names64[code - eAX_reg];
14605       else
14606         {
14607           if (sizeflag & DFLAG)
14608             s = names32[code - eAX_reg];
14609           else
14610             s = names16[code - eAX_reg];
14611           used_prefixes |= (prefixes & PREFIX_DATA);
14612         }
14613       break;
14614     case z_mode_ax_reg:
14615       if ((rex & REX_W) || (sizeflag & DFLAG))
14616         s = *names32;
14617       else
14618         s = *names16;
14619       if (!(rex & REX_W))
14620         used_prefixes |= (prefixes & PREFIX_DATA);
14621       break;
14622     default:
14623       s = INTERNAL_DISASSEMBLER_ERROR;
14624       break;
14625     }
14626   oappend (s);
14627 }
14628
14629 static void
14630 OP_I (int bytemode, int sizeflag)
14631 {
14632   bfd_signed_vma op;
14633   bfd_signed_vma mask = -1;
14634
14635   switch (bytemode)
14636     {
14637     case b_mode:
14638       FETCH_DATA (the_info, codep + 1);
14639       op = *codep++;
14640       mask = 0xff;
14641       break;
14642     case v_mode:
14643       USED_REX (REX_W);
14644       if (rex & REX_W)
14645         op = get32s ();
14646       else
14647         {
14648           if (sizeflag & DFLAG)
14649             {
14650               op = get32 ();
14651               mask = 0xffffffff;
14652             }
14653           else
14654             {
14655               op = get16 ();
14656               mask = 0xfffff;
14657             }
14658           used_prefixes |= (prefixes & PREFIX_DATA);
14659         }
14660       break;
14661     case d_mode:
14662       mask = 0xffffffff;
14663       op = get32 ();
14664       break;
14665     case w_mode:
14666       mask = 0xfffff;
14667       op = get16 ();
14668       break;
14669     case const_1_mode:
14670       if (intel_syntax)
14671         oappend ("1");
14672       return;
14673     default:
14674       oappend (INTERNAL_DISASSEMBLER_ERROR);
14675       return;
14676     }
14677
14678   op &= mask;
14679   scratchbuf[0] = '$';
14680   print_operand_value (scratchbuf + 1, 1, op);
14681   oappend_maybe_intel (scratchbuf);
14682   scratchbuf[0] = '\0';
14683 }
14684
14685 static void
14686 OP_I64 (int bytemode, int sizeflag)
14687 {
14688   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14689     {
14690       OP_I (bytemode, sizeflag);
14691       return;
14692     }
14693
14694   USED_REX (REX_W);
14695
14696   scratchbuf[0] = '$';
14697   print_operand_value (scratchbuf + 1, 1, get64 ());
14698   oappend_maybe_intel (scratchbuf);
14699   scratchbuf[0] = '\0';
14700 }
14701
14702 static void
14703 OP_sI (int bytemode, int sizeflag)
14704 {
14705   bfd_signed_vma op;
14706
14707   switch (bytemode)
14708     {
14709     case b_mode:
14710     case b_T_mode:
14711       FETCH_DATA (the_info, codep + 1);
14712       op = *codep++;
14713       if ((op & 0x80) != 0)
14714         op -= 0x100;
14715       if (bytemode == b_T_mode)
14716         {
14717           if (address_mode != mode_64bit
14718               || !((sizeflag & DFLAG) || (rex & REX_W)))
14719             {
14720               /* The operand-size prefix is overridden by a REX prefix.  */
14721               if ((sizeflag & DFLAG) || (rex & REX_W))
14722                 op &= 0xffffffff;
14723               else
14724                 op &= 0xffff;
14725           }
14726         }
14727       else
14728         {
14729           if (!(rex & REX_W))
14730             {
14731               if (sizeflag & DFLAG)
14732                 op &= 0xffffffff;
14733               else
14734                 op &= 0xffff;
14735             }
14736         }
14737       break;
14738     case v_mode:
14739       /* The operand-size prefix is overridden by a REX prefix.  */
14740       if ((sizeflag & DFLAG) || (rex & REX_W))
14741         op = get32s ();
14742       else
14743         op = get16 ();
14744       break;
14745     default:
14746       oappend (INTERNAL_DISASSEMBLER_ERROR);
14747       return;
14748     }
14749
14750   scratchbuf[0] = '$';
14751   print_operand_value (scratchbuf + 1, 1, op);
14752   oappend_maybe_intel (scratchbuf);
14753 }
14754
14755 static void
14756 OP_J (int bytemode, int sizeflag)
14757 {
14758   bfd_vma disp;
14759   bfd_vma mask = -1;
14760   bfd_vma segment = 0;
14761
14762   switch (bytemode)
14763     {
14764     case b_mode:
14765       FETCH_DATA (the_info, codep + 1);
14766       disp = *codep++;
14767       if ((disp & 0x80) != 0)
14768         disp -= 0x100;
14769       break;
14770     case v_mode:
14771       if (isa64 != intel64)
14772     case dqw_mode:
14773         USED_REX (REX_W);
14774       if ((sizeflag & DFLAG)
14775           || (address_mode == mode_64bit
14776               && ((isa64 == intel64 && bytemode != dqw_mode)
14777                   || (rex & REX_W))))
14778         disp = get32s ();
14779       else
14780         {
14781           disp = get16 ();
14782           if ((disp & 0x8000) != 0)
14783             disp -= 0x10000;
14784           /* In 16bit mode, address is wrapped around at 64k within
14785              the same segment.  Otherwise, a data16 prefix on a jump
14786              instruction means that the pc is masked to 16 bits after
14787              the displacement is added!  */
14788           mask = 0xffff;
14789           if ((prefixes & PREFIX_DATA) == 0)
14790             segment = ((start_pc + (codep - start_codep))
14791                        & ~((bfd_vma) 0xffff));
14792         }
14793       if (address_mode != mode_64bit
14794           || (isa64 != intel64 && !(rex & REX_W)))
14795         used_prefixes |= (prefixes & PREFIX_DATA);
14796       break;
14797     default:
14798       oappend (INTERNAL_DISASSEMBLER_ERROR);
14799       return;
14800     }
14801   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14802   set_op (disp, 0);
14803   print_operand_value (scratchbuf, 1, disp);
14804   oappend (scratchbuf);
14805 }
14806
14807 static void
14808 OP_SEG (int bytemode, int sizeflag)
14809 {
14810   if (bytemode == w_mode)
14811     oappend (names_seg[modrm.reg]);
14812   else
14813     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14814 }
14815
14816 static void
14817 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14818 {
14819   int seg, offset;
14820
14821   if (sizeflag & DFLAG)
14822     {
14823       offset = get32 ();
14824       seg = get16 ();
14825     }
14826   else
14827     {
14828       offset = get16 ();
14829       seg = get16 ();
14830     }
14831   used_prefixes |= (prefixes & PREFIX_DATA);
14832   if (intel_syntax)
14833     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14834   else
14835     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14836   oappend (scratchbuf);
14837 }
14838
14839 static void
14840 OP_OFF (int bytemode, int sizeflag)
14841 {
14842   bfd_vma off;
14843
14844   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14845     intel_operand_size (bytemode, sizeflag);
14846   append_seg ();
14847
14848   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14849     off = get32 ();
14850   else
14851     off = get16 ();
14852
14853   if (intel_syntax)
14854     {
14855       if (!active_seg_prefix)
14856         {
14857           oappend (names_seg[ds_reg - es_reg]);
14858           oappend (":");
14859         }
14860     }
14861   print_operand_value (scratchbuf, 1, off);
14862   oappend (scratchbuf);
14863 }
14864
14865 static void
14866 OP_OFF64 (int bytemode, int sizeflag)
14867 {
14868   bfd_vma off;
14869
14870   if (address_mode != mode_64bit
14871       || (prefixes & PREFIX_ADDR))
14872     {
14873       OP_OFF (bytemode, sizeflag);
14874       return;
14875     }
14876
14877   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14878     intel_operand_size (bytemode, sizeflag);
14879   append_seg ();
14880
14881   off = get64 ();
14882
14883   if (intel_syntax)
14884     {
14885       if (!active_seg_prefix)
14886         {
14887           oappend (names_seg[ds_reg - es_reg]);
14888           oappend (":");
14889         }
14890     }
14891   print_operand_value (scratchbuf, 1, off);
14892   oappend (scratchbuf);
14893 }
14894
14895 static void
14896 ptr_reg (int code, int sizeflag)
14897 {
14898   const char *s;
14899
14900   *obufp++ = open_char;
14901   used_prefixes |= (prefixes & PREFIX_ADDR);
14902   if (address_mode == mode_64bit)
14903     {
14904       if (!(sizeflag & AFLAG))
14905         s = names32[code - eAX_reg];
14906       else
14907         s = names64[code - eAX_reg];
14908     }
14909   else if (sizeflag & AFLAG)
14910     s = names32[code - eAX_reg];
14911   else
14912     s = names16[code - eAX_reg];
14913   oappend (s);
14914   *obufp++ = close_char;
14915   *obufp = 0;
14916 }
14917
14918 static void
14919 OP_ESreg (int code, int sizeflag)
14920 {
14921   if (intel_syntax)
14922     {
14923       switch (codep[-1])
14924         {
14925         case 0x6d:      /* insw/insl */
14926           intel_operand_size (z_mode, sizeflag);
14927           break;
14928         case 0xa5:      /* movsw/movsl/movsq */
14929         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14930         case 0xab:      /* stosw/stosl */
14931         case 0xaf:      /* scasw/scasl */
14932           intel_operand_size (v_mode, sizeflag);
14933           break;
14934         default:
14935           intel_operand_size (b_mode, sizeflag);
14936         }
14937     }
14938   oappend_maybe_intel ("%es:");
14939   ptr_reg (code, sizeflag);
14940 }
14941
14942 static void
14943 OP_DSreg (int code, int sizeflag)
14944 {
14945   if (intel_syntax)
14946     {
14947       switch (codep[-1])
14948         {
14949         case 0x6f:      /* outsw/outsl */
14950           intel_operand_size (z_mode, sizeflag);
14951           break;
14952         case 0xa5:      /* movsw/movsl/movsq */
14953         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14954         case 0xad:      /* lodsw/lodsl/lodsq */
14955           intel_operand_size (v_mode, sizeflag);
14956           break;
14957         default:
14958           intel_operand_size (b_mode, sizeflag);
14959         }
14960     }
14961   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14962      default segment register DS is printed.  */
14963   if (!active_seg_prefix)
14964     active_seg_prefix = PREFIX_DS;
14965   append_seg ();
14966   ptr_reg (code, sizeflag);
14967 }
14968
14969 static void
14970 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14971 {
14972   int add;
14973   if (rex & REX_R)
14974     {
14975       USED_REX (REX_R);
14976       add = 8;
14977     }
14978   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
14979     {
14980       all_prefixes[last_lock_prefix] = 0;
14981       used_prefixes |= PREFIX_LOCK;
14982       add = 8;
14983     }
14984   else
14985     add = 0;
14986   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
14987   oappend_maybe_intel (scratchbuf);
14988 }
14989
14990 static void
14991 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14992 {
14993   int add;
14994   USED_REX (REX_R);
14995   if (rex & REX_R)
14996     add = 8;
14997   else
14998     add = 0;
14999   if (intel_syntax)
15000     sprintf (scratchbuf, "db%d", modrm.reg + add);
15001   else
15002     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15003   oappend (scratchbuf);
15004 }
15005
15006 static void
15007 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15008 {
15009   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15010   oappend_maybe_intel (scratchbuf);
15011 }
15012
15013 static void
15014 OP_R (int bytemode, int sizeflag)
15015 {
15016   /* Skip mod/rm byte.  */
15017   MODRM_CHECK;
15018   codep++;
15019   OP_E_register (bytemode, sizeflag);
15020 }
15021
15022 static void
15023 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15024 {
15025   int reg = modrm.reg;
15026   const char **names;
15027
15028   used_prefixes |= (prefixes & PREFIX_DATA);
15029   if (prefixes & PREFIX_DATA)
15030     {
15031       names = names_xmm;
15032       USED_REX (REX_R);
15033       if (rex & REX_R)
15034         reg += 8;
15035     }
15036   else
15037     names = names_mm;
15038   oappend (names[reg]);
15039 }
15040
15041 static void
15042 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15043 {
15044   int reg = modrm.reg;
15045   const char **names;
15046
15047   USED_REX (REX_R);
15048   if (rex & REX_R)
15049     reg += 8;
15050   if (vex.evex)
15051     {
15052       if (!vex.r)
15053         reg += 16;
15054     }
15055
15056   if (need_vex
15057       && bytemode != xmm_mode
15058       && bytemode != xmmq_mode
15059       && bytemode != evex_half_bcst_xmmq_mode
15060       && bytemode != ymm_mode
15061       && bytemode != scalar_mode)
15062     {
15063       switch (vex.length)
15064         {
15065         case 128:
15066           names = names_xmm;
15067           break;
15068         case 256:
15069           if (vex.w
15070               || (bytemode != vex_vsib_q_w_dq_mode
15071                   && bytemode != vex_vsib_q_w_d_mode))
15072             names = names_ymm;
15073           else
15074             names = names_xmm;
15075           break;
15076         case 512:
15077           names = names_zmm;
15078           break;
15079         default:
15080           abort ();
15081         }
15082     }
15083   else if (bytemode == xmmq_mode
15084            || bytemode == evex_half_bcst_xmmq_mode)
15085     {
15086       switch (vex.length)
15087         {
15088         case 128:
15089         case 256:
15090           names = names_xmm;
15091           break;
15092         case 512:
15093           names = names_ymm;
15094           break;
15095         default:
15096           abort ();
15097         }
15098     }
15099   else if (bytemode == ymm_mode)
15100     names = names_ymm;
15101   else
15102     names = names_xmm;
15103   oappend (names[reg]);
15104 }
15105
15106 static void
15107 OP_EM (int bytemode, int sizeflag)
15108 {
15109   int reg;
15110   const char **names;
15111
15112   if (modrm.mod != 3)
15113     {
15114       if (intel_syntax
15115           && (bytemode == v_mode || bytemode == v_swap_mode))
15116         {
15117           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15118           used_prefixes |= (prefixes & PREFIX_DATA);
15119         }
15120       OP_E (bytemode, sizeflag);
15121       return;
15122     }
15123
15124   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15125     swap_operand ();
15126
15127   /* Skip mod/rm byte.  */
15128   MODRM_CHECK;
15129   codep++;
15130   used_prefixes |= (prefixes & PREFIX_DATA);
15131   reg = modrm.rm;
15132   if (prefixes & PREFIX_DATA)
15133     {
15134       names = names_xmm;
15135       USED_REX (REX_B);
15136       if (rex & REX_B)
15137         reg += 8;
15138     }
15139   else
15140     names = names_mm;
15141   oappend (names[reg]);
15142 }
15143
15144 /* cvt* are the only instructions in sse2 which have
15145    both SSE and MMX operands and also have 0x66 prefix
15146    in their opcode. 0x66 was originally used to differentiate
15147    between SSE and MMX instruction(operands). So we have to handle the
15148    cvt* separately using OP_EMC and OP_MXC */
15149 static void
15150 OP_EMC (int bytemode, int sizeflag)
15151 {
15152   if (modrm.mod != 3)
15153     {
15154       if (intel_syntax && bytemode == v_mode)
15155         {
15156           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15157           used_prefixes |= (prefixes & PREFIX_DATA);
15158         }
15159       OP_E (bytemode, sizeflag);
15160       return;
15161     }
15162
15163   /* Skip mod/rm byte.  */
15164   MODRM_CHECK;
15165   codep++;
15166   used_prefixes |= (prefixes & PREFIX_DATA);
15167   oappend (names_mm[modrm.rm]);
15168 }
15169
15170 static void
15171 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15172 {
15173   used_prefixes |= (prefixes & PREFIX_DATA);
15174   oappend (names_mm[modrm.reg]);
15175 }
15176
15177 static void
15178 OP_EX (int bytemode, int sizeflag)
15179 {
15180   int reg;
15181   const char **names;
15182
15183   /* Skip mod/rm byte.  */
15184   MODRM_CHECK;
15185   codep++;
15186
15187   if (modrm.mod != 3)
15188     {
15189       OP_E_memory (bytemode, sizeflag);
15190       return;
15191     }
15192
15193   reg = modrm.rm;
15194   USED_REX (REX_B);
15195   if (rex & REX_B)
15196     reg += 8;
15197   if (vex.evex)
15198     {
15199       USED_REX (REX_X);
15200       if ((rex & REX_X))
15201         reg += 16;
15202     }
15203
15204   if ((sizeflag & SUFFIX_ALWAYS)
15205       && (bytemode == x_swap_mode
15206           || bytemode == d_swap_mode
15207           || bytemode == d_scalar_swap_mode
15208           || bytemode == q_swap_mode
15209           || bytemode == q_scalar_swap_mode))
15210     swap_operand ();
15211
15212   if (need_vex
15213       && bytemode != xmm_mode
15214       && bytemode != xmmdw_mode
15215       && bytemode != xmmqd_mode
15216       && bytemode != xmm_mb_mode
15217       && bytemode != xmm_mw_mode
15218       && bytemode != xmm_md_mode
15219       && bytemode != xmm_mq_mode
15220       && bytemode != xmmq_mode
15221       && bytemode != evex_half_bcst_xmmq_mode
15222       && bytemode != ymm_mode
15223       && bytemode != d_scalar_swap_mode
15224       && bytemode != q_scalar_swap_mode
15225       && bytemode != vex_scalar_w_dq_mode)
15226     {
15227       switch (vex.length)
15228         {
15229         case 128:
15230           names = names_xmm;
15231           break;
15232         case 256:
15233           names = names_ymm;
15234           break;
15235         case 512:
15236           names = names_zmm;
15237           break;
15238         default:
15239           abort ();
15240         }
15241     }
15242   else if (bytemode == xmmq_mode
15243            || bytemode == evex_half_bcst_xmmq_mode)
15244     {
15245       switch (vex.length)
15246         {
15247         case 128:
15248         case 256:
15249           names = names_xmm;
15250           break;
15251         case 512:
15252           names = names_ymm;
15253           break;
15254         default:
15255           abort ();
15256         }
15257     }
15258   else if (bytemode == ymm_mode)
15259     names = names_ymm;
15260   else
15261     names = names_xmm;
15262   oappend (names[reg]);
15263 }
15264
15265 static void
15266 OP_MS (int bytemode, int sizeflag)
15267 {
15268   if (modrm.mod == 3)
15269     OP_EM (bytemode, sizeflag);
15270   else
15271     BadOp ();
15272 }
15273
15274 static void
15275 OP_XS (int bytemode, int sizeflag)
15276 {
15277   if (modrm.mod == 3)
15278     OP_EX (bytemode, sizeflag);
15279   else
15280     BadOp ();
15281 }
15282
15283 static void
15284 OP_M (int bytemode, int sizeflag)
15285 {
15286   if (modrm.mod == 3)
15287     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15288     BadOp ();
15289   else
15290     OP_E (bytemode, sizeflag);
15291 }
15292
15293 static void
15294 OP_0f07 (int bytemode, int sizeflag)
15295 {
15296   if (modrm.mod != 3 || modrm.rm != 0)
15297     BadOp ();
15298   else
15299     OP_E (bytemode, sizeflag);
15300 }
15301
15302 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15303    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15304
15305 static void
15306 NOP_Fixup1 (int bytemode, int sizeflag)
15307 {
15308   if ((prefixes & PREFIX_DATA) != 0
15309       || (rex != 0
15310           && rex != 0x48
15311           && address_mode == mode_64bit))
15312     OP_REG (bytemode, sizeflag);
15313   else
15314     strcpy (obuf, "nop");
15315 }
15316
15317 static void
15318 NOP_Fixup2 (int bytemode, int sizeflag)
15319 {
15320   if ((prefixes & PREFIX_DATA) != 0
15321       || (rex != 0
15322           && rex != 0x48
15323           && address_mode == mode_64bit))
15324     OP_IMREG (bytemode, sizeflag);
15325 }
15326
15327 static const char *const Suffix3DNow[] = {
15328 /* 00 */        NULL,           NULL,           NULL,           NULL,
15329 /* 04 */        NULL,           NULL,           NULL,           NULL,
15330 /* 08 */        NULL,           NULL,           NULL,           NULL,
15331 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15332 /* 10 */        NULL,           NULL,           NULL,           NULL,
15333 /* 14 */        NULL,           NULL,           NULL,           NULL,
15334 /* 18 */        NULL,           NULL,           NULL,           NULL,
15335 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15336 /* 20 */        NULL,           NULL,           NULL,           NULL,
15337 /* 24 */        NULL,           NULL,           NULL,           NULL,
15338 /* 28 */        NULL,           NULL,           NULL,           NULL,
15339 /* 2C */        NULL,           NULL,           NULL,           NULL,
15340 /* 30 */        NULL,           NULL,           NULL,           NULL,
15341 /* 34 */        NULL,           NULL,           NULL,           NULL,
15342 /* 38 */        NULL,           NULL,           NULL,           NULL,
15343 /* 3C */        NULL,           NULL,           NULL,           NULL,
15344 /* 40 */        NULL,           NULL,           NULL,           NULL,
15345 /* 44 */        NULL,           NULL,           NULL,           NULL,
15346 /* 48 */        NULL,           NULL,           NULL,           NULL,
15347 /* 4C */        NULL,           NULL,           NULL,           NULL,
15348 /* 50 */        NULL,           NULL,           NULL,           NULL,
15349 /* 54 */        NULL,           NULL,           NULL,           NULL,
15350 /* 58 */        NULL,           NULL,           NULL,           NULL,
15351 /* 5C */        NULL,           NULL,           NULL,           NULL,
15352 /* 60 */        NULL,           NULL,           NULL,           NULL,
15353 /* 64 */        NULL,           NULL,           NULL,           NULL,
15354 /* 68 */        NULL,           NULL,           NULL,           NULL,
15355 /* 6C */        NULL,           NULL,           NULL,           NULL,
15356 /* 70 */        NULL,           NULL,           NULL,           NULL,
15357 /* 74 */        NULL,           NULL,           NULL,           NULL,
15358 /* 78 */        NULL,           NULL,           NULL,           NULL,
15359 /* 7C */        NULL,           NULL,           NULL,           NULL,
15360 /* 80 */        NULL,           NULL,           NULL,           NULL,
15361 /* 84 */        NULL,           NULL,           NULL,           NULL,
15362 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15363 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15364 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15365 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15366 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15367 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15368 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15369 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15370 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15371 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15372 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15373 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15374 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15375 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15376 /* C0 */        NULL,           NULL,           NULL,           NULL,
15377 /* C4 */        NULL,           NULL,           NULL,           NULL,
15378 /* C8 */        NULL,           NULL,           NULL,           NULL,
15379 /* CC */        NULL,           NULL,           NULL,           NULL,
15380 /* D0 */        NULL,           NULL,           NULL,           NULL,
15381 /* D4 */        NULL,           NULL,           NULL,           NULL,
15382 /* D8 */        NULL,           NULL,           NULL,           NULL,
15383 /* DC */        NULL,           NULL,           NULL,           NULL,
15384 /* E0 */        NULL,           NULL,           NULL,           NULL,
15385 /* E4 */        NULL,           NULL,           NULL,           NULL,
15386 /* E8 */        NULL,           NULL,           NULL,           NULL,
15387 /* EC */        NULL,           NULL,           NULL,           NULL,
15388 /* F0 */        NULL,           NULL,           NULL,           NULL,
15389 /* F4 */        NULL,           NULL,           NULL,           NULL,
15390 /* F8 */        NULL,           NULL,           NULL,           NULL,
15391 /* FC */        NULL,           NULL,           NULL,           NULL,
15392 };
15393
15394 static void
15395 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15396 {
15397   const char *mnemonic;
15398
15399   FETCH_DATA (the_info, codep + 1);
15400   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15401      place where an 8-bit immediate would normally go.  ie. the last
15402      byte of the instruction.  */
15403   obufp = mnemonicendp;
15404   mnemonic = Suffix3DNow[*codep++ & 0xff];
15405   if (mnemonic)
15406     oappend (mnemonic);
15407   else
15408     {
15409       /* Since a variable sized modrm/sib chunk is between the start
15410          of the opcode (0x0f0f) and the opcode suffix, we need to do
15411          all the modrm processing first, and don't know until now that
15412          we have a bad opcode.  This necessitates some cleaning up.  */
15413       op_out[0][0] = '\0';
15414       op_out[1][0] = '\0';
15415       BadOp ();
15416     }
15417   mnemonicendp = obufp;
15418 }
15419
15420 static struct op simd_cmp_op[] =
15421 {
15422   { STRING_COMMA_LEN ("eq") },
15423   { STRING_COMMA_LEN ("lt") },
15424   { STRING_COMMA_LEN ("le") },
15425   { STRING_COMMA_LEN ("unord") },
15426   { STRING_COMMA_LEN ("neq") },
15427   { STRING_COMMA_LEN ("nlt") },
15428   { STRING_COMMA_LEN ("nle") },
15429   { STRING_COMMA_LEN ("ord") }
15430 };
15431
15432 static void
15433 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15434 {
15435   unsigned int cmp_type;
15436
15437   FETCH_DATA (the_info, codep + 1);
15438   cmp_type = *codep++ & 0xff;
15439   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15440     {
15441       char suffix [3];
15442       char *p = mnemonicendp - 2;
15443       suffix[0] = p[0];
15444       suffix[1] = p[1];
15445       suffix[2] = '\0';
15446       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15447       mnemonicendp += simd_cmp_op[cmp_type].len;
15448     }
15449   else
15450     {
15451       /* We have a reserved extension byte.  Output it directly.  */
15452       scratchbuf[0] = '$';
15453       print_operand_value (scratchbuf + 1, 1, cmp_type);
15454       oappend_maybe_intel (scratchbuf);
15455       scratchbuf[0] = '\0';
15456     }
15457 }
15458
15459 static void
15460 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15461 {
15462   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15463   if (!intel_syntax)
15464     {
15465       strcpy (op_out[0], names32[0]);
15466       strcpy (op_out[1], names32[1]);
15467       if (bytemode == eBX_reg)
15468         strcpy (op_out[2], names32[3]);
15469       two_source_ops = 1;
15470     }
15471   /* Skip mod/rm byte.  */
15472   MODRM_CHECK;
15473   codep++;
15474 }
15475
15476 static void
15477 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15478             int sizeflag ATTRIBUTE_UNUSED)
15479 {
15480   /* monitor %{e,r,}ax,%ecx,%edx"  */
15481   if (!intel_syntax)
15482     {
15483       const char **names = (address_mode == mode_64bit
15484                             ? names64 : names32);
15485
15486       if (prefixes & PREFIX_ADDR)
15487         {
15488           /* Remove "addr16/addr32".  */
15489           all_prefixes[last_addr_prefix] = 0;
15490           names = (address_mode != mode_32bit
15491                    ? names32 : names16);
15492           used_prefixes |= PREFIX_ADDR;
15493         }
15494       else if (address_mode == mode_16bit)
15495         names = names16;
15496       strcpy (op_out[0], names[0]);
15497       strcpy (op_out[1], names32[1]);
15498       strcpy (op_out[2], names32[2]);
15499       two_source_ops = 1;
15500     }
15501   /* Skip mod/rm byte.  */
15502   MODRM_CHECK;
15503   codep++;
15504 }
15505
15506 static void
15507 BadOp (void)
15508 {
15509   /* Throw away prefixes and 1st. opcode byte.  */
15510   codep = insn_codep + 1;
15511   oappend ("(bad)");
15512 }
15513
15514 static void
15515 REP_Fixup (int bytemode, int sizeflag)
15516 {
15517   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15518      lods and stos.  */
15519   if (prefixes & PREFIX_REPZ)
15520     all_prefixes[last_repz_prefix] = REP_PREFIX;
15521
15522   switch (bytemode)
15523     {
15524     case al_reg:
15525     case eAX_reg:
15526     case indir_dx_reg:
15527       OP_IMREG (bytemode, sizeflag);
15528       break;
15529     case eDI_reg:
15530       OP_ESreg (bytemode, sizeflag);
15531       break;
15532     case eSI_reg:
15533       OP_DSreg (bytemode, sizeflag);
15534       break;
15535     default:
15536       abort ();
15537       break;
15538     }
15539 }
15540
15541 static void
15542 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15543 {
15544   if ( isa64 != amd64 )
15545     return;
15546
15547   obufp = obuf;
15548   BadOp ();
15549   mnemonicendp = obufp;
15550   ++codep;
15551 }
15552
15553 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15554    "bnd".  */
15555
15556 static void
15557 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15558 {
15559   if (prefixes & PREFIX_REPNZ)
15560     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15561 }
15562
15563 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15564    "notrack".  */
15565
15566 static void
15567 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15568                int sizeflag ATTRIBUTE_UNUSED)
15569 {
15570   if (active_seg_prefix == PREFIX_DS
15571       && (address_mode != mode_64bit || last_data_prefix < 0))
15572     {
15573       /* NOTRACK prefix is only valid on indirect branch instructions.
15574          NB: DATA prefix is unsupported for Intel64.  */
15575       active_seg_prefix = 0;
15576       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15577     }
15578 }
15579
15580 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15581    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15582  */
15583
15584 static void
15585 HLE_Fixup1 (int bytemode, int sizeflag)
15586 {
15587   if (modrm.mod != 3
15588       && (prefixes & PREFIX_LOCK) != 0)
15589     {
15590       if (prefixes & PREFIX_REPZ)
15591         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15592       if (prefixes & PREFIX_REPNZ)
15593         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15594     }
15595
15596   OP_E (bytemode, sizeflag);
15597 }
15598
15599 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15600    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15601  */
15602
15603 static void
15604 HLE_Fixup2 (int bytemode, int sizeflag)
15605 {
15606   if (modrm.mod != 3)
15607     {
15608       if (prefixes & PREFIX_REPZ)
15609         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15610       if (prefixes & PREFIX_REPNZ)
15611         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15612     }
15613
15614   OP_E (bytemode, sizeflag);
15615 }
15616
15617 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15618    "xrelease" for memory operand.  No check for LOCK prefix.   */
15619
15620 static void
15621 HLE_Fixup3 (int bytemode, int sizeflag)
15622 {
15623   if (modrm.mod != 3
15624       && last_repz_prefix > last_repnz_prefix
15625       && (prefixes & PREFIX_REPZ) != 0)
15626     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15627
15628   OP_E (bytemode, sizeflag);
15629 }
15630
15631 static void
15632 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15633 {
15634   USED_REX (REX_W);
15635   if (rex & REX_W)
15636     {
15637       /* Change cmpxchg8b to cmpxchg16b.  */
15638       char *p = mnemonicendp - 2;
15639       mnemonicendp = stpcpy (p, "16b");
15640       bytemode = o_mode;
15641     }
15642   else if ((prefixes & PREFIX_LOCK) != 0)
15643     {
15644       if (prefixes & PREFIX_REPZ)
15645         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15646       if (prefixes & PREFIX_REPNZ)
15647         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15648     }
15649
15650   OP_M (bytemode, sizeflag);
15651 }
15652
15653 static void
15654 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15655 {
15656   const char **names;
15657
15658   if (need_vex)
15659     {
15660       switch (vex.length)
15661         {
15662         case 128:
15663           names = names_xmm;
15664           break;
15665         case 256:
15666           names = names_ymm;
15667           break;
15668         default:
15669           abort ();
15670         }
15671     }
15672   else
15673     names = names_xmm;
15674   oappend (names[reg]);
15675 }
15676
15677 static void
15678 CRC32_Fixup (int bytemode, int sizeflag)
15679 {
15680   /* Add proper suffix to "crc32".  */
15681   char *p = mnemonicendp;
15682
15683   switch (bytemode)
15684     {
15685     case b_mode:
15686       if (intel_syntax)
15687         goto skip;
15688
15689       *p++ = 'b';
15690       break;
15691     case v_mode:
15692       if (intel_syntax)
15693         goto skip;
15694
15695       USED_REX (REX_W);
15696       if (rex & REX_W)
15697         *p++ = 'q';
15698       else
15699         {
15700           if (sizeflag & DFLAG)
15701             *p++ = 'l';
15702           else
15703             *p++ = 'w';
15704           used_prefixes |= (prefixes & PREFIX_DATA);
15705         }
15706       break;
15707     default:
15708       oappend (INTERNAL_DISASSEMBLER_ERROR);
15709       break;
15710     }
15711   mnemonicendp = p;
15712   *p = '\0';
15713
15714  skip:
15715   if (modrm.mod == 3)
15716     {
15717       int add;
15718
15719       /* Skip mod/rm byte.  */
15720       MODRM_CHECK;
15721       codep++;
15722
15723       USED_REX (REX_B);
15724       add = (rex & REX_B) ? 8 : 0;
15725       if (bytemode == b_mode)
15726         {
15727           USED_REX (0);
15728           if (rex)
15729             oappend (names8rex[modrm.rm + add]);
15730           else
15731             oappend (names8[modrm.rm + add]);
15732         }
15733       else
15734         {
15735           USED_REX (REX_W);
15736           if (rex & REX_W)
15737             oappend (names64[modrm.rm + add]);
15738           else if ((prefixes & PREFIX_DATA))
15739             oappend (names16[modrm.rm + add]);
15740           else
15741             oappend (names32[modrm.rm + add]);
15742         }
15743     }
15744   else
15745     OP_E (bytemode, sizeflag);
15746 }
15747
15748 static void
15749 FXSAVE_Fixup (int bytemode, int sizeflag)
15750 {
15751   /* Add proper suffix to "fxsave" and "fxrstor".  */
15752   USED_REX (REX_W);
15753   if (rex & REX_W)
15754     {
15755       char *p = mnemonicendp;
15756       *p++ = '6';
15757       *p++ = '4';
15758       *p = '\0';
15759       mnemonicendp = p;
15760     }
15761   OP_M (bytemode, sizeflag);
15762 }
15763
15764 static void
15765 PCMPESTR_Fixup (int bytemode, int sizeflag)
15766 {
15767   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15768   if (!intel_syntax)
15769     {
15770       char *p = mnemonicendp;
15771
15772       USED_REX (REX_W);
15773       if (rex & REX_W)
15774         *p++ = 'q';
15775       else if (sizeflag & SUFFIX_ALWAYS)
15776         *p++ = 'l';
15777
15778       *p = '\0';
15779       mnemonicendp = p;
15780     }
15781
15782   OP_EX (bytemode, sizeflag);
15783 }
15784
15785 /* Display the destination register operand for instructions with
15786    VEX. */
15787
15788 static void
15789 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15790 {
15791   int reg;
15792   const char **names;
15793
15794   if (!need_vex)
15795     abort ();
15796
15797   if (!need_vex_reg)
15798     return;
15799
15800   reg = vex.register_specifier;
15801   vex.register_specifier = 0;
15802   if (address_mode != mode_64bit)
15803     reg &= 7;
15804   else if (vex.evex && !vex.v)
15805     reg += 16;
15806
15807   if (bytemode == vex_scalar_mode)
15808     {
15809       oappend (names_xmm[reg]);
15810       return;
15811     }
15812
15813   switch (vex.length)
15814     {
15815     case 128:
15816       switch (bytemode)
15817         {
15818         case vex_mode:
15819         case vex128_mode:
15820         case vex_vsib_q_w_dq_mode:
15821         case vex_vsib_q_w_d_mode:
15822           names = names_xmm;
15823           break;
15824         case dq_mode:
15825           if (rex & REX_W)
15826             names = names64;
15827           else
15828             names = names32;
15829           break;
15830         case mask_bd_mode:
15831         case mask_mode:
15832           if (reg > 0x7)
15833             {
15834               oappend ("(bad)");
15835               return;
15836             }
15837           names = names_mask;
15838           break;
15839         default:
15840           abort ();
15841           return;
15842         }
15843       break;
15844     case 256:
15845       switch (bytemode)
15846         {
15847         case vex_mode:
15848         case vex256_mode:
15849           names = names_ymm;
15850           break;
15851         case vex_vsib_q_w_dq_mode:
15852         case vex_vsib_q_w_d_mode:
15853           names = vex.w ? names_ymm : names_xmm;
15854           break;
15855         case mask_bd_mode:
15856         case mask_mode:
15857           if (reg > 0x7)
15858             {
15859               oappend ("(bad)");
15860               return;
15861             }
15862           names = names_mask;
15863           break;
15864         default:
15865           /* See PR binutils/20893 for a reproducer.  */
15866           oappend ("(bad)");
15867           return;
15868         }
15869       break;
15870     case 512:
15871       names = names_zmm;
15872       break;
15873     default:
15874       abort ();
15875       break;
15876     }
15877   oappend (names[reg]);
15878 }
15879
15880 /* Get the VEX immediate byte without moving codep.  */
15881
15882 static unsigned char
15883 get_vex_imm8 (int sizeflag, int opnum)
15884 {
15885   int bytes_before_imm = 0;
15886
15887   if (modrm.mod != 3)
15888     {
15889       /* There are SIB/displacement bytes.  */
15890       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15891         {
15892           /* 32/64 bit address mode */
15893           int base = modrm.rm;
15894
15895           /* Check SIB byte.  */
15896           if (base == 4)
15897             {
15898               FETCH_DATA (the_info, codep + 1);
15899               base = *codep & 7;
15900               /* When decoding the third source, don't increase
15901                  bytes_before_imm as this has already been incremented
15902                  by one in OP_E_memory while decoding the second
15903                  source operand.  */
15904               if (opnum == 0)
15905                 bytes_before_imm++;
15906             }
15907
15908           /* Don't increase bytes_before_imm when decoding the third source,
15909              it has already been incremented by OP_E_memory while decoding
15910              the second source operand.  */
15911           if (opnum == 0)
15912             {
15913               switch (modrm.mod)
15914                 {
15915                   case 0:
15916                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15917                        SIB == 5, there is a 4 byte displacement.  */
15918                     if (base != 5)
15919                       /* No displacement. */
15920                       break;
15921                     /* Fall through.  */
15922                   case 2:
15923                     /* 4 byte displacement.  */
15924                     bytes_before_imm += 4;
15925                     break;
15926                   case 1:
15927                     /* 1 byte displacement.  */
15928                     bytes_before_imm++;
15929                     break;
15930                 }
15931             }
15932         }
15933       else
15934         {
15935           /* 16 bit address mode */
15936           /* Don't increase bytes_before_imm when decoding the third source,
15937              it has already been incremented by OP_E_memory while decoding
15938              the second source operand.  */
15939           if (opnum == 0)
15940             {
15941               switch (modrm.mod)
15942                 {
15943                 case 0:
15944                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
15945                   if (modrm.rm != 6)
15946                     /* No displacement. */
15947                     break;
15948                   /* Fall through.  */
15949                 case 2:
15950                   /* 2 byte displacement.  */
15951                   bytes_before_imm += 2;
15952                   break;
15953                 case 1:
15954                   /* 1 byte displacement: when decoding the third source,
15955                      don't increase bytes_before_imm as this has already
15956                      been incremented by one in OP_E_memory while decoding
15957                      the second source operand.  */
15958                   if (opnum == 0)
15959                     bytes_before_imm++;
15960
15961                   break;
15962                 }
15963             }
15964         }
15965     }
15966
15967   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
15968   return codep [bytes_before_imm];
15969 }
15970
15971 static void
15972 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
15973 {
15974   const char **names;
15975
15976   if (reg == -1 && modrm.mod != 3)
15977     {
15978       OP_E_memory (bytemode, sizeflag);
15979       return;
15980     }
15981   else
15982     {
15983       if (reg == -1)
15984         {
15985           reg = modrm.rm;
15986           USED_REX (REX_B);
15987           if (rex & REX_B)
15988             reg += 8;
15989         }
15990       if (address_mode != mode_64bit)
15991         reg &= 7;
15992     }
15993
15994   switch (vex.length)
15995     {
15996     case 128:
15997       names = names_xmm;
15998       break;
15999     case 256:
16000       names = names_ymm;
16001       break;
16002     default:
16003       abort ();
16004     }
16005   oappend (names[reg]);
16006 }
16007
16008 static void
16009 OP_EX_VexImmW (int bytemode, int sizeflag)
16010 {
16011   int reg = -1;
16012   static unsigned char vex_imm8;
16013
16014   if (vex_w_done == 0)
16015     {
16016       vex_w_done = 1;
16017
16018       /* Skip mod/rm byte.  */
16019       MODRM_CHECK;
16020       codep++;
16021
16022       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16023
16024       if (vex.w)
16025           reg = vex_imm8 >> 4;
16026
16027       OP_EX_VexReg (bytemode, sizeflag, reg);
16028     }
16029   else if (vex_w_done == 1)
16030     {
16031       vex_w_done = 2;
16032
16033       if (!vex.w)
16034           reg = vex_imm8 >> 4;
16035
16036       OP_EX_VexReg (bytemode, sizeflag, reg);
16037     }
16038   else
16039     {
16040       /* Output the imm8 directly.  */
16041       scratchbuf[0] = '$';
16042       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16043       oappend_maybe_intel (scratchbuf);
16044       scratchbuf[0] = '\0';
16045       codep++;
16046     }
16047 }
16048
16049 static void
16050 OP_Vex_2src (int bytemode, int sizeflag)
16051 {
16052   if (modrm.mod == 3)
16053     {
16054       int reg = modrm.rm;
16055       USED_REX (REX_B);
16056       if (rex & REX_B)
16057         reg += 8;
16058       oappend (names_xmm[reg]);
16059     }
16060   else
16061     {
16062       if (intel_syntax
16063           && (bytemode == v_mode || bytemode == v_swap_mode))
16064         {
16065           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16066           used_prefixes |= (prefixes & PREFIX_DATA);
16067         }
16068       OP_E (bytemode, sizeflag);
16069     }
16070 }
16071
16072 static void
16073 OP_Vex_2src_1 (int bytemode, int sizeflag)
16074 {
16075   if (modrm.mod == 3)
16076     {
16077       /* Skip mod/rm byte.   */
16078       MODRM_CHECK;
16079       codep++;
16080     }
16081
16082   if (vex.w)
16083     {
16084       unsigned int reg = vex.register_specifier;
16085       vex.register_specifier = 0;
16086
16087       if (address_mode != mode_64bit)
16088         reg &= 7;
16089       oappend (names_xmm[reg]);
16090     }
16091   else
16092     OP_Vex_2src (bytemode, sizeflag);
16093 }
16094
16095 static void
16096 OP_Vex_2src_2 (int bytemode, int sizeflag)
16097 {
16098   if (vex.w)
16099     OP_Vex_2src (bytemode, sizeflag);
16100   else
16101     {
16102       unsigned int reg = vex.register_specifier;
16103       vex.register_specifier = 0;
16104
16105       if (address_mode != mode_64bit)
16106         reg &= 7;
16107       oappend (names_xmm[reg]);
16108     }
16109 }
16110
16111 static void
16112 OP_EX_VexW (int bytemode, int sizeflag)
16113 {
16114   int reg = -1;
16115
16116   if (!vex_w_done)
16117     {
16118       /* Skip mod/rm byte.  */
16119       MODRM_CHECK;
16120       codep++;
16121
16122       if (vex.w)
16123         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16124     }
16125   else
16126     {
16127       if (!vex.w)
16128         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16129     }
16130
16131   OP_EX_VexReg (bytemode, sizeflag, reg);
16132
16133   if (vex_w_done)
16134     codep++;
16135   vex_w_done = 1;
16136 }
16137
16138 static void
16139 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16140 {
16141   int reg;
16142   const char **names;
16143
16144   FETCH_DATA (the_info, codep + 1);
16145   reg = *codep++;
16146
16147   if (bytemode != x_mode)
16148     abort ();
16149
16150   reg >>= 4;
16151   if (address_mode != mode_64bit)
16152     reg &= 7;
16153
16154   switch (vex.length)
16155     {
16156     case 128:
16157       names = names_xmm;
16158       break;
16159     case 256:
16160       names = names_ymm;
16161       break;
16162     default:
16163       abort ();
16164     }
16165   oappend (names[reg]);
16166 }
16167
16168 static void
16169 OP_XMM_VexW (int bytemode, int sizeflag)
16170 {
16171   /* Turn off the REX.W bit since it is used for swapping operands
16172      now.  */
16173   rex &= ~REX_W;
16174   OP_XMM (bytemode, sizeflag);
16175 }
16176
16177 static void
16178 OP_EX_Vex (int bytemode, int sizeflag)
16179 {
16180   if (modrm.mod != 3)
16181     need_vex_reg = 0;
16182   OP_EX (bytemode, sizeflag);
16183 }
16184
16185 static void
16186 OP_XMM_Vex (int bytemode, int sizeflag)
16187 {
16188   if (modrm.mod != 3)
16189     need_vex_reg = 0;
16190   OP_XMM (bytemode, sizeflag);
16191 }
16192
16193 static struct op vex_cmp_op[] =
16194 {
16195   { STRING_COMMA_LEN ("eq") },
16196   { STRING_COMMA_LEN ("lt") },
16197   { STRING_COMMA_LEN ("le") },
16198   { STRING_COMMA_LEN ("unord") },
16199   { STRING_COMMA_LEN ("neq") },
16200   { STRING_COMMA_LEN ("nlt") },
16201   { STRING_COMMA_LEN ("nle") },
16202   { STRING_COMMA_LEN ("ord") },
16203   { STRING_COMMA_LEN ("eq_uq") },
16204   { STRING_COMMA_LEN ("nge") },
16205   { STRING_COMMA_LEN ("ngt") },
16206   { STRING_COMMA_LEN ("false") },
16207   { STRING_COMMA_LEN ("neq_oq") },
16208   { STRING_COMMA_LEN ("ge") },
16209   { STRING_COMMA_LEN ("gt") },
16210   { STRING_COMMA_LEN ("true") },
16211   { STRING_COMMA_LEN ("eq_os") },
16212   { STRING_COMMA_LEN ("lt_oq") },
16213   { STRING_COMMA_LEN ("le_oq") },
16214   { STRING_COMMA_LEN ("unord_s") },
16215   { STRING_COMMA_LEN ("neq_us") },
16216   { STRING_COMMA_LEN ("nlt_uq") },
16217   { STRING_COMMA_LEN ("nle_uq") },
16218   { STRING_COMMA_LEN ("ord_s") },
16219   { STRING_COMMA_LEN ("eq_us") },
16220   { STRING_COMMA_LEN ("nge_uq") },
16221   { STRING_COMMA_LEN ("ngt_uq") },
16222   { STRING_COMMA_LEN ("false_os") },
16223   { STRING_COMMA_LEN ("neq_os") },
16224   { STRING_COMMA_LEN ("ge_oq") },
16225   { STRING_COMMA_LEN ("gt_oq") },
16226   { STRING_COMMA_LEN ("true_us") },
16227 };
16228
16229 static void
16230 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16231 {
16232   unsigned int cmp_type;
16233
16234   FETCH_DATA (the_info, codep + 1);
16235   cmp_type = *codep++ & 0xff;
16236   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16237     {
16238       char suffix [3];
16239       char *p = mnemonicendp - 2;
16240       suffix[0] = p[0];
16241       suffix[1] = p[1];
16242       suffix[2] = '\0';
16243       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16244       mnemonicendp += vex_cmp_op[cmp_type].len;
16245     }
16246   else
16247     {
16248       /* We have a reserved extension byte.  Output it directly.  */
16249       scratchbuf[0] = '$';
16250       print_operand_value (scratchbuf + 1, 1, cmp_type);
16251       oappend_maybe_intel (scratchbuf);
16252       scratchbuf[0] = '\0';
16253     }
16254 }
16255
16256 static void
16257 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16258              int sizeflag ATTRIBUTE_UNUSED)
16259 {
16260   unsigned int cmp_type;
16261
16262   if (!vex.evex)
16263     abort ();
16264
16265   FETCH_DATA (the_info, codep + 1);
16266   cmp_type = *codep++ & 0xff;
16267   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16268      If it's the case, print suffix, otherwise - print the immediate.  */
16269   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16270       && cmp_type != 3
16271       && cmp_type != 7)
16272     {
16273       char suffix [3];
16274       char *p = mnemonicendp - 2;
16275
16276       /* vpcmp* can have both one- and two-lettered suffix.  */
16277       if (p[0] == 'p')
16278         {
16279           p++;
16280           suffix[0] = p[0];
16281           suffix[1] = '\0';
16282         }
16283       else
16284         {
16285           suffix[0] = p[0];
16286           suffix[1] = p[1];
16287           suffix[2] = '\0';
16288         }
16289
16290       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16291       mnemonicendp += simd_cmp_op[cmp_type].len;
16292     }
16293   else
16294     {
16295       /* We have a reserved extension byte.  Output it directly.  */
16296       scratchbuf[0] = '$';
16297       print_operand_value (scratchbuf + 1, 1, cmp_type);
16298       oappend_maybe_intel (scratchbuf);
16299       scratchbuf[0] = '\0';
16300     }
16301 }
16302
16303 static const struct op xop_cmp_op[] =
16304 {
16305   { STRING_COMMA_LEN ("lt") },
16306   { STRING_COMMA_LEN ("le") },
16307   { STRING_COMMA_LEN ("gt") },
16308   { STRING_COMMA_LEN ("ge") },
16309   { STRING_COMMA_LEN ("eq") },
16310   { STRING_COMMA_LEN ("neq") },
16311   { STRING_COMMA_LEN ("false") },
16312   { STRING_COMMA_LEN ("true") }
16313 };
16314
16315 static void
16316 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16317              int sizeflag ATTRIBUTE_UNUSED)
16318 {
16319   unsigned int cmp_type;
16320
16321   FETCH_DATA (the_info, codep + 1);
16322   cmp_type = *codep++ & 0xff;
16323   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16324     {
16325       char suffix[3];
16326       char *p = mnemonicendp - 2;
16327
16328       /* vpcom* can have both one- and two-lettered suffix.  */
16329       if (p[0] == 'm')
16330         {
16331           p++;
16332           suffix[0] = p[0];
16333           suffix[1] = '\0';
16334         }
16335       else
16336         {
16337           suffix[0] = p[0];
16338           suffix[1] = p[1];
16339           suffix[2] = '\0';
16340         }
16341
16342       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16343       mnemonicendp += xop_cmp_op[cmp_type].len;
16344     }
16345   else
16346     {
16347       /* We have a reserved extension byte.  Output it directly.  */
16348       scratchbuf[0] = '$';
16349       print_operand_value (scratchbuf + 1, 1, cmp_type);
16350       oappend_maybe_intel (scratchbuf);
16351       scratchbuf[0] = '\0';
16352     }
16353 }
16354
16355 static const struct op pclmul_op[] =
16356 {
16357   { STRING_COMMA_LEN ("lql") },
16358   { STRING_COMMA_LEN ("hql") },
16359   { STRING_COMMA_LEN ("lqh") },
16360   { STRING_COMMA_LEN ("hqh") }
16361 };
16362
16363 static void
16364 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16365               int sizeflag ATTRIBUTE_UNUSED)
16366 {
16367   unsigned int pclmul_type;
16368
16369   FETCH_DATA (the_info, codep + 1);
16370   pclmul_type = *codep++ & 0xff;
16371   switch (pclmul_type)
16372     {
16373     case 0x10:
16374       pclmul_type = 2;
16375       break;
16376     case 0x11:
16377       pclmul_type = 3;
16378       break;
16379     default:
16380       break;
16381     }
16382   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16383     {
16384       char suffix [4];
16385       char *p = mnemonicendp - 3;
16386       suffix[0] = p[0];
16387       suffix[1] = p[1];
16388       suffix[2] = p[2];
16389       suffix[3] = '\0';
16390       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16391       mnemonicendp += pclmul_op[pclmul_type].len;
16392     }
16393   else
16394     {
16395       /* We have a reserved extension byte.  Output it directly.  */
16396       scratchbuf[0] = '$';
16397       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16398       oappend_maybe_intel (scratchbuf);
16399       scratchbuf[0] = '\0';
16400     }
16401 }
16402
16403 static void
16404 MOVBE_Fixup (int bytemode, int sizeflag)
16405 {
16406   /* Add proper suffix to "movbe".  */
16407   char *p = mnemonicendp;
16408
16409   switch (bytemode)
16410     {
16411     case v_mode:
16412       if (intel_syntax)
16413         goto skip;
16414
16415       USED_REX (REX_W);
16416       if (sizeflag & SUFFIX_ALWAYS)
16417         {
16418           if (rex & REX_W)
16419             *p++ = 'q';
16420           else
16421             {
16422               if (sizeflag & DFLAG)
16423                 *p++ = 'l';
16424               else
16425                 *p++ = 'w';
16426               used_prefixes |= (prefixes & PREFIX_DATA);
16427             }
16428         }
16429       break;
16430     default:
16431       oappend (INTERNAL_DISASSEMBLER_ERROR);
16432       break;
16433     }
16434   mnemonicendp = p;
16435   *p = '\0';
16436
16437  skip:
16438   OP_M (bytemode, sizeflag);
16439 }
16440
16441 static void
16442 MOVSXD_Fixup (int bytemode, int sizeflag)
16443 {
16444   /* Add proper suffix to "movsxd".  */
16445   char *p = mnemonicendp;
16446
16447   switch (bytemode)
16448     {
16449     case movsxd_mode:
16450       if (intel_syntax)
16451         {
16452           *p++ = 'x';
16453           *p++ = 'd';
16454           goto skip;
16455         }
16456
16457       USED_REX (REX_W);
16458       if (rex & REX_W)
16459         {
16460           *p++ = 'l';
16461           *p++ = 'q';
16462         }
16463       else
16464         {
16465           *p++ = 'x';
16466           *p++ = 'd';
16467         }
16468       break;
16469     default:
16470       oappend (INTERNAL_DISASSEMBLER_ERROR);
16471       break;
16472     }
16473
16474  skip:
16475   mnemonicendp = p;
16476   *p = '\0';
16477   OP_E (bytemode, sizeflag);
16478 }
16479
16480 static void
16481 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16482 {
16483   int reg;
16484   const char **names;
16485
16486   /* Skip mod/rm byte.  */
16487   MODRM_CHECK;
16488   codep++;
16489
16490   if (rex & REX_W)
16491     names = names64;
16492   else
16493     names = names32;
16494
16495   reg = modrm.rm;
16496   USED_REX (REX_B);
16497   if (rex & REX_B)
16498     reg += 8;
16499
16500   oappend (names[reg]);
16501 }
16502
16503 static void
16504 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16505 {
16506   const char **names;
16507   unsigned int reg = vex.register_specifier;
16508   vex.register_specifier = 0;
16509
16510   if (rex & REX_W)
16511     names = names64;
16512   else
16513     names = names32;
16514
16515   if (address_mode != mode_64bit)
16516     reg &= 7;
16517   oappend (names[reg]);
16518 }
16519
16520 static void
16521 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16522 {
16523   if (!vex.evex
16524       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16525     abort ();
16526
16527   USED_REX (REX_R);
16528   if ((rex & REX_R) != 0 || !vex.r)
16529     {
16530       BadOp ();
16531       return;
16532     }
16533
16534   oappend (names_mask [modrm.reg]);
16535 }
16536
16537 static void
16538 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16539 {
16540   if (modrm.mod == 3 && vex.b)
16541     switch (bytemode)
16542       {
16543       case evex_rounding_64_mode:
16544         if (address_mode != mode_64bit)
16545           {
16546             oappend ("(bad)");
16547             break;
16548           }
16549         /* Fall through.  */
16550       case evex_rounding_mode:
16551         oappend (names_rounding[vex.ll]);
16552         break;
16553       case evex_sae_mode:
16554         oappend ("{sae}");
16555         break;
16556       default:
16557         abort ();
16558         break;
16559       }
16560 }