opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 /* Possible values for prefix requirement.  */
 225 #define PREFIX_IGNORED_SHIFT    16
 226 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 227 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 231
 232 /* Opcode prefixes.  */
 233 #define PREFIX_OPCODE           (PREFIX_REPZ \
 234                                  | PREFIX_REPNZ \
 235                                  | PREFIX_DATA)
 236
 237 /* Prefixes ignored.  */
 238 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 239                                  | PREFIX_IGNORED_REPNZ \
 240                                  | PREFIX_IGNORED_DATA)
 241
 242 #define XX { NULL, 0 }
 243 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 244
 245 #define Eb { OP_E, b_mode }
 246 #define Ebnd { OP_E, bnd_mode }
 247 #define EbS { OP_E, b_swap_mode }
 248 #define Ev { OP_E, v_mode }
 249 #define Ev_bnd { OP_E, v_bnd_mode }
 250 #define EvS { OP_E, v_swap_mode }
 251 #define Ed { OP_E, d_mode }
 252 #define Edq { OP_E, dq_mode }
 253 #define Edqw { OP_E, dqw_mode }
 254 #define EdqwS { OP_E, dqw_swap_mode }
 255 #define Edqb { OP_E, dqb_mode }
 256 #define Edb { OP_E, db_mode }
 257 #define Edw { OP_E, dw_mode }
 258 #define Edqd { OP_E, dqd_mode }
 259 #define Eq { OP_E, q_mode }
 260 #define indirEv { OP_indirE, stack_v_mode }
 261 #define indirEp { OP_indirE, f_mode }
 262 #define stackEv { OP_E, stack_v_mode }
 263 #define Em { OP_E, m_mode }
 264 #define Ew { OP_E, w_mode }
 265 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 266 #define Ma { OP_M, a_mode }
 267 #define Mb { OP_M, b_mode }
 268 #define Md { OP_M, d_mode }
 269 #define Mo { OP_M, o_mode }
 270 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 271 #define Mq { OP_M, q_mode }
 272 #define Mx { OP_M, x_mode }
 273 #define Mxmm { OP_M, xmm_mode }
 274 #define Gb { OP_G, b_mode }
 275 #define Gbnd { OP_G, bnd_mode }
 276 #define Gv { OP_G, v_mode }
 277 #define Gd { OP_G, d_mode }
 278 #define Gdq { OP_G, dq_mode }
 279 #define Gm { OP_G, m_mode }
 280 #define Gw { OP_G, w_mode }
 281 #define Rd { OP_R, d_mode }
 282 #define Rdq { OP_R, dq_mode }
 283 #define Rm { OP_R, m_mode }
 284 #define Ib { OP_I, b_mode }
 285 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 286 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 287 #define Iv { OP_I, v_mode }
 288 #define sIv { OP_sI, v_mode }
 289 #define Iq { OP_I, q_mode }
 290 #define Iv64 { OP_I64, v_mode }
 291 #define Iw { OP_I, w_mode }
 292 #define I1 { OP_I, const_1_mode }
 293 #define Jb { OP_J, b_mode }
 294 #define Jv { OP_J, v_mode }
 295 #define Cm { OP_C, m_mode }
 296 #define Dm { OP_D, m_mode }
 297 #define Td { OP_T, d_mode }
 298 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 299
 300 #define RMeAX { OP_REG, eAX_reg }
 301 #define RMeBX { OP_REG, eBX_reg }
 302 #define RMeCX { OP_REG, eCX_reg }
 303 #define RMeDX { OP_REG, eDX_reg }
 304 #define RMeSP { OP_REG, eSP_reg }
 305 #define RMeBP { OP_REG, eBP_reg }
 306 #define RMeSI { OP_REG, eSI_reg }
 307 #define RMeDI { OP_REG, eDI_reg }
 308 #define RMrAX { OP_REG, rAX_reg }
 309 #define RMrBX { OP_REG, rBX_reg }
 310 #define RMrCX { OP_REG, rCX_reg }
 311 #define RMrDX { OP_REG, rDX_reg }
 312 #define RMrSP { OP_REG, rSP_reg }
 313 #define RMrBP { OP_REG, rBP_reg }
 314 #define RMrSI { OP_REG, rSI_reg }
 315 #define RMrDI { OP_REG, rDI_reg }
 316 #define RMAL { OP_REG, al_reg }
 317 #define RMCL { OP_REG, cl_reg }
 318 #define RMDL { OP_REG, dl_reg }
 319 #define RMBL { OP_REG, bl_reg }
 320 #define RMAH { OP_REG, ah_reg }
 321 #define RMCH { OP_REG, ch_reg }
 322 #define RMDH { OP_REG, dh_reg }
 323 #define RMBH { OP_REG, bh_reg }
 324 #define RMAX { OP_REG, ax_reg }
 325 #define RMDX { OP_REG, dx_reg }
 326
 327 #define eAX { OP_IMREG, eAX_reg }
 328 #define eBX { OP_IMREG, eBX_reg }
 329 #define eCX { OP_IMREG, eCX_reg }
 330 #define eDX { OP_IMREG, eDX_reg }
 331 #define eSP { OP_IMREG, eSP_reg }
 332 #define eBP { OP_IMREG, eBP_reg }
 333 #define eSI { OP_IMREG, eSI_reg }
 334 #define eDI { OP_IMREG, eDI_reg }
 335 #define AL { OP_IMREG, al_reg }
 336 #define CL { OP_IMREG, cl_reg }
 337 #define DL { OP_IMREG, dl_reg }
 338 #define BL { OP_IMREG, bl_reg }
 339 #define AH { OP_IMREG, ah_reg }
 340 #define CH { OP_IMREG, ch_reg }
 341 #define DH { OP_IMREG, dh_reg }
 342 #define BH { OP_IMREG, bh_reg }
 343 #define AX { OP_IMREG, ax_reg }
 344 #define DX { OP_IMREG, dx_reg }
 345 #define zAX { OP_IMREG, z_mode_ax_reg }
 346 #define indirDX { OP_IMREG, indir_dx_reg }
 347
 348 #define Sw { OP_SEG, w_mode }
 349 #define Sv { OP_SEG, v_mode }
 350 #define Ap { OP_DIR, 0 }
 351 #define Ob { OP_OFF64, b_mode }
 352 #define Ov { OP_OFF64, v_mode }
 353 #define Xb { OP_DSreg, eSI_reg }
 354 #define Xv { OP_DSreg, eSI_reg }
 355 #define Xz { OP_DSreg, eSI_reg }
 356 #define Yb { OP_ESreg, eDI_reg }
 357 #define Yv { OP_ESreg, eDI_reg }
 358 #define DSBX { OP_DSreg, eBX_reg }
 359
 360 #define es { OP_REG, es_reg }
 361 #define ss { OP_REG, ss_reg }
 362 #define cs { OP_REG, cs_reg }
 363 #define ds { OP_REG, ds_reg }
 364 #define fs { OP_REG, fs_reg }
 365 #define gs { OP_REG, gs_reg }
 366
 367 #define MX { OP_MMX, 0 }
 368 #define XM { OP_XMM, 0 }
 369 #define XMScalar { OP_XMM, scalar_mode }
 370 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 371 #define XMM { OP_XMM, xmm_mode }
 372 #define XMxmmq { OP_XMM, xmmq_mode }
 373 #define EM { OP_EM, v_mode }
 374 #define EMS { OP_EM, v_swap_mode }
 375 #define EMd { OP_EM, d_mode }
 376 #define EMx { OP_EM, x_mode }
 377 #define EXw { OP_EX, w_mode }
 378 #define EXd { OP_EX, d_mode }
 379 #define EXdScalar { OP_EX, d_scalar_mode }
 380 #define EXdS { OP_EX, d_swap_mode }
 381 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 382 #define EXq { OP_EX, q_mode }
 383 #define EXqScalar { OP_EX, q_scalar_mode }
 384 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 385 #define EXqS { OP_EX, q_swap_mode }
 386 #define EXx { OP_EX, x_mode }
 387 #define EXxS { OP_EX, x_swap_mode }
 388 #define EXxmm { OP_EX, xmm_mode }
 389 #define EXymm { OP_EX, ymm_mode }
 390 #define EXxmmq { OP_EX, xmmq_mode }
 391 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 392 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 393 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 394 #define EXxmm_md { OP_EX, xmm_md_mode }
 395 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 396 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 397 #define EXxmmdw { OP_EX, xmmdw_mode }
 398 #define EXxmmqd { OP_EX, xmmqd_mode }
 399 #define EXymmq { OP_EX, ymmq_mode }
 400 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 401 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 402 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 403 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 404 #define MS { OP_MS, v_mode }
 405 #define XS { OP_XS, v_mode }
 406 #define EMCq { OP_EMC, q_mode }
 407 #define MXC { OP_MXC, 0 }
 408 #define OPSUF { OP_3DNowSuffix, 0 }
 409 #define CMP { CMP_Fixup, 0 }
 410 #define XMM0 { XMM_Fixup, 0 }
 411 #define FXSAVE { FXSAVE_Fixup, 0 }
 412 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 413 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 414
 415 #define Vex { OP_VEX, vex_mode }
 416 #define VexScalar { OP_VEX, vex_scalar_mode }
 417 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 418 #define Vex128 { OP_VEX, vex128_mode }
 419 #define Vex256 { OP_VEX, vex256_mode }
 420 #define VexGdq { OP_VEX, dq_mode }
 421 #define VexI4 { VEXI4_Fixup, 0}
 422 #define EXdVex { OP_EX_Vex, d_mode }
 423 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVex { OP_EX_Vex, q_mode }
 426 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 428 #define EXVexW { OP_EX_VexW, x_mode }
 429 #define EXdVexW { OP_EX_VexW, d_mode }
 430 #define EXqVexW { OP_EX_VexW, q_mode }
 431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 432 #define XMVex { OP_XMM_Vex, 0 }
 433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 434 #define XMVexW { OP_XMM_VexW, 0 }
 435 #define XMVexI4 { OP_REG_VexI4, x_mode }
 436 #define PCLMUL { PCLMUL_Fixup, 0 }
 437 #define VZERO { VZERO_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440
 441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 443
 444 #define XMask { OP_Mask, mask_mode }
 445 #define MaskG { OP_G, mask_mode }
 446 #define MaskE { OP_E, mask_mode }
 447 #define MaskBDE { OP_E, mask_bd_mode }
 448 #define MaskR { OP_R, mask_mode }
 449 #define MaskVex { OP_VEX, mask_mode }
 450
 451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 455
 456 /* Used handle "rep" prefix for string instructions.  */
 457 #define Xbr { REP_Fixup, eSI_reg }
 458 #define Xvr { REP_Fixup, eSI_reg }
 459 #define Ybr { REP_Fixup, eDI_reg }
 460 #define Yvr { REP_Fixup, eDI_reg }
 461 #define Yzr { REP_Fixup, eDI_reg }
 462 #define indirDXr { REP_Fixup, indir_dx_reg }
 463 #define ALr { REP_Fixup, al_reg }
 464 #define eAXr { REP_Fixup, eAX_reg }
 465
 466 /* Used handle HLE prefix for lockable instructions.  */
 467 #define Ebh1 { HLE_Fixup1, b_mode }
 468 #define Evh1 { HLE_Fixup1, v_mode }
 469 #define Ebh2 { HLE_Fixup2, b_mode }
 470 #define Evh2 { HLE_Fixup2, v_mode }
 471 #define Ebh3 { HLE_Fixup3, b_mode }
 472 #define Evh3 { HLE_Fixup3, v_mode }
 473
 474 #define BND { BND_Fixup, 0 }
 475
 476 #define cond_jump_flag { NULL, cond_jump_mode }
 477 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 478
 479 /* bits in sizeflag */
 480 #define SUFFIX_ALWAYS 4
 481 #define AFLAG 2
 482 #define DFLAG 1
 483
 484 enum
 485 {
 486   /* byte operand */
 487   b_mode = 1,
 488   /* byte operand with operand swapped */
 489   b_swap_mode,
 490   /* byte operand, sign extend like 'T' suffix */
 491   b_T_mode,
 492   /* operand size depends on prefixes */
 493   v_mode,
 494   /* operand size depends on prefixes with operand swapped */
 495   v_swap_mode,
 496   /* word operand */
 497   w_mode,
 498   /* double word operand  */
 499   d_mode,
 500   /* double word operand with operand swapped */
 501   d_swap_mode,
 502   /* quad word operand */
 503   q_mode,
 504   /* quad word operand with operand swapped */
 505   q_swap_mode,
 506   /* ten-byte operand */
 507   t_mode,
 508   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 509      broadcast enabled.  */
 510   x_mode,
 511   /* Similar to x_mode, but with different EVEX mem shifts.  */
 512   evex_x_gscat_mode,
 513   /* Similar to x_mode, but with disabled broadcast.  */
 514   evex_x_nobcst_mode,
 515   /* Similar to x_mode, but with operands swapped and disabled broadcast
 516      in EVEX.  */
 517   x_swap_mode,
 518   /* 16-byte XMM operand */
 519   xmm_mode,
 520   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 521      memory operand (depending on vector length).  Broadcast isn't
 522      allowed.  */
 523   xmmq_mode,
 524   /* Same as xmmq_mode, but broadcast is allowed.  */
 525   evex_half_bcst_xmmq_mode,
 526   /* XMM register or byte memory operand */
 527   xmm_mb_mode,
 528   /* XMM register or word memory operand */
 529   xmm_mw_mode,
 530   /* XMM register or double word memory operand */
 531   xmm_md_mode,
 532   /* XMM register or quad word memory operand */
 533   xmm_mq_mode,
 534   /* XMM register or double/quad word memory operand, depending on
 535      VEX.W.  */
 536   xmm_mdq_mode,
 537   /* 16-byte XMM, word, double word or quad word operand.  */
 538   xmmdw_mode,
 539   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 540   xmmqd_mode,
 541   /* 32-byte YMM operand */
 542   ymm_mode,
 543   /* quad word, ymmword or zmmword memory operand.  */
 544   ymmq_mode,
 545   /* 32-byte YMM or 16-byte word operand */
 546   ymmxmm_mode,
 547   /* d_mode in 32bit, q_mode in 64bit mode.  */
 548   m_mode,
 549   /* pair of v_mode operands */
 550   a_mode,
 551   cond_jump_mode,
 552   loop_jcxz_mode,
 553   v_bnd_mode,
 554   /* operand size depends on REX prefixes.  */
 555   dq_mode,
 556   /* registers like dq_mode, memory like w_mode.  */
 557   dqw_mode,
 558   dqw_swap_mode,
 559   bnd_mode,
 560   /* 4- or 6-byte pointer operand */
 561   f_mode,
 562   const_1_mode,
 563   /* v_mode for stack-related opcodes.  */
 564   stack_v_mode,
 565   /* non-quad operand size depends on prefixes */
 566   z_mode,
 567   /* 16-byte operand */
 568   o_mode,
 569   /* registers like dq_mode, memory like b_mode.  */
 570   dqb_mode,
 571   /* registers like d_mode, memory like b_mode.  */
 572   db_mode,
 573   /* registers like d_mode, memory like w_mode.  */
 574   dw_mode,
 575   /* registers like dq_mode, memory like d_mode.  */
 576   dqd_mode,
 577   /* normal vex mode */
 578   vex_mode,
 579   /* 128bit vex mode */
 580   vex128_mode,
 581   /* 256bit vex mode */
 582   vex256_mode,
 583   /* operand size depends on the VEX.W bit.  */
 584   vex_w_dq_mode,
 585
 586   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 587   vex_vsib_d_w_dq_mode,
 588   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 589   vex_vsib_d_w_d_mode,
 590   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 591   vex_vsib_q_w_dq_mode,
 592   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 593   vex_vsib_q_w_d_mode,
 594
 595   /* scalar, ignore vector length.  */
 596   scalar_mode,
 597   /* like d_mode, ignore vector length.  */
 598   d_scalar_mode,
 599   /* like d_swap_mode, ignore vector length.  */
 600   d_scalar_swap_mode,
 601   /* like q_mode, ignore vector length.  */
 602   q_scalar_mode,
 603   /* like q_swap_mode, ignore vector length.  */
 604   q_scalar_swap_mode,
 605   /* like vex_mode, ignore vector length.  */
 606   vex_scalar_mode,
 607   /* like vex_w_dq_mode, ignore vector length.  */
 608   vex_scalar_w_dq_mode,
 609
 610   /* Static rounding.  */
 611   evex_rounding_mode,
 612   /* Supress all exceptions.  */
 613   evex_sae_mode,
 614
 615   /* Mask register operand.  */
 616   mask_mode,
 617   /* Mask register operand.  */
 618   mask_bd_mode,
 619
 620   es_reg,
 621   cs_reg,
 622   ss_reg,
 623   ds_reg,
 624   fs_reg,
 625   gs_reg,
 626
 627   eAX_reg,
 628   eCX_reg,
 629   eDX_reg,
 630   eBX_reg,
 631   eSP_reg,
 632   eBP_reg,
 633   eSI_reg,
 634   eDI_reg,
 635
 636   al_reg,
 637   cl_reg,
 638   dl_reg,
 639   bl_reg,
 640   ah_reg,
 641   ch_reg,
 642   dh_reg,
 643   bh_reg,
 644
 645   ax_reg,
 646   cx_reg,
 647   dx_reg,
 648   bx_reg,
 649   sp_reg,
 650   bp_reg,
 651   si_reg,
 652   di_reg,
 653
 654   rAX_reg,
 655   rCX_reg,
 656   rDX_reg,
 657   rBX_reg,
 658   rSP_reg,
 659   rBP_reg,
 660   rSI_reg,
 661   rDI_reg,
 662
 663   z_mode_ax_reg,
 664   indir_dx_reg
 665 };
 666
 667 enum
 668 {
 669   FLOATCODE = 1,
 670   USE_REG_TABLE,
 671   USE_MOD_TABLE,
 672   USE_RM_TABLE,
 673   USE_PREFIX_TABLE,
 674   USE_X86_64_TABLE,
 675   USE_3BYTE_TABLE,
 676   USE_XOP_8F_TABLE,
 677   USE_VEX_C4_TABLE,
 678   USE_VEX_C5_TABLE,
 679   USE_VEX_LEN_TABLE,
 680   USE_VEX_W_TABLE,
 681   USE_EVEX_TABLE
 682 };
 683
 684 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 685
 686 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 687 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 688 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 689 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 690 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 691 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 692 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 693 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 694 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 695 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 696 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 697 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 698 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 699 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 700 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 701
 702 enum
 703 {
 704   REG_80 = 0,
 705   REG_81,
 706   REG_82,
 707   REG_8F,
 708   REG_C0,
 709   REG_C1,
 710   REG_C6,
 711   REG_C7,
 712   REG_D0,
 713   REG_D1,
 714   REG_D2,
 715   REG_D3,
 716   REG_F6,
 717   REG_F7,
 718   REG_FE,
 719   REG_FF,
 720   REG_0F00,
 721   REG_0F01,
 722   REG_0F0D,
 723   REG_0F18,
 724   REG_0F71,
 725   REG_0F72,
 726   REG_0F73,
 727   REG_0FA6,
 728   REG_0FA7,
 729   REG_0FAE,
 730   REG_0FBA,
 731   REG_0FC7,
 732   REG_VEX_0F71,
 733   REG_VEX_0F72,
 734   REG_VEX_0F73,
 735   REG_VEX_0FAE,
 736   REG_VEX_0F38F3,
 737   REG_XOP_LWPCB,
 738   REG_XOP_LWP,
 739   REG_XOP_TBM_01,
 740   REG_XOP_TBM_02,
 741
 742   REG_EVEX_0F71,
 743   REG_EVEX_0F72,
 744   REG_EVEX_0F73,
 745   REG_EVEX_0F38C6,
 746   REG_EVEX_0F38C7
 747 };
 748
 749 enum
 750 {
 751   MOD_8D = 0,
 752   MOD_C6_REG_7,
 753   MOD_C7_REG_7,
 754   MOD_FF_REG_3,
 755   MOD_FF_REG_5,
 756   MOD_0F01_REG_0,
 757   MOD_0F01_REG_1,
 758   MOD_0F01_REG_2,
 759   MOD_0F01_REG_3,
 760   MOD_0F01_REG_7,
 761   MOD_0F12_PREFIX_0,
 762   MOD_0F13,
 763   MOD_0F16_PREFIX_0,
 764   MOD_0F17,
 765   MOD_0F18_REG_0,
 766   MOD_0F18_REG_1,
 767   MOD_0F18_REG_2,
 768   MOD_0F18_REG_3,
 769   MOD_0F18_REG_4,
 770   MOD_0F18_REG_5,
 771   MOD_0F18_REG_6,
 772   MOD_0F18_REG_7,
 773   MOD_0F1A_PREFIX_0,
 774   MOD_0F1B_PREFIX_0,
 775   MOD_0F1B_PREFIX_1,
 776   MOD_0F24,
 777   MOD_0F26,
 778   MOD_0F2B_PREFIX_0,
 779   MOD_0F2B_PREFIX_1,
 780   MOD_0F2B_PREFIX_2,
 781   MOD_0F2B_PREFIX_3,
 782   MOD_0F51,
 783   MOD_0F71_REG_2,
 784   MOD_0F71_REG_4,
 785   MOD_0F71_REG_6,
 786   MOD_0F72_REG_2,
 787   MOD_0F72_REG_4,
 788   MOD_0F72_REG_6,
 789   MOD_0F73_REG_2,
 790   MOD_0F73_REG_3,
 791   MOD_0F73_REG_6,
 792   MOD_0F73_REG_7,
 793   MOD_0FAE_REG_0,
 794   MOD_0FAE_REG_1,
 795   MOD_0FAE_REG_2,
 796   MOD_0FAE_REG_3,
 797   MOD_0FAE_REG_4,
 798   MOD_0FAE_REG_5,
 799   MOD_0FAE_REG_6,
 800   MOD_0FAE_REG_7,
 801   MOD_0FB2,
 802   MOD_0FB4,
 803   MOD_0FB5,
 804   MOD_0FC7_REG_3,
 805   MOD_0FC7_REG_4,
 806   MOD_0FC7_REG_5,
 807   MOD_0FC7_REG_6,
 808   MOD_0FC7_REG_7,
 809   MOD_0FD7,
 810   MOD_0FE7_PREFIX_2,
 811   MOD_0FF0_PREFIX_3,
 812   MOD_0F382A_PREFIX_2,
 813   MOD_62_32BIT,
 814   MOD_C4_32BIT,
 815   MOD_C5_32BIT,
 816   MOD_VEX_0F12_PREFIX_0,
 817   MOD_VEX_0F13,
 818   MOD_VEX_0F16_PREFIX_0,
 819   MOD_VEX_0F17,
 820   MOD_VEX_0F2B,
 821   MOD_VEX_0F50,
 822   MOD_VEX_0F71_REG_2,
 823   MOD_VEX_0F71_REG_4,
 824   MOD_VEX_0F71_REG_6,
 825   MOD_VEX_0F72_REG_2,
 826   MOD_VEX_0F72_REG_4,
 827   MOD_VEX_0F72_REG_6,
 828   MOD_VEX_0F73_REG_2,
 829   MOD_VEX_0F73_REG_3,
 830   MOD_VEX_0F73_REG_6,
 831   MOD_VEX_0F73_REG_7,
 832   MOD_VEX_0FAE_REG_2,
 833   MOD_VEX_0FAE_REG_3,
 834   MOD_VEX_0FD7_PREFIX_2,
 835   MOD_VEX_0FE7_PREFIX_2,
 836   MOD_VEX_0FF0_PREFIX_3,
 837   MOD_VEX_0F381A_PREFIX_2,
 838   MOD_VEX_0F382A_PREFIX_2,
 839   MOD_VEX_0F382C_PREFIX_2,
 840   MOD_VEX_0F382D_PREFIX_2,
 841   MOD_VEX_0F382E_PREFIX_2,
 842   MOD_VEX_0F382F_PREFIX_2,
 843   MOD_VEX_0F385A_PREFIX_2,
 844   MOD_VEX_0F388C_PREFIX_2,
 845   MOD_VEX_0F388E_PREFIX_2,
 846
 847   MOD_EVEX_0F10_PREFIX_1,
 848   MOD_EVEX_0F10_PREFIX_3,
 849   MOD_EVEX_0F11_PREFIX_1,
 850   MOD_EVEX_0F11_PREFIX_3,
 851   MOD_EVEX_0F12_PREFIX_0,
 852   MOD_EVEX_0F16_PREFIX_0,
 853   MOD_EVEX_0F38C6_REG_1,
 854   MOD_EVEX_0F38C6_REG_2,
 855   MOD_EVEX_0F38C6_REG_5,
 856   MOD_EVEX_0F38C6_REG_6,
 857   MOD_EVEX_0F38C7_REG_1,
 858   MOD_EVEX_0F38C7_REG_2,
 859   MOD_EVEX_0F38C7_REG_5,
 860   MOD_EVEX_0F38C7_REG_6
 861 };
 862
 863 enum
 864 {
 865   RM_C6_REG_7 = 0,
 866   RM_C7_REG_7,
 867   RM_0F01_REG_0,
 868   RM_0F01_REG_1,
 869   RM_0F01_REG_2,
 870   RM_0F01_REG_3,
 871   RM_0F01_REG_7,
 872   RM_0FAE_REG_5,
 873   RM_0FAE_REG_6,
 874   RM_0FAE_REG_7
 875 };
 876
 877 enum
 878 {
 879   PREFIX_90 = 0,
 880   PREFIX_0F10,
 881   PREFIX_0F11,
 882   PREFIX_0F12,
 883   PREFIX_0F16,
 884   PREFIX_0F1A,
 885   PREFIX_0F1B,
 886   PREFIX_0F2A,
 887   PREFIX_0F2B,
 888   PREFIX_0F2C,
 889   PREFIX_0F2D,
 890   PREFIX_0F2E,
 891   PREFIX_0F2F,
 892   PREFIX_0F51,
 893   PREFIX_0F52,
 894   PREFIX_0F53,
 895   PREFIX_0F58,
 896   PREFIX_0F59,
 897   PREFIX_0F5A,
 898   PREFIX_0F5B,
 899   PREFIX_0F5C,
 900   PREFIX_0F5D,
 901   PREFIX_0F5E,
 902   PREFIX_0F5F,
 903   PREFIX_0F60,
 904   PREFIX_0F61,
 905   PREFIX_0F62,
 906   PREFIX_0F6C,
 907   PREFIX_0F6D,
 908   PREFIX_0F6F,
 909   PREFIX_0F70,
 910   PREFIX_0F73_REG_3,
 911   PREFIX_0F73_REG_7,
 912   PREFIX_0F78,
 913   PREFIX_0F79,
 914   PREFIX_0F7C,
 915   PREFIX_0F7D,
 916   PREFIX_0F7E,
 917   PREFIX_0F7F,
 918   PREFIX_0FAE_REG_0,
 919   PREFIX_0FAE_REG_1,
 920   PREFIX_0FAE_REG_2,
 921   PREFIX_0FAE_REG_3,
 922   PREFIX_0FAE_REG_6,
 923   PREFIX_0FAE_REG_7,
 924   PREFIX_RM_0_0FAE_REG_7,
 925   PREFIX_0FB8,
 926   PREFIX_0FBC,
 927   PREFIX_0FBD,
 928   PREFIX_0FC2,
 929   PREFIX_0FC3,
 930   PREFIX_MOD_0_0FC7_REG_6,
 931   PREFIX_MOD_3_0FC7_REG_6,
 932   PREFIX_MOD_3_0FC7_REG_7,
 933   PREFIX_0FD0,
 934   PREFIX_0FD6,
 935   PREFIX_0FE6,
 936   PREFIX_0FE7,
 937   PREFIX_0FF0,
 938   PREFIX_0FF7,
 939   PREFIX_0F3810,
 940   PREFIX_0F3814,
 941   PREFIX_0F3815,
 942   PREFIX_0F3817,
 943   PREFIX_0F3820,
 944   PREFIX_0F3821,
 945   PREFIX_0F3822,
 946   PREFIX_0F3823,
 947   PREFIX_0F3824,
 948   PREFIX_0F3825,
 949   PREFIX_0F3828,
 950   PREFIX_0F3829,
 951   PREFIX_0F382A,
 952   PREFIX_0F382B,
 953   PREFIX_0F3830,
 954   PREFIX_0F3831,
 955   PREFIX_0F3832,
 956   PREFIX_0F3833,
 957   PREFIX_0F3834,
 958   PREFIX_0F3835,
 959   PREFIX_0F3837,
 960   PREFIX_0F3838,
 961   PREFIX_0F3839,
 962   PREFIX_0F383A,
 963   PREFIX_0F383B,
 964   PREFIX_0F383C,
 965   PREFIX_0F383D,
 966   PREFIX_0F383E,
 967   PREFIX_0F383F,
 968   PREFIX_0F3840,
 969   PREFIX_0F3841,
 970   PREFIX_0F3880,
 971   PREFIX_0F3881,
 972   PREFIX_0F3882,
 973   PREFIX_0F38C8,
 974   PREFIX_0F38C9,
 975   PREFIX_0F38CA,
 976   PREFIX_0F38CB,
 977   PREFIX_0F38CC,
 978   PREFIX_0F38CD,
 979   PREFIX_0F38DB,
 980   PREFIX_0F38DC,
 981   PREFIX_0F38DD,
 982   PREFIX_0F38DE,
 983   PREFIX_0F38DF,
 984   PREFIX_0F38F0,
 985   PREFIX_0F38F1,
 986   PREFIX_0F38F6,
 987   PREFIX_0F3A08,
 988   PREFIX_0F3A09,
 989   PREFIX_0F3A0A,
 990   PREFIX_0F3A0B,
 991   PREFIX_0F3A0C,
 992   PREFIX_0F3A0D,
 993   PREFIX_0F3A0E,
 994   PREFIX_0F3A14,
 995   PREFIX_0F3A15,
 996   PREFIX_0F3A16,
 997   PREFIX_0F3A17,
 998   PREFIX_0F3A20,
 999   PREFIX_0F3A21,
1000   PREFIX_0F3A22,
1001   PREFIX_0F3A40,
1002   PREFIX_0F3A41,
1003   PREFIX_0F3A42,
1004   PREFIX_0F3A44,
1005   PREFIX_0F3A60,
1006   PREFIX_0F3A61,
1007   PREFIX_0F3A62,
1008   PREFIX_0F3A63,
1009   PREFIX_0F3ACC,
1010   PREFIX_0F3ADF,
1011   PREFIX_VEX_0F10,
1012   PREFIX_VEX_0F11,
1013   PREFIX_VEX_0F12,
1014   PREFIX_VEX_0F16,
1015   PREFIX_VEX_0F2A,
1016   PREFIX_VEX_0F2C,
1017   PREFIX_VEX_0F2D,
1018   PREFIX_VEX_0F2E,
1019   PREFIX_VEX_0F2F,
1020   PREFIX_VEX_0F41,
1021   PREFIX_VEX_0F42,
1022   PREFIX_VEX_0F44,
1023   PREFIX_VEX_0F45,
1024   PREFIX_VEX_0F46,
1025   PREFIX_VEX_0F47,
1026   PREFIX_VEX_0F4A,
1027   PREFIX_VEX_0F4B,
1028   PREFIX_VEX_0F51,
1029   PREFIX_VEX_0F52,
1030   PREFIX_VEX_0F53,
1031   PREFIX_VEX_0F58,
1032   PREFIX_VEX_0F59,
1033   PREFIX_VEX_0F5A,
1034   PREFIX_VEX_0F5B,
1035   PREFIX_VEX_0F5C,
1036   PREFIX_VEX_0F5D,
1037   PREFIX_VEX_0F5E,
1038   PREFIX_VEX_0F5F,
1039   PREFIX_VEX_0F60,
1040   PREFIX_VEX_0F61,
1041   PREFIX_VEX_0F62,
1042   PREFIX_VEX_0F63,
1043   PREFIX_VEX_0F64,
1044   PREFIX_VEX_0F65,
1045   PREFIX_VEX_0F66,
1046   PREFIX_VEX_0F67,
1047   PREFIX_VEX_0F68,
1048   PREFIX_VEX_0F69,
1049   PREFIX_VEX_0F6A,
1050   PREFIX_VEX_0F6B,
1051   PREFIX_VEX_0F6C,
1052   PREFIX_VEX_0F6D,
1053   PREFIX_VEX_0F6E,
1054   PREFIX_VEX_0F6F,
1055   PREFIX_VEX_0F70,
1056   PREFIX_VEX_0F71_REG_2,
1057   PREFIX_VEX_0F71_REG_4,
1058   PREFIX_VEX_0F71_REG_6,
1059   PREFIX_VEX_0F72_REG_2,
1060   PREFIX_VEX_0F72_REG_4,
1061   PREFIX_VEX_0F72_REG_6,
1062   PREFIX_VEX_0F73_REG_2,
1063   PREFIX_VEX_0F73_REG_3,
1064   PREFIX_VEX_0F73_REG_6,
1065   PREFIX_VEX_0F73_REG_7,
1066   PREFIX_VEX_0F74,
1067   PREFIX_VEX_0F75,
1068   PREFIX_VEX_0F76,
1069   PREFIX_VEX_0F77,
1070   PREFIX_VEX_0F7C,
1071   PREFIX_VEX_0F7D,
1072   PREFIX_VEX_0F7E,
1073   PREFIX_VEX_0F7F,
1074   PREFIX_VEX_0F90,
1075   PREFIX_VEX_0F91,
1076   PREFIX_VEX_0F92,
1077   PREFIX_VEX_0F93,
1078   PREFIX_VEX_0F98,
1079   PREFIX_VEX_0F99,
1080   PREFIX_VEX_0FC2,
1081   PREFIX_VEX_0FC4,
1082   PREFIX_VEX_0FC5,
1083   PREFIX_VEX_0FD0,
1084   PREFIX_VEX_0FD1,
1085   PREFIX_VEX_0FD2,
1086   PREFIX_VEX_0FD3,
1087   PREFIX_VEX_0FD4,
1088   PREFIX_VEX_0FD5,
1089   PREFIX_VEX_0FD6,
1090   PREFIX_VEX_0FD7,
1091   PREFIX_VEX_0FD8,
1092   PREFIX_VEX_0FD9,
1093   PREFIX_VEX_0FDA,
1094   PREFIX_VEX_0FDB,
1095   PREFIX_VEX_0FDC,
1096   PREFIX_VEX_0FDD,
1097   PREFIX_VEX_0FDE,
1098   PREFIX_VEX_0FDF,
1099   PREFIX_VEX_0FE0,
1100   PREFIX_VEX_0FE1,
1101   PREFIX_VEX_0FE2,
1102   PREFIX_VEX_0FE3,
1103   PREFIX_VEX_0FE4,
1104   PREFIX_VEX_0FE5,
1105   PREFIX_VEX_0FE6,
1106   PREFIX_VEX_0FE7,
1107   PREFIX_VEX_0FE8,
1108   PREFIX_VEX_0FE9,
1109   PREFIX_VEX_0FEA,
1110   PREFIX_VEX_0FEB,
1111   PREFIX_VEX_0FEC,
1112   PREFIX_VEX_0FED,
1113   PREFIX_VEX_0FEE,
1114   PREFIX_VEX_0FEF,
1115   PREFIX_VEX_0FF0,
1116   PREFIX_VEX_0FF1,
1117   PREFIX_VEX_0FF2,
1118   PREFIX_VEX_0FF3,
1119   PREFIX_VEX_0FF4,
1120   PREFIX_VEX_0FF5,
1121   PREFIX_VEX_0FF6,
1122   PREFIX_VEX_0FF7,
1123   PREFIX_VEX_0FF8,
1124   PREFIX_VEX_0FF9,
1125   PREFIX_VEX_0FFA,
1126   PREFIX_VEX_0FFB,
1127   PREFIX_VEX_0FFC,
1128   PREFIX_VEX_0FFD,
1129   PREFIX_VEX_0FFE,
1130   PREFIX_VEX_0F3800,
1131   PREFIX_VEX_0F3801,
1132   PREFIX_VEX_0F3802,
1133   PREFIX_VEX_0F3803,
1134   PREFIX_VEX_0F3804,
1135   PREFIX_VEX_0F3805,
1136   PREFIX_VEX_0F3806,
1137   PREFIX_VEX_0F3807,
1138   PREFIX_VEX_0F3808,
1139   PREFIX_VEX_0F3809,
1140   PREFIX_VEX_0F380A,
1141   PREFIX_VEX_0F380B,
1142   PREFIX_VEX_0F380C,
1143   PREFIX_VEX_0F380D,
1144   PREFIX_VEX_0F380E,
1145   PREFIX_VEX_0F380F,
1146   PREFIX_VEX_0F3813,
1147   PREFIX_VEX_0F3816,
1148   PREFIX_VEX_0F3817,
1149   PREFIX_VEX_0F3818,
1150   PREFIX_VEX_0F3819,
1151   PREFIX_VEX_0F381A,
1152   PREFIX_VEX_0F381C,
1153   PREFIX_VEX_0F381D,
1154   PREFIX_VEX_0F381E,
1155   PREFIX_VEX_0F3820,
1156   PREFIX_VEX_0F3821,
1157   PREFIX_VEX_0F3822,
1158   PREFIX_VEX_0F3823,
1159   PREFIX_VEX_0F3824,
1160   PREFIX_VEX_0F3825,
1161   PREFIX_VEX_0F3828,
1162   PREFIX_VEX_0F3829,
1163   PREFIX_VEX_0F382A,
1164   PREFIX_VEX_0F382B,
1165   PREFIX_VEX_0F382C,
1166   PREFIX_VEX_0F382D,
1167   PREFIX_VEX_0F382E,
1168   PREFIX_VEX_0F382F,
1169   PREFIX_VEX_0F3830,
1170   PREFIX_VEX_0F3831,
1171   PREFIX_VEX_0F3832,
1172   PREFIX_VEX_0F3833,
1173   PREFIX_VEX_0F3834,
1174   PREFIX_VEX_0F3835,
1175   PREFIX_VEX_0F3836,
1176   PREFIX_VEX_0F3837,
1177   PREFIX_VEX_0F3838,
1178   PREFIX_VEX_0F3839,
1179   PREFIX_VEX_0F383A,
1180   PREFIX_VEX_0F383B,
1181   PREFIX_VEX_0F383C,
1182   PREFIX_VEX_0F383D,
1183   PREFIX_VEX_0F383E,
1184   PREFIX_VEX_0F383F,
1185   PREFIX_VEX_0F3840,
1186   PREFIX_VEX_0F3841,
1187   PREFIX_VEX_0F3845,
1188   PREFIX_VEX_0F3846,
1189   PREFIX_VEX_0F3847,
1190   PREFIX_VEX_0F3858,
1191   PREFIX_VEX_0F3859,
1192   PREFIX_VEX_0F385A,
1193   PREFIX_VEX_0F3878,
1194   PREFIX_VEX_0F3879,
1195   PREFIX_VEX_0F388C,
1196   PREFIX_VEX_0F388E,
1197   PREFIX_VEX_0F3890,
1198   PREFIX_VEX_0F3891,
1199   PREFIX_VEX_0F3892,
1200   PREFIX_VEX_0F3893,
1201   PREFIX_VEX_0F3896,
1202   PREFIX_VEX_0F3897,
1203   PREFIX_VEX_0F3898,
1204   PREFIX_VEX_0F3899,
1205   PREFIX_VEX_0F389A,
1206   PREFIX_VEX_0F389B,
1207   PREFIX_VEX_0F389C,
1208   PREFIX_VEX_0F389D,
1209   PREFIX_VEX_0F389E,
1210   PREFIX_VEX_0F389F,
1211   PREFIX_VEX_0F38A6,
1212   PREFIX_VEX_0F38A7,
1213   PREFIX_VEX_0F38A8,
1214   PREFIX_VEX_0F38A9,
1215   PREFIX_VEX_0F38AA,
1216   PREFIX_VEX_0F38AB,
1217   PREFIX_VEX_0F38AC,
1218   PREFIX_VEX_0F38AD,
1219   PREFIX_VEX_0F38AE,
1220   PREFIX_VEX_0F38AF,
1221   PREFIX_VEX_0F38B6,
1222   PREFIX_VEX_0F38B7,
1223   PREFIX_VEX_0F38B8,
1224   PREFIX_VEX_0F38B9,
1225   PREFIX_VEX_0F38BA,
1226   PREFIX_VEX_0F38BB,
1227   PREFIX_VEX_0F38BC,
1228   PREFIX_VEX_0F38BD,
1229   PREFIX_VEX_0F38BE,
1230   PREFIX_VEX_0F38BF,
1231   PREFIX_VEX_0F38DB,
1232   PREFIX_VEX_0F38DC,
1233   PREFIX_VEX_0F38DD,
1234   PREFIX_VEX_0F38DE,
1235   PREFIX_VEX_0F38DF,
1236   PREFIX_VEX_0F38F2,
1237   PREFIX_VEX_0F38F3_REG_1,
1238   PREFIX_VEX_0F38F3_REG_2,
1239   PREFIX_VEX_0F38F3_REG_3,
1240   PREFIX_VEX_0F38F5,
1241   PREFIX_VEX_0F38F6,
1242   PREFIX_VEX_0F38F7,
1243   PREFIX_VEX_0F3A00,
1244   PREFIX_VEX_0F3A01,
1245   PREFIX_VEX_0F3A02,
1246   PREFIX_VEX_0F3A04,
1247   PREFIX_VEX_0F3A05,
1248   PREFIX_VEX_0F3A06,
1249   PREFIX_VEX_0F3A08,
1250   PREFIX_VEX_0F3A09,
1251   PREFIX_VEX_0F3A0A,
1252   PREFIX_VEX_0F3A0B,
1253   PREFIX_VEX_0F3A0C,
1254   PREFIX_VEX_0F3A0D,
1255   PREFIX_VEX_0F3A0E,
1256   PREFIX_VEX_0F3A0F,
1257   PREFIX_VEX_0F3A14,
1258   PREFIX_VEX_0F3A15,
1259   PREFIX_VEX_0F3A16,
1260   PREFIX_VEX_0F3A17,
1261   PREFIX_VEX_0F3A18,
1262   PREFIX_VEX_0F3A19,
1263   PREFIX_VEX_0F3A1D,
1264   PREFIX_VEX_0F3A20,
1265   PREFIX_VEX_0F3A21,
1266   PREFIX_VEX_0F3A22,
1267   PREFIX_VEX_0F3A30,
1268   PREFIX_VEX_0F3A31,
1269   PREFIX_VEX_0F3A32,
1270   PREFIX_VEX_0F3A33,
1271   PREFIX_VEX_0F3A38,
1272   PREFIX_VEX_0F3A39,
1273   PREFIX_VEX_0F3A40,
1274   PREFIX_VEX_0F3A41,
1275   PREFIX_VEX_0F3A42,
1276   PREFIX_VEX_0F3A44,
1277   PREFIX_VEX_0F3A46,
1278   PREFIX_VEX_0F3A48,
1279   PREFIX_VEX_0F3A49,
1280   PREFIX_VEX_0F3A4A,
1281   PREFIX_VEX_0F3A4B,
1282   PREFIX_VEX_0F3A4C,
1283   PREFIX_VEX_0F3A5C,
1284   PREFIX_VEX_0F3A5D,
1285   PREFIX_VEX_0F3A5E,
1286   PREFIX_VEX_0F3A5F,
1287   PREFIX_VEX_0F3A60,
1288   PREFIX_VEX_0F3A61,
1289   PREFIX_VEX_0F3A62,
1290   PREFIX_VEX_0F3A63,
1291   PREFIX_VEX_0F3A68,
1292   PREFIX_VEX_0F3A69,
1293   PREFIX_VEX_0F3A6A,
1294   PREFIX_VEX_0F3A6B,
1295   PREFIX_VEX_0F3A6C,
1296   PREFIX_VEX_0F3A6D,
1297   PREFIX_VEX_0F3A6E,
1298   PREFIX_VEX_0F3A6F,
1299   PREFIX_VEX_0F3A78,
1300   PREFIX_VEX_0F3A79,
1301   PREFIX_VEX_0F3A7A,
1302   PREFIX_VEX_0F3A7B,
1303   PREFIX_VEX_0F3A7C,
1304   PREFIX_VEX_0F3A7D,
1305   PREFIX_VEX_0F3A7E,
1306   PREFIX_VEX_0F3A7F,
1307   PREFIX_VEX_0F3ADF,
1308   PREFIX_VEX_0F3AF0,
1309
1310   PREFIX_EVEX_0F10,
1311   PREFIX_EVEX_0F11,
1312   PREFIX_EVEX_0F12,
1313   PREFIX_EVEX_0F13,
1314   PREFIX_EVEX_0F14,
1315   PREFIX_EVEX_0F15,
1316   PREFIX_EVEX_0F16,
1317   PREFIX_EVEX_0F17,
1318   PREFIX_EVEX_0F28,
1319   PREFIX_EVEX_0F29,
1320   PREFIX_EVEX_0F2A,
1321   PREFIX_EVEX_0F2B,
1322   PREFIX_EVEX_0F2C,
1323   PREFIX_EVEX_0F2D,
1324   PREFIX_EVEX_0F2E,
1325   PREFIX_EVEX_0F2F,
1326   PREFIX_EVEX_0F51,
1327   PREFIX_EVEX_0F54,
1328   PREFIX_EVEX_0F55,
1329   PREFIX_EVEX_0F56,
1330   PREFIX_EVEX_0F57,
1331   PREFIX_EVEX_0F58,
1332   PREFIX_EVEX_0F59,
1333   PREFIX_EVEX_0F5A,
1334   PREFIX_EVEX_0F5B,
1335   PREFIX_EVEX_0F5C,
1336   PREFIX_EVEX_0F5D,
1337   PREFIX_EVEX_0F5E,
1338   PREFIX_EVEX_0F5F,
1339   PREFIX_EVEX_0F60,
1340   PREFIX_EVEX_0F61,
1341   PREFIX_EVEX_0F62,
1342   PREFIX_EVEX_0F63,
1343   PREFIX_EVEX_0F64,
1344   PREFIX_EVEX_0F65,
1345   PREFIX_EVEX_0F66,
1346   PREFIX_EVEX_0F67,
1347   PREFIX_EVEX_0F68,
1348   PREFIX_EVEX_0F69,
1349   PREFIX_EVEX_0F6A,
1350   PREFIX_EVEX_0F6B,
1351   PREFIX_EVEX_0F6C,
1352   PREFIX_EVEX_0F6D,
1353   PREFIX_EVEX_0F6E,
1354   PREFIX_EVEX_0F6F,
1355   PREFIX_EVEX_0F70,
1356   PREFIX_EVEX_0F71_REG_2,
1357   PREFIX_EVEX_0F71_REG_4,
1358   PREFIX_EVEX_0F71_REG_6,
1359   PREFIX_EVEX_0F72_REG_0,
1360   PREFIX_EVEX_0F72_REG_1,
1361   PREFIX_EVEX_0F72_REG_2,
1362   PREFIX_EVEX_0F72_REG_4,
1363   PREFIX_EVEX_0F72_REG_6,
1364   PREFIX_EVEX_0F73_REG_2,
1365   PREFIX_EVEX_0F73_REG_3,
1366   PREFIX_EVEX_0F73_REG_6,
1367   PREFIX_EVEX_0F73_REG_7,
1368   PREFIX_EVEX_0F74,
1369   PREFIX_EVEX_0F75,
1370   PREFIX_EVEX_0F76,
1371   PREFIX_EVEX_0F78,
1372   PREFIX_EVEX_0F79,
1373   PREFIX_EVEX_0F7A,
1374   PREFIX_EVEX_0F7B,
1375   PREFIX_EVEX_0F7E,
1376   PREFIX_EVEX_0F7F,
1377   PREFIX_EVEX_0FC2,
1378   PREFIX_EVEX_0FC4,
1379   PREFIX_EVEX_0FC5,
1380   PREFIX_EVEX_0FC6,
1381   PREFIX_EVEX_0FD1,
1382   PREFIX_EVEX_0FD2,
1383   PREFIX_EVEX_0FD3,
1384   PREFIX_EVEX_0FD4,
1385   PREFIX_EVEX_0FD5,
1386   PREFIX_EVEX_0FD6,
1387   PREFIX_EVEX_0FD8,
1388   PREFIX_EVEX_0FD9,
1389   PREFIX_EVEX_0FDA,
1390   PREFIX_EVEX_0FDB,
1391   PREFIX_EVEX_0FDC,
1392   PREFIX_EVEX_0FDD,
1393   PREFIX_EVEX_0FDE,
1394   PREFIX_EVEX_0FDF,
1395   PREFIX_EVEX_0FE0,
1396   PREFIX_EVEX_0FE1,
1397   PREFIX_EVEX_0FE2,
1398   PREFIX_EVEX_0FE3,
1399   PREFIX_EVEX_0FE4,
1400   PREFIX_EVEX_0FE5,
1401   PREFIX_EVEX_0FE6,
1402   PREFIX_EVEX_0FE7,
1403   PREFIX_EVEX_0FE8,
1404   PREFIX_EVEX_0FE9,
1405   PREFIX_EVEX_0FEA,
1406   PREFIX_EVEX_0FEB,
1407   PREFIX_EVEX_0FEC,
1408   PREFIX_EVEX_0FED,
1409   PREFIX_EVEX_0FEE,
1410   PREFIX_EVEX_0FEF,
1411   PREFIX_EVEX_0FF1,
1412   PREFIX_EVEX_0FF2,
1413   PREFIX_EVEX_0FF3,
1414   PREFIX_EVEX_0FF4,
1415   PREFIX_EVEX_0FF5,
1416   PREFIX_EVEX_0FF6,
1417   PREFIX_EVEX_0FF8,
1418   PREFIX_EVEX_0FF9,
1419   PREFIX_EVEX_0FFA,
1420   PREFIX_EVEX_0FFB,
1421   PREFIX_EVEX_0FFC,
1422   PREFIX_EVEX_0FFD,
1423   PREFIX_EVEX_0FFE,
1424   PREFIX_EVEX_0F3800,
1425   PREFIX_EVEX_0F3804,
1426   PREFIX_EVEX_0F380B,
1427   PREFIX_EVEX_0F380C,
1428   PREFIX_EVEX_0F380D,
1429   PREFIX_EVEX_0F3810,
1430   PREFIX_EVEX_0F3811,
1431   PREFIX_EVEX_0F3812,
1432   PREFIX_EVEX_0F3813,
1433   PREFIX_EVEX_0F3814,
1434   PREFIX_EVEX_0F3815,
1435   PREFIX_EVEX_0F3816,
1436   PREFIX_EVEX_0F3818,
1437   PREFIX_EVEX_0F3819,
1438   PREFIX_EVEX_0F381A,
1439   PREFIX_EVEX_0F381B,
1440   PREFIX_EVEX_0F381C,
1441   PREFIX_EVEX_0F381D,
1442   PREFIX_EVEX_0F381E,
1443   PREFIX_EVEX_0F381F,
1444   PREFIX_EVEX_0F3820,
1445   PREFIX_EVEX_0F3821,
1446   PREFIX_EVEX_0F3822,
1447   PREFIX_EVEX_0F3823,
1448   PREFIX_EVEX_0F3824,
1449   PREFIX_EVEX_0F3825,
1450   PREFIX_EVEX_0F3826,
1451   PREFIX_EVEX_0F3827,
1452   PREFIX_EVEX_0F3828,
1453   PREFIX_EVEX_0F3829,
1454   PREFIX_EVEX_0F382A,
1455   PREFIX_EVEX_0F382B,
1456   PREFIX_EVEX_0F382C,
1457   PREFIX_EVEX_0F382D,
1458   PREFIX_EVEX_0F3830,
1459   PREFIX_EVEX_0F3831,
1460   PREFIX_EVEX_0F3832,
1461   PREFIX_EVEX_0F3833,
1462   PREFIX_EVEX_0F3834,
1463   PREFIX_EVEX_0F3835,
1464   PREFIX_EVEX_0F3836,
1465   PREFIX_EVEX_0F3837,
1466   PREFIX_EVEX_0F3838,
1467   PREFIX_EVEX_0F3839,
1468   PREFIX_EVEX_0F383A,
1469   PREFIX_EVEX_0F383B,
1470   PREFIX_EVEX_0F383C,
1471   PREFIX_EVEX_0F383D,
1472   PREFIX_EVEX_0F383E,
1473   PREFIX_EVEX_0F383F,
1474   PREFIX_EVEX_0F3840,
1475   PREFIX_EVEX_0F3842,
1476   PREFIX_EVEX_0F3843,
1477   PREFIX_EVEX_0F3844,
1478   PREFIX_EVEX_0F3845,
1479   PREFIX_EVEX_0F3846,
1480   PREFIX_EVEX_0F3847,
1481   PREFIX_EVEX_0F384C,
1482   PREFIX_EVEX_0F384D,
1483   PREFIX_EVEX_0F384E,
1484   PREFIX_EVEX_0F384F,
1485   PREFIX_EVEX_0F3858,
1486   PREFIX_EVEX_0F3859,
1487   PREFIX_EVEX_0F385A,
1488   PREFIX_EVEX_0F385B,
1489   PREFIX_EVEX_0F3864,
1490   PREFIX_EVEX_0F3865,
1491   PREFIX_EVEX_0F3866,
1492   PREFIX_EVEX_0F3875,
1493   PREFIX_EVEX_0F3876,
1494   PREFIX_EVEX_0F3877,
1495   PREFIX_EVEX_0F3878,
1496   PREFIX_EVEX_0F3879,
1497   PREFIX_EVEX_0F387A,
1498   PREFIX_EVEX_0F387B,
1499   PREFIX_EVEX_0F387C,
1500   PREFIX_EVEX_0F387D,
1501   PREFIX_EVEX_0F387E,
1502   PREFIX_EVEX_0F387F,
1503   PREFIX_EVEX_0F3883,
1504   PREFIX_EVEX_0F3888,
1505   PREFIX_EVEX_0F3889,
1506   PREFIX_EVEX_0F388A,
1507   PREFIX_EVEX_0F388B,
1508   PREFIX_EVEX_0F388D,
1509   PREFIX_EVEX_0F3890,
1510   PREFIX_EVEX_0F3891,
1511   PREFIX_EVEX_0F3892,
1512   PREFIX_EVEX_0F3893,
1513   PREFIX_EVEX_0F3896,
1514   PREFIX_EVEX_0F3897,
1515   PREFIX_EVEX_0F3898,
1516   PREFIX_EVEX_0F3899,
1517   PREFIX_EVEX_0F389A,
1518   PREFIX_EVEX_0F389B,
1519   PREFIX_EVEX_0F389C,
1520   PREFIX_EVEX_0F389D,
1521   PREFIX_EVEX_0F389E,
1522   PREFIX_EVEX_0F389F,
1523   PREFIX_EVEX_0F38A0,
1524   PREFIX_EVEX_0F38A1,
1525   PREFIX_EVEX_0F38A2,
1526   PREFIX_EVEX_0F38A3,
1527   PREFIX_EVEX_0F38A6,
1528   PREFIX_EVEX_0F38A7,
1529   PREFIX_EVEX_0F38A8,
1530   PREFIX_EVEX_0F38A9,
1531   PREFIX_EVEX_0F38AA,
1532   PREFIX_EVEX_0F38AB,
1533   PREFIX_EVEX_0F38AC,
1534   PREFIX_EVEX_0F38AD,
1535   PREFIX_EVEX_0F38AE,
1536   PREFIX_EVEX_0F38AF,
1537   PREFIX_EVEX_0F38B4,
1538   PREFIX_EVEX_0F38B5,
1539   PREFIX_EVEX_0F38B6,
1540   PREFIX_EVEX_0F38B7,
1541   PREFIX_EVEX_0F38B8,
1542   PREFIX_EVEX_0F38B9,
1543   PREFIX_EVEX_0F38BA,
1544   PREFIX_EVEX_0F38BB,
1545   PREFIX_EVEX_0F38BC,
1546   PREFIX_EVEX_0F38BD,
1547   PREFIX_EVEX_0F38BE,
1548   PREFIX_EVEX_0F38BF,
1549   PREFIX_EVEX_0F38C4,
1550   PREFIX_EVEX_0F38C6_REG_1,
1551   PREFIX_EVEX_0F38C6_REG_2,
1552   PREFIX_EVEX_0F38C6_REG_5,
1553   PREFIX_EVEX_0F38C6_REG_6,
1554   PREFIX_EVEX_0F38C7_REG_1,
1555   PREFIX_EVEX_0F38C7_REG_2,
1556   PREFIX_EVEX_0F38C7_REG_5,
1557   PREFIX_EVEX_0F38C7_REG_6,
1558   PREFIX_EVEX_0F38C8,
1559   PREFIX_EVEX_0F38CA,
1560   PREFIX_EVEX_0F38CB,
1561   PREFIX_EVEX_0F38CC,
1562   PREFIX_EVEX_0F38CD,
1563
1564   PREFIX_EVEX_0F3A00,
1565   PREFIX_EVEX_0F3A01,
1566   PREFIX_EVEX_0F3A03,
1567   PREFIX_EVEX_0F3A04,
1568   PREFIX_EVEX_0F3A05,
1569   PREFIX_EVEX_0F3A08,
1570   PREFIX_EVEX_0F3A09,
1571   PREFIX_EVEX_0F3A0A,
1572   PREFIX_EVEX_0F3A0B,
1573   PREFIX_EVEX_0F3A0F,
1574   PREFIX_EVEX_0F3A14,
1575   PREFIX_EVEX_0F3A15,
1576   PREFIX_EVEX_0F3A16,
1577   PREFIX_EVEX_0F3A17,
1578   PREFIX_EVEX_0F3A18,
1579   PREFIX_EVEX_0F3A19,
1580   PREFIX_EVEX_0F3A1A,
1581   PREFIX_EVEX_0F3A1B,
1582   PREFIX_EVEX_0F3A1D,
1583   PREFIX_EVEX_0F3A1E,
1584   PREFIX_EVEX_0F3A1F,
1585   PREFIX_EVEX_0F3A20,
1586   PREFIX_EVEX_0F3A21,
1587   PREFIX_EVEX_0F3A22,
1588   PREFIX_EVEX_0F3A23,
1589   PREFIX_EVEX_0F3A25,
1590   PREFIX_EVEX_0F3A26,
1591   PREFIX_EVEX_0F3A27,
1592   PREFIX_EVEX_0F3A38,
1593   PREFIX_EVEX_0F3A39,
1594   PREFIX_EVEX_0F3A3A,
1595   PREFIX_EVEX_0F3A3B,
1596   PREFIX_EVEX_0F3A3E,
1597   PREFIX_EVEX_0F3A3F,
1598   PREFIX_EVEX_0F3A42,
1599   PREFIX_EVEX_0F3A43,
1600   PREFIX_EVEX_0F3A50,
1601   PREFIX_EVEX_0F3A51,
1602   PREFIX_EVEX_0F3A54,
1603   PREFIX_EVEX_0F3A55,
1604   PREFIX_EVEX_0F3A56,
1605   PREFIX_EVEX_0F3A57,
1606   PREFIX_EVEX_0F3A66,
1607   PREFIX_EVEX_0F3A67
1608 };
1609
1610 enum
1611 {
1612   X86_64_06 = 0,
1613   X86_64_07,
1614   X86_64_0D,
1615   X86_64_16,
1616   X86_64_17,
1617   X86_64_1E,
1618   X86_64_1F,
1619   X86_64_27,
1620   X86_64_2F,
1621   X86_64_37,
1622   X86_64_3F,
1623   X86_64_60,
1624   X86_64_61,
1625   X86_64_62,
1626   X86_64_63,
1627   X86_64_6D,
1628   X86_64_6F,
1629   X86_64_9A,
1630   X86_64_C4,
1631   X86_64_C5,
1632   X86_64_CE,
1633   X86_64_D4,
1634   X86_64_D5,
1635   X86_64_EA,
1636   X86_64_0F01_REG_0,
1637   X86_64_0F01_REG_1,
1638   X86_64_0F01_REG_2,
1639   X86_64_0F01_REG_3
1640 };
1641
1642 enum
1643 {
1644   THREE_BYTE_0F38 = 0,
1645   THREE_BYTE_0F3A,
1646   THREE_BYTE_0F7A
1647 };
1648
1649 enum
1650 {
1651   XOP_08 = 0,
1652   XOP_09,
1653   XOP_0A
1654 };
1655
1656 enum
1657 {
1658   VEX_0F = 0,
1659   VEX_0F38,
1660   VEX_0F3A
1661 };
1662
1663 enum
1664 {
1665   EVEX_0F = 0,
1666   EVEX_0F38,
1667   EVEX_0F3A
1668 };
1669
1670 enum
1671 {
1672   VEX_LEN_0F10_P_1 = 0,
1673   VEX_LEN_0F10_P_3,
1674   VEX_LEN_0F11_P_1,
1675   VEX_LEN_0F11_P_3,
1676   VEX_LEN_0F12_P_0_M_0,
1677   VEX_LEN_0F12_P_0_M_1,
1678   VEX_LEN_0F12_P_2,
1679   VEX_LEN_0F13_M_0,
1680   VEX_LEN_0F16_P_0_M_0,
1681   VEX_LEN_0F16_P_0_M_1,
1682   VEX_LEN_0F16_P_2,
1683   VEX_LEN_0F17_M_0,
1684   VEX_LEN_0F2A_P_1,
1685   VEX_LEN_0F2A_P_3,
1686   VEX_LEN_0F2C_P_1,
1687   VEX_LEN_0F2C_P_3,
1688   VEX_LEN_0F2D_P_1,
1689   VEX_LEN_0F2D_P_3,
1690   VEX_LEN_0F2E_P_0,
1691   VEX_LEN_0F2E_P_2,
1692   VEX_LEN_0F2F_P_0,
1693   VEX_LEN_0F2F_P_2,
1694   VEX_LEN_0F41_P_0,
1695   VEX_LEN_0F41_P_2,
1696   VEX_LEN_0F42_P_0,
1697   VEX_LEN_0F42_P_2,
1698   VEX_LEN_0F44_P_0,
1699   VEX_LEN_0F44_P_2,
1700   VEX_LEN_0F45_P_0,
1701   VEX_LEN_0F45_P_2,
1702   VEX_LEN_0F46_P_0,
1703   VEX_LEN_0F46_P_2,
1704   VEX_LEN_0F47_P_0,
1705   VEX_LEN_0F47_P_2,
1706   VEX_LEN_0F4A_P_0,
1707   VEX_LEN_0F4A_P_2,
1708   VEX_LEN_0F4B_P_0,
1709   VEX_LEN_0F4B_P_2,
1710   VEX_LEN_0F51_P_1,
1711   VEX_LEN_0F51_P_3,
1712   VEX_LEN_0F52_P_1,
1713   VEX_LEN_0F53_P_1,
1714   VEX_LEN_0F58_P_1,
1715   VEX_LEN_0F58_P_3,
1716   VEX_LEN_0F59_P_1,
1717   VEX_LEN_0F59_P_3,
1718   VEX_LEN_0F5A_P_1,
1719   VEX_LEN_0F5A_P_3,
1720   VEX_LEN_0F5C_P_1,
1721   VEX_LEN_0F5C_P_3,
1722   VEX_LEN_0F5D_P_1,
1723   VEX_LEN_0F5D_P_3,
1724   VEX_LEN_0F5E_P_1,
1725   VEX_LEN_0F5E_P_3,
1726   VEX_LEN_0F5F_P_1,
1727   VEX_LEN_0F5F_P_3,
1728   VEX_LEN_0F6E_P_2,
1729   VEX_LEN_0F7E_P_1,
1730   VEX_LEN_0F7E_P_2,
1731   VEX_LEN_0F90_P_0,
1732   VEX_LEN_0F90_P_2,
1733   VEX_LEN_0F91_P_0,
1734   VEX_LEN_0F91_P_2,
1735   VEX_LEN_0F92_P_0,
1736   VEX_LEN_0F92_P_2,
1737   VEX_LEN_0F92_P_3,
1738   VEX_LEN_0F93_P_0,
1739   VEX_LEN_0F93_P_2,
1740   VEX_LEN_0F93_P_3,
1741   VEX_LEN_0F98_P_0,
1742   VEX_LEN_0F98_P_2,
1743   VEX_LEN_0F99_P_0,
1744   VEX_LEN_0F99_P_2,
1745   VEX_LEN_0FAE_R_2_M_0,
1746   VEX_LEN_0FAE_R_3_M_0,
1747   VEX_LEN_0FC2_P_1,
1748   VEX_LEN_0FC2_P_3,
1749   VEX_LEN_0FC4_P_2,
1750   VEX_LEN_0FC5_P_2,
1751   VEX_LEN_0FD6_P_2,
1752   VEX_LEN_0FF7_P_2,
1753   VEX_LEN_0F3816_P_2,
1754   VEX_LEN_0F3819_P_2,
1755   VEX_LEN_0F381A_P_2_M_0,
1756   VEX_LEN_0F3836_P_2,
1757   VEX_LEN_0F3841_P_2,
1758   VEX_LEN_0F385A_P_2_M_0,
1759   VEX_LEN_0F38DB_P_2,
1760   VEX_LEN_0F38DC_P_2,
1761   VEX_LEN_0F38DD_P_2,
1762   VEX_LEN_0F38DE_P_2,
1763   VEX_LEN_0F38DF_P_2,
1764   VEX_LEN_0F38F2_P_0,
1765   VEX_LEN_0F38F3_R_1_P_0,
1766   VEX_LEN_0F38F3_R_2_P_0,
1767   VEX_LEN_0F38F3_R_3_P_0,
1768   VEX_LEN_0F38F5_P_0,
1769   VEX_LEN_0F38F5_P_1,
1770   VEX_LEN_0F38F5_P_3,
1771   VEX_LEN_0F38F6_P_3,
1772   VEX_LEN_0F38F7_P_0,
1773   VEX_LEN_0F38F7_P_1,
1774   VEX_LEN_0F38F7_P_2,
1775   VEX_LEN_0F38F7_P_3,
1776   VEX_LEN_0F3A00_P_2,
1777   VEX_LEN_0F3A01_P_2,
1778   VEX_LEN_0F3A06_P_2,
1779   VEX_LEN_0F3A0A_P_2,
1780   VEX_LEN_0F3A0B_P_2,
1781   VEX_LEN_0F3A14_P_2,
1782   VEX_LEN_0F3A15_P_2,
1783   VEX_LEN_0F3A16_P_2,
1784   VEX_LEN_0F3A17_P_2,
1785   VEX_LEN_0F3A18_P_2,
1786   VEX_LEN_0F3A19_P_2,
1787   VEX_LEN_0F3A20_P_2,
1788   VEX_LEN_0F3A21_P_2,
1789   VEX_LEN_0F3A22_P_2,
1790   VEX_LEN_0F3A30_P_2,
1791   VEX_LEN_0F3A31_P_2,
1792   VEX_LEN_0F3A32_P_2,
1793   VEX_LEN_0F3A33_P_2,
1794   VEX_LEN_0F3A38_P_2,
1795   VEX_LEN_0F3A39_P_2,
1796   VEX_LEN_0F3A41_P_2,
1797   VEX_LEN_0F3A44_P_2,
1798   VEX_LEN_0F3A46_P_2,
1799   VEX_LEN_0F3A60_P_2,
1800   VEX_LEN_0F3A61_P_2,
1801   VEX_LEN_0F3A62_P_2,
1802   VEX_LEN_0F3A63_P_2,
1803   VEX_LEN_0F3A6A_P_2,
1804   VEX_LEN_0F3A6B_P_2,
1805   VEX_LEN_0F3A6E_P_2,
1806   VEX_LEN_0F3A6F_P_2,
1807   VEX_LEN_0F3A7A_P_2,
1808   VEX_LEN_0F3A7B_P_2,
1809   VEX_LEN_0F3A7E_P_2,
1810   VEX_LEN_0F3A7F_P_2,
1811   VEX_LEN_0F3ADF_P_2,
1812   VEX_LEN_0F3AF0_P_3,
1813   VEX_LEN_0FXOP_08_CC,
1814   VEX_LEN_0FXOP_08_CD,
1815   VEX_LEN_0FXOP_08_CE,
1816   VEX_LEN_0FXOP_08_CF,
1817   VEX_LEN_0FXOP_08_EC,
1818   VEX_LEN_0FXOP_08_ED,
1819   VEX_LEN_0FXOP_08_EE,
1820   VEX_LEN_0FXOP_08_EF,
1821   VEX_LEN_0FXOP_09_80,
1822   VEX_LEN_0FXOP_09_81
1823 };
1824
1825 enum
1826 {
1827   VEX_W_0F10_P_0 = 0,
1828   VEX_W_0F10_P_1,
1829   VEX_W_0F10_P_2,
1830   VEX_W_0F10_P_3,
1831   VEX_W_0F11_P_0,
1832   VEX_W_0F11_P_1,
1833   VEX_W_0F11_P_2,
1834   VEX_W_0F11_P_3,
1835   VEX_W_0F12_P_0_M_0,
1836   VEX_W_0F12_P_0_M_1,
1837   VEX_W_0F12_P_1,
1838   VEX_W_0F12_P_2,
1839   VEX_W_0F12_P_3,
1840   VEX_W_0F13_M_0,
1841   VEX_W_0F14,
1842   VEX_W_0F15,
1843   VEX_W_0F16_P_0_M_0,
1844   VEX_W_0F16_P_0_M_1,
1845   VEX_W_0F16_P_1,
1846   VEX_W_0F16_P_2,
1847   VEX_W_0F17_M_0,
1848   VEX_W_0F28,
1849   VEX_W_0F29,
1850   VEX_W_0F2B_M_0,
1851   VEX_W_0F2E_P_0,
1852   VEX_W_0F2E_P_2,
1853   VEX_W_0F2F_P_0,
1854   VEX_W_0F2F_P_2,
1855   VEX_W_0F41_P_0_LEN_1,
1856   VEX_W_0F41_P_2_LEN_1,
1857   VEX_W_0F42_P_0_LEN_1,
1858   VEX_W_0F42_P_2_LEN_1,
1859   VEX_W_0F44_P_0_LEN_0,
1860   VEX_W_0F44_P_2_LEN_0,
1861   VEX_W_0F45_P_0_LEN_1,
1862   VEX_W_0F45_P_2_LEN_1,
1863   VEX_W_0F46_P_0_LEN_1,
1864   VEX_W_0F46_P_2_LEN_1,
1865   VEX_W_0F47_P_0_LEN_1,
1866   VEX_W_0F47_P_2_LEN_1,
1867   VEX_W_0F4A_P_0_LEN_1,
1868   VEX_W_0F4A_P_2_LEN_1,
1869   VEX_W_0F4B_P_0_LEN_1,
1870   VEX_W_0F4B_P_2_LEN_1,
1871   VEX_W_0F50_M_0,
1872   VEX_W_0F51_P_0,
1873   VEX_W_0F51_P_1,
1874   VEX_W_0F51_P_2,
1875   VEX_W_0F51_P_3,
1876   VEX_W_0F52_P_0,
1877   VEX_W_0F52_P_1,
1878   VEX_W_0F53_P_0,
1879   VEX_W_0F53_P_1,
1880   VEX_W_0F58_P_0,
1881   VEX_W_0F58_P_1,
1882   VEX_W_0F58_P_2,
1883   VEX_W_0F58_P_3,
1884   VEX_W_0F59_P_0,
1885   VEX_W_0F59_P_1,
1886   VEX_W_0F59_P_2,
1887   VEX_W_0F59_P_3,
1888   VEX_W_0F5A_P_0,
1889   VEX_W_0F5A_P_1,
1890   VEX_W_0F5A_P_3,
1891   VEX_W_0F5B_P_0,
1892   VEX_W_0F5B_P_1,
1893   VEX_W_0F5B_P_2,
1894   VEX_W_0F5C_P_0,
1895   VEX_W_0F5C_P_1,
1896   VEX_W_0F5C_P_2,
1897   VEX_W_0F5C_P_3,
1898   VEX_W_0F5D_P_0,
1899   VEX_W_0F5D_P_1,
1900   VEX_W_0F5D_P_2,
1901   VEX_W_0F5D_P_3,
1902   VEX_W_0F5E_P_0,
1903   VEX_W_0F5E_P_1,
1904   VEX_W_0F5E_P_2,
1905   VEX_W_0F5E_P_3,
1906   VEX_W_0F5F_P_0,
1907   VEX_W_0F5F_P_1,
1908   VEX_W_0F5F_P_2,
1909   VEX_W_0F5F_P_3,
1910   VEX_W_0F60_P_2,
1911   VEX_W_0F61_P_2,
1912   VEX_W_0F62_P_2,
1913   VEX_W_0F63_P_2,
1914   VEX_W_0F64_P_2,
1915   VEX_W_0F65_P_2,
1916   VEX_W_0F66_P_2,
1917   VEX_W_0F67_P_2,
1918   VEX_W_0F68_P_2,
1919   VEX_W_0F69_P_2,
1920   VEX_W_0F6A_P_2,
1921   VEX_W_0F6B_P_2,
1922   VEX_W_0F6C_P_2,
1923   VEX_W_0F6D_P_2,
1924   VEX_W_0F6F_P_1,
1925   VEX_W_0F6F_P_2,
1926   VEX_W_0F70_P_1,
1927   VEX_W_0F70_P_2,
1928   VEX_W_0F70_P_3,
1929   VEX_W_0F71_R_2_P_2,
1930   VEX_W_0F71_R_4_P_2,
1931   VEX_W_0F71_R_6_P_2,
1932   VEX_W_0F72_R_2_P_2,
1933   VEX_W_0F72_R_4_P_2,
1934   VEX_W_0F72_R_6_P_2,
1935   VEX_W_0F73_R_2_P_2,
1936   VEX_W_0F73_R_3_P_2,
1937   VEX_W_0F73_R_6_P_2,
1938   VEX_W_0F73_R_7_P_2,
1939   VEX_W_0F74_P_2,
1940   VEX_W_0F75_P_2,
1941   VEX_W_0F76_P_2,
1942   VEX_W_0F77_P_0,
1943   VEX_W_0F7C_P_2,
1944   VEX_W_0F7C_P_3,
1945   VEX_W_0F7D_P_2,
1946   VEX_W_0F7D_P_3,
1947   VEX_W_0F7E_P_1,
1948   VEX_W_0F7F_P_1,
1949   VEX_W_0F7F_P_2,
1950   VEX_W_0F90_P_0_LEN_0,
1951   VEX_W_0F90_P_2_LEN_0,
1952   VEX_W_0F91_P_0_LEN_0,
1953   VEX_W_0F91_P_2_LEN_0,
1954   VEX_W_0F92_P_0_LEN_0,
1955   VEX_W_0F92_P_2_LEN_0,
1956   VEX_W_0F92_P_3_LEN_0,
1957   VEX_W_0F93_P_0_LEN_0,
1958   VEX_W_0F93_P_2_LEN_0,
1959   VEX_W_0F93_P_3_LEN_0,
1960   VEX_W_0F98_P_0_LEN_0,
1961   VEX_W_0F98_P_2_LEN_0,
1962   VEX_W_0F99_P_0_LEN_0,
1963   VEX_W_0F99_P_2_LEN_0,
1964   VEX_W_0FAE_R_2_M_0,
1965   VEX_W_0FAE_R_3_M_0,
1966   VEX_W_0FC2_P_0,
1967   VEX_W_0FC2_P_1,
1968   VEX_W_0FC2_P_2,
1969   VEX_W_0FC2_P_3,
1970   VEX_W_0FC4_P_2,
1971   VEX_W_0FC5_P_2,
1972   VEX_W_0FD0_P_2,
1973   VEX_W_0FD0_P_3,
1974   VEX_W_0FD1_P_2,
1975   VEX_W_0FD2_P_2,
1976   VEX_W_0FD3_P_2,
1977   VEX_W_0FD4_P_2,
1978   VEX_W_0FD5_P_2,
1979   VEX_W_0FD6_P_2,
1980   VEX_W_0FD7_P_2_M_1,
1981   VEX_W_0FD8_P_2,
1982   VEX_W_0FD9_P_2,
1983   VEX_W_0FDA_P_2,
1984   VEX_W_0FDB_P_2,
1985   VEX_W_0FDC_P_2,
1986   VEX_W_0FDD_P_2,
1987   VEX_W_0FDE_P_2,
1988   VEX_W_0FDF_P_2,
1989   VEX_W_0FE0_P_2,
1990   VEX_W_0FE1_P_2,
1991   VEX_W_0FE2_P_2,
1992   VEX_W_0FE3_P_2,
1993   VEX_W_0FE4_P_2,
1994   VEX_W_0FE5_P_2,
1995   VEX_W_0FE6_P_1,
1996   VEX_W_0FE6_P_2,
1997   VEX_W_0FE6_P_3,
1998   VEX_W_0FE7_P_2_M_0,
1999   VEX_W_0FE8_P_2,
2000   VEX_W_0FE9_P_2,
2001   VEX_W_0FEA_P_2,
2002   VEX_W_0FEB_P_2,
2003   VEX_W_0FEC_P_2,
2004   VEX_W_0FED_P_2,
2005   VEX_W_0FEE_P_2,
2006   VEX_W_0FEF_P_2,
2007   VEX_W_0FF0_P_3_M_0,
2008   VEX_W_0FF1_P_2,
2009   VEX_W_0FF2_P_2,
2010   VEX_W_0FF3_P_2,
2011   VEX_W_0FF4_P_2,
2012   VEX_W_0FF5_P_2,
2013   VEX_W_0FF6_P_2,
2014   VEX_W_0FF7_P_2,
2015   VEX_W_0FF8_P_2,
2016   VEX_W_0FF9_P_2,
2017   VEX_W_0FFA_P_2,
2018   VEX_W_0FFB_P_2,
2019   VEX_W_0FFC_P_2,
2020   VEX_W_0FFD_P_2,
2021   VEX_W_0FFE_P_2,
2022   VEX_W_0F3800_P_2,
2023   VEX_W_0F3801_P_2,
2024   VEX_W_0F3802_P_2,
2025   VEX_W_0F3803_P_2,
2026   VEX_W_0F3804_P_2,
2027   VEX_W_0F3805_P_2,
2028   VEX_W_0F3806_P_2,
2029   VEX_W_0F3807_P_2,
2030   VEX_W_0F3808_P_2,
2031   VEX_W_0F3809_P_2,
2032   VEX_W_0F380A_P_2,
2033   VEX_W_0F380B_P_2,
2034   VEX_W_0F380C_P_2,
2035   VEX_W_0F380D_P_2,
2036   VEX_W_0F380E_P_2,
2037   VEX_W_0F380F_P_2,
2038   VEX_W_0F3816_P_2,
2039   VEX_W_0F3817_P_2,
2040   VEX_W_0F3818_P_2,
2041   VEX_W_0F3819_P_2,
2042   VEX_W_0F381A_P_2_M_0,
2043   VEX_W_0F381C_P_2,
2044   VEX_W_0F381D_P_2,
2045   VEX_W_0F381E_P_2,
2046   VEX_W_0F3820_P_2,
2047   VEX_W_0F3821_P_2,
2048   VEX_W_0F3822_P_2,
2049   VEX_W_0F3823_P_2,
2050   VEX_W_0F3824_P_2,
2051   VEX_W_0F3825_P_2,
2052   VEX_W_0F3828_P_2,
2053   VEX_W_0F3829_P_2,
2054   VEX_W_0F382A_P_2_M_0,
2055   VEX_W_0F382B_P_2,
2056   VEX_W_0F382C_P_2_M_0,
2057   VEX_W_0F382D_P_2_M_0,
2058   VEX_W_0F382E_P_2_M_0,
2059   VEX_W_0F382F_P_2_M_0,
2060   VEX_W_0F3830_P_2,
2061   VEX_W_0F3831_P_2,
2062   VEX_W_0F3832_P_2,
2063   VEX_W_0F3833_P_2,
2064   VEX_W_0F3834_P_2,
2065   VEX_W_0F3835_P_2,
2066   VEX_W_0F3836_P_2,
2067   VEX_W_0F3837_P_2,
2068   VEX_W_0F3838_P_2,
2069   VEX_W_0F3839_P_2,
2070   VEX_W_0F383A_P_2,
2071   VEX_W_0F383B_P_2,
2072   VEX_W_0F383C_P_2,
2073   VEX_W_0F383D_P_2,
2074   VEX_W_0F383E_P_2,
2075   VEX_W_0F383F_P_2,
2076   VEX_W_0F3840_P_2,
2077   VEX_W_0F3841_P_2,
2078   VEX_W_0F3846_P_2,
2079   VEX_W_0F3858_P_2,
2080   VEX_W_0F3859_P_2,
2081   VEX_W_0F385A_P_2_M_0,
2082   VEX_W_0F3878_P_2,
2083   VEX_W_0F3879_P_2,
2084   VEX_W_0F38DB_P_2,
2085   VEX_W_0F38DC_P_2,
2086   VEX_W_0F38DD_P_2,
2087   VEX_W_0F38DE_P_2,
2088   VEX_W_0F38DF_P_2,
2089   VEX_W_0F3A00_P_2,
2090   VEX_W_0F3A01_P_2,
2091   VEX_W_0F3A02_P_2,
2092   VEX_W_0F3A04_P_2,
2093   VEX_W_0F3A05_P_2,
2094   VEX_W_0F3A06_P_2,
2095   VEX_W_0F3A08_P_2,
2096   VEX_W_0F3A09_P_2,
2097   VEX_W_0F3A0A_P_2,
2098   VEX_W_0F3A0B_P_2,
2099   VEX_W_0F3A0C_P_2,
2100   VEX_W_0F3A0D_P_2,
2101   VEX_W_0F3A0E_P_2,
2102   VEX_W_0F3A0F_P_2,
2103   VEX_W_0F3A14_P_2,
2104   VEX_W_0F3A15_P_2,
2105   VEX_W_0F3A18_P_2,
2106   VEX_W_0F3A19_P_2,
2107   VEX_W_0F3A20_P_2,
2108   VEX_W_0F3A21_P_2,
2109   VEX_W_0F3A30_P_2_LEN_0,
2110   VEX_W_0F3A31_P_2_LEN_0,
2111   VEX_W_0F3A32_P_2_LEN_0,
2112   VEX_W_0F3A33_P_2_LEN_0,
2113   VEX_W_0F3A38_P_2,
2114   VEX_W_0F3A39_P_2,
2115   VEX_W_0F3A40_P_2,
2116   VEX_W_0F3A41_P_2,
2117   VEX_W_0F3A42_P_2,
2118   VEX_W_0F3A44_P_2,
2119   VEX_W_0F3A46_P_2,
2120   VEX_W_0F3A48_P_2,
2121   VEX_W_0F3A49_P_2,
2122   VEX_W_0F3A4A_P_2,
2123   VEX_W_0F3A4B_P_2,
2124   VEX_W_0F3A4C_P_2,
2125   VEX_W_0F3A60_P_2,
2126   VEX_W_0F3A61_P_2,
2127   VEX_W_0F3A62_P_2,
2128   VEX_W_0F3A63_P_2,
2129   VEX_W_0F3ADF_P_2,
2130
2131   EVEX_W_0F10_P_0,
2132   EVEX_W_0F10_P_1_M_0,
2133   EVEX_W_0F10_P_1_M_1,
2134   EVEX_W_0F10_P_2,
2135   EVEX_W_0F10_P_3_M_0,
2136   EVEX_W_0F10_P_3_M_1,
2137   EVEX_W_0F11_P_0,
2138   EVEX_W_0F11_P_1_M_0,
2139   EVEX_W_0F11_P_1_M_1,
2140   EVEX_W_0F11_P_2,
2141   EVEX_W_0F11_P_3_M_0,
2142   EVEX_W_0F11_P_3_M_1,
2143   EVEX_W_0F12_P_0_M_0,
2144   EVEX_W_0F12_P_0_M_1,
2145   EVEX_W_0F12_P_1,
2146   EVEX_W_0F12_P_2,
2147   EVEX_W_0F12_P_3,
2148   EVEX_W_0F13_P_0,
2149   EVEX_W_0F13_P_2,
2150   EVEX_W_0F14_P_0,
2151   EVEX_W_0F14_P_2,
2152   EVEX_W_0F15_P_0,
2153   EVEX_W_0F15_P_2,
2154   EVEX_W_0F16_P_0_M_0,
2155   EVEX_W_0F16_P_0_M_1,
2156   EVEX_W_0F16_P_1,
2157   EVEX_W_0F16_P_2,
2158   EVEX_W_0F17_P_0,
2159   EVEX_W_0F17_P_2,
2160   EVEX_W_0F28_P_0,
2161   EVEX_W_0F28_P_2,
2162   EVEX_W_0F29_P_0,
2163   EVEX_W_0F29_P_2,
2164   EVEX_W_0F2A_P_1,
2165   EVEX_W_0F2A_P_3,
2166   EVEX_W_0F2B_P_0,
2167   EVEX_W_0F2B_P_2,
2168   EVEX_W_0F2E_P_0,
2169   EVEX_W_0F2E_P_2,
2170   EVEX_W_0F2F_P_0,
2171   EVEX_W_0F2F_P_2,
2172   EVEX_W_0F51_P_0,
2173   EVEX_W_0F51_P_1,
2174   EVEX_W_0F51_P_2,
2175   EVEX_W_0F51_P_3,
2176   EVEX_W_0F54_P_0,
2177   EVEX_W_0F54_P_2,
2178   EVEX_W_0F55_P_0,
2179   EVEX_W_0F55_P_2,
2180   EVEX_W_0F56_P_0,
2181   EVEX_W_0F56_P_2,
2182   EVEX_W_0F57_P_0,
2183   EVEX_W_0F57_P_2,
2184   EVEX_W_0F58_P_0,
2185   EVEX_W_0F58_P_1,
2186   EVEX_W_0F58_P_2,
2187   EVEX_W_0F58_P_3,
2188   EVEX_W_0F59_P_0,
2189   EVEX_W_0F59_P_1,
2190   EVEX_W_0F59_P_2,
2191   EVEX_W_0F59_P_3,
2192   EVEX_W_0F5A_P_0,
2193   EVEX_W_0F5A_P_1,
2194   EVEX_W_0F5A_P_2,
2195   EVEX_W_0F5A_P_3,
2196   EVEX_W_0F5B_P_0,
2197   EVEX_W_0F5B_P_1,
2198   EVEX_W_0F5B_P_2,
2199   EVEX_W_0F5C_P_0,
2200   EVEX_W_0F5C_P_1,
2201   EVEX_W_0F5C_P_2,
2202   EVEX_W_0F5C_P_3,
2203   EVEX_W_0F5D_P_0,
2204   EVEX_W_0F5D_P_1,
2205   EVEX_W_0F5D_P_2,
2206   EVEX_W_0F5D_P_3,
2207   EVEX_W_0F5E_P_0,
2208   EVEX_W_0F5E_P_1,
2209   EVEX_W_0F5E_P_2,
2210   EVEX_W_0F5E_P_3,
2211   EVEX_W_0F5F_P_0,
2212   EVEX_W_0F5F_P_1,
2213   EVEX_W_0F5F_P_2,
2214   EVEX_W_0F5F_P_3,
2215   EVEX_W_0F62_P_2,
2216   EVEX_W_0F66_P_2,
2217   EVEX_W_0F6A_P_2,
2218   EVEX_W_0F6B_P_2,
2219   EVEX_W_0F6C_P_2,
2220   EVEX_W_0F6D_P_2,
2221   EVEX_W_0F6E_P_2,
2222   EVEX_W_0F6F_P_1,
2223   EVEX_W_0F6F_P_2,
2224   EVEX_W_0F6F_P_3,
2225   EVEX_W_0F70_P_2,
2226   EVEX_W_0F72_R_2_P_2,
2227   EVEX_W_0F72_R_6_P_2,
2228   EVEX_W_0F73_R_2_P_2,
2229   EVEX_W_0F73_R_6_P_2,
2230   EVEX_W_0F76_P_2,
2231   EVEX_W_0F78_P_0,
2232   EVEX_W_0F78_P_2,
2233   EVEX_W_0F79_P_0,
2234   EVEX_W_0F79_P_2,
2235   EVEX_W_0F7A_P_1,
2236   EVEX_W_0F7A_P_2,
2237   EVEX_W_0F7A_P_3,
2238   EVEX_W_0F7B_P_1,
2239   EVEX_W_0F7B_P_2,
2240   EVEX_W_0F7B_P_3,
2241   EVEX_W_0F7E_P_1,
2242   EVEX_W_0F7E_P_2,
2243   EVEX_W_0F7F_P_1,
2244   EVEX_W_0F7F_P_2,
2245   EVEX_W_0F7F_P_3,
2246   EVEX_W_0FC2_P_0,
2247   EVEX_W_0FC2_P_1,
2248   EVEX_W_0FC2_P_2,
2249   EVEX_W_0FC2_P_3,
2250   EVEX_W_0FC6_P_0,
2251   EVEX_W_0FC6_P_2,
2252   EVEX_W_0FD2_P_2,
2253   EVEX_W_0FD3_P_2,
2254   EVEX_W_0FD4_P_2,
2255   EVEX_W_0FD6_P_2,
2256   EVEX_W_0FE6_P_1,
2257   EVEX_W_0FE6_P_2,
2258   EVEX_W_0FE6_P_3,
2259   EVEX_W_0FE7_P_2,
2260   EVEX_W_0FF2_P_2,
2261   EVEX_W_0FF3_P_2,
2262   EVEX_W_0FF4_P_2,
2263   EVEX_W_0FFA_P_2,
2264   EVEX_W_0FFB_P_2,
2265   EVEX_W_0FFE_P_2,
2266   EVEX_W_0F380C_P_2,
2267   EVEX_W_0F380D_P_2,
2268   EVEX_W_0F3810_P_1,
2269   EVEX_W_0F3810_P_2,
2270   EVEX_W_0F3811_P_1,
2271   EVEX_W_0F3811_P_2,
2272   EVEX_W_0F3812_P_1,
2273   EVEX_W_0F3812_P_2,
2274   EVEX_W_0F3813_P_1,
2275   EVEX_W_0F3813_P_2,
2276   EVEX_W_0F3814_P_1,
2277   EVEX_W_0F3815_P_1,
2278   EVEX_W_0F3818_P_2,
2279   EVEX_W_0F3819_P_2,
2280   EVEX_W_0F381A_P_2,
2281   EVEX_W_0F381B_P_2,
2282   EVEX_W_0F381E_P_2,
2283   EVEX_W_0F381F_P_2,
2284   EVEX_W_0F3820_P_1,
2285   EVEX_W_0F3821_P_1,
2286   EVEX_W_0F3822_P_1,
2287   EVEX_W_0F3823_P_1,
2288   EVEX_W_0F3824_P_1,
2289   EVEX_W_0F3825_P_1,
2290   EVEX_W_0F3825_P_2,
2291   EVEX_W_0F3826_P_1,
2292   EVEX_W_0F3826_P_2,
2293   EVEX_W_0F3828_P_1,
2294   EVEX_W_0F3828_P_2,
2295   EVEX_W_0F3829_P_1,
2296   EVEX_W_0F3829_P_2,
2297   EVEX_W_0F382A_P_1,
2298   EVEX_W_0F382A_P_2,
2299   EVEX_W_0F382B_P_2,
2300   EVEX_W_0F3830_P_1,
2301   EVEX_W_0F3831_P_1,
2302   EVEX_W_0F3832_P_1,
2303   EVEX_W_0F3833_P_1,
2304   EVEX_W_0F3834_P_1,
2305   EVEX_W_0F3835_P_1,
2306   EVEX_W_0F3835_P_2,
2307   EVEX_W_0F3837_P_2,
2308   EVEX_W_0F3838_P_1,
2309   EVEX_W_0F3839_P_1,
2310   EVEX_W_0F383A_P_1,
2311   EVEX_W_0F3840_P_2,
2312   EVEX_W_0F3858_P_2,
2313   EVEX_W_0F3859_P_2,
2314   EVEX_W_0F385A_P_2,
2315   EVEX_W_0F385B_P_2,
2316   EVEX_W_0F3866_P_2,
2317   EVEX_W_0F3875_P_2,
2318   EVEX_W_0F3878_P_2,
2319   EVEX_W_0F3879_P_2,
2320   EVEX_W_0F387A_P_2,
2321   EVEX_W_0F387B_P_2,
2322   EVEX_W_0F387D_P_2,
2323   EVEX_W_0F3883_P_2,
2324   EVEX_W_0F388D_P_2,
2325   EVEX_W_0F3891_P_2,
2326   EVEX_W_0F3893_P_2,
2327   EVEX_W_0F38A1_P_2,
2328   EVEX_W_0F38A3_P_2,
2329   EVEX_W_0F38C7_R_1_P_2,
2330   EVEX_W_0F38C7_R_2_P_2,
2331   EVEX_W_0F38C7_R_5_P_2,
2332   EVEX_W_0F38C7_R_6_P_2,
2333
2334   EVEX_W_0F3A00_P_2,
2335   EVEX_W_0F3A01_P_2,
2336   EVEX_W_0F3A04_P_2,
2337   EVEX_W_0F3A05_P_2,
2338   EVEX_W_0F3A08_P_2,
2339   EVEX_W_0F3A09_P_2,
2340   EVEX_W_0F3A0A_P_2,
2341   EVEX_W_0F3A0B_P_2,
2342   EVEX_W_0F3A16_P_2,
2343   EVEX_W_0F3A18_P_2,
2344   EVEX_W_0F3A19_P_2,
2345   EVEX_W_0F3A1A_P_2,
2346   EVEX_W_0F3A1B_P_2,
2347   EVEX_W_0F3A1D_P_2,
2348   EVEX_W_0F3A21_P_2,
2349   EVEX_W_0F3A22_P_2,
2350   EVEX_W_0F3A23_P_2,
2351   EVEX_W_0F3A38_P_2,
2352   EVEX_W_0F3A39_P_2,
2353   EVEX_W_0F3A3A_P_2,
2354   EVEX_W_0F3A3B_P_2,
2355   EVEX_W_0F3A3E_P_2,
2356   EVEX_W_0F3A3F_P_2,
2357   EVEX_W_0F3A42_P_2,
2358   EVEX_W_0F3A43_P_2,
2359   EVEX_W_0F3A50_P_2,
2360   EVEX_W_0F3A51_P_2,
2361   EVEX_W_0F3A56_P_2,
2362   EVEX_W_0F3A57_P_2,
2363   EVEX_W_0F3A66_P_2,
2364   EVEX_W_0F3A67_P_2
2365 };
2366
2367 typedef void (*op_rtn) (int bytemode, int sizeflag);
2368
2369 struct dis386 {
2370   const char *name;
2371   struct
2372     {
2373       op_rtn rtn;
2374       int bytemode;
2375     } op[MAX_OPERANDS];
2376   unsigned int prefix_requirement;
2377 };
2378
2379 /* Upper case letters in the instruction names here are macros.
2380    'A' => print 'b' if no register operands or suffix_always is true
2381    'B' => print 'b' if suffix_always is true
2382    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2383           size prefix
2384    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2385           suffix_always is true
2386    'E' => print 'e' if 32-bit form of jcxz
2387    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2388    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2389    'H' => print ",pt" or ",pn" branch hint
2390    'I' => honor following macro letter even in Intel mode (implemented only
2391           for some of the macro letters)
2392    'J' => print 'l'
2393    'K' => print 'd' or 'q' if rex prefix is present.
2394    'L' => print 'l' if suffix_always is true
2395    'M' => print 'r' if intel_mnemonic is false.
2396    'N' => print 'n' if instruction has no wait "prefix"
2397    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2398    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2399           or suffix_always is true.  print 'q' if rex prefix is present.
2400    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2401           is true
2402    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2403    'S' => print 'w', 'l' or 'q' if suffix_always is true
2404    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2405    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2406    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2407    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2408    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2409    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2410           suffix_always is true.
2411    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2412    '!' => change condition from true to false or from false to true.
2413    '%' => add 1 upper case letter to the macro.
2414
2415    2 upper case letter macros:
2416    "XY" => print 'x' or 'y' if suffix_always is true or no register
2417            operands and no broadcast.
2418    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2419            register operands and no broadcast.
2420    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2421    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2422            or suffix_always is true
2423    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2424    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2425    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2426    "LW" => print 'd', 'q' depending on the VEX.W bit
2427    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2428            an operand size prefix, or suffix_always is true.  print
2429            'q' if rex prefix is present.
2430
2431    Many of the above letters print nothing in Intel mode.  See "putop"
2432    for the details.
2433
2434    Braces '{' and '}', and vertical bars '|', indicate alternative
2435    mnemonic strings for AT&T and Intel.  */
2436
2437 static const struct dis386 dis386[] = {
2438   /* 00 */
2439   { "addB",             { Ebh1, Gb }, 0 },
2440   { "addS",             { Evh1, Gv }, 0 },
2441   { "addB",             { Gb, EbS }, 0 },
2442   { "addS",             { Gv, EvS }, 0 },
2443   { "addB",             { AL, Ib }, 0 },
2444   { "addS",             { eAX, Iv }, 0 },
2445   { X86_64_TABLE (X86_64_06) },
2446   { X86_64_TABLE (X86_64_07) },
2447   /* 08 */
2448   { "orB",              { Ebh1, Gb }, 0 },
2449   { "orS",              { Evh1, Gv }, 0 },
2450   { "orB",              { Gb, EbS }, 0 },
2451   { "orS",              { Gv, EvS }, 0 },
2452   { "orB",              { AL, Ib }, 0 },
2453   { "orS",              { eAX, Iv }, 0 },
2454   { X86_64_TABLE (X86_64_0D) },
2455   { Bad_Opcode },       /* 0x0f extended opcode escape */
2456   /* 10 */
2457   { "adcB",             { Ebh1, Gb }, 0 },
2458   { "adcS",             { Evh1, Gv }, 0 },
2459   { "adcB",             { Gb, EbS }, 0 },
2460   { "adcS",             { Gv, EvS }, 0 },
2461   { "adcB",             { AL, Ib }, 0 },
2462   { "adcS",             { eAX, Iv }, 0 },
2463   { X86_64_TABLE (X86_64_16) },
2464   { X86_64_TABLE (X86_64_17) },
2465   /* 18 */
2466   { "sbbB",             { Ebh1, Gb }, 0 },
2467   { "sbbS",             { Evh1, Gv }, 0 },
2468   { "sbbB",             { Gb, EbS }, 0 },
2469   { "sbbS",             { Gv, EvS }, 0 },
2470   { "sbbB",             { AL, Ib }, 0 },
2471   { "sbbS",             { eAX, Iv }, 0 },
2472   { X86_64_TABLE (X86_64_1E) },
2473   { X86_64_TABLE (X86_64_1F) },
2474   /* 20 */
2475   { "andB",             { Ebh1, Gb }, 0 },
2476   { "andS",             { Evh1, Gv }, 0 },
2477   { "andB",             { Gb, EbS }, 0 },
2478   { "andS",             { Gv, EvS }, 0 },
2479   { "andB",             { AL, Ib }, 0 },
2480   { "andS",             { eAX, Iv }, 0 },
2481   { Bad_Opcode },       /* SEG ES prefix */
2482   { X86_64_TABLE (X86_64_27) },
2483   /* 28 */
2484   { "subB",             { Ebh1, Gb }, 0 },
2485   { "subS",             { Evh1, Gv }, 0 },
2486   { "subB",             { Gb, EbS }, 0 },
2487   { "subS",             { Gv, EvS }, 0 },
2488   { "subB",             { AL, Ib }, 0 },
2489   { "subS",             { eAX, Iv }, 0 },
2490   { Bad_Opcode },       /* SEG CS prefix */
2491   { X86_64_TABLE (X86_64_2F) },
2492   /* 30 */
2493   { "xorB",             { Ebh1, Gb }, 0 },
2494   { "xorS",             { Evh1, Gv }, 0 },
2495   { "xorB",             { Gb, EbS }, 0 },
2496   { "xorS",             { Gv, EvS }, 0 },
2497   { "xorB",             { AL, Ib }, 0 },
2498   { "xorS",             { eAX, Iv }, 0 },
2499   { Bad_Opcode },       /* SEG SS prefix */
2500   { X86_64_TABLE (X86_64_37) },
2501   /* 38 */
2502   { "cmpB",             { Eb, Gb }, 0 },
2503   { "cmpS",             { Ev, Gv }, 0 },
2504   { "cmpB",             { Gb, EbS }, 0 },
2505   { "cmpS",             { Gv, EvS }, 0 },
2506   { "cmpB",             { AL, Ib }, 0 },
2507   { "cmpS",             { eAX, Iv }, 0 },
2508   { Bad_Opcode },       /* SEG DS prefix */
2509   { X86_64_TABLE (X86_64_3F) },
2510   /* 40 */
2511   { "inc{S|}",          { RMeAX }, 0 },
2512   { "inc{S|}",          { RMeCX }, 0 },
2513   { "inc{S|}",          { RMeDX }, 0 },
2514   { "inc{S|}",          { RMeBX }, 0 },
2515   { "inc{S|}",          { RMeSP }, 0 },
2516   { "inc{S|}",          { RMeBP }, 0 },
2517   { "inc{S|}",          { RMeSI }, 0 },
2518   { "inc{S|}",          { RMeDI }, 0 },
2519   /* 48 */
2520   { "dec{S|}",          { RMeAX }, 0 },
2521   { "dec{S|}",          { RMeCX }, 0 },
2522   { "dec{S|}",          { RMeDX }, 0 },
2523   { "dec{S|}",          { RMeBX }, 0 },
2524   { "dec{S|}",          { RMeSP }, 0 },
2525   { "dec{S|}",          { RMeBP }, 0 },
2526   { "dec{S|}",          { RMeSI }, 0 },
2527   { "dec{S|}",          { RMeDI }, 0 },
2528   /* 50 */
2529   { "pushV",            { RMrAX }, 0 },
2530   { "pushV",            { RMrCX }, 0 },
2531   { "pushV",            { RMrDX }, 0 },
2532   { "pushV",            { RMrBX }, 0 },
2533   { "pushV",            { RMrSP }, 0 },
2534   { "pushV",            { RMrBP }, 0 },
2535   { "pushV",            { RMrSI }, 0 },
2536   { "pushV",            { RMrDI }, 0 },
2537   /* 58 */
2538   { "popV",             { RMrAX }, 0 },
2539   { "popV",             { RMrCX }, 0 },
2540   { "popV",             { RMrDX }, 0 },
2541   { "popV",             { RMrBX }, 0 },
2542   { "popV",             { RMrSP }, 0 },
2543   { "popV",             { RMrBP }, 0 },
2544   { "popV",             { RMrSI }, 0 },
2545   { "popV",             { RMrDI }, 0 },
2546   /* 60 */
2547   { X86_64_TABLE (X86_64_60) },
2548   { X86_64_TABLE (X86_64_61) },
2549   { X86_64_TABLE (X86_64_62) },
2550   { X86_64_TABLE (X86_64_63) },
2551   { Bad_Opcode },       /* seg fs */
2552   { Bad_Opcode },       /* seg gs */
2553   { Bad_Opcode },       /* op size prefix */
2554   { Bad_Opcode },       /* adr size prefix */
2555   /* 68 */
2556   { "pushT",            { sIv }, 0 },
2557   { "imulS",            { Gv, Ev, Iv }, 0 },
2558   { "pushT",            { sIbT }, 0 },
2559   { "imulS",            { Gv, Ev, sIb }, 0 },
2560   { "ins{b|}",          { Ybr, indirDX }, 0 },
2561   { X86_64_TABLE (X86_64_6D) },
2562   { "outs{b|}",         { indirDXr, Xb }, 0 },
2563   { X86_64_TABLE (X86_64_6F) },
2564   /* 70 */
2565   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2566   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2567   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2568   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2569   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2570   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2571   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2572   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2573   /* 78 */
2574   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2575   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2576   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2577   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2578   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2579   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2580   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2581   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2582   /* 80 */
2583   { REG_TABLE (REG_80) },
2584   { REG_TABLE (REG_81) },
2585   { Bad_Opcode },
2586   { REG_TABLE (REG_82) },
2587   { "testB",            { Eb, Gb }, 0 },
2588   { "testS",            { Ev, Gv }, 0 },
2589   { "xchgB",            { Ebh2, Gb }, 0 },
2590   { "xchgS",            { Evh2, Gv }, 0 },
2591   /* 88 */
2592   { "movB",             { Ebh3, Gb }, 0 },
2593   { "movS",             { Evh3, Gv }, 0 },
2594   { "movB",             { Gb, EbS }, 0 },
2595   { "movS",             { Gv, EvS }, 0 },
2596   { "movD",             { Sv, Sw }, 0 },
2597   { MOD_TABLE (MOD_8D) },
2598   { "movD",             { Sw, Sv }, 0 },
2599   { REG_TABLE (REG_8F) },
2600   /* 90 */
2601   { PREFIX_TABLE (PREFIX_90) },
2602   { "xchgS",            { RMeCX, eAX }, 0 },
2603   { "xchgS",            { RMeDX, eAX }, 0 },
2604   { "xchgS",            { RMeBX, eAX }, 0 },
2605   { "xchgS",            { RMeSP, eAX }, 0 },
2606   { "xchgS",            { RMeBP, eAX }, 0 },
2607   { "xchgS",            { RMeSI, eAX }, 0 },
2608   { "xchgS",            { RMeDI, eAX }, 0 },
2609   /* 98 */
2610   { "cW{t|}R",          { XX }, 0 },
2611   { "cR{t|}O",          { XX }, 0 },
2612   { X86_64_TABLE (X86_64_9A) },
2613   { Bad_Opcode },       /* fwait */
2614   { "pushfT",           { XX }, 0 },
2615   { "popfT",            { XX }, 0 },
2616   { "sahf",             { XX }, 0 },
2617   { "lahf",             { XX }, 0 },
2618   /* a0 */
2619   { "mov%LB",           { AL, Ob }, 0 },
2620   { "mov%LS",           { eAX, Ov }, 0 },
2621   { "mov%LB",           { Ob, AL }, 0 },
2622   { "mov%LS",           { Ov, eAX }, 0 },
2623   { "movs{b|}",         { Ybr, Xb }, 0 },
2624   { "movs{R|}",         { Yvr, Xv }, 0 },
2625   { "cmps{b|}",         { Xb, Yb }, 0 },
2626   { "cmps{R|}",         { Xv, Yv }, 0 },
2627   /* a8 */
2628   { "testB",            { AL, Ib }, 0 },
2629   { "testS",            { eAX, Iv }, 0 },
2630   { "stosB",            { Ybr, AL }, 0 },
2631   { "stosS",            { Yvr, eAX }, 0 },
2632   { "lodsB",            { ALr, Xb }, 0 },
2633   { "lodsS",            { eAXr, Xv }, 0 },
2634   { "scasB",            { AL, Yb }, 0 },
2635   { "scasS",            { eAX, Yv }, 0 },
2636   /* b0 */
2637   { "movB",             { RMAL, Ib }, 0 },
2638   { "movB",             { RMCL, Ib }, 0 },
2639   { "movB",             { RMDL, Ib }, 0 },
2640   { "movB",             { RMBL, Ib }, 0 },
2641   { "movB",             { RMAH, Ib }, 0 },
2642   { "movB",             { RMCH, Ib }, 0 },
2643   { "movB",             { RMDH, Ib }, 0 },
2644   { "movB",             { RMBH, Ib }, 0 },
2645   /* b8 */
2646   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2647   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2648   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2649   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2650   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2651   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2652   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2653   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2654   /* c0 */
2655   { REG_TABLE (REG_C0) },
2656   { REG_TABLE (REG_C1) },
2657   { "retT",             { Iw, BND }, 0 },
2658   { "retT",             { BND }, 0 },
2659   { X86_64_TABLE (X86_64_C4) },
2660   { X86_64_TABLE (X86_64_C5) },
2661   { REG_TABLE (REG_C6) },
2662   { REG_TABLE (REG_C7) },
2663   /* c8 */
2664   { "enterT",           { Iw, Ib }, 0 },
2665   { "leaveT",           { XX }, 0 },
2666   { "Jret{|f}P",        { Iw }, 0 },
2667   { "Jret{|f}P",        { XX }, 0 },
2668   { "int3",             { XX }, 0 },
2669   { "int",              { Ib }, 0 },
2670   { X86_64_TABLE (X86_64_CE) },
2671   { "iret%LP",          { XX }, 0 },
2672   /* d0 */
2673   { REG_TABLE (REG_D0) },
2674   { REG_TABLE (REG_D1) },
2675   { REG_TABLE (REG_D2) },
2676   { REG_TABLE (REG_D3) },
2677   { X86_64_TABLE (X86_64_D4) },
2678   { X86_64_TABLE (X86_64_D5) },
2679   { Bad_Opcode },
2680   { "xlat",             { DSBX }, 0 },
2681   /* d8 */
2682   { FLOAT },
2683   { FLOAT },
2684   { FLOAT },
2685   { FLOAT },
2686   { FLOAT },
2687   { FLOAT },
2688   { FLOAT },
2689   { FLOAT },
2690   /* e0 */
2691   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2692   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2693   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2694   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2695   { "inB",              { AL, Ib }, 0 },
2696   { "inG",              { zAX, Ib }, 0 },
2697   { "outB",             { Ib, AL }, 0 },
2698   { "outG",             { Ib, zAX }, 0 },
2699   /* e8 */
2700   { "callT",            { Jv, BND }, 0 },
2701   { "jmpT",             { Jv, BND }, 0 },
2702   { X86_64_TABLE (X86_64_EA) },
2703   { "jmp",              { Jb, BND }, 0 },
2704   { "inB",              { AL, indirDX }, 0 },
2705   { "inG",              { zAX, indirDX }, 0 },
2706   { "outB",             { indirDX, AL }, 0 },
2707   { "outG",             { indirDX, zAX }, 0 },
2708   /* f0 */
2709   { Bad_Opcode },       /* lock prefix */
2710   { "icebp",            { XX }, 0 },
2711   { Bad_Opcode },       /* repne */
2712   { Bad_Opcode },       /* repz */
2713   { "hlt",              { XX }, 0 },
2714   { "cmc",              { XX }, 0 },
2715   { REG_TABLE (REG_F6) },
2716   { REG_TABLE (REG_F7) },
2717   /* f8 */
2718   { "clc",              { XX }, 0 },
2719   { "stc",              { XX }, 0 },
2720   { "cli",              { XX }, 0 },
2721   { "sti",              { XX }, 0 },
2722   { "cld",              { XX }, 0 },
2723   { "std",              { XX }, 0 },
2724   { REG_TABLE (REG_FE) },
2725   { REG_TABLE (REG_FF) },
2726 };
2727
2728 static const struct dis386 dis386_twobyte[] = {
2729   /* 00 */
2730   { REG_TABLE (REG_0F00 ) },
2731   { REG_TABLE (REG_0F01 ) },
2732   { "larS",             { Gv, Ew }, 0 },
2733   { "lslS",             { Gv, Ew }, 0 },
2734   { Bad_Opcode },
2735   { "syscall",          { XX }, 0 },
2736   { "clts",             { XX }, 0 },
2737   { "sysret%LP",                { XX }, 0 },
2738   /* 08 */
2739   { "invd",             { XX }, 0 },
2740   { "wbinvd",           { XX }, 0 },
2741   { Bad_Opcode },
2742   { "ud2",              { XX }, 0 },
2743   { Bad_Opcode },
2744   { REG_TABLE (REG_0F0D) },
2745   { "femms",            { XX }, 0 },
2746   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2747   /* 10 */
2748   { PREFIX_TABLE (PREFIX_0F10) },
2749   { PREFIX_TABLE (PREFIX_0F11) },
2750   { PREFIX_TABLE (PREFIX_0F12) },
2751   { MOD_TABLE (MOD_0F13) },
2752   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2753   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2754   { PREFIX_TABLE (PREFIX_0F16) },
2755   { MOD_TABLE (MOD_0F17) },
2756   /* 18 */
2757   { REG_TABLE (REG_0F18) },
2758   { "nopQ",             { Ev }, 0 },
2759   { PREFIX_TABLE (PREFIX_0F1A) },
2760   { PREFIX_TABLE (PREFIX_0F1B) },
2761   { "nopQ",             { Ev }, 0 },
2762   { "nopQ",             { Ev }, 0 },
2763   { "nopQ",             { Ev }, 0 },
2764   { "nopQ",             { Ev }, 0 },
2765   /* 20 */
2766   { "movZ",             { Rm, Cm }, 0 },
2767   { "movZ",             { Rm, Dm }, 0 },
2768   { "movZ",             { Cm, Rm }, 0 },
2769   { "movZ",             { Dm, Rm }, 0 },
2770   { MOD_TABLE (MOD_0F24) },
2771   { Bad_Opcode },
2772   { MOD_TABLE (MOD_0F26) },
2773   { Bad_Opcode },
2774   /* 28 */
2775   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2776   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2777   { PREFIX_TABLE (PREFIX_0F2A) },
2778   { PREFIX_TABLE (PREFIX_0F2B) },
2779   { PREFIX_TABLE (PREFIX_0F2C) },
2780   { PREFIX_TABLE (PREFIX_0F2D) },
2781   { PREFIX_TABLE (PREFIX_0F2E) },
2782   { PREFIX_TABLE (PREFIX_0F2F) },
2783   /* 30 */
2784   { "wrmsr",            { XX }, 0 },
2785   { "rdtsc",            { XX }, 0 },
2786   { "rdmsr",            { XX }, 0 },
2787   { "rdpmc",            { XX }, 0 },
2788   { "sysenter",         { XX }, 0 },
2789   { "sysexit",          { XX }, 0 },
2790   { Bad_Opcode },
2791   { "getsec",           { XX }, 0 },
2792   /* 38 */
2793   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2794   { Bad_Opcode },
2795   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2796   { Bad_Opcode },
2797   { Bad_Opcode },
2798   { Bad_Opcode },
2799   { Bad_Opcode },
2800   { Bad_Opcode },
2801   /* 40 */
2802   { "cmovoS",           { Gv, Ev }, 0 },
2803   { "cmovnoS",          { Gv, Ev }, 0 },
2804   { "cmovbS",           { Gv, Ev }, 0 },
2805   { "cmovaeS",          { Gv, Ev }, 0 },
2806   { "cmoveS",           { Gv, Ev }, 0 },
2807   { "cmovneS",          { Gv, Ev }, 0 },
2808   { "cmovbeS",          { Gv, Ev }, 0 },
2809   { "cmovaS",           { Gv, Ev }, 0 },
2810   /* 48 */
2811   { "cmovsS",           { Gv, Ev }, 0 },
2812   { "cmovnsS",          { Gv, Ev }, 0 },
2813   { "cmovpS",           { Gv, Ev }, 0 },
2814   { "cmovnpS",          { Gv, Ev }, 0 },
2815   { "cmovlS",           { Gv, Ev }, 0 },
2816   { "cmovgeS",          { Gv, Ev }, 0 },
2817   { "cmovleS",          { Gv, Ev }, 0 },
2818   { "cmovgS",           { Gv, Ev }, 0 },
2819   /* 50 */
2820   { MOD_TABLE (MOD_0F51) },
2821   { PREFIX_TABLE (PREFIX_0F51) },
2822   { PREFIX_TABLE (PREFIX_0F52) },
2823   { PREFIX_TABLE (PREFIX_0F53) },
2824   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2825   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2826   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2827   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2828   /* 58 */
2829   { PREFIX_TABLE (PREFIX_0F58) },
2830   { PREFIX_TABLE (PREFIX_0F59) },
2831   { PREFIX_TABLE (PREFIX_0F5A) },
2832   { PREFIX_TABLE (PREFIX_0F5B) },
2833   { PREFIX_TABLE (PREFIX_0F5C) },
2834   { PREFIX_TABLE (PREFIX_0F5D) },
2835   { PREFIX_TABLE (PREFIX_0F5E) },
2836   { PREFIX_TABLE (PREFIX_0F5F) },
2837   /* 60 */
2838   { PREFIX_TABLE (PREFIX_0F60) },
2839   { PREFIX_TABLE (PREFIX_0F61) },
2840   { PREFIX_TABLE (PREFIX_0F62) },
2841   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2842   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2843   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2844   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2845   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2846   /* 68 */
2847   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2848   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2849   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2850   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2851   { PREFIX_TABLE (PREFIX_0F6C) },
2852   { PREFIX_TABLE (PREFIX_0F6D) },
2853   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2854   { PREFIX_TABLE (PREFIX_0F6F) },
2855   /* 70 */
2856   { PREFIX_TABLE (PREFIX_0F70) },
2857   { REG_TABLE (REG_0F71) },
2858   { REG_TABLE (REG_0F72) },
2859   { REG_TABLE (REG_0F73) },
2860   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2861   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2862   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2863   { "emms",             { XX }, PREFIX_OPCODE },
2864   /* 78 */
2865   { PREFIX_TABLE (PREFIX_0F78) },
2866   { PREFIX_TABLE (PREFIX_0F79) },
2867   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2868   { Bad_Opcode },
2869   { PREFIX_TABLE (PREFIX_0F7C) },
2870   { PREFIX_TABLE (PREFIX_0F7D) },
2871   { PREFIX_TABLE (PREFIX_0F7E) },
2872   { PREFIX_TABLE (PREFIX_0F7F) },
2873   /* 80 */
2874   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2875   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2876   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2877   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2878   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2879   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2880   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2881   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2882   /* 88 */
2883   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2884   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2885   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2886   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2887   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2888   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2889   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2890   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2891   /* 90 */
2892   { "seto",             { Eb }, 0 },
2893   { "setno",            { Eb }, 0 },
2894   { "setb",             { Eb }, 0 },
2895   { "setae",            { Eb }, 0 },
2896   { "sete",             { Eb }, 0 },
2897   { "setne",            { Eb }, 0 },
2898   { "setbe",            { Eb }, 0 },
2899   { "seta",             { Eb }, 0 },
2900   /* 98 */
2901   { "sets",             { Eb }, 0 },
2902   { "setns",            { Eb }, 0 },
2903   { "setp",             { Eb }, 0 },
2904   { "setnp",            { Eb }, 0 },
2905   { "setl",             { Eb }, 0 },
2906   { "setge",            { Eb }, 0 },
2907   { "setle",            { Eb }, 0 },
2908   { "setg",             { Eb }, 0 },
2909   /* a0 */
2910   { "pushT",            { fs }, 0 },
2911   { "popT",             { fs }, 0 },
2912   { "cpuid",            { XX }, 0 },
2913   { "btS",              { Ev, Gv }, 0 },
2914   { "shldS",            { Ev, Gv, Ib }, 0 },
2915   { "shldS",            { Ev, Gv, CL }, 0 },
2916   { REG_TABLE (REG_0FA6) },
2917   { REG_TABLE (REG_0FA7) },
2918   /* a8 */
2919   { "pushT",            { gs }, 0 },
2920   { "popT",             { gs }, 0 },
2921   { "rsm",              { XX }, 0 },
2922   { "btsS",             { Evh1, Gv }, 0 },
2923   { "shrdS",            { Ev, Gv, Ib }, 0 },
2924   { "shrdS",            { Ev, Gv, CL }, 0 },
2925   { REG_TABLE (REG_0FAE) },
2926   { "imulS",            { Gv, Ev }, 0 },
2927   /* b0 */
2928   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2929   { "cmpxchgS",         { Evh1, Gv }, 0 },
2930   { MOD_TABLE (MOD_0FB2) },
2931   { "btrS",             { Evh1, Gv }, 0 },
2932   { MOD_TABLE (MOD_0FB4) },
2933   { MOD_TABLE (MOD_0FB5) },
2934   { "movz{bR|x}",       { Gv, Eb }, 0 },
2935   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2936   /* b8 */
2937   { PREFIX_TABLE (PREFIX_0FB8) },
2938   { "ud1",              { XX }, 0 },
2939   { REG_TABLE (REG_0FBA) },
2940   { "btcS",             { Evh1, Gv }, 0 },
2941   { PREFIX_TABLE (PREFIX_0FBC) },
2942   { PREFIX_TABLE (PREFIX_0FBD) },
2943   { "movs{bR|x}",       { Gv, Eb }, 0 },
2944   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2945   /* c0 */
2946   { "xaddB",            { Ebh1, Gb }, 0 },
2947   { "xaddS",            { Evh1, Gv }, 0 },
2948   { PREFIX_TABLE (PREFIX_0FC2) },
2949   { PREFIX_TABLE (PREFIX_0FC3) },
2950   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2951   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2952   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2953   { REG_TABLE (REG_0FC7) },
2954   /* c8 */
2955   { "bswap",            { RMeAX }, 0 },
2956   { "bswap",            { RMeCX }, 0 },
2957   { "bswap",            { RMeDX }, 0 },
2958   { "bswap",            { RMeBX }, 0 },
2959   { "bswap",            { RMeSP }, 0 },
2960   { "bswap",            { RMeBP }, 0 },
2961   { "bswap",            { RMeSI }, 0 },
2962   { "bswap",            { RMeDI }, 0 },
2963   /* d0 */
2964   { PREFIX_TABLE (PREFIX_0FD0) },
2965   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2966   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2967   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2968   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2969   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2970   { PREFIX_TABLE (PREFIX_0FD6) },
2971   { MOD_TABLE (MOD_0FD7) },
2972   /* d8 */
2973   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2974   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2975   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2976   { "pand",             { MX, EM }, PREFIX_OPCODE },
2977   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2978   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2979   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2980   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2981   /* e0 */
2982   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2983   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2984   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2985   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2986   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2987   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2988   { PREFIX_TABLE (PREFIX_0FE6) },
2989   { PREFIX_TABLE (PREFIX_0FE7) },
2990   /* e8 */
2991   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2992   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2993   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2994   { "por",              { MX, EM }, PREFIX_OPCODE },
2995   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2996   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2997   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2998   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2999   /* f0 */
3000   { PREFIX_TABLE (PREFIX_0FF0) },
3001   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3002   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3003   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3004   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3005   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3006   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3007   { PREFIX_TABLE (PREFIX_0FF7) },
3008   /* f8 */
3009   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3010   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3011   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3012   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3013   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3014   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3015   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3016   { Bad_Opcode },
3017 };
3018
3019 static const unsigned char onebyte_has_modrm[256] = {
3020   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3021   /*       -------------------------------        */
3022   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3023   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3024   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3025   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3026   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3027   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3028   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3029   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3030   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3031   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3032   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3033   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3034   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3035   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3036   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3037   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3038   /*       -------------------------------        */
3039   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3040 };
3041
3042 static const unsigned char twobyte_has_modrm[256] = {
3043   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3044   /*       -------------------------------        */
3045   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3046   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3047   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3048   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3049   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3050   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3051   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3052   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3053   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3054   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3055   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3056   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3057   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3058   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3059   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3060   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3061   /*       -------------------------------        */
3062   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3063 };
3064
3065 static char obuf[100];
3066 static char *obufp;
3067 static char *mnemonicendp;
3068 static char scratchbuf[100];
3069 static unsigned char *start_codep;
3070 static unsigned char *insn_codep;
3071 static unsigned char *codep;
3072 static unsigned char *end_codep;
3073 static int last_lock_prefix;
3074 static int last_repz_prefix;
3075 static int last_repnz_prefix;
3076 static int last_data_prefix;
3077 static int last_addr_prefix;
3078 static int last_rex_prefix;
3079 static int last_seg_prefix;
3080 static int fwait_prefix;
3081 /* The active segment register prefix.  */
3082 static int active_seg_prefix;
3083 #define MAX_CODE_LENGTH 15
3084 /* We can up to 14 prefixes since the maximum instruction length is
3085    15bytes.  */
3086 static int all_prefixes[MAX_CODE_LENGTH - 1];
3087 static disassemble_info *the_info;
3088 static struct
3089   {
3090     int mod;
3091     int reg;
3092     int rm;
3093   }
3094 modrm;
3095 static unsigned char need_modrm;
3096 static struct
3097   {
3098     int scale;
3099     int index;
3100     int base;
3101   }
3102 sib;
3103 static struct
3104   {
3105     int register_specifier;
3106     int length;
3107     int prefix;
3108     int w;
3109     int evex;
3110     int r;
3111     int v;
3112     int mask_register_specifier;
3113     int zeroing;
3114     int ll;
3115     int b;
3116   }
3117 vex;
3118 static unsigned char need_vex;
3119 static unsigned char need_vex_reg;
3120 static unsigned char vex_w_done;
3121
3122 struct op
3123   {
3124     const char *name;
3125     unsigned int len;
3126   };
3127
3128 /* If we are accessing mod/rm/reg without need_modrm set, then the
3129    values are stale.  Hitting this abort likely indicates that you
3130    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3131 #define MODRM_CHECK  if (!need_modrm) abort ()
3132
3133 static const char **names64;
3134 static const char **names32;
3135 static const char **names16;
3136 static const char **names8;
3137 static const char **names8rex;
3138 static const char **names_seg;
3139 static const char *index64;
3140 static const char *index32;
3141 static const char **index16;
3142 static const char **names_bnd;
3143
3144 static const char *intel_names64[] = {
3145   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3146   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3147 };
3148 static const char *intel_names32[] = {
3149   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3150   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3151 };
3152 static const char *intel_names16[] = {
3153   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3154   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3155 };
3156 static const char *intel_names8[] = {
3157   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3158 };
3159 static const char *intel_names8rex[] = {
3160   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3161   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3162 };
3163 static const char *intel_names_seg[] = {
3164   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3165 };
3166 static const char *intel_index64 = "riz";
3167 static const char *intel_index32 = "eiz";
3168 static const char *intel_index16[] = {
3169   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3170 };
3171
3172 static const char *att_names64[] = {
3173   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3174   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3175 };
3176 static const char *att_names32[] = {
3177   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3178   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3179 };
3180 static const char *att_names16[] = {
3181   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3182   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3183 };
3184 static const char *att_names8[] = {
3185   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3186 };
3187 static const char *att_names8rex[] = {
3188   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3189   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3190 };
3191 static const char *att_names_seg[] = {
3192   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3193 };
3194 static const char *att_index64 = "%riz";
3195 static const char *att_index32 = "%eiz";
3196 static const char *att_index16[] = {
3197   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3198 };
3199
3200 static const char **names_mm;
3201 static const char *intel_names_mm[] = {
3202   "mm0", "mm1", "mm2", "mm3",
3203   "mm4", "mm5", "mm6", "mm7"
3204 };
3205 static const char *att_names_mm[] = {
3206   "%mm0", "%mm1", "%mm2", "%mm3",
3207   "%mm4", "%mm5", "%mm6", "%mm7"
3208 };
3209
3210 static const char *intel_names_bnd[] = {
3211   "bnd0", "bnd1", "bnd2", "bnd3"
3212 };
3213
3214 static const char *att_names_bnd[] = {
3215   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3216 };
3217
3218 static const char **names_xmm;
3219 static const char *intel_names_xmm[] = {
3220   "xmm0", "xmm1", "xmm2", "xmm3",
3221   "xmm4", "xmm5", "xmm6", "xmm7",
3222   "xmm8", "xmm9", "xmm10", "xmm11",
3223   "xmm12", "xmm13", "xmm14", "xmm15",
3224   "xmm16", "xmm17", "xmm18", "xmm19",
3225   "xmm20", "xmm21", "xmm22", "xmm23",
3226   "xmm24", "xmm25", "xmm26", "xmm27",
3227   "xmm28", "xmm29", "xmm30", "xmm31"
3228 };
3229 static const char *att_names_xmm[] = {
3230   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3231   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3232   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3233   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3234   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3235   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3236   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3237   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3238 };
3239
3240 static const char **names_ymm;
3241 static const char *intel_names_ymm[] = {
3242   "ymm0", "ymm1", "ymm2", "ymm3",
3243   "ymm4", "ymm5", "ymm6", "ymm7",
3244   "ymm8", "ymm9", "ymm10", "ymm11",
3245   "ymm12", "ymm13", "ymm14", "ymm15",
3246   "ymm16", "ymm17", "ymm18", "ymm19",
3247   "ymm20", "ymm21", "ymm22", "ymm23",
3248   "ymm24", "ymm25", "ymm26", "ymm27",
3249   "ymm28", "ymm29", "ymm30", "ymm31"
3250 };
3251 static const char *att_names_ymm[] = {
3252   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3253   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3254   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3255   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3256   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3257   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3258   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3259   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3260 };
3261
3262 static const char **names_zmm;
3263 static const char *intel_names_zmm[] = {
3264   "zmm0", "zmm1", "zmm2", "zmm3",
3265   "zmm4", "zmm5", "zmm6", "zmm7",
3266   "zmm8", "zmm9", "zmm10", "zmm11",
3267   "zmm12", "zmm13", "zmm14", "zmm15",
3268   "zmm16", "zmm17", "zmm18", "zmm19",
3269   "zmm20", "zmm21", "zmm22", "zmm23",
3270   "zmm24", "zmm25", "zmm26", "zmm27",
3271   "zmm28", "zmm29", "zmm30", "zmm31"
3272 };
3273 static const char *att_names_zmm[] = {
3274   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3275   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3276   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3277   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3278   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3279   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3280   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3281   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3282 };
3283
3284 static const char **names_mask;
3285 static const char *intel_names_mask[] = {
3286   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3287 };
3288 static const char *att_names_mask[] = {
3289   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3290 };
3291
3292 static const char *names_rounding[] =
3293 {
3294   "{rn-sae}",
3295   "{rd-sae}",
3296   "{ru-sae}",
3297   "{rz-sae}"
3298 };
3299
3300 static const struct dis386 reg_table[][8] = {
3301   /* REG_80 */
3302   {
3303     { "addA",   { Ebh1, Ib }, 0 },
3304     { "orA",    { Ebh1, Ib }, 0 },
3305     { "adcA",   { Ebh1, Ib }, 0 },
3306     { "sbbA",   { Ebh1, Ib }, 0 },
3307     { "andA",   { Ebh1, Ib }, 0 },
3308     { "subA",   { Ebh1, Ib }, 0 },
3309     { "xorA",   { Ebh1, Ib }, 0 },
3310     { "cmpA",   { Eb, Ib }, 0 },
3311   },
3312   /* REG_81 */
3313   {
3314     { "addQ",   { Evh1, Iv }, 0 },
3315     { "orQ",    { Evh1, Iv }, 0 },
3316     { "adcQ",   { Evh1, Iv }, 0 },
3317     { "sbbQ",   { Evh1, Iv }, 0 },
3318     { "andQ",   { Evh1, Iv }, 0 },
3319     { "subQ",   { Evh1, Iv }, 0 },
3320     { "xorQ",   { Evh1, Iv }, 0 },
3321     { "cmpQ",   { Ev, Iv }, 0 },
3322   },
3323   /* REG_82 */
3324   {
3325     { "addQ",   { Evh1, sIb }, 0 },
3326     { "orQ",    { Evh1, sIb }, 0 },
3327     { "adcQ",   { Evh1, sIb }, 0 },
3328     { "sbbQ",   { Evh1, sIb }, 0 },
3329     { "andQ",   { Evh1, sIb }, 0 },
3330     { "subQ",   { Evh1, sIb }, 0 },
3331     { "xorQ",   { Evh1, sIb }, 0 },
3332     { "cmpQ",   { Ev, sIb }, 0 },
3333   },
3334   /* REG_8F */
3335   {
3336     { "popU",   { stackEv }, 0 },
3337     { XOP_8F_TABLE (XOP_09) },
3338     { Bad_Opcode },
3339     { Bad_Opcode },
3340     { Bad_Opcode },
3341     { XOP_8F_TABLE (XOP_09) },
3342   },
3343   /* REG_C0 */
3344   {
3345     { "rolA",   { Eb, Ib }, 0 },
3346     { "rorA",   { Eb, Ib }, 0 },
3347     { "rclA",   { Eb, Ib }, 0 },
3348     { "rcrA",   { Eb, Ib }, 0 },
3349     { "shlA",   { Eb, Ib }, 0 },
3350     { "shrA",   { Eb, Ib }, 0 },
3351     { Bad_Opcode },
3352     { "sarA",   { Eb, Ib }, 0 },
3353   },
3354   /* REG_C1 */
3355   {
3356     { "rolQ",   { Ev, Ib }, 0 },
3357     { "rorQ",   { Ev, Ib }, 0 },
3358     { "rclQ",   { Ev, Ib }, 0 },
3359     { "rcrQ",   { Ev, Ib }, 0 },
3360     { "shlQ",   { Ev, Ib }, 0 },
3361     { "shrQ",   { Ev, Ib }, 0 },
3362     { Bad_Opcode },
3363     { "sarQ",   { Ev, Ib }, 0 },
3364   },
3365   /* REG_C6 */
3366   {
3367     { "movA",   { Ebh3, Ib }, 0 },
3368     { Bad_Opcode },
3369     { Bad_Opcode },
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { Bad_Opcode },
3373     { Bad_Opcode },
3374     { MOD_TABLE (MOD_C6_REG_7) },
3375   },
3376   /* REG_C7 */
3377   {
3378     { "movQ",   { Evh3, Iv }, 0 },
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383     { Bad_Opcode },
3384     { Bad_Opcode },
3385     { MOD_TABLE (MOD_C7_REG_7) },
3386   },
3387   /* REG_D0 */
3388   {
3389     { "rolA",   { Eb, I1 }, 0 },
3390     { "rorA",   { Eb, I1 }, 0 },
3391     { "rclA",   { Eb, I1 }, 0 },
3392     { "rcrA",   { Eb, I1 }, 0 },
3393     { "shlA",   { Eb, I1 }, 0 },
3394     { "shrA",   { Eb, I1 }, 0 },
3395     { Bad_Opcode },
3396     { "sarA",   { Eb, I1 }, 0 },
3397   },
3398   /* REG_D1 */
3399   {
3400     { "rolQ",   { Ev, I1 }, 0 },
3401     { "rorQ",   { Ev, I1 }, 0 },
3402     { "rclQ",   { Ev, I1 }, 0 },
3403     { "rcrQ",   { Ev, I1 }, 0 },
3404     { "shlQ",   { Ev, I1 }, 0 },
3405     { "shrQ",   { Ev, I1 }, 0 },
3406     { Bad_Opcode },
3407     { "sarQ",   { Ev, I1 }, 0 },
3408   },
3409   /* REG_D2 */
3410   {
3411     { "rolA",   { Eb, CL }, 0 },
3412     { "rorA",   { Eb, CL }, 0 },
3413     { "rclA",   { Eb, CL }, 0 },
3414     { "rcrA",   { Eb, CL }, 0 },
3415     { "shlA",   { Eb, CL }, 0 },
3416     { "shrA",   { Eb, CL }, 0 },
3417     { Bad_Opcode },
3418     { "sarA",   { Eb, CL }, 0 },
3419   },
3420   /* REG_D3 */
3421   {
3422     { "rolQ",   { Ev, CL }, 0 },
3423     { "rorQ",   { Ev, CL }, 0 },
3424     { "rclQ",   { Ev, CL }, 0 },
3425     { "rcrQ",   { Ev, CL }, 0 },
3426     { "shlQ",   { Ev, CL }, 0 },
3427     { "shrQ",   { Ev, CL }, 0 },
3428     { Bad_Opcode },
3429     { "sarQ",   { Ev, CL }, 0 },
3430   },
3431   /* REG_F6 */
3432   {
3433     { "testA",  { Eb, Ib }, 0 },
3434     { Bad_Opcode },
3435     { "notA",   { Ebh1 }, 0 },
3436     { "negA",   { Ebh1 }, 0 },
3437     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3438     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3439     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3440     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3441   },
3442   /* REG_F7 */
3443   {
3444     { "testQ",  { Ev, Iv }, 0 },
3445     { Bad_Opcode },
3446     { "notQ",   { Evh1 }, 0 },
3447     { "negQ",   { Evh1 }, 0 },
3448     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3449     { "imulQ",  { Ev }, 0 },
3450     { "divQ",   { Ev }, 0 },
3451     { "idivQ",  { Ev }, 0 },
3452   },
3453   /* REG_FE */
3454   {
3455     { "incA",   { Ebh1 }, 0 },
3456     { "decA",   { Ebh1 }, 0 },
3457   },
3458   /* REG_FF */
3459   {
3460     { "incQ",   { Evh1 }, 0 },
3461     { "decQ",   { Evh1 }, 0 },
3462     { "call{T|}", { indirEv, BND }, 0 },
3463     { MOD_TABLE (MOD_FF_REG_3) },
3464     { "jmp{T|}", { indirEv, BND }, 0 },
3465     { MOD_TABLE (MOD_FF_REG_5) },
3466     { "pushU",  { stackEv }, 0 },
3467     { Bad_Opcode },
3468   },
3469   /* REG_0F00 */
3470   {
3471     { "sldtD",  { Sv }, 0 },
3472     { "strD",   { Sv }, 0 },
3473     { "lldt",   { Ew }, 0 },
3474     { "ltr",    { Ew }, 0 },
3475     { "verr",   { Ew }, 0 },
3476     { "verw",   { Ew }, 0 },
3477     { Bad_Opcode },
3478     { Bad_Opcode },
3479   },
3480   /* REG_0F01 */
3481   {
3482     { MOD_TABLE (MOD_0F01_REG_0) },
3483     { MOD_TABLE (MOD_0F01_REG_1) },
3484     { MOD_TABLE (MOD_0F01_REG_2) },
3485     { MOD_TABLE (MOD_0F01_REG_3) },
3486     { "smswD",  { Sv }, 0 },
3487     { Bad_Opcode },
3488     { "lmsw",   { Ew }, 0 },
3489     { MOD_TABLE (MOD_0F01_REG_7) },
3490   },
3491   /* REG_0F0D */
3492   {
3493     { "prefetch",       { Mb }, 0 },
3494     { "prefetchw",      { Mb }, 0 },
3495     { "prefetchwt1",    { Mb }, 0 },
3496     { "prefetch",       { Mb }, 0 },
3497     { "prefetch",       { Mb }, 0 },
3498     { "prefetch",       { Mb }, 0 },
3499     { "prefetch",       { Mb }, 0 },
3500     { "prefetch",       { Mb }, 0 },
3501   },
3502   /* REG_0F18 */
3503   {
3504     { MOD_TABLE (MOD_0F18_REG_0) },
3505     { MOD_TABLE (MOD_0F18_REG_1) },
3506     { MOD_TABLE (MOD_0F18_REG_2) },
3507     { MOD_TABLE (MOD_0F18_REG_3) },
3508     { MOD_TABLE (MOD_0F18_REG_4) },
3509     { MOD_TABLE (MOD_0F18_REG_5) },
3510     { MOD_TABLE (MOD_0F18_REG_6) },
3511     { MOD_TABLE (MOD_0F18_REG_7) },
3512   },
3513   /* REG_0F71 */
3514   {
3515     { Bad_Opcode },
3516     { Bad_Opcode },
3517     { MOD_TABLE (MOD_0F71_REG_2) },
3518     { Bad_Opcode },
3519     { MOD_TABLE (MOD_0F71_REG_4) },
3520     { Bad_Opcode },
3521     { MOD_TABLE (MOD_0F71_REG_6) },
3522   },
3523   /* REG_0F72 */
3524   {
3525     { Bad_Opcode },
3526     { Bad_Opcode },
3527     { MOD_TABLE (MOD_0F72_REG_2) },
3528     { Bad_Opcode },
3529     { MOD_TABLE (MOD_0F72_REG_4) },
3530     { Bad_Opcode },
3531     { MOD_TABLE (MOD_0F72_REG_6) },
3532   },
3533   /* REG_0F73 */
3534   {
3535     { Bad_Opcode },
3536     { Bad_Opcode },
3537     { MOD_TABLE (MOD_0F73_REG_2) },
3538     { MOD_TABLE (MOD_0F73_REG_3) },
3539     { Bad_Opcode },
3540     { Bad_Opcode },
3541     { MOD_TABLE (MOD_0F73_REG_6) },
3542     { MOD_TABLE (MOD_0F73_REG_7) },
3543   },
3544   /* REG_0FA6 */
3545   {
3546     { "montmul",        { { OP_0f07, 0 } }, 0 },
3547     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3548     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3549   },
3550   /* REG_0FA7 */
3551   {
3552     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3553     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3554     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3555     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3556     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3557     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3558   },
3559   /* REG_0FAE */
3560   {
3561     { MOD_TABLE (MOD_0FAE_REG_0) },
3562     { MOD_TABLE (MOD_0FAE_REG_1) },
3563     { MOD_TABLE (MOD_0FAE_REG_2) },
3564     { MOD_TABLE (MOD_0FAE_REG_3) },
3565     { MOD_TABLE (MOD_0FAE_REG_4) },
3566     { MOD_TABLE (MOD_0FAE_REG_5) },
3567     { MOD_TABLE (MOD_0FAE_REG_6) },
3568     { MOD_TABLE (MOD_0FAE_REG_7) },
3569   },
3570   /* REG_0FBA */
3571   {
3572     { Bad_Opcode },
3573     { Bad_Opcode },
3574     { Bad_Opcode },
3575     { Bad_Opcode },
3576     { "btQ",    { Ev, Ib }, 0 },
3577     { "btsQ",   { Evh1, Ib }, 0 },
3578     { "btrQ",   { Evh1, Ib }, 0 },
3579     { "btcQ",   { Evh1, Ib }, 0 },
3580   },
3581   /* REG_0FC7 */
3582   {
3583     { Bad_Opcode },
3584     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3585     { Bad_Opcode },
3586     { MOD_TABLE (MOD_0FC7_REG_3) },
3587     { MOD_TABLE (MOD_0FC7_REG_4) },
3588     { MOD_TABLE (MOD_0FC7_REG_5) },
3589     { MOD_TABLE (MOD_0FC7_REG_6) },
3590     { MOD_TABLE (MOD_0FC7_REG_7) },
3591   },
3592   /* REG_VEX_0F71 */
3593   {
3594     { Bad_Opcode },
3595     { Bad_Opcode },
3596     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3597     { Bad_Opcode },
3598     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3599     { Bad_Opcode },
3600     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3601   },
3602   /* REG_VEX_0F72 */
3603   {
3604     { Bad_Opcode },
3605     { Bad_Opcode },
3606     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3607     { Bad_Opcode },
3608     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3609     { Bad_Opcode },
3610     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3611   },
3612   /* REG_VEX_0F73 */
3613   {
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3617     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3618     { Bad_Opcode },
3619     { Bad_Opcode },
3620     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3621     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3622   },
3623   /* REG_VEX_0FAE */
3624   {
3625     { Bad_Opcode },
3626     { Bad_Opcode },
3627     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3628     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3629   },
3630   /* REG_VEX_0F38F3 */
3631   {
3632     { Bad_Opcode },
3633     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3634     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3635     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3636   },
3637   /* REG_XOP_LWPCB */
3638   {
3639     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3640     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3641   },
3642   /* REG_XOP_LWP */
3643   {
3644     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3645     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3646   },
3647   /* REG_XOP_TBM_01 */
3648   {
3649     { Bad_Opcode },
3650     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3651     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3652     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3653     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3654     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3655     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3656     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3657   },
3658   /* REG_XOP_TBM_02 */
3659   {
3660     { Bad_Opcode },
3661     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3662     { Bad_Opcode },
3663     { Bad_Opcode },
3664     { Bad_Opcode },
3665     { Bad_Opcode },
3666     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3667   },
3668 #define NEED_REG_TABLE
3669 #include "i386-dis-evex.h"
3670 #undef NEED_REG_TABLE
3671 };
3672
3673 static const struct dis386 prefix_table[][4] = {
3674   /* PREFIX_90 */
3675   {
3676     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3677     { "pause", { XX }, 0 },
3678     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3679     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3680   },
3681
3682   /* PREFIX_0F10 */
3683   {
3684     { "movups", { XM, EXx }, PREFIX_OPCODE },
3685     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3686     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3687     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3688   },
3689
3690   /* PREFIX_0F11 */
3691   {
3692     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3693     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3694     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3695     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3696   },
3697
3698   /* PREFIX_0F12 */
3699   {
3700     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3701     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3702     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3703     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3704   },
3705
3706   /* PREFIX_0F16 */
3707   {
3708     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3709     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3710     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3711   },
3712
3713   /* PREFIX_0F1A */
3714   {
3715     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3716     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3717     { "bndmov", { Gbnd, Ebnd }, 0 },
3718     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3719   },
3720
3721   /* PREFIX_0F1B */
3722   {
3723     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3724     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3725     { "bndmov", { Ebnd, Gbnd }, 0 },
3726     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3727   },
3728
3729   /* PREFIX_0F2A */
3730   {
3731     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3732     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3733     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3734     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3735   },
3736
3737   /* PREFIX_0F2B */
3738   {
3739     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3740     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3741     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3742     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3743   },
3744
3745   /* PREFIX_0F2C */
3746   {
3747     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3748     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3749     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3750     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3751   },
3752
3753   /* PREFIX_0F2D */
3754   {
3755     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3756     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3757     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3758     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3759   },
3760
3761   /* PREFIX_0F2E */
3762   {
3763     { "ucomiss",{ XM, EXd }, 0 },
3764     { Bad_Opcode },
3765     { "ucomisd",{ XM, EXq }, 0 },
3766   },
3767
3768   /* PREFIX_0F2F */
3769   {
3770     { "comiss", { XM, EXd }, 0 },
3771     { Bad_Opcode },
3772     { "comisd", { XM, EXq }, 0 },
3773   },
3774
3775   /* PREFIX_0F51 */
3776   {
3777     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3778     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3779     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3780     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3781   },
3782
3783   /* PREFIX_0F52 */
3784   {
3785     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3786     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F53 */
3790   {
3791     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3792     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3793   },
3794
3795   /* PREFIX_0F58 */
3796   {
3797     { "addps", { XM, EXx }, PREFIX_OPCODE },
3798     { "addss", { XM, EXd }, PREFIX_OPCODE },
3799     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3800     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3801   },
3802
3803   /* PREFIX_0F59 */
3804   {
3805     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3806     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3807     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3808     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3809   },
3810
3811   /* PREFIX_0F5A */
3812   {
3813     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3814     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3815     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3816     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3817   },
3818
3819   /* PREFIX_0F5B */
3820   {
3821     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3822     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3823     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3824   },
3825
3826   /* PREFIX_0F5C */
3827   {
3828     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3829     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3830     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3831     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F5D */
3835   {
3836     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3837     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3838     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3839     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F5E */
3843   {
3844     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3845     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3846     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3847     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3848   },
3849
3850   /* PREFIX_0F5F */
3851   {
3852     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3853     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3854     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3855     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F60 */
3859   {
3860     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3861     { Bad_Opcode },
3862     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0F61 */
3866   {
3867     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3868     { Bad_Opcode },
3869     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3870   },
3871
3872   /* PREFIX_0F62 */
3873   {
3874     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3875     { Bad_Opcode },
3876     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3877   },
3878
3879   /* PREFIX_0F6C */
3880   {
3881     { Bad_Opcode },
3882     { Bad_Opcode },
3883     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3884   },
3885
3886   /* PREFIX_0F6D */
3887   {
3888     { Bad_Opcode },
3889     { Bad_Opcode },
3890     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3891   },
3892
3893   /* PREFIX_0F6F */
3894   {
3895     { "movq",   { MX, EM }, PREFIX_OPCODE },
3896     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3897     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3898   },
3899
3900   /* PREFIX_0F70 */
3901   {
3902     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3903     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3904     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3905     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3906   },
3907
3908   /* PREFIX_0F73_REG_3 */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { "psrldq", { XS, Ib }, 0 },
3913   },
3914
3915   /* PREFIX_0F73_REG_7 */
3916   {
3917     { Bad_Opcode },
3918     { Bad_Opcode },
3919     { "pslldq", { XS, Ib }, 0 },
3920   },
3921
3922   /* PREFIX_0F78 */
3923   {
3924     {"vmread",  { Em, Gm }, 0 },
3925     { Bad_Opcode },
3926     {"extrq",   { XS, Ib, Ib }, 0 },
3927     {"insertq", { XM, XS, Ib, Ib }, 0 },
3928   },
3929
3930   /* PREFIX_0F79 */
3931   {
3932     {"vmwrite", { Gm, Em }, 0 },
3933     { Bad_Opcode },
3934     {"extrq",   { XM, XS }, 0 },
3935     {"insertq", { XM, XS }, 0 },
3936   },
3937
3938   /* PREFIX_0F7C */
3939   {
3940     { Bad_Opcode },
3941     { Bad_Opcode },
3942     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3943     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3944   },
3945
3946   /* PREFIX_0F7D */
3947   {
3948     { Bad_Opcode },
3949     { Bad_Opcode },
3950     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3951     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3952   },
3953
3954   /* PREFIX_0F7E */
3955   {
3956     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3957     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3958     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3959   },
3960
3961   /* PREFIX_0F7F */
3962   {
3963     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3964     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3965     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3966   },
3967
3968   /* PREFIX_0FAE_REG_0 */
3969   {
3970     { Bad_Opcode },
3971     { "rdfsbase", { Ev }, 0 },
3972   },
3973
3974   /* PREFIX_0FAE_REG_1 */
3975   {
3976     { Bad_Opcode },
3977     { "rdgsbase", { Ev }, 0 },
3978   },
3979
3980   /* PREFIX_0FAE_REG_2 */
3981   {
3982     { Bad_Opcode },
3983     { "wrfsbase", { Ev }, 0 },
3984   },
3985
3986   /* PREFIX_0FAE_REG_3 */
3987   {
3988     { Bad_Opcode },
3989     { "wrgsbase", { Ev }, 0 },
3990   },
3991
3992   /* PREFIX_0FAE_REG_6 */
3993   {
3994     { "xsaveopt",      { FXSAVE }, 0 },
3995     { Bad_Opcode },
3996     { "clwb",   { Mb }, 0 },
3997   },
3998
3999   /* PREFIX_0FAE_REG_7 */
4000   {
4001     { "clflush",        { Mb }, 0 },
4002     { Bad_Opcode },
4003     { "clflushopt",     { Mb }, 0 },
4004   },
4005
4006   /* PREFIX_RM_0_0FAE_REG_7 */
4007   {
4008     { "sfence",         { Skip_MODRM }, 0 },
4009     { Bad_Opcode },
4010     { "pcommit",                { Skip_MODRM }, 0 },
4011   },
4012
4013   /* PREFIX_0FB8 */
4014   {
4015     { Bad_Opcode },
4016     { "popcntS", { Gv, Ev }, 0 },
4017   },
4018
4019   /* PREFIX_0FBC */
4020   {
4021     { "bsfS",   { Gv, Ev }, 0 },
4022     { "tzcntS", { Gv, Ev }, 0 },
4023     { "bsfS",   { Gv, Ev }, 0 },
4024   },
4025
4026   /* PREFIX_0FBD */
4027   {
4028     { "bsrS",   { Gv, Ev }, 0 },
4029     { "lzcntS", { Gv, Ev }, 0 },
4030     { "bsrS",   { Gv, Ev }, 0 },
4031   },
4032
4033   /* PREFIX_0FC2 */
4034   {
4035     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4036     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4037     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4038     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4039   },
4040
4041   /* PREFIX_0FC3 */
4042   {
4043     { "movntiS", { Ma, Gv }, PREFIX_OPCODE },
4044   },
4045
4046   /* PREFIX_MOD_0_0FC7_REG_6 */
4047   {
4048     { "vmptrld",{ Mq }, 0 },
4049     { "vmxon",  { Mq }, 0 },
4050     { "vmclear",{ Mq }, 0 },
4051   },
4052
4053   /* PREFIX_MOD_3_0FC7_REG_6 */
4054   {
4055     { "rdrand", { Ev }, 0 },
4056     { Bad_Opcode },
4057     { "rdrand", { Ev }, 0 }
4058   },
4059
4060   /* PREFIX_MOD_3_0FC7_REG_7 */
4061   {
4062     { "rdseed", { Ev }, 0 },
4063     { Bad_Opcode },
4064     { "rdseed", { Ev }, 0 },
4065   },
4066
4067   /* PREFIX_0FD0 */
4068   {
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { "addsubpd", { XM, EXx }, 0 },
4072     { "addsubps", { XM, EXx }, 0 },
4073   },
4074
4075   /* PREFIX_0FD6 */
4076   {
4077     { Bad_Opcode },
4078     { "movq2dq",{ XM, MS }, 0 },
4079     { "movq",   { EXqS, XM }, 0 },
4080     { "movdq2q",{ MX, XS }, 0 },
4081   },
4082
4083   /* PREFIX_0FE6 */
4084   {
4085     { Bad_Opcode },
4086     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4087     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4088     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4089   },
4090
4091   /* PREFIX_0FE7 */
4092   {
4093     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4094     { Bad_Opcode },
4095     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4096   },
4097
4098   /* PREFIX_0FF0 */
4099   {
4100     { Bad_Opcode },
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4104   },
4105
4106   /* PREFIX_0FF7 */
4107   {
4108     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4109     { Bad_Opcode },
4110     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0F3810 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4118   },
4119
4120   /* PREFIX_0F3814 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_0F3815 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F3817 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F3820 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0F3821 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4153   },
4154
4155   /* PREFIX_0F3822 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F3823 */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4167   },
4168
4169   /* PREFIX_0F3824 */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0F3825 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F3828 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4188   },
4189
4190   /* PREFIX_0F3829 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F382A */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4202   },
4203
4204   /* PREFIX_0F382B */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3830 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3831 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3832 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3833 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3834 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3835 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3837 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F3838 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F3839 */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4272   },
4273
4274   /* PREFIX_0F383A */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F383B */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4286   },
4287
4288   /* PREFIX_0F383C */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4293   },
4294
4295   /* PREFIX_0F383D */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F383E */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F383F */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F3840 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3841 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3880 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3881 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F3882 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F38C8 */
4352   {
4353     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F38C9 */
4357   {
4358     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F38CA */
4362   {
4363     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F38CB */
4367   {
4368     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F38CC */
4372   {
4373     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F38CD */
4377   {
4378     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4379   },
4380
4381   /* PREFIX_0F38DB */
4382   {
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38DC */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F38DD */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F38DE */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F38DF */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4414   },
4415
4416   /* PREFIX_0F38F0 */
4417   {
4418     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4419     { Bad_Opcode },
4420     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4421     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F38F1 */
4425   {
4426     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4427     { Bad_Opcode },
4428     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4429     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4430   },
4431
4432   /* PREFIX_0F38F6 */
4433   {
4434     { Bad_Opcode },
4435     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4436     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4437     { Bad_Opcode },
4438   },
4439
4440   /* PREFIX_0F3A08 */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4445   },
4446
4447   /* PREFIX_0F3A09 */
4448   {
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F3A0A */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F3A0B */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4466   },
4467
4468   /* PREFIX_0F3A0C */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F3A0D */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F3A0E */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F3A14 */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F3A15 */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F3A16 */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F3A17 */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3A20 */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3A21 */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A22 */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A40 */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A41 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A42 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A44 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A60 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A61 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A62 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A63 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3ACC */
4595   {
4596     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4597   },
4598
4599   /* PREFIX_0F3ADF */
4600   {
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4604   },
4605
4606   /* PREFIX_VEX_0F10 */
4607   {
4608     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4609     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4610     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4611     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4612   },
4613
4614   /* PREFIX_VEX_0F11 */
4615   {
4616     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4617     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4618     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4619     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4620   },
4621
4622   /* PREFIX_VEX_0F12 */
4623   {
4624     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4625     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4626     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4627     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4628   },
4629
4630   /* PREFIX_VEX_0F16 */
4631   {
4632     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4633     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4634     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4635   },
4636
4637   /* PREFIX_VEX_0F2A */
4638   {
4639     { Bad_Opcode },
4640     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4641     { Bad_Opcode },
4642     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4643   },
4644
4645   /* PREFIX_VEX_0F2C */
4646   {
4647     { Bad_Opcode },
4648     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4649     { Bad_Opcode },
4650     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4651   },
4652
4653   /* PREFIX_VEX_0F2D */
4654   {
4655     { Bad_Opcode },
4656     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4657     { Bad_Opcode },
4658     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4659   },
4660
4661   /* PREFIX_VEX_0F2E */
4662   {
4663     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4664     { Bad_Opcode },
4665     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4666   },
4667
4668   /* PREFIX_VEX_0F2F */
4669   {
4670     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4671     { Bad_Opcode },
4672     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4673   },
4674
4675   /* PREFIX_VEX_0F41 */
4676   {
4677     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4678     { Bad_Opcode },
4679     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4680   },
4681
4682   /* PREFIX_VEX_0F42 */
4683   {
4684     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4685     { Bad_Opcode },
4686     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4687   },
4688
4689   /* PREFIX_VEX_0F44 */
4690   {
4691     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4692     { Bad_Opcode },
4693     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4694   },
4695
4696   /* PREFIX_VEX_0F45 */
4697   {
4698     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4699     { Bad_Opcode },
4700     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4701   },
4702
4703   /* PREFIX_VEX_0F46 */
4704   {
4705     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4706     { Bad_Opcode },
4707     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4708   },
4709
4710   /* PREFIX_VEX_0F47 */
4711   {
4712     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4713     { Bad_Opcode },
4714     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4715   },
4716
4717   /* PREFIX_VEX_0F4A */
4718   {
4719     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4720     { Bad_Opcode },
4721     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4722   },
4723
4724   /* PREFIX_VEX_0F4B */
4725   {
4726     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4727     { Bad_Opcode },
4728     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4729   },
4730
4731   /* PREFIX_VEX_0F51 */
4732   {
4733     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4734     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4735     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4736     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4737   },
4738
4739   /* PREFIX_VEX_0F52 */
4740   {
4741     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4742     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4743   },
4744
4745   /* PREFIX_VEX_0F53 */
4746   {
4747     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4748     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4749   },
4750
4751   /* PREFIX_VEX_0F58 */
4752   {
4753     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4754     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4755     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4756     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4757   },
4758
4759   /* PREFIX_VEX_0F59 */
4760   {
4761     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4762     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4763     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4764     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4765   },
4766
4767   /* PREFIX_VEX_0F5A */
4768   {
4769     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4770     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4771     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4772     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4773   },
4774
4775   /* PREFIX_VEX_0F5B */
4776   {
4777     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4778     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4779     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4780   },
4781
4782   /* PREFIX_VEX_0F5C */
4783   {
4784     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4785     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4786     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4787     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4788   },
4789
4790   /* PREFIX_VEX_0F5D */
4791   {
4792     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4793     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4794     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4795     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4796   },
4797
4798   /* PREFIX_VEX_0F5E */
4799   {
4800     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4801     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4802     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4803     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4804   },
4805
4806   /* PREFIX_VEX_0F5F */
4807   {
4808     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4809     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4810     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4811     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4812   },
4813
4814   /* PREFIX_VEX_0F60 */
4815   {
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4819   },
4820
4821   /* PREFIX_VEX_0F61 */
4822   {
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4826   },
4827
4828   /* PREFIX_VEX_0F62 */
4829   {
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4833   },
4834
4835   /* PREFIX_VEX_0F63 */
4836   {
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4840   },
4841
4842   /* PREFIX_VEX_0F64 */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4847   },
4848
4849   /* PREFIX_VEX_0F65 */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4854   },
4855
4856   /* PREFIX_VEX_0F66 */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4861   },
4862
4863   /* PREFIX_VEX_0F67 */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4868   },
4869
4870   /* PREFIX_VEX_0F68 */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4875   },
4876
4877   /* PREFIX_VEX_0F69 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4882   },
4883
4884   /* PREFIX_VEX_0F6A */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4889   },
4890
4891   /* PREFIX_VEX_0F6B */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4896   },
4897
4898   /* PREFIX_VEX_0F6C */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4903   },
4904
4905   /* PREFIX_VEX_0F6D */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4910   },
4911
4912   /* PREFIX_VEX_0F6E */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4917   },
4918
4919   /* PREFIX_VEX_0F6F */
4920   {
4921     { Bad_Opcode },
4922     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4923     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4924   },
4925
4926   /* PREFIX_VEX_0F70 */
4927   {
4928     { Bad_Opcode },
4929     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4930     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4931     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4932   },
4933
4934   /* PREFIX_VEX_0F71_REG_2 */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_0F71_REG_4 */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_0F71_REG_6 */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_0F72_REG_2 */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_0F72_REG_4 */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_0F72_REG_6 */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_0F73_REG_2 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_0F73_REG_3 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_0F73_REG_6 */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_0F73_REG_7 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5002   },
5003
5004   /* PREFIX_VEX_0F74 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_0F75 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_0F76 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_0F77 */
5026   {
5027     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5028   },
5029
5030   /* PREFIX_VEX_0F7C */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5035     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5036   },
5037
5038   /* PREFIX_VEX_0F7D */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5043     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5044   },
5045
5046   /* PREFIX_VEX_0F7E */
5047   {
5048     { Bad_Opcode },
5049     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5050     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_0F7F */
5054   {
5055     { Bad_Opcode },
5056     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5057     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_0F90 */
5061   {
5062     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5063     { Bad_Opcode },
5064     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_0F91 */
5068   {
5069     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5070     { Bad_Opcode },
5071     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_0F92 */
5075   {
5076     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5077     { Bad_Opcode },
5078     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5079     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5080   },
5081
5082   /* PREFIX_VEX_0F93 */
5083   {
5084     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5085     { Bad_Opcode },
5086     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5087     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5088   },
5089
5090   /* PREFIX_VEX_0F98 */
5091   {
5092     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5093     { Bad_Opcode },
5094     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5095   },
5096
5097   /* PREFIX_VEX_0F99 */
5098   {
5099     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5100     { Bad_Opcode },
5101     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0FC2 */
5105   {
5106     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5107     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5108     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5109     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5110   },
5111
5112   /* PREFIX_VEX_0FC4 */
5113   {
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5117   },
5118
5119   /* PREFIX_VEX_0FC5 */
5120   {
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5124   },
5125
5126   /* PREFIX_VEX_0FD0 */
5127   {
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5131     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5132   },
5133
5134   /* PREFIX_VEX_0FD1 */
5135   {
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5139   },
5140
5141   /* PREFIX_VEX_0FD2 */
5142   {
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5146   },
5147
5148   /* PREFIX_VEX_0FD3 */
5149   {
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5153   },
5154
5155   /* PREFIX_VEX_0FD4 */
5156   {
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5160   },
5161
5162   /* PREFIX_VEX_0FD5 */
5163   {
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0FD6 */
5170   {
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5174   },
5175
5176   /* PREFIX_VEX_0FD7 */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5181   },
5182
5183   /* PREFIX_VEX_0FD8 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5188   },
5189
5190   /* PREFIX_VEX_0FD9 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5195   },
5196
5197   /* PREFIX_VEX_0FDA */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5202   },
5203
5204   /* PREFIX_VEX_0FDB */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5209   },
5210
5211   /* PREFIX_VEX_0FDC */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5216   },
5217
5218   /* PREFIX_VEX_0FDD */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5223   },
5224
5225   /* PREFIX_VEX_0FDE */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0FDF */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0FE0 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0FE1 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5251   },
5252
5253   /* PREFIX_VEX_0FE2 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0FE3 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0FE4 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5272   },
5273
5274   /* PREFIX_VEX_0FE5 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5279   },
5280
5281   /* PREFIX_VEX_0FE6 */
5282   {
5283     { Bad_Opcode },
5284     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5285     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5286     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5287   },
5288
5289   /* PREFIX_VEX_0FE7 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5294   },
5295
5296   /* PREFIX_VEX_0FE8 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5301   },
5302
5303   /* PREFIX_VEX_0FE9 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0FEA */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0FEB */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5322   },
5323
5324   /* PREFIX_VEX_0FEC */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5329   },
5330
5331   /* PREFIX_VEX_0FED */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5336   },
5337
5338   /* PREFIX_VEX_0FEE */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5343   },
5344
5345   /* PREFIX_VEX_0FEF */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5350   },
5351
5352   /* PREFIX_VEX_0FF0 */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5358   },
5359
5360   /* PREFIX_VEX_0FF1 */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5365   },
5366
5367   /* PREFIX_VEX_0FF2 */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5372   },
5373
5374   /* PREFIX_VEX_0FF3 */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5379   },
5380
5381   /* PREFIX_VEX_0FF4 */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5386   },
5387
5388   /* PREFIX_VEX_0FF5 */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5393   },
5394
5395   /* PREFIX_VEX_0FF6 */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5400   },
5401
5402   /* PREFIX_VEX_0FF7 */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5407   },
5408
5409   /* PREFIX_VEX_0FF8 */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5414   },
5415
5416   /* PREFIX_VEX_0FF9 */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5421   },
5422
5423   /* PREFIX_VEX_0FFA */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5428   },
5429
5430   /* PREFIX_VEX_0FFB */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5435   },
5436
5437   /* PREFIX_VEX_0FFC */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5442   },
5443
5444   /* PREFIX_VEX_0FFD */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5449   },
5450
5451   /* PREFIX_VEX_0FFE */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5456   },
5457
5458   /* PREFIX_VEX_0F3800 */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5463   },
5464
5465   /* PREFIX_VEX_0F3801 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0F3802 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5477   },
5478
5479   /* PREFIX_VEX_0F3803 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5484   },
5485
5486   /* PREFIX_VEX_0F3804 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0F3805 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0F3806 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5505   },
5506
5507   /* PREFIX_VEX_0F3807 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0F3808 */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5519   },
5520
5521   /* PREFIX_VEX_0F3809 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5526   },
5527
5528   /* PREFIX_VEX_0F380A */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5533   },
5534
5535   /* PREFIX_VEX_0F380B */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5540   },
5541
5542   /* PREFIX_VEX_0F380C */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5547   },
5548
5549   /* PREFIX_VEX_0F380D */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5554   },
5555
5556   /* PREFIX_VEX_0F380E */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5561   },
5562
5563   /* PREFIX_VEX_0F380F */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5568   },
5569
5570   /* PREFIX_VEX_0F3813 */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5575   },
5576
5577   /* PREFIX_VEX_0F3816 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F3817 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F3818 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F3819 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F381A */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F381C */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F381D */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F381E */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F3820 */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F3821 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F3822 */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0F3823 */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5659   },
5660
5661   /* PREFIX_VEX_0F3824 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0F3825 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5673   },
5674
5675   /* PREFIX_VEX_0F3828 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5680   },
5681
5682   /* PREFIX_VEX_0F3829 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5687   },
5688
5689   /* PREFIX_VEX_0F382A */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5694   },
5695
5696   /* PREFIX_VEX_0F382B */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5701   },
5702
5703   /* PREFIX_VEX_0F382C */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5708   },
5709
5710   /* PREFIX_VEX_0F382D */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5715   },
5716
5717   /* PREFIX_VEX_0F382E */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5722   },
5723
5724   /* PREFIX_VEX_0F382F */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5729   },
5730
5731   /* PREFIX_VEX_0F3830 */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F3831 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F3832 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F3833 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F3834 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F3835 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F3836 */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F3837 */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F3838 */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F3839 */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5799   },
5800
5801   /* PREFIX_VEX_0F383A */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F383B */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F383C */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5820   },
5821
5822   /* PREFIX_VEX_0F383D */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5827   },
5828
5829   /* PREFIX_VEX_0F383E */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5834   },
5835
5836   /* PREFIX_VEX_0F383F */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5841   },
5842
5843   /* PREFIX_VEX_0F3840 */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5848   },
5849
5850   /* PREFIX_VEX_0F3841 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5855   },
5856
5857   /* PREFIX_VEX_0F3845 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5862   },
5863
5864   /* PREFIX_VEX_0F3846 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5869   },
5870
5871   /* PREFIX_VEX_0F3847 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5876   },
5877
5878   /* PREFIX_VEX_0F3858 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5883   },
5884
5885   /* PREFIX_VEX_0F3859 */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F385A */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F3878 */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F3879 */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F388C */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F388E */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F3890 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5932   },
5933
5934   /* PREFIX_VEX_0F3891 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5939   },
5940
5941   /* PREFIX_VEX_0F3892 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5946   },
5947
5948   /* PREFIX_VEX_0F3893 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5953   },
5954
5955   /* PREFIX_VEX_0F3896 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5960   },
5961
5962   /* PREFIX_VEX_0F3897 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5967   },
5968
5969   /* PREFIX_VEX_0F3898 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5974   },
5975
5976   /* PREFIX_VEX_0F3899 */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5981   },
5982
5983   /* PREFIX_VEX_0F389A */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5988   },
5989
5990   /* PREFIX_VEX_0F389B */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5995   },
5996
5997   /* PREFIX_VEX_0F389C */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F389D */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F389E */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F389F */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F38A6 */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6030     { Bad_Opcode },
6031   },
6032
6033   /* PREFIX_VEX_0F38A7 */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F38A8 */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F38A9 */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F38AA */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6059   },
6060
6061   /* PREFIX_VEX_0F38AB */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F38AC */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F38AD */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F38AE */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F38AF */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6094   },
6095
6096   /* PREFIX_VEX_0F38B6 */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6101   },
6102
6103   /* PREFIX_VEX_0F38B7 */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6108   },
6109
6110   /* PREFIX_VEX_0F38B8 */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6115   },
6116
6117   /* PREFIX_VEX_0F38B9 */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F38BA */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38BB */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38BC */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38BD */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38BE */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38BF */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38DB */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6171   },
6172
6173   /* PREFIX_VEX_0F38DC */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6178   },
6179
6180   /* PREFIX_VEX_0F38DD */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6185   },
6186
6187   /* PREFIX_VEX_0F38DE */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6192   },
6193
6194   /* PREFIX_VEX_0F38DF */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6199   },
6200
6201   /* PREFIX_VEX_0F38F2 */
6202   {
6203     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6204   },
6205
6206   /* PREFIX_VEX_0F38F3_REG_1 */
6207   {
6208     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6209   },
6210
6211   /* PREFIX_VEX_0F38F3_REG_2 */
6212   {
6213     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6214   },
6215
6216   /* PREFIX_VEX_0F38F3_REG_3 */
6217   {
6218     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6219   },
6220
6221   /* PREFIX_VEX_0F38F5 */
6222   {
6223     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6224     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6225     { Bad_Opcode },
6226     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6227   },
6228
6229   /* PREFIX_VEX_0F38F6 */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6235   },
6236
6237   /* PREFIX_VEX_0F38F7 */
6238   {
6239     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6240     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6241     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6242     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6243   },
6244
6245   /* PREFIX_VEX_0F3A00 */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6250   },
6251
6252   /* PREFIX_VEX_0F3A01 */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6257   },
6258
6259   /* PREFIX_VEX_0F3A02 */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6264   },
6265
6266   /* PREFIX_VEX_0F3A04 */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6271   },
6272
6273   /* PREFIX_VEX_0F3A05 */
6274   {
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6278   },
6279
6280   /* PREFIX_VEX_0F3A06 */
6281   {
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6285   },
6286
6287   /* PREFIX_VEX_0F3A08 */
6288   {
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6292   },
6293
6294   /* PREFIX_VEX_0F3A09 */
6295   {
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6299   },
6300
6301   /* PREFIX_VEX_0F3A0A */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6306   },
6307
6308   /* PREFIX_VEX_0F3A0B */
6309   {
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6313   },
6314
6315   /* PREFIX_VEX_0F3A0C */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6320   },
6321
6322   /* PREFIX_VEX_0F3A0D */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6327   },
6328
6329   /* PREFIX_VEX_0F3A0E */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A0F */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6341   },
6342
6343   /* PREFIX_VEX_0F3A14 */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6348   },
6349
6350   /* PREFIX_VEX_0F3A15 */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A16 */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6362   },
6363
6364   /* PREFIX_VEX_0F3A17 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6369   },
6370
6371   /* PREFIX_VEX_0F3A18 */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3A19 */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3A1D */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6390   },
6391
6392   /* PREFIX_VEX_0F3A20 */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6397   },
6398
6399   /* PREFIX_VEX_0F3A21 */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6404   },
6405
6406   /* PREFIX_VEX_0F3A22 */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6411   },
6412
6413   /* PREFIX_VEX_0F3A30 */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A31 */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A32 */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A33 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A38 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A39 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A40 */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6460   },
6461
6462   /* PREFIX_VEX_0F3A41 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A42 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A44 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A46 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A48 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A49 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A4A */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A4B */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A4C */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A5C */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6530   },
6531
6532   /* PREFIX_VEX_0F3A5D */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6537   },
6538
6539   /* PREFIX_VEX_0F3A5E */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6544   },
6545
6546   /* PREFIX_VEX_0F3A5F */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6551   },
6552
6553   /* PREFIX_VEX_0F3A60 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6558     { Bad_Opcode },
6559   },
6560
6561   /* PREFIX_VEX_0F3A61 */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6566   },
6567
6568   /* PREFIX_VEX_0F3A62 */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6573   },
6574
6575   /* PREFIX_VEX_0F3A63 */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6580   },
6581
6582   /* PREFIX_VEX_0F3A68 */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6587   },
6588
6589   /* PREFIX_VEX_0F3A69 */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6594   },
6595
6596   /* PREFIX_VEX_0F3A6A */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6601   },
6602
6603   /* PREFIX_VEX_0F3A6B */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6608   },
6609
6610   /* PREFIX_VEX_0F3A6C */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6615   },
6616
6617   /* PREFIX_VEX_0F3A6D */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6622   },
6623
6624   /* PREFIX_VEX_0F3A6E */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6629   },
6630
6631   /* PREFIX_VEX_0F3A6F */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6636   },
6637
6638   /* PREFIX_VEX_0F3A78 */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6643   },
6644
6645   /* PREFIX_VEX_0F3A79 */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6650   },
6651
6652   /* PREFIX_VEX_0F3A7A */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6657   },
6658
6659   /* PREFIX_VEX_0F3A7B */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6664   },
6665
6666   /* PREFIX_VEX_0F3A7C */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6671     { Bad_Opcode },
6672   },
6673
6674   /* PREFIX_VEX_0F3A7D */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6679   },
6680
6681   /* PREFIX_VEX_0F3A7E */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6686   },
6687
6688   /* PREFIX_VEX_0F3A7F */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6693   },
6694
6695   /* PREFIX_VEX_0F3ADF */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6700   },
6701
6702   /* PREFIX_VEX_0F3AF0 */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6708   },
6709
6710 #define NEED_PREFIX_TABLE
6711 #include "i386-dis-evex.h"
6712 #undef NEED_PREFIX_TABLE
6713 };
6714
6715 static const struct dis386 x86_64_table[][2] = {
6716   /* X86_64_06 */
6717   {
6718     { "pushP", { es }, 0 },
6719   },
6720
6721   /* X86_64_07 */
6722   {
6723     { "popP", { es }, 0 },
6724   },
6725
6726   /* X86_64_0D */
6727   {
6728     { "pushP", { cs }, 0 },
6729   },
6730
6731   /* X86_64_16 */
6732   {
6733     { "pushP", { ss }, 0 },
6734   },
6735
6736   /* X86_64_17 */
6737   {
6738     { "popP", { ss }, 0 },
6739   },
6740
6741   /* X86_64_1E */
6742   {
6743     { "pushP", { ds }, 0 },
6744   },
6745
6746   /* X86_64_1F */
6747   {
6748     { "popP", { ds }, 0 },
6749   },
6750
6751   /* X86_64_27 */
6752   {
6753     { "daa", { XX }, 0 },
6754   },
6755
6756   /* X86_64_2F */
6757   {
6758     { "das", { XX }, 0 },
6759   },
6760
6761   /* X86_64_37 */
6762   {
6763     { "aaa", { XX }, 0 },
6764   },
6765
6766   /* X86_64_3F */
6767   {
6768     { "aas", { XX }, 0 },
6769   },
6770
6771   /* X86_64_60 */
6772   {
6773     { "pushaP", { XX }, 0 },
6774   },
6775
6776   /* X86_64_61 */
6777   {
6778     { "popaP", { XX }, 0 },
6779   },
6780
6781   /* X86_64_62 */
6782   {
6783     { MOD_TABLE (MOD_62_32BIT) },
6784     { EVEX_TABLE (EVEX_0F) },
6785   },
6786
6787   /* X86_64_63 */
6788   {
6789     { "arpl", { Ew, Gw }, 0 },
6790     { "movs{lq|xd}", { Gv, Ed }, 0 },
6791   },
6792
6793   /* X86_64_6D */
6794   {
6795     { "ins{R|}", { Yzr, indirDX }, 0 },
6796     { "ins{G|}", { Yzr, indirDX }, 0 },
6797   },
6798
6799   /* X86_64_6F */
6800   {
6801     { "outs{R|}", { indirDXr, Xz }, 0 },
6802     { "outs{G|}", { indirDXr, Xz }, 0 },
6803   },
6804
6805   /* X86_64_9A */
6806   {
6807     { "Jcall{T|}", { Ap }, 0 },
6808   },
6809
6810   /* X86_64_C4 */
6811   {
6812     { MOD_TABLE (MOD_C4_32BIT) },
6813     { VEX_C4_TABLE (VEX_0F) },
6814   },
6815
6816   /* X86_64_C5 */
6817   {
6818     { MOD_TABLE (MOD_C5_32BIT) },
6819     { VEX_C5_TABLE (VEX_0F) },
6820   },
6821
6822   /* X86_64_CE */
6823   {
6824     { "into", { XX }, 0 },
6825   },
6826
6827   /* X86_64_D4 */
6828   {
6829     { "aam", { Ib }, 0 },
6830   },
6831
6832   /* X86_64_D5 */
6833   {
6834     { "aad", { Ib }, 0 },
6835   },
6836
6837   /* X86_64_EA */
6838   {
6839     { "Jjmp{T|}", { Ap }, 0 },
6840   },
6841
6842   /* X86_64_0F01_REG_0 */
6843   {
6844     { "sgdt{Q|IQ}", { M }, 0 },
6845     { "sgdt", { M }, 0 },
6846   },
6847
6848   /* X86_64_0F01_REG_1 */
6849   {
6850     { "sidt{Q|IQ}", { M }, 0 },
6851     { "sidt", { M }, 0 },
6852   },
6853
6854   /* X86_64_0F01_REG_2 */
6855   {
6856     { "lgdt{Q|Q}", { M }, 0 },
6857     { "lgdt", { M }, 0 },
6858   },
6859
6860   /* X86_64_0F01_REG_3 */
6861   {
6862     { "lidt{Q|Q}", { M }, 0 },
6863     { "lidt", { M }, 0 },
6864   },
6865 };
6866
6867 static const struct dis386 three_byte_table[][256] = {
6868
6869   /* THREE_BYTE_0F38 */
6870   {
6871     /* 00 */
6872     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6873     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6874     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6875     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6876     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6877     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6878     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6879     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6880     /* 08 */
6881     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6882     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6883     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6884     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     /* 10 */
6890     { PREFIX_TABLE (PREFIX_0F3810) },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { PREFIX_TABLE (PREFIX_0F3814) },
6895     { PREFIX_TABLE (PREFIX_0F3815) },
6896     { Bad_Opcode },
6897     { PREFIX_TABLE (PREFIX_0F3817) },
6898     /* 18 */
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6904     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6905     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6906     { Bad_Opcode },
6907     /* 20 */
6908     { PREFIX_TABLE (PREFIX_0F3820) },
6909     { PREFIX_TABLE (PREFIX_0F3821) },
6910     { PREFIX_TABLE (PREFIX_0F3822) },
6911     { PREFIX_TABLE (PREFIX_0F3823) },
6912     { PREFIX_TABLE (PREFIX_0F3824) },
6913     { PREFIX_TABLE (PREFIX_0F3825) },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     /* 28 */
6917     { PREFIX_TABLE (PREFIX_0F3828) },
6918     { PREFIX_TABLE (PREFIX_0F3829) },
6919     { PREFIX_TABLE (PREFIX_0F382A) },
6920     { PREFIX_TABLE (PREFIX_0F382B) },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     /* 30 */
6926     { PREFIX_TABLE (PREFIX_0F3830) },
6927     { PREFIX_TABLE (PREFIX_0F3831) },
6928     { PREFIX_TABLE (PREFIX_0F3832) },
6929     { PREFIX_TABLE (PREFIX_0F3833) },
6930     { PREFIX_TABLE (PREFIX_0F3834) },
6931     { PREFIX_TABLE (PREFIX_0F3835) },
6932     { Bad_Opcode },
6933     { PREFIX_TABLE (PREFIX_0F3837) },
6934     /* 38 */
6935     { PREFIX_TABLE (PREFIX_0F3838) },
6936     { PREFIX_TABLE (PREFIX_0F3839) },
6937     { PREFIX_TABLE (PREFIX_0F383A) },
6938     { PREFIX_TABLE (PREFIX_0F383B) },
6939     { PREFIX_TABLE (PREFIX_0F383C) },
6940     { PREFIX_TABLE (PREFIX_0F383D) },
6941     { PREFIX_TABLE (PREFIX_0F383E) },
6942     { PREFIX_TABLE (PREFIX_0F383F) },
6943     /* 40 */
6944     { PREFIX_TABLE (PREFIX_0F3840) },
6945     { PREFIX_TABLE (PREFIX_0F3841) },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* 48 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 50 */
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* 58 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* 60 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 68 */
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* 70 */
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 78 */
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 80 */
7016     { PREFIX_TABLE (PREFIX_0F3880) },
7017     { PREFIX_TABLE (PREFIX_0F3881) },
7018     { PREFIX_TABLE (PREFIX_0F3882) },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* 88 */
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* 90 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* 98 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* a0 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* a8 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* b0 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* b8 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* c0 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* c8 */
7097     { PREFIX_TABLE (PREFIX_0F38C8) },
7098     { PREFIX_TABLE (PREFIX_0F38C9) },
7099     { PREFIX_TABLE (PREFIX_0F38CA) },
7100     { PREFIX_TABLE (PREFIX_0F38CB) },
7101     { PREFIX_TABLE (PREFIX_0F38CC) },
7102     { PREFIX_TABLE (PREFIX_0F38CD) },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* d0 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* d8 */
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { PREFIX_TABLE (PREFIX_0F38DB) },
7119     { PREFIX_TABLE (PREFIX_0F38DC) },
7120     { PREFIX_TABLE (PREFIX_0F38DD) },
7121     { PREFIX_TABLE (PREFIX_0F38DE) },
7122     { PREFIX_TABLE (PREFIX_0F38DF) },
7123     /* e0 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     /* e8 */
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     /* f0 */
7142     { PREFIX_TABLE (PREFIX_0F38F0) },
7143     { PREFIX_TABLE (PREFIX_0F38F1) },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { PREFIX_TABLE (PREFIX_0F38F6) },
7149     { Bad_Opcode },
7150     /* f8 */
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159   },
7160   /* THREE_BYTE_0F3A */
7161   {
7162     /* 00 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* 08 */
7172     { PREFIX_TABLE (PREFIX_0F3A08) },
7173     { PREFIX_TABLE (PREFIX_0F3A09) },
7174     { PREFIX_TABLE (PREFIX_0F3A0A) },
7175     { PREFIX_TABLE (PREFIX_0F3A0B) },
7176     { PREFIX_TABLE (PREFIX_0F3A0C) },
7177     { PREFIX_TABLE (PREFIX_0F3A0D) },
7178     { PREFIX_TABLE (PREFIX_0F3A0E) },
7179     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7180     /* 10 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { PREFIX_TABLE (PREFIX_0F3A14) },
7186     { PREFIX_TABLE (PREFIX_0F3A15) },
7187     { PREFIX_TABLE (PREFIX_0F3A16) },
7188     { PREFIX_TABLE (PREFIX_0F3A17) },
7189     /* 18 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* 20 */
7199     { PREFIX_TABLE (PREFIX_0F3A20) },
7200     { PREFIX_TABLE (PREFIX_0F3A21) },
7201     { PREFIX_TABLE (PREFIX_0F3A22) },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* 28 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* 30 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* 38 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* 40 */
7235     { PREFIX_TABLE (PREFIX_0F3A40) },
7236     { PREFIX_TABLE (PREFIX_0F3A41) },
7237     { PREFIX_TABLE (PREFIX_0F3A42) },
7238     { Bad_Opcode },
7239     { PREFIX_TABLE (PREFIX_0F3A44) },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* 48 */
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* 50 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* 58 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* 60 */
7271     { PREFIX_TABLE (PREFIX_0F3A60) },
7272     { PREFIX_TABLE (PREFIX_0F3A61) },
7273     { PREFIX_TABLE (PREFIX_0F3A62) },
7274     { PREFIX_TABLE (PREFIX_0F3A63) },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* 68 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 70 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 78 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 80 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* 88 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* 90 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* 98 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* a0 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* a8 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* b0 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* b8 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* c0 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* c8 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { PREFIX_TABLE (PREFIX_0F3ACC) },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* d0 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* d8 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { PREFIX_TABLE (PREFIX_0F3ADF) },
7414     /* e0 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* e8 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     /* f0 */
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     /* f8 */
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450   },
7451
7452   /* THREE_BYTE_0F7A */
7453   {
7454     /* 00 */
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     /* 08 */
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     /* 10 */
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     /* 18 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* 20 */
7491     { "ptest",          { XX }, PREFIX_OPCODE },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     /* 28 */
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     /* 30 */
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     /* 38 */
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     /* 40 */
7527     { Bad_Opcode },
7528     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7529     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7530     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7534     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7535     /* 48 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* 50 */
7545     { Bad_Opcode },
7546     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7547     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7548     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7552     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7553     /* 58 */
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* 60 */
7563     { Bad_Opcode },
7564     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7565     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7566     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     /* 68 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     /* 70 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* 78 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* 80 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* 88 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* 90 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* 98 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* a0 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* a8 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* b0 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* b8 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* c0 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     /* c8 */
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     /* d0 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     /* d8 */
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     /* e0 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     /* e8 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     /* f0 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     /* f8 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742   },
7743 };
7744
7745 static const struct dis386 xop_table[][256] = {
7746   /* XOP_08 */
7747   {
7748     /* 00 */
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     /* 08 */
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     /* 10 */
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     /* 18 */
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     /* 20 */
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     /* 28 */
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     /* 30 */
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     /* 38 */
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     /* 40 */
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     /* 48 */
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     /* 50 */
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     /* 58 */
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     /* 60 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     /* 68 */
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     /* 70 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     /* 78 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     /* 80 */
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7899     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7900     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7901     /* 88 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7909     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7910     /* 90 */
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7917     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7918     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7919     /* 98 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7927     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7928     /* a0 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7932     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7936     { Bad_Opcode },
7937     /* a8 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* b0 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7954     { Bad_Opcode },
7955     /* b8 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* c0 */
7965     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7966     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7967     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7968     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* c8 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7979     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7980     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7981     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7982     /* d0 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* d8 */
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* e0 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     /* e8 */
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8015     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8016     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8017     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8018     /* f0 */
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     /* f8 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036   },
8037   /* XOP_09 */
8038   {
8039     /* 00 */
8040     { Bad_Opcode },
8041     { REG_TABLE (REG_XOP_TBM_01) },
8042     { REG_TABLE (REG_XOP_TBM_02) },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     /* 08 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     /* 10 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { REG_TABLE (REG_XOP_LWPCB) },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     /* 18 */
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     /* 20 */
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     /* 28 */
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     /* 30 */
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     /* 38 */
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     /* 40 */
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     /* 48 */
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     /* 50 */
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     /* 58 */
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     /* 60 */
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     /* 68 */
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     /* 70 */
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     /* 78 */
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     /* 80 */
8184     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8185     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8186     { "vfrczss",        { XM, EXd }, 0 },
8187     { "vfrczsd",        { XM, EXq }, 0 },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     /* 88 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* 90 */
8202     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8203     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8204     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8205     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8206     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8207     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8208     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8209     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8210     /* 98 */
8211     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8212     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8213     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8214     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* a0 */
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* a8 */
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     /* b0 */
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* b8 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     /* c0 */
8256     { Bad_Opcode },
8257     { "vphaddbw",       { XM, EXxmm }, 0 },
8258     { "vphaddbd",       { XM, EXxmm }, 0 },
8259     { "vphaddbq",       { XM, EXxmm }, 0 },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { "vphaddwd",       { XM, EXxmm }, 0 },
8263     { "vphaddwq",       { XM, EXxmm }, 0 },
8264     /* c8 */
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { "vphadddq",       { XM, EXxmm }, 0 },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     /* d0 */
8274     { Bad_Opcode },
8275     { "vphaddubw",      { XM, EXxmm }, 0 },
8276     { "vphaddubd",      { XM, EXxmm }, 0 },
8277     { "vphaddubq",      { XM, EXxmm }, 0 },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { "vphadduwd",      { XM, EXxmm }, 0 },
8281     { "vphadduwq",      { XM, EXxmm }, 0 },
8282     /* d8 */
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { "vphaddudq",      { XM, EXxmm }, 0 },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     /* e0 */
8292     { Bad_Opcode },
8293     { "vphsubbw",       { XM, EXxmm }, 0 },
8294     { "vphsubwd",       { XM, EXxmm }, 0 },
8295     { "vphsubdq",       { XM, EXxmm }, 0 },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* e8 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* f0 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* f8 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327   },
8328   /* XOP_0A */
8329   {
8330     /* 00 */
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     /* 08 */
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     /* 10 */
8349     { "bextr",  { Gv, Ev, Iq }, 0 },
8350     { Bad_Opcode },
8351     { REG_TABLE (REG_XOP_LWP) },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     /* 18 */
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     /* 20 */
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     /* 28 */
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     /* 30 */
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     /* 38 */
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     /* 40 */
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     /* 48 */
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     /* 50 */
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     /* 58 */
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     /* 60 */
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     /* 68 */
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     /* 70 */
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     /* 78 */
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     /* 80 */
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     /* 88 */
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     /* 90 */
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     /* 98 */
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     /* a0 */
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     /* a8 */
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     /* b0 */
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     /* b8 */
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     /* c0 */
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     /* c8 */
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     /* d0 */
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     /* d8 */
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     /* e0 */
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     /* e8 */
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     /* f0 */
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     /* f8 */
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618   },
8619 };
8620
8621 static const struct dis386 vex_table[][256] = {
8622   /* VEX_0F */
8623   {
8624     /* 00 */
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     /* 08 */
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     /* 10 */
8643     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8646     { MOD_TABLE (MOD_VEX_0F13) },
8647     { VEX_W_TABLE (VEX_W_0F14) },
8648     { VEX_W_TABLE (VEX_W_0F15) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8650     { MOD_TABLE (MOD_VEX_0F17) },
8651     /* 18 */
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     /* 20 */
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     /* 28 */
8670     { VEX_W_TABLE (VEX_W_0F28) },
8671     { VEX_W_TABLE (VEX_W_0F29) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8673     { MOD_TABLE (MOD_VEX_0F2B) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8677     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8678     /* 30 */
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     /* 38 */
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     /* 40 */
8697     { Bad_Opcode },
8698     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8700     { Bad_Opcode },
8701     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8705     /* 48 */
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     /* 50 */
8715     { MOD_TABLE (MOD_VEX_0F50) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8719     { "vandpX",         { XM, Vex, EXx }, 0 },
8720     { "vandnpX",        { XM, Vex, EXx }, 0 },
8721     { "vorpX",          { XM, Vex, EXx }, 0 },
8722     { "vxorpX",         { XM, Vex, EXx }, 0 },
8723     /* 58 */
8724     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8732     /* 60 */
8733     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8741     /* 68 */
8742     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8750     /* 70 */
8751     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8752     { REG_TABLE (REG_VEX_0F71) },
8753     { REG_TABLE (REG_VEX_0F72) },
8754     { REG_TABLE (REG_VEX_0F73) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8759     /* 78 */
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8768     /* 80 */
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     /* 88 */
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     /* 90 */
8787     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     /* 98 */
8796     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     /* a0 */
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     /* a8 */
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { REG_TABLE (REG_VEX_0FAE) },
8821     { Bad_Opcode },
8822     /* b0 */
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     /* b8 */
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     /* c0 */
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8844     { Bad_Opcode },
8845     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8847     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8848     { Bad_Opcode },
8849     /* c8 */
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     /* d0 */
8859     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8867     /* d8 */
8868     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8876     /* e0 */
8877     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8878     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8880     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8881     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8882     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8883     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8884     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8885     /* e8 */
8886     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8889     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8892     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8894     /* f0 */
8895     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8896     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8897     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8898     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8899     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8900     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8901     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8902     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8903     /* f8 */
8904     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8905     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8906     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8907     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8908     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8909     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8910     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8911     { Bad_Opcode },
8912   },
8913   /* VEX_0F38 */
8914   {
8915     /* 00 */
8916     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8924     /* 08 */
8925     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8933     /* 10 */
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8942     /* 18 */
8943     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8946     { Bad_Opcode },
8947     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8950     { Bad_Opcode },
8951     /* 20 */
8952     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     /* 28 */
8961     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8969     /* 30 */
8970     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8978     /* 38 */
8979     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8987     /* 40 */
8988     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8996     /* 48 */
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     /* 50 */
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     /* 58 */
9015     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     /* 60 */
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     /* 68 */
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     /* 70 */
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     /* 78 */
9051     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     /* 80 */
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     /* 88 */
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9074     { Bad_Opcode },
9075     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9076     { Bad_Opcode },
9077     /* 90 */
9078     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9086     /* 98 */
9087     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9095     /* a0 */
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9104     /* a8 */
9105     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9113     /* b0 */
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9122     /* b8 */
9123     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9131     /* c0 */
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     /* c8 */
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     /* d0 */
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     /* d8 */
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9163     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9164     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9165     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9166     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9167     /* e0 */
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     /* e8 */
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     /* f0 */
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9189     { REG_TABLE (REG_VEX_0F38F3) },
9190     { Bad_Opcode },
9191     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9194     /* f8 */
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203   },
9204   /* VEX_0F3A */
9205   {
9206     /* 00 */
9207     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9208     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9209     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9210     { Bad_Opcode },
9211     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9213     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9214     { Bad_Opcode },
9215     /* 08 */
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9218     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9219     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9221     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9222     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9223     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9224     /* 10 */
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9230     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9231     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9232     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9233     /* 18 */
9234     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     /* 20 */
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     /* 28 */
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     /* 30 */
9261     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9263     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9264     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     /* 38 */
9270     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9271     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     /* 40 */
9279     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9280     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9281     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9282     { Bad_Opcode },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9284     { Bad_Opcode },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9286     { Bad_Opcode },
9287     /* 48 */
9288     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9290     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     /* 50 */
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     /* 58 */
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9314     /* 60 */
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9318     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     /* 68 */
9324     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9325     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9326     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9327     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9328     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9329     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9330     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9331     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9332     /* 70 */
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     /* 78 */
9342     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9343     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9344     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9345     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9346     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9349     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9350     /* 80 */
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     /* 88 */
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     /* 90 */
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     /* 98 */
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     /* a0 */
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     /* a8 */
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     /* b0 */
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     /* b8 */
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     /* c0 */
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     /* c8 */
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     /* d0 */
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     /* d8 */
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9458     /* e0 */
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     /* e8 */
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     /* f0 */
9477     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     { Bad_Opcode },
9481     { Bad_Opcode },
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     /* f8 */
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     { Bad_Opcode },
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494   },
9495 };
9496
9497 #define NEED_OPCODE_TABLE
9498 #include "i386-dis-evex.h"
9499 #undef NEED_OPCODE_TABLE
9500 static const struct dis386 vex_len_table[][2] = {
9501   /* VEX_LEN_0F10_P_1 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9504     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9505   },
9506
9507   /* VEX_LEN_0F10_P_3 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9510     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9511   },
9512
9513   /* VEX_LEN_0F11_P_1 */
9514   {
9515     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9516     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9517   },
9518
9519   /* VEX_LEN_0F11_P_3 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9522     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9523   },
9524
9525   /* VEX_LEN_0F12_P_0_M_0 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9528   },
9529
9530   /* VEX_LEN_0F12_P_0_M_1 */
9531   {
9532     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9533   },
9534
9535   /* VEX_LEN_0F12_P_2 */
9536   {
9537     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9538   },
9539
9540   /* VEX_LEN_0F13_M_0 */
9541   {
9542     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9543   },
9544
9545   /* VEX_LEN_0F16_P_0_M_0 */
9546   {
9547     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9548   },
9549
9550   /* VEX_LEN_0F16_P_0_M_1 */
9551   {
9552     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9553   },
9554
9555   /* VEX_LEN_0F16_P_2 */
9556   {
9557     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9558   },
9559
9560   /* VEX_LEN_0F17_M_0 */
9561   {
9562     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9563   },
9564
9565   /* VEX_LEN_0F2A_P_1 */
9566   {
9567     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9568     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9569   },
9570
9571   /* VEX_LEN_0F2A_P_3 */
9572   {
9573     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9574     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9575   },
9576
9577   /* VEX_LEN_0F2C_P_1 */
9578   {
9579     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9580     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9581   },
9582
9583   /* VEX_LEN_0F2C_P_3 */
9584   {
9585     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9586     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9587   },
9588
9589   /* VEX_LEN_0F2D_P_1 */
9590   {
9591     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9592     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9593   },
9594
9595   /* VEX_LEN_0F2D_P_3 */
9596   {
9597     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9598     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9599   },
9600
9601   /* VEX_LEN_0F2E_P_0 */
9602   {
9603     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9604     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9605   },
9606
9607   /* VEX_LEN_0F2E_P_2 */
9608   {
9609     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9610     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9611   },
9612
9613   /* VEX_LEN_0F2F_P_0 */
9614   {
9615     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9616     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9617   },
9618
9619   /* VEX_LEN_0F2F_P_2 */
9620   {
9621     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9622     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9623   },
9624
9625   /* VEX_LEN_0F41_P_0 */
9626   {
9627     { Bad_Opcode },
9628     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9629   },
9630   /* VEX_LEN_0F41_P_2 */
9631   {
9632     { Bad_Opcode },
9633     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9634   },
9635   /* VEX_LEN_0F42_P_0 */
9636   {
9637     { Bad_Opcode },
9638     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9639   },
9640   /* VEX_LEN_0F42_P_2 */
9641   {
9642     { Bad_Opcode },
9643     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9644   },
9645   /* VEX_LEN_0F44_P_0 */
9646   {
9647     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9648   },
9649   /* VEX_LEN_0F44_P_2 */
9650   {
9651     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9652   },
9653   /* VEX_LEN_0F45_P_0 */
9654   {
9655     { Bad_Opcode },
9656     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9657   },
9658   /* VEX_LEN_0F45_P_2 */
9659   {
9660     { Bad_Opcode },
9661     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9662   },
9663   /* VEX_LEN_0F46_P_0 */
9664   {
9665     { Bad_Opcode },
9666     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9667   },
9668   /* VEX_LEN_0F46_P_2 */
9669   {
9670     { Bad_Opcode },
9671     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9672   },
9673   /* VEX_LEN_0F47_P_0 */
9674   {
9675     { Bad_Opcode },
9676     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9677   },
9678   /* VEX_LEN_0F47_P_2 */
9679   {
9680     { Bad_Opcode },
9681     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9682   },
9683   /* VEX_LEN_0F4A_P_0 */
9684   {
9685     { Bad_Opcode },
9686     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9687   },
9688   /* VEX_LEN_0F4A_P_2 */
9689   {
9690     { Bad_Opcode },
9691     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9692   },
9693   /* VEX_LEN_0F4B_P_0 */
9694   {
9695     { Bad_Opcode },
9696     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9697   },
9698   /* VEX_LEN_0F4B_P_2 */
9699   {
9700     { Bad_Opcode },
9701     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9702   },
9703
9704   /* VEX_LEN_0F51_P_1 */
9705   {
9706     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9707     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9708   },
9709
9710   /* VEX_LEN_0F51_P_3 */
9711   {
9712     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9713     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9714   },
9715
9716   /* VEX_LEN_0F52_P_1 */
9717   {
9718     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9719     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9720   },
9721
9722   /* VEX_LEN_0F53_P_1 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9725     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9726   },
9727
9728   /* VEX_LEN_0F58_P_1 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9731     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9732   },
9733
9734   /* VEX_LEN_0F58_P_3 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9737     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9738   },
9739
9740   /* VEX_LEN_0F59_P_1 */
9741   {
9742     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9743     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9744   },
9745
9746   /* VEX_LEN_0F59_P_3 */
9747   {
9748     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9749     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9750   },
9751
9752   /* VEX_LEN_0F5A_P_1 */
9753   {
9754     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9755     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9756   },
9757
9758   /* VEX_LEN_0F5A_P_3 */
9759   {
9760     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9761     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9762   },
9763
9764   /* VEX_LEN_0F5C_P_1 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9767     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9768   },
9769
9770   /* VEX_LEN_0F5C_P_3 */
9771   {
9772     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9773     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9774   },
9775
9776   /* VEX_LEN_0F5D_P_1 */
9777   {
9778     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9779     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9780   },
9781
9782   /* VEX_LEN_0F5D_P_3 */
9783   {
9784     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9785     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9786   },
9787
9788   /* VEX_LEN_0F5E_P_1 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9791     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9792   },
9793
9794   /* VEX_LEN_0F5E_P_3 */
9795   {
9796     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9797     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9798   },
9799
9800   /* VEX_LEN_0F5F_P_1 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9803     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9804   },
9805
9806   /* VEX_LEN_0F5F_P_3 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9809     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9810   },
9811
9812   /* VEX_LEN_0F6E_P_2 */
9813   {
9814     { "vmovK",          { XMScalar, Edq }, 0 },
9815     { "vmovK",          { XMScalar, Edq }, 0 },
9816   },
9817
9818   /* VEX_LEN_0F7E_P_1 */
9819   {
9820     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9821     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9822   },
9823
9824   /* VEX_LEN_0F7E_P_2 */
9825   {
9826     { "vmovK",          { Edq, XMScalar }, 0 },
9827     { "vmovK",          { Edq, XMScalar }, 0 },
9828   },
9829
9830   /* VEX_LEN_0F90_P_0 */
9831   {
9832     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9833   },
9834
9835   /* VEX_LEN_0F90_P_2 */
9836   {
9837     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9838   },
9839
9840   /* VEX_LEN_0F91_P_0 */
9841   {
9842     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9843   },
9844
9845   /* VEX_LEN_0F91_P_2 */
9846   {
9847     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9848   },
9849
9850   /* VEX_LEN_0F92_P_0 */
9851   {
9852     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9853   },
9854
9855   /* VEX_LEN_0F92_P_2 */
9856   {
9857     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9858   },
9859
9860   /* VEX_LEN_0F92_P_3 */
9861   {
9862     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9863   },
9864
9865   /* VEX_LEN_0F93_P_0 */
9866   {
9867     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9868   },
9869
9870   /* VEX_LEN_0F93_P_2 */
9871   {
9872     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9873   },
9874
9875   /* VEX_LEN_0F93_P_3 */
9876   {
9877     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9878   },
9879
9880   /* VEX_LEN_0F98_P_0 */
9881   {
9882     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9883   },
9884
9885   /* VEX_LEN_0F98_P_2 */
9886   {
9887     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9888   },
9889
9890   /* VEX_LEN_0F99_P_0 */
9891   {
9892     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9893   },
9894
9895   /* VEX_LEN_0F99_P_2 */
9896   {
9897     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9898   },
9899
9900   /* VEX_LEN_0FAE_R_2_M_0 */
9901   {
9902     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9903   },
9904
9905   /* VEX_LEN_0FAE_R_3_M_0 */
9906   {
9907     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9908   },
9909
9910   /* VEX_LEN_0FC2_P_1 */
9911   {
9912     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9913     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9914   },
9915
9916   /* VEX_LEN_0FC2_P_3 */
9917   {
9918     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9919     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9920   },
9921
9922   /* VEX_LEN_0FC4_P_2 */
9923   {
9924     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9925   },
9926
9927   /* VEX_LEN_0FC5_P_2 */
9928   {
9929     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9930   },
9931
9932   /* VEX_LEN_0FD6_P_2 */
9933   {
9934     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9935     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9936   },
9937
9938   /* VEX_LEN_0FF7_P_2 */
9939   {
9940     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9941   },
9942
9943   /* VEX_LEN_0F3816_P_2 */
9944   {
9945     { Bad_Opcode },
9946     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9947   },
9948
9949   /* VEX_LEN_0F3819_P_2 */
9950   {
9951     { Bad_Opcode },
9952     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9953   },
9954
9955   /* VEX_LEN_0F381A_P_2_M_0 */
9956   {
9957     { Bad_Opcode },
9958     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9959   },
9960
9961   /* VEX_LEN_0F3836_P_2 */
9962   {
9963     { Bad_Opcode },
9964     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9965   },
9966
9967   /* VEX_LEN_0F3841_P_2 */
9968   {
9969     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9970   },
9971
9972   /* VEX_LEN_0F385A_P_2_M_0 */
9973   {
9974     { Bad_Opcode },
9975     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9976   },
9977
9978   /* VEX_LEN_0F38DB_P_2 */
9979   {
9980     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9981   },
9982
9983   /* VEX_LEN_0F38DC_P_2 */
9984   {
9985     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9986   },
9987
9988   /* VEX_LEN_0F38DD_P_2 */
9989   {
9990     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9991   },
9992
9993   /* VEX_LEN_0F38DE_P_2 */
9994   {
9995     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9996   },
9997
9998   /* VEX_LEN_0F38DF_P_2 */
9999   {
10000     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10001   },
10002
10003   /* VEX_LEN_0F38F2_P_0 */
10004   {
10005     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10006   },
10007
10008   /* VEX_LEN_0F38F3_R_1_P_0 */
10009   {
10010     { "blsrS",          { VexGdq, Edq }, 0 },
10011   },
10012
10013   /* VEX_LEN_0F38F3_R_2_P_0 */
10014   {
10015     { "blsmskS",        { VexGdq, Edq }, 0 },
10016   },
10017
10018   /* VEX_LEN_0F38F3_R_3_P_0 */
10019   {
10020     { "blsiS",          { VexGdq, Edq }, 0 },
10021   },
10022
10023   /* VEX_LEN_0F38F5_P_0 */
10024   {
10025     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10026   },
10027
10028   /* VEX_LEN_0F38F5_P_1 */
10029   {
10030     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10031   },
10032
10033   /* VEX_LEN_0F38F5_P_3 */
10034   {
10035     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10036   },
10037
10038   /* VEX_LEN_0F38F6_P_3 */
10039   {
10040     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10041   },
10042
10043   /* VEX_LEN_0F38F7_P_0 */
10044   {
10045     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10046   },
10047
10048   /* VEX_LEN_0F38F7_P_1 */
10049   {
10050     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10051   },
10052
10053   /* VEX_LEN_0F38F7_P_2 */
10054   {
10055     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10056   },
10057
10058   /* VEX_LEN_0F38F7_P_3 */
10059   {
10060     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10061   },
10062
10063   /* VEX_LEN_0F3A00_P_2 */
10064   {
10065     { Bad_Opcode },
10066     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10067   },
10068
10069   /* VEX_LEN_0F3A01_P_2 */
10070   {
10071     { Bad_Opcode },
10072     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10073   },
10074
10075   /* VEX_LEN_0F3A06_P_2 */
10076   {
10077     { Bad_Opcode },
10078     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10079   },
10080
10081   /* VEX_LEN_0F3A0A_P_2 */
10082   {
10083     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10084     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10085   },
10086
10087   /* VEX_LEN_0F3A0B_P_2 */
10088   {
10089     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10090     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10091   },
10092
10093   /* VEX_LEN_0F3A14_P_2 */
10094   {
10095     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10096   },
10097
10098   /* VEX_LEN_0F3A15_P_2 */
10099   {
10100     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10101   },
10102
10103   /* VEX_LEN_0F3A16_P_2  */
10104   {
10105     { "vpextrK",        { Edq, XM, Ib }, 0 },
10106   },
10107
10108   /* VEX_LEN_0F3A17_P_2 */
10109   {
10110     { "vextractps",     { Edqd, XM, Ib }, 0 },
10111   },
10112
10113   /* VEX_LEN_0F3A18_P_2 */
10114   {
10115     { Bad_Opcode },
10116     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10117   },
10118
10119   /* VEX_LEN_0F3A19_P_2 */
10120   {
10121     { Bad_Opcode },
10122     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10123   },
10124
10125   /* VEX_LEN_0F3A20_P_2 */
10126   {
10127     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10128   },
10129
10130   /* VEX_LEN_0F3A21_P_2 */
10131   {
10132     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10133   },
10134
10135   /* VEX_LEN_0F3A22_P_2 */
10136   {
10137     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10138   },
10139
10140   /* VEX_LEN_0F3A30_P_2 */
10141   {
10142     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10143   },
10144
10145   /* VEX_LEN_0F3A31_P_2 */
10146   {
10147     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10148   },
10149
10150   /* VEX_LEN_0F3A32_P_2 */
10151   {
10152     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10153   },
10154
10155   /* VEX_LEN_0F3A33_P_2 */
10156   {
10157     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10158   },
10159
10160   /* VEX_LEN_0F3A38_P_2 */
10161   {
10162     { Bad_Opcode },
10163     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10164   },
10165
10166   /* VEX_LEN_0F3A39_P_2 */
10167   {
10168     { Bad_Opcode },
10169     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10170   },
10171
10172   /* VEX_LEN_0F3A41_P_2 */
10173   {
10174     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10175   },
10176
10177   /* VEX_LEN_0F3A44_P_2 */
10178   {
10179     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10180   },
10181
10182   /* VEX_LEN_0F3A46_P_2 */
10183   {
10184     { Bad_Opcode },
10185     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10186   },
10187
10188   /* VEX_LEN_0F3A60_P_2 */
10189   {
10190     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10191   },
10192
10193   /* VEX_LEN_0F3A61_P_2 */
10194   {
10195     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10196   },
10197
10198   /* VEX_LEN_0F3A62_P_2 */
10199   {
10200     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10201   },
10202
10203   /* VEX_LEN_0F3A63_P_2 */
10204   {
10205     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10206   },
10207
10208   /* VEX_LEN_0F3A6A_P_2 */
10209   {
10210     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10211   },
10212
10213   /* VEX_LEN_0F3A6B_P_2 */
10214   {
10215     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10216   },
10217
10218   /* VEX_LEN_0F3A6E_P_2 */
10219   {
10220     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10221   },
10222
10223   /* VEX_LEN_0F3A6F_P_2 */
10224   {
10225     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10226   },
10227
10228   /* VEX_LEN_0F3A7A_P_2 */
10229   {
10230     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10231   },
10232
10233   /* VEX_LEN_0F3A7B_P_2 */
10234   {
10235     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10236   },
10237
10238   /* VEX_LEN_0F3A7E_P_2 */
10239   {
10240     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10241   },
10242
10243   /* VEX_LEN_0F3A7F_P_2 */
10244   {
10245     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10246   },
10247
10248   /* VEX_LEN_0F3ADF_P_2 */
10249   {
10250     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10251   },
10252
10253   /* VEX_LEN_0F3AF0_P_3 */
10254   {
10255     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10256   },
10257
10258   /* VEX_LEN_0FXOP_08_CC */
10259   {
10260      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10261   },
10262
10263   /* VEX_LEN_0FXOP_08_CD */
10264   {
10265      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10266   },
10267
10268   /* VEX_LEN_0FXOP_08_CE */
10269   {
10270      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10271   },
10272
10273   /* VEX_LEN_0FXOP_08_CF */
10274   {
10275      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10276   },
10277
10278   /* VEX_LEN_0FXOP_08_EC */
10279   {
10280      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10281   },
10282
10283   /* VEX_LEN_0FXOP_08_ED */
10284   {
10285      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10286   },
10287
10288   /* VEX_LEN_0FXOP_08_EE */
10289   {
10290      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10291   },
10292
10293   /* VEX_LEN_0FXOP_08_EF */
10294   {
10295      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10296   },
10297
10298   /* VEX_LEN_0FXOP_09_80 */
10299   {
10300     { "vfrczps",        { XM, EXxmm }, 0 },
10301     { "vfrczps",        { XM, EXymmq }, 0 },
10302   },
10303
10304   /* VEX_LEN_0FXOP_09_81 */
10305   {
10306     { "vfrczpd",        { XM, EXxmm }, 0 },
10307     { "vfrczpd",        { XM, EXymmq }, 0 },
10308   },
10309 };
10310
10311 static const struct dis386 vex_w_table[][2] = {
10312   {
10313     /* VEX_W_0F10_P_0 */
10314     { "vmovups",        { XM, EXx }, 0 },
10315   },
10316   {
10317     /* VEX_W_0F10_P_1 */
10318     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10319   },
10320   {
10321     /* VEX_W_0F10_P_2 */
10322     { "vmovupd",        { XM, EXx }, 0 },
10323   },
10324   {
10325     /* VEX_W_0F10_P_3 */
10326     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10327   },
10328   {
10329     /* VEX_W_0F11_P_0 */
10330     { "vmovups",        { EXxS, XM }, 0 },
10331   },
10332   {
10333     /* VEX_W_0F11_P_1 */
10334     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10335   },
10336   {
10337     /* VEX_W_0F11_P_2 */
10338     { "vmovupd",        { EXxS, XM }, 0 },
10339   },
10340   {
10341     /* VEX_W_0F11_P_3 */
10342     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10343   },
10344   {
10345     /* VEX_W_0F12_P_0_M_0 */
10346     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10347   },
10348   {
10349     /* VEX_W_0F12_P_0_M_1 */
10350     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10351   },
10352   {
10353     /* VEX_W_0F12_P_1 */
10354     { "vmovsldup",      { XM, EXx }, 0 },
10355   },
10356   {
10357     /* VEX_W_0F12_P_2 */
10358     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10359   },
10360   {
10361     /* VEX_W_0F12_P_3 */
10362     { "vmovddup",       { XM, EXymmq }, 0 },
10363   },
10364   {
10365     /* VEX_W_0F13_M_0 */
10366     { "vmovlpX",        { EXq, XM }, 0 },
10367   },
10368   {
10369     /* VEX_W_0F14 */
10370     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10371   },
10372   {
10373     /* VEX_W_0F15 */
10374     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10375   },
10376   {
10377     /* VEX_W_0F16_P_0_M_0 */
10378     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10379   },
10380   {
10381     /* VEX_W_0F16_P_0_M_1 */
10382     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10383   },
10384   {
10385     /* VEX_W_0F16_P_1 */
10386     { "vmovshdup",      { XM, EXx }, 0 },
10387   },
10388   {
10389     /* VEX_W_0F16_P_2 */
10390     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10391   },
10392   {
10393     /* VEX_W_0F17_M_0 */
10394     { "vmovhpX",        { EXq, XM }, 0 },
10395   },
10396   {
10397     /* VEX_W_0F28 */
10398     { "vmovapX",        { XM, EXx }, 0 },
10399   },
10400   {
10401     /* VEX_W_0F29 */
10402     { "vmovapX",        { EXxS, XM }, 0 },
10403   },
10404   {
10405     /* VEX_W_0F2B_M_0 */
10406     { "vmovntpX",       { Mx, XM }, 0 },
10407   },
10408   {
10409     /* VEX_W_0F2E_P_0 */
10410     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10411   },
10412   {
10413     /* VEX_W_0F2E_P_2 */
10414     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10415   },
10416   {
10417     /* VEX_W_0F2F_P_0 */
10418     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10419   },
10420   {
10421     /* VEX_W_0F2F_P_2 */
10422     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10423   },
10424   {
10425     /* VEX_W_0F41_P_0_LEN_1 */
10426     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10427     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10428   },
10429   {
10430     /* VEX_W_0F41_P_2_LEN_1 */
10431     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10432     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10433   },
10434   {
10435     /* VEX_W_0F42_P_0_LEN_1 */
10436     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10437     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10438   },
10439   {
10440     /* VEX_W_0F42_P_2_LEN_1 */
10441     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10442     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10443   },
10444   {
10445     /* VEX_W_0F44_P_0_LEN_0 */
10446     { "knotw",          { MaskG, MaskR }, 0 },
10447     { "knotq",          { MaskG, MaskR }, 0 },
10448   },
10449   {
10450     /* VEX_W_0F44_P_2_LEN_0 */
10451     { "knotb",          { MaskG, MaskR }, 0 },
10452     { "knotd",          { MaskG, MaskR }, 0 },
10453   },
10454   {
10455     /* VEX_W_0F45_P_0_LEN_1 */
10456     { "korw",           { MaskG, MaskVex, MaskR }, 0 },
10457     { "korq",           { MaskG, MaskVex, MaskR }, 0 },
10458   },
10459   {
10460     /* VEX_W_0F45_P_2_LEN_1 */
10461     { "korb",           { MaskG, MaskVex, MaskR }, 0 },
10462     { "kord",           { MaskG, MaskVex, MaskR }, 0 },
10463   },
10464   {
10465     /* VEX_W_0F46_P_0_LEN_1 */
10466     { "kxnorw",         { MaskG, MaskVex, MaskR }, 0 },
10467     { "kxnorq",         { MaskG, MaskVex, MaskR }, 0 },
10468   },
10469   {
10470     /* VEX_W_0F46_P_2_LEN_1 */
10471     { "kxnorb",         { MaskG, MaskVex, MaskR }, 0 },
10472     { "kxnord",         { MaskG, MaskVex, MaskR }, 0 },
10473   },
10474   {
10475     /* VEX_W_0F47_P_0_LEN_1 */
10476     { "kxorw",          { MaskG, MaskVex, MaskR }, 0 },
10477     { "kxorq",          { MaskG, MaskVex, MaskR }, 0 },
10478   },
10479   {
10480     /* VEX_W_0F47_P_2_LEN_1 */
10481     { "kxorb",          { MaskG, MaskVex, MaskR }, 0 },
10482     { "kxord",          { MaskG, MaskVex, MaskR }, 0 },
10483   },
10484   {
10485     /* VEX_W_0F4A_P_0_LEN_1 */
10486     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10487     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F4A_P_2_LEN_1 */
10491     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10492     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10493   },
10494   {
10495     /* VEX_W_0F4B_P_0_LEN_1 */
10496     { "kunpckwd",       { MaskG, MaskVex, MaskR }, 0 },
10497     { "kunpckdq",       { MaskG, MaskVex, MaskR }, 0 },
10498   },
10499   {
10500     /* VEX_W_0F4B_P_2_LEN_1 */
10501     { "kunpckbw",       { MaskG, MaskVex, MaskR }, 0 },
10502   },
10503   {
10504     /* VEX_W_0F50_M_0 */
10505     { "vmovmskpX",      { Gdq, XS }, 0 },
10506   },
10507   {
10508     /* VEX_W_0F51_P_0 */
10509     { "vsqrtps",        { XM, EXx }, 0 },
10510   },
10511   {
10512     /* VEX_W_0F51_P_1 */
10513     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10514   },
10515   {
10516     /* VEX_W_0F51_P_2  */
10517     { "vsqrtpd",        { XM, EXx }, 0 },
10518   },
10519   {
10520     /* VEX_W_0F51_P_3 */
10521     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10522   },
10523   {
10524     /* VEX_W_0F52_P_0 */
10525     { "vrsqrtps",       { XM, EXx }, 0 },
10526   },
10527   {
10528     /* VEX_W_0F52_P_1 */
10529     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10530   },
10531   {
10532     /* VEX_W_0F53_P_0  */
10533     { "vrcpps",         { XM, EXx }, 0 },
10534   },
10535   {
10536     /* VEX_W_0F53_P_1  */
10537     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10538   },
10539   {
10540     /* VEX_W_0F58_P_0  */
10541     { "vaddps",         { XM, Vex, EXx }, 0 },
10542   },
10543   {
10544     /* VEX_W_0F58_P_1  */
10545     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10546   },
10547   {
10548     /* VEX_W_0F58_P_2  */
10549     { "vaddpd",         { XM, Vex, EXx }, 0 },
10550   },
10551   {
10552     /* VEX_W_0F58_P_3  */
10553     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10554   },
10555   {
10556     /* VEX_W_0F59_P_0  */
10557     { "vmulps",         { XM, Vex, EXx }, 0 },
10558   },
10559   {
10560     /* VEX_W_0F59_P_1  */
10561     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10562   },
10563   {
10564     /* VEX_W_0F59_P_2  */
10565     { "vmulpd",         { XM, Vex, EXx }, 0 },
10566   },
10567   {
10568     /* VEX_W_0F59_P_3  */
10569     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10570   },
10571   {
10572     /* VEX_W_0F5A_P_0  */
10573     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10574   },
10575   {
10576     /* VEX_W_0F5A_P_1  */
10577     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10578   },
10579   {
10580     /* VEX_W_0F5A_P_3  */
10581     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10582   },
10583   {
10584     /* VEX_W_0F5B_P_0  */
10585     { "vcvtdq2ps",      { XM, EXx }, 0 },
10586   },
10587   {
10588     /* VEX_W_0F5B_P_1  */
10589     { "vcvttps2dq",     { XM, EXx }, 0 },
10590   },
10591   {
10592     /* VEX_W_0F5B_P_2  */
10593     { "vcvtps2dq",      { XM, EXx }, 0 },
10594   },
10595   {
10596     /* VEX_W_0F5C_P_0  */
10597     { "vsubps",         { XM, Vex, EXx }, 0 },
10598   },
10599   {
10600     /* VEX_W_0F5C_P_1  */
10601     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10602   },
10603   {
10604     /* VEX_W_0F5C_P_2  */
10605     { "vsubpd",         { XM, Vex, EXx }, 0 },
10606   },
10607   {
10608     /* VEX_W_0F5C_P_3  */
10609     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10610   },
10611   {
10612     /* VEX_W_0F5D_P_0  */
10613     { "vminps",         { XM, Vex, EXx }, 0 },
10614   },
10615   {
10616     /* VEX_W_0F5D_P_1  */
10617     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10618   },
10619   {
10620     /* VEX_W_0F5D_P_2  */
10621     { "vminpd",         { XM, Vex, EXx }, 0 },
10622   },
10623   {
10624     /* VEX_W_0F5D_P_3  */
10625     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10626   },
10627   {
10628     /* VEX_W_0F5E_P_0  */
10629     { "vdivps",         { XM, Vex, EXx }, 0 },
10630   },
10631   {
10632     /* VEX_W_0F5E_P_1  */
10633     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10634   },
10635   {
10636     /* VEX_W_0F5E_P_2  */
10637     { "vdivpd",         { XM, Vex, EXx }, 0 },
10638   },
10639   {
10640     /* VEX_W_0F5E_P_3  */
10641     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10642   },
10643   {
10644     /* VEX_W_0F5F_P_0  */
10645     { "vmaxps",         { XM, Vex, EXx }, 0 },
10646   },
10647   {
10648     /* VEX_W_0F5F_P_1  */
10649     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10650   },
10651   {
10652     /* VEX_W_0F5F_P_2  */
10653     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10654   },
10655   {
10656     /* VEX_W_0F5F_P_3  */
10657     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10658   },
10659   {
10660     /* VEX_W_0F60_P_2  */
10661     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10662   },
10663   {
10664     /* VEX_W_0F61_P_2  */
10665     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10666   },
10667   {
10668     /* VEX_W_0F62_P_2  */
10669     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10670   },
10671   {
10672     /* VEX_W_0F63_P_2  */
10673     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10674   },
10675   {
10676     /* VEX_W_0F64_P_2  */
10677     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10678   },
10679   {
10680     /* VEX_W_0F65_P_2  */
10681     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10682   },
10683   {
10684     /* VEX_W_0F66_P_2  */
10685     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10686   },
10687   {
10688     /* VEX_W_0F67_P_2  */
10689     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10690   },
10691   {
10692     /* VEX_W_0F68_P_2  */
10693     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10694   },
10695   {
10696     /* VEX_W_0F69_P_2  */
10697     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10698   },
10699   {
10700     /* VEX_W_0F6A_P_2  */
10701     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10702   },
10703   {
10704     /* VEX_W_0F6B_P_2  */
10705     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10706   },
10707   {
10708     /* VEX_W_0F6C_P_2  */
10709     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10710   },
10711   {
10712     /* VEX_W_0F6D_P_2  */
10713     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10714   },
10715   {
10716     /* VEX_W_0F6F_P_1  */
10717     { "vmovdqu",        { XM, EXx }, 0 },
10718   },
10719   {
10720     /* VEX_W_0F6F_P_2  */
10721     { "vmovdqa",        { XM, EXx }, 0 },
10722   },
10723   {
10724     /* VEX_W_0F70_P_1 */
10725     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10726   },
10727   {
10728     /* VEX_W_0F70_P_2 */
10729     { "vpshufd",        { XM, EXx, Ib }, 0 },
10730   },
10731   {
10732     /* VEX_W_0F70_P_3 */
10733     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10734   },
10735   {
10736     /* VEX_W_0F71_R_2_P_2  */
10737     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10738   },
10739   {
10740     /* VEX_W_0F71_R_4_P_2  */
10741     { "vpsraw",         { Vex, XS, Ib }, 0 },
10742   },
10743   {
10744     /* VEX_W_0F71_R_6_P_2  */
10745     { "vpsllw",         { Vex, XS, Ib }, 0 },
10746   },
10747   {
10748     /* VEX_W_0F72_R_2_P_2  */
10749     { "vpsrld",         { Vex, XS, Ib }, 0 },
10750   },
10751   {
10752     /* VEX_W_0F72_R_4_P_2  */
10753     { "vpsrad",         { Vex, XS, Ib }, 0 },
10754   },
10755   {
10756     /* VEX_W_0F72_R_6_P_2  */
10757     { "vpslld",         { Vex, XS, Ib }, 0 },
10758   },
10759   {
10760     /* VEX_W_0F73_R_2_P_2  */
10761     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10762   },
10763   {
10764     /* VEX_W_0F73_R_3_P_2  */
10765     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10766   },
10767   {
10768     /* VEX_W_0F73_R_6_P_2  */
10769     { "vpsllq",         { Vex, XS, Ib }, 0 },
10770   },
10771   {
10772     /* VEX_W_0F73_R_7_P_2  */
10773     { "vpslldq",        { Vex, XS, Ib }, 0 },
10774   },
10775   {
10776     /* VEX_W_0F74_P_2 */
10777     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10778   },
10779   {
10780     /* VEX_W_0F75_P_2 */
10781     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10782   },
10783   {
10784     /* VEX_W_0F76_P_2 */
10785     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10786   },
10787   {
10788     /* VEX_W_0F77_P_0 */
10789     { "",               { VZERO }, 0 },
10790   },
10791   {
10792     /* VEX_W_0F7C_P_2 */
10793     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10794   },
10795   {
10796     /* VEX_W_0F7C_P_3 */
10797     { "vhaddps",        { XM, Vex, EXx }, 0 },
10798   },
10799   {
10800     /* VEX_W_0F7D_P_2 */
10801     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10802   },
10803   {
10804     /* VEX_W_0F7D_P_3 */
10805     { "vhsubps",        { XM, Vex, EXx }, 0 },
10806   },
10807   {
10808     /* VEX_W_0F7E_P_1 */
10809     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10810   },
10811   {
10812     /* VEX_W_0F7F_P_1 */
10813     { "vmovdqu",        { EXxS, XM }, 0 },
10814   },
10815   {
10816     /* VEX_W_0F7F_P_2 */
10817     { "vmovdqa",        { EXxS, XM }, 0 },
10818   },
10819   {
10820     /* VEX_W_0F90_P_0_LEN_0 */
10821     { "kmovw",          { MaskG, MaskE }, 0 },
10822     { "kmovq",          { MaskG, MaskE }, 0 },
10823   },
10824   {
10825     /* VEX_W_0F90_P_2_LEN_0 */
10826     { "kmovb",          { MaskG, MaskBDE }, 0 },
10827     { "kmovd",          { MaskG, MaskBDE }, 0 },
10828   },
10829   {
10830     /* VEX_W_0F91_P_0_LEN_0 */
10831     { "kmovw",          { Ew, MaskG }, 0 },
10832     { "kmovq",          { Eq, MaskG }, 0 },
10833   },
10834   {
10835     /* VEX_W_0F91_P_2_LEN_0 */
10836     { "kmovb",          { Eb, MaskG }, 0 },
10837     { "kmovd",          { Ed, MaskG }, 0 },
10838   },
10839   {
10840     /* VEX_W_0F92_P_0_LEN_0 */
10841     { "kmovw",          { MaskG, Rdq }, 0 },
10842   },
10843   {
10844     /* VEX_W_0F92_P_2_LEN_0 */
10845     { "kmovb",          { MaskG, Rdq }, 0 },
10846   },
10847   {
10848     /* VEX_W_0F92_P_3_LEN_0 */
10849     { "kmovd",          { MaskG, Rdq }, 0 },
10850     { "kmovq",          { MaskG, Rdq }, 0 },
10851   },
10852   {
10853     /* VEX_W_0F93_P_0_LEN_0 */
10854     { "kmovw",          { Gdq, MaskR }, 0 },
10855   },
10856   {
10857     /* VEX_W_0F93_P_2_LEN_0 */
10858     { "kmovb",          { Gdq, MaskR }, 0 },
10859   },
10860   {
10861     /* VEX_W_0F93_P_3_LEN_0 */
10862     { "kmovd",          { Gdq, MaskR }, 0 },
10863     { "kmovq",          { Gdq, MaskR }, 0 },
10864   },
10865   {
10866     /* VEX_W_0F98_P_0_LEN_0 */
10867     { "kortestw",       { MaskG, MaskR }, 0 },
10868     { "kortestq",       { MaskG, MaskR }, 0 },
10869   },
10870   {
10871     /* VEX_W_0F98_P_2_LEN_0 */
10872     { "kortestb",       { MaskG, MaskR }, 0 },
10873     { "kortestd",       { MaskG, MaskR }, 0 },
10874   },
10875   {
10876     /* VEX_W_0F99_P_0_LEN_0 */
10877     { "ktestw", { MaskG, MaskR }, 0 },
10878     { "ktestq", { MaskG, MaskR }, 0 },
10879   },
10880   {
10881     /* VEX_W_0F99_P_2_LEN_0 */
10882     { "ktestb", { MaskG, MaskR }, 0 },
10883     { "ktestd", { MaskG, MaskR }, 0 },
10884   },
10885   {
10886     /* VEX_W_0FAE_R_2_M_0 */
10887     { "vldmxcsr",       { Md }, 0 },
10888   },
10889   {
10890     /* VEX_W_0FAE_R_3_M_0 */
10891     { "vstmxcsr",       { Md }, 0 },
10892   },
10893   {
10894     /* VEX_W_0FC2_P_0 */
10895     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10896   },
10897   {
10898     /* VEX_W_0FC2_P_1 */
10899     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10900   },
10901   {
10902     /* VEX_W_0FC2_P_2 */
10903     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10904   },
10905   {
10906     /* VEX_W_0FC2_P_3 */
10907     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10908   },
10909   {
10910     /* VEX_W_0FC4_P_2 */
10911     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10912   },
10913   {
10914     /* VEX_W_0FC5_P_2 */
10915     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10916   },
10917   {
10918     /* VEX_W_0FD0_P_2 */
10919     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10920   },
10921   {
10922     /* VEX_W_0FD0_P_3 */
10923     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10924   },
10925   {
10926     /* VEX_W_0FD1_P_2 */
10927     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10928   },
10929   {
10930     /* VEX_W_0FD2_P_2 */
10931     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10932   },
10933   {
10934     /* VEX_W_0FD3_P_2 */
10935     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10936   },
10937   {
10938     /* VEX_W_0FD4_P_2 */
10939     { "vpaddq",         { XM, Vex, EXx }, 0 },
10940   },
10941   {
10942     /* VEX_W_0FD5_P_2 */
10943     { "vpmullw",        { XM, Vex, EXx }, 0 },
10944   },
10945   {
10946     /* VEX_W_0FD6_P_2 */
10947     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10948   },
10949   {
10950     /* VEX_W_0FD7_P_2_M_1 */
10951     { "vpmovmskb",      { Gdq, XS }, 0 },
10952   },
10953   {
10954     /* VEX_W_0FD8_P_2 */
10955     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10956   },
10957   {
10958     /* VEX_W_0FD9_P_2 */
10959     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10960   },
10961   {
10962     /* VEX_W_0FDA_P_2 */
10963     { "vpminub",        { XM, Vex, EXx }, 0 },
10964   },
10965   {
10966     /* VEX_W_0FDB_P_2 */
10967     { "vpand",          { XM, Vex, EXx }, 0 },
10968   },
10969   {
10970     /* VEX_W_0FDC_P_2 */
10971     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10972   },
10973   {
10974     /* VEX_W_0FDD_P_2 */
10975     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10976   },
10977   {
10978     /* VEX_W_0FDE_P_2 */
10979     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10980   },
10981   {
10982     /* VEX_W_0FDF_P_2 */
10983     { "vpandn",         { XM, Vex, EXx }, 0 },
10984   },
10985   {
10986     /* VEX_W_0FE0_P_2  */
10987     { "vpavgb",         { XM, Vex, EXx }, 0 },
10988   },
10989   {
10990     /* VEX_W_0FE1_P_2  */
10991     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10992   },
10993   {
10994     /* VEX_W_0FE2_P_2  */
10995     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10996   },
10997   {
10998     /* VEX_W_0FE3_P_2  */
10999     { "vpavgw",         { XM, Vex, EXx }, 0 },
11000   },
11001   {
11002     /* VEX_W_0FE4_P_2  */
11003     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11004   },
11005   {
11006     /* VEX_W_0FE5_P_2  */
11007     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11008   },
11009   {
11010     /* VEX_W_0FE6_P_1  */
11011     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11012   },
11013   {
11014     /* VEX_W_0FE6_P_2  */
11015     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11016   },
11017   {
11018     /* VEX_W_0FE6_P_3  */
11019     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11020   },
11021   {
11022     /* VEX_W_0FE7_P_2_M_0 */
11023     { "vmovntdq",       { Mx, XM }, 0 },
11024   },
11025   {
11026     /* VEX_W_0FE8_P_2  */
11027     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11028   },
11029   {
11030     /* VEX_W_0FE9_P_2  */
11031     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11032   },
11033   {
11034     /* VEX_W_0FEA_P_2  */
11035     { "vpminsw",        { XM, Vex, EXx }, 0 },
11036   },
11037   {
11038     /* VEX_W_0FEB_P_2  */
11039     { "vpor",           { XM, Vex, EXx }, 0 },
11040   },
11041   {
11042     /* VEX_W_0FEC_P_2  */
11043     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11044   },
11045   {
11046     /* VEX_W_0FED_P_2  */
11047     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11048   },
11049   {
11050     /* VEX_W_0FEE_P_2  */
11051     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11052   },
11053   {
11054     /* VEX_W_0FEF_P_2  */
11055     { "vpxor",          { XM, Vex, EXx }, 0 },
11056   },
11057   {
11058     /* VEX_W_0FF0_P_3_M_0 */
11059     { "vlddqu",         { XM, M }, 0 },
11060   },
11061   {
11062     /* VEX_W_0FF1_P_2 */
11063     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11064   },
11065   {
11066     /* VEX_W_0FF2_P_2 */
11067     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11068   },
11069   {
11070     /* VEX_W_0FF3_P_2 */
11071     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11072   },
11073   {
11074     /* VEX_W_0FF4_P_2 */
11075     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11076   },
11077   {
11078     /* VEX_W_0FF5_P_2 */
11079     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11080   },
11081   {
11082     /* VEX_W_0FF6_P_2 */
11083     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11084   },
11085   {
11086     /* VEX_W_0FF7_P_2 */
11087     { "vmaskmovdqu",    { XM, XS }, 0 },
11088   },
11089   {
11090     /* VEX_W_0FF8_P_2 */
11091     { "vpsubb",         { XM, Vex, EXx }, 0 },
11092   },
11093   {
11094     /* VEX_W_0FF9_P_2 */
11095     { "vpsubw",         { XM, Vex, EXx }, 0 },
11096   },
11097   {
11098     /* VEX_W_0FFA_P_2 */
11099     { "vpsubd",         { XM, Vex, EXx }, 0 },
11100   },
11101   {
11102     /* VEX_W_0FFB_P_2 */
11103     { "vpsubq",         { XM, Vex, EXx }, 0 },
11104   },
11105   {
11106     /* VEX_W_0FFC_P_2 */
11107     { "vpaddb",         { XM, Vex, EXx }, 0 },
11108   },
11109   {
11110     /* VEX_W_0FFD_P_2 */
11111     { "vpaddw",         { XM, Vex, EXx }, 0 },
11112   },
11113   {
11114     /* VEX_W_0FFE_P_2 */
11115     { "vpaddd",         { XM, Vex, EXx }, 0 },
11116   },
11117   {
11118     /* VEX_W_0F3800_P_2  */
11119     { "vpshufb",        { XM, Vex, EXx }, 0 },
11120   },
11121   {
11122     /* VEX_W_0F3801_P_2  */
11123     { "vphaddw",        { XM, Vex, EXx }, 0 },
11124   },
11125   {
11126     /* VEX_W_0F3802_P_2  */
11127     { "vphaddd",        { XM, Vex, EXx }, 0 },
11128   },
11129   {
11130     /* VEX_W_0F3803_P_2  */
11131     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11132   },
11133   {
11134     /* VEX_W_0F3804_P_2  */
11135     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11136   },
11137   {
11138     /* VEX_W_0F3805_P_2  */
11139     { "vphsubw",        { XM, Vex, EXx }, 0 },
11140   },
11141   {
11142     /* VEX_W_0F3806_P_2  */
11143     { "vphsubd",        { XM, Vex, EXx }, 0 },
11144   },
11145   {
11146     /* VEX_W_0F3807_P_2  */
11147     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11148   },
11149   {
11150     /* VEX_W_0F3808_P_2  */
11151     { "vpsignb",        { XM, Vex, EXx }, 0 },
11152   },
11153   {
11154     /* VEX_W_0F3809_P_2  */
11155     { "vpsignw",        { XM, Vex, EXx }, 0 },
11156   },
11157   {
11158     /* VEX_W_0F380A_P_2  */
11159     { "vpsignd",        { XM, Vex, EXx }, 0 },
11160   },
11161   {
11162     /* VEX_W_0F380B_P_2  */
11163     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11164   },
11165   {
11166     /* VEX_W_0F380C_P_2  */
11167     { "vpermilps",      { XM, Vex, EXx }, 0 },
11168   },
11169   {
11170     /* VEX_W_0F380D_P_2  */
11171     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11172   },
11173   {
11174     /* VEX_W_0F380E_P_2  */
11175     { "vtestps",        { XM, EXx }, 0 },
11176   },
11177   {
11178     /* VEX_W_0F380F_P_2  */
11179     { "vtestpd",        { XM, EXx }, 0 },
11180   },
11181   {
11182     /* VEX_W_0F3816_P_2  */
11183     { "vpermps",        { XM, Vex, EXx }, 0 },
11184   },
11185   {
11186     /* VEX_W_0F3817_P_2 */
11187     { "vptest",         { XM, EXx }, 0 },
11188   },
11189   {
11190     /* VEX_W_0F3818_P_2 */
11191     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11192   },
11193   {
11194     /* VEX_W_0F3819_P_2 */
11195     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11196   },
11197   {
11198     /* VEX_W_0F381A_P_2_M_0 */
11199     { "vbroadcastf128", { XM, Mxmm }, 0 },
11200   },
11201   {
11202     /* VEX_W_0F381C_P_2 */
11203     { "vpabsb",         { XM, EXx }, 0 },
11204   },
11205   {
11206     /* VEX_W_0F381D_P_2 */
11207     { "vpabsw",         { XM, EXx }, 0 },
11208   },
11209   {
11210     /* VEX_W_0F381E_P_2 */
11211     { "vpabsd",         { XM, EXx }, 0 },
11212   },
11213   {
11214     /* VEX_W_0F3820_P_2 */
11215     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11216   },
11217   {
11218     /* VEX_W_0F3821_P_2 */
11219     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11220   },
11221   {
11222     /* VEX_W_0F3822_P_2 */
11223     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11224   },
11225   {
11226     /* VEX_W_0F3823_P_2 */
11227     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11228   },
11229   {
11230     /* VEX_W_0F3824_P_2 */
11231     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11232   },
11233   {
11234     /* VEX_W_0F3825_P_2 */
11235     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11236   },
11237   {
11238     /* VEX_W_0F3828_P_2 */
11239     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11240   },
11241   {
11242     /* VEX_W_0F3829_P_2 */
11243     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11244   },
11245   {
11246     /* VEX_W_0F382A_P_2_M_0 */
11247     { "vmovntdqa",      { XM, Mx }, 0 },
11248   },
11249   {
11250     /* VEX_W_0F382B_P_2 */
11251     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11252   },
11253   {
11254     /* VEX_W_0F382C_P_2_M_0 */
11255     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11256   },
11257   {
11258     /* VEX_W_0F382D_P_2_M_0 */
11259     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11260   },
11261   {
11262     /* VEX_W_0F382E_P_2_M_0 */
11263     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11264   },
11265   {
11266     /* VEX_W_0F382F_P_2_M_0 */
11267     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11268   },
11269   {
11270     /* VEX_W_0F3830_P_2 */
11271     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11272   },
11273   {
11274     /* VEX_W_0F3831_P_2 */
11275     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11276   },
11277   {
11278     /* VEX_W_0F3832_P_2 */
11279     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11280   },
11281   {
11282     /* VEX_W_0F3833_P_2 */
11283     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11284   },
11285   {
11286     /* VEX_W_0F3834_P_2 */
11287     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11288   },
11289   {
11290     /* VEX_W_0F3835_P_2 */
11291     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11292   },
11293   {
11294     /* VEX_W_0F3836_P_2  */
11295     { "vpermd",         { XM, Vex, EXx }, 0 },
11296   },
11297   {
11298     /* VEX_W_0F3837_P_2 */
11299     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11300   },
11301   {
11302     /* VEX_W_0F3838_P_2 */
11303     { "vpminsb",        { XM, Vex, EXx }, 0 },
11304   },
11305   {
11306     /* VEX_W_0F3839_P_2 */
11307     { "vpminsd",        { XM, Vex, EXx }, 0 },
11308   },
11309   {
11310     /* VEX_W_0F383A_P_2 */
11311     { "vpminuw",        { XM, Vex, EXx }, 0 },
11312   },
11313   {
11314     /* VEX_W_0F383B_P_2 */
11315     { "vpminud",        { XM, Vex, EXx }, 0 },
11316   },
11317   {
11318     /* VEX_W_0F383C_P_2 */
11319     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11320   },
11321   {
11322     /* VEX_W_0F383D_P_2 */
11323     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11324   },
11325   {
11326     /* VEX_W_0F383E_P_2 */
11327     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11328   },
11329   {
11330     /* VEX_W_0F383F_P_2 */
11331     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11332   },
11333   {
11334     /* VEX_W_0F3840_P_2 */
11335     { "vpmulld",        { XM, Vex, EXx }, 0 },
11336   },
11337   {
11338     /* VEX_W_0F3841_P_2 */
11339     { "vphminposuw",    { XM, EXx }, 0 },
11340   },
11341   {
11342     /* VEX_W_0F3846_P_2 */
11343     { "vpsravd",        { XM, Vex, EXx }, 0 },
11344   },
11345   {
11346     /* VEX_W_0F3858_P_2 */
11347     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11348   },
11349   {
11350     /* VEX_W_0F3859_P_2 */
11351     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11352   },
11353   {
11354     /* VEX_W_0F385A_P_2_M_0 */
11355     { "vbroadcasti128", { XM, Mxmm }, 0 },
11356   },
11357   {
11358     /* VEX_W_0F3878_P_2 */
11359     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11360   },
11361   {
11362     /* VEX_W_0F3879_P_2 */
11363     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11364   },
11365   {
11366     /* VEX_W_0F38DB_P_2 */
11367     { "vaesimc",        { XM, EXx }, 0 },
11368   },
11369   {
11370     /* VEX_W_0F38DC_P_2 */
11371     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11372   },
11373   {
11374     /* VEX_W_0F38DD_P_2 */
11375     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F38DE_P_2 */
11379     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11380   },
11381   {
11382     /* VEX_W_0F38DF_P_2 */
11383     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F3A00_P_2 */
11387     { Bad_Opcode },
11388     { "vpermq",         { XM, EXx, Ib }, 0 },
11389   },
11390   {
11391     /* VEX_W_0F3A01_P_2 */
11392     { Bad_Opcode },
11393     { "vpermpd",        { XM, EXx, Ib }, 0 },
11394   },
11395   {
11396     /* VEX_W_0F3A02_P_2 */
11397     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11398   },
11399   {
11400     /* VEX_W_0F3A04_P_2 */
11401     { "vpermilps",      { XM, EXx, Ib }, 0 },
11402   },
11403   {
11404     /* VEX_W_0F3A05_P_2 */
11405     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11406   },
11407   {
11408     /* VEX_W_0F3A06_P_2 */
11409     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11410   },
11411   {
11412     /* VEX_W_0F3A08_P_2 */
11413     { "vroundps",       { XM, EXx, Ib }, 0 },
11414   },
11415   {
11416     /* VEX_W_0F3A09_P_2 */
11417     { "vroundpd",       { XM, EXx, Ib }, 0 },
11418   },
11419   {
11420     /* VEX_W_0F3A0A_P_2 */
11421     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11422   },
11423   {
11424     /* VEX_W_0F3A0B_P_2 */
11425     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11426   },
11427   {
11428     /* VEX_W_0F3A0C_P_2 */
11429     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11430   },
11431   {
11432     /* VEX_W_0F3A0D_P_2 */
11433     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11434   },
11435   {
11436     /* VEX_W_0F3A0E_P_2 */
11437     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11438   },
11439   {
11440     /* VEX_W_0F3A0F_P_2 */
11441     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11442   },
11443   {
11444     /* VEX_W_0F3A14_P_2 */
11445     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11446   },
11447   {
11448     /* VEX_W_0F3A15_P_2 */
11449     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11450   },
11451   {
11452     /* VEX_W_0F3A18_P_2 */
11453     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11454   },
11455   {
11456     /* VEX_W_0F3A19_P_2 */
11457     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11458   },
11459   {
11460     /* VEX_W_0F3A20_P_2 */
11461     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11462   },
11463   {
11464     /* VEX_W_0F3A21_P_2 */
11465     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11466   },
11467   {
11468     /* VEX_W_0F3A30_P_2_LEN_0 */
11469     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11470     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11471   },
11472   {
11473     /* VEX_W_0F3A31_P_2_LEN_0 */
11474     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11475     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11476   },
11477   {
11478     /* VEX_W_0F3A32_P_2_LEN_0 */
11479     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11480     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11481   },
11482   {
11483     /* VEX_W_0F3A33_P_2_LEN_0 */
11484     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11485     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11486   },
11487   {
11488     /* VEX_W_0F3A38_P_2 */
11489     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11490   },
11491   {
11492     /* VEX_W_0F3A39_P_2 */
11493     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11494   },
11495   {
11496     /* VEX_W_0F3A40_P_2 */
11497     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11498   },
11499   {
11500     /* VEX_W_0F3A41_P_2 */
11501     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11502   },
11503   {
11504     /* VEX_W_0F3A42_P_2 */
11505     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11506   },
11507   {
11508     /* VEX_W_0F3A44_P_2 */
11509     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11510   },
11511   {
11512     /* VEX_W_0F3A46_P_2 */
11513     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11514   },
11515   {
11516     /* VEX_W_0F3A48_P_2 */
11517     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11518     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11519   },
11520   {
11521     /* VEX_W_0F3A49_P_2 */
11522     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11523     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11524   },
11525   {
11526     /* VEX_W_0F3A4A_P_2 */
11527     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11528   },
11529   {
11530     /* VEX_W_0F3A4B_P_2 */
11531     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11532   },
11533   {
11534     /* VEX_W_0F3A4C_P_2 */
11535     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11536   },
11537   {
11538     /* VEX_W_0F3A60_P_2 */
11539     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11540   },
11541   {
11542     /* VEX_W_0F3A61_P_2 */
11543     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11544   },
11545   {
11546     /* VEX_W_0F3A62_P_2 */
11547     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11548   },
11549   {
11550     /* VEX_W_0F3A63_P_2 */
11551     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11552   },
11553   {
11554     /* VEX_W_0F3ADF_P_2 */
11555     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11556   },
11557 #define NEED_VEX_W_TABLE
11558 #include "i386-dis-evex.h"
11559 #undef NEED_VEX_W_TABLE
11560 };
11561
11562 static const struct dis386 mod_table[][2] = {
11563   {
11564     /* MOD_8D */
11565     { "leaS",           { Gv, M }, 0 },
11566   },
11567   {
11568     /* MOD_C6_REG_7 */
11569     { Bad_Opcode },
11570     { RM_TABLE (RM_C6_REG_7) },
11571   },
11572   {
11573     /* MOD_C7_REG_7 */
11574     { Bad_Opcode },
11575     { RM_TABLE (RM_C7_REG_7) },
11576   },
11577   {
11578     /* MOD_FF_REG_3 */
11579     { "Jcall{T|}", { indirEp }, 0 },
11580   },
11581   {
11582     /* MOD_FF_REG_5 */
11583     { "Jjmp{T|}", { indirEp }, 0 },
11584   },
11585   {
11586     /* MOD_0F01_REG_0 */
11587     { X86_64_TABLE (X86_64_0F01_REG_0) },
11588     { RM_TABLE (RM_0F01_REG_0) },
11589   },
11590   {
11591     /* MOD_0F01_REG_1 */
11592     { X86_64_TABLE (X86_64_0F01_REG_1) },
11593     { RM_TABLE (RM_0F01_REG_1) },
11594   },
11595   {
11596     /* MOD_0F01_REG_2 */
11597     { X86_64_TABLE (X86_64_0F01_REG_2) },
11598     { RM_TABLE (RM_0F01_REG_2) },
11599   },
11600   {
11601     /* MOD_0F01_REG_3 */
11602     { X86_64_TABLE (X86_64_0F01_REG_3) },
11603     { RM_TABLE (RM_0F01_REG_3) },
11604   },
11605   {
11606     /* MOD_0F01_REG_7 */
11607     { "invlpg",         { Mb }, 0 },
11608     { RM_TABLE (RM_0F01_REG_7) },
11609   },
11610   {
11611     /* MOD_0F12_PREFIX_0 */
11612     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11613     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11614   },
11615   {
11616     /* MOD_0F13 */
11617     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11618   },
11619   {
11620     /* MOD_0F16_PREFIX_0 */
11621     { "movhps",         { XM, EXq }, 0 },
11622     { "movlhps",        { XM, EXq }, 0 },
11623   },
11624   {
11625     /* MOD_0F17 */
11626     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11627   },
11628   {
11629     /* MOD_0F18_REG_0 */
11630     { "prefetchnta",    { Mb }, 0 },
11631   },
11632   {
11633     /* MOD_0F18_REG_1 */
11634     { "prefetcht0",     { Mb }, 0 },
11635   },
11636   {
11637     /* MOD_0F18_REG_2 */
11638     { "prefetcht1",     { Mb }, 0 },
11639   },
11640   {
11641     /* MOD_0F18_REG_3 */
11642     { "prefetcht2",     { Mb }, 0 },
11643   },
11644   {
11645     /* MOD_0F18_REG_4 */
11646     { "nop/reserved",   { Mb }, 0 },
11647   },
11648   {
11649     /* MOD_0F18_REG_5 */
11650     { "nop/reserved",   { Mb }, 0 },
11651   },
11652   {
11653     /* MOD_0F18_REG_6 */
11654     { "nop/reserved",   { Mb }, 0 },
11655   },
11656   {
11657     /* MOD_0F18_REG_7 */
11658     { "nop/reserved",   { Mb }, 0 },
11659   },
11660   {
11661     /* MOD_0F1A_PREFIX_0 */
11662     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11663     { "nopQ",           { Ev }, 0 },
11664   },
11665   {
11666     /* MOD_0F1B_PREFIX_0 */
11667     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11668     { "nopQ",           { Ev }, 0 },
11669   },
11670   {
11671     /* MOD_0F1B_PREFIX_1 */
11672     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11673     { "nopQ",           { Ev }, 0 },
11674   },
11675   {
11676     /* MOD_0F24 */
11677     { Bad_Opcode },
11678     { "movL",           { Rd, Td }, 0 },
11679   },
11680   {
11681     /* MOD_0F26 */
11682     { Bad_Opcode },
11683     { "movL",           { Td, Rd }, 0 },
11684   },
11685   {
11686     /* MOD_0F2B_PREFIX_0 */
11687     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11688   },
11689   {
11690     /* MOD_0F2B_PREFIX_1 */
11691     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11692   },
11693   {
11694     /* MOD_0F2B_PREFIX_2 */
11695     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11696   },
11697   {
11698     /* MOD_0F2B_PREFIX_3 */
11699     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11700   },
11701   {
11702     /* MOD_0F51 */
11703     { Bad_Opcode },
11704     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11705   },
11706   {
11707     /* MOD_0F71_REG_2 */
11708     { Bad_Opcode },
11709     { "psrlw",          { MS, Ib }, 0 },
11710   },
11711   {
11712     /* MOD_0F71_REG_4 */
11713     { Bad_Opcode },
11714     { "psraw",          { MS, Ib }, 0 },
11715   },
11716   {
11717     /* MOD_0F71_REG_6 */
11718     { Bad_Opcode },
11719     { "psllw",          { MS, Ib }, 0 },
11720   },
11721   {
11722     /* MOD_0F72_REG_2 */
11723     { Bad_Opcode },
11724     { "psrld",          { MS, Ib }, 0 },
11725   },
11726   {
11727     /* MOD_0F72_REG_4 */
11728     { Bad_Opcode },
11729     { "psrad",          { MS, Ib }, 0 },
11730   },
11731   {
11732     /* MOD_0F72_REG_6 */
11733     { Bad_Opcode },
11734     { "pslld",          { MS, Ib }, 0 },
11735   },
11736   {
11737     /* MOD_0F73_REG_2 */
11738     { Bad_Opcode },
11739     { "psrlq",          { MS, Ib }, 0 },
11740   },
11741   {
11742     /* MOD_0F73_REG_3 */
11743     { Bad_Opcode },
11744     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11745   },
11746   {
11747     /* MOD_0F73_REG_6 */
11748     { Bad_Opcode },
11749     { "psllq",          { MS, Ib }, 0 },
11750   },
11751   {
11752     /* MOD_0F73_REG_7 */
11753     { Bad_Opcode },
11754     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11755   },
11756   {
11757     /* MOD_0FAE_REG_0 */
11758     { "fxsave",         { FXSAVE }, 0 },
11759     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11760   },
11761   {
11762     /* MOD_0FAE_REG_1 */
11763     { "fxrstor",        { FXSAVE }, 0 },
11764     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11765   },
11766   {
11767     /* MOD_0FAE_REG_2 */
11768     { "ldmxcsr",        { Md }, 0 },
11769     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11770   },
11771   {
11772     /* MOD_0FAE_REG_3 */
11773     { "stmxcsr",        { Md }, 0 },
11774     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11775   },
11776   {
11777     /* MOD_0FAE_REG_4 */
11778     { "xsave",          { FXSAVE }, 0 },
11779   },
11780   {
11781     /* MOD_0FAE_REG_5 */
11782     { "xrstor",         { FXSAVE }, 0 },
11783     { RM_TABLE (RM_0FAE_REG_5) },
11784   },
11785   {
11786     /* MOD_0FAE_REG_6 */
11787     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11788     { RM_TABLE (RM_0FAE_REG_6) },
11789   },
11790   {
11791     /* MOD_0FAE_REG_7 */
11792     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11793     { RM_TABLE (RM_0FAE_REG_7) },
11794   },
11795   {
11796     /* MOD_0FB2 */
11797     { "lssS",           { Gv, Mp }, 0 },
11798   },
11799   {
11800     /* MOD_0FB4 */
11801     { "lfsS",           { Gv, Mp }, 0 },
11802   },
11803   {
11804     /* MOD_0FB5 */
11805     { "lgsS",           { Gv, Mp }, 0 },
11806   },
11807   {
11808     /* MOD_0FC7_REG_3 */
11809     { "xrstors",                { FXSAVE }, 0 },
11810   },
11811   {
11812     /* MOD_0FC7_REG_4 */
11813     { "xsavec",         { FXSAVE }, 0 },
11814   },
11815   {
11816     /* MOD_0FC7_REG_5 */
11817     { "xsaves",         { FXSAVE }, 0 },
11818   },
11819   {
11820     /* MOD_0FC7_REG_6 */
11821     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11822     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11823   },
11824   {
11825     /* MOD_0FC7_REG_7 */
11826     { "vmptrst",        { Mq }, 0 },
11827     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11828   },
11829   {
11830     /* MOD_0FD7 */
11831     { Bad_Opcode },
11832     { "pmovmskb",       { Gdq, MS }, 0 },
11833   },
11834   {
11835     /* MOD_0FE7_PREFIX_2 */
11836     { "movntdq",        { Mx, XM }, 0 },
11837   },
11838   {
11839     /* MOD_0FF0_PREFIX_3 */
11840     { "lddqu",          { XM, M }, 0 },
11841   },
11842   {
11843     /* MOD_0F382A_PREFIX_2 */
11844     { "movntdqa",       { XM, Mx }, 0 },
11845   },
11846   {
11847     /* MOD_62_32BIT */
11848     { "bound{S|}",      { Gv, Ma }, 0 },
11849     { EVEX_TABLE (EVEX_0F) },
11850   },
11851   {
11852     /* MOD_C4_32BIT */
11853     { "lesS",           { Gv, Mp }, 0 },
11854     { VEX_C4_TABLE (VEX_0F) },
11855   },
11856   {
11857     /* MOD_C5_32BIT */
11858     { "ldsS",           { Gv, Mp }, 0 },
11859     { VEX_C5_TABLE (VEX_0F) },
11860   },
11861   {
11862     /* MOD_VEX_0F12_PREFIX_0 */
11863     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11864     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11865   },
11866   {
11867     /* MOD_VEX_0F13 */
11868     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11869   },
11870   {
11871     /* MOD_VEX_0F16_PREFIX_0 */
11872     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11873     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11874   },
11875   {
11876     /* MOD_VEX_0F17 */
11877     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11878   },
11879   {
11880     /* MOD_VEX_0F2B */
11881     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11882   },
11883   {
11884     /* MOD_VEX_0F50 */
11885     { Bad_Opcode },
11886     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11887   },
11888   {
11889     /* MOD_VEX_0F71_REG_2 */
11890     { Bad_Opcode },
11891     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11892   },
11893   {
11894     /* MOD_VEX_0F71_REG_4 */
11895     { Bad_Opcode },
11896     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11897   },
11898   {
11899     /* MOD_VEX_0F71_REG_6 */
11900     { Bad_Opcode },
11901     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11902   },
11903   {
11904     /* MOD_VEX_0F72_REG_2 */
11905     { Bad_Opcode },
11906     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11907   },
11908   {
11909     /* MOD_VEX_0F72_REG_4 */
11910     { Bad_Opcode },
11911     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11912   },
11913   {
11914     /* MOD_VEX_0F72_REG_6 */
11915     { Bad_Opcode },
11916     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11917   },
11918   {
11919     /* MOD_VEX_0F73_REG_2 */
11920     { Bad_Opcode },
11921     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11922   },
11923   {
11924     /* MOD_VEX_0F73_REG_3 */
11925     { Bad_Opcode },
11926     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11927   },
11928   {
11929     /* MOD_VEX_0F73_REG_6 */
11930     { Bad_Opcode },
11931     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11932   },
11933   {
11934     /* MOD_VEX_0F73_REG_7 */
11935     { Bad_Opcode },
11936     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11937   },
11938   {
11939     /* MOD_VEX_0FAE_REG_2 */
11940     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11941   },
11942   {
11943     /* MOD_VEX_0FAE_REG_3 */
11944     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11945   },
11946   {
11947     /* MOD_VEX_0FD7_PREFIX_2 */
11948     { Bad_Opcode },
11949     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11950   },
11951   {
11952     /* MOD_VEX_0FE7_PREFIX_2 */
11953     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11954   },
11955   {
11956     /* MOD_VEX_0FF0_PREFIX_3 */
11957     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11958   },
11959   {
11960     /* MOD_VEX_0F381A_PREFIX_2 */
11961     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11962   },
11963   {
11964     /* MOD_VEX_0F382A_PREFIX_2 */
11965     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11966   },
11967   {
11968     /* MOD_VEX_0F382C_PREFIX_2 */
11969     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11970   },
11971   {
11972     /* MOD_VEX_0F382D_PREFIX_2 */
11973     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11974   },
11975   {
11976     /* MOD_VEX_0F382E_PREFIX_2 */
11977     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11978   },
11979   {
11980     /* MOD_VEX_0F382F_PREFIX_2 */
11981     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11982   },
11983   {
11984     /* MOD_VEX_0F385A_PREFIX_2 */
11985     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11986   },
11987   {
11988     /* MOD_VEX_0F388C_PREFIX_2 */
11989     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
11990   },
11991   {
11992     /* MOD_VEX_0F388E_PREFIX_2 */
11993     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
11994   },
11995 #define NEED_MOD_TABLE
11996 #include "i386-dis-evex.h"
11997 #undef NEED_MOD_TABLE
11998 };
11999
12000 static const struct dis386 rm_table[][8] = {
12001   {
12002     /* RM_C6_REG_7 */
12003     { "xabort",         { Skip_MODRM, Ib }, 0 },
12004   },
12005   {
12006     /* RM_C7_REG_7 */
12007     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12008   },
12009   {
12010     /* RM_0F01_REG_0 */
12011     { Bad_Opcode },
12012     { "vmcall",         { Skip_MODRM }, 0 },
12013     { "vmlaunch",       { Skip_MODRM }, 0 },
12014     { "vmresume",       { Skip_MODRM }, 0 },
12015     { "vmxoff",         { Skip_MODRM }, 0 },
12016   },
12017   {
12018     /* RM_0F01_REG_1 */
12019     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12020     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12021     { "clac",           { Skip_MODRM }, 0 },
12022     { "stac",           { Skip_MODRM }, 0 },
12023     { Bad_Opcode },
12024     { Bad_Opcode },
12025     { Bad_Opcode },
12026     { "encls",          { Skip_MODRM }, 0 },
12027   },
12028   {
12029     /* RM_0F01_REG_2 */
12030     { "xgetbv",         { Skip_MODRM }, 0 },
12031     { "xsetbv",         { Skip_MODRM }, 0 },
12032     { Bad_Opcode },
12033     { Bad_Opcode },
12034     { "vmfunc",         { Skip_MODRM }, 0 },
12035     { "xend",           { Skip_MODRM }, 0 },
12036     { "xtest",          { Skip_MODRM }, 0 },
12037     { "enclu",          { Skip_MODRM }, 0 },
12038   },
12039   {
12040     /* RM_0F01_REG_3 */
12041     { "vmrun",          { Skip_MODRM }, 0 },
12042     { "vmmcall",        { Skip_MODRM }, 0 },
12043     { "vmload",         { Skip_MODRM }, 0 },
12044     { "vmsave",         { Skip_MODRM }, 0 },
12045     { "stgi",           { Skip_MODRM }, 0 },
12046     { "clgi",           { Skip_MODRM }, 0 },
12047     { "skinit",         { Skip_MODRM }, 0 },
12048     { "invlpga",        { Skip_MODRM }, 0 },
12049   },
12050   {
12051     /* RM_0F01_REG_7 */
12052     { "swapgs",         { Skip_MODRM }, 0  },
12053     { "rdtscp",         { Skip_MODRM }, 0  },
12054     { Bad_Opcode },
12055     { Bad_Opcode },
12056     { "clzero",         { Skip_MODRM }, 0  },
12057   },
12058   {
12059     /* RM_0FAE_REG_5 */
12060     { "lfence",         { Skip_MODRM }, 0 },
12061   },
12062   {
12063     /* RM_0FAE_REG_6 */
12064     { "mfence",         { Skip_MODRM }, 0 },
12065   },
12066   {
12067     /* RM_0FAE_REG_7 */
12068     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12069   },
12070 };
12071
12072 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12073
12074 /* We use the high bit to indicate different name for the same
12075    prefix.  */
12076 #define REP_PREFIX      (0xf3 | 0x100)
12077 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12078 #define XRELEASE_PREFIX (0xf3 | 0x400)
12079 #define BND_PREFIX      (0xf2 | 0x400)
12080
12081 static int
12082 ckprefix (void)
12083 {
12084   int newrex, i, length;
12085   rex = 0;
12086   rex_ignored = 0;
12087   prefixes = 0;
12088   used_prefixes = 0;
12089   rex_used = 0;
12090   last_lock_prefix = -1;
12091   last_repz_prefix = -1;
12092   last_repnz_prefix = -1;
12093   last_data_prefix = -1;
12094   last_addr_prefix = -1;
12095   last_rex_prefix = -1;
12096   last_seg_prefix = -1;
12097   fwait_prefix = -1;
12098   active_seg_prefix = 0;
12099   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12100     all_prefixes[i] = 0;
12101   i = 0;
12102   length = 0;
12103   /* The maximum instruction length is 15bytes.  */
12104   while (length < MAX_CODE_LENGTH - 1)
12105     {
12106       FETCH_DATA (the_info, codep + 1);
12107       newrex = 0;
12108       switch (*codep)
12109         {
12110         /* REX prefixes family.  */
12111         case 0x40:
12112         case 0x41:
12113         case 0x42:
12114         case 0x43:
12115         case 0x44:
12116         case 0x45:
12117         case 0x46:
12118         case 0x47:
12119         case 0x48:
12120         case 0x49:
12121         case 0x4a:
12122         case 0x4b:
12123         case 0x4c:
12124         case 0x4d:
12125         case 0x4e:
12126         case 0x4f:
12127           if (address_mode == mode_64bit)
12128             newrex = *codep;
12129           else
12130             return 1;
12131           last_rex_prefix = i;
12132           break;
12133         case 0xf3:
12134           prefixes |= PREFIX_REPZ;
12135           last_repz_prefix = i;
12136           break;
12137         case 0xf2:
12138           prefixes |= PREFIX_REPNZ;
12139           last_repnz_prefix = i;
12140           break;
12141         case 0xf0:
12142           prefixes |= PREFIX_LOCK;
12143           last_lock_prefix = i;
12144           break;
12145         case 0x2e:
12146           prefixes |= PREFIX_CS;
12147           last_seg_prefix = i;
12148           active_seg_prefix = PREFIX_CS;
12149           break;
12150         case 0x36:
12151           prefixes |= PREFIX_SS;
12152           last_seg_prefix = i;
12153           active_seg_prefix = PREFIX_SS;
12154           break;
12155         case 0x3e:
12156           prefixes |= PREFIX_DS;
12157           last_seg_prefix = i;
12158           active_seg_prefix = PREFIX_DS;
12159           break;
12160         case 0x26:
12161           prefixes |= PREFIX_ES;
12162           last_seg_prefix = i;
12163           active_seg_prefix = PREFIX_ES;
12164           break;
12165         case 0x64:
12166           prefixes |= PREFIX_FS;
12167           last_seg_prefix = i;
12168           active_seg_prefix = PREFIX_FS;
12169           break;
12170         case 0x65:
12171           prefixes |= PREFIX_GS;
12172           last_seg_prefix = i;
12173           active_seg_prefix = PREFIX_GS;
12174           break;
12175         case 0x66:
12176           prefixes |= PREFIX_DATA;
12177           last_data_prefix = i;
12178           break;
12179         case 0x67:
12180           prefixes |= PREFIX_ADDR;
12181           last_addr_prefix = i;
12182           break;
12183         case FWAIT_OPCODE:
12184           /* fwait is really an instruction.  If there are prefixes
12185              before the fwait, they belong to the fwait, *not* to the
12186              following instruction.  */
12187           fwait_prefix = i;
12188           if (prefixes || rex)
12189             {
12190               prefixes |= PREFIX_FWAIT;
12191               codep++;
12192               /* This ensures that the previous REX prefixes are noticed
12193                  as unused prefixes, as in the return case below.  */
12194               rex_used = rex;
12195               return 1;
12196             }
12197           prefixes = PREFIX_FWAIT;
12198           break;
12199         default:
12200           return 1;
12201         }
12202       /* Rex is ignored when followed by another prefix.  */
12203       if (rex)
12204         {
12205           rex_used = rex;
12206           return 1;
12207         }
12208       if (*codep != FWAIT_OPCODE)
12209         all_prefixes[i++] = *codep;
12210       rex = newrex;
12211       codep++;
12212       length++;
12213     }
12214   return 0;
12215 }
12216
12217 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12218    prefix byte.  */
12219
12220 static const char *
12221 prefix_name (int pref, int sizeflag)
12222 {
12223   static const char *rexes [16] =
12224     {
12225       "rex",            /* 0x40 */
12226       "rex.B",          /* 0x41 */
12227       "rex.X",          /* 0x42 */
12228       "rex.XB",         /* 0x43 */
12229       "rex.R",          /* 0x44 */
12230       "rex.RB",         /* 0x45 */
12231       "rex.RX",         /* 0x46 */
12232       "rex.RXB",        /* 0x47 */
12233       "rex.W",          /* 0x48 */
12234       "rex.WB",         /* 0x49 */
12235       "rex.WX",         /* 0x4a */
12236       "rex.WXB",        /* 0x4b */
12237       "rex.WR",         /* 0x4c */
12238       "rex.WRB",        /* 0x4d */
12239       "rex.WRX",        /* 0x4e */
12240       "rex.WRXB",       /* 0x4f */
12241     };
12242
12243   switch (pref)
12244     {
12245     /* REX prefixes family.  */
12246     case 0x40:
12247     case 0x41:
12248     case 0x42:
12249     case 0x43:
12250     case 0x44:
12251     case 0x45:
12252     case 0x46:
12253     case 0x47:
12254     case 0x48:
12255     case 0x49:
12256     case 0x4a:
12257     case 0x4b:
12258     case 0x4c:
12259     case 0x4d:
12260     case 0x4e:
12261     case 0x4f:
12262       return rexes [pref - 0x40];
12263     case 0xf3:
12264       return "repz";
12265     case 0xf2:
12266       return "repnz";
12267     case 0xf0:
12268       return "lock";
12269     case 0x2e:
12270       return "cs";
12271     case 0x36:
12272       return "ss";
12273     case 0x3e:
12274       return "ds";
12275     case 0x26:
12276       return "es";
12277     case 0x64:
12278       return "fs";
12279     case 0x65:
12280       return "gs";
12281     case 0x66:
12282       return (sizeflag & DFLAG) ? "data16" : "data32";
12283     case 0x67:
12284       if (address_mode == mode_64bit)
12285         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12286       else
12287         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12288     case FWAIT_OPCODE:
12289       return "fwait";
12290     case REP_PREFIX:
12291       return "rep";
12292     case XACQUIRE_PREFIX:
12293       return "xacquire";
12294     case XRELEASE_PREFIX:
12295       return "xrelease";
12296     case BND_PREFIX:
12297       return "bnd";
12298     default:
12299       return NULL;
12300     }
12301 }
12302
12303 static char op_out[MAX_OPERANDS][100];
12304 static int op_ad, op_index[MAX_OPERANDS];
12305 static int two_source_ops;
12306 static bfd_vma op_address[MAX_OPERANDS];
12307 static bfd_vma op_riprel[MAX_OPERANDS];
12308 static bfd_vma start_pc;
12309
12310 /*
12311  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12312  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12313  *   section of the "Virtual 8086 Mode" chapter.)
12314  * 'pc' should be the address of this instruction, it will
12315  *   be used to print the target address if this is a relative jump or call
12316  * The function returns the length of this instruction in bytes.
12317  */
12318
12319 static char intel_syntax;
12320 static char intel_mnemonic = !SYSV386_COMPAT;
12321 static char open_char;
12322 static char close_char;
12323 static char separator_char;
12324 static char scale_char;
12325
12326 /* Here for backwards compatibility.  When gdb stops using
12327    print_insn_i386_att and print_insn_i386_intel these functions can
12328    disappear, and print_insn_i386 be merged into print_insn.  */
12329 int
12330 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12331 {
12332   intel_syntax = 0;
12333
12334   return print_insn (pc, info);
12335 }
12336
12337 int
12338 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12339 {
12340   intel_syntax = 1;
12341
12342   return print_insn (pc, info);
12343 }
12344
12345 int
12346 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12347 {
12348   intel_syntax = -1;
12349
12350   return print_insn (pc, info);
12351 }
12352
12353 void
12354 print_i386_disassembler_options (FILE *stream)
12355 {
12356   fprintf (stream, _("\n\
12357 The following i386/x86-64 specific disassembler options are supported for use\n\
12358 with the -M switch (multiple options should be separated by commas):\n"));
12359
12360   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12361   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12362   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12363   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12364   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12365   fprintf (stream, _("  att-mnemonic\n"
12366                      "              Display instruction in AT&T mnemonic\n"));
12367   fprintf (stream, _("  intel-mnemonic\n"
12368                      "              Display instruction in Intel mnemonic\n"));
12369   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12370   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12371   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12372   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12373   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12374   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12375 }
12376
12377 /* Bad opcode.  */
12378 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12379
12380 /* Get a pointer to struct dis386 with a valid name.  */
12381
12382 static const struct dis386 *
12383 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12384 {
12385   int vindex, vex_table_index;
12386
12387   if (dp->name != NULL)
12388     return dp;
12389
12390   switch (dp->op[0].bytemode)
12391     {
12392     case USE_REG_TABLE:
12393       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12394       break;
12395
12396     case USE_MOD_TABLE:
12397       vindex = modrm.mod == 0x3 ? 1 : 0;
12398       dp = &mod_table[dp->op[1].bytemode][vindex];
12399       break;
12400
12401     case USE_RM_TABLE:
12402       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12403       break;
12404
12405     case USE_PREFIX_TABLE:
12406       if (need_vex)
12407         {
12408           /* The prefix in VEX is implicit.  */
12409           switch (vex.prefix)
12410             {
12411             case 0:
12412               vindex = 0;
12413               break;
12414             case REPE_PREFIX_OPCODE:
12415               vindex = 1;
12416               break;
12417             case DATA_PREFIX_OPCODE:
12418               vindex = 2;
12419               break;
12420             case REPNE_PREFIX_OPCODE:
12421               vindex = 3;
12422               break;
12423             default:
12424               abort ();
12425               break;
12426             }
12427         }
12428       else
12429         {
12430           int last_prefix = -1;
12431           int prefix = 0;
12432           vindex = 0;
12433           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12434              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12435              last one wins.  */
12436           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12437             {
12438               if (last_repz_prefix > last_repnz_prefix)
12439                 {
12440                   vindex = 1;
12441                   prefix = PREFIX_REPZ;
12442                   last_prefix = last_repz_prefix;
12443                 }
12444               else
12445                 {
12446                   vindex = 3;
12447                   prefix = PREFIX_REPNZ;
12448                   last_prefix = last_repnz_prefix;
12449                 }
12450
12451               /* Check if prefix should be ignored.  */
12452               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12453                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12454                    & prefix) != 0)
12455                 vindex = 0;
12456             }
12457
12458           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12459             {
12460               vindex = 2;
12461               prefix = PREFIX_DATA;
12462               last_prefix = last_data_prefix;
12463             }
12464
12465           if (vindex != 0)
12466             {
12467               used_prefixes |= prefix;
12468               all_prefixes[last_prefix] = 0;
12469             }
12470         }
12471       dp = &prefix_table[dp->op[1].bytemode][vindex];
12472       break;
12473
12474     case USE_X86_64_TABLE:
12475       vindex = address_mode == mode_64bit ? 1 : 0;
12476       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12477       break;
12478
12479     case USE_3BYTE_TABLE:
12480       FETCH_DATA (info, codep + 2);
12481       vindex = *codep++;
12482       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12483       end_codep = codep;
12484       modrm.mod = (*codep >> 6) & 3;
12485       modrm.reg = (*codep >> 3) & 7;
12486       modrm.rm = *codep & 7;
12487       break;
12488
12489     case USE_VEX_LEN_TABLE:
12490       if (!need_vex)
12491         abort ();
12492
12493       switch (vex.length)
12494         {
12495         case 128:
12496           vindex = 0;
12497           break;
12498         case 256:
12499           vindex = 1;
12500           break;
12501         default:
12502           abort ();
12503           break;
12504         }
12505
12506       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12507       break;
12508
12509     case USE_XOP_8F_TABLE:
12510       FETCH_DATA (info, codep + 3);
12511       /* All bits in the REX prefix are ignored.  */
12512       rex_ignored = rex;
12513       rex = ~(*codep >> 5) & 0x7;
12514
12515       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12516       switch ((*codep & 0x1f))
12517         {
12518         default:
12519           dp = &bad_opcode;
12520           return dp;
12521         case 0x8:
12522           vex_table_index = XOP_08;
12523           break;
12524         case 0x9:
12525           vex_table_index = XOP_09;
12526           break;
12527         case 0xa:
12528           vex_table_index = XOP_0A;
12529           break;
12530         }
12531       codep++;
12532       vex.w = *codep & 0x80;
12533       if (vex.w && address_mode == mode_64bit)
12534         rex |= REX_W;
12535
12536       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12537       if (address_mode != mode_64bit
12538           && vex.register_specifier > 0x7)
12539         {
12540           dp = &bad_opcode;
12541           return dp;
12542         }
12543
12544       vex.length = (*codep & 0x4) ? 256 : 128;
12545       switch ((*codep & 0x3))
12546         {
12547         case 0:
12548           vex.prefix = 0;
12549           break;
12550         case 1:
12551           vex.prefix = DATA_PREFIX_OPCODE;
12552           break;
12553         case 2:
12554           vex.prefix = REPE_PREFIX_OPCODE;
12555           break;
12556         case 3:
12557           vex.prefix = REPNE_PREFIX_OPCODE;
12558           break;
12559         }
12560       need_vex = 1;
12561       need_vex_reg = 1;
12562       codep++;
12563       vindex = *codep++;
12564       dp = &xop_table[vex_table_index][vindex];
12565
12566       end_codep = codep;
12567       FETCH_DATA (info, codep + 1);
12568       modrm.mod = (*codep >> 6) & 3;
12569       modrm.reg = (*codep >> 3) & 7;
12570       modrm.rm = *codep & 7;
12571       break;
12572
12573     case USE_VEX_C4_TABLE:
12574       /* VEX prefix.  */
12575       FETCH_DATA (info, codep + 3);
12576       /* All bits in the REX prefix are ignored.  */
12577       rex_ignored = rex;
12578       rex = ~(*codep >> 5) & 0x7;
12579       switch ((*codep & 0x1f))
12580         {
12581         default:
12582           dp = &bad_opcode;
12583           return dp;
12584         case 0x1:
12585           vex_table_index = VEX_0F;
12586           break;
12587         case 0x2:
12588           vex_table_index = VEX_0F38;
12589           break;
12590         case 0x3:
12591           vex_table_index = VEX_0F3A;
12592           break;
12593         }
12594       codep++;
12595       vex.w = *codep & 0x80;
12596       if (vex.w && address_mode == mode_64bit)
12597         rex |= REX_W;
12598
12599       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12600       if (address_mode != mode_64bit
12601           && vex.register_specifier > 0x7)
12602         {
12603           dp = &bad_opcode;
12604           return dp;
12605         }
12606
12607       vex.length = (*codep & 0x4) ? 256 : 128;
12608       switch ((*codep & 0x3))
12609         {
12610         case 0:
12611           vex.prefix = 0;
12612           break;
12613         case 1:
12614           vex.prefix = DATA_PREFIX_OPCODE;
12615           break;
12616         case 2:
12617           vex.prefix = REPE_PREFIX_OPCODE;
12618           break;
12619         case 3:
12620           vex.prefix = REPNE_PREFIX_OPCODE;
12621           break;
12622         }
12623       need_vex = 1;
12624       need_vex_reg = 1;
12625       codep++;
12626       vindex = *codep++;
12627       dp = &vex_table[vex_table_index][vindex];
12628       end_codep = codep;
12629       /* There is no MODRM byte for VEX [82|77].  */
12630       if (vindex != 0x77 && vindex != 0x82)
12631         {
12632           FETCH_DATA (info, codep + 1);
12633           modrm.mod = (*codep >> 6) & 3;
12634           modrm.reg = (*codep >> 3) & 7;
12635           modrm.rm = *codep & 7;
12636         }
12637       break;
12638
12639     case USE_VEX_C5_TABLE:
12640       /* VEX prefix.  */
12641       FETCH_DATA (info, codep + 2);
12642       /* All bits in the REX prefix are ignored.  */
12643       rex_ignored = rex;
12644       rex = (*codep & 0x80) ? 0 : REX_R;
12645
12646       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12647       if (address_mode != mode_64bit
12648           && vex.register_specifier > 0x7)
12649         {
12650           dp = &bad_opcode;
12651           return dp;
12652         }
12653
12654       vex.w = 0;
12655
12656       vex.length = (*codep & 0x4) ? 256 : 128;
12657       switch ((*codep & 0x3))
12658         {
12659         case 0:
12660           vex.prefix = 0;
12661           break;
12662         case 1:
12663           vex.prefix = DATA_PREFIX_OPCODE;
12664           break;
12665         case 2:
12666           vex.prefix = REPE_PREFIX_OPCODE;
12667           break;
12668         case 3:
12669           vex.prefix = REPNE_PREFIX_OPCODE;
12670           break;
12671         }
12672       need_vex = 1;
12673       need_vex_reg = 1;
12674       codep++;
12675       vindex = *codep++;
12676       dp = &vex_table[dp->op[1].bytemode][vindex];
12677       end_codep = codep;
12678       /* There is no MODRM byte for VEX [82|77].  */
12679       if (vindex != 0x77 && vindex != 0x82)
12680         {
12681           FETCH_DATA (info, codep + 1);
12682           modrm.mod = (*codep >> 6) & 3;
12683           modrm.reg = (*codep >> 3) & 7;
12684           modrm.rm = *codep & 7;
12685         }
12686       break;
12687
12688     case USE_VEX_W_TABLE:
12689       if (!need_vex)
12690         abort ();
12691
12692       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12693       break;
12694
12695     case USE_EVEX_TABLE:
12696       two_source_ops = 0;
12697       /* EVEX prefix.  */
12698       vex.evex = 1;
12699       FETCH_DATA (info, codep + 4);
12700       /* All bits in the REX prefix are ignored.  */
12701       rex_ignored = rex;
12702       /* The first byte after 0x62.  */
12703       rex = ~(*codep >> 5) & 0x7;
12704       vex.r = *codep & 0x10;
12705       switch ((*codep & 0xf))
12706         {
12707         default:
12708           return &bad_opcode;
12709         case 0x1:
12710           vex_table_index = EVEX_0F;
12711           break;
12712         case 0x2:
12713           vex_table_index = EVEX_0F38;
12714           break;
12715         case 0x3:
12716           vex_table_index = EVEX_0F3A;
12717           break;
12718         }
12719
12720       /* The second byte after 0x62.  */
12721       codep++;
12722       vex.w = *codep & 0x80;
12723       if (vex.w && address_mode == mode_64bit)
12724         rex |= REX_W;
12725
12726       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12727       if (address_mode != mode_64bit)
12728         {
12729           /* In 16/32-bit mode silently ignore following bits.  */
12730           rex &= ~REX_B;
12731           vex.r = 1;
12732           vex.v = 1;
12733           vex.register_specifier &= 0x7;
12734         }
12735
12736       /* The U bit.  */
12737       if (!(*codep & 0x4))
12738         return &bad_opcode;
12739
12740       switch ((*codep & 0x3))
12741         {
12742         case 0:
12743           vex.prefix = 0;
12744           break;
12745         case 1:
12746           vex.prefix = DATA_PREFIX_OPCODE;
12747           break;
12748         case 2:
12749           vex.prefix = REPE_PREFIX_OPCODE;
12750           break;
12751         case 3:
12752           vex.prefix = REPNE_PREFIX_OPCODE;
12753           break;
12754         }
12755
12756       /* The third byte after 0x62.  */
12757       codep++;
12758
12759       /* Remember the static rounding bits.  */
12760       vex.ll = (*codep >> 5) & 3;
12761       vex.b = (*codep & 0x10) != 0;
12762
12763       vex.v = *codep & 0x8;
12764       vex.mask_register_specifier = *codep & 0x7;
12765       vex.zeroing = *codep & 0x80;
12766
12767       need_vex = 1;
12768       need_vex_reg = 1;
12769       codep++;
12770       vindex = *codep++;
12771       dp = &evex_table[vex_table_index][vindex];
12772       end_codep = codep;
12773       FETCH_DATA (info, codep + 1);
12774       modrm.mod = (*codep >> 6) & 3;
12775       modrm.reg = (*codep >> 3) & 7;
12776       modrm.rm = *codep & 7;
12777
12778       /* Set vector length.  */
12779       if (modrm.mod == 3 && vex.b)
12780         vex.length = 512;
12781       else
12782         {
12783           switch (vex.ll)
12784             {
12785             case 0x0:
12786               vex.length = 128;
12787               break;
12788             case 0x1:
12789               vex.length = 256;
12790               break;
12791             case 0x2:
12792               vex.length = 512;
12793               break;
12794             default:
12795               return &bad_opcode;
12796             }
12797         }
12798       break;
12799
12800     case 0:
12801       dp = &bad_opcode;
12802       break;
12803
12804     default:
12805       abort ();
12806     }
12807
12808   if (dp->name != NULL)
12809     return dp;
12810   else
12811     return get_valid_dis386 (dp, info);
12812 }
12813
12814 static void
12815 get_sib (disassemble_info *info, int sizeflag)
12816 {
12817   /* If modrm.mod == 3, operand must be register.  */
12818   if (need_modrm
12819       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12820       && modrm.mod != 3
12821       && modrm.rm == 4)
12822     {
12823       FETCH_DATA (info, codep + 2);
12824       sib.index = (codep [1] >> 3) & 7;
12825       sib.scale = (codep [1] >> 6) & 3;
12826       sib.base = codep [1] & 7;
12827     }
12828 }
12829
12830 static int
12831 print_insn (bfd_vma pc, disassemble_info *info)
12832 {
12833   const struct dis386 *dp;
12834   int i;
12835   char *op_txt[MAX_OPERANDS];
12836   int needcomma;
12837   int sizeflag, orig_sizeflag;
12838   const char *p;
12839   struct dis_private priv;
12840   int prefix_length;
12841
12842   priv.orig_sizeflag = AFLAG | DFLAG;
12843   if ((info->mach & bfd_mach_i386_i386) != 0)
12844     address_mode = mode_32bit;
12845   else if (info->mach == bfd_mach_i386_i8086)
12846     {
12847       address_mode = mode_16bit;
12848       priv.orig_sizeflag = 0;
12849     }
12850   else
12851     address_mode = mode_64bit;
12852
12853   if (intel_syntax == (char) -1)
12854     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12855
12856   for (p = info->disassembler_options; p != NULL; )
12857     {
12858       if (CONST_STRNEQ (p, "x86-64"))
12859         {
12860           address_mode = mode_64bit;
12861           priv.orig_sizeflag = AFLAG | DFLAG;
12862         }
12863       else if (CONST_STRNEQ (p, "i386"))
12864         {
12865           address_mode = mode_32bit;
12866           priv.orig_sizeflag = AFLAG | DFLAG;
12867         }
12868       else if (CONST_STRNEQ (p, "i8086"))
12869         {
12870           address_mode = mode_16bit;
12871           priv.orig_sizeflag = 0;
12872         }
12873       else if (CONST_STRNEQ (p, "intel"))
12874         {
12875           intel_syntax = 1;
12876           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12877             intel_mnemonic = 1;
12878         }
12879       else if (CONST_STRNEQ (p, "att"))
12880         {
12881           intel_syntax = 0;
12882           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12883             intel_mnemonic = 0;
12884         }
12885       else if (CONST_STRNEQ (p, "addr"))
12886         {
12887           if (address_mode == mode_64bit)
12888             {
12889               if (p[4] == '3' && p[5] == '2')
12890                 priv.orig_sizeflag &= ~AFLAG;
12891               else if (p[4] == '6' && p[5] == '4')
12892                 priv.orig_sizeflag |= AFLAG;
12893             }
12894           else
12895             {
12896               if (p[4] == '1' && p[5] == '6')
12897                 priv.orig_sizeflag &= ~AFLAG;
12898               else if (p[4] == '3' && p[5] == '2')
12899                 priv.orig_sizeflag |= AFLAG;
12900             }
12901         }
12902       else if (CONST_STRNEQ (p, "data"))
12903         {
12904           if (p[4] == '1' && p[5] == '6')
12905             priv.orig_sizeflag &= ~DFLAG;
12906           else if (p[4] == '3' && p[5] == '2')
12907             priv.orig_sizeflag |= DFLAG;
12908         }
12909       else if (CONST_STRNEQ (p, "suffix"))
12910         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12911
12912       p = strchr (p, ',');
12913       if (p != NULL)
12914         p++;
12915     }
12916
12917   if (intel_syntax)
12918     {
12919       names64 = intel_names64;
12920       names32 = intel_names32;
12921       names16 = intel_names16;
12922       names8 = intel_names8;
12923       names8rex = intel_names8rex;
12924       names_seg = intel_names_seg;
12925       names_mm = intel_names_mm;
12926       names_bnd = intel_names_bnd;
12927       names_xmm = intel_names_xmm;
12928       names_ymm = intel_names_ymm;
12929       names_zmm = intel_names_zmm;
12930       index64 = intel_index64;
12931       index32 = intel_index32;
12932       names_mask = intel_names_mask;
12933       index16 = intel_index16;
12934       open_char = '[';
12935       close_char = ']';
12936       separator_char = '+';
12937       scale_char = '*';
12938     }
12939   else
12940     {
12941       names64 = att_names64;
12942       names32 = att_names32;
12943       names16 = att_names16;
12944       names8 = att_names8;
12945       names8rex = att_names8rex;
12946       names_seg = att_names_seg;
12947       names_mm = att_names_mm;
12948       names_bnd = att_names_bnd;
12949       names_xmm = att_names_xmm;
12950       names_ymm = att_names_ymm;
12951       names_zmm = att_names_zmm;
12952       index64 = att_index64;
12953       index32 = att_index32;
12954       names_mask = att_names_mask;
12955       index16 = att_index16;
12956       open_char = '(';
12957       close_char =  ')';
12958       separator_char = ',';
12959       scale_char = ',';
12960     }
12961
12962   /* The output looks better if we put 7 bytes on a line, since that
12963      puts most long word instructions on a single line.  Use 8 bytes
12964      for Intel L1OM.  */
12965   if ((info->mach & bfd_mach_l1om) != 0)
12966     info->bytes_per_line = 8;
12967   else
12968     info->bytes_per_line = 7;
12969
12970   info->private_data = &priv;
12971   priv.max_fetched = priv.the_buffer;
12972   priv.insn_start = pc;
12973
12974   obuf[0] = 0;
12975   for (i = 0; i < MAX_OPERANDS; ++i)
12976     {
12977       op_out[i][0] = 0;
12978       op_index[i] = -1;
12979     }
12980
12981   the_info = info;
12982   start_pc = pc;
12983   start_codep = priv.the_buffer;
12984   codep = priv.the_buffer;
12985
12986   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12987     {
12988       const char *name;
12989
12990       /* Getting here means we tried for data but didn't get it.  That
12991          means we have an incomplete instruction of some sort.  Just
12992          print the first byte as a prefix or a .byte pseudo-op.  */
12993       if (codep > priv.the_buffer)
12994         {
12995           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12996           if (name != NULL)
12997             (*info->fprintf_func) (info->stream, "%s", name);
12998           else
12999             {
13000               /* Just print the first byte as a .byte instruction.  */
13001               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13002                                      (unsigned int) priv.the_buffer[0]);
13003             }
13004
13005           return 1;
13006         }
13007
13008       return -1;
13009     }
13010
13011   obufp = obuf;
13012   sizeflag = priv.orig_sizeflag;
13013
13014   if (!ckprefix () || rex_used)
13015     {
13016       /* Too many prefixes or unused REX prefixes.  */
13017       for (i = 0;
13018            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13019            i++)
13020         (*info->fprintf_func) (info->stream, "%s%s",
13021                                i == 0 ? "" : " ",
13022                                prefix_name (all_prefixes[i], sizeflag));
13023       return i;
13024     }
13025
13026   insn_codep = codep;
13027
13028   FETCH_DATA (info, codep + 1);
13029   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13030
13031   if (((prefixes & PREFIX_FWAIT)
13032        && ((*codep < 0xd8) || (*codep > 0xdf))))
13033     {
13034       /* Handle prefixes before fwait.  */
13035       for (i = 0; i < fwait_prefix && all_prefixes[i];
13036            i++)
13037         (*info->fprintf_func) (info->stream, "%s ",
13038                                prefix_name (all_prefixes[i], sizeflag));
13039       (*info->fprintf_func) (info->stream, "fwait");
13040       return i + 1;
13041     }
13042
13043   if (*codep == 0x0f)
13044     {
13045       unsigned char threebyte;
13046       FETCH_DATA (info, codep + 2);
13047       threebyte = *++codep;
13048       dp = &dis386_twobyte[threebyte];
13049       need_modrm = twobyte_has_modrm[*codep];
13050       codep++;
13051     }
13052   else
13053     {
13054       dp = &dis386[*codep];
13055       need_modrm = onebyte_has_modrm[*codep];
13056       codep++;
13057     }
13058
13059   /* Save sizeflag for printing the extra prefixes later before updating
13060      it for mnemonic and operand processing.  The prefix names depend
13061      only on the address mode.  */
13062   orig_sizeflag = sizeflag;
13063   if (prefixes & PREFIX_ADDR)
13064     sizeflag ^= AFLAG;
13065   if ((prefixes & PREFIX_DATA))
13066     sizeflag ^= DFLAG;
13067
13068   end_codep = codep;
13069   if (need_modrm)
13070     {
13071       FETCH_DATA (info, codep + 1);
13072       modrm.mod = (*codep >> 6) & 3;
13073       modrm.reg = (*codep >> 3) & 7;
13074       modrm.rm = *codep & 7;
13075     }
13076
13077   need_vex = 0;
13078   need_vex_reg = 0;
13079   vex_w_done = 0;
13080   vex.evex = 0;
13081
13082   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13083     {
13084       get_sib (info, sizeflag);
13085       dofloat (sizeflag);
13086     }
13087   else
13088     {
13089       dp = get_valid_dis386 (dp, info);
13090       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13091         {
13092           get_sib (info, sizeflag);
13093           for (i = 0; i < MAX_OPERANDS; ++i)
13094             {
13095               obufp = op_out[i];
13096               op_ad = MAX_OPERANDS - 1 - i;
13097               if (dp->op[i].rtn)
13098                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13099               /* For EVEX instruction after the last operand masking
13100                  should be printed.  */
13101               if (i == 0 && vex.evex)
13102                 {
13103                   /* Don't print {%k0}.  */
13104                   if (vex.mask_register_specifier)
13105                     {
13106                       oappend ("{");
13107                       oappend (names_mask[vex.mask_register_specifier]);
13108                       oappend ("}");
13109                     }
13110                   if (vex.zeroing)
13111                     oappend ("{z}");
13112                 }
13113             }
13114         }
13115     }
13116
13117   /* Check if the REX prefix is used.  */
13118   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13119     all_prefixes[last_rex_prefix] = 0;
13120
13121   /* Check if the SEG prefix is used.  */
13122   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13123                    | PREFIX_FS | PREFIX_GS)) != 0
13124       && (used_prefixes & active_seg_prefix) != 0)
13125     all_prefixes[last_seg_prefix] = 0;
13126
13127   /* Check if the ADDR prefix is used.  */
13128   if ((prefixes & PREFIX_ADDR) != 0
13129       && (used_prefixes & PREFIX_ADDR) != 0)
13130     all_prefixes[last_addr_prefix] = 0;
13131
13132   /* Check if the DATA prefix is used.  */
13133   if ((prefixes & PREFIX_DATA) != 0
13134       && (used_prefixes & PREFIX_DATA) != 0)
13135     all_prefixes[last_data_prefix] = 0;
13136
13137   /* Print the extra prefixes.  */
13138   prefix_length = 0;
13139   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13140     if (all_prefixes[i])
13141       {
13142         const char *name;
13143         name = prefix_name (all_prefixes[i], orig_sizeflag);
13144         if (name == NULL)
13145           abort ();
13146         prefix_length += strlen (name) + 1;
13147         (*info->fprintf_func) (info->stream, "%s ", name);
13148       }
13149
13150   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13151      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13152      used by putop and MMX/SSE operand and may be overriden by the
13153      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13154      separately.  */
13155   if (dp->prefix_requirement == PREFIX_OPCODE
13156       && dp != &bad_opcode
13157       && (((prefixes
13158             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13159            && (used_prefixes
13160                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13161           || ((((prefixes
13162                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13163                 == PREFIX_DATA)
13164                && (used_prefixes & PREFIX_DATA) == 0))))
13165     {
13166       (*info->fprintf_func) (info->stream, "(bad)");
13167       return end_codep - priv.the_buffer;
13168     }
13169
13170   /* Check maximum code length.  */
13171   if ((codep - start_codep) > MAX_CODE_LENGTH)
13172     {
13173       (*info->fprintf_func) (info->stream, "(bad)");
13174       return MAX_CODE_LENGTH;
13175     }
13176
13177   obufp = mnemonicendp;
13178   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13179     oappend (" ");
13180   oappend (" ");
13181   (*info->fprintf_func) (info->stream, "%s", obuf);
13182
13183   /* The enter and bound instructions are printed with operands in the same
13184      order as the intel book; everything else is printed in reverse order.  */
13185   if (intel_syntax || two_source_ops)
13186     {
13187       bfd_vma riprel;
13188
13189       for (i = 0; i < MAX_OPERANDS; ++i)
13190         op_txt[i] = op_out[i];
13191
13192       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13193         {
13194           op_ad = op_index[i];
13195           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13196           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13197           riprel = op_riprel[i];
13198           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13199           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13200         }
13201     }
13202   else
13203     {
13204       for (i = 0; i < MAX_OPERANDS; ++i)
13205         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13206     }
13207
13208   needcomma = 0;
13209   for (i = 0; i < MAX_OPERANDS; ++i)
13210     if (*op_txt[i])
13211       {
13212         if (needcomma)
13213           (*info->fprintf_func) (info->stream, ",");
13214         if (op_index[i] != -1 && !op_riprel[i])
13215           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13216         else
13217           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13218         needcomma = 1;
13219       }
13220
13221   for (i = 0; i < MAX_OPERANDS; i++)
13222     if (op_index[i] != -1 && op_riprel[i])
13223       {
13224         (*info->fprintf_func) (info->stream, "        # ");
13225         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13226                                                 + op_address[op_index[i]]), info);
13227         break;
13228       }
13229   return codep - priv.the_buffer;
13230 }
13231
13232 static const char *float_mem[] = {
13233   /* d8 */
13234   "fadd{s|}",
13235   "fmul{s|}",
13236   "fcom{s|}",
13237   "fcomp{s|}",
13238   "fsub{s|}",
13239   "fsubr{s|}",
13240   "fdiv{s|}",
13241   "fdivr{s|}",
13242   /* d9 */
13243   "fld{s|}",
13244   "(bad)",
13245   "fst{s|}",
13246   "fstp{s|}",
13247   "fldenvIC",
13248   "fldcw",
13249   "fNstenvIC",
13250   "fNstcw",
13251   /* da */
13252   "fiadd{l|}",
13253   "fimul{l|}",
13254   "ficom{l|}",
13255   "ficomp{l|}",
13256   "fisub{l|}",
13257   "fisubr{l|}",
13258   "fidiv{l|}",
13259   "fidivr{l|}",
13260   /* db */
13261   "fild{l|}",
13262   "fisttp{l|}",
13263   "fist{l|}",
13264   "fistp{l|}",
13265   "(bad)",
13266   "fld{t||t|}",
13267   "(bad)",
13268   "fstp{t||t|}",
13269   /* dc */
13270   "fadd{l|}",
13271   "fmul{l|}",
13272   "fcom{l|}",
13273   "fcomp{l|}",
13274   "fsub{l|}",
13275   "fsubr{l|}",
13276   "fdiv{l|}",
13277   "fdivr{l|}",
13278   /* dd */
13279   "fld{l|}",
13280   "fisttp{ll|}",
13281   "fst{l||}",
13282   "fstp{l|}",
13283   "frstorIC",
13284   "(bad)",
13285   "fNsaveIC",
13286   "fNstsw",
13287   /* de */
13288   "fiadd",
13289   "fimul",
13290   "ficom",
13291   "ficomp",
13292   "fisub",
13293   "fisubr",
13294   "fidiv",
13295   "fidivr",
13296   /* df */
13297   "fild",
13298   "fisttp",
13299   "fist",
13300   "fistp",
13301   "fbld",
13302   "fild{ll|}",
13303   "fbstp",
13304   "fistp{ll|}",
13305 };
13306
13307 static const unsigned char float_mem_mode[] = {
13308   /* d8 */
13309   d_mode,
13310   d_mode,
13311   d_mode,
13312   d_mode,
13313   d_mode,
13314   d_mode,
13315   d_mode,
13316   d_mode,
13317   /* d9 */
13318   d_mode,
13319   0,
13320   d_mode,
13321   d_mode,
13322   0,
13323   w_mode,
13324   0,
13325   w_mode,
13326   /* da */
13327   d_mode,
13328   d_mode,
13329   d_mode,
13330   d_mode,
13331   d_mode,
13332   d_mode,
13333   d_mode,
13334   d_mode,
13335   /* db */
13336   d_mode,
13337   d_mode,
13338   d_mode,
13339   d_mode,
13340   0,
13341   t_mode,
13342   0,
13343   t_mode,
13344   /* dc */
13345   q_mode,
13346   q_mode,
13347   q_mode,
13348   q_mode,
13349   q_mode,
13350   q_mode,
13351   q_mode,
13352   q_mode,
13353   /* dd */
13354   q_mode,
13355   q_mode,
13356   q_mode,
13357   q_mode,
13358   0,
13359   0,
13360   0,
13361   w_mode,
13362   /* de */
13363   w_mode,
13364   w_mode,
13365   w_mode,
13366   w_mode,
13367   w_mode,
13368   w_mode,
13369   w_mode,
13370   w_mode,
13371   /* df */
13372   w_mode,
13373   w_mode,
13374   w_mode,
13375   w_mode,
13376   t_mode,
13377   q_mode,
13378   t_mode,
13379   q_mode
13380 };
13381
13382 #define ST { OP_ST, 0 }
13383 #define STi { OP_STi, 0 }
13384
13385 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13386 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13387 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13388 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13389 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13390 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13391 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13392 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13393 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13394
13395 static const struct dis386 float_reg[][8] = {
13396   /* d8 */
13397   {
13398     { "fadd",   { ST, STi }, 0 },
13399     { "fmul",   { ST, STi }, 0 },
13400     { "fcom",   { STi }, 0 },
13401     { "fcomp",  { STi }, 0 },
13402     { "fsub",   { ST, STi }, 0 },
13403     { "fsubr",  { ST, STi }, 0 },
13404     { "fdiv",   { ST, STi }, 0 },
13405     { "fdivr",  { ST, STi }, 0 },
13406   },
13407   /* d9 */
13408   {
13409     { "fld",    { STi }, 0 },
13410     { "fxch",   { STi }, 0 },
13411     { FGRPd9_2 },
13412     { Bad_Opcode },
13413     { FGRPd9_4 },
13414     { FGRPd9_5 },
13415     { FGRPd9_6 },
13416     { FGRPd9_7 },
13417   },
13418   /* da */
13419   {
13420     { "fcmovb", { ST, STi }, 0 },
13421     { "fcmove", { ST, STi }, 0 },
13422     { "fcmovbe",{ ST, STi }, 0 },
13423     { "fcmovu", { ST, STi }, 0 },
13424     { Bad_Opcode },
13425     { FGRPda_5 },
13426     { Bad_Opcode },
13427     { Bad_Opcode },
13428   },
13429   /* db */
13430   {
13431     { "fcmovnb",{ ST, STi }, 0 },
13432     { "fcmovne",{ ST, STi }, 0 },
13433     { "fcmovnbe",{ ST, STi }, 0 },
13434     { "fcmovnu",{ ST, STi }, 0 },
13435     { FGRPdb_4 },
13436     { "fucomi", { ST, STi }, 0 },
13437     { "fcomi",  { ST, STi }, 0 },
13438     { Bad_Opcode },
13439   },
13440   /* dc */
13441   {
13442     { "fadd",   { STi, ST }, 0 },
13443     { "fmul",   { STi, ST }, 0 },
13444     { Bad_Opcode },
13445     { Bad_Opcode },
13446     { "fsub!M", { STi, ST }, 0 },
13447     { "fsubM",  { STi, ST }, 0 },
13448     { "fdiv!M", { STi, ST }, 0 },
13449     { "fdivM",  { STi, ST }, 0 },
13450   },
13451   /* dd */
13452   {
13453     { "ffree",  { STi }, 0 },
13454     { Bad_Opcode },
13455     { "fst",    { STi }, 0 },
13456     { "fstp",   { STi }, 0 },
13457     { "fucom",  { STi }, 0 },
13458     { "fucomp", { STi }, 0 },
13459     { Bad_Opcode },
13460     { Bad_Opcode },
13461   },
13462   /* de */
13463   {
13464     { "faddp",  { STi, ST }, 0 },
13465     { "fmulp",  { STi, ST }, 0 },
13466     { Bad_Opcode },
13467     { FGRPde_3 },
13468     { "fsub!Mp", { STi, ST }, 0 },
13469     { "fsubMp", { STi, ST }, 0 },
13470     { "fdiv!Mp", { STi, ST }, 0 },
13471     { "fdivMp", { STi, ST }, 0 },
13472   },
13473   /* df */
13474   {
13475     { "ffreep", { STi }, 0 },
13476     { Bad_Opcode },
13477     { Bad_Opcode },
13478     { Bad_Opcode },
13479     { FGRPdf_4 },
13480     { "fucomip", { ST, STi }, 0 },
13481     { "fcomip", { ST, STi }, 0 },
13482     { Bad_Opcode },
13483   },
13484 };
13485
13486 static char *fgrps[][8] = {
13487   /* d9_2  0 */
13488   {
13489     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13490   },
13491
13492   /* d9_4  1 */
13493   {
13494     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13495   },
13496
13497   /* d9_5  2 */
13498   {
13499     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13500   },
13501
13502   /* d9_6  3 */
13503   {
13504     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13505   },
13506
13507   /* d9_7  4 */
13508   {
13509     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13510   },
13511
13512   /* da_5  5 */
13513   {
13514     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13515   },
13516
13517   /* db_4  6 */
13518   {
13519     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13520     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13521   },
13522
13523   /* de_3  7 */
13524   {
13525     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13526   },
13527
13528   /* df_4  8 */
13529   {
13530     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13531   },
13532 };
13533
13534 static void
13535 swap_operand (void)
13536 {
13537   mnemonicendp[0] = '.';
13538   mnemonicendp[1] = 's';
13539   mnemonicendp += 2;
13540 }
13541
13542 static void
13543 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13544                int sizeflag ATTRIBUTE_UNUSED)
13545 {
13546   /* Skip mod/rm byte.  */
13547   MODRM_CHECK;
13548   codep++;
13549 }
13550
13551 static void
13552 dofloat (int sizeflag)
13553 {
13554   const struct dis386 *dp;
13555   unsigned char floatop;
13556
13557   floatop = codep[-1];
13558
13559   if (modrm.mod != 3)
13560     {
13561       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13562
13563       putop (float_mem[fp_indx], sizeflag);
13564       obufp = op_out[0];
13565       op_ad = 2;
13566       OP_E (float_mem_mode[fp_indx], sizeflag);
13567       return;
13568     }
13569   /* Skip mod/rm byte.  */
13570   MODRM_CHECK;
13571   codep++;
13572
13573   dp = &float_reg[floatop - 0xd8][modrm.reg];
13574   if (dp->name == NULL)
13575     {
13576       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13577
13578       /* Instruction fnstsw is only one with strange arg.  */
13579       if (floatop == 0xdf && codep[-1] == 0xe0)
13580         strcpy (op_out[0], names16[0]);
13581     }
13582   else
13583     {
13584       putop (dp->name, sizeflag);
13585
13586       obufp = op_out[0];
13587       op_ad = 2;
13588       if (dp->op[0].rtn)
13589         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13590
13591       obufp = op_out[1];
13592       op_ad = 1;
13593       if (dp->op[1].rtn)
13594         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13595     }
13596 }
13597
13598 /* Like oappend (below), but S is a string starting with '%'.
13599    In Intel syntax, the '%' is elided.  */
13600 static void
13601 oappend_maybe_intel (const char *s)
13602 {
13603   oappend (s + intel_syntax);
13604 }
13605
13606 static void
13607 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13608 {
13609   oappend_maybe_intel ("%st");
13610 }
13611
13612 static void
13613 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13614 {
13615   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13616   oappend_maybe_intel (scratchbuf);
13617 }
13618
13619 /* Capital letters in template are macros.  */
13620 static int
13621 putop (const char *in_template, int sizeflag)
13622 {
13623   const char *p;
13624   int alt = 0;
13625   int cond = 1;
13626   unsigned int l = 0, len = 1;
13627   char last[4];
13628
13629 #define SAVE_LAST(c)                    \
13630   if (l < len && l < sizeof (last))     \
13631     last[l++] = c;                      \
13632   else                                  \
13633     abort ();
13634
13635   for (p = in_template; *p; p++)
13636     {
13637       switch (*p)
13638         {
13639         default:
13640           *obufp++ = *p;
13641           break;
13642         case '%':
13643           len++;
13644           break;
13645         case '!':
13646           cond = 0;
13647           break;
13648         case '{':
13649           alt = 0;
13650           if (intel_syntax)
13651             {
13652               while (*++p != '|')
13653                 if (*p == '}' || *p == '\0')
13654                   abort ();
13655             }
13656           /* Fall through.  */
13657         case 'I':
13658           alt = 1;
13659           continue;
13660         case '|':
13661           while (*++p != '}')
13662             {
13663               if (*p == '\0')
13664                 abort ();
13665             }
13666           break;
13667         case '}':
13668           break;
13669         case 'A':
13670           if (intel_syntax)
13671             break;
13672           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13673             *obufp++ = 'b';
13674           break;
13675         case 'B':
13676           if (l == 0 && len == 1)
13677             {
13678 case_B:
13679               if (intel_syntax)
13680                 break;
13681               if (sizeflag & SUFFIX_ALWAYS)
13682                 *obufp++ = 'b';
13683             }
13684           else
13685             {
13686               if (l != 1
13687                   || len != 2
13688                   || last[0] != 'L')
13689                 {
13690                   SAVE_LAST (*p);
13691                   break;
13692                 }
13693
13694               if (address_mode == mode_64bit
13695                   && !(prefixes & PREFIX_ADDR))
13696                 {
13697                   *obufp++ = 'a';
13698                   *obufp++ = 'b';
13699                   *obufp++ = 's';
13700                 }
13701
13702               goto case_B;
13703             }
13704           break;
13705         case 'C':
13706           if (intel_syntax && !alt)
13707             break;
13708           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13709             {
13710               if (sizeflag & DFLAG)
13711                 *obufp++ = intel_syntax ? 'd' : 'l';
13712               else
13713                 *obufp++ = intel_syntax ? 'w' : 's';
13714               used_prefixes |= (prefixes & PREFIX_DATA);
13715             }
13716           break;
13717         case 'D':
13718           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13719             break;
13720           USED_REX (REX_W);
13721           if (modrm.mod == 3)
13722             {
13723               if (rex & REX_W)
13724                 *obufp++ = 'q';
13725               else
13726                 {
13727                   if (sizeflag & DFLAG)
13728                     *obufp++ = intel_syntax ? 'd' : 'l';
13729                   else
13730                     *obufp++ = 'w';
13731                   used_prefixes |= (prefixes & PREFIX_DATA);
13732                 }
13733             }
13734           else
13735             *obufp++ = 'w';
13736           break;
13737         case 'E':               /* For jcxz/jecxz */
13738           if (address_mode == mode_64bit)
13739             {
13740               if (sizeflag & AFLAG)
13741                 *obufp++ = 'r';
13742               else
13743                 *obufp++ = 'e';
13744             }
13745           else
13746             if (sizeflag & AFLAG)
13747               *obufp++ = 'e';
13748           used_prefixes |= (prefixes & PREFIX_ADDR);
13749           break;
13750         case 'F':
13751           if (intel_syntax)
13752             break;
13753           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13754             {
13755               if (sizeflag & AFLAG)
13756                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13757               else
13758                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13759               used_prefixes |= (prefixes & PREFIX_ADDR);
13760             }
13761           break;
13762         case 'G':
13763           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13764             break;
13765           if ((rex & REX_W) || (sizeflag & DFLAG))
13766             *obufp++ = 'l';
13767           else
13768             *obufp++ = 'w';
13769           if (!(rex & REX_W))
13770             used_prefixes |= (prefixes & PREFIX_DATA);
13771           break;
13772         case 'H':
13773           if (intel_syntax)
13774             break;
13775           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13776               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13777             {
13778               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13779               *obufp++ = ',';
13780               *obufp++ = 'p';
13781               if (prefixes & PREFIX_DS)
13782                 *obufp++ = 't';
13783               else
13784                 *obufp++ = 'n';
13785             }
13786           break;
13787         case 'J':
13788           if (intel_syntax)
13789             break;
13790           *obufp++ = 'l';
13791           break;
13792         case 'K':
13793           USED_REX (REX_W);
13794           if (rex & REX_W)
13795             *obufp++ = 'q';
13796           else
13797             *obufp++ = 'd';
13798           break;
13799         case 'Z':
13800           if (l != 0 || len != 1)
13801             {
13802               if (l != 1 || len != 2 || last[0] != 'X')
13803                 {
13804                   SAVE_LAST (*p);
13805                   break;
13806                 }
13807               if (!need_vex || !vex.evex)
13808                 abort ();
13809               if (intel_syntax
13810                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13811                 break;
13812               switch (vex.length)
13813                 {
13814                 case 128:
13815                   *obufp++ = 'x';
13816                   break;
13817                 case 256:
13818                   *obufp++ = 'y';
13819                   break;
13820                 case 512:
13821                   *obufp++ = 'z';
13822                   break;
13823                 default:
13824                   abort ();
13825                 }
13826               break;
13827             }
13828           if (intel_syntax)
13829             break;
13830           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13831             {
13832               *obufp++ = 'q';
13833               break;
13834             }
13835           /* Fall through.  */
13836           goto case_L;
13837         case 'L':
13838           if (l != 0 || len != 1)
13839             {
13840               SAVE_LAST (*p);
13841               break;
13842             }
13843 case_L:
13844           if (intel_syntax)
13845             break;
13846           if (sizeflag & SUFFIX_ALWAYS)
13847             *obufp++ = 'l';
13848           break;
13849         case 'M':
13850           if (intel_mnemonic != cond)
13851             *obufp++ = 'r';
13852           break;
13853         case 'N':
13854           if ((prefixes & PREFIX_FWAIT) == 0)
13855             *obufp++ = 'n';
13856           else
13857             used_prefixes |= PREFIX_FWAIT;
13858           break;
13859         case 'O':
13860           USED_REX (REX_W);
13861           if (rex & REX_W)
13862             *obufp++ = 'o';
13863           else if (intel_syntax && (sizeflag & DFLAG))
13864             *obufp++ = 'q';
13865           else
13866             *obufp++ = 'd';
13867           if (!(rex & REX_W))
13868             used_prefixes |= (prefixes & PREFIX_DATA);
13869           break;
13870         case 'T':
13871           if (!intel_syntax
13872               && address_mode == mode_64bit
13873               && ((sizeflag & DFLAG) || (rex & REX_W)))
13874             {
13875               *obufp++ = 'q';
13876               break;
13877             }
13878           /* Fall through.  */
13879           goto case_P;
13880         case 'P':
13881           if (l == 0 && len == 1)
13882             {
13883 case_P:
13884               if (intel_syntax)
13885                 {
13886                   if ((rex & REX_W) == 0
13887                       && (prefixes & PREFIX_DATA))
13888                     {
13889                       if ((sizeflag & DFLAG) == 0)
13890                         *obufp++ = 'w';
13891                       used_prefixes |= (prefixes & PREFIX_DATA);
13892                     }
13893                   break;
13894                 }
13895               if ((prefixes & PREFIX_DATA)
13896                   || (rex & REX_W)
13897                   || (sizeflag & SUFFIX_ALWAYS))
13898                 {
13899                   USED_REX (REX_W);
13900                   if (rex & REX_W)
13901                     *obufp++ = 'q';
13902                   else
13903                     {
13904                       if (sizeflag & DFLAG)
13905                         *obufp++ = 'l';
13906                       else
13907                         *obufp++ = 'w';
13908                       used_prefixes |= (prefixes & PREFIX_DATA);
13909                     }
13910                 }
13911             }
13912           else
13913             {
13914               if (l != 1 || len != 2 || last[0] != 'L')
13915                 {
13916                   SAVE_LAST (*p);
13917                   break;
13918                 }
13919
13920               if ((prefixes & PREFIX_DATA)
13921                   || (rex & REX_W)
13922                   || (sizeflag & SUFFIX_ALWAYS))
13923                 {
13924                   USED_REX (REX_W);
13925                   if (rex & REX_W)
13926                     *obufp++ = 'q';
13927                   else
13928                     {
13929                       if (sizeflag & DFLAG)
13930                         *obufp++ = intel_syntax ? 'd' : 'l';
13931                       else
13932                         *obufp++ = 'w';
13933                       used_prefixes |= (prefixes & PREFIX_DATA);
13934                     }
13935                 }
13936             }
13937           break;
13938         case 'U':
13939           if (intel_syntax)
13940             break;
13941           if (address_mode == mode_64bit
13942               && ((sizeflag & DFLAG) || (rex & REX_W)))
13943             {
13944               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13945                 *obufp++ = 'q';
13946               break;
13947             }
13948           /* Fall through.  */
13949           goto case_Q;
13950         case 'Q':
13951           if (l == 0 && len == 1)
13952             {
13953 case_Q:
13954               if (intel_syntax && !alt)
13955                 break;
13956               USED_REX (REX_W);
13957               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13958                 {
13959                   if (rex & REX_W)
13960                     *obufp++ = 'q';
13961                   else
13962                     {
13963                       if (sizeflag & DFLAG)
13964                         *obufp++ = intel_syntax ? 'd' : 'l';
13965                       else
13966                         *obufp++ = 'w';
13967                       used_prefixes |= (prefixes & PREFIX_DATA);
13968                     }
13969                 }
13970             }
13971           else
13972             {
13973               if (l != 1 || len != 2 || last[0] != 'L')
13974                 {
13975                   SAVE_LAST (*p);
13976                   break;
13977                 }
13978               if (intel_syntax
13979                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13980                 break;
13981               if ((rex & REX_W))
13982                 {
13983                   USED_REX (REX_W);
13984                   *obufp++ = 'q';
13985                 }
13986               else
13987                 *obufp++ = 'l';
13988             }
13989           break;
13990         case 'R':
13991           USED_REX (REX_W);
13992           if (rex & REX_W)
13993             *obufp++ = 'q';
13994           else if (sizeflag & DFLAG)
13995             {
13996               if (intel_syntax)
13997                   *obufp++ = 'd';
13998               else
13999                   *obufp++ = 'l';
14000             }
14001           else
14002             *obufp++ = 'w';
14003           if (intel_syntax && !p[1]
14004               && ((rex & REX_W) || (sizeflag & DFLAG)))
14005             *obufp++ = 'e';
14006           if (!(rex & REX_W))
14007             used_prefixes |= (prefixes & PREFIX_DATA);
14008           break;
14009         case 'V':
14010           if (l == 0 && len == 1)
14011             {
14012               if (intel_syntax)
14013                 break;
14014               if (address_mode == mode_64bit
14015                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14016                 {
14017                   if (sizeflag & SUFFIX_ALWAYS)
14018                     *obufp++ = 'q';
14019                   break;
14020                 }
14021             }
14022           else
14023             {
14024               if (l != 1
14025                   || len != 2
14026                   || last[0] != 'L')
14027                 {
14028                   SAVE_LAST (*p);
14029                   break;
14030                 }
14031
14032               if (rex & REX_W)
14033                 {
14034                   *obufp++ = 'a';
14035                   *obufp++ = 'b';
14036                   *obufp++ = 's';
14037                 }
14038             }
14039           /* Fall through.  */
14040           goto case_S;
14041         case 'S':
14042           if (l == 0 && len == 1)
14043             {
14044 case_S:
14045               if (intel_syntax)
14046                 break;
14047               if (sizeflag & SUFFIX_ALWAYS)
14048                 {
14049                   if (rex & REX_W)
14050                     *obufp++ = 'q';
14051                   else
14052                     {
14053                       if (sizeflag & DFLAG)
14054                         *obufp++ = 'l';
14055                       else
14056                         *obufp++ = 'w';
14057                       used_prefixes |= (prefixes & PREFIX_DATA);
14058                     }
14059                 }
14060             }
14061           else
14062             {
14063               if (l != 1
14064                   || len != 2
14065                   || last[0] != 'L')
14066                 {
14067                   SAVE_LAST (*p);
14068                   break;
14069                 }
14070
14071               if (address_mode == mode_64bit
14072                   && !(prefixes & PREFIX_ADDR))
14073                 {
14074                   *obufp++ = 'a';
14075                   *obufp++ = 'b';
14076                   *obufp++ = 's';
14077                 }
14078
14079               goto case_S;
14080             }
14081           break;
14082         case 'X':
14083           if (l != 0 || len != 1)
14084             {
14085               SAVE_LAST (*p);
14086               break;
14087             }
14088           if (need_vex && vex.prefix)
14089             {
14090               if (vex.prefix == DATA_PREFIX_OPCODE)
14091                 *obufp++ = 'd';
14092               else
14093                 *obufp++ = 's';
14094             }
14095           else
14096             {
14097               if (prefixes & PREFIX_DATA)
14098                 *obufp++ = 'd';
14099               else
14100                 *obufp++ = 's';
14101               used_prefixes |= (prefixes & PREFIX_DATA);
14102             }
14103           break;
14104         case 'Y':
14105           if (l == 0 && len == 1)
14106             {
14107               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14108                 break;
14109               if (rex & REX_W)
14110                 {
14111                   USED_REX (REX_W);
14112                   *obufp++ = 'q';
14113                 }
14114               break;
14115             }
14116           else
14117             {
14118               if (l != 1 || len != 2 || last[0] != 'X')
14119                 {
14120                   SAVE_LAST (*p);
14121                   break;
14122                 }
14123               if (!need_vex)
14124                 abort ();
14125               if (intel_syntax
14126                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14127                 break;
14128               switch (vex.length)
14129                 {
14130                 case 128:
14131                   *obufp++ = 'x';
14132                   break;
14133                 case 256:
14134                   *obufp++ = 'y';
14135                   break;
14136                 case 512:
14137                   if (!vex.evex)
14138                 default:
14139                     abort ();
14140                 }
14141             }
14142           break;
14143         case 'W':
14144           if (l == 0 && len == 1)
14145             {
14146               /* operand size flag for cwtl, cbtw */
14147               USED_REX (REX_W);
14148               if (rex & REX_W)
14149                 {
14150                   if (intel_syntax)
14151                     *obufp++ = 'd';
14152                   else
14153                     *obufp++ = 'l';
14154                 }
14155               else if (sizeflag & DFLAG)
14156                 *obufp++ = 'w';
14157               else
14158                 *obufp++ = 'b';
14159               if (!(rex & REX_W))
14160                 used_prefixes |= (prefixes & PREFIX_DATA);
14161             }
14162           else
14163             {
14164               if (l != 1
14165                   || len != 2
14166                   || (last[0] != 'X'
14167                       && last[0] != 'L'))
14168                 {
14169                   SAVE_LAST (*p);
14170                   break;
14171                 }
14172               if (!need_vex)
14173                 abort ();
14174               if (last[0] == 'X')
14175                 *obufp++ = vex.w ? 'd': 's';
14176               else
14177                 *obufp++ = vex.w ? 'q': 'd';
14178             }
14179           break;
14180         }
14181       alt = 0;
14182     }
14183   *obufp = 0;
14184   mnemonicendp = obufp;
14185   return 0;
14186 }
14187
14188 static void
14189 oappend (const char *s)
14190 {
14191   obufp = stpcpy (obufp, s);
14192 }
14193
14194 static void
14195 append_seg (void)
14196 {
14197   /* Only print the active segment register.  */
14198   if (!active_seg_prefix)
14199     return;
14200
14201   used_prefixes |= active_seg_prefix;
14202   switch (active_seg_prefix)
14203     {
14204     case PREFIX_CS:
14205       oappend_maybe_intel ("%cs:");
14206       break;
14207     case PREFIX_DS:
14208       oappend_maybe_intel ("%ds:");
14209       break;
14210     case PREFIX_SS:
14211       oappend_maybe_intel ("%ss:");
14212       break;
14213     case PREFIX_ES:
14214       oappend_maybe_intel ("%es:");
14215       break;
14216     case PREFIX_FS:
14217       oappend_maybe_intel ("%fs:");
14218       break;
14219     case PREFIX_GS:
14220       oappend_maybe_intel ("%gs:");
14221       break;
14222     default:
14223       break;
14224     }
14225 }
14226
14227 static void
14228 OP_indirE (int bytemode, int sizeflag)
14229 {
14230   if (!intel_syntax)
14231     oappend ("*");
14232   OP_E (bytemode, sizeflag);
14233 }
14234
14235 static void
14236 print_operand_value (char *buf, int hex, bfd_vma disp)
14237 {
14238   if (address_mode == mode_64bit)
14239     {
14240       if (hex)
14241         {
14242           char tmp[30];
14243           int i;
14244           buf[0] = '0';
14245           buf[1] = 'x';
14246           sprintf_vma (tmp, disp);
14247           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14248           strcpy (buf + 2, tmp + i);
14249         }
14250       else
14251         {
14252           bfd_signed_vma v = disp;
14253           char tmp[30];
14254           int i;
14255           if (v < 0)
14256             {
14257               *(buf++) = '-';
14258               v = -disp;
14259               /* Check for possible overflow on 0x8000000000000000.  */
14260               if (v < 0)
14261                 {
14262                   strcpy (buf, "9223372036854775808");
14263                   return;
14264                 }
14265             }
14266           if (!v)
14267             {
14268               strcpy (buf, "0");
14269               return;
14270             }
14271
14272           i = 0;
14273           tmp[29] = 0;
14274           while (v)
14275             {
14276               tmp[28 - i] = (v % 10) + '0';
14277               v /= 10;
14278               i++;
14279             }
14280           strcpy (buf, tmp + 29 - i);
14281         }
14282     }
14283   else
14284     {
14285       if (hex)
14286         sprintf (buf, "0x%x", (unsigned int) disp);
14287       else
14288         sprintf (buf, "%d", (int) disp);
14289     }
14290 }
14291
14292 /* Put DISP in BUF as signed hex number.  */
14293
14294 static void
14295 print_displacement (char *buf, bfd_vma disp)
14296 {
14297   bfd_signed_vma val = disp;
14298   char tmp[30];
14299   int i, j = 0;
14300
14301   if (val < 0)
14302     {
14303       buf[j++] = '-';
14304       val = -disp;
14305
14306       /* Check for possible overflow.  */
14307       if (val < 0)
14308         {
14309           switch (address_mode)
14310             {
14311             case mode_64bit:
14312               strcpy (buf + j, "0x8000000000000000");
14313               break;
14314             case mode_32bit:
14315               strcpy (buf + j, "0x80000000");
14316               break;
14317             case mode_16bit:
14318               strcpy (buf + j, "0x8000");
14319               break;
14320             }
14321           return;
14322         }
14323     }
14324
14325   buf[j++] = '0';
14326   buf[j++] = 'x';
14327
14328   sprintf_vma (tmp, (bfd_vma) val);
14329   for (i = 0; tmp[i] == '0'; i++)
14330     continue;
14331   if (tmp[i] == '\0')
14332     i--;
14333   strcpy (buf + j, tmp + i);
14334 }
14335
14336 static void
14337 intel_operand_size (int bytemode, int sizeflag)
14338 {
14339   if (vex.evex
14340       && vex.b
14341       && (bytemode == x_mode
14342           || bytemode == evex_half_bcst_xmmq_mode))
14343     {
14344       if (vex.w)
14345         oappend ("QWORD PTR ");
14346       else
14347         oappend ("DWORD PTR ");
14348       return;
14349     }
14350   switch (bytemode)
14351     {
14352     case b_mode:
14353     case b_swap_mode:
14354     case dqb_mode:
14355     case db_mode:
14356       oappend ("BYTE PTR ");
14357       break;
14358     case w_mode:
14359     case dw_mode:
14360     case dqw_mode:
14361     case dqw_swap_mode:
14362       oappend ("WORD PTR ");
14363       break;
14364     case stack_v_mode:
14365       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14366         {
14367           oappend ("QWORD PTR ");
14368           break;
14369         }
14370       /* FALLTHRU */
14371     case v_mode:
14372     case v_swap_mode:
14373     case dq_mode:
14374       USED_REX (REX_W);
14375       if (rex & REX_W)
14376         oappend ("QWORD PTR ");
14377       else
14378         {
14379           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14380             oappend ("DWORD PTR ");
14381           else
14382             oappend ("WORD PTR ");
14383           used_prefixes |= (prefixes & PREFIX_DATA);
14384         }
14385       break;
14386     case z_mode:
14387       if ((rex & REX_W) || (sizeflag & DFLAG))
14388         *obufp++ = 'D';
14389       oappend ("WORD PTR ");
14390       if (!(rex & REX_W))
14391         used_prefixes |= (prefixes & PREFIX_DATA);
14392       break;
14393     case a_mode:
14394       if (sizeflag & DFLAG)
14395         oappend ("QWORD PTR ");
14396       else
14397         oappend ("DWORD PTR ");
14398       used_prefixes |= (prefixes & PREFIX_DATA);
14399       break;
14400     case d_mode:
14401     case d_scalar_mode:
14402     case d_scalar_swap_mode:
14403     case d_swap_mode:
14404     case dqd_mode:
14405       oappend ("DWORD PTR ");
14406       break;
14407     case q_mode:
14408     case q_scalar_mode:
14409     case q_scalar_swap_mode:
14410     case q_swap_mode:
14411       oappend ("QWORD PTR ");
14412       break;
14413     case m_mode:
14414       if (address_mode == mode_64bit)
14415         oappend ("QWORD PTR ");
14416       else
14417         oappend ("DWORD PTR ");
14418       break;
14419     case f_mode:
14420       if (sizeflag & DFLAG)
14421         oappend ("FWORD PTR ");
14422       else
14423         oappend ("DWORD PTR ");
14424       used_prefixes |= (prefixes & PREFIX_DATA);
14425       break;
14426     case t_mode:
14427       oappend ("TBYTE PTR ");
14428       break;
14429     case x_mode:
14430     case x_swap_mode:
14431     case evex_x_gscat_mode:
14432     case evex_x_nobcst_mode:
14433       if (need_vex)
14434         {
14435           switch (vex.length)
14436             {
14437             case 128:
14438               oappend ("XMMWORD PTR ");
14439               break;
14440             case 256:
14441               oappend ("YMMWORD PTR ");
14442               break;
14443             case 512:
14444               oappend ("ZMMWORD PTR ");
14445               break;
14446             default:
14447               abort ();
14448             }
14449         }
14450       else
14451         oappend ("XMMWORD PTR ");
14452       break;
14453     case xmm_mode:
14454       oappend ("XMMWORD PTR ");
14455       break;
14456     case ymm_mode:
14457       oappend ("YMMWORD PTR ");
14458       break;
14459     case xmmq_mode:
14460     case evex_half_bcst_xmmq_mode:
14461       if (!need_vex)
14462         abort ();
14463
14464       switch (vex.length)
14465         {
14466         case 128:
14467           oappend ("QWORD PTR ");
14468           break;
14469         case 256:
14470           oappend ("XMMWORD PTR ");
14471           break;
14472         case 512:
14473           oappend ("YMMWORD PTR ");
14474           break;
14475         default:
14476           abort ();
14477         }
14478       break;
14479     case xmm_mb_mode:
14480       if (!need_vex)
14481         abort ();
14482
14483       switch (vex.length)
14484         {
14485         case 128:
14486         case 256:
14487         case 512:
14488           oappend ("BYTE PTR ");
14489           break;
14490         default:
14491           abort ();
14492         }
14493       break;
14494     case xmm_mw_mode:
14495       if (!need_vex)
14496         abort ();
14497
14498       switch (vex.length)
14499         {
14500         case 128:
14501         case 256:
14502         case 512:
14503           oappend ("WORD PTR ");
14504           break;
14505         default:
14506           abort ();
14507         }
14508       break;
14509     case xmm_md_mode:
14510       if (!need_vex)
14511         abort ();
14512
14513       switch (vex.length)
14514         {
14515         case 128:
14516         case 256:
14517         case 512:
14518           oappend ("DWORD PTR ");
14519           break;
14520         default:
14521           abort ();
14522         }
14523       break;
14524     case xmm_mq_mode:
14525       if (!need_vex)
14526         abort ();
14527
14528       switch (vex.length)
14529         {
14530         case 128:
14531         case 256:
14532         case 512:
14533           oappend ("QWORD PTR ");
14534           break;
14535         default:
14536           abort ();
14537         }
14538       break;
14539     case xmmdw_mode:
14540       if (!need_vex)
14541         abort ();
14542
14543       switch (vex.length)
14544         {
14545         case 128:
14546           oappend ("WORD PTR ");
14547           break;
14548         case 256:
14549           oappend ("DWORD PTR ");
14550           break;
14551         case 512:
14552           oappend ("QWORD PTR ");
14553           break;
14554         default:
14555           abort ();
14556         }
14557       break;
14558     case xmmqd_mode:
14559       if (!need_vex)
14560         abort ();
14561
14562       switch (vex.length)
14563         {
14564         case 128:
14565           oappend ("DWORD PTR ");
14566           break;
14567         case 256:
14568           oappend ("QWORD PTR ");
14569           break;
14570         case 512:
14571           oappend ("XMMWORD PTR ");
14572           break;
14573         default:
14574           abort ();
14575         }
14576       break;
14577     case ymmq_mode:
14578       if (!need_vex)
14579         abort ();
14580
14581       switch (vex.length)
14582         {
14583         case 128:
14584           oappend ("QWORD PTR ");
14585           break;
14586         case 256:
14587           oappend ("YMMWORD PTR ");
14588           break;
14589         case 512:
14590           oappend ("ZMMWORD PTR ");
14591           break;
14592         default:
14593           abort ();
14594         }
14595       break;
14596     case ymmxmm_mode:
14597       if (!need_vex)
14598         abort ();
14599
14600       switch (vex.length)
14601         {
14602         case 128:
14603         case 256:
14604           oappend ("XMMWORD PTR ");
14605           break;
14606         default:
14607           abort ();
14608         }
14609       break;
14610     case o_mode:
14611       oappend ("OWORD PTR ");
14612       break;
14613     case xmm_mdq_mode:
14614     case vex_w_dq_mode:
14615     case vex_scalar_w_dq_mode:
14616       if (!need_vex)
14617         abort ();
14618
14619       if (vex.w)
14620         oappend ("QWORD PTR ");
14621       else
14622         oappend ("DWORD PTR ");
14623       break;
14624     case vex_vsib_d_w_dq_mode:
14625     case vex_vsib_q_w_dq_mode:
14626       if (!need_vex)
14627         abort ();
14628
14629       if (!vex.evex)
14630         {
14631           if (vex.w)
14632             oappend ("QWORD PTR ");
14633           else
14634             oappend ("DWORD PTR ");
14635         }
14636       else
14637         {
14638           switch (vex.length)
14639             {
14640             case 128:
14641               oappend ("XMMWORD PTR ");
14642               break;
14643             case 256:
14644               oappend ("YMMWORD PTR ");
14645               break;
14646             case 512:
14647               oappend ("ZMMWORD PTR ");
14648               break;
14649             default:
14650               abort ();
14651             }
14652         }
14653       break;
14654     case vex_vsib_q_w_d_mode:
14655     case vex_vsib_d_w_d_mode:
14656       if (!need_vex || !vex.evex)
14657         abort ();
14658
14659       switch (vex.length)
14660         {
14661         case 128:
14662           oappend ("QWORD PTR ");
14663           break;
14664         case 256:
14665           oappend ("XMMWORD PTR ");
14666           break;
14667         case 512:
14668           oappend ("YMMWORD PTR ");
14669           break;
14670         default:
14671           abort ();
14672         }
14673
14674       break;
14675     case mask_bd_mode:
14676       if (!need_vex || vex.length != 128)
14677         abort ();
14678       if (vex.w)
14679         oappend ("DWORD PTR ");
14680       else
14681         oappend ("BYTE PTR ");
14682       break;
14683     case mask_mode:
14684       if (!need_vex)
14685         abort ();
14686       if (vex.w)
14687         oappend ("QWORD PTR ");
14688       else
14689         oappend ("WORD PTR ");
14690       break;
14691     case v_bnd_mode:
14692     default:
14693       break;
14694     }
14695 }
14696
14697 static void
14698 OP_E_register (int bytemode, int sizeflag)
14699 {
14700   int reg = modrm.rm;
14701   const char **names;
14702
14703   USED_REX (REX_B);
14704   if ((rex & REX_B))
14705     reg += 8;
14706
14707   if ((sizeflag & SUFFIX_ALWAYS)
14708       && (bytemode == b_swap_mode
14709           || bytemode == v_swap_mode
14710           || bytemode == dqw_swap_mode))
14711     swap_operand ();
14712
14713   switch (bytemode)
14714     {
14715     case b_mode:
14716     case b_swap_mode:
14717       USED_REX (0);
14718       if (rex)
14719         names = names8rex;
14720       else
14721         names = names8;
14722       break;
14723     case w_mode:
14724       names = names16;
14725       break;
14726     case d_mode:
14727     case dw_mode:
14728     case db_mode:
14729       names = names32;
14730       break;
14731     case q_mode:
14732       names = names64;
14733       break;
14734     case m_mode:
14735     case v_bnd_mode:
14736       names = address_mode == mode_64bit ? names64 : names32;
14737       break;
14738     case bnd_mode:
14739       names = names_bnd;
14740       break;
14741     case stack_v_mode:
14742       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14743         {
14744           names = names64;
14745           break;
14746         }
14747       bytemode = v_mode;
14748       /* FALLTHRU */
14749     case v_mode:
14750     case v_swap_mode:
14751     case dq_mode:
14752     case dqb_mode:
14753     case dqd_mode:
14754     case dqw_mode:
14755     case dqw_swap_mode:
14756       USED_REX (REX_W);
14757       if (rex & REX_W)
14758         names = names64;
14759       else
14760         {
14761           if ((sizeflag & DFLAG)
14762               || (bytemode != v_mode
14763                   && bytemode != v_swap_mode))
14764             names = names32;
14765           else
14766             names = names16;
14767           used_prefixes |= (prefixes & PREFIX_DATA);
14768         }
14769       break;
14770     case mask_bd_mode:
14771     case mask_mode:
14772       names = names_mask;
14773       break;
14774     case 0:
14775       return;
14776     default:
14777       oappend (INTERNAL_DISASSEMBLER_ERROR);
14778       return;
14779     }
14780   oappend (names[reg]);
14781 }
14782
14783 static void
14784 OP_E_memory (int bytemode, int sizeflag)
14785 {
14786   bfd_vma disp = 0;
14787   int add = (rex & REX_B) ? 8 : 0;
14788   int riprel = 0;
14789   int shift;
14790
14791   if (vex.evex)
14792     {
14793       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14794       if (vex.b
14795           && bytemode != x_mode
14796           && bytemode != xmmq_mode
14797           && bytemode != evex_half_bcst_xmmq_mode)
14798         {
14799           BadOp ();
14800           return;
14801         }
14802       switch (bytemode)
14803         {
14804         case dqw_mode:
14805         case dw_mode:
14806         case dqw_swap_mode:
14807           shift = 1;
14808           break;
14809         case dqb_mode:
14810         case db_mode:
14811           shift = 0;
14812           break;
14813         case vex_vsib_d_w_dq_mode:
14814         case vex_vsib_d_w_d_mode:
14815         case vex_vsib_q_w_dq_mode:
14816         case vex_vsib_q_w_d_mode:
14817         case evex_x_gscat_mode:
14818         case xmm_mdq_mode:
14819           shift = vex.w ? 3 : 2;
14820           break;
14821         case x_mode:
14822         case evex_half_bcst_xmmq_mode:
14823         case xmmq_mode:
14824           if (vex.b)
14825             {
14826               shift = vex.w ? 3 : 2;
14827               break;
14828             }
14829           /* Fall through if vex.b == 0.  */
14830         case xmmqd_mode:
14831         case xmmdw_mode:
14832         case ymmq_mode:
14833         case evex_x_nobcst_mode:
14834         case x_swap_mode:
14835           switch (vex.length)
14836             {
14837             case 128:
14838               shift = 4;
14839               break;
14840             case 256:
14841               shift = 5;
14842               break;
14843             case 512:
14844               shift = 6;
14845               break;
14846             default:
14847               abort ();
14848             }
14849           break;
14850         case ymm_mode:
14851           shift = 5;
14852           break;
14853         case xmm_mode:
14854           shift = 4;
14855           break;
14856         case xmm_mq_mode:
14857         case q_mode:
14858         case q_scalar_mode:
14859         case q_swap_mode:
14860         case q_scalar_swap_mode:
14861           shift = 3;
14862           break;
14863         case dqd_mode:
14864         case xmm_md_mode:
14865         case d_mode:
14866         case d_scalar_mode:
14867         case d_swap_mode:
14868         case d_scalar_swap_mode:
14869           shift = 2;
14870           break;
14871         case xmm_mw_mode:
14872           shift = 1;
14873           break;
14874         case xmm_mb_mode:
14875           shift = 0;
14876           break;
14877         default:
14878           abort ();
14879         }
14880       /* Make necessary corrections to shift for modes that need it.
14881          For these modes we currently have shift 4, 5 or 6 depending on
14882          vex.length (it corresponds to xmmword, ymmword or zmmword
14883          operand).  We might want to make it 3, 4 or 5 (e.g. for
14884          xmmq_mode).  In case of broadcast enabled the corrections
14885          aren't needed, as element size is always 32 or 64 bits.  */
14886       if (!vex.b
14887           && (bytemode == xmmq_mode
14888               || bytemode == evex_half_bcst_xmmq_mode))
14889         shift -= 1;
14890       else if (bytemode == xmmqd_mode)
14891         shift -= 2;
14892       else if (bytemode == xmmdw_mode)
14893         shift -= 3;
14894       else if (bytemode == ymmq_mode && vex.length == 128)
14895         shift -= 1;
14896     }
14897   else
14898     shift = 0;
14899
14900   USED_REX (REX_B);
14901   if (intel_syntax)
14902     intel_operand_size (bytemode, sizeflag);
14903   append_seg ();
14904
14905   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14906     {
14907       /* 32/64 bit address mode */
14908       int havedisp;
14909       int havesib;
14910       int havebase;
14911       int haveindex;
14912       int needindex;
14913       int base, rbase;
14914       int vindex = 0;
14915       int scale = 0;
14916       int addr32flag = !((sizeflag & AFLAG)
14917                          || bytemode == v_bnd_mode
14918                          || bytemode == bnd_mode);
14919       const char **indexes64 = names64;
14920       const char **indexes32 = names32;
14921
14922       havesib = 0;
14923       havebase = 1;
14924       haveindex = 0;
14925       base = modrm.rm;
14926
14927       if (base == 4)
14928         {
14929           havesib = 1;
14930           vindex = sib.index;
14931           USED_REX (REX_X);
14932           if (rex & REX_X)
14933             vindex += 8;
14934           switch (bytemode)
14935             {
14936             case vex_vsib_d_w_dq_mode:
14937             case vex_vsib_d_w_d_mode:
14938             case vex_vsib_q_w_dq_mode:
14939             case vex_vsib_q_w_d_mode:
14940               if (!need_vex)
14941                 abort ();
14942               if (vex.evex)
14943                 {
14944                   if (!vex.v)
14945                     vindex += 16;
14946                 }
14947
14948               haveindex = 1;
14949               switch (vex.length)
14950                 {
14951                 case 128:
14952                   indexes64 = indexes32 = names_xmm;
14953                   break;
14954                 case 256:
14955                   if (!vex.w
14956                       || bytemode == vex_vsib_q_w_dq_mode
14957                       || bytemode == vex_vsib_q_w_d_mode)
14958                     indexes64 = indexes32 = names_ymm;
14959                   else
14960                     indexes64 = indexes32 = names_xmm;
14961                   break;
14962                 case 512:
14963                   if (!vex.w
14964                       || bytemode == vex_vsib_q_w_dq_mode
14965                       || bytemode == vex_vsib_q_w_d_mode)
14966                     indexes64 = indexes32 = names_zmm;
14967                   else
14968                     indexes64 = indexes32 = names_ymm;
14969                   break;
14970                 default:
14971                   abort ();
14972                 }
14973               break;
14974             default:
14975               haveindex = vindex != 4;
14976               break;
14977             }
14978           scale = sib.scale;
14979           base = sib.base;
14980           codep++;
14981         }
14982       rbase = base + add;
14983
14984       switch (modrm.mod)
14985         {
14986         case 0:
14987           if (base == 5)
14988             {
14989               havebase = 0;
14990               if (address_mode == mode_64bit && !havesib)
14991                 riprel = 1;
14992               disp = get32s ();
14993             }
14994           break;
14995         case 1:
14996           FETCH_DATA (the_info, codep + 1);
14997           disp = *codep++;
14998           if ((disp & 0x80) != 0)
14999             disp -= 0x100;
15000           if (vex.evex && shift > 0)
15001             disp <<= shift;
15002           break;
15003         case 2:
15004           disp = get32s ();
15005           break;
15006         }
15007
15008       /* In 32bit mode, we need index register to tell [offset] from
15009          [eiz*1 + offset].  */
15010       needindex = (havesib
15011                    && !havebase
15012                    && !haveindex
15013                    && address_mode == mode_32bit);
15014       havedisp = (havebase
15015                   || needindex
15016                   || (havesib && (haveindex || scale != 0)));
15017
15018       if (!intel_syntax)
15019         if (modrm.mod != 0 || base == 5)
15020           {
15021             if (havedisp || riprel)
15022               print_displacement (scratchbuf, disp);
15023             else
15024               print_operand_value (scratchbuf, 1, disp);
15025             oappend (scratchbuf);
15026             if (riprel)
15027               {
15028                 set_op (disp, 1);
15029                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
15030               }
15031           }
15032
15033       if ((havebase || haveindex || riprel)
15034           && (bytemode != v_bnd_mode)
15035           && (bytemode != bnd_mode))
15036         used_prefixes |= PREFIX_ADDR;
15037
15038       if (havedisp || (intel_syntax && riprel))
15039         {
15040           *obufp++ = open_char;
15041           if (intel_syntax && riprel)
15042             {
15043               set_op (disp, 1);
15044               oappend (sizeflag & AFLAG ? "rip" : "eip");
15045             }
15046           *obufp = '\0';
15047           if (havebase)
15048             oappend (address_mode == mode_64bit && !addr32flag
15049                      ? names64[rbase] : names32[rbase]);
15050           if (havesib)
15051             {
15052               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15053                  print index to tell base + index from base.  */
15054               if (scale != 0
15055                   || needindex
15056                   || haveindex
15057                   || (havebase && base != ESP_REG_NUM))
15058                 {
15059                   if (!intel_syntax || havebase)
15060                     {
15061                       *obufp++ = separator_char;
15062                       *obufp = '\0';
15063                     }
15064                   if (haveindex)
15065                     oappend (address_mode == mode_64bit && !addr32flag
15066                              ? indexes64[vindex] : indexes32[vindex]);
15067                   else
15068                     oappend (address_mode == mode_64bit && !addr32flag
15069                              ? index64 : index32);
15070
15071                   *obufp++ = scale_char;
15072                   *obufp = '\0';
15073                   sprintf (scratchbuf, "%d", 1 << scale);
15074                   oappend (scratchbuf);
15075                 }
15076             }
15077           if (intel_syntax
15078               && (disp || modrm.mod != 0 || base == 5))
15079             {
15080               if (!havedisp || (bfd_signed_vma) disp >= 0)
15081                 {
15082                   *obufp++ = '+';
15083                   *obufp = '\0';
15084                 }
15085               else if (modrm.mod != 1 && disp != -disp)
15086                 {
15087                   *obufp++ = '-';
15088                   *obufp = '\0';
15089                   disp = - (bfd_signed_vma) disp;
15090                 }
15091
15092               if (havedisp)
15093                 print_displacement (scratchbuf, disp);
15094               else
15095                 print_operand_value (scratchbuf, 1, disp);
15096               oappend (scratchbuf);
15097             }
15098
15099           *obufp++ = close_char;
15100           *obufp = '\0';
15101         }
15102       else if (intel_syntax)
15103         {
15104           if (modrm.mod != 0 || base == 5)
15105             {
15106               if (!active_seg_prefix)
15107                 {
15108                   oappend (names_seg[ds_reg - es_reg]);
15109                   oappend (":");
15110                 }
15111               print_operand_value (scratchbuf, 1, disp);
15112               oappend (scratchbuf);
15113             }
15114         }
15115     }
15116   else
15117     {
15118       /* 16 bit address mode */
15119       used_prefixes |= prefixes & PREFIX_ADDR;
15120       switch (modrm.mod)
15121         {
15122         case 0:
15123           if (modrm.rm == 6)
15124             {
15125               disp = get16 ();
15126               if ((disp & 0x8000) != 0)
15127                 disp -= 0x10000;
15128             }
15129           break;
15130         case 1:
15131           FETCH_DATA (the_info, codep + 1);
15132           disp = *codep++;
15133           if ((disp & 0x80) != 0)
15134             disp -= 0x100;
15135           break;
15136         case 2:
15137           disp = get16 ();
15138           if ((disp & 0x8000) != 0)
15139             disp -= 0x10000;
15140           break;
15141         }
15142
15143       if (!intel_syntax)
15144         if (modrm.mod != 0 || modrm.rm == 6)
15145           {
15146             print_displacement (scratchbuf, disp);
15147             oappend (scratchbuf);
15148           }
15149
15150       if (modrm.mod != 0 || modrm.rm != 6)
15151         {
15152           *obufp++ = open_char;
15153           *obufp = '\0';
15154           oappend (index16[modrm.rm]);
15155           if (intel_syntax
15156               && (disp || modrm.mod != 0 || modrm.rm == 6))
15157             {
15158               if ((bfd_signed_vma) disp >= 0)
15159                 {
15160                   *obufp++ = '+';
15161                   *obufp = '\0';
15162                 }
15163               else if (modrm.mod != 1)
15164                 {
15165                   *obufp++ = '-';
15166                   *obufp = '\0';
15167                   disp = - (bfd_signed_vma) disp;
15168                 }
15169
15170               print_displacement (scratchbuf, disp);
15171               oappend (scratchbuf);
15172             }
15173
15174           *obufp++ = close_char;
15175           *obufp = '\0';
15176         }
15177       else if (intel_syntax)
15178         {
15179           if (!active_seg_prefix)
15180             {
15181               oappend (names_seg[ds_reg - es_reg]);
15182               oappend (":");
15183             }
15184           print_operand_value (scratchbuf, 1, disp & 0xffff);
15185           oappend (scratchbuf);
15186         }
15187     }
15188   if (vex.evex && vex.b
15189       && (bytemode == x_mode
15190           || bytemode == xmmq_mode
15191           || bytemode == evex_half_bcst_xmmq_mode))
15192     {
15193       if (vex.w
15194           || bytemode == xmmq_mode
15195           || bytemode == evex_half_bcst_xmmq_mode)
15196         {
15197           switch (vex.length)
15198             {
15199             case 128:
15200               oappend ("{1to2}");
15201               break;
15202             case 256:
15203               oappend ("{1to4}");
15204               break;
15205             case 512:
15206               oappend ("{1to8}");
15207               break;
15208             default:
15209               abort ();
15210             }
15211         }
15212       else
15213         {
15214           switch (vex.length)
15215             {
15216             case 128:
15217               oappend ("{1to4}");
15218               break;
15219             case 256:
15220               oappend ("{1to8}");
15221               break;
15222             case 512:
15223               oappend ("{1to16}");
15224               break;
15225             default:
15226               abort ();
15227             }
15228         }
15229     }
15230 }
15231
15232 static void
15233 OP_E (int bytemode, int sizeflag)
15234 {
15235   /* Skip mod/rm byte.  */
15236   MODRM_CHECK;
15237   codep++;
15238
15239   if (modrm.mod == 3)
15240     OP_E_register (bytemode, sizeflag);
15241   else
15242     OP_E_memory (bytemode, sizeflag);
15243 }
15244
15245 static void
15246 OP_G (int bytemode, int sizeflag)
15247 {
15248   int add = 0;
15249   USED_REX (REX_R);
15250   if (rex & REX_R)
15251     add += 8;
15252   switch (bytemode)
15253     {
15254     case b_mode:
15255       USED_REX (0);
15256       if (rex)
15257         oappend (names8rex[modrm.reg + add]);
15258       else
15259         oappend (names8[modrm.reg + add]);
15260       break;
15261     case w_mode:
15262       oappend (names16[modrm.reg + add]);
15263       break;
15264     case d_mode:
15265     case db_mode:
15266     case dw_mode:
15267       oappend (names32[modrm.reg + add]);
15268       break;
15269     case q_mode:
15270       oappend (names64[modrm.reg + add]);
15271       break;
15272     case bnd_mode:
15273       oappend (names_bnd[modrm.reg]);
15274       break;
15275     case v_mode:
15276     case dq_mode:
15277     case dqb_mode:
15278     case dqd_mode:
15279     case dqw_mode:
15280     case dqw_swap_mode:
15281       USED_REX (REX_W);
15282       if (rex & REX_W)
15283         oappend (names64[modrm.reg + add]);
15284       else
15285         {
15286           if ((sizeflag & DFLAG) || bytemode != v_mode)
15287             oappend (names32[modrm.reg + add]);
15288           else
15289             oappend (names16[modrm.reg + add]);
15290           used_prefixes |= (prefixes & PREFIX_DATA);
15291         }
15292       break;
15293     case m_mode:
15294       if (address_mode == mode_64bit)
15295         oappend (names64[modrm.reg + add]);
15296       else
15297         oappend (names32[modrm.reg + add]);
15298       break;
15299     case mask_bd_mode:
15300     case mask_mode:
15301       oappend (names_mask[modrm.reg + add]);
15302       break;
15303     default:
15304       oappend (INTERNAL_DISASSEMBLER_ERROR);
15305       break;
15306     }
15307 }
15308
15309 static bfd_vma
15310 get64 (void)
15311 {
15312   bfd_vma x;
15313 #ifdef BFD64
15314   unsigned int a;
15315   unsigned int b;
15316
15317   FETCH_DATA (the_info, codep + 8);
15318   a = *codep++ & 0xff;
15319   a |= (*codep++ & 0xff) << 8;
15320   a |= (*codep++ & 0xff) << 16;
15321   a |= (*codep++ & 0xff) << 24;
15322   b = *codep++ & 0xff;
15323   b |= (*codep++ & 0xff) << 8;
15324   b |= (*codep++ & 0xff) << 16;
15325   b |= (*codep++ & 0xff) << 24;
15326   x = a + ((bfd_vma) b << 32);
15327 #else
15328   abort ();
15329   x = 0;
15330 #endif
15331   return x;
15332 }
15333
15334 static bfd_signed_vma
15335 get32 (void)
15336 {
15337   bfd_signed_vma x = 0;
15338
15339   FETCH_DATA (the_info, codep + 4);
15340   x = *codep++ & (bfd_signed_vma) 0xff;
15341   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15342   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15343   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15344   return x;
15345 }
15346
15347 static bfd_signed_vma
15348 get32s (void)
15349 {
15350   bfd_signed_vma x = 0;
15351
15352   FETCH_DATA (the_info, codep + 4);
15353   x = *codep++ & (bfd_signed_vma) 0xff;
15354   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15355   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15356   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15357
15358   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15359
15360   return x;
15361 }
15362
15363 static int
15364 get16 (void)
15365 {
15366   int x = 0;
15367
15368   FETCH_DATA (the_info, codep + 2);
15369   x = *codep++ & 0xff;
15370   x |= (*codep++ & 0xff) << 8;
15371   return x;
15372 }
15373
15374 static void
15375 set_op (bfd_vma op, int riprel)
15376 {
15377   op_index[op_ad] = op_ad;
15378   if (address_mode == mode_64bit)
15379     {
15380       op_address[op_ad] = op;
15381       op_riprel[op_ad] = riprel;
15382     }
15383   else
15384     {
15385       /* Mask to get a 32-bit address.  */
15386       op_address[op_ad] = op & 0xffffffff;
15387       op_riprel[op_ad] = riprel & 0xffffffff;
15388     }
15389 }
15390
15391 static void
15392 OP_REG (int code, int sizeflag)
15393 {
15394   const char *s;
15395   int add;
15396
15397   switch (code)
15398     {
15399     case es_reg: case ss_reg: case cs_reg:
15400     case ds_reg: case fs_reg: case gs_reg:
15401       oappend (names_seg[code - es_reg]);
15402       return;
15403     }
15404
15405   USED_REX (REX_B);
15406   if (rex & REX_B)
15407     add = 8;
15408   else
15409     add = 0;
15410
15411   switch (code)
15412     {
15413     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15414     case sp_reg: case bp_reg: case si_reg: case di_reg:
15415       s = names16[code - ax_reg + add];
15416       break;
15417     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15418     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15419       USED_REX (0);
15420       if (rex)
15421         s = names8rex[code - al_reg + add];
15422       else
15423         s = names8[code - al_reg];
15424       break;
15425     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15426     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15427       if (address_mode == mode_64bit
15428           && ((sizeflag & DFLAG) || (rex & REX_W)))
15429         {
15430           s = names64[code - rAX_reg + add];
15431           break;
15432         }
15433       code += eAX_reg - rAX_reg;
15434       /* Fall through.  */
15435     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15436     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15437       USED_REX (REX_W);
15438       if (rex & REX_W)
15439         s = names64[code - eAX_reg + add];
15440       else
15441         {
15442           if (sizeflag & DFLAG)
15443             s = names32[code - eAX_reg + add];
15444           else
15445             s = names16[code - eAX_reg + add];
15446           used_prefixes |= (prefixes & PREFIX_DATA);
15447         }
15448       break;
15449     default:
15450       s = INTERNAL_DISASSEMBLER_ERROR;
15451       break;
15452     }
15453   oappend (s);
15454 }
15455
15456 static void
15457 OP_IMREG (int code, int sizeflag)
15458 {
15459   const char *s;
15460
15461   switch (code)
15462     {
15463     case indir_dx_reg:
15464       if (intel_syntax)
15465         s = "dx";
15466       else
15467         s = "(%dx)";
15468       break;
15469     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15470     case sp_reg: case bp_reg: case si_reg: case di_reg:
15471       s = names16[code - ax_reg];
15472       break;
15473     case es_reg: case ss_reg: case cs_reg:
15474     case ds_reg: case fs_reg: case gs_reg:
15475       s = names_seg[code - es_reg];
15476       break;
15477     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15478     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15479       USED_REX (0);
15480       if (rex)
15481         s = names8rex[code - al_reg];
15482       else
15483         s = names8[code - al_reg];
15484       break;
15485     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15486     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15487       USED_REX (REX_W);
15488       if (rex & REX_W)
15489         s = names64[code - eAX_reg];
15490       else
15491         {
15492           if (sizeflag & DFLAG)
15493             s = names32[code - eAX_reg];
15494           else
15495             s = names16[code - eAX_reg];
15496           used_prefixes |= (prefixes & PREFIX_DATA);
15497         }
15498       break;
15499     case z_mode_ax_reg:
15500       if ((rex & REX_W) || (sizeflag & DFLAG))
15501         s = *names32;
15502       else
15503         s = *names16;
15504       if (!(rex & REX_W))
15505         used_prefixes |= (prefixes & PREFIX_DATA);
15506       break;
15507     default:
15508       s = INTERNAL_DISASSEMBLER_ERROR;
15509       break;
15510     }
15511   oappend (s);
15512 }
15513
15514 static void
15515 OP_I (int bytemode, int sizeflag)
15516 {
15517   bfd_signed_vma op;
15518   bfd_signed_vma mask = -1;
15519
15520   switch (bytemode)
15521     {
15522     case b_mode:
15523       FETCH_DATA (the_info, codep + 1);
15524       op = *codep++;
15525       mask = 0xff;
15526       break;
15527     case q_mode:
15528       if (address_mode == mode_64bit)
15529         {
15530           op = get32s ();
15531           break;
15532         }
15533       /* Fall through.  */
15534     case v_mode:
15535       USED_REX (REX_W);
15536       if (rex & REX_W)
15537         op = get32s ();
15538       else
15539         {
15540           if (sizeflag & DFLAG)
15541             {
15542               op = get32 ();
15543               mask = 0xffffffff;
15544             }
15545           else
15546             {
15547               op = get16 ();
15548               mask = 0xfffff;
15549             }
15550           used_prefixes |= (prefixes & PREFIX_DATA);
15551         }
15552       break;
15553     case w_mode:
15554       mask = 0xfffff;
15555       op = get16 ();
15556       break;
15557     case const_1_mode:
15558       if (intel_syntax)
15559         oappend ("1");
15560       return;
15561     default:
15562       oappend (INTERNAL_DISASSEMBLER_ERROR);
15563       return;
15564     }
15565
15566   op &= mask;
15567   scratchbuf[0] = '$';
15568   print_operand_value (scratchbuf + 1, 1, op);
15569   oappend_maybe_intel (scratchbuf);
15570   scratchbuf[0] = '\0';
15571 }
15572
15573 static void
15574 OP_I64 (int bytemode, int sizeflag)
15575 {
15576   bfd_signed_vma op;
15577   bfd_signed_vma mask = -1;
15578
15579   if (address_mode != mode_64bit)
15580     {
15581       OP_I (bytemode, sizeflag);
15582       return;
15583     }
15584
15585   switch (bytemode)
15586     {
15587     case b_mode:
15588       FETCH_DATA (the_info, codep + 1);
15589       op = *codep++;
15590       mask = 0xff;
15591       break;
15592     case v_mode:
15593       USED_REX (REX_W);
15594       if (rex & REX_W)
15595         op = get64 ();
15596       else
15597         {
15598           if (sizeflag & DFLAG)
15599             {
15600               op = get32 ();
15601               mask = 0xffffffff;
15602             }
15603           else
15604             {
15605               op = get16 ();
15606               mask = 0xfffff;
15607             }
15608           used_prefixes |= (prefixes & PREFIX_DATA);
15609         }
15610       break;
15611     case w_mode:
15612       mask = 0xfffff;
15613       op = get16 ();
15614       break;
15615     default:
15616       oappend (INTERNAL_DISASSEMBLER_ERROR);
15617       return;
15618     }
15619
15620   op &= mask;
15621   scratchbuf[0] = '$';
15622   print_operand_value (scratchbuf + 1, 1, op);
15623   oappend_maybe_intel (scratchbuf);
15624   scratchbuf[0] = '\0';
15625 }
15626
15627 static void
15628 OP_sI (int bytemode, int sizeflag)
15629 {
15630   bfd_signed_vma op;
15631
15632   switch (bytemode)
15633     {
15634     case b_mode:
15635     case b_T_mode:
15636       FETCH_DATA (the_info, codep + 1);
15637       op = *codep++;
15638       if ((op & 0x80) != 0)
15639         op -= 0x100;
15640       if (bytemode == b_T_mode)
15641         {
15642           if (address_mode != mode_64bit
15643               || !((sizeflag & DFLAG) || (rex & REX_W)))
15644             {
15645               /* The operand-size prefix is overridden by a REX prefix.  */
15646               if ((sizeflag & DFLAG) || (rex & REX_W))
15647                 op &= 0xffffffff;
15648               else
15649                 op &= 0xffff;
15650           }
15651         }
15652       else
15653         {
15654           if (!(rex & REX_W))
15655             {
15656               if (sizeflag & DFLAG)
15657                 op &= 0xffffffff;
15658               else
15659                 op &= 0xffff;
15660             }
15661         }
15662       break;
15663     case v_mode:
15664       /* The operand-size prefix is overridden by a REX prefix.  */
15665       if ((sizeflag & DFLAG) || (rex & REX_W))
15666         op = get32s ();
15667       else
15668         op = get16 ();
15669       break;
15670     default:
15671       oappend (INTERNAL_DISASSEMBLER_ERROR);
15672       return;
15673     }
15674
15675   scratchbuf[0] = '$';
15676   print_operand_value (scratchbuf + 1, 1, op);
15677   oappend_maybe_intel (scratchbuf);
15678 }
15679
15680 static void
15681 OP_J (int bytemode, int sizeflag)
15682 {
15683   bfd_vma disp;
15684   bfd_vma mask = -1;
15685   bfd_vma segment = 0;
15686
15687   switch (bytemode)
15688     {
15689     case b_mode:
15690       FETCH_DATA (the_info, codep + 1);
15691       disp = *codep++;
15692       if ((disp & 0x80) != 0)
15693         disp -= 0x100;
15694       break;
15695     case v_mode:
15696       USED_REX (REX_W);
15697       if ((sizeflag & DFLAG) || (rex & REX_W))
15698         disp = get32s ();
15699       else
15700         {
15701           disp = get16 ();
15702           if ((disp & 0x8000) != 0)
15703             disp -= 0x10000;
15704           /* In 16bit mode, address is wrapped around at 64k within
15705              the same segment.  Otherwise, a data16 prefix on a jump
15706              instruction means that the pc is masked to 16 bits after
15707              the displacement is added!  */
15708           mask = 0xffff;
15709           if ((prefixes & PREFIX_DATA) == 0)
15710             segment = ((start_pc + codep - start_codep)
15711                        & ~((bfd_vma) 0xffff));
15712         }
15713       if (!(rex & REX_W))
15714         used_prefixes |= (prefixes & PREFIX_DATA);
15715       break;
15716     default:
15717       oappend (INTERNAL_DISASSEMBLER_ERROR);
15718       return;
15719     }
15720   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15721   set_op (disp, 0);
15722   print_operand_value (scratchbuf, 1, disp);
15723   oappend (scratchbuf);
15724 }
15725
15726 static void
15727 OP_SEG (int bytemode, int sizeflag)
15728 {
15729   if (bytemode == w_mode)
15730     oappend (names_seg[modrm.reg]);
15731   else
15732     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15733 }
15734
15735 static void
15736 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15737 {
15738   int seg, offset;
15739
15740   if (sizeflag & DFLAG)
15741     {
15742       offset = get32 ();
15743       seg = get16 ();
15744     }
15745   else
15746     {
15747       offset = get16 ();
15748       seg = get16 ();
15749     }
15750   used_prefixes |= (prefixes & PREFIX_DATA);
15751   if (intel_syntax)
15752     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15753   else
15754     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15755   oappend (scratchbuf);
15756 }
15757
15758 static void
15759 OP_OFF (int bytemode, int sizeflag)
15760 {
15761   bfd_vma off;
15762
15763   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15764     intel_operand_size (bytemode, sizeflag);
15765   append_seg ();
15766
15767   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15768     off = get32 ();
15769   else
15770     off = get16 ();
15771
15772   if (intel_syntax)
15773     {
15774       if (!active_seg_prefix)
15775         {
15776           oappend (names_seg[ds_reg - es_reg]);
15777           oappend (":");
15778         }
15779     }
15780   print_operand_value (scratchbuf, 1, off);
15781   oappend (scratchbuf);
15782 }
15783
15784 static void
15785 OP_OFF64 (int bytemode, int sizeflag)
15786 {
15787   bfd_vma off;
15788
15789   if (address_mode != mode_64bit
15790       || (prefixes & PREFIX_ADDR))
15791     {
15792       OP_OFF (bytemode, sizeflag);
15793       return;
15794     }
15795
15796   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15797     intel_operand_size (bytemode, sizeflag);
15798   append_seg ();
15799
15800   off = get64 ();
15801
15802   if (intel_syntax)
15803     {
15804       if (!active_seg_prefix)
15805         {
15806           oappend (names_seg[ds_reg - es_reg]);
15807           oappend (":");
15808         }
15809     }
15810   print_operand_value (scratchbuf, 1, off);
15811   oappend (scratchbuf);
15812 }
15813
15814 static void
15815 ptr_reg (int code, int sizeflag)
15816 {
15817   const char *s;
15818
15819   *obufp++ = open_char;
15820   used_prefixes |= (prefixes & PREFIX_ADDR);
15821   if (address_mode == mode_64bit)
15822     {
15823       if (!(sizeflag & AFLAG))
15824         s = names32[code - eAX_reg];
15825       else
15826         s = names64[code - eAX_reg];
15827     }
15828   else if (sizeflag & AFLAG)
15829     s = names32[code - eAX_reg];
15830   else
15831     s = names16[code - eAX_reg];
15832   oappend (s);
15833   *obufp++ = close_char;
15834   *obufp = 0;
15835 }
15836
15837 static void
15838 OP_ESreg (int code, int sizeflag)
15839 {
15840   if (intel_syntax)
15841     {
15842       switch (codep[-1])
15843         {
15844         case 0x6d:      /* insw/insl */
15845           intel_operand_size (z_mode, sizeflag);
15846           break;
15847         case 0xa5:      /* movsw/movsl/movsq */
15848         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15849         case 0xab:      /* stosw/stosl */
15850         case 0xaf:      /* scasw/scasl */
15851           intel_operand_size (v_mode, sizeflag);
15852           break;
15853         default:
15854           intel_operand_size (b_mode, sizeflag);
15855         }
15856     }
15857   oappend_maybe_intel ("%es:");
15858   ptr_reg (code, sizeflag);
15859 }
15860
15861 static void
15862 OP_DSreg (int code, int sizeflag)
15863 {
15864   if (intel_syntax)
15865     {
15866       switch (codep[-1])
15867         {
15868         case 0x6f:      /* outsw/outsl */
15869           intel_operand_size (z_mode, sizeflag);
15870           break;
15871         case 0xa5:      /* movsw/movsl/movsq */
15872         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15873         case 0xad:      /* lodsw/lodsl/lodsq */
15874           intel_operand_size (v_mode, sizeflag);
15875           break;
15876         default:
15877           intel_operand_size (b_mode, sizeflag);
15878         }
15879     }
15880   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15881      default segment register DS is printed.  */
15882   if (!active_seg_prefix)
15883     active_seg_prefix = PREFIX_DS;
15884   append_seg ();
15885   ptr_reg (code, sizeflag);
15886 }
15887
15888 static void
15889 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15890 {
15891   int add;
15892   if (rex & REX_R)
15893     {
15894       USED_REX (REX_R);
15895       add = 8;
15896     }
15897   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15898     {
15899       all_prefixes[last_lock_prefix] = 0;
15900       used_prefixes |= PREFIX_LOCK;
15901       add = 8;
15902     }
15903   else
15904     add = 0;
15905   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15906   oappend_maybe_intel (scratchbuf);
15907 }
15908
15909 static void
15910 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15911 {
15912   int add;
15913   USED_REX (REX_R);
15914   if (rex & REX_R)
15915     add = 8;
15916   else
15917     add = 0;
15918   if (intel_syntax)
15919     sprintf (scratchbuf, "db%d", modrm.reg + add);
15920   else
15921     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15922   oappend (scratchbuf);
15923 }
15924
15925 static void
15926 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15927 {
15928   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15929   oappend_maybe_intel (scratchbuf);
15930 }
15931
15932 static void
15933 OP_R (int bytemode, int sizeflag)
15934 {
15935   /* Skip mod/rm byte.  */
15936   MODRM_CHECK;
15937   codep++;
15938   OP_E_register (bytemode, sizeflag);
15939 }
15940
15941 static void
15942 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15943 {
15944   int reg = modrm.reg;
15945   const char **names;
15946
15947   used_prefixes |= (prefixes & PREFIX_DATA);
15948   if (prefixes & PREFIX_DATA)
15949     {
15950       names = names_xmm;
15951       USED_REX (REX_R);
15952       if (rex & REX_R)
15953         reg += 8;
15954     }
15955   else
15956     names = names_mm;
15957   oappend (names[reg]);
15958 }
15959
15960 static void
15961 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15962 {
15963   int reg = modrm.reg;
15964   const char **names;
15965
15966   USED_REX (REX_R);
15967   if (rex & REX_R)
15968     reg += 8;
15969   if (vex.evex)
15970     {
15971       if (!vex.r)
15972         reg += 16;
15973     }
15974
15975   if (need_vex
15976       && bytemode != xmm_mode
15977       && bytemode != xmmq_mode
15978       && bytemode != evex_half_bcst_xmmq_mode
15979       && bytemode != ymm_mode
15980       && bytemode != scalar_mode)
15981     {
15982       switch (vex.length)
15983         {
15984         case 128:
15985           names = names_xmm;
15986           break;
15987         case 256:
15988           if (vex.w
15989               || (bytemode != vex_vsib_q_w_dq_mode
15990                   && bytemode != vex_vsib_q_w_d_mode))
15991             names = names_ymm;
15992           else
15993             names = names_xmm;
15994           break;
15995         case 512:
15996           names = names_zmm;
15997           break;
15998         default:
15999           abort ();
16000         }
16001     }
16002   else if (bytemode == xmmq_mode
16003            || bytemode == evex_half_bcst_xmmq_mode)
16004     {
16005       switch (vex.length)
16006         {
16007         case 128:
16008         case 256:
16009           names = names_xmm;
16010           break;
16011         case 512:
16012           names = names_ymm;
16013           break;
16014         default:
16015           abort ();
16016         }
16017     }
16018   else if (bytemode == ymm_mode)
16019     names = names_ymm;
16020   else
16021     names = names_xmm;
16022   oappend (names[reg]);
16023 }
16024
16025 static void
16026 OP_EM (int bytemode, int sizeflag)
16027 {
16028   int reg;
16029   const char **names;
16030
16031   if (modrm.mod != 3)
16032     {
16033       if (intel_syntax
16034           && (bytemode == v_mode || bytemode == v_swap_mode))
16035         {
16036           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16037           used_prefixes |= (prefixes & PREFIX_DATA);
16038         }
16039       OP_E (bytemode, sizeflag);
16040       return;
16041     }
16042
16043   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16044     swap_operand ();
16045
16046   /* Skip mod/rm byte.  */
16047   MODRM_CHECK;
16048   codep++;
16049   used_prefixes |= (prefixes & PREFIX_DATA);
16050   reg = modrm.rm;
16051   if (prefixes & PREFIX_DATA)
16052     {
16053       names = names_xmm;
16054       USED_REX (REX_B);
16055       if (rex & REX_B)
16056         reg += 8;
16057     }
16058   else
16059     names = names_mm;
16060   oappend (names[reg]);
16061 }
16062
16063 /* cvt* are the only instructions in sse2 which have
16064    both SSE and MMX operands and also have 0x66 prefix
16065    in their opcode. 0x66 was originally used to differentiate
16066    between SSE and MMX instruction(operands). So we have to handle the
16067    cvt* separately using OP_EMC and OP_MXC */
16068 static void
16069 OP_EMC (int bytemode, int sizeflag)
16070 {
16071   if (modrm.mod != 3)
16072     {
16073       if (intel_syntax && bytemode == v_mode)
16074         {
16075           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16076           used_prefixes |= (prefixes & PREFIX_DATA);
16077         }
16078       OP_E (bytemode, sizeflag);
16079       return;
16080     }
16081
16082   /* Skip mod/rm byte.  */
16083   MODRM_CHECK;
16084   codep++;
16085   used_prefixes |= (prefixes & PREFIX_DATA);
16086   oappend (names_mm[modrm.rm]);
16087 }
16088
16089 static void
16090 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16091 {
16092   used_prefixes |= (prefixes & PREFIX_DATA);
16093   oappend (names_mm[modrm.reg]);
16094 }
16095
16096 static void
16097 OP_EX (int bytemode, int sizeflag)
16098 {
16099   int reg;
16100   const char **names;
16101
16102   /* Skip mod/rm byte.  */
16103   MODRM_CHECK;
16104   codep++;
16105
16106   if (modrm.mod != 3)
16107     {
16108       OP_E_memory (bytemode, sizeflag);
16109       return;
16110     }
16111
16112   reg = modrm.rm;
16113   USED_REX (REX_B);
16114   if (rex & REX_B)
16115     reg += 8;
16116   if (vex.evex)
16117     {
16118       USED_REX (REX_X);
16119       if ((rex & REX_X))
16120         reg += 16;
16121     }
16122
16123   if ((sizeflag & SUFFIX_ALWAYS)
16124       && (bytemode == x_swap_mode
16125           || bytemode == d_swap_mode
16126           || bytemode == dqw_swap_mode
16127           || bytemode == d_scalar_swap_mode
16128           || bytemode == q_swap_mode
16129           || bytemode == q_scalar_swap_mode))
16130     swap_operand ();
16131
16132   if (need_vex
16133       && bytemode != xmm_mode
16134       && bytemode != xmmdw_mode
16135       && bytemode != xmmqd_mode
16136       && bytemode != xmm_mb_mode
16137       && bytemode != xmm_mw_mode
16138       && bytemode != xmm_md_mode
16139       && bytemode != xmm_mq_mode
16140       && bytemode != xmm_mdq_mode
16141       && bytemode != xmmq_mode
16142       && bytemode != evex_half_bcst_xmmq_mode
16143       && bytemode != ymm_mode
16144       && bytemode != d_scalar_mode
16145       && bytemode != d_scalar_swap_mode
16146       && bytemode != q_scalar_mode
16147       && bytemode != q_scalar_swap_mode
16148       && bytemode != vex_scalar_w_dq_mode)
16149     {
16150       switch (vex.length)
16151         {
16152         case 128:
16153           names = names_xmm;
16154           break;
16155         case 256:
16156           names = names_ymm;
16157           break;
16158         case 512:
16159           names = names_zmm;
16160           break;
16161         default:
16162           abort ();
16163         }
16164     }
16165   else if (bytemode == xmmq_mode
16166            || bytemode == evex_half_bcst_xmmq_mode)
16167     {
16168       switch (vex.length)
16169         {
16170         case 128:
16171         case 256:
16172           names = names_xmm;
16173           break;
16174         case 512:
16175           names = names_ymm;
16176           break;
16177         default:
16178           abort ();
16179         }
16180     }
16181   else if (bytemode == ymm_mode)
16182     names = names_ymm;
16183   else
16184     names = names_xmm;
16185   oappend (names[reg]);
16186 }
16187
16188 static void
16189 OP_MS (int bytemode, int sizeflag)
16190 {
16191   if (modrm.mod == 3)
16192     OP_EM (bytemode, sizeflag);
16193   else
16194     BadOp ();
16195 }
16196
16197 static void
16198 OP_XS (int bytemode, int sizeflag)
16199 {
16200   if (modrm.mod == 3)
16201     OP_EX (bytemode, sizeflag);
16202   else
16203     BadOp ();
16204 }
16205
16206 static void
16207 OP_M (int bytemode, int sizeflag)
16208 {
16209   if (modrm.mod == 3)
16210     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16211     BadOp ();
16212   else
16213     OP_E (bytemode, sizeflag);
16214 }
16215
16216 static void
16217 OP_0f07 (int bytemode, int sizeflag)
16218 {
16219   if (modrm.mod != 3 || modrm.rm != 0)
16220     BadOp ();
16221   else
16222     OP_E (bytemode, sizeflag);
16223 }
16224
16225 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16226    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16227
16228 static void
16229 NOP_Fixup1 (int bytemode, int sizeflag)
16230 {
16231   if ((prefixes & PREFIX_DATA) != 0
16232       || (rex != 0
16233           && rex != 0x48
16234           && address_mode == mode_64bit))
16235     OP_REG (bytemode, sizeflag);
16236   else
16237     strcpy (obuf, "nop");
16238 }
16239
16240 static void
16241 NOP_Fixup2 (int bytemode, int sizeflag)
16242 {
16243   if ((prefixes & PREFIX_DATA) != 0
16244       || (rex != 0
16245           && rex != 0x48
16246           && address_mode == mode_64bit))
16247     OP_IMREG (bytemode, sizeflag);
16248 }
16249
16250 static const char *const Suffix3DNow[] = {
16251 /* 00 */        NULL,           NULL,           NULL,           NULL,
16252 /* 04 */        NULL,           NULL,           NULL,           NULL,
16253 /* 08 */        NULL,           NULL,           NULL,           NULL,
16254 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16255 /* 10 */        NULL,           NULL,           NULL,           NULL,
16256 /* 14 */        NULL,           NULL,           NULL,           NULL,
16257 /* 18 */        NULL,           NULL,           NULL,           NULL,
16258 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16259 /* 20 */        NULL,           NULL,           NULL,           NULL,
16260 /* 24 */        NULL,           NULL,           NULL,           NULL,
16261 /* 28 */        NULL,           NULL,           NULL,           NULL,
16262 /* 2C */        NULL,           NULL,           NULL,           NULL,
16263 /* 30 */        NULL,           NULL,           NULL,           NULL,
16264 /* 34 */        NULL,           NULL,           NULL,           NULL,
16265 /* 38 */        NULL,           NULL,           NULL,           NULL,
16266 /* 3C */        NULL,           NULL,           NULL,           NULL,
16267 /* 40 */        NULL,           NULL,           NULL,           NULL,
16268 /* 44 */        NULL,           NULL,           NULL,           NULL,
16269 /* 48 */        NULL,           NULL,           NULL,           NULL,
16270 /* 4C */        NULL,           NULL,           NULL,           NULL,
16271 /* 50 */        NULL,           NULL,           NULL,           NULL,
16272 /* 54 */        NULL,           NULL,           NULL,           NULL,
16273 /* 58 */        NULL,           NULL,           NULL,           NULL,
16274 /* 5C */        NULL,           NULL,           NULL,           NULL,
16275 /* 60 */        NULL,           NULL,           NULL,           NULL,
16276 /* 64 */        NULL,           NULL,           NULL,           NULL,
16277 /* 68 */        NULL,           NULL,           NULL,           NULL,
16278 /* 6C */        NULL,           NULL,           NULL,           NULL,
16279 /* 70 */        NULL,           NULL,           NULL,           NULL,
16280 /* 74 */        NULL,           NULL,           NULL,           NULL,
16281 /* 78 */        NULL,           NULL,           NULL,           NULL,
16282 /* 7C */        NULL,           NULL,           NULL,           NULL,
16283 /* 80 */        NULL,           NULL,           NULL,           NULL,
16284 /* 84 */        NULL,           NULL,           NULL,           NULL,
16285 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16286 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16287 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16288 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16289 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16290 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16291 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16292 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16293 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16294 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16295 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16296 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16297 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16298 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16299 /* C0 */        NULL,           NULL,           NULL,           NULL,
16300 /* C4 */        NULL,           NULL,           NULL,           NULL,
16301 /* C8 */        NULL,           NULL,           NULL,           NULL,
16302 /* CC */        NULL,           NULL,           NULL,           NULL,
16303 /* D0 */        NULL,           NULL,           NULL,           NULL,
16304 /* D4 */        NULL,           NULL,           NULL,           NULL,
16305 /* D8 */        NULL,           NULL,           NULL,           NULL,
16306 /* DC */        NULL,           NULL,           NULL,           NULL,
16307 /* E0 */        NULL,           NULL,           NULL,           NULL,
16308 /* E4 */        NULL,           NULL,           NULL,           NULL,
16309 /* E8 */        NULL,           NULL,           NULL,           NULL,
16310 /* EC */        NULL,           NULL,           NULL,           NULL,
16311 /* F0 */        NULL,           NULL,           NULL,           NULL,
16312 /* F4 */        NULL,           NULL,           NULL,           NULL,
16313 /* F8 */        NULL,           NULL,           NULL,           NULL,
16314 /* FC */        NULL,           NULL,           NULL,           NULL,
16315 };
16316
16317 static void
16318 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16319 {
16320   const char *mnemonic;
16321
16322   FETCH_DATA (the_info, codep + 1);
16323   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16324      place where an 8-bit immediate would normally go.  ie. the last
16325      byte of the instruction.  */
16326   obufp = mnemonicendp;
16327   mnemonic = Suffix3DNow[*codep++ & 0xff];
16328   if (mnemonic)
16329     oappend (mnemonic);
16330   else
16331     {
16332       /* Since a variable sized modrm/sib chunk is between the start
16333          of the opcode (0x0f0f) and the opcode suffix, we need to do
16334          all the modrm processing first, and don't know until now that
16335          we have a bad opcode.  This necessitates some cleaning up.  */
16336       op_out[0][0] = '\0';
16337       op_out[1][0] = '\0';
16338       BadOp ();
16339     }
16340   mnemonicendp = obufp;
16341 }
16342
16343 static struct op simd_cmp_op[] =
16344 {
16345   { STRING_COMMA_LEN ("eq") },
16346   { STRING_COMMA_LEN ("lt") },
16347   { STRING_COMMA_LEN ("le") },
16348   { STRING_COMMA_LEN ("unord") },
16349   { STRING_COMMA_LEN ("neq") },
16350   { STRING_COMMA_LEN ("nlt") },
16351   { STRING_COMMA_LEN ("nle") },
16352   { STRING_COMMA_LEN ("ord") }
16353 };
16354
16355 static void
16356 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16357 {
16358   unsigned int cmp_type;
16359
16360   FETCH_DATA (the_info, codep + 1);
16361   cmp_type = *codep++ & 0xff;
16362   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16363     {
16364       char suffix [3];
16365       char *p = mnemonicendp - 2;
16366       suffix[0] = p[0];
16367       suffix[1] = p[1];
16368       suffix[2] = '\0';
16369       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16370       mnemonicendp += simd_cmp_op[cmp_type].len;
16371     }
16372   else
16373     {
16374       /* We have a reserved extension byte.  Output it directly.  */
16375       scratchbuf[0] = '$';
16376       print_operand_value (scratchbuf + 1, 1, cmp_type);
16377       oappend_maybe_intel (scratchbuf);
16378       scratchbuf[0] = '\0';
16379     }
16380 }
16381
16382 static void
16383 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16384           int sizeflag ATTRIBUTE_UNUSED)
16385 {
16386   /* mwait %eax,%ecx  */
16387   if (!intel_syntax)
16388     {
16389       const char **names = (address_mode == mode_64bit
16390                             ? names64 : names32);
16391       strcpy (op_out[0], names[0]);
16392       strcpy (op_out[1], names[1]);
16393       two_source_ops = 1;
16394     }
16395   /* Skip mod/rm byte.  */
16396   MODRM_CHECK;
16397   codep++;
16398 }
16399
16400 static void
16401 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16402             int sizeflag ATTRIBUTE_UNUSED)
16403 {
16404   /* monitor %eax,%ecx,%edx"  */
16405   if (!intel_syntax)
16406     {
16407       const char **op1_names;
16408       const char **names = (address_mode == mode_64bit
16409                             ? names64 : names32);
16410
16411       if (!(prefixes & PREFIX_ADDR))
16412         op1_names = (address_mode == mode_16bit
16413                      ? names16 : names);
16414       else
16415         {
16416           /* Remove "addr16/addr32".  */
16417           all_prefixes[last_addr_prefix] = 0;
16418           op1_names = (address_mode != mode_32bit
16419                        ? names32 : names16);
16420           used_prefixes |= PREFIX_ADDR;
16421         }
16422       strcpy (op_out[0], op1_names[0]);
16423       strcpy (op_out[1], names[1]);
16424       strcpy (op_out[2], names[2]);
16425       two_source_ops = 1;
16426     }
16427   /* Skip mod/rm byte.  */
16428   MODRM_CHECK;
16429   codep++;
16430 }
16431
16432 static void
16433 BadOp (void)
16434 {
16435   /* Throw away prefixes and 1st. opcode byte.  */
16436   codep = insn_codep + 1;
16437   oappend ("(bad)");
16438 }
16439
16440 static void
16441 REP_Fixup (int bytemode, int sizeflag)
16442 {
16443   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16444      lods and stos.  */
16445   if (prefixes & PREFIX_REPZ)
16446     all_prefixes[last_repz_prefix] = REP_PREFIX;
16447
16448   switch (bytemode)
16449     {
16450     case al_reg:
16451     case eAX_reg:
16452     case indir_dx_reg:
16453       OP_IMREG (bytemode, sizeflag);
16454       break;
16455     case eDI_reg:
16456       OP_ESreg (bytemode, sizeflag);
16457       break;
16458     case eSI_reg:
16459       OP_DSreg (bytemode, sizeflag);
16460       break;
16461     default:
16462       abort ();
16463       break;
16464     }
16465 }
16466
16467 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16468    "bnd".  */
16469
16470 static void
16471 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16472 {
16473   if (prefixes & PREFIX_REPNZ)
16474     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16475 }
16476
16477 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16478    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16479  */
16480
16481 static void
16482 HLE_Fixup1 (int bytemode, int sizeflag)
16483 {
16484   if (modrm.mod != 3
16485       && (prefixes & PREFIX_LOCK) != 0)
16486     {
16487       if (prefixes & PREFIX_REPZ)
16488         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16489       if (prefixes & PREFIX_REPNZ)
16490         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16491     }
16492
16493   OP_E (bytemode, sizeflag);
16494 }
16495
16496 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16497    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16498  */
16499
16500 static void
16501 HLE_Fixup2 (int bytemode, int sizeflag)
16502 {
16503   if (modrm.mod != 3)
16504     {
16505       if (prefixes & PREFIX_REPZ)
16506         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16507       if (prefixes & PREFIX_REPNZ)
16508         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16509     }
16510
16511   OP_E (bytemode, sizeflag);
16512 }
16513
16514 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16515    "xrelease" for memory operand.  No check for LOCK prefix.   */
16516
16517 static void
16518 HLE_Fixup3 (int bytemode, int sizeflag)
16519 {
16520   if (modrm.mod != 3
16521       && last_repz_prefix > last_repnz_prefix
16522       && (prefixes & PREFIX_REPZ) != 0)
16523     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16524
16525   OP_E (bytemode, sizeflag);
16526 }
16527
16528 static void
16529 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16530 {
16531   USED_REX (REX_W);
16532   if (rex & REX_W)
16533     {
16534       /* Change cmpxchg8b to cmpxchg16b.  */
16535       char *p = mnemonicendp - 2;
16536       mnemonicendp = stpcpy (p, "16b");
16537       bytemode = o_mode;
16538     }
16539   else if ((prefixes & PREFIX_LOCK) != 0)
16540     {
16541       if (prefixes & PREFIX_REPZ)
16542         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16543       if (prefixes & PREFIX_REPNZ)
16544         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16545     }
16546
16547   OP_M (bytemode, sizeflag);
16548 }
16549
16550 static void
16551 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16552 {
16553   const char **names;
16554
16555   if (need_vex)
16556     {
16557       switch (vex.length)
16558         {
16559         case 128:
16560           names = names_xmm;
16561           break;
16562         case 256:
16563           names = names_ymm;
16564           break;
16565         default:
16566           abort ();
16567         }
16568     }
16569   else
16570     names = names_xmm;
16571   oappend (names[reg]);
16572 }
16573
16574 static void
16575 CRC32_Fixup (int bytemode, int sizeflag)
16576 {
16577   /* Add proper suffix to "crc32".  */
16578   char *p = mnemonicendp;
16579
16580   switch (bytemode)
16581     {
16582     case b_mode:
16583       if (intel_syntax)
16584         goto skip;
16585
16586       *p++ = 'b';
16587       break;
16588     case v_mode:
16589       if (intel_syntax)
16590         goto skip;
16591
16592       USED_REX (REX_W);
16593       if (rex & REX_W)
16594         *p++ = 'q';
16595       else
16596         {
16597           if (sizeflag & DFLAG)
16598             *p++ = 'l';
16599           else
16600             *p++ = 'w';
16601           used_prefixes |= (prefixes & PREFIX_DATA);
16602         }
16603       break;
16604     default:
16605       oappend (INTERNAL_DISASSEMBLER_ERROR);
16606       break;
16607     }
16608   mnemonicendp = p;
16609   *p = '\0';
16610
16611 skip:
16612   if (modrm.mod == 3)
16613     {
16614       int add;
16615
16616       /* Skip mod/rm byte.  */
16617       MODRM_CHECK;
16618       codep++;
16619
16620       USED_REX (REX_B);
16621       add = (rex & REX_B) ? 8 : 0;
16622       if (bytemode == b_mode)
16623         {
16624           USED_REX (0);
16625           if (rex)
16626             oappend (names8rex[modrm.rm + add]);
16627           else
16628             oappend (names8[modrm.rm + add]);
16629         }
16630       else
16631         {
16632           USED_REX (REX_W);
16633           if (rex & REX_W)
16634             oappend (names64[modrm.rm + add]);
16635           else if ((prefixes & PREFIX_DATA))
16636             oappend (names16[modrm.rm + add]);
16637           else
16638             oappend (names32[modrm.rm + add]);
16639         }
16640     }
16641   else
16642     OP_E (bytemode, sizeflag);
16643 }
16644
16645 static void
16646 FXSAVE_Fixup (int bytemode, int sizeflag)
16647 {
16648   /* Add proper suffix to "fxsave" and "fxrstor".  */
16649   USED_REX (REX_W);
16650   if (rex & REX_W)
16651     {
16652       char *p = mnemonicendp;
16653       *p++ = '6';
16654       *p++ = '4';
16655       *p = '\0';
16656       mnemonicendp = p;
16657     }
16658   OP_M (bytemode, sizeflag);
16659 }
16660
16661 /* Display the destination register operand for instructions with
16662    VEX. */
16663
16664 static void
16665 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16666 {
16667   int reg;
16668   const char **names;
16669
16670   if (!need_vex)
16671     abort ();
16672
16673   if (!need_vex_reg)
16674     return;
16675
16676   reg = vex.register_specifier;
16677   if (vex.evex)
16678     {
16679       if (!vex.v)
16680         reg += 16;
16681     }
16682
16683   if (bytemode == vex_scalar_mode)
16684     {
16685       oappend (names_xmm[reg]);
16686       return;
16687     }
16688
16689   switch (vex.length)
16690     {
16691     case 128:
16692       switch (bytemode)
16693         {
16694         case vex_mode:
16695         case vex128_mode:
16696         case vex_vsib_q_w_dq_mode:
16697         case vex_vsib_q_w_d_mode:
16698           names = names_xmm;
16699           break;
16700         case dq_mode:
16701           if (vex.w)
16702             names = names64;
16703           else
16704             names = names32;
16705           break;
16706         case mask_bd_mode:
16707         case mask_mode:
16708           names = names_mask;
16709           break;
16710         default:
16711           abort ();
16712           return;
16713         }
16714       break;
16715     case 256:
16716       switch (bytemode)
16717         {
16718         case vex_mode:
16719         case vex256_mode:
16720           names = names_ymm;
16721           break;
16722         case vex_vsib_q_w_dq_mode:
16723         case vex_vsib_q_w_d_mode:
16724           names = vex.w ? names_ymm : names_xmm;
16725           break;
16726         case mask_bd_mode:
16727         case mask_mode:
16728           names = names_mask;
16729           break;
16730         default:
16731           abort ();
16732           return;
16733         }
16734       break;
16735     case 512:
16736       names = names_zmm;
16737       break;
16738     default:
16739       abort ();
16740       break;
16741     }
16742   oappend (names[reg]);
16743 }
16744
16745 /* Get the VEX immediate byte without moving codep.  */
16746
16747 static unsigned char
16748 get_vex_imm8 (int sizeflag, int opnum)
16749 {
16750   int bytes_before_imm = 0;
16751
16752   if (modrm.mod != 3)
16753     {
16754       /* There are SIB/displacement bytes.  */
16755       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16756         {
16757           /* 32/64 bit address mode */
16758           int base = modrm.rm;
16759
16760           /* Check SIB byte.  */
16761           if (base == 4)
16762             {
16763               FETCH_DATA (the_info, codep + 1);
16764               base = *codep & 7;
16765               /* When decoding the third source, don't increase
16766                  bytes_before_imm as this has already been incremented
16767                  by one in OP_E_memory while decoding the second
16768                  source operand.  */
16769               if (opnum == 0)
16770                 bytes_before_imm++;
16771             }
16772
16773           /* Don't increase bytes_before_imm when decoding the third source,
16774              it has already been incremented by OP_E_memory while decoding
16775              the second source operand.  */
16776           if (opnum == 0)
16777             {
16778               switch (modrm.mod)
16779                 {
16780                   case 0:
16781                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16782                        SIB == 5, there is a 4 byte displacement.  */
16783                     if (base != 5)
16784                       /* No displacement. */
16785                       break;
16786                   case 2:
16787                     /* 4 byte displacement.  */
16788                     bytes_before_imm += 4;
16789                     break;
16790                   case 1:
16791                     /* 1 byte displacement.  */
16792                     bytes_before_imm++;
16793                     break;
16794                 }
16795             }
16796         }
16797       else
16798         {
16799           /* 16 bit address mode */
16800           /* Don't increase bytes_before_imm when decoding the third source,
16801              it has already been incremented by OP_E_memory while decoding
16802              the second source operand.  */
16803           if (opnum == 0)
16804             {
16805               switch (modrm.mod)
16806                 {
16807                 case 0:
16808                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16809                   if (modrm.rm != 6)
16810                     /* No displacement. */
16811                     break;
16812                 case 2:
16813                   /* 2 byte displacement.  */
16814                   bytes_before_imm += 2;
16815                   break;
16816                 case 1:
16817                   /* 1 byte displacement: when decoding the third source,
16818                      don't increase bytes_before_imm as this has already
16819                      been incremented by one in OP_E_memory while decoding
16820                      the second source operand.  */
16821                   if (opnum == 0)
16822                     bytes_before_imm++;
16823
16824                   break;
16825                 }
16826             }
16827         }
16828     }
16829
16830   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16831   return codep [bytes_before_imm];
16832 }
16833
16834 static void
16835 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16836 {
16837   const char **names;
16838
16839   if (reg == -1 && modrm.mod != 3)
16840     {
16841       OP_E_memory (bytemode, sizeflag);
16842       return;
16843     }
16844   else
16845     {
16846       if (reg == -1)
16847         {
16848           reg = modrm.rm;
16849           USED_REX (REX_B);
16850           if (rex & REX_B)
16851             reg += 8;
16852         }
16853       else if (reg > 7 && address_mode != mode_64bit)
16854         BadOp ();
16855     }
16856
16857   switch (vex.length)
16858     {
16859     case 128:
16860       names = names_xmm;
16861       break;
16862     case 256:
16863       names = names_ymm;
16864       break;
16865     default:
16866       abort ();
16867     }
16868   oappend (names[reg]);
16869 }
16870
16871 static void
16872 OP_EX_VexImmW (int bytemode, int sizeflag)
16873 {
16874   int reg = -1;
16875   static unsigned char vex_imm8;
16876
16877   if (vex_w_done == 0)
16878     {
16879       vex_w_done = 1;
16880
16881       /* Skip mod/rm byte.  */
16882       MODRM_CHECK;
16883       codep++;
16884
16885       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16886
16887       if (vex.w)
16888           reg = vex_imm8 >> 4;
16889
16890       OP_EX_VexReg (bytemode, sizeflag, reg);
16891     }
16892   else if (vex_w_done == 1)
16893     {
16894       vex_w_done = 2;
16895
16896       if (!vex.w)
16897           reg = vex_imm8 >> 4;
16898
16899       OP_EX_VexReg (bytemode, sizeflag, reg);
16900     }
16901   else
16902     {
16903       /* Output the imm8 directly.  */
16904       scratchbuf[0] = '$';
16905       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16906       oappend_maybe_intel (scratchbuf);
16907       scratchbuf[0] = '\0';
16908       codep++;
16909     }
16910 }
16911
16912 static void
16913 OP_Vex_2src (int bytemode, int sizeflag)
16914 {
16915   if (modrm.mod == 3)
16916     {
16917       int reg = modrm.rm;
16918       USED_REX (REX_B);
16919       if (rex & REX_B)
16920         reg += 8;
16921       oappend (names_xmm[reg]);
16922     }
16923   else
16924     {
16925       if (intel_syntax
16926           && (bytemode == v_mode || bytemode == v_swap_mode))
16927         {
16928           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16929           used_prefixes |= (prefixes & PREFIX_DATA);
16930         }
16931       OP_E (bytemode, sizeflag);
16932     }
16933 }
16934
16935 static void
16936 OP_Vex_2src_1 (int bytemode, int sizeflag)
16937 {
16938   if (modrm.mod == 3)
16939     {
16940       /* Skip mod/rm byte.   */
16941       MODRM_CHECK;
16942       codep++;
16943     }
16944
16945   if (vex.w)
16946     oappend (names_xmm[vex.register_specifier]);
16947   else
16948     OP_Vex_2src (bytemode, sizeflag);
16949 }
16950
16951 static void
16952 OP_Vex_2src_2 (int bytemode, int sizeflag)
16953 {
16954   if (vex.w)
16955     OP_Vex_2src (bytemode, sizeflag);
16956   else
16957     oappend (names_xmm[vex.register_specifier]);
16958 }
16959
16960 static void
16961 OP_EX_VexW (int bytemode, int sizeflag)
16962 {
16963   int reg = -1;
16964
16965   if (!vex_w_done)
16966     {
16967       vex_w_done = 1;
16968
16969       /* Skip mod/rm byte.  */
16970       MODRM_CHECK;
16971       codep++;
16972
16973       if (vex.w)
16974         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16975     }
16976   else
16977     {
16978       if (!vex.w)
16979         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16980     }
16981
16982   OP_EX_VexReg (bytemode, sizeflag, reg);
16983 }
16984
16985 static void
16986 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16987              int sizeflag ATTRIBUTE_UNUSED)
16988 {
16989   /* Skip the immediate byte and check for invalid bits.  */
16990   FETCH_DATA (the_info, codep + 1);
16991   if (*codep++ & 0xf)
16992     BadOp ();
16993 }
16994
16995 static void
16996 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16997 {
16998   int reg;
16999   const char **names;
17000
17001   FETCH_DATA (the_info, codep + 1);
17002   reg = *codep++;
17003
17004   if (bytemode != x_mode)
17005     abort ();
17006
17007   if (reg & 0xf)
17008       BadOp ();
17009
17010   reg >>= 4;
17011   if (reg > 7 && address_mode != mode_64bit)
17012     BadOp ();
17013
17014   switch (vex.length)
17015     {
17016     case 128:
17017       names = names_xmm;
17018       break;
17019     case 256:
17020       names = names_ymm;
17021       break;
17022     default:
17023       abort ();
17024     }
17025   oappend (names[reg]);
17026 }
17027
17028 static void
17029 OP_XMM_VexW (int bytemode, int sizeflag)
17030 {
17031   /* Turn off the REX.W bit since it is used for swapping operands
17032      now.  */
17033   rex &= ~REX_W;
17034   OP_XMM (bytemode, sizeflag);
17035 }
17036
17037 static void
17038 OP_EX_Vex (int bytemode, int sizeflag)
17039 {
17040   if (modrm.mod != 3)
17041     {
17042       if (vex.register_specifier != 0)
17043         BadOp ();
17044       need_vex_reg = 0;
17045     }
17046   OP_EX (bytemode, sizeflag);
17047 }
17048
17049 static void
17050 OP_XMM_Vex (int bytemode, int sizeflag)
17051 {
17052   if (modrm.mod != 3)
17053     {
17054       if (vex.register_specifier != 0)
17055         BadOp ();
17056       need_vex_reg = 0;
17057     }
17058   OP_XMM (bytemode, sizeflag);
17059 }
17060
17061 static void
17062 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17063 {
17064   switch (vex.length)
17065     {
17066     case 128:
17067       mnemonicendp = stpcpy (obuf, "vzeroupper");
17068       break;
17069     case 256:
17070       mnemonicendp = stpcpy (obuf, "vzeroall");
17071       break;
17072     default:
17073       abort ();
17074     }
17075 }
17076
17077 static struct op vex_cmp_op[] =
17078 {
17079   { STRING_COMMA_LEN ("eq") },
17080   { STRING_COMMA_LEN ("lt") },
17081   { STRING_COMMA_LEN ("le") },
17082   { STRING_COMMA_LEN ("unord") },
17083   { STRING_COMMA_LEN ("neq") },
17084   { STRING_COMMA_LEN ("nlt") },
17085   { STRING_COMMA_LEN ("nle") },
17086   { STRING_COMMA_LEN ("ord") },
17087   { STRING_COMMA_LEN ("eq_uq") },
17088   { STRING_COMMA_LEN ("nge") },
17089   { STRING_COMMA_LEN ("ngt") },
17090   { STRING_COMMA_LEN ("false") },
17091   { STRING_COMMA_LEN ("neq_oq") },
17092   { STRING_COMMA_LEN ("ge") },
17093   { STRING_COMMA_LEN ("gt") },
17094   { STRING_COMMA_LEN ("true") },
17095   { STRING_COMMA_LEN ("eq_os") },
17096   { STRING_COMMA_LEN ("lt_oq") },
17097   { STRING_COMMA_LEN ("le_oq") },
17098   { STRING_COMMA_LEN ("unord_s") },
17099   { STRING_COMMA_LEN ("neq_us") },
17100   { STRING_COMMA_LEN ("nlt_uq") },
17101   { STRING_COMMA_LEN ("nle_uq") },
17102   { STRING_COMMA_LEN ("ord_s") },
17103   { STRING_COMMA_LEN ("eq_us") },
17104   { STRING_COMMA_LEN ("nge_uq") },
17105   { STRING_COMMA_LEN ("ngt_uq") },
17106   { STRING_COMMA_LEN ("false_os") },
17107   { STRING_COMMA_LEN ("neq_os") },
17108   { STRING_COMMA_LEN ("ge_oq") },
17109   { STRING_COMMA_LEN ("gt_oq") },
17110   { STRING_COMMA_LEN ("true_us") },
17111 };
17112
17113 static void
17114 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17115 {
17116   unsigned int cmp_type;
17117
17118   FETCH_DATA (the_info, codep + 1);
17119   cmp_type = *codep++ & 0xff;
17120   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17121     {
17122       char suffix [3];
17123       char *p = mnemonicendp - 2;
17124       suffix[0] = p[0];
17125       suffix[1] = p[1];
17126       suffix[2] = '\0';
17127       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17128       mnemonicendp += vex_cmp_op[cmp_type].len;
17129     }
17130   else
17131     {
17132       /* We have a reserved extension byte.  Output it directly.  */
17133       scratchbuf[0] = '$';
17134       print_operand_value (scratchbuf + 1, 1, cmp_type);
17135       oappend_maybe_intel (scratchbuf);
17136       scratchbuf[0] = '\0';
17137     }
17138 }
17139
17140 static void
17141 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17142              int sizeflag ATTRIBUTE_UNUSED)
17143 {
17144   unsigned int cmp_type;
17145
17146   if (!vex.evex)
17147     abort ();
17148
17149   FETCH_DATA (the_info, codep + 1);
17150   cmp_type = *codep++ & 0xff;
17151   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17152      If it's the case, print suffix, otherwise - print the immediate.  */
17153   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17154       && cmp_type != 3
17155       && cmp_type != 7)
17156     {
17157       char suffix [3];
17158       char *p = mnemonicendp - 2;
17159
17160       /* vpcmp* can have both one- and two-lettered suffix.  */
17161       if (p[0] == 'p')
17162         {
17163           p++;
17164           suffix[0] = p[0];
17165           suffix[1] = '\0';
17166         }
17167       else
17168         {
17169           suffix[0] = p[0];
17170           suffix[1] = p[1];
17171           suffix[2] = '\0';
17172         }
17173
17174       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17175       mnemonicendp += simd_cmp_op[cmp_type].len;
17176     }
17177   else
17178     {
17179       /* We have a reserved extension byte.  Output it directly.  */
17180       scratchbuf[0] = '$';
17181       print_operand_value (scratchbuf + 1, 1, cmp_type);
17182       oappend_maybe_intel (scratchbuf);
17183       scratchbuf[0] = '\0';
17184     }
17185 }
17186
17187 static const struct op pclmul_op[] =
17188 {
17189   { STRING_COMMA_LEN ("lql") },
17190   { STRING_COMMA_LEN ("hql") },
17191   { STRING_COMMA_LEN ("lqh") },
17192   { STRING_COMMA_LEN ("hqh") }
17193 };
17194
17195 static void
17196 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17197               int sizeflag ATTRIBUTE_UNUSED)
17198 {
17199   unsigned int pclmul_type;
17200
17201   FETCH_DATA (the_info, codep + 1);
17202   pclmul_type = *codep++ & 0xff;
17203   switch (pclmul_type)
17204     {
17205     case 0x10:
17206       pclmul_type = 2;
17207       break;
17208     case 0x11:
17209       pclmul_type = 3;
17210       break;
17211     default:
17212       break;
17213     }
17214   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17215     {
17216       char suffix [4];
17217       char *p = mnemonicendp - 3;
17218       suffix[0] = p[0];
17219       suffix[1] = p[1];
17220       suffix[2] = p[2];
17221       suffix[3] = '\0';
17222       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17223       mnemonicendp += pclmul_op[pclmul_type].len;
17224     }
17225   else
17226     {
17227       /* We have a reserved extension byte.  Output it directly.  */
17228       scratchbuf[0] = '$';
17229       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17230       oappend_maybe_intel (scratchbuf);
17231       scratchbuf[0] = '\0';
17232     }
17233 }
17234
17235 static void
17236 MOVBE_Fixup (int bytemode, int sizeflag)
17237 {
17238   /* Add proper suffix to "movbe".  */
17239   char *p = mnemonicendp;
17240
17241   switch (bytemode)
17242     {
17243     case v_mode:
17244       if (intel_syntax)
17245         goto skip;
17246
17247       USED_REX (REX_W);
17248       if (sizeflag & SUFFIX_ALWAYS)
17249         {
17250           if (rex & REX_W)
17251             *p++ = 'q';
17252           else
17253             {
17254               if (sizeflag & DFLAG)
17255                 *p++ = 'l';
17256               else
17257                 *p++ = 'w';
17258               used_prefixes |= (prefixes & PREFIX_DATA);
17259             }
17260         }
17261       break;
17262     default:
17263       oappend (INTERNAL_DISASSEMBLER_ERROR);
17264       break;
17265     }
17266   mnemonicendp = p;
17267   *p = '\0';
17268
17269 skip:
17270   OP_M (bytemode, sizeflag);
17271 }
17272
17273 static void
17274 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17275 {
17276   int reg;
17277   const char **names;
17278
17279   /* Skip mod/rm byte.  */
17280   MODRM_CHECK;
17281   codep++;
17282
17283   if (vex.w)
17284     names = names64;
17285   else
17286     names = names32;
17287
17288   reg = modrm.rm;
17289   USED_REX (REX_B);
17290   if (rex & REX_B)
17291     reg += 8;
17292
17293   oappend (names[reg]);
17294 }
17295
17296 static void
17297 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17298 {
17299   const char **names;
17300
17301   if (vex.w)
17302     names = names64;
17303   else
17304     names = names32;
17305
17306   oappend (names[vex.register_specifier]);
17307 }
17308
17309 static void
17310 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17311 {
17312   if (!vex.evex
17313       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17314     abort ();
17315
17316   USED_REX (REX_R);
17317   if ((rex & REX_R) != 0 || !vex.r)
17318     {
17319       BadOp ();
17320       return;
17321     }
17322
17323   oappend (names_mask [modrm.reg]);
17324 }
17325
17326 static void
17327 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17328 {
17329   if (!vex.evex
17330       || (bytemode != evex_rounding_mode
17331           && bytemode != evex_sae_mode))
17332     abort ();
17333   if (modrm.mod == 3 && vex.b)
17334     switch (bytemode)
17335       {
17336       case evex_rounding_mode:
17337         oappend (names_rounding[vex.ll]);
17338         break;
17339       case evex_sae_mode:
17340         oappend ("{sae}");
17341         break;
17342       default:
17343         break;
17344       }
17345 }