opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127 static void MOVSXD_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Eva { OP_E, va_mode }
 254 #define Ev_bnd { OP_E, v_bnd_mode }
 255 #define EvS { OP_E, v_swap_mode }
 256 #define Ed { OP_E, d_mode }
 257 #define Edq { OP_E, dq_mode }
 258 #define Edqw { OP_E, dqw_mode }
 259 #define Edqb { OP_E, dqb_mode }
 260 #define Edb { OP_E, db_mode }
 261 #define Edw { OP_E, dw_mode }
 262 #define Edqd { OP_E, dqd_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iv64 { OP_I64, v_mode }
 296 #define Id { OP_I, d_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Jdqw { OP_J, dqw_mode }
 302 #define Cm { OP_C, m_mode }
 303 #define Dm { OP_D, m_mode }
 304 #define Td { OP_T, d_mode }
 305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 306
 307 #define RMeAX { OP_REG, eAX_reg }
 308 #define RMeBX { OP_REG, eBX_reg }
 309 #define RMeCX { OP_REG, eCX_reg }
 310 #define RMeDX { OP_REG, eDX_reg }
 311 #define RMeSP { OP_REG, eSP_reg }
 312 #define RMeBP { OP_REG, eBP_reg }
 313 #define RMeSI { OP_REG, eSI_reg }
 314 #define RMeDI { OP_REG, eDI_reg }
 315 #define RMrAX { OP_REG, rAX_reg }
 316 #define RMrBX { OP_REG, rBX_reg }
 317 #define RMrCX { OP_REG, rCX_reg }
 318 #define RMrDX { OP_REG, rDX_reg }
 319 #define RMrSP { OP_REG, rSP_reg }
 320 #define RMrBP { OP_REG, rBP_reg }
 321 #define RMrSI { OP_REG, rSI_reg }
 322 #define RMrDI { OP_REG, rDI_reg }
 323 #define RMAL { OP_REG, al_reg }
 324 #define RMCL { OP_REG, cl_reg }
 325 #define RMDL { OP_REG, dl_reg }
 326 #define RMBL { OP_REG, bl_reg }
 327 #define RMAH { OP_REG, ah_reg }
 328 #define RMCH { OP_REG, ch_reg }
 329 #define RMDH { OP_REG, dh_reg }
 330 #define RMBH { OP_REG, bh_reg }
 331 #define RMAX { OP_REG, ax_reg }
 332 #define RMDX { OP_REG, dx_reg }
 333
 334 #define eAX { OP_IMREG, eAX_reg }
 335 #define eBX { OP_IMREG, eBX_reg }
 336 #define eCX { OP_IMREG, eCX_reg }
 337 #define eDX { OP_IMREG, eDX_reg }
 338 #define eSP { OP_IMREG, eSP_reg }
 339 #define eBP { OP_IMREG, eBP_reg }
 340 #define eSI { OP_IMREG, eSI_reg }
 341 #define eDI { OP_IMREG, eDI_reg }
 342 #define AL { OP_IMREG, al_reg }
 343 #define CL { OP_IMREG, cl_reg }
 344 #define DL { OP_IMREG, dl_reg }
 345 #define BL { OP_IMREG, bl_reg }
 346 #define AH { OP_IMREG, ah_reg }
 347 #define CH { OP_IMREG, ch_reg }
 348 #define DH { OP_IMREG, dh_reg }
 349 #define BH { OP_IMREG, bh_reg }
 350 #define AX { OP_IMREG, ax_reg }
 351 #define DX { OP_IMREG, dx_reg }
 352 #define zAX { OP_IMREG, z_mode_ax_reg }
 353 #define indirDX { OP_IMREG, indir_dx_reg }
 354
 355 #define Sw { OP_SEG, w_mode }
 356 #define Sv { OP_SEG, v_mode }
 357 #define Ap { OP_DIR, 0 }
 358 #define Ob { OP_OFF64, b_mode }
 359 #define Ov { OP_OFF64, v_mode }
 360 #define Xb { OP_DSreg, eSI_reg }
 361 #define Xv { OP_DSreg, eSI_reg }
 362 #define Xz { OP_DSreg, eSI_reg }
 363 #define Yb { OP_ESreg, eDI_reg }
 364 #define Yv { OP_ESreg, eDI_reg }
 365 #define DSBX { OP_DSreg, eBX_reg }
 366
 367 #define es { OP_REG, es_reg }
 368 #define ss { OP_REG, ss_reg }
 369 #define cs { OP_REG, cs_reg }
 370 #define ds { OP_REG, ds_reg }
 371 #define fs { OP_REG, fs_reg }
 372 #define gs { OP_REG, gs_reg }
 373
 374 #define MX { OP_MMX, 0 }
 375 #define XM { OP_XMM, 0 }
 376 #define XMScalar { OP_XMM, scalar_mode }
 377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 378 #define XMM { OP_XMM, xmm_mode }
 379 #define XMxmmq { OP_XMM, xmmq_mode }
 380 #define EM { OP_EM, v_mode }
 381 #define EMS { OP_EM, v_swap_mode }
 382 #define EMd { OP_EM, d_mode }
 383 #define EMx { OP_EM, x_mode }
 384 #define EXbScalar { OP_EX, b_scalar_mode }
 385 #define EXw { OP_EX, w_mode }
 386 #define EXwScalar { OP_EX, w_scalar_mode }
 387 #define EXd { OP_EX, d_mode }
 388 #define EXdScalar { OP_EX, d_scalar_mode }
 389 #define EXdS { OP_EX, d_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmmdw { OP_EX, xmmdw_mode }
 405 #define EXxmmqd { OP_EX, xmmqd_mode }
 406 #define EXymmq { OP_EX, ymmq_mode }
 407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 410 #define MS { OP_MS, v_mode }
 411 #define XS { OP_XS, v_mode }
 412 #define EMCq { OP_EMC, q_mode }
 413 #define MXC { OP_MXC, 0 }
 414 #define OPSUF { OP_3DNowSuffix, 0 }
 415 #define SEP { SEP_Fixup, 0 }
 416 #define CMP { CMP_Fixup, 0 }
 417 #define XMM0 { XMM_Fixup, 0 }
 418 #define FXSAVE { FXSAVE_Fixup, 0 }
 419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 421
 422 #define Vex { OP_VEX, vex_mode }
 423 #define VexScalar { OP_VEX, vex_scalar_mode }
 424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 425 #define Vex128 { OP_VEX, vex128_mode }
 426 #define Vex256 { OP_VEX, vex256_mode }
 427 #define VexGdq { OP_VEX, dq_mode }
 428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 430 #define EXVexW { OP_EX_VexW, x_mode }
 431 #define EXdVexW { OP_EX_VexW, d_mode }
 432 #define EXqVexW { OP_EX_VexW, q_mode }
 433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440 #define VPCOM { VPCOM_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 445
 446 #define XMask { OP_Mask, mask_mode }
 447 #define MaskG { OP_G, mask_mode }
 448 #define MaskE { OP_E, mask_mode }
 449 #define MaskBDE { OP_E, mask_bd_mode }
 450 #define MaskR { OP_R, mask_mode }
 451 #define MaskVex { OP_VEX, mask_mode }
 452
 453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 457
 458 /* Used handle "rep" prefix for string instructions.  */
 459 #define Xbr { REP_Fixup, eSI_reg }
 460 #define Xvr { REP_Fixup, eSI_reg }
 461 #define Ybr { REP_Fixup, eDI_reg }
 462 #define Yvr { REP_Fixup, eDI_reg }
 463 #define Yzr { REP_Fixup, eDI_reg }
 464 #define indirDXr { REP_Fixup, indir_dx_reg }
 465 #define ALr { REP_Fixup, al_reg }
 466 #define eAXr { REP_Fixup, eAX_reg }
 467
 468 /* Used handle HLE prefix for lockable instructions.  */
 469 #define Ebh1 { HLE_Fixup1, b_mode }
 470 #define Evh1 { HLE_Fixup1, v_mode }
 471 #define Ebh2 { HLE_Fixup2, b_mode }
 472 #define Evh2 { HLE_Fixup2, v_mode }
 473 #define Ebh3 { HLE_Fixup3, b_mode }
 474 #define Evh3 { HLE_Fixup3, v_mode }
 475
 476 #define BND { BND_Fixup, 0 }
 477 #define NOTRACK { NOTRACK_Fixup, 0 }
 478
 479 #define cond_jump_flag { NULL, cond_jump_mode }
 480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 481
 482 /* bits in sizeflag */
 483 #define SUFFIX_ALWAYS 4
 484 #define AFLAG 2
 485 #define DFLAG 1
 486
 487 enum
 488 {
 489   /* byte operand */
 490   b_mode = 1,
 491   /* byte operand with operand swapped */
 492   b_swap_mode,
 493   /* byte operand, sign extend like 'T' suffix */
 494   b_T_mode,
 495   /* operand size depends on prefixes */
 496   v_mode,
 497   /* operand size depends on prefixes with operand swapped */
 498   v_swap_mode,
 499   /* operand size depends on address prefix */
 500   va_mode,
 501   /* word operand */
 502   w_mode,
 503   /* double word operand  */
 504   d_mode,
 505   /* double word operand with operand swapped */
 506   d_swap_mode,
 507   /* quad word operand */
 508   q_mode,
 509   /* quad word operand with operand swapped */
 510   q_swap_mode,
 511   /* ten-byte operand */
 512   t_mode,
 513   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 514      broadcast enabled.  */
 515   x_mode,
 516   /* Similar to x_mode, but with different EVEX mem shifts.  */
 517   evex_x_gscat_mode,
 518   /* Similar to x_mode, but with disabled broadcast.  */
 519   evex_x_nobcst_mode,
 520   /* Similar to x_mode, but with operands swapped and disabled broadcast
 521      in EVEX.  */
 522   x_swap_mode,
 523   /* 16-byte XMM operand */
 524   xmm_mode,
 525   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 526      memory operand (depending on vector length).  Broadcast isn't
 527      allowed.  */
 528   xmmq_mode,
 529   /* Same as xmmq_mode, but broadcast is allowed.  */
 530   evex_half_bcst_xmmq_mode,
 531   /* XMM register or byte memory operand */
 532   xmm_mb_mode,
 533   /* XMM register or word memory operand */
 534   xmm_mw_mode,
 535   /* XMM register or double word memory operand */
 536   xmm_md_mode,
 537   /* XMM register or quad word memory operand */
 538   xmm_mq_mode,
 539   /* 16-byte XMM, word, double word or quad word operand.  */
 540   xmmdw_mode,
 541   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 542   xmmqd_mode,
 543   /* 32-byte YMM operand */
 544   ymm_mode,
 545   /* quad word, ymmword or zmmword memory operand.  */
 546   ymmq_mode,
 547   /* 32-byte YMM or 16-byte word operand */
 548   ymmxmm_mode,
 549   /* d_mode in 32bit, q_mode in 64bit mode.  */
 550   m_mode,
 551   /* pair of v_mode operands */
 552   a_mode,
 553   cond_jump_mode,
 554   loop_jcxz_mode,
 555   movsxd_mode,
 556   v_bnd_mode,
 557   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 558   v_bndmk_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode, displacements like
 562      v_mode without considering Intel64 ISA.  */
 563   dqw_mode,
 564   /* bounds operand */
 565   bnd_mode,
 566   /* bounds operand with operand swapped */
 567   bnd_swap_mode,
 568   /* 4- or 6-byte pointer operand */
 569   f_mode,
 570   const_1_mode,
 571   /* v_mode for indirect branch opcodes.  */
 572   indir_v_mode,
 573   /* v_mode for stack-related opcodes.  */
 574   stack_v_mode,
 575   /* non-quad operand size depends on prefixes */
 576   z_mode,
 577   /* 16-byte operand */
 578   o_mode,
 579   /* registers like dq_mode, memory like b_mode.  */
 580   dqb_mode,
 581   /* registers like d_mode, memory like b_mode.  */
 582   db_mode,
 583   /* registers like d_mode, memory like w_mode.  */
 584   dw_mode,
 585   /* registers like dq_mode, memory like d_mode.  */
 586   dqd_mode,
 587   /* normal vex mode */
 588   vex_mode,
 589   /* 128bit vex mode */
 590   vex128_mode,
 591   /* 256bit vex mode */
 592   vex256_mode,
 593
 594   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 595   vex_vsib_d_w_dq_mode,
 596   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 597   vex_vsib_d_w_d_mode,
 598   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 599   vex_vsib_q_w_dq_mode,
 600   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 601   vex_vsib_q_w_d_mode,
 602
 603   /* scalar, ignore vector length.  */
 604   scalar_mode,
 605   /* like b_mode, ignore vector length.  */
 606   b_scalar_mode,
 607   /* like w_mode, ignore vector length.  */
 608   w_scalar_mode,
 609   /* like d_mode, ignore vector length.  */
 610   d_scalar_mode,
 611   /* like d_swap_mode, ignore vector length.  */
 612   d_scalar_swap_mode,
 613   /* like q_mode, ignore vector length.  */
 614   q_scalar_mode,
 615   /* like q_swap_mode, ignore vector length.  */
 616   q_scalar_swap_mode,
 617   /* like vex_mode, ignore vector length.  */
 618   vex_scalar_mode,
 619   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 620   vex_scalar_w_dq_mode,
 621
 622   /* Static rounding.  */
 623   evex_rounding_mode,
 624   /* Static rounding, 64-bit mode only.  */
 625   evex_rounding_64_mode,
 626   /* Supress all exceptions.  */
 627   evex_sae_mode,
 628
 629   /* Mask register operand.  */
 630   mask_mode,
 631   /* Mask register operand.  */
 632   mask_bd_mode,
 633
 634   es_reg,
 635   cs_reg,
 636   ss_reg,
 637   ds_reg,
 638   fs_reg,
 639   gs_reg,
 640
 641   eAX_reg,
 642   eCX_reg,
 643   eDX_reg,
 644   eBX_reg,
 645   eSP_reg,
 646   eBP_reg,
 647   eSI_reg,
 648   eDI_reg,
 649
 650   al_reg,
 651   cl_reg,
 652   dl_reg,
 653   bl_reg,
 654   ah_reg,
 655   ch_reg,
 656   dh_reg,
 657   bh_reg,
 658
 659   ax_reg,
 660   cx_reg,
 661   dx_reg,
 662   bx_reg,
 663   sp_reg,
 664   bp_reg,
 665   si_reg,
 666   di_reg,
 667
 668   rAX_reg,
 669   rCX_reg,
 670   rDX_reg,
 671   rBX_reg,
 672   rSP_reg,
 673   rBP_reg,
 674   rSI_reg,
 675   rDI_reg,
 676
 677   z_mode_ax_reg,
 678   indir_dx_reg
 679 };
 680
 681 enum
 682 {
 683   FLOATCODE = 1,
 684   USE_REG_TABLE,
 685   USE_MOD_TABLE,
 686   USE_RM_TABLE,
 687   USE_PREFIX_TABLE,
 688   USE_X86_64_TABLE,
 689   USE_3BYTE_TABLE,
 690   USE_XOP_8F_TABLE,
 691   USE_VEX_C4_TABLE,
 692   USE_VEX_C5_TABLE,
 693   USE_VEX_LEN_TABLE,
 694   USE_VEX_W_TABLE,
 695   USE_EVEX_TABLE,
 696   USE_EVEX_LEN_TABLE
 697 };
 698
 699 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 700
 701 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 702 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 703 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 704 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 705 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 706 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 707 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 708 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 709 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 710 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 711 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 712 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 713 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 714 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 715 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 716 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 717
 718 enum
 719 {
 720   REG_80 = 0,
 721   REG_81,
 722   REG_83,
 723   REG_8F,
 724   REG_C0,
 725   REG_C1,
 726   REG_C6,
 727   REG_C7,
 728   REG_D0,
 729   REG_D1,
 730   REG_D2,
 731   REG_D3,
 732   REG_F6,
 733   REG_F7,
 734   REG_FE,
 735   REG_FF,
 736   REG_0F00,
 737   REG_0F01,
 738   REG_0F0D,
 739   REG_0F18,
 740   REG_0F1C_P_0_MOD_0,
 741   REG_0F1E_P_1_MOD_3,
 742   REG_0F71,
 743   REG_0F72,
 744   REG_0F73,
 745   REG_0FA6,
 746   REG_0FA7,
 747   REG_0FAE,
 748   REG_0FBA,
 749   REG_0FC7,
 750   REG_VEX_0F71,
 751   REG_VEX_0F72,
 752   REG_VEX_0F73,
 753   REG_VEX_0FAE,
 754   REG_VEX_0F38F3,
 755   REG_XOP_LWPCB,
 756   REG_XOP_LWP,
 757   REG_XOP_TBM_01,
 758   REG_XOP_TBM_02,
 759
 760   REG_EVEX_0F71,
 761   REG_EVEX_0F72,
 762   REG_EVEX_0F73,
 763   REG_EVEX_0F38C6,
 764   REG_EVEX_0F38C7
 765 };
 766
 767 enum
 768 {
 769   MOD_8D = 0,
 770   MOD_C6_REG_7,
 771   MOD_C7_REG_7,
 772   MOD_FF_REG_3,
 773   MOD_FF_REG_5,
 774   MOD_0F01_REG_0,
 775   MOD_0F01_REG_1,
 776   MOD_0F01_REG_2,
 777   MOD_0F01_REG_3,
 778   MOD_0F01_REG_5,
 779   MOD_0F01_REG_7,
 780   MOD_0F12_PREFIX_0,
 781   MOD_0F12_PREFIX_2,
 782   MOD_0F13,
 783   MOD_0F16_PREFIX_0,
 784   MOD_0F16_PREFIX_2,
 785   MOD_0F17,
 786   MOD_0F18_REG_0,
 787   MOD_0F18_REG_1,
 788   MOD_0F18_REG_2,
 789   MOD_0F18_REG_3,
 790   MOD_0F18_REG_4,
 791   MOD_0F18_REG_5,
 792   MOD_0F18_REG_6,
 793   MOD_0F18_REG_7,
 794   MOD_0F1A_PREFIX_0,
 795   MOD_0F1B_PREFIX_0,
 796   MOD_0F1B_PREFIX_1,
 797   MOD_0F1C_PREFIX_0,
 798   MOD_0F1E_PREFIX_1,
 799   MOD_0F24,
 800   MOD_0F26,
 801   MOD_0F2B_PREFIX_0,
 802   MOD_0F2B_PREFIX_1,
 803   MOD_0F2B_PREFIX_2,
 804   MOD_0F2B_PREFIX_3,
 805   MOD_0F50,
 806   MOD_0F71_REG_2,
 807   MOD_0F71_REG_4,
 808   MOD_0F71_REG_6,
 809   MOD_0F72_REG_2,
 810   MOD_0F72_REG_4,
 811   MOD_0F72_REG_6,
 812   MOD_0F73_REG_2,
 813   MOD_0F73_REG_3,
 814   MOD_0F73_REG_6,
 815   MOD_0F73_REG_7,
 816   MOD_0FAE_REG_0,
 817   MOD_0FAE_REG_1,
 818   MOD_0FAE_REG_2,
 819   MOD_0FAE_REG_3,
 820   MOD_0FAE_REG_4,
 821   MOD_0FAE_REG_5,
 822   MOD_0FAE_REG_6,
 823   MOD_0FAE_REG_7,
 824   MOD_0FB2,
 825   MOD_0FB4,
 826   MOD_0FB5,
 827   MOD_0FC3,
 828   MOD_0FC7_REG_3,
 829   MOD_0FC7_REG_4,
 830   MOD_0FC7_REG_5,
 831   MOD_0FC7_REG_6,
 832   MOD_0FC7_REG_7,
 833   MOD_0FD7,
 834   MOD_0FE7_PREFIX_2,
 835   MOD_0FF0_PREFIX_3,
 836   MOD_0F382A_PREFIX_2,
 837   MOD_0F38F5_PREFIX_2,
 838   MOD_0F38F6_PREFIX_0,
 839   MOD_0F38F8_PREFIX_1,
 840   MOD_0F38F8_PREFIX_2,
 841   MOD_0F38F8_PREFIX_3,
 842   MOD_0F38F9_PREFIX_0,
 843   MOD_62_32BIT,
 844   MOD_C4_32BIT,
 845   MOD_C5_32BIT,
 846   MOD_VEX_0F12_PREFIX_0,
 847   MOD_VEX_0F12_PREFIX_2,
 848   MOD_VEX_0F13,
 849   MOD_VEX_0F16_PREFIX_0,
 850   MOD_VEX_0F16_PREFIX_2,
 851   MOD_VEX_0F17,
 852   MOD_VEX_0F2B,
 853   MOD_VEX_W_0_0F41_P_0_LEN_1,
 854   MOD_VEX_W_1_0F41_P_0_LEN_1,
 855   MOD_VEX_W_0_0F41_P_2_LEN_1,
 856   MOD_VEX_W_1_0F41_P_2_LEN_1,
 857   MOD_VEX_W_0_0F42_P_0_LEN_1,
 858   MOD_VEX_W_1_0F42_P_0_LEN_1,
 859   MOD_VEX_W_0_0F42_P_2_LEN_1,
 860   MOD_VEX_W_1_0F42_P_2_LEN_1,
 861   MOD_VEX_W_0_0F44_P_0_LEN_1,
 862   MOD_VEX_W_1_0F44_P_0_LEN_1,
 863   MOD_VEX_W_0_0F44_P_2_LEN_1,
 864   MOD_VEX_W_1_0F44_P_2_LEN_1,
 865   MOD_VEX_W_0_0F45_P_0_LEN_1,
 866   MOD_VEX_W_1_0F45_P_0_LEN_1,
 867   MOD_VEX_W_0_0F45_P_2_LEN_1,
 868   MOD_VEX_W_1_0F45_P_2_LEN_1,
 869   MOD_VEX_W_0_0F46_P_0_LEN_1,
 870   MOD_VEX_W_1_0F46_P_0_LEN_1,
 871   MOD_VEX_W_0_0F46_P_2_LEN_1,
 872   MOD_VEX_W_1_0F46_P_2_LEN_1,
 873   MOD_VEX_W_0_0F47_P_0_LEN_1,
 874   MOD_VEX_W_1_0F47_P_0_LEN_1,
 875   MOD_VEX_W_0_0F47_P_2_LEN_1,
 876   MOD_VEX_W_1_0F47_P_2_LEN_1,
 877   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 878   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 879   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 880   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 881   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 882   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 883   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 884   MOD_VEX_0F50,
 885   MOD_VEX_0F71_REG_2,
 886   MOD_VEX_0F71_REG_4,
 887   MOD_VEX_0F71_REG_6,
 888   MOD_VEX_0F72_REG_2,
 889   MOD_VEX_0F72_REG_4,
 890   MOD_VEX_0F72_REG_6,
 891   MOD_VEX_0F73_REG_2,
 892   MOD_VEX_0F73_REG_3,
 893   MOD_VEX_0F73_REG_6,
 894   MOD_VEX_0F73_REG_7,
 895   MOD_VEX_W_0_0F91_P_0_LEN_0,
 896   MOD_VEX_W_1_0F91_P_0_LEN_0,
 897   MOD_VEX_W_0_0F91_P_2_LEN_0,
 898   MOD_VEX_W_1_0F91_P_2_LEN_0,
 899   MOD_VEX_W_0_0F92_P_0_LEN_0,
 900   MOD_VEX_W_0_0F92_P_2_LEN_0,
 901   MOD_VEX_0F92_P_3_LEN_0,
 902   MOD_VEX_W_0_0F93_P_0_LEN_0,
 903   MOD_VEX_W_0_0F93_P_2_LEN_0,
 904   MOD_VEX_0F93_P_3_LEN_0,
 905   MOD_VEX_W_0_0F98_P_0_LEN_0,
 906   MOD_VEX_W_1_0F98_P_0_LEN_0,
 907   MOD_VEX_W_0_0F98_P_2_LEN_0,
 908   MOD_VEX_W_1_0F98_P_2_LEN_0,
 909   MOD_VEX_W_0_0F99_P_0_LEN_0,
 910   MOD_VEX_W_1_0F99_P_0_LEN_0,
 911   MOD_VEX_W_0_0F99_P_2_LEN_0,
 912   MOD_VEX_W_1_0F99_P_2_LEN_0,
 913   MOD_VEX_0FAE_REG_2,
 914   MOD_VEX_0FAE_REG_3,
 915   MOD_VEX_0FD7_PREFIX_2,
 916   MOD_VEX_0FE7_PREFIX_2,
 917   MOD_VEX_0FF0_PREFIX_3,
 918   MOD_VEX_0F381A_PREFIX_2,
 919   MOD_VEX_0F382A_PREFIX_2,
 920   MOD_VEX_0F382C_PREFIX_2,
 921   MOD_VEX_0F382D_PREFIX_2,
 922   MOD_VEX_0F382E_PREFIX_2,
 923   MOD_VEX_0F382F_PREFIX_2,
 924   MOD_VEX_0F385A_PREFIX_2,
 925   MOD_VEX_0F388C_PREFIX_2,
 926   MOD_VEX_0F388E_PREFIX_2,
 927   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 928   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 929   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 930   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 931   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 932   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 933   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 934   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 935
 936   MOD_EVEX_0F12_PREFIX_0,
 937   MOD_EVEX_0F12_PREFIX_2,
 938   MOD_EVEX_0F13,
 939   MOD_EVEX_0F16_PREFIX_0,
 940   MOD_EVEX_0F16_PREFIX_2,
 941   MOD_EVEX_0F17,
 942   MOD_EVEX_0F2B,
 943   MOD_EVEX_0F38C6_REG_1,
 944   MOD_EVEX_0F38C6_REG_2,
 945   MOD_EVEX_0F38C6_REG_5,
 946   MOD_EVEX_0F38C6_REG_6,
 947   MOD_EVEX_0F38C7_REG_1,
 948   MOD_EVEX_0F38C7_REG_2,
 949   MOD_EVEX_0F38C7_REG_5,
 950   MOD_EVEX_0F38C7_REG_6
 951 };
 952
 953 enum
 954 {
 955   RM_C6_REG_7 = 0,
 956   RM_C7_REG_7,
 957   RM_0F01_REG_0,
 958   RM_0F01_REG_1,
 959   RM_0F01_REG_2,
 960   RM_0F01_REG_3,
 961   RM_0F01_REG_5_MOD_3,
 962   RM_0F01_REG_7_MOD_3,
 963   RM_0F1E_P_1_MOD_3_REG_7,
 964   RM_0FAE_REG_6_MOD_3_P_0,
 965   RM_0FAE_REG_7_MOD_3,
 966 };
 967
 968 enum
 969 {
 970   PREFIX_90 = 0,
 971   PREFIX_0F01_REG_3_RM_1,
 972   PREFIX_0F01_REG_5_MOD_0,
 973   PREFIX_0F01_REG_5_MOD_3_RM_0,
 974   PREFIX_0F01_REG_5_MOD_3_RM_1,
 975   PREFIX_0F01_REG_5_MOD_3_RM_2,
 976   PREFIX_0F01_REG_7_MOD_3_RM_2,
 977   PREFIX_0F01_REG_7_MOD_3_RM_3,
 978   PREFIX_0F09,
 979   PREFIX_0F10,
 980   PREFIX_0F11,
 981   PREFIX_0F12,
 982   PREFIX_0F16,
 983   PREFIX_0F1A,
 984   PREFIX_0F1B,
 985   PREFIX_0F1C,
 986   PREFIX_0F1E,
 987   PREFIX_0F2A,
 988   PREFIX_0F2B,
 989   PREFIX_0F2C,
 990   PREFIX_0F2D,
 991   PREFIX_0F2E,
 992   PREFIX_0F2F,
 993   PREFIX_0F51,
 994   PREFIX_0F52,
 995   PREFIX_0F53,
 996   PREFIX_0F58,
 997   PREFIX_0F59,
 998   PREFIX_0F5A,
 999   PREFIX_0F5B,
1000   PREFIX_0F5C,
1001   PREFIX_0F5D,
1002   PREFIX_0F5E,
1003   PREFIX_0F5F,
1004   PREFIX_0F60,
1005   PREFIX_0F61,
1006   PREFIX_0F62,
1007   PREFIX_0F6C,
1008   PREFIX_0F6D,
1009   PREFIX_0F6F,
1010   PREFIX_0F70,
1011   PREFIX_0F73_REG_3,
1012   PREFIX_0F73_REG_7,
1013   PREFIX_0F78,
1014   PREFIX_0F79,
1015   PREFIX_0F7C,
1016   PREFIX_0F7D,
1017   PREFIX_0F7E,
1018   PREFIX_0F7F,
1019   PREFIX_0FAE_REG_0_MOD_3,
1020   PREFIX_0FAE_REG_1_MOD_3,
1021   PREFIX_0FAE_REG_2_MOD_3,
1022   PREFIX_0FAE_REG_3_MOD_3,
1023   PREFIX_0FAE_REG_4_MOD_0,
1024   PREFIX_0FAE_REG_4_MOD_3,
1025   PREFIX_0FAE_REG_5_MOD_0,
1026   PREFIX_0FAE_REG_5_MOD_3,
1027   PREFIX_0FAE_REG_6_MOD_0,
1028   PREFIX_0FAE_REG_6_MOD_3,
1029   PREFIX_0FAE_REG_7_MOD_0,
1030   PREFIX_0FB8,
1031   PREFIX_0FBC,
1032   PREFIX_0FBD,
1033   PREFIX_0FC2,
1034   PREFIX_0FC3_MOD_0,
1035   PREFIX_0FC7_REG_6_MOD_0,
1036   PREFIX_0FC7_REG_6_MOD_3,
1037   PREFIX_0FC7_REG_7_MOD_3,
1038   PREFIX_0FD0,
1039   PREFIX_0FD6,
1040   PREFIX_0FE6,
1041   PREFIX_0FE7,
1042   PREFIX_0FF0,
1043   PREFIX_0FF7,
1044   PREFIX_0F3810,
1045   PREFIX_0F3814,
1046   PREFIX_0F3815,
1047   PREFIX_0F3817,
1048   PREFIX_0F3820,
1049   PREFIX_0F3821,
1050   PREFIX_0F3822,
1051   PREFIX_0F3823,
1052   PREFIX_0F3824,
1053   PREFIX_0F3825,
1054   PREFIX_0F3828,
1055   PREFIX_0F3829,
1056   PREFIX_0F382A,
1057   PREFIX_0F382B,
1058   PREFIX_0F3830,
1059   PREFIX_0F3831,
1060   PREFIX_0F3832,
1061   PREFIX_0F3833,
1062   PREFIX_0F3834,
1063   PREFIX_0F3835,
1064   PREFIX_0F3837,
1065   PREFIX_0F3838,
1066   PREFIX_0F3839,
1067   PREFIX_0F383A,
1068   PREFIX_0F383B,
1069   PREFIX_0F383C,
1070   PREFIX_0F383D,
1071   PREFIX_0F383E,
1072   PREFIX_0F383F,
1073   PREFIX_0F3840,
1074   PREFIX_0F3841,
1075   PREFIX_0F3880,
1076   PREFIX_0F3881,
1077   PREFIX_0F3882,
1078   PREFIX_0F38C8,
1079   PREFIX_0F38C9,
1080   PREFIX_0F38CA,
1081   PREFIX_0F38CB,
1082   PREFIX_0F38CC,
1083   PREFIX_0F38CD,
1084   PREFIX_0F38CF,
1085   PREFIX_0F38DB,
1086   PREFIX_0F38DC,
1087   PREFIX_0F38DD,
1088   PREFIX_0F38DE,
1089   PREFIX_0F38DF,
1090   PREFIX_0F38F0,
1091   PREFIX_0F38F1,
1092   PREFIX_0F38F5,
1093   PREFIX_0F38F6,
1094   PREFIX_0F38F8,
1095   PREFIX_0F38F9,
1096   PREFIX_0F3A08,
1097   PREFIX_0F3A09,
1098   PREFIX_0F3A0A,
1099   PREFIX_0F3A0B,
1100   PREFIX_0F3A0C,
1101   PREFIX_0F3A0D,
1102   PREFIX_0F3A0E,
1103   PREFIX_0F3A14,
1104   PREFIX_0F3A15,
1105   PREFIX_0F3A16,
1106   PREFIX_0F3A17,
1107   PREFIX_0F3A20,
1108   PREFIX_0F3A21,
1109   PREFIX_0F3A22,
1110   PREFIX_0F3A40,
1111   PREFIX_0F3A41,
1112   PREFIX_0F3A42,
1113   PREFIX_0F3A44,
1114   PREFIX_0F3A60,
1115   PREFIX_0F3A61,
1116   PREFIX_0F3A62,
1117   PREFIX_0F3A63,
1118   PREFIX_0F3ACC,
1119   PREFIX_0F3ACE,
1120   PREFIX_0F3ACF,
1121   PREFIX_0F3ADF,
1122   PREFIX_VEX_0F10,
1123   PREFIX_VEX_0F11,
1124   PREFIX_VEX_0F12,
1125   PREFIX_VEX_0F16,
1126   PREFIX_VEX_0F2A,
1127   PREFIX_VEX_0F2C,
1128   PREFIX_VEX_0F2D,
1129   PREFIX_VEX_0F2E,
1130   PREFIX_VEX_0F2F,
1131   PREFIX_VEX_0F41,
1132   PREFIX_VEX_0F42,
1133   PREFIX_VEX_0F44,
1134   PREFIX_VEX_0F45,
1135   PREFIX_VEX_0F46,
1136   PREFIX_VEX_0F47,
1137   PREFIX_VEX_0F4A,
1138   PREFIX_VEX_0F4B,
1139   PREFIX_VEX_0F51,
1140   PREFIX_VEX_0F52,
1141   PREFIX_VEX_0F53,
1142   PREFIX_VEX_0F58,
1143   PREFIX_VEX_0F59,
1144   PREFIX_VEX_0F5A,
1145   PREFIX_VEX_0F5B,
1146   PREFIX_VEX_0F5C,
1147   PREFIX_VEX_0F5D,
1148   PREFIX_VEX_0F5E,
1149   PREFIX_VEX_0F5F,
1150   PREFIX_VEX_0F60,
1151   PREFIX_VEX_0F61,
1152   PREFIX_VEX_0F62,
1153   PREFIX_VEX_0F63,
1154   PREFIX_VEX_0F64,
1155   PREFIX_VEX_0F65,
1156   PREFIX_VEX_0F66,
1157   PREFIX_VEX_0F67,
1158   PREFIX_VEX_0F68,
1159   PREFIX_VEX_0F69,
1160   PREFIX_VEX_0F6A,
1161   PREFIX_VEX_0F6B,
1162   PREFIX_VEX_0F6C,
1163   PREFIX_VEX_0F6D,
1164   PREFIX_VEX_0F6E,
1165   PREFIX_VEX_0F6F,
1166   PREFIX_VEX_0F70,
1167   PREFIX_VEX_0F71_REG_2,
1168   PREFIX_VEX_0F71_REG_4,
1169   PREFIX_VEX_0F71_REG_6,
1170   PREFIX_VEX_0F72_REG_2,
1171   PREFIX_VEX_0F72_REG_4,
1172   PREFIX_VEX_0F72_REG_6,
1173   PREFIX_VEX_0F73_REG_2,
1174   PREFIX_VEX_0F73_REG_3,
1175   PREFIX_VEX_0F73_REG_6,
1176   PREFIX_VEX_0F73_REG_7,
1177   PREFIX_VEX_0F74,
1178   PREFIX_VEX_0F75,
1179   PREFIX_VEX_0F76,
1180   PREFIX_VEX_0F77,
1181   PREFIX_VEX_0F7C,
1182   PREFIX_VEX_0F7D,
1183   PREFIX_VEX_0F7E,
1184   PREFIX_VEX_0F7F,
1185   PREFIX_VEX_0F90,
1186   PREFIX_VEX_0F91,
1187   PREFIX_VEX_0F92,
1188   PREFIX_VEX_0F93,
1189   PREFIX_VEX_0F98,
1190   PREFIX_VEX_0F99,
1191   PREFIX_VEX_0FC2,
1192   PREFIX_VEX_0FC4,
1193   PREFIX_VEX_0FC5,
1194   PREFIX_VEX_0FD0,
1195   PREFIX_VEX_0FD1,
1196   PREFIX_VEX_0FD2,
1197   PREFIX_VEX_0FD3,
1198   PREFIX_VEX_0FD4,
1199   PREFIX_VEX_0FD5,
1200   PREFIX_VEX_0FD6,
1201   PREFIX_VEX_0FD7,
1202   PREFIX_VEX_0FD8,
1203   PREFIX_VEX_0FD9,
1204   PREFIX_VEX_0FDA,
1205   PREFIX_VEX_0FDB,
1206   PREFIX_VEX_0FDC,
1207   PREFIX_VEX_0FDD,
1208   PREFIX_VEX_0FDE,
1209   PREFIX_VEX_0FDF,
1210   PREFIX_VEX_0FE0,
1211   PREFIX_VEX_0FE1,
1212   PREFIX_VEX_0FE2,
1213   PREFIX_VEX_0FE3,
1214   PREFIX_VEX_0FE4,
1215   PREFIX_VEX_0FE5,
1216   PREFIX_VEX_0FE6,
1217   PREFIX_VEX_0FE7,
1218   PREFIX_VEX_0FE8,
1219   PREFIX_VEX_0FE9,
1220   PREFIX_VEX_0FEA,
1221   PREFIX_VEX_0FEB,
1222   PREFIX_VEX_0FEC,
1223   PREFIX_VEX_0FED,
1224   PREFIX_VEX_0FEE,
1225   PREFIX_VEX_0FEF,
1226   PREFIX_VEX_0FF0,
1227   PREFIX_VEX_0FF1,
1228   PREFIX_VEX_0FF2,
1229   PREFIX_VEX_0FF3,
1230   PREFIX_VEX_0FF4,
1231   PREFIX_VEX_0FF5,
1232   PREFIX_VEX_0FF6,
1233   PREFIX_VEX_0FF7,
1234   PREFIX_VEX_0FF8,
1235   PREFIX_VEX_0FF9,
1236   PREFIX_VEX_0FFA,
1237   PREFIX_VEX_0FFB,
1238   PREFIX_VEX_0FFC,
1239   PREFIX_VEX_0FFD,
1240   PREFIX_VEX_0FFE,
1241   PREFIX_VEX_0F3800,
1242   PREFIX_VEX_0F3801,
1243   PREFIX_VEX_0F3802,
1244   PREFIX_VEX_0F3803,
1245   PREFIX_VEX_0F3804,
1246   PREFIX_VEX_0F3805,
1247   PREFIX_VEX_0F3806,
1248   PREFIX_VEX_0F3807,
1249   PREFIX_VEX_0F3808,
1250   PREFIX_VEX_0F3809,
1251   PREFIX_VEX_0F380A,
1252   PREFIX_VEX_0F380B,
1253   PREFIX_VEX_0F380C,
1254   PREFIX_VEX_0F380D,
1255   PREFIX_VEX_0F380E,
1256   PREFIX_VEX_0F380F,
1257   PREFIX_VEX_0F3813,
1258   PREFIX_VEX_0F3816,
1259   PREFIX_VEX_0F3817,
1260   PREFIX_VEX_0F3818,
1261   PREFIX_VEX_0F3819,
1262   PREFIX_VEX_0F381A,
1263   PREFIX_VEX_0F381C,
1264   PREFIX_VEX_0F381D,
1265   PREFIX_VEX_0F381E,
1266   PREFIX_VEX_0F3820,
1267   PREFIX_VEX_0F3821,
1268   PREFIX_VEX_0F3822,
1269   PREFIX_VEX_0F3823,
1270   PREFIX_VEX_0F3824,
1271   PREFIX_VEX_0F3825,
1272   PREFIX_VEX_0F3828,
1273   PREFIX_VEX_0F3829,
1274   PREFIX_VEX_0F382A,
1275   PREFIX_VEX_0F382B,
1276   PREFIX_VEX_0F382C,
1277   PREFIX_VEX_0F382D,
1278   PREFIX_VEX_0F382E,
1279   PREFIX_VEX_0F382F,
1280   PREFIX_VEX_0F3830,
1281   PREFIX_VEX_0F3831,
1282   PREFIX_VEX_0F3832,
1283   PREFIX_VEX_0F3833,
1284   PREFIX_VEX_0F3834,
1285   PREFIX_VEX_0F3835,
1286   PREFIX_VEX_0F3836,
1287   PREFIX_VEX_0F3837,
1288   PREFIX_VEX_0F3838,
1289   PREFIX_VEX_0F3839,
1290   PREFIX_VEX_0F383A,
1291   PREFIX_VEX_0F383B,
1292   PREFIX_VEX_0F383C,
1293   PREFIX_VEX_0F383D,
1294   PREFIX_VEX_0F383E,
1295   PREFIX_VEX_0F383F,
1296   PREFIX_VEX_0F3840,
1297   PREFIX_VEX_0F3841,
1298   PREFIX_VEX_0F3845,
1299   PREFIX_VEX_0F3846,
1300   PREFIX_VEX_0F3847,
1301   PREFIX_VEX_0F3858,
1302   PREFIX_VEX_0F3859,
1303   PREFIX_VEX_0F385A,
1304   PREFIX_VEX_0F3878,
1305   PREFIX_VEX_0F3879,
1306   PREFIX_VEX_0F388C,
1307   PREFIX_VEX_0F388E,
1308   PREFIX_VEX_0F3890,
1309   PREFIX_VEX_0F3891,
1310   PREFIX_VEX_0F3892,
1311   PREFIX_VEX_0F3893,
1312   PREFIX_VEX_0F3896,
1313   PREFIX_VEX_0F3897,
1314   PREFIX_VEX_0F3898,
1315   PREFIX_VEX_0F3899,
1316   PREFIX_VEX_0F389A,
1317   PREFIX_VEX_0F389B,
1318   PREFIX_VEX_0F389C,
1319   PREFIX_VEX_0F389D,
1320   PREFIX_VEX_0F389E,
1321   PREFIX_VEX_0F389F,
1322   PREFIX_VEX_0F38A6,
1323   PREFIX_VEX_0F38A7,
1324   PREFIX_VEX_0F38A8,
1325   PREFIX_VEX_0F38A9,
1326   PREFIX_VEX_0F38AA,
1327   PREFIX_VEX_0F38AB,
1328   PREFIX_VEX_0F38AC,
1329   PREFIX_VEX_0F38AD,
1330   PREFIX_VEX_0F38AE,
1331   PREFIX_VEX_0F38AF,
1332   PREFIX_VEX_0F38B6,
1333   PREFIX_VEX_0F38B7,
1334   PREFIX_VEX_0F38B8,
1335   PREFIX_VEX_0F38B9,
1336   PREFIX_VEX_0F38BA,
1337   PREFIX_VEX_0F38BB,
1338   PREFIX_VEX_0F38BC,
1339   PREFIX_VEX_0F38BD,
1340   PREFIX_VEX_0F38BE,
1341   PREFIX_VEX_0F38BF,
1342   PREFIX_VEX_0F38CF,
1343   PREFIX_VEX_0F38DB,
1344   PREFIX_VEX_0F38DC,
1345   PREFIX_VEX_0F38DD,
1346   PREFIX_VEX_0F38DE,
1347   PREFIX_VEX_0F38DF,
1348   PREFIX_VEX_0F38F2,
1349   PREFIX_VEX_0F38F3_REG_1,
1350   PREFIX_VEX_0F38F3_REG_2,
1351   PREFIX_VEX_0F38F3_REG_3,
1352   PREFIX_VEX_0F38F5,
1353   PREFIX_VEX_0F38F6,
1354   PREFIX_VEX_0F38F7,
1355   PREFIX_VEX_0F3A00,
1356   PREFIX_VEX_0F3A01,
1357   PREFIX_VEX_0F3A02,
1358   PREFIX_VEX_0F3A04,
1359   PREFIX_VEX_0F3A05,
1360   PREFIX_VEX_0F3A06,
1361   PREFIX_VEX_0F3A08,
1362   PREFIX_VEX_0F3A09,
1363   PREFIX_VEX_0F3A0A,
1364   PREFIX_VEX_0F3A0B,
1365   PREFIX_VEX_0F3A0C,
1366   PREFIX_VEX_0F3A0D,
1367   PREFIX_VEX_0F3A0E,
1368   PREFIX_VEX_0F3A0F,
1369   PREFIX_VEX_0F3A14,
1370   PREFIX_VEX_0F3A15,
1371   PREFIX_VEX_0F3A16,
1372   PREFIX_VEX_0F3A17,
1373   PREFIX_VEX_0F3A18,
1374   PREFIX_VEX_0F3A19,
1375   PREFIX_VEX_0F3A1D,
1376   PREFIX_VEX_0F3A20,
1377   PREFIX_VEX_0F3A21,
1378   PREFIX_VEX_0F3A22,
1379   PREFIX_VEX_0F3A30,
1380   PREFIX_VEX_0F3A31,
1381   PREFIX_VEX_0F3A32,
1382   PREFIX_VEX_0F3A33,
1383   PREFIX_VEX_0F3A38,
1384   PREFIX_VEX_0F3A39,
1385   PREFIX_VEX_0F3A40,
1386   PREFIX_VEX_0F3A41,
1387   PREFIX_VEX_0F3A42,
1388   PREFIX_VEX_0F3A44,
1389   PREFIX_VEX_0F3A46,
1390   PREFIX_VEX_0F3A48,
1391   PREFIX_VEX_0F3A49,
1392   PREFIX_VEX_0F3A4A,
1393   PREFIX_VEX_0F3A4B,
1394   PREFIX_VEX_0F3A4C,
1395   PREFIX_VEX_0F3A5C,
1396   PREFIX_VEX_0F3A5D,
1397   PREFIX_VEX_0F3A5E,
1398   PREFIX_VEX_0F3A5F,
1399   PREFIX_VEX_0F3A60,
1400   PREFIX_VEX_0F3A61,
1401   PREFIX_VEX_0F3A62,
1402   PREFIX_VEX_0F3A63,
1403   PREFIX_VEX_0F3A68,
1404   PREFIX_VEX_0F3A69,
1405   PREFIX_VEX_0F3A6A,
1406   PREFIX_VEX_0F3A6B,
1407   PREFIX_VEX_0F3A6C,
1408   PREFIX_VEX_0F3A6D,
1409   PREFIX_VEX_0F3A6E,
1410   PREFIX_VEX_0F3A6F,
1411   PREFIX_VEX_0F3A78,
1412   PREFIX_VEX_0F3A79,
1413   PREFIX_VEX_0F3A7A,
1414   PREFIX_VEX_0F3A7B,
1415   PREFIX_VEX_0F3A7C,
1416   PREFIX_VEX_0F3A7D,
1417   PREFIX_VEX_0F3A7E,
1418   PREFIX_VEX_0F3A7F,
1419   PREFIX_VEX_0F3ACE,
1420   PREFIX_VEX_0F3ACF,
1421   PREFIX_VEX_0F3ADF,
1422   PREFIX_VEX_0F3AF0,
1423
1424   PREFIX_EVEX_0F10,
1425   PREFIX_EVEX_0F11,
1426   PREFIX_EVEX_0F12,
1427   PREFIX_EVEX_0F16,
1428   PREFIX_EVEX_0F2A,
1429   PREFIX_EVEX_0F2C,
1430   PREFIX_EVEX_0F2D,
1431   PREFIX_EVEX_0F2E,
1432   PREFIX_EVEX_0F2F,
1433   PREFIX_EVEX_0F51,
1434   PREFIX_EVEX_0F58,
1435   PREFIX_EVEX_0F59,
1436   PREFIX_EVEX_0F5A,
1437   PREFIX_EVEX_0F5B,
1438   PREFIX_EVEX_0F5C,
1439   PREFIX_EVEX_0F5D,
1440   PREFIX_EVEX_0F5E,
1441   PREFIX_EVEX_0F5F,
1442   PREFIX_EVEX_0F60,
1443   PREFIX_EVEX_0F61,
1444   PREFIX_EVEX_0F62,
1445   PREFIX_EVEX_0F63,
1446   PREFIX_EVEX_0F64,
1447   PREFIX_EVEX_0F65,
1448   PREFIX_EVEX_0F66,
1449   PREFIX_EVEX_0F67,
1450   PREFIX_EVEX_0F68,
1451   PREFIX_EVEX_0F69,
1452   PREFIX_EVEX_0F6A,
1453   PREFIX_EVEX_0F6B,
1454   PREFIX_EVEX_0F6C,
1455   PREFIX_EVEX_0F6D,
1456   PREFIX_EVEX_0F6E,
1457   PREFIX_EVEX_0F6F,
1458   PREFIX_EVEX_0F70,
1459   PREFIX_EVEX_0F71_REG_2,
1460   PREFIX_EVEX_0F71_REG_4,
1461   PREFIX_EVEX_0F71_REG_6,
1462   PREFIX_EVEX_0F72_REG_0,
1463   PREFIX_EVEX_0F72_REG_1,
1464   PREFIX_EVEX_0F72_REG_2,
1465   PREFIX_EVEX_0F72_REG_4,
1466   PREFIX_EVEX_0F72_REG_6,
1467   PREFIX_EVEX_0F73_REG_2,
1468   PREFIX_EVEX_0F73_REG_3,
1469   PREFIX_EVEX_0F73_REG_6,
1470   PREFIX_EVEX_0F73_REG_7,
1471   PREFIX_EVEX_0F74,
1472   PREFIX_EVEX_0F75,
1473   PREFIX_EVEX_0F76,
1474   PREFIX_EVEX_0F78,
1475   PREFIX_EVEX_0F79,
1476   PREFIX_EVEX_0F7A,
1477   PREFIX_EVEX_0F7B,
1478   PREFIX_EVEX_0F7E,
1479   PREFIX_EVEX_0F7F,
1480   PREFIX_EVEX_0FC2,
1481   PREFIX_EVEX_0FC4,
1482   PREFIX_EVEX_0FC5,
1483   PREFIX_EVEX_0FD1,
1484   PREFIX_EVEX_0FD2,
1485   PREFIX_EVEX_0FD3,
1486   PREFIX_EVEX_0FD4,
1487   PREFIX_EVEX_0FD5,
1488   PREFIX_EVEX_0FD6,
1489   PREFIX_EVEX_0FD8,
1490   PREFIX_EVEX_0FD9,
1491   PREFIX_EVEX_0FDA,
1492   PREFIX_EVEX_0FDB,
1493   PREFIX_EVEX_0FDC,
1494   PREFIX_EVEX_0FDD,
1495   PREFIX_EVEX_0FDE,
1496   PREFIX_EVEX_0FDF,
1497   PREFIX_EVEX_0FE0,
1498   PREFIX_EVEX_0FE1,
1499   PREFIX_EVEX_0FE2,
1500   PREFIX_EVEX_0FE3,
1501   PREFIX_EVEX_0FE4,
1502   PREFIX_EVEX_0FE5,
1503   PREFIX_EVEX_0FE6,
1504   PREFIX_EVEX_0FE7,
1505   PREFIX_EVEX_0FE8,
1506   PREFIX_EVEX_0FE9,
1507   PREFIX_EVEX_0FEA,
1508   PREFIX_EVEX_0FEB,
1509   PREFIX_EVEX_0FEC,
1510   PREFIX_EVEX_0FED,
1511   PREFIX_EVEX_0FEE,
1512   PREFIX_EVEX_0FEF,
1513   PREFIX_EVEX_0FF1,
1514   PREFIX_EVEX_0FF2,
1515   PREFIX_EVEX_0FF3,
1516   PREFIX_EVEX_0FF4,
1517   PREFIX_EVEX_0FF5,
1518   PREFIX_EVEX_0FF6,
1519   PREFIX_EVEX_0FF8,
1520   PREFIX_EVEX_0FF9,
1521   PREFIX_EVEX_0FFA,
1522   PREFIX_EVEX_0FFB,
1523   PREFIX_EVEX_0FFC,
1524   PREFIX_EVEX_0FFD,
1525   PREFIX_EVEX_0FFE,
1526   PREFIX_EVEX_0F3800,
1527   PREFIX_EVEX_0F3804,
1528   PREFIX_EVEX_0F380B,
1529   PREFIX_EVEX_0F380C,
1530   PREFIX_EVEX_0F380D,
1531   PREFIX_EVEX_0F3810,
1532   PREFIX_EVEX_0F3811,
1533   PREFIX_EVEX_0F3812,
1534   PREFIX_EVEX_0F3813,
1535   PREFIX_EVEX_0F3814,
1536   PREFIX_EVEX_0F3815,
1537   PREFIX_EVEX_0F3816,
1538   PREFIX_EVEX_0F3818,
1539   PREFIX_EVEX_0F3819,
1540   PREFIX_EVEX_0F381A,
1541   PREFIX_EVEX_0F381B,
1542   PREFIX_EVEX_0F381C,
1543   PREFIX_EVEX_0F381D,
1544   PREFIX_EVEX_0F381E,
1545   PREFIX_EVEX_0F381F,
1546   PREFIX_EVEX_0F3820,
1547   PREFIX_EVEX_0F3821,
1548   PREFIX_EVEX_0F3822,
1549   PREFIX_EVEX_0F3823,
1550   PREFIX_EVEX_0F3824,
1551   PREFIX_EVEX_0F3825,
1552   PREFIX_EVEX_0F3826,
1553   PREFIX_EVEX_0F3827,
1554   PREFIX_EVEX_0F3828,
1555   PREFIX_EVEX_0F3829,
1556   PREFIX_EVEX_0F382A,
1557   PREFIX_EVEX_0F382B,
1558   PREFIX_EVEX_0F382C,
1559   PREFIX_EVEX_0F382D,
1560   PREFIX_EVEX_0F3830,
1561   PREFIX_EVEX_0F3831,
1562   PREFIX_EVEX_0F3832,
1563   PREFIX_EVEX_0F3833,
1564   PREFIX_EVEX_0F3834,
1565   PREFIX_EVEX_0F3835,
1566   PREFIX_EVEX_0F3836,
1567   PREFIX_EVEX_0F3837,
1568   PREFIX_EVEX_0F3838,
1569   PREFIX_EVEX_0F3839,
1570   PREFIX_EVEX_0F383A,
1571   PREFIX_EVEX_0F383B,
1572   PREFIX_EVEX_0F383C,
1573   PREFIX_EVEX_0F383D,
1574   PREFIX_EVEX_0F383E,
1575   PREFIX_EVEX_0F383F,
1576   PREFIX_EVEX_0F3840,
1577   PREFIX_EVEX_0F3842,
1578   PREFIX_EVEX_0F3843,
1579   PREFIX_EVEX_0F3844,
1580   PREFIX_EVEX_0F3845,
1581   PREFIX_EVEX_0F3846,
1582   PREFIX_EVEX_0F3847,
1583   PREFIX_EVEX_0F384C,
1584   PREFIX_EVEX_0F384D,
1585   PREFIX_EVEX_0F384E,
1586   PREFIX_EVEX_0F384F,
1587   PREFIX_EVEX_0F3850,
1588   PREFIX_EVEX_0F3851,
1589   PREFIX_EVEX_0F3852,
1590   PREFIX_EVEX_0F3853,
1591   PREFIX_EVEX_0F3854,
1592   PREFIX_EVEX_0F3855,
1593   PREFIX_EVEX_0F3858,
1594   PREFIX_EVEX_0F3859,
1595   PREFIX_EVEX_0F385A,
1596   PREFIX_EVEX_0F385B,
1597   PREFIX_EVEX_0F3862,
1598   PREFIX_EVEX_0F3863,
1599   PREFIX_EVEX_0F3864,
1600   PREFIX_EVEX_0F3865,
1601   PREFIX_EVEX_0F3866,
1602   PREFIX_EVEX_0F3868,
1603   PREFIX_EVEX_0F3870,
1604   PREFIX_EVEX_0F3871,
1605   PREFIX_EVEX_0F3872,
1606   PREFIX_EVEX_0F3873,
1607   PREFIX_EVEX_0F3875,
1608   PREFIX_EVEX_0F3876,
1609   PREFIX_EVEX_0F3877,
1610   PREFIX_EVEX_0F3878,
1611   PREFIX_EVEX_0F3879,
1612   PREFIX_EVEX_0F387A,
1613   PREFIX_EVEX_0F387B,
1614   PREFIX_EVEX_0F387C,
1615   PREFIX_EVEX_0F387D,
1616   PREFIX_EVEX_0F387E,
1617   PREFIX_EVEX_0F387F,
1618   PREFIX_EVEX_0F3883,
1619   PREFIX_EVEX_0F3888,
1620   PREFIX_EVEX_0F3889,
1621   PREFIX_EVEX_0F388A,
1622   PREFIX_EVEX_0F388B,
1623   PREFIX_EVEX_0F388D,
1624   PREFIX_EVEX_0F388F,
1625   PREFIX_EVEX_0F3890,
1626   PREFIX_EVEX_0F3891,
1627   PREFIX_EVEX_0F3892,
1628   PREFIX_EVEX_0F3893,
1629   PREFIX_EVEX_0F3896,
1630   PREFIX_EVEX_0F3897,
1631   PREFIX_EVEX_0F3898,
1632   PREFIX_EVEX_0F3899,
1633   PREFIX_EVEX_0F389A,
1634   PREFIX_EVEX_0F389B,
1635   PREFIX_EVEX_0F389C,
1636   PREFIX_EVEX_0F389D,
1637   PREFIX_EVEX_0F389E,
1638   PREFIX_EVEX_0F389F,
1639   PREFIX_EVEX_0F38A0,
1640   PREFIX_EVEX_0F38A1,
1641   PREFIX_EVEX_0F38A2,
1642   PREFIX_EVEX_0F38A3,
1643   PREFIX_EVEX_0F38A6,
1644   PREFIX_EVEX_0F38A7,
1645   PREFIX_EVEX_0F38A8,
1646   PREFIX_EVEX_0F38A9,
1647   PREFIX_EVEX_0F38AA,
1648   PREFIX_EVEX_0F38AB,
1649   PREFIX_EVEX_0F38AC,
1650   PREFIX_EVEX_0F38AD,
1651   PREFIX_EVEX_0F38AE,
1652   PREFIX_EVEX_0F38AF,
1653   PREFIX_EVEX_0F38B4,
1654   PREFIX_EVEX_0F38B5,
1655   PREFIX_EVEX_0F38B6,
1656   PREFIX_EVEX_0F38B7,
1657   PREFIX_EVEX_0F38B8,
1658   PREFIX_EVEX_0F38B9,
1659   PREFIX_EVEX_0F38BA,
1660   PREFIX_EVEX_0F38BB,
1661   PREFIX_EVEX_0F38BC,
1662   PREFIX_EVEX_0F38BD,
1663   PREFIX_EVEX_0F38BE,
1664   PREFIX_EVEX_0F38BF,
1665   PREFIX_EVEX_0F38C4,
1666   PREFIX_EVEX_0F38C6_REG_1,
1667   PREFIX_EVEX_0F38C6_REG_2,
1668   PREFIX_EVEX_0F38C6_REG_5,
1669   PREFIX_EVEX_0F38C6_REG_6,
1670   PREFIX_EVEX_0F38C7_REG_1,
1671   PREFIX_EVEX_0F38C7_REG_2,
1672   PREFIX_EVEX_0F38C7_REG_5,
1673   PREFIX_EVEX_0F38C7_REG_6,
1674   PREFIX_EVEX_0F38C8,
1675   PREFIX_EVEX_0F38CA,
1676   PREFIX_EVEX_0F38CB,
1677   PREFIX_EVEX_0F38CC,
1678   PREFIX_EVEX_0F38CD,
1679   PREFIX_EVEX_0F38CF,
1680   PREFIX_EVEX_0F38DC,
1681   PREFIX_EVEX_0F38DD,
1682   PREFIX_EVEX_0F38DE,
1683   PREFIX_EVEX_0F38DF,
1684
1685   PREFIX_EVEX_0F3A00,
1686   PREFIX_EVEX_0F3A01,
1687   PREFIX_EVEX_0F3A03,
1688   PREFIX_EVEX_0F3A04,
1689   PREFIX_EVEX_0F3A05,
1690   PREFIX_EVEX_0F3A08,
1691   PREFIX_EVEX_0F3A09,
1692   PREFIX_EVEX_0F3A0A,
1693   PREFIX_EVEX_0F3A0B,
1694   PREFIX_EVEX_0F3A0F,
1695   PREFIX_EVEX_0F3A14,
1696   PREFIX_EVEX_0F3A15,
1697   PREFIX_EVEX_0F3A16,
1698   PREFIX_EVEX_0F3A17,
1699   PREFIX_EVEX_0F3A18,
1700   PREFIX_EVEX_0F3A19,
1701   PREFIX_EVEX_0F3A1A,
1702   PREFIX_EVEX_0F3A1B,
1703   PREFIX_EVEX_0F3A1D,
1704   PREFIX_EVEX_0F3A1E,
1705   PREFIX_EVEX_0F3A1F,
1706   PREFIX_EVEX_0F3A20,
1707   PREFIX_EVEX_0F3A21,
1708   PREFIX_EVEX_0F3A22,
1709   PREFIX_EVEX_0F3A23,
1710   PREFIX_EVEX_0F3A25,
1711   PREFIX_EVEX_0F3A26,
1712   PREFIX_EVEX_0F3A27,
1713   PREFIX_EVEX_0F3A38,
1714   PREFIX_EVEX_0F3A39,
1715   PREFIX_EVEX_0F3A3A,
1716   PREFIX_EVEX_0F3A3B,
1717   PREFIX_EVEX_0F3A3E,
1718   PREFIX_EVEX_0F3A3F,
1719   PREFIX_EVEX_0F3A42,
1720   PREFIX_EVEX_0F3A43,
1721   PREFIX_EVEX_0F3A44,
1722   PREFIX_EVEX_0F3A50,
1723   PREFIX_EVEX_0F3A51,
1724   PREFIX_EVEX_0F3A54,
1725   PREFIX_EVEX_0F3A55,
1726   PREFIX_EVEX_0F3A56,
1727   PREFIX_EVEX_0F3A57,
1728   PREFIX_EVEX_0F3A66,
1729   PREFIX_EVEX_0F3A67,
1730   PREFIX_EVEX_0F3A70,
1731   PREFIX_EVEX_0F3A71,
1732   PREFIX_EVEX_0F3A72,
1733   PREFIX_EVEX_0F3A73,
1734   PREFIX_EVEX_0F3ACE,
1735   PREFIX_EVEX_0F3ACF
1736 };
1737
1738 enum
1739 {
1740   X86_64_06 = 0,
1741   X86_64_07,
1742   X86_64_0E,
1743   X86_64_16,
1744   X86_64_17,
1745   X86_64_1E,
1746   X86_64_1F,
1747   X86_64_27,
1748   X86_64_2F,
1749   X86_64_37,
1750   X86_64_3F,
1751   X86_64_60,
1752   X86_64_61,
1753   X86_64_62,
1754   X86_64_63,
1755   X86_64_6D,
1756   X86_64_6F,
1757   X86_64_82,
1758   X86_64_9A,
1759   X86_64_C2,
1760   X86_64_C3,
1761   X86_64_C4,
1762   X86_64_C5,
1763   X86_64_CE,
1764   X86_64_D4,
1765   X86_64_D5,
1766   X86_64_E8,
1767   X86_64_E9,
1768   X86_64_EA,
1769   X86_64_0F01_REG_0,
1770   X86_64_0F01_REG_1,
1771   X86_64_0F01_REG_2,
1772   X86_64_0F01_REG_3
1773 };
1774
1775 enum
1776 {
1777   THREE_BYTE_0F38 = 0,
1778   THREE_BYTE_0F3A
1779 };
1780
1781 enum
1782 {
1783   XOP_08 = 0,
1784   XOP_09,
1785   XOP_0A
1786 };
1787
1788 enum
1789 {
1790   VEX_0F = 0,
1791   VEX_0F38,
1792   VEX_0F3A
1793 };
1794
1795 enum
1796 {
1797   EVEX_0F = 0,
1798   EVEX_0F38,
1799   EVEX_0F3A
1800 };
1801
1802 enum
1803 {
1804   VEX_LEN_0F12_P_0_M_0 = 0,
1805   VEX_LEN_0F12_P_0_M_1,
1806 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1807   VEX_LEN_0F13_M_0,
1808   VEX_LEN_0F16_P_0_M_0,
1809   VEX_LEN_0F16_P_0_M_1,
1810 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1811   VEX_LEN_0F17_M_0,
1812   VEX_LEN_0F41_P_0,
1813   VEX_LEN_0F41_P_2,
1814   VEX_LEN_0F42_P_0,
1815   VEX_LEN_0F42_P_2,
1816   VEX_LEN_0F44_P_0,
1817   VEX_LEN_0F44_P_2,
1818   VEX_LEN_0F45_P_0,
1819   VEX_LEN_0F45_P_2,
1820   VEX_LEN_0F46_P_0,
1821   VEX_LEN_0F46_P_2,
1822   VEX_LEN_0F47_P_0,
1823   VEX_LEN_0F47_P_2,
1824   VEX_LEN_0F4A_P_0,
1825   VEX_LEN_0F4A_P_2,
1826   VEX_LEN_0F4B_P_0,
1827   VEX_LEN_0F4B_P_2,
1828   VEX_LEN_0F6E_P_2,
1829   VEX_LEN_0F77_P_0,
1830   VEX_LEN_0F7E_P_1,
1831   VEX_LEN_0F7E_P_2,
1832   VEX_LEN_0F90_P_0,
1833   VEX_LEN_0F90_P_2,
1834   VEX_LEN_0F91_P_0,
1835   VEX_LEN_0F91_P_2,
1836   VEX_LEN_0F92_P_0,
1837   VEX_LEN_0F92_P_2,
1838   VEX_LEN_0F92_P_3,
1839   VEX_LEN_0F93_P_0,
1840   VEX_LEN_0F93_P_2,
1841   VEX_LEN_0F93_P_3,
1842   VEX_LEN_0F98_P_0,
1843   VEX_LEN_0F98_P_2,
1844   VEX_LEN_0F99_P_0,
1845   VEX_LEN_0F99_P_2,
1846   VEX_LEN_0FAE_R_2_M_0,
1847   VEX_LEN_0FAE_R_3_M_0,
1848   VEX_LEN_0FC4_P_2,
1849   VEX_LEN_0FC5_P_2,
1850   VEX_LEN_0FD6_P_2,
1851   VEX_LEN_0FF7_P_2,
1852   VEX_LEN_0F3816_P_2,
1853   VEX_LEN_0F3819_P_2,
1854   VEX_LEN_0F381A_P_2_M_0,
1855   VEX_LEN_0F3836_P_2,
1856   VEX_LEN_0F3841_P_2,
1857   VEX_LEN_0F385A_P_2_M_0,
1858   VEX_LEN_0F38DB_P_2,
1859   VEX_LEN_0F38F2_P_0,
1860   VEX_LEN_0F38F3_R_1_P_0,
1861   VEX_LEN_0F38F3_R_2_P_0,
1862   VEX_LEN_0F38F3_R_3_P_0,
1863   VEX_LEN_0F38F5_P_0,
1864   VEX_LEN_0F38F5_P_1,
1865   VEX_LEN_0F38F5_P_3,
1866   VEX_LEN_0F38F6_P_3,
1867   VEX_LEN_0F38F7_P_0,
1868   VEX_LEN_0F38F7_P_1,
1869   VEX_LEN_0F38F7_P_2,
1870   VEX_LEN_0F38F7_P_3,
1871   VEX_LEN_0F3A00_P_2,
1872   VEX_LEN_0F3A01_P_2,
1873   VEX_LEN_0F3A06_P_2,
1874   VEX_LEN_0F3A14_P_2,
1875   VEX_LEN_0F3A15_P_2,
1876   VEX_LEN_0F3A16_P_2,
1877   VEX_LEN_0F3A17_P_2,
1878   VEX_LEN_0F3A18_P_2,
1879   VEX_LEN_0F3A19_P_2,
1880   VEX_LEN_0F3A20_P_2,
1881   VEX_LEN_0F3A21_P_2,
1882   VEX_LEN_0F3A22_P_2,
1883   VEX_LEN_0F3A30_P_2,
1884   VEX_LEN_0F3A31_P_2,
1885   VEX_LEN_0F3A32_P_2,
1886   VEX_LEN_0F3A33_P_2,
1887   VEX_LEN_0F3A38_P_2,
1888   VEX_LEN_0F3A39_P_2,
1889   VEX_LEN_0F3A41_P_2,
1890   VEX_LEN_0F3A46_P_2,
1891   VEX_LEN_0F3A60_P_2,
1892   VEX_LEN_0F3A61_P_2,
1893   VEX_LEN_0F3A62_P_2,
1894   VEX_LEN_0F3A63_P_2,
1895   VEX_LEN_0F3A6A_P_2,
1896   VEX_LEN_0F3A6B_P_2,
1897   VEX_LEN_0F3A6E_P_2,
1898   VEX_LEN_0F3A6F_P_2,
1899   VEX_LEN_0F3A7A_P_2,
1900   VEX_LEN_0F3A7B_P_2,
1901   VEX_LEN_0F3A7E_P_2,
1902   VEX_LEN_0F3A7F_P_2,
1903   VEX_LEN_0F3ADF_P_2,
1904   VEX_LEN_0F3AF0_P_3,
1905   VEX_LEN_0FXOP_08_CC,
1906   VEX_LEN_0FXOP_08_CD,
1907   VEX_LEN_0FXOP_08_CE,
1908   VEX_LEN_0FXOP_08_CF,
1909   VEX_LEN_0FXOP_08_EC,
1910   VEX_LEN_0FXOP_08_ED,
1911   VEX_LEN_0FXOP_08_EE,
1912   VEX_LEN_0FXOP_08_EF,
1913   VEX_LEN_0FXOP_09_80,
1914   VEX_LEN_0FXOP_09_81
1915 };
1916
1917 enum
1918 {
1919   EVEX_LEN_0F6E_P_2 = 0,
1920   EVEX_LEN_0F7E_P_1,
1921   EVEX_LEN_0F7E_P_2,
1922   EVEX_LEN_0FD6_P_2,
1923   EVEX_LEN_0F3819_P_2_W_0,
1924   EVEX_LEN_0F3819_P_2_W_1,
1925   EVEX_LEN_0F381A_P_2_W_0,
1926   EVEX_LEN_0F381A_P_2_W_1,
1927   EVEX_LEN_0F381B_P_2_W_0,
1928   EVEX_LEN_0F381B_P_2_W_1,
1929   EVEX_LEN_0F385A_P_2_W_0,
1930   EVEX_LEN_0F385A_P_2_W_1,
1931   EVEX_LEN_0F385B_P_2_W_0,
1932   EVEX_LEN_0F385B_P_2_W_1,
1933   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1934   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1935   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1936   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1937   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1938   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1939   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1940   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1941   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1942   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1943   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1944   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1945   EVEX_LEN_0F3A18_P_2_W_0,
1946   EVEX_LEN_0F3A18_P_2_W_1,
1947   EVEX_LEN_0F3A19_P_2_W_0,
1948   EVEX_LEN_0F3A19_P_2_W_1,
1949   EVEX_LEN_0F3A1A_P_2_W_0,
1950   EVEX_LEN_0F3A1A_P_2_W_1,
1951   EVEX_LEN_0F3A1B_P_2_W_0,
1952   EVEX_LEN_0F3A1B_P_2_W_1,
1953   EVEX_LEN_0F3A23_P_2_W_0,
1954   EVEX_LEN_0F3A23_P_2_W_1,
1955   EVEX_LEN_0F3A38_P_2_W_0,
1956   EVEX_LEN_0F3A38_P_2_W_1,
1957   EVEX_LEN_0F3A39_P_2_W_0,
1958   EVEX_LEN_0F3A39_P_2_W_1,
1959   EVEX_LEN_0F3A3A_P_2_W_0,
1960   EVEX_LEN_0F3A3A_P_2_W_1,
1961   EVEX_LEN_0F3A3B_P_2_W_0,
1962   EVEX_LEN_0F3A3B_P_2_W_1,
1963   EVEX_LEN_0F3A43_P_2_W_0,
1964   EVEX_LEN_0F3A43_P_2_W_1
1965 };
1966
1967 enum
1968 {
1969   VEX_W_0F41_P_0_LEN_1 = 0,
1970   VEX_W_0F41_P_2_LEN_1,
1971   VEX_W_0F42_P_0_LEN_1,
1972   VEX_W_0F42_P_2_LEN_1,
1973   VEX_W_0F44_P_0_LEN_0,
1974   VEX_W_0F44_P_2_LEN_0,
1975   VEX_W_0F45_P_0_LEN_1,
1976   VEX_W_0F45_P_2_LEN_1,
1977   VEX_W_0F46_P_0_LEN_1,
1978   VEX_W_0F46_P_2_LEN_1,
1979   VEX_W_0F47_P_0_LEN_1,
1980   VEX_W_0F47_P_2_LEN_1,
1981   VEX_W_0F4A_P_0_LEN_1,
1982   VEX_W_0F4A_P_2_LEN_1,
1983   VEX_W_0F4B_P_0_LEN_1,
1984   VEX_W_0F4B_P_2_LEN_1,
1985   VEX_W_0F90_P_0_LEN_0,
1986   VEX_W_0F90_P_2_LEN_0,
1987   VEX_W_0F91_P_0_LEN_0,
1988   VEX_W_0F91_P_2_LEN_0,
1989   VEX_W_0F92_P_0_LEN_0,
1990   VEX_W_0F92_P_2_LEN_0,
1991   VEX_W_0F93_P_0_LEN_0,
1992   VEX_W_0F93_P_2_LEN_0,
1993   VEX_W_0F98_P_0_LEN_0,
1994   VEX_W_0F98_P_2_LEN_0,
1995   VEX_W_0F99_P_0_LEN_0,
1996   VEX_W_0F99_P_2_LEN_0,
1997   VEX_W_0F380C_P_2,
1998   VEX_W_0F380D_P_2,
1999   VEX_W_0F380E_P_2,
2000   VEX_W_0F380F_P_2,
2001   VEX_W_0F3816_P_2,
2002   VEX_W_0F3818_P_2,
2003   VEX_W_0F3819_P_2,
2004   VEX_W_0F381A_P_2_M_0,
2005   VEX_W_0F382C_P_2_M_0,
2006   VEX_W_0F382D_P_2_M_0,
2007   VEX_W_0F382E_P_2_M_0,
2008   VEX_W_0F382F_P_2_M_0,
2009   VEX_W_0F3836_P_2,
2010   VEX_W_0F3846_P_2,
2011   VEX_W_0F3858_P_2,
2012   VEX_W_0F3859_P_2,
2013   VEX_W_0F385A_P_2_M_0,
2014   VEX_W_0F3878_P_2,
2015   VEX_W_0F3879_P_2,
2016   VEX_W_0F38CF_P_2,
2017   VEX_W_0F3A00_P_2,
2018   VEX_W_0F3A01_P_2,
2019   VEX_W_0F3A02_P_2,
2020   VEX_W_0F3A04_P_2,
2021   VEX_W_0F3A05_P_2,
2022   VEX_W_0F3A06_P_2,
2023   VEX_W_0F3A18_P_2,
2024   VEX_W_0F3A19_P_2,
2025   VEX_W_0F3A30_P_2_LEN_0,
2026   VEX_W_0F3A31_P_2_LEN_0,
2027   VEX_W_0F3A32_P_2_LEN_0,
2028   VEX_W_0F3A33_P_2_LEN_0,
2029   VEX_W_0F3A38_P_2,
2030   VEX_W_0F3A39_P_2,
2031   VEX_W_0F3A46_P_2,
2032   VEX_W_0F3A48_P_2,
2033   VEX_W_0F3A49_P_2,
2034   VEX_W_0F3A4A_P_2,
2035   VEX_W_0F3A4B_P_2,
2036   VEX_W_0F3A4C_P_2,
2037   VEX_W_0F3ACE_P_2,
2038   VEX_W_0F3ACF_P_2,
2039
2040   EVEX_W_0F10_P_1,
2041   EVEX_W_0F10_P_3,
2042   EVEX_W_0F11_P_1,
2043   EVEX_W_0F11_P_3,
2044   EVEX_W_0F12_P_0_M_1,
2045   EVEX_W_0F12_P_1,
2046   EVEX_W_0F12_P_3,
2047   EVEX_W_0F16_P_0_M_1,
2048   EVEX_W_0F16_P_1,
2049   EVEX_W_0F2A_P_3,
2050   EVEX_W_0F51_P_1,
2051   EVEX_W_0F51_P_3,
2052   EVEX_W_0F58_P_1,
2053   EVEX_W_0F58_P_3,
2054   EVEX_W_0F59_P_1,
2055   EVEX_W_0F59_P_3,
2056   EVEX_W_0F5A_P_0,
2057   EVEX_W_0F5A_P_1,
2058   EVEX_W_0F5A_P_2,
2059   EVEX_W_0F5A_P_3,
2060   EVEX_W_0F5B_P_0,
2061   EVEX_W_0F5B_P_1,
2062   EVEX_W_0F5B_P_2,
2063   EVEX_W_0F5C_P_1,
2064   EVEX_W_0F5C_P_3,
2065   EVEX_W_0F5D_P_1,
2066   EVEX_W_0F5D_P_3,
2067   EVEX_W_0F5E_P_1,
2068   EVEX_W_0F5E_P_3,
2069   EVEX_W_0F5F_P_1,
2070   EVEX_W_0F5F_P_3,
2071   EVEX_W_0F62_P_2,
2072   EVEX_W_0F66_P_2,
2073   EVEX_W_0F6A_P_2,
2074   EVEX_W_0F6B_P_2,
2075   EVEX_W_0F6C_P_2,
2076   EVEX_W_0F6D_P_2,
2077   EVEX_W_0F6F_P_1,
2078   EVEX_W_0F6F_P_2,
2079   EVEX_W_0F6F_P_3,
2080   EVEX_W_0F70_P_2,
2081   EVEX_W_0F72_R_2_P_2,
2082   EVEX_W_0F72_R_6_P_2,
2083   EVEX_W_0F73_R_2_P_2,
2084   EVEX_W_0F73_R_6_P_2,
2085   EVEX_W_0F76_P_2,
2086   EVEX_W_0F78_P_0,
2087   EVEX_W_0F78_P_2,
2088   EVEX_W_0F79_P_0,
2089   EVEX_W_0F79_P_2,
2090   EVEX_W_0F7A_P_1,
2091   EVEX_W_0F7A_P_2,
2092   EVEX_W_0F7A_P_3,
2093   EVEX_W_0F7B_P_2,
2094   EVEX_W_0F7B_P_3,
2095   EVEX_W_0F7E_P_1,
2096   EVEX_W_0F7F_P_1,
2097   EVEX_W_0F7F_P_2,
2098   EVEX_W_0F7F_P_3,
2099   EVEX_W_0FC2_P_1,
2100   EVEX_W_0FC2_P_3,
2101   EVEX_W_0FD2_P_2,
2102   EVEX_W_0FD3_P_2,
2103   EVEX_W_0FD4_P_2,
2104   EVEX_W_0FD6_P_2,
2105   EVEX_W_0FE6_P_1,
2106   EVEX_W_0FE6_P_2,
2107   EVEX_W_0FE6_P_3,
2108   EVEX_W_0FE7_P_2,
2109   EVEX_W_0FF2_P_2,
2110   EVEX_W_0FF3_P_2,
2111   EVEX_W_0FF4_P_2,
2112   EVEX_W_0FFA_P_2,
2113   EVEX_W_0FFB_P_2,
2114   EVEX_W_0FFE_P_2,
2115   EVEX_W_0F380C_P_2,
2116   EVEX_W_0F380D_P_2,
2117   EVEX_W_0F3810_P_1,
2118   EVEX_W_0F3810_P_2,
2119   EVEX_W_0F3811_P_1,
2120   EVEX_W_0F3811_P_2,
2121   EVEX_W_0F3812_P_1,
2122   EVEX_W_0F3812_P_2,
2123   EVEX_W_0F3813_P_1,
2124   EVEX_W_0F3813_P_2,
2125   EVEX_W_0F3814_P_1,
2126   EVEX_W_0F3815_P_1,
2127   EVEX_W_0F3818_P_2,
2128   EVEX_W_0F3819_P_2,
2129   EVEX_W_0F381A_P_2,
2130   EVEX_W_0F381B_P_2,
2131   EVEX_W_0F381E_P_2,
2132   EVEX_W_0F381F_P_2,
2133   EVEX_W_0F3820_P_1,
2134   EVEX_W_0F3821_P_1,
2135   EVEX_W_0F3822_P_1,
2136   EVEX_W_0F3823_P_1,
2137   EVEX_W_0F3824_P_1,
2138   EVEX_W_0F3825_P_1,
2139   EVEX_W_0F3825_P_2,
2140   EVEX_W_0F3826_P_1,
2141   EVEX_W_0F3826_P_2,
2142   EVEX_W_0F3828_P_1,
2143   EVEX_W_0F3828_P_2,
2144   EVEX_W_0F3829_P_1,
2145   EVEX_W_0F3829_P_2,
2146   EVEX_W_0F382A_P_1,
2147   EVEX_W_0F382A_P_2,
2148   EVEX_W_0F382B_P_2,
2149   EVEX_W_0F3830_P_1,
2150   EVEX_W_0F3831_P_1,
2151   EVEX_W_0F3832_P_1,
2152   EVEX_W_0F3833_P_1,
2153   EVEX_W_0F3834_P_1,
2154   EVEX_W_0F3835_P_1,
2155   EVEX_W_0F3835_P_2,
2156   EVEX_W_0F3837_P_2,
2157   EVEX_W_0F3838_P_1,
2158   EVEX_W_0F3839_P_1,
2159   EVEX_W_0F383A_P_1,
2160   EVEX_W_0F3840_P_2,
2161   EVEX_W_0F3852_P_1,
2162   EVEX_W_0F3854_P_2,
2163   EVEX_W_0F3855_P_2,
2164   EVEX_W_0F3858_P_2,
2165   EVEX_W_0F3859_P_2,
2166   EVEX_W_0F385A_P_2,
2167   EVEX_W_0F385B_P_2,
2168   EVEX_W_0F3862_P_2,
2169   EVEX_W_0F3863_P_2,
2170   EVEX_W_0F3866_P_2,
2171   EVEX_W_0F3868_P_3,
2172   EVEX_W_0F3870_P_2,
2173   EVEX_W_0F3871_P_2,
2174   EVEX_W_0F3872_P_1,
2175   EVEX_W_0F3872_P_2,
2176   EVEX_W_0F3872_P_3,
2177   EVEX_W_0F3873_P_2,
2178   EVEX_W_0F3875_P_2,
2179   EVEX_W_0F3878_P_2,
2180   EVEX_W_0F3879_P_2,
2181   EVEX_W_0F387A_P_2,
2182   EVEX_W_0F387B_P_2,
2183   EVEX_W_0F387D_P_2,
2184   EVEX_W_0F3883_P_2,
2185   EVEX_W_0F388D_P_2,
2186   EVEX_W_0F3891_P_2,
2187   EVEX_W_0F3893_P_2,
2188   EVEX_W_0F38A1_P_2,
2189   EVEX_W_0F38A3_P_2,
2190   EVEX_W_0F38C7_R_1_P_2,
2191   EVEX_W_0F38C7_R_2_P_2,
2192   EVEX_W_0F38C7_R_5_P_2,
2193   EVEX_W_0F38C7_R_6_P_2,
2194
2195   EVEX_W_0F3A00_P_2,
2196   EVEX_W_0F3A01_P_2,
2197   EVEX_W_0F3A04_P_2,
2198   EVEX_W_0F3A05_P_2,
2199   EVEX_W_0F3A08_P_2,
2200   EVEX_W_0F3A09_P_2,
2201   EVEX_W_0F3A0A_P_2,
2202   EVEX_W_0F3A0B_P_2,
2203   EVEX_W_0F3A18_P_2,
2204   EVEX_W_0F3A19_P_2,
2205   EVEX_W_0F3A1A_P_2,
2206   EVEX_W_0F3A1B_P_2,
2207   EVEX_W_0F3A1D_P_2,
2208   EVEX_W_0F3A21_P_2,
2209   EVEX_W_0F3A23_P_2,
2210   EVEX_W_0F3A38_P_2,
2211   EVEX_W_0F3A39_P_2,
2212   EVEX_W_0F3A3A_P_2,
2213   EVEX_W_0F3A3B_P_2,
2214   EVEX_W_0F3A3E_P_2,
2215   EVEX_W_0F3A3F_P_2,
2216   EVEX_W_0F3A42_P_2,
2217   EVEX_W_0F3A43_P_2,
2218   EVEX_W_0F3A50_P_2,
2219   EVEX_W_0F3A51_P_2,
2220   EVEX_W_0F3A56_P_2,
2221   EVEX_W_0F3A57_P_2,
2222   EVEX_W_0F3A66_P_2,
2223   EVEX_W_0F3A67_P_2,
2224   EVEX_W_0F3A70_P_2,
2225   EVEX_W_0F3A71_P_2,
2226   EVEX_W_0F3A72_P_2,
2227   EVEX_W_0F3A73_P_2,
2228   EVEX_W_0F3ACE_P_2,
2229   EVEX_W_0F3ACF_P_2
2230 };
2231
2232 typedef void (*op_rtn) (int bytemode, int sizeflag);
2233
2234 struct dis386 {
2235   const char *name;
2236   struct
2237     {
2238       op_rtn rtn;
2239       int bytemode;
2240     } op[MAX_OPERANDS];
2241   unsigned int prefix_requirement;
2242 };
2243
2244 /* Upper case letters in the instruction names here are macros.
2245    'A' => print 'b' if no register operands or suffix_always is true
2246    'B' => print 'b' if suffix_always is true
2247    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2248           size prefix
2249    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2250           suffix_always is true
2251    'E' => print 'e' if 32-bit form of jcxz
2252    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2253    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2254    'H' => print ",pt" or ",pn" branch hint
2255    'I' => honor following macro letter even in Intel mode (implemented only
2256           for some of the macro letters)
2257    'J' => print 'l'
2258    'K' => print 'd' or 'q' if rex prefix is present.
2259    'L' => print 'l' if suffix_always is true
2260    'M' => print 'r' if intel_mnemonic is false.
2261    'N' => print 'n' if instruction has no wait "prefix"
2262    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2263    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2264           or suffix_always is true.  print 'q' if rex prefix is present.
2265    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2266           is true
2267    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2268    'S' => print 'w', 'l' or 'q' if suffix_always is true
2269    'T' => print 'q' in 64bit mode if instruction has no operand size
2270           prefix and behave as 'P' otherwise
2271    'U' => print 'q' in 64bit mode if instruction has no operand size
2272           prefix and behave as 'Q' otherwise
2273    'V' => print 'q' in 64bit mode if instruction has no operand size
2274           prefix and behave as 'S' otherwise
2275    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2276    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2277    'Y' unused.
2278    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2279    '!' => change condition from true to false or from false to true.
2280    '%' => add 1 upper case letter to the macro.
2281    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2282           prefix or suffix_always is true (lcall/ljmp).
2283    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2284           on operand size prefix.
2285    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2286           has no operand size prefix for AMD64 ISA, behave as 'P'
2287           otherwise
2288
2289    2 upper case letter macros:
2290    "XY" => print 'x' or 'y' if suffix_always is true or no register
2291            operands and no broadcast.
2292    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2293            register operands and no broadcast.
2294    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2295    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2296            or suffix_always is true
2297    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2298    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2299    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2300    "LW" => print 'd', 'q' depending on the VEX.W bit
2301    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2302            an operand size prefix, or suffix_always is true.  print
2303            'q' if rex prefix is present.
2304
2305    Many of the above letters print nothing in Intel mode.  See "putop"
2306    for the details.
2307
2308    Braces '{' and '}', and vertical bars '|', indicate alternative
2309    mnemonic strings for AT&T and Intel.  */
2310
2311 static const struct dis386 dis386[] = {
2312   /* 00 */
2313   { "addB",             { Ebh1, Gb }, 0 },
2314   { "addS",             { Evh1, Gv }, 0 },
2315   { "addB",             { Gb, EbS }, 0 },
2316   { "addS",             { Gv, EvS }, 0 },
2317   { "addB",             { AL, Ib }, 0 },
2318   { "addS",             { eAX, Iv }, 0 },
2319   { X86_64_TABLE (X86_64_06) },
2320   { X86_64_TABLE (X86_64_07) },
2321   /* 08 */
2322   { "orB",              { Ebh1, Gb }, 0 },
2323   { "orS",              { Evh1, Gv }, 0 },
2324   { "orB",              { Gb, EbS }, 0 },
2325   { "orS",              { Gv, EvS }, 0 },
2326   { "orB",              { AL, Ib }, 0 },
2327   { "orS",              { eAX, Iv }, 0 },
2328   { X86_64_TABLE (X86_64_0E) },
2329   { Bad_Opcode },       /* 0x0f extended opcode escape */
2330   /* 10 */
2331   { "adcB",             { Ebh1, Gb }, 0 },
2332   { "adcS",             { Evh1, Gv }, 0 },
2333   { "adcB",             { Gb, EbS }, 0 },
2334   { "adcS",             { Gv, EvS }, 0 },
2335   { "adcB",             { AL, Ib }, 0 },
2336   { "adcS",             { eAX, Iv }, 0 },
2337   { X86_64_TABLE (X86_64_16) },
2338   { X86_64_TABLE (X86_64_17) },
2339   /* 18 */
2340   { "sbbB",             { Ebh1, Gb }, 0 },
2341   { "sbbS",             { Evh1, Gv }, 0 },
2342   { "sbbB",             { Gb, EbS }, 0 },
2343   { "sbbS",             { Gv, EvS }, 0 },
2344   { "sbbB",             { AL, Ib }, 0 },
2345   { "sbbS",             { eAX, Iv }, 0 },
2346   { X86_64_TABLE (X86_64_1E) },
2347   { X86_64_TABLE (X86_64_1F) },
2348   /* 20 */
2349   { "andB",             { Ebh1, Gb }, 0 },
2350   { "andS",             { Evh1, Gv }, 0 },
2351   { "andB",             { Gb, EbS }, 0 },
2352   { "andS",             { Gv, EvS }, 0 },
2353   { "andB",             { AL, Ib }, 0 },
2354   { "andS",             { eAX, Iv }, 0 },
2355   { Bad_Opcode },       /* SEG ES prefix */
2356   { X86_64_TABLE (X86_64_27) },
2357   /* 28 */
2358   { "subB",             { Ebh1, Gb }, 0 },
2359   { "subS",             { Evh1, Gv }, 0 },
2360   { "subB",             { Gb, EbS }, 0 },
2361   { "subS",             { Gv, EvS }, 0 },
2362   { "subB",             { AL, Ib }, 0 },
2363   { "subS",             { eAX, Iv }, 0 },
2364   { Bad_Opcode },       /* SEG CS prefix */
2365   { X86_64_TABLE (X86_64_2F) },
2366   /* 30 */
2367   { "xorB",             { Ebh1, Gb }, 0 },
2368   { "xorS",             { Evh1, Gv }, 0 },
2369   { "xorB",             { Gb, EbS }, 0 },
2370   { "xorS",             { Gv, EvS }, 0 },
2371   { "xorB",             { AL, Ib }, 0 },
2372   { "xorS",             { eAX, Iv }, 0 },
2373   { Bad_Opcode },       /* SEG SS prefix */
2374   { X86_64_TABLE (X86_64_37) },
2375   /* 38 */
2376   { "cmpB",             { Eb, Gb }, 0 },
2377   { "cmpS",             { Ev, Gv }, 0 },
2378   { "cmpB",             { Gb, EbS }, 0 },
2379   { "cmpS",             { Gv, EvS }, 0 },
2380   { "cmpB",             { AL, Ib }, 0 },
2381   { "cmpS",             { eAX, Iv }, 0 },
2382   { Bad_Opcode },       /* SEG DS prefix */
2383   { X86_64_TABLE (X86_64_3F) },
2384   /* 40 */
2385   { "inc{S|}",          { RMeAX }, 0 },
2386   { "inc{S|}",          { RMeCX }, 0 },
2387   { "inc{S|}",          { RMeDX }, 0 },
2388   { "inc{S|}",          { RMeBX }, 0 },
2389   { "inc{S|}",          { RMeSP }, 0 },
2390   { "inc{S|}",          { RMeBP }, 0 },
2391   { "inc{S|}",          { RMeSI }, 0 },
2392   { "inc{S|}",          { RMeDI }, 0 },
2393   /* 48 */
2394   { "dec{S|}",          { RMeAX }, 0 },
2395   { "dec{S|}",          { RMeCX }, 0 },
2396   { "dec{S|}",          { RMeDX }, 0 },
2397   { "dec{S|}",          { RMeBX }, 0 },
2398   { "dec{S|}",          { RMeSP }, 0 },
2399   { "dec{S|}",          { RMeBP }, 0 },
2400   { "dec{S|}",          { RMeSI }, 0 },
2401   { "dec{S|}",          { RMeDI }, 0 },
2402   /* 50 */
2403   { "pushV",            { RMrAX }, 0 },
2404   { "pushV",            { RMrCX }, 0 },
2405   { "pushV",            { RMrDX }, 0 },
2406   { "pushV",            { RMrBX }, 0 },
2407   { "pushV",            { RMrSP }, 0 },
2408   { "pushV",            { RMrBP }, 0 },
2409   { "pushV",            { RMrSI }, 0 },
2410   { "pushV",            { RMrDI }, 0 },
2411   /* 58 */
2412   { "popV",             { RMrAX }, 0 },
2413   { "popV",             { RMrCX }, 0 },
2414   { "popV",             { RMrDX }, 0 },
2415   { "popV",             { RMrBX }, 0 },
2416   { "popV",             { RMrSP }, 0 },
2417   { "popV",             { RMrBP }, 0 },
2418   { "popV",             { RMrSI }, 0 },
2419   { "popV",             { RMrDI }, 0 },
2420   /* 60 */
2421   { X86_64_TABLE (X86_64_60) },
2422   { X86_64_TABLE (X86_64_61) },
2423   { X86_64_TABLE (X86_64_62) },
2424   { X86_64_TABLE (X86_64_63) },
2425   { Bad_Opcode },       /* seg fs */
2426   { Bad_Opcode },       /* seg gs */
2427   { Bad_Opcode },       /* op size prefix */
2428   { Bad_Opcode },       /* adr size prefix */
2429   /* 68 */
2430   { "pushT",            { sIv }, 0 },
2431   { "imulS",            { Gv, Ev, Iv }, 0 },
2432   { "pushT",            { sIbT }, 0 },
2433   { "imulS",            { Gv, Ev, sIb }, 0 },
2434   { "ins{b|}",          { Ybr, indirDX }, 0 },
2435   { X86_64_TABLE (X86_64_6D) },
2436   { "outs{b|}",         { indirDXr, Xb }, 0 },
2437   { X86_64_TABLE (X86_64_6F) },
2438   /* 70 */
2439   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2440   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2441   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2442   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2443   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2444   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2445   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2446   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2447   /* 78 */
2448   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2449   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2450   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2451   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2452   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2453   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2454   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2455   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2456   /* 80 */
2457   { REG_TABLE (REG_80) },
2458   { REG_TABLE (REG_81) },
2459   { X86_64_TABLE (X86_64_82) },
2460   { REG_TABLE (REG_83) },
2461   { "testB",            { Eb, Gb }, 0 },
2462   { "testS",            { Ev, Gv }, 0 },
2463   { "xchgB",            { Ebh2, Gb }, 0 },
2464   { "xchgS",            { Evh2, Gv }, 0 },
2465   /* 88 */
2466   { "movB",             { Ebh3, Gb }, 0 },
2467   { "movS",             { Evh3, Gv }, 0 },
2468   { "movB",             { Gb, EbS }, 0 },
2469   { "movS",             { Gv, EvS }, 0 },
2470   { "movD",             { Sv, Sw }, 0 },
2471   { MOD_TABLE (MOD_8D) },
2472   { "movD",             { Sw, Sv }, 0 },
2473   { REG_TABLE (REG_8F) },
2474   /* 90 */
2475   { PREFIX_TABLE (PREFIX_90) },
2476   { "xchgS",            { RMeCX, eAX }, 0 },
2477   { "xchgS",            { RMeDX, eAX }, 0 },
2478   { "xchgS",            { RMeBX, eAX }, 0 },
2479   { "xchgS",            { RMeSP, eAX }, 0 },
2480   { "xchgS",            { RMeBP, eAX }, 0 },
2481   { "xchgS",            { RMeSI, eAX }, 0 },
2482   { "xchgS",            { RMeDI, eAX }, 0 },
2483   /* 98 */
2484   { "cW{t|}R",          { XX }, 0 },
2485   { "cR{t|}O",          { XX }, 0 },
2486   { X86_64_TABLE (X86_64_9A) },
2487   { Bad_Opcode },       /* fwait */
2488   { "pushfT",           { XX }, 0 },
2489   { "popfT",            { XX }, 0 },
2490   { "sahf",             { XX }, 0 },
2491   { "lahf",             { XX }, 0 },
2492   /* a0 */
2493   { "mov%LB",           { AL, Ob }, 0 },
2494   { "mov%LS",           { eAX, Ov }, 0 },
2495   { "mov%LB",           { Ob, AL }, 0 },
2496   { "mov%LS",           { Ov, eAX }, 0 },
2497   { "movs{b|}",         { Ybr, Xb }, 0 },
2498   { "movs{R|}",         { Yvr, Xv }, 0 },
2499   { "cmps{b|}",         { Xb, Yb }, 0 },
2500   { "cmps{R|}",         { Xv, Yv }, 0 },
2501   /* a8 */
2502   { "testB",            { AL, Ib }, 0 },
2503   { "testS",            { eAX, Iv }, 0 },
2504   { "stosB",            { Ybr, AL }, 0 },
2505   { "stosS",            { Yvr, eAX }, 0 },
2506   { "lodsB",            { ALr, Xb }, 0 },
2507   { "lodsS",            { eAXr, Xv }, 0 },
2508   { "scasB",            { AL, Yb }, 0 },
2509   { "scasS",            { eAX, Yv }, 0 },
2510   /* b0 */
2511   { "movB",             { RMAL, Ib }, 0 },
2512   { "movB",             { RMCL, Ib }, 0 },
2513   { "movB",             { RMDL, Ib }, 0 },
2514   { "movB",             { RMBL, Ib }, 0 },
2515   { "movB",             { RMAH, Ib }, 0 },
2516   { "movB",             { RMCH, Ib }, 0 },
2517   { "movB",             { RMDH, Ib }, 0 },
2518   { "movB",             { RMBH, Ib }, 0 },
2519   /* b8 */
2520   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2521   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2522   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2523   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2524   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2525   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2526   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2527   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2528   /* c0 */
2529   { REG_TABLE (REG_C0) },
2530   { REG_TABLE (REG_C1) },
2531   { X86_64_TABLE (X86_64_C2) },
2532   { X86_64_TABLE (X86_64_C3) },
2533   { X86_64_TABLE (X86_64_C4) },
2534   { X86_64_TABLE (X86_64_C5) },
2535   { REG_TABLE (REG_C6) },
2536   { REG_TABLE (REG_C7) },
2537   /* c8 */
2538   { "enterT",           { Iw, Ib }, 0 },
2539   { "leaveT",           { XX }, 0 },
2540   { "Jret{|f}P",        { Iw }, 0 },
2541   { "Jret{|f}P",        { XX }, 0 },
2542   { "int3",             { XX }, 0 },
2543   { "int",              { Ib }, 0 },
2544   { X86_64_TABLE (X86_64_CE) },
2545   { "iret%LP",          { XX }, 0 },
2546   /* d0 */
2547   { REG_TABLE (REG_D0) },
2548   { REG_TABLE (REG_D1) },
2549   { REG_TABLE (REG_D2) },
2550   { REG_TABLE (REG_D3) },
2551   { X86_64_TABLE (X86_64_D4) },
2552   { X86_64_TABLE (X86_64_D5) },
2553   { Bad_Opcode },
2554   { "xlat",             { DSBX }, 0 },
2555   /* d8 */
2556   { FLOAT },
2557   { FLOAT },
2558   { FLOAT },
2559   { FLOAT },
2560   { FLOAT },
2561   { FLOAT },
2562   { FLOAT },
2563   { FLOAT },
2564   /* e0 */
2565   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2566   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2567   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2568   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2569   { "inB",              { AL, Ib }, 0 },
2570   { "inG",              { zAX, Ib }, 0 },
2571   { "outB",             { Ib, AL }, 0 },
2572   { "outG",             { Ib, zAX }, 0 },
2573   /* e8 */
2574   { X86_64_TABLE (X86_64_E8) },
2575   { X86_64_TABLE (X86_64_E9) },
2576   { X86_64_TABLE (X86_64_EA) },
2577   { "jmp",              { Jb, BND }, 0 },
2578   { "inB",              { AL, indirDX }, 0 },
2579   { "inG",              { zAX, indirDX }, 0 },
2580   { "outB",             { indirDX, AL }, 0 },
2581   { "outG",             { indirDX, zAX }, 0 },
2582   /* f0 */
2583   { Bad_Opcode },       /* lock prefix */
2584   { "icebp",            { XX }, 0 },
2585   { Bad_Opcode },       /* repne */
2586   { Bad_Opcode },       /* repz */
2587   { "hlt",              { XX }, 0 },
2588   { "cmc",              { XX }, 0 },
2589   { REG_TABLE (REG_F6) },
2590   { REG_TABLE (REG_F7) },
2591   /* f8 */
2592   { "clc",              { XX }, 0 },
2593   { "stc",              { XX }, 0 },
2594   { "cli",              { XX }, 0 },
2595   { "sti",              { XX }, 0 },
2596   { "cld",              { XX }, 0 },
2597   { "std",              { XX }, 0 },
2598   { REG_TABLE (REG_FE) },
2599   { REG_TABLE (REG_FF) },
2600 };
2601
2602 static const struct dis386 dis386_twobyte[] = {
2603   /* 00 */
2604   { REG_TABLE (REG_0F00 ) },
2605   { REG_TABLE (REG_0F01 ) },
2606   { "larS",             { Gv, Ew }, 0 },
2607   { "lslS",             { Gv, Ew }, 0 },
2608   { Bad_Opcode },
2609   { "syscall",          { XX }, 0 },
2610   { "clts",             { XX }, 0 },
2611   { "sysret%LP",                { XX }, 0 },
2612   /* 08 */
2613   { "invd",             { XX }, 0 },
2614   { PREFIX_TABLE (PREFIX_0F09) },
2615   { Bad_Opcode },
2616   { "ud2",              { XX }, 0 },
2617   { Bad_Opcode },
2618   { REG_TABLE (REG_0F0D) },
2619   { "femms",            { XX }, 0 },
2620   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2621   /* 10 */
2622   { PREFIX_TABLE (PREFIX_0F10) },
2623   { PREFIX_TABLE (PREFIX_0F11) },
2624   { PREFIX_TABLE (PREFIX_0F12) },
2625   { MOD_TABLE (MOD_0F13) },
2626   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2627   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2628   { PREFIX_TABLE (PREFIX_0F16) },
2629   { MOD_TABLE (MOD_0F17) },
2630   /* 18 */
2631   { REG_TABLE (REG_0F18) },
2632   { "nopQ",             { Ev }, 0 },
2633   { PREFIX_TABLE (PREFIX_0F1A) },
2634   { PREFIX_TABLE (PREFIX_0F1B) },
2635   { PREFIX_TABLE (PREFIX_0F1C) },
2636   { "nopQ",             { Ev }, 0 },
2637   { PREFIX_TABLE (PREFIX_0F1E) },
2638   { "nopQ",             { Ev }, 0 },
2639   /* 20 */
2640   { "movZ",             { Rm, Cm }, 0 },
2641   { "movZ",             { Rm, Dm }, 0 },
2642   { "movZ",             { Cm, Rm }, 0 },
2643   { "movZ",             { Dm, Rm }, 0 },
2644   { MOD_TABLE (MOD_0F24) },
2645   { Bad_Opcode },
2646   { MOD_TABLE (MOD_0F26) },
2647   { Bad_Opcode },
2648   /* 28 */
2649   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2650   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2651   { PREFIX_TABLE (PREFIX_0F2A) },
2652   { PREFIX_TABLE (PREFIX_0F2B) },
2653   { PREFIX_TABLE (PREFIX_0F2C) },
2654   { PREFIX_TABLE (PREFIX_0F2D) },
2655   { PREFIX_TABLE (PREFIX_0F2E) },
2656   { PREFIX_TABLE (PREFIX_0F2F) },
2657   /* 30 */
2658   { "wrmsr",            { XX }, 0 },
2659   { "rdtsc",            { XX }, 0 },
2660   { "rdmsr",            { XX }, 0 },
2661   { "rdpmc",            { XX }, 0 },
2662   { "sysenter",         { SEP }, 0 },
2663   { "sysexit",          { SEP }, 0 },
2664   { Bad_Opcode },
2665   { "getsec",           { XX }, 0 },
2666   /* 38 */
2667   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2668   { Bad_Opcode },
2669   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2670   { Bad_Opcode },
2671   { Bad_Opcode },
2672   { Bad_Opcode },
2673   { Bad_Opcode },
2674   { Bad_Opcode },
2675   /* 40 */
2676   { "cmovoS",           { Gv, Ev }, 0 },
2677   { "cmovnoS",          { Gv, Ev }, 0 },
2678   { "cmovbS",           { Gv, Ev }, 0 },
2679   { "cmovaeS",          { Gv, Ev }, 0 },
2680   { "cmoveS",           { Gv, Ev }, 0 },
2681   { "cmovneS",          { Gv, Ev }, 0 },
2682   { "cmovbeS",          { Gv, Ev }, 0 },
2683   { "cmovaS",           { Gv, Ev }, 0 },
2684   /* 48 */
2685   { "cmovsS",           { Gv, Ev }, 0 },
2686   { "cmovnsS",          { Gv, Ev }, 0 },
2687   { "cmovpS",           { Gv, Ev }, 0 },
2688   { "cmovnpS",          { Gv, Ev }, 0 },
2689   { "cmovlS",           { Gv, Ev }, 0 },
2690   { "cmovgeS",          { Gv, Ev }, 0 },
2691   { "cmovleS",          { Gv, Ev }, 0 },
2692   { "cmovgS",           { Gv, Ev }, 0 },
2693   /* 50 */
2694   { MOD_TABLE (MOD_0F50) },
2695   { PREFIX_TABLE (PREFIX_0F51) },
2696   { PREFIX_TABLE (PREFIX_0F52) },
2697   { PREFIX_TABLE (PREFIX_0F53) },
2698   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2699   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2700   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2701   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2702   /* 58 */
2703   { PREFIX_TABLE (PREFIX_0F58) },
2704   { PREFIX_TABLE (PREFIX_0F59) },
2705   { PREFIX_TABLE (PREFIX_0F5A) },
2706   { PREFIX_TABLE (PREFIX_0F5B) },
2707   { PREFIX_TABLE (PREFIX_0F5C) },
2708   { PREFIX_TABLE (PREFIX_0F5D) },
2709   { PREFIX_TABLE (PREFIX_0F5E) },
2710   { PREFIX_TABLE (PREFIX_0F5F) },
2711   /* 60 */
2712   { PREFIX_TABLE (PREFIX_0F60) },
2713   { PREFIX_TABLE (PREFIX_0F61) },
2714   { PREFIX_TABLE (PREFIX_0F62) },
2715   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2716   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2717   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2718   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2719   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2720   /* 68 */
2721   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2722   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2723   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2724   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2725   { PREFIX_TABLE (PREFIX_0F6C) },
2726   { PREFIX_TABLE (PREFIX_0F6D) },
2727   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2728   { PREFIX_TABLE (PREFIX_0F6F) },
2729   /* 70 */
2730   { PREFIX_TABLE (PREFIX_0F70) },
2731   { REG_TABLE (REG_0F71) },
2732   { REG_TABLE (REG_0F72) },
2733   { REG_TABLE (REG_0F73) },
2734   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2735   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2736   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2737   { "emms",             { XX }, PREFIX_OPCODE },
2738   /* 78 */
2739   { PREFIX_TABLE (PREFIX_0F78) },
2740   { PREFIX_TABLE (PREFIX_0F79) },
2741   { Bad_Opcode },
2742   { Bad_Opcode },
2743   { PREFIX_TABLE (PREFIX_0F7C) },
2744   { PREFIX_TABLE (PREFIX_0F7D) },
2745   { PREFIX_TABLE (PREFIX_0F7E) },
2746   { PREFIX_TABLE (PREFIX_0F7F) },
2747   /* 80 */
2748   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2749   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2750   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2751   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2752   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2753   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2754   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2755   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2756   /* 88 */
2757   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2758   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2759   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2760   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2761   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2762   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2763   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2764   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2765   /* 90 */
2766   { "seto",             { Eb }, 0 },
2767   { "setno",            { Eb }, 0 },
2768   { "setb",             { Eb }, 0 },
2769   { "setae",            { Eb }, 0 },
2770   { "sete",             { Eb }, 0 },
2771   { "setne",            { Eb }, 0 },
2772   { "setbe",            { Eb }, 0 },
2773   { "seta",             { Eb }, 0 },
2774   /* 98 */
2775   { "sets",             { Eb }, 0 },
2776   { "setns",            { Eb }, 0 },
2777   { "setp",             { Eb }, 0 },
2778   { "setnp",            { Eb }, 0 },
2779   { "setl",             { Eb }, 0 },
2780   { "setge",            { Eb }, 0 },
2781   { "setle",            { Eb }, 0 },
2782   { "setg",             { Eb }, 0 },
2783   /* a0 */
2784   { "pushT",            { fs }, 0 },
2785   { "popT",             { fs }, 0 },
2786   { "cpuid",            { XX }, 0 },
2787   { "btS",              { Ev, Gv }, 0 },
2788   { "shldS",            { Ev, Gv, Ib }, 0 },
2789   { "shldS",            { Ev, Gv, CL }, 0 },
2790   { REG_TABLE (REG_0FA6) },
2791   { REG_TABLE (REG_0FA7) },
2792   /* a8 */
2793   { "pushT",            { gs }, 0 },
2794   { "popT",             { gs }, 0 },
2795   { "rsm",              { XX }, 0 },
2796   { "btsS",             { Evh1, Gv }, 0 },
2797   { "shrdS",            { Ev, Gv, Ib }, 0 },
2798   { "shrdS",            { Ev, Gv, CL }, 0 },
2799   { REG_TABLE (REG_0FAE) },
2800   { "imulS",            { Gv, Ev }, 0 },
2801   /* b0 */
2802   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2803   { "cmpxchgS",         { Evh1, Gv }, 0 },
2804   { MOD_TABLE (MOD_0FB2) },
2805   { "btrS",             { Evh1, Gv }, 0 },
2806   { MOD_TABLE (MOD_0FB4) },
2807   { MOD_TABLE (MOD_0FB5) },
2808   { "movz{bR|x}",       { Gv, Eb }, 0 },
2809   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2810   /* b8 */
2811   { PREFIX_TABLE (PREFIX_0FB8) },
2812   { "ud1S",             { Gv, Ev }, 0 },
2813   { REG_TABLE (REG_0FBA) },
2814   { "btcS",             { Evh1, Gv }, 0 },
2815   { PREFIX_TABLE (PREFIX_0FBC) },
2816   { PREFIX_TABLE (PREFIX_0FBD) },
2817   { "movs{bR|x}",       { Gv, Eb }, 0 },
2818   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2819   /* c0 */
2820   { "xaddB",            { Ebh1, Gb }, 0 },
2821   { "xaddS",            { Evh1, Gv }, 0 },
2822   { PREFIX_TABLE (PREFIX_0FC2) },
2823   { MOD_TABLE (MOD_0FC3) },
2824   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2825   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2826   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2827   { REG_TABLE (REG_0FC7) },
2828   /* c8 */
2829   { "bswap",            { RMeAX }, 0 },
2830   { "bswap",            { RMeCX }, 0 },
2831   { "bswap",            { RMeDX }, 0 },
2832   { "bswap",            { RMeBX }, 0 },
2833   { "bswap",            { RMeSP }, 0 },
2834   { "bswap",            { RMeBP }, 0 },
2835   { "bswap",            { RMeSI }, 0 },
2836   { "bswap",            { RMeDI }, 0 },
2837   /* d0 */
2838   { PREFIX_TABLE (PREFIX_0FD0) },
2839   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2840   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2841   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2842   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2843   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2844   { PREFIX_TABLE (PREFIX_0FD6) },
2845   { MOD_TABLE (MOD_0FD7) },
2846   /* d8 */
2847   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2848   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2849   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2850   { "pand",             { MX, EM }, PREFIX_OPCODE },
2851   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2852   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2853   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2854   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2855   /* e0 */
2856   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2857   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2858   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2859   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2860   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2861   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2862   { PREFIX_TABLE (PREFIX_0FE6) },
2863   { PREFIX_TABLE (PREFIX_0FE7) },
2864   /* e8 */
2865   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2866   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2867   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2868   { "por",              { MX, EM }, PREFIX_OPCODE },
2869   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2870   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2871   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2872   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2873   /* f0 */
2874   { PREFIX_TABLE (PREFIX_0FF0) },
2875   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2876   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2877   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2878   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2879   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2880   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2881   { PREFIX_TABLE (PREFIX_0FF7) },
2882   /* f8 */
2883   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2884   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2885   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2886   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2887   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2888   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2889   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2890   { "ud0S",             { Gv, Ev }, 0 },
2891 };
2892
2893 static const unsigned char onebyte_has_modrm[256] = {
2894   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2895   /*       -------------------------------        */
2896   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2897   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2898   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2899   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2900   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2901   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2902   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2903   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2904   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2905   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2906   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2907   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2908   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2909   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2910   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2911   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2912   /*       -------------------------------        */
2913   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2914 };
2915
2916 static const unsigned char twobyte_has_modrm[256] = {
2917   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2918   /*       -------------------------------        */
2919   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2920   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2921   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2922   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2923   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2924   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2925   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2926   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2927   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2928   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2929   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2930   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2931   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2932   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2933   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2934   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2935   /*       -------------------------------        */
2936   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2937 };
2938
2939 static char obuf[100];
2940 static char *obufp;
2941 static char *mnemonicendp;
2942 static char scratchbuf[100];
2943 static unsigned char *start_codep;
2944 static unsigned char *insn_codep;
2945 static unsigned char *codep;
2946 static unsigned char *end_codep;
2947 static int last_lock_prefix;
2948 static int last_repz_prefix;
2949 static int last_repnz_prefix;
2950 static int last_data_prefix;
2951 static int last_addr_prefix;
2952 static int last_rex_prefix;
2953 static int last_seg_prefix;
2954 static int fwait_prefix;
2955 /* The active segment register prefix.  */
2956 static int active_seg_prefix;
2957 #define MAX_CODE_LENGTH 15
2958 /* We can up to 14 prefixes since the maximum instruction length is
2959    15bytes.  */
2960 static int all_prefixes[MAX_CODE_LENGTH - 1];
2961 static disassemble_info *the_info;
2962 static struct
2963   {
2964     int mod;
2965     int reg;
2966     int rm;
2967   }
2968 modrm;
2969 static unsigned char need_modrm;
2970 static struct
2971   {
2972     int scale;
2973     int index;
2974     int base;
2975   }
2976 sib;
2977 static struct
2978   {
2979     int register_specifier;
2980     int length;
2981     int prefix;
2982     int w;
2983     int evex;
2984     int r;
2985     int v;
2986     int mask_register_specifier;
2987     int zeroing;
2988     int ll;
2989     int b;
2990   }
2991 vex;
2992 static unsigned char need_vex;
2993 static unsigned char need_vex_reg;
2994 static unsigned char vex_w_done;
2995
2996 struct op
2997   {
2998     const char *name;
2999     unsigned int len;
3000   };
3001
3002 /* If we are accessing mod/rm/reg without need_modrm set, then the
3003    values are stale.  Hitting this abort likely indicates that you
3004    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3005 #define MODRM_CHECK  if (!need_modrm) abort ()
3006
3007 static const char **names64;
3008 static const char **names32;
3009 static const char **names16;
3010 static const char **names8;
3011 static const char **names8rex;
3012 static const char **names_seg;
3013 static const char *index64;
3014 static const char *index32;
3015 static const char **index16;
3016 static const char **names_bnd;
3017
3018 static const char *intel_names64[] = {
3019   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3020   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3021 };
3022 static const char *intel_names32[] = {
3023   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3024   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3025 };
3026 static const char *intel_names16[] = {
3027   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3028   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3029 };
3030 static const char *intel_names8[] = {
3031   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3032 };
3033 static const char *intel_names8rex[] = {
3034   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3035   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3036 };
3037 static const char *intel_names_seg[] = {
3038   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3039 };
3040 static const char *intel_index64 = "riz";
3041 static const char *intel_index32 = "eiz";
3042 static const char *intel_index16[] = {
3043   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3044 };
3045
3046 static const char *att_names64[] = {
3047   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3048   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3049 };
3050 static const char *att_names32[] = {
3051   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3052   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3053 };
3054 static const char *att_names16[] = {
3055   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3056   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3057 };
3058 static const char *att_names8[] = {
3059   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3060 };
3061 static const char *att_names8rex[] = {
3062   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3063   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3064 };
3065 static const char *att_names_seg[] = {
3066   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3067 };
3068 static const char *att_index64 = "%riz";
3069 static const char *att_index32 = "%eiz";
3070 static const char *att_index16[] = {
3071   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3072 };
3073
3074 static const char **names_mm;
3075 static const char *intel_names_mm[] = {
3076   "mm0", "mm1", "mm2", "mm3",
3077   "mm4", "mm5", "mm6", "mm7"
3078 };
3079 static const char *att_names_mm[] = {
3080   "%mm0", "%mm1", "%mm2", "%mm3",
3081   "%mm4", "%mm5", "%mm6", "%mm7"
3082 };
3083
3084 static const char *intel_names_bnd[] = {
3085   "bnd0", "bnd1", "bnd2", "bnd3"
3086 };
3087
3088 static const char *att_names_bnd[] = {
3089   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3090 };
3091
3092 static const char **names_xmm;
3093 static const char *intel_names_xmm[] = {
3094   "xmm0", "xmm1", "xmm2", "xmm3",
3095   "xmm4", "xmm5", "xmm6", "xmm7",
3096   "xmm8", "xmm9", "xmm10", "xmm11",
3097   "xmm12", "xmm13", "xmm14", "xmm15",
3098   "xmm16", "xmm17", "xmm18", "xmm19",
3099   "xmm20", "xmm21", "xmm22", "xmm23",
3100   "xmm24", "xmm25", "xmm26", "xmm27",
3101   "xmm28", "xmm29", "xmm30", "xmm31"
3102 };
3103 static const char *att_names_xmm[] = {
3104   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3105   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3106   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3107   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3108   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3109   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3110   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3111   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3112 };
3113
3114 static const char **names_ymm;
3115 static const char *intel_names_ymm[] = {
3116   "ymm0", "ymm1", "ymm2", "ymm3",
3117   "ymm4", "ymm5", "ymm6", "ymm7",
3118   "ymm8", "ymm9", "ymm10", "ymm11",
3119   "ymm12", "ymm13", "ymm14", "ymm15",
3120   "ymm16", "ymm17", "ymm18", "ymm19",
3121   "ymm20", "ymm21", "ymm22", "ymm23",
3122   "ymm24", "ymm25", "ymm26", "ymm27",
3123   "ymm28", "ymm29", "ymm30", "ymm31"
3124 };
3125 static const char *att_names_ymm[] = {
3126   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3127   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3128   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3129   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3130   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3131   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3132   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3133   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3134 };
3135
3136 static const char **names_zmm;
3137 static const char *intel_names_zmm[] = {
3138   "zmm0", "zmm1", "zmm2", "zmm3",
3139   "zmm4", "zmm5", "zmm6", "zmm7",
3140   "zmm8", "zmm9", "zmm10", "zmm11",
3141   "zmm12", "zmm13", "zmm14", "zmm15",
3142   "zmm16", "zmm17", "zmm18", "zmm19",
3143   "zmm20", "zmm21", "zmm22", "zmm23",
3144   "zmm24", "zmm25", "zmm26", "zmm27",
3145   "zmm28", "zmm29", "zmm30", "zmm31"
3146 };
3147 static const char *att_names_zmm[] = {
3148   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3149   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3150   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3151   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3152   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3153   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3154   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3155   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3156 };
3157
3158 static const char **names_mask;
3159 static const char *intel_names_mask[] = {
3160   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3161 };
3162 static const char *att_names_mask[] = {
3163   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3164 };
3165
3166 static const char *names_rounding[] =
3167 {
3168   "{rn-sae}",
3169   "{rd-sae}",
3170   "{ru-sae}",
3171   "{rz-sae}"
3172 };
3173
3174 static const struct dis386 reg_table[][8] = {
3175   /* REG_80 */
3176   {
3177     { "addA",   { Ebh1, Ib }, 0 },
3178     { "orA",    { Ebh1, Ib }, 0 },
3179     { "adcA",   { Ebh1, Ib }, 0 },
3180     { "sbbA",   { Ebh1, Ib }, 0 },
3181     { "andA",   { Ebh1, Ib }, 0 },
3182     { "subA",   { Ebh1, Ib }, 0 },
3183     { "xorA",   { Ebh1, Ib }, 0 },
3184     { "cmpA",   { Eb, Ib }, 0 },
3185   },
3186   /* REG_81 */
3187   {
3188     { "addQ",   { Evh1, Iv }, 0 },
3189     { "orQ",    { Evh1, Iv }, 0 },
3190     { "adcQ",   { Evh1, Iv }, 0 },
3191     { "sbbQ",   { Evh1, Iv }, 0 },
3192     { "andQ",   { Evh1, Iv }, 0 },
3193     { "subQ",   { Evh1, Iv }, 0 },
3194     { "xorQ",   { Evh1, Iv }, 0 },
3195     { "cmpQ",   { Ev, Iv }, 0 },
3196   },
3197   /* REG_83 */
3198   {
3199     { "addQ",   { Evh1, sIb }, 0 },
3200     { "orQ",    { Evh1, sIb }, 0 },
3201     { "adcQ",   { Evh1, sIb }, 0 },
3202     { "sbbQ",   { Evh1, sIb }, 0 },
3203     { "andQ",   { Evh1, sIb }, 0 },
3204     { "subQ",   { Evh1, sIb }, 0 },
3205     { "xorQ",   { Evh1, sIb }, 0 },
3206     { "cmpQ",   { Ev, sIb }, 0 },
3207   },
3208   /* REG_8F */
3209   {
3210     { "popU",   { stackEv }, 0 },
3211     { XOP_8F_TABLE (XOP_09) },
3212     { Bad_Opcode },
3213     { Bad_Opcode },
3214     { Bad_Opcode },
3215     { XOP_8F_TABLE (XOP_09) },
3216   },
3217   /* REG_C0 */
3218   {
3219     { "rolA",   { Eb, Ib }, 0 },
3220     { "rorA",   { Eb, Ib }, 0 },
3221     { "rclA",   { Eb, Ib }, 0 },
3222     { "rcrA",   { Eb, Ib }, 0 },
3223     { "shlA",   { Eb, Ib }, 0 },
3224     { "shrA",   { Eb, Ib }, 0 },
3225     { "shlA",   { Eb, Ib }, 0 },
3226     { "sarA",   { Eb, Ib }, 0 },
3227   },
3228   /* REG_C1 */
3229   {
3230     { "rolQ",   { Ev, Ib }, 0 },
3231     { "rorQ",   { Ev, Ib }, 0 },
3232     { "rclQ",   { Ev, Ib }, 0 },
3233     { "rcrQ",   { Ev, Ib }, 0 },
3234     { "shlQ",   { Ev, Ib }, 0 },
3235     { "shrQ",   { Ev, Ib }, 0 },
3236     { "shlQ",   { Ev, Ib }, 0 },
3237     { "sarQ",   { Ev, Ib }, 0 },
3238   },
3239   /* REG_C6 */
3240   {
3241     { "movA",   { Ebh3, Ib }, 0 },
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { Bad_Opcode },
3245     { Bad_Opcode },
3246     { Bad_Opcode },
3247     { Bad_Opcode },
3248     { MOD_TABLE (MOD_C6_REG_7) },
3249   },
3250   /* REG_C7 */
3251   {
3252     { "movQ",   { Evh3, Iv }, 0 },
3253     { Bad_Opcode },
3254     { Bad_Opcode },
3255     { Bad_Opcode },
3256     { Bad_Opcode },
3257     { Bad_Opcode },
3258     { Bad_Opcode },
3259     { MOD_TABLE (MOD_C7_REG_7) },
3260   },
3261   /* REG_D0 */
3262   {
3263     { "rolA",   { Eb, I1 }, 0 },
3264     { "rorA",   { Eb, I1 }, 0 },
3265     { "rclA",   { Eb, I1 }, 0 },
3266     { "rcrA",   { Eb, I1 }, 0 },
3267     { "shlA",   { Eb, I1 }, 0 },
3268     { "shrA",   { Eb, I1 }, 0 },
3269     { "shlA",   { Eb, I1 }, 0 },
3270     { "sarA",   { Eb, I1 }, 0 },
3271   },
3272   /* REG_D1 */
3273   {
3274     { "rolQ",   { Ev, I1 }, 0 },
3275     { "rorQ",   { Ev, I1 }, 0 },
3276     { "rclQ",   { Ev, I1 }, 0 },
3277     { "rcrQ",   { Ev, I1 }, 0 },
3278     { "shlQ",   { Ev, I1 }, 0 },
3279     { "shrQ",   { Ev, I1 }, 0 },
3280     { "shlQ",   { Ev, I1 }, 0 },
3281     { "sarQ",   { Ev, I1 }, 0 },
3282   },
3283   /* REG_D2 */
3284   {
3285     { "rolA",   { Eb, CL }, 0 },
3286     { "rorA",   { Eb, CL }, 0 },
3287     { "rclA",   { Eb, CL }, 0 },
3288     { "rcrA",   { Eb, CL }, 0 },
3289     { "shlA",   { Eb, CL }, 0 },
3290     { "shrA",   { Eb, CL }, 0 },
3291     { "shlA",   { Eb, CL }, 0 },
3292     { "sarA",   { Eb, CL }, 0 },
3293   },
3294   /* REG_D3 */
3295   {
3296     { "rolQ",   { Ev, CL }, 0 },
3297     { "rorQ",   { Ev, CL }, 0 },
3298     { "rclQ",   { Ev, CL }, 0 },
3299     { "rcrQ",   { Ev, CL }, 0 },
3300     { "shlQ",   { Ev, CL }, 0 },
3301     { "shrQ",   { Ev, CL }, 0 },
3302     { "shlQ",   { Ev, CL }, 0 },
3303     { "sarQ",   { Ev, CL }, 0 },
3304   },
3305   /* REG_F6 */
3306   {
3307     { "testA",  { Eb, Ib }, 0 },
3308     { "testA",  { Eb, Ib }, 0 },
3309     { "notA",   { Ebh1 }, 0 },
3310     { "negA",   { Ebh1 }, 0 },
3311     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3312     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3313     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3314     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3315   },
3316   /* REG_F7 */
3317   {
3318     { "testQ",  { Ev, Iv }, 0 },
3319     { "testQ",  { Ev, Iv }, 0 },
3320     { "notQ",   { Evh1 }, 0 },
3321     { "negQ",   { Evh1 }, 0 },
3322     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3323     { "imulQ",  { Ev }, 0 },
3324     { "divQ",   { Ev }, 0 },
3325     { "idivQ",  { Ev }, 0 },
3326   },
3327   /* REG_FE */
3328   {
3329     { "incA",   { Ebh1 }, 0 },
3330     { "decA",   { Ebh1 }, 0 },
3331   },
3332   /* REG_FF */
3333   {
3334     { "incQ",   { Evh1 }, 0 },
3335     { "decQ",   { Evh1 }, 0 },
3336     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3337     { MOD_TABLE (MOD_FF_REG_3) },
3338     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3339     { MOD_TABLE (MOD_FF_REG_5) },
3340     { "pushU",  { stackEv }, 0 },
3341     { Bad_Opcode },
3342   },
3343   /* REG_0F00 */
3344   {
3345     { "sldtD",  { Sv }, 0 },
3346     { "strD",   { Sv }, 0 },
3347     { "lldt",   { Ew }, 0 },
3348     { "ltr",    { Ew }, 0 },
3349     { "verr",   { Ew }, 0 },
3350     { "verw",   { Ew }, 0 },
3351     { Bad_Opcode },
3352     { Bad_Opcode },
3353   },
3354   /* REG_0F01 */
3355   {
3356     { MOD_TABLE (MOD_0F01_REG_0) },
3357     { MOD_TABLE (MOD_0F01_REG_1) },
3358     { MOD_TABLE (MOD_0F01_REG_2) },
3359     { MOD_TABLE (MOD_0F01_REG_3) },
3360     { "smswD",  { Sv }, 0 },
3361     { MOD_TABLE (MOD_0F01_REG_5) },
3362     { "lmsw",   { Ew }, 0 },
3363     { MOD_TABLE (MOD_0F01_REG_7) },
3364   },
3365   /* REG_0F0D */
3366   {
3367     { "prefetch",       { Mb }, 0 },
3368     { "prefetchw",      { Mb }, 0 },
3369     { "prefetchwt1",    { Mb }, 0 },
3370     { "prefetch",       { Mb }, 0 },
3371     { "prefetch",       { Mb }, 0 },
3372     { "prefetch",       { Mb }, 0 },
3373     { "prefetch",       { Mb }, 0 },
3374     { "prefetch",       { Mb }, 0 },
3375   },
3376   /* REG_0F18 */
3377   {
3378     { MOD_TABLE (MOD_0F18_REG_0) },
3379     { MOD_TABLE (MOD_0F18_REG_1) },
3380     { MOD_TABLE (MOD_0F18_REG_2) },
3381     { MOD_TABLE (MOD_0F18_REG_3) },
3382     { MOD_TABLE (MOD_0F18_REG_4) },
3383     { MOD_TABLE (MOD_0F18_REG_5) },
3384     { MOD_TABLE (MOD_0F18_REG_6) },
3385     { MOD_TABLE (MOD_0F18_REG_7) },
3386   },
3387   /* REG_0F1C_P_0_MOD_0 */
3388   {
3389     { "cldemote",       { Mb }, 0 },
3390     { "nopQ",           { Ev }, 0 },
3391     { "nopQ",           { Ev }, 0 },
3392     { "nopQ",           { Ev }, 0 },
3393     { "nopQ",           { Ev }, 0 },
3394     { "nopQ",           { Ev }, 0 },
3395     { "nopQ",           { Ev }, 0 },
3396     { "nopQ",           { Ev }, 0 },
3397   },
3398   /* REG_0F1E_P_1_MOD_3 */
3399   {
3400     { "nopQ",           { Ev }, 0 },
3401     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3402     { "nopQ",           { Ev }, 0 },
3403     { "nopQ",           { Ev }, 0 },
3404     { "nopQ",           { Ev }, 0 },
3405     { "nopQ",           { Ev }, 0 },
3406     { "nopQ",           { Ev }, 0 },
3407     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3408   },
3409   /* REG_0F71 */
3410   {
3411     { Bad_Opcode },
3412     { Bad_Opcode },
3413     { MOD_TABLE (MOD_0F71_REG_2) },
3414     { Bad_Opcode },
3415     { MOD_TABLE (MOD_0F71_REG_4) },
3416     { Bad_Opcode },
3417     { MOD_TABLE (MOD_0F71_REG_6) },
3418   },
3419   /* REG_0F72 */
3420   {
3421     { Bad_Opcode },
3422     { Bad_Opcode },
3423     { MOD_TABLE (MOD_0F72_REG_2) },
3424     { Bad_Opcode },
3425     { MOD_TABLE (MOD_0F72_REG_4) },
3426     { Bad_Opcode },
3427     { MOD_TABLE (MOD_0F72_REG_6) },
3428   },
3429   /* REG_0F73 */
3430   {
3431     { Bad_Opcode },
3432     { Bad_Opcode },
3433     { MOD_TABLE (MOD_0F73_REG_2) },
3434     { MOD_TABLE (MOD_0F73_REG_3) },
3435     { Bad_Opcode },
3436     { Bad_Opcode },
3437     { MOD_TABLE (MOD_0F73_REG_6) },
3438     { MOD_TABLE (MOD_0F73_REG_7) },
3439   },
3440   /* REG_0FA6 */
3441   {
3442     { "montmul",        { { OP_0f07, 0 } }, 0 },
3443     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3444     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3445   },
3446   /* REG_0FA7 */
3447   {
3448     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3449     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3450     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3451     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3452     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3453     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3454   },
3455   /* REG_0FAE */
3456   {
3457     { MOD_TABLE (MOD_0FAE_REG_0) },
3458     { MOD_TABLE (MOD_0FAE_REG_1) },
3459     { MOD_TABLE (MOD_0FAE_REG_2) },
3460     { MOD_TABLE (MOD_0FAE_REG_3) },
3461     { MOD_TABLE (MOD_0FAE_REG_4) },
3462     { MOD_TABLE (MOD_0FAE_REG_5) },
3463     { MOD_TABLE (MOD_0FAE_REG_6) },
3464     { MOD_TABLE (MOD_0FAE_REG_7) },
3465   },
3466   /* REG_0FBA */
3467   {
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { Bad_Opcode },
3472     { "btQ",    { Ev, Ib }, 0 },
3473     { "btsQ",   { Evh1, Ib }, 0 },
3474     { "btrQ",   { Evh1, Ib }, 0 },
3475     { "btcQ",   { Evh1, Ib }, 0 },
3476   },
3477   /* REG_0FC7 */
3478   {
3479     { Bad_Opcode },
3480     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3481     { Bad_Opcode },
3482     { MOD_TABLE (MOD_0FC7_REG_3) },
3483     { MOD_TABLE (MOD_0FC7_REG_4) },
3484     { MOD_TABLE (MOD_0FC7_REG_5) },
3485     { MOD_TABLE (MOD_0FC7_REG_6) },
3486     { MOD_TABLE (MOD_0FC7_REG_7) },
3487   },
3488   /* REG_VEX_0F71 */
3489   {
3490     { Bad_Opcode },
3491     { Bad_Opcode },
3492     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3493     { Bad_Opcode },
3494     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3495     { Bad_Opcode },
3496     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3497   },
3498   /* REG_VEX_0F72 */
3499   {
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3503     { Bad_Opcode },
3504     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3505     { Bad_Opcode },
3506     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3507   },
3508   /* REG_VEX_0F73 */
3509   {
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3513     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3517     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3518   },
3519   /* REG_VEX_0FAE */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3524     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3525   },
3526   /* REG_VEX_0F38F3 */
3527   {
3528     { Bad_Opcode },
3529     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3530     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3531     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3532   },
3533   /* REG_XOP_LWPCB */
3534   {
3535     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3536     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3537   },
3538   /* REG_XOP_LWP */
3539   {
3540     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3541     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3542   },
3543   /* REG_XOP_TBM_01 */
3544   {
3545     { Bad_Opcode },
3546     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3547     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3548     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3549     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3550     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3551     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3552     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3553   },
3554   /* REG_XOP_TBM_02 */
3555   {
3556     { Bad_Opcode },
3557     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3558     { Bad_Opcode },
3559     { Bad_Opcode },
3560     { Bad_Opcode },
3561     { Bad_Opcode },
3562     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3563   },
3564
3565 #include "i386-dis-evex-reg.h"
3566 };
3567
3568 static const struct dis386 prefix_table[][4] = {
3569   /* PREFIX_90 */
3570   {
3571     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3572     { "pause", { XX }, 0 },
3573     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3574     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3575   },
3576
3577   /* PREFIX_0F01_REG_3_MOD_1 */
3578   {
3579     { "vmmcall",        { Skip_MODRM }, 0 },
3580     { "vmgexit",        { Skip_MODRM }, 0 },
3581     { Bad_Opcode },
3582     { "vmgexit",        { Skip_MODRM }, 0 },
3583   },
3584
3585   /* PREFIX_0F01_REG_5_MOD_0 */
3586   {
3587     { Bad_Opcode },
3588     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3589   },
3590
3591   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3592   {
3593     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3594     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3595     { Bad_Opcode },
3596     { "xsuspldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3597   },
3598
3599   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3600   {
3601     { Bad_Opcode },
3602     { Bad_Opcode },
3603     { Bad_Opcode },
3604     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3605   },
3606
3607   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3608   {
3609     { Bad_Opcode },
3610     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3611   },
3612
3613   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3614   {
3615     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3616     { "mcommit",        { Skip_MODRM }, 0 },
3617   },
3618
3619   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3620   {
3621     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3622   },
3623
3624   /* PREFIX_0F09 */
3625   {
3626     { "wbinvd",   { XX }, 0 },
3627     { "wbnoinvd", { XX }, 0 },
3628   },
3629
3630   /* PREFIX_0F10 */
3631   {
3632     { "movups", { XM, EXx }, PREFIX_OPCODE },
3633     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3634     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3635     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3636   },
3637
3638   /* PREFIX_0F11 */
3639   {
3640     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3641     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3642     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3643     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3644   },
3645
3646   /* PREFIX_0F12 */
3647   {
3648     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3649     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3650     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3651     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3652   },
3653
3654   /* PREFIX_0F16 */
3655   {
3656     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3657     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3658     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3659   },
3660
3661   /* PREFIX_0F1A */
3662   {
3663     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3664     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3665     { "bndmov", { Gbnd, Ebnd }, 0 },
3666     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3667   },
3668
3669   /* PREFIX_0F1B */
3670   {
3671     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3672     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3673     { "bndmov", { EbndS, Gbnd }, 0 },
3674     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3675   },
3676
3677   /* PREFIX_0F1C */
3678   {
3679     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3680     { "nopQ",   { Ev }, PREFIX_OPCODE },
3681     { "nopQ",   { Ev }, PREFIX_OPCODE },
3682     { "nopQ",   { Ev }, PREFIX_OPCODE },
3683   },
3684
3685   /* PREFIX_0F1E */
3686   {
3687     { "nopQ",   { Ev }, PREFIX_OPCODE },
3688     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3689     { "nopQ",   { Ev }, PREFIX_OPCODE },
3690     { "nopQ",   { Ev }, PREFIX_OPCODE },
3691   },
3692
3693   /* PREFIX_0F2A */
3694   {
3695     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3696     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3697     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3698     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3699   },
3700
3701   /* PREFIX_0F2B */
3702   {
3703     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3704     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3705     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3706     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3707   },
3708
3709   /* PREFIX_0F2C */
3710   {
3711     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3712     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3713     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3714     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3715   },
3716
3717   /* PREFIX_0F2D */
3718   {
3719     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3720     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3721     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3722     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3723   },
3724
3725   /* PREFIX_0F2E */
3726   {
3727     { "ucomiss",{ XM, EXd }, 0 },
3728     { Bad_Opcode },
3729     { "ucomisd",{ XM, EXq }, 0 },
3730   },
3731
3732   /* PREFIX_0F2F */
3733   {
3734     { "comiss", { XM, EXd }, 0 },
3735     { Bad_Opcode },
3736     { "comisd", { XM, EXq }, 0 },
3737   },
3738
3739   /* PREFIX_0F51 */
3740   {
3741     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3742     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3743     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3744     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3745   },
3746
3747   /* PREFIX_0F52 */
3748   {
3749     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3750     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3751   },
3752
3753   /* PREFIX_0F53 */
3754   {
3755     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3756     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F58 */
3760   {
3761     { "addps", { XM, EXx }, PREFIX_OPCODE },
3762     { "addss", { XM, EXd }, PREFIX_OPCODE },
3763     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3764     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3765   },
3766
3767   /* PREFIX_0F59 */
3768   {
3769     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3770     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3771     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3772     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3773   },
3774
3775   /* PREFIX_0F5A */
3776   {
3777     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3778     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3779     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3780     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3781   },
3782
3783   /* PREFIX_0F5B */
3784   {
3785     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3786     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3787     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3788   },
3789
3790   /* PREFIX_0F5C */
3791   {
3792     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3793     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3794     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3795     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3796   },
3797
3798   /* PREFIX_0F5D */
3799   {
3800     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3801     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3802     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3803     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3804   },
3805
3806   /* PREFIX_0F5E */
3807   {
3808     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3809     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3810     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3811     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3812   },
3813
3814   /* PREFIX_0F5F */
3815   {
3816     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3817     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3818     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3819     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3820   },
3821
3822   /* PREFIX_0F60 */
3823   {
3824     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3825     { Bad_Opcode },
3826     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3827   },
3828
3829   /* PREFIX_0F61 */
3830   {
3831     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3832     { Bad_Opcode },
3833     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3834   },
3835
3836   /* PREFIX_0F62 */
3837   {
3838     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3839     { Bad_Opcode },
3840     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3841   },
3842
3843   /* PREFIX_0F6C */
3844   {
3845     { Bad_Opcode },
3846     { Bad_Opcode },
3847     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3848   },
3849
3850   /* PREFIX_0F6D */
3851   {
3852     { Bad_Opcode },
3853     { Bad_Opcode },
3854     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3855   },
3856
3857   /* PREFIX_0F6F */
3858   {
3859     { "movq",   { MX, EM }, PREFIX_OPCODE },
3860     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3861     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3862   },
3863
3864   /* PREFIX_0F70 */
3865   {
3866     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3867     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3868     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3869     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3870   },
3871
3872   /* PREFIX_0F73_REG_3 */
3873   {
3874     { Bad_Opcode },
3875     { Bad_Opcode },
3876     { "psrldq", { XS, Ib }, 0 },
3877   },
3878
3879   /* PREFIX_0F73_REG_7 */
3880   {
3881     { Bad_Opcode },
3882     { Bad_Opcode },
3883     { "pslldq", { XS, Ib }, 0 },
3884   },
3885
3886   /* PREFIX_0F78 */
3887   {
3888     {"vmread",  { Em, Gm }, 0 },
3889     { Bad_Opcode },
3890     {"extrq",   { XS, Ib, Ib }, 0 },
3891     {"insertq", { XM, XS, Ib, Ib }, 0 },
3892   },
3893
3894   /* PREFIX_0F79 */
3895   {
3896     {"vmwrite", { Gm, Em }, 0 },
3897     { Bad_Opcode },
3898     {"extrq",   { XM, XS }, 0 },
3899     {"insertq", { XM, XS }, 0 },
3900   },
3901
3902   /* PREFIX_0F7C */
3903   {
3904     { Bad_Opcode },
3905     { Bad_Opcode },
3906     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3907     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3908   },
3909
3910   /* PREFIX_0F7D */
3911   {
3912     { Bad_Opcode },
3913     { Bad_Opcode },
3914     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3915     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3916   },
3917
3918   /* PREFIX_0F7E */
3919   {
3920     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3921     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3922     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3923   },
3924
3925   /* PREFIX_0F7F */
3926   {
3927     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3928     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3929     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3930   },
3931
3932   /* PREFIX_0FAE_REG_0_MOD_3 */
3933   {
3934     { Bad_Opcode },
3935     { "rdfsbase", { Ev }, 0 },
3936   },
3937
3938   /* PREFIX_0FAE_REG_1_MOD_3 */
3939   {
3940     { Bad_Opcode },
3941     { "rdgsbase", { Ev }, 0 },
3942   },
3943
3944   /* PREFIX_0FAE_REG_2_MOD_3 */
3945   {
3946     { Bad_Opcode },
3947     { "wrfsbase", { Ev }, 0 },
3948   },
3949
3950   /* PREFIX_0FAE_REG_3_MOD_3 */
3951   {
3952     { Bad_Opcode },
3953     { "wrgsbase", { Ev }, 0 },
3954   },
3955
3956   /* PREFIX_0FAE_REG_4_MOD_0 */
3957   {
3958     { "xsave",  { FXSAVE }, 0 },
3959     { "ptwrite%LQ", { Edq }, 0 },
3960   },
3961
3962   /* PREFIX_0FAE_REG_4_MOD_3 */
3963   {
3964     { Bad_Opcode },
3965     { "ptwrite%LQ", { Edq }, 0 },
3966   },
3967
3968   /* PREFIX_0FAE_REG_5_MOD_0 */
3969   {
3970     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3971   },
3972
3973   /* PREFIX_0FAE_REG_5_MOD_3 */
3974   {
3975     { "lfence",         { Skip_MODRM }, 0 },
3976     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_0FAE_REG_6_MOD_0 */
3980   {
3981     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3982     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3983     { "clwb",   { Mb }, PREFIX_OPCODE },
3984   },
3985
3986   /* PREFIX_0FAE_REG_6_MOD_3 */
3987   {
3988     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3989     { "umonitor",       { Eva }, PREFIX_OPCODE },
3990     { "tpause", { Edq }, PREFIX_OPCODE },
3991     { "umwait", { Edq }, PREFIX_OPCODE },
3992   },
3993
3994   /* PREFIX_0FAE_REG_7_MOD_0 */
3995   {
3996     { "clflush",        { Mb }, 0 },
3997     { Bad_Opcode },
3998     { "clflushopt",     { Mb }, 0 },
3999   },
4000
4001   /* PREFIX_0FB8 */
4002   {
4003     { Bad_Opcode },
4004     { "popcntS", { Gv, Ev }, 0 },
4005   },
4006
4007   /* PREFIX_0FBC */
4008   {
4009     { "bsfS",   { Gv, Ev }, 0 },
4010     { "tzcntS", { Gv, Ev }, 0 },
4011     { "bsfS",   { Gv, Ev }, 0 },
4012   },
4013
4014   /* PREFIX_0FBD */
4015   {
4016     { "bsrS",   { Gv, Ev }, 0 },
4017     { "lzcntS", { Gv, Ev }, 0 },
4018     { "bsrS",   { Gv, Ev }, 0 },
4019   },
4020
4021   /* PREFIX_0FC2 */
4022   {
4023     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4024     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4025     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4026     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4027   },
4028
4029   /* PREFIX_0FC3_MOD_0 */
4030   {
4031     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4032   },
4033
4034   /* PREFIX_0FC7_REG_6_MOD_0 */
4035   {
4036     { "vmptrld",{ Mq }, 0 },
4037     { "vmxon",  { Mq }, 0 },
4038     { "vmclear",{ Mq }, 0 },
4039   },
4040
4041   /* PREFIX_0FC7_REG_6_MOD_3 */
4042   {
4043     { "rdrand", { Ev }, 0 },
4044     { Bad_Opcode },
4045     { "rdrand", { Ev }, 0 }
4046   },
4047
4048   /* PREFIX_0FC7_REG_7_MOD_3 */
4049   {
4050     { "rdseed", { Ev }, 0 },
4051     { "rdpid",  { Em }, 0 },
4052     { "rdseed", { Ev }, 0 },
4053   },
4054
4055   /* PREFIX_0FD0 */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { "addsubpd", { XM, EXx }, 0 },
4060     { "addsubps", { XM, EXx }, 0 },
4061   },
4062
4063   /* PREFIX_0FD6 */
4064   {
4065     { Bad_Opcode },
4066     { "movq2dq",{ XM, MS }, 0 },
4067     { "movq",   { EXqS, XM }, 0 },
4068     { "movdq2q",{ MX, XS }, 0 },
4069   },
4070
4071   /* PREFIX_0FE6 */
4072   {
4073     { Bad_Opcode },
4074     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4075     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4076     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4077   },
4078
4079   /* PREFIX_0FE7 */
4080   {
4081     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4082     { Bad_Opcode },
4083     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4084   },
4085
4086   /* PREFIX_0FF0 */
4087   {
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4092   },
4093
4094   /* PREFIX_0FF7 */
4095   {
4096     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4097     { Bad_Opcode },
4098     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4099   },
4100
4101   /* PREFIX_0F3810 */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4106   },
4107
4108   /* PREFIX_0F3814 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4113   },
4114
4115   /* PREFIX_0F3815 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4120   },
4121
4122   /* PREFIX_0F3817 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4127   },
4128
4129   /* PREFIX_0F3820 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4134   },
4135
4136   /* PREFIX_0F3821 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4141   },
4142
4143   /* PREFIX_0F3822 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4148   },
4149
4150   /* PREFIX_0F3823 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4155   },
4156
4157   /* PREFIX_0F3824 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_0F3825 */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4169   },
4170
4171   /* PREFIX_0F3828 */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4176   },
4177
4178   /* PREFIX_0F3829 */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_0F382A */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4190   },
4191
4192   /* PREFIX_0F382B */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3830 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F3831 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3832 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F3833 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_0F3834 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F3835 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F3837 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F3838 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F3839 */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F383A */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F383B */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F383C */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F383D */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F383E */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F383F */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F3840 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F3841 */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4316   },
4317
4318   /* PREFIX_0F3880 */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F3881 */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4330   },
4331
4332   /* PREFIX_0F3882 */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4337   },
4338
4339   /* PREFIX_0F38C8 */
4340   {
4341     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F38C9 */
4345   {
4346     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4347   },
4348
4349   /* PREFIX_0F38CA */
4350   {
4351     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F38CB */
4355   {
4356     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4357   },
4358
4359   /* PREFIX_0F38CC */
4360   {
4361     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F38CD */
4365   {
4366     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4367   },
4368
4369   /* PREFIX_0F38CF */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F38DB */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F38DC */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F38DD */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4395   },
4396
4397   /* PREFIX_0F38DE */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4402   },
4403
4404   /* PREFIX_0F38DF */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4409   },
4410
4411   /* PREFIX_0F38F0 */
4412   {
4413     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4414     { Bad_Opcode },
4415     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4416     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F38F1 */
4420   {
4421     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4422     { Bad_Opcode },
4423     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4424     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F38F5 */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4432   },
4433
4434   /* PREFIX_0F38F6 */
4435   {
4436     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4437     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4438     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4439     { Bad_Opcode },
4440   },
4441
4442   /* PREFIX_0F38F8 */
4443   {
4444     { Bad_Opcode },
4445     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4446     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4447     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4448   },
4449
4450   /* PREFIX_0F38F9 */
4451   {
4452     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4453   },
4454
4455   /* PREFIX_0F3A08 */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F3A09 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F3A0A */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F3A0B */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F3A0C */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F3A0D */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F3A0E */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3A14 */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3A15 */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3A16 */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3A17 */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3A20 */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F3A21 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F3A22 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F3A40 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4558   },
4559
4560   /* PREFIX_0F3A41 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F3A42 */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4572   },
4573
4574   /* PREFIX_0F3A44 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4579   },
4580
4581   /* PREFIX_0F3A60 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4586   },
4587
4588   /* PREFIX_0F3A61 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F3A62 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4600   },
4601
4602   /* PREFIX_0F3A63 */
4603   {
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4607   },
4608
4609   /* PREFIX_0F3ACC */
4610   {
4611     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4612   },
4613
4614   /* PREFIX_0F3ACE */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4619   },
4620
4621   /* PREFIX_0F3ACF */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4626   },
4627
4628   /* PREFIX_0F3ADF */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4633   },
4634
4635   /* PREFIX_VEX_0F10 */
4636   {
4637     { "vmovups",        { XM, EXx }, 0 },
4638     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4639     { "vmovupd",        { XM, EXx }, 0 },
4640     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4641   },
4642
4643   /* PREFIX_VEX_0F11 */
4644   {
4645     { "vmovups",        { EXxS, XM }, 0 },
4646     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4647     { "vmovupd",        { EXxS, XM }, 0 },
4648     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4649   },
4650
4651   /* PREFIX_VEX_0F12 */
4652   {
4653     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4654     { "vmovsldup",      { XM, EXx }, 0 },
4655     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4656     { "vmovddup",       { XM, EXymmq }, 0 },
4657   },
4658
4659   /* PREFIX_VEX_0F16 */
4660   {
4661     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4662     { "vmovshdup",      { XM, EXx }, 0 },
4663     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4664   },
4665
4666   /* PREFIX_VEX_0F2A */
4667   {
4668     { Bad_Opcode },
4669     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4670     { Bad_Opcode },
4671     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4672   },
4673
4674   /* PREFIX_VEX_0F2C */
4675   {
4676     { Bad_Opcode },
4677     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4678     { Bad_Opcode },
4679     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4680   },
4681
4682   /* PREFIX_VEX_0F2D */
4683   {
4684     { Bad_Opcode },
4685     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4686     { Bad_Opcode },
4687     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4688   },
4689
4690   /* PREFIX_VEX_0F2E */
4691   {
4692     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4693     { Bad_Opcode },
4694     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4695   },
4696
4697   /* PREFIX_VEX_0F2F */
4698   {
4699     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4700     { Bad_Opcode },
4701     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4702   },
4703
4704   /* PREFIX_VEX_0F41 */
4705   {
4706     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4707     { Bad_Opcode },
4708     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4709   },
4710
4711   /* PREFIX_VEX_0F42 */
4712   {
4713     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4714     { Bad_Opcode },
4715     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4716   },
4717
4718   /* PREFIX_VEX_0F44 */
4719   {
4720     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4721     { Bad_Opcode },
4722     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4723   },
4724
4725   /* PREFIX_VEX_0F45 */
4726   {
4727     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4728     { Bad_Opcode },
4729     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4730   },
4731
4732   /* PREFIX_VEX_0F46 */
4733   {
4734     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4735     { Bad_Opcode },
4736     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4737   },
4738
4739   /* PREFIX_VEX_0F47 */
4740   {
4741     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4742     { Bad_Opcode },
4743     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4744   },
4745
4746   /* PREFIX_VEX_0F4A */
4747   {
4748     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4749     { Bad_Opcode },
4750     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4751   },
4752
4753   /* PREFIX_VEX_0F4B */
4754   {
4755     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4756     { Bad_Opcode },
4757     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4758   },
4759
4760   /* PREFIX_VEX_0F51 */
4761   {
4762     { "vsqrtps",        { XM, EXx }, 0 },
4763     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4764     { "vsqrtpd",        { XM, EXx }, 0 },
4765     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4766   },
4767
4768   /* PREFIX_VEX_0F52 */
4769   {
4770     { "vrsqrtps",       { XM, EXx }, 0 },
4771     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4772   },
4773
4774   /* PREFIX_VEX_0F53 */
4775   {
4776     { "vrcpps",         { XM, EXx }, 0 },
4777     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4778   },
4779
4780   /* PREFIX_VEX_0F58 */
4781   {
4782     { "vaddps",         { XM, Vex, EXx }, 0 },
4783     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4784     { "vaddpd",         { XM, Vex, EXx }, 0 },
4785     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4786   },
4787
4788   /* PREFIX_VEX_0F59 */
4789   {
4790     { "vmulps",         { XM, Vex, EXx }, 0 },
4791     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4792     { "vmulpd",         { XM, Vex, EXx }, 0 },
4793     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4794   },
4795
4796   /* PREFIX_VEX_0F5A */
4797   {
4798     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4799     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4800     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4801     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4802   },
4803
4804   /* PREFIX_VEX_0F5B */
4805   {
4806     { "vcvtdq2ps",      { XM, EXx }, 0 },
4807     { "vcvttps2dq",     { XM, EXx }, 0 },
4808     { "vcvtps2dq",      { XM, EXx }, 0 },
4809   },
4810
4811   /* PREFIX_VEX_0F5C */
4812   {
4813     { "vsubps",         { XM, Vex, EXx }, 0 },
4814     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4815     { "vsubpd",         { XM, Vex, EXx }, 0 },
4816     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4817   },
4818
4819   /* PREFIX_VEX_0F5D */
4820   {
4821     { "vminps",         { XM, Vex, EXx }, 0 },
4822     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4823     { "vminpd",         { XM, Vex, EXx }, 0 },
4824     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4825   },
4826
4827   /* PREFIX_VEX_0F5E */
4828   {
4829     { "vdivps",         { XM, Vex, EXx }, 0 },
4830     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4831     { "vdivpd",         { XM, Vex, EXx }, 0 },
4832     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4833   },
4834
4835   /* PREFIX_VEX_0F5F */
4836   {
4837     { "vmaxps",         { XM, Vex, EXx }, 0 },
4838     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4839     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4840     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4841   },
4842
4843   /* PREFIX_VEX_0F60 */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4848   },
4849
4850   /* PREFIX_VEX_0F61 */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4855   },
4856
4857   /* PREFIX_VEX_0F62 */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4862   },
4863
4864   /* PREFIX_VEX_0F63 */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4869   },
4870
4871   /* PREFIX_VEX_0F64 */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4876   },
4877
4878   /* PREFIX_VEX_0F65 */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4883   },
4884
4885   /* PREFIX_VEX_0F66 */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4890   },
4891
4892   /* PREFIX_VEX_0F67 */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4897   },
4898
4899   /* PREFIX_VEX_0F68 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4904   },
4905
4906   /* PREFIX_VEX_0F69 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4911   },
4912
4913   /* PREFIX_VEX_0F6A */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4918   },
4919
4920   /* PREFIX_VEX_0F6B */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4925   },
4926
4927   /* PREFIX_VEX_0F6C */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4932   },
4933
4934   /* PREFIX_VEX_0F6D */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4939   },
4940
4941   /* PREFIX_VEX_0F6E */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_0F6F */
4949   {
4950     { Bad_Opcode },
4951     { "vmovdqu",        { XM, EXx }, 0 },
4952     { "vmovdqa",        { XM, EXx }, 0 },
4953   },
4954
4955   /* PREFIX_VEX_0F70 */
4956   {
4957     { Bad_Opcode },
4958     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4959     { "vpshufd",        { XM, EXx, Ib }, 0 },
4960     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4961   },
4962
4963   /* PREFIX_VEX_0F71_REG_2 */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4968   },
4969
4970   /* PREFIX_VEX_0F71_REG_4 */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { "vpsraw",         { Vex, XS, Ib }, 0 },
4975   },
4976
4977   /* PREFIX_VEX_0F71_REG_6 */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { "vpsllw",         { Vex, XS, Ib }, 0 },
4982   },
4983
4984   /* PREFIX_VEX_0F72_REG_2 */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { "vpsrld",         { Vex, XS, Ib }, 0 },
4989   },
4990
4991   /* PREFIX_VEX_0F72_REG_4 */
4992   {
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { "vpsrad",         { Vex, XS, Ib }, 0 },
4996   },
4997
4998   /* PREFIX_VEX_0F72_REG_6 */
4999   {
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { "vpslld",         { Vex, XS, Ib }, 0 },
5003   },
5004
5005   /* PREFIX_VEX_0F73_REG_2 */
5006   {
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5010   },
5011
5012   /* PREFIX_VEX_0F73_REG_3 */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5017   },
5018
5019   /* PREFIX_VEX_0F73_REG_6 */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { "vpsllq",         { Vex, XS, Ib }, 0 },
5024   },
5025
5026   /* PREFIX_VEX_0F73_REG_7 */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { "vpslldq",        { Vex, XS, Ib }, 0 },
5031   },
5032
5033   /* PREFIX_VEX_0F74 */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5038   },
5039
5040   /* PREFIX_VEX_0F75 */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5045   },
5046
5047   /* PREFIX_VEX_0F76 */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5052   },
5053
5054   /* PREFIX_VEX_0F77 */
5055   {
5056     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5057   },
5058
5059   /* PREFIX_VEX_0F7C */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5064     { "vhaddps",        { XM, Vex, EXx }, 0 },
5065   },
5066
5067   /* PREFIX_VEX_0F7D */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5072     { "vhsubps",        { XM, Vex, EXx }, 0 },
5073   },
5074
5075   /* PREFIX_VEX_0F7E */
5076   {
5077     { Bad_Opcode },
5078     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5079     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5080   },
5081
5082   /* PREFIX_VEX_0F7F */
5083   {
5084     { Bad_Opcode },
5085     { "vmovdqu",        { EXxS, XM }, 0 },
5086     { "vmovdqa",        { EXxS, XM }, 0 },
5087   },
5088
5089   /* PREFIX_VEX_0F90 */
5090   {
5091     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5092     { Bad_Opcode },
5093     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5094   },
5095
5096   /* PREFIX_VEX_0F91 */
5097   {
5098     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5099     { Bad_Opcode },
5100     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5101   },
5102
5103   /* PREFIX_VEX_0F92 */
5104   {
5105     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5106     { Bad_Opcode },
5107     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5108     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5109   },
5110
5111   /* PREFIX_VEX_0F93 */
5112   {
5113     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5114     { Bad_Opcode },
5115     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5116     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5117   },
5118
5119   /* PREFIX_VEX_0F98 */
5120   {
5121     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5122     { Bad_Opcode },
5123     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5124   },
5125
5126   /* PREFIX_VEX_0F99 */
5127   {
5128     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5129     { Bad_Opcode },
5130     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5131   },
5132
5133   /* PREFIX_VEX_0FC2 */
5134   {
5135     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5136     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5137     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5138     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5139   },
5140
5141   /* PREFIX_VEX_0FC4 */
5142   {
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5146   },
5147
5148   /* PREFIX_VEX_0FC5 */
5149   {
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5153   },
5154
5155   /* PREFIX_VEX_0FD0 */
5156   {
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5160     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5161   },
5162
5163   /* PREFIX_VEX_0FD1 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5168   },
5169
5170   /* PREFIX_VEX_0FD2 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5175   },
5176
5177   /* PREFIX_VEX_0FD3 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5182   },
5183
5184   /* PREFIX_VEX_0FD4 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { "vpaddq",         { XM, Vex, EXx }, 0 },
5189   },
5190
5191   /* PREFIX_VEX_0FD5 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { "vpmullw",        { XM, Vex, EXx }, 0 },
5196   },
5197
5198   /* PREFIX_VEX_0FD6 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0FD7 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5210   },
5211
5212   /* PREFIX_VEX_0FD8 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5217   },
5218
5219   /* PREFIX_VEX_0FD9 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5224   },
5225
5226   /* PREFIX_VEX_0FDA */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { "vpminub",        { XM, Vex, EXx }, 0 },
5231   },
5232
5233   /* PREFIX_VEX_0FDB */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { "vpand",          { XM, Vex, EXx }, 0 },
5238   },
5239
5240   /* PREFIX_VEX_0FDC */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5245   },
5246
5247   /* PREFIX_VEX_0FDD */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5252   },
5253
5254   /* PREFIX_VEX_0FDE */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5259   },
5260
5261   /* PREFIX_VEX_0FDF */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { "vpandn",         { XM, Vex, EXx }, 0 },
5266   },
5267
5268   /* PREFIX_VEX_0FE0 */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { "vpavgb",         { XM, Vex, EXx }, 0 },
5273   },
5274
5275   /* PREFIX_VEX_0FE1 */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5280   },
5281
5282   /* PREFIX_VEX_0FE2 */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5287   },
5288
5289   /* PREFIX_VEX_0FE3 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpavgw",         { XM, Vex, EXx }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FE4 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5301   },
5302
5303   /* PREFIX_VEX_0FE5 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5308   },
5309
5310   /* PREFIX_VEX_0FE6 */
5311   {
5312     { Bad_Opcode },
5313     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5314     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5315     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5316   },
5317
5318   /* PREFIX_VEX_0FE7 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5323   },
5324
5325   /* PREFIX_VEX_0FE8 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5330   },
5331
5332   /* PREFIX_VEX_0FE9 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5337   },
5338
5339   /* PREFIX_VEX_0FEA */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { "vpminsw",        { XM, Vex, EXx }, 0 },
5344   },
5345
5346   /* PREFIX_VEX_0FEB */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { "vpor",           { XM, Vex, EXx }, 0 },
5351   },
5352
5353   /* PREFIX_VEX_0FEC */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5358   },
5359
5360   /* PREFIX_VEX_0FED */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5365   },
5366
5367   /* PREFIX_VEX_0FEE */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5372   },
5373
5374   /* PREFIX_VEX_0FEF */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { "vpxor",          { XM, Vex, EXx }, 0 },
5379   },
5380
5381   /* PREFIX_VEX_0FF0 */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5387   },
5388
5389   /* PREFIX_VEX_0FF1 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5394   },
5395
5396   /* PREFIX_VEX_0FF2 */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5401   },
5402
5403   /* PREFIX_VEX_0FF3 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5408   },
5409
5410   /* PREFIX_VEX_0FF4 */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5415   },
5416
5417   /* PREFIX_VEX_0FF5 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5422   },
5423
5424   /* PREFIX_VEX_0FF6 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5429   },
5430
5431   /* PREFIX_VEX_0FF7 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5436   },
5437
5438   /* PREFIX_VEX_0FF8 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { "vpsubb",         { XM, Vex, EXx }, 0 },
5443   },
5444
5445   /* PREFIX_VEX_0FF9 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { "vpsubw",         { XM, Vex, EXx }, 0 },
5450   },
5451
5452   /* PREFIX_VEX_0FFA */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { "vpsubd",         { XM, Vex, EXx }, 0 },
5457   },
5458
5459   /* PREFIX_VEX_0FFB */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { "vpsubq",         { XM, Vex, EXx }, 0 },
5464   },
5465
5466   /* PREFIX_VEX_0FFC */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { "vpaddb",         { XM, Vex, EXx }, 0 },
5471   },
5472
5473   /* PREFIX_VEX_0FFD */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { "vpaddw",         { XM, Vex, EXx }, 0 },
5478   },
5479
5480   /* PREFIX_VEX_0FFE */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { "vpaddd",         { XM, Vex, EXx }, 0 },
5485   },
5486
5487   /* PREFIX_VEX_0F3800 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { "vpshufb",        { XM, Vex, EXx }, 0 },
5492   },
5493
5494   /* PREFIX_VEX_0F3801 */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { "vphaddw",        { XM, Vex, EXx }, 0 },
5499   },
5500
5501   /* PREFIX_VEX_0F3802 */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { "vphaddd",        { XM, Vex, EXx }, 0 },
5506   },
5507
5508   /* PREFIX_VEX_0F3803 */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5513   },
5514
5515   /* PREFIX_VEX_0F3804 */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5520   },
5521
5522   /* PREFIX_VEX_0F3805 */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { "vphsubw",        { XM, Vex, EXx }, 0 },
5527   },
5528
5529   /* PREFIX_VEX_0F3806 */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { "vphsubd",        { XM, Vex, EXx }, 0 },
5534   },
5535
5536   /* PREFIX_VEX_0F3807 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5541   },
5542
5543   /* PREFIX_VEX_0F3808 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vpsignb",        { XM, Vex, EXx }, 0 },
5548   },
5549
5550   /* PREFIX_VEX_0F3809 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { "vpsignw",        { XM, Vex, EXx }, 0 },
5555   },
5556
5557   /* PREFIX_VEX_0F380A */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { "vpsignd",        { XM, Vex, EXx }, 0 },
5562   },
5563
5564   /* PREFIX_VEX_0F380B */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5569   },
5570
5571   /* PREFIX_VEX_0F380C */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5576   },
5577
5578   /* PREFIX_VEX_0F380D */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5583   },
5584
5585   /* PREFIX_VEX_0F380E */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5590   },
5591
5592   /* PREFIX_VEX_0F380F */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5597   },
5598
5599   /* PREFIX_VEX_0F3813 */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5604   },
5605
5606   /* PREFIX_VEX_0F3816 */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5611   },
5612
5613   /* PREFIX_VEX_0F3817 */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { "vptest",         { XM, EXx }, 0 },
5618   },
5619
5620   /* PREFIX_VEX_0F3818 */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F3819 */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F381A */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F381C */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { "vpabsb",         { XM, EXx }, 0 },
5646   },
5647
5648   /* PREFIX_VEX_0F381D */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { "vpabsw",         { XM, EXx }, 0 },
5653   },
5654
5655   /* PREFIX_VEX_0F381E */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { "vpabsd",         { XM, EXx }, 0 },
5660   },
5661
5662   /* PREFIX_VEX_0F3820 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5667   },
5668
5669   /* PREFIX_VEX_0F3821 */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5674   },
5675
5676   /* PREFIX_VEX_0F3822 */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5681   },
5682
5683   /* PREFIX_VEX_0F3823 */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5688   },
5689
5690   /* PREFIX_VEX_0F3824 */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5695   },
5696
5697   /* PREFIX_VEX_0F3825 */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5702   },
5703
5704   /* PREFIX_VEX_0F3828 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5709   },
5710
5711   /* PREFIX_VEX_0F3829 */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5716   },
5717
5718   /* PREFIX_VEX_0F382A */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5723   },
5724
5725   /* PREFIX_VEX_0F382B */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5730   },
5731
5732   /* PREFIX_VEX_0F382C */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5737   },
5738
5739   /* PREFIX_VEX_0F382D */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5744   },
5745
5746   /* PREFIX_VEX_0F382E */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5751   },
5752
5753   /* PREFIX_VEX_0F382F */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5758   },
5759
5760   /* PREFIX_VEX_0F3830 */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5765   },
5766
5767   /* PREFIX_VEX_0F3831 */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5772   },
5773
5774   /* PREFIX_VEX_0F3832 */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5779   },
5780
5781   /* PREFIX_VEX_0F3833 */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5786   },
5787
5788   /* PREFIX_VEX_0F3834 */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5793   },
5794
5795   /* PREFIX_VEX_0F3835 */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5800   },
5801
5802   /* PREFIX_VEX_0F3836 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5807   },
5808
5809   /* PREFIX_VEX_0F3837 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5814   },
5815
5816   /* PREFIX_VEX_0F3838 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { "vpminsb",        { XM, Vex, EXx }, 0 },
5821   },
5822
5823   /* PREFIX_VEX_0F3839 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vpminsd",        { XM, Vex, EXx }, 0 },
5828   },
5829
5830   /* PREFIX_VEX_0F383A */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vpminuw",        { XM, Vex, EXx }, 0 },
5835   },
5836
5837   /* PREFIX_VEX_0F383B */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { "vpminud",        { XM, Vex, EXx }, 0 },
5842   },
5843
5844   /* PREFIX_VEX_0F383C */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5849   },
5850
5851   /* PREFIX_VEX_0F383D */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5856   },
5857
5858   /* PREFIX_VEX_0F383E */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5863   },
5864
5865   /* PREFIX_VEX_0F383F */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5870   },
5871
5872   /* PREFIX_VEX_0F3840 */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { "vpmulld",        { XM, Vex, EXx }, 0 },
5877   },
5878
5879   /* PREFIX_VEX_0F3841 */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5884   },
5885
5886   /* PREFIX_VEX_0F3845 */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5891   },
5892
5893   /* PREFIX_VEX_0F3846 */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5898   },
5899
5900   /* PREFIX_VEX_0F3847 */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5905   },
5906
5907   /* PREFIX_VEX_0F3858 */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5912   },
5913
5914   /* PREFIX_VEX_0F3859 */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5919   },
5920
5921   /* PREFIX_VEX_0F385A */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5926   },
5927
5928   /* PREFIX_VEX_0F3878 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5933   },
5934
5935   /* PREFIX_VEX_0F3879 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5940   },
5941
5942   /* PREFIX_VEX_0F388C */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5947   },
5948
5949   /* PREFIX_VEX_0F388E */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F3890 */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5961   },
5962
5963   /* PREFIX_VEX_0F3891 */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5968   },
5969
5970   /* PREFIX_VEX_0F3892 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5975   },
5976
5977   /* PREFIX_VEX_0F3893 */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5982   },
5983
5984   /* PREFIX_VEX_0F3896 */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5989   },
5990
5991   /* PREFIX_VEX_0F3897 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5996   },
5997
5998   /* PREFIX_VEX_0F3898 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6003   },
6004
6005   /* PREFIX_VEX_0F3899 */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6010   },
6011
6012   /* PREFIX_VEX_0F389A */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6017   },
6018
6019   /* PREFIX_VEX_0F389B */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F389C */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6031   },
6032
6033   /* PREFIX_VEX_0F389D */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F389E */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F389F */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F38A6 */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6059     { Bad_Opcode },
6060   },
6061
6062   /* PREFIX_VEX_0F38A7 */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F38A8 */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F38A9 */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F38AA */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F38AB */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6095   },
6096
6097   /* PREFIX_VEX_0F38AC */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6102   },
6103
6104   /* PREFIX_VEX_0F38AD */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38AE */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38AF */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38B6 */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38B7 */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6137   },
6138
6139   /* PREFIX_VEX_0F38B8 */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6144   },
6145
6146   /* PREFIX_VEX_0F38B9 */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6151   },
6152
6153   /* PREFIX_VEX_0F38BA */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6158   },
6159
6160   /* PREFIX_VEX_0F38BB */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6165   },
6166
6167   /* PREFIX_VEX_0F38BC */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6172   },
6173
6174   /* PREFIX_VEX_0F38BD */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6179   },
6180
6181   /* PREFIX_VEX_0F38BE */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38BF */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6193   },
6194
6195   /* PREFIX_VEX_0F38CF */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6200   },
6201
6202   /* PREFIX_VEX_0F38DB */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6207   },
6208
6209   /* PREFIX_VEX_0F38DC */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vaesenc",        { XM, Vex, EXx }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F38DD */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F38DE */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vaesdec",        { XM, Vex, EXx }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F38DF */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6235   },
6236
6237   /* PREFIX_VEX_0F38F2 */
6238   {
6239     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6240   },
6241
6242   /* PREFIX_VEX_0F38F3_REG_1 */
6243   {
6244     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6245   },
6246
6247   /* PREFIX_VEX_0F38F3_REG_2 */
6248   {
6249     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6250   },
6251
6252   /* PREFIX_VEX_0F38F3_REG_3 */
6253   {
6254     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6255   },
6256
6257   /* PREFIX_VEX_0F38F5 */
6258   {
6259     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6260     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6261     { Bad_Opcode },
6262     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6263   },
6264
6265   /* PREFIX_VEX_0F38F6 */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6271   },
6272
6273   /* PREFIX_VEX_0F38F7 */
6274   {
6275     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6276     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6277     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6278     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6279   },
6280
6281   /* PREFIX_VEX_0F3A00 */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6286   },
6287
6288   /* PREFIX_VEX_0F3A01 */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6293   },
6294
6295   /* PREFIX_VEX_0F3A02 */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A04 */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6307   },
6308
6309   /* PREFIX_VEX_0F3A05 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A06 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A08 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { "vroundps",       { XM, EXx, Ib }, 0 },
6328   },
6329
6330   /* PREFIX_VEX_0F3A09 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { "vroundpd",       { XM, EXx, Ib }, 0 },
6335   },
6336
6337   /* PREFIX_VEX_0F3A0A */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6342   },
6343
6344   /* PREFIX_VEX_0F3A0B */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6349   },
6350
6351   /* PREFIX_VEX_0F3A0C */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6356   },
6357
6358   /* PREFIX_VEX_0F3A0D */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F3A0E */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F3A0F */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F3A14 */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F3A15 */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F3A16 */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F3A17 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6405   },
6406
6407   /* PREFIX_VEX_0F3A18 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6412   },
6413
6414   /* PREFIX_VEX_0F3A19 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A1D */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6426   },
6427
6428   /* PREFIX_VEX_0F3A20 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A21 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A22 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A30 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A31 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A32 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A33 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A38 */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A39 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A40 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6496   },
6497
6498   /* PREFIX_VEX_0F3A41 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6503   },
6504
6505   /* PREFIX_VEX_0F3A42 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6510   },
6511
6512   /* PREFIX_VEX_0F3A44 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6517   },
6518
6519   /* PREFIX_VEX_0F3A46 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6524   },
6525
6526   /* PREFIX_VEX_0F3A48 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6531   },
6532
6533   /* PREFIX_VEX_0F3A49 */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6538   },
6539
6540   /* PREFIX_VEX_0F3A4A */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6545   },
6546
6547   /* PREFIX_VEX_0F3A4B */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6552   },
6553
6554   /* PREFIX_VEX_0F3A4C */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6559   },
6560
6561   /* PREFIX_VEX_0F3A5C */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6566   },
6567
6568   /* PREFIX_VEX_0F3A5D */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6573   },
6574
6575   /* PREFIX_VEX_0F3A5E */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6580   },
6581
6582   /* PREFIX_VEX_0F3A5F */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6587   },
6588
6589   /* PREFIX_VEX_0F3A60 */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6594     { Bad_Opcode },
6595   },
6596
6597   /* PREFIX_VEX_0F3A61 */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6602   },
6603
6604   /* PREFIX_VEX_0F3A62 */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6609   },
6610
6611   /* PREFIX_VEX_0F3A63 */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6616   },
6617
6618   /* PREFIX_VEX_0F3A68 */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6623   },
6624
6625   /* PREFIX_VEX_0F3A69 */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6630   },
6631
6632   /* PREFIX_VEX_0F3A6A */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6637   },
6638
6639   /* PREFIX_VEX_0F3A6B */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6644   },
6645
6646   /* PREFIX_VEX_0F3A6C */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6651   },
6652
6653   /* PREFIX_VEX_0F3A6D */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6658   },
6659
6660   /* PREFIX_VEX_0F3A6E */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6665   },
6666
6667   /* PREFIX_VEX_0F3A6F */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6672   },
6673
6674   /* PREFIX_VEX_0F3A78 */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6679   },
6680
6681   /* PREFIX_VEX_0F3A79 */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6686   },
6687
6688   /* PREFIX_VEX_0F3A7A */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6693   },
6694
6695   /* PREFIX_VEX_0F3A7B */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6700   },
6701
6702   /* PREFIX_VEX_0F3A7C */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6707     { Bad_Opcode },
6708   },
6709
6710   /* PREFIX_VEX_0F3A7D */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6715   },
6716
6717   /* PREFIX_VEX_0F3A7E */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6722   },
6723
6724   /* PREFIX_VEX_0F3A7F */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3ACE */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3ACF */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6743   },
6744
6745   /* PREFIX_VEX_0F3ADF */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6750   },
6751
6752   /* PREFIX_VEX_0F3AF0 */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6758   },
6759
6760 #include "i386-dis-evex-prefix.h"
6761 };
6762
6763 static const struct dis386 x86_64_table[][2] = {
6764   /* X86_64_06 */
6765   {
6766     { "pushP", { es }, 0 },
6767   },
6768
6769   /* X86_64_07 */
6770   {
6771     { "popP", { es }, 0 },
6772   },
6773
6774   /* X86_64_0E */
6775   {
6776     { "pushP", { cs }, 0 },
6777   },
6778
6779   /* X86_64_16 */
6780   {
6781     { "pushP", { ss }, 0 },
6782   },
6783
6784   /* X86_64_17 */
6785   {
6786     { "popP", { ss }, 0 },
6787   },
6788
6789   /* X86_64_1E */
6790   {
6791     { "pushP", { ds }, 0 },
6792   },
6793
6794   /* X86_64_1F */
6795   {
6796     { "popP", { ds }, 0 },
6797   },
6798
6799   /* X86_64_27 */
6800   {
6801     { "daa", { XX }, 0 },
6802   },
6803
6804   /* X86_64_2F */
6805   {
6806     { "das", { XX }, 0 },
6807   },
6808
6809   /* X86_64_37 */
6810   {
6811     { "aaa", { XX }, 0 },
6812   },
6813
6814   /* X86_64_3F */
6815   {
6816     { "aas", { XX }, 0 },
6817   },
6818
6819   /* X86_64_60 */
6820   {
6821     { "pushaP", { XX }, 0 },
6822   },
6823
6824   /* X86_64_61 */
6825   {
6826     { "popaP", { XX }, 0 },
6827   },
6828
6829   /* X86_64_62 */
6830   {
6831     { MOD_TABLE (MOD_62_32BIT) },
6832     { EVEX_TABLE (EVEX_0F) },
6833   },
6834
6835   /* X86_64_63 */
6836   {
6837     { "arpl", { Ew, Gw }, 0 },
6838     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6839   },
6840
6841   /* X86_64_6D */
6842   {
6843     { "ins{R|}", { Yzr, indirDX }, 0 },
6844     { "ins{G|}", { Yzr, indirDX }, 0 },
6845   },
6846
6847   /* X86_64_6F */
6848   {
6849     { "outs{R|}", { indirDXr, Xz }, 0 },
6850     { "outs{G|}", { indirDXr, Xz }, 0 },
6851   },
6852
6853   /* X86_64_82 */
6854   {
6855     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6856     { REG_TABLE (REG_80) },
6857   },
6858
6859   /* X86_64_9A */
6860   {
6861     { "Jcall{T|}", { Ap }, 0 },
6862   },
6863
6864   /* X86_64_C2 */
6865   {
6866     { "retP",           { Iw, BND }, 0 },
6867     { "ret@",           { Iw, BND }, 0 },
6868   },
6869
6870   /* X86_64_C3 */
6871   {
6872     { "retP",           { BND }, 0 },
6873     { "ret@",           { BND }, 0 },
6874   },
6875
6876   /* X86_64_C4 */
6877   {
6878     { MOD_TABLE (MOD_C4_32BIT) },
6879     { VEX_C4_TABLE (VEX_0F) },
6880   },
6881
6882   /* X86_64_C5 */
6883   {
6884     { MOD_TABLE (MOD_C5_32BIT) },
6885     { VEX_C5_TABLE (VEX_0F) },
6886   },
6887
6888   /* X86_64_CE */
6889   {
6890     { "into", { XX }, 0 },
6891   },
6892
6893   /* X86_64_D4 */
6894   {
6895     { "aam", { Ib }, 0 },
6896   },
6897
6898   /* X86_64_D5 */
6899   {
6900     { "aad", { Ib }, 0 },
6901   },
6902
6903   /* X86_64_E8 */
6904   {
6905     { "callP",          { Jv, BND }, 0 },
6906     { "call@",          { Jv, BND }, 0 }
6907   },
6908
6909   /* X86_64_E9 */
6910   {
6911     { "jmpP",           { Jv, BND }, 0 },
6912     { "jmp@",           { Jv, BND }, 0 }
6913   },
6914
6915   /* X86_64_EA */
6916   {
6917     { "Jjmp{T|}", { Ap }, 0 },
6918   },
6919
6920   /* X86_64_0F01_REG_0 */
6921   {
6922     { "sgdt{Q|IQ}", { M }, 0 },
6923     { "sgdt", { M }, 0 },
6924   },
6925
6926   /* X86_64_0F01_REG_1 */
6927   {
6928     { "sidt{Q|IQ}", { M }, 0 },
6929     { "sidt", { M }, 0 },
6930   },
6931
6932   /* X86_64_0F01_REG_2 */
6933   {
6934     { "lgdt{Q|Q}", { M }, 0 },
6935     { "lgdt", { M }, 0 },
6936   },
6937
6938   /* X86_64_0F01_REG_3 */
6939   {
6940     { "lidt{Q|Q}", { M }, 0 },
6941     { "lidt", { M }, 0 },
6942   },
6943 };
6944
6945 static const struct dis386 three_byte_table[][256] = {
6946
6947   /* THREE_BYTE_0F38 */
6948   {
6949     /* 00 */
6950     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6951     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6952     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6953     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6954     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6955     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6956     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6957     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6958     /* 08 */
6959     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6960     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6961     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6962     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     /* 10 */
6968     { PREFIX_TABLE (PREFIX_0F3810) },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { PREFIX_TABLE (PREFIX_0F3814) },
6973     { PREFIX_TABLE (PREFIX_0F3815) },
6974     { Bad_Opcode },
6975     { PREFIX_TABLE (PREFIX_0F3817) },
6976     /* 18 */
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6982     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6983     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6984     { Bad_Opcode },
6985     /* 20 */
6986     { PREFIX_TABLE (PREFIX_0F3820) },
6987     { PREFIX_TABLE (PREFIX_0F3821) },
6988     { PREFIX_TABLE (PREFIX_0F3822) },
6989     { PREFIX_TABLE (PREFIX_0F3823) },
6990     { PREFIX_TABLE (PREFIX_0F3824) },
6991     { PREFIX_TABLE (PREFIX_0F3825) },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     /* 28 */
6995     { PREFIX_TABLE (PREFIX_0F3828) },
6996     { PREFIX_TABLE (PREFIX_0F3829) },
6997     { PREFIX_TABLE (PREFIX_0F382A) },
6998     { PREFIX_TABLE (PREFIX_0F382B) },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     /* 30 */
7004     { PREFIX_TABLE (PREFIX_0F3830) },
7005     { PREFIX_TABLE (PREFIX_0F3831) },
7006     { PREFIX_TABLE (PREFIX_0F3832) },
7007     { PREFIX_TABLE (PREFIX_0F3833) },
7008     { PREFIX_TABLE (PREFIX_0F3834) },
7009     { PREFIX_TABLE (PREFIX_0F3835) },
7010     { Bad_Opcode },
7011     { PREFIX_TABLE (PREFIX_0F3837) },
7012     /* 38 */
7013     { PREFIX_TABLE (PREFIX_0F3838) },
7014     { PREFIX_TABLE (PREFIX_0F3839) },
7015     { PREFIX_TABLE (PREFIX_0F383A) },
7016     { PREFIX_TABLE (PREFIX_0F383B) },
7017     { PREFIX_TABLE (PREFIX_0F383C) },
7018     { PREFIX_TABLE (PREFIX_0F383D) },
7019     { PREFIX_TABLE (PREFIX_0F383E) },
7020     { PREFIX_TABLE (PREFIX_0F383F) },
7021     /* 40 */
7022     { PREFIX_TABLE (PREFIX_0F3840) },
7023     { PREFIX_TABLE (PREFIX_0F3841) },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     /* 48 */
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     /* 50 */
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     /* 58 */
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     /* 60 */
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     /* 68 */
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     /* 70 */
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     /* 78 */
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     /* 80 */
7094     { PREFIX_TABLE (PREFIX_0F3880) },
7095     { PREFIX_TABLE (PREFIX_0F3881) },
7096     { PREFIX_TABLE (PREFIX_0F3882) },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     /* 88 */
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     /* 90 */
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     /* 98 */
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     /* a0 */
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     /* a8 */
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     /* b0 */
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     /* b8 */
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     /* c0 */
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     /* c8 */
7175     { PREFIX_TABLE (PREFIX_0F38C8) },
7176     { PREFIX_TABLE (PREFIX_0F38C9) },
7177     { PREFIX_TABLE (PREFIX_0F38CA) },
7178     { PREFIX_TABLE (PREFIX_0F38CB) },
7179     { PREFIX_TABLE (PREFIX_0F38CC) },
7180     { PREFIX_TABLE (PREFIX_0F38CD) },
7181     { Bad_Opcode },
7182     { PREFIX_TABLE (PREFIX_0F38CF) },
7183     /* d0 */
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     /* d8 */
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { PREFIX_TABLE (PREFIX_0F38DB) },
7197     { PREFIX_TABLE (PREFIX_0F38DC) },
7198     { PREFIX_TABLE (PREFIX_0F38DD) },
7199     { PREFIX_TABLE (PREFIX_0F38DE) },
7200     { PREFIX_TABLE (PREFIX_0F38DF) },
7201     /* e0 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     /* e8 */
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     /* f0 */
7220     { PREFIX_TABLE (PREFIX_0F38F0) },
7221     { PREFIX_TABLE (PREFIX_0F38F1) },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { PREFIX_TABLE (PREFIX_0F38F5) },
7226     { PREFIX_TABLE (PREFIX_0F38F6) },
7227     { Bad_Opcode },
7228     /* f8 */
7229     { PREFIX_TABLE (PREFIX_0F38F8) },
7230     { PREFIX_TABLE (PREFIX_0F38F9) },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237   },
7238   /* THREE_BYTE_0F3A */
7239   {
7240     /* 00 */
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     /* 08 */
7250     { PREFIX_TABLE (PREFIX_0F3A08) },
7251     { PREFIX_TABLE (PREFIX_0F3A09) },
7252     { PREFIX_TABLE (PREFIX_0F3A0A) },
7253     { PREFIX_TABLE (PREFIX_0F3A0B) },
7254     { PREFIX_TABLE (PREFIX_0F3A0C) },
7255     { PREFIX_TABLE (PREFIX_0F3A0D) },
7256     { PREFIX_TABLE (PREFIX_0F3A0E) },
7257     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7258     /* 10 */
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { PREFIX_TABLE (PREFIX_0F3A14) },
7264     { PREFIX_TABLE (PREFIX_0F3A15) },
7265     { PREFIX_TABLE (PREFIX_0F3A16) },
7266     { PREFIX_TABLE (PREFIX_0F3A17) },
7267     /* 18 */
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     /* 20 */
7277     { PREFIX_TABLE (PREFIX_0F3A20) },
7278     { PREFIX_TABLE (PREFIX_0F3A21) },
7279     { PREFIX_TABLE (PREFIX_0F3A22) },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     /* 28 */
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     /* 30 */
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     /* 38 */
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     /* 40 */
7313     { PREFIX_TABLE (PREFIX_0F3A40) },
7314     { PREFIX_TABLE (PREFIX_0F3A41) },
7315     { PREFIX_TABLE (PREFIX_0F3A42) },
7316     { Bad_Opcode },
7317     { PREFIX_TABLE (PREFIX_0F3A44) },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     /* 48 */
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     /* 50 */
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     /* 58 */
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     /* 60 */
7349     { PREFIX_TABLE (PREFIX_0F3A60) },
7350     { PREFIX_TABLE (PREFIX_0F3A61) },
7351     { PREFIX_TABLE (PREFIX_0F3A62) },
7352     { PREFIX_TABLE (PREFIX_0F3A63) },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     /* 68 */
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     /* 70 */
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     /* 78 */
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     /* 80 */
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     /* 88 */
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     /* 90 */
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     /* 98 */
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     /* a0 */
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     /* a8 */
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     /* b0 */
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     /* b8 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     /* c0 */
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     /* c8 */
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { PREFIX_TABLE (PREFIX_0F3ACC) },
7471     { Bad_Opcode },
7472     { PREFIX_TABLE (PREFIX_0F3ACE) },
7473     { PREFIX_TABLE (PREFIX_0F3ACF) },
7474     /* d0 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     /* d8 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { PREFIX_TABLE (PREFIX_0F3ADF) },
7492     /* e0 */
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     /* e8 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* f0 */
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     /* f8 */
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528   },
7529 };
7530
7531 static const struct dis386 xop_table[][256] = {
7532   /* XOP_08 */
7533   {
7534     /* 00 */
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     /* 08 */
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     /* 10 */
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     /* 18 */
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     /* 20 */
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     /* 28 */
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     /* 30 */
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     /* 38 */
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     /* 40 */
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     /* 48 */
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     /* 50 */
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     /* 58 */
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     /* 60 */
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     /* 68 */
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     /* 70 */
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     /* 78 */
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     /* 80 */
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7685     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7686     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7687     /* 88 */
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7695     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7696     /* 90 */
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7703     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7704     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7705     /* 98 */
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7713     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7714     /* a0 */
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7718     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7722     { Bad_Opcode },
7723     /* a8 */
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     /* b0 */
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740     { Bad_Opcode },
7741     /* b8 */
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     /* c0 */
7751     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7752     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7753     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7754     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     /* c8 */
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7765     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7766     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7767     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7768     /* d0 */
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     /* d8 */
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     /* e0 */
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     /* e8 */
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7801     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7802     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7803     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7804     /* f0 */
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     /* f8 */
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822   },
7823   /* XOP_09 */
7824   {
7825     /* 00 */
7826     { Bad_Opcode },
7827     { REG_TABLE (REG_XOP_TBM_01) },
7828     { REG_TABLE (REG_XOP_TBM_02) },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     /* 08 */
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     /* 10 */
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { REG_TABLE (REG_XOP_LWPCB) },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     /* 18 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     /* 20 */
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     /* 28 */
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     /* 30 */
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     /* 38 */
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     /* 40 */
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     /* 48 */
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     /* 50 */
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     /* 58 */
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     /* 60 */
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     /* 68 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     /* 70 */
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     /* 78 */
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* 80 */
7970     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7971     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7972     { "vfrczss",        { XM, EXd }, 0 },
7973     { "vfrczsd",        { XM, EXq }, 0 },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     /* 88 */
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     /* 90 */
7988     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7989     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7990     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7991     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7992     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7993     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7994     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7995     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7996     /* 98 */
7997     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7998     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7999     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8000     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     /* a0 */
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     /* a8 */
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     /* b0 */
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     /* b8 */
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     /* c0 */
8042     { Bad_Opcode },
8043     { "vphaddbw",       { XM, EXxmm }, 0 },
8044     { "vphaddbd",       { XM, EXxmm }, 0 },
8045     { "vphaddbq",       { XM, EXxmm }, 0 },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { "vphaddwd",       { XM, EXxmm }, 0 },
8049     { "vphaddwq",       { XM, EXxmm }, 0 },
8050     /* c8 */
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { "vphadddq",       { XM, EXxmm }, 0 },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     /* d0 */
8060     { Bad_Opcode },
8061     { "vphaddubw",      { XM, EXxmm }, 0 },
8062     { "vphaddubd",      { XM, EXxmm }, 0 },
8063     { "vphaddubq",      { XM, EXxmm }, 0 },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { "vphadduwd",      { XM, EXxmm }, 0 },
8067     { "vphadduwq",      { XM, EXxmm }, 0 },
8068     /* d8 */
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { "vphaddudq",      { XM, EXxmm }, 0 },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     /* e0 */
8078     { Bad_Opcode },
8079     { "vphsubbw",       { XM, EXxmm }, 0 },
8080     { "vphsubwd",       { XM, EXxmm }, 0 },
8081     { "vphsubdq",       { XM, EXxmm }, 0 },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     /* e8 */
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     /* f0 */
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     /* f8 */
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113   },
8114   /* XOP_0A */
8115   {
8116     /* 00 */
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     /* 08 */
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     /* 10 */
8135     { "bextrS", { Gdq, Edq, Id }, 0 },
8136     { Bad_Opcode },
8137     { REG_TABLE (REG_XOP_LWP) },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     /* 18 */
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     /* 20 */
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     /* 28 */
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     /* 30 */
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     /* 38 */
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     /* 40 */
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     /* 48 */
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     /* 50 */
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     /* 58 */
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     /* 60 */
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     /* 68 */
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     /* 70 */
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     /* 78 */
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     /* 80 */
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     /* 88 */
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     /* 90 */
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     /* 98 */
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     /* a0 */
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     /* a8 */
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     /* b0 */
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* b8 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* c0 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* c8 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* d0 */
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     /* d8 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* e0 */
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     /* e8 */
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     /* f0 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* f8 */
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404   },
8405 };
8406
8407 static const struct dis386 vex_table[][256] = {
8408   /* VEX_0F */
8409   {
8410     /* 00 */
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     /* 08 */
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     /* 10 */
8429     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8432     { MOD_TABLE (MOD_VEX_0F13) },
8433     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8434     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8435     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8436     { MOD_TABLE (MOD_VEX_0F17) },
8437     /* 18 */
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     /* 20 */
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     /* 28 */
8456     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8457     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8458     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8459     { MOD_TABLE (MOD_VEX_0F2B) },
8460     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8461     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8462     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8463     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8464     /* 30 */
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     /* 38 */
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     /* 40 */
8483     { Bad_Opcode },
8484     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8486     { Bad_Opcode },
8487     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8488     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8489     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8490     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8491     /* 48 */
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8495     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     /* 50 */
8501     { MOD_TABLE (MOD_VEX_0F50) },
8502     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8505     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8506     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8507     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8508     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8509     /* 58 */
8510     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8518     /* 60 */
8519     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8527     /* 68 */
8528     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8536     /* 70 */
8537     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8538     { REG_TABLE (REG_VEX_0F71) },
8539     { REG_TABLE (REG_VEX_0F72) },
8540     { REG_TABLE (REG_VEX_0F73) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8545     /* 78 */
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8554     /* 80 */
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     /* 88 */
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     /* 90 */
8573     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     /* 98 */
8582     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     /* a0 */
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     /* a8 */
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { REG_TABLE (REG_VEX_0FAE) },
8607     { Bad_Opcode },
8608     /* b0 */
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     /* b8 */
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     /* c0 */
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8630     { Bad_Opcode },
8631     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8632     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8633     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8634     { Bad_Opcode },
8635     /* c8 */
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     /* d0 */
8645     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8646     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8647     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8648     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8649     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8650     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8652     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8653     /* d8 */
8654     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8662     /* e0 */
8663     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8664     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8671     /* e8 */
8672     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8680     /* f0 */
8681     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8689     /* f8 */
8690     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8697     { Bad_Opcode },
8698   },
8699   /* VEX_0F38 */
8700   {
8701     /* 00 */
8702     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8710     /* 08 */
8711     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8719     /* 10 */
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8728     /* 18 */
8729     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8732     { Bad_Opcode },
8733     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8736     { Bad_Opcode },
8737     /* 20 */
8738     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     /* 28 */
8747     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8755     /* 30 */
8756     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8764     /* 38 */
8765     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8773     /* 40 */
8774     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8782     /* 48 */
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     /* 50 */
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     /* 58 */
8801     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     /* 60 */
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     /* 68 */
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     /* 70 */
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     /* 78 */
8837     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     /* 80 */
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     /* 88 */
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8860     { Bad_Opcode },
8861     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8862     { Bad_Opcode },
8863     /* 90 */
8864     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8865     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8872     /* 98 */
8873     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8881     /* a0 */
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8890     /* a8 */
8891     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8899     /* b0 */
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8908     /* b8 */
8909     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8917     /* c0 */
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     /* c8 */
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8935     /* d0 */
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     /* d8 */
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8953     /* e0 */
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     /* e8 */
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     /* f0 */
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8975     { REG_TABLE (REG_VEX_0F38F3) },
8976     { Bad_Opcode },
8977     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8980     /* f8 */
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989   },
8990   /* VEX_0F3A */
8991   {
8992     /* 00 */
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8996     { Bad_Opcode },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9000     { Bad_Opcode },
9001     /* 08 */
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9010     /* 10 */
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9019     /* 18 */
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     /* 20 */
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     /* 28 */
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     /* 30 */
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     /* 38 */
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     /* 40 */
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9068     { Bad_Opcode },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9070     { Bad_Opcode },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9072     { Bad_Opcode },
9073     /* 48 */
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     /* 50 */
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     /* 58 */
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9100     /* 60 */
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     /* 68 */
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9118     /* 70 */
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     /* 78 */
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9136     /* 80 */
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     /* 88 */
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     /* 90 */
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     /* 98 */
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     /* a0 */
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     /* a8 */
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     /* b0 */
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     /* b8 */
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     /* c0 */
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     /* c8 */
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9225     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9226     /* d0 */
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     /* d8 */
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9244     /* e0 */
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     /* e8 */
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     /* f0 */
9263     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     /* f8 */
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280   },
9281 };
9282
9283 #include "i386-dis-evex.h"
9284
9285 static const struct dis386 vex_len_table[][2] = {
9286   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9287   {
9288     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9289   },
9290
9291   /* VEX_LEN_0F12_P_0_M_1 */
9292   {
9293     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9294   },
9295
9296   /* VEX_LEN_0F13_M_0 */
9297   {
9298     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9299   },
9300
9301   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9302   {
9303     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9304   },
9305
9306   /* VEX_LEN_0F16_P_0_M_1 */
9307   {
9308     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9309   },
9310
9311   /* VEX_LEN_0F17_M_0 */
9312   {
9313     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9314   },
9315
9316   /* VEX_LEN_0F41_P_0 */
9317   {
9318     { Bad_Opcode },
9319     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9320   },
9321   /* VEX_LEN_0F41_P_2 */
9322   {
9323     { Bad_Opcode },
9324     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9325   },
9326   /* VEX_LEN_0F42_P_0 */
9327   {
9328     { Bad_Opcode },
9329     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9330   },
9331   /* VEX_LEN_0F42_P_2 */
9332   {
9333     { Bad_Opcode },
9334     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9335   },
9336   /* VEX_LEN_0F44_P_0 */
9337   {
9338     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9339   },
9340   /* VEX_LEN_0F44_P_2 */
9341   {
9342     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9343   },
9344   /* VEX_LEN_0F45_P_0 */
9345   {
9346     { Bad_Opcode },
9347     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9348   },
9349   /* VEX_LEN_0F45_P_2 */
9350   {
9351     { Bad_Opcode },
9352     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9353   },
9354   /* VEX_LEN_0F46_P_0 */
9355   {
9356     { Bad_Opcode },
9357     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9358   },
9359   /* VEX_LEN_0F46_P_2 */
9360   {
9361     { Bad_Opcode },
9362     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9363   },
9364   /* VEX_LEN_0F47_P_0 */
9365   {
9366     { Bad_Opcode },
9367     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9368   },
9369   /* VEX_LEN_0F47_P_2 */
9370   {
9371     { Bad_Opcode },
9372     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9373   },
9374   /* VEX_LEN_0F4A_P_0 */
9375   {
9376     { Bad_Opcode },
9377     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9378   },
9379   /* VEX_LEN_0F4A_P_2 */
9380   {
9381     { Bad_Opcode },
9382     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9383   },
9384   /* VEX_LEN_0F4B_P_0 */
9385   {
9386     { Bad_Opcode },
9387     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9388   },
9389   /* VEX_LEN_0F4B_P_2 */
9390   {
9391     { Bad_Opcode },
9392     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9393   },
9394
9395   /* VEX_LEN_0F6E_P_2 */
9396   {
9397     { "vmovK",          { XMScalar, Edq }, 0 },
9398   },
9399
9400   /* VEX_LEN_0F77_P_1 */
9401   {
9402     { "vzeroupper",     { XX }, 0 },
9403     { "vzeroall",       { XX }, 0 },
9404   },
9405
9406   /* VEX_LEN_0F7E_P_1 */
9407   {
9408     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9409   },
9410
9411   /* VEX_LEN_0F7E_P_2 */
9412   {
9413     { "vmovK",          { Edq, XMScalar }, 0 },
9414   },
9415
9416   /* VEX_LEN_0F90_P_0 */
9417   {
9418     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9419   },
9420
9421   /* VEX_LEN_0F90_P_2 */
9422   {
9423     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9424   },
9425
9426   /* VEX_LEN_0F91_P_0 */
9427   {
9428     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9429   },
9430
9431   /* VEX_LEN_0F91_P_2 */
9432   {
9433     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9434   },
9435
9436   /* VEX_LEN_0F92_P_0 */
9437   {
9438     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9439   },
9440
9441   /* VEX_LEN_0F92_P_2 */
9442   {
9443     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9444   },
9445
9446   /* VEX_LEN_0F92_P_3 */
9447   {
9448     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9449   },
9450
9451   /* VEX_LEN_0F93_P_0 */
9452   {
9453     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9454   },
9455
9456   /* VEX_LEN_0F93_P_2 */
9457   {
9458     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9459   },
9460
9461   /* VEX_LEN_0F93_P_3 */
9462   {
9463     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9464   },
9465
9466   /* VEX_LEN_0F98_P_0 */
9467   {
9468     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9469   },
9470
9471   /* VEX_LEN_0F98_P_2 */
9472   {
9473     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9474   },
9475
9476   /* VEX_LEN_0F99_P_0 */
9477   {
9478     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9479   },
9480
9481   /* VEX_LEN_0F99_P_2 */
9482   {
9483     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9484   },
9485
9486   /* VEX_LEN_0FAE_R_2_M_0 */
9487   {
9488     { "vldmxcsr",       { Md }, 0 },
9489   },
9490
9491   /* VEX_LEN_0FAE_R_3_M_0 */
9492   {
9493     { "vstmxcsr",       { Md }, 0 },
9494   },
9495
9496   /* VEX_LEN_0FC4_P_2 */
9497   {
9498     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9499   },
9500
9501   /* VEX_LEN_0FC5_P_2 */
9502   {
9503     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9504   },
9505
9506   /* VEX_LEN_0FD6_P_2 */
9507   {
9508     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9509   },
9510
9511   /* VEX_LEN_0FF7_P_2 */
9512   {
9513     { "vmaskmovdqu",    { XM, XS }, 0 },
9514   },
9515
9516   /* VEX_LEN_0F3816_P_2 */
9517   {
9518     { Bad_Opcode },
9519     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9520   },
9521
9522   /* VEX_LEN_0F3819_P_2 */
9523   {
9524     { Bad_Opcode },
9525     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9526   },
9527
9528   /* VEX_LEN_0F381A_P_2_M_0 */
9529   {
9530     { Bad_Opcode },
9531     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9532   },
9533
9534   /* VEX_LEN_0F3836_P_2 */
9535   {
9536     { Bad_Opcode },
9537     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9538   },
9539
9540   /* VEX_LEN_0F3841_P_2 */
9541   {
9542     { "vphminposuw",    { XM, EXx }, 0 },
9543   },
9544
9545   /* VEX_LEN_0F385A_P_2_M_0 */
9546   {
9547     { Bad_Opcode },
9548     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9549   },
9550
9551   /* VEX_LEN_0F38DB_P_2 */
9552   {
9553     { "vaesimc",        { XM, EXx }, 0 },
9554   },
9555
9556   /* VEX_LEN_0F38F2_P_0 */
9557   {
9558     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9559   },
9560
9561   /* VEX_LEN_0F38F3_R_1_P_0 */
9562   {
9563     { "blsrS",          { VexGdq, Edq }, 0 },
9564   },
9565
9566   /* VEX_LEN_0F38F3_R_2_P_0 */
9567   {
9568     { "blsmskS",        { VexGdq, Edq }, 0 },
9569   },
9570
9571   /* VEX_LEN_0F38F3_R_3_P_0 */
9572   {
9573     { "blsiS",          { VexGdq, Edq }, 0 },
9574   },
9575
9576   /* VEX_LEN_0F38F5_P_0 */
9577   {
9578     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9579   },
9580
9581   /* VEX_LEN_0F38F5_P_1 */
9582   {
9583     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9584   },
9585
9586   /* VEX_LEN_0F38F5_P_3 */
9587   {
9588     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9589   },
9590
9591   /* VEX_LEN_0F38F6_P_3 */
9592   {
9593     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9594   },
9595
9596   /* VEX_LEN_0F38F7_P_0 */
9597   {
9598     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9599   },
9600
9601   /* VEX_LEN_0F38F7_P_1 */
9602   {
9603     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9604   },
9605
9606   /* VEX_LEN_0F38F7_P_2 */
9607   {
9608     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9609   },
9610
9611   /* VEX_LEN_0F38F7_P_3 */
9612   {
9613     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9614   },
9615
9616   /* VEX_LEN_0F3A00_P_2 */
9617   {
9618     { Bad_Opcode },
9619     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9620   },
9621
9622   /* VEX_LEN_0F3A01_P_2 */
9623   {
9624     { Bad_Opcode },
9625     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9626   },
9627
9628   /* VEX_LEN_0F3A06_P_2 */
9629   {
9630     { Bad_Opcode },
9631     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9632   },
9633
9634   /* VEX_LEN_0F3A14_P_2 */
9635   {
9636     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9637   },
9638
9639   /* VEX_LEN_0F3A15_P_2 */
9640   {
9641     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9642   },
9643
9644   /* VEX_LEN_0F3A16_P_2  */
9645   {
9646     { "vpextrK",        { Edq, XM, Ib }, 0 },
9647   },
9648
9649   /* VEX_LEN_0F3A17_P_2 */
9650   {
9651     { "vextractps",     { Edqd, XM, Ib }, 0 },
9652   },
9653
9654   /* VEX_LEN_0F3A18_P_2 */
9655   {
9656     { Bad_Opcode },
9657     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9658   },
9659
9660   /* VEX_LEN_0F3A19_P_2 */
9661   {
9662     { Bad_Opcode },
9663     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9664   },
9665
9666   /* VEX_LEN_0F3A20_P_2 */
9667   {
9668     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9669   },
9670
9671   /* VEX_LEN_0F3A21_P_2 */
9672   {
9673     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9674   },
9675
9676   /* VEX_LEN_0F3A22_P_2 */
9677   {
9678     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9679   },
9680
9681   /* VEX_LEN_0F3A30_P_2 */
9682   {
9683     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9684   },
9685
9686   /* VEX_LEN_0F3A31_P_2 */
9687   {
9688     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9689   },
9690
9691   /* VEX_LEN_0F3A32_P_2 */
9692   {
9693     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9694   },
9695
9696   /* VEX_LEN_0F3A33_P_2 */
9697   {
9698     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9699   },
9700
9701   /* VEX_LEN_0F3A38_P_2 */
9702   {
9703     { Bad_Opcode },
9704     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9705   },
9706
9707   /* VEX_LEN_0F3A39_P_2 */
9708   {
9709     { Bad_Opcode },
9710     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9711   },
9712
9713   /* VEX_LEN_0F3A41_P_2 */
9714   {
9715     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9716   },
9717
9718   /* VEX_LEN_0F3A46_P_2 */
9719   {
9720     { Bad_Opcode },
9721     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9722   },
9723
9724   /* VEX_LEN_0F3A60_P_2 */
9725   {
9726     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9727   },
9728
9729   /* VEX_LEN_0F3A61_P_2 */
9730   {
9731     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9732   },
9733
9734   /* VEX_LEN_0F3A62_P_2 */
9735   {
9736     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9737   },
9738
9739   /* VEX_LEN_0F3A63_P_2 */
9740   {
9741     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9742   },
9743
9744   /* VEX_LEN_0F3A6A_P_2 */
9745   {
9746     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9747   },
9748
9749   /* VEX_LEN_0F3A6B_P_2 */
9750   {
9751     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9752   },
9753
9754   /* VEX_LEN_0F3A6E_P_2 */
9755   {
9756     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9757   },
9758
9759   /* VEX_LEN_0F3A6F_P_2 */
9760   {
9761     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9762   },
9763
9764   /* VEX_LEN_0F3A7A_P_2 */
9765   {
9766     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9767   },
9768
9769   /* VEX_LEN_0F3A7B_P_2 */
9770   {
9771     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9772   },
9773
9774   /* VEX_LEN_0F3A7E_P_2 */
9775   {
9776     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9777   },
9778
9779   /* VEX_LEN_0F3A7F_P_2 */
9780   {
9781     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9782   },
9783
9784   /* VEX_LEN_0F3ADF_P_2 */
9785   {
9786     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9787   },
9788
9789   /* VEX_LEN_0F3AF0_P_3 */
9790   {
9791     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9792   },
9793
9794   /* VEX_LEN_0FXOP_08_CC */
9795   {
9796      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9797   },
9798
9799   /* VEX_LEN_0FXOP_08_CD */
9800   {
9801      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9802   },
9803
9804   /* VEX_LEN_0FXOP_08_CE */
9805   {
9806      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9807   },
9808
9809   /* VEX_LEN_0FXOP_08_CF */
9810   {
9811      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9812   },
9813
9814   /* VEX_LEN_0FXOP_08_EC */
9815   {
9816      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9817   },
9818
9819   /* VEX_LEN_0FXOP_08_ED */
9820   {
9821      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9822   },
9823
9824   /* VEX_LEN_0FXOP_08_EE */
9825   {
9826      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9827   },
9828
9829   /* VEX_LEN_0FXOP_08_EF */
9830   {
9831      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9832   },
9833
9834   /* VEX_LEN_0FXOP_09_80 */
9835   {
9836     { "vfrczps",        { XM, EXxmm }, 0 },
9837     { "vfrczps",        { XM, EXymmq }, 0 },
9838   },
9839
9840   /* VEX_LEN_0FXOP_09_81 */
9841   {
9842     { "vfrczpd",        { XM, EXxmm }, 0 },
9843     { "vfrczpd",        { XM, EXymmq }, 0 },
9844   },
9845 };
9846
9847 #include "i386-dis-evex-len.h"
9848
9849 static const struct dis386 vex_w_table[][2] = {
9850   {
9851     /* VEX_W_0F41_P_0_LEN_1 */
9852     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9853     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9854   },
9855   {
9856     /* VEX_W_0F41_P_2_LEN_1 */
9857     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9858     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9859   },
9860   {
9861     /* VEX_W_0F42_P_0_LEN_1 */
9862     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9863     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9864   },
9865   {
9866     /* VEX_W_0F42_P_2_LEN_1 */
9867     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9868     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9869   },
9870   {
9871     /* VEX_W_0F44_P_0_LEN_0 */
9872     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9873     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9874   },
9875   {
9876     /* VEX_W_0F44_P_2_LEN_0 */
9877     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9878     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9879   },
9880   {
9881     /* VEX_W_0F45_P_0_LEN_1 */
9882     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9883     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9884   },
9885   {
9886     /* VEX_W_0F45_P_2_LEN_1 */
9887     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9888     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9889   },
9890   {
9891     /* VEX_W_0F46_P_0_LEN_1 */
9892     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9893     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9894   },
9895   {
9896     /* VEX_W_0F46_P_2_LEN_1 */
9897     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9898     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9899   },
9900   {
9901     /* VEX_W_0F47_P_0_LEN_1 */
9902     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9903     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9904   },
9905   {
9906     /* VEX_W_0F47_P_2_LEN_1 */
9907     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9908     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9909   },
9910   {
9911     /* VEX_W_0F4A_P_0_LEN_1 */
9912     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9913     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9914   },
9915   {
9916     /* VEX_W_0F4A_P_2_LEN_1 */
9917     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9918     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9919   },
9920   {
9921     /* VEX_W_0F4B_P_0_LEN_1 */
9922     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9923     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9924   },
9925   {
9926     /* VEX_W_0F4B_P_2_LEN_1 */
9927     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9928   },
9929   {
9930     /* VEX_W_0F90_P_0_LEN_0 */
9931     { "kmovw",          { MaskG, MaskE }, 0 },
9932     { "kmovq",          { MaskG, MaskE }, 0 },
9933   },
9934   {
9935     /* VEX_W_0F90_P_2_LEN_0 */
9936     { "kmovb",          { MaskG, MaskBDE }, 0 },
9937     { "kmovd",          { MaskG, MaskBDE }, 0 },
9938   },
9939   {
9940     /* VEX_W_0F91_P_0_LEN_0 */
9941     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9942     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9943   },
9944   {
9945     /* VEX_W_0F91_P_2_LEN_0 */
9946     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9947     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9948   },
9949   {
9950     /* VEX_W_0F92_P_0_LEN_0 */
9951     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9952   },
9953   {
9954     /* VEX_W_0F92_P_2_LEN_0 */
9955     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9956   },
9957   {
9958     /* VEX_W_0F93_P_0_LEN_0 */
9959     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9960   },
9961   {
9962     /* VEX_W_0F93_P_2_LEN_0 */
9963     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9964   },
9965   {
9966     /* VEX_W_0F98_P_0_LEN_0 */
9967     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9968     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9969   },
9970   {
9971     /* VEX_W_0F98_P_2_LEN_0 */
9972     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9973     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9974   },
9975   {
9976     /* VEX_W_0F99_P_0_LEN_0 */
9977     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9978     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9979   },
9980   {
9981     /* VEX_W_0F99_P_2_LEN_0 */
9982     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9983     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9984   },
9985   {
9986     /* VEX_W_0F380C_P_2  */
9987     { "vpermilps",      { XM, Vex, EXx }, 0 },
9988   },
9989   {
9990     /* VEX_W_0F380D_P_2  */
9991     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9992   },
9993   {
9994     /* VEX_W_0F380E_P_2  */
9995     { "vtestps",        { XM, EXx }, 0 },
9996   },
9997   {
9998     /* VEX_W_0F380F_P_2  */
9999     { "vtestpd",        { XM, EXx }, 0 },
10000   },
10001   {
10002     /* VEX_W_0F3816_P_2  */
10003     { "vpermps",        { XM, Vex, EXx }, 0 },
10004   },
10005   {
10006     /* VEX_W_0F3818_P_2 */
10007     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10008   },
10009   {
10010     /* VEX_W_0F3819_P_2 */
10011     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10012   },
10013   {
10014     /* VEX_W_0F381A_P_2_M_0 */
10015     { "vbroadcastf128", { XM, Mxmm }, 0 },
10016   },
10017   {
10018     /* VEX_W_0F382C_P_2_M_0 */
10019     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10020   },
10021   {
10022     /* VEX_W_0F382D_P_2_M_0 */
10023     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10024   },
10025   {
10026     /* VEX_W_0F382E_P_2_M_0 */
10027     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10028   },
10029   {
10030     /* VEX_W_0F382F_P_2_M_0 */
10031     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10032   },
10033   {
10034     /* VEX_W_0F3836_P_2  */
10035     { "vpermd",         { XM, Vex, EXx }, 0 },
10036   },
10037   {
10038     /* VEX_W_0F3846_P_2 */
10039     { "vpsravd",        { XM, Vex, EXx }, 0 },
10040   },
10041   {
10042     /* VEX_W_0F3858_P_2 */
10043     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10044   },
10045   {
10046     /* VEX_W_0F3859_P_2 */
10047     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10048   },
10049   {
10050     /* VEX_W_0F385A_P_2_M_0 */
10051     { "vbroadcasti128", { XM, Mxmm }, 0 },
10052   },
10053   {
10054     /* VEX_W_0F3878_P_2 */
10055     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10056   },
10057   {
10058     /* VEX_W_0F3879_P_2 */
10059     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10060   },
10061   {
10062     /* VEX_W_0F38CF_P_2 */
10063     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10064   },
10065   {
10066     /* VEX_W_0F3A00_P_2 */
10067     { Bad_Opcode },
10068     { "vpermq",         { XM, EXx, Ib }, 0 },
10069   },
10070   {
10071     /* VEX_W_0F3A01_P_2 */
10072     { Bad_Opcode },
10073     { "vpermpd",        { XM, EXx, Ib }, 0 },
10074   },
10075   {
10076     /* VEX_W_0F3A02_P_2 */
10077     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10078   },
10079   {
10080     /* VEX_W_0F3A04_P_2 */
10081     { "vpermilps",      { XM, EXx, Ib }, 0 },
10082   },
10083   {
10084     /* VEX_W_0F3A05_P_2 */
10085     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10086   },
10087   {
10088     /* VEX_W_0F3A06_P_2 */
10089     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10090   },
10091   {
10092     /* VEX_W_0F3A18_P_2 */
10093     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10094   },
10095   {
10096     /* VEX_W_0F3A19_P_2 */
10097     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10098   },
10099   {
10100     /* VEX_W_0F3A30_P_2_LEN_0 */
10101     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10102     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10103   },
10104   {
10105     /* VEX_W_0F3A31_P_2_LEN_0 */
10106     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10107     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10108   },
10109   {
10110     /* VEX_W_0F3A32_P_2_LEN_0 */
10111     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10112     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10113   },
10114   {
10115     /* VEX_W_0F3A33_P_2_LEN_0 */
10116     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10117     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10118   },
10119   {
10120     /* VEX_W_0F3A38_P_2 */
10121     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10122   },
10123   {
10124     /* VEX_W_0F3A39_P_2 */
10125     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10126   },
10127   {
10128     /* VEX_W_0F3A46_P_2 */
10129     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10130   },
10131   {
10132     /* VEX_W_0F3A48_P_2 */
10133     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10134     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10135   },
10136   {
10137     /* VEX_W_0F3A49_P_2 */
10138     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10139     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10140   },
10141   {
10142     /* VEX_W_0F3A4A_P_2 */
10143     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10144   },
10145   {
10146     /* VEX_W_0F3A4B_P_2 */
10147     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10148   },
10149   {
10150     /* VEX_W_0F3A4C_P_2 */
10151     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10152   },
10153   {
10154     /* VEX_W_0F3ACE_P_2 */
10155     { Bad_Opcode },
10156     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10157   },
10158   {
10159     /* VEX_W_0F3ACF_P_2 */
10160     { Bad_Opcode },
10161     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10162   },
10163
10164 #include "i386-dis-evex-w.h"
10165 };
10166
10167 static const struct dis386 mod_table[][2] = {
10168   {
10169     /* MOD_8D */
10170     { "leaS",           { Gv, M }, 0 },
10171   },
10172   {
10173     /* MOD_C6_REG_7 */
10174     { Bad_Opcode },
10175     { RM_TABLE (RM_C6_REG_7) },
10176   },
10177   {
10178     /* MOD_C7_REG_7 */
10179     { Bad_Opcode },
10180     { RM_TABLE (RM_C7_REG_7) },
10181   },
10182   {
10183     /* MOD_FF_REG_3 */
10184     { "Jcall^", { indirEp }, 0 },
10185   },
10186   {
10187     /* MOD_FF_REG_5 */
10188     { "Jjmp^", { indirEp }, 0 },
10189   },
10190   {
10191     /* MOD_0F01_REG_0 */
10192     { X86_64_TABLE (X86_64_0F01_REG_0) },
10193     { RM_TABLE (RM_0F01_REG_0) },
10194   },
10195   {
10196     /* MOD_0F01_REG_1 */
10197     { X86_64_TABLE (X86_64_0F01_REG_1) },
10198     { RM_TABLE (RM_0F01_REG_1) },
10199   },
10200   {
10201     /* MOD_0F01_REG_2 */
10202     { X86_64_TABLE (X86_64_0F01_REG_2) },
10203     { RM_TABLE (RM_0F01_REG_2) },
10204   },
10205   {
10206     /* MOD_0F01_REG_3 */
10207     { X86_64_TABLE (X86_64_0F01_REG_3) },
10208     { RM_TABLE (RM_0F01_REG_3) },
10209   },
10210   {
10211     /* MOD_0F01_REG_5 */
10212     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10213     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10214   },
10215   {
10216     /* MOD_0F01_REG_7 */
10217     { "invlpg",         { Mb }, 0 },
10218     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10219   },
10220   {
10221     /* MOD_0F12_PREFIX_0 */
10222     { "movlpX",         { XM, EXq }, 0 },
10223     { "movhlps",        { XM, EXq }, 0 },
10224   },
10225   {
10226     /* MOD_0F12_PREFIX_2 */
10227     { "movlpX", { XM, EXq }, 0 },
10228   },
10229   {
10230     /* MOD_0F13 */
10231     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10232   },
10233   {
10234     /* MOD_0F16_PREFIX_0 */
10235     { "movhpX",         { XM, EXq }, 0 },
10236     { "movlhps",        { XM, EXq }, 0 },
10237   },
10238   {
10239     /* MOD_0F16_PREFIX_2 */
10240     { "movhpX", { XM, EXq }, 0 },
10241   },
10242   {
10243     /* MOD_0F17 */
10244     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10245   },
10246   {
10247     /* MOD_0F18_REG_0 */
10248     { "prefetchnta",    { Mb }, 0 },
10249   },
10250   {
10251     /* MOD_0F18_REG_1 */
10252     { "prefetcht0",     { Mb }, 0 },
10253   },
10254   {
10255     /* MOD_0F18_REG_2 */
10256     { "prefetcht1",     { Mb }, 0 },
10257   },
10258   {
10259     /* MOD_0F18_REG_3 */
10260     { "prefetcht2",     { Mb }, 0 },
10261   },
10262   {
10263     /* MOD_0F18_REG_4 */
10264     { "nop/reserved",   { Mb }, 0 },
10265   },
10266   {
10267     /* MOD_0F18_REG_5 */
10268     { "nop/reserved",   { Mb }, 0 },
10269   },
10270   {
10271     /* MOD_0F18_REG_6 */
10272     { "nop/reserved",   { Mb }, 0 },
10273   },
10274   {
10275     /* MOD_0F18_REG_7 */
10276     { "nop/reserved",   { Mb }, 0 },
10277   },
10278   {
10279     /* MOD_0F1A_PREFIX_0 */
10280     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10281     { "nopQ",           { Ev }, 0 },
10282   },
10283   {
10284     /* MOD_0F1B_PREFIX_0 */
10285     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10286     { "nopQ",           { Ev }, 0 },
10287   },
10288   {
10289     /* MOD_0F1B_PREFIX_1 */
10290     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10291     { "nopQ",           { Ev }, 0 },
10292   },
10293   {
10294     /* MOD_0F1C_PREFIX_0 */
10295     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10296     { "nopQ",           { Ev }, 0 },
10297   },
10298   {
10299     /* MOD_0F1E_PREFIX_1 */
10300     { "nopQ",           { Ev }, 0 },
10301     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10302   },
10303   {
10304     /* MOD_0F24 */
10305     { Bad_Opcode },
10306     { "movL",           { Rd, Td }, 0 },
10307   },
10308   {
10309     /* MOD_0F26 */
10310     { Bad_Opcode },
10311     { "movL",           { Td, Rd }, 0 },
10312   },
10313   {
10314     /* MOD_0F2B_PREFIX_0 */
10315     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10316   },
10317   {
10318     /* MOD_0F2B_PREFIX_1 */
10319     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10320   },
10321   {
10322     /* MOD_0F2B_PREFIX_2 */
10323     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10324   },
10325   {
10326     /* MOD_0F2B_PREFIX_3 */
10327     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10328   },
10329   {
10330     /* MOD_0F50 */
10331     { Bad_Opcode },
10332     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10333   },
10334   {
10335     /* MOD_0F71_REG_2 */
10336     { Bad_Opcode },
10337     { "psrlw",          { MS, Ib }, 0 },
10338   },
10339   {
10340     /* MOD_0F71_REG_4 */
10341     { Bad_Opcode },
10342     { "psraw",          { MS, Ib }, 0 },
10343   },
10344   {
10345     /* MOD_0F71_REG_6 */
10346     { Bad_Opcode },
10347     { "psllw",          { MS, Ib }, 0 },
10348   },
10349   {
10350     /* MOD_0F72_REG_2 */
10351     { Bad_Opcode },
10352     { "psrld",          { MS, Ib }, 0 },
10353   },
10354   {
10355     /* MOD_0F72_REG_4 */
10356     { Bad_Opcode },
10357     { "psrad",          { MS, Ib }, 0 },
10358   },
10359   {
10360     /* MOD_0F72_REG_6 */
10361     { Bad_Opcode },
10362     { "pslld",          { MS, Ib }, 0 },
10363   },
10364   {
10365     /* MOD_0F73_REG_2 */
10366     { Bad_Opcode },
10367     { "psrlq",          { MS, Ib }, 0 },
10368   },
10369   {
10370     /* MOD_0F73_REG_3 */
10371     { Bad_Opcode },
10372     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10373   },
10374   {
10375     /* MOD_0F73_REG_6 */
10376     { Bad_Opcode },
10377     { "psllq",          { MS, Ib }, 0 },
10378   },
10379   {
10380     /* MOD_0F73_REG_7 */
10381     { Bad_Opcode },
10382     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10383   },
10384   {
10385     /* MOD_0FAE_REG_0 */
10386     { "fxsave",         { FXSAVE }, 0 },
10387     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10388   },
10389   {
10390     /* MOD_0FAE_REG_1 */
10391     { "fxrstor",        { FXSAVE }, 0 },
10392     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10393   },
10394   {
10395     /* MOD_0FAE_REG_2 */
10396     { "ldmxcsr",        { Md }, 0 },
10397     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10398   },
10399   {
10400     /* MOD_0FAE_REG_3 */
10401     { "stmxcsr",        { Md }, 0 },
10402     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10403   },
10404   {
10405     /* MOD_0FAE_REG_4 */
10406     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10407     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10408   },
10409   {
10410     /* MOD_0FAE_REG_5 */
10411     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10412     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10413   },
10414   {
10415     /* MOD_0FAE_REG_6 */
10416     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10417     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10418   },
10419   {
10420     /* MOD_0FAE_REG_7 */
10421     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10422     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10423   },
10424   {
10425     /* MOD_0FB2 */
10426     { "lssS",           { Gv, Mp }, 0 },
10427   },
10428   {
10429     /* MOD_0FB4 */
10430     { "lfsS",           { Gv, Mp }, 0 },
10431   },
10432   {
10433     /* MOD_0FB5 */
10434     { "lgsS",           { Gv, Mp }, 0 },
10435   },
10436   {
10437     /* MOD_0FC3 */
10438     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10439   },
10440   {
10441     /* MOD_0FC7_REG_3 */
10442     { "xrstors",        { FXSAVE }, 0 },
10443   },
10444   {
10445     /* MOD_0FC7_REG_4 */
10446     { "xsavec",         { FXSAVE }, 0 },
10447   },
10448   {
10449     /* MOD_0FC7_REG_5 */
10450     { "xsaves",         { FXSAVE }, 0 },
10451   },
10452   {
10453     /* MOD_0FC7_REG_6 */
10454     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10455     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10456   },
10457   {
10458     /* MOD_0FC7_REG_7 */
10459     { "vmptrst",        { Mq }, 0 },
10460     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10461   },
10462   {
10463     /* MOD_0FD7 */
10464     { Bad_Opcode },
10465     { "pmovmskb",       { Gdq, MS }, 0 },
10466   },
10467   {
10468     /* MOD_0FE7_PREFIX_2 */
10469     { "movntdq",        { Mx, XM }, 0 },
10470   },
10471   {
10472     /* MOD_0FF0_PREFIX_3 */
10473     { "lddqu",          { XM, M }, 0 },
10474   },
10475   {
10476     /* MOD_0F382A_PREFIX_2 */
10477     { "movntdqa",       { XM, Mx }, 0 },
10478   },
10479   {
10480     /* MOD_0F38F5_PREFIX_2 */
10481     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10482   },
10483   {
10484     /* MOD_0F38F6_PREFIX_0 */
10485     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10486   },
10487   {
10488     /* MOD_0F38F8_PREFIX_1 */
10489     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10490   },
10491   {
10492     /* MOD_0F38F8_PREFIX_2 */
10493     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10494   },
10495   {
10496     /* MOD_0F38F8_PREFIX_3 */
10497     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10498   },
10499   {
10500     /* MOD_0F38F9_PREFIX_0 */
10501     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10502   },
10503   {
10504     /* MOD_62_32BIT */
10505     { "bound{S|}",      { Gv, Ma }, 0 },
10506     { EVEX_TABLE (EVEX_0F) },
10507   },
10508   {
10509     /* MOD_C4_32BIT */
10510     { "lesS",           { Gv, Mp }, 0 },
10511     { VEX_C4_TABLE (VEX_0F) },
10512   },
10513   {
10514     /* MOD_C5_32BIT */
10515     { "ldsS",           { Gv, Mp }, 0 },
10516     { VEX_C5_TABLE (VEX_0F) },
10517   },
10518   {
10519     /* MOD_VEX_0F12_PREFIX_0 */
10520     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10521     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10522   },
10523   {
10524     /* MOD_VEX_0F12_PREFIX_2 */
10525     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10526   },
10527   {
10528     /* MOD_VEX_0F13 */
10529     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10530   },
10531   {
10532     /* MOD_VEX_0F16_PREFIX_0 */
10533     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10534     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10535   },
10536   {
10537     /* MOD_VEX_0F16_PREFIX_2 */
10538     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10539   },
10540   {
10541     /* MOD_VEX_0F17 */
10542     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10543   },
10544   {
10545     /* MOD_VEX_0F2B */
10546     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10547   },
10548   {
10549     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10550     { Bad_Opcode },
10551     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10552   },
10553   {
10554     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10555     { Bad_Opcode },
10556     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10557   },
10558   {
10559     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10560     { Bad_Opcode },
10561     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10562   },
10563   {
10564     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10565     { Bad_Opcode },
10566     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10567   },
10568   {
10569     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10570     { Bad_Opcode },
10571     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10572   },
10573   {
10574     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10575     { Bad_Opcode },
10576     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10577   },
10578   {
10579     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10580     { Bad_Opcode },
10581     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10582   },
10583   {
10584     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10585     { Bad_Opcode },
10586     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10587   },
10588   {
10589     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10590     { Bad_Opcode },
10591     { "knotw",          { MaskG, MaskR }, 0 },
10592   },
10593   {
10594     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10595     { Bad_Opcode },
10596     { "knotq",          { MaskG, MaskR }, 0 },
10597   },
10598   {
10599     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10600     { Bad_Opcode },
10601     { "knotb",          { MaskG, MaskR }, 0 },
10602   },
10603   {
10604     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10605     { Bad_Opcode },
10606     { "knotd",          { MaskG, MaskR }, 0 },
10607   },
10608   {
10609     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10610     { Bad_Opcode },
10611     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10612   },
10613   {
10614     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10615     { Bad_Opcode },
10616     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10617   },
10618   {
10619     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10620     { Bad_Opcode },
10621     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10622   },
10623   {
10624     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10625     { Bad_Opcode },
10626     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10627   },
10628  {
10629     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10630     { Bad_Opcode },
10631     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10632   },
10633   {
10634     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10635     { Bad_Opcode },
10636     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10637   },
10638   {
10639     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10640     { Bad_Opcode },
10641     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10642   },
10643   {
10644     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10645     { Bad_Opcode },
10646     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10647   },
10648   {
10649     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10650     { Bad_Opcode },
10651     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10652   },
10653   {
10654     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10655     { Bad_Opcode },
10656     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10657   },
10658   {
10659     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10660     { Bad_Opcode },
10661     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10662   },
10663   {
10664     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10665     { Bad_Opcode },
10666     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10667   },
10668   {
10669     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10670     { Bad_Opcode },
10671     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10672   },
10673   {
10674     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10675     { Bad_Opcode },
10676     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10677   },
10678   {
10679     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10680     { Bad_Opcode },
10681     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10682   },
10683   {
10684     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10685     { Bad_Opcode },
10686     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10687   },
10688   {
10689     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10690     { Bad_Opcode },
10691     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10692   },
10693   {
10694     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10695     { Bad_Opcode },
10696     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10697   },
10698   {
10699     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10700     { Bad_Opcode },
10701     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10702   },
10703   {
10704     /* MOD_VEX_0F50 */
10705     { Bad_Opcode },
10706     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10707   },
10708   {
10709     /* MOD_VEX_0F71_REG_2 */
10710     { Bad_Opcode },
10711     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10712   },
10713   {
10714     /* MOD_VEX_0F71_REG_4 */
10715     { Bad_Opcode },
10716     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10717   },
10718   {
10719     /* MOD_VEX_0F71_REG_6 */
10720     { Bad_Opcode },
10721     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10722   },
10723   {
10724     /* MOD_VEX_0F72_REG_2 */
10725     { Bad_Opcode },
10726     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10727   },
10728   {
10729     /* MOD_VEX_0F72_REG_4 */
10730     { Bad_Opcode },
10731     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10732   },
10733   {
10734     /* MOD_VEX_0F72_REG_6 */
10735     { Bad_Opcode },
10736     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10737   },
10738   {
10739     /* MOD_VEX_0F73_REG_2 */
10740     { Bad_Opcode },
10741     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10742   },
10743   {
10744     /* MOD_VEX_0F73_REG_3 */
10745     { Bad_Opcode },
10746     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10747   },
10748   {
10749     /* MOD_VEX_0F73_REG_6 */
10750     { Bad_Opcode },
10751     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10752   },
10753   {
10754     /* MOD_VEX_0F73_REG_7 */
10755     { Bad_Opcode },
10756     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10757   },
10758   {
10759     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10760     { "kmovw",          { Ew, MaskG }, 0 },
10761     { Bad_Opcode },
10762   },
10763   {
10764     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10765     { "kmovq",          { Eq, MaskG }, 0 },
10766     { Bad_Opcode },
10767   },
10768   {
10769     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10770     { "kmovb",          { Eb, MaskG }, 0 },
10771     { Bad_Opcode },
10772   },
10773   {
10774     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10775     { "kmovd",          { Ed, MaskG }, 0 },
10776     { Bad_Opcode },
10777   },
10778   {
10779     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10780     { Bad_Opcode },
10781     { "kmovw",          { MaskG, Rdq }, 0 },
10782   },
10783   {
10784     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10785     { Bad_Opcode },
10786     { "kmovb",          { MaskG, Rdq }, 0 },
10787   },
10788   {
10789     /* MOD_VEX_0F92_P_3_LEN_0 */
10790     { Bad_Opcode },
10791     { "kmovK",          { MaskG, Rdq }, 0 },
10792   },
10793   {
10794     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10795     { Bad_Opcode },
10796     { "kmovw",          { Gdq, MaskR }, 0 },
10797   },
10798   {
10799     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10800     { Bad_Opcode },
10801     { "kmovb",          { Gdq, MaskR }, 0 },
10802   },
10803   {
10804     /* MOD_VEX_0F93_P_3_LEN_0 */
10805     { Bad_Opcode },
10806     { "kmovK",          { Gdq, MaskR }, 0 },
10807   },
10808   {
10809     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10810     { Bad_Opcode },
10811     { "kortestw", { MaskG, MaskR }, 0 },
10812   },
10813   {
10814     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10815     { Bad_Opcode },
10816     { "kortestq", { MaskG, MaskR }, 0 },
10817   },
10818   {
10819     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10820     { Bad_Opcode },
10821     { "kortestb", { MaskG, MaskR }, 0 },
10822   },
10823   {
10824     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10825     { Bad_Opcode },
10826     { "kortestd", { MaskG, MaskR }, 0 },
10827   },
10828   {
10829     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10830     { Bad_Opcode },
10831     { "ktestw", { MaskG, MaskR }, 0 },
10832   },
10833   {
10834     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10835     { Bad_Opcode },
10836     { "ktestq", { MaskG, MaskR }, 0 },
10837   },
10838   {
10839     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10840     { Bad_Opcode },
10841     { "ktestb", { MaskG, MaskR }, 0 },
10842   },
10843   {
10844     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10845     { Bad_Opcode },
10846     { "ktestd", { MaskG, MaskR }, 0 },
10847   },
10848   {
10849     /* MOD_VEX_0FAE_REG_2 */
10850     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10851   },
10852   {
10853     /* MOD_VEX_0FAE_REG_3 */
10854     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10855   },
10856   {
10857     /* MOD_VEX_0FD7_PREFIX_2 */
10858     { Bad_Opcode },
10859     { "vpmovmskb",      { Gdq, XS }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_0FE7_PREFIX_2 */
10863     { "vmovntdq",       { Mx, XM }, 0 },
10864   },
10865   {
10866     /* MOD_VEX_0FF0_PREFIX_3 */
10867     { "vlddqu",         { XM, M }, 0 },
10868   },
10869   {
10870     /* MOD_VEX_0F381A_PREFIX_2 */
10871     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10872   },
10873   {
10874     /* MOD_VEX_0F382A_PREFIX_2 */
10875     { "vmovntdqa",      { XM, Mx }, 0 },
10876   },
10877   {
10878     /* MOD_VEX_0F382C_PREFIX_2 */
10879     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10880   },
10881   {
10882     /* MOD_VEX_0F382D_PREFIX_2 */
10883     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10884   },
10885   {
10886     /* MOD_VEX_0F382E_PREFIX_2 */
10887     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10888   },
10889   {
10890     /* MOD_VEX_0F382F_PREFIX_2 */
10891     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10892   },
10893   {
10894     /* MOD_VEX_0F385A_PREFIX_2 */
10895     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10896   },
10897   {
10898     /* MOD_VEX_0F388C_PREFIX_2 */
10899     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10900   },
10901   {
10902     /* MOD_VEX_0F388E_PREFIX_2 */
10903     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10904   },
10905   {
10906     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10907     { Bad_Opcode },
10908     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10909   },
10910   {
10911     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10912     { Bad_Opcode },
10913     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10914   },
10915   {
10916     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10917     { Bad_Opcode },
10918     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10919   },
10920   {
10921     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10922     { Bad_Opcode },
10923     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10924   },
10925   {
10926     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10927     { Bad_Opcode },
10928     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10929   },
10930   {
10931     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10932     { Bad_Opcode },
10933     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10934   },
10935   {
10936     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10937     { Bad_Opcode },
10938     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10939   },
10940   {
10941     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10942     { Bad_Opcode },
10943     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10944   },
10945
10946 #include "i386-dis-evex-mod.h"
10947 };
10948
10949 static const struct dis386 rm_table[][8] = {
10950   {
10951     /* RM_C6_REG_7 */
10952     { "xabort",         { Skip_MODRM, Ib }, 0 },
10953   },
10954   {
10955     /* RM_C7_REG_7 */
10956     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10957   },
10958   {
10959     /* RM_0F01_REG_0 */
10960     { "enclv",          { Skip_MODRM }, 0 },
10961     { "vmcall",         { Skip_MODRM }, 0 },
10962     { "vmlaunch",       { Skip_MODRM }, 0 },
10963     { "vmresume",       { Skip_MODRM }, 0 },
10964     { "vmxoff",         { Skip_MODRM }, 0 },
10965     { "pconfig",        { Skip_MODRM }, 0 },
10966   },
10967   {
10968     /* RM_0F01_REG_1 */
10969     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10970     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10971     { "clac",           { Skip_MODRM }, 0 },
10972     { "stac",           { Skip_MODRM }, 0 },
10973     { Bad_Opcode },
10974     { Bad_Opcode },
10975     { Bad_Opcode },
10976     { "encls",          { Skip_MODRM }, 0 },
10977   },
10978   {
10979     /* RM_0F01_REG_2 */
10980     { "xgetbv",         { Skip_MODRM }, 0 },
10981     { "xsetbv",         { Skip_MODRM }, 0 },
10982     { Bad_Opcode },
10983     { Bad_Opcode },
10984     { "vmfunc",         { Skip_MODRM }, 0 },
10985     { "xend",           { Skip_MODRM }, 0 },
10986     { "xtest",          { Skip_MODRM }, 0 },
10987     { "enclu",          { Skip_MODRM }, 0 },
10988   },
10989   {
10990     /* RM_0F01_REG_3 */
10991     { "vmrun",          { Skip_MODRM }, 0 },
10992     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10993     { "vmload",         { Skip_MODRM }, 0 },
10994     { "vmsave",         { Skip_MODRM }, 0 },
10995     { "stgi",           { Skip_MODRM }, 0 },
10996     { "clgi",           { Skip_MODRM }, 0 },
10997     { "skinit",         { Skip_MODRM }, 0 },
10998     { "invlpga",        { Skip_MODRM }, 0 },
10999   },
11000   {
11001     /* RM_0F01_REG_5_MOD_3 */
11002     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11003     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
11004     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11005     { Bad_Opcode },
11006     { Bad_Opcode },
11007     { Bad_Opcode },
11008     { "rdpkru",         { Skip_MODRM }, 0 },
11009     { "wrpkru",         { Skip_MODRM }, 0 },
11010   },
11011   {
11012     /* RM_0F01_REG_7_MOD_3 */
11013     { "swapgs",         { Skip_MODRM }, 0  },
11014     { "rdtscp",         { Skip_MODRM }, 0  },
11015     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11016     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11017     { "clzero",         { Skip_MODRM }, 0  },
11018     { "rdpru",          { Skip_MODRM }, 0  },
11019   },
11020   {
11021     /* RM_0F1E_P_1_MOD_3_REG_7 */
11022     { "nopQ",           { Ev }, 0 },
11023     { "nopQ",           { Ev }, 0 },
11024     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11025     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11026     { "nopQ",           { Ev }, 0 },
11027     { "nopQ",           { Ev }, 0 },
11028     { "nopQ",           { Ev }, 0 },
11029     { "nopQ",           { Ev }, 0 },
11030   },
11031   {
11032     /* RM_0FAE_REG_6_MOD_3 */
11033     { "mfence",         { Skip_MODRM }, 0 },
11034   },
11035   {
11036     /* RM_0FAE_REG_7_MOD_3 */
11037     { "sfence",         { Skip_MODRM }, 0 },
11038
11039   },
11040 };
11041
11042 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11043
11044 /* We use the high bit to indicate different name for the same
11045    prefix.  */
11046 #define REP_PREFIX      (0xf3 | 0x100)
11047 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11048 #define XRELEASE_PREFIX (0xf3 | 0x400)
11049 #define BND_PREFIX      (0xf2 | 0x400)
11050 #define NOTRACK_PREFIX  (0x3e | 0x100)
11051
11052 /* Remember if the current op is a jump instruction.  */
11053 static bfd_boolean op_is_jump = FALSE;
11054
11055 static int
11056 ckprefix (void)
11057 {
11058   int newrex, i, length;
11059   rex = 0;
11060   rex_ignored = 0;
11061   prefixes = 0;
11062   used_prefixes = 0;
11063   rex_used = 0;
11064   last_lock_prefix = -1;
11065   last_repz_prefix = -1;
11066   last_repnz_prefix = -1;
11067   last_data_prefix = -1;
11068   last_addr_prefix = -1;
11069   last_rex_prefix = -1;
11070   last_seg_prefix = -1;
11071   fwait_prefix = -1;
11072   active_seg_prefix = 0;
11073   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11074     all_prefixes[i] = 0;
11075   i = 0;
11076   length = 0;
11077   /* The maximum instruction length is 15bytes.  */
11078   while (length < MAX_CODE_LENGTH - 1)
11079     {
11080       FETCH_DATA (the_info, codep + 1);
11081       newrex = 0;
11082       switch (*codep)
11083         {
11084         /* REX prefixes family.  */
11085         case 0x40:
11086         case 0x41:
11087         case 0x42:
11088         case 0x43:
11089         case 0x44:
11090         case 0x45:
11091         case 0x46:
11092         case 0x47:
11093         case 0x48:
11094         case 0x49:
11095         case 0x4a:
11096         case 0x4b:
11097         case 0x4c:
11098         case 0x4d:
11099         case 0x4e:
11100         case 0x4f:
11101           if (address_mode == mode_64bit)
11102             newrex = *codep;
11103           else
11104             return 1;
11105           last_rex_prefix = i;
11106           break;
11107         case 0xf3:
11108           prefixes |= PREFIX_REPZ;
11109           last_repz_prefix = i;
11110           break;
11111         case 0xf2:
11112           prefixes |= PREFIX_REPNZ;
11113           last_repnz_prefix = i;
11114           break;
11115         case 0xf0:
11116           prefixes |= PREFIX_LOCK;
11117           last_lock_prefix = i;
11118           break;
11119         case 0x2e:
11120           prefixes |= PREFIX_CS;
11121           last_seg_prefix = i;
11122           active_seg_prefix = PREFIX_CS;
11123           break;
11124         case 0x36:
11125           prefixes |= PREFIX_SS;
11126           last_seg_prefix = i;
11127           active_seg_prefix = PREFIX_SS;
11128           break;
11129         case 0x3e:
11130           prefixes |= PREFIX_DS;
11131           last_seg_prefix = i;
11132           active_seg_prefix = PREFIX_DS;
11133           break;
11134         case 0x26:
11135           prefixes |= PREFIX_ES;
11136           last_seg_prefix = i;
11137           active_seg_prefix = PREFIX_ES;
11138           break;
11139         case 0x64:
11140           prefixes |= PREFIX_FS;
11141           last_seg_prefix = i;
11142           active_seg_prefix = PREFIX_FS;
11143           break;
11144         case 0x65:
11145           prefixes |= PREFIX_GS;
11146           last_seg_prefix = i;
11147           active_seg_prefix = PREFIX_GS;
11148           break;
11149         case 0x66:
11150           prefixes |= PREFIX_DATA;
11151           last_data_prefix = i;
11152           break;
11153         case 0x67:
11154           prefixes |= PREFIX_ADDR;
11155           last_addr_prefix = i;
11156           break;
11157         case FWAIT_OPCODE:
11158           /* fwait is really an instruction.  If there are prefixes
11159              before the fwait, they belong to the fwait, *not* to the
11160              following instruction.  */
11161           fwait_prefix = i;
11162           if (prefixes || rex)
11163             {
11164               prefixes |= PREFIX_FWAIT;
11165               codep++;
11166               /* This ensures that the previous REX prefixes are noticed
11167                  as unused prefixes, as in the return case below.  */
11168               rex_used = rex;
11169               return 1;
11170             }
11171           prefixes = PREFIX_FWAIT;
11172           break;
11173         default:
11174           return 1;
11175         }
11176       /* Rex is ignored when followed by another prefix.  */
11177       if (rex)
11178         {
11179           rex_used = rex;
11180           return 1;
11181         }
11182       if (*codep != FWAIT_OPCODE)
11183         all_prefixes[i++] = *codep;
11184       rex = newrex;
11185       codep++;
11186       length++;
11187     }
11188   return 0;
11189 }
11190
11191 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11192    prefix byte.  */
11193
11194 static const char *
11195 prefix_name (int pref, int sizeflag)
11196 {
11197   static const char *rexes [16] =
11198     {
11199       "rex",            /* 0x40 */
11200       "rex.B",          /* 0x41 */
11201       "rex.X",          /* 0x42 */
11202       "rex.XB",         /* 0x43 */
11203       "rex.R",          /* 0x44 */
11204       "rex.RB",         /* 0x45 */
11205       "rex.RX",         /* 0x46 */
11206       "rex.RXB",        /* 0x47 */
11207       "rex.W",          /* 0x48 */
11208       "rex.WB",         /* 0x49 */
11209       "rex.WX",         /* 0x4a */
11210       "rex.WXB",        /* 0x4b */
11211       "rex.WR",         /* 0x4c */
11212       "rex.WRB",        /* 0x4d */
11213       "rex.WRX",        /* 0x4e */
11214       "rex.WRXB",       /* 0x4f */
11215     };
11216
11217   switch (pref)
11218     {
11219     /* REX prefixes family.  */
11220     case 0x40:
11221     case 0x41:
11222     case 0x42:
11223     case 0x43:
11224     case 0x44:
11225     case 0x45:
11226     case 0x46:
11227     case 0x47:
11228     case 0x48:
11229     case 0x49:
11230     case 0x4a:
11231     case 0x4b:
11232     case 0x4c:
11233     case 0x4d:
11234     case 0x4e:
11235     case 0x4f:
11236       return rexes [pref - 0x40];
11237     case 0xf3:
11238       return "repz";
11239     case 0xf2:
11240       return "repnz";
11241     case 0xf0:
11242       return "lock";
11243     case 0x2e:
11244       return "cs";
11245     case 0x36:
11246       return "ss";
11247     case 0x3e:
11248       return "ds";
11249     case 0x26:
11250       return "es";
11251     case 0x64:
11252       return "fs";
11253     case 0x65:
11254       return "gs";
11255     case 0x66:
11256       return (sizeflag & DFLAG) ? "data16" : "data32";
11257     case 0x67:
11258       if (address_mode == mode_64bit)
11259         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11260       else
11261         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11262     case FWAIT_OPCODE:
11263       return "fwait";
11264     case REP_PREFIX:
11265       return "rep";
11266     case XACQUIRE_PREFIX:
11267       return "xacquire";
11268     case XRELEASE_PREFIX:
11269       return "xrelease";
11270     case BND_PREFIX:
11271       return "bnd";
11272     case NOTRACK_PREFIX:
11273       return "notrack";
11274     default:
11275       return NULL;
11276     }
11277 }
11278
11279 static char op_out[MAX_OPERANDS][100];
11280 static int op_ad, op_index[MAX_OPERANDS];
11281 static int two_source_ops;
11282 static bfd_vma op_address[MAX_OPERANDS];
11283 static bfd_vma op_riprel[MAX_OPERANDS];
11284 static bfd_vma start_pc;
11285
11286 /*
11287  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11288  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11289  *   section of the "Virtual 8086 Mode" chapter.)
11290  * 'pc' should be the address of this instruction, it will
11291  *   be used to print the target address if this is a relative jump or call
11292  * The function returns the length of this instruction in bytes.
11293  */
11294
11295 static char intel_syntax;
11296 static char intel_mnemonic = !SYSV386_COMPAT;
11297 static char open_char;
11298 static char close_char;
11299 static char separator_char;
11300 static char scale_char;
11301
11302 enum x86_64_isa
11303 {
11304   amd64 = 1,
11305   intel64
11306 };
11307
11308 static enum x86_64_isa isa64;
11309
11310 /* Here for backwards compatibility.  When gdb stops using
11311    print_insn_i386_att and print_insn_i386_intel these functions can
11312    disappear, and print_insn_i386 be merged into print_insn.  */
11313 int
11314 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11315 {
11316   intel_syntax = 0;
11317
11318   return print_insn (pc, info);
11319 }
11320
11321 int
11322 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11323 {
11324   intel_syntax = 1;
11325
11326   return print_insn (pc, info);
11327 }
11328
11329 int
11330 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11331 {
11332   intel_syntax = -1;
11333
11334   return print_insn (pc, info);
11335 }
11336
11337 void
11338 print_i386_disassembler_options (FILE *stream)
11339 {
11340   fprintf (stream, _("\n\
11341 The following i386/x86-64 specific disassembler options are supported for use\n\
11342 with the -M switch (multiple options should be separated by commas):\n"));
11343
11344   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11345   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11346   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11347   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11348   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11349   fprintf (stream, _("  att-mnemonic\n"
11350                      "              Display instruction in AT&T mnemonic\n"));
11351   fprintf (stream, _("  intel-mnemonic\n"
11352                      "              Display instruction in Intel mnemonic\n"));
11353   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11354   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11355   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11356   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11357   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11358   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11359   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11360   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11361 }
11362
11363 /* Bad opcode.  */
11364 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11365
11366 /* Get a pointer to struct dis386 with a valid name.  */
11367
11368 static const struct dis386 *
11369 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11370 {
11371   int vindex, vex_table_index;
11372
11373   if (dp->name != NULL)
11374     return dp;
11375
11376   switch (dp->op[0].bytemode)
11377     {
11378     case USE_REG_TABLE:
11379       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11380       break;
11381
11382     case USE_MOD_TABLE:
11383       vindex = modrm.mod == 0x3 ? 1 : 0;
11384       dp = &mod_table[dp->op[1].bytemode][vindex];
11385       break;
11386
11387     case USE_RM_TABLE:
11388       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11389       break;
11390
11391     case USE_PREFIX_TABLE:
11392       if (need_vex)
11393         {
11394           /* The prefix in VEX is implicit.  */
11395           switch (vex.prefix)
11396             {
11397             case 0:
11398               vindex = 0;
11399               break;
11400             case REPE_PREFIX_OPCODE:
11401               vindex = 1;
11402               break;
11403             case DATA_PREFIX_OPCODE:
11404               vindex = 2;
11405               break;
11406             case REPNE_PREFIX_OPCODE:
11407               vindex = 3;
11408               break;
11409             default:
11410               abort ();
11411               break;
11412             }
11413         }
11414       else
11415         {
11416           int last_prefix = -1;
11417           int prefix = 0;
11418           vindex = 0;
11419           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11420              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11421              last one wins.  */
11422           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11423             {
11424               if (last_repz_prefix > last_repnz_prefix)
11425                 {
11426                   vindex = 1;
11427                   prefix = PREFIX_REPZ;
11428                   last_prefix = last_repz_prefix;
11429                 }
11430               else
11431                 {
11432                   vindex = 3;
11433                   prefix = PREFIX_REPNZ;
11434                   last_prefix = last_repnz_prefix;
11435                 }
11436
11437               /* Check if prefix should be ignored.  */
11438               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11439                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11440                    & prefix) != 0)
11441                 vindex = 0;
11442             }
11443
11444           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11445             {
11446               vindex = 2;
11447               prefix = PREFIX_DATA;
11448               last_prefix = last_data_prefix;
11449             }
11450
11451           if (vindex != 0)
11452             {
11453               used_prefixes |= prefix;
11454               all_prefixes[last_prefix] = 0;
11455             }
11456         }
11457       dp = &prefix_table[dp->op[1].bytemode][vindex];
11458       break;
11459
11460     case USE_X86_64_TABLE:
11461       vindex = address_mode == mode_64bit ? 1 : 0;
11462       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11463       break;
11464
11465     case USE_3BYTE_TABLE:
11466       FETCH_DATA (info, codep + 2);
11467       vindex = *codep++;
11468       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11469       end_codep = codep;
11470       modrm.mod = (*codep >> 6) & 3;
11471       modrm.reg = (*codep >> 3) & 7;
11472       modrm.rm = *codep & 7;
11473       break;
11474
11475     case USE_VEX_LEN_TABLE:
11476       if (!need_vex)
11477         abort ();
11478
11479       switch (vex.length)
11480         {
11481         case 128:
11482           vindex = 0;
11483           break;
11484         case 256:
11485           vindex = 1;
11486           break;
11487         default:
11488           abort ();
11489           break;
11490         }
11491
11492       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11493       break;
11494
11495     case USE_EVEX_LEN_TABLE:
11496       if (!vex.evex)
11497         abort ();
11498
11499       switch (vex.length)
11500         {
11501         case 128:
11502           vindex = 0;
11503           break;
11504         case 256:
11505           vindex = 1;
11506           break;
11507         case 512:
11508           vindex = 2;
11509           break;
11510         default:
11511           abort ();
11512           break;
11513         }
11514
11515       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11516       break;
11517
11518     case USE_XOP_8F_TABLE:
11519       FETCH_DATA (info, codep + 3);
11520       /* All bits in the REX prefix are ignored.  */
11521       rex_ignored = rex;
11522       rex = ~(*codep >> 5) & 0x7;
11523
11524       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11525       switch ((*codep & 0x1f))
11526         {
11527         default:
11528           dp = &bad_opcode;
11529           return dp;
11530         case 0x8:
11531           vex_table_index = XOP_08;
11532           break;
11533         case 0x9:
11534           vex_table_index = XOP_09;
11535           break;
11536         case 0xa:
11537           vex_table_index = XOP_0A;
11538           break;
11539         }
11540       codep++;
11541       vex.w = *codep & 0x80;
11542       if (vex.w && address_mode == mode_64bit)
11543         rex |= REX_W;
11544
11545       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11546       if (address_mode != mode_64bit)
11547         {
11548           /* In 16/32-bit mode REX_B is silently ignored.  */
11549           rex &= ~REX_B;
11550         }
11551
11552       vex.length = (*codep & 0x4) ? 256 : 128;
11553       switch ((*codep & 0x3))
11554         {
11555         case 0:
11556           break;
11557         case 1:
11558           vex.prefix = DATA_PREFIX_OPCODE;
11559           break;
11560         case 2:
11561           vex.prefix = REPE_PREFIX_OPCODE;
11562           break;
11563         case 3:
11564           vex.prefix = REPNE_PREFIX_OPCODE;
11565           break;
11566         }
11567       need_vex = 1;
11568       need_vex_reg = 1;
11569       codep++;
11570       vindex = *codep++;
11571       dp = &xop_table[vex_table_index][vindex];
11572
11573       end_codep = codep;
11574       FETCH_DATA (info, codep + 1);
11575       modrm.mod = (*codep >> 6) & 3;
11576       modrm.reg = (*codep >> 3) & 7;
11577       modrm.rm = *codep & 7;
11578       break;
11579
11580     case USE_VEX_C4_TABLE:
11581       /* VEX prefix.  */
11582       FETCH_DATA (info, codep + 3);
11583       /* All bits in the REX prefix are ignored.  */
11584       rex_ignored = rex;
11585       rex = ~(*codep >> 5) & 0x7;
11586       switch ((*codep & 0x1f))
11587         {
11588         default:
11589           dp = &bad_opcode;
11590           return dp;
11591         case 0x1:
11592           vex_table_index = VEX_0F;
11593           break;
11594         case 0x2:
11595           vex_table_index = VEX_0F38;
11596           break;
11597         case 0x3:
11598           vex_table_index = VEX_0F3A;
11599           break;
11600         }
11601       codep++;
11602       vex.w = *codep & 0x80;
11603       if (address_mode == mode_64bit)
11604         {
11605           if (vex.w)
11606             rex |= REX_W;
11607         }
11608       else
11609         {
11610           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11611              is ignored, other REX bits are 0 and the highest bit in
11612              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11613           rex = 0;
11614         }
11615       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11616       vex.length = (*codep & 0x4) ? 256 : 128;
11617       switch ((*codep & 0x3))
11618         {
11619         case 0:
11620           break;
11621         case 1:
11622           vex.prefix = DATA_PREFIX_OPCODE;
11623           break;
11624         case 2:
11625           vex.prefix = REPE_PREFIX_OPCODE;
11626           break;
11627         case 3:
11628           vex.prefix = REPNE_PREFIX_OPCODE;
11629           break;
11630         }
11631       need_vex = 1;
11632       need_vex_reg = 1;
11633       codep++;
11634       vindex = *codep++;
11635       dp = &vex_table[vex_table_index][vindex];
11636       end_codep = codep;
11637       /* There is no MODRM byte for VEX0F 77.  */
11638       if (vex_table_index != VEX_0F || vindex != 0x77)
11639         {
11640           FETCH_DATA (info, codep + 1);
11641           modrm.mod = (*codep >> 6) & 3;
11642           modrm.reg = (*codep >> 3) & 7;
11643           modrm.rm = *codep & 7;
11644         }
11645       break;
11646
11647     case USE_VEX_C5_TABLE:
11648       /* VEX prefix.  */
11649       FETCH_DATA (info, codep + 2);
11650       /* All bits in the REX prefix are ignored.  */
11651       rex_ignored = rex;
11652       rex = (*codep & 0x80) ? 0 : REX_R;
11653
11654       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11655          VEX.vvvv is 1.  */
11656       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11657       vex.length = (*codep & 0x4) ? 256 : 128;
11658       switch ((*codep & 0x3))
11659         {
11660         case 0:
11661           break;
11662         case 1:
11663           vex.prefix = DATA_PREFIX_OPCODE;
11664           break;
11665         case 2:
11666           vex.prefix = REPE_PREFIX_OPCODE;
11667           break;
11668         case 3:
11669           vex.prefix = REPNE_PREFIX_OPCODE;
11670           break;
11671         }
11672       need_vex = 1;
11673       need_vex_reg = 1;
11674       codep++;
11675       vindex = *codep++;
11676       dp = &vex_table[dp->op[1].bytemode][vindex];
11677       end_codep = codep;
11678       /* There is no MODRM byte for VEX 77.  */
11679       if (vindex != 0x77)
11680         {
11681           FETCH_DATA (info, codep + 1);
11682           modrm.mod = (*codep >> 6) & 3;
11683           modrm.reg = (*codep >> 3) & 7;
11684           modrm.rm = *codep & 7;
11685         }
11686       break;
11687
11688     case USE_VEX_W_TABLE:
11689       if (!need_vex)
11690         abort ();
11691
11692       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11693       break;
11694
11695     case USE_EVEX_TABLE:
11696       two_source_ops = 0;
11697       /* EVEX prefix.  */
11698       vex.evex = 1;
11699       FETCH_DATA (info, codep + 4);
11700       /* All bits in the REX prefix are ignored.  */
11701       rex_ignored = rex;
11702       /* The first byte after 0x62.  */
11703       rex = ~(*codep >> 5) & 0x7;
11704       vex.r = *codep & 0x10;
11705       switch ((*codep & 0xf))
11706         {
11707         default:
11708           return &bad_opcode;
11709         case 0x1:
11710           vex_table_index = EVEX_0F;
11711           break;
11712         case 0x2:
11713           vex_table_index = EVEX_0F38;
11714           break;
11715         case 0x3:
11716           vex_table_index = EVEX_0F3A;
11717           break;
11718         }
11719
11720       /* The second byte after 0x62.  */
11721       codep++;
11722       vex.w = *codep & 0x80;
11723       if (vex.w && address_mode == mode_64bit)
11724         rex |= REX_W;
11725
11726       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11727
11728       /* The U bit.  */
11729       if (!(*codep & 0x4))
11730         return &bad_opcode;
11731
11732       switch ((*codep & 0x3))
11733         {
11734         case 0:
11735           break;
11736         case 1:
11737           vex.prefix = DATA_PREFIX_OPCODE;
11738           break;
11739         case 2:
11740           vex.prefix = REPE_PREFIX_OPCODE;
11741           break;
11742         case 3:
11743           vex.prefix = REPNE_PREFIX_OPCODE;
11744           break;
11745         }
11746
11747       /* The third byte after 0x62.  */
11748       codep++;
11749
11750       /* Remember the static rounding bits.  */
11751       vex.ll = (*codep >> 5) & 3;
11752       vex.b = (*codep & 0x10) != 0;
11753
11754       vex.v = *codep & 0x8;
11755       vex.mask_register_specifier = *codep & 0x7;
11756       vex.zeroing = *codep & 0x80;
11757
11758       if (address_mode != mode_64bit)
11759         {
11760           /* In 16/32-bit mode silently ignore following bits.  */
11761           rex &= ~REX_B;
11762           vex.r = 1;
11763           vex.v = 1;
11764         }
11765
11766       need_vex = 1;
11767       need_vex_reg = 1;
11768       codep++;
11769       vindex = *codep++;
11770       dp = &evex_table[vex_table_index][vindex];
11771       end_codep = codep;
11772       FETCH_DATA (info, codep + 1);
11773       modrm.mod = (*codep >> 6) & 3;
11774       modrm.reg = (*codep >> 3) & 7;
11775       modrm.rm = *codep & 7;
11776
11777       /* Set vector length.  */
11778       if (modrm.mod == 3 && vex.b)
11779         vex.length = 512;
11780       else
11781         {
11782           switch (vex.ll)
11783             {
11784             case 0x0:
11785               vex.length = 128;
11786               break;
11787             case 0x1:
11788               vex.length = 256;
11789               break;
11790             case 0x2:
11791               vex.length = 512;
11792               break;
11793             default:
11794               return &bad_opcode;
11795             }
11796         }
11797       break;
11798
11799     case 0:
11800       dp = &bad_opcode;
11801       break;
11802
11803     default:
11804       abort ();
11805     }
11806
11807   if (dp->name != NULL)
11808     return dp;
11809   else
11810     return get_valid_dis386 (dp, info);
11811 }
11812
11813 static void
11814 get_sib (disassemble_info *info, int sizeflag)
11815 {
11816   /* If modrm.mod == 3, operand must be register.  */
11817   if (need_modrm
11818       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11819       && modrm.mod != 3
11820       && modrm.rm == 4)
11821     {
11822       FETCH_DATA (info, codep + 2);
11823       sib.index = (codep [1] >> 3) & 7;
11824       sib.scale = (codep [1] >> 6) & 3;
11825       sib.base = codep [1] & 7;
11826     }
11827 }
11828
11829 static int
11830 print_insn (bfd_vma pc, disassemble_info *info)
11831 {
11832   const struct dis386 *dp;
11833   int i;
11834   char *op_txt[MAX_OPERANDS];
11835   int needcomma;
11836   int sizeflag, orig_sizeflag;
11837   const char *p;
11838   struct dis_private priv;
11839   int prefix_length;
11840
11841   priv.orig_sizeflag = AFLAG | DFLAG;
11842   if ((info->mach & bfd_mach_i386_i386) != 0)
11843     address_mode = mode_32bit;
11844   else if (info->mach == bfd_mach_i386_i8086)
11845     {
11846       address_mode = mode_16bit;
11847       priv.orig_sizeflag = 0;
11848     }
11849   else
11850     address_mode = mode_64bit;
11851
11852   if (intel_syntax == (char) -1)
11853     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11854
11855   for (p = info->disassembler_options; p != NULL; )
11856     {
11857       if (CONST_STRNEQ (p, "amd64"))
11858         isa64 = amd64;
11859       else if (CONST_STRNEQ (p, "intel64"))
11860         isa64 = intel64;
11861       else if (CONST_STRNEQ (p, "x86-64"))
11862         {
11863           address_mode = mode_64bit;
11864           priv.orig_sizeflag = AFLAG | DFLAG;
11865         }
11866       else if (CONST_STRNEQ (p, "i386"))
11867         {
11868           address_mode = mode_32bit;
11869           priv.orig_sizeflag = AFLAG | DFLAG;
11870         }
11871       else if (CONST_STRNEQ (p, "i8086"))
11872         {
11873           address_mode = mode_16bit;
11874           priv.orig_sizeflag = 0;
11875         }
11876       else if (CONST_STRNEQ (p, "intel"))
11877         {
11878           intel_syntax = 1;
11879           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11880             intel_mnemonic = 1;
11881         }
11882       else if (CONST_STRNEQ (p, "att"))
11883         {
11884           intel_syntax = 0;
11885           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11886             intel_mnemonic = 0;
11887         }
11888       else if (CONST_STRNEQ (p, "addr"))
11889         {
11890           if (address_mode == mode_64bit)
11891             {
11892               if (p[4] == '3' && p[5] == '2')
11893                 priv.orig_sizeflag &= ~AFLAG;
11894               else if (p[4] == '6' && p[5] == '4')
11895                 priv.orig_sizeflag |= AFLAG;
11896             }
11897           else
11898             {
11899               if (p[4] == '1' && p[5] == '6')
11900                 priv.orig_sizeflag &= ~AFLAG;
11901               else if (p[4] == '3' && p[5] == '2')
11902                 priv.orig_sizeflag |= AFLAG;
11903             }
11904         }
11905       else if (CONST_STRNEQ (p, "data"))
11906         {
11907           if (p[4] == '1' && p[5] == '6')
11908             priv.orig_sizeflag &= ~DFLAG;
11909           else if (p[4] == '3' && p[5] == '2')
11910             priv.orig_sizeflag |= DFLAG;
11911         }
11912       else if (CONST_STRNEQ (p, "suffix"))
11913         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11914
11915       p = strchr (p, ',');
11916       if (p != NULL)
11917         p++;
11918     }
11919
11920   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11921     {
11922       (*info->fprintf_func) (info->stream,
11923                              _("64-bit address is disabled"));
11924       return -1;
11925     }
11926
11927   if (intel_syntax)
11928     {
11929       names64 = intel_names64;
11930       names32 = intel_names32;
11931       names16 = intel_names16;
11932       names8 = intel_names8;
11933       names8rex = intel_names8rex;
11934       names_seg = intel_names_seg;
11935       names_mm = intel_names_mm;
11936       names_bnd = intel_names_bnd;
11937       names_xmm = intel_names_xmm;
11938       names_ymm = intel_names_ymm;
11939       names_zmm = intel_names_zmm;
11940       index64 = intel_index64;
11941       index32 = intel_index32;
11942       names_mask = intel_names_mask;
11943       index16 = intel_index16;
11944       open_char = '[';
11945       close_char = ']';
11946       separator_char = '+';
11947       scale_char = '*';
11948     }
11949   else
11950     {
11951       names64 = att_names64;
11952       names32 = att_names32;
11953       names16 = att_names16;
11954       names8 = att_names8;
11955       names8rex = att_names8rex;
11956       names_seg = att_names_seg;
11957       names_mm = att_names_mm;
11958       names_bnd = att_names_bnd;
11959       names_xmm = att_names_xmm;
11960       names_ymm = att_names_ymm;
11961       names_zmm = att_names_zmm;
11962       index64 = att_index64;
11963       index32 = att_index32;
11964       names_mask = att_names_mask;
11965       index16 = att_index16;
11966       open_char = '(';
11967       close_char =  ')';
11968       separator_char = ',';
11969       scale_char = ',';
11970     }
11971
11972   /* The output looks better if we put 7 bytes on a line, since that
11973      puts most long word instructions on a single line.  Use 8 bytes
11974      for Intel L1OM.  */
11975   if ((info->mach & bfd_mach_l1om) != 0)
11976     info->bytes_per_line = 8;
11977   else
11978     info->bytes_per_line = 7;
11979
11980   info->private_data = &priv;
11981   priv.max_fetched = priv.the_buffer;
11982   priv.insn_start = pc;
11983
11984   obuf[0] = 0;
11985   for (i = 0; i < MAX_OPERANDS; ++i)
11986     {
11987       op_out[i][0] = 0;
11988       op_index[i] = -1;
11989     }
11990
11991   the_info = info;
11992   start_pc = pc;
11993   start_codep = priv.the_buffer;
11994   codep = priv.the_buffer;
11995
11996   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11997     {
11998       const char *name;
11999
12000       /* Getting here means we tried for data but didn't get it.  That
12001          means we have an incomplete instruction of some sort.  Just
12002          print the first byte as a prefix or a .byte pseudo-op.  */
12003       if (codep > priv.the_buffer)
12004         {
12005           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12006           if (name != NULL)
12007             (*info->fprintf_func) (info->stream, "%s", name);
12008           else
12009             {
12010               /* Just print the first byte as a .byte instruction.  */
12011               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12012                                      (unsigned int) priv.the_buffer[0]);
12013             }
12014
12015           return 1;
12016         }
12017
12018       return -1;
12019     }
12020
12021   obufp = obuf;
12022   sizeflag = priv.orig_sizeflag;
12023
12024   if (!ckprefix () || rex_used)
12025     {
12026       /* Too many prefixes or unused REX prefixes.  */
12027       for (i = 0;
12028            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12029            i++)
12030         (*info->fprintf_func) (info->stream, "%s%s",
12031                                i == 0 ? "" : " ",
12032                                prefix_name (all_prefixes[i], sizeflag));
12033       return i;
12034     }
12035
12036   insn_codep = codep;
12037
12038   FETCH_DATA (info, codep + 1);
12039   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12040
12041   if (((prefixes & PREFIX_FWAIT)
12042        && ((*codep < 0xd8) || (*codep > 0xdf))))
12043     {
12044       /* Handle prefixes before fwait.  */
12045       for (i = 0; i < fwait_prefix && all_prefixes[i];
12046            i++)
12047         (*info->fprintf_func) (info->stream, "%s ",
12048                                prefix_name (all_prefixes[i], sizeflag));
12049       (*info->fprintf_func) (info->stream, "fwait");
12050       return i + 1;
12051     }
12052
12053   if (*codep == 0x0f)
12054     {
12055       unsigned char threebyte;
12056
12057       codep++;
12058       FETCH_DATA (info, codep + 1);
12059       threebyte = *codep;
12060       dp = &dis386_twobyte[threebyte];
12061       need_modrm = twobyte_has_modrm[*codep];
12062       codep++;
12063     }
12064   else
12065     {
12066       dp = &dis386[*codep];
12067       need_modrm = onebyte_has_modrm[*codep];
12068       codep++;
12069     }
12070
12071   /* Save sizeflag for printing the extra prefixes later before updating
12072      it for mnemonic and operand processing.  The prefix names depend
12073      only on the address mode.  */
12074   orig_sizeflag = sizeflag;
12075   if (prefixes & PREFIX_ADDR)
12076     sizeflag ^= AFLAG;
12077   if ((prefixes & PREFIX_DATA))
12078     sizeflag ^= DFLAG;
12079
12080   end_codep = codep;
12081   if (need_modrm)
12082     {
12083       FETCH_DATA (info, codep + 1);
12084       modrm.mod = (*codep >> 6) & 3;
12085       modrm.reg = (*codep >> 3) & 7;
12086       modrm.rm = *codep & 7;
12087     }
12088
12089   need_vex = 0;
12090   need_vex_reg = 0;
12091   vex_w_done = 0;
12092   memset (&vex, 0, sizeof (vex));
12093
12094   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12095     {
12096       get_sib (info, sizeflag);
12097       dofloat (sizeflag);
12098     }
12099   else
12100     {
12101       dp = get_valid_dis386 (dp, info);
12102       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12103         {
12104           get_sib (info, sizeflag);
12105           for (i = 0; i < MAX_OPERANDS; ++i)
12106             {
12107               obufp = op_out[i];
12108               op_ad = MAX_OPERANDS - 1 - i;
12109               if (dp->op[i].rtn)
12110                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12111               /* For EVEX instruction after the last operand masking
12112                  should be printed.  */
12113               if (i == 0 && vex.evex)
12114                 {
12115                   /* Don't print {%k0}.  */
12116                   if (vex.mask_register_specifier)
12117                     {
12118                       oappend ("{");
12119                       oappend (names_mask[vex.mask_register_specifier]);
12120                       oappend ("}");
12121                     }
12122                   if (vex.zeroing)
12123                     oappend ("{z}");
12124                 }
12125             }
12126         }
12127     }
12128
12129   /* Clear instruction information.  */
12130   if (the_info)
12131     {
12132       the_info->insn_info_valid = 0;
12133       the_info->branch_delay_insns = 0;
12134       the_info->data_size = 0;
12135       the_info->insn_type = dis_noninsn;
12136       the_info->target = 0;
12137       the_info->target2 = 0;
12138     }
12139
12140   /* Reset jump operation indicator.  */
12141   op_is_jump = FALSE;
12142
12143   {
12144     int jump_detection = 0;
12145
12146     /* Extract flags.  */
12147     for (i = 0; i < MAX_OPERANDS; ++i)
12148       {
12149         if ((dp->op[i].rtn == OP_J)
12150             || (dp->op[i].rtn == OP_indirE))
12151           jump_detection |= 1;
12152         else if ((dp->op[i].rtn == BND_Fixup)
12153                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12154           jump_detection |= 2;
12155         else if ((dp->op[i].bytemode == cond_jump_mode)
12156                  || (dp->op[i].bytemode == loop_jcxz_mode))
12157           jump_detection |= 4;
12158       }
12159
12160     /* Determine if this is a jump or branch.  */
12161     if ((jump_detection & 0x3) == 0x3)
12162       {
12163         op_is_jump = TRUE;
12164         if (jump_detection & 0x4)
12165           the_info->insn_type = dis_condbranch;
12166         else
12167           the_info->insn_type =
12168             (dp->name && !strncmp(dp->name, "call", 4))
12169             ? dis_jsr : dis_branch;
12170       }
12171   }
12172
12173   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12174      are all 0s in inverted form.  */
12175   if (need_vex && vex.register_specifier != 0)
12176     {
12177       (*info->fprintf_func) (info->stream, "(bad)");
12178       return end_codep - priv.the_buffer;
12179     }
12180
12181   /* Check if the REX prefix is used.  */
12182   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12183     all_prefixes[last_rex_prefix] = 0;
12184
12185   /* Check if the SEG prefix is used.  */
12186   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12187                    | PREFIX_FS | PREFIX_GS)) != 0
12188       && (used_prefixes & active_seg_prefix) != 0)
12189     all_prefixes[last_seg_prefix] = 0;
12190
12191   /* Check if the ADDR prefix is used.  */
12192   if ((prefixes & PREFIX_ADDR) != 0
12193       && (used_prefixes & PREFIX_ADDR) != 0)
12194     all_prefixes[last_addr_prefix] = 0;
12195
12196   /* Check if the DATA prefix is used.  */
12197   if ((prefixes & PREFIX_DATA) != 0
12198       && (used_prefixes & PREFIX_DATA) != 0)
12199     all_prefixes[last_data_prefix] = 0;
12200
12201   /* Print the extra prefixes.  */
12202   prefix_length = 0;
12203   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12204     if (all_prefixes[i])
12205       {
12206         const char *name;
12207         name = prefix_name (all_prefixes[i], orig_sizeflag);
12208         if (name == NULL)
12209           abort ();
12210         prefix_length += strlen (name) + 1;
12211         (*info->fprintf_func) (info->stream, "%s ", name);
12212       }
12213
12214   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12215      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12216      used by putop and MMX/SSE operand and may be overriden by the
12217      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12218      separately.  */
12219   if (dp->prefix_requirement == PREFIX_OPCODE
12220       && (((need_vex
12221             ? vex.prefix == REPE_PREFIX_OPCODE
12222               || vex.prefix == REPNE_PREFIX_OPCODE
12223             : (prefixes
12224                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12225            && (used_prefixes
12226                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12227           || (((need_vex
12228                 ? vex.prefix == DATA_PREFIX_OPCODE
12229                 : ((prefixes
12230                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12231                    == PREFIX_DATA))
12232                && (used_prefixes & PREFIX_DATA) == 0))
12233           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12234     {
12235       (*info->fprintf_func) (info->stream, "(bad)");
12236       return end_codep - priv.the_buffer;
12237     }
12238
12239   /* Check maximum code length.  */
12240   if ((codep - start_codep) > MAX_CODE_LENGTH)
12241     {
12242       (*info->fprintf_func) (info->stream, "(bad)");
12243       return MAX_CODE_LENGTH;
12244     }
12245
12246   obufp = mnemonicendp;
12247   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12248     oappend (" ");
12249   oappend (" ");
12250   (*info->fprintf_func) (info->stream, "%s", obuf);
12251
12252   /* The enter and bound instructions are printed with operands in the same
12253      order as the intel book; everything else is printed in reverse order.  */
12254   if (intel_syntax || two_source_ops)
12255     {
12256       bfd_vma riprel;
12257
12258       for (i = 0; i < MAX_OPERANDS; ++i)
12259         op_txt[i] = op_out[i];
12260
12261       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12262           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12263         {
12264           op_txt[2] = op_out[3];
12265           op_txt[3] = op_out[2];
12266         }
12267
12268       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12269         {
12270           op_ad = op_index[i];
12271           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12272           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12273           riprel = op_riprel[i];
12274           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12275           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12276         }
12277     }
12278   else
12279     {
12280       for (i = 0; i < MAX_OPERANDS; ++i)
12281         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12282     }
12283
12284   needcomma = 0;
12285   for (i = 0; i < MAX_OPERANDS; ++i)
12286     if (*op_txt[i])
12287       {
12288         if (needcomma)
12289           (*info->fprintf_func) (info->stream, ",");
12290         if (op_index[i] != -1 && !op_riprel[i])
12291           {
12292             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12293
12294             if (the_info && op_is_jump)
12295               {
12296                 the_info->insn_info_valid = 1;
12297                 the_info->branch_delay_insns = 0;
12298                 the_info->data_size = 0;
12299                 the_info->target = target;
12300                 the_info->target2 = 0;
12301               }
12302             (*info->print_address_func) (target, info);
12303           }
12304         else
12305           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12306         needcomma = 1;
12307       }
12308
12309   for (i = 0; i < MAX_OPERANDS; i++)
12310     if (op_index[i] != -1 && op_riprel[i])
12311       {
12312         (*info->fprintf_func) (info->stream, "        # ");
12313         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12314                                                 + op_address[op_index[i]]), info);
12315         break;
12316       }
12317   return codep - priv.the_buffer;
12318 }
12319
12320 static const char *float_mem[] = {
12321   /* d8 */
12322   "fadd{s|}",
12323   "fmul{s|}",
12324   "fcom{s|}",
12325   "fcomp{s|}",
12326   "fsub{s|}",
12327   "fsubr{s|}",
12328   "fdiv{s|}",
12329   "fdivr{s|}",
12330   /* d9 */
12331   "fld{s|}",
12332   "(bad)",
12333   "fst{s|}",
12334   "fstp{s|}",
12335   "fldenvIC",
12336   "fldcw",
12337   "fNstenvIC",
12338   "fNstcw",
12339   /* da */
12340   "fiadd{l|}",
12341   "fimul{l|}",
12342   "ficom{l|}",
12343   "ficomp{l|}",
12344   "fisub{l|}",
12345   "fisubr{l|}",
12346   "fidiv{l|}",
12347   "fidivr{l|}",
12348   /* db */
12349   "fild{l|}",
12350   "fisttp{l|}",
12351   "fist{l|}",
12352   "fistp{l|}",
12353   "(bad)",
12354   "fld{t||t|}",
12355   "(bad)",
12356   "fstp{t||t|}",
12357   /* dc */
12358   "fadd{l|}",
12359   "fmul{l|}",
12360   "fcom{l|}",
12361   "fcomp{l|}",
12362   "fsub{l|}",
12363   "fsubr{l|}",
12364   "fdiv{l|}",
12365   "fdivr{l|}",
12366   /* dd */
12367   "fld{l|}",
12368   "fisttp{ll|}",
12369   "fst{l||}",
12370   "fstp{l|}",
12371   "frstorIC",
12372   "(bad)",
12373   "fNsaveIC",
12374   "fNstsw",
12375   /* de */
12376   "fiadd{s|}",
12377   "fimul{s|}",
12378   "ficom{s|}",
12379   "ficomp{s|}",
12380   "fisub{s|}",
12381   "fisubr{s|}",
12382   "fidiv{s|}",
12383   "fidivr{s|}",
12384   /* df */
12385   "fild{s|}",
12386   "fisttp{s|}",
12387   "fist{s|}",
12388   "fistp{s|}",
12389   "fbld",
12390   "fild{ll|}",
12391   "fbstp",
12392   "fistp{ll|}",
12393 };
12394
12395 static const unsigned char float_mem_mode[] = {
12396   /* d8 */
12397   d_mode,
12398   d_mode,
12399   d_mode,
12400   d_mode,
12401   d_mode,
12402   d_mode,
12403   d_mode,
12404   d_mode,
12405   /* d9 */
12406   d_mode,
12407   0,
12408   d_mode,
12409   d_mode,
12410   0,
12411   w_mode,
12412   0,
12413   w_mode,
12414   /* da */
12415   d_mode,
12416   d_mode,
12417   d_mode,
12418   d_mode,
12419   d_mode,
12420   d_mode,
12421   d_mode,
12422   d_mode,
12423   /* db */
12424   d_mode,
12425   d_mode,
12426   d_mode,
12427   d_mode,
12428   0,
12429   t_mode,
12430   0,
12431   t_mode,
12432   /* dc */
12433   q_mode,
12434   q_mode,
12435   q_mode,
12436   q_mode,
12437   q_mode,
12438   q_mode,
12439   q_mode,
12440   q_mode,
12441   /* dd */
12442   q_mode,
12443   q_mode,
12444   q_mode,
12445   q_mode,
12446   0,
12447   0,
12448   0,
12449   w_mode,
12450   /* de */
12451   w_mode,
12452   w_mode,
12453   w_mode,
12454   w_mode,
12455   w_mode,
12456   w_mode,
12457   w_mode,
12458   w_mode,
12459   /* df */
12460   w_mode,
12461   w_mode,
12462   w_mode,
12463   w_mode,
12464   t_mode,
12465   q_mode,
12466   t_mode,
12467   q_mode
12468 };
12469
12470 #define ST { OP_ST, 0 }
12471 #define STi { OP_STi, 0 }
12472
12473 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12474 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12475 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12476 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12477 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12478 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12479 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12480 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12481 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12482
12483 static const struct dis386 float_reg[][8] = {
12484   /* d8 */
12485   {
12486     { "fadd",   { ST, STi }, 0 },
12487     { "fmul",   { ST, STi }, 0 },
12488     { "fcom",   { STi }, 0 },
12489     { "fcomp",  { STi }, 0 },
12490     { "fsub",   { ST, STi }, 0 },
12491     { "fsubr",  { ST, STi }, 0 },
12492     { "fdiv",   { ST, STi }, 0 },
12493     { "fdivr",  { ST, STi }, 0 },
12494   },
12495   /* d9 */
12496   {
12497     { "fld",    { STi }, 0 },
12498     { "fxch",   { STi }, 0 },
12499     { FGRPd9_2 },
12500     { Bad_Opcode },
12501     { FGRPd9_4 },
12502     { FGRPd9_5 },
12503     { FGRPd9_6 },
12504     { FGRPd9_7 },
12505   },
12506   /* da */
12507   {
12508     { "fcmovb", { ST, STi }, 0 },
12509     { "fcmove", { ST, STi }, 0 },
12510     { "fcmovbe",{ ST, STi }, 0 },
12511     { "fcmovu", { ST, STi }, 0 },
12512     { Bad_Opcode },
12513     { FGRPda_5 },
12514     { Bad_Opcode },
12515     { Bad_Opcode },
12516   },
12517   /* db */
12518   {
12519     { "fcmovnb",{ ST, STi }, 0 },
12520     { "fcmovne",{ ST, STi }, 0 },
12521     { "fcmovnbe",{ ST, STi }, 0 },
12522     { "fcmovnu",{ ST, STi }, 0 },
12523     { FGRPdb_4 },
12524     { "fucomi", { ST, STi }, 0 },
12525     { "fcomi",  { ST, STi }, 0 },
12526     { Bad_Opcode },
12527   },
12528   /* dc */
12529   {
12530     { "fadd",   { STi, ST }, 0 },
12531     { "fmul",   { STi, ST }, 0 },
12532     { Bad_Opcode },
12533     { Bad_Opcode },
12534     { "fsub{!M|r}",     { STi, ST }, 0 },
12535     { "fsub{M|}",       { STi, ST }, 0 },
12536     { "fdiv{!M|r}",     { STi, ST }, 0 },
12537     { "fdiv{M|}",       { STi, ST }, 0 },
12538   },
12539   /* dd */
12540   {
12541     { "ffree",  { STi }, 0 },
12542     { Bad_Opcode },
12543     { "fst",    { STi }, 0 },
12544     { "fstp",   { STi }, 0 },
12545     { "fucom",  { STi }, 0 },
12546     { "fucomp", { STi }, 0 },
12547     { Bad_Opcode },
12548     { Bad_Opcode },
12549   },
12550   /* de */
12551   {
12552     { "faddp",  { STi, ST }, 0 },
12553     { "fmulp",  { STi, ST }, 0 },
12554     { Bad_Opcode },
12555     { FGRPde_3 },
12556     { "fsub{!M|r}p",    { STi, ST }, 0 },
12557     { "fsub{M|}p",      { STi, ST }, 0 },
12558     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12559     { "fdiv{M|}p",      { STi, ST }, 0 },
12560   },
12561   /* df */
12562   {
12563     { "ffreep", { STi }, 0 },
12564     { Bad_Opcode },
12565     { Bad_Opcode },
12566     { Bad_Opcode },
12567     { FGRPdf_4 },
12568     { "fucomip", { ST, STi }, 0 },
12569     { "fcomip", { ST, STi }, 0 },
12570     { Bad_Opcode },
12571   },
12572 };
12573
12574 static char *fgrps[][8] = {
12575   /* Bad opcode 0 */
12576   {
12577     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12578   },
12579
12580   /* d9_2  1 */
12581   {
12582     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12583   },
12584
12585   /* d9_4  2 */
12586   {
12587     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12588   },
12589
12590   /* d9_5  3 */
12591   {
12592     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12593   },
12594
12595   /* d9_6  4 */
12596   {
12597     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12598   },
12599
12600   /* d9_7  5 */
12601   {
12602     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12603   },
12604
12605   /* da_5  6 */
12606   {
12607     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12608   },
12609
12610   /* db_4  7 */
12611   {
12612     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12613     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12614   },
12615
12616   /* de_3  8 */
12617   {
12618     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12619   },
12620
12621   /* df_4  9 */
12622   {
12623     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12624   },
12625 };
12626
12627 static void
12628 swap_operand (void)
12629 {
12630   mnemonicendp[0] = '.';
12631   mnemonicendp[1] = 's';
12632   mnemonicendp += 2;
12633 }
12634
12635 static void
12636 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12637                int sizeflag ATTRIBUTE_UNUSED)
12638 {
12639   /* Skip mod/rm byte.  */
12640   MODRM_CHECK;
12641   codep++;
12642 }
12643
12644 static void
12645 dofloat (int sizeflag)
12646 {
12647   const struct dis386 *dp;
12648   unsigned char floatop;
12649
12650   floatop = codep[-1];
12651
12652   if (modrm.mod != 3)
12653     {
12654       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12655
12656       putop (float_mem[fp_indx], sizeflag);
12657       obufp = op_out[0];
12658       op_ad = 2;
12659       OP_E (float_mem_mode[fp_indx], sizeflag);
12660       return;
12661     }
12662   /* Skip mod/rm byte.  */
12663   MODRM_CHECK;
12664   codep++;
12665
12666   dp = &float_reg[floatop - 0xd8][modrm.reg];
12667   if (dp->name == NULL)
12668     {
12669       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12670
12671       /* Instruction fnstsw is only one with strange arg.  */
12672       if (floatop == 0xdf && codep[-1] == 0xe0)
12673         strcpy (op_out[0], names16[0]);
12674     }
12675   else
12676     {
12677       putop (dp->name, sizeflag);
12678
12679       obufp = op_out[0];
12680       op_ad = 2;
12681       if (dp->op[0].rtn)
12682         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12683
12684       obufp = op_out[1];
12685       op_ad = 1;
12686       if (dp->op[1].rtn)
12687         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12688     }
12689 }
12690
12691 /* Like oappend (below), but S is a string starting with '%'.
12692    In Intel syntax, the '%' is elided.  */
12693 static void
12694 oappend_maybe_intel (const char *s)
12695 {
12696   oappend (s + intel_syntax);
12697 }
12698
12699 static void
12700 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12701 {
12702   oappend_maybe_intel ("%st");
12703 }
12704
12705 static void
12706 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12707 {
12708   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12709   oappend_maybe_intel (scratchbuf);
12710 }
12711
12712 /* Capital letters in template are macros.  */
12713 static int
12714 putop (const char *in_template, int sizeflag)
12715 {
12716   const char *p;
12717   int alt = 0;
12718   int cond = 1;
12719   unsigned int l = 0, len = 1;
12720   char last[4];
12721
12722 #define SAVE_LAST(c)                    \
12723   if (l < len && l < sizeof (last))     \
12724     last[l++] = c;                      \
12725   else                                  \
12726     abort ();
12727
12728   for (p = in_template; *p; p++)
12729     {
12730       switch (*p)
12731         {
12732         default:
12733           *obufp++ = *p;
12734           break;
12735         case '%':
12736           len++;
12737           break;
12738         case '!':
12739           cond = 0;
12740           break;
12741         case '{':
12742           if (intel_syntax)
12743             {
12744               while (*++p != '|')
12745                 if (*p == '}' || *p == '\0')
12746                   abort ();
12747             }
12748           /* Fall through.  */
12749         case 'I':
12750           alt = 1;
12751           continue;
12752         case '|':
12753           while (*++p != '}')
12754             {
12755               if (*p == '\0')
12756                 abort ();
12757             }
12758           break;
12759         case '}':
12760           break;
12761         case 'A':
12762           if (intel_syntax)
12763             break;
12764           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12765             *obufp++ = 'b';
12766           break;
12767         case 'B':
12768           if (l == 0 && len == 1)
12769             {
12770             case_B:
12771               if (intel_syntax)
12772                 break;
12773               if (sizeflag & SUFFIX_ALWAYS)
12774                 *obufp++ = 'b';
12775             }
12776           else
12777             {
12778               if (l != 1
12779                   || len != 2
12780                   || last[0] != 'L')
12781                 {
12782                   SAVE_LAST (*p);
12783                   break;
12784                 }
12785
12786               if (address_mode == mode_64bit
12787                   && !(prefixes & PREFIX_ADDR))
12788                 {
12789                   *obufp++ = 'a';
12790                   *obufp++ = 'b';
12791                   *obufp++ = 's';
12792                 }
12793
12794               goto case_B;
12795             }
12796           break;
12797         case 'C':
12798           if (intel_syntax && !alt)
12799             break;
12800           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12801             {
12802               if (sizeflag & DFLAG)
12803                 *obufp++ = intel_syntax ? 'd' : 'l';
12804               else
12805                 *obufp++ = intel_syntax ? 'w' : 's';
12806               used_prefixes |= (prefixes & PREFIX_DATA);
12807             }
12808           break;
12809         case 'D':
12810           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12811             break;
12812           USED_REX (REX_W);
12813           if (modrm.mod == 3)
12814             {
12815               if (rex & REX_W)
12816                 *obufp++ = 'q';
12817               else
12818                 {
12819                   if (sizeflag & DFLAG)
12820                     *obufp++ = intel_syntax ? 'd' : 'l';
12821                   else
12822                     *obufp++ = 'w';
12823                   used_prefixes |= (prefixes & PREFIX_DATA);
12824                 }
12825             }
12826           else
12827             *obufp++ = 'w';
12828           break;
12829         case 'E':               /* For jcxz/jecxz */
12830           if (address_mode == mode_64bit)
12831             {
12832               if (sizeflag & AFLAG)
12833                 *obufp++ = 'r';
12834               else
12835                 *obufp++ = 'e';
12836             }
12837           else
12838             if (sizeflag & AFLAG)
12839               *obufp++ = 'e';
12840           used_prefixes |= (prefixes & PREFIX_ADDR);
12841           break;
12842         case 'F':
12843           if (intel_syntax)
12844             break;
12845           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12846             {
12847               if (sizeflag & AFLAG)
12848                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12849               else
12850                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12851               used_prefixes |= (prefixes & PREFIX_ADDR);
12852             }
12853           break;
12854         case 'G':
12855           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12856             break;
12857           if ((rex & REX_W) || (sizeflag & DFLAG))
12858             *obufp++ = 'l';
12859           else
12860             *obufp++ = 'w';
12861           if (!(rex & REX_W))
12862             used_prefixes |= (prefixes & PREFIX_DATA);
12863           break;
12864         case 'H':
12865           if (intel_syntax)
12866             break;
12867           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12868               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12869             {
12870               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12871               *obufp++ = ',';
12872               *obufp++ = 'p';
12873               if (prefixes & PREFIX_DS)
12874                 *obufp++ = 't';
12875               else
12876                 *obufp++ = 'n';
12877             }
12878           break;
12879         case 'J':
12880           if (intel_syntax)
12881             break;
12882           *obufp++ = 'l';
12883           break;
12884         case 'K':
12885           USED_REX (REX_W);
12886           if (rex & REX_W)
12887             *obufp++ = 'q';
12888           else
12889             *obufp++ = 'd';
12890           break;
12891         case 'Z':
12892           if (l != 0 || len != 1)
12893             {
12894               if (l != 1 || len != 2 || last[0] != 'X')
12895                 {
12896                   SAVE_LAST (*p);
12897                   break;
12898                 }
12899               if (!need_vex || !vex.evex)
12900                 abort ();
12901               if (intel_syntax
12902                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12903                 break;
12904               switch (vex.length)
12905                 {
12906                 case 128:
12907                   *obufp++ = 'x';
12908                   break;
12909                 case 256:
12910                   *obufp++ = 'y';
12911                   break;
12912                 case 512:
12913                   *obufp++ = 'z';
12914                   break;
12915                 default:
12916                   abort ();
12917                 }
12918               break;
12919             }
12920           if (intel_syntax)
12921             break;
12922           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12923             {
12924               *obufp++ = 'q';
12925               break;
12926             }
12927           /* Fall through.  */
12928           goto case_L;
12929         case 'L':
12930           if (l != 0 || len != 1)
12931             {
12932               SAVE_LAST (*p);
12933               break;
12934             }
12935         case_L:
12936           if (intel_syntax)
12937             break;
12938           if (sizeflag & SUFFIX_ALWAYS)
12939             *obufp++ = 'l';
12940           break;
12941         case 'M':
12942           if (intel_mnemonic != cond)
12943             *obufp++ = 'r';
12944           break;
12945         case 'N':
12946           if ((prefixes & PREFIX_FWAIT) == 0)
12947             *obufp++ = 'n';
12948           else
12949             used_prefixes |= PREFIX_FWAIT;
12950           break;
12951         case 'O':
12952           USED_REX (REX_W);
12953           if (rex & REX_W)
12954             *obufp++ = 'o';
12955           else if (intel_syntax && (sizeflag & DFLAG))
12956             *obufp++ = 'q';
12957           else
12958             *obufp++ = 'd';
12959           if (!(rex & REX_W))
12960             used_prefixes |= (prefixes & PREFIX_DATA);
12961           break;
12962         case '&':
12963           if (!intel_syntax
12964               && address_mode == mode_64bit
12965               && isa64 == intel64)
12966             {
12967               *obufp++ = 'q';
12968               break;
12969             }
12970           /* Fall through.  */
12971         case 'T':
12972           if (!intel_syntax
12973               && address_mode == mode_64bit
12974               && ((sizeflag & DFLAG) || (rex & REX_W)))
12975             {
12976               *obufp++ = 'q';
12977               break;
12978             }
12979           /* Fall through.  */
12980           goto case_P;
12981         case 'P':
12982           if (l == 0 && len == 1)
12983             {
12984             case_P:
12985               if (intel_syntax)
12986                 {
12987                   if ((rex & REX_W) == 0
12988                       && (prefixes & PREFIX_DATA))
12989                     {
12990                       if ((sizeflag & DFLAG) == 0)
12991                         *obufp++ = 'w';
12992                       used_prefixes |= (prefixes & PREFIX_DATA);
12993                     }
12994                   break;
12995                 }
12996               if ((prefixes & PREFIX_DATA)
12997                   || (rex & REX_W)
12998                   || (sizeflag & SUFFIX_ALWAYS))
12999                 {
13000                   USED_REX (REX_W);
13001                   if (rex & REX_W)
13002                     *obufp++ = 'q';
13003                   else
13004                     {
13005                       if (sizeflag & DFLAG)
13006                         *obufp++ = 'l';
13007                       else
13008                         *obufp++ = 'w';
13009                       used_prefixes |= (prefixes & PREFIX_DATA);
13010                     }
13011                 }
13012             }
13013           else
13014             {
13015               if (l != 1 || len != 2 || last[0] != 'L')
13016                 {
13017                   SAVE_LAST (*p);
13018                   break;
13019                 }
13020
13021               if ((prefixes & PREFIX_DATA)
13022                   || (rex & REX_W)
13023                   || (sizeflag & SUFFIX_ALWAYS))
13024                 {
13025                   USED_REX (REX_W);
13026                   if (rex & REX_W)
13027                     *obufp++ = 'q';
13028                   else
13029                     {
13030                       if (sizeflag & DFLAG)
13031                         *obufp++ = intel_syntax ? 'd' : 'l';
13032                       else
13033                         *obufp++ = 'w';
13034                       used_prefixes |= (prefixes & PREFIX_DATA);
13035                     }
13036                 }
13037             }
13038           break;
13039         case 'U':
13040           if (intel_syntax)
13041             break;
13042           if (address_mode == mode_64bit
13043               && ((sizeflag & DFLAG) || (rex & REX_W)))
13044             {
13045               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13046                 *obufp++ = 'q';
13047               break;
13048             }
13049           /* Fall through.  */
13050           goto case_Q;
13051         case 'Q':
13052           if (l == 0 && len == 1)
13053             {
13054             case_Q:
13055               if (intel_syntax && !alt)
13056                 break;
13057               USED_REX (REX_W);
13058               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13059                 {
13060                   if (rex & REX_W)
13061                     *obufp++ = 'q';
13062                   else
13063                     {
13064                       if (sizeflag & DFLAG)
13065                         *obufp++ = intel_syntax ? 'd' : 'l';
13066                       else
13067                         *obufp++ = 'w';
13068                       used_prefixes |= (prefixes & PREFIX_DATA);
13069                     }
13070                 }
13071             }
13072           else
13073             {
13074               if (l != 1 || len != 2 || last[0] != 'L')
13075                 {
13076                   SAVE_LAST (*p);
13077                   break;
13078                 }
13079               if (intel_syntax
13080                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13081                 break;
13082               if ((rex & REX_W))
13083                 {
13084                   USED_REX (REX_W);
13085                   *obufp++ = 'q';
13086                 }
13087               else
13088                 *obufp++ = 'l';
13089             }
13090           break;
13091         case 'R':
13092           USED_REX (REX_W);
13093           if (rex & REX_W)
13094             *obufp++ = 'q';
13095           else if (sizeflag & DFLAG)
13096             {
13097               if (intel_syntax)
13098                   *obufp++ = 'd';
13099               else
13100                   *obufp++ = 'l';
13101             }
13102           else
13103             *obufp++ = 'w';
13104           if (intel_syntax && !p[1]
13105               && ((rex & REX_W) || (sizeflag & DFLAG)))
13106             *obufp++ = 'e';
13107           if (!(rex & REX_W))
13108             used_prefixes |= (prefixes & PREFIX_DATA);
13109           break;
13110         case 'V':
13111           if (l == 0 && len == 1)
13112             {
13113               if (intel_syntax)
13114                 break;
13115               if (address_mode == mode_64bit
13116                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13117                 {
13118                   if (sizeflag & SUFFIX_ALWAYS)
13119                     *obufp++ = 'q';
13120                   break;
13121                 }
13122             }
13123           else
13124             {
13125               if (l != 1
13126                   || len != 2
13127                   || last[0] != 'L')
13128                 {
13129                   SAVE_LAST (*p);
13130                   break;
13131                 }
13132
13133               if (rex & REX_W)
13134                 {
13135                   *obufp++ = 'a';
13136                   *obufp++ = 'b';
13137                   *obufp++ = 's';
13138                 }
13139             }
13140           /* Fall through.  */
13141           goto case_S;
13142         case 'S':
13143           if (l == 0 && len == 1)
13144             {
13145             case_S:
13146               if (intel_syntax)
13147                 break;
13148               if (sizeflag & SUFFIX_ALWAYS)
13149                 {
13150                   if (rex & REX_W)
13151                     *obufp++ = 'q';
13152                   else
13153                     {
13154                       if (sizeflag & DFLAG)
13155                         *obufp++ = 'l';
13156                       else
13157                         *obufp++ = 'w';
13158                       used_prefixes |= (prefixes & PREFIX_DATA);
13159                     }
13160                 }
13161             }
13162           else
13163             {
13164               if (l != 1
13165                   || len != 2
13166                   || last[0] != 'L')
13167                 {
13168                   SAVE_LAST (*p);
13169                   break;
13170                 }
13171
13172               if (address_mode == mode_64bit
13173                   && !(prefixes & PREFIX_ADDR))
13174                 {
13175                   *obufp++ = 'a';
13176                   *obufp++ = 'b';
13177                   *obufp++ = 's';
13178                 }
13179
13180               goto case_S;
13181             }
13182           break;
13183         case 'X':
13184           if (l != 0 || len != 1)
13185             {
13186               SAVE_LAST (*p);
13187               break;
13188             }
13189           if (need_vex
13190               ? vex.prefix == DATA_PREFIX_OPCODE
13191               : prefixes & PREFIX_DATA)
13192             {
13193               *obufp++ = 'd';
13194               used_prefixes |= PREFIX_DATA;
13195             }
13196           else
13197             *obufp++ = 's';
13198           break;
13199         case 'Y':
13200           if (l == 0 && len == 1)
13201             abort ();
13202           else
13203             {
13204               if (l != 1 || len != 2 || last[0] != 'X')
13205                 {
13206                   SAVE_LAST (*p);
13207                   break;
13208                 }
13209               if (!need_vex)
13210                 abort ();
13211               if (intel_syntax
13212                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13213                 break;
13214               switch (vex.length)
13215                 {
13216                 case 128:
13217                   *obufp++ = 'x';
13218                   break;
13219                 case 256:
13220                   *obufp++ = 'y';
13221                   break;
13222                 case 512:
13223                   if (!vex.evex)
13224                 default:
13225                     abort ();
13226                 }
13227             }
13228           break;
13229         case 'W':
13230           if (l == 0 && len == 1)
13231             {
13232               /* operand size flag for cwtl, cbtw */
13233               USED_REX (REX_W);
13234               if (rex & REX_W)
13235                 {
13236                   if (intel_syntax)
13237                     *obufp++ = 'd';
13238                   else
13239                     *obufp++ = 'l';
13240                 }
13241               else if (sizeflag & DFLAG)
13242                 *obufp++ = 'w';
13243               else
13244                 *obufp++ = 'b';
13245               if (!(rex & REX_W))
13246                 used_prefixes |= (prefixes & PREFIX_DATA);
13247             }
13248           else
13249             {
13250               if (l != 1
13251                   || len != 2
13252                   || (last[0] != 'X'
13253                       && last[0] != 'L'))
13254                 {
13255                   SAVE_LAST (*p);
13256                   break;
13257                 }
13258               if (!need_vex)
13259                 abort ();
13260               if (last[0] == 'X')
13261                 *obufp++ = vex.w ? 'd': 's';
13262               else
13263                 *obufp++ = vex.w ? 'q': 'd';
13264             }
13265           break;
13266         case '^':
13267           if (intel_syntax)
13268             break;
13269           if (isa64 == intel64 && (rex & REX_W))
13270             {
13271               USED_REX (REX_W);
13272               *obufp++ = 'q';
13273               break;
13274             }
13275           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13276             {
13277               if (sizeflag & DFLAG)
13278                 *obufp++ = 'l';
13279               else
13280                 *obufp++ = 'w';
13281               used_prefixes |= (prefixes & PREFIX_DATA);
13282             }
13283           break;
13284         case '@':
13285           if (intel_syntax)
13286             break;
13287           if (address_mode == mode_64bit
13288               && (isa64 == intel64
13289                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13290               *obufp++ = 'q';
13291           else if ((prefixes & PREFIX_DATA))
13292             {
13293               if (!(sizeflag & DFLAG))
13294                 *obufp++ = 'w';
13295               used_prefixes |= (prefixes & PREFIX_DATA);
13296             }
13297           break;
13298         }
13299       alt = 0;
13300     }
13301   *obufp = 0;
13302   mnemonicendp = obufp;
13303   return 0;
13304 }
13305
13306 static void
13307 oappend (const char *s)
13308 {
13309   obufp = stpcpy (obufp, s);
13310 }
13311
13312 static void
13313 append_seg (void)
13314 {
13315   /* Only print the active segment register.  */
13316   if (!active_seg_prefix)
13317     return;
13318
13319   used_prefixes |= active_seg_prefix;
13320   switch (active_seg_prefix)
13321     {
13322     case PREFIX_CS:
13323       oappend_maybe_intel ("%cs:");
13324       break;
13325     case PREFIX_DS:
13326       oappend_maybe_intel ("%ds:");
13327       break;
13328     case PREFIX_SS:
13329       oappend_maybe_intel ("%ss:");
13330       break;
13331     case PREFIX_ES:
13332       oappend_maybe_intel ("%es:");
13333       break;
13334     case PREFIX_FS:
13335       oappend_maybe_intel ("%fs:");
13336       break;
13337     case PREFIX_GS:
13338       oappend_maybe_intel ("%gs:");
13339       break;
13340     default:
13341       break;
13342     }
13343 }
13344
13345 static void
13346 OP_indirE (int bytemode, int sizeflag)
13347 {
13348   if (!intel_syntax)
13349     oappend ("*");
13350   OP_E (bytemode, sizeflag);
13351 }
13352
13353 static void
13354 print_operand_value (char *buf, int hex, bfd_vma disp)
13355 {
13356   if (address_mode == mode_64bit)
13357     {
13358       if (hex)
13359         {
13360           char tmp[30];
13361           int i;
13362           buf[0] = '0';
13363           buf[1] = 'x';
13364           sprintf_vma (tmp, disp);
13365           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13366           strcpy (buf + 2, tmp + i);
13367         }
13368       else
13369         {
13370           bfd_signed_vma v = disp;
13371           char tmp[30];
13372           int i;
13373           if (v < 0)
13374             {
13375               *(buf++) = '-';
13376               v = -disp;
13377               /* Check for possible overflow on 0x8000000000000000.  */
13378               if (v < 0)
13379                 {
13380                   strcpy (buf, "9223372036854775808");
13381                   return;
13382                 }
13383             }
13384           if (!v)
13385             {
13386               strcpy (buf, "0");
13387               return;
13388             }
13389
13390           i = 0;
13391           tmp[29] = 0;
13392           while (v)
13393             {
13394               tmp[28 - i] = (v % 10) + '0';
13395               v /= 10;
13396               i++;
13397             }
13398           strcpy (buf, tmp + 29 - i);
13399         }
13400     }
13401   else
13402     {
13403       if (hex)
13404         sprintf (buf, "0x%x", (unsigned int) disp);
13405       else
13406         sprintf (buf, "%d", (int) disp);
13407     }
13408 }
13409
13410 /* Put DISP in BUF as signed hex number.  */
13411
13412 static void
13413 print_displacement (char *buf, bfd_vma disp)
13414 {
13415   bfd_signed_vma val = disp;
13416   char tmp[30];
13417   int i, j = 0;
13418
13419   if (val < 0)
13420     {
13421       buf[j++] = '-';
13422       val = -disp;
13423
13424       /* Check for possible overflow.  */
13425       if (val < 0)
13426         {
13427           switch (address_mode)
13428             {
13429             case mode_64bit:
13430               strcpy (buf + j, "0x8000000000000000");
13431               break;
13432             case mode_32bit:
13433               strcpy (buf + j, "0x80000000");
13434               break;
13435             case mode_16bit:
13436               strcpy (buf + j, "0x8000");
13437               break;
13438             }
13439           return;
13440         }
13441     }
13442
13443   buf[j++] = '0';
13444   buf[j++] = 'x';
13445
13446   sprintf_vma (tmp, (bfd_vma) val);
13447   for (i = 0; tmp[i] == '0'; i++)
13448     continue;
13449   if (tmp[i] == '\0')
13450     i--;
13451   strcpy (buf + j, tmp + i);
13452 }
13453
13454 static void
13455 intel_operand_size (int bytemode, int sizeflag)
13456 {
13457   if (vex.evex
13458       && vex.b
13459       && (bytemode == x_mode
13460           || bytemode == evex_half_bcst_xmmq_mode))
13461     {
13462       if (vex.w)
13463         oappend ("QWORD PTR ");
13464       else
13465         oappend ("DWORD PTR ");
13466       return;
13467     }
13468   switch (bytemode)
13469     {
13470     case b_mode:
13471     case b_swap_mode:
13472     case dqb_mode:
13473     case db_mode:
13474       oappend ("BYTE PTR ");
13475       break;
13476     case w_mode:
13477     case dw_mode:
13478     case dqw_mode:
13479       oappend ("WORD PTR ");
13480       break;
13481     case indir_v_mode:
13482       if (address_mode == mode_64bit && isa64 == intel64)
13483         {
13484           oappend ("QWORD PTR ");
13485           break;
13486         }
13487       /* Fall through.  */
13488     case stack_v_mode:
13489       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13490         {
13491           oappend ("QWORD PTR ");
13492           break;
13493         }
13494       /* Fall through.  */
13495     case v_mode:
13496     case v_swap_mode:
13497     case dq_mode:
13498       USED_REX (REX_W);
13499       if (rex & REX_W)
13500         oappend ("QWORD PTR ");
13501       else
13502         {
13503           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13504             oappend ("DWORD PTR ");
13505           else
13506             oappend ("WORD PTR ");
13507           used_prefixes |= (prefixes & PREFIX_DATA);
13508         }
13509       break;
13510     case z_mode:
13511       if ((rex & REX_W) || (sizeflag & DFLAG))
13512         *obufp++ = 'D';
13513       oappend ("WORD PTR ");
13514       if (!(rex & REX_W))
13515         used_prefixes |= (prefixes & PREFIX_DATA);
13516       break;
13517     case a_mode:
13518       if (sizeflag & DFLAG)
13519         oappend ("QWORD PTR ");
13520       else
13521         oappend ("DWORD PTR ");
13522       used_prefixes |= (prefixes & PREFIX_DATA);
13523       break;
13524     case movsxd_mode:
13525       if (!(sizeflag & DFLAG) && isa64 == intel64)
13526         oappend ("WORD PTR ");
13527       else
13528         oappend ("DWORD PTR ");
13529       used_prefixes |= (prefixes & PREFIX_DATA);
13530       break;
13531     case d_mode:
13532     case d_scalar_mode:
13533     case d_scalar_swap_mode:
13534     case d_swap_mode:
13535     case dqd_mode:
13536       oappend ("DWORD PTR ");
13537       break;
13538     case q_mode:
13539     case q_scalar_mode:
13540     case q_scalar_swap_mode:
13541     case q_swap_mode:
13542       oappend ("QWORD PTR ");
13543       break;
13544     case m_mode:
13545       if (address_mode == mode_64bit)
13546         oappend ("QWORD PTR ");
13547       else
13548         oappend ("DWORD PTR ");
13549       break;
13550     case f_mode:
13551       if (sizeflag & DFLAG)
13552         oappend ("FWORD PTR ");
13553       else
13554         oappend ("DWORD PTR ");
13555       used_prefixes |= (prefixes & PREFIX_DATA);
13556       break;
13557     case t_mode:
13558       oappend ("TBYTE PTR ");
13559       break;
13560     case x_mode:
13561     case x_swap_mode:
13562     case evex_x_gscat_mode:
13563     case evex_x_nobcst_mode:
13564     case b_scalar_mode:
13565     case w_scalar_mode:
13566       if (need_vex)
13567         {
13568           switch (vex.length)
13569             {
13570             case 128:
13571               oappend ("XMMWORD PTR ");
13572               break;
13573             case 256:
13574               oappend ("YMMWORD PTR ");
13575               break;
13576             case 512:
13577               oappend ("ZMMWORD PTR ");
13578               break;
13579             default:
13580               abort ();
13581             }
13582         }
13583       else
13584         oappend ("XMMWORD PTR ");
13585       break;
13586     case xmm_mode:
13587       oappend ("XMMWORD PTR ");
13588       break;
13589     case ymm_mode:
13590       oappend ("YMMWORD PTR ");
13591       break;
13592     case xmmq_mode:
13593     case evex_half_bcst_xmmq_mode:
13594       if (!need_vex)
13595         abort ();
13596
13597       switch (vex.length)
13598         {
13599         case 128:
13600           oappend ("QWORD PTR ");
13601           break;
13602         case 256:
13603           oappend ("XMMWORD PTR ");
13604           break;
13605         case 512:
13606           oappend ("YMMWORD PTR ");
13607           break;
13608         default:
13609           abort ();
13610         }
13611       break;
13612     case xmm_mb_mode:
13613       if (!need_vex)
13614         abort ();
13615
13616       switch (vex.length)
13617         {
13618         case 128:
13619         case 256:
13620         case 512:
13621           oappend ("BYTE PTR ");
13622           break;
13623         default:
13624           abort ();
13625         }
13626       break;
13627     case xmm_mw_mode:
13628       if (!need_vex)
13629         abort ();
13630
13631       switch (vex.length)
13632         {
13633         case 128:
13634         case 256:
13635         case 512:
13636           oappend ("WORD PTR ");
13637           break;
13638         default:
13639           abort ();
13640         }
13641       break;
13642     case xmm_md_mode:
13643       if (!need_vex)
13644         abort ();
13645
13646       switch (vex.length)
13647         {
13648         case 128:
13649         case 256:
13650         case 512:
13651           oappend ("DWORD PTR ");
13652           break;
13653         default:
13654           abort ();
13655         }
13656       break;
13657     case xmm_mq_mode:
13658       if (!need_vex)
13659         abort ();
13660
13661       switch (vex.length)
13662         {
13663         case 128:
13664         case 256:
13665         case 512:
13666           oappend ("QWORD PTR ");
13667           break;
13668         default:
13669           abort ();
13670         }
13671       break;
13672     case xmmdw_mode:
13673       if (!need_vex)
13674         abort ();
13675
13676       switch (vex.length)
13677         {
13678         case 128:
13679           oappend ("WORD PTR ");
13680           break;
13681         case 256:
13682           oappend ("DWORD PTR ");
13683           break;
13684         case 512:
13685           oappend ("QWORD PTR ");
13686           break;
13687         default:
13688           abort ();
13689         }
13690       break;
13691     case xmmqd_mode:
13692       if (!need_vex)
13693         abort ();
13694
13695       switch (vex.length)
13696         {
13697         case 128:
13698           oappend ("DWORD PTR ");
13699           break;
13700         case 256:
13701           oappend ("QWORD PTR ");
13702           break;
13703         case 512:
13704           oappend ("XMMWORD PTR ");
13705           break;
13706         default:
13707           abort ();
13708         }
13709       break;
13710     case ymmq_mode:
13711       if (!need_vex)
13712         abort ();
13713
13714       switch (vex.length)
13715         {
13716         case 128:
13717           oappend ("QWORD PTR ");
13718           break;
13719         case 256:
13720           oappend ("YMMWORD PTR ");
13721           break;
13722         case 512:
13723           oappend ("ZMMWORD PTR ");
13724           break;
13725         default:
13726           abort ();
13727         }
13728       break;
13729     case ymmxmm_mode:
13730       if (!need_vex)
13731         abort ();
13732
13733       switch (vex.length)
13734         {
13735         case 128:
13736         case 256:
13737           oappend ("XMMWORD PTR ");
13738           break;
13739         default:
13740           abort ();
13741         }
13742       break;
13743     case o_mode:
13744       oappend ("OWORD PTR ");
13745       break;
13746     case vex_scalar_w_dq_mode:
13747       if (!need_vex)
13748         abort ();
13749
13750       if (vex.w)
13751         oappend ("QWORD PTR ");
13752       else
13753         oappend ("DWORD PTR ");
13754       break;
13755     case vex_vsib_d_w_dq_mode:
13756     case vex_vsib_q_w_dq_mode:
13757       if (!need_vex)
13758         abort ();
13759
13760       if (!vex.evex)
13761         {
13762           if (vex.w)
13763             oappend ("QWORD PTR ");
13764           else
13765             oappend ("DWORD PTR ");
13766         }
13767       else
13768         {
13769           switch (vex.length)
13770             {
13771             case 128:
13772               oappend ("XMMWORD PTR ");
13773               break;
13774             case 256:
13775               oappend ("YMMWORD PTR ");
13776               break;
13777             case 512:
13778               oappend ("ZMMWORD PTR ");
13779               break;
13780             default:
13781               abort ();
13782             }
13783         }
13784       break;
13785     case vex_vsib_q_w_d_mode:
13786     case vex_vsib_d_w_d_mode:
13787       if (!need_vex || !vex.evex)
13788         abort ();
13789
13790       switch (vex.length)
13791         {
13792         case 128:
13793           oappend ("QWORD PTR ");
13794           break;
13795         case 256:
13796           oappend ("XMMWORD PTR ");
13797           break;
13798         case 512:
13799           oappend ("YMMWORD PTR ");
13800           break;
13801         default:
13802           abort ();
13803         }
13804
13805       break;
13806     case mask_bd_mode:
13807       if (!need_vex || vex.length != 128)
13808         abort ();
13809       if (vex.w)
13810         oappend ("DWORD PTR ");
13811       else
13812         oappend ("BYTE PTR ");
13813       break;
13814     case mask_mode:
13815       if (!need_vex)
13816         abort ();
13817       if (vex.w)
13818         oappend ("QWORD PTR ");
13819       else
13820         oappend ("WORD PTR ");
13821       break;
13822     case v_bnd_mode:
13823     case v_bndmk_mode:
13824     default:
13825       break;
13826     }
13827 }
13828
13829 static void
13830 OP_E_register (int bytemode, int sizeflag)
13831 {
13832   int reg = modrm.rm;
13833   const char **names;
13834
13835   USED_REX (REX_B);
13836   if ((rex & REX_B))
13837     reg += 8;
13838
13839   if ((sizeflag & SUFFIX_ALWAYS)
13840       && (bytemode == b_swap_mode
13841           || bytemode == bnd_swap_mode
13842           || bytemode == v_swap_mode))
13843     swap_operand ();
13844
13845   switch (bytemode)
13846     {
13847     case b_mode:
13848     case b_swap_mode:
13849       USED_REX (0);
13850       if (rex)
13851         names = names8rex;
13852       else
13853         names = names8;
13854       break;
13855     case w_mode:
13856       names = names16;
13857       break;
13858     case d_mode:
13859     case dw_mode:
13860     case db_mode:
13861       names = names32;
13862       break;
13863     case q_mode:
13864       names = names64;
13865       break;
13866     case m_mode:
13867     case v_bnd_mode:
13868       names = address_mode == mode_64bit ? names64 : names32;
13869       break;
13870     case bnd_mode:
13871     case bnd_swap_mode:
13872       if (reg > 0x3)
13873         {
13874           oappend ("(bad)");
13875           return;
13876         }
13877       names = names_bnd;
13878       break;
13879     case indir_v_mode:
13880       if (address_mode == mode_64bit && isa64 == intel64)
13881         {
13882           names = names64;
13883           break;
13884         }
13885       /* Fall through.  */
13886     case stack_v_mode:
13887       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13888         {
13889           names = names64;
13890           break;
13891         }
13892       bytemode = v_mode;
13893       /* Fall through.  */
13894     case v_mode:
13895     case v_swap_mode:
13896     case dq_mode:
13897     case dqb_mode:
13898     case dqd_mode:
13899     case dqw_mode:
13900       USED_REX (REX_W);
13901       if (rex & REX_W)
13902         names = names64;
13903       else
13904         {
13905           if ((sizeflag & DFLAG)
13906               || (bytemode != v_mode
13907                   && bytemode != v_swap_mode))
13908             names = names32;
13909           else
13910             names = names16;
13911           used_prefixes |= (prefixes & PREFIX_DATA);
13912         }
13913       break;
13914     case movsxd_mode:
13915       if (!(sizeflag & DFLAG) && isa64 == intel64)
13916         names = names16;
13917       else
13918         names = names32;
13919       used_prefixes |= (prefixes & PREFIX_DATA);
13920       break;
13921     case va_mode:
13922       names = (address_mode == mode_64bit
13923                ? names64 : names32);
13924       if (!(prefixes & PREFIX_ADDR))
13925         names = (address_mode == mode_16bit
13926                      ? names16 : names);
13927       else
13928         {
13929           /* Remove "addr16/addr32".  */
13930           all_prefixes[last_addr_prefix] = 0;
13931           names = (address_mode != mode_32bit
13932                        ? names32 : names16);
13933           used_prefixes |= PREFIX_ADDR;
13934         }
13935       break;
13936     case mask_bd_mode:
13937     case mask_mode:
13938       if (reg > 0x7)
13939         {
13940           oappend ("(bad)");
13941           return;
13942         }
13943       names = names_mask;
13944       break;
13945     case 0:
13946       return;
13947     default:
13948       oappend (INTERNAL_DISASSEMBLER_ERROR);
13949       return;
13950     }
13951   oappend (names[reg]);
13952 }
13953
13954 static void
13955 OP_E_memory (int bytemode, int sizeflag)
13956 {
13957   bfd_vma disp = 0;
13958   int add = (rex & REX_B) ? 8 : 0;
13959   int riprel = 0;
13960   int shift;
13961
13962   if (vex.evex)
13963     {
13964       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13965       if (vex.b
13966           && bytemode != x_mode
13967           && bytemode != xmmq_mode
13968           && bytemode != evex_half_bcst_xmmq_mode)
13969         {
13970           BadOp ();
13971           return;
13972         }
13973       switch (bytemode)
13974         {
13975         case dqw_mode:
13976         case dw_mode:
13977           shift = 1;
13978           break;
13979         case dqb_mode:
13980         case db_mode:
13981           shift = 0;
13982           break;
13983         case dq_mode:
13984           if (address_mode != mode_64bit)
13985             {
13986               shift = 2;
13987               break;
13988             }
13989             /* fall through */
13990         case vex_scalar_w_dq_mode:
13991         case vex_vsib_d_w_dq_mode:
13992         case vex_vsib_d_w_d_mode:
13993         case vex_vsib_q_w_dq_mode:
13994         case vex_vsib_q_w_d_mode:
13995         case evex_x_gscat_mode:
13996           shift = vex.w ? 3 : 2;
13997           break;
13998         case x_mode:
13999         case evex_half_bcst_xmmq_mode:
14000         case xmmq_mode:
14001           if (vex.b)
14002             {
14003               shift = vex.w ? 3 : 2;
14004               break;
14005             }
14006           /* Fall through.  */
14007         case xmmqd_mode:
14008         case xmmdw_mode:
14009         case ymmq_mode:
14010         case evex_x_nobcst_mode:
14011         case x_swap_mode:
14012           switch (vex.length)
14013             {
14014             case 128:
14015               shift = 4;
14016               break;
14017             case 256:
14018               shift = 5;
14019               break;
14020             case 512:
14021               shift = 6;
14022               break;
14023             default:
14024               abort ();
14025             }
14026           break;
14027         case ymm_mode:
14028           shift = 5;
14029           break;
14030         case xmm_mode:
14031           shift = 4;
14032           break;
14033         case xmm_mq_mode:
14034         case q_mode:
14035         case q_scalar_mode:
14036         case q_swap_mode:
14037         case q_scalar_swap_mode:
14038           shift = 3;
14039           break;
14040         case dqd_mode:
14041         case xmm_md_mode:
14042         case d_mode:
14043         case d_scalar_mode:
14044         case d_swap_mode:
14045         case d_scalar_swap_mode:
14046           shift = 2;
14047           break;
14048         case w_scalar_mode:
14049         case xmm_mw_mode:
14050           shift = 1;
14051           break;
14052         case b_scalar_mode:
14053         case xmm_mb_mode:
14054           shift = 0;
14055           break;
14056         default:
14057           abort ();
14058         }
14059       /* Make necessary corrections to shift for modes that need it.
14060          For these modes we currently have shift 4, 5 or 6 depending on
14061          vex.length (it corresponds to xmmword, ymmword or zmmword
14062          operand).  We might want to make it 3, 4 or 5 (e.g. for
14063          xmmq_mode).  In case of broadcast enabled the corrections
14064          aren't needed, as element size is always 32 or 64 bits.  */
14065       if (!vex.b
14066           && (bytemode == xmmq_mode
14067               || bytemode == evex_half_bcst_xmmq_mode))
14068         shift -= 1;
14069       else if (bytemode == xmmqd_mode)
14070         shift -= 2;
14071       else if (bytemode == xmmdw_mode)
14072         shift -= 3;
14073       else if (bytemode == ymmq_mode && vex.length == 128)
14074         shift -= 1;
14075     }
14076   else
14077     shift = 0;
14078
14079   USED_REX (REX_B);
14080   if (intel_syntax)
14081     intel_operand_size (bytemode, sizeflag);
14082   append_seg ();
14083
14084   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14085     {
14086       /* 32/64 bit address mode */
14087       int havedisp;
14088       int havesib;
14089       int havebase;
14090       int haveindex;
14091       int needindex;
14092       int needaddr32;
14093       int base, rbase;
14094       int vindex = 0;
14095       int scale = 0;
14096       int addr32flag = !((sizeflag & AFLAG)
14097                          || bytemode == v_bnd_mode
14098                          || bytemode == v_bndmk_mode
14099                          || bytemode == bnd_mode
14100                          || bytemode == bnd_swap_mode);
14101       const char **indexes64 = names64;
14102       const char **indexes32 = names32;
14103
14104       havesib = 0;
14105       havebase = 1;
14106       haveindex = 0;
14107       base = modrm.rm;
14108
14109       if (base == 4)
14110         {
14111           havesib = 1;
14112           vindex = sib.index;
14113           USED_REX (REX_X);
14114           if (rex & REX_X)
14115             vindex += 8;
14116           switch (bytemode)
14117             {
14118             case vex_vsib_d_w_dq_mode:
14119             case vex_vsib_d_w_d_mode:
14120             case vex_vsib_q_w_dq_mode:
14121             case vex_vsib_q_w_d_mode:
14122               if (!need_vex)
14123                 abort ();
14124               if (vex.evex)
14125                 {
14126                   if (!vex.v)
14127                     vindex += 16;
14128                 }
14129
14130               haveindex = 1;
14131               switch (vex.length)
14132                 {
14133                 case 128:
14134                   indexes64 = indexes32 = names_xmm;
14135                   break;
14136                 case 256:
14137                   if (!vex.w
14138                       || bytemode == vex_vsib_q_w_dq_mode
14139                       || bytemode == vex_vsib_q_w_d_mode)
14140                     indexes64 = indexes32 = names_ymm;
14141                   else
14142                     indexes64 = indexes32 = names_xmm;
14143                   break;
14144                 case 512:
14145                   if (!vex.w
14146                       || bytemode == vex_vsib_q_w_dq_mode
14147                       || bytemode == vex_vsib_q_w_d_mode)
14148                     indexes64 = indexes32 = names_zmm;
14149                   else
14150                     indexes64 = indexes32 = names_ymm;
14151                   break;
14152                 default:
14153                   abort ();
14154                 }
14155               break;
14156             default:
14157               haveindex = vindex != 4;
14158               break;
14159             }
14160           scale = sib.scale;
14161           base = sib.base;
14162           codep++;
14163         }
14164       rbase = base + add;
14165
14166       switch (modrm.mod)
14167         {
14168         case 0:
14169           if (base == 5)
14170             {
14171               havebase = 0;
14172               if (address_mode == mode_64bit && !havesib)
14173                 riprel = 1;
14174               disp = get32s ();
14175               if (riprel && bytemode == v_bndmk_mode)
14176                 {
14177                   oappend ("(bad)");
14178                   return;
14179                 }
14180             }
14181           break;
14182         case 1:
14183           FETCH_DATA (the_info, codep + 1);
14184           disp = *codep++;
14185           if ((disp & 0x80) != 0)
14186             disp -= 0x100;
14187           if (vex.evex && shift > 0)
14188             disp <<= shift;
14189           break;
14190         case 2:
14191           disp = get32s ();
14192           break;
14193         }
14194
14195       needindex = 0;
14196       needaddr32 = 0;
14197       if (havesib
14198           && !havebase
14199           && !haveindex
14200           && address_mode != mode_16bit)
14201         {
14202           if (address_mode == mode_64bit)
14203             {
14204               /* Display eiz instead of addr32.  */
14205               needindex = addr32flag;
14206               needaddr32 = 1;
14207             }
14208           else
14209             {
14210               /* In 32-bit mode, we need index register to tell [offset]
14211                  from [eiz*1 + offset].  */
14212               needindex = 1;
14213             }
14214         }
14215
14216       havedisp = (havebase
14217                   || needindex
14218                   || (havesib && (haveindex || scale != 0)));
14219
14220       if (!intel_syntax)
14221         if (modrm.mod != 0 || base == 5)
14222           {
14223             if (havedisp || riprel)
14224               print_displacement (scratchbuf, disp);
14225             else
14226               print_operand_value (scratchbuf, 1, disp);
14227             oappend (scratchbuf);
14228             if (riprel)
14229               {
14230                 set_op (disp, 1);
14231                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14232               }
14233           }
14234
14235       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14236           && (address_mode != mode_64bit
14237               || ((bytemode != v_bnd_mode)
14238                   && (bytemode != v_bndmk_mode)
14239                   && (bytemode != bnd_mode)
14240                   && (bytemode != bnd_swap_mode))))
14241         used_prefixes |= PREFIX_ADDR;
14242
14243       if (havedisp || (intel_syntax && riprel))
14244         {
14245           *obufp++ = open_char;
14246           if (intel_syntax && riprel)
14247             {
14248               set_op (disp, 1);
14249               oappend (!addr32flag ? "rip" : "eip");
14250             }
14251           *obufp = '\0';
14252           if (havebase)
14253             oappend (address_mode == mode_64bit && !addr32flag
14254                      ? names64[rbase] : names32[rbase]);
14255           if (havesib)
14256             {
14257               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14258                  print index to tell base + index from base.  */
14259               if (scale != 0
14260                   || needindex
14261                   || haveindex
14262                   || (havebase && base != ESP_REG_NUM))
14263                 {
14264                   if (!intel_syntax || havebase)
14265                     {
14266                       *obufp++ = separator_char;
14267                       *obufp = '\0';
14268                     }
14269                   if (haveindex)
14270                     oappend (address_mode == mode_64bit && !addr32flag
14271                              ? indexes64[vindex] : indexes32[vindex]);
14272                   else
14273                     oappend (address_mode == mode_64bit && !addr32flag
14274                              ? index64 : index32);
14275
14276                   *obufp++ = scale_char;
14277                   *obufp = '\0';
14278                   sprintf (scratchbuf, "%d", 1 << scale);
14279                   oappend (scratchbuf);
14280                 }
14281             }
14282           if (intel_syntax
14283               && (disp || modrm.mod != 0 || base == 5))
14284             {
14285               if (!havedisp || (bfd_signed_vma) disp >= 0)
14286                 {
14287                   *obufp++ = '+';
14288                   *obufp = '\0';
14289                 }
14290               else if (modrm.mod != 1 && disp != -disp)
14291                 {
14292                   *obufp++ = '-';
14293                   *obufp = '\0';
14294                   disp = - (bfd_signed_vma) disp;
14295                 }
14296
14297               if (havedisp)
14298                 print_displacement (scratchbuf, disp);
14299               else
14300                 print_operand_value (scratchbuf, 1, disp);
14301               oappend (scratchbuf);
14302             }
14303
14304           *obufp++ = close_char;
14305           *obufp = '\0';
14306         }
14307       else if (intel_syntax)
14308         {
14309           if (modrm.mod != 0 || base == 5)
14310             {
14311               if (!active_seg_prefix)
14312                 {
14313                   oappend (names_seg[ds_reg - es_reg]);
14314                   oappend (":");
14315                 }
14316               print_operand_value (scratchbuf, 1, disp);
14317               oappend (scratchbuf);
14318             }
14319         }
14320     }
14321   else if (bytemode == v_bnd_mode
14322            || bytemode == v_bndmk_mode
14323            || bytemode == bnd_mode
14324            || bytemode == bnd_swap_mode)
14325     {
14326       oappend ("(bad)");
14327       return;
14328     }
14329   else
14330     {
14331       /* 16 bit address mode */
14332       used_prefixes |= prefixes & PREFIX_ADDR;
14333       switch (modrm.mod)
14334         {
14335         case 0:
14336           if (modrm.rm == 6)
14337             {
14338               disp = get16 ();
14339               if ((disp & 0x8000) != 0)
14340                 disp -= 0x10000;
14341             }
14342           break;
14343         case 1:
14344           FETCH_DATA (the_info, codep + 1);
14345           disp = *codep++;
14346           if ((disp & 0x80) != 0)
14347             disp -= 0x100;
14348           if (vex.evex && shift > 0)
14349             disp <<= shift;
14350           break;
14351         case 2:
14352           disp = get16 ();
14353           if ((disp & 0x8000) != 0)
14354             disp -= 0x10000;
14355           break;
14356         }
14357
14358       if (!intel_syntax)
14359         if (modrm.mod != 0 || modrm.rm == 6)
14360           {
14361             print_displacement (scratchbuf, disp);
14362             oappend (scratchbuf);
14363           }
14364
14365       if (modrm.mod != 0 || modrm.rm != 6)
14366         {
14367           *obufp++ = open_char;
14368           *obufp = '\0';
14369           oappend (index16[modrm.rm]);
14370           if (intel_syntax
14371               && (disp || modrm.mod != 0 || modrm.rm == 6))
14372             {
14373               if ((bfd_signed_vma) disp >= 0)
14374                 {
14375                   *obufp++ = '+';
14376                   *obufp = '\0';
14377                 }
14378               else if (modrm.mod != 1)
14379                 {
14380                   *obufp++ = '-';
14381                   *obufp = '\0';
14382                   disp = - (bfd_signed_vma) disp;
14383                 }
14384
14385               print_displacement (scratchbuf, disp);
14386               oappend (scratchbuf);
14387             }
14388
14389           *obufp++ = close_char;
14390           *obufp = '\0';
14391         }
14392       else if (intel_syntax)
14393         {
14394           if (!active_seg_prefix)
14395             {
14396               oappend (names_seg[ds_reg - es_reg]);
14397               oappend (":");
14398             }
14399           print_operand_value (scratchbuf, 1, disp & 0xffff);
14400           oappend (scratchbuf);
14401         }
14402     }
14403   if (vex.evex && vex.b
14404       && (bytemode == x_mode
14405           || bytemode == xmmq_mode
14406           || bytemode == evex_half_bcst_xmmq_mode))
14407     {
14408       if (vex.w
14409           || bytemode == xmmq_mode
14410           || bytemode == evex_half_bcst_xmmq_mode)
14411         {
14412           switch (vex.length)
14413             {
14414             case 128:
14415               oappend ("{1to2}");
14416               break;
14417             case 256:
14418               oappend ("{1to4}");
14419               break;
14420             case 512:
14421               oappend ("{1to8}");
14422               break;
14423             default:
14424               abort ();
14425             }
14426         }
14427       else
14428         {
14429           switch (vex.length)
14430             {
14431             case 128:
14432               oappend ("{1to4}");
14433               break;
14434             case 256:
14435               oappend ("{1to8}");
14436               break;
14437             case 512:
14438               oappend ("{1to16}");
14439               break;
14440             default:
14441               abort ();
14442             }
14443         }
14444     }
14445 }
14446
14447 static void
14448 OP_E (int bytemode, int sizeflag)
14449 {
14450   /* Skip mod/rm byte.  */
14451   MODRM_CHECK;
14452   codep++;
14453
14454   if (modrm.mod == 3)
14455     OP_E_register (bytemode, sizeflag);
14456   else
14457     OP_E_memory (bytemode, sizeflag);
14458 }
14459
14460 static void
14461 OP_G (int bytemode, int sizeflag)
14462 {
14463   int add = 0;
14464   const char **names;
14465   USED_REX (REX_R);
14466   if (rex & REX_R)
14467     add += 8;
14468   switch (bytemode)
14469     {
14470     case b_mode:
14471       USED_REX (0);
14472       if (rex)
14473         oappend (names8rex[modrm.reg + add]);
14474       else
14475         oappend (names8[modrm.reg + add]);
14476       break;
14477     case w_mode:
14478       oappend (names16[modrm.reg + add]);
14479       break;
14480     case d_mode:
14481     case db_mode:
14482     case dw_mode:
14483       oappend (names32[modrm.reg + add]);
14484       break;
14485     case q_mode:
14486       oappend (names64[modrm.reg + add]);
14487       break;
14488     case bnd_mode:
14489       if (modrm.reg > 0x3)
14490         {
14491           oappend ("(bad)");
14492           return;
14493         }
14494       oappend (names_bnd[modrm.reg]);
14495       break;
14496     case v_mode:
14497     case dq_mode:
14498     case dqb_mode:
14499     case dqd_mode:
14500     case dqw_mode:
14501     case movsxd_mode:
14502       USED_REX (REX_W);
14503       if (rex & REX_W)
14504         oappend (names64[modrm.reg + add]);
14505       else
14506         {
14507           if ((sizeflag & DFLAG)
14508               || (bytemode != v_mode && bytemode != movsxd_mode))
14509             oappend (names32[modrm.reg + add]);
14510           else
14511             oappend (names16[modrm.reg + add]);
14512           used_prefixes |= (prefixes & PREFIX_DATA);
14513         }
14514       break;
14515     case va_mode:
14516       names = (address_mode == mode_64bit
14517                ? names64 : names32);
14518       if (!(prefixes & PREFIX_ADDR))
14519         {
14520           if (address_mode == mode_16bit)
14521             names = names16;
14522         }
14523       else
14524         {
14525           /* Remove "addr16/addr32".  */
14526           all_prefixes[last_addr_prefix] = 0;
14527           names = (address_mode != mode_32bit
14528                        ? names32 : names16);
14529           used_prefixes |= PREFIX_ADDR;
14530         }
14531       oappend (names[modrm.reg + add]);
14532       break;
14533     case m_mode:
14534       if (address_mode == mode_64bit)
14535         oappend (names64[modrm.reg + add]);
14536       else
14537         oappend (names32[modrm.reg + add]);
14538       break;
14539     case mask_bd_mode:
14540     case mask_mode:
14541       if ((modrm.reg + add) > 0x7)
14542         {
14543           oappend ("(bad)");
14544           return;
14545         }
14546       oappend (names_mask[modrm.reg + add]);
14547       break;
14548     default:
14549       oappend (INTERNAL_DISASSEMBLER_ERROR);
14550       break;
14551     }
14552 }
14553
14554 static bfd_vma
14555 get64 (void)
14556 {
14557   bfd_vma x;
14558 #ifdef BFD64
14559   unsigned int a;
14560   unsigned int b;
14561
14562   FETCH_DATA (the_info, codep + 8);
14563   a = *codep++ & 0xff;
14564   a |= (*codep++ & 0xff) << 8;
14565   a |= (*codep++ & 0xff) << 16;
14566   a |= (*codep++ & 0xffu) << 24;
14567   b = *codep++ & 0xff;
14568   b |= (*codep++ & 0xff) << 8;
14569   b |= (*codep++ & 0xff) << 16;
14570   b |= (*codep++ & 0xffu) << 24;
14571   x = a + ((bfd_vma) b << 32);
14572 #else
14573   abort ();
14574   x = 0;
14575 #endif
14576   return x;
14577 }
14578
14579 static bfd_signed_vma
14580 get32 (void)
14581 {
14582   bfd_signed_vma x = 0;
14583
14584   FETCH_DATA (the_info, codep + 4);
14585   x = *codep++ & (bfd_signed_vma) 0xff;
14586   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14587   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14588   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14589   return x;
14590 }
14591
14592 static bfd_signed_vma
14593 get32s (void)
14594 {
14595   bfd_signed_vma x = 0;
14596
14597   FETCH_DATA (the_info, codep + 4);
14598   x = *codep++ & (bfd_signed_vma) 0xff;
14599   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14600   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14601   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14602
14603   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14604
14605   return x;
14606 }
14607
14608 static int
14609 get16 (void)
14610 {
14611   int x = 0;
14612
14613   FETCH_DATA (the_info, codep + 2);
14614   x = *codep++ & 0xff;
14615   x |= (*codep++ & 0xff) << 8;
14616   return x;
14617 }
14618
14619 static void
14620 set_op (bfd_vma op, int riprel)
14621 {
14622   op_index[op_ad] = op_ad;
14623   if (address_mode == mode_64bit)
14624     {
14625       op_address[op_ad] = op;
14626       op_riprel[op_ad] = riprel;
14627     }
14628   else
14629     {
14630       /* Mask to get a 32-bit address.  */
14631       op_address[op_ad] = op & 0xffffffff;
14632       op_riprel[op_ad] = riprel & 0xffffffff;
14633     }
14634 }
14635
14636 static void
14637 OP_REG (int code, int sizeflag)
14638 {
14639   const char *s;
14640   int add;
14641
14642   switch (code)
14643     {
14644     case es_reg: case ss_reg: case cs_reg:
14645     case ds_reg: case fs_reg: case gs_reg:
14646       oappend (names_seg[code - es_reg]);
14647       return;
14648     }
14649
14650   USED_REX (REX_B);
14651   if (rex & REX_B)
14652     add = 8;
14653   else
14654     add = 0;
14655
14656   switch (code)
14657     {
14658     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14659     case sp_reg: case bp_reg: case si_reg: case di_reg:
14660       s = names16[code - ax_reg + add];
14661       break;
14662     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14663     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14664       USED_REX (0);
14665       if (rex)
14666         s = names8rex[code - al_reg + add];
14667       else
14668         s = names8[code - al_reg];
14669       break;
14670     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14671     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14672       if (address_mode == mode_64bit
14673           && ((sizeflag & DFLAG) || (rex & REX_W)))
14674         {
14675           s = names64[code - rAX_reg + add];
14676           break;
14677         }
14678       code += eAX_reg - rAX_reg;
14679       /* Fall through.  */
14680     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14681     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14682       USED_REX (REX_W);
14683       if (rex & REX_W)
14684         s = names64[code - eAX_reg + add];
14685       else
14686         {
14687           if (sizeflag & DFLAG)
14688             s = names32[code - eAX_reg + add];
14689           else
14690             s = names16[code - eAX_reg + add];
14691           used_prefixes |= (prefixes & PREFIX_DATA);
14692         }
14693       break;
14694     default:
14695       s = INTERNAL_DISASSEMBLER_ERROR;
14696       break;
14697     }
14698   oappend (s);
14699 }
14700
14701 static void
14702 OP_IMREG (int code, int sizeflag)
14703 {
14704   const char *s;
14705
14706   switch (code)
14707     {
14708     case indir_dx_reg:
14709       if (intel_syntax)
14710         s = "dx";
14711       else
14712         s = "(%dx)";
14713       break;
14714     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14715     case sp_reg: case bp_reg: case si_reg: case di_reg:
14716       s = names16[code - ax_reg];
14717       break;
14718     case es_reg: case ss_reg: case cs_reg:
14719     case ds_reg: case fs_reg: case gs_reg:
14720       s = names_seg[code - es_reg];
14721       break;
14722     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14723     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14724       USED_REX (0);
14725       if (rex)
14726         s = names8rex[code - al_reg];
14727       else
14728         s = names8[code - al_reg];
14729       break;
14730     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14731     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14732       USED_REX (REX_W);
14733       if (rex & REX_W)
14734         s = names64[code - eAX_reg];
14735       else
14736         {
14737           if (sizeflag & DFLAG)
14738             s = names32[code - eAX_reg];
14739           else
14740             s = names16[code - eAX_reg];
14741           used_prefixes |= (prefixes & PREFIX_DATA);
14742         }
14743       break;
14744     case z_mode_ax_reg:
14745       if ((rex & REX_W) || (sizeflag & DFLAG))
14746         s = *names32;
14747       else
14748         s = *names16;
14749       if (!(rex & REX_W))
14750         used_prefixes |= (prefixes & PREFIX_DATA);
14751       break;
14752     default:
14753       s = INTERNAL_DISASSEMBLER_ERROR;
14754       break;
14755     }
14756   oappend (s);
14757 }
14758
14759 static void
14760 OP_I (int bytemode, int sizeflag)
14761 {
14762   bfd_signed_vma op;
14763   bfd_signed_vma mask = -1;
14764
14765   switch (bytemode)
14766     {
14767     case b_mode:
14768       FETCH_DATA (the_info, codep + 1);
14769       op = *codep++;
14770       mask = 0xff;
14771       break;
14772     case v_mode:
14773       USED_REX (REX_W);
14774       if (rex & REX_W)
14775         op = get32s ();
14776       else
14777         {
14778           if (sizeflag & DFLAG)
14779             {
14780               op = get32 ();
14781               mask = 0xffffffff;
14782             }
14783           else
14784             {
14785               op = get16 ();
14786               mask = 0xfffff;
14787             }
14788           used_prefixes |= (prefixes & PREFIX_DATA);
14789         }
14790       break;
14791     case d_mode:
14792       mask = 0xffffffff;
14793       op = get32 ();
14794       break;
14795     case w_mode:
14796       mask = 0xfffff;
14797       op = get16 ();
14798       break;
14799     case const_1_mode:
14800       if (intel_syntax)
14801         oappend ("1");
14802       return;
14803     default:
14804       oappend (INTERNAL_DISASSEMBLER_ERROR);
14805       return;
14806     }
14807
14808   op &= mask;
14809   scratchbuf[0] = '$';
14810   print_operand_value (scratchbuf + 1, 1, op);
14811   oappend_maybe_intel (scratchbuf);
14812   scratchbuf[0] = '\0';
14813 }
14814
14815 static void
14816 OP_I64 (int bytemode, int sizeflag)
14817 {
14818   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14819     {
14820       OP_I (bytemode, sizeflag);
14821       return;
14822     }
14823
14824   USED_REX (REX_W);
14825
14826   scratchbuf[0] = '$';
14827   print_operand_value (scratchbuf + 1, 1, get64 ());
14828   oappend_maybe_intel (scratchbuf);
14829   scratchbuf[0] = '\0';
14830 }
14831
14832 static void
14833 OP_sI (int bytemode, int sizeflag)
14834 {
14835   bfd_signed_vma op;
14836
14837   switch (bytemode)
14838     {
14839     case b_mode:
14840     case b_T_mode:
14841       FETCH_DATA (the_info, codep + 1);
14842       op = *codep++;
14843       if ((op & 0x80) != 0)
14844         op -= 0x100;
14845       if (bytemode == b_T_mode)
14846         {
14847           if (address_mode != mode_64bit
14848               || !((sizeflag & DFLAG) || (rex & REX_W)))
14849             {
14850               /* The operand-size prefix is overridden by a REX prefix.  */
14851               if ((sizeflag & DFLAG) || (rex & REX_W))
14852                 op &= 0xffffffff;
14853               else
14854                 op &= 0xffff;
14855           }
14856         }
14857       else
14858         {
14859           if (!(rex & REX_W))
14860             {
14861               if (sizeflag & DFLAG)
14862                 op &= 0xffffffff;
14863               else
14864                 op &= 0xffff;
14865             }
14866         }
14867       break;
14868     case v_mode:
14869       /* The operand-size prefix is overridden by a REX prefix.  */
14870       if ((sizeflag & DFLAG) || (rex & REX_W))
14871         op = get32s ();
14872       else
14873         op = get16 ();
14874       break;
14875     default:
14876       oappend (INTERNAL_DISASSEMBLER_ERROR);
14877       return;
14878     }
14879
14880   scratchbuf[0] = '$';
14881   print_operand_value (scratchbuf + 1, 1, op);
14882   oappend_maybe_intel (scratchbuf);
14883 }
14884
14885 static void
14886 OP_J (int bytemode, int sizeflag)
14887 {
14888   bfd_vma disp;
14889   bfd_vma mask = -1;
14890   bfd_vma segment = 0;
14891
14892   switch (bytemode)
14893     {
14894     case b_mode:
14895       FETCH_DATA (the_info, codep + 1);
14896       disp = *codep++;
14897       if ((disp & 0x80) != 0)
14898         disp -= 0x100;
14899       break;
14900     case v_mode:
14901       if (isa64 != intel64)
14902     case dqw_mode:
14903         USED_REX (REX_W);
14904       if ((sizeflag & DFLAG)
14905           || (address_mode == mode_64bit
14906               && ((isa64 == intel64 && bytemode != dqw_mode)
14907                   || (rex & REX_W))))
14908         disp = get32s ();
14909       else
14910         {
14911           disp = get16 ();
14912           if ((disp & 0x8000) != 0)
14913             disp -= 0x10000;
14914           /* In 16bit mode, address is wrapped around at 64k within
14915              the same segment.  Otherwise, a data16 prefix on a jump
14916              instruction means that the pc is masked to 16 bits after
14917              the displacement is added!  */
14918           mask = 0xffff;
14919           if ((prefixes & PREFIX_DATA) == 0)
14920             segment = ((start_pc + (codep - start_codep))
14921                        & ~((bfd_vma) 0xffff));
14922         }
14923       if (address_mode != mode_64bit
14924           || (isa64 != intel64 && !(rex & REX_W)))
14925         used_prefixes |= (prefixes & PREFIX_DATA);
14926       break;
14927     default:
14928       oappend (INTERNAL_DISASSEMBLER_ERROR);
14929       return;
14930     }
14931   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14932   set_op (disp, 0);
14933   print_operand_value (scratchbuf, 1, disp);
14934   oappend (scratchbuf);
14935 }
14936
14937 static void
14938 OP_SEG (int bytemode, int sizeflag)
14939 {
14940   if (bytemode == w_mode)
14941     oappend (names_seg[modrm.reg]);
14942   else
14943     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14944 }
14945
14946 static void
14947 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14948 {
14949   int seg, offset;
14950
14951   if (sizeflag & DFLAG)
14952     {
14953       offset = get32 ();
14954       seg = get16 ();
14955     }
14956   else
14957     {
14958       offset = get16 ();
14959       seg = get16 ();
14960     }
14961   used_prefixes |= (prefixes & PREFIX_DATA);
14962   if (intel_syntax)
14963     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14964   else
14965     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14966   oappend (scratchbuf);
14967 }
14968
14969 static void
14970 OP_OFF (int bytemode, int sizeflag)
14971 {
14972   bfd_vma off;
14973
14974   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14975     intel_operand_size (bytemode, sizeflag);
14976   append_seg ();
14977
14978   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14979     off = get32 ();
14980   else
14981     off = get16 ();
14982
14983   if (intel_syntax)
14984     {
14985       if (!active_seg_prefix)
14986         {
14987           oappend (names_seg[ds_reg - es_reg]);
14988           oappend (":");
14989         }
14990     }
14991   print_operand_value (scratchbuf, 1, off);
14992   oappend (scratchbuf);
14993 }
14994
14995 static void
14996 OP_OFF64 (int bytemode, int sizeflag)
14997 {
14998   bfd_vma off;
14999
15000   if (address_mode != mode_64bit
15001       || (prefixes & PREFIX_ADDR))
15002     {
15003       OP_OFF (bytemode, sizeflag);
15004       return;
15005     }
15006
15007   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15008     intel_operand_size (bytemode, sizeflag);
15009   append_seg ();
15010
15011   off = get64 ();
15012
15013   if (intel_syntax)
15014     {
15015       if (!active_seg_prefix)
15016         {
15017           oappend (names_seg[ds_reg - es_reg]);
15018           oappend (":");
15019         }
15020     }
15021   print_operand_value (scratchbuf, 1, off);
15022   oappend (scratchbuf);
15023 }
15024
15025 static void
15026 ptr_reg (int code, int sizeflag)
15027 {
15028   const char *s;
15029
15030   *obufp++ = open_char;
15031   used_prefixes |= (prefixes & PREFIX_ADDR);
15032   if (address_mode == mode_64bit)
15033     {
15034       if (!(sizeflag & AFLAG))
15035         s = names32[code - eAX_reg];
15036       else
15037         s = names64[code - eAX_reg];
15038     }
15039   else if (sizeflag & AFLAG)
15040     s = names32[code - eAX_reg];
15041   else
15042     s = names16[code - eAX_reg];
15043   oappend (s);
15044   *obufp++ = close_char;
15045   *obufp = 0;
15046 }
15047
15048 static void
15049 OP_ESreg (int code, int sizeflag)
15050 {
15051   if (intel_syntax)
15052     {
15053       switch (codep[-1])
15054         {
15055         case 0x6d:      /* insw/insl */
15056           intel_operand_size (z_mode, sizeflag);
15057           break;
15058         case 0xa5:      /* movsw/movsl/movsq */
15059         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15060         case 0xab:      /* stosw/stosl */
15061         case 0xaf:      /* scasw/scasl */
15062           intel_operand_size (v_mode, sizeflag);
15063           break;
15064         default:
15065           intel_operand_size (b_mode, sizeflag);
15066         }
15067     }
15068   oappend_maybe_intel ("%es:");
15069   ptr_reg (code, sizeflag);
15070 }
15071
15072 static void
15073 OP_DSreg (int code, int sizeflag)
15074 {
15075   if (intel_syntax)
15076     {
15077       switch (codep[-1])
15078         {
15079         case 0x6f:      /* outsw/outsl */
15080           intel_operand_size (z_mode, sizeflag);
15081           break;
15082         case 0xa5:      /* movsw/movsl/movsq */
15083         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15084         case 0xad:      /* lodsw/lodsl/lodsq */
15085           intel_operand_size (v_mode, sizeflag);
15086           break;
15087         default:
15088           intel_operand_size (b_mode, sizeflag);
15089         }
15090     }
15091   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15092      default segment register DS is printed.  */
15093   if (!active_seg_prefix)
15094     active_seg_prefix = PREFIX_DS;
15095   append_seg ();
15096   ptr_reg (code, sizeflag);
15097 }
15098
15099 static void
15100 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15101 {
15102   int add;
15103   if (rex & REX_R)
15104     {
15105       USED_REX (REX_R);
15106       add = 8;
15107     }
15108   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15109     {
15110       all_prefixes[last_lock_prefix] = 0;
15111       used_prefixes |= PREFIX_LOCK;
15112       add = 8;
15113     }
15114   else
15115     add = 0;
15116   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15117   oappend_maybe_intel (scratchbuf);
15118 }
15119
15120 static void
15121 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15122 {
15123   int add;
15124   USED_REX (REX_R);
15125   if (rex & REX_R)
15126     add = 8;
15127   else
15128     add = 0;
15129   if (intel_syntax)
15130     sprintf (scratchbuf, "db%d", modrm.reg + add);
15131   else
15132     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15133   oappend (scratchbuf);
15134 }
15135
15136 static void
15137 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15138 {
15139   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15140   oappend_maybe_intel (scratchbuf);
15141 }
15142
15143 static void
15144 OP_R (int bytemode, int sizeflag)
15145 {
15146   /* Skip mod/rm byte.  */
15147   MODRM_CHECK;
15148   codep++;
15149   OP_E_register (bytemode, sizeflag);
15150 }
15151
15152 static void
15153 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15154 {
15155   int reg = modrm.reg;
15156   const char **names;
15157
15158   used_prefixes |= (prefixes & PREFIX_DATA);
15159   if (prefixes & PREFIX_DATA)
15160     {
15161       names = names_xmm;
15162       USED_REX (REX_R);
15163       if (rex & REX_R)
15164         reg += 8;
15165     }
15166   else
15167     names = names_mm;
15168   oappend (names[reg]);
15169 }
15170
15171 static void
15172 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15173 {
15174   int reg = modrm.reg;
15175   const char **names;
15176
15177   USED_REX (REX_R);
15178   if (rex & REX_R)
15179     reg += 8;
15180   if (vex.evex)
15181     {
15182       if (!vex.r)
15183         reg += 16;
15184     }
15185
15186   if (need_vex
15187       && bytemode != xmm_mode
15188       && bytemode != xmmq_mode
15189       && bytemode != evex_half_bcst_xmmq_mode
15190       && bytemode != ymm_mode
15191       && bytemode != scalar_mode)
15192     {
15193       switch (vex.length)
15194         {
15195         case 128:
15196           names = names_xmm;
15197           break;
15198         case 256:
15199           if (vex.w
15200               || (bytemode != vex_vsib_q_w_dq_mode
15201                   && bytemode != vex_vsib_q_w_d_mode))
15202             names = names_ymm;
15203           else
15204             names = names_xmm;
15205           break;
15206         case 512:
15207           names = names_zmm;
15208           break;
15209         default:
15210           abort ();
15211         }
15212     }
15213   else if (bytemode == xmmq_mode
15214            || bytemode == evex_half_bcst_xmmq_mode)
15215     {
15216       switch (vex.length)
15217         {
15218         case 128:
15219         case 256:
15220           names = names_xmm;
15221           break;
15222         case 512:
15223           names = names_ymm;
15224           break;
15225         default:
15226           abort ();
15227         }
15228     }
15229   else if (bytemode == ymm_mode)
15230     names = names_ymm;
15231   else
15232     names = names_xmm;
15233   oappend (names[reg]);
15234 }
15235
15236 static void
15237 OP_EM (int bytemode, int sizeflag)
15238 {
15239   int reg;
15240   const char **names;
15241
15242   if (modrm.mod != 3)
15243     {
15244       if (intel_syntax
15245           && (bytemode == v_mode || bytemode == v_swap_mode))
15246         {
15247           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15248           used_prefixes |= (prefixes & PREFIX_DATA);
15249         }
15250       OP_E (bytemode, sizeflag);
15251       return;
15252     }
15253
15254   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15255     swap_operand ();
15256
15257   /* Skip mod/rm byte.  */
15258   MODRM_CHECK;
15259   codep++;
15260   used_prefixes |= (prefixes & PREFIX_DATA);
15261   reg = modrm.rm;
15262   if (prefixes & PREFIX_DATA)
15263     {
15264       names = names_xmm;
15265       USED_REX (REX_B);
15266       if (rex & REX_B)
15267         reg += 8;
15268     }
15269   else
15270     names = names_mm;
15271   oappend (names[reg]);
15272 }
15273
15274 /* cvt* are the only instructions in sse2 which have
15275    both SSE and MMX operands and also have 0x66 prefix
15276    in their opcode. 0x66 was originally used to differentiate
15277    between SSE and MMX instruction(operands). So we have to handle the
15278    cvt* separately using OP_EMC and OP_MXC */
15279 static void
15280 OP_EMC (int bytemode, int sizeflag)
15281 {
15282   if (modrm.mod != 3)
15283     {
15284       if (intel_syntax && bytemode == v_mode)
15285         {
15286           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15287           used_prefixes |= (prefixes & PREFIX_DATA);
15288         }
15289       OP_E (bytemode, sizeflag);
15290       return;
15291     }
15292
15293   /* Skip mod/rm byte.  */
15294   MODRM_CHECK;
15295   codep++;
15296   used_prefixes |= (prefixes & PREFIX_DATA);
15297   oappend (names_mm[modrm.rm]);
15298 }
15299
15300 static void
15301 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15302 {
15303   used_prefixes |= (prefixes & PREFIX_DATA);
15304   oappend (names_mm[modrm.reg]);
15305 }
15306
15307 static void
15308 OP_EX (int bytemode, int sizeflag)
15309 {
15310   int reg;
15311   const char **names;
15312
15313   /* Skip mod/rm byte.  */
15314   MODRM_CHECK;
15315   codep++;
15316
15317   if (modrm.mod != 3)
15318     {
15319       OP_E_memory (bytemode, sizeflag);
15320       return;
15321     }
15322
15323   reg = modrm.rm;
15324   USED_REX (REX_B);
15325   if (rex & REX_B)
15326     reg += 8;
15327   if (vex.evex)
15328     {
15329       USED_REX (REX_X);
15330       if ((rex & REX_X))
15331         reg += 16;
15332     }
15333
15334   if ((sizeflag & SUFFIX_ALWAYS)
15335       && (bytemode == x_swap_mode
15336           || bytemode == d_swap_mode
15337           || bytemode == d_scalar_swap_mode
15338           || bytemode == q_swap_mode
15339           || bytemode == q_scalar_swap_mode))
15340     swap_operand ();
15341
15342   if (need_vex
15343       && bytemode != xmm_mode
15344       && bytemode != xmmdw_mode
15345       && bytemode != xmmqd_mode
15346       && bytemode != xmm_mb_mode
15347       && bytemode != xmm_mw_mode
15348       && bytemode != xmm_md_mode
15349       && bytemode != xmm_mq_mode
15350       && bytemode != xmmq_mode
15351       && bytemode != evex_half_bcst_xmmq_mode
15352       && bytemode != ymm_mode
15353       && bytemode != d_scalar_mode
15354       && bytemode != d_scalar_swap_mode
15355       && bytemode != q_scalar_mode
15356       && bytemode != q_scalar_swap_mode
15357       && bytemode != vex_scalar_w_dq_mode)
15358     {
15359       switch (vex.length)
15360         {
15361         case 128:
15362           names = names_xmm;
15363           break;
15364         case 256:
15365           names = names_ymm;
15366           break;
15367         case 512:
15368           names = names_zmm;
15369           break;
15370         default:
15371           abort ();
15372         }
15373     }
15374   else if (bytemode == xmmq_mode
15375            || bytemode == evex_half_bcst_xmmq_mode)
15376     {
15377       switch (vex.length)
15378         {
15379         case 128:
15380         case 256:
15381           names = names_xmm;
15382           break;
15383         case 512:
15384           names = names_ymm;
15385           break;
15386         default:
15387           abort ();
15388         }
15389     }
15390   else if (bytemode == ymm_mode)
15391     names = names_ymm;
15392   else
15393     names = names_xmm;
15394   oappend (names[reg]);
15395 }
15396
15397 static void
15398 OP_MS (int bytemode, int sizeflag)
15399 {
15400   if (modrm.mod == 3)
15401     OP_EM (bytemode, sizeflag);
15402   else
15403     BadOp ();
15404 }
15405
15406 static void
15407 OP_XS (int bytemode, int sizeflag)
15408 {
15409   if (modrm.mod == 3)
15410     OP_EX (bytemode, sizeflag);
15411   else
15412     BadOp ();
15413 }
15414
15415 static void
15416 OP_M (int bytemode, int sizeflag)
15417 {
15418   if (modrm.mod == 3)
15419     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15420     BadOp ();
15421   else
15422     OP_E (bytemode, sizeflag);
15423 }
15424
15425 static void
15426 OP_0f07 (int bytemode, int sizeflag)
15427 {
15428   if (modrm.mod != 3 || modrm.rm != 0)
15429     BadOp ();
15430   else
15431     OP_E (bytemode, sizeflag);
15432 }
15433
15434 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15435    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15436
15437 static void
15438 NOP_Fixup1 (int bytemode, int sizeflag)
15439 {
15440   if ((prefixes & PREFIX_DATA) != 0
15441       || (rex != 0
15442           && rex != 0x48
15443           && address_mode == mode_64bit))
15444     OP_REG (bytemode, sizeflag);
15445   else
15446     strcpy (obuf, "nop");
15447 }
15448
15449 static void
15450 NOP_Fixup2 (int bytemode, int sizeflag)
15451 {
15452   if ((prefixes & PREFIX_DATA) != 0
15453       || (rex != 0
15454           && rex != 0x48
15455           && address_mode == mode_64bit))
15456     OP_IMREG (bytemode, sizeflag);
15457 }
15458
15459 static const char *const Suffix3DNow[] = {
15460 /* 00 */        NULL,           NULL,           NULL,           NULL,
15461 /* 04 */        NULL,           NULL,           NULL,           NULL,
15462 /* 08 */        NULL,           NULL,           NULL,           NULL,
15463 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15464 /* 10 */        NULL,           NULL,           NULL,           NULL,
15465 /* 14 */        NULL,           NULL,           NULL,           NULL,
15466 /* 18 */        NULL,           NULL,           NULL,           NULL,
15467 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15468 /* 20 */        NULL,           NULL,           NULL,           NULL,
15469 /* 24 */        NULL,           NULL,           NULL,           NULL,
15470 /* 28 */        NULL,           NULL,           NULL,           NULL,
15471 /* 2C */        NULL,           NULL,           NULL,           NULL,
15472 /* 30 */        NULL,           NULL,           NULL,           NULL,
15473 /* 34 */        NULL,           NULL,           NULL,           NULL,
15474 /* 38 */        NULL,           NULL,           NULL,           NULL,
15475 /* 3C */        NULL,           NULL,           NULL,           NULL,
15476 /* 40 */        NULL,           NULL,           NULL,           NULL,
15477 /* 44 */        NULL,           NULL,           NULL,           NULL,
15478 /* 48 */        NULL,           NULL,           NULL,           NULL,
15479 /* 4C */        NULL,           NULL,           NULL,           NULL,
15480 /* 50 */        NULL,           NULL,           NULL,           NULL,
15481 /* 54 */        NULL,           NULL,           NULL,           NULL,
15482 /* 58 */        NULL,           NULL,           NULL,           NULL,
15483 /* 5C */        NULL,           NULL,           NULL,           NULL,
15484 /* 60 */        NULL,           NULL,           NULL,           NULL,
15485 /* 64 */        NULL,           NULL,           NULL,           NULL,
15486 /* 68 */        NULL,           NULL,           NULL,           NULL,
15487 /* 6C */        NULL,           NULL,           NULL,           NULL,
15488 /* 70 */        NULL,           NULL,           NULL,           NULL,
15489 /* 74 */        NULL,           NULL,           NULL,           NULL,
15490 /* 78 */        NULL,           NULL,           NULL,           NULL,
15491 /* 7C */        NULL,           NULL,           NULL,           NULL,
15492 /* 80 */        NULL,           NULL,           NULL,           NULL,
15493 /* 84 */        NULL,           NULL,           NULL,           NULL,
15494 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15495 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15496 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15497 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15498 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15499 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15500 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15501 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15502 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15503 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15504 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15505 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15506 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15507 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15508 /* C0 */        NULL,           NULL,           NULL,           NULL,
15509 /* C4 */        NULL,           NULL,           NULL,           NULL,
15510 /* C8 */        NULL,           NULL,           NULL,           NULL,
15511 /* CC */        NULL,           NULL,           NULL,           NULL,
15512 /* D0 */        NULL,           NULL,           NULL,           NULL,
15513 /* D4 */        NULL,           NULL,           NULL,           NULL,
15514 /* D8 */        NULL,           NULL,           NULL,           NULL,
15515 /* DC */        NULL,           NULL,           NULL,           NULL,
15516 /* E0 */        NULL,           NULL,           NULL,           NULL,
15517 /* E4 */        NULL,           NULL,           NULL,           NULL,
15518 /* E8 */        NULL,           NULL,           NULL,           NULL,
15519 /* EC */        NULL,           NULL,           NULL,           NULL,
15520 /* F0 */        NULL,           NULL,           NULL,           NULL,
15521 /* F4 */        NULL,           NULL,           NULL,           NULL,
15522 /* F8 */        NULL,           NULL,           NULL,           NULL,
15523 /* FC */        NULL,           NULL,           NULL,           NULL,
15524 };
15525
15526 static void
15527 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15528 {
15529   const char *mnemonic;
15530
15531   FETCH_DATA (the_info, codep + 1);
15532   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15533      place where an 8-bit immediate would normally go.  ie. the last
15534      byte of the instruction.  */
15535   obufp = mnemonicendp;
15536   mnemonic = Suffix3DNow[*codep++ & 0xff];
15537   if (mnemonic)
15538     oappend (mnemonic);
15539   else
15540     {
15541       /* Since a variable sized modrm/sib chunk is between the start
15542          of the opcode (0x0f0f) and the opcode suffix, we need to do
15543          all the modrm processing first, and don't know until now that
15544          we have a bad opcode.  This necessitates some cleaning up.  */
15545       op_out[0][0] = '\0';
15546       op_out[1][0] = '\0';
15547       BadOp ();
15548     }
15549   mnemonicendp = obufp;
15550 }
15551
15552 static struct op simd_cmp_op[] =
15553 {
15554   { STRING_COMMA_LEN ("eq") },
15555   { STRING_COMMA_LEN ("lt") },
15556   { STRING_COMMA_LEN ("le") },
15557   { STRING_COMMA_LEN ("unord") },
15558   { STRING_COMMA_LEN ("neq") },
15559   { STRING_COMMA_LEN ("nlt") },
15560   { STRING_COMMA_LEN ("nle") },
15561   { STRING_COMMA_LEN ("ord") }
15562 };
15563
15564 static void
15565 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15566 {
15567   unsigned int cmp_type;
15568
15569   FETCH_DATA (the_info, codep + 1);
15570   cmp_type = *codep++ & 0xff;
15571   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15572     {
15573       char suffix [3];
15574       char *p = mnemonicendp - 2;
15575       suffix[0] = p[0];
15576       suffix[1] = p[1];
15577       suffix[2] = '\0';
15578       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15579       mnemonicendp += simd_cmp_op[cmp_type].len;
15580     }
15581   else
15582     {
15583       /* We have a reserved extension byte.  Output it directly.  */
15584       scratchbuf[0] = '$';
15585       print_operand_value (scratchbuf + 1, 1, cmp_type);
15586       oappend_maybe_intel (scratchbuf);
15587       scratchbuf[0] = '\0';
15588     }
15589 }
15590
15591 static void
15592 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15593 {
15594   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15595   if (!intel_syntax)
15596     {
15597       strcpy (op_out[0], names32[0]);
15598       strcpy (op_out[1], names32[1]);
15599       if (bytemode == eBX_reg)
15600         strcpy (op_out[2], names32[3]);
15601       two_source_ops = 1;
15602     }
15603   /* Skip mod/rm byte.  */
15604   MODRM_CHECK;
15605   codep++;
15606 }
15607
15608 static void
15609 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15610             int sizeflag ATTRIBUTE_UNUSED)
15611 {
15612   /* monitor %{e,r,}ax,%ecx,%edx"  */
15613   if (!intel_syntax)
15614     {
15615       const char **names = (address_mode == mode_64bit
15616                             ? names64 : names32);
15617
15618       if (prefixes & PREFIX_ADDR)
15619         {
15620           /* Remove "addr16/addr32".  */
15621           all_prefixes[last_addr_prefix] = 0;
15622           names = (address_mode != mode_32bit
15623                    ? names32 : names16);
15624           used_prefixes |= PREFIX_ADDR;
15625         }
15626       else if (address_mode == mode_16bit)
15627         names = names16;
15628       strcpy (op_out[0], names[0]);
15629       strcpy (op_out[1], names32[1]);
15630       strcpy (op_out[2], names32[2]);
15631       two_source_ops = 1;
15632     }
15633   /* Skip mod/rm byte.  */
15634   MODRM_CHECK;
15635   codep++;
15636 }
15637
15638 static void
15639 BadOp (void)
15640 {
15641   /* Throw away prefixes and 1st. opcode byte.  */
15642   codep = insn_codep + 1;
15643   oappend ("(bad)");
15644 }
15645
15646 static void
15647 REP_Fixup (int bytemode, int sizeflag)
15648 {
15649   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15650      lods and stos.  */
15651   if (prefixes & PREFIX_REPZ)
15652     all_prefixes[last_repz_prefix] = REP_PREFIX;
15653
15654   switch (bytemode)
15655     {
15656     case al_reg:
15657     case eAX_reg:
15658     case indir_dx_reg:
15659       OP_IMREG (bytemode, sizeflag);
15660       break;
15661     case eDI_reg:
15662       OP_ESreg (bytemode, sizeflag);
15663       break;
15664     case eSI_reg:
15665       OP_DSreg (bytemode, sizeflag);
15666       break;
15667     default:
15668       abort ();
15669       break;
15670     }
15671 }
15672
15673 static void
15674 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15675 {
15676   if ( isa64 != amd64 )
15677     return;
15678
15679   obufp = obuf;
15680   BadOp ();
15681   mnemonicendp = obufp;
15682   ++codep;
15683 }
15684
15685 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15686    "bnd".  */
15687
15688 static void
15689 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15690 {
15691   if (prefixes & PREFIX_REPNZ)
15692     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15693 }
15694
15695 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15696    "notrack".  */
15697
15698 static void
15699 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15700                int sizeflag ATTRIBUTE_UNUSED)
15701 {
15702   if (active_seg_prefix == PREFIX_DS
15703       && (address_mode != mode_64bit || last_data_prefix < 0))
15704     {
15705       /* NOTRACK prefix is only valid on indirect branch instructions.
15706          NB: DATA prefix is unsupported for Intel64.  */
15707       active_seg_prefix = 0;
15708       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15709     }
15710 }
15711
15712 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15713    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15714  */
15715
15716 static void
15717 HLE_Fixup1 (int bytemode, int sizeflag)
15718 {
15719   if (modrm.mod != 3
15720       && (prefixes & PREFIX_LOCK) != 0)
15721     {
15722       if (prefixes & PREFIX_REPZ)
15723         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15724       if (prefixes & PREFIX_REPNZ)
15725         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15726     }
15727
15728   OP_E (bytemode, sizeflag);
15729 }
15730
15731 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15732    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15733  */
15734
15735 static void
15736 HLE_Fixup2 (int bytemode, int sizeflag)
15737 {
15738   if (modrm.mod != 3)
15739     {
15740       if (prefixes & PREFIX_REPZ)
15741         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15742       if (prefixes & PREFIX_REPNZ)
15743         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15744     }
15745
15746   OP_E (bytemode, sizeflag);
15747 }
15748
15749 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15750    "xrelease" for memory operand.  No check for LOCK prefix.   */
15751
15752 static void
15753 HLE_Fixup3 (int bytemode, int sizeflag)
15754 {
15755   if (modrm.mod != 3
15756       && last_repz_prefix > last_repnz_prefix
15757       && (prefixes & PREFIX_REPZ) != 0)
15758     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15759
15760   OP_E (bytemode, sizeflag);
15761 }
15762
15763 static void
15764 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15765 {
15766   USED_REX (REX_W);
15767   if (rex & REX_W)
15768     {
15769       /* Change cmpxchg8b to cmpxchg16b.  */
15770       char *p = mnemonicendp - 2;
15771       mnemonicendp = stpcpy (p, "16b");
15772       bytemode = o_mode;
15773     }
15774   else if ((prefixes & PREFIX_LOCK) != 0)
15775     {
15776       if (prefixes & PREFIX_REPZ)
15777         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15778       if (prefixes & PREFIX_REPNZ)
15779         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15780     }
15781
15782   OP_M (bytemode, sizeflag);
15783 }
15784
15785 static void
15786 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15787 {
15788   const char **names;
15789
15790   if (need_vex)
15791     {
15792       switch (vex.length)
15793         {
15794         case 128:
15795           names = names_xmm;
15796           break;
15797         case 256:
15798           names = names_ymm;
15799           break;
15800         default:
15801           abort ();
15802         }
15803     }
15804   else
15805     names = names_xmm;
15806   oappend (names[reg]);
15807 }
15808
15809 static void
15810 CRC32_Fixup (int bytemode, int sizeflag)
15811 {
15812   /* Add proper suffix to "crc32".  */
15813   char *p = mnemonicendp;
15814
15815   switch (bytemode)
15816     {
15817     case b_mode:
15818       if (intel_syntax)
15819         goto skip;
15820
15821       *p++ = 'b';
15822       break;
15823     case v_mode:
15824       if (intel_syntax)
15825         goto skip;
15826
15827       USED_REX (REX_W);
15828       if (rex & REX_W)
15829         *p++ = 'q';
15830       else
15831         {
15832           if (sizeflag & DFLAG)
15833             *p++ = 'l';
15834           else
15835             *p++ = 'w';
15836           used_prefixes |= (prefixes & PREFIX_DATA);
15837         }
15838       break;
15839     default:
15840       oappend (INTERNAL_DISASSEMBLER_ERROR);
15841       break;
15842     }
15843   mnemonicendp = p;
15844   *p = '\0';
15845
15846  skip:
15847   if (modrm.mod == 3)
15848     {
15849       int add;
15850
15851       /* Skip mod/rm byte.  */
15852       MODRM_CHECK;
15853       codep++;
15854
15855       USED_REX (REX_B);
15856       add = (rex & REX_B) ? 8 : 0;
15857       if (bytemode == b_mode)
15858         {
15859           USED_REX (0);
15860           if (rex)
15861             oappend (names8rex[modrm.rm + add]);
15862           else
15863             oappend (names8[modrm.rm + add]);
15864         }
15865       else
15866         {
15867           USED_REX (REX_W);
15868           if (rex & REX_W)
15869             oappend (names64[modrm.rm + add]);
15870           else if ((prefixes & PREFIX_DATA))
15871             oappend (names16[modrm.rm + add]);
15872           else
15873             oappend (names32[modrm.rm + add]);
15874         }
15875     }
15876   else
15877     OP_E (bytemode, sizeflag);
15878 }
15879
15880 static void
15881 FXSAVE_Fixup (int bytemode, int sizeflag)
15882 {
15883   /* Add proper suffix to "fxsave" and "fxrstor".  */
15884   USED_REX (REX_W);
15885   if (rex & REX_W)
15886     {
15887       char *p = mnemonicendp;
15888       *p++ = '6';
15889       *p++ = '4';
15890       *p = '\0';
15891       mnemonicendp = p;
15892     }
15893   OP_M (bytemode, sizeflag);
15894 }
15895
15896 static void
15897 PCMPESTR_Fixup (int bytemode, int sizeflag)
15898 {
15899   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15900   if (!intel_syntax)
15901     {
15902       char *p = mnemonicendp;
15903
15904       USED_REX (REX_W);
15905       if (rex & REX_W)
15906         *p++ = 'q';
15907       else if (sizeflag & SUFFIX_ALWAYS)
15908         *p++ = 'l';
15909
15910       *p = '\0';
15911       mnemonicendp = p;
15912     }
15913
15914   OP_EX (bytemode, sizeflag);
15915 }
15916
15917 /* Display the destination register operand for instructions with
15918    VEX. */
15919
15920 static void
15921 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15922 {
15923   int reg;
15924   const char **names;
15925
15926   if (!need_vex)
15927     abort ();
15928
15929   if (!need_vex_reg)
15930     return;
15931
15932   reg = vex.register_specifier;
15933   vex.register_specifier = 0;
15934   if (address_mode != mode_64bit)
15935     reg &= 7;
15936   else if (vex.evex && !vex.v)
15937     reg += 16;
15938
15939   if (bytemode == vex_scalar_mode)
15940     {
15941       oappend (names_xmm[reg]);
15942       return;
15943     }
15944
15945   switch (vex.length)
15946     {
15947     case 128:
15948       switch (bytemode)
15949         {
15950         case vex_mode:
15951         case vex128_mode:
15952         case vex_vsib_q_w_dq_mode:
15953         case vex_vsib_q_w_d_mode:
15954           names = names_xmm;
15955           break;
15956         case dq_mode:
15957           if (rex & REX_W)
15958             names = names64;
15959           else
15960             names = names32;
15961           break;
15962         case mask_bd_mode:
15963         case mask_mode:
15964           if (reg > 0x7)
15965             {
15966               oappend ("(bad)");
15967               return;
15968             }
15969           names = names_mask;
15970           break;
15971         default:
15972           abort ();
15973           return;
15974         }
15975       break;
15976     case 256:
15977       switch (bytemode)
15978         {
15979         case vex_mode:
15980         case vex256_mode:
15981           names = names_ymm;
15982           break;
15983         case vex_vsib_q_w_dq_mode:
15984         case vex_vsib_q_w_d_mode:
15985           names = vex.w ? names_ymm : names_xmm;
15986           break;
15987         case mask_bd_mode:
15988         case mask_mode:
15989           if (reg > 0x7)
15990             {
15991               oappend ("(bad)");
15992               return;
15993             }
15994           names = names_mask;
15995           break;
15996         default:
15997           /* See PR binutils/20893 for a reproducer.  */
15998           oappend ("(bad)");
15999           return;
16000         }
16001       break;
16002     case 512:
16003       names = names_zmm;
16004       break;
16005     default:
16006       abort ();
16007       break;
16008     }
16009   oappend (names[reg]);
16010 }
16011
16012 /* Get the VEX immediate byte without moving codep.  */
16013
16014 static unsigned char
16015 get_vex_imm8 (int sizeflag, int opnum)
16016 {
16017   int bytes_before_imm = 0;
16018
16019   if (modrm.mod != 3)
16020     {
16021       /* There are SIB/displacement bytes.  */
16022       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16023         {
16024           /* 32/64 bit address mode */
16025           int base = modrm.rm;
16026
16027           /* Check SIB byte.  */
16028           if (base == 4)
16029             {
16030               FETCH_DATA (the_info, codep + 1);
16031               base = *codep & 7;
16032               /* When decoding the third source, don't increase
16033                  bytes_before_imm as this has already been incremented
16034                  by one in OP_E_memory while decoding the second
16035                  source operand.  */
16036               if (opnum == 0)
16037                 bytes_before_imm++;
16038             }
16039
16040           /* Don't increase bytes_before_imm when decoding the third source,
16041              it has already been incremented by OP_E_memory while decoding
16042              the second source operand.  */
16043           if (opnum == 0)
16044             {
16045               switch (modrm.mod)
16046                 {
16047                   case 0:
16048                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16049                        SIB == 5, there is a 4 byte displacement.  */
16050                     if (base != 5)
16051                       /* No displacement. */
16052                       break;
16053                     /* Fall through.  */
16054                   case 2:
16055                     /* 4 byte displacement.  */
16056                     bytes_before_imm += 4;
16057                     break;
16058                   case 1:
16059                     /* 1 byte displacement.  */
16060                     bytes_before_imm++;
16061                     break;
16062                 }
16063             }
16064         }
16065       else
16066         {
16067           /* 16 bit address mode */
16068           /* Don't increase bytes_before_imm when decoding the third source,
16069              it has already been incremented by OP_E_memory while decoding
16070              the second source operand.  */
16071           if (opnum == 0)
16072             {
16073               switch (modrm.mod)
16074                 {
16075                 case 0:
16076                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16077                   if (modrm.rm != 6)
16078                     /* No displacement. */
16079                     break;
16080                   /* Fall through.  */
16081                 case 2:
16082                   /* 2 byte displacement.  */
16083                   bytes_before_imm += 2;
16084                   break;
16085                 case 1:
16086                   /* 1 byte displacement: when decoding the third source,
16087                      don't increase bytes_before_imm as this has already
16088                      been incremented by one in OP_E_memory while decoding
16089                      the second source operand.  */
16090                   if (opnum == 0)
16091                     bytes_before_imm++;
16092
16093                   break;
16094                 }
16095             }
16096         }
16097     }
16098
16099   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16100   return codep [bytes_before_imm];
16101 }
16102
16103 static void
16104 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16105 {
16106   const char **names;
16107
16108   if (reg == -1 && modrm.mod != 3)
16109     {
16110       OP_E_memory (bytemode, sizeflag);
16111       return;
16112     }
16113   else
16114     {
16115       if (reg == -1)
16116         {
16117           reg = modrm.rm;
16118           USED_REX (REX_B);
16119           if (rex & REX_B)
16120             reg += 8;
16121         }
16122       if (address_mode != mode_64bit)
16123         reg &= 7;
16124     }
16125
16126   switch (vex.length)
16127     {
16128     case 128:
16129       names = names_xmm;
16130       break;
16131     case 256:
16132       names = names_ymm;
16133       break;
16134     default:
16135       abort ();
16136     }
16137   oappend (names[reg]);
16138 }
16139
16140 static void
16141 OP_EX_VexImmW (int bytemode, int sizeflag)
16142 {
16143   int reg = -1;
16144   static unsigned char vex_imm8;
16145
16146   if (vex_w_done == 0)
16147     {
16148       vex_w_done = 1;
16149
16150       /* Skip mod/rm byte.  */
16151       MODRM_CHECK;
16152       codep++;
16153
16154       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16155
16156       if (vex.w)
16157           reg = vex_imm8 >> 4;
16158
16159       OP_EX_VexReg (bytemode, sizeflag, reg);
16160     }
16161   else if (vex_w_done == 1)
16162     {
16163       vex_w_done = 2;
16164
16165       if (!vex.w)
16166           reg = vex_imm8 >> 4;
16167
16168       OP_EX_VexReg (bytemode, sizeflag, reg);
16169     }
16170   else
16171     {
16172       /* Output the imm8 directly.  */
16173       scratchbuf[0] = '$';
16174       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16175       oappend_maybe_intel (scratchbuf);
16176       scratchbuf[0] = '\0';
16177       codep++;
16178     }
16179 }
16180
16181 static void
16182 OP_Vex_2src (int bytemode, int sizeflag)
16183 {
16184   if (modrm.mod == 3)
16185     {
16186       int reg = modrm.rm;
16187       USED_REX (REX_B);
16188       if (rex & REX_B)
16189         reg += 8;
16190       oappend (names_xmm[reg]);
16191     }
16192   else
16193     {
16194       if (intel_syntax
16195           && (bytemode == v_mode || bytemode == v_swap_mode))
16196         {
16197           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16198           used_prefixes |= (prefixes & PREFIX_DATA);
16199         }
16200       OP_E (bytemode, sizeflag);
16201     }
16202 }
16203
16204 static void
16205 OP_Vex_2src_1 (int bytemode, int sizeflag)
16206 {
16207   if (modrm.mod == 3)
16208     {
16209       /* Skip mod/rm byte.   */
16210       MODRM_CHECK;
16211       codep++;
16212     }
16213
16214   if (vex.w)
16215     {
16216       unsigned int reg = vex.register_specifier;
16217       vex.register_specifier = 0;
16218
16219       if (address_mode != mode_64bit)
16220         reg &= 7;
16221       oappend (names_xmm[reg]);
16222     }
16223   else
16224     OP_Vex_2src (bytemode, sizeflag);
16225 }
16226
16227 static void
16228 OP_Vex_2src_2 (int bytemode, int sizeflag)
16229 {
16230   if (vex.w)
16231     OP_Vex_2src (bytemode, sizeflag);
16232   else
16233     {
16234       unsigned int reg = vex.register_specifier;
16235       vex.register_specifier = 0;
16236
16237       if (address_mode != mode_64bit)
16238         reg &= 7;
16239       oappend (names_xmm[reg]);
16240     }
16241 }
16242
16243 static void
16244 OP_EX_VexW (int bytemode, int sizeflag)
16245 {
16246   int reg = -1;
16247
16248   if (!vex_w_done)
16249     {
16250       /* Skip mod/rm byte.  */
16251       MODRM_CHECK;
16252       codep++;
16253
16254       if (vex.w)
16255         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16256     }
16257   else
16258     {
16259       if (!vex.w)
16260         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16261     }
16262
16263   OP_EX_VexReg (bytemode, sizeflag, reg);
16264
16265   if (vex_w_done)
16266     codep++;
16267   vex_w_done = 1;
16268 }
16269
16270 static void
16271 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16272 {
16273   int reg;
16274   const char **names;
16275
16276   FETCH_DATA (the_info, codep + 1);
16277   reg = *codep++;
16278
16279   if (bytemode != x_mode)
16280     abort ();
16281
16282   reg >>= 4;
16283   if (address_mode != mode_64bit)
16284     reg &= 7;
16285
16286   switch (vex.length)
16287     {
16288     case 128:
16289       names = names_xmm;
16290       break;
16291     case 256:
16292       names = names_ymm;
16293       break;
16294     default:
16295       abort ();
16296     }
16297   oappend (names[reg]);
16298 }
16299
16300 static void
16301 OP_XMM_VexW (int bytemode, int sizeflag)
16302 {
16303   /* Turn off the REX.W bit since it is used for swapping operands
16304      now.  */
16305   rex &= ~REX_W;
16306   OP_XMM (bytemode, sizeflag);
16307 }
16308
16309 static void
16310 OP_EX_Vex (int bytemode, int sizeflag)
16311 {
16312   if (modrm.mod != 3)
16313     need_vex_reg = 0;
16314   OP_EX (bytemode, sizeflag);
16315 }
16316
16317 static void
16318 OP_XMM_Vex (int bytemode, int sizeflag)
16319 {
16320   if (modrm.mod != 3)
16321     need_vex_reg = 0;
16322   OP_XMM (bytemode, sizeflag);
16323 }
16324
16325 static struct op vex_cmp_op[] =
16326 {
16327   { STRING_COMMA_LEN ("eq") },
16328   { STRING_COMMA_LEN ("lt") },
16329   { STRING_COMMA_LEN ("le") },
16330   { STRING_COMMA_LEN ("unord") },
16331   { STRING_COMMA_LEN ("neq") },
16332   { STRING_COMMA_LEN ("nlt") },
16333   { STRING_COMMA_LEN ("nle") },
16334   { STRING_COMMA_LEN ("ord") },
16335   { STRING_COMMA_LEN ("eq_uq") },
16336   { STRING_COMMA_LEN ("nge") },
16337   { STRING_COMMA_LEN ("ngt") },
16338   { STRING_COMMA_LEN ("false") },
16339   { STRING_COMMA_LEN ("neq_oq") },
16340   { STRING_COMMA_LEN ("ge") },
16341   { STRING_COMMA_LEN ("gt") },
16342   { STRING_COMMA_LEN ("true") },
16343   { STRING_COMMA_LEN ("eq_os") },
16344   { STRING_COMMA_LEN ("lt_oq") },
16345   { STRING_COMMA_LEN ("le_oq") },
16346   { STRING_COMMA_LEN ("unord_s") },
16347   { STRING_COMMA_LEN ("neq_us") },
16348   { STRING_COMMA_LEN ("nlt_uq") },
16349   { STRING_COMMA_LEN ("nle_uq") },
16350   { STRING_COMMA_LEN ("ord_s") },
16351   { STRING_COMMA_LEN ("eq_us") },
16352   { STRING_COMMA_LEN ("nge_uq") },
16353   { STRING_COMMA_LEN ("ngt_uq") },
16354   { STRING_COMMA_LEN ("false_os") },
16355   { STRING_COMMA_LEN ("neq_os") },
16356   { STRING_COMMA_LEN ("ge_oq") },
16357   { STRING_COMMA_LEN ("gt_oq") },
16358   { STRING_COMMA_LEN ("true_us") },
16359 };
16360
16361 static void
16362 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16363 {
16364   unsigned int cmp_type;
16365
16366   FETCH_DATA (the_info, codep + 1);
16367   cmp_type = *codep++ & 0xff;
16368   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16369     {
16370       char suffix [3];
16371       char *p = mnemonicendp - 2;
16372       suffix[0] = p[0];
16373       suffix[1] = p[1];
16374       suffix[2] = '\0';
16375       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16376       mnemonicendp += vex_cmp_op[cmp_type].len;
16377     }
16378   else
16379     {
16380       /* We have a reserved extension byte.  Output it directly.  */
16381       scratchbuf[0] = '$';
16382       print_operand_value (scratchbuf + 1, 1, cmp_type);
16383       oappend_maybe_intel (scratchbuf);
16384       scratchbuf[0] = '\0';
16385     }
16386 }
16387
16388 static void
16389 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16390              int sizeflag ATTRIBUTE_UNUSED)
16391 {
16392   unsigned int cmp_type;
16393
16394   if (!vex.evex)
16395     abort ();
16396
16397   FETCH_DATA (the_info, codep + 1);
16398   cmp_type = *codep++ & 0xff;
16399   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16400      If it's the case, print suffix, otherwise - print the immediate.  */
16401   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16402       && cmp_type != 3
16403       && cmp_type != 7)
16404     {
16405       char suffix [3];
16406       char *p = mnemonicendp - 2;
16407
16408       /* vpcmp* can have both one- and two-lettered suffix.  */
16409       if (p[0] == 'p')
16410         {
16411           p++;
16412           suffix[0] = p[0];
16413           suffix[1] = '\0';
16414         }
16415       else
16416         {
16417           suffix[0] = p[0];
16418           suffix[1] = p[1];
16419           suffix[2] = '\0';
16420         }
16421
16422       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16423       mnemonicendp += simd_cmp_op[cmp_type].len;
16424     }
16425   else
16426     {
16427       /* We have a reserved extension byte.  Output it directly.  */
16428       scratchbuf[0] = '$';
16429       print_operand_value (scratchbuf + 1, 1, cmp_type);
16430       oappend_maybe_intel (scratchbuf);
16431       scratchbuf[0] = '\0';
16432     }
16433 }
16434
16435 static const struct op xop_cmp_op[] =
16436 {
16437   { STRING_COMMA_LEN ("lt") },
16438   { STRING_COMMA_LEN ("le") },
16439   { STRING_COMMA_LEN ("gt") },
16440   { STRING_COMMA_LEN ("ge") },
16441   { STRING_COMMA_LEN ("eq") },
16442   { STRING_COMMA_LEN ("neq") },
16443   { STRING_COMMA_LEN ("false") },
16444   { STRING_COMMA_LEN ("true") }
16445 };
16446
16447 static void
16448 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16449              int sizeflag ATTRIBUTE_UNUSED)
16450 {
16451   unsigned int cmp_type;
16452
16453   FETCH_DATA (the_info, codep + 1);
16454   cmp_type = *codep++ & 0xff;
16455   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16456     {
16457       char suffix[3];
16458       char *p = mnemonicendp - 2;
16459
16460       /* vpcom* can have both one- and two-lettered suffix.  */
16461       if (p[0] == 'm')
16462         {
16463           p++;
16464           suffix[0] = p[0];
16465           suffix[1] = '\0';
16466         }
16467       else
16468         {
16469           suffix[0] = p[0];
16470           suffix[1] = p[1];
16471           suffix[2] = '\0';
16472         }
16473
16474       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16475       mnemonicendp += xop_cmp_op[cmp_type].len;
16476     }
16477   else
16478     {
16479       /* We have a reserved extension byte.  Output it directly.  */
16480       scratchbuf[0] = '$';
16481       print_operand_value (scratchbuf + 1, 1, cmp_type);
16482       oappend_maybe_intel (scratchbuf);
16483       scratchbuf[0] = '\0';
16484     }
16485 }
16486
16487 static const struct op pclmul_op[] =
16488 {
16489   { STRING_COMMA_LEN ("lql") },
16490   { STRING_COMMA_LEN ("hql") },
16491   { STRING_COMMA_LEN ("lqh") },
16492   { STRING_COMMA_LEN ("hqh") }
16493 };
16494
16495 static void
16496 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16497               int sizeflag ATTRIBUTE_UNUSED)
16498 {
16499   unsigned int pclmul_type;
16500
16501   FETCH_DATA (the_info, codep + 1);
16502   pclmul_type = *codep++ & 0xff;
16503   switch (pclmul_type)
16504     {
16505     case 0x10:
16506       pclmul_type = 2;
16507       break;
16508     case 0x11:
16509       pclmul_type = 3;
16510       break;
16511     default:
16512       break;
16513     }
16514   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16515     {
16516       char suffix [4];
16517       char *p = mnemonicendp - 3;
16518       suffix[0] = p[0];
16519       suffix[1] = p[1];
16520       suffix[2] = p[2];
16521       suffix[3] = '\0';
16522       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16523       mnemonicendp += pclmul_op[pclmul_type].len;
16524     }
16525   else
16526     {
16527       /* We have a reserved extension byte.  Output it directly.  */
16528       scratchbuf[0] = '$';
16529       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16530       oappend_maybe_intel (scratchbuf);
16531       scratchbuf[0] = '\0';
16532     }
16533 }
16534
16535 static void
16536 MOVBE_Fixup (int bytemode, int sizeflag)
16537 {
16538   /* Add proper suffix to "movbe".  */
16539   char *p = mnemonicendp;
16540
16541   switch (bytemode)
16542     {
16543     case v_mode:
16544       if (intel_syntax)
16545         goto skip;
16546
16547       USED_REX (REX_W);
16548       if (sizeflag & SUFFIX_ALWAYS)
16549         {
16550           if (rex & REX_W)
16551             *p++ = 'q';
16552           else
16553             {
16554               if (sizeflag & DFLAG)
16555                 *p++ = 'l';
16556               else
16557                 *p++ = 'w';
16558               used_prefixes |= (prefixes & PREFIX_DATA);
16559             }
16560         }
16561       break;
16562     default:
16563       oappend (INTERNAL_DISASSEMBLER_ERROR);
16564       break;
16565     }
16566   mnemonicendp = p;
16567   *p = '\0';
16568
16569  skip:
16570   OP_M (bytemode, sizeflag);
16571 }
16572
16573 static void
16574 MOVSXD_Fixup (int bytemode, int sizeflag)
16575 {
16576   /* Add proper suffix to "movsxd".  */
16577   char *p = mnemonicendp;
16578
16579   switch (bytemode)
16580     {
16581     case movsxd_mode:
16582       if (intel_syntax)
16583         {
16584           *p++ = 'x';
16585           *p++ = 'd';
16586           goto skip;
16587         }
16588
16589       USED_REX (REX_W);
16590       if (rex & REX_W)
16591         {
16592           *p++ = 'l';
16593           *p++ = 'q';
16594         }
16595       else
16596         {
16597           *p++ = 'x';
16598           *p++ = 'd';
16599         }
16600       break;
16601     default:
16602       oappend (INTERNAL_DISASSEMBLER_ERROR);
16603       break;
16604     }
16605
16606  skip:
16607   mnemonicendp = p;
16608   *p = '\0';
16609   OP_E (bytemode, sizeflag);
16610 }
16611
16612 static void
16613 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16614 {
16615   int reg;
16616   const char **names;
16617
16618   /* Skip mod/rm byte.  */
16619   MODRM_CHECK;
16620   codep++;
16621
16622   if (rex & REX_W)
16623     names = names64;
16624   else
16625     names = names32;
16626
16627   reg = modrm.rm;
16628   USED_REX (REX_B);
16629   if (rex & REX_B)
16630     reg += 8;
16631
16632   oappend (names[reg]);
16633 }
16634
16635 static void
16636 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16637 {
16638   const char **names;
16639   unsigned int reg = vex.register_specifier;
16640   vex.register_specifier = 0;
16641
16642   if (rex & REX_W)
16643     names = names64;
16644   else
16645     names = names32;
16646
16647   if (address_mode != mode_64bit)
16648     reg &= 7;
16649   oappend (names[reg]);
16650 }
16651
16652 static void
16653 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16654 {
16655   if (!vex.evex
16656       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16657     abort ();
16658
16659   USED_REX (REX_R);
16660   if ((rex & REX_R) != 0 || !vex.r)
16661     {
16662       BadOp ();
16663       return;
16664     }
16665
16666   oappend (names_mask [modrm.reg]);
16667 }
16668
16669 static void
16670 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16671 {
16672   if (!vex.evex
16673       || (bytemode != evex_rounding_mode
16674           && bytemode != evex_rounding_64_mode
16675           && bytemode != evex_sae_mode))
16676     abort ();
16677   if (modrm.mod == 3 && vex.b)
16678     switch (bytemode)
16679       {
16680       case evex_rounding_64_mode:
16681         if (address_mode != mode_64bit)
16682           {
16683             oappend ("(bad)");
16684             break;
16685           }
16686         /* Fall through.  */
16687       case evex_rounding_mode:
16688         oappend (names_rounding[vex.ll]);
16689         break;
16690       case evex_sae_mode:
16691         oappend ("{sae}");
16692         break;
16693       default:
16694         break;
16695       }
16696 }