opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 #define XX { NULL, 0 }
 225 #define Bad_Opcode NULL, { { NULL, 0 } }
 226
 227 #define Eb { OP_E, b_mode }
 228 #define Ebnd { OP_E, bnd_mode }
 229 #define EbS { OP_E, b_swap_mode }
 230 #define Ev { OP_E, v_mode }
 231 #define Ev_bnd { OP_E, v_bnd_mode }
 232 #define EvS { OP_E, v_swap_mode }
 233 #define Ed { OP_E, d_mode }
 234 #define Edq { OP_E, dq_mode }
 235 #define Edqw { OP_E, dqw_mode }
 236 #define EdqwS { OP_E, dqw_swap_mode }
 237 #define Edqb { OP_E, dqb_mode }
 238 #define Edb { OP_E, db_mode }
 239 #define Edw { OP_E, dw_mode }
 240 #define Edqd { OP_E, dqd_mode }
 241 #define Eq { OP_E, q_mode }
 242 #define indirEv { OP_indirE, stack_v_mode }
 243 #define indirEp { OP_indirE, f_mode }
 244 #define stackEv { OP_E, stack_v_mode }
 245 #define Em { OP_E, m_mode }
 246 #define Ew { OP_E, w_mode }
 247 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 248 #define Ma { OP_M, a_mode }
 249 #define Mb { OP_M, b_mode }
 250 #define Md { OP_M, d_mode }
 251 #define Mo { OP_M, o_mode }
 252 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 253 #define Mq { OP_M, q_mode }
 254 #define Mx { OP_M, x_mode }
 255 #define Mxmm { OP_M, xmm_mode }
 256 #define Gb { OP_G, b_mode }
 257 #define Gbnd { OP_G, bnd_mode }
 258 #define Gv { OP_G, v_mode }
 259 #define Gd { OP_G, d_mode }
 260 #define Gdq { OP_G, dq_mode }
 261 #define Gm { OP_G, m_mode }
 262 #define Gw { OP_G, w_mode }
 263 #define Rd { OP_R, d_mode }
 264 #define Rdq { OP_R, dq_mode }
 265 #define Rm { OP_R, m_mode }
 266 #define Ib { OP_I, b_mode }
 267 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 269 #define Iv { OP_I, v_mode }
 270 #define sIv { OP_sI, v_mode }
 271 #define Iq { OP_I, q_mode }
 272 #define Iv64 { OP_I64, v_mode }
 273 #define Iw { OP_I, w_mode }
 274 #define I1 { OP_I, const_1_mode }
 275 #define Jb { OP_J, b_mode }
 276 #define Jv { OP_J, v_mode }
 277 #define Cm { OP_C, m_mode }
 278 #define Dm { OP_D, m_mode }
 279 #define Td { OP_T, d_mode }
 280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 281
 282 #define RMeAX { OP_REG, eAX_reg }
 283 #define RMeBX { OP_REG, eBX_reg }
 284 #define RMeCX { OP_REG, eCX_reg }
 285 #define RMeDX { OP_REG, eDX_reg }
 286 #define RMeSP { OP_REG, eSP_reg }
 287 #define RMeBP { OP_REG, eBP_reg }
 288 #define RMeSI { OP_REG, eSI_reg }
 289 #define RMeDI { OP_REG, eDI_reg }
 290 #define RMrAX { OP_REG, rAX_reg }
 291 #define RMrBX { OP_REG, rBX_reg }
 292 #define RMrCX { OP_REG, rCX_reg }
 293 #define RMrDX { OP_REG, rDX_reg }
 294 #define RMrSP { OP_REG, rSP_reg }
 295 #define RMrBP { OP_REG, rBP_reg }
 296 #define RMrSI { OP_REG, rSI_reg }
 297 #define RMrDI { OP_REG, rDI_reg }
 298 #define RMAL { OP_REG, al_reg }
 299 #define RMCL { OP_REG, cl_reg }
 300 #define RMDL { OP_REG, dl_reg }
 301 #define RMBL { OP_REG, bl_reg }
 302 #define RMAH { OP_REG, ah_reg }
 303 #define RMCH { OP_REG, ch_reg }
 304 #define RMDH { OP_REG, dh_reg }
 305 #define RMBH { OP_REG, bh_reg }
 306 #define RMAX { OP_REG, ax_reg }
 307 #define RMDX { OP_REG, dx_reg }
 308
 309 #define eAX { OP_IMREG, eAX_reg }
 310 #define eBX { OP_IMREG, eBX_reg }
 311 #define eCX { OP_IMREG, eCX_reg }
 312 #define eDX { OP_IMREG, eDX_reg }
 313 #define eSP { OP_IMREG, eSP_reg }
 314 #define eBP { OP_IMREG, eBP_reg }
 315 #define eSI { OP_IMREG, eSI_reg }
 316 #define eDI { OP_IMREG, eDI_reg }
 317 #define AL { OP_IMREG, al_reg }
 318 #define CL { OP_IMREG, cl_reg }
 319 #define DL { OP_IMREG, dl_reg }
 320 #define BL { OP_IMREG, bl_reg }
 321 #define AH { OP_IMREG, ah_reg }
 322 #define CH { OP_IMREG, ch_reg }
 323 #define DH { OP_IMREG, dh_reg }
 324 #define BH { OP_IMREG, bh_reg }
 325 #define AX { OP_IMREG, ax_reg }
 326 #define DX { OP_IMREG, dx_reg }
 327 #define zAX { OP_IMREG, z_mode_ax_reg }
 328 #define indirDX { OP_IMREG, indir_dx_reg }
 329
 330 #define Sw { OP_SEG, w_mode }
 331 #define Sv { OP_SEG, v_mode }
 332 #define Ap { OP_DIR, 0 }
 333 #define Ob { OP_OFF64, b_mode }
 334 #define Ov { OP_OFF64, v_mode }
 335 #define Xb { OP_DSreg, eSI_reg }
 336 #define Xv { OP_DSreg, eSI_reg }
 337 #define Xz { OP_DSreg, eSI_reg }
 338 #define Yb { OP_ESreg, eDI_reg }
 339 #define Yv { OP_ESreg, eDI_reg }
 340 #define DSBX { OP_DSreg, eBX_reg }
 341
 342 #define es { OP_REG, es_reg }
 343 #define ss { OP_REG, ss_reg }
 344 #define cs { OP_REG, cs_reg }
 345 #define ds { OP_REG, ds_reg }
 346 #define fs { OP_REG, fs_reg }
 347 #define gs { OP_REG, gs_reg }
 348
 349 #define MX { OP_MMX, 0 }
 350 #define XM { OP_XMM, 0 }
 351 #define XMScalar { OP_XMM, scalar_mode }
 352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 353 #define XMM { OP_XMM, xmm_mode }
 354 #define XMxmmq { OP_XMM, xmmq_mode }
 355 #define EM { OP_EM, v_mode }
 356 #define EMS { OP_EM, v_swap_mode }
 357 #define EMd { OP_EM, d_mode }
 358 #define EMx { OP_EM, x_mode }
 359 #define EXw { OP_EX, w_mode }
 360 #define EXd { OP_EX, d_mode }
 361 #define EXdScalar { OP_EX, d_scalar_mode }
 362 #define EXdS { OP_EX, d_swap_mode }
 363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 364 #define EXq { OP_EX, q_mode }
 365 #define EXqScalar { OP_EX, q_scalar_mode }
 366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 367 #define EXqS { OP_EX, q_swap_mode }
 368 #define EXx { OP_EX, x_mode }
 369 #define EXxS { OP_EX, x_swap_mode }
 370 #define EXxmm { OP_EX, xmm_mode }
 371 #define EXymm { OP_EX, ymm_mode }
 372 #define EXxmmq { OP_EX, xmmq_mode }
 373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 376 #define EXxmm_md { OP_EX, xmm_md_mode }
 377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 379 #define EXxmmdw { OP_EX, xmmdw_mode }
 380 #define EXxmmqd { OP_EX, xmmqd_mode }
 381 #define EXymmq { OP_EX, ymmq_mode }
 382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 386 #define MS { OP_MS, v_mode }
 387 #define XS { OP_XS, v_mode }
 388 #define EMCq { OP_EMC, q_mode }
 389 #define MXC { OP_MXC, 0 }
 390 #define OPSUF { OP_3DNowSuffix, 0 }
 391 #define CMP { CMP_Fixup, 0 }
 392 #define XMM0 { XMM_Fixup, 0 }
 393 #define FXSAVE { FXSAVE_Fixup, 0 }
 394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 396
 397 #define Vex { OP_VEX, vex_mode }
 398 #define VexScalar { OP_VEX, vex_scalar_mode }
 399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 400 #define Vex128 { OP_VEX, vex128_mode }
 401 #define Vex256 { OP_VEX, vex256_mode }
 402 #define VexGdq { OP_VEX, dq_mode }
 403 #define VexI4 { VEXI4_Fixup, 0}
 404 #define EXdVex { OP_EX_Vex, d_mode }
 405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 407 #define EXqVex { OP_EX_Vex, q_mode }
 408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 410 #define EXVexW { OP_EX_VexW, x_mode }
 411 #define EXdVexW { OP_EX_VexW, d_mode }
 412 #define EXqVexW { OP_EX_VexW, q_mode }
 413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 414 #define XMVex { OP_XMM_Vex, 0 }
 415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 416 #define XMVexW { OP_XMM_VexW, 0 }
 417 #define XMVexI4 { OP_REG_VexI4, x_mode }
 418 #define PCLMUL { PCLMUL_Fixup, 0 }
 419 #define VZERO { VZERO_Fixup, 0 }
 420 #define VCMP { VCMP_Fixup, 0 }
 421 #define VPCMP { VPCMP_Fixup, 0 }
 422
 423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 425
 426 #define XMask { OP_Mask, mask_mode }
 427 #define MaskG { OP_G, mask_mode }
 428 #define MaskE { OP_E, mask_mode }
 429 #define MaskBDE { OP_E, mask_bd_mode }
 430 #define MaskR { OP_R, mask_mode }
 431 #define MaskVex { OP_VEX, mask_mode }
 432
 433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 437
 438 /* Used handle "rep" prefix for string instructions.  */
 439 #define Xbr { REP_Fixup, eSI_reg }
 440 #define Xvr { REP_Fixup, eSI_reg }
 441 #define Ybr { REP_Fixup, eDI_reg }
 442 #define Yvr { REP_Fixup, eDI_reg }
 443 #define Yzr { REP_Fixup, eDI_reg }
 444 #define indirDXr { REP_Fixup, indir_dx_reg }
 445 #define ALr { REP_Fixup, al_reg }
 446 #define eAXr { REP_Fixup, eAX_reg }
 447
 448 /* Used handle HLE prefix for lockable instructions.  */
 449 #define Ebh1 { HLE_Fixup1, b_mode }
 450 #define Evh1 { HLE_Fixup1, v_mode }
 451 #define Ebh2 { HLE_Fixup2, b_mode }
 452 #define Evh2 { HLE_Fixup2, v_mode }
 453 #define Ebh3 { HLE_Fixup3, b_mode }
 454 #define Evh3 { HLE_Fixup3, v_mode }
 455
 456 #define BND { BND_Fixup, 0 }
 457
 458 #define cond_jump_flag { NULL, cond_jump_mode }
 459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 460
 461 /* bits in sizeflag */
 462 #define SUFFIX_ALWAYS 4
 463 #define AFLAG 2
 464 #define DFLAG 1
 465
 466 enum
 467 {
 468   /* byte operand */
 469   b_mode = 1,
 470   /* byte operand with operand swapped */
 471   b_swap_mode,
 472   /* byte operand, sign extend like 'T' suffix */
 473   b_T_mode,
 474   /* operand size depends on prefixes */
 475   v_mode,
 476   /* operand size depends on prefixes with operand swapped */
 477   v_swap_mode,
 478   /* word operand */
 479   w_mode,
 480   /* double word operand  */
 481   d_mode,
 482   /* double word operand with operand swapped */
 483   d_swap_mode,
 484   /* quad word operand */
 485   q_mode,
 486   /* quad word operand with operand swapped */
 487   q_swap_mode,
 488   /* ten-byte operand */
 489   t_mode,
 490   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 491      broadcast enabled.  */
 492   x_mode,
 493   /* Similar to x_mode, but with different EVEX mem shifts.  */
 494   evex_x_gscat_mode,
 495   /* Similar to x_mode, but with disabled broadcast.  */
 496   evex_x_nobcst_mode,
 497   /* Similar to x_mode, but with operands swapped and disabled broadcast
 498      in EVEX.  */
 499   x_swap_mode,
 500   /* 16-byte XMM operand */
 501   xmm_mode,
 502   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 503      memory operand (depending on vector length).  Broadcast isn't
 504      allowed.  */
 505   xmmq_mode,
 506   /* Same as xmmq_mode, but broadcast is allowed.  */
 507   evex_half_bcst_xmmq_mode,
 508   /* XMM register or byte memory operand */
 509   xmm_mb_mode,
 510   /* XMM register or word memory operand */
 511   xmm_mw_mode,
 512   /* XMM register or double word memory operand */
 513   xmm_md_mode,
 514   /* XMM register or quad word memory operand */
 515   xmm_mq_mode,
 516   /* XMM register or double/quad word memory operand, depending on
 517      VEX.W.  */
 518   xmm_mdq_mode,
 519   /* 16-byte XMM, word, double word or quad word operand.  */
 520   xmmdw_mode,
 521   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 522   xmmqd_mode,
 523   /* 32-byte YMM operand */
 524   ymm_mode,
 525   /* quad word, ymmword or zmmword memory operand.  */
 526   ymmq_mode,
 527   /* 32-byte YMM or 16-byte word operand */
 528   ymmxmm_mode,
 529   /* d_mode in 32bit, q_mode in 64bit mode.  */
 530   m_mode,
 531   /* pair of v_mode operands */
 532   a_mode,
 533   cond_jump_mode,
 534   loop_jcxz_mode,
 535   v_bnd_mode,
 536   /* operand size depends on REX prefixes.  */
 537   dq_mode,
 538   /* registers like dq_mode, memory like w_mode.  */
 539   dqw_mode,
 540   dqw_swap_mode,
 541   bnd_mode,
 542   /* 4- or 6-byte pointer operand */
 543   f_mode,
 544   const_1_mode,
 545   /* v_mode for stack-related opcodes.  */
 546   stack_v_mode,
 547   /* non-quad operand size depends on prefixes */
 548   z_mode,
 549   /* 16-byte operand */
 550   o_mode,
 551   /* registers like dq_mode, memory like b_mode.  */
 552   dqb_mode,
 553   /* registers like d_mode, memory like b_mode.  */
 554   db_mode,
 555   /* registers like d_mode, memory like w_mode.  */
 556   dw_mode,
 557   /* registers like dq_mode, memory like d_mode.  */
 558   dqd_mode,
 559   /* normal vex mode */
 560   vex_mode,
 561   /* 128bit vex mode */
 562   vex128_mode,
 563   /* 256bit vex mode */
 564   vex256_mode,
 565   /* operand size depends on the VEX.W bit.  */
 566   vex_w_dq_mode,
 567
 568   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 569   vex_vsib_d_w_dq_mode,
 570   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 571   vex_vsib_d_w_d_mode,
 572   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 573   vex_vsib_q_w_dq_mode,
 574   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 575   vex_vsib_q_w_d_mode,
 576
 577   /* scalar, ignore vector length.  */
 578   scalar_mode,
 579   /* like d_mode, ignore vector length.  */
 580   d_scalar_mode,
 581   /* like d_swap_mode, ignore vector length.  */
 582   d_scalar_swap_mode,
 583   /* like q_mode, ignore vector length.  */
 584   q_scalar_mode,
 585   /* like q_swap_mode, ignore vector length.  */
 586   q_scalar_swap_mode,
 587   /* like vex_mode, ignore vector length.  */
 588   vex_scalar_mode,
 589   /* like vex_w_dq_mode, ignore vector length.  */
 590   vex_scalar_w_dq_mode,
 591
 592   /* Static rounding.  */
 593   evex_rounding_mode,
 594   /* Supress all exceptions.  */
 595   evex_sae_mode,
 596
 597   /* Mask register operand.  */
 598   mask_mode,
 599   /* Mask register operand.  */
 600   mask_bd_mode,
 601
 602   es_reg,
 603   cs_reg,
 604   ss_reg,
 605   ds_reg,
 606   fs_reg,
 607   gs_reg,
 608
 609   eAX_reg,
 610   eCX_reg,
 611   eDX_reg,
 612   eBX_reg,
 613   eSP_reg,
 614   eBP_reg,
 615   eSI_reg,
 616   eDI_reg,
 617
 618   al_reg,
 619   cl_reg,
 620   dl_reg,
 621   bl_reg,
 622   ah_reg,
 623   ch_reg,
 624   dh_reg,
 625   bh_reg,
 626
 627   ax_reg,
 628   cx_reg,
 629   dx_reg,
 630   bx_reg,
 631   sp_reg,
 632   bp_reg,
 633   si_reg,
 634   di_reg,
 635
 636   rAX_reg,
 637   rCX_reg,
 638   rDX_reg,
 639   rBX_reg,
 640   rSP_reg,
 641   rBP_reg,
 642   rSI_reg,
 643   rDI_reg,
 644
 645   z_mode_ax_reg,
 646   indir_dx_reg
 647 };
 648
 649 enum
 650 {
 651   FLOATCODE = 1,
 652   USE_REG_TABLE,
 653   USE_MOD_TABLE,
 654   USE_RM_TABLE,
 655   USE_PREFIX_TABLE,
 656   USE_X86_64_TABLE,
 657   USE_3BYTE_TABLE,
 658   USE_XOP_8F_TABLE,
 659   USE_VEX_C4_TABLE,
 660   USE_VEX_C5_TABLE,
 661   USE_VEX_LEN_TABLE,
 662   USE_VEX_W_TABLE,
 663   USE_EVEX_TABLE
 664 };
 665
 666 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 667
 668 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 669 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 670 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 671 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 672 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 673 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 674 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 675 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 676 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 677 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 678 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 679 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 680 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 681
 682 enum
 683 {
 684   REG_80 = 0,
 685   REG_81,
 686   REG_82,
 687   REG_8F,
 688   REG_C0,
 689   REG_C1,
 690   REG_C6,
 691   REG_C7,
 692   REG_D0,
 693   REG_D1,
 694   REG_D2,
 695   REG_D3,
 696   REG_F6,
 697   REG_F7,
 698   REG_FE,
 699   REG_FF,
 700   REG_0F00,
 701   REG_0F01,
 702   REG_0F0D,
 703   REG_0F18,
 704   REG_0F71,
 705   REG_0F72,
 706   REG_0F73,
 707   REG_0FA6,
 708   REG_0FA7,
 709   REG_0FAE,
 710   REG_0FBA,
 711   REG_0FC7,
 712   REG_VEX_0F71,
 713   REG_VEX_0F72,
 714   REG_VEX_0F73,
 715   REG_VEX_0FAE,
 716   REG_VEX_0F38F3,
 717   REG_XOP_LWPCB,
 718   REG_XOP_LWP,
 719   REG_XOP_TBM_01,
 720   REG_XOP_TBM_02,
 721
 722   REG_EVEX_0F71,
 723   REG_EVEX_0F72,
 724   REG_EVEX_0F73,
 725   REG_EVEX_0F38C6,
 726   REG_EVEX_0F38C7
 727 };
 728
 729 enum
 730 {
 731   MOD_8D = 0,
 732   MOD_C6_REG_7,
 733   MOD_C7_REG_7,
 734   MOD_FF_REG_3,
 735   MOD_FF_REG_5,
 736   MOD_0F01_REG_0,
 737   MOD_0F01_REG_1,
 738   MOD_0F01_REG_2,
 739   MOD_0F01_REG_3,
 740   MOD_0F01_REG_7,
 741   MOD_0F12_PREFIX_0,
 742   MOD_0F13,
 743   MOD_0F16_PREFIX_0,
 744   MOD_0F17,
 745   MOD_0F18_REG_0,
 746   MOD_0F18_REG_1,
 747   MOD_0F18_REG_2,
 748   MOD_0F18_REG_3,
 749   MOD_0F18_REG_4,
 750   MOD_0F18_REG_5,
 751   MOD_0F18_REG_6,
 752   MOD_0F18_REG_7,
 753   MOD_0F1A_PREFIX_0,
 754   MOD_0F1B_PREFIX_0,
 755   MOD_0F1B_PREFIX_1,
 756   MOD_0F20,
 757   MOD_0F21,
 758   MOD_0F22,
 759   MOD_0F23,
 760   MOD_0F24,
 761   MOD_0F26,
 762   MOD_0F2B_PREFIX_0,
 763   MOD_0F2B_PREFIX_1,
 764   MOD_0F2B_PREFIX_2,
 765   MOD_0F2B_PREFIX_3,
 766   MOD_0F51,
 767   MOD_0F71_REG_2,
 768   MOD_0F71_REG_4,
 769   MOD_0F71_REG_6,
 770   MOD_0F72_REG_2,
 771   MOD_0F72_REG_4,
 772   MOD_0F72_REG_6,
 773   MOD_0F73_REG_2,
 774   MOD_0F73_REG_3,
 775   MOD_0F73_REG_6,
 776   MOD_0F73_REG_7,
 777   MOD_0FAE_REG_0,
 778   MOD_0FAE_REG_1,
 779   MOD_0FAE_REG_2,
 780   MOD_0FAE_REG_3,
 781   MOD_0FAE_REG_4,
 782   MOD_0FAE_REG_5,
 783   MOD_0FAE_REG_6,
 784   MOD_0FAE_REG_7,
 785   MOD_0FB2,
 786   MOD_0FB4,
 787   MOD_0FB5,
 788   MOD_0FC7_REG_3,
 789   MOD_0FC7_REG_4,
 790   MOD_0FC7_REG_5,
 791   MOD_0FC7_REG_6,
 792   MOD_0FC7_REG_7,
 793   MOD_0FD7,
 794   MOD_0FE7_PREFIX_2,
 795   MOD_0FF0_PREFIX_3,
 796   MOD_0F382A_PREFIX_2,
 797   MOD_62_32BIT,
 798   MOD_C4_32BIT,
 799   MOD_C5_32BIT,
 800   MOD_VEX_0F12_PREFIX_0,
 801   MOD_VEX_0F13,
 802   MOD_VEX_0F16_PREFIX_0,
 803   MOD_VEX_0F17,
 804   MOD_VEX_0F2B,
 805   MOD_VEX_0F50,
 806   MOD_VEX_0F71_REG_2,
 807   MOD_VEX_0F71_REG_4,
 808   MOD_VEX_0F71_REG_6,
 809   MOD_VEX_0F72_REG_2,
 810   MOD_VEX_0F72_REG_4,
 811   MOD_VEX_0F72_REG_6,
 812   MOD_VEX_0F73_REG_2,
 813   MOD_VEX_0F73_REG_3,
 814   MOD_VEX_0F73_REG_6,
 815   MOD_VEX_0F73_REG_7,
 816   MOD_VEX_0FAE_REG_2,
 817   MOD_VEX_0FAE_REG_3,
 818   MOD_VEX_0FD7_PREFIX_2,
 819   MOD_VEX_0FE7_PREFIX_2,
 820   MOD_VEX_0FF0_PREFIX_3,
 821   MOD_VEX_0F381A_PREFIX_2,
 822   MOD_VEX_0F382A_PREFIX_2,
 823   MOD_VEX_0F382C_PREFIX_2,
 824   MOD_VEX_0F382D_PREFIX_2,
 825   MOD_VEX_0F382E_PREFIX_2,
 826   MOD_VEX_0F382F_PREFIX_2,
 827   MOD_VEX_0F385A_PREFIX_2,
 828   MOD_VEX_0F388C_PREFIX_2,
 829   MOD_VEX_0F388E_PREFIX_2,
 830
 831   MOD_EVEX_0F10_PREFIX_1,
 832   MOD_EVEX_0F10_PREFIX_3,
 833   MOD_EVEX_0F11_PREFIX_1,
 834   MOD_EVEX_0F11_PREFIX_3,
 835   MOD_EVEX_0F12_PREFIX_0,
 836   MOD_EVEX_0F16_PREFIX_0,
 837   MOD_EVEX_0F38C6_REG_1,
 838   MOD_EVEX_0F38C6_REG_2,
 839   MOD_EVEX_0F38C6_REG_5,
 840   MOD_EVEX_0F38C6_REG_6,
 841   MOD_EVEX_0F38C7_REG_1,
 842   MOD_EVEX_0F38C7_REG_2,
 843   MOD_EVEX_0F38C7_REG_5,
 844   MOD_EVEX_0F38C7_REG_6
 845 };
 846
 847 enum
 848 {
 849   RM_C6_REG_7 = 0,
 850   RM_C7_REG_7,
 851   RM_0F01_REG_0,
 852   RM_0F01_REG_1,
 853   RM_0F01_REG_2,
 854   RM_0F01_REG_3,
 855   RM_0F01_REG_7,
 856   RM_0FAE_REG_5,
 857   RM_0FAE_REG_6,
 858   RM_0FAE_REG_7
 859 };
 860
 861 enum
 862 {
 863   PREFIX_90 = 0,
 864   PREFIX_0F10,
 865   PREFIX_0F11,
 866   PREFIX_0F12,
 867   PREFIX_0F16,
 868   PREFIX_0F1A,
 869   PREFIX_0F1B,
 870   PREFIX_0F2A,
 871   PREFIX_0F2B,
 872   PREFIX_0F2C,
 873   PREFIX_0F2D,
 874   PREFIX_0F2E,
 875   PREFIX_0F2F,
 876   PREFIX_0F51,
 877   PREFIX_0F52,
 878   PREFIX_0F53,
 879   PREFIX_0F58,
 880   PREFIX_0F59,
 881   PREFIX_0F5A,
 882   PREFIX_0F5B,
 883   PREFIX_0F5C,
 884   PREFIX_0F5D,
 885   PREFIX_0F5E,
 886   PREFIX_0F5F,
 887   PREFIX_0F60,
 888   PREFIX_0F61,
 889   PREFIX_0F62,
 890   PREFIX_0F6C,
 891   PREFIX_0F6D,
 892   PREFIX_0F6F,
 893   PREFIX_0F70,
 894   PREFIX_0F73_REG_3,
 895   PREFIX_0F73_REG_7,
 896   PREFIX_0F78,
 897   PREFIX_0F79,
 898   PREFIX_0F7C,
 899   PREFIX_0F7D,
 900   PREFIX_0F7E,
 901   PREFIX_0F7F,
 902   PREFIX_0FAE_REG_0,
 903   PREFIX_0FAE_REG_1,
 904   PREFIX_0FAE_REG_2,
 905   PREFIX_0FAE_REG_3,
 906   PREFIX_0FAE_REG_7,
 907   PREFIX_0FB8,
 908   PREFIX_0FBC,
 909   PREFIX_0FBD,
 910   PREFIX_0FC2,
 911   PREFIX_0FC3,
 912   PREFIX_0FC7_REG_6,
 913   PREFIX_0FD0,
 914   PREFIX_0FD6,
 915   PREFIX_0FE6,
 916   PREFIX_0FE7,
 917   PREFIX_0FF0,
 918   PREFIX_0FF7,
 919   PREFIX_0F3810,
 920   PREFIX_0F3814,
 921   PREFIX_0F3815,
 922   PREFIX_0F3817,
 923   PREFIX_0F3820,
 924   PREFIX_0F3821,
 925   PREFIX_0F3822,
 926   PREFIX_0F3823,
 927   PREFIX_0F3824,
 928   PREFIX_0F3825,
 929   PREFIX_0F3828,
 930   PREFIX_0F3829,
 931   PREFIX_0F382A,
 932   PREFIX_0F382B,
 933   PREFIX_0F3830,
 934   PREFIX_0F3831,
 935   PREFIX_0F3832,
 936   PREFIX_0F3833,
 937   PREFIX_0F3834,
 938   PREFIX_0F3835,
 939   PREFIX_0F3837,
 940   PREFIX_0F3838,
 941   PREFIX_0F3839,
 942   PREFIX_0F383A,
 943   PREFIX_0F383B,
 944   PREFIX_0F383C,
 945   PREFIX_0F383D,
 946   PREFIX_0F383E,
 947   PREFIX_0F383F,
 948   PREFIX_0F3840,
 949   PREFIX_0F3841,
 950   PREFIX_0F3880,
 951   PREFIX_0F3881,
 952   PREFIX_0F3882,
 953   PREFIX_0F38C8,
 954   PREFIX_0F38C9,
 955   PREFIX_0F38CA,
 956   PREFIX_0F38CB,
 957   PREFIX_0F38CC,
 958   PREFIX_0F38CD,
 959   PREFIX_0F38DB,
 960   PREFIX_0F38DC,
 961   PREFIX_0F38DD,
 962   PREFIX_0F38DE,
 963   PREFIX_0F38DF,
 964   PREFIX_0F38F0,
 965   PREFIX_0F38F1,
 966   PREFIX_0F38F6,
 967   PREFIX_0F3A08,
 968   PREFIX_0F3A09,
 969   PREFIX_0F3A0A,
 970   PREFIX_0F3A0B,
 971   PREFIX_0F3A0C,
 972   PREFIX_0F3A0D,
 973   PREFIX_0F3A0E,
 974   PREFIX_0F3A14,
 975   PREFIX_0F3A15,
 976   PREFIX_0F3A16,
 977   PREFIX_0F3A17,
 978   PREFIX_0F3A20,
 979   PREFIX_0F3A21,
 980   PREFIX_0F3A22,
 981   PREFIX_0F3A40,
 982   PREFIX_0F3A41,
 983   PREFIX_0F3A42,
 984   PREFIX_0F3A44,
 985   PREFIX_0F3A60,
 986   PREFIX_0F3A61,
 987   PREFIX_0F3A62,
 988   PREFIX_0F3A63,
 989   PREFIX_0F3ACC,
 990   PREFIX_0F3ADF,
 991   PREFIX_VEX_0F10,
 992   PREFIX_VEX_0F11,
 993   PREFIX_VEX_0F12,
 994   PREFIX_VEX_0F16,
 995   PREFIX_VEX_0F2A,
 996   PREFIX_VEX_0F2C,
 997   PREFIX_VEX_0F2D,
 998   PREFIX_VEX_0F2E,
 999   PREFIX_VEX_0F2F,
1000   PREFIX_VEX_0F41,
1001   PREFIX_VEX_0F42,
1002   PREFIX_VEX_0F44,
1003   PREFIX_VEX_0F45,
1004   PREFIX_VEX_0F46,
1005   PREFIX_VEX_0F47,
1006   PREFIX_VEX_0F4A,
1007   PREFIX_VEX_0F4B,
1008   PREFIX_VEX_0F51,
1009   PREFIX_VEX_0F52,
1010   PREFIX_VEX_0F53,
1011   PREFIX_VEX_0F58,
1012   PREFIX_VEX_0F59,
1013   PREFIX_VEX_0F5A,
1014   PREFIX_VEX_0F5B,
1015   PREFIX_VEX_0F5C,
1016   PREFIX_VEX_0F5D,
1017   PREFIX_VEX_0F5E,
1018   PREFIX_VEX_0F5F,
1019   PREFIX_VEX_0F60,
1020   PREFIX_VEX_0F61,
1021   PREFIX_VEX_0F62,
1022   PREFIX_VEX_0F63,
1023   PREFIX_VEX_0F64,
1024   PREFIX_VEX_0F65,
1025   PREFIX_VEX_0F66,
1026   PREFIX_VEX_0F67,
1027   PREFIX_VEX_0F68,
1028   PREFIX_VEX_0F69,
1029   PREFIX_VEX_0F6A,
1030   PREFIX_VEX_0F6B,
1031   PREFIX_VEX_0F6C,
1032   PREFIX_VEX_0F6D,
1033   PREFIX_VEX_0F6E,
1034   PREFIX_VEX_0F6F,
1035   PREFIX_VEX_0F70,
1036   PREFIX_VEX_0F71_REG_2,
1037   PREFIX_VEX_0F71_REG_4,
1038   PREFIX_VEX_0F71_REG_6,
1039   PREFIX_VEX_0F72_REG_2,
1040   PREFIX_VEX_0F72_REG_4,
1041   PREFIX_VEX_0F72_REG_6,
1042   PREFIX_VEX_0F73_REG_2,
1043   PREFIX_VEX_0F73_REG_3,
1044   PREFIX_VEX_0F73_REG_6,
1045   PREFIX_VEX_0F73_REG_7,
1046   PREFIX_VEX_0F74,
1047   PREFIX_VEX_0F75,
1048   PREFIX_VEX_0F76,
1049   PREFIX_VEX_0F77,
1050   PREFIX_VEX_0F7C,
1051   PREFIX_VEX_0F7D,
1052   PREFIX_VEX_0F7E,
1053   PREFIX_VEX_0F7F,
1054   PREFIX_VEX_0F90,
1055   PREFIX_VEX_0F91,
1056   PREFIX_VEX_0F92,
1057   PREFIX_VEX_0F93,
1058   PREFIX_VEX_0F98,
1059   PREFIX_VEX_0F99,
1060   PREFIX_VEX_0FC2,
1061   PREFIX_VEX_0FC4,
1062   PREFIX_VEX_0FC5,
1063   PREFIX_VEX_0FD0,
1064   PREFIX_VEX_0FD1,
1065   PREFIX_VEX_0FD2,
1066   PREFIX_VEX_0FD3,
1067   PREFIX_VEX_0FD4,
1068   PREFIX_VEX_0FD5,
1069   PREFIX_VEX_0FD6,
1070   PREFIX_VEX_0FD7,
1071   PREFIX_VEX_0FD8,
1072   PREFIX_VEX_0FD9,
1073   PREFIX_VEX_0FDA,
1074   PREFIX_VEX_0FDB,
1075   PREFIX_VEX_0FDC,
1076   PREFIX_VEX_0FDD,
1077   PREFIX_VEX_0FDE,
1078   PREFIX_VEX_0FDF,
1079   PREFIX_VEX_0FE0,
1080   PREFIX_VEX_0FE1,
1081   PREFIX_VEX_0FE2,
1082   PREFIX_VEX_0FE3,
1083   PREFIX_VEX_0FE4,
1084   PREFIX_VEX_0FE5,
1085   PREFIX_VEX_0FE6,
1086   PREFIX_VEX_0FE7,
1087   PREFIX_VEX_0FE8,
1088   PREFIX_VEX_0FE9,
1089   PREFIX_VEX_0FEA,
1090   PREFIX_VEX_0FEB,
1091   PREFIX_VEX_0FEC,
1092   PREFIX_VEX_0FED,
1093   PREFIX_VEX_0FEE,
1094   PREFIX_VEX_0FEF,
1095   PREFIX_VEX_0FF0,
1096   PREFIX_VEX_0FF1,
1097   PREFIX_VEX_0FF2,
1098   PREFIX_VEX_0FF3,
1099   PREFIX_VEX_0FF4,
1100   PREFIX_VEX_0FF5,
1101   PREFIX_VEX_0FF6,
1102   PREFIX_VEX_0FF7,
1103   PREFIX_VEX_0FF8,
1104   PREFIX_VEX_0FF9,
1105   PREFIX_VEX_0FFA,
1106   PREFIX_VEX_0FFB,
1107   PREFIX_VEX_0FFC,
1108   PREFIX_VEX_0FFD,
1109   PREFIX_VEX_0FFE,
1110   PREFIX_VEX_0F3800,
1111   PREFIX_VEX_0F3801,
1112   PREFIX_VEX_0F3802,
1113   PREFIX_VEX_0F3803,
1114   PREFIX_VEX_0F3804,
1115   PREFIX_VEX_0F3805,
1116   PREFIX_VEX_0F3806,
1117   PREFIX_VEX_0F3807,
1118   PREFIX_VEX_0F3808,
1119   PREFIX_VEX_0F3809,
1120   PREFIX_VEX_0F380A,
1121   PREFIX_VEX_0F380B,
1122   PREFIX_VEX_0F380C,
1123   PREFIX_VEX_0F380D,
1124   PREFIX_VEX_0F380E,
1125   PREFIX_VEX_0F380F,
1126   PREFIX_VEX_0F3813,
1127   PREFIX_VEX_0F3816,
1128   PREFIX_VEX_0F3817,
1129   PREFIX_VEX_0F3818,
1130   PREFIX_VEX_0F3819,
1131   PREFIX_VEX_0F381A,
1132   PREFIX_VEX_0F381C,
1133   PREFIX_VEX_0F381D,
1134   PREFIX_VEX_0F381E,
1135   PREFIX_VEX_0F3820,
1136   PREFIX_VEX_0F3821,
1137   PREFIX_VEX_0F3822,
1138   PREFIX_VEX_0F3823,
1139   PREFIX_VEX_0F3824,
1140   PREFIX_VEX_0F3825,
1141   PREFIX_VEX_0F3828,
1142   PREFIX_VEX_0F3829,
1143   PREFIX_VEX_0F382A,
1144   PREFIX_VEX_0F382B,
1145   PREFIX_VEX_0F382C,
1146   PREFIX_VEX_0F382D,
1147   PREFIX_VEX_0F382E,
1148   PREFIX_VEX_0F382F,
1149   PREFIX_VEX_0F3830,
1150   PREFIX_VEX_0F3831,
1151   PREFIX_VEX_0F3832,
1152   PREFIX_VEX_0F3833,
1153   PREFIX_VEX_0F3834,
1154   PREFIX_VEX_0F3835,
1155   PREFIX_VEX_0F3836,
1156   PREFIX_VEX_0F3837,
1157   PREFIX_VEX_0F3838,
1158   PREFIX_VEX_0F3839,
1159   PREFIX_VEX_0F383A,
1160   PREFIX_VEX_0F383B,
1161   PREFIX_VEX_0F383C,
1162   PREFIX_VEX_0F383D,
1163   PREFIX_VEX_0F383E,
1164   PREFIX_VEX_0F383F,
1165   PREFIX_VEX_0F3840,
1166   PREFIX_VEX_0F3841,
1167   PREFIX_VEX_0F3845,
1168   PREFIX_VEX_0F3846,
1169   PREFIX_VEX_0F3847,
1170   PREFIX_VEX_0F3858,
1171   PREFIX_VEX_0F3859,
1172   PREFIX_VEX_0F385A,
1173   PREFIX_VEX_0F3878,
1174   PREFIX_VEX_0F3879,
1175   PREFIX_VEX_0F388C,
1176   PREFIX_VEX_0F388E,
1177   PREFIX_VEX_0F3890,
1178   PREFIX_VEX_0F3891,
1179   PREFIX_VEX_0F3892,
1180   PREFIX_VEX_0F3893,
1181   PREFIX_VEX_0F3896,
1182   PREFIX_VEX_0F3897,
1183   PREFIX_VEX_0F3898,
1184   PREFIX_VEX_0F3899,
1185   PREFIX_VEX_0F389A,
1186   PREFIX_VEX_0F389B,
1187   PREFIX_VEX_0F389C,
1188   PREFIX_VEX_0F389D,
1189   PREFIX_VEX_0F389E,
1190   PREFIX_VEX_0F389F,
1191   PREFIX_VEX_0F38A6,
1192   PREFIX_VEX_0F38A7,
1193   PREFIX_VEX_0F38A8,
1194   PREFIX_VEX_0F38A9,
1195   PREFIX_VEX_0F38AA,
1196   PREFIX_VEX_0F38AB,
1197   PREFIX_VEX_0F38AC,
1198   PREFIX_VEX_0F38AD,
1199   PREFIX_VEX_0F38AE,
1200   PREFIX_VEX_0F38AF,
1201   PREFIX_VEX_0F38B6,
1202   PREFIX_VEX_0F38B7,
1203   PREFIX_VEX_0F38B8,
1204   PREFIX_VEX_0F38B9,
1205   PREFIX_VEX_0F38BA,
1206   PREFIX_VEX_0F38BB,
1207   PREFIX_VEX_0F38BC,
1208   PREFIX_VEX_0F38BD,
1209   PREFIX_VEX_0F38BE,
1210   PREFIX_VEX_0F38BF,
1211   PREFIX_VEX_0F38DB,
1212   PREFIX_VEX_0F38DC,
1213   PREFIX_VEX_0F38DD,
1214   PREFIX_VEX_0F38DE,
1215   PREFIX_VEX_0F38DF,
1216   PREFIX_VEX_0F38F2,
1217   PREFIX_VEX_0F38F3_REG_1,
1218   PREFIX_VEX_0F38F3_REG_2,
1219   PREFIX_VEX_0F38F3_REG_3,
1220   PREFIX_VEX_0F38F5,
1221   PREFIX_VEX_0F38F6,
1222   PREFIX_VEX_0F38F7,
1223   PREFIX_VEX_0F3A00,
1224   PREFIX_VEX_0F3A01,
1225   PREFIX_VEX_0F3A02,
1226   PREFIX_VEX_0F3A04,
1227   PREFIX_VEX_0F3A05,
1228   PREFIX_VEX_0F3A06,
1229   PREFIX_VEX_0F3A08,
1230   PREFIX_VEX_0F3A09,
1231   PREFIX_VEX_0F3A0A,
1232   PREFIX_VEX_0F3A0B,
1233   PREFIX_VEX_0F3A0C,
1234   PREFIX_VEX_0F3A0D,
1235   PREFIX_VEX_0F3A0E,
1236   PREFIX_VEX_0F3A0F,
1237   PREFIX_VEX_0F3A14,
1238   PREFIX_VEX_0F3A15,
1239   PREFIX_VEX_0F3A16,
1240   PREFIX_VEX_0F3A17,
1241   PREFIX_VEX_0F3A18,
1242   PREFIX_VEX_0F3A19,
1243   PREFIX_VEX_0F3A1D,
1244   PREFIX_VEX_0F3A20,
1245   PREFIX_VEX_0F3A21,
1246   PREFIX_VEX_0F3A22,
1247   PREFIX_VEX_0F3A30,
1248   PREFIX_VEX_0F3A31,
1249   PREFIX_VEX_0F3A32,
1250   PREFIX_VEX_0F3A33,
1251   PREFIX_VEX_0F3A38,
1252   PREFIX_VEX_0F3A39,
1253   PREFIX_VEX_0F3A40,
1254   PREFIX_VEX_0F3A41,
1255   PREFIX_VEX_0F3A42,
1256   PREFIX_VEX_0F3A44,
1257   PREFIX_VEX_0F3A46,
1258   PREFIX_VEX_0F3A48,
1259   PREFIX_VEX_0F3A49,
1260   PREFIX_VEX_0F3A4A,
1261   PREFIX_VEX_0F3A4B,
1262   PREFIX_VEX_0F3A4C,
1263   PREFIX_VEX_0F3A5C,
1264   PREFIX_VEX_0F3A5D,
1265   PREFIX_VEX_0F3A5E,
1266   PREFIX_VEX_0F3A5F,
1267   PREFIX_VEX_0F3A60,
1268   PREFIX_VEX_0F3A61,
1269   PREFIX_VEX_0F3A62,
1270   PREFIX_VEX_0F3A63,
1271   PREFIX_VEX_0F3A68,
1272   PREFIX_VEX_0F3A69,
1273   PREFIX_VEX_0F3A6A,
1274   PREFIX_VEX_0F3A6B,
1275   PREFIX_VEX_0F3A6C,
1276   PREFIX_VEX_0F3A6D,
1277   PREFIX_VEX_0F3A6E,
1278   PREFIX_VEX_0F3A6F,
1279   PREFIX_VEX_0F3A78,
1280   PREFIX_VEX_0F3A79,
1281   PREFIX_VEX_0F3A7A,
1282   PREFIX_VEX_0F3A7B,
1283   PREFIX_VEX_0F3A7C,
1284   PREFIX_VEX_0F3A7D,
1285   PREFIX_VEX_0F3A7E,
1286   PREFIX_VEX_0F3A7F,
1287   PREFIX_VEX_0F3ADF,
1288   PREFIX_VEX_0F3AF0,
1289
1290   PREFIX_EVEX_0F10,
1291   PREFIX_EVEX_0F11,
1292   PREFIX_EVEX_0F12,
1293   PREFIX_EVEX_0F13,
1294   PREFIX_EVEX_0F14,
1295   PREFIX_EVEX_0F15,
1296   PREFIX_EVEX_0F16,
1297   PREFIX_EVEX_0F17,
1298   PREFIX_EVEX_0F28,
1299   PREFIX_EVEX_0F29,
1300   PREFIX_EVEX_0F2A,
1301   PREFIX_EVEX_0F2B,
1302   PREFIX_EVEX_0F2C,
1303   PREFIX_EVEX_0F2D,
1304   PREFIX_EVEX_0F2E,
1305   PREFIX_EVEX_0F2F,
1306   PREFIX_EVEX_0F51,
1307   PREFIX_EVEX_0F58,
1308   PREFIX_EVEX_0F59,
1309   PREFIX_EVEX_0F5A,
1310   PREFIX_EVEX_0F5B,
1311   PREFIX_EVEX_0F5C,
1312   PREFIX_EVEX_0F5D,
1313   PREFIX_EVEX_0F5E,
1314   PREFIX_EVEX_0F5F,
1315   PREFIX_EVEX_0F60,
1316   PREFIX_EVEX_0F61,
1317   PREFIX_EVEX_0F62,
1318   PREFIX_EVEX_0F63,
1319   PREFIX_EVEX_0F64,
1320   PREFIX_EVEX_0F65,
1321   PREFIX_EVEX_0F66,
1322   PREFIX_EVEX_0F67,
1323   PREFIX_EVEX_0F68,
1324   PREFIX_EVEX_0F69,
1325   PREFIX_EVEX_0F6A,
1326   PREFIX_EVEX_0F6B,
1327   PREFIX_EVEX_0F6C,
1328   PREFIX_EVEX_0F6D,
1329   PREFIX_EVEX_0F6E,
1330   PREFIX_EVEX_0F6F,
1331   PREFIX_EVEX_0F70,
1332   PREFIX_EVEX_0F71_REG_2,
1333   PREFIX_EVEX_0F71_REG_4,
1334   PREFIX_EVEX_0F71_REG_6,
1335   PREFIX_EVEX_0F72_REG_0,
1336   PREFIX_EVEX_0F72_REG_1,
1337   PREFIX_EVEX_0F72_REG_2,
1338   PREFIX_EVEX_0F72_REG_4,
1339   PREFIX_EVEX_0F72_REG_6,
1340   PREFIX_EVEX_0F73_REG_2,
1341   PREFIX_EVEX_0F73_REG_3,
1342   PREFIX_EVEX_0F73_REG_6,
1343   PREFIX_EVEX_0F73_REG_7,
1344   PREFIX_EVEX_0F74,
1345   PREFIX_EVEX_0F75,
1346   PREFIX_EVEX_0F76,
1347   PREFIX_EVEX_0F78,
1348   PREFIX_EVEX_0F79,
1349   PREFIX_EVEX_0F7A,
1350   PREFIX_EVEX_0F7B,
1351   PREFIX_EVEX_0F7E,
1352   PREFIX_EVEX_0F7F,
1353   PREFIX_EVEX_0FC2,
1354   PREFIX_EVEX_0FC4,
1355   PREFIX_EVEX_0FC5,
1356   PREFIX_EVEX_0FC6,
1357   PREFIX_EVEX_0FD1,
1358   PREFIX_EVEX_0FD2,
1359   PREFIX_EVEX_0FD3,
1360   PREFIX_EVEX_0FD4,
1361   PREFIX_EVEX_0FD5,
1362   PREFIX_EVEX_0FD6,
1363   PREFIX_EVEX_0FD8,
1364   PREFIX_EVEX_0FD9,
1365   PREFIX_EVEX_0FDA,
1366   PREFIX_EVEX_0FDB,
1367   PREFIX_EVEX_0FDC,
1368   PREFIX_EVEX_0FDD,
1369   PREFIX_EVEX_0FDE,
1370   PREFIX_EVEX_0FDF,
1371   PREFIX_EVEX_0FE0,
1372   PREFIX_EVEX_0FE1,
1373   PREFIX_EVEX_0FE2,
1374   PREFIX_EVEX_0FE3,
1375   PREFIX_EVEX_0FE4,
1376   PREFIX_EVEX_0FE5,
1377   PREFIX_EVEX_0FE6,
1378   PREFIX_EVEX_0FE7,
1379   PREFIX_EVEX_0FE8,
1380   PREFIX_EVEX_0FE9,
1381   PREFIX_EVEX_0FEA,
1382   PREFIX_EVEX_0FEB,
1383   PREFIX_EVEX_0FEC,
1384   PREFIX_EVEX_0FED,
1385   PREFIX_EVEX_0FEE,
1386   PREFIX_EVEX_0FEF,
1387   PREFIX_EVEX_0FF1,
1388   PREFIX_EVEX_0FF2,
1389   PREFIX_EVEX_0FF3,
1390   PREFIX_EVEX_0FF4,
1391   PREFIX_EVEX_0FF5,
1392   PREFIX_EVEX_0FF6,
1393   PREFIX_EVEX_0FF8,
1394   PREFIX_EVEX_0FF9,
1395   PREFIX_EVEX_0FFA,
1396   PREFIX_EVEX_0FFB,
1397   PREFIX_EVEX_0FFC,
1398   PREFIX_EVEX_0FFD,
1399   PREFIX_EVEX_0FFE,
1400   PREFIX_EVEX_0F3800,
1401   PREFIX_EVEX_0F3804,
1402   PREFIX_EVEX_0F380B,
1403   PREFIX_EVEX_0F380C,
1404   PREFIX_EVEX_0F380D,
1405   PREFIX_EVEX_0F3810,
1406   PREFIX_EVEX_0F3811,
1407   PREFIX_EVEX_0F3812,
1408   PREFIX_EVEX_0F3813,
1409   PREFIX_EVEX_0F3814,
1410   PREFIX_EVEX_0F3815,
1411   PREFIX_EVEX_0F3816,
1412   PREFIX_EVEX_0F3818,
1413   PREFIX_EVEX_0F3819,
1414   PREFIX_EVEX_0F381A,
1415   PREFIX_EVEX_0F381B,
1416   PREFIX_EVEX_0F381C,
1417   PREFIX_EVEX_0F381D,
1418   PREFIX_EVEX_0F381E,
1419   PREFIX_EVEX_0F381F,
1420   PREFIX_EVEX_0F3820,
1421   PREFIX_EVEX_0F3821,
1422   PREFIX_EVEX_0F3822,
1423   PREFIX_EVEX_0F3823,
1424   PREFIX_EVEX_0F3824,
1425   PREFIX_EVEX_0F3825,
1426   PREFIX_EVEX_0F3826,
1427   PREFIX_EVEX_0F3827,
1428   PREFIX_EVEX_0F3828,
1429   PREFIX_EVEX_0F3829,
1430   PREFIX_EVEX_0F382A,
1431   PREFIX_EVEX_0F382B,
1432   PREFIX_EVEX_0F382C,
1433   PREFIX_EVEX_0F382D,
1434   PREFIX_EVEX_0F3830,
1435   PREFIX_EVEX_0F3831,
1436   PREFIX_EVEX_0F3832,
1437   PREFIX_EVEX_0F3833,
1438   PREFIX_EVEX_0F3834,
1439   PREFIX_EVEX_0F3835,
1440   PREFIX_EVEX_0F3836,
1441   PREFIX_EVEX_0F3837,
1442   PREFIX_EVEX_0F3838,
1443   PREFIX_EVEX_0F3839,
1444   PREFIX_EVEX_0F383A,
1445   PREFIX_EVEX_0F383B,
1446   PREFIX_EVEX_0F383C,
1447   PREFIX_EVEX_0F383D,
1448   PREFIX_EVEX_0F383E,
1449   PREFIX_EVEX_0F383F,
1450   PREFIX_EVEX_0F3840,
1451   PREFIX_EVEX_0F3842,
1452   PREFIX_EVEX_0F3843,
1453   PREFIX_EVEX_0F3844,
1454   PREFIX_EVEX_0F3845,
1455   PREFIX_EVEX_0F3846,
1456   PREFIX_EVEX_0F3847,
1457   PREFIX_EVEX_0F384C,
1458   PREFIX_EVEX_0F384D,
1459   PREFIX_EVEX_0F384E,
1460   PREFIX_EVEX_0F384F,
1461   PREFIX_EVEX_0F3858,
1462   PREFIX_EVEX_0F3859,
1463   PREFIX_EVEX_0F385A,
1464   PREFIX_EVEX_0F385B,
1465   PREFIX_EVEX_0F3864,
1466   PREFIX_EVEX_0F3865,
1467   PREFIX_EVEX_0F3866,
1468   PREFIX_EVEX_0F3875,
1469   PREFIX_EVEX_0F3876,
1470   PREFIX_EVEX_0F3877,
1471   PREFIX_EVEX_0F3878,
1472   PREFIX_EVEX_0F3879,
1473   PREFIX_EVEX_0F387A,
1474   PREFIX_EVEX_0F387B,
1475   PREFIX_EVEX_0F387C,
1476   PREFIX_EVEX_0F387D,
1477   PREFIX_EVEX_0F387E,
1478   PREFIX_EVEX_0F387F,
1479   PREFIX_EVEX_0F3888,
1480   PREFIX_EVEX_0F3889,
1481   PREFIX_EVEX_0F388A,
1482   PREFIX_EVEX_0F388B,
1483   PREFIX_EVEX_0F388D,
1484   PREFIX_EVEX_0F3890,
1485   PREFIX_EVEX_0F3891,
1486   PREFIX_EVEX_0F3892,
1487   PREFIX_EVEX_0F3893,
1488   PREFIX_EVEX_0F3896,
1489   PREFIX_EVEX_0F3897,
1490   PREFIX_EVEX_0F3898,
1491   PREFIX_EVEX_0F3899,
1492   PREFIX_EVEX_0F389A,
1493   PREFIX_EVEX_0F389B,
1494   PREFIX_EVEX_0F389C,
1495   PREFIX_EVEX_0F389D,
1496   PREFIX_EVEX_0F389E,
1497   PREFIX_EVEX_0F389F,
1498   PREFIX_EVEX_0F38A0,
1499   PREFIX_EVEX_0F38A1,
1500   PREFIX_EVEX_0F38A2,
1501   PREFIX_EVEX_0F38A3,
1502   PREFIX_EVEX_0F38A6,
1503   PREFIX_EVEX_0F38A7,
1504   PREFIX_EVEX_0F38A8,
1505   PREFIX_EVEX_0F38A9,
1506   PREFIX_EVEX_0F38AA,
1507   PREFIX_EVEX_0F38AB,
1508   PREFIX_EVEX_0F38AC,
1509   PREFIX_EVEX_0F38AD,
1510   PREFIX_EVEX_0F38AE,
1511   PREFIX_EVEX_0F38AF,
1512   PREFIX_EVEX_0F38B6,
1513   PREFIX_EVEX_0F38B7,
1514   PREFIX_EVEX_0F38B8,
1515   PREFIX_EVEX_0F38B9,
1516   PREFIX_EVEX_0F38BA,
1517   PREFIX_EVEX_0F38BB,
1518   PREFIX_EVEX_0F38BC,
1519   PREFIX_EVEX_0F38BD,
1520   PREFIX_EVEX_0F38BE,
1521   PREFIX_EVEX_0F38BF,
1522   PREFIX_EVEX_0F38C4,
1523   PREFIX_EVEX_0F38C6_REG_1,
1524   PREFIX_EVEX_0F38C6_REG_2,
1525   PREFIX_EVEX_0F38C6_REG_5,
1526   PREFIX_EVEX_0F38C6_REG_6,
1527   PREFIX_EVEX_0F38C7_REG_1,
1528   PREFIX_EVEX_0F38C7_REG_2,
1529   PREFIX_EVEX_0F38C7_REG_5,
1530   PREFIX_EVEX_0F38C7_REG_6,
1531   PREFIX_EVEX_0F38C8,
1532   PREFIX_EVEX_0F38CA,
1533   PREFIX_EVEX_0F38CB,
1534   PREFIX_EVEX_0F38CC,
1535   PREFIX_EVEX_0F38CD,
1536
1537   PREFIX_EVEX_0F3A00,
1538   PREFIX_EVEX_0F3A01,
1539   PREFIX_EVEX_0F3A03,
1540   PREFIX_EVEX_0F3A04,
1541   PREFIX_EVEX_0F3A05,
1542   PREFIX_EVEX_0F3A08,
1543   PREFIX_EVEX_0F3A09,
1544   PREFIX_EVEX_0F3A0A,
1545   PREFIX_EVEX_0F3A0B,
1546   PREFIX_EVEX_0F3A0F,
1547   PREFIX_EVEX_0F3A14,
1548   PREFIX_EVEX_0F3A15,
1549   PREFIX_EVEX_0F3A17,
1550   PREFIX_EVEX_0F3A18,
1551   PREFIX_EVEX_0F3A19,
1552   PREFIX_EVEX_0F3A1A,
1553   PREFIX_EVEX_0F3A1B,
1554   PREFIX_EVEX_0F3A1D,
1555   PREFIX_EVEX_0F3A1E,
1556   PREFIX_EVEX_0F3A1F,
1557   PREFIX_EVEX_0F3A20,
1558   PREFIX_EVEX_0F3A21,
1559   PREFIX_EVEX_0F3A23,
1560   PREFIX_EVEX_0F3A25,
1561   PREFIX_EVEX_0F3A26,
1562   PREFIX_EVEX_0F3A27,
1563   PREFIX_EVEX_0F3A38,
1564   PREFIX_EVEX_0F3A39,
1565   PREFIX_EVEX_0F3A3A,
1566   PREFIX_EVEX_0F3A3B,
1567   PREFIX_EVEX_0F3A3E,
1568   PREFIX_EVEX_0F3A3F,
1569   PREFIX_EVEX_0F3A42,
1570   PREFIX_EVEX_0F3A43,
1571   PREFIX_EVEX_0F3A54,
1572   PREFIX_EVEX_0F3A55
1573 };
1574
1575 enum
1576 {
1577   X86_64_06 = 0,
1578   X86_64_07,
1579   X86_64_0D,
1580   X86_64_16,
1581   X86_64_17,
1582   X86_64_1E,
1583   X86_64_1F,
1584   X86_64_27,
1585   X86_64_2F,
1586   X86_64_37,
1587   X86_64_3F,
1588   X86_64_60,
1589   X86_64_61,
1590   X86_64_62,
1591   X86_64_63,
1592   X86_64_6D,
1593   X86_64_6F,
1594   X86_64_9A,
1595   X86_64_C4,
1596   X86_64_C5,
1597   X86_64_CE,
1598   X86_64_D4,
1599   X86_64_D5,
1600   X86_64_EA,
1601   X86_64_0F01_REG_0,
1602   X86_64_0F01_REG_1,
1603   X86_64_0F01_REG_2,
1604   X86_64_0F01_REG_3
1605 };
1606
1607 enum
1608 {
1609   THREE_BYTE_0F38 = 0,
1610   THREE_BYTE_0F3A,
1611   THREE_BYTE_0F7A
1612 };
1613
1614 enum
1615 {
1616   XOP_08 = 0,
1617   XOP_09,
1618   XOP_0A
1619 };
1620
1621 enum
1622 {
1623   VEX_0F = 0,
1624   VEX_0F38,
1625   VEX_0F3A
1626 };
1627
1628 enum
1629 {
1630   EVEX_0F = 0,
1631   EVEX_0F38,
1632   EVEX_0F3A
1633 };
1634
1635 enum
1636 {
1637   VEX_LEN_0F10_P_1 = 0,
1638   VEX_LEN_0F10_P_3,
1639   VEX_LEN_0F11_P_1,
1640   VEX_LEN_0F11_P_3,
1641   VEX_LEN_0F12_P_0_M_0,
1642   VEX_LEN_0F12_P_0_M_1,
1643   VEX_LEN_0F12_P_2,
1644   VEX_LEN_0F13_M_0,
1645   VEX_LEN_0F16_P_0_M_0,
1646   VEX_LEN_0F16_P_0_M_1,
1647   VEX_LEN_0F16_P_2,
1648   VEX_LEN_0F17_M_0,
1649   VEX_LEN_0F2A_P_1,
1650   VEX_LEN_0F2A_P_3,
1651   VEX_LEN_0F2C_P_1,
1652   VEX_LEN_0F2C_P_3,
1653   VEX_LEN_0F2D_P_1,
1654   VEX_LEN_0F2D_P_3,
1655   VEX_LEN_0F2E_P_0,
1656   VEX_LEN_0F2E_P_2,
1657   VEX_LEN_0F2F_P_0,
1658   VEX_LEN_0F2F_P_2,
1659   VEX_LEN_0F41_P_0,
1660   VEX_LEN_0F41_P_2,
1661   VEX_LEN_0F42_P_0,
1662   VEX_LEN_0F42_P_2,
1663   VEX_LEN_0F44_P_0,
1664   VEX_LEN_0F44_P_2,
1665   VEX_LEN_0F45_P_0,
1666   VEX_LEN_0F45_P_2,
1667   VEX_LEN_0F46_P_0,
1668   VEX_LEN_0F46_P_2,
1669   VEX_LEN_0F47_P_0,
1670   VEX_LEN_0F47_P_2,
1671   VEX_LEN_0F4A_P_0,
1672   VEX_LEN_0F4A_P_2,
1673   VEX_LEN_0F4B_P_0,
1674   VEX_LEN_0F4B_P_2,
1675   VEX_LEN_0F51_P_1,
1676   VEX_LEN_0F51_P_3,
1677   VEX_LEN_0F52_P_1,
1678   VEX_LEN_0F53_P_1,
1679   VEX_LEN_0F58_P_1,
1680   VEX_LEN_0F58_P_3,
1681   VEX_LEN_0F59_P_1,
1682   VEX_LEN_0F59_P_3,
1683   VEX_LEN_0F5A_P_1,
1684   VEX_LEN_0F5A_P_3,
1685   VEX_LEN_0F5C_P_1,
1686   VEX_LEN_0F5C_P_3,
1687   VEX_LEN_0F5D_P_1,
1688   VEX_LEN_0F5D_P_3,
1689   VEX_LEN_0F5E_P_1,
1690   VEX_LEN_0F5E_P_3,
1691   VEX_LEN_0F5F_P_1,
1692   VEX_LEN_0F5F_P_3,
1693   VEX_LEN_0F6E_P_2,
1694   VEX_LEN_0F7E_P_1,
1695   VEX_LEN_0F7E_P_2,
1696   VEX_LEN_0F90_P_0,
1697   VEX_LEN_0F90_P_2,
1698   VEX_LEN_0F91_P_0,
1699   VEX_LEN_0F91_P_2,
1700   VEX_LEN_0F92_P_0,
1701   VEX_LEN_0F92_P_3,
1702   VEX_LEN_0F93_P_0,
1703   VEX_LEN_0F93_P_3,
1704   VEX_LEN_0F98_P_0,
1705   VEX_LEN_0F98_P_2,
1706   VEX_LEN_0F99_P_0,
1707   VEX_LEN_0F99_P_2,
1708   VEX_LEN_0FAE_R_2_M_0,
1709   VEX_LEN_0FAE_R_3_M_0,
1710   VEX_LEN_0FC2_P_1,
1711   VEX_LEN_0FC2_P_3,
1712   VEX_LEN_0FC4_P_2,
1713   VEX_LEN_0FC5_P_2,
1714   VEX_LEN_0FD6_P_2,
1715   VEX_LEN_0FF7_P_2,
1716   VEX_LEN_0F3816_P_2,
1717   VEX_LEN_0F3819_P_2,
1718   VEX_LEN_0F381A_P_2_M_0,
1719   VEX_LEN_0F3836_P_2,
1720   VEX_LEN_0F3841_P_2,
1721   VEX_LEN_0F385A_P_2_M_0,
1722   VEX_LEN_0F38DB_P_2,
1723   VEX_LEN_0F38DC_P_2,
1724   VEX_LEN_0F38DD_P_2,
1725   VEX_LEN_0F38DE_P_2,
1726   VEX_LEN_0F38DF_P_2,
1727   VEX_LEN_0F38F2_P_0,
1728   VEX_LEN_0F38F3_R_1_P_0,
1729   VEX_LEN_0F38F3_R_2_P_0,
1730   VEX_LEN_0F38F3_R_3_P_0,
1731   VEX_LEN_0F38F5_P_0,
1732   VEX_LEN_0F38F5_P_1,
1733   VEX_LEN_0F38F5_P_3,
1734   VEX_LEN_0F38F6_P_3,
1735   VEX_LEN_0F38F7_P_0,
1736   VEX_LEN_0F38F7_P_1,
1737   VEX_LEN_0F38F7_P_2,
1738   VEX_LEN_0F38F7_P_3,
1739   VEX_LEN_0F3A00_P_2,
1740   VEX_LEN_0F3A01_P_2,
1741   VEX_LEN_0F3A06_P_2,
1742   VEX_LEN_0F3A0A_P_2,
1743   VEX_LEN_0F3A0B_P_2,
1744   VEX_LEN_0F3A14_P_2,
1745   VEX_LEN_0F3A15_P_2,
1746   VEX_LEN_0F3A16_P_2,
1747   VEX_LEN_0F3A17_P_2,
1748   VEX_LEN_0F3A18_P_2,
1749   VEX_LEN_0F3A19_P_2,
1750   VEX_LEN_0F3A20_P_2,
1751   VEX_LEN_0F3A21_P_2,
1752   VEX_LEN_0F3A22_P_2,
1753   VEX_LEN_0F3A30_P_2,
1754   VEX_LEN_0F3A31_P_2,
1755   VEX_LEN_0F3A32_P_2,
1756   VEX_LEN_0F3A33_P_2,
1757   VEX_LEN_0F3A38_P_2,
1758   VEX_LEN_0F3A39_P_2,
1759   VEX_LEN_0F3A41_P_2,
1760   VEX_LEN_0F3A44_P_2,
1761   VEX_LEN_0F3A46_P_2,
1762   VEX_LEN_0F3A60_P_2,
1763   VEX_LEN_0F3A61_P_2,
1764   VEX_LEN_0F3A62_P_2,
1765   VEX_LEN_0F3A63_P_2,
1766   VEX_LEN_0F3A6A_P_2,
1767   VEX_LEN_0F3A6B_P_2,
1768   VEX_LEN_0F3A6E_P_2,
1769   VEX_LEN_0F3A6F_P_2,
1770   VEX_LEN_0F3A7A_P_2,
1771   VEX_LEN_0F3A7B_P_2,
1772   VEX_LEN_0F3A7E_P_2,
1773   VEX_LEN_0F3A7F_P_2,
1774   VEX_LEN_0F3ADF_P_2,
1775   VEX_LEN_0F3AF0_P_3,
1776   VEX_LEN_0FXOP_08_CC,
1777   VEX_LEN_0FXOP_08_CD,
1778   VEX_LEN_0FXOP_08_CE,
1779   VEX_LEN_0FXOP_08_CF,
1780   VEX_LEN_0FXOP_08_EC,
1781   VEX_LEN_0FXOP_08_ED,
1782   VEX_LEN_0FXOP_08_EE,
1783   VEX_LEN_0FXOP_08_EF,
1784   VEX_LEN_0FXOP_09_80,
1785   VEX_LEN_0FXOP_09_81
1786 };
1787
1788 enum
1789 {
1790   VEX_W_0F10_P_0 = 0,
1791   VEX_W_0F10_P_1,
1792   VEX_W_0F10_P_2,
1793   VEX_W_0F10_P_3,
1794   VEX_W_0F11_P_0,
1795   VEX_W_0F11_P_1,
1796   VEX_W_0F11_P_2,
1797   VEX_W_0F11_P_3,
1798   VEX_W_0F12_P_0_M_0,
1799   VEX_W_0F12_P_0_M_1,
1800   VEX_W_0F12_P_1,
1801   VEX_W_0F12_P_2,
1802   VEX_W_0F12_P_3,
1803   VEX_W_0F13_M_0,
1804   VEX_W_0F14,
1805   VEX_W_0F15,
1806   VEX_W_0F16_P_0_M_0,
1807   VEX_W_0F16_P_0_M_1,
1808   VEX_W_0F16_P_1,
1809   VEX_W_0F16_P_2,
1810   VEX_W_0F17_M_0,
1811   VEX_W_0F28,
1812   VEX_W_0F29,
1813   VEX_W_0F2B_M_0,
1814   VEX_W_0F2E_P_0,
1815   VEX_W_0F2E_P_2,
1816   VEX_W_0F2F_P_0,
1817   VEX_W_0F2F_P_2,
1818   VEX_W_0F41_P_0_LEN_1,
1819   VEX_W_0F41_P_2_LEN_1,
1820   VEX_W_0F42_P_0_LEN_1,
1821   VEX_W_0F42_P_2_LEN_1,
1822   VEX_W_0F44_P_0_LEN_0,
1823   VEX_W_0F44_P_2_LEN_0,
1824   VEX_W_0F45_P_0_LEN_1,
1825   VEX_W_0F45_P_2_LEN_1,
1826   VEX_W_0F46_P_0_LEN_1,
1827   VEX_W_0F46_P_2_LEN_1,
1828   VEX_W_0F47_P_0_LEN_1,
1829   VEX_W_0F47_P_2_LEN_1,
1830   VEX_W_0F4A_P_0_LEN_1,
1831   VEX_W_0F4A_P_2_LEN_1,
1832   VEX_W_0F4B_P_0_LEN_1,
1833   VEX_W_0F4B_P_2_LEN_1,
1834   VEX_W_0F50_M_0,
1835   VEX_W_0F51_P_0,
1836   VEX_W_0F51_P_1,
1837   VEX_W_0F51_P_2,
1838   VEX_W_0F51_P_3,
1839   VEX_W_0F52_P_0,
1840   VEX_W_0F52_P_1,
1841   VEX_W_0F53_P_0,
1842   VEX_W_0F53_P_1,
1843   VEX_W_0F58_P_0,
1844   VEX_W_0F58_P_1,
1845   VEX_W_0F58_P_2,
1846   VEX_W_0F58_P_3,
1847   VEX_W_0F59_P_0,
1848   VEX_W_0F59_P_1,
1849   VEX_W_0F59_P_2,
1850   VEX_W_0F59_P_3,
1851   VEX_W_0F5A_P_0,
1852   VEX_W_0F5A_P_1,
1853   VEX_W_0F5A_P_3,
1854   VEX_W_0F5B_P_0,
1855   VEX_W_0F5B_P_1,
1856   VEX_W_0F5B_P_2,
1857   VEX_W_0F5C_P_0,
1858   VEX_W_0F5C_P_1,
1859   VEX_W_0F5C_P_2,
1860   VEX_W_0F5C_P_3,
1861   VEX_W_0F5D_P_0,
1862   VEX_W_0F5D_P_1,
1863   VEX_W_0F5D_P_2,
1864   VEX_W_0F5D_P_3,
1865   VEX_W_0F5E_P_0,
1866   VEX_W_0F5E_P_1,
1867   VEX_W_0F5E_P_2,
1868   VEX_W_0F5E_P_3,
1869   VEX_W_0F5F_P_0,
1870   VEX_W_0F5F_P_1,
1871   VEX_W_0F5F_P_2,
1872   VEX_W_0F5F_P_3,
1873   VEX_W_0F60_P_2,
1874   VEX_W_0F61_P_2,
1875   VEX_W_0F62_P_2,
1876   VEX_W_0F63_P_2,
1877   VEX_W_0F64_P_2,
1878   VEX_W_0F65_P_2,
1879   VEX_W_0F66_P_2,
1880   VEX_W_0F67_P_2,
1881   VEX_W_0F68_P_2,
1882   VEX_W_0F69_P_2,
1883   VEX_W_0F6A_P_2,
1884   VEX_W_0F6B_P_2,
1885   VEX_W_0F6C_P_2,
1886   VEX_W_0F6D_P_2,
1887   VEX_W_0F6F_P_1,
1888   VEX_W_0F6F_P_2,
1889   VEX_W_0F70_P_1,
1890   VEX_W_0F70_P_2,
1891   VEX_W_0F70_P_3,
1892   VEX_W_0F71_R_2_P_2,
1893   VEX_W_0F71_R_4_P_2,
1894   VEX_W_0F71_R_6_P_2,
1895   VEX_W_0F72_R_2_P_2,
1896   VEX_W_0F72_R_4_P_2,
1897   VEX_W_0F72_R_6_P_2,
1898   VEX_W_0F73_R_2_P_2,
1899   VEX_W_0F73_R_3_P_2,
1900   VEX_W_0F73_R_6_P_2,
1901   VEX_W_0F73_R_7_P_2,
1902   VEX_W_0F74_P_2,
1903   VEX_W_0F75_P_2,
1904   VEX_W_0F76_P_2,
1905   VEX_W_0F77_P_0,
1906   VEX_W_0F7C_P_2,
1907   VEX_W_0F7C_P_3,
1908   VEX_W_0F7D_P_2,
1909   VEX_W_0F7D_P_3,
1910   VEX_W_0F7E_P_1,
1911   VEX_W_0F7F_P_1,
1912   VEX_W_0F7F_P_2,
1913   VEX_W_0F90_P_0_LEN_0,
1914   VEX_W_0F90_P_2_LEN_0,
1915   VEX_W_0F91_P_0_LEN_0,
1916   VEX_W_0F91_P_2_LEN_0,
1917   VEX_W_0F92_P_0_LEN_0,
1918   VEX_W_0F92_P_3_LEN_0,
1919   VEX_W_0F93_P_0_LEN_0,
1920   VEX_W_0F93_P_3_LEN_0,
1921   VEX_W_0F98_P_0_LEN_0,
1922   VEX_W_0F98_P_2_LEN_0,
1923   VEX_W_0F99_P_0_LEN_0,
1924   VEX_W_0F99_P_2_LEN_0,
1925   VEX_W_0FAE_R_2_M_0,
1926   VEX_W_0FAE_R_3_M_0,
1927   VEX_W_0FC2_P_0,
1928   VEX_W_0FC2_P_1,
1929   VEX_W_0FC2_P_2,
1930   VEX_W_0FC2_P_3,
1931   VEX_W_0FC4_P_2,
1932   VEX_W_0FC5_P_2,
1933   VEX_W_0FD0_P_2,
1934   VEX_W_0FD0_P_3,
1935   VEX_W_0FD1_P_2,
1936   VEX_W_0FD2_P_2,
1937   VEX_W_0FD3_P_2,
1938   VEX_W_0FD4_P_2,
1939   VEX_W_0FD5_P_2,
1940   VEX_W_0FD6_P_2,
1941   VEX_W_0FD7_P_2_M_1,
1942   VEX_W_0FD8_P_2,
1943   VEX_W_0FD9_P_2,
1944   VEX_W_0FDA_P_2,
1945   VEX_W_0FDB_P_2,
1946   VEX_W_0FDC_P_2,
1947   VEX_W_0FDD_P_2,
1948   VEX_W_0FDE_P_2,
1949   VEX_W_0FDF_P_2,
1950   VEX_W_0FE0_P_2,
1951   VEX_W_0FE1_P_2,
1952   VEX_W_0FE2_P_2,
1953   VEX_W_0FE3_P_2,
1954   VEX_W_0FE4_P_2,
1955   VEX_W_0FE5_P_2,
1956   VEX_W_0FE6_P_1,
1957   VEX_W_0FE6_P_2,
1958   VEX_W_0FE6_P_3,
1959   VEX_W_0FE7_P_2_M_0,
1960   VEX_W_0FE8_P_2,
1961   VEX_W_0FE9_P_2,
1962   VEX_W_0FEA_P_2,
1963   VEX_W_0FEB_P_2,
1964   VEX_W_0FEC_P_2,
1965   VEX_W_0FED_P_2,
1966   VEX_W_0FEE_P_2,
1967   VEX_W_0FEF_P_2,
1968   VEX_W_0FF0_P_3_M_0,
1969   VEX_W_0FF1_P_2,
1970   VEX_W_0FF2_P_2,
1971   VEX_W_0FF3_P_2,
1972   VEX_W_0FF4_P_2,
1973   VEX_W_0FF5_P_2,
1974   VEX_W_0FF6_P_2,
1975   VEX_W_0FF7_P_2,
1976   VEX_W_0FF8_P_2,
1977   VEX_W_0FF9_P_2,
1978   VEX_W_0FFA_P_2,
1979   VEX_W_0FFB_P_2,
1980   VEX_W_0FFC_P_2,
1981   VEX_W_0FFD_P_2,
1982   VEX_W_0FFE_P_2,
1983   VEX_W_0F3800_P_2,
1984   VEX_W_0F3801_P_2,
1985   VEX_W_0F3802_P_2,
1986   VEX_W_0F3803_P_2,
1987   VEX_W_0F3804_P_2,
1988   VEX_W_0F3805_P_2,
1989   VEX_W_0F3806_P_2,
1990   VEX_W_0F3807_P_2,
1991   VEX_W_0F3808_P_2,
1992   VEX_W_0F3809_P_2,
1993   VEX_W_0F380A_P_2,
1994   VEX_W_0F380B_P_2,
1995   VEX_W_0F380C_P_2,
1996   VEX_W_0F380D_P_2,
1997   VEX_W_0F380E_P_2,
1998   VEX_W_0F380F_P_2,
1999   VEX_W_0F3816_P_2,
2000   VEX_W_0F3817_P_2,
2001   VEX_W_0F3818_P_2,
2002   VEX_W_0F3819_P_2,
2003   VEX_W_0F381A_P_2_M_0,
2004   VEX_W_0F381C_P_2,
2005   VEX_W_0F381D_P_2,
2006   VEX_W_0F381E_P_2,
2007   VEX_W_0F3820_P_2,
2008   VEX_W_0F3821_P_2,
2009   VEX_W_0F3822_P_2,
2010   VEX_W_0F3823_P_2,
2011   VEX_W_0F3824_P_2,
2012   VEX_W_0F3825_P_2,
2013   VEX_W_0F3828_P_2,
2014   VEX_W_0F3829_P_2,
2015   VEX_W_0F382A_P_2_M_0,
2016   VEX_W_0F382B_P_2,
2017   VEX_W_0F382C_P_2_M_0,
2018   VEX_W_0F382D_P_2_M_0,
2019   VEX_W_0F382E_P_2_M_0,
2020   VEX_W_0F382F_P_2_M_0,
2021   VEX_W_0F3830_P_2,
2022   VEX_W_0F3831_P_2,
2023   VEX_W_0F3832_P_2,
2024   VEX_W_0F3833_P_2,
2025   VEX_W_0F3834_P_2,
2026   VEX_W_0F3835_P_2,
2027   VEX_W_0F3836_P_2,
2028   VEX_W_0F3837_P_2,
2029   VEX_W_0F3838_P_2,
2030   VEX_W_0F3839_P_2,
2031   VEX_W_0F383A_P_2,
2032   VEX_W_0F383B_P_2,
2033   VEX_W_0F383C_P_2,
2034   VEX_W_0F383D_P_2,
2035   VEX_W_0F383E_P_2,
2036   VEX_W_0F383F_P_2,
2037   VEX_W_0F3840_P_2,
2038   VEX_W_0F3841_P_2,
2039   VEX_W_0F3846_P_2,
2040   VEX_W_0F3858_P_2,
2041   VEX_W_0F3859_P_2,
2042   VEX_W_0F385A_P_2_M_0,
2043   VEX_W_0F3878_P_2,
2044   VEX_W_0F3879_P_2,
2045   VEX_W_0F38DB_P_2,
2046   VEX_W_0F38DC_P_2,
2047   VEX_W_0F38DD_P_2,
2048   VEX_W_0F38DE_P_2,
2049   VEX_W_0F38DF_P_2,
2050   VEX_W_0F3A00_P_2,
2051   VEX_W_0F3A01_P_2,
2052   VEX_W_0F3A02_P_2,
2053   VEX_W_0F3A04_P_2,
2054   VEX_W_0F3A05_P_2,
2055   VEX_W_0F3A06_P_2,
2056   VEX_W_0F3A08_P_2,
2057   VEX_W_0F3A09_P_2,
2058   VEX_W_0F3A0A_P_2,
2059   VEX_W_0F3A0B_P_2,
2060   VEX_W_0F3A0C_P_2,
2061   VEX_W_0F3A0D_P_2,
2062   VEX_W_0F3A0E_P_2,
2063   VEX_W_0F3A0F_P_2,
2064   VEX_W_0F3A14_P_2,
2065   VEX_W_0F3A15_P_2,
2066   VEX_W_0F3A18_P_2,
2067   VEX_W_0F3A19_P_2,
2068   VEX_W_0F3A20_P_2,
2069   VEX_W_0F3A21_P_2,
2070   VEX_W_0F3A30_P_2_LEN_0,
2071   VEX_W_0F3A31_P_2_LEN_0,
2072   VEX_W_0F3A32_P_2_LEN_0,
2073   VEX_W_0F3A33_P_2_LEN_0,
2074   VEX_W_0F3A38_P_2,
2075   VEX_W_0F3A39_P_2,
2076   VEX_W_0F3A40_P_2,
2077   VEX_W_0F3A41_P_2,
2078   VEX_W_0F3A42_P_2,
2079   VEX_W_0F3A44_P_2,
2080   VEX_W_0F3A46_P_2,
2081   VEX_W_0F3A48_P_2,
2082   VEX_W_0F3A49_P_2,
2083   VEX_W_0F3A4A_P_2,
2084   VEX_W_0F3A4B_P_2,
2085   VEX_W_0F3A4C_P_2,
2086   VEX_W_0F3A60_P_2,
2087   VEX_W_0F3A61_P_2,
2088   VEX_W_0F3A62_P_2,
2089   VEX_W_0F3A63_P_2,
2090   VEX_W_0F3ADF_P_2,
2091
2092   EVEX_W_0F10_P_0,
2093   EVEX_W_0F10_P_1_M_0,
2094   EVEX_W_0F10_P_1_M_1,
2095   EVEX_W_0F10_P_2,
2096   EVEX_W_0F10_P_3_M_0,
2097   EVEX_W_0F10_P_3_M_1,
2098   EVEX_W_0F11_P_0,
2099   EVEX_W_0F11_P_1_M_0,
2100   EVEX_W_0F11_P_1_M_1,
2101   EVEX_W_0F11_P_2,
2102   EVEX_W_0F11_P_3_M_0,
2103   EVEX_W_0F11_P_3_M_1,
2104   EVEX_W_0F12_P_0_M_0,
2105   EVEX_W_0F12_P_0_M_1,
2106   EVEX_W_0F12_P_1,
2107   EVEX_W_0F12_P_2,
2108   EVEX_W_0F12_P_3,
2109   EVEX_W_0F13_P_0,
2110   EVEX_W_0F13_P_2,
2111   EVEX_W_0F14_P_0,
2112   EVEX_W_0F14_P_2,
2113   EVEX_W_0F15_P_0,
2114   EVEX_W_0F15_P_2,
2115   EVEX_W_0F16_P_0_M_0,
2116   EVEX_W_0F16_P_0_M_1,
2117   EVEX_W_0F16_P_1,
2118   EVEX_W_0F16_P_2,
2119   EVEX_W_0F17_P_0,
2120   EVEX_W_0F17_P_2,
2121   EVEX_W_0F28_P_0,
2122   EVEX_W_0F28_P_2,
2123   EVEX_W_0F29_P_0,
2124   EVEX_W_0F29_P_2,
2125   EVEX_W_0F2A_P_1,
2126   EVEX_W_0F2A_P_3,
2127   EVEX_W_0F2B_P_0,
2128   EVEX_W_0F2B_P_2,
2129   EVEX_W_0F2E_P_0,
2130   EVEX_W_0F2E_P_2,
2131   EVEX_W_0F2F_P_0,
2132   EVEX_W_0F2F_P_2,
2133   EVEX_W_0F51_P_0,
2134   EVEX_W_0F51_P_1,
2135   EVEX_W_0F51_P_2,
2136   EVEX_W_0F51_P_3,
2137   EVEX_W_0F58_P_0,
2138   EVEX_W_0F58_P_1,
2139   EVEX_W_0F58_P_2,
2140   EVEX_W_0F58_P_3,
2141   EVEX_W_0F59_P_0,
2142   EVEX_W_0F59_P_1,
2143   EVEX_W_0F59_P_2,
2144   EVEX_W_0F59_P_3,
2145   EVEX_W_0F5A_P_0,
2146   EVEX_W_0F5A_P_1,
2147   EVEX_W_0F5A_P_2,
2148   EVEX_W_0F5A_P_3,
2149   EVEX_W_0F5B_P_0,
2150   EVEX_W_0F5B_P_1,
2151   EVEX_W_0F5B_P_2,
2152   EVEX_W_0F5C_P_0,
2153   EVEX_W_0F5C_P_1,
2154   EVEX_W_0F5C_P_2,
2155   EVEX_W_0F5C_P_3,
2156   EVEX_W_0F5D_P_0,
2157   EVEX_W_0F5D_P_1,
2158   EVEX_W_0F5D_P_2,
2159   EVEX_W_0F5D_P_3,
2160   EVEX_W_0F5E_P_0,
2161   EVEX_W_0F5E_P_1,
2162   EVEX_W_0F5E_P_2,
2163   EVEX_W_0F5E_P_3,
2164   EVEX_W_0F5F_P_0,
2165   EVEX_W_0F5F_P_1,
2166   EVEX_W_0F5F_P_2,
2167   EVEX_W_0F5F_P_3,
2168   EVEX_W_0F62_P_2,
2169   EVEX_W_0F66_P_2,
2170   EVEX_W_0F6A_P_2,
2171   EVEX_W_0F6B_P_2,
2172   EVEX_W_0F6C_P_2,
2173   EVEX_W_0F6D_P_2,
2174   EVEX_W_0F6E_P_2,
2175   EVEX_W_0F6F_P_1,
2176   EVEX_W_0F6F_P_2,
2177   EVEX_W_0F6F_P_3,
2178   EVEX_W_0F70_P_2,
2179   EVEX_W_0F72_R_2_P_2,
2180   EVEX_W_0F72_R_6_P_2,
2181   EVEX_W_0F73_R_2_P_2,
2182   EVEX_W_0F73_R_6_P_2,
2183   EVEX_W_0F76_P_2,
2184   EVEX_W_0F78_P_0,
2185   EVEX_W_0F79_P_0,
2186   EVEX_W_0F7A_P_1,
2187   EVEX_W_0F7A_P_3,
2188   EVEX_W_0F7B_P_1,
2189   EVEX_W_0F7B_P_3,
2190   EVEX_W_0F7E_P_1,
2191   EVEX_W_0F7E_P_2,
2192   EVEX_W_0F7F_P_1,
2193   EVEX_W_0F7F_P_2,
2194   EVEX_W_0F7F_P_3,
2195   EVEX_W_0FC2_P_0,
2196   EVEX_W_0FC2_P_1,
2197   EVEX_W_0FC2_P_2,
2198   EVEX_W_0FC2_P_3,
2199   EVEX_W_0FC6_P_0,
2200   EVEX_W_0FC6_P_2,
2201   EVEX_W_0FD2_P_2,
2202   EVEX_W_0FD3_P_2,
2203   EVEX_W_0FD4_P_2,
2204   EVEX_W_0FD6_P_2,
2205   EVEX_W_0FE6_P_1,
2206   EVEX_W_0FE6_P_2,
2207   EVEX_W_0FE6_P_3,
2208   EVEX_W_0FE7_P_2,
2209   EVEX_W_0FF2_P_2,
2210   EVEX_W_0FF3_P_2,
2211   EVEX_W_0FF4_P_2,
2212   EVEX_W_0FFA_P_2,
2213   EVEX_W_0FFB_P_2,
2214   EVEX_W_0FFE_P_2,
2215   EVEX_W_0F380C_P_2,
2216   EVEX_W_0F380D_P_2,
2217   EVEX_W_0F3810_P_1,
2218   EVEX_W_0F3810_P_2,
2219   EVEX_W_0F3811_P_1,
2220   EVEX_W_0F3811_P_2,
2221   EVEX_W_0F3812_P_1,
2222   EVEX_W_0F3812_P_2,
2223   EVEX_W_0F3813_P_1,
2224   EVEX_W_0F3813_P_2,
2225   EVEX_W_0F3814_P_1,
2226   EVEX_W_0F3815_P_1,
2227   EVEX_W_0F3818_P_2,
2228   EVEX_W_0F3819_P_2,
2229   EVEX_W_0F381A_P_2,
2230   EVEX_W_0F381B_P_2,
2231   EVEX_W_0F381E_P_2,
2232   EVEX_W_0F381F_P_2,
2233   EVEX_W_0F3820_P_1,
2234   EVEX_W_0F3821_P_1,
2235   EVEX_W_0F3822_P_1,
2236   EVEX_W_0F3823_P_1,
2237   EVEX_W_0F3824_P_1,
2238   EVEX_W_0F3825_P_1,
2239   EVEX_W_0F3825_P_2,
2240   EVEX_W_0F3826_P_1,
2241   EVEX_W_0F3826_P_2,
2242   EVEX_W_0F3828_P_1,
2243   EVEX_W_0F3828_P_2,
2244   EVEX_W_0F3829_P_1,
2245   EVEX_W_0F3829_P_2,
2246   EVEX_W_0F382A_P_1,
2247   EVEX_W_0F382A_P_2,
2248   EVEX_W_0F382B_P_2,
2249   EVEX_W_0F3830_P_1,
2250   EVEX_W_0F3831_P_1,
2251   EVEX_W_0F3832_P_1,
2252   EVEX_W_0F3833_P_1,
2253   EVEX_W_0F3834_P_1,
2254   EVEX_W_0F3835_P_1,
2255   EVEX_W_0F3835_P_2,
2256   EVEX_W_0F3837_P_2,
2257   EVEX_W_0F383A_P_1,
2258   EVEX_W_0F3840_P_2,
2259   EVEX_W_0F3858_P_2,
2260   EVEX_W_0F3859_P_2,
2261   EVEX_W_0F385A_P_2,
2262   EVEX_W_0F385B_P_2,
2263   EVEX_W_0F3866_P_2,
2264   EVEX_W_0F3875_P_2,
2265   EVEX_W_0F3878_P_2,
2266   EVEX_W_0F3879_P_2,
2267   EVEX_W_0F387A_P_2,
2268   EVEX_W_0F387B_P_2,
2269   EVEX_W_0F387D_P_2,
2270   EVEX_W_0F388D_P_2,
2271   EVEX_W_0F3891_P_2,
2272   EVEX_W_0F3893_P_2,
2273   EVEX_W_0F38A1_P_2,
2274   EVEX_W_0F38A3_P_2,
2275   EVEX_W_0F38C7_R_1_P_2,
2276   EVEX_W_0F38C7_R_2_P_2,
2277   EVEX_W_0F38C7_R_5_P_2,
2278   EVEX_W_0F38C7_R_6_P_2,
2279
2280   EVEX_W_0F3A00_P_2,
2281   EVEX_W_0F3A01_P_2,
2282   EVEX_W_0F3A04_P_2,
2283   EVEX_W_0F3A05_P_2,
2284   EVEX_W_0F3A08_P_2,
2285   EVEX_W_0F3A09_P_2,
2286   EVEX_W_0F3A0A_P_2,
2287   EVEX_W_0F3A0B_P_2,
2288   EVEX_W_0F3A18_P_2,
2289   EVEX_W_0F3A19_P_2,
2290   EVEX_W_0F3A1A_P_2,
2291   EVEX_W_0F3A1B_P_2,
2292   EVEX_W_0F3A1D_P_2,
2293   EVEX_W_0F3A21_P_2,
2294   EVEX_W_0F3A23_P_2,
2295   EVEX_W_0F3A38_P_2,
2296   EVEX_W_0F3A39_P_2,
2297   EVEX_W_0F3A3A_P_2,
2298   EVEX_W_0F3A3B_P_2,
2299   EVEX_W_0F3A3E_P_2,
2300   EVEX_W_0F3A3F_P_2,
2301   EVEX_W_0F3A42_P_2,
2302   EVEX_W_0F3A43_P_2
2303 };
2304
2305 typedef void (*op_rtn) (int bytemode, int sizeflag);
2306
2307 struct dis386 {
2308   const char *name;
2309   struct
2310     {
2311       op_rtn rtn;
2312       int bytemode;
2313     } op[MAX_OPERANDS];
2314 };
2315
2316 /* Upper case letters in the instruction names here are macros.
2317    'A' => print 'b' if no register operands or suffix_always is true
2318    'B' => print 'b' if suffix_always is true
2319    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2320           size prefix
2321    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2322           suffix_always is true
2323    'E' => print 'e' if 32-bit form of jcxz
2324    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2325    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2326    'H' => print ",pt" or ",pn" branch hint
2327    'I' => honor following macro letter even in Intel mode (implemented only
2328           for some of the macro letters)
2329    'J' => print 'l'
2330    'K' => print 'd' or 'q' if rex prefix is present.
2331    'L' => print 'l' if suffix_always is true
2332    'M' => print 'r' if intel_mnemonic is false.
2333    'N' => print 'n' if instruction has no wait "prefix"
2334    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2335    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2336           or suffix_always is true.  print 'q' if rex prefix is present.
2337    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2338           is true
2339    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2340    'S' => print 'w', 'l' or 'q' if suffix_always is true
2341    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2342    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2343    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2344    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2345    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2346    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2347           suffix_always is true.
2348    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2349    '!' => change condition from true to false or from false to true.
2350    '%' => add 1 upper case letter to the macro.
2351
2352    2 upper case letter macros:
2353    "XY" => print 'x' or 'y' if no register operands or suffix_always
2354            is true.
2355    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2356    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2357            or suffix_always is true
2358    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2359    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2360    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2361    "LW" => print 'd', 'q' depending on the VEX.W bit
2362
2363    Many of the above letters print nothing in Intel mode.  See "putop"
2364    for the details.
2365
2366    Braces '{' and '}', and vertical bars '|', indicate alternative
2367    mnemonic strings for AT&T and Intel.  */
2368
2369 static const struct dis386 dis386[] = {
2370   /* 00 */
2371   { "addB",             { Ebh1, Gb } },
2372   { "addS",             { Evh1, Gv } },
2373   { "addB",             { Gb, EbS } },
2374   { "addS",             { Gv, EvS } },
2375   { "addB",             { AL, Ib } },
2376   { "addS",             { eAX, Iv } },
2377   { X86_64_TABLE (X86_64_06) },
2378   { X86_64_TABLE (X86_64_07) },
2379   /* 08 */
2380   { "orB",              { Ebh1, Gb } },
2381   { "orS",              { Evh1, Gv } },
2382   { "orB",              { Gb, EbS } },
2383   { "orS",              { Gv, EvS } },
2384   { "orB",              { AL, Ib } },
2385   { "orS",              { eAX, Iv } },
2386   { X86_64_TABLE (X86_64_0D) },
2387   { Bad_Opcode },       /* 0x0f extended opcode escape */
2388   /* 10 */
2389   { "adcB",             { Ebh1, Gb } },
2390   { "adcS",             { Evh1, Gv } },
2391   { "adcB",             { Gb, EbS } },
2392   { "adcS",             { Gv, EvS } },
2393   { "adcB",             { AL, Ib } },
2394   { "adcS",             { eAX, Iv } },
2395   { X86_64_TABLE (X86_64_16) },
2396   { X86_64_TABLE (X86_64_17) },
2397   /* 18 */
2398   { "sbbB",             { Ebh1, Gb } },
2399   { "sbbS",             { Evh1, Gv } },
2400   { "sbbB",             { Gb, EbS } },
2401   { "sbbS",             { Gv, EvS } },
2402   { "sbbB",             { AL, Ib } },
2403   { "sbbS",             { eAX, Iv } },
2404   { X86_64_TABLE (X86_64_1E) },
2405   { X86_64_TABLE (X86_64_1F) },
2406   /* 20 */
2407   { "andB",             { Ebh1, Gb } },
2408   { "andS",             { Evh1, Gv } },
2409   { "andB",             { Gb, EbS } },
2410   { "andS",             { Gv, EvS } },
2411   { "andB",             { AL, Ib } },
2412   { "andS",             { eAX, Iv } },
2413   { Bad_Opcode },       /* SEG ES prefix */
2414   { X86_64_TABLE (X86_64_27) },
2415   /* 28 */
2416   { "subB",             { Ebh1, Gb } },
2417   { "subS",             { Evh1, Gv } },
2418   { "subB",             { Gb, EbS } },
2419   { "subS",             { Gv, EvS } },
2420   { "subB",             { AL, Ib } },
2421   { "subS",             { eAX, Iv } },
2422   { Bad_Opcode },       /* SEG CS prefix */
2423   { X86_64_TABLE (X86_64_2F) },
2424   /* 30 */
2425   { "xorB",             { Ebh1, Gb } },
2426   { "xorS",             { Evh1, Gv } },
2427   { "xorB",             { Gb, EbS } },
2428   { "xorS",             { Gv, EvS } },
2429   { "xorB",             { AL, Ib } },
2430   { "xorS",             { eAX, Iv } },
2431   { Bad_Opcode },       /* SEG SS prefix */
2432   { X86_64_TABLE (X86_64_37) },
2433   /* 38 */
2434   { "cmpB",             { Eb, Gb } },
2435   { "cmpS",             { Ev, Gv } },
2436   { "cmpB",             { Gb, EbS } },
2437   { "cmpS",             { Gv, EvS } },
2438   { "cmpB",             { AL, Ib } },
2439   { "cmpS",             { eAX, Iv } },
2440   { Bad_Opcode },       /* SEG DS prefix */
2441   { X86_64_TABLE (X86_64_3F) },
2442   /* 40 */
2443   { "inc{S|}",          { RMeAX } },
2444   { "inc{S|}",          { RMeCX } },
2445   { "inc{S|}",          { RMeDX } },
2446   { "inc{S|}",          { RMeBX } },
2447   { "inc{S|}",          { RMeSP } },
2448   { "inc{S|}",          { RMeBP } },
2449   { "inc{S|}",          { RMeSI } },
2450   { "inc{S|}",          { RMeDI } },
2451   /* 48 */
2452   { "dec{S|}",          { RMeAX } },
2453   { "dec{S|}",          { RMeCX } },
2454   { "dec{S|}",          { RMeDX } },
2455   { "dec{S|}",          { RMeBX } },
2456   { "dec{S|}",          { RMeSP } },
2457   { "dec{S|}",          { RMeBP } },
2458   { "dec{S|}",          { RMeSI } },
2459   { "dec{S|}",          { RMeDI } },
2460   /* 50 */
2461   { "pushV",            { RMrAX } },
2462   { "pushV",            { RMrCX } },
2463   { "pushV",            { RMrDX } },
2464   { "pushV",            { RMrBX } },
2465   { "pushV",            { RMrSP } },
2466   { "pushV",            { RMrBP } },
2467   { "pushV",            { RMrSI } },
2468   { "pushV",            { RMrDI } },
2469   /* 58 */
2470   { "popV",             { RMrAX } },
2471   { "popV",             { RMrCX } },
2472   { "popV",             { RMrDX } },
2473   { "popV",             { RMrBX } },
2474   { "popV",             { RMrSP } },
2475   { "popV",             { RMrBP } },
2476   { "popV",             { RMrSI } },
2477   { "popV",             { RMrDI } },
2478   /* 60 */
2479   { X86_64_TABLE (X86_64_60) },
2480   { X86_64_TABLE (X86_64_61) },
2481   { X86_64_TABLE (X86_64_62) },
2482   { X86_64_TABLE (X86_64_63) },
2483   { Bad_Opcode },       /* seg fs */
2484   { Bad_Opcode },       /* seg gs */
2485   { Bad_Opcode },       /* op size prefix */
2486   { Bad_Opcode },       /* adr size prefix */
2487   /* 68 */
2488   { "pushT",            { sIv } },
2489   { "imulS",            { Gv, Ev, Iv } },
2490   { "pushT",            { sIbT } },
2491   { "imulS",            { Gv, Ev, sIb } },
2492   { "ins{b|}",          { Ybr, indirDX } },
2493   { X86_64_TABLE (X86_64_6D) },
2494   { "outs{b|}",         { indirDXr, Xb } },
2495   { X86_64_TABLE (X86_64_6F) },
2496   /* 70 */
2497   { "joH",              { Jb, BND, cond_jump_flag } },
2498   { "jnoH",             { Jb, BND, cond_jump_flag } },
2499   { "jbH",              { Jb, BND, cond_jump_flag } },
2500   { "jaeH",             { Jb, BND, cond_jump_flag } },
2501   { "jeH",              { Jb, BND, cond_jump_flag } },
2502   { "jneH",             { Jb, BND, cond_jump_flag } },
2503   { "jbeH",             { Jb, BND, cond_jump_flag } },
2504   { "jaH",              { Jb, BND, cond_jump_flag } },
2505   /* 78 */
2506   { "jsH",              { Jb, BND, cond_jump_flag } },
2507   { "jnsH",             { Jb, BND, cond_jump_flag } },
2508   { "jpH",              { Jb, BND, cond_jump_flag } },
2509   { "jnpH",             { Jb, BND, cond_jump_flag } },
2510   { "jlH",              { Jb, BND, cond_jump_flag } },
2511   { "jgeH",             { Jb, BND, cond_jump_flag } },
2512   { "jleH",             { Jb, BND, cond_jump_flag } },
2513   { "jgH",              { Jb, BND, cond_jump_flag } },
2514   /* 80 */
2515   { REG_TABLE (REG_80) },
2516   { REG_TABLE (REG_81) },
2517   { Bad_Opcode },
2518   { REG_TABLE (REG_82) },
2519   { "testB",            { Eb, Gb } },
2520   { "testS",            { Ev, Gv } },
2521   { "xchgB",            { Ebh2, Gb } },
2522   { "xchgS",            { Evh2, Gv } },
2523   /* 88 */
2524   { "movB",             { Ebh3, Gb } },
2525   { "movS",             { Evh3, Gv } },
2526   { "movB",             { Gb, EbS } },
2527   { "movS",             { Gv, EvS } },
2528   { "movD",             { Sv, Sw } },
2529   { MOD_TABLE (MOD_8D) },
2530   { "movD",             { Sw, Sv } },
2531   { REG_TABLE (REG_8F) },
2532   /* 90 */
2533   { PREFIX_TABLE (PREFIX_90) },
2534   { "xchgS",            { RMeCX, eAX } },
2535   { "xchgS",            { RMeDX, eAX } },
2536   { "xchgS",            { RMeBX, eAX } },
2537   { "xchgS",            { RMeSP, eAX } },
2538   { "xchgS",            { RMeBP, eAX } },
2539   { "xchgS",            { RMeSI, eAX } },
2540   { "xchgS",            { RMeDI, eAX } },
2541   /* 98 */
2542   { "cW{t|}R",          { XX } },
2543   { "cR{t|}O",          { XX } },
2544   { X86_64_TABLE (X86_64_9A) },
2545   { Bad_Opcode },       /* fwait */
2546   { "pushfT",           { XX } },
2547   { "popfT",            { XX } },
2548   { "sahf",             { XX } },
2549   { "lahf",             { XX } },
2550   /* a0 */
2551   { "mov%LB",           { AL, Ob } },
2552   { "mov%LS",           { eAX, Ov } },
2553   { "mov%LB",           { Ob, AL } },
2554   { "mov%LS",           { Ov, eAX } },
2555   { "movs{b|}",         { Ybr, Xb } },
2556   { "movs{R|}",         { Yvr, Xv } },
2557   { "cmps{b|}",         { Xb, Yb } },
2558   { "cmps{R|}",         { Xv, Yv } },
2559   /* a8 */
2560   { "testB",            { AL, Ib } },
2561   { "testS",            { eAX, Iv } },
2562   { "stosB",            { Ybr, AL } },
2563   { "stosS",            { Yvr, eAX } },
2564   { "lodsB",            { ALr, Xb } },
2565   { "lodsS",            { eAXr, Xv } },
2566   { "scasB",            { AL, Yb } },
2567   { "scasS",            { eAX, Yv } },
2568   /* b0 */
2569   { "movB",             { RMAL, Ib } },
2570   { "movB",             { RMCL, Ib } },
2571   { "movB",             { RMDL, Ib } },
2572   { "movB",             { RMBL, Ib } },
2573   { "movB",             { RMAH, Ib } },
2574   { "movB",             { RMCH, Ib } },
2575   { "movB",             { RMDH, Ib } },
2576   { "movB",             { RMBH, Ib } },
2577   /* b8 */
2578   { "mov%LV",           { RMeAX, Iv64 } },
2579   { "mov%LV",           { RMeCX, Iv64 } },
2580   { "mov%LV",           { RMeDX, Iv64 } },
2581   { "mov%LV",           { RMeBX, Iv64 } },
2582   { "mov%LV",           { RMeSP, Iv64 } },
2583   { "mov%LV",           { RMeBP, Iv64 } },
2584   { "mov%LV",           { RMeSI, Iv64 } },
2585   { "mov%LV",           { RMeDI, Iv64 } },
2586   /* c0 */
2587   { REG_TABLE (REG_C0) },
2588   { REG_TABLE (REG_C1) },
2589   { "retT",             { Iw, BND } },
2590   { "retT",             { BND } },
2591   { X86_64_TABLE (X86_64_C4) },
2592   { X86_64_TABLE (X86_64_C5) },
2593   { REG_TABLE (REG_C6) },
2594   { REG_TABLE (REG_C7) },
2595   /* c8 */
2596   { "enterT",           { Iw, Ib } },
2597   { "leaveT",           { XX } },
2598   { "Jret{|f}P",        { Iw } },
2599   { "Jret{|f}P",        { XX } },
2600   { "int3",             { XX } },
2601   { "int",              { Ib } },
2602   { X86_64_TABLE (X86_64_CE) },
2603   { "iretP",            { XX } },
2604   /* d0 */
2605   { REG_TABLE (REG_D0) },
2606   { REG_TABLE (REG_D1) },
2607   { REG_TABLE (REG_D2) },
2608   { REG_TABLE (REG_D3) },
2609   { X86_64_TABLE (X86_64_D4) },
2610   { X86_64_TABLE (X86_64_D5) },
2611   { Bad_Opcode },
2612   { "xlat",             { DSBX } },
2613   /* d8 */
2614   { FLOAT },
2615   { FLOAT },
2616   { FLOAT },
2617   { FLOAT },
2618   { FLOAT },
2619   { FLOAT },
2620   { FLOAT },
2621   { FLOAT },
2622   /* e0 */
2623   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2624   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2625   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2626   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2627   { "inB",              { AL, Ib } },
2628   { "inG",              { zAX, Ib } },
2629   { "outB",             { Ib, AL } },
2630   { "outG",             { Ib, zAX } },
2631   /* e8 */
2632   { "callT",            { Jv, BND } },
2633   { "jmpT",             { Jv, BND } },
2634   { X86_64_TABLE (X86_64_EA) },
2635   { "jmp",              { Jb, BND } },
2636   { "inB",              { AL, indirDX } },
2637   { "inG",              { zAX, indirDX } },
2638   { "outB",             { indirDX, AL } },
2639   { "outG",             { indirDX, zAX } },
2640   /* f0 */
2641   { Bad_Opcode },       /* lock prefix */
2642   { "icebp",            { XX } },
2643   { Bad_Opcode },       /* repne */
2644   { Bad_Opcode },       /* repz */
2645   { "hlt",              { XX } },
2646   { "cmc",              { XX } },
2647   { REG_TABLE (REG_F6) },
2648   { REG_TABLE (REG_F7) },
2649   /* f8 */
2650   { "clc",              { XX } },
2651   { "stc",              { XX } },
2652   { "cli",              { XX } },
2653   { "sti",              { XX } },
2654   { "cld",              { XX } },
2655   { "std",              { XX } },
2656   { REG_TABLE (REG_FE) },
2657   { REG_TABLE (REG_FF) },
2658 };
2659
2660 static const struct dis386 dis386_twobyte[] = {
2661   /* 00 */
2662   { REG_TABLE (REG_0F00 ) },
2663   { REG_TABLE (REG_0F01 ) },
2664   { "larS",             { Gv, Ew } },
2665   { "lslS",             { Gv, Ew } },
2666   { Bad_Opcode },
2667   { "syscall",          { XX } },
2668   { "clts",             { XX } },
2669   { "sysretP",          { XX } },
2670   /* 08 */
2671   { "invd",             { XX } },
2672   { "wbinvd",           { XX } },
2673   { Bad_Opcode },
2674   { "ud2",              { XX } },
2675   { Bad_Opcode },
2676   { REG_TABLE (REG_0F0D) },
2677   { "femms",            { XX } },
2678   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2679   /* 10 */
2680   { PREFIX_TABLE (PREFIX_0F10) },
2681   { PREFIX_TABLE (PREFIX_0F11) },
2682   { PREFIX_TABLE (PREFIX_0F12) },
2683   { MOD_TABLE (MOD_0F13) },
2684   { "unpcklpX",         { XM, EXx } },
2685   { "unpckhpX",         { XM, EXx } },
2686   { PREFIX_TABLE (PREFIX_0F16) },
2687   { MOD_TABLE (MOD_0F17) },
2688   /* 18 */
2689   { REG_TABLE (REG_0F18) },
2690   { "nopQ",             { Ev } },
2691   { PREFIX_TABLE (PREFIX_0F1A) },
2692   { PREFIX_TABLE (PREFIX_0F1B) },
2693   { "nopQ",             { Ev } },
2694   { "nopQ",             { Ev } },
2695   { "nopQ",             { Ev } },
2696   { "nopQ",             { Ev } },
2697   /* 20 */
2698   { MOD_TABLE (MOD_0F20) },
2699   { MOD_TABLE (MOD_0F21) },
2700   { MOD_TABLE (MOD_0F22) },
2701   { MOD_TABLE (MOD_0F23) },
2702   { MOD_TABLE (MOD_0F24) },
2703   { Bad_Opcode },
2704   { MOD_TABLE (MOD_0F26) },
2705   { Bad_Opcode },
2706   /* 28 */
2707   { "movapX",           { XM, EXx } },
2708   { "movapX",           { EXxS, XM } },
2709   { PREFIX_TABLE (PREFIX_0F2A) },
2710   { PREFIX_TABLE (PREFIX_0F2B) },
2711   { PREFIX_TABLE (PREFIX_0F2C) },
2712   { PREFIX_TABLE (PREFIX_0F2D) },
2713   { PREFIX_TABLE (PREFIX_0F2E) },
2714   { PREFIX_TABLE (PREFIX_0F2F) },
2715   /* 30 */
2716   { "wrmsr",            { XX } },
2717   { "rdtsc",            { XX } },
2718   { "rdmsr",            { XX } },
2719   { "rdpmc",            { XX } },
2720   { "sysenter",         { XX } },
2721   { "sysexit",          { XX } },
2722   { Bad_Opcode },
2723   { "getsec",           { XX } },
2724   /* 38 */
2725   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2726   { Bad_Opcode },
2727   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2728   { Bad_Opcode },
2729   { Bad_Opcode },
2730   { Bad_Opcode },
2731   { Bad_Opcode },
2732   { Bad_Opcode },
2733   /* 40 */
2734   { "cmovoS",           { Gv, Ev } },
2735   { "cmovnoS",          { Gv, Ev } },
2736   { "cmovbS",           { Gv, Ev } },
2737   { "cmovaeS",          { Gv, Ev } },
2738   { "cmoveS",           { Gv, Ev } },
2739   { "cmovneS",          { Gv, Ev } },
2740   { "cmovbeS",          { Gv, Ev } },
2741   { "cmovaS",           { Gv, Ev } },
2742   /* 48 */
2743   { "cmovsS",           { Gv, Ev } },
2744   { "cmovnsS",          { Gv, Ev } },
2745   { "cmovpS",           { Gv, Ev } },
2746   { "cmovnpS",          { Gv, Ev } },
2747   { "cmovlS",           { Gv, Ev } },
2748   { "cmovgeS",          { Gv, Ev } },
2749   { "cmovleS",          { Gv, Ev } },
2750   { "cmovgS",           { Gv, Ev } },
2751   /* 50 */
2752   { MOD_TABLE (MOD_0F51) },
2753   { PREFIX_TABLE (PREFIX_0F51) },
2754   { PREFIX_TABLE (PREFIX_0F52) },
2755   { PREFIX_TABLE (PREFIX_0F53) },
2756   { "andpX",            { XM, EXx } },
2757   { "andnpX",           { XM, EXx } },
2758   { "orpX",             { XM, EXx } },
2759   { "xorpX",            { XM, EXx } },
2760   /* 58 */
2761   { PREFIX_TABLE (PREFIX_0F58) },
2762   { PREFIX_TABLE (PREFIX_0F59) },
2763   { PREFIX_TABLE (PREFIX_0F5A) },
2764   { PREFIX_TABLE (PREFIX_0F5B) },
2765   { PREFIX_TABLE (PREFIX_0F5C) },
2766   { PREFIX_TABLE (PREFIX_0F5D) },
2767   { PREFIX_TABLE (PREFIX_0F5E) },
2768   { PREFIX_TABLE (PREFIX_0F5F) },
2769   /* 60 */
2770   { PREFIX_TABLE (PREFIX_0F60) },
2771   { PREFIX_TABLE (PREFIX_0F61) },
2772   { PREFIX_TABLE (PREFIX_0F62) },
2773   { "packsswb",         { MX, EM } },
2774   { "pcmpgtb",          { MX, EM } },
2775   { "pcmpgtw",          { MX, EM } },
2776   { "pcmpgtd",          { MX, EM } },
2777   { "packuswb",         { MX, EM } },
2778   /* 68 */
2779   { "punpckhbw",        { MX, EM } },
2780   { "punpckhwd",        { MX, EM } },
2781   { "punpckhdq",        { MX, EM } },
2782   { "packssdw",         { MX, EM } },
2783   { PREFIX_TABLE (PREFIX_0F6C) },
2784   { PREFIX_TABLE (PREFIX_0F6D) },
2785   { "movK",             { MX, Edq } },
2786   { PREFIX_TABLE (PREFIX_0F6F) },
2787   /* 70 */
2788   { PREFIX_TABLE (PREFIX_0F70) },
2789   { REG_TABLE (REG_0F71) },
2790   { REG_TABLE (REG_0F72) },
2791   { REG_TABLE (REG_0F73) },
2792   { "pcmpeqb",          { MX, EM } },
2793   { "pcmpeqw",          { MX, EM } },
2794   { "pcmpeqd",          { MX, EM } },
2795   { "emms",             { XX } },
2796   /* 78 */
2797   { PREFIX_TABLE (PREFIX_0F78) },
2798   { PREFIX_TABLE (PREFIX_0F79) },
2799   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2800   { Bad_Opcode },
2801   { PREFIX_TABLE (PREFIX_0F7C) },
2802   { PREFIX_TABLE (PREFIX_0F7D) },
2803   { PREFIX_TABLE (PREFIX_0F7E) },
2804   { PREFIX_TABLE (PREFIX_0F7F) },
2805   /* 80 */
2806   { "joH",              { Jv, BND, cond_jump_flag } },
2807   { "jnoH",             { Jv, BND, cond_jump_flag } },
2808   { "jbH",              { Jv, BND, cond_jump_flag } },
2809   { "jaeH",             { Jv, BND, cond_jump_flag } },
2810   { "jeH",              { Jv, BND, cond_jump_flag } },
2811   { "jneH",             { Jv, BND, cond_jump_flag } },
2812   { "jbeH",             { Jv, BND, cond_jump_flag } },
2813   { "jaH",              { Jv, BND, cond_jump_flag } },
2814   /* 88 */
2815   { "jsH",              { Jv, BND, cond_jump_flag } },
2816   { "jnsH",             { Jv, BND, cond_jump_flag } },
2817   { "jpH",              { Jv, BND, cond_jump_flag } },
2818   { "jnpH",             { Jv, BND, cond_jump_flag } },
2819   { "jlH",              { Jv, BND, cond_jump_flag } },
2820   { "jgeH",             { Jv, BND, cond_jump_flag } },
2821   { "jleH",             { Jv, BND, cond_jump_flag } },
2822   { "jgH",              { Jv, BND, cond_jump_flag } },
2823   /* 90 */
2824   { "seto",             { Eb } },
2825   { "setno",            { Eb } },
2826   { "setb",             { Eb } },
2827   { "setae",            { Eb } },
2828   { "sete",             { Eb } },
2829   { "setne",            { Eb } },
2830   { "setbe",            { Eb } },
2831   { "seta",             { Eb } },
2832   /* 98 */
2833   { "sets",             { Eb } },
2834   { "setns",            { Eb } },
2835   { "setp",             { Eb } },
2836   { "setnp",            { Eb } },
2837   { "setl",             { Eb } },
2838   { "setge",            { Eb } },
2839   { "setle",            { Eb } },
2840   { "setg",             { Eb } },
2841   /* a0 */
2842   { "pushT",            { fs } },
2843   { "popT",             { fs } },
2844   { "cpuid",            { XX } },
2845   { "btS",              { Ev, Gv } },
2846   { "shldS",            { Ev, Gv, Ib } },
2847   { "shldS",            { Ev, Gv, CL } },
2848   { REG_TABLE (REG_0FA6) },
2849   { REG_TABLE (REG_0FA7) },
2850   /* a8 */
2851   { "pushT",            { gs } },
2852   { "popT",             { gs } },
2853   { "rsm",              { XX } },
2854   { "btsS",             { Evh1, Gv } },
2855   { "shrdS",            { Ev, Gv, Ib } },
2856   { "shrdS",            { Ev, Gv, CL } },
2857   { REG_TABLE (REG_0FAE) },
2858   { "imulS",            { Gv, Ev } },
2859   /* b0 */
2860   { "cmpxchgB",         { Ebh1, Gb } },
2861   { "cmpxchgS",         { Evh1, Gv } },
2862   { MOD_TABLE (MOD_0FB2) },
2863   { "btrS",             { Evh1, Gv } },
2864   { MOD_TABLE (MOD_0FB4) },
2865   { MOD_TABLE (MOD_0FB5) },
2866   { "movz{bR|x}",       { Gv, Eb } },
2867   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2868   /* b8 */
2869   { PREFIX_TABLE (PREFIX_0FB8) },
2870   { "ud1",              { XX } },
2871   { REG_TABLE (REG_0FBA) },
2872   { "btcS",             { Evh1, Gv } },
2873   { PREFIX_TABLE (PREFIX_0FBC) },
2874   { PREFIX_TABLE (PREFIX_0FBD) },
2875   { "movs{bR|x}",       { Gv, Eb } },
2876   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2877   /* c0 */
2878   { "xaddB",            { Ebh1, Gb } },
2879   { "xaddS",            { Evh1, Gv } },
2880   { PREFIX_TABLE (PREFIX_0FC2) },
2881   { PREFIX_TABLE (PREFIX_0FC3) },
2882   { "pinsrw",           { MX, Edqw, Ib } },
2883   { "pextrw",           { Gdq, MS, Ib } },
2884   { "shufpX",           { XM, EXx, Ib } },
2885   { REG_TABLE (REG_0FC7) },
2886   /* c8 */
2887   { "bswap",            { RMeAX } },
2888   { "bswap",            { RMeCX } },
2889   { "bswap",            { RMeDX } },
2890   { "bswap",            { RMeBX } },
2891   { "bswap",            { RMeSP } },
2892   { "bswap",            { RMeBP } },
2893   { "bswap",            { RMeSI } },
2894   { "bswap",            { RMeDI } },
2895   /* d0 */
2896   { PREFIX_TABLE (PREFIX_0FD0) },
2897   { "psrlw",            { MX, EM } },
2898   { "psrld",            { MX, EM } },
2899   { "psrlq",            { MX, EM } },
2900   { "paddq",            { MX, EM } },
2901   { "pmullw",           { MX, EM } },
2902   { PREFIX_TABLE (PREFIX_0FD6) },
2903   { MOD_TABLE (MOD_0FD7) },
2904   /* d8 */
2905   { "psubusb",          { MX, EM } },
2906   { "psubusw",          { MX, EM } },
2907   { "pminub",           { MX, EM } },
2908   { "pand",             { MX, EM } },
2909   { "paddusb",          { MX, EM } },
2910   { "paddusw",          { MX, EM } },
2911   { "pmaxub",           { MX, EM } },
2912   { "pandn",            { MX, EM } },
2913   /* e0 */
2914   { "pavgb",            { MX, EM } },
2915   { "psraw",            { MX, EM } },
2916   { "psrad",            { MX, EM } },
2917   { "pavgw",            { MX, EM } },
2918   { "pmulhuw",          { MX, EM } },
2919   { "pmulhw",           { MX, EM } },
2920   { PREFIX_TABLE (PREFIX_0FE6) },
2921   { PREFIX_TABLE (PREFIX_0FE7) },
2922   /* e8 */
2923   { "psubsb",           { MX, EM } },
2924   { "psubsw",           { MX, EM } },
2925   { "pminsw",           { MX, EM } },
2926   { "por",              { MX, EM } },
2927   { "paddsb",           { MX, EM } },
2928   { "paddsw",           { MX, EM } },
2929   { "pmaxsw",           { MX, EM } },
2930   { "pxor",             { MX, EM } },
2931   /* f0 */
2932   { PREFIX_TABLE (PREFIX_0FF0) },
2933   { "psllw",            { MX, EM } },
2934   { "pslld",            { MX, EM } },
2935   { "psllq",            { MX, EM } },
2936   { "pmuludq",          { MX, EM } },
2937   { "pmaddwd",          { MX, EM } },
2938   { "psadbw",           { MX, EM } },
2939   { PREFIX_TABLE (PREFIX_0FF7) },
2940   /* f8 */
2941   { "psubb",            { MX, EM } },
2942   { "psubw",            { MX, EM } },
2943   { "psubd",            { MX, EM } },
2944   { "psubq",            { MX, EM } },
2945   { "paddb",            { MX, EM } },
2946   { "paddw",            { MX, EM } },
2947   { "paddd",            { MX, EM } },
2948   { Bad_Opcode },
2949 };
2950
2951 static const unsigned char onebyte_has_modrm[256] = {
2952   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2953   /*       -------------------------------        */
2954   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2955   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2956   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2957   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2958   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2959   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2960   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2961   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2962   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2963   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2964   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2965   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2966   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2967   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2968   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2969   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2970   /*       -------------------------------        */
2971   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2972 };
2973
2974 static const unsigned char twobyte_has_modrm[256] = {
2975   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2976   /*       -------------------------------        */
2977   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2978   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2979   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2980   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2981   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2982   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2983   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2984   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2985   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2986   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2987   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2988   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2989   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2990   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2991   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2992   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2993   /*       -------------------------------        */
2994   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2995 };
2996
2997 static const unsigned char twobyte_has_mandatory_prefix[256] = {
2998   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2999   /*       -------------------------------        */
3000   /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3001   /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3002   /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3003   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3004   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3005   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3006   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3007   /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3008   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3009   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3010   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3011   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3012   /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3013   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3014   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3015   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3016   /*       -------------------------------        */
3017   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3018 };
3019
3020 static char obuf[100];
3021 static char *obufp;
3022 static char *mnemonicendp;
3023 static char scratchbuf[100];
3024 static unsigned char *start_codep;
3025 static unsigned char *insn_codep;
3026 static unsigned char *codep;
3027 static unsigned char *end_codep;
3028 static int last_lock_prefix;
3029 static int last_repz_prefix;
3030 static int last_repnz_prefix;
3031 static int last_data_prefix;
3032 static int last_addr_prefix;
3033 static int last_rex_prefix;
3034 static int last_seg_prefix;
3035 static int fwait_prefix;
3036 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
3037 static int mandatory_prefix;
3038 /* The active segment register prefix.  */
3039 static int active_seg_prefix;
3040 #define MAX_CODE_LENGTH 15
3041 /* We can up to 14 prefixes since the maximum instruction length is
3042    15bytes.  */
3043 static int all_prefixes[MAX_CODE_LENGTH - 1];
3044 static disassemble_info *the_info;
3045 static struct
3046   {
3047     int mod;
3048     int reg;
3049     int rm;
3050   }
3051 modrm;
3052 static unsigned char need_modrm;
3053 static struct
3054   {
3055     int scale;
3056     int index;
3057     int base;
3058   }
3059 sib;
3060 static struct
3061   {
3062     int register_specifier;
3063     int length;
3064     int prefix;
3065     int w;
3066     int evex;
3067     int r;
3068     int v;
3069     int mask_register_specifier;
3070     int zeroing;
3071     int ll;
3072     int b;
3073   }
3074 vex;
3075 static unsigned char need_vex;
3076 static unsigned char need_vex_reg;
3077 static unsigned char vex_w_done;
3078
3079 struct op
3080   {
3081     const char *name;
3082     unsigned int len;
3083   };
3084
3085 /* If we are accessing mod/rm/reg without need_modrm set, then the
3086    values are stale.  Hitting this abort likely indicates that you
3087    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3088 #define MODRM_CHECK  if (!need_modrm) abort ()
3089
3090 static const char **names64;
3091 static const char **names32;
3092 static const char **names16;
3093 static const char **names8;
3094 static const char **names8rex;
3095 static const char **names_seg;
3096 static const char *index64;
3097 static const char *index32;
3098 static const char **index16;
3099 static const char **names_bnd;
3100
3101 static const char *intel_names64[] = {
3102   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3103   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3104 };
3105 static const char *intel_names32[] = {
3106   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3107   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3108 };
3109 static const char *intel_names16[] = {
3110   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3111   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3112 };
3113 static const char *intel_names8[] = {
3114   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3115 };
3116 static const char *intel_names8rex[] = {
3117   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3118   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3119 };
3120 static const char *intel_names_seg[] = {
3121   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3122 };
3123 static const char *intel_index64 = "riz";
3124 static const char *intel_index32 = "eiz";
3125 static const char *intel_index16[] = {
3126   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3127 };
3128
3129 static const char *att_names64[] = {
3130   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3131   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3132 };
3133 static const char *att_names32[] = {
3134   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3135   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3136 };
3137 static const char *att_names16[] = {
3138   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3139   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3140 };
3141 static const char *att_names8[] = {
3142   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3143 };
3144 static const char *att_names8rex[] = {
3145   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3146   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3147 };
3148 static const char *att_names_seg[] = {
3149   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3150 };
3151 static const char *att_index64 = "%riz";
3152 static const char *att_index32 = "%eiz";
3153 static const char *att_index16[] = {
3154   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3155 };
3156
3157 static const char **names_mm;
3158 static const char *intel_names_mm[] = {
3159   "mm0", "mm1", "mm2", "mm3",
3160   "mm4", "mm5", "mm6", "mm7"
3161 };
3162 static const char *att_names_mm[] = {
3163   "%mm0", "%mm1", "%mm2", "%mm3",
3164   "%mm4", "%mm5", "%mm6", "%mm7"
3165 };
3166
3167 static const char *intel_names_bnd[] = {
3168   "bnd0", "bnd1", "bnd2", "bnd3"
3169 };
3170
3171 static const char *att_names_bnd[] = {
3172   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3173 };
3174
3175 static const char **names_xmm;
3176 static const char *intel_names_xmm[] = {
3177   "xmm0", "xmm1", "xmm2", "xmm3",
3178   "xmm4", "xmm5", "xmm6", "xmm7",
3179   "xmm8", "xmm9", "xmm10", "xmm11",
3180   "xmm12", "xmm13", "xmm14", "xmm15",
3181   "xmm16", "xmm17", "xmm18", "xmm19",
3182   "xmm20", "xmm21", "xmm22", "xmm23",
3183   "xmm24", "xmm25", "xmm26", "xmm27",
3184   "xmm28", "xmm29", "xmm30", "xmm31"
3185 };
3186 static const char *att_names_xmm[] = {
3187   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3188   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3189   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3190   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3191   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3192   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3193   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3194   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3195 };
3196
3197 static const char **names_ymm;
3198 static const char *intel_names_ymm[] = {
3199   "ymm0", "ymm1", "ymm2", "ymm3",
3200   "ymm4", "ymm5", "ymm6", "ymm7",
3201   "ymm8", "ymm9", "ymm10", "ymm11",
3202   "ymm12", "ymm13", "ymm14", "ymm15",
3203   "ymm16", "ymm17", "ymm18", "ymm19",
3204   "ymm20", "ymm21", "ymm22", "ymm23",
3205   "ymm24", "ymm25", "ymm26", "ymm27",
3206   "ymm28", "ymm29", "ymm30", "ymm31"
3207 };
3208 static const char *att_names_ymm[] = {
3209   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3210   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3211   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3212   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3213   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3214   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3215   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3216   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3217 };
3218
3219 static const char **names_zmm;
3220 static const char *intel_names_zmm[] = {
3221   "zmm0", "zmm1", "zmm2", "zmm3",
3222   "zmm4", "zmm5", "zmm6", "zmm7",
3223   "zmm8", "zmm9", "zmm10", "zmm11",
3224   "zmm12", "zmm13", "zmm14", "zmm15",
3225   "zmm16", "zmm17", "zmm18", "zmm19",
3226   "zmm20", "zmm21", "zmm22", "zmm23",
3227   "zmm24", "zmm25", "zmm26", "zmm27",
3228   "zmm28", "zmm29", "zmm30", "zmm31"
3229 };
3230 static const char *att_names_zmm[] = {
3231   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3232   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3233   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3234   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3235   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3236   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3237   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3238   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3239 };
3240
3241 static const char **names_mask;
3242 static const char *intel_names_mask[] = {
3243   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3244 };
3245 static const char *att_names_mask[] = {
3246   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3247 };
3248
3249 static const char *names_rounding[] =
3250 {
3251   "{rn-sae}",
3252   "{rd-sae}",
3253   "{ru-sae}",
3254   "{rz-sae}"
3255 };
3256
3257 static const struct dis386 reg_table[][8] = {
3258   /* REG_80 */
3259   {
3260     { "addA",   { Ebh1, Ib } },
3261     { "orA",    { Ebh1, Ib } },
3262     { "adcA",   { Ebh1, Ib } },
3263     { "sbbA",   { Ebh1, Ib } },
3264     { "andA",   { Ebh1, Ib } },
3265     { "subA",   { Ebh1, Ib } },
3266     { "xorA",   { Ebh1, Ib } },
3267     { "cmpA",   { Eb, Ib } },
3268   },
3269   /* REG_81 */
3270   {
3271     { "addQ",   { Evh1, Iv } },
3272     { "orQ",    { Evh1, Iv } },
3273     { "adcQ",   { Evh1, Iv } },
3274     { "sbbQ",   { Evh1, Iv } },
3275     { "andQ",   { Evh1, Iv } },
3276     { "subQ",   { Evh1, Iv } },
3277     { "xorQ",   { Evh1, Iv } },
3278     { "cmpQ",   { Ev, Iv } },
3279   },
3280   /* REG_82 */
3281   {
3282     { "addQ",   { Evh1, sIb } },
3283     { "orQ",    { Evh1, sIb } },
3284     { "adcQ",   { Evh1, sIb } },
3285     { "sbbQ",   { Evh1, sIb } },
3286     { "andQ",   { Evh1, sIb } },
3287     { "subQ",   { Evh1, sIb } },
3288     { "xorQ",   { Evh1, sIb } },
3289     { "cmpQ",   { Ev, sIb } },
3290   },
3291   /* REG_8F */
3292   {
3293     { "popU",   { stackEv } },
3294     { XOP_8F_TABLE (XOP_09) },
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { XOP_8F_TABLE (XOP_09) },
3299   },
3300   /* REG_C0 */
3301   {
3302     { "rolA",   { Eb, Ib } },
3303     { "rorA",   { Eb, Ib } },
3304     { "rclA",   { Eb, Ib } },
3305     { "rcrA",   { Eb, Ib } },
3306     { "shlA",   { Eb, Ib } },
3307     { "shrA",   { Eb, Ib } },
3308     { Bad_Opcode },
3309     { "sarA",   { Eb, Ib } },
3310   },
3311   /* REG_C1 */
3312   {
3313     { "rolQ",   { Ev, Ib } },
3314     { "rorQ",   { Ev, Ib } },
3315     { "rclQ",   { Ev, Ib } },
3316     { "rcrQ",   { Ev, Ib } },
3317     { "shlQ",   { Ev, Ib } },
3318     { "shrQ",   { Ev, Ib } },
3319     { Bad_Opcode },
3320     { "sarQ",   { Ev, Ib } },
3321   },
3322   /* REG_C6 */
3323   {
3324     { "movA",   { Ebh3, Ib } },
3325     { Bad_Opcode },
3326     { Bad_Opcode },
3327     { Bad_Opcode },
3328     { Bad_Opcode },
3329     { Bad_Opcode },
3330     { Bad_Opcode },
3331     { MOD_TABLE (MOD_C6_REG_7) },
3332   },
3333   /* REG_C7 */
3334   {
3335     { "movQ",   { Evh3, Iv } },
3336     { Bad_Opcode },
3337     { Bad_Opcode },
3338     { Bad_Opcode },
3339     { Bad_Opcode },
3340     { Bad_Opcode },
3341     { Bad_Opcode },
3342     { MOD_TABLE (MOD_C7_REG_7) },
3343   },
3344   /* REG_D0 */
3345   {
3346     { "rolA",   { Eb, I1 } },
3347     { "rorA",   { Eb, I1 } },
3348     { "rclA",   { Eb, I1 } },
3349     { "rcrA",   { Eb, I1 } },
3350     { "shlA",   { Eb, I1 } },
3351     { "shrA",   { Eb, I1 } },
3352     { Bad_Opcode },
3353     { "sarA",   { Eb, I1 } },
3354   },
3355   /* REG_D1 */
3356   {
3357     { "rolQ",   { Ev, I1 } },
3358     { "rorQ",   { Ev, I1 } },
3359     { "rclQ",   { Ev, I1 } },
3360     { "rcrQ",   { Ev, I1 } },
3361     { "shlQ",   { Ev, I1 } },
3362     { "shrQ",   { Ev, I1 } },
3363     { Bad_Opcode },
3364     { "sarQ",   { Ev, I1 } },
3365   },
3366   /* REG_D2 */
3367   {
3368     { "rolA",   { Eb, CL } },
3369     { "rorA",   { Eb, CL } },
3370     { "rclA",   { Eb, CL } },
3371     { "rcrA",   { Eb, CL } },
3372     { "shlA",   { Eb, CL } },
3373     { "shrA",   { Eb, CL } },
3374     { Bad_Opcode },
3375     { "sarA",   { Eb, CL } },
3376   },
3377   /* REG_D3 */
3378   {
3379     { "rolQ",   { Ev, CL } },
3380     { "rorQ",   { Ev, CL } },
3381     { "rclQ",   { Ev, CL } },
3382     { "rcrQ",   { Ev, CL } },
3383     { "shlQ",   { Ev, CL } },
3384     { "shrQ",   { Ev, CL } },
3385     { Bad_Opcode },
3386     { "sarQ",   { Ev, CL } },
3387   },
3388   /* REG_F6 */
3389   {
3390     { "testA",  { Eb, Ib } },
3391     { Bad_Opcode },
3392     { "notA",   { Ebh1 } },
3393     { "negA",   { Ebh1 } },
3394     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3395     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3396     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3397     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3398   },
3399   /* REG_F7 */
3400   {
3401     { "testQ",  { Ev, Iv } },
3402     { Bad_Opcode },
3403     { "notQ",   { Evh1 } },
3404     { "negQ",   { Evh1 } },
3405     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3406     { "imulQ",  { Ev } },
3407     { "divQ",   { Ev } },
3408     { "idivQ",  { Ev } },
3409   },
3410   /* REG_FE */
3411   {
3412     { "incA",   { Ebh1 } },
3413     { "decA",   { Ebh1 } },
3414   },
3415   /* REG_FF */
3416   {
3417     { "incQ",   { Evh1 } },
3418     { "decQ",   { Evh1 } },
3419     { "call{T|}", { indirEv, BND } },
3420     { MOD_TABLE (MOD_FF_REG_3) },
3421     { "jmp{T|}", { indirEv, BND } },
3422     { MOD_TABLE (MOD_FF_REG_5) },
3423     { "pushU",  { stackEv } },
3424     { Bad_Opcode },
3425   },
3426   /* REG_0F00 */
3427   {
3428     { "sldtD",  { Sv } },
3429     { "strD",   { Sv } },
3430     { "lldt",   { Ew } },
3431     { "ltr",    { Ew } },
3432     { "verr",   { Ew } },
3433     { "verw",   { Ew } },
3434     { Bad_Opcode },
3435     { Bad_Opcode },
3436   },
3437   /* REG_0F01 */
3438   {
3439     { MOD_TABLE (MOD_0F01_REG_0) },
3440     { MOD_TABLE (MOD_0F01_REG_1) },
3441     { MOD_TABLE (MOD_0F01_REG_2) },
3442     { MOD_TABLE (MOD_0F01_REG_3) },
3443     { "smswD",  { Sv } },
3444     { Bad_Opcode },
3445     { "lmsw",   { Ew } },
3446     { MOD_TABLE (MOD_0F01_REG_7) },
3447   },
3448   /* REG_0F0D */
3449   {
3450     { "prefetch",       { Mb } },
3451     { "prefetchw",      { Mb } },
3452     { "prefetchwt1",    { Mb } },
3453     { "prefetch",       { Mb } },
3454     { "prefetch",       { Mb } },
3455     { "prefetch",       { Mb } },
3456     { "prefetch",       { Mb } },
3457     { "prefetch",       { Mb } },
3458   },
3459   /* REG_0F18 */
3460   {
3461     { MOD_TABLE (MOD_0F18_REG_0) },
3462     { MOD_TABLE (MOD_0F18_REG_1) },
3463     { MOD_TABLE (MOD_0F18_REG_2) },
3464     { MOD_TABLE (MOD_0F18_REG_3) },
3465     { MOD_TABLE (MOD_0F18_REG_4) },
3466     { MOD_TABLE (MOD_0F18_REG_5) },
3467     { MOD_TABLE (MOD_0F18_REG_6) },
3468     { MOD_TABLE (MOD_0F18_REG_7) },
3469   },
3470   /* REG_0F71 */
3471   {
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { MOD_TABLE (MOD_0F71_REG_2) },
3475     { Bad_Opcode },
3476     { MOD_TABLE (MOD_0F71_REG_4) },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_0F71_REG_6) },
3479   },
3480   /* REG_0F72 */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { MOD_TABLE (MOD_0F72_REG_2) },
3485     { Bad_Opcode },
3486     { MOD_TABLE (MOD_0F72_REG_4) },
3487     { Bad_Opcode },
3488     { MOD_TABLE (MOD_0F72_REG_6) },
3489   },
3490   /* REG_0F73 */
3491   {
3492     { Bad_Opcode },
3493     { Bad_Opcode },
3494     { MOD_TABLE (MOD_0F73_REG_2) },
3495     { MOD_TABLE (MOD_0F73_REG_3) },
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { MOD_TABLE (MOD_0F73_REG_6) },
3499     { MOD_TABLE (MOD_0F73_REG_7) },
3500   },
3501   /* REG_0FA6 */
3502   {
3503     { "montmul",        { { OP_0f07, 0 } } },
3504     { "xsha1",          { { OP_0f07, 0 } } },
3505     { "xsha256",        { { OP_0f07, 0 } } },
3506   },
3507   /* REG_0FA7 */
3508   {
3509     { "xstore-rng",     { { OP_0f07, 0 } } },
3510     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3511     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3512     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3513     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3514     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3515   },
3516   /* REG_0FAE */
3517   {
3518     { MOD_TABLE (MOD_0FAE_REG_0) },
3519     { MOD_TABLE (MOD_0FAE_REG_1) },
3520     { MOD_TABLE (MOD_0FAE_REG_2) },
3521     { MOD_TABLE (MOD_0FAE_REG_3) },
3522     { MOD_TABLE (MOD_0FAE_REG_4) },
3523     { MOD_TABLE (MOD_0FAE_REG_5) },
3524     { MOD_TABLE (MOD_0FAE_REG_6) },
3525     { MOD_TABLE (MOD_0FAE_REG_7) },
3526   },
3527   /* REG_0FBA */
3528   {
3529     { Bad_Opcode },
3530     { Bad_Opcode },
3531     { Bad_Opcode },
3532     { Bad_Opcode },
3533     { "btQ",    { Ev, Ib } },
3534     { "btsQ",   { Evh1, Ib } },
3535     { "btrQ",   { Evh1, Ib } },
3536     { "btcQ",   { Evh1, Ib } },
3537   },
3538   /* REG_0FC7 */
3539   {
3540     { Bad_Opcode },
3541     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3542     { Bad_Opcode },
3543     { MOD_TABLE (MOD_0FC7_REG_3) },
3544     { MOD_TABLE (MOD_0FC7_REG_4) },
3545     { MOD_TABLE (MOD_0FC7_REG_5) },
3546     { MOD_TABLE (MOD_0FC7_REG_6) },
3547     { MOD_TABLE (MOD_0FC7_REG_7) },
3548   },
3549   /* REG_VEX_0F71 */
3550   {
3551     { Bad_Opcode },
3552     { Bad_Opcode },
3553     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3554     { Bad_Opcode },
3555     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3556     { Bad_Opcode },
3557     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3558   },
3559   /* REG_VEX_0F72 */
3560   {
3561     { Bad_Opcode },
3562     { Bad_Opcode },
3563     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3564     { Bad_Opcode },
3565     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3566     { Bad_Opcode },
3567     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3568   },
3569   /* REG_VEX_0F73 */
3570   {
3571     { Bad_Opcode },
3572     { Bad_Opcode },
3573     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3574     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3575     { Bad_Opcode },
3576     { Bad_Opcode },
3577     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3578     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3579   },
3580   /* REG_VEX_0FAE */
3581   {
3582     { Bad_Opcode },
3583     { Bad_Opcode },
3584     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3585     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3586   },
3587   /* REG_VEX_0F38F3 */
3588   {
3589     { Bad_Opcode },
3590     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3591     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3592     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3593   },
3594   /* REG_XOP_LWPCB */
3595   {
3596     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3597     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3598   },
3599   /* REG_XOP_LWP */
3600   {
3601     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3602     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3603   },
3604   /* REG_XOP_TBM_01 */
3605   {
3606     { Bad_Opcode },
3607     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3608     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3609     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3610     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3611     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3612     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3613     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3614   },
3615   /* REG_XOP_TBM_02 */
3616   {
3617     { Bad_Opcode },
3618     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { Bad_Opcode },
3622     { Bad_Opcode },
3623     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3624   },
3625 #define NEED_REG_TABLE
3626 #include "i386-dis-evex.h"
3627 #undef NEED_REG_TABLE
3628 };
3629
3630 static const struct dis386 prefix_table[][4] = {
3631   /* PREFIX_90 */
3632   {
3633     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3634     { "pause", { XX } },
3635     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3636   },
3637
3638   /* PREFIX_0F10 */
3639   {
3640     { "movups", { XM, EXx } },
3641     { "movss",  { XM, EXd } },
3642     { "movupd", { XM, EXx } },
3643     { "movsd",  { XM, EXq } },
3644   },
3645
3646   /* PREFIX_0F11 */
3647   {
3648     { "movups", { EXxS, XM } },
3649     { "movss",  { EXdS, XM } },
3650     { "movupd", { EXxS, XM } },
3651     { "movsd",  { EXqS, XM } },
3652   },
3653
3654   /* PREFIX_0F12 */
3655   {
3656     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3657     { "movsldup", { XM, EXx } },
3658     { "movlpd", { XM, EXq } },
3659     { "movddup", { XM, EXq } },
3660   },
3661
3662   /* PREFIX_0F16 */
3663   {
3664     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3665     { "movshdup", { XM, EXx } },
3666     { "movhpd", { XM, EXq } },
3667   },
3668
3669   /* PREFIX_0F1A */
3670   {
3671     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3672     { "bndcl",  { Gbnd, Ev_bnd } },
3673     { "bndmov", { Gbnd, Ebnd } },
3674     { "bndcu",  { Gbnd, Ev_bnd } },
3675   },
3676
3677   /* PREFIX_0F1B */
3678   {
3679     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3680     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3681     { "bndmov", { Ebnd, Gbnd } },
3682     { "bndcn",  { Gbnd, Ev_bnd } },
3683   },
3684
3685   /* PREFIX_0F2A */
3686   {
3687     { "cvtpi2ps", { XM, EMCq } },
3688     { "cvtsi2ss%LQ", { XM, Ev } },
3689     { "cvtpi2pd", { XM, EMCq } },
3690     { "cvtsi2sd%LQ", { XM, Ev } },
3691   },
3692
3693   /* PREFIX_0F2B */
3694   {
3695     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3696     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3697     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3698     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3699   },
3700
3701   /* PREFIX_0F2C */
3702   {
3703     { "cvttps2pi", { MXC, EXq } },
3704     { "cvttss2siY", { Gv, EXd } },
3705     { "cvttpd2pi", { MXC, EXx } },
3706     { "cvttsd2siY", { Gv, EXq } },
3707   },
3708
3709   /* PREFIX_0F2D */
3710   {
3711     { "cvtps2pi", { MXC, EXq } },
3712     { "cvtss2siY", { Gv, EXd } },
3713     { "cvtpd2pi", { MXC, EXx } },
3714     { "cvtsd2siY", { Gv, EXq } },
3715   },
3716
3717   /* PREFIX_0F2E */
3718   {
3719     { "ucomiss",{ XM, EXd } },
3720     { Bad_Opcode },
3721     { "ucomisd",{ XM, EXq } },
3722   },
3723
3724   /* PREFIX_0F2F */
3725   {
3726     { "comiss", { XM, EXd } },
3727     { Bad_Opcode },
3728     { "comisd", { XM, EXq } },
3729   },
3730
3731   /* PREFIX_0F51 */
3732   {
3733     { "sqrtps", { XM, EXx } },
3734     { "sqrtss", { XM, EXd } },
3735     { "sqrtpd", { XM, EXx } },
3736     { "sqrtsd", { XM, EXq } },
3737   },
3738
3739   /* PREFIX_0F52 */
3740   {
3741     { "rsqrtps",{ XM, EXx } },
3742     { "rsqrtss",{ XM, EXd } },
3743   },
3744
3745   /* PREFIX_0F53 */
3746   {
3747     { "rcpps",  { XM, EXx } },
3748     { "rcpss",  { XM, EXd } },
3749   },
3750
3751   /* PREFIX_0F58 */
3752   {
3753     { "addps", { XM, EXx } },
3754     { "addss", { XM, EXd } },
3755     { "addpd", { XM, EXx } },
3756     { "addsd", { XM, EXq } },
3757   },
3758
3759   /* PREFIX_0F59 */
3760   {
3761     { "mulps",  { XM, EXx } },
3762     { "mulss",  { XM, EXd } },
3763     { "mulpd",  { XM, EXx } },
3764     { "mulsd",  { XM, EXq } },
3765   },
3766
3767   /* PREFIX_0F5A */
3768   {
3769     { "cvtps2pd", { XM, EXq } },
3770     { "cvtss2sd", { XM, EXd } },
3771     { "cvtpd2ps", { XM, EXx } },
3772     { "cvtsd2ss", { XM, EXq } },
3773   },
3774
3775   /* PREFIX_0F5B */
3776   {
3777     { "cvtdq2ps", { XM, EXx } },
3778     { "cvttps2dq", { XM, EXx } },
3779     { "cvtps2dq", { XM, EXx } },
3780   },
3781
3782   /* PREFIX_0F5C */
3783   {
3784     { "subps",  { XM, EXx } },
3785     { "subss",  { XM, EXd } },
3786     { "subpd",  { XM, EXx } },
3787     { "subsd",  { XM, EXq } },
3788   },
3789
3790   /* PREFIX_0F5D */
3791   {
3792     { "minps",  { XM, EXx } },
3793     { "minss",  { XM, EXd } },
3794     { "minpd",  { XM, EXx } },
3795     { "minsd",  { XM, EXq } },
3796   },
3797
3798   /* PREFIX_0F5E */
3799   {
3800     { "divps",  { XM, EXx } },
3801     { "divss",  { XM, EXd } },
3802     { "divpd",  { XM, EXx } },
3803     { "divsd",  { XM, EXq } },
3804   },
3805
3806   /* PREFIX_0F5F */
3807   {
3808     { "maxps",  { XM, EXx } },
3809     { "maxss",  { XM, EXd } },
3810     { "maxpd",  { XM, EXx } },
3811     { "maxsd",  { XM, EXq } },
3812   },
3813
3814   /* PREFIX_0F60 */
3815   {
3816     { "punpcklbw",{ MX, EMd } },
3817     { Bad_Opcode },
3818     { "punpcklbw",{ MX, EMx } },
3819   },
3820
3821   /* PREFIX_0F61 */
3822   {
3823     { "punpcklwd",{ MX, EMd } },
3824     { Bad_Opcode },
3825     { "punpcklwd",{ MX, EMx } },
3826   },
3827
3828   /* PREFIX_0F62 */
3829   {
3830     { "punpckldq",{ MX, EMd } },
3831     { Bad_Opcode },
3832     { "punpckldq",{ MX, EMx } },
3833   },
3834
3835   /* PREFIX_0F6C */
3836   {
3837     { Bad_Opcode },
3838     { Bad_Opcode },
3839     { "punpcklqdq", { XM, EXx } },
3840   },
3841
3842   /* PREFIX_0F6D */
3843   {
3844     { Bad_Opcode },
3845     { Bad_Opcode },
3846     { "punpckhqdq", { XM, EXx } },
3847   },
3848
3849   /* PREFIX_0F6F */
3850   {
3851     { "movq",   { MX, EM } },
3852     { "movdqu", { XM, EXx } },
3853     { "movdqa", { XM, EXx } },
3854   },
3855
3856   /* PREFIX_0F70 */
3857   {
3858     { "pshufw", { MX, EM, Ib } },
3859     { "pshufhw",{ XM, EXx, Ib } },
3860     { "pshufd", { XM, EXx, Ib } },
3861     { "pshuflw",{ XM, EXx, Ib } },
3862   },
3863
3864   /* PREFIX_0F73_REG_3 */
3865   {
3866     { Bad_Opcode },
3867     { Bad_Opcode },
3868     { "psrldq", { XS, Ib } },
3869   },
3870
3871   /* PREFIX_0F73_REG_7 */
3872   {
3873     { Bad_Opcode },
3874     { Bad_Opcode },
3875     { "pslldq", { XS, Ib } },
3876   },
3877
3878   /* PREFIX_0F78 */
3879   {
3880     {"vmread",  { Em, Gm } },
3881     { Bad_Opcode },
3882     {"extrq",   { XS, Ib, Ib } },
3883     {"insertq", { XM, XS, Ib, Ib } },
3884   },
3885
3886   /* PREFIX_0F79 */
3887   {
3888     {"vmwrite", { Gm, Em } },
3889     { Bad_Opcode },
3890     {"extrq",   { XM, XS } },
3891     {"insertq", { XM, XS } },
3892   },
3893
3894   /* PREFIX_0F7C */
3895   {
3896     { Bad_Opcode },
3897     { Bad_Opcode },
3898     { "haddpd", { XM, EXx } },
3899     { "haddps", { XM, EXx } },
3900   },
3901
3902   /* PREFIX_0F7D */
3903   {
3904     { Bad_Opcode },
3905     { Bad_Opcode },
3906     { "hsubpd", { XM, EXx } },
3907     { "hsubps", { XM, EXx } },
3908   },
3909
3910   /* PREFIX_0F7E */
3911   {
3912     { "movK",   { Edq, MX } },
3913     { "movq",   { XM, EXq } },
3914     { "movK",   { Edq, XM } },
3915   },
3916
3917   /* PREFIX_0F7F */
3918   {
3919     { "movq",   { EMS, MX } },
3920     { "movdqu", { EXxS, XM } },
3921     { "movdqa", { EXxS, XM } },
3922   },
3923
3924   /* PREFIX_0FAE_REG_0 */
3925   {
3926     { Bad_Opcode },
3927     { "rdfsbase", { Ev } },
3928   },
3929
3930   /* PREFIX_0FAE_REG_1 */
3931   {
3932     { Bad_Opcode },
3933     { "rdgsbase", { Ev } },
3934   },
3935
3936   /* PREFIX_0FAE_REG_2 */
3937   {
3938     { Bad_Opcode },
3939     { "wrfsbase", { Ev } },
3940   },
3941
3942   /* PREFIX_0FAE_REG_3 */
3943   {
3944     { Bad_Opcode },
3945     { "wrgsbase", { Ev } },
3946   },
3947
3948   /* PREFIX_0FAE_REG_7 */
3949   {
3950     { "clflush",        { Mb } },
3951     { Bad_Opcode },
3952     { "clflushopt",     { Mb } },
3953   },
3954
3955   /* PREFIX_0FB8 */
3956   {
3957     { Bad_Opcode },
3958     { "popcntS", { Gv, Ev } },
3959   },
3960
3961   /* PREFIX_0FBC */
3962   {
3963     { "bsfS",   { Gv, Ev } },
3964     { "tzcntS", { Gv, Ev } },
3965     { "bsfS",   { Gv, Ev } },
3966   },
3967
3968   /* PREFIX_0FBD */
3969   {
3970     { "bsrS",   { Gv, Ev } },
3971     { "lzcntS", { Gv, Ev } },
3972     { "bsrS",   { Gv, Ev } },
3973   },
3974
3975   /* PREFIX_0FC2 */
3976   {
3977     { "cmpps",  { XM, EXx, CMP } },
3978     { "cmpss",  { XM, EXd, CMP } },
3979     { "cmppd",  { XM, EXx, CMP } },
3980     { "cmpsd",  { XM, EXq, CMP } },
3981   },
3982
3983   /* PREFIX_0FC3 */
3984   {
3985     { "movntiS", { Ma, Gv } },
3986   },
3987
3988   /* PREFIX_0FC7_REG_6 */
3989   {
3990     { "vmptrld",{ Mq } },
3991     { "vmxon",  { Mq } },
3992     { "vmclear",{ Mq } },
3993   },
3994
3995   /* PREFIX_0FD0 */
3996   {
3997     { Bad_Opcode },
3998     { Bad_Opcode },
3999     { "addsubpd", { XM, EXx } },
4000     { "addsubps", { XM, EXx } },
4001   },
4002
4003   /* PREFIX_0FD6 */
4004   {
4005     { Bad_Opcode },
4006     { "movq2dq",{ XM, MS } },
4007     { "movq",   { EXqS, XM } },
4008     { "movdq2q",{ MX, XS } },
4009   },
4010
4011   /* PREFIX_0FE6 */
4012   {
4013     { Bad_Opcode },
4014     { "cvtdq2pd", { XM, EXq } },
4015     { "cvttpd2dq", { XM, EXx } },
4016     { "cvtpd2dq", { XM, EXx } },
4017   },
4018
4019   /* PREFIX_0FE7 */
4020   {
4021     { "movntq", { Mq, MX } },
4022     { Bad_Opcode },
4023     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4024   },
4025
4026   /* PREFIX_0FF0 */
4027   {
4028     { Bad_Opcode },
4029     { Bad_Opcode },
4030     { Bad_Opcode },
4031     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4032   },
4033
4034   /* PREFIX_0FF7 */
4035   {
4036     { "maskmovq", { MX, MS } },
4037     { Bad_Opcode },
4038     { "maskmovdqu", { XM, XS } },
4039   },
4040
4041   /* PREFIX_0F3810 */
4042   {
4043     { Bad_Opcode },
4044     { Bad_Opcode },
4045     { "pblendvb", { XM, EXx, XMM0 } },
4046   },
4047
4048   /* PREFIX_0F3814 */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { "blendvps", { XM, EXx, XMM0 } },
4053   },
4054
4055   /* PREFIX_0F3815 */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { "blendvpd", { XM, EXx, XMM0 } },
4060   },
4061
4062   /* PREFIX_0F3817 */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { "ptest",  { XM, EXx } },
4067   },
4068
4069   /* PREFIX_0F3820 */
4070   {
4071     { Bad_Opcode },
4072     { Bad_Opcode },
4073     { "pmovsxbw", { XM, EXq } },
4074   },
4075
4076   /* PREFIX_0F3821 */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { "pmovsxbd", { XM, EXd } },
4081   },
4082
4083   /* PREFIX_0F3822 */
4084   {
4085     { Bad_Opcode },
4086     { Bad_Opcode },
4087     { "pmovsxbq", { XM, EXw } },
4088   },
4089
4090   /* PREFIX_0F3823 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { "pmovsxwd", { XM, EXq } },
4095   },
4096
4097   /* PREFIX_0F3824 */
4098   {
4099     { Bad_Opcode },
4100     { Bad_Opcode },
4101     { "pmovsxwq", { XM, EXd } },
4102   },
4103
4104   /* PREFIX_0F3825 */
4105   {
4106     { Bad_Opcode },
4107     { Bad_Opcode },
4108     { "pmovsxdq", { XM, EXq } },
4109   },
4110
4111   /* PREFIX_0F3828 */
4112   {
4113     { Bad_Opcode },
4114     { Bad_Opcode },
4115     { "pmuldq", { XM, EXx } },
4116   },
4117
4118   /* PREFIX_0F3829 */
4119   {
4120     { Bad_Opcode },
4121     { Bad_Opcode },
4122     { "pcmpeqq", { XM, EXx } },
4123   },
4124
4125   /* PREFIX_0F382A */
4126   {
4127     { Bad_Opcode },
4128     { Bad_Opcode },
4129     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4130   },
4131
4132   /* PREFIX_0F382B */
4133   {
4134     { Bad_Opcode },
4135     { Bad_Opcode },
4136     { "packusdw", { XM, EXx } },
4137   },
4138
4139   /* PREFIX_0F3830 */
4140   {
4141     { Bad_Opcode },
4142     { Bad_Opcode },
4143     { "pmovzxbw", { XM, EXq } },
4144   },
4145
4146   /* PREFIX_0F3831 */
4147   {
4148     { Bad_Opcode },
4149     { Bad_Opcode },
4150     { "pmovzxbd", { XM, EXd } },
4151   },
4152
4153   /* PREFIX_0F3832 */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { "pmovzxbq", { XM, EXw } },
4158   },
4159
4160   /* PREFIX_0F3833 */
4161   {
4162     { Bad_Opcode },
4163     { Bad_Opcode },
4164     { "pmovzxwd", { XM, EXq } },
4165   },
4166
4167   /* PREFIX_0F3834 */
4168   {
4169     { Bad_Opcode },
4170     { Bad_Opcode },
4171     { "pmovzxwq", { XM, EXd } },
4172   },
4173
4174   /* PREFIX_0F3835 */
4175   {
4176     { Bad_Opcode },
4177     { Bad_Opcode },
4178     { "pmovzxdq", { XM, EXq } },
4179   },
4180
4181   /* PREFIX_0F3837 */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { "pcmpgtq", { XM, EXx } },
4186   },
4187
4188   /* PREFIX_0F3838 */
4189   {
4190     { Bad_Opcode },
4191     { Bad_Opcode },
4192     { "pminsb", { XM, EXx } },
4193   },
4194
4195   /* PREFIX_0F3839 */
4196   {
4197     { Bad_Opcode },
4198     { Bad_Opcode },
4199     { "pminsd", { XM, EXx } },
4200   },
4201
4202   /* PREFIX_0F383A */
4203   {
4204     { Bad_Opcode },
4205     { Bad_Opcode },
4206     { "pminuw", { XM, EXx } },
4207   },
4208
4209   /* PREFIX_0F383B */
4210   {
4211     { Bad_Opcode },
4212     { Bad_Opcode },
4213     { "pminud", { XM, EXx } },
4214   },
4215
4216   /* PREFIX_0F383C */
4217   {
4218     { Bad_Opcode },
4219     { Bad_Opcode },
4220     { "pmaxsb", { XM, EXx } },
4221   },
4222
4223   /* PREFIX_0F383D */
4224   {
4225     { Bad_Opcode },
4226     { Bad_Opcode },
4227     { "pmaxsd", { XM, EXx } },
4228   },
4229
4230   /* PREFIX_0F383E */
4231   {
4232     { Bad_Opcode },
4233     { Bad_Opcode },
4234     { "pmaxuw", { XM, EXx } },
4235   },
4236
4237   /* PREFIX_0F383F */
4238   {
4239     { Bad_Opcode },
4240     { Bad_Opcode },
4241     { "pmaxud", { XM, EXx } },
4242   },
4243
4244   /* PREFIX_0F3840 */
4245   {
4246     { Bad_Opcode },
4247     { Bad_Opcode },
4248     { "pmulld", { XM, EXx } },
4249   },
4250
4251   /* PREFIX_0F3841 */
4252   {
4253     { Bad_Opcode },
4254     { Bad_Opcode },
4255     { "phminposuw", { XM, EXx } },
4256   },
4257
4258   /* PREFIX_0F3880 */
4259   {
4260     { Bad_Opcode },
4261     { Bad_Opcode },
4262     { "invept", { Gm, Mo } },
4263   },
4264
4265   /* PREFIX_0F3881 */
4266   {
4267     { Bad_Opcode },
4268     { Bad_Opcode },
4269     { "invvpid", { Gm, Mo } },
4270   },
4271
4272   /* PREFIX_0F3882 */
4273   {
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { "invpcid", { Gm, M } },
4277   },
4278
4279   /* PREFIX_0F38C8 */
4280   {
4281     { "sha1nexte", { XM, EXxmm } },
4282   },
4283
4284   /* PREFIX_0F38C9 */
4285   {
4286     { "sha1msg1", { XM, EXxmm } },
4287   },
4288
4289   /* PREFIX_0F38CA */
4290   {
4291     { "sha1msg2", { XM, EXxmm } },
4292   },
4293
4294   /* PREFIX_0F38CB */
4295   {
4296     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4297   },
4298
4299   /* PREFIX_0F38CC */
4300   {
4301     { "sha256msg1", { XM, EXxmm } },
4302   },
4303
4304   /* PREFIX_0F38CD */
4305   {
4306     { "sha256msg2", { XM, EXxmm } },
4307   },
4308
4309   /* PREFIX_0F38DB */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "aesimc", { XM, EXx } },
4314   },
4315
4316   /* PREFIX_0F38DC */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "aesenc", { XM, EXx } },
4321   },
4322
4323   /* PREFIX_0F38DD */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "aesenclast", { XM, EXx } },
4328   },
4329
4330   /* PREFIX_0F38DE */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "aesdec", { XM, EXx } },
4335   },
4336
4337   /* PREFIX_0F38DF */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "aesdeclast", { XM, EXx } },
4342   },
4343
4344   /* PREFIX_0F38F0 */
4345   {
4346     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4347     { Bad_Opcode },
4348     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4349     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4350   },
4351
4352   /* PREFIX_0F38F1 */
4353   {
4354     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4355     { Bad_Opcode },
4356     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4357     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4358   },
4359
4360   /* PREFIX_0F38F6 */
4361   {
4362     { Bad_Opcode },
4363     { "adoxS",  { Gdq, Edq} },
4364     { "adcxS",  { Gdq, Edq} },
4365     { Bad_Opcode },
4366   },
4367
4368   /* PREFIX_0F3A08 */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "roundps", { XM, EXx, Ib } },
4373   },
4374
4375   /* PREFIX_0F3A09 */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "roundpd", { XM, EXx, Ib } },
4380   },
4381
4382   /* PREFIX_0F3A0A */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "roundss", { XM, EXd, Ib } },
4387   },
4388
4389   /* PREFIX_0F3A0B */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { "roundsd", { XM, EXq, Ib } },
4394   },
4395
4396   /* PREFIX_0F3A0C */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "blendps", { XM, EXx, Ib } },
4401   },
4402
4403   /* PREFIX_0F3A0D */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "blendpd", { XM, EXx, Ib } },
4408   },
4409
4410   /* PREFIX_0F3A0E */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { "pblendw", { XM, EXx, Ib } },
4415   },
4416
4417   /* PREFIX_0F3A14 */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { "pextrb", { Edqb, XM, Ib } },
4422   },
4423
4424   /* PREFIX_0F3A15 */
4425   {
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { "pextrw", { Edqw, XM, Ib } },
4429   },
4430
4431   /* PREFIX_0F3A16 */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { "pextrK", { Edq, XM, Ib } },
4436   },
4437
4438   /* PREFIX_0F3A17 */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "extractps", { Edqd, XM, Ib } },
4443   },
4444
4445   /* PREFIX_0F3A20 */
4446   {
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { "pinsrb", { XM, Edqb, Ib } },
4450   },
4451
4452   /* PREFIX_0F3A21 */
4453   {
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { "insertps", { XM, EXd, Ib } },
4457   },
4458
4459   /* PREFIX_0F3A22 */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "pinsrK", { XM, Edq, Ib } },
4464   },
4465
4466   /* PREFIX_0F3A40 */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "dpps",   { XM, EXx, Ib } },
4471   },
4472
4473   /* PREFIX_0F3A41 */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "dppd",   { XM, EXx, Ib } },
4478   },
4479
4480   /* PREFIX_0F3A42 */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "mpsadbw", { XM, EXx, Ib } },
4485   },
4486
4487   /* PREFIX_0F3A44 */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "pclmulqdq", { XM, EXx, PCLMUL } },
4492   },
4493
4494   /* PREFIX_0F3A60 */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "pcmpestrm", { XM, EXx, Ib } },
4499   },
4500
4501   /* PREFIX_0F3A61 */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "pcmpestri", { XM, EXx, Ib } },
4506   },
4507
4508   /* PREFIX_0F3A62 */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "pcmpistrm", { XM, EXx, Ib } },
4513   },
4514
4515   /* PREFIX_0F3A63 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "pcmpistri", { XM, EXx, Ib } },
4520   },
4521
4522   /* PREFIX_0F3ACC */
4523   {
4524     { "sha1rnds4", { XM, EXxmm, Ib } },
4525   },
4526
4527   /* PREFIX_0F3ADF */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { "aeskeygenassist", { XM, EXx, Ib } },
4532   },
4533
4534   /* PREFIX_VEX_0F10 */
4535   {
4536     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4537     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4538     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4539     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4540   },
4541
4542   /* PREFIX_VEX_0F11 */
4543   {
4544     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4545     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4546     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4547     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4548   },
4549
4550   /* PREFIX_VEX_0F12 */
4551   {
4552     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4553     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4554     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4555     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4556   },
4557
4558   /* PREFIX_VEX_0F16 */
4559   {
4560     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4561     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4562     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4563   },
4564
4565   /* PREFIX_VEX_0F2A */
4566   {
4567     { Bad_Opcode },
4568     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4569     { Bad_Opcode },
4570     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4571   },
4572
4573   /* PREFIX_VEX_0F2C */
4574   {
4575     { Bad_Opcode },
4576     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4577     { Bad_Opcode },
4578     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4579   },
4580
4581   /* PREFIX_VEX_0F2D */
4582   {
4583     { Bad_Opcode },
4584     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4585     { Bad_Opcode },
4586     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4587   },
4588
4589   /* PREFIX_VEX_0F2E */
4590   {
4591     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4592     { Bad_Opcode },
4593     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4594   },
4595
4596   /* PREFIX_VEX_0F2F */
4597   {
4598     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4599     { Bad_Opcode },
4600     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4601   },
4602
4603   /* PREFIX_VEX_0F41 */
4604   {
4605     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4606     { Bad_Opcode },
4607     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4608   },
4609
4610   /* PREFIX_VEX_0F42 */
4611   {
4612     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4613     { Bad_Opcode },
4614     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4615   },
4616
4617   /* PREFIX_VEX_0F44 */
4618   {
4619     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4620     { Bad_Opcode },
4621     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4622   },
4623
4624   /* PREFIX_VEX_0F45 */
4625   {
4626     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4627     { Bad_Opcode },
4628     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4629   },
4630
4631   /* PREFIX_VEX_0F46 */
4632   {
4633     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4634     { Bad_Opcode },
4635     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4636   },
4637
4638   /* PREFIX_VEX_0F47 */
4639   {
4640     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4641     { Bad_Opcode },
4642     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4643   },
4644
4645   /* PREFIX_VEX_0F4A */
4646   {
4647     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4648     { Bad_Opcode },
4649     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4650   },
4651
4652   /* PREFIX_VEX_0F4B */
4653   {
4654     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4655     { Bad_Opcode },
4656     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4657   },
4658
4659   /* PREFIX_VEX_0F51 */
4660   {
4661     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4662     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4663     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4664     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4665   },
4666
4667   /* PREFIX_VEX_0F52 */
4668   {
4669     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4670     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4671   },
4672
4673   /* PREFIX_VEX_0F53 */
4674   {
4675     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4676     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4677   },
4678
4679   /* PREFIX_VEX_0F58 */
4680   {
4681     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4682     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4683     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4684     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4685   },
4686
4687   /* PREFIX_VEX_0F59 */
4688   {
4689     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4690     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4691     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4692     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4693   },
4694
4695   /* PREFIX_VEX_0F5A */
4696   {
4697     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4698     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4699     { "vcvtpd2ps%XY", { XMM, EXx } },
4700     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4701   },
4702
4703   /* PREFIX_VEX_0F5B */
4704   {
4705     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4706     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4707     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4708   },
4709
4710   /* PREFIX_VEX_0F5C */
4711   {
4712     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4713     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4714     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4715     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4716   },
4717
4718   /* PREFIX_VEX_0F5D */
4719   {
4720     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4721     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4722     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4723     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4724   },
4725
4726   /* PREFIX_VEX_0F5E */
4727   {
4728     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4729     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4730     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4731     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4732   },
4733
4734   /* PREFIX_VEX_0F5F */
4735   {
4736     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4737     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4738     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4739     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4740   },
4741
4742   /* PREFIX_VEX_0F60 */
4743   {
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4747   },
4748
4749   /* PREFIX_VEX_0F61 */
4750   {
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4754   },
4755
4756   /* PREFIX_VEX_0F62 */
4757   {
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4761   },
4762
4763   /* PREFIX_VEX_0F63 */
4764   {
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4768   },
4769
4770   /* PREFIX_VEX_0F64 */
4771   {
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4775   },
4776
4777   /* PREFIX_VEX_0F65 */
4778   {
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4782   },
4783
4784   /* PREFIX_VEX_0F66 */
4785   {
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4789   },
4790
4791   /* PREFIX_VEX_0F67 */
4792   {
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4796   },
4797
4798   /* PREFIX_VEX_0F68 */
4799   {
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4803   },
4804
4805   /* PREFIX_VEX_0F69 */
4806   {
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4810   },
4811
4812   /* PREFIX_VEX_0F6A */
4813   {
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4817   },
4818
4819   /* PREFIX_VEX_0F6B */
4820   {
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4824   },
4825
4826   /* PREFIX_VEX_0F6C */
4827   {
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4831   },
4832
4833   /* PREFIX_VEX_0F6D */
4834   {
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4838   },
4839
4840   /* PREFIX_VEX_0F6E */
4841   {
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4845   },
4846
4847   /* PREFIX_VEX_0F6F */
4848   {
4849     { Bad_Opcode },
4850     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4851     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4852   },
4853
4854   /* PREFIX_VEX_0F70 */
4855   {
4856     { Bad_Opcode },
4857     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4858     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4859     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4860   },
4861
4862   /* PREFIX_VEX_0F71_REG_2 */
4863   {
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4867   },
4868
4869   /* PREFIX_VEX_0F71_REG_4 */
4870   {
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4874   },
4875
4876   /* PREFIX_VEX_0F71_REG_6 */
4877   {
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4881   },
4882
4883   /* PREFIX_VEX_0F72_REG_2 */
4884   {
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4888   },
4889
4890   /* PREFIX_VEX_0F72_REG_4 */
4891   {
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4895   },
4896
4897   /* PREFIX_VEX_0F72_REG_6 */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4902   },
4903
4904   /* PREFIX_VEX_0F73_REG_2 */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4909   },
4910
4911   /* PREFIX_VEX_0F73_REG_3 */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4916   },
4917
4918   /* PREFIX_VEX_0F73_REG_6 */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4923   },
4924
4925   /* PREFIX_VEX_0F73_REG_7 */
4926   {
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4930   },
4931
4932   /* PREFIX_VEX_0F74 */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4937   },
4938
4939   /* PREFIX_VEX_0F75 */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4944   },
4945
4946   /* PREFIX_VEX_0F76 */
4947   {
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4951   },
4952
4953   /* PREFIX_VEX_0F77 */
4954   {
4955     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4956   },
4957
4958   /* PREFIX_VEX_0F7C */
4959   {
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4963     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4964   },
4965
4966   /* PREFIX_VEX_0F7D */
4967   {
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4971     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4972   },
4973
4974   /* PREFIX_VEX_0F7E */
4975   {
4976     { Bad_Opcode },
4977     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4978     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4979   },
4980
4981   /* PREFIX_VEX_0F7F */
4982   {
4983     { Bad_Opcode },
4984     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4985     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4986   },
4987
4988   /* PREFIX_VEX_0F90 */
4989   {
4990     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4991     { Bad_Opcode },
4992     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
4993   },
4994
4995   /* PREFIX_VEX_0F91 */
4996   {
4997     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4998     { Bad_Opcode },
4999     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5000   },
5001
5002   /* PREFIX_VEX_0F92 */
5003   {
5004     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5008   },
5009
5010   /* PREFIX_VEX_0F93 */
5011   {
5012     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5016   },
5017
5018   /* PREFIX_VEX_0F98 */
5019   {
5020     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5021     { Bad_Opcode },
5022     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_0F99 */
5026   {
5027     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5028     { Bad_Opcode },
5029     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_0FC2 */
5033   {
5034     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5035     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5036     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5037     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5038   },
5039
5040   /* PREFIX_VEX_0FC4 */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5045   },
5046
5047   /* PREFIX_VEX_0FC5 */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5052   },
5053
5054   /* PREFIX_VEX_0FD0 */
5055   {
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5059     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5060   },
5061
5062   /* PREFIX_VEX_0FD1 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5067   },
5068
5069   /* PREFIX_VEX_0FD2 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5074   },
5075
5076   /* PREFIX_VEX_0FD3 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5081   },
5082
5083   /* PREFIX_VEX_0FD4 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5088   },
5089
5090   /* PREFIX_VEX_0FD5 */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5095   },
5096
5097   /* PREFIX_VEX_0FD6 */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0FD7 */
5105   {
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5109   },
5110
5111   /* PREFIX_VEX_0FD8 */
5112   {
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0FD9 */
5119   {
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0FDA */
5126   {
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0FDB */
5133   {
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0FDC */
5140   {
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0FDD */
5147   {
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5151   },
5152
5153   /* PREFIX_VEX_0FDE */
5154   {
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5158   },
5159
5160   /* PREFIX_VEX_0FDF */
5161   {
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5165   },
5166
5167   /* PREFIX_VEX_0FE0 */
5168   {
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5172   },
5173
5174   /* PREFIX_VEX_0FE1 */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5179   },
5180
5181   /* PREFIX_VEX_0FE2 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5186   },
5187
5188   /* PREFIX_VEX_0FE3 */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5193   },
5194
5195   /* PREFIX_VEX_0FE4 */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5200   },
5201
5202   /* PREFIX_VEX_0FE5 */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5207   },
5208
5209   /* PREFIX_VEX_0FE6 */
5210   {
5211     { Bad_Opcode },
5212     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5213     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5214     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5215   },
5216
5217   /* PREFIX_VEX_0FE7 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5222   },
5223
5224   /* PREFIX_VEX_0FE8 */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5229   },
5230
5231   /* PREFIX_VEX_0FE9 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5236   },
5237
5238   /* PREFIX_VEX_0FEA */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5243   },
5244
5245   /* PREFIX_VEX_0FEB */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5250   },
5251
5252   /* PREFIX_VEX_0FEC */
5253   {
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5257   },
5258
5259   /* PREFIX_VEX_0FED */
5260   {
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5264   },
5265
5266   /* PREFIX_VEX_0FEE */
5267   {
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5271   },
5272
5273   /* PREFIX_VEX_0FEF */
5274   {
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5278   },
5279
5280   /* PREFIX_VEX_0FF0 */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5286   },
5287
5288   /* PREFIX_VEX_0FF1 */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5293   },
5294
5295   /* PREFIX_VEX_0FF2 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5300   },
5301
5302   /* PREFIX_VEX_0FF3 */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5307   },
5308
5309   /* PREFIX_VEX_0FF4 */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5314   },
5315
5316   /* PREFIX_VEX_0FF5 */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5321   },
5322
5323   /* PREFIX_VEX_0FF6 */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5328   },
5329
5330   /* PREFIX_VEX_0FF7 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5335   },
5336
5337   /* PREFIX_VEX_0FF8 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5342   },
5343
5344   /* PREFIX_VEX_0FF9 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0FFA */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5356   },
5357
5358   /* PREFIX_VEX_0FFB */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5363   },
5364
5365   /* PREFIX_VEX_0FFC */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5370   },
5371
5372   /* PREFIX_VEX_0FFD */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5377   },
5378
5379   /* PREFIX_VEX_0FFE */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5384   },
5385
5386   /* PREFIX_VEX_0F3800 */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5391   },
5392
5393   /* PREFIX_VEX_0F3801 */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5398   },
5399
5400   /* PREFIX_VEX_0F3802 */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5405   },
5406
5407   /* PREFIX_VEX_0F3803 */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5412   },
5413
5414   /* PREFIX_VEX_0F3804 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5419   },
5420
5421   /* PREFIX_VEX_0F3805 */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5426   },
5427
5428   /* PREFIX_VEX_0F3806 */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5433   },
5434
5435   /* PREFIX_VEX_0F3807 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5440   },
5441
5442   /* PREFIX_VEX_0F3808 */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5447   },
5448
5449   /* PREFIX_VEX_0F3809 */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5454   },
5455
5456   /* PREFIX_VEX_0F380A */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5461   },
5462
5463   /* PREFIX_VEX_0F380B */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5468   },
5469
5470   /* PREFIX_VEX_0F380C */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5475   },
5476
5477   /* PREFIX_VEX_0F380D */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5482   },
5483
5484   /* PREFIX_VEX_0F380E */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5489   },
5490
5491   /* PREFIX_VEX_0F380F */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5496   },
5497
5498   /* PREFIX_VEX_0F3813 */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { "vcvtph2ps", { XM, EXxmmq } },
5503   },
5504
5505   /* PREFIX_VEX_0F3816 */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5510   },
5511
5512   /* PREFIX_VEX_0F3817 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5517   },
5518
5519   /* PREFIX_VEX_0F3818 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5524   },
5525
5526   /* PREFIX_VEX_0F3819 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5531   },
5532
5533   /* PREFIX_VEX_0F381A */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5538   },
5539
5540   /* PREFIX_VEX_0F381C */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5545   },
5546
5547   /* PREFIX_VEX_0F381D */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5552   },
5553
5554   /* PREFIX_VEX_0F381E */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5559   },
5560
5561   /* PREFIX_VEX_0F3820 */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5566   },
5567
5568   /* PREFIX_VEX_0F3821 */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5573   },
5574
5575   /* PREFIX_VEX_0F3822 */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5580   },
5581
5582   /* PREFIX_VEX_0F3823 */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0F3824 */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5594   },
5595
5596   /* PREFIX_VEX_0F3825 */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0F3828 */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5608   },
5609
5610   /* PREFIX_VEX_0F3829 */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5615   },
5616
5617   /* PREFIX_VEX_0F382A */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5622   },
5623
5624   /* PREFIX_VEX_0F382B */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5629   },
5630
5631   /* PREFIX_VEX_0F382C */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5636   },
5637
5638   /* PREFIX_VEX_0F382D */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5643   },
5644
5645   /* PREFIX_VEX_0F382E */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5650   },
5651
5652   /* PREFIX_VEX_0F382F */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5657   },
5658
5659   /* PREFIX_VEX_0F3830 */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5664   },
5665
5666   /* PREFIX_VEX_0F3831 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5671   },
5672
5673   /* PREFIX_VEX_0F3832 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5678   },
5679
5680   /* PREFIX_VEX_0F3833 */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5685   },
5686
5687   /* PREFIX_VEX_0F3834 */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5692   },
5693
5694   /* PREFIX_VEX_0F3835 */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5699   },
5700
5701   /* PREFIX_VEX_0F3836 */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5706   },
5707
5708   /* PREFIX_VEX_0F3837 */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5713   },
5714
5715   /* PREFIX_VEX_0F3838 */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5720   },
5721
5722   /* PREFIX_VEX_0F3839 */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5727   },
5728
5729   /* PREFIX_VEX_0F383A */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5734   },
5735
5736   /* PREFIX_VEX_0F383B */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5741   },
5742
5743   /* PREFIX_VEX_0F383C */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5748   },
5749
5750   /* PREFIX_VEX_0F383D */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5755   },
5756
5757   /* PREFIX_VEX_0F383E */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5762   },
5763
5764   /* PREFIX_VEX_0F383F */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5769   },
5770
5771   /* PREFIX_VEX_0F3840 */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5776   },
5777
5778   /* PREFIX_VEX_0F3841 */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5783   },
5784
5785   /* PREFIX_VEX_0F3845 */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { "vpsrlv%LW", { XM, Vex, EXx } },
5790   },
5791
5792   /* PREFIX_VEX_0F3846 */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5797   },
5798
5799   /* PREFIX_VEX_0F3847 */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { "vpsllv%LW", { XM, Vex, EXx } },
5804   },
5805
5806   /* PREFIX_VEX_0F3858 */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5811   },
5812
5813   /* PREFIX_VEX_0F3859 */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5818   },
5819
5820   /* PREFIX_VEX_0F385A */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5825   },
5826
5827   /* PREFIX_VEX_0F3878 */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5832   },
5833
5834   /* PREFIX_VEX_0F3879 */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5839   },
5840
5841   /* PREFIX_VEX_0F388C */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5846   },
5847
5848   /* PREFIX_VEX_0F388E */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5853   },
5854
5855   /* PREFIX_VEX_0F3890 */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5860   },
5861
5862   /* PREFIX_VEX_0F3891 */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5867   },
5868
5869   /* PREFIX_VEX_0F3892 */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5874   },
5875
5876   /* PREFIX_VEX_0F3893 */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5881   },
5882
5883   /* PREFIX_VEX_0F3896 */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5888   },
5889
5890   /* PREFIX_VEX_0F3897 */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5895   },
5896
5897   /* PREFIX_VEX_0F3898 */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { "vfmadd132p%XW", { XM, Vex, EXx } },
5902   },
5903
5904   /* PREFIX_VEX_0F3899 */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5909   },
5910
5911   /* PREFIX_VEX_0F389A */
5912   {
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { "vfmsub132p%XW", { XM, Vex, EXx } },
5916   },
5917
5918   /* PREFIX_VEX_0F389B */
5919   {
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5923   },
5924
5925   /* PREFIX_VEX_0F389C */
5926   {
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5930   },
5931
5932   /* PREFIX_VEX_0F389D */
5933   {
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5937   },
5938
5939   /* PREFIX_VEX_0F389E */
5940   {
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5944   },
5945
5946   /* PREFIX_VEX_0F389F */
5947   {
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5951   },
5952
5953   /* PREFIX_VEX_0F38A6 */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5958     { Bad_Opcode },
5959   },
5960
5961   /* PREFIX_VEX_0F38A7 */
5962   {
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5966   },
5967
5968   /* PREFIX_VEX_0F38A8 */
5969   {
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { "vfmadd213p%XW", { XM, Vex, EXx } },
5973   },
5974
5975   /* PREFIX_VEX_0F38A9 */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5980   },
5981
5982   /* PREFIX_VEX_0F38AA */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { "vfmsub213p%XW", { XM, Vex, EXx } },
5987   },
5988
5989   /* PREFIX_VEX_0F38AB */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5994   },
5995
5996   /* PREFIX_VEX_0F38AC */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { "vfnmadd213p%XW", { XM, Vex, EXx } },
6001   },
6002
6003   /* PREFIX_VEX_0F38AD */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6008   },
6009
6010   /* PREFIX_VEX_0F38AE */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { "vfnmsub213p%XW", { XM, Vex, EXx } },
6015   },
6016
6017   /* PREFIX_VEX_0F38AF */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6022   },
6023
6024   /* PREFIX_VEX_0F38B6 */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
6029   },
6030
6031   /* PREFIX_VEX_0F38B7 */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
6036   },
6037
6038   /* PREFIX_VEX_0F38B8 */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { "vfmadd231p%XW", { XM, Vex, EXx } },
6043   },
6044
6045   /* PREFIX_VEX_0F38B9 */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6050   },
6051
6052   /* PREFIX_VEX_0F38BA */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { "vfmsub231p%XW", { XM, Vex, EXx } },
6057   },
6058
6059   /* PREFIX_VEX_0F38BB */
6060   {
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6064   },
6065
6066   /* PREFIX_VEX_0F38BC */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { "vfnmadd231p%XW", { XM, Vex, EXx } },
6071   },
6072
6073   /* PREFIX_VEX_0F38BD */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6078   },
6079
6080   /* PREFIX_VEX_0F38BE */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vfnmsub231p%XW", { XM, Vex, EXx } },
6085   },
6086
6087   /* PREFIX_VEX_0F38BF */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6092   },
6093
6094   /* PREFIX_VEX_0F38DB */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6099   },
6100
6101   /* PREFIX_VEX_0F38DC */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6106   },
6107
6108   /* PREFIX_VEX_0F38DD */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6113   },
6114
6115   /* PREFIX_VEX_0F38DE */
6116   {
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6120   },
6121
6122   /* PREFIX_VEX_0F38DF */
6123   {
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6127   },
6128
6129   /* PREFIX_VEX_0F38F2 */
6130   {
6131     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6132   },
6133
6134   /* PREFIX_VEX_0F38F3_REG_1 */
6135   {
6136     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6137   },
6138
6139   /* PREFIX_VEX_0F38F3_REG_2 */
6140   {
6141     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6142   },
6143
6144   /* PREFIX_VEX_0F38F3_REG_3 */
6145   {
6146     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6147   },
6148
6149   /* PREFIX_VEX_0F38F5 */
6150   {
6151     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6152     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6153     { Bad_Opcode },
6154     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6155   },
6156
6157   /* PREFIX_VEX_0F38F6 */
6158   {
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6163   },
6164
6165   /* PREFIX_VEX_0F38F7 */
6166   {
6167     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6168     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6169     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6170     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6171   },
6172
6173   /* PREFIX_VEX_0F3A00 */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6178   },
6179
6180   /* PREFIX_VEX_0F3A01 */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6185   },
6186
6187   /* PREFIX_VEX_0F3A02 */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6192   },
6193
6194   /* PREFIX_VEX_0F3A04 */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6199   },
6200
6201   /* PREFIX_VEX_0F3A05 */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6206   },
6207
6208   /* PREFIX_VEX_0F3A06 */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6213   },
6214
6215   /* PREFIX_VEX_0F3A08 */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6220   },
6221
6222   /* PREFIX_VEX_0F3A09 */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6227   },
6228
6229   /* PREFIX_VEX_0F3A0A */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6234   },
6235
6236   /* PREFIX_VEX_0F3A0B */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6241   },
6242
6243   /* PREFIX_VEX_0F3A0C */
6244   {
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6248   },
6249
6250   /* PREFIX_VEX_0F3A0D */
6251   {
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6255   },
6256
6257   /* PREFIX_VEX_0F3A0E */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6262   },
6263
6264   /* PREFIX_VEX_0F3A0F */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6269   },
6270
6271   /* PREFIX_VEX_0F3A14 */
6272   {
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6276   },
6277
6278   /* PREFIX_VEX_0F3A15 */
6279   {
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6283   },
6284
6285   /* PREFIX_VEX_0F3A16 */
6286   {
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6290   },
6291
6292   /* PREFIX_VEX_0F3A17 */
6293   {
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6297   },
6298
6299   /* PREFIX_VEX_0F3A18 */
6300   {
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6304   },
6305
6306   /* PREFIX_VEX_0F3A19 */
6307   {
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6311   },
6312
6313   /* PREFIX_VEX_0F3A1D */
6314   {
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6318   },
6319
6320   /* PREFIX_VEX_0F3A20 */
6321   {
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6325   },
6326
6327   /* PREFIX_VEX_0F3A21 */
6328   {
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6332   },
6333
6334   /* PREFIX_VEX_0F3A22 */
6335   {
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6339   },
6340
6341   /* PREFIX_VEX_0F3A30 */
6342   {
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6346   },
6347
6348   /* PREFIX_VEX_0F3A31 */
6349   {
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6353   },
6354
6355   /* PREFIX_VEX_0F3A32 */
6356   {
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6360   },
6361
6362   /* PREFIX_VEX_0F3A33 */
6363   {
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6367   },
6368
6369   /* PREFIX_VEX_0F3A38 */
6370   {
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6374   },
6375
6376   /* PREFIX_VEX_0F3A39 */
6377   {
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6381   },
6382
6383   /* PREFIX_VEX_0F3A40 */
6384   {
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6388   },
6389
6390   /* PREFIX_VEX_0F3A41 */
6391   {
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6395   },
6396
6397   /* PREFIX_VEX_0F3A42 */
6398   {
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6402   },
6403
6404   /* PREFIX_VEX_0F3A44 */
6405   {
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6409   },
6410
6411   /* PREFIX_VEX_0F3A46 */
6412   {
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6416   },
6417
6418   /* PREFIX_VEX_0F3A48 */
6419   {
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6423   },
6424
6425   /* PREFIX_VEX_0F3A49 */
6426   {
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6430   },
6431
6432   /* PREFIX_VEX_0F3A4A */
6433   {
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6437   },
6438
6439   /* PREFIX_VEX_0F3A4B */
6440   {
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6444   },
6445
6446   /* PREFIX_VEX_0F3A4C */
6447   {
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6451   },
6452
6453   /* PREFIX_VEX_0F3A5C */
6454   {
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6458   },
6459
6460   /* PREFIX_VEX_0F3A5D */
6461   {
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6465   },
6466
6467   /* PREFIX_VEX_0F3A5E */
6468   {
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6472   },
6473
6474   /* PREFIX_VEX_0F3A5F */
6475   {
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6479   },
6480
6481   /* PREFIX_VEX_0F3A60 */
6482   {
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6486     { Bad_Opcode },
6487   },
6488
6489   /* PREFIX_VEX_0F3A61 */
6490   {
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6494   },
6495
6496   /* PREFIX_VEX_0F3A62 */
6497   {
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6501   },
6502
6503   /* PREFIX_VEX_0F3A63 */
6504   {
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6508   },
6509
6510   /* PREFIX_VEX_0F3A68 */
6511   {
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6515   },
6516
6517   /* PREFIX_VEX_0F3A69 */
6518   {
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6522   },
6523
6524   /* PREFIX_VEX_0F3A6A */
6525   {
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6529   },
6530
6531   /* PREFIX_VEX_0F3A6B */
6532   {
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6536   },
6537
6538   /* PREFIX_VEX_0F3A6C */
6539   {
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6543   },
6544
6545   /* PREFIX_VEX_0F3A6D */
6546   {
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6550   },
6551
6552   /* PREFIX_VEX_0F3A6E */
6553   {
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6557   },
6558
6559   /* PREFIX_VEX_0F3A6F */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6564   },
6565
6566   /* PREFIX_VEX_0F3A78 */
6567   {
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6571   },
6572
6573   /* PREFIX_VEX_0F3A79 */
6574   {
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6578   },
6579
6580   /* PREFIX_VEX_0F3A7A */
6581   {
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6585   },
6586
6587   /* PREFIX_VEX_0F3A7B */
6588   {
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6592   },
6593
6594   /* PREFIX_VEX_0F3A7C */
6595   {
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6599     { Bad_Opcode },
6600   },
6601
6602   /* PREFIX_VEX_0F3A7D */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6607   },
6608
6609   /* PREFIX_VEX_0F3A7E */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6614   },
6615
6616   /* PREFIX_VEX_0F3A7F */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6621   },
6622
6623   /* PREFIX_VEX_0F3ADF */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6628   },
6629
6630   /* PREFIX_VEX_0F3AF0 */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6636   },
6637
6638 #define NEED_PREFIX_TABLE
6639 #include "i386-dis-evex.h"
6640 #undef NEED_PREFIX_TABLE
6641 };
6642
6643 static const struct dis386 x86_64_table[][2] = {
6644   /* X86_64_06 */
6645   {
6646     { "pushP", { es } },
6647   },
6648
6649   /* X86_64_07 */
6650   {
6651     { "popP", { es } },
6652   },
6653
6654   /* X86_64_0D */
6655   {
6656     { "pushP", { cs } },
6657   },
6658
6659   /* X86_64_16 */
6660   {
6661     { "pushP", { ss } },
6662   },
6663
6664   /* X86_64_17 */
6665   {
6666     { "popP", { ss } },
6667   },
6668
6669   /* X86_64_1E */
6670   {
6671     { "pushP", { ds } },
6672   },
6673
6674   /* X86_64_1F */
6675   {
6676     { "popP", { ds } },
6677   },
6678
6679   /* X86_64_27 */
6680   {
6681     { "daa", { XX } },
6682   },
6683
6684   /* X86_64_2F */
6685   {
6686     { "das", { XX } },
6687   },
6688
6689   /* X86_64_37 */
6690   {
6691     { "aaa", { XX } },
6692   },
6693
6694   /* X86_64_3F */
6695   {
6696     { "aas", { XX } },
6697   },
6698
6699   /* X86_64_60 */
6700   {
6701     { "pushaP", { XX } },
6702   },
6703
6704   /* X86_64_61 */
6705   {
6706     { "popaP", { XX } },
6707   },
6708
6709   /* X86_64_62 */
6710   {
6711     { MOD_TABLE (MOD_62_32BIT) },
6712     { EVEX_TABLE (EVEX_0F) },
6713   },
6714
6715   /* X86_64_63 */
6716   {
6717     { "arpl", { Ew, Gw } },
6718     { "movs{lq|xd}", { Gv, Ed } },
6719   },
6720
6721   /* X86_64_6D */
6722   {
6723     { "ins{R|}", { Yzr, indirDX } },
6724     { "ins{G|}", { Yzr, indirDX } },
6725   },
6726
6727   /* X86_64_6F */
6728   {
6729     { "outs{R|}", { indirDXr, Xz } },
6730     { "outs{G|}", { indirDXr, Xz } },
6731   },
6732
6733   /* X86_64_9A */
6734   {
6735     { "Jcall{T|}", { Ap } },
6736   },
6737
6738   /* X86_64_C4 */
6739   {
6740     { MOD_TABLE (MOD_C4_32BIT) },
6741     { VEX_C4_TABLE (VEX_0F) },
6742   },
6743
6744   /* X86_64_C5 */
6745   {
6746     { MOD_TABLE (MOD_C5_32BIT) },
6747     { VEX_C5_TABLE (VEX_0F) },
6748   },
6749
6750   /* X86_64_CE */
6751   {
6752     { "into", { XX } },
6753   },
6754
6755   /* X86_64_D4 */
6756   {
6757     { "aam", { Ib } },
6758   },
6759
6760   /* X86_64_D5 */
6761   {
6762     { "aad", { Ib } },
6763   },
6764
6765   /* X86_64_EA */
6766   {
6767     { "Jjmp{T|}", { Ap } },
6768   },
6769
6770   /* X86_64_0F01_REG_0 */
6771   {
6772     { "sgdt{Q|IQ}", { M } },
6773     { "sgdt", { M } },
6774   },
6775
6776   /* X86_64_0F01_REG_1 */
6777   {
6778     { "sidt{Q|IQ}", { M } },
6779     { "sidt", { M } },
6780   },
6781
6782   /* X86_64_0F01_REG_2 */
6783   {
6784     { "lgdt{Q|Q}", { M } },
6785     { "lgdt", { M } },
6786   },
6787
6788   /* X86_64_0F01_REG_3 */
6789   {
6790     { "lidt{Q|Q}", { M } },
6791     { "lidt", { M } },
6792   },
6793 };
6794
6795 static const struct dis386 three_byte_table[][256] = {
6796
6797   /* THREE_BYTE_0F38 */
6798   {
6799     /* 00 */
6800     { "pshufb",         { MX, EM } },
6801     { "phaddw",         { MX, EM } },
6802     { "phaddd",         { MX, EM } },
6803     { "phaddsw",        { MX, EM } },
6804     { "pmaddubsw",      { MX, EM } },
6805     { "phsubw",         { MX, EM } },
6806     { "phsubd",         { MX, EM } },
6807     { "phsubsw",        { MX, EM } },
6808     /* 08 */
6809     { "psignb",         { MX, EM } },
6810     { "psignw",         { MX, EM } },
6811     { "psignd",         { MX, EM } },
6812     { "pmulhrsw",       { MX, EM } },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     /* 10 */
6818     { PREFIX_TABLE (PREFIX_0F3810) },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { PREFIX_TABLE (PREFIX_0F3814) },
6823     { PREFIX_TABLE (PREFIX_0F3815) },
6824     { Bad_Opcode },
6825     { PREFIX_TABLE (PREFIX_0F3817) },
6826     /* 18 */
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { "pabsb",          { MX, EM } },
6832     { "pabsw",          { MX, EM } },
6833     { "pabsd",          { MX, EM } },
6834     { Bad_Opcode },
6835     /* 20 */
6836     { PREFIX_TABLE (PREFIX_0F3820) },
6837     { PREFIX_TABLE (PREFIX_0F3821) },
6838     { PREFIX_TABLE (PREFIX_0F3822) },
6839     { PREFIX_TABLE (PREFIX_0F3823) },
6840     { PREFIX_TABLE (PREFIX_0F3824) },
6841     { PREFIX_TABLE (PREFIX_0F3825) },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     /* 28 */
6845     { PREFIX_TABLE (PREFIX_0F3828) },
6846     { PREFIX_TABLE (PREFIX_0F3829) },
6847     { PREFIX_TABLE (PREFIX_0F382A) },
6848     { PREFIX_TABLE (PREFIX_0F382B) },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     /* 30 */
6854     { PREFIX_TABLE (PREFIX_0F3830) },
6855     { PREFIX_TABLE (PREFIX_0F3831) },
6856     { PREFIX_TABLE (PREFIX_0F3832) },
6857     { PREFIX_TABLE (PREFIX_0F3833) },
6858     { PREFIX_TABLE (PREFIX_0F3834) },
6859     { PREFIX_TABLE (PREFIX_0F3835) },
6860     { Bad_Opcode },
6861     { PREFIX_TABLE (PREFIX_0F3837) },
6862     /* 38 */
6863     { PREFIX_TABLE (PREFIX_0F3838) },
6864     { PREFIX_TABLE (PREFIX_0F3839) },
6865     { PREFIX_TABLE (PREFIX_0F383A) },
6866     { PREFIX_TABLE (PREFIX_0F383B) },
6867     { PREFIX_TABLE (PREFIX_0F383C) },
6868     { PREFIX_TABLE (PREFIX_0F383D) },
6869     { PREFIX_TABLE (PREFIX_0F383E) },
6870     { PREFIX_TABLE (PREFIX_0F383F) },
6871     /* 40 */
6872     { PREFIX_TABLE (PREFIX_0F3840) },
6873     { PREFIX_TABLE (PREFIX_0F3841) },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     /* 48 */
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     /* 50 */
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     /* 58 */
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     /* 60 */
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     /* 68 */
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     /* 70 */
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     /* 78 */
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     /* 80 */
6944     { PREFIX_TABLE (PREFIX_0F3880) },
6945     { PREFIX_TABLE (PREFIX_0F3881) },
6946     { PREFIX_TABLE (PREFIX_0F3882) },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* 88 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 90 */
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* 98 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* a0 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* a8 */
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* b0 */
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* b8 */
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* c0 */
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* c8 */
7025     { PREFIX_TABLE (PREFIX_0F38C8) },
7026     { PREFIX_TABLE (PREFIX_0F38C9) },
7027     { PREFIX_TABLE (PREFIX_0F38CA) },
7028     { PREFIX_TABLE (PREFIX_0F38CB) },
7029     { PREFIX_TABLE (PREFIX_0F38CC) },
7030     { PREFIX_TABLE (PREFIX_0F38CD) },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* d0 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* d8 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { PREFIX_TABLE (PREFIX_0F38DB) },
7047     { PREFIX_TABLE (PREFIX_0F38DC) },
7048     { PREFIX_TABLE (PREFIX_0F38DD) },
7049     { PREFIX_TABLE (PREFIX_0F38DE) },
7050     { PREFIX_TABLE (PREFIX_0F38DF) },
7051     /* e0 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* e8 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* f0 */
7070     { PREFIX_TABLE (PREFIX_0F38F0) },
7071     { PREFIX_TABLE (PREFIX_0F38F1) },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { PREFIX_TABLE (PREFIX_0F38F6) },
7077     { Bad_Opcode },
7078     /* f8 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087   },
7088   /* THREE_BYTE_0F3A */
7089   {
7090     /* 00 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* 08 */
7100     { PREFIX_TABLE (PREFIX_0F3A08) },
7101     { PREFIX_TABLE (PREFIX_0F3A09) },
7102     { PREFIX_TABLE (PREFIX_0F3A0A) },
7103     { PREFIX_TABLE (PREFIX_0F3A0B) },
7104     { PREFIX_TABLE (PREFIX_0F3A0C) },
7105     { PREFIX_TABLE (PREFIX_0F3A0D) },
7106     { PREFIX_TABLE (PREFIX_0F3A0E) },
7107     { "palignr",        { MX, EM, Ib } },
7108     /* 10 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { PREFIX_TABLE (PREFIX_0F3A14) },
7114     { PREFIX_TABLE (PREFIX_0F3A15) },
7115     { PREFIX_TABLE (PREFIX_0F3A16) },
7116     { PREFIX_TABLE (PREFIX_0F3A17) },
7117     /* 18 */
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* 20 */
7127     { PREFIX_TABLE (PREFIX_0F3A20) },
7128     { PREFIX_TABLE (PREFIX_0F3A21) },
7129     { PREFIX_TABLE (PREFIX_0F3A22) },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* 28 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* 30 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* 38 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* 40 */
7163     { PREFIX_TABLE (PREFIX_0F3A40) },
7164     { PREFIX_TABLE (PREFIX_0F3A41) },
7165     { PREFIX_TABLE (PREFIX_0F3A42) },
7166     { Bad_Opcode },
7167     { PREFIX_TABLE (PREFIX_0F3A44) },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* 48 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* 50 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* 58 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* 60 */
7199     { PREFIX_TABLE (PREFIX_0F3A60) },
7200     { PREFIX_TABLE (PREFIX_0F3A61) },
7201     { PREFIX_TABLE (PREFIX_0F3A62) },
7202     { PREFIX_TABLE (PREFIX_0F3A63) },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* 68 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* 70 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* 78 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* 80 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* 88 */
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* 90 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* 98 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* a0 */
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* a8 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* b0 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* b8 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* c0 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* c8 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { PREFIX_TABLE (PREFIX_0F3ACC) },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* d0 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* d8 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { PREFIX_TABLE (PREFIX_0F3ADF) },
7342     /* e0 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* e8 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* f0 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* f8 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378   },
7379
7380   /* THREE_BYTE_0F7A */
7381   {
7382     /* 00 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* 08 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* 10 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* 18 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     /* 20 */
7419     { "ptest",          { XX } },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     /* 28 */
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     /* 30 */
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     /* 38 */
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     /* 40 */
7455     { Bad_Opcode },
7456     { "phaddbw",        { XM, EXq } },
7457     { "phaddbd",        { XM, EXq } },
7458     { "phaddbq",        { XM, EXq } },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { "phaddwd",        { XM, EXq } },
7462     { "phaddwq",        { XM, EXq } },
7463     /* 48 */
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { "phadddq",        { XM, EXq } },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     /* 50 */
7473     { Bad_Opcode },
7474     { "phaddubw",       { XM, EXq } },
7475     { "phaddubd",       { XM, EXq } },
7476     { "phaddubq",       { XM, EXq } },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { "phadduwd",       { XM, EXq } },
7480     { "phadduwq",       { XM, EXq } },
7481     /* 58 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { "phaddudq",       { XM, EXq } },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* 60 */
7491     { Bad_Opcode },
7492     { "phsubbw",        { XM, EXq } },
7493     { "phsubbd",        { XM, EXq } },
7494     { "phsubbq",        { XM, EXq } },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     /* 68 */
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     /* 70 */
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     /* 78 */
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     /* 80 */
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     /* 88 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* 90 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* 98 */
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* a0 */
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     /* a8 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     /* b0 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* b8 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* c0 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* c8 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* d0 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* d8 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* e0 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* e8 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* f0 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* f8 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670   },
7671 };
7672
7673 static const struct dis386 xop_table[][256] = {
7674   /* XOP_08 */
7675   {
7676     /* 00 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* 08 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* 10 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     /* 18 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     /* 20 */
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     /* 28 */
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     /* 30 */
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     /* 38 */
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     /* 40 */
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     /* 48 */
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     /* 50 */
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     /* 58 */
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     /* 60 */
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     /* 68 */
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     /* 70 */
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     /* 78 */
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     /* 80 */
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7827     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7828     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7829     /* 88 */
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7837     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7838     /* 90 */
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7845     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7846     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7847     /* 98 */
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7855     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7856     /* a0 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7860     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7864     { Bad_Opcode },
7865     /* a8 */
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     /* b0 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7882     { Bad_Opcode },
7883     /* b8 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     /* c0 */
7893     { "vprotb",         { XM, Vex_2src_1, Ib } },
7894     { "vprotw",         { XM, Vex_2src_1, Ib } },
7895     { "vprotd",         { XM, Vex_2src_1, Ib } },
7896     { "vprotq",         { XM, Vex_2src_1, Ib } },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     /* c8 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7907     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7908     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7909     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7910     /* d0 */
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     /* d8 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     /* e0 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     /* e8 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7943     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7944     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7945     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7946     /* f0 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* f8 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964   },
7965   /* XOP_09 */
7966   {
7967     /* 00 */
7968     { Bad_Opcode },
7969     { REG_TABLE (REG_XOP_TBM_01) },
7970     { REG_TABLE (REG_XOP_TBM_02) },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* 08 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     /* 10 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { REG_TABLE (REG_XOP_LWPCB) },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* 18 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     /* 20 */
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     /* 28 */
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     /* 30 */
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* 38 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     /* 40 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     /* 48 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     /* 50 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     /* 58 */
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     /* 60 */
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     /* 68 */
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     /* 70 */
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     /* 78 */
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     /* 80 */
8112     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8113     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8114     { "vfrczss",        { XM, EXd } },
8115     { "vfrczsd",        { XM, EXq } },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     /* 88 */
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     /* 90 */
8130     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
8131     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
8132     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
8133     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
8134     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
8135     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
8136     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
8137     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
8138     /* 98 */
8139     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
8140     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
8141     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
8142     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     /* a0 */
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     /* a8 */
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     /* b0 */
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     /* b8 */
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     /* c0 */
8184     { Bad_Opcode },
8185     { "vphaddbw",       { XM, EXxmm } },
8186     { "vphaddbd",       { XM, EXxmm } },
8187     { "vphaddbq",       { XM, EXxmm } },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { "vphaddwd",       { XM, EXxmm } },
8191     { "vphaddwq",       { XM, EXxmm } },
8192     /* c8 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { "vphadddq",       { XM, EXxmm } },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* d0 */
8202     { Bad_Opcode },
8203     { "vphaddubw",      { XM, EXxmm } },
8204     { "vphaddubd",      { XM, EXxmm } },
8205     { "vphaddubq",      { XM, EXxmm } },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { "vphadduwd",      { XM, EXxmm } },
8209     { "vphadduwq",      { XM, EXxmm } },
8210     /* d8 */
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { "vphaddudq",      { XM, EXxmm } },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* e0 */
8220     { Bad_Opcode },
8221     { "vphsubbw",       { XM, EXxmm } },
8222     { "vphsubwd",       { XM, EXxmm } },
8223     { "vphsubdq",       { XM, EXxmm } },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* e8 */
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     /* f0 */
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* f8 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255   },
8256   /* XOP_0A */
8257   {
8258     /* 00 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* 08 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* 10 */
8277     { "bextr",  { Gv, Ev, Iq } },
8278     { Bad_Opcode },
8279     { REG_TABLE (REG_XOP_LWP) },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* 18 */
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     /* 20 */
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     /* 28 */
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     /* 30 */
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     /* 38 */
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     /* 40 */
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     /* 48 */
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     /* 50 */
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     /* 58 */
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     /* 60 */
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     /* 68 */
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     /* 70 */
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     /* 78 */
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     /* 80 */
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     /* 88 */
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     /* 90 */
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     /* 98 */
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     /* a0 */
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     /* a8 */
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     /* b0 */
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     /* b8 */
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     /* c0 */
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     /* c8 */
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     /* d0 */
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     /* d8 */
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     /* e0 */
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     /* e8 */
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     /* f0 */
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     /* f8 */
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546   },
8547 };
8548
8549 static const struct dis386 vex_table[][256] = {
8550   /* VEX_0F */
8551   {
8552     /* 00 */
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     /* 08 */
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     /* 10 */
8571     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8572     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8574     { MOD_TABLE (MOD_VEX_0F13) },
8575     { VEX_W_TABLE (VEX_W_0F14) },
8576     { VEX_W_TABLE (VEX_W_0F15) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8578     { MOD_TABLE (MOD_VEX_0F17) },
8579     /* 18 */
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     /* 20 */
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     /* 28 */
8598     { VEX_W_TABLE (VEX_W_0F28) },
8599     { VEX_W_TABLE (VEX_W_0F29) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8601     { MOD_TABLE (MOD_VEX_0F2B) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8606     /* 30 */
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     /* 38 */
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     /* 40 */
8625     { Bad_Opcode },
8626     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8628     { Bad_Opcode },
8629     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8633     /* 48 */
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     /* 50 */
8643     { MOD_TABLE (MOD_VEX_0F50) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8647     { "vandpX",         { XM, Vex, EXx } },
8648     { "vandnpX",        { XM, Vex, EXx } },
8649     { "vorpX",          { XM, Vex, EXx } },
8650     { "vxorpX",         { XM, Vex, EXx } },
8651     /* 58 */
8652     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8660     /* 60 */
8661     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8669     /* 68 */
8670     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8677     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8678     /* 70 */
8679     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8680     { REG_TABLE (REG_VEX_0F71) },
8681     { REG_TABLE (REG_VEX_0F72) },
8682     { REG_TABLE (REG_VEX_0F73) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8686     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8687     /* 78 */
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8696     /* 80 */
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     /* 88 */
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     /* 90 */
8715     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     /* 98 */
8724     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     /* a0 */
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     /* a8 */
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { REG_TABLE (REG_VEX_0FAE) },
8749     { Bad_Opcode },
8750     /* b0 */
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     /* b8 */
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     /* c0 */
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8772     { Bad_Opcode },
8773     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8774     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8775     { "vshufpX",        { XM, Vex, EXx, Ib } },
8776     { Bad_Opcode },
8777     /* c8 */
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     /* d0 */
8787     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8788     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8789     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8790     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8791     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8792     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8793     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8794     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8795     /* d8 */
8796     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8797     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8798     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8799     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8800     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8801     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8802     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8803     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8804     /* e0 */
8805     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8806     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8807     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8808     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8809     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8810     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8811     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8812     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8813     /* e8 */
8814     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8815     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8816     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8817     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8818     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8819     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8820     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8821     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8822     /* f0 */
8823     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8824     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8825     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8826     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8827     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8828     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8829     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8830     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8831     /* f8 */
8832     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8833     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8834     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8835     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8836     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8837     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8838     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8839     { Bad_Opcode },
8840   },
8841   /* VEX_0F38 */
8842   {
8843     /* 00 */
8844     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8845     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8852     /* 08 */
8853     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8854     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8861     /* 10 */
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8870     /* 18 */
8871     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8874     { Bad_Opcode },
8875     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8878     { Bad_Opcode },
8879     /* 20 */
8880     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     /* 28 */
8889     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8897     /* 30 */
8898     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8906     /* 38 */
8907     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8915     /* 40 */
8916     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8924     /* 48 */
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     /* 50 */
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     /* 58 */
8943     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     /* 60 */
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     /* 68 */
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     /* 70 */
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     /* 78 */
8979     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     /* 80 */
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     /* 88 */
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9002     { Bad_Opcode },
9003     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9004     { Bad_Opcode },
9005     /* 90 */
9006     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9014     /* 98 */
9015     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9023     /* a0 */
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9032     /* a8 */
9033     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9041     /* b0 */
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9050     /* b8 */
9051     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9059     /* c0 */
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     /* c8 */
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     /* d0 */
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     /* d8 */
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9095     /* e0 */
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     /* e8 */
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     /* f0 */
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9117     { REG_TABLE (REG_VEX_0F38F3) },
9118     { Bad_Opcode },
9119     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9122     /* f8 */
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131   },
9132   /* VEX_0F3A */
9133   {
9134     /* 00 */
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9138     { Bad_Opcode },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9142     { Bad_Opcode },
9143     /* 08 */
9144     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9152     /* 10 */
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9161     /* 18 */
9162     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9163     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     /* 20 */
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     /* 28 */
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     /* 30 */
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     /* 38 */
9198     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     /* 40 */
9207     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9208     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9209     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9210     { Bad_Opcode },
9211     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9212     { Bad_Opcode },
9213     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9214     { Bad_Opcode },
9215     /* 48 */
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9218     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9219     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     /* 50 */
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     /* 58 */
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9240     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9242     /* 60 */
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     /* 68 */
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9254     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9255     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9256     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9257     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9258     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9259     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9260     /* 70 */
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     /* 78 */
9270     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9271     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9272     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9273     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9274     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9275     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9276     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9277     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9278     /* 80 */
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     /* 88 */
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     /* 90 */
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     /* 98 */
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     /* a0 */
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     /* a8 */
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     /* b0 */
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     /* b8 */
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     /* c0 */
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     /* c8 */
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     /* d0 */
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     /* d8 */
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9386     /* e0 */
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     /* e8 */
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     /* f0 */
9405     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     /* f8 */
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422   },
9423 };
9424
9425 #define NEED_OPCODE_TABLE
9426 #include "i386-dis-evex.h"
9427 #undef NEED_OPCODE_TABLE
9428 static const struct dis386 vex_len_table[][2] = {
9429   /* VEX_LEN_0F10_P_1 */
9430   {
9431     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9432     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9433   },
9434
9435   /* VEX_LEN_0F10_P_3 */
9436   {
9437     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9438     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9439   },
9440
9441   /* VEX_LEN_0F11_P_1 */
9442   {
9443     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9444     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9445   },
9446
9447   /* VEX_LEN_0F11_P_3 */
9448   {
9449     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9450     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9451   },
9452
9453   /* VEX_LEN_0F12_P_0_M_0 */
9454   {
9455     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9456   },
9457
9458   /* VEX_LEN_0F12_P_0_M_1 */
9459   {
9460     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9461   },
9462
9463   /* VEX_LEN_0F12_P_2 */
9464   {
9465     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9466   },
9467
9468   /* VEX_LEN_0F13_M_0 */
9469   {
9470     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9471   },
9472
9473   /* VEX_LEN_0F16_P_0_M_0 */
9474   {
9475     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9476   },
9477
9478   /* VEX_LEN_0F16_P_0_M_1 */
9479   {
9480     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9481   },
9482
9483   /* VEX_LEN_0F16_P_2 */
9484   {
9485     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9486   },
9487
9488   /* VEX_LEN_0F17_M_0 */
9489   {
9490     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9491   },
9492
9493   /* VEX_LEN_0F2A_P_1 */
9494   {
9495     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9496     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9497   },
9498
9499   /* VEX_LEN_0F2A_P_3 */
9500   {
9501     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9502     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9503   },
9504
9505   /* VEX_LEN_0F2C_P_1 */
9506   {
9507     { "vcvttss2siY",    { Gv, EXdScalar } },
9508     { "vcvttss2siY",    { Gv, EXdScalar } },
9509   },
9510
9511   /* VEX_LEN_0F2C_P_3 */
9512   {
9513     { "vcvttsd2siY",    { Gv, EXqScalar } },
9514     { "vcvttsd2siY",    { Gv, EXqScalar } },
9515   },
9516
9517   /* VEX_LEN_0F2D_P_1 */
9518   {
9519     { "vcvtss2siY",     { Gv, EXdScalar } },
9520     { "vcvtss2siY",     { Gv, EXdScalar } },
9521   },
9522
9523   /* VEX_LEN_0F2D_P_3 */
9524   {
9525     { "vcvtsd2siY",     { Gv, EXqScalar } },
9526     { "vcvtsd2siY",     { Gv, EXqScalar } },
9527   },
9528
9529   /* VEX_LEN_0F2E_P_0 */
9530   {
9531     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9532     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9533   },
9534
9535   /* VEX_LEN_0F2E_P_2 */
9536   {
9537     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9538     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9539   },
9540
9541   /* VEX_LEN_0F2F_P_0 */
9542   {
9543     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9544     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9545   },
9546
9547   /* VEX_LEN_0F2F_P_2 */
9548   {
9549     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9550     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9551   },
9552
9553   /* VEX_LEN_0F41_P_0 */
9554   {
9555     { Bad_Opcode },
9556     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9557   },
9558   /* VEX_LEN_0F41_P_2 */
9559   {
9560     { Bad_Opcode },
9561     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9562   },
9563   /* VEX_LEN_0F42_P_0 */
9564   {
9565     { Bad_Opcode },
9566     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9567   },
9568   /* VEX_LEN_0F42_P_2 */
9569   {
9570     { Bad_Opcode },
9571     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9572   },
9573   /* VEX_LEN_0F44_P_0 */
9574   {
9575     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9576   },
9577   /* VEX_LEN_0F44_P_2 */
9578   {
9579     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9580   },
9581   /* VEX_LEN_0F45_P_0 */
9582   {
9583     { Bad_Opcode },
9584     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9585   },
9586   /* VEX_LEN_0F45_P_2 */
9587   {
9588     { Bad_Opcode },
9589     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9590   },
9591   /* VEX_LEN_0F46_P_0 */
9592   {
9593     { Bad_Opcode },
9594     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9595   },
9596   /* VEX_LEN_0F46_P_2 */
9597   {
9598     { Bad_Opcode },
9599     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9600   },
9601   /* VEX_LEN_0F47_P_0 */
9602   {
9603     { Bad_Opcode },
9604     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9605   },
9606   /* VEX_LEN_0F47_P_2 */
9607   {
9608     { Bad_Opcode },
9609     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9610   },
9611   /* VEX_LEN_0F4A_P_0 */
9612   {
9613     { Bad_Opcode },
9614     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9615   },
9616   /* VEX_LEN_0F4A_P_2 */
9617   {
9618     { Bad_Opcode },
9619     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9620   },
9621   /* VEX_LEN_0F4B_P_0 */
9622   {
9623     { Bad_Opcode },
9624     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9625   },
9626   /* VEX_LEN_0F4B_P_2 */
9627   {
9628     { Bad_Opcode },
9629     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9630   },
9631
9632   /* VEX_LEN_0F51_P_1 */
9633   {
9634     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9635     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9636   },
9637
9638   /* VEX_LEN_0F51_P_3 */
9639   {
9640     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9641     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9642   },
9643
9644   /* VEX_LEN_0F52_P_1 */
9645   {
9646     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9647     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9648   },
9649
9650   /* VEX_LEN_0F53_P_1 */
9651   {
9652     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9653     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9654   },
9655
9656   /* VEX_LEN_0F58_P_1 */
9657   {
9658     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9659     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9660   },
9661
9662   /* VEX_LEN_0F58_P_3 */
9663   {
9664     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9665     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9666   },
9667
9668   /* VEX_LEN_0F59_P_1 */
9669   {
9670     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9671     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9672   },
9673
9674   /* VEX_LEN_0F59_P_3 */
9675   {
9676     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9677     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9678   },
9679
9680   /* VEX_LEN_0F5A_P_1 */
9681   {
9682     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9683     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9684   },
9685
9686   /* VEX_LEN_0F5A_P_3 */
9687   {
9688     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9689     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9690   },
9691
9692   /* VEX_LEN_0F5C_P_1 */
9693   {
9694     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9695     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9696   },
9697
9698   /* VEX_LEN_0F5C_P_3 */
9699   {
9700     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9701     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9702   },
9703
9704   /* VEX_LEN_0F5D_P_1 */
9705   {
9706     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9707     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9708   },
9709
9710   /* VEX_LEN_0F5D_P_3 */
9711   {
9712     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9713     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9714   },
9715
9716   /* VEX_LEN_0F5E_P_1 */
9717   {
9718     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9719     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9720   },
9721
9722   /* VEX_LEN_0F5E_P_3 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9725     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9726   },
9727
9728   /* VEX_LEN_0F5F_P_1 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9731     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9732   },
9733
9734   /* VEX_LEN_0F5F_P_3 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9737     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9738   },
9739
9740   /* VEX_LEN_0F6E_P_2 */
9741   {
9742     { "vmovK",          { XMScalar, Edq } },
9743     { "vmovK",          { XMScalar, Edq } },
9744   },
9745
9746   /* VEX_LEN_0F7E_P_1 */
9747   {
9748     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9749     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9750   },
9751
9752   /* VEX_LEN_0F7E_P_2 */
9753   {
9754     { "vmovK",          { Edq, XMScalar } },
9755     { "vmovK",          { Edq, XMScalar } },
9756   },
9757
9758   /* VEX_LEN_0F90_P_0 */
9759   {
9760     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9761   },
9762
9763   /* VEX_LEN_0F90_P_2 */
9764   {
9765     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9766   },
9767
9768   /* VEX_LEN_0F91_P_0 */
9769   {
9770     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9771   },
9772
9773   /* VEX_LEN_0F91_P_2 */
9774   {
9775     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9776   },
9777
9778   /* VEX_LEN_0F92_P_0 */
9779   {
9780     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9781   },
9782
9783   /* VEX_LEN_0F92_P_3 */
9784   {
9785     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9786   },
9787
9788   /* VEX_LEN_0F93_P_0 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9791   },
9792
9793   /* VEX_LEN_0F93_P_3 */
9794   {
9795     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9796   },
9797
9798   /* VEX_LEN_0F98_P_0 */
9799   {
9800     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9801   },
9802
9803   /* VEX_LEN_0F98_P_2 */
9804   {
9805     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9806   },
9807
9808   /* VEX_LEN_0F99_P_0 */
9809   {
9810     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9811   },
9812
9813   /* VEX_LEN_0F99_P_2 */
9814   {
9815     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9816   },
9817
9818   /* VEX_LEN_0FAE_R_2_M_0 */
9819   {
9820     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9821   },
9822
9823   /* VEX_LEN_0FAE_R_3_M_0 */
9824   {
9825     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9826   },
9827
9828   /* VEX_LEN_0FC2_P_1 */
9829   {
9830     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9831     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9832   },
9833
9834   /* VEX_LEN_0FC2_P_3 */
9835   {
9836     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9837     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9838   },
9839
9840   /* VEX_LEN_0FC4_P_2 */
9841   {
9842     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9843   },
9844
9845   /* VEX_LEN_0FC5_P_2 */
9846   {
9847     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9848   },
9849
9850   /* VEX_LEN_0FD6_P_2 */
9851   {
9852     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9853     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9854   },
9855
9856   /* VEX_LEN_0FF7_P_2 */
9857   {
9858     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9859   },
9860
9861   /* VEX_LEN_0F3816_P_2 */
9862   {
9863     { Bad_Opcode },
9864     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9865   },
9866
9867   /* VEX_LEN_0F3819_P_2 */
9868   {
9869     { Bad_Opcode },
9870     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9871   },
9872
9873   /* VEX_LEN_0F381A_P_2_M_0 */
9874   {
9875     { Bad_Opcode },
9876     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9877   },
9878
9879   /* VEX_LEN_0F3836_P_2 */
9880   {
9881     { Bad_Opcode },
9882     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9883   },
9884
9885   /* VEX_LEN_0F3841_P_2 */
9886   {
9887     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9888   },
9889
9890   /* VEX_LEN_0F385A_P_2_M_0 */
9891   {
9892     { Bad_Opcode },
9893     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9894   },
9895
9896   /* VEX_LEN_0F38DB_P_2 */
9897   {
9898     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9899   },
9900
9901   /* VEX_LEN_0F38DC_P_2 */
9902   {
9903     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9904   },
9905
9906   /* VEX_LEN_0F38DD_P_2 */
9907   {
9908     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9909   },
9910
9911   /* VEX_LEN_0F38DE_P_2 */
9912   {
9913     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9914   },
9915
9916   /* VEX_LEN_0F38DF_P_2 */
9917   {
9918     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9919   },
9920
9921   /* VEX_LEN_0F38F2_P_0 */
9922   {
9923     { "andnS",          { Gdq, VexGdq, Edq } },
9924   },
9925
9926   /* VEX_LEN_0F38F3_R_1_P_0 */
9927   {
9928     { "blsrS",          { VexGdq, Edq } },
9929   },
9930
9931   /* VEX_LEN_0F38F3_R_2_P_0 */
9932   {
9933     { "blsmskS",        { VexGdq, Edq } },
9934   },
9935
9936   /* VEX_LEN_0F38F3_R_3_P_0 */
9937   {
9938     { "blsiS",          { VexGdq, Edq } },
9939   },
9940
9941   /* VEX_LEN_0F38F5_P_0 */
9942   {
9943     { "bzhiS",          { Gdq, Edq, VexGdq } },
9944   },
9945
9946   /* VEX_LEN_0F38F5_P_1 */
9947   {
9948     { "pextS",          { Gdq, VexGdq, Edq } },
9949   },
9950
9951   /* VEX_LEN_0F38F5_P_3 */
9952   {
9953     { "pdepS",          { Gdq, VexGdq, Edq } },
9954   },
9955
9956   /* VEX_LEN_0F38F6_P_3 */
9957   {
9958     { "mulxS",          { Gdq, VexGdq, Edq } },
9959   },
9960
9961   /* VEX_LEN_0F38F7_P_0 */
9962   {
9963     { "bextrS",         { Gdq, Edq, VexGdq } },
9964   },
9965
9966   /* VEX_LEN_0F38F7_P_1 */
9967   {
9968     { "sarxS",          { Gdq, Edq, VexGdq } },
9969   },
9970
9971   /* VEX_LEN_0F38F7_P_2 */
9972   {
9973     { "shlxS",          { Gdq, Edq, VexGdq } },
9974   },
9975
9976   /* VEX_LEN_0F38F7_P_3 */
9977   {
9978     { "shrxS",          { Gdq, Edq, VexGdq } },
9979   },
9980
9981   /* VEX_LEN_0F3A00_P_2 */
9982   {
9983     { Bad_Opcode },
9984     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9985   },
9986
9987   /* VEX_LEN_0F3A01_P_2 */
9988   {
9989     { Bad_Opcode },
9990     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9991   },
9992
9993   /* VEX_LEN_0F3A06_P_2 */
9994   {
9995     { Bad_Opcode },
9996     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9997   },
9998
9999   /* VEX_LEN_0F3A0A_P_2 */
10000   {
10001     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10002     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10003   },
10004
10005   /* VEX_LEN_0F3A0B_P_2 */
10006   {
10007     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10008     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10009   },
10010
10011   /* VEX_LEN_0F3A14_P_2 */
10012   {
10013     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10014   },
10015
10016   /* VEX_LEN_0F3A15_P_2 */
10017   {
10018     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10019   },
10020
10021   /* VEX_LEN_0F3A16_P_2  */
10022   {
10023     { "vpextrK",        { Edq, XM, Ib } },
10024   },
10025
10026   /* VEX_LEN_0F3A17_P_2 */
10027   {
10028     { "vextractps",     { Edqd, XM, Ib } },
10029   },
10030
10031   /* VEX_LEN_0F3A18_P_2 */
10032   {
10033     { Bad_Opcode },
10034     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10035   },
10036
10037   /* VEX_LEN_0F3A19_P_2 */
10038   {
10039     { Bad_Opcode },
10040     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10041   },
10042
10043   /* VEX_LEN_0F3A20_P_2 */
10044   {
10045     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10046   },
10047
10048   /* VEX_LEN_0F3A21_P_2 */
10049   {
10050     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10051   },
10052
10053   /* VEX_LEN_0F3A22_P_2 */
10054   {
10055     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
10056   },
10057
10058   /* VEX_LEN_0F3A30_P_2 */
10059   {
10060     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10061   },
10062
10063   /* VEX_LEN_0F3A31_P_2 */
10064   {
10065     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10066   },
10067
10068   /* VEX_LEN_0F3A32_P_2 */
10069   {
10070     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10071   },
10072
10073   /* VEX_LEN_0F3A33_P_2 */
10074   {
10075     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10076   },
10077
10078   /* VEX_LEN_0F3A38_P_2 */
10079   {
10080     { Bad_Opcode },
10081     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10082   },
10083
10084   /* VEX_LEN_0F3A39_P_2 */
10085   {
10086     { Bad_Opcode },
10087     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10088   },
10089
10090   /* VEX_LEN_0F3A41_P_2 */
10091   {
10092     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10093   },
10094
10095   /* VEX_LEN_0F3A44_P_2 */
10096   {
10097     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10098   },
10099
10100   /* VEX_LEN_0F3A46_P_2 */
10101   {
10102     { Bad_Opcode },
10103     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10104   },
10105
10106   /* VEX_LEN_0F3A60_P_2 */
10107   {
10108     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10109   },
10110
10111   /* VEX_LEN_0F3A61_P_2 */
10112   {
10113     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10114   },
10115
10116   /* VEX_LEN_0F3A62_P_2 */
10117   {
10118     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10119   },
10120
10121   /* VEX_LEN_0F3A63_P_2 */
10122   {
10123     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10124   },
10125
10126   /* VEX_LEN_0F3A6A_P_2 */
10127   {
10128     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10129   },
10130
10131   /* VEX_LEN_0F3A6B_P_2 */
10132   {
10133     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10134   },
10135
10136   /* VEX_LEN_0F3A6E_P_2 */
10137   {
10138     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10139   },
10140
10141   /* VEX_LEN_0F3A6F_P_2 */
10142   {
10143     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10144   },
10145
10146   /* VEX_LEN_0F3A7A_P_2 */
10147   {
10148     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10149   },
10150
10151   /* VEX_LEN_0F3A7B_P_2 */
10152   {
10153     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10154   },
10155
10156   /* VEX_LEN_0F3A7E_P_2 */
10157   {
10158     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10159   },
10160
10161   /* VEX_LEN_0F3A7F_P_2 */
10162   {
10163     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10164   },
10165
10166   /* VEX_LEN_0F3ADF_P_2 */
10167   {
10168     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10169   },
10170
10171   /* VEX_LEN_0F3AF0_P_3 */
10172   {
10173     { "rorxS",          { Gdq, Edq, Ib } },
10174   },
10175
10176   /* VEX_LEN_0FXOP_08_CC */
10177   {
10178      { "vpcomb",        { XM, Vex128, EXx, Ib } },
10179   },
10180
10181   /* VEX_LEN_0FXOP_08_CD */
10182   {
10183      { "vpcomw",        { XM, Vex128, EXx, Ib } },
10184   },
10185
10186   /* VEX_LEN_0FXOP_08_CE */
10187   {
10188      { "vpcomd",        { XM, Vex128, EXx, Ib } },
10189   },
10190
10191   /* VEX_LEN_0FXOP_08_CF */
10192   {
10193      { "vpcomq",        { XM, Vex128, EXx, Ib } },
10194   },
10195
10196   /* VEX_LEN_0FXOP_08_EC */
10197   {
10198      { "vpcomub",       { XM, Vex128, EXx, Ib } },
10199   },
10200
10201   /* VEX_LEN_0FXOP_08_ED */
10202   {
10203      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
10204   },
10205
10206   /* VEX_LEN_0FXOP_08_EE */
10207   {
10208      { "vpcomud",       { XM, Vex128, EXx, Ib } },
10209   },
10210
10211   /* VEX_LEN_0FXOP_08_EF */
10212   {
10213      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
10214   },
10215
10216   /* VEX_LEN_0FXOP_09_80 */
10217   {
10218     { "vfrczps",        { XM, EXxmm } },
10219     { "vfrczps",        { XM, EXymmq } },
10220   },
10221
10222   /* VEX_LEN_0FXOP_09_81 */
10223   {
10224     { "vfrczpd",        { XM, EXxmm } },
10225     { "vfrczpd",        { XM, EXymmq } },
10226   },
10227 };
10228
10229 static const struct dis386 vex_w_table[][2] = {
10230   {
10231     /* VEX_W_0F10_P_0 */
10232     { "vmovups",        { XM, EXx } },
10233   },
10234   {
10235     /* VEX_W_0F10_P_1 */
10236     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
10237   },
10238   {
10239     /* VEX_W_0F10_P_2 */
10240     { "vmovupd",        { XM, EXx } },
10241   },
10242   {
10243     /* VEX_W_0F10_P_3 */
10244     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
10245   },
10246   {
10247     /* VEX_W_0F11_P_0 */
10248     { "vmovups",        { EXxS, XM } },
10249   },
10250   {
10251     /* VEX_W_0F11_P_1 */
10252     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
10253   },
10254   {
10255     /* VEX_W_0F11_P_2 */
10256     { "vmovupd",        { EXxS, XM } },
10257   },
10258   {
10259     /* VEX_W_0F11_P_3 */
10260     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
10261   },
10262   {
10263     /* VEX_W_0F12_P_0_M_0 */
10264     { "vmovlps",        { XM, Vex128, EXq } },
10265   },
10266   {
10267     /* VEX_W_0F12_P_0_M_1 */
10268     { "vmovhlps",       { XM, Vex128, EXq } },
10269   },
10270   {
10271     /* VEX_W_0F12_P_1 */
10272     { "vmovsldup",      { XM, EXx } },
10273   },
10274   {
10275     /* VEX_W_0F12_P_2 */
10276     { "vmovlpd",        { XM, Vex128, EXq } },
10277   },
10278   {
10279     /* VEX_W_0F12_P_3 */
10280     { "vmovddup",       { XM, EXymmq } },
10281   },
10282   {
10283     /* VEX_W_0F13_M_0 */
10284     { "vmovlpX",        { EXq, XM } },
10285   },
10286   {
10287     /* VEX_W_0F14 */
10288     { "vunpcklpX",      { XM, Vex, EXx } },
10289   },
10290   {
10291     /* VEX_W_0F15 */
10292     { "vunpckhpX",      { XM, Vex, EXx } },
10293   },
10294   {
10295     /* VEX_W_0F16_P_0_M_0 */
10296     { "vmovhps",        { XM, Vex128, EXq } },
10297   },
10298   {
10299     /* VEX_W_0F16_P_0_M_1 */
10300     { "vmovlhps",       { XM, Vex128, EXq } },
10301   },
10302   {
10303     /* VEX_W_0F16_P_1 */
10304     { "vmovshdup",      { XM, EXx } },
10305   },
10306   {
10307     /* VEX_W_0F16_P_2 */
10308     { "vmovhpd",        { XM, Vex128, EXq } },
10309   },
10310   {
10311     /* VEX_W_0F17_M_0 */
10312     { "vmovhpX",        { EXq, XM } },
10313   },
10314   {
10315     /* VEX_W_0F28 */
10316     { "vmovapX",        { XM, EXx } },
10317   },
10318   {
10319     /* VEX_W_0F29 */
10320     { "vmovapX",        { EXxS, XM } },
10321   },
10322   {
10323     /* VEX_W_0F2B_M_0 */
10324     { "vmovntpX",       { Mx, XM } },
10325   },
10326   {
10327     /* VEX_W_0F2E_P_0 */
10328     { "vucomiss",       { XMScalar, EXdScalar } },
10329   },
10330   {
10331     /* VEX_W_0F2E_P_2 */
10332     { "vucomisd",       { XMScalar, EXqScalar } },
10333   },
10334   {
10335     /* VEX_W_0F2F_P_0 */
10336     { "vcomiss",        { XMScalar, EXdScalar } },
10337   },
10338   {
10339     /* VEX_W_0F2F_P_2 */
10340     { "vcomisd",        { XMScalar, EXqScalar } },
10341   },
10342   {
10343     /* VEX_W_0F41_P_0_LEN_1 */
10344     { "kandw",          { MaskG, MaskVex, MaskR } },
10345     { "kandq",          { MaskG, MaskVex, MaskR } },
10346   },
10347   {
10348     /* VEX_W_0F41_P_2_LEN_1 */
10349     { Bad_Opcode },
10350     { "kandd",          { MaskG, MaskVex, MaskR } },
10351   },
10352   {
10353     /* VEX_W_0F42_P_0_LEN_1 */
10354     { "kandnw",         { MaskG, MaskVex, MaskR } },
10355     { "kandnq",         { MaskG, MaskVex, MaskR } },
10356   },
10357   {
10358     /* VEX_W_0F42_P_2_LEN_1 */
10359     { Bad_Opcode },
10360     { "kandnd",         { MaskG, MaskVex, MaskR } },
10361   },
10362   {
10363     /* VEX_W_0F44_P_0_LEN_0 */
10364     { "knotw",          { MaskG, MaskR } },
10365     { "knotq",          { MaskG, MaskR } },
10366   },
10367   {
10368     /* VEX_W_0F44_P_2_LEN_0 */
10369     { Bad_Opcode },
10370     { "knotd",          { MaskG, MaskR } },
10371   },
10372   {
10373     /* VEX_W_0F45_P_0_LEN_1 */
10374     { "korw",           { MaskG, MaskVex, MaskR } },
10375     { "korq",           { MaskG, MaskVex, MaskR } },
10376   },
10377   {
10378     /* VEX_W_0F45_P_2_LEN_1 */
10379     { Bad_Opcode },
10380     { "kord",           { MaskG, MaskVex, MaskR } },
10381   },
10382   {
10383     /* VEX_W_0F46_P_0_LEN_1 */
10384     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10385     { "kxnorq",         { MaskG, MaskVex, MaskR } },
10386   },
10387   {
10388     /* VEX_W_0F46_P_2_LEN_1 */
10389     { Bad_Opcode },
10390     { "kxnord",         { MaskG, MaskVex, MaskR } },
10391   },
10392   {
10393     /* VEX_W_0F47_P_0_LEN_1 */
10394     { "kxorw",          { MaskG, MaskVex, MaskR } },
10395     { "kxorq",          { MaskG, MaskVex, MaskR } },
10396   },
10397   {
10398     /* VEX_W_0F47_P_2_LEN_1 */
10399     { Bad_Opcode },
10400     { "kxord",          { MaskG, MaskVex, MaskR } },
10401   },
10402   {
10403     /* VEX_W_0F4A_P_0_LEN_1 */
10404     { "kaddw",          { MaskG, MaskVex, MaskR } },
10405     { "kaddq",          { MaskG, MaskVex, MaskR } },
10406   },
10407   {
10408     /* VEX_W_0F4A_P_2_LEN_1 */
10409     { Bad_Opcode },
10410     { "kaddd",          { MaskG, MaskVex, MaskR } },
10411   },
10412   {
10413     /* VEX_W_0F4B_P_0_LEN_1 */
10414     { "kunpckwd",       { MaskG, MaskVex, MaskR } },
10415     { "kunpckdq",       { MaskG, MaskVex, MaskR } },
10416   },
10417   {
10418     /* VEX_W_0F4B_P_2_LEN_1 */
10419     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10420   },
10421   {
10422     /* VEX_W_0F50_M_0 */
10423     { "vmovmskpX",      { Gdq, XS } },
10424   },
10425   {
10426     /* VEX_W_0F51_P_0 */
10427     { "vsqrtps",        { XM, EXx } },
10428   },
10429   {
10430     /* VEX_W_0F51_P_1 */
10431     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10432   },
10433   {
10434     /* VEX_W_0F51_P_2  */
10435     { "vsqrtpd",        { XM, EXx } },
10436   },
10437   {
10438     /* VEX_W_0F51_P_3 */
10439     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10440   },
10441   {
10442     /* VEX_W_0F52_P_0 */
10443     { "vrsqrtps",       { XM, EXx } },
10444   },
10445   {
10446     /* VEX_W_0F52_P_1 */
10447     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10448   },
10449   {
10450     /* VEX_W_0F53_P_0  */
10451     { "vrcpps",         { XM, EXx } },
10452   },
10453   {
10454     /* VEX_W_0F53_P_1  */
10455     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10456   },
10457   {
10458     /* VEX_W_0F58_P_0  */
10459     { "vaddps",         { XM, Vex, EXx } },
10460   },
10461   {
10462     /* VEX_W_0F58_P_1  */
10463     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10464   },
10465   {
10466     /* VEX_W_0F58_P_2  */
10467     { "vaddpd",         { XM, Vex, EXx } },
10468   },
10469   {
10470     /* VEX_W_0F58_P_3  */
10471     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10472   },
10473   {
10474     /* VEX_W_0F59_P_0  */
10475     { "vmulps",         { XM, Vex, EXx } },
10476   },
10477   {
10478     /* VEX_W_0F59_P_1  */
10479     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10480   },
10481   {
10482     /* VEX_W_0F59_P_2  */
10483     { "vmulpd",         { XM, Vex, EXx } },
10484   },
10485   {
10486     /* VEX_W_0F59_P_3  */
10487     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10488   },
10489   {
10490     /* VEX_W_0F5A_P_0  */
10491     { "vcvtps2pd",      { XM, EXxmmq } },
10492   },
10493   {
10494     /* VEX_W_0F5A_P_1  */
10495     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10496   },
10497   {
10498     /* VEX_W_0F5A_P_3  */
10499     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10500   },
10501   {
10502     /* VEX_W_0F5B_P_0  */
10503     { "vcvtdq2ps",      { XM, EXx } },
10504   },
10505   {
10506     /* VEX_W_0F5B_P_1  */
10507     { "vcvttps2dq",     { XM, EXx } },
10508   },
10509   {
10510     /* VEX_W_0F5B_P_2  */
10511     { "vcvtps2dq",      { XM, EXx } },
10512   },
10513   {
10514     /* VEX_W_0F5C_P_0  */
10515     { "vsubps",         { XM, Vex, EXx } },
10516   },
10517   {
10518     /* VEX_W_0F5C_P_1  */
10519     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10520   },
10521   {
10522     /* VEX_W_0F5C_P_2  */
10523     { "vsubpd",         { XM, Vex, EXx } },
10524   },
10525   {
10526     /* VEX_W_0F5C_P_3  */
10527     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10528   },
10529   {
10530     /* VEX_W_0F5D_P_0  */
10531     { "vminps",         { XM, Vex, EXx } },
10532   },
10533   {
10534     /* VEX_W_0F5D_P_1  */
10535     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10536   },
10537   {
10538     /* VEX_W_0F5D_P_2  */
10539     { "vminpd",         { XM, Vex, EXx } },
10540   },
10541   {
10542     /* VEX_W_0F5D_P_3  */
10543     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10544   },
10545   {
10546     /* VEX_W_0F5E_P_0  */
10547     { "vdivps",         { XM, Vex, EXx } },
10548   },
10549   {
10550     /* VEX_W_0F5E_P_1  */
10551     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10552   },
10553   {
10554     /* VEX_W_0F5E_P_2  */
10555     { "vdivpd",         { XM, Vex, EXx } },
10556   },
10557   {
10558     /* VEX_W_0F5E_P_3  */
10559     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10560   },
10561   {
10562     /* VEX_W_0F5F_P_0  */
10563     { "vmaxps",         { XM, Vex, EXx } },
10564   },
10565   {
10566     /* VEX_W_0F5F_P_1  */
10567     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10568   },
10569   {
10570     /* VEX_W_0F5F_P_2  */
10571     { "vmaxpd",         { XM, Vex, EXx } },
10572   },
10573   {
10574     /* VEX_W_0F5F_P_3  */
10575     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10576   },
10577   {
10578     /* VEX_W_0F60_P_2  */
10579     { "vpunpcklbw",     { XM, Vex, EXx } },
10580   },
10581   {
10582     /* VEX_W_0F61_P_2  */
10583     { "vpunpcklwd",     { XM, Vex, EXx } },
10584   },
10585   {
10586     /* VEX_W_0F62_P_2  */
10587     { "vpunpckldq",     { XM, Vex, EXx } },
10588   },
10589   {
10590     /* VEX_W_0F63_P_2  */
10591     { "vpacksswb",      { XM, Vex, EXx } },
10592   },
10593   {
10594     /* VEX_W_0F64_P_2  */
10595     { "vpcmpgtb",       { XM, Vex, EXx } },
10596   },
10597   {
10598     /* VEX_W_0F65_P_2  */
10599     { "vpcmpgtw",       { XM, Vex, EXx } },
10600   },
10601   {
10602     /* VEX_W_0F66_P_2  */
10603     { "vpcmpgtd",       { XM, Vex, EXx } },
10604   },
10605   {
10606     /* VEX_W_0F67_P_2  */
10607     { "vpackuswb",      { XM, Vex, EXx } },
10608   },
10609   {
10610     /* VEX_W_0F68_P_2  */
10611     { "vpunpckhbw",     { XM, Vex, EXx } },
10612   },
10613   {
10614     /* VEX_W_0F69_P_2  */
10615     { "vpunpckhwd",     { XM, Vex, EXx } },
10616   },
10617   {
10618     /* VEX_W_0F6A_P_2  */
10619     { "vpunpckhdq",     { XM, Vex, EXx } },
10620   },
10621   {
10622     /* VEX_W_0F6B_P_2  */
10623     { "vpackssdw",      { XM, Vex, EXx } },
10624   },
10625   {
10626     /* VEX_W_0F6C_P_2  */
10627     { "vpunpcklqdq",    { XM, Vex, EXx } },
10628   },
10629   {
10630     /* VEX_W_0F6D_P_2  */
10631     { "vpunpckhqdq",    { XM, Vex, EXx } },
10632   },
10633   {
10634     /* VEX_W_0F6F_P_1  */
10635     { "vmovdqu",        { XM, EXx } },
10636   },
10637   {
10638     /* VEX_W_0F6F_P_2  */
10639     { "vmovdqa",        { XM, EXx } },
10640   },
10641   {
10642     /* VEX_W_0F70_P_1 */
10643     { "vpshufhw",       { XM, EXx, Ib } },
10644   },
10645   {
10646     /* VEX_W_0F70_P_2 */
10647     { "vpshufd",        { XM, EXx, Ib } },
10648   },
10649   {
10650     /* VEX_W_0F70_P_3 */
10651     { "vpshuflw",       { XM, EXx, Ib } },
10652   },
10653   {
10654     /* VEX_W_0F71_R_2_P_2  */
10655     { "vpsrlw",         { Vex, XS, Ib } },
10656   },
10657   {
10658     /* VEX_W_0F71_R_4_P_2  */
10659     { "vpsraw",         { Vex, XS, Ib } },
10660   },
10661   {
10662     /* VEX_W_0F71_R_6_P_2  */
10663     { "vpsllw",         { Vex, XS, Ib } },
10664   },
10665   {
10666     /* VEX_W_0F72_R_2_P_2  */
10667     { "vpsrld",         { Vex, XS, Ib } },
10668   },
10669   {
10670     /* VEX_W_0F72_R_4_P_2  */
10671     { "vpsrad",         { Vex, XS, Ib } },
10672   },
10673   {
10674     /* VEX_W_0F72_R_6_P_2  */
10675     { "vpslld",         { Vex, XS, Ib } },
10676   },
10677   {
10678     /* VEX_W_0F73_R_2_P_2  */
10679     { "vpsrlq",         { Vex, XS, Ib } },
10680   },
10681   {
10682     /* VEX_W_0F73_R_3_P_2  */
10683     { "vpsrldq",        { Vex, XS, Ib } },
10684   },
10685   {
10686     /* VEX_W_0F73_R_6_P_2  */
10687     { "vpsllq",         { Vex, XS, Ib } },
10688   },
10689   {
10690     /* VEX_W_0F73_R_7_P_2  */
10691     { "vpslldq",        { Vex, XS, Ib } },
10692   },
10693   {
10694     /* VEX_W_0F74_P_2 */
10695     { "vpcmpeqb",       { XM, Vex, EXx } },
10696   },
10697   {
10698     /* VEX_W_0F75_P_2 */
10699     { "vpcmpeqw",       { XM, Vex, EXx } },
10700   },
10701   {
10702     /* VEX_W_0F76_P_2 */
10703     { "vpcmpeqd",       { XM, Vex, EXx } },
10704   },
10705   {
10706     /* VEX_W_0F77_P_0 */
10707     { "",               { VZERO } },
10708   },
10709   {
10710     /* VEX_W_0F7C_P_2 */
10711     { "vhaddpd",        { XM, Vex, EXx } },
10712   },
10713   {
10714     /* VEX_W_0F7C_P_3 */
10715     { "vhaddps",        { XM, Vex, EXx } },
10716   },
10717   {
10718     /* VEX_W_0F7D_P_2 */
10719     { "vhsubpd",        { XM, Vex, EXx } },
10720   },
10721   {
10722     /* VEX_W_0F7D_P_3 */
10723     { "vhsubps",        { XM, Vex, EXx } },
10724   },
10725   {
10726     /* VEX_W_0F7E_P_1 */
10727     { "vmovq",          { XMScalar, EXqScalar } },
10728   },
10729   {
10730     /* VEX_W_0F7F_P_1 */
10731     { "vmovdqu",        { EXxS, XM } },
10732   },
10733   {
10734     /* VEX_W_0F7F_P_2 */
10735     { "vmovdqa",        { EXxS, XM } },
10736   },
10737   {
10738     /* VEX_W_0F90_P_0_LEN_0 */
10739     { "kmovw",          { MaskG, MaskE } },
10740     { "kmovq",          { MaskG, MaskE } },
10741   },
10742   {
10743     /* VEX_W_0F90_P_2_LEN_0 */
10744     { Bad_Opcode },
10745     { "kmovd",          { MaskG, MaskBDE } },
10746   },
10747   {
10748     /* VEX_W_0F91_P_0_LEN_0 */
10749     { "kmovw",          { Ew, MaskG } },
10750     { "kmovq",          { Eq, MaskG } },
10751   },
10752   {
10753     /* VEX_W_0F91_P_2_LEN_0 */
10754     { Bad_Opcode },
10755     { "kmovd",          { Ed, MaskG } },
10756   },
10757   {
10758     /* VEX_W_0F92_P_0_LEN_0 */
10759     { "kmovw",          { MaskG, Rdq } },
10760   },
10761   {
10762     /* VEX_W_0F92_P_3_LEN_0 */
10763     { "kmovd",          { MaskG, Rdq } },
10764     { "kmovq",          { MaskG, Rdq } },
10765   },
10766   {
10767     /* VEX_W_0F93_P_0_LEN_0 */
10768     { "kmovw",          { Gdq, MaskR } },
10769   },
10770   {
10771     /* VEX_W_0F93_P_3_LEN_0 */
10772     { "kmovd",          { Gdq, MaskR } },
10773     { "kmovq",          { Gdq, MaskR } },
10774   },
10775   {
10776     /* VEX_W_0F98_P_0_LEN_0 */
10777     { "kortestw",       { MaskG, MaskR } },
10778     { "kortestq",       { MaskG, MaskR } },
10779   },
10780   {
10781     /* VEX_W_0F98_P_2_LEN_0 */
10782     { "kortestb",       { MaskG, MaskR } },
10783     { "kortestd",       { MaskG, MaskR } },
10784   },
10785   {
10786     /* VEX_W_0F99_P_0_LEN_0 */
10787     { "ktestw", { MaskG, MaskR } },
10788     { "ktestq", { MaskG, MaskR } },
10789   },
10790   {
10791     /* VEX_W_0F99_P_2_LEN_0 */
10792     { Bad_Opcode },
10793     { "ktestd", { MaskG, MaskR } },
10794   },
10795   {
10796     /* VEX_W_0FAE_R_2_M_0 */
10797     { "vldmxcsr",       { Md } },
10798   },
10799   {
10800     /* VEX_W_0FAE_R_3_M_0 */
10801     { "vstmxcsr",       { Md } },
10802   },
10803   {
10804     /* VEX_W_0FC2_P_0 */
10805     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10806   },
10807   {
10808     /* VEX_W_0FC2_P_1 */
10809     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10810   },
10811   {
10812     /* VEX_W_0FC2_P_2 */
10813     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10814   },
10815   {
10816     /* VEX_W_0FC2_P_3 */
10817     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10818   },
10819   {
10820     /* VEX_W_0FC4_P_2 */
10821     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10822   },
10823   {
10824     /* VEX_W_0FC5_P_2 */
10825     { "vpextrw",        { Gdq, XS, Ib } },
10826   },
10827   {
10828     /* VEX_W_0FD0_P_2 */
10829     { "vaddsubpd",      { XM, Vex, EXx } },
10830   },
10831   {
10832     /* VEX_W_0FD0_P_3 */
10833     { "vaddsubps",      { XM, Vex, EXx } },
10834   },
10835   {
10836     /* VEX_W_0FD1_P_2 */
10837     { "vpsrlw",         { XM, Vex, EXxmm } },
10838   },
10839   {
10840     /* VEX_W_0FD2_P_2 */
10841     { "vpsrld",         { XM, Vex, EXxmm } },
10842   },
10843   {
10844     /* VEX_W_0FD3_P_2 */
10845     { "vpsrlq",         { XM, Vex, EXxmm } },
10846   },
10847   {
10848     /* VEX_W_0FD4_P_2 */
10849     { "vpaddq",         { XM, Vex, EXx } },
10850   },
10851   {
10852     /* VEX_W_0FD5_P_2 */
10853     { "vpmullw",        { XM, Vex, EXx } },
10854   },
10855   {
10856     /* VEX_W_0FD6_P_2 */
10857     { "vmovq",          { EXqScalarS, XMScalar } },
10858   },
10859   {
10860     /* VEX_W_0FD7_P_2_M_1 */
10861     { "vpmovmskb",      { Gdq, XS } },
10862   },
10863   {
10864     /* VEX_W_0FD8_P_2 */
10865     { "vpsubusb",       { XM, Vex, EXx } },
10866   },
10867   {
10868     /* VEX_W_0FD9_P_2 */
10869     { "vpsubusw",       { XM, Vex, EXx } },
10870   },
10871   {
10872     /* VEX_W_0FDA_P_2 */
10873     { "vpminub",        { XM, Vex, EXx } },
10874   },
10875   {
10876     /* VEX_W_0FDB_P_2 */
10877     { "vpand",          { XM, Vex, EXx } },
10878   },
10879   {
10880     /* VEX_W_0FDC_P_2 */
10881     { "vpaddusb",       { XM, Vex, EXx } },
10882   },
10883   {
10884     /* VEX_W_0FDD_P_2 */
10885     { "vpaddusw",       { XM, Vex, EXx } },
10886   },
10887   {
10888     /* VEX_W_0FDE_P_2 */
10889     { "vpmaxub",        { XM, Vex, EXx } },
10890   },
10891   {
10892     /* VEX_W_0FDF_P_2 */
10893     { "vpandn",         { XM, Vex, EXx } },
10894   },
10895   {
10896     /* VEX_W_0FE0_P_2  */
10897     { "vpavgb",         { XM, Vex, EXx } },
10898   },
10899   {
10900     /* VEX_W_0FE1_P_2  */
10901     { "vpsraw",         { XM, Vex, EXxmm } },
10902   },
10903   {
10904     /* VEX_W_0FE2_P_2  */
10905     { "vpsrad",         { XM, Vex, EXxmm } },
10906   },
10907   {
10908     /* VEX_W_0FE3_P_2  */
10909     { "vpavgw",         { XM, Vex, EXx } },
10910   },
10911   {
10912     /* VEX_W_0FE4_P_2  */
10913     { "vpmulhuw",       { XM, Vex, EXx } },
10914   },
10915   {
10916     /* VEX_W_0FE5_P_2  */
10917     { "vpmulhw",        { XM, Vex, EXx } },
10918   },
10919   {
10920     /* VEX_W_0FE6_P_1  */
10921     { "vcvtdq2pd",      { XM, EXxmmq } },
10922   },
10923   {
10924     /* VEX_W_0FE6_P_2  */
10925     { "vcvttpd2dq%XY",  { XMM, EXx } },
10926   },
10927   {
10928     /* VEX_W_0FE6_P_3  */
10929     { "vcvtpd2dq%XY",   { XMM, EXx } },
10930   },
10931   {
10932     /* VEX_W_0FE7_P_2_M_0 */
10933     { "vmovntdq",       { Mx, XM } },
10934   },
10935   {
10936     /* VEX_W_0FE8_P_2  */
10937     { "vpsubsb",        { XM, Vex, EXx } },
10938   },
10939   {
10940     /* VEX_W_0FE9_P_2  */
10941     { "vpsubsw",        { XM, Vex, EXx } },
10942   },
10943   {
10944     /* VEX_W_0FEA_P_2  */
10945     { "vpminsw",        { XM, Vex, EXx } },
10946   },
10947   {
10948     /* VEX_W_0FEB_P_2  */
10949     { "vpor",           { XM, Vex, EXx } },
10950   },
10951   {
10952     /* VEX_W_0FEC_P_2  */
10953     { "vpaddsb",        { XM, Vex, EXx } },
10954   },
10955   {
10956     /* VEX_W_0FED_P_2  */
10957     { "vpaddsw",        { XM, Vex, EXx } },
10958   },
10959   {
10960     /* VEX_W_0FEE_P_2  */
10961     { "vpmaxsw",        { XM, Vex, EXx } },
10962   },
10963   {
10964     /* VEX_W_0FEF_P_2  */
10965     { "vpxor",          { XM, Vex, EXx } },
10966   },
10967   {
10968     /* VEX_W_0FF0_P_3_M_0 */
10969     { "vlddqu",         { XM, M } },
10970   },
10971   {
10972     /* VEX_W_0FF1_P_2 */
10973     { "vpsllw",         { XM, Vex, EXxmm } },
10974   },
10975   {
10976     /* VEX_W_0FF2_P_2 */
10977     { "vpslld",         { XM, Vex, EXxmm } },
10978   },
10979   {
10980     /* VEX_W_0FF3_P_2 */
10981     { "vpsllq",         { XM, Vex, EXxmm } },
10982   },
10983   {
10984     /* VEX_W_0FF4_P_2 */
10985     { "vpmuludq",       { XM, Vex, EXx } },
10986   },
10987   {
10988     /* VEX_W_0FF5_P_2 */
10989     { "vpmaddwd",       { XM, Vex, EXx } },
10990   },
10991   {
10992     /* VEX_W_0FF6_P_2 */
10993     { "vpsadbw",        { XM, Vex, EXx } },
10994   },
10995   {
10996     /* VEX_W_0FF7_P_2 */
10997     { "vmaskmovdqu",    { XM, XS } },
10998   },
10999   {
11000     /* VEX_W_0FF8_P_2 */
11001     { "vpsubb",         { XM, Vex, EXx } },
11002   },
11003   {
11004     /* VEX_W_0FF9_P_2 */
11005     { "vpsubw",         { XM, Vex, EXx } },
11006   },
11007   {
11008     /* VEX_W_0FFA_P_2 */
11009     { "vpsubd",         { XM, Vex, EXx } },
11010   },
11011   {
11012     /* VEX_W_0FFB_P_2 */
11013     { "vpsubq",         { XM, Vex, EXx } },
11014   },
11015   {
11016     /* VEX_W_0FFC_P_2 */
11017     { "vpaddb",         { XM, Vex, EXx } },
11018   },
11019   {
11020     /* VEX_W_0FFD_P_2 */
11021     { "vpaddw",         { XM, Vex, EXx } },
11022   },
11023   {
11024     /* VEX_W_0FFE_P_2 */
11025     { "vpaddd",         { XM, Vex, EXx } },
11026   },
11027   {
11028     /* VEX_W_0F3800_P_2  */
11029     { "vpshufb",        { XM, Vex, EXx } },
11030   },
11031   {
11032     /* VEX_W_0F3801_P_2  */
11033     { "vphaddw",        { XM, Vex, EXx } },
11034   },
11035   {
11036     /* VEX_W_0F3802_P_2  */
11037     { "vphaddd",        { XM, Vex, EXx } },
11038   },
11039   {
11040     /* VEX_W_0F3803_P_2  */
11041     { "vphaddsw",       { XM, Vex, EXx } },
11042   },
11043   {
11044     /* VEX_W_0F3804_P_2  */
11045     { "vpmaddubsw",     { XM, Vex, EXx } },
11046   },
11047   {
11048     /* VEX_W_0F3805_P_2  */
11049     { "vphsubw",        { XM, Vex, EXx } },
11050   },
11051   {
11052     /* VEX_W_0F3806_P_2  */
11053     { "vphsubd",        { XM, Vex, EXx } },
11054   },
11055   {
11056     /* VEX_W_0F3807_P_2  */
11057     { "vphsubsw",       { XM, Vex, EXx } },
11058   },
11059   {
11060     /* VEX_W_0F3808_P_2  */
11061     { "vpsignb",        { XM, Vex, EXx } },
11062   },
11063   {
11064     /* VEX_W_0F3809_P_2  */
11065     { "vpsignw",        { XM, Vex, EXx } },
11066   },
11067   {
11068     /* VEX_W_0F380A_P_2  */
11069     { "vpsignd",        { XM, Vex, EXx } },
11070   },
11071   {
11072     /* VEX_W_0F380B_P_2  */
11073     { "vpmulhrsw",      { XM, Vex, EXx } },
11074   },
11075   {
11076     /* VEX_W_0F380C_P_2  */
11077     { "vpermilps",      { XM, Vex, EXx } },
11078   },
11079   {
11080     /* VEX_W_0F380D_P_2  */
11081     { "vpermilpd",      { XM, Vex, EXx } },
11082   },
11083   {
11084     /* VEX_W_0F380E_P_2  */
11085     { "vtestps",        { XM, EXx } },
11086   },
11087   {
11088     /* VEX_W_0F380F_P_2  */
11089     { "vtestpd",        { XM, EXx } },
11090   },
11091   {
11092     /* VEX_W_0F3816_P_2  */
11093     { "vpermps",        { XM, Vex, EXx } },
11094   },
11095   {
11096     /* VEX_W_0F3817_P_2 */
11097     { "vptest",         { XM, EXx } },
11098   },
11099   {
11100     /* VEX_W_0F3818_P_2 */
11101     { "vbroadcastss",   { XM, EXxmm_md } },
11102   },
11103   {
11104     /* VEX_W_0F3819_P_2 */
11105     { "vbroadcastsd",   { XM, EXxmm_mq } },
11106   },
11107   {
11108     /* VEX_W_0F381A_P_2_M_0 */
11109     { "vbroadcastf128", { XM, Mxmm } },
11110   },
11111   {
11112     /* VEX_W_0F381C_P_2 */
11113     { "vpabsb",         { XM, EXx } },
11114   },
11115   {
11116     /* VEX_W_0F381D_P_2 */
11117     { "vpabsw",         { XM, EXx } },
11118   },
11119   {
11120     /* VEX_W_0F381E_P_2 */
11121     { "vpabsd",         { XM, EXx } },
11122   },
11123   {
11124     /* VEX_W_0F3820_P_2 */
11125     { "vpmovsxbw",      { XM, EXxmmq } },
11126   },
11127   {
11128     /* VEX_W_0F3821_P_2 */
11129     { "vpmovsxbd",      { XM, EXxmmqd } },
11130   },
11131   {
11132     /* VEX_W_0F3822_P_2 */
11133     { "vpmovsxbq",      { XM, EXxmmdw } },
11134   },
11135   {
11136     /* VEX_W_0F3823_P_2 */
11137     { "vpmovsxwd",      { XM, EXxmmq } },
11138   },
11139   {
11140     /* VEX_W_0F3824_P_2 */
11141     { "vpmovsxwq",      { XM, EXxmmqd } },
11142   },
11143   {
11144     /* VEX_W_0F3825_P_2 */
11145     { "vpmovsxdq",      { XM, EXxmmq } },
11146   },
11147   {
11148     /* VEX_W_0F3828_P_2 */
11149     { "vpmuldq",        { XM, Vex, EXx } },
11150   },
11151   {
11152     /* VEX_W_0F3829_P_2 */
11153     { "vpcmpeqq",       { XM, Vex, EXx } },
11154   },
11155   {
11156     /* VEX_W_0F382A_P_2_M_0 */
11157     { "vmovntdqa",      { XM, Mx } },
11158   },
11159   {
11160     /* VEX_W_0F382B_P_2 */
11161     { "vpackusdw",      { XM, Vex, EXx } },
11162   },
11163   {
11164     /* VEX_W_0F382C_P_2_M_0 */
11165     { "vmaskmovps",     { XM, Vex, Mx } },
11166   },
11167   {
11168     /* VEX_W_0F382D_P_2_M_0 */
11169     { "vmaskmovpd",     { XM, Vex, Mx } },
11170   },
11171   {
11172     /* VEX_W_0F382E_P_2_M_0 */
11173     { "vmaskmovps",     { Mx, Vex, XM } },
11174   },
11175   {
11176     /* VEX_W_0F382F_P_2_M_0 */
11177     { "vmaskmovpd",     { Mx, Vex, XM } },
11178   },
11179   {
11180     /* VEX_W_0F3830_P_2 */
11181     { "vpmovzxbw",      { XM, EXxmmq } },
11182   },
11183   {
11184     /* VEX_W_0F3831_P_2 */
11185     { "vpmovzxbd",      { XM, EXxmmqd } },
11186   },
11187   {
11188     /* VEX_W_0F3832_P_2 */
11189     { "vpmovzxbq",      { XM, EXxmmdw } },
11190   },
11191   {
11192     /* VEX_W_0F3833_P_2 */
11193     { "vpmovzxwd",      { XM, EXxmmq } },
11194   },
11195   {
11196     /* VEX_W_0F3834_P_2 */
11197     { "vpmovzxwq",      { XM, EXxmmqd } },
11198   },
11199   {
11200     /* VEX_W_0F3835_P_2 */
11201     { "vpmovzxdq",      { XM, EXxmmq } },
11202   },
11203   {
11204     /* VEX_W_0F3836_P_2  */
11205     { "vpermd",         { XM, Vex, EXx } },
11206   },
11207   {
11208     /* VEX_W_0F3837_P_2 */
11209     { "vpcmpgtq",       { XM, Vex, EXx } },
11210   },
11211   {
11212     /* VEX_W_0F3838_P_2 */
11213     { "vpminsb",        { XM, Vex, EXx } },
11214   },
11215   {
11216     /* VEX_W_0F3839_P_2 */
11217     { "vpminsd",        { XM, Vex, EXx } },
11218   },
11219   {
11220     /* VEX_W_0F383A_P_2 */
11221     { "vpminuw",        { XM, Vex, EXx } },
11222   },
11223   {
11224     /* VEX_W_0F383B_P_2 */
11225     { "vpminud",        { XM, Vex, EXx } },
11226   },
11227   {
11228     /* VEX_W_0F383C_P_2 */
11229     { "vpmaxsb",        { XM, Vex, EXx } },
11230   },
11231   {
11232     /* VEX_W_0F383D_P_2 */
11233     { "vpmaxsd",        { XM, Vex, EXx } },
11234   },
11235   {
11236     /* VEX_W_0F383E_P_2 */
11237     { "vpmaxuw",        { XM, Vex, EXx } },
11238   },
11239   {
11240     /* VEX_W_0F383F_P_2 */
11241     { "vpmaxud",        { XM, Vex, EXx } },
11242   },
11243   {
11244     /* VEX_W_0F3840_P_2 */
11245     { "vpmulld",        { XM, Vex, EXx } },
11246   },
11247   {
11248     /* VEX_W_0F3841_P_2 */
11249     { "vphminposuw",    { XM, EXx } },
11250   },
11251   {
11252     /* VEX_W_0F3846_P_2 */
11253     { "vpsravd",        { XM, Vex, EXx } },
11254   },
11255   {
11256     /* VEX_W_0F3858_P_2 */
11257     { "vpbroadcastd", { XM, EXxmm_md } },
11258   },
11259   {
11260     /* VEX_W_0F3859_P_2 */
11261     { "vpbroadcastq",   { XM, EXxmm_mq } },
11262   },
11263   {
11264     /* VEX_W_0F385A_P_2_M_0 */
11265     { "vbroadcasti128", { XM, Mxmm } },
11266   },
11267   {
11268     /* VEX_W_0F3878_P_2 */
11269     { "vpbroadcastb",   { XM, EXxmm_mb } },
11270   },
11271   {
11272     /* VEX_W_0F3879_P_2 */
11273     { "vpbroadcastw",   { XM, EXxmm_mw } },
11274   },
11275   {
11276     /* VEX_W_0F38DB_P_2 */
11277     { "vaesimc",        { XM, EXx } },
11278   },
11279   {
11280     /* VEX_W_0F38DC_P_2 */
11281     { "vaesenc",        { XM, Vex128, EXx } },
11282   },
11283   {
11284     /* VEX_W_0F38DD_P_2 */
11285     { "vaesenclast",    { XM, Vex128, EXx } },
11286   },
11287   {
11288     /* VEX_W_0F38DE_P_2 */
11289     { "vaesdec",        { XM, Vex128, EXx } },
11290   },
11291   {
11292     /* VEX_W_0F38DF_P_2 */
11293     { "vaesdeclast",    { XM, Vex128, EXx } },
11294   },
11295   {
11296     /* VEX_W_0F3A00_P_2 */
11297     { Bad_Opcode },
11298     { "vpermq",         { XM, EXx, Ib } },
11299   },
11300   {
11301     /* VEX_W_0F3A01_P_2 */
11302     { Bad_Opcode },
11303     { "vpermpd",        { XM, EXx, Ib } },
11304   },
11305   {
11306     /* VEX_W_0F3A02_P_2 */
11307     { "vpblendd",       { XM, Vex, EXx, Ib } },
11308   },
11309   {
11310     /* VEX_W_0F3A04_P_2 */
11311     { "vpermilps",      { XM, EXx, Ib } },
11312   },
11313   {
11314     /* VEX_W_0F3A05_P_2 */
11315     { "vpermilpd",      { XM, EXx, Ib } },
11316   },
11317   {
11318     /* VEX_W_0F3A06_P_2 */
11319     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
11320   },
11321   {
11322     /* VEX_W_0F3A08_P_2 */
11323     { "vroundps",       { XM, EXx, Ib } },
11324   },
11325   {
11326     /* VEX_W_0F3A09_P_2 */
11327     { "vroundpd",       { XM, EXx, Ib } },
11328   },
11329   {
11330     /* VEX_W_0F3A0A_P_2 */
11331     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
11332   },
11333   {
11334     /* VEX_W_0F3A0B_P_2 */
11335     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
11336   },
11337   {
11338     /* VEX_W_0F3A0C_P_2 */
11339     { "vblendps",       { XM, Vex, EXx, Ib } },
11340   },
11341   {
11342     /* VEX_W_0F3A0D_P_2 */
11343     { "vblendpd",       { XM, Vex, EXx, Ib } },
11344   },
11345   {
11346     /* VEX_W_0F3A0E_P_2 */
11347     { "vpblendw",       { XM, Vex, EXx, Ib } },
11348   },
11349   {
11350     /* VEX_W_0F3A0F_P_2 */
11351     { "vpalignr",       { XM, Vex, EXx, Ib } },
11352   },
11353   {
11354     /* VEX_W_0F3A14_P_2 */
11355     { "vpextrb",        { Edqb, XM, Ib } },
11356   },
11357   {
11358     /* VEX_W_0F3A15_P_2 */
11359     { "vpextrw",        { Edqw, XM, Ib } },
11360   },
11361   {
11362     /* VEX_W_0F3A18_P_2 */
11363     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
11364   },
11365   {
11366     /* VEX_W_0F3A19_P_2 */
11367     { "vextractf128",   { EXxmm, XM, Ib } },
11368   },
11369   {
11370     /* VEX_W_0F3A20_P_2 */
11371     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
11372   },
11373   {
11374     /* VEX_W_0F3A21_P_2 */
11375     { "vinsertps",      { XM, Vex128, EXd, Ib } },
11376   },
11377   {
11378     /* VEX_W_0F3A30_P_2_LEN_0 */
11379     { Bad_Opcode },
11380     { "kshiftrw",       { MaskG, MaskR, Ib } },
11381   },
11382   {
11383     /* VEX_W_0F3A31_P_2_LEN_0 */
11384     { "kshiftrd",       { MaskG, MaskR, Ib } },
11385     { "kshiftrq",       { MaskG, MaskR, Ib } },
11386   },
11387   {
11388     /* VEX_W_0F3A32_P_2_LEN_0 */
11389     { Bad_Opcode },
11390     { "kshiftlw",       { MaskG, MaskR, Ib } },
11391   },
11392   {
11393     /* VEX_W_0F3A33_P_2_LEN_0 */
11394     { "kshiftld",       { MaskG, MaskR, Ib } },
11395     { "kshiftlq",       { MaskG, MaskR, Ib } },
11396   },
11397   {
11398     /* VEX_W_0F3A38_P_2 */
11399     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
11400   },
11401   {
11402     /* VEX_W_0F3A39_P_2 */
11403     { "vextracti128",   { EXxmm, XM, Ib } },
11404   },
11405   {
11406     /* VEX_W_0F3A40_P_2 */
11407     { "vdpps",          { XM, Vex, EXx, Ib } },
11408   },
11409   {
11410     /* VEX_W_0F3A41_P_2 */
11411     { "vdppd",          { XM, Vex128, EXx, Ib } },
11412   },
11413   {
11414     /* VEX_W_0F3A42_P_2 */
11415     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
11416   },
11417   {
11418     /* VEX_W_0F3A44_P_2 */
11419     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
11420   },
11421   {
11422     /* VEX_W_0F3A46_P_2 */
11423     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11424   },
11425   {
11426     /* VEX_W_0F3A48_P_2 */
11427     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11428     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11429   },
11430   {
11431     /* VEX_W_0F3A49_P_2 */
11432     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11433     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11434   },
11435   {
11436     /* VEX_W_0F3A4A_P_2 */
11437     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11438   },
11439   {
11440     /* VEX_W_0F3A4B_P_2 */
11441     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11442   },
11443   {
11444     /* VEX_W_0F3A4C_P_2 */
11445     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11446   },
11447   {
11448     /* VEX_W_0F3A60_P_2 */
11449     { "vpcmpestrm",     { XM, EXx, Ib } },
11450   },
11451   {
11452     /* VEX_W_0F3A61_P_2 */
11453     { "vpcmpestri",     { XM, EXx, Ib } },
11454   },
11455   {
11456     /* VEX_W_0F3A62_P_2 */
11457     { "vpcmpistrm",     { XM, EXx, Ib } },
11458   },
11459   {
11460     /* VEX_W_0F3A63_P_2 */
11461     { "vpcmpistri",     { XM, EXx, Ib } },
11462   },
11463   {
11464     /* VEX_W_0F3ADF_P_2 */
11465     { "vaeskeygenassist", { XM, EXx, Ib } },
11466   },
11467 #define NEED_VEX_W_TABLE
11468 #include "i386-dis-evex.h"
11469 #undef NEED_VEX_W_TABLE
11470 };
11471
11472 static const struct dis386 mod_table[][2] = {
11473   {
11474     /* MOD_8D */
11475     { "leaS",           { Gv, M } },
11476   },
11477   {
11478     /* MOD_C6_REG_7 */
11479     { Bad_Opcode },
11480     { RM_TABLE (RM_C6_REG_7) },
11481   },
11482   {
11483     /* MOD_C7_REG_7 */
11484     { Bad_Opcode },
11485     { RM_TABLE (RM_C7_REG_7) },
11486   },
11487   {
11488     /* MOD_FF_REG_3 */
11489     { "Jcall{T|}", { indirEp } },
11490   },
11491   {
11492     /* MOD_FF_REG_5 */
11493     { "Jjmp{T|}", { indirEp } },
11494   },
11495   {
11496     /* MOD_0F01_REG_0 */
11497     { X86_64_TABLE (X86_64_0F01_REG_0) },
11498     { RM_TABLE (RM_0F01_REG_0) },
11499   },
11500   {
11501     /* MOD_0F01_REG_1 */
11502     { X86_64_TABLE (X86_64_0F01_REG_1) },
11503     { RM_TABLE (RM_0F01_REG_1) },
11504   },
11505   {
11506     /* MOD_0F01_REG_2 */
11507     { X86_64_TABLE (X86_64_0F01_REG_2) },
11508     { RM_TABLE (RM_0F01_REG_2) },
11509   },
11510   {
11511     /* MOD_0F01_REG_3 */
11512     { X86_64_TABLE (X86_64_0F01_REG_3) },
11513     { RM_TABLE (RM_0F01_REG_3) },
11514   },
11515   {
11516     /* MOD_0F01_REG_7 */
11517     { "invlpg",         { Mb } },
11518     { RM_TABLE (RM_0F01_REG_7) },
11519   },
11520   {
11521     /* MOD_0F12_PREFIX_0 */
11522     { "movlps",         { XM, EXq } },
11523     { "movhlps",        { XM, EXq } },
11524   },
11525   {
11526     /* MOD_0F13 */
11527     { "movlpX",         { EXq, XM } },
11528   },
11529   {
11530     /* MOD_0F16_PREFIX_0 */
11531     { "movhps",         { XM, EXq } },
11532     { "movlhps",        { XM, EXq } },
11533   },
11534   {
11535     /* MOD_0F17 */
11536     { "movhpX",         { EXq, XM } },
11537   },
11538   {
11539     /* MOD_0F18_REG_0 */
11540     { "prefetchnta",    { Mb } },
11541   },
11542   {
11543     /* MOD_0F18_REG_1 */
11544     { "prefetcht0",     { Mb } },
11545   },
11546   {
11547     /* MOD_0F18_REG_2 */
11548     { "prefetcht1",     { Mb } },
11549   },
11550   {
11551     /* MOD_0F18_REG_3 */
11552     { "prefetcht2",     { Mb } },
11553   },
11554   {
11555     /* MOD_0F18_REG_4 */
11556     { "nop/reserved",   { Mb } },
11557   },
11558   {
11559     /* MOD_0F18_REG_5 */
11560     { "nop/reserved",   { Mb } },
11561   },
11562   {
11563     /* MOD_0F18_REG_6 */
11564     { "nop/reserved",   { Mb } },
11565   },
11566   {
11567     /* MOD_0F18_REG_7 */
11568     { "nop/reserved",   { Mb } },
11569   },
11570   {
11571     /* MOD_0F1A_PREFIX_0 */
11572     { "bndldx",         { Gbnd, Ev_bnd } },
11573     { "nopQ",           { Ev } },
11574   },
11575   {
11576     /* MOD_0F1B_PREFIX_0 */
11577     { "bndstx",         { Ev_bnd, Gbnd } },
11578     { "nopQ",           { Ev } },
11579   },
11580   {
11581     /* MOD_0F1B_PREFIX_1 */
11582     { "bndmk",          { Gbnd, Ev_bnd } },
11583     { "nopQ",           { Ev } },
11584   },
11585   {
11586     /* MOD_0F20 */
11587     { Bad_Opcode },
11588     { "movZ",           { Rm, Cm } },
11589   },
11590   {
11591     /* MOD_0F21 */
11592     { Bad_Opcode },
11593     { "movZ",           { Rm, Dm } },
11594   },
11595   {
11596     /* MOD_0F22 */
11597     { Bad_Opcode },
11598     { "movZ",           { Cm, Rm } },
11599   },
11600   {
11601     /* MOD_0F23 */
11602     { Bad_Opcode },
11603     { "movZ",           { Dm, Rm } },
11604   },
11605   {
11606     /* MOD_0F24 */
11607     { Bad_Opcode },
11608     { "movL",           { Rd, Td } },
11609   },
11610   {
11611     /* MOD_0F26 */
11612     { Bad_Opcode },
11613     { "movL",           { Td, Rd } },
11614   },
11615   {
11616     /* MOD_0F2B_PREFIX_0 */
11617     {"movntps",         { Mx, XM } },
11618   },
11619   {
11620     /* MOD_0F2B_PREFIX_1 */
11621     {"movntss",         { Md, XM } },
11622   },
11623   {
11624     /* MOD_0F2B_PREFIX_2 */
11625     {"movntpd",         { Mx, XM } },
11626   },
11627   {
11628     /* MOD_0F2B_PREFIX_3 */
11629     {"movntsd",         { Mq, XM } },
11630   },
11631   {
11632     /* MOD_0F51 */
11633     { Bad_Opcode },
11634     { "movmskpX",       { Gdq, XS } },
11635   },
11636   {
11637     /* MOD_0F71_REG_2 */
11638     { Bad_Opcode },
11639     { "psrlw",          { MS, Ib } },
11640   },
11641   {
11642     /* MOD_0F71_REG_4 */
11643     { Bad_Opcode },
11644     { "psraw",          { MS, Ib } },
11645   },
11646   {
11647     /* MOD_0F71_REG_6 */
11648     { Bad_Opcode },
11649     { "psllw",          { MS, Ib } },
11650   },
11651   {
11652     /* MOD_0F72_REG_2 */
11653     { Bad_Opcode },
11654     { "psrld",          { MS, Ib } },
11655   },
11656   {
11657     /* MOD_0F72_REG_4 */
11658     { Bad_Opcode },
11659     { "psrad",          { MS, Ib } },
11660   },
11661   {
11662     /* MOD_0F72_REG_6 */
11663     { Bad_Opcode },
11664     { "pslld",          { MS, Ib } },
11665   },
11666   {
11667     /* MOD_0F73_REG_2 */
11668     { Bad_Opcode },
11669     { "psrlq",          { MS, Ib } },
11670   },
11671   {
11672     /* MOD_0F73_REG_3 */
11673     { Bad_Opcode },
11674     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11675   },
11676   {
11677     /* MOD_0F73_REG_6 */
11678     { Bad_Opcode },
11679     { "psllq",          { MS, Ib } },
11680   },
11681   {
11682     /* MOD_0F73_REG_7 */
11683     { Bad_Opcode },
11684     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11685   },
11686   {
11687     /* MOD_0FAE_REG_0 */
11688     { "fxsave",         { FXSAVE } },
11689     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11690   },
11691   {
11692     /* MOD_0FAE_REG_1 */
11693     { "fxrstor",        { FXSAVE } },
11694     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11695   },
11696   {
11697     /* MOD_0FAE_REG_2 */
11698     { "ldmxcsr",        { Md } },
11699     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11700   },
11701   {
11702     /* MOD_0FAE_REG_3 */
11703     { "stmxcsr",        { Md } },
11704     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11705   },
11706   {
11707     /* MOD_0FAE_REG_4 */
11708     { "xsave",          { FXSAVE } },
11709   },
11710   {
11711     /* MOD_0FAE_REG_5 */
11712     { "xrstor",         { FXSAVE } },
11713     { RM_TABLE (RM_0FAE_REG_5) },
11714   },
11715   {
11716     /* MOD_0FAE_REG_6 */
11717     { "xsaveopt",       { FXSAVE } },
11718     { RM_TABLE (RM_0FAE_REG_6) },
11719   },
11720   {
11721     /* MOD_0FAE_REG_7 */
11722     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11723     { RM_TABLE (RM_0FAE_REG_7) },
11724   },
11725   {
11726     /* MOD_0FB2 */
11727     { "lssS",           { Gv, Mp } },
11728   },
11729   {
11730     /* MOD_0FB4 */
11731     { "lfsS",           { Gv, Mp } },
11732   },
11733   {
11734     /* MOD_0FB5 */
11735     { "lgsS",           { Gv, Mp } },
11736   },
11737   {
11738     /* MOD_0FC7_REG_3 */
11739     { "xrstors",                { FXSAVE } },
11740   },
11741   {
11742     /* MOD_0FC7_REG_4 */
11743     { "xsavec",         { FXSAVE } },
11744   },
11745   {
11746     /* MOD_0FC7_REG_5 */
11747     { "xsaves",         { FXSAVE } },
11748   },
11749   {
11750     /* MOD_0FC7_REG_6 */
11751     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11752     { "rdrand",         { Ev } },
11753   },
11754   {
11755     /* MOD_0FC7_REG_7 */
11756     { "vmptrst",        { Mq } },
11757     { "rdseed",         { Ev } },
11758   },
11759   {
11760     /* MOD_0FD7 */
11761     { Bad_Opcode },
11762     { "pmovmskb",       { Gdq, MS } },
11763   },
11764   {
11765     /* MOD_0FE7_PREFIX_2 */
11766     { "movntdq",        { Mx, XM } },
11767   },
11768   {
11769     /* MOD_0FF0_PREFIX_3 */
11770     { "lddqu",          { XM, M } },
11771   },
11772   {
11773     /* MOD_0F382A_PREFIX_2 */
11774     { "movntdqa",       { XM, Mx } },
11775   },
11776   {
11777     /* MOD_62_32BIT */
11778     { "bound{S|}",      { Gv, Ma } },
11779     { EVEX_TABLE (EVEX_0F) },
11780   },
11781   {
11782     /* MOD_C4_32BIT */
11783     { "lesS",           { Gv, Mp } },
11784     { VEX_C4_TABLE (VEX_0F) },
11785   },
11786   {
11787     /* MOD_C5_32BIT */
11788     { "ldsS",           { Gv, Mp } },
11789     { VEX_C5_TABLE (VEX_0F) },
11790   },
11791   {
11792     /* MOD_VEX_0F12_PREFIX_0 */
11793     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11794     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11795   },
11796   {
11797     /* MOD_VEX_0F13 */
11798     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11799   },
11800   {
11801     /* MOD_VEX_0F16_PREFIX_0 */
11802     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11803     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11804   },
11805   {
11806     /* MOD_VEX_0F17 */
11807     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11808   },
11809   {
11810     /* MOD_VEX_0F2B */
11811     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11812   },
11813   {
11814     /* MOD_VEX_0F50 */
11815     { Bad_Opcode },
11816     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11817   },
11818   {
11819     /* MOD_VEX_0F71_REG_2 */
11820     { Bad_Opcode },
11821     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11822   },
11823   {
11824     /* MOD_VEX_0F71_REG_4 */
11825     { Bad_Opcode },
11826     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11827   },
11828   {
11829     /* MOD_VEX_0F71_REG_6 */
11830     { Bad_Opcode },
11831     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11832   },
11833   {
11834     /* MOD_VEX_0F72_REG_2 */
11835     { Bad_Opcode },
11836     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11837   },
11838   {
11839     /* MOD_VEX_0F72_REG_4 */
11840     { Bad_Opcode },
11841     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11842   },
11843   {
11844     /* MOD_VEX_0F72_REG_6 */
11845     { Bad_Opcode },
11846     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11847   },
11848   {
11849     /* MOD_VEX_0F73_REG_2 */
11850     { Bad_Opcode },
11851     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11852   },
11853   {
11854     /* MOD_VEX_0F73_REG_3 */
11855     { Bad_Opcode },
11856     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11857   },
11858   {
11859     /* MOD_VEX_0F73_REG_6 */
11860     { Bad_Opcode },
11861     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11862   },
11863   {
11864     /* MOD_VEX_0F73_REG_7 */
11865     { Bad_Opcode },
11866     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11867   },
11868   {
11869     /* MOD_VEX_0FAE_REG_2 */
11870     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11871   },
11872   {
11873     /* MOD_VEX_0FAE_REG_3 */
11874     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11875   },
11876   {
11877     /* MOD_VEX_0FD7_PREFIX_2 */
11878     { Bad_Opcode },
11879     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11880   },
11881   {
11882     /* MOD_VEX_0FE7_PREFIX_2 */
11883     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11884   },
11885   {
11886     /* MOD_VEX_0FF0_PREFIX_3 */
11887     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11888   },
11889   {
11890     /* MOD_VEX_0F381A_PREFIX_2 */
11891     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11892   },
11893   {
11894     /* MOD_VEX_0F382A_PREFIX_2 */
11895     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11896   },
11897   {
11898     /* MOD_VEX_0F382C_PREFIX_2 */
11899     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11900   },
11901   {
11902     /* MOD_VEX_0F382D_PREFIX_2 */
11903     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11904   },
11905   {
11906     /* MOD_VEX_0F382E_PREFIX_2 */
11907     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11908   },
11909   {
11910     /* MOD_VEX_0F382F_PREFIX_2 */
11911     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11912   },
11913   {
11914     /* MOD_VEX_0F385A_PREFIX_2 */
11915     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11916   },
11917   {
11918     /* MOD_VEX_0F388C_PREFIX_2 */
11919     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11920   },
11921   {
11922     /* MOD_VEX_0F388E_PREFIX_2 */
11923     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11924   },
11925 #define NEED_MOD_TABLE
11926 #include "i386-dis-evex.h"
11927 #undef NEED_MOD_TABLE
11928 };
11929
11930 static const struct dis386 rm_table[][8] = {
11931   {
11932     /* RM_C6_REG_7 */
11933     { "xabort",         { Skip_MODRM, Ib } },
11934   },
11935   {
11936     /* RM_C7_REG_7 */
11937     { "xbeginT",        { Skip_MODRM, Jv } },
11938   },
11939   {
11940     /* RM_0F01_REG_0 */
11941     { Bad_Opcode },
11942     { "vmcall",         { Skip_MODRM } },
11943     { "vmlaunch",       { Skip_MODRM } },
11944     { "vmresume",       { Skip_MODRM } },
11945     { "vmxoff",         { Skip_MODRM } },
11946   },
11947   {
11948     /* RM_0F01_REG_1 */
11949     { "monitor",        { { OP_Monitor, 0 } } },
11950     { "mwait",          { { OP_Mwait, 0 } } },
11951     { "clac",           { Skip_MODRM } },
11952     { "stac",           { Skip_MODRM } },
11953     { Bad_Opcode },
11954     { Bad_Opcode },
11955     { Bad_Opcode },
11956     { "encls",          { Skip_MODRM } },
11957   },
11958   {
11959     /* RM_0F01_REG_2 */
11960     { "xgetbv",         { Skip_MODRM } },
11961     { "xsetbv",         { Skip_MODRM } },
11962     { Bad_Opcode },
11963     { Bad_Opcode },
11964     { "vmfunc",         { Skip_MODRM } },
11965     { "xend",           { Skip_MODRM } },
11966     { "xtest",          { Skip_MODRM } },
11967     { "enclu",          { Skip_MODRM } },
11968   },
11969   {
11970     /* RM_0F01_REG_3 */
11971     { "vmrun",          { Skip_MODRM } },
11972     { "vmmcall",        { Skip_MODRM } },
11973     { "vmload",         { Skip_MODRM } },
11974     { "vmsave",         { Skip_MODRM } },
11975     { "stgi",           { Skip_MODRM } },
11976     { "clgi",           { Skip_MODRM } },
11977     { "skinit",         { Skip_MODRM } },
11978     { "invlpga",        { Skip_MODRM } },
11979   },
11980   {
11981     /* RM_0F01_REG_7 */
11982     { "swapgs",         { Skip_MODRM } },
11983     { "rdtscp",         { Skip_MODRM } },
11984   },
11985   {
11986     /* RM_0FAE_REG_5 */
11987     { "lfence",         { Skip_MODRM } },
11988   },
11989   {
11990     /* RM_0FAE_REG_6 */
11991     { "mfence",         { Skip_MODRM } },
11992   },
11993   {
11994     /* RM_0FAE_REG_7 */
11995     { "sfence",         { Skip_MODRM } },
11996   },
11997 };
11998
11999 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12000
12001 /* We use the high bit to indicate different name for the same
12002    prefix.  */
12003 #define REP_PREFIX      (0xf3 | 0x100)
12004 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12005 #define XRELEASE_PREFIX (0xf3 | 0x400)
12006 #define BND_PREFIX      (0xf2 | 0x400)
12007
12008 static int
12009 ckprefix (void)
12010 {
12011   int newrex, i, length;
12012   rex = 0;
12013   rex_ignored = 0;
12014   prefixes = 0;
12015   used_prefixes = 0;
12016   rex_used = 0;
12017   last_lock_prefix = -1;
12018   last_repz_prefix = -1;
12019   last_repnz_prefix = -1;
12020   last_data_prefix = -1;
12021   last_addr_prefix = -1;
12022   last_rex_prefix = -1;
12023   last_seg_prefix = -1;
12024   fwait_prefix = -1;
12025   active_seg_prefix = 0;
12026   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12027     all_prefixes[i] = 0;
12028   i = 0;
12029   length = 0;
12030   /* The maximum instruction length is 15bytes.  */
12031   while (length < MAX_CODE_LENGTH - 1)
12032     {
12033       FETCH_DATA (the_info, codep + 1);
12034       newrex = 0;
12035       switch (*codep)
12036         {
12037         /* REX prefixes family.  */
12038         case 0x40:
12039         case 0x41:
12040         case 0x42:
12041         case 0x43:
12042         case 0x44:
12043         case 0x45:
12044         case 0x46:
12045         case 0x47:
12046         case 0x48:
12047         case 0x49:
12048         case 0x4a:
12049         case 0x4b:
12050         case 0x4c:
12051         case 0x4d:
12052         case 0x4e:
12053         case 0x4f:
12054           if (address_mode == mode_64bit)
12055             newrex = *codep;
12056           else
12057             return 1;
12058           last_rex_prefix = i;
12059           break;
12060         case 0xf3:
12061           prefixes |= PREFIX_REPZ;
12062           last_repz_prefix = i;
12063           break;
12064         case 0xf2:
12065           prefixes |= PREFIX_REPNZ;
12066           last_repnz_prefix = i;
12067           break;
12068         case 0xf0:
12069           prefixes |= PREFIX_LOCK;
12070           last_lock_prefix = i;
12071           break;
12072         case 0x2e:
12073           prefixes |= PREFIX_CS;
12074           last_seg_prefix = i;
12075           active_seg_prefix = PREFIX_CS;
12076           break;
12077         case 0x36:
12078           prefixes |= PREFIX_SS;
12079           last_seg_prefix = i;
12080           active_seg_prefix = PREFIX_SS;
12081           break;
12082         case 0x3e:
12083           prefixes |= PREFIX_DS;
12084           last_seg_prefix = i;
12085           active_seg_prefix = PREFIX_DS;
12086           break;
12087         case 0x26:
12088           prefixes |= PREFIX_ES;
12089           last_seg_prefix = i;
12090           active_seg_prefix = PREFIX_ES;
12091           break;
12092         case 0x64:
12093           prefixes |= PREFIX_FS;
12094           last_seg_prefix = i;
12095           active_seg_prefix = PREFIX_FS;
12096           break;
12097         case 0x65:
12098           prefixes |= PREFIX_GS;
12099           last_seg_prefix = i;
12100           active_seg_prefix = PREFIX_GS;
12101           break;
12102         case 0x66:
12103           prefixes |= PREFIX_DATA;
12104           last_data_prefix = i;
12105           break;
12106         case 0x67:
12107           prefixes |= PREFIX_ADDR;
12108           last_addr_prefix = i;
12109           break;
12110         case FWAIT_OPCODE:
12111           /* fwait is really an instruction.  If there are prefixes
12112              before the fwait, they belong to the fwait, *not* to the
12113              following instruction.  */
12114           fwait_prefix = i;
12115           if (prefixes || rex)
12116             {
12117               prefixes |= PREFIX_FWAIT;
12118               codep++;
12119               /* This ensures that the previous REX prefixes are noticed
12120                  as unused prefixes, as in the return case below.  */
12121               rex_used = rex;
12122               return 1;
12123             }
12124           prefixes = PREFIX_FWAIT;
12125           break;
12126         default:
12127           return 1;
12128         }
12129       /* Rex is ignored when followed by another prefix.  */
12130       if (rex)
12131         {
12132           rex_used = rex;
12133           return 1;
12134         }
12135       if (*codep != FWAIT_OPCODE)
12136         all_prefixes[i++] = *codep;
12137       rex = newrex;
12138       codep++;
12139       length++;
12140     }
12141   return 0;
12142 }
12143
12144 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12145    prefix byte.  */
12146
12147 static const char *
12148 prefix_name (int pref, int sizeflag)
12149 {
12150   static const char *rexes [16] =
12151     {
12152       "rex",            /* 0x40 */
12153       "rex.B",          /* 0x41 */
12154       "rex.X",          /* 0x42 */
12155       "rex.XB",         /* 0x43 */
12156       "rex.R",          /* 0x44 */
12157       "rex.RB",         /* 0x45 */
12158       "rex.RX",         /* 0x46 */
12159       "rex.RXB",        /* 0x47 */
12160       "rex.W",          /* 0x48 */
12161       "rex.WB",         /* 0x49 */
12162       "rex.WX",         /* 0x4a */
12163       "rex.WXB",        /* 0x4b */
12164       "rex.WR",         /* 0x4c */
12165       "rex.WRB",        /* 0x4d */
12166       "rex.WRX",        /* 0x4e */
12167       "rex.WRXB",       /* 0x4f */
12168     };
12169
12170   switch (pref)
12171     {
12172     /* REX prefixes family.  */
12173     case 0x40:
12174     case 0x41:
12175     case 0x42:
12176     case 0x43:
12177     case 0x44:
12178     case 0x45:
12179     case 0x46:
12180     case 0x47:
12181     case 0x48:
12182     case 0x49:
12183     case 0x4a:
12184     case 0x4b:
12185     case 0x4c:
12186     case 0x4d:
12187     case 0x4e:
12188     case 0x4f:
12189       return rexes [pref - 0x40];
12190     case 0xf3:
12191       return "repz";
12192     case 0xf2:
12193       return "repnz";
12194     case 0xf0:
12195       return "lock";
12196     case 0x2e:
12197       return "cs";
12198     case 0x36:
12199       return "ss";
12200     case 0x3e:
12201       return "ds";
12202     case 0x26:
12203       return "es";
12204     case 0x64:
12205       return "fs";
12206     case 0x65:
12207       return "gs";
12208     case 0x66:
12209       return (sizeflag & DFLAG) ? "data16" : "data32";
12210     case 0x67:
12211       if (address_mode == mode_64bit)
12212         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12213       else
12214         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12215     case FWAIT_OPCODE:
12216       return "fwait";
12217     case REP_PREFIX:
12218       return "rep";
12219     case XACQUIRE_PREFIX:
12220       return "xacquire";
12221     case XRELEASE_PREFIX:
12222       return "xrelease";
12223     case BND_PREFIX:
12224       return "bnd";
12225     default:
12226       return NULL;
12227     }
12228 }
12229
12230 static char op_out[MAX_OPERANDS][100];
12231 static int op_ad, op_index[MAX_OPERANDS];
12232 static int two_source_ops;
12233 static bfd_vma op_address[MAX_OPERANDS];
12234 static bfd_vma op_riprel[MAX_OPERANDS];
12235 static bfd_vma start_pc;
12236
12237 /*
12238  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12239  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12240  *   section of the "Virtual 8086 Mode" chapter.)
12241  * 'pc' should be the address of this instruction, it will
12242  *   be used to print the target address if this is a relative jump or call
12243  * The function returns the length of this instruction in bytes.
12244  */
12245
12246 static char intel_syntax;
12247 static char intel_mnemonic = !SYSV386_COMPAT;
12248 static char open_char;
12249 static char close_char;
12250 static char separator_char;
12251 static char scale_char;
12252
12253 /* Here for backwards compatibility.  When gdb stops using
12254    print_insn_i386_att and print_insn_i386_intel these functions can
12255    disappear, and print_insn_i386 be merged into print_insn.  */
12256 int
12257 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12258 {
12259   intel_syntax = 0;
12260
12261   return print_insn (pc, info);
12262 }
12263
12264 int
12265 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12266 {
12267   intel_syntax = 1;
12268
12269   return print_insn (pc, info);
12270 }
12271
12272 int
12273 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12274 {
12275   intel_syntax = -1;
12276
12277   return print_insn (pc, info);
12278 }
12279
12280 void
12281 print_i386_disassembler_options (FILE *stream)
12282 {
12283   fprintf (stream, _("\n\
12284 The following i386/x86-64 specific disassembler options are supported for use\n\
12285 with the -M switch (multiple options should be separated by commas):\n"));
12286
12287   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12288   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12289   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12290   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12291   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12292   fprintf (stream, _("  att-mnemonic\n"
12293                      "              Display instruction in AT&T mnemonic\n"));
12294   fprintf (stream, _("  intel-mnemonic\n"
12295                      "              Display instruction in Intel mnemonic\n"));
12296   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12297   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12298   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12299   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12300   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12301   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12302 }
12303
12304 /* Bad opcode.  */
12305 static const struct dis386 bad_opcode = { "(bad)", { XX } };
12306
12307 /* Get a pointer to struct dis386 with a valid name.  */
12308
12309 static const struct dis386 *
12310 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12311 {
12312   int vindex, vex_table_index;
12313
12314   if (dp->name != NULL)
12315     return dp;
12316
12317   switch (dp->op[0].bytemode)
12318     {
12319     case USE_REG_TABLE:
12320       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12321       break;
12322
12323     case USE_MOD_TABLE:
12324       vindex = modrm.mod == 0x3 ? 1 : 0;
12325       dp = &mod_table[dp->op[1].bytemode][vindex];
12326       break;
12327
12328     case USE_RM_TABLE:
12329       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12330       break;
12331
12332     case USE_PREFIX_TABLE:
12333       if (need_vex)
12334         {
12335           /* The prefix in VEX is implicit.  */
12336           switch (vex.prefix)
12337             {
12338             case 0:
12339               vindex = 0;
12340               break;
12341             case REPE_PREFIX_OPCODE:
12342               vindex = 1;
12343               break;
12344             case DATA_PREFIX_OPCODE:
12345               vindex = 2;
12346               break;
12347             case REPNE_PREFIX_OPCODE:
12348               vindex = 3;
12349               break;
12350             default:
12351               abort ();
12352               break;
12353             }
12354         }
12355       else
12356         {
12357           int last_prefix = -1;
12358           int prefix = 0;
12359           vindex = 0;
12360           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12361              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12362              last one wins.  */
12363           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12364             {
12365               if (last_repz_prefix > last_repnz_prefix)
12366                 {
12367                   vindex = 1;
12368                   prefix = PREFIX_REPZ;
12369                   last_prefix = last_repz_prefix;
12370                 }
12371               else
12372                 {
12373                   vindex = 3;
12374                   prefix = PREFIX_REPNZ;
12375                   last_prefix = last_repnz_prefix;
12376                 }
12377
12378               /* Ignore the invalid index if it isn't mandatory.  */
12379               if (!mandatory_prefix
12380                   && (prefix_table[dp->op[1].bytemode][vindex].name
12381                       == NULL)
12382                   && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12383                       == 0))
12384                 vindex = 0;
12385             }
12386
12387           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12388             {
12389               vindex = 2;
12390               prefix = PREFIX_DATA;
12391               last_prefix = last_data_prefix;
12392             }
12393
12394           if (vindex != 0)
12395             {
12396               used_prefixes |= prefix;
12397               all_prefixes[last_prefix] = 0;
12398             }
12399         }
12400       dp = &prefix_table[dp->op[1].bytemode][vindex];
12401       break;
12402
12403     case USE_X86_64_TABLE:
12404       vindex = address_mode == mode_64bit ? 1 : 0;
12405       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12406       break;
12407
12408     case USE_3BYTE_TABLE:
12409       FETCH_DATA (info, codep + 2);
12410       vindex = *codep++;
12411       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12412       end_codep = codep;
12413       modrm.mod = (*codep >> 6) & 3;
12414       modrm.reg = (*codep >> 3) & 7;
12415       modrm.rm = *codep & 7;
12416       break;
12417
12418     case USE_VEX_LEN_TABLE:
12419       if (!need_vex)
12420         abort ();
12421
12422       switch (vex.length)
12423         {
12424         case 128:
12425           vindex = 0;
12426           break;
12427         case 256:
12428           vindex = 1;
12429           break;
12430         default:
12431           abort ();
12432           break;
12433         }
12434
12435       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12436       break;
12437
12438     case USE_XOP_8F_TABLE:
12439       FETCH_DATA (info, codep + 3);
12440       /* All bits in the REX prefix are ignored.  */
12441       rex_ignored = rex;
12442       rex = ~(*codep >> 5) & 0x7;
12443
12444       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12445       switch ((*codep & 0x1f))
12446         {
12447         default:
12448           dp = &bad_opcode;
12449           return dp;
12450         case 0x8:
12451           vex_table_index = XOP_08;
12452           break;
12453         case 0x9:
12454           vex_table_index = XOP_09;
12455           break;
12456         case 0xa:
12457           vex_table_index = XOP_0A;
12458           break;
12459         }
12460       codep++;
12461       vex.w = *codep & 0x80;
12462       if (vex.w && address_mode == mode_64bit)
12463         rex |= REX_W;
12464
12465       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12466       if (address_mode != mode_64bit
12467           && vex.register_specifier > 0x7)
12468         {
12469           dp = &bad_opcode;
12470           return dp;
12471         }
12472
12473       vex.length = (*codep & 0x4) ? 256 : 128;
12474       switch ((*codep & 0x3))
12475         {
12476         case 0:
12477           vex.prefix = 0;
12478           break;
12479         case 1:
12480           vex.prefix = DATA_PREFIX_OPCODE;
12481           break;
12482         case 2:
12483           vex.prefix = REPE_PREFIX_OPCODE;
12484           break;
12485         case 3:
12486           vex.prefix = REPNE_PREFIX_OPCODE;
12487           break;
12488         }
12489       need_vex = 1;
12490       need_vex_reg = 1;
12491       codep++;
12492       vindex = *codep++;
12493       dp = &xop_table[vex_table_index][vindex];
12494
12495       end_codep = codep;
12496       FETCH_DATA (info, codep + 1);
12497       modrm.mod = (*codep >> 6) & 3;
12498       modrm.reg = (*codep >> 3) & 7;
12499       modrm.rm = *codep & 7;
12500       break;
12501
12502     case USE_VEX_C4_TABLE:
12503       /* VEX prefix.  */
12504       FETCH_DATA (info, codep + 3);
12505       /* All bits in the REX prefix are ignored.  */
12506       rex_ignored = rex;
12507       rex = ~(*codep >> 5) & 0x7;
12508       switch ((*codep & 0x1f))
12509         {
12510         default:
12511           dp = &bad_opcode;
12512           return dp;
12513         case 0x1:
12514           vex_table_index = VEX_0F;
12515           break;
12516         case 0x2:
12517           vex_table_index = VEX_0F38;
12518           break;
12519         case 0x3:
12520           vex_table_index = VEX_0F3A;
12521           break;
12522         }
12523       codep++;
12524       vex.w = *codep & 0x80;
12525       if (vex.w && address_mode == mode_64bit)
12526         rex |= REX_W;
12527
12528       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12529       if (address_mode != mode_64bit
12530           && vex.register_specifier > 0x7)
12531         {
12532           dp = &bad_opcode;
12533           return dp;
12534         }
12535
12536       vex.length = (*codep & 0x4) ? 256 : 128;
12537       switch ((*codep & 0x3))
12538         {
12539         case 0:
12540           vex.prefix = 0;
12541           break;
12542         case 1:
12543           vex.prefix = DATA_PREFIX_OPCODE;
12544           break;
12545         case 2:
12546           vex.prefix = REPE_PREFIX_OPCODE;
12547           break;
12548         case 3:
12549           vex.prefix = REPNE_PREFIX_OPCODE;
12550           break;
12551         }
12552       need_vex = 1;
12553       need_vex_reg = 1;
12554       codep++;
12555       vindex = *codep++;
12556       dp = &vex_table[vex_table_index][vindex];
12557       end_codep = codep;
12558       /* There is no MODRM byte for VEX [82|77].  */
12559       if (vindex != 0x77 && vindex != 0x82)
12560         {
12561           FETCH_DATA (info, codep + 1);
12562           modrm.mod = (*codep >> 6) & 3;
12563           modrm.reg = (*codep >> 3) & 7;
12564           modrm.rm = *codep & 7;
12565         }
12566       break;
12567
12568     case USE_VEX_C5_TABLE:
12569       /* VEX prefix.  */
12570       FETCH_DATA (info, codep + 2);
12571       /* All bits in the REX prefix are ignored.  */
12572       rex_ignored = rex;
12573       rex = (*codep & 0x80) ? 0 : REX_R;
12574
12575       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12576       if (address_mode != mode_64bit
12577           && vex.register_specifier > 0x7)
12578         {
12579           dp = &bad_opcode;
12580           return dp;
12581         }
12582
12583       vex.w = 0;
12584
12585       vex.length = (*codep & 0x4) ? 256 : 128;
12586       switch ((*codep & 0x3))
12587         {
12588         case 0:
12589           vex.prefix = 0;
12590           break;
12591         case 1:
12592           vex.prefix = DATA_PREFIX_OPCODE;
12593           break;
12594         case 2:
12595           vex.prefix = REPE_PREFIX_OPCODE;
12596           break;
12597         case 3:
12598           vex.prefix = REPNE_PREFIX_OPCODE;
12599           break;
12600         }
12601       need_vex = 1;
12602       need_vex_reg = 1;
12603       codep++;
12604       vindex = *codep++;
12605       dp = &vex_table[dp->op[1].bytemode][vindex];
12606       end_codep = codep;
12607       /* There is no MODRM byte for VEX [82|77].  */
12608       if (vindex != 0x77 && vindex != 0x82)
12609         {
12610           FETCH_DATA (info, codep + 1);
12611           modrm.mod = (*codep >> 6) & 3;
12612           modrm.reg = (*codep >> 3) & 7;
12613           modrm.rm = *codep & 7;
12614         }
12615       break;
12616
12617     case USE_VEX_W_TABLE:
12618       if (!need_vex)
12619         abort ();
12620
12621       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12622       break;
12623
12624     case USE_EVEX_TABLE:
12625       two_source_ops = 0;
12626       /* EVEX prefix.  */
12627       vex.evex = 1;
12628       FETCH_DATA (info, codep + 4);
12629       /* All bits in the REX prefix are ignored.  */
12630       rex_ignored = rex;
12631       /* The first byte after 0x62.  */
12632       rex = ~(*codep >> 5) & 0x7;
12633       vex.r = *codep & 0x10;
12634       switch ((*codep & 0xf))
12635         {
12636         default:
12637           return &bad_opcode;
12638         case 0x1:
12639           vex_table_index = EVEX_0F;
12640           break;
12641         case 0x2:
12642           vex_table_index = EVEX_0F38;
12643           break;
12644         case 0x3:
12645           vex_table_index = EVEX_0F3A;
12646           break;
12647         }
12648
12649       /* The second byte after 0x62.  */
12650       codep++;
12651       vex.w = *codep & 0x80;
12652       if (vex.w && address_mode == mode_64bit)
12653         rex |= REX_W;
12654
12655       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12656       if (address_mode != mode_64bit)
12657         {
12658           /* In 16/32-bit mode silently ignore following bits.  */
12659           rex &= ~REX_B;
12660           vex.r = 1;
12661           vex.v = 1;
12662           vex.register_specifier &= 0x7;
12663         }
12664
12665       /* The U bit.  */
12666       if (!(*codep & 0x4))
12667         return &bad_opcode;
12668
12669       switch ((*codep & 0x3))
12670         {
12671         case 0:
12672           vex.prefix = 0;
12673           break;
12674         case 1:
12675           vex.prefix = DATA_PREFIX_OPCODE;
12676           break;
12677         case 2:
12678           vex.prefix = REPE_PREFIX_OPCODE;
12679           break;
12680         case 3:
12681           vex.prefix = REPNE_PREFIX_OPCODE;
12682           break;
12683         }
12684
12685       /* The third byte after 0x62.  */
12686       codep++;
12687
12688       /* Remember the static rounding bits.  */
12689       vex.ll = (*codep >> 5) & 3;
12690       vex.b = (*codep & 0x10) != 0;
12691
12692       vex.v = *codep & 0x8;
12693       vex.mask_register_specifier = *codep & 0x7;
12694       vex.zeroing = *codep & 0x80;
12695
12696       need_vex = 1;
12697       need_vex_reg = 1;
12698       codep++;
12699       vindex = *codep++;
12700       dp = &evex_table[vex_table_index][vindex];
12701       end_codep = codep;
12702       FETCH_DATA (info, codep + 1);
12703       modrm.mod = (*codep >> 6) & 3;
12704       modrm.reg = (*codep >> 3) & 7;
12705       modrm.rm = *codep & 7;
12706
12707       /* Set vector length.  */
12708       if (modrm.mod == 3 && vex.b)
12709         vex.length = 512;
12710       else
12711         {
12712           switch (vex.ll)
12713             {
12714             case 0x0:
12715               vex.length = 128;
12716               break;
12717             case 0x1:
12718               vex.length = 256;
12719               break;
12720             case 0x2:
12721               vex.length = 512;
12722               break;
12723             default:
12724               return &bad_opcode;
12725             }
12726         }
12727       break;
12728
12729     case 0:
12730       dp = &bad_opcode;
12731       break;
12732
12733     default:
12734       abort ();
12735     }
12736
12737   if (dp->name != NULL)
12738     return dp;
12739   else
12740     return get_valid_dis386 (dp, info);
12741 }
12742
12743 static void
12744 get_sib (disassemble_info *info, int sizeflag)
12745 {
12746   /* If modrm.mod == 3, operand must be register.  */
12747   if (need_modrm
12748       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12749       && modrm.mod != 3
12750       && modrm.rm == 4)
12751     {
12752       FETCH_DATA (info, codep + 2);
12753       sib.index = (codep [1] >> 3) & 7;
12754       sib.scale = (codep [1] >> 6) & 3;
12755       sib.base = codep [1] & 7;
12756     }
12757 }
12758
12759 static int
12760 print_insn (bfd_vma pc, disassemble_info *info)
12761 {
12762   const struct dis386 *dp;
12763   int i;
12764   char *op_txt[MAX_OPERANDS];
12765   int needcomma;
12766   int sizeflag, orig_sizeflag;
12767   const char *p;
12768   struct dis_private priv;
12769   int prefix_length;
12770
12771   priv.orig_sizeflag = AFLAG | DFLAG;
12772   if ((info->mach & bfd_mach_i386_i386) != 0)
12773     address_mode = mode_32bit;
12774   else if (info->mach == bfd_mach_i386_i8086)
12775     {
12776       address_mode = mode_16bit;
12777       priv.orig_sizeflag = 0;
12778     }
12779   else
12780     address_mode = mode_64bit;
12781
12782   if (intel_syntax == (char) -1)
12783     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12784
12785   for (p = info->disassembler_options; p != NULL; )
12786     {
12787       if (CONST_STRNEQ (p, "x86-64"))
12788         {
12789           address_mode = mode_64bit;
12790           priv.orig_sizeflag = AFLAG | DFLAG;
12791         }
12792       else if (CONST_STRNEQ (p, "i386"))
12793         {
12794           address_mode = mode_32bit;
12795           priv.orig_sizeflag = AFLAG | DFLAG;
12796         }
12797       else if (CONST_STRNEQ (p, "i8086"))
12798         {
12799           address_mode = mode_16bit;
12800           priv.orig_sizeflag = 0;
12801         }
12802       else if (CONST_STRNEQ (p, "intel"))
12803         {
12804           intel_syntax = 1;
12805           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12806             intel_mnemonic = 1;
12807         }
12808       else if (CONST_STRNEQ (p, "att"))
12809         {
12810           intel_syntax = 0;
12811           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12812             intel_mnemonic = 0;
12813         }
12814       else if (CONST_STRNEQ (p, "addr"))
12815         {
12816           if (address_mode == mode_64bit)
12817             {
12818               if (p[4] == '3' && p[5] == '2')
12819                 priv.orig_sizeflag &= ~AFLAG;
12820               else if (p[4] == '6' && p[5] == '4')
12821                 priv.orig_sizeflag |= AFLAG;
12822             }
12823           else
12824             {
12825               if (p[4] == '1' && p[5] == '6')
12826                 priv.orig_sizeflag &= ~AFLAG;
12827               else if (p[4] == '3' && p[5] == '2')
12828                 priv.orig_sizeflag |= AFLAG;
12829             }
12830         }
12831       else if (CONST_STRNEQ (p, "data"))
12832         {
12833           if (p[4] == '1' && p[5] == '6')
12834             priv.orig_sizeflag &= ~DFLAG;
12835           else if (p[4] == '3' && p[5] == '2')
12836             priv.orig_sizeflag |= DFLAG;
12837         }
12838       else if (CONST_STRNEQ (p, "suffix"))
12839         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12840
12841       p = strchr (p, ',');
12842       if (p != NULL)
12843         p++;
12844     }
12845
12846   if (intel_syntax)
12847     {
12848       names64 = intel_names64;
12849       names32 = intel_names32;
12850       names16 = intel_names16;
12851       names8 = intel_names8;
12852       names8rex = intel_names8rex;
12853       names_seg = intel_names_seg;
12854       names_mm = intel_names_mm;
12855       names_bnd = intel_names_bnd;
12856       names_xmm = intel_names_xmm;
12857       names_ymm = intel_names_ymm;
12858       names_zmm = intel_names_zmm;
12859       index64 = intel_index64;
12860       index32 = intel_index32;
12861       names_mask = intel_names_mask;
12862       index16 = intel_index16;
12863       open_char = '[';
12864       close_char = ']';
12865       separator_char = '+';
12866       scale_char = '*';
12867     }
12868   else
12869     {
12870       names64 = att_names64;
12871       names32 = att_names32;
12872       names16 = att_names16;
12873       names8 = att_names8;
12874       names8rex = att_names8rex;
12875       names_seg = att_names_seg;
12876       names_mm = att_names_mm;
12877       names_bnd = att_names_bnd;
12878       names_xmm = att_names_xmm;
12879       names_ymm = att_names_ymm;
12880       names_zmm = att_names_zmm;
12881       index64 = att_index64;
12882       index32 = att_index32;
12883       names_mask = att_names_mask;
12884       index16 = att_index16;
12885       open_char = '(';
12886       close_char =  ')';
12887       separator_char = ',';
12888       scale_char = ',';
12889     }
12890
12891   /* The output looks better if we put 7 bytes on a line, since that
12892      puts most long word instructions on a single line.  Use 8 bytes
12893      for Intel L1OM.  */
12894   if ((info->mach & bfd_mach_l1om) != 0)
12895     info->bytes_per_line = 8;
12896   else
12897     info->bytes_per_line = 7;
12898
12899   info->private_data = &priv;
12900   priv.max_fetched = priv.the_buffer;
12901   priv.insn_start = pc;
12902
12903   obuf[0] = 0;
12904   for (i = 0; i < MAX_OPERANDS; ++i)
12905     {
12906       op_out[i][0] = 0;
12907       op_index[i] = -1;
12908     }
12909
12910   the_info = info;
12911   start_pc = pc;
12912   start_codep = priv.the_buffer;
12913   codep = priv.the_buffer;
12914
12915   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12916     {
12917       const char *name;
12918
12919       /* Getting here means we tried for data but didn't get it.  That
12920          means we have an incomplete instruction of some sort.  Just
12921          print the first byte as a prefix or a .byte pseudo-op.  */
12922       if (codep > priv.the_buffer)
12923         {
12924           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12925           if (name != NULL)
12926             (*info->fprintf_func) (info->stream, "%s", name);
12927           else
12928             {
12929               /* Just print the first byte as a .byte instruction.  */
12930               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12931                                      (unsigned int) priv.the_buffer[0]);
12932             }
12933
12934           return 1;
12935         }
12936
12937       return -1;
12938     }
12939
12940   obufp = obuf;
12941   sizeflag = priv.orig_sizeflag;
12942
12943   if (!ckprefix () || rex_used)
12944     {
12945       /* Too many prefixes or unused REX prefixes.  */
12946       for (i = 0;
12947            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12948            i++)
12949         (*info->fprintf_func) (info->stream, "%s%s",
12950                                i == 0 ? "" : " ",
12951                                prefix_name (all_prefixes[i], sizeflag));
12952       return i;
12953     }
12954
12955   insn_codep = codep;
12956
12957   FETCH_DATA (info, codep + 1);
12958   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12959
12960   if (((prefixes & PREFIX_FWAIT)
12961        && ((*codep < 0xd8) || (*codep > 0xdf))))
12962     {
12963       /* Handle prefixes before fwait.  */
12964       for (i = 0; i < fwait_prefix && all_prefixes[i];
12965            i++)
12966         (*info->fprintf_func) (info->stream, "%s ",
12967                                prefix_name (all_prefixes[i], sizeflag));
12968       (*info->fprintf_func) (info->stream, "fwait");
12969       return i + 1;
12970     }
12971
12972   if (*codep == 0x0f)
12973     {
12974       unsigned char threebyte;
12975       FETCH_DATA (info, codep + 2);
12976       threebyte = *++codep;
12977       dp = &dis386_twobyte[threebyte];
12978       need_modrm = twobyte_has_modrm[*codep];
12979       mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
12980       codep++;
12981     }
12982   else
12983     {
12984       dp = &dis386[*codep];
12985       need_modrm = onebyte_has_modrm[*codep];
12986       mandatory_prefix = 0;
12987       codep++;
12988     }
12989
12990   /* Save sizeflag for printing the extra prefixes later before updating
12991      it for mnemonic and operand processing.  The prefix names depend
12992      only on the address mode.  */
12993   orig_sizeflag = sizeflag;
12994   if (prefixes & PREFIX_ADDR)
12995     sizeflag ^= AFLAG;
12996   if ((prefixes & PREFIX_DATA))
12997     sizeflag ^= DFLAG;
12998
12999   end_codep = codep;
13000   if (need_modrm)
13001     {
13002       FETCH_DATA (info, codep + 1);
13003       modrm.mod = (*codep >> 6) & 3;
13004       modrm.reg = (*codep >> 3) & 7;
13005       modrm.rm = *codep & 7;
13006     }
13007
13008   need_vex = 0;
13009   need_vex_reg = 0;
13010   vex_w_done = 0;
13011   vex.evex = 0;
13012
13013   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13014     {
13015       get_sib (info, sizeflag);
13016       dofloat (sizeflag);
13017     }
13018   else
13019     {
13020       dp = get_valid_dis386 (dp, info);
13021       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13022         {
13023           get_sib (info, sizeflag);
13024           for (i = 0; i < MAX_OPERANDS; ++i)
13025             {
13026               obufp = op_out[i];
13027               op_ad = MAX_OPERANDS - 1 - i;
13028               if (dp->op[i].rtn)
13029                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13030               /* For EVEX instruction after the last operand masking
13031                  should be printed.  */
13032               if (i == 0 && vex.evex)
13033                 {
13034                   /* Don't print {%k0}.  */
13035                   if (vex.mask_register_specifier)
13036                     {
13037                       oappend ("{");
13038                       oappend (names_mask[vex.mask_register_specifier]);
13039                       oappend ("}");
13040                     }
13041                   if (vex.zeroing)
13042                     oappend ("{z}");
13043                 }
13044             }
13045         }
13046     }
13047
13048   /* Check if the REX prefix is used.  */
13049   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13050     all_prefixes[last_rex_prefix] = 0;
13051
13052   /* Check if the SEG prefix is used.  */
13053   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13054                    | PREFIX_FS | PREFIX_GS)) != 0
13055       && (used_prefixes & active_seg_prefix) != 0)
13056     all_prefixes[last_seg_prefix] = 0;
13057
13058   /* Check if the ADDR prefix is used.  */
13059   if ((prefixes & PREFIX_ADDR) != 0
13060       && (used_prefixes & PREFIX_ADDR) != 0)
13061     all_prefixes[last_addr_prefix] = 0;
13062
13063   /* Check if the DATA prefix is used.  */
13064   if ((prefixes & PREFIX_DATA) != 0
13065       && (used_prefixes & PREFIX_DATA) != 0)
13066     all_prefixes[last_data_prefix] = 0;
13067
13068   /* Print the extra prefixes.  */
13069   prefix_length = 0;
13070   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13071     if (all_prefixes[i])
13072       {
13073         const char *name;
13074         name = prefix_name (all_prefixes[i], orig_sizeflag);
13075         if (name == NULL)
13076           abort ();
13077         prefix_length += strlen (name) + 1;
13078         (*info->fprintf_func) (info->stream, "%s ", name);
13079       }
13080
13081   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13082      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13083      used by putop and MMX/SSE operand and may be overriden by the
13084      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13085      separately.  */
13086   if (mandatory_prefix
13087       && dp != &bad_opcode
13088       && (((prefixes
13089             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13090            && (used_prefixes
13091                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13092           || ((((prefixes
13093                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13094                 == PREFIX_DATA)
13095                && (used_prefixes & PREFIX_DATA) == 0))))
13096     {
13097       (*info->fprintf_func) (info->stream, "(bad)");
13098       return end_codep - priv.the_buffer;
13099     }
13100
13101   /* Check maximum code length.  */
13102   if ((codep - start_codep) > MAX_CODE_LENGTH)
13103     {
13104       (*info->fprintf_func) (info->stream, "(bad)");
13105       return MAX_CODE_LENGTH;
13106     }
13107
13108   obufp = mnemonicendp;
13109   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13110     oappend (" ");
13111   oappend (" ");
13112   (*info->fprintf_func) (info->stream, "%s", obuf);
13113
13114   /* The enter and bound instructions are printed with operands in the same
13115      order as the intel book; everything else is printed in reverse order.  */
13116   if (intel_syntax || two_source_ops)
13117     {
13118       bfd_vma riprel;
13119
13120       for (i = 0; i < MAX_OPERANDS; ++i)
13121         op_txt[i] = op_out[i];
13122
13123       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13124         {
13125           op_ad = op_index[i];
13126           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13127           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13128           riprel = op_riprel[i];
13129           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13130           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13131         }
13132     }
13133   else
13134     {
13135       for (i = 0; i < MAX_OPERANDS; ++i)
13136         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13137     }
13138
13139   needcomma = 0;
13140   for (i = 0; i < MAX_OPERANDS; ++i)
13141     if (*op_txt[i])
13142       {
13143         if (needcomma)
13144           (*info->fprintf_func) (info->stream, ",");
13145         if (op_index[i] != -1 && !op_riprel[i])
13146           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13147         else
13148           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13149         needcomma = 1;
13150       }
13151
13152   for (i = 0; i < MAX_OPERANDS; i++)
13153     if (op_index[i] != -1 && op_riprel[i])
13154       {
13155         (*info->fprintf_func) (info->stream, "        # ");
13156         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13157                                                 + op_address[op_index[i]]), info);
13158         break;
13159       }
13160   return codep - priv.the_buffer;
13161 }
13162
13163 static const char *float_mem[] = {
13164   /* d8 */
13165   "fadd{s|}",
13166   "fmul{s|}",
13167   "fcom{s|}",
13168   "fcomp{s|}",
13169   "fsub{s|}",
13170   "fsubr{s|}",
13171   "fdiv{s|}",
13172   "fdivr{s|}",
13173   /* d9 */
13174   "fld{s|}",
13175   "(bad)",
13176   "fst{s|}",
13177   "fstp{s|}",
13178   "fldenvIC",
13179   "fldcw",
13180   "fNstenvIC",
13181   "fNstcw",
13182   /* da */
13183   "fiadd{l|}",
13184   "fimul{l|}",
13185   "ficom{l|}",
13186   "ficomp{l|}",
13187   "fisub{l|}",
13188   "fisubr{l|}",
13189   "fidiv{l|}",
13190   "fidivr{l|}",
13191   /* db */
13192   "fild{l|}",
13193   "fisttp{l|}",
13194   "fist{l|}",
13195   "fistp{l|}",
13196   "(bad)",
13197   "fld{t||t|}",
13198   "(bad)",
13199   "fstp{t||t|}",
13200   /* dc */
13201   "fadd{l|}",
13202   "fmul{l|}",
13203   "fcom{l|}",
13204   "fcomp{l|}",
13205   "fsub{l|}",
13206   "fsubr{l|}",
13207   "fdiv{l|}",
13208   "fdivr{l|}",
13209   /* dd */
13210   "fld{l|}",
13211   "fisttp{ll|}",
13212   "fst{l||}",
13213   "fstp{l|}",
13214   "frstorIC",
13215   "(bad)",
13216   "fNsaveIC",
13217   "fNstsw",
13218   /* de */
13219   "fiadd",
13220   "fimul",
13221   "ficom",
13222   "ficomp",
13223   "fisub",
13224   "fisubr",
13225   "fidiv",
13226   "fidivr",
13227   /* df */
13228   "fild",
13229   "fisttp",
13230   "fist",
13231   "fistp",
13232   "fbld",
13233   "fild{ll|}",
13234   "fbstp",
13235   "fistp{ll|}",
13236 };
13237
13238 static const unsigned char float_mem_mode[] = {
13239   /* d8 */
13240   d_mode,
13241   d_mode,
13242   d_mode,
13243   d_mode,
13244   d_mode,
13245   d_mode,
13246   d_mode,
13247   d_mode,
13248   /* d9 */
13249   d_mode,
13250   0,
13251   d_mode,
13252   d_mode,
13253   0,
13254   w_mode,
13255   0,
13256   w_mode,
13257   /* da */
13258   d_mode,
13259   d_mode,
13260   d_mode,
13261   d_mode,
13262   d_mode,
13263   d_mode,
13264   d_mode,
13265   d_mode,
13266   /* db */
13267   d_mode,
13268   d_mode,
13269   d_mode,
13270   d_mode,
13271   0,
13272   t_mode,
13273   0,
13274   t_mode,
13275   /* dc */
13276   q_mode,
13277   q_mode,
13278   q_mode,
13279   q_mode,
13280   q_mode,
13281   q_mode,
13282   q_mode,
13283   q_mode,
13284   /* dd */
13285   q_mode,
13286   q_mode,
13287   q_mode,
13288   q_mode,
13289   0,
13290   0,
13291   0,
13292   w_mode,
13293   /* de */
13294   w_mode,
13295   w_mode,
13296   w_mode,
13297   w_mode,
13298   w_mode,
13299   w_mode,
13300   w_mode,
13301   w_mode,
13302   /* df */
13303   w_mode,
13304   w_mode,
13305   w_mode,
13306   w_mode,
13307   t_mode,
13308   q_mode,
13309   t_mode,
13310   q_mode
13311 };
13312
13313 #define ST { OP_ST, 0 }
13314 #define STi { OP_STi, 0 }
13315
13316 #define FGRPd9_2 NULL, { { NULL, 0 } }
13317 #define FGRPd9_4 NULL, { { NULL, 1 } }
13318 #define FGRPd9_5 NULL, { { NULL, 2 } }
13319 #define FGRPd9_6 NULL, { { NULL, 3 } }
13320 #define FGRPd9_7 NULL, { { NULL, 4 } }
13321 #define FGRPda_5 NULL, { { NULL, 5 } }
13322 #define FGRPdb_4 NULL, { { NULL, 6 } }
13323 #define FGRPde_3 NULL, { { NULL, 7 } }
13324 #define FGRPdf_4 NULL, { { NULL, 8 } }
13325
13326 static const struct dis386 float_reg[][8] = {
13327   /* d8 */
13328   {
13329     { "fadd",   { ST, STi } },
13330     { "fmul",   { ST, STi } },
13331     { "fcom",   { STi } },
13332     { "fcomp",  { STi } },
13333     { "fsub",   { ST, STi } },
13334     { "fsubr",  { ST, STi } },
13335     { "fdiv",   { ST, STi } },
13336     { "fdivr",  { ST, STi } },
13337   },
13338   /* d9 */
13339   {
13340     { "fld",    { STi } },
13341     { "fxch",   { STi } },
13342     { FGRPd9_2 },
13343     { Bad_Opcode },
13344     { FGRPd9_4 },
13345     { FGRPd9_5 },
13346     { FGRPd9_6 },
13347     { FGRPd9_7 },
13348   },
13349   /* da */
13350   {
13351     { "fcmovb", { ST, STi } },
13352     { "fcmove", { ST, STi } },
13353     { "fcmovbe",{ ST, STi } },
13354     { "fcmovu", { ST, STi } },
13355     { Bad_Opcode },
13356     { FGRPda_5 },
13357     { Bad_Opcode },
13358     { Bad_Opcode },
13359   },
13360   /* db */
13361   {
13362     { "fcmovnb",{ ST, STi } },
13363     { "fcmovne",{ ST, STi } },
13364     { "fcmovnbe",{ ST, STi } },
13365     { "fcmovnu",{ ST, STi } },
13366     { FGRPdb_4 },
13367     { "fucomi", { ST, STi } },
13368     { "fcomi",  { ST, STi } },
13369     { Bad_Opcode },
13370   },
13371   /* dc */
13372   {
13373     { "fadd",   { STi, ST } },
13374     { "fmul",   { STi, ST } },
13375     { Bad_Opcode },
13376     { Bad_Opcode },
13377     { "fsub!M", { STi, ST } },
13378     { "fsubM",  { STi, ST } },
13379     { "fdiv!M", { STi, ST } },
13380     { "fdivM",  { STi, ST } },
13381   },
13382   /* dd */
13383   {
13384     { "ffree",  { STi } },
13385     { Bad_Opcode },
13386     { "fst",    { STi } },
13387     { "fstp",   { STi } },
13388     { "fucom",  { STi } },
13389     { "fucomp", { STi } },
13390     { Bad_Opcode },
13391     { Bad_Opcode },
13392   },
13393   /* de */
13394   {
13395     { "faddp",  { STi, ST } },
13396     { "fmulp",  { STi, ST } },
13397     { Bad_Opcode },
13398     { FGRPde_3 },
13399     { "fsub!Mp", { STi, ST } },
13400     { "fsubMp", { STi, ST } },
13401     { "fdiv!Mp", { STi, ST } },
13402     { "fdivMp", { STi, ST } },
13403   },
13404   /* df */
13405   {
13406     { "ffreep", { STi } },
13407     { Bad_Opcode },
13408     { Bad_Opcode },
13409     { Bad_Opcode },
13410     { FGRPdf_4 },
13411     { "fucomip", { ST, STi } },
13412     { "fcomip", { ST, STi } },
13413     { Bad_Opcode },
13414   },
13415 };
13416
13417 static char *fgrps[][8] = {
13418   /* d9_2  0 */
13419   {
13420     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13421   },
13422
13423   /* d9_4  1 */
13424   {
13425     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13426   },
13427
13428   /* d9_5  2 */
13429   {
13430     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13431   },
13432
13433   /* d9_6  3 */
13434   {
13435     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13436   },
13437
13438   /* d9_7  4 */
13439   {
13440     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13441   },
13442
13443   /* da_5  5 */
13444   {
13445     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13446   },
13447
13448   /* db_4  6 */
13449   {
13450     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13451     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13452   },
13453
13454   /* de_3  7 */
13455   {
13456     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13457   },
13458
13459   /* df_4  8 */
13460   {
13461     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13462   },
13463 };
13464
13465 static void
13466 swap_operand (void)
13467 {
13468   mnemonicendp[0] = '.';
13469   mnemonicendp[1] = 's';
13470   mnemonicendp += 2;
13471 }
13472
13473 static void
13474 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13475                int sizeflag ATTRIBUTE_UNUSED)
13476 {
13477   /* Skip mod/rm byte.  */
13478   MODRM_CHECK;
13479   codep++;
13480 }
13481
13482 static void
13483 dofloat (int sizeflag)
13484 {
13485   const struct dis386 *dp;
13486   unsigned char floatop;
13487
13488   floatop = codep[-1];
13489
13490   if (modrm.mod != 3)
13491     {
13492       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13493
13494       putop (float_mem[fp_indx], sizeflag);
13495       obufp = op_out[0];
13496       op_ad = 2;
13497       OP_E (float_mem_mode[fp_indx], sizeflag);
13498       return;
13499     }
13500   /* Skip mod/rm byte.  */
13501   MODRM_CHECK;
13502   codep++;
13503
13504   dp = &float_reg[floatop - 0xd8][modrm.reg];
13505   if (dp->name == NULL)
13506     {
13507       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13508
13509       /* Instruction fnstsw is only one with strange arg.  */
13510       if (floatop == 0xdf && codep[-1] == 0xe0)
13511         strcpy (op_out[0], names16[0]);
13512     }
13513   else
13514     {
13515       putop (dp->name, sizeflag);
13516
13517       obufp = op_out[0];
13518       op_ad = 2;
13519       if (dp->op[0].rtn)
13520         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13521
13522       obufp = op_out[1];
13523       op_ad = 1;
13524       if (dp->op[1].rtn)
13525         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13526     }
13527 }
13528
13529 /* Like oappend (below), but S is a string starting with '%'.
13530    In Intel syntax, the '%' is elided.  */
13531 static void
13532 oappend_maybe_intel (const char *s)
13533 {
13534   oappend (s + intel_syntax);
13535 }
13536
13537 static void
13538 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13539 {
13540   oappend_maybe_intel ("%st");
13541 }
13542
13543 static void
13544 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13545 {
13546   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13547   oappend_maybe_intel (scratchbuf);
13548 }
13549
13550 /* Capital letters in template are macros.  */
13551 static int
13552 putop (const char *in_template, int sizeflag)
13553 {
13554   const char *p;
13555   int alt = 0;
13556   int cond = 1;
13557   unsigned int l = 0, len = 1;
13558   char last[4];
13559
13560 #define SAVE_LAST(c)                    \
13561   if (l < len && l < sizeof (last))     \
13562     last[l++] = c;                      \
13563   else                                  \
13564     abort ();
13565
13566   for (p = in_template; *p; p++)
13567     {
13568       switch (*p)
13569         {
13570         default:
13571           *obufp++ = *p;
13572           break;
13573         case '%':
13574           len++;
13575           break;
13576         case '!':
13577           cond = 0;
13578           break;
13579         case '{':
13580           alt = 0;
13581           if (intel_syntax)
13582             {
13583               while (*++p != '|')
13584                 if (*p == '}' || *p == '\0')
13585                   abort ();
13586             }
13587           /* Fall through.  */
13588         case 'I':
13589           alt = 1;
13590           continue;
13591         case '|':
13592           while (*++p != '}')
13593             {
13594               if (*p == '\0')
13595                 abort ();
13596             }
13597           break;
13598         case '}':
13599           break;
13600         case 'A':
13601           if (intel_syntax)
13602             break;
13603           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13604             *obufp++ = 'b';
13605           break;
13606         case 'B':
13607           if (l == 0 && len == 1)
13608             {
13609 case_B:
13610               if (intel_syntax)
13611                 break;
13612               if (sizeflag & SUFFIX_ALWAYS)
13613                 *obufp++ = 'b';
13614             }
13615           else
13616             {
13617               if (l != 1
13618                   || len != 2
13619                   || last[0] != 'L')
13620                 {
13621                   SAVE_LAST (*p);
13622                   break;
13623                 }
13624
13625               if (address_mode == mode_64bit
13626                   && !(prefixes & PREFIX_ADDR))
13627                 {
13628                   *obufp++ = 'a';
13629                   *obufp++ = 'b';
13630                   *obufp++ = 's';
13631                 }
13632
13633               goto case_B;
13634             }
13635           break;
13636         case 'C':
13637           if (intel_syntax && !alt)
13638             break;
13639           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13640             {
13641               if (sizeflag & DFLAG)
13642                 *obufp++ = intel_syntax ? 'd' : 'l';
13643               else
13644                 *obufp++ = intel_syntax ? 'w' : 's';
13645               used_prefixes |= (prefixes & PREFIX_DATA);
13646             }
13647           break;
13648         case 'D':
13649           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13650             break;
13651           USED_REX (REX_W);
13652           if (modrm.mod == 3)
13653             {
13654               if (rex & REX_W)
13655                 *obufp++ = 'q';
13656               else
13657                 {
13658                   if (sizeflag & DFLAG)
13659                     *obufp++ = intel_syntax ? 'd' : 'l';
13660                   else
13661                     *obufp++ = 'w';
13662                   used_prefixes |= (prefixes & PREFIX_DATA);
13663                 }
13664             }
13665           else
13666             *obufp++ = 'w';
13667           break;
13668         case 'E':               /* For jcxz/jecxz */
13669           if (address_mode == mode_64bit)
13670             {
13671               if (sizeflag & AFLAG)
13672                 *obufp++ = 'r';
13673               else
13674                 *obufp++ = 'e';
13675             }
13676           else
13677             if (sizeflag & AFLAG)
13678               *obufp++ = 'e';
13679           used_prefixes |= (prefixes & PREFIX_ADDR);
13680           break;
13681         case 'F':
13682           if (intel_syntax)
13683             break;
13684           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13685             {
13686               if (sizeflag & AFLAG)
13687                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13688               else
13689                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13690               used_prefixes |= (prefixes & PREFIX_ADDR);
13691             }
13692           break;
13693         case 'G':
13694           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13695             break;
13696           if ((rex & REX_W) || (sizeflag & DFLAG))
13697             *obufp++ = 'l';
13698           else
13699             *obufp++ = 'w';
13700           if (!(rex & REX_W))
13701             used_prefixes |= (prefixes & PREFIX_DATA);
13702           break;
13703         case 'H':
13704           if (intel_syntax)
13705             break;
13706           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13707               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13708             {
13709               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13710               *obufp++ = ',';
13711               *obufp++ = 'p';
13712               if (prefixes & PREFIX_DS)
13713                 *obufp++ = 't';
13714               else
13715                 *obufp++ = 'n';
13716             }
13717           break;
13718         case 'J':
13719           if (intel_syntax)
13720             break;
13721           *obufp++ = 'l';
13722           break;
13723         case 'K':
13724           USED_REX (REX_W);
13725           if (rex & REX_W)
13726             *obufp++ = 'q';
13727           else
13728             *obufp++ = 'd';
13729           break;
13730         case 'Z':
13731           if (intel_syntax)
13732             break;
13733           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13734             {
13735               *obufp++ = 'q';
13736               break;
13737             }
13738           /* Fall through.  */
13739           goto case_L;
13740         case 'L':
13741           if (l != 0 || len != 1)
13742             {
13743               SAVE_LAST (*p);
13744               break;
13745             }
13746 case_L:
13747           if (intel_syntax)
13748             break;
13749           if (sizeflag & SUFFIX_ALWAYS)
13750             *obufp++ = 'l';
13751           break;
13752         case 'M':
13753           if (intel_mnemonic != cond)
13754             *obufp++ = 'r';
13755           break;
13756         case 'N':
13757           if ((prefixes & PREFIX_FWAIT) == 0)
13758             *obufp++ = 'n';
13759           else
13760             used_prefixes |= PREFIX_FWAIT;
13761           break;
13762         case 'O':
13763           USED_REX (REX_W);
13764           if (rex & REX_W)
13765             *obufp++ = 'o';
13766           else if (intel_syntax && (sizeflag & DFLAG))
13767             *obufp++ = 'q';
13768           else
13769             *obufp++ = 'd';
13770           if (!(rex & REX_W))
13771             used_prefixes |= (prefixes & PREFIX_DATA);
13772           break;
13773         case 'T':
13774           if (!intel_syntax
13775               && address_mode == mode_64bit
13776               && ((sizeflag & DFLAG) || (rex & REX_W)))
13777             {
13778               *obufp++ = 'q';
13779               break;
13780             }
13781           /* Fall through.  */
13782         case 'P':
13783           if (intel_syntax)
13784             {
13785               if ((rex & REX_W) == 0
13786                   && (prefixes & PREFIX_DATA))
13787                 {
13788                   if ((sizeflag & DFLAG) == 0)
13789                     *obufp++ = 'w';
13790                    used_prefixes |= (prefixes & PREFIX_DATA);
13791                 }
13792               break;
13793             }
13794           if ((prefixes & PREFIX_DATA)
13795               || (rex & REX_W)
13796               || (sizeflag & SUFFIX_ALWAYS))
13797             {
13798               USED_REX (REX_W);
13799               if (rex & REX_W)
13800                 *obufp++ = 'q';
13801               else
13802                 {
13803                    if (sizeflag & DFLAG)
13804                       *obufp++ = 'l';
13805                    else
13806                      *obufp++ = 'w';
13807                    used_prefixes |= (prefixes & PREFIX_DATA);
13808                 }
13809             }
13810           break;
13811         case 'U':
13812           if (intel_syntax)
13813             break;
13814           if (address_mode == mode_64bit
13815               && ((sizeflag & DFLAG) || (rex & REX_W)))
13816             {
13817               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13818                 *obufp++ = 'q';
13819               break;
13820             }
13821           /* Fall through.  */
13822           goto case_Q;
13823         case 'Q':
13824           if (l == 0 && len == 1)
13825             {
13826 case_Q:
13827               if (intel_syntax && !alt)
13828                 break;
13829               USED_REX (REX_W);
13830               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13831                 {
13832                   if (rex & REX_W)
13833                     *obufp++ = 'q';
13834                   else
13835                     {
13836                       if (sizeflag & DFLAG)
13837                         *obufp++ = intel_syntax ? 'd' : 'l';
13838                       else
13839                         *obufp++ = 'w';
13840                       used_prefixes |= (prefixes & PREFIX_DATA);
13841                     }
13842                 }
13843             }
13844           else
13845             {
13846               if (l != 1 || len != 2 || last[0] != 'L')
13847                 {
13848                   SAVE_LAST (*p);
13849                   break;
13850                 }
13851               if (intel_syntax
13852                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13853                 break;
13854               if ((rex & REX_W))
13855                 {
13856                   USED_REX (REX_W);
13857                   *obufp++ = 'q';
13858                 }
13859               else
13860                 *obufp++ = 'l';
13861             }
13862           break;
13863         case 'R':
13864           USED_REX (REX_W);
13865           if (rex & REX_W)
13866             *obufp++ = 'q';
13867           else if (sizeflag & DFLAG)
13868             {
13869               if (intel_syntax)
13870                   *obufp++ = 'd';
13871               else
13872                   *obufp++ = 'l';
13873             }
13874           else
13875             *obufp++ = 'w';
13876           if (intel_syntax && !p[1]
13877               && ((rex & REX_W) || (sizeflag & DFLAG)))
13878             *obufp++ = 'e';
13879           if (!(rex & REX_W))
13880             used_prefixes |= (prefixes & PREFIX_DATA);
13881           break;
13882         case 'V':
13883           if (l == 0 && len == 1)
13884             {
13885               if (intel_syntax)
13886                 break;
13887               if (address_mode == mode_64bit
13888                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13889                 {
13890                   if (sizeflag & SUFFIX_ALWAYS)
13891                     *obufp++ = 'q';
13892                   break;
13893                 }
13894             }
13895           else
13896             {
13897               if (l != 1
13898                   || len != 2
13899                   || last[0] != 'L')
13900                 {
13901                   SAVE_LAST (*p);
13902                   break;
13903                 }
13904
13905               if (rex & REX_W)
13906                 {
13907                   *obufp++ = 'a';
13908                   *obufp++ = 'b';
13909                   *obufp++ = 's';
13910                 }
13911             }
13912           /* Fall through.  */
13913           goto case_S;
13914         case 'S':
13915           if (l == 0 && len == 1)
13916             {
13917 case_S:
13918               if (intel_syntax)
13919                 break;
13920               if (sizeflag & SUFFIX_ALWAYS)
13921                 {
13922                   if (rex & REX_W)
13923                     *obufp++ = 'q';
13924                   else
13925                     {
13926                       if (sizeflag & DFLAG)
13927                         *obufp++ = 'l';
13928                       else
13929                         *obufp++ = 'w';
13930                       used_prefixes |= (prefixes & PREFIX_DATA);
13931                     }
13932                 }
13933             }
13934           else
13935             {
13936               if (l != 1
13937                   || len != 2
13938                   || last[0] != 'L')
13939                 {
13940                   SAVE_LAST (*p);
13941                   break;
13942                 }
13943
13944               if (address_mode == mode_64bit
13945                   && !(prefixes & PREFIX_ADDR))
13946                 {
13947                   *obufp++ = 'a';
13948                   *obufp++ = 'b';
13949                   *obufp++ = 's';
13950                 }
13951
13952               goto case_S;
13953             }
13954           break;
13955         case 'X':
13956           if (l != 0 || len != 1)
13957             {
13958               SAVE_LAST (*p);
13959               break;
13960             }
13961           if (need_vex && vex.prefix)
13962             {
13963               if (vex.prefix == DATA_PREFIX_OPCODE)
13964                 *obufp++ = 'd';
13965               else
13966                 *obufp++ = 's';
13967             }
13968           else
13969             {
13970               if (prefixes & PREFIX_DATA)
13971                 *obufp++ = 'd';
13972               else
13973                 *obufp++ = 's';
13974               used_prefixes |= (prefixes & PREFIX_DATA);
13975             }
13976           break;
13977         case 'Y':
13978           if (l == 0 && len == 1)
13979             {
13980               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13981                 break;
13982               if (rex & REX_W)
13983                 {
13984                   USED_REX (REX_W);
13985                   *obufp++ = 'q';
13986                 }
13987               break;
13988             }
13989           else
13990             {
13991               if (l != 1 || len != 2 || last[0] != 'X')
13992                 {
13993                   SAVE_LAST (*p);
13994                   break;
13995                 }
13996               if (!need_vex)
13997                 abort ();
13998               if (intel_syntax
13999                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14000                 break;
14001               switch (vex.length)
14002                 {
14003                 case 128:
14004                   *obufp++ = 'x';
14005                   break;
14006                 case 256:
14007                   *obufp++ = 'y';
14008                   break;
14009                 default:
14010                   abort ();
14011                 }
14012             }
14013           break;
14014         case 'W':
14015           if (l == 0 && len == 1)
14016             {
14017               /* operand size flag for cwtl, cbtw */
14018               USED_REX (REX_W);
14019               if (rex & REX_W)
14020                 {
14021                   if (intel_syntax)
14022                     *obufp++ = 'd';
14023                   else
14024                     *obufp++ = 'l';
14025                 }
14026               else if (sizeflag & DFLAG)
14027                 *obufp++ = 'w';
14028               else
14029                 *obufp++ = 'b';
14030               if (!(rex & REX_W))
14031                 used_prefixes |= (prefixes & PREFIX_DATA);
14032             }
14033           else
14034             {
14035               if (l != 1
14036                   || len != 2
14037                   || (last[0] != 'X'
14038                       && last[0] != 'L'))
14039                 {
14040                   SAVE_LAST (*p);
14041                   break;
14042                 }
14043               if (!need_vex)
14044                 abort ();
14045               if (last[0] == 'X')
14046                 *obufp++ = vex.w ? 'd': 's';
14047               else
14048                 *obufp++ = vex.w ? 'q': 'd';
14049             }
14050           break;
14051         }
14052       alt = 0;
14053     }
14054   *obufp = 0;
14055   mnemonicendp = obufp;
14056   return 0;
14057 }
14058
14059 static void
14060 oappend (const char *s)
14061 {
14062   obufp = stpcpy (obufp, s);
14063 }
14064
14065 static void
14066 append_seg (void)
14067 {
14068   /* Only print the active segment register.  */
14069   if (!active_seg_prefix)
14070     return;
14071
14072   used_prefixes |= active_seg_prefix;
14073   switch (active_seg_prefix)
14074     {
14075     case PREFIX_CS:
14076       oappend_maybe_intel ("%cs:");
14077       break;
14078     case PREFIX_DS:
14079       oappend_maybe_intel ("%ds:");
14080       break;
14081     case PREFIX_SS:
14082       oappend_maybe_intel ("%ss:");
14083       break;
14084     case PREFIX_ES:
14085       oappend_maybe_intel ("%es:");
14086       break;
14087     case PREFIX_FS:
14088       oappend_maybe_intel ("%fs:");
14089       break;
14090     case PREFIX_GS:
14091       oappend_maybe_intel ("%gs:");
14092       break;
14093     default:
14094       break;
14095     }
14096 }
14097
14098 static void
14099 OP_indirE (int bytemode, int sizeflag)
14100 {
14101   if (!intel_syntax)
14102     oappend ("*");
14103   OP_E (bytemode, sizeflag);
14104 }
14105
14106 static void
14107 print_operand_value (char *buf, int hex, bfd_vma disp)
14108 {
14109   if (address_mode == mode_64bit)
14110     {
14111       if (hex)
14112         {
14113           char tmp[30];
14114           int i;
14115           buf[0] = '0';
14116           buf[1] = 'x';
14117           sprintf_vma (tmp, disp);
14118           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14119           strcpy (buf + 2, tmp + i);
14120         }
14121       else
14122         {
14123           bfd_signed_vma v = disp;
14124           char tmp[30];
14125           int i;
14126           if (v < 0)
14127             {
14128               *(buf++) = '-';
14129               v = -disp;
14130               /* Check for possible overflow on 0x8000000000000000.  */
14131               if (v < 0)
14132                 {
14133                   strcpy (buf, "9223372036854775808");
14134                   return;
14135                 }
14136             }
14137           if (!v)
14138             {
14139               strcpy (buf, "0");
14140               return;
14141             }
14142
14143           i = 0;
14144           tmp[29] = 0;
14145           while (v)
14146             {
14147               tmp[28 - i] = (v % 10) + '0';
14148               v /= 10;
14149               i++;
14150             }
14151           strcpy (buf, tmp + 29 - i);
14152         }
14153     }
14154   else
14155     {
14156       if (hex)
14157         sprintf (buf, "0x%x", (unsigned int) disp);
14158       else
14159         sprintf (buf, "%d", (int) disp);
14160     }
14161 }
14162
14163 /* Put DISP in BUF as signed hex number.  */
14164
14165 static void
14166 print_displacement (char *buf, bfd_vma disp)
14167 {
14168   bfd_signed_vma val = disp;
14169   char tmp[30];
14170   int i, j = 0;
14171
14172   if (val < 0)
14173     {
14174       buf[j++] = '-';
14175       val = -disp;
14176
14177       /* Check for possible overflow.  */
14178       if (val < 0)
14179         {
14180           switch (address_mode)
14181             {
14182             case mode_64bit:
14183               strcpy (buf + j, "0x8000000000000000");
14184               break;
14185             case mode_32bit:
14186               strcpy (buf + j, "0x80000000");
14187               break;
14188             case mode_16bit:
14189               strcpy (buf + j, "0x8000");
14190               break;
14191             }
14192           return;
14193         }
14194     }
14195
14196   buf[j++] = '0';
14197   buf[j++] = 'x';
14198
14199   sprintf_vma (tmp, (bfd_vma) val);
14200   for (i = 0; tmp[i] == '0'; i++)
14201     continue;
14202   if (tmp[i] == '\0')
14203     i--;
14204   strcpy (buf + j, tmp + i);
14205 }
14206
14207 static void
14208 intel_operand_size (int bytemode, int sizeflag)
14209 {
14210   if (vex.evex
14211       && vex.b
14212       && (bytemode == x_mode
14213           || bytemode == evex_half_bcst_xmmq_mode))
14214     {
14215       if (vex.w)
14216         oappend ("QWORD PTR ");
14217       else
14218         oappend ("DWORD PTR ");
14219       return;
14220     }
14221   switch (bytemode)
14222     {
14223     case b_mode:
14224     case b_swap_mode:
14225     case dqb_mode:
14226     case db_mode:
14227       oappend ("BYTE PTR ");
14228       break;
14229     case w_mode:
14230     case dw_mode:
14231     case dqw_mode:
14232     case dqw_swap_mode:
14233       oappend ("WORD PTR ");
14234       break;
14235     case stack_v_mode:
14236       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14237         {
14238           oappend ("QWORD PTR ");
14239           break;
14240         }
14241       /* FALLTHRU */
14242     case v_mode:
14243     case v_swap_mode:
14244     case dq_mode:
14245       USED_REX (REX_W);
14246       if (rex & REX_W)
14247         oappend ("QWORD PTR ");
14248       else
14249         {
14250           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14251             oappend ("DWORD PTR ");
14252           else
14253             oappend ("WORD PTR ");
14254           used_prefixes |= (prefixes & PREFIX_DATA);
14255         }
14256       break;
14257     case z_mode:
14258       if ((rex & REX_W) || (sizeflag & DFLAG))
14259         *obufp++ = 'D';
14260       oappend ("WORD PTR ");
14261       if (!(rex & REX_W))
14262         used_prefixes |= (prefixes & PREFIX_DATA);
14263       break;
14264     case a_mode:
14265       if (sizeflag & DFLAG)
14266         oappend ("QWORD PTR ");
14267       else
14268         oappend ("DWORD PTR ");
14269       used_prefixes |= (prefixes & PREFIX_DATA);
14270       break;
14271     case d_mode:
14272     case d_scalar_mode:
14273     case d_scalar_swap_mode:
14274     case d_swap_mode:
14275     case dqd_mode:
14276       oappend ("DWORD PTR ");
14277       break;
14278     case q_mode:
14279     case q_scalar_mode:
14280     case q_scalar_swap_mode:
14281     case q_swap_mode:
14282       oappend ("QWORD PTR ");
14283       break;
14284     case m_mode:
14285       if (address_mode == mode_64bit)
14286         oappend ("QWORD PTR ");
14287       else
14288         oappend ("DWORD PTR ");
14289       break;
14290     case f_mode:
14291       if (sizeflag & DFLAG)
14292         oappend ("FWORD PTR ");
14293       else
14294         oappend ("DWORD PTR ");
14295       used_prefixes |= (prefixes & PREFIX_DATA);
14296       break;
14297     case t_mode:
14298       oappend ("TBYTE PTR ");
14299       break;
14300     case x_mode:
14301     case x_swap_mode:
14302     case evex_x_gscat_mode:
14303     case evex_x_nobcst_mode:
14304       if (need_vex)
14305         {
14306           switch (vex.length)
14307             {
14308             case 128:
14309               oappend ("XMMWORD PTR ");
14310               break;
14311             case 256:
14312               oappend ("YMMWORD PTR ");
14313               break;
14314             case 512:
14315               oappend ("ZMMWORD PTR ");
14316               break;
14317             default:
14318               abort ();
14319             }
14320         }
14321       else
14322         oappend ("XMMWORD PTR ");
14323       break;
14324     case xmm_mode:
14325       oappend ("XMMWORD PTR ");
14326       break;
14327     case ymm_mode:
14328       oappend ("YMMWORD PTR ");
14329       break;
14330     case xmmq_mode:
14331     case evex_half_bcst_xmmq_mode:
14332       if (!need_vex)
14333         abort ();
14334
14335       switch (vex.length)
14336         {
14337         case 128:
14338           oappend ("QWORD PTR ");
14339           break;
14340         case 256:
14341           oappend ("XMMWORD PTR ");
14342           break;
14343         case 512:
14344           oappend ("YMMWORD PTR ");
14345           break;
14346         default:
14347           abort ();
14348         }
14349       break;
14350     case xmm_mb_mode:
14351       if (!need_vex)
14352         abort ();
14353
14354       switch (vex.length)
14355         {
14356         case 128:
14357         case 256:
14358         case 512:
14359           oappend ("BYTE PTR ");
14360           break;
14361         default:
14362           abort ();
14363         }
14364       break;
14365     case xmm_mw_mode:
14366       if (!need_vex)
14367         abort ();
14368
14369       switch (vex.length)
14370         {
14371         case 128:
14372         case 256:
14373         case 512:
14374           oappend ("WORD PTR ");
14375           break;
14376         default:
14377           abort ();
14378         }
14379       break;
14380     case xmm_md_mode:
14381       if (!need_vex)
14382         abort ();
14383
14384       switch (vex.length)
14385         {
14386         case 128:
14387         case 256:
14388         case 512:
14389           oappend ("DWORD PTR ");
14390           break;
14391         default:
14392           abort ();
14393         }
14394       break;
14395     case xmm_mq_mode:
14396       if (!need_vex)
14397         abort ();
14398
14399       switch (vex.length)
14400         {
14401         case 128:
14402         case 256:
14403         case 512:
14404           oappend ("QWORD PTR ");
14405           break;
14406         default:
14407           abort ();
14408         }
14409       break;
14410     case xmmdw_mode:
14411       if (!need_vex)
14412         abort ();
14413
14414       switch (vex.length)
14415         {
14416         case 128:
14417           oappend ("WORD PTR ");
14418           break;
14419         case 256:
14420           oappend ("DWORD PTR ");
14421           break;
14422         case 512:
14423           oappend ("QWORD PTR ");
14424           break;
14425         default:
14426           abort ();
14427         }
14428       break;
14429     case xmmqd_mode:
14430       if (!need_vex)
14431         abort ();
14432
14433       switch (vex.length)
14434         {
14435         case 128:
14436           oappend ("DWORD PTR ");
14437           break;
14438         case 256:
14439           oappend ("QWORD PTR ");
14440           break;
14441         case 512:
14442           oappend ("XMMWORD PTR ");
14443           break;
14444         default:
14445           abort ();
14446         }
14447       break;
14448     case ymmq_mode:
14449       if (!need_vex)
14450         abort ();
14451
14452       switch (vex.length)
14453         {
14454         case 128:
14455           oappend ("QWORD PTR ");
14456           break;
14457         case 256:
14458           oappend ("YMMWORD PTR ");
14459           break;
14460         case 512:
14461           oappend ("ZMMWORD PTR ");
14462           break;
14463         default:
14464           abort ();
14465         }
14466       break;
14467     case ymmxmm_mode:
14468       if (!need_vex)
14469         abort ();
14470
14471       switch (vex.length)
14472         {
14473         case 128:
14474         case 256:
14475           oappend ("XMMWORD PTR ");
14476           break;
14477         default:
14478           abort ();
14479         }
14480       break;
14481     case o_mode:
14482       oappend ("OWORD PTR ");
14483       break;
14484     case xmm_mdq_mode:
14485     case vex_w_dq_mode:
14486     case vex_scalar_w_dq_mode:
14487       if (!need_vex)
14488         abort ();
14489
14490       if (vex.w)
14491         oappend ("QWORD PTR ");
14492       else
14493         oappend ("DWORD PTR ");
14494       break;
14495     case vex_vsib_d_w_dq_mode:
14496     case vex_vsib_q_w_dq_mode:
14497       if (!need_vex)
14498         abort ();
14499
14500       if (!vex.evex)
14501         {
14502           if (vex.w)
14503             oappend ("QWORD PTR ");
14504           else
14505             oappend ("DWORD PTR ");
14506         }
14507       else
14508         {
14509           switch (vex.length)
14510             {
14511             case 128:
14512               oappend ("XMMWORD PTR ");
14513               break;
14514             case 256:
14515               oappend ("YMMWORD PTR ");
14516               break;
14517             case 512:
14518               oappend ("ZMMWORD PTR ");
14519               break;
14520             default:
14521               abort ();
14522             }
14523         }
14524       break;
14525     case vex_vsib_q_w_d_mode:
14526     case vex_vsib_d_w_d_mode:
14527       if (!need_vex || !vex.evex)
14528         abort ();
14529
14530       switch (vex.length)
14531         {
14532         case 128:
14533           oappend ("QWORD PTR ");
14534           break;
14535         case 256:
14536           oappend ("XMMWORD PTR ");
14537           break;
14538         case 512:
14539           oappend ("YMMWORD PTR ");
14540           break;
14541         default:
14542           abort ();
14543         }
14544
14545       break;
14546     case mask_bd_mode:
14547       if (!need_vex || vex.length != 128)
14548         abort ();
14549       if (vex.w)
14550         oappend ("DWORD PTR ");
14551       else
14552         oappend ("BYTE PTR ");
14553       break;
14554     case mask_mode:
14555       if (!need_vex)
14556         abort ();
14557       if (vex.w)
14558         oappend ("QWORD PTR ");
14559       else
14560         oappend ("WORD PTR ");
14561       break;
14562     case v_bnd_mode:
14563     default:
14564       break;
14565     }
14566 }
14567
14568 static void
14569 OP_E_register (int bytemode, int sizeflag)
14570 {
14571   int reg = modrm.rm;
14572   const char **names;
14573
14574   USED_REX (REX_B);
14575   if ((rex & REX_B))
14576     reg += 8;
14577
14578   if ((sizeflag & SUFFIX_ALWAYS)
14579       && (bytemode == b_swap_mode
14580           || bytemode == v_swap_mode
14581           || bytemode == dqw_swap_mode))
14582     swap_operand ();
14583
14584   switch (bytemode)
14585     {
14586     case b_mode:
14587     case b_swap_mode:
14588       USED_REX (0);
14589       if (rex)
14590         names = names8rex;
14591       else
14592         names = names8;
14593       break;
14594     case w_mode:
14595       names = names16;
14596       break;
14597     case d_mode:
14598     case dw_mode:
14599     case db_mode:
14600       names = names32;
14601       break;
14602     case q_mode:
14603       names = names64;
14604       break;
14605     case m_mode:
14606     case v_bnd_mode:
14607       names = address_mode == mode_64bit ? names64 : names32;
14608       break;
14609     case bnd_mode:
14610       names = names_bnd;
14611       break;
14612     case stack_v_mode:
14613       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14614         {
14615           names = names64;
14616           break;
14617         }
14618       bytemode = v_mode;
14619       /* FALLTHRU */
14620     case v_mode:
14621     case v_swap_mode:
14622     case dq_mode:
14623     case dqb_mode:
14624     case dqd_mode:
14625     case dqw_mode:
14626     case dqw_swap_mode:
14627       USED_REX (REX_W);
14628       if (rex & REX_W)
14629         names = names64;
14630       else
14631         {
14632           if ((sizeflag & DFLAG)
14633               || (bytemode != v_mode
14634                   && bytemode != v_swap_mode))
14635             names = names32;
14636           else
14637             names = names16;
14638           used_prefixes |= (prefixes & PREFIX_DATA);
14639         }
14640       break;
14641     case mask_bd_mode:
14642     case mask_mode:
14643       names = names_mask;
14644       break;
14645     case 0:
14646       return;
14647     default:
14648       oappend (INTERNAL_DISASSEMBLER_ERROR);
14649       return;
14650     }
14651   oappend (names[reg]);
14652 }
14653
14654 static void
14655 OP_E_memory (int bytemode, int sizeflag)
14656 {
14657   bfd_vma disp = 0;
14658   int add = (rex & REX_B) ? 8 : 0;
14659   int riprel = 0;
14660   int shift;
14661
14662   if (vex.evex)
14663     {
14664       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14665       if (vex.b
14666           && bytemode != x_mode
14667           && bytemode != evex_half_bcst_xmmq_mode)
14668         {
14669           BadOp ();
14670           return;
14671         }
14672       switch (bytemode)
14673         {
14674         case dqw_mode:
14675         case dw_mode:
14676         case dqw_swap_mode:
14677           shift = 1;
14678           break;
14679         case dqb_mode:
14680         case db_mode:
14681           shift = 0;
14682           break;
14683         case vex_vsib_d_w_dq_mode:
14684         case vex_vsib_d_w_d_mode:
14685         case vex_vsib_q_w_dq_mode:
14686         case vex_vsib_q_w_d_mode:
14687         case evex_x_gscat_mode:
14688         case xmm_mdq_mode:
14689           shift = vex.w ? 3 : 2;
14690           break;
14691         case x_mode:
14692         case evex_half_bcst_xmmq_mode:
14693           if (vex.b)
14694             {
14695               shift = vex.w ? 3 : 2;
14696               break;
14697             }
14698           /* Fall through if vex.b == 0.  */
14699         case xmmqd_mode:
14700         case xmmdw_mode:
14701         case xmmq_mode:
14702         case ymmq_mode:
14703         case evex_x_nobcst_mode:
14704         case x_swap_mode:
14705           switch (vex.length)
14706             {
14707             case 128:
14708               shift = 4;
14709               break;
14710             case 256:
14711               shift = 5;
14712               break;
14713             case 512:
14714               shift = 6;
14715               break;
14716             default:
14717               abort ();
14718             }
14719           break;
14720         case ymm_mode:
14721           shift = 5;
14722           break;
14723         case xmm_mode:
14724           shift = 4;
14725           break;
14726         case xmm_mq_mode:
14727         case q_mode:
14728         case q_scalar_mode:
14729         case q_swap_mode:
14730         case q_scalar_swap_mode:
14731           shift = 3;
14732           break;
14733         case dqd_mode:
14734         case xmm_md_mode:
14735         case d_mode:
14736         case d_scalar_mode:
14737         case d_swap_mode:
14738         case d_scalar_swap_mode:
14739           shift = 2;
14740           break;
14741         case xmm_mw_mode:
14742           shift = 1;
14743           break;
14744         case xmm_mb_mode:
14745           shift = 0;
14746           break;
14747         default:
14748           abort ();
14749         }
14750       /* Make necessary corrections to shift for modes that need it.
14751          For these modes we currently have shift 4, 5 or 6 depending on
14752          vex.length (it corresponds to xmmword, ymmword or zmmword
14753          operand).  We might want to make it 3, 4 or 5 (e.g. for
14754          xmmq_mode).  In case of broadcast enabled the corrections
14755          aren't needed, as element size is always 32 or 64 bits.  */
14756       if (bytemode == xmmq_mode
14757           || (bytemode == evex_half_bcst_xmmq_mode
14758               && !vex.b))
14759         shift -= 1;
14760       else if (bytemode == xmmqd_mode)
14761         shift -= 2;
14762       else if (bytemode == xmmdw_mode)
14763         shift -= 3;
14764       else if (bytemode == ymmq_mode && vex.length == 128)
14765         shift -= 1;
14766     }
14767   else
14768     shift = 0;
14769
14770   USED_REX (REX_B);
14771   if (intel_syntax)
14772     intel_operand_size (bytemode, sizeflag);
14773   append_seg ();
14774
14775   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14776     {
14777       /* 32/64 bit address mode */
14778       int havedisp;
14779       int havesib;
14780       int havebase;
14781       int haveindex;
14782       int needindex;
14783       int base, rbase;
14784       int vindex = 0;
14785       int scale = 0;
14786       int addr32flag = !((sizeflag & AFLAG)
14787                          || bytemode == v_bnd_mode
14788                          || bytemode == bnd_mode);
14789       const char **indexes64 = names64;
14790       const char **indexes32 = names32;
14791
14792       havesib = 0;
14793       havebase = 1;
14794       haveindex = 0;
14795       base = modrm.rm;
14796
14797       if (base == 4)
14798         {
14799           havesib = 1;
14800           vindex = sib.index;
14801           USED_REX (REX_X);
14802           if (rex & REX_X)
14803             vindex += 8;
14804           switch (bytemode)
14805             {
14806             case vex_vsib_d_w_dq_mode:
14807             case vex_vsib_d_w_d_mode:
14808             case vex_vsib_q_w_dq_mode:
14809             case vex_vsib_q_w_d_mode:
14810               if (!need_vex)
14811                 abort ();
14812               if (vex.evex)
14813                 {
14814                   if (!vex.v)
14815                     vindex += 16;
14816                 }
14817
14818               haveindex = 1;
14819               switch (vex.length)
14820                 {
14821                 case 128:
14822                   indexes64 = indexes32 = names_xmm;
14823                   break;
14824                 case 256:
14825                   if (!vex.w
14826                       || bytemode == vex_vsib_q_w_dq_mode
14827                       || bytemode == vex_vsib_q_w_d_mode)
14828                     indexes64 = indexes32 = names_ymm;
14829                   else
14830                     indexes64 = indexes32 = names_xmm;
14831                   break;
14832                 case 512:
14833                   if (!vex.w
14834                       || bytemode == vex_vsib_q_w_dq_mode
14835                       || bytemode == vex_vsib_q_w_d_mode)
14836                     indexes64 = indexes32 = names_zmm;
14837                   else
14838                     indexes64 = indexes32 = names_ymm;
14839                   break;
14840                 default:
14841                   abort ();
14842                 }
14843               break;
14844             default:
14845               haveindex = vindex != 4;
14846               break;
14847             }
14848           scale = sib.scale;
14849           base = sib.base;
14850           codep++;
14851         }
14852       rbase = base + add;
14853
14854       switch (modrm.mod)
14855         {
14856         case 0:
14857           if (base == 5)
14858             {
14859               havebase = 0;
14860               if (address_mode == mode_64bit && !havesib)
14861                 riprel = 1;
14862               disp = get32s ();
14863             }
14864           break;
14865         case 1:
14866           FETCH_DATA (the_info, codep + 1);
14867           disp = *codep++;
14868           if ((disp & 0x80) != 0)
14869             disp -= 0x100;
14870           if (vex.evex && shift > 0)
14871             disp <<= shift;
14872           break;
14873         case 2:
14874           disp = get32s ();
14875           break;
14876         }
14877
14878       /* In 32bit mode, we need index register to tell [offset] from
14879          [eiz*1 + offset].  */
14880       needindex = (havesib
14881                    && !havebase
14882                    && !haveindex
14883                    && address_mode == mode_32bit);
14884       havedisp = (havebase
14885                   || needindex
14886                   || (havesib && (haveindex || scale != 0)));
14887
14888       if (!intel_syntax)
14889         if (modrm.mod != 0 || base == 5)
14890           {
14891             if (havedisp || riprel)
14892               print_displacement (scratchbuf, disp);
14893             else
14894               print_operand_value (scratchbuf, 1, disp);
14895             oappend (scratchbuf);
14896             if (riprel)
14897               {
14898                 set_op (disp, 1);
14899                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14900               }
14901           }
14902
14903       if ((havebase || haveindex || riprel)
14904           && (bytemode != v_bnd_mode)
14905           && (bytemode != bnd_mode))
14906         used_prefixes |= PREFIX_ADDR;
14907
14908       if (havedisp || (intel_syntax && riprel))
14909         {
14910           *obufp++ = open_char;
14911           if (intel_syntax && riprel)
14912             {
14913               set_op (disp, 1);
14914               oappend (sizeflag & AFLAG ? "rip" : "eip");
14915             }
14916           *obufp = '\0';
14917           if (havebase)
14918             oappend (address_mode == mode_64bit && !addr32flag
14919                      ? names64[rbase] : names32[rbase]);
14920           if (havesib)
14921             {
14922               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14923                  print index to tell base + index from base.  */
14924               if (scale != 0
14925                   || needindex
14926                   || haveindex
14927                   || (havebase && base != ESP_REG_NUM))
14928                 {
14929                   if (!intel_syntax || havebase)
14930                     {
14931                       *obufp++ = separator_char;
14932                       *obufp = '\0';
14933                     }
14934                   if (haveindex)
14935                     oappend (address_mode == mode_64bit && !addr32flag
14936                              ? indexes64[vindex] : indexes32[vindex]);
14937                   else
14938                     oappend (address_mode == mode_64bit && !addr32flag
14939                              ? index64 : index32);
14940
14941                   *obufp++ = scale_char;
14942                   *obufp = '\0';
14943                   sprintf (scratchbuf, "%d", 1 << scale);
14944                   oappend (scratchbuf);
14945                 }
14946             }
14947           if (intel_syntax
14948               && (disp || modrm.mod != 0 || base == 5))
14949             {
14950               if (!havedisp || (bfd_signed_vma) disp >= 0)
14951                 {
14952                   *obufp++ = '+';
14953                   *obufp = '\0';
14954                 }
14955               else if (modrm.mod != 1 && disp != -disp)
14956                 {
14957                   *obufp++ = '-';
14958                   *obufp = '\0';
14959                   disp = - (bfd_signed_vma) disp;
14960                 }
14961
14962               if (havedisp)
14963                 print_displacement (scratchbuf, disp);
14964               else
14965                 print_operand_value (scratchbuf, 1, disp);
14966               oappend (scratchbuf);
14967             }
14968
14969           *obufp++ = close_char;
14970           *obufp = '\0';
14971         }
14972       else if (intel_syntax)
14973         {
14974           if (modrm.mod != 0 || base == 5)
14975             {
14976               if (!active_seg_prefix)
14977                 {
14978                   oappend (names_seg[ds_reg - es_reg]);
14979                   oappend (":");
14980                 }
14981               print_operand_value (scratchbuf, 1, disp);
14982               oappend (scratchbuf);
14983             }
14984         }
14985     }
14986   else
14987     {
14988       /* 16 bit address mode */
14989       used_prefixes |= prefixes & PREFIX_ADDR;
14990       switch (modrm.mod)
14991         {
14992         case 0:
14993           if (modrm.rm == 6)
14994             {
14995               disp = get16 ();
14996               if ((disp & 0x8000) != 0)
14997                 disp -= 0x10000;
14998             }
14999           break;
15000         case 1:
15001           FETCH_DATA (the_info, codep + 1);
15002           disp = *codep++;
15003           if ((disp & 0x80) != 0)
15004             disp -= 0x100;
15005           break;
15006         case 2:
15007           disp = get16 ();
15008           if ((disp & 0x8000) != 0)
15009             disp -= 0x10000;
15010           break;
15011         }
15012
15013       if (!intel_syntax)
15014         if (modrm.mod != 0 || modrm.rm == 6)
15015           {
15016             print_displacement (scratchbuf, disp);
15017             oappend (scratchbuf);
15018           }
15019
15020       if (modrm.mod != 0 || modrm.rm != 6)
15021         {
15022           *obufp++ = open_char;
15023           *obufp = '\0';
15024           oappend (index16[modrm.rm]);
15025           if (intel_syntax
15026               && (disp || modrm.mod != 0 || modrm.rm == 6))
15027             {
15028               if ((bfd_signed_vma) disp >= 0)
15029                 {
15030                   *obufp++ = '+';
15031                   *obufp = '\0';
15032                 }
15033               else if (modrm.mod != 1)
15034                 {
15035                   *obufp++ = '-';
15036                   *obufp = '\0';
15037                   disp = - (bfd_signed_vma) disp;
15038                 }
15039
15040               print_displacement (scratchbuf, disp);
15041               oappend (scratchbuf);
15042             }
15043
15044           *obufp++ = close_char;
15045           *obufp = '\0';
15046         }
15047       else if (intel_syntax)
15048         {
15049           if (!active_seg_prefix)
15050             {
15051               oappend (names_seg[ds_reg - es_reg]);
15052               oappend (":");
15053             }
15054           print_operand_value (scratchbuf, 1, disp & 0xffff);
15055           oappend (scratchbuf);
15056         }
15057     }
15058   if (vex.evex && vex.b
15059       && (bytemode == x_mode
15060           || bytemode == evex_half_bcst_xmmq_mode))
15061     {
15062       if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
15063         {
15064           switch (vex.length)
15065             {
15066             case 128:
15067               oappend ("{1to2}");
15068               break;
15069             case 256:
15070               oappend ("{1to4}");
15071               break;
15072             case 512:
15073               oappend ("{1to8}");
15074               break;
15075             default:
15076               abort ();
15077             }
15078         }
15079       else
15080         {
15081           switch (vex.length)
15082             {
15083             case 128:
15084               oappend ("{1to4}");
15085               break;
15086             case 256:
15087               oappend ("{1to8}");
15088               break;
15089             case 512:
15090               oappend ("{1to16}");
15091               break;
15092             default:
15093               abort ();
15094             }
15095         }
15096     }
15097 }
15098
15099 static void
15100 OP_E (int bytemode, int sizeflag)
15101 {
15102   /* Skip mod/rm byte.  */
15103   MODRM_CHECK;
15104   codep++;
15105
15106   if (modrm.mod == 3)
15107     OP_E_register (bytemode, sizeflag);
15108   else
15109     OP_E_memory (bytemode, sizeflag);
15110 }
15111
15112 static void
15113 OP_G (int bytemode, int sizeflag)
15114 {
15115   int add = 0;
15116   USED_REX (REX_R);
15117   if (rex & REX_R)
15118     add += 8;
15119   switch (bytemode)
15120     {
15121     case b_mode:
15122       USED_REX (0);
15123       if (rex)
15124         oappend (names8rex[modrm.reg + add]);
15125       else
15126         oappend (names8[modrm.reg + add]);
15127       break;
15128     case w_mode:
15129       oappend (names16[modrm.reg + add]);
15130       break;
15131     case d_mode:
15132     case db_mode:
15133     case dw_mode:
15134       oappend (names32[modrm.reg + add]);
15135       break;
15136     case q_mode:
15137       oappend (names64[modrm.reg + add]);
15138       break;
15139     case bnd_mode:
15140       oappend (names_bnd[modrm.reg]);
15141       break;
15142     case v_mode:
15143     case dq_mode:
15144     case dqb_mode:
15145     case dqd_mode:
15146     case dqw_mode:
15147     case dqw_swap_mode:
15148       USED_REX (REX_W);
15149       if (rex & REX_W)
15150         oappend (names64[modrm.reg + add]);
15151       else
15152         {
15153           if ((sizeflag & DFLAG) || bytemode != v_mode)
15154             oappend (names32[modrm.reg + add]);
15155           else
15156             oappend (names16[modrm.reg + add]);
15157           used_prefixes |= (prefixes & PREFIX_DATA);
15158         }
15159       break;
15160     case m_mode:
15161       if (address_mode == mode_64bit)
15162         oappend (names64[modrm.reg + add]);
15163       else
15164         oappend (names32[modrm.reg + add]);
15165       break;
15166     case mask_bd_mode:
15167     case mask_mode:
15168       oappend (names_mask[modrm.reg + add]);
15169       break;
15170     default:
15171       oappend (INTERNAL_DISASSEMBLER_ERROR);
15172       break;
15173     }
15174 }
15175
15176 static bfd_vma
15177 get64 (void)
15178 {
15179   bfd_vma x;
15180 #ifdef BFD64
15181   unsigned int a;
15182   unsigned int b;
15183
15184   FETCH_DATA (the_info, codep + 8);
15185   a = *codep++ & 0xff;
15186   a |= (*codep++ & 0xff) << 8;
15187   a |= (*codep++ & 0xff) << 16;
15188   a |= (*codep++ & 0xff) << 24;
15189   b = *codep++ & 0xff;
15190   b |= (*codep++ & 0xff) << 8;
15191   b |= (*codep++ & 0xff) << 16;
15192   b |= (*codep++ & 0xff) << 24;
15193   x = a + ((bfd_vma) b << 32);
15194 #else
15195   abort ();
15196   x = 0;
15197 #endif
15198   return x;
15199 }
15200
15201 static bfd_signed_vma
15202 get32 (void)
15203 {
15204   bfd_signed_vma x = 0;
15205
15206   FETCH_DATA (the_info, codep + 4);
15207   x = *codep++ & (bfd_signed_vma) 0xff;
15208   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15209   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15210   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15211   return x;
15212 }
15213
15214 static bfd_signed_vma
15215 get32s (void)
15216 {
15217   bfd_signed_vma x = 0;
15218
15219   FETCH_DATA (the_info, codep + 4);
15220   x = *codep++ & (bfd_signed_vma) 0xff;
15221   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15222   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15223   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15224
15225   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15226
15227   return x;
15228 }
15229
15230 static int
15231 get16 (void)
15232 {
15233   int x = 0;
15234
15235   FETCH_DATA (the_info, codep + 2);
15236   x = *codep++ & 0xff;
15237   x |= (*codep++ & 0xff) << 8;
15238   return x;
15239 }
15240
15241 static void
15242 set_op (bfd_vma op, int riprel)
15243 {
15244   op_index[op_ad] = op_ad;
15245   if (address_mode == mode_64bit)
15246     {
15247       op_address[op_ad] = op;
15248       op_riprel[op_ad] = riprel;
15249     }
15250   else
15251     {
15252       /* Mask to get a 32-bit address.  */
15253       op_address[op_ad] = op & 0xffffffff;
15254       op_riprel[op_ad] = riprel & 0xffffffff;
15255     }
15256 }
15257
15258 static void
15259 OP_REG (int code, int sizeflag)
15260 {
15261   const char *s;
15262   int add;
15263
15264   switch (code)
15265     {
15266     case es_reg: case ss_reg: case cs_reg:
15267     case ds_reg: case fs_reg: case gs_reg:
15268       oappend (names_seg[code - es_reg]);
15269       return;
15270     }
15271
15272   USED_REX (REX_B);
15273   if (rex & REX_B)
15274     add = 8;
15275   else
15276     add = 0;
15277
15278   switch (code)
15279     {
15280     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15281     case sp_reg: case bp_reg: case si_reg: case di_reg:
15282       s = names16[code - ax_reg + add];
15283       break;
15284     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15285     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15286       USED_REX (0);
15287       if (rex)
15288         s = names8rex[code - al_reg + add];
15289       else
15290         s = names8[code - al_reg];
15291       break;
15292     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15293     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15294       if (address_mode == mode_64bit
15295           && ((sizeflag & DFLAG) || (rex & REX_W)))
15296         {
15297           s = names64[code - rAX_reg + add];
15298           break;
15299         }
15300       code += eAX_reg - rAX_reg;
15301       /* Fall through.  */
15302     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15303     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15304       USED_REX (REX_W);
15305       if (rex & REX_W)
15306         s = names64[code - eAX_reg + add];
15307       else
15308         {
15309           if (sizeflag & DFLAG)
15310             s = names32[code - eAX_reg + add];
15311           else
15312             s = names16[code - eAX_reg + add];
15313           used_prefixes |= (prefixes & PREFIX_DATA);
15314         }
15315       break;
15316     default:
15317       s = INTERNAL_DISASSEMBLER_ERROR;
15318       break;
15319     }
15320   oappend (s);
15321 }
15322
15323 static void
15324 OP_IMREG (int code, int sizeflag)
15325 {
15326   const char *s;
15327
15328   switch (code)
15329     {
15330     case indir_dx_reg:
15331       if (intel_syntax)
15332         s = "dx";
15333       else
15334         s = "(%dx)";
15335       break;
15336     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15337     case sp_reg: case bp_reg: case si_reg: case di_reg:
15338       s = names16[code - ax_reg];
15339       break;
15340     case es_reg: case ss_reg: case cs_reg:
15341     case ds_reg: case fs_reg: case gs_reg:
15342       s = names_seg[code - es_reg];
15343       break;
15344     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15345     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15346       USED_REX (0);
15347       if (rex)
15348         s = names8rex[code - al_reg];
15349       else
15350         s = names8[code - al_reg];
15351       break;
15352     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15353     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15354       USED_REX (REX_W);
15355       if (rex & REX_W)
15356         s = names64[code - eAX_reg];
15357       else
15358         {
15359           if (sizeflag & DFLAG)
15360             s = names32[code - eAX_reg];
15361           else
15362             s = names16[code - eAX_reg];
15363           used_prefixes |= (prefixes & PREFIX_DATA);
15364         }
15365       break;
15366     case z_mode_ax_reg:
15367       if ((rex & REX_W) || (sizeflag & DFLAG))
15368         s = *names32;
15369       else
15370         s = *names16;
15371       if (!(rex & REX_W))
15372         used_prefixes |= (prefixes & PREFIX_DATA);
15373       break;
15374     default:
15375       s = INTERNAL_DISASSEMBLER_ERROR;
15376       break;
15377     }
15378   oappend (s);
15379 }
15380
15381 static void
15382 OP_I (int bytemode, int sizeflag)
15383 {
15384   bfd_signed_vma op;
15385   bfd_signed_vma mask = -1;
15386
15387   switch (bytemode)
15388     {
15389     case b_mode:
15390       FETCH_DATA (the_info, codep + 1);
15391       op = *codep++;
15392       mask = 0xff;
15393       break;
15394     case q_mode:
15395       if (address_mode == mode_64bit)
15396         {
15397           op = get32s ();
15398           break;
15399         }
15400       /* Fall through.  */
15401     case v_mode:
15402       USED_REX (REX_W);
15403       if (rex & REX_W)
15404         op = get32s ();
15405       else
15406         {
15407           if (sizeflag & DFLAG)
15408             {
15409               op = get32 ();
15410               mask = 0xffffffff;
15411             }
15412           else
15413             {
15414               op = get16 ();
15415               mask = 0xfffff;
15416             }
15417           used_prefixes |= (prefixes & PREFIX_DATA);
15418         }
15419       break;
15420     case w_mode:
15421       mask = 0xfffff;
15422       op = get16 ();
15423       break;
15424     case const_1_mode:
15425       if (intel_syntax)
15426         oappend ("1");
15427       return;
15428     default:
15429       oappend (INTERNAL_DISASSEMBLER_ERROR);
15430       return;
15431     }
15432
15433   op &= mask;
15434   scratchbuf[0] = '$';
15435   print_operand_value (scratchbuf + 1, 1, op);
15436   oappend_maybe_intel (scratchbuf);
15437   scratchbuf[0] = '\0';
15438 }
15439
15440 static void
15441 OP_I64 (int bytemode, int sizeflag)
15442 {
15443   bfd_signed_vma op;
15444   bfd_signed_vma mask = -1;
15445
15446   if (address_mode != mode_64bit)
15447     {
15448       OP_I (bytemode, sizeflag);
15449       return;
15450     }
15451
15452   switch (bytemode)
15453     {
15454     case b_mode:
15455       FETCH_DATA (the_info, codep + 1);
15456       op = *codep++;
15457       mask = 0xff;
15458       break;
15459     case v_mode:
15460       USED_REX (REX_W);
15461       if (rex & REX_W)
15462         op = get64 ();
15463       else
15464         {
15465           if (sizeflag & DFLAG)
15466             {
15467               op = get32 ();
15468               mask = 0xffffffff;
15469             }
15470           else
15471             {
15472               op = get16 ();
15473               mask = 0xfffff;
15474             }
15475           used_prefixes |= (prefixes & PREFIX_DATA);
15476         }
15477       break;
15478     case w_mode:
15479       mask = 0xfffff;
15480       op = get16 ();
15481       break;
15482     default:
15483       oappend (INTERNAL_DISASSEMBLER_ERROR);
15484       return;
15485     }
15486
15487   op &= mask;
15488   scratchbuf[0] = '$';
15489   print_operand_value (scratchbuf + 1, 1, op);
15490   oappend_maybe_intel (scratchbuf);
15491   scratchbuf[0] = '\0';
15492 }
15493
15494 static void
15495 OP_sI (int bytemode, int sizeflag)
15496 {
15497   bfd_signed_vma op;
15498
15499   switch (bytemode)
15500     {
15501     case b_mode:
15502     case b_T_mode:
15503       FETCH_DATA (the_info, codep + 1);
15504       op = *codep++;
15505       if ((op & 0x80) != 0)
15506         op -= 0x100;
15507       if (bytemode == b_T_mode)
15508         {
15509           if (address_mode != mode_64bit
15510               || !((sizeflag & DFLAG) || (rex & REX_W)))
15511             {
15512               /* The operand-size prefix is overridden by a REX prefix.  */
15513               if ((sizeflag & DFLAG) || (rex & REX_W))
15514                 op &= 0xffffffff;
15515               else
15516                 op &= 0xffff;
15517           }
15518         }
15519       else
15520         {
15521           if (!(rex & REX_W))
15522             {
15523               if (sizeflag & DFLAG)
15524                 op &= 0xffffffff;
15525               else
15526                 op &= 0xffff;
15527             }
15528         }
15529       break;
15530     case v_mode:
15531       /* The operand-size prefix is overridden by a REX prefix.  */
15532       if ((sizeflag & DFLAG) || (rex & REX_W))
15533         op = get32s ();
15534       else
15535         op = get16 ();
15536       break;
15537     default:
15538       oappend (INTERNAL_DISASSEMBLER_ERROR);
15539       return;
15540     }
15541
15542   scratchbuf[0] = '$';
15543   print_operand_value (scratchbuf + 1, 1, op);
15544   oappend_maybe_intel (scratchbuf);
15545 }
15546
15547 static void
15548 OP_J (int bytemode, int sizeflag)
15549 {
15550   bfd_vma disp;
15551   bfd_vma mask = -1;
15552   bfd_vma segment = 0;
15553
15554   switch (bytemode)
15555     {
15556     case b_mode:
15557       FETCH_DATA (the_info, codep + 1);
15558       disp = *codep++;
15559       if ((disp & 0x80) != 0)
15560         disp -= 0x100;
15561       break;
15562     case v_mode:
15563       USED_REX (REX_W);
15564       if ((sizeflag & DFLAG) || (rex & REX_W))
15565         disp = get32s ();
15566       else
15567         {
15568           disp = get16 ();
15569           if ((disp & 0x8000) != 0)
15570             disp -= 0x10000;
15571           /* In 16bit mode, address is wrapped around at 64k within
15572              the same segment.  Otherwise, a data16 prefix on a jump
15573              instruction means that the pc is masked to 16 bits after
15574              the displacement is added!  */
15575           mask = 0xffff;
15576           if ((prefixes & PREFIX_DATA) == 0)
15577             segment = ((start_pc + codep - start_codep)
15578                        & ~((bfd_vma) 0xffff));
15579         }
15580       if (!(rex & REX_W))
15581         used_prefixes |= (prefixes & PREFIX_DATA);
15582       break;
15583     default:
15584       oappend (INTERNAL_DISASSEMBLER_ERROR);
15585       return;
15586     }
15587   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15588   set_op (disp, 0);
15589   print_operand_value (scratchbuf, 1, disp);
15590   oappend (scratchbuf);
15591 }
15592
15593 static void
15594 OP_SEG (int bytemode, int sizeflag)
15595 {
15596   if (bytemode == w_mode)
15597     oappend (names_seg[modrm.reg]);
15598   else
15599     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15600 }
15601
15602 static void
15603 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15604 {
15605   int seg, offset;
15606
15607   if (sizeflag & DFLAG)
15608     {
15609       offset = get32 ();
15610       seg = get16 ();
15611     }
15612   else
15613     {
15614       offset = get16 ();
15615       seg = get16 ();
15616     }
15617   used_prefixes |= (prefixes & PREFIX_DATA);
15618   if (intel_syntax)
15619     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15620   else
15621     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15622   oappend (scratchbuf);
15623 }
15624
15625 static void
15626 OP_OFF (int bytemode, int sizeflag)
15627 {
15628   bfd_vma off;
15629
15630   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15631     intel_operand_size (bytemode, sizeflag);
15632   append_seg ();
15633
15634   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15635     off = get32 ();
15636   else
15637     off = get16 ();
15638
15639   if (intel_syntax)
15640     {
15641       if (!active_seg_prefix)
15642         {
15643           oappend (names_seg[ds_reg - es_reg]);
15644           oappend (":");
15645         }
15646     }
15647   print_operand_value (scratchbuf, 1, off);
15648   oappend (scratchbuf);
15649 }
15650
15651 static void
15652 OP_OFF64 (int bytemode, int sizeflag)
15653 {
15654   bfd_vma off;
15655
15656   if (address_mode != mode_64bit
15657       || (prefixes & PREFIX_ADDR))
15658     {
15659       OP_OFF (bytemode, sizeflag);
15660       return;
15661     }
15662
15663   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15664     intel_operand_size (bytemode, sizeflag);
15665   append_seg ();
15666
15667   off = get64 ();
15668
15669   if (intel_syntax)
15670     {
15671       if (!active_seg_prefix)
15672         {
15673           oappend (names_seg[ds_reg - es_reg]);
15674           oappend (":");
15675         }
15676     }
15677   print_operand_value (scratchbuf, 1, off);
15678   oappend (scratchbuf);
15679 }
15680
15681 static void
15682 ptr_reg (int code, int sizeflag)
15683 {
15684   const char *s;
15685
15686   *obufp++ = open_char;
15687   used_prefixes |= (prefixes & PREFIX_ADDR);
15688   if (address_mode == mode_64bit)
15689     {
15690       if (!(sizeflag & AFLAG))
15691         s = names32[code - eAX_reg];
15692       else
15693         s = names64[code - eAX_reg];
15694     }
15695   else if (sizeflag & AFLAG)
15696     s = names32[code - eAX_reg];
15697   else
15698     s = names16[code - eAX_reg];
15699   oappend (s);
15700   *obufp++ = close_char;
15701   *obufp = 0;
15702 }
15703
15704 static void
15705 OP_ESreg (int code, int sizeflag)
15706 {
15707   if (intel_syntax)
15708     {
15709       switch (codep[-1])
15710         {
15711         case 0x6d:      /* insw/insl */
15712           intel_operand_size (z_mode, sizeflag);
15713           break;
15714         case 0xa5:      /* movsw/movsl/movsq */
15715         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15716         case 0xab:      /* stosw/stosl */
15717         case 0xaf:      /* scasw/scasl */
15718           intel_operand_size (v_mode, sizeflag);
15719           break;
15720         default:
15721           intel_operand_size (b_mode, sizeflag);
15722         }
15723     }
15724   oappend_maybe_intel ("%es:");
15725   ptr_reg (code, sizeflag);
15726 }
15727
15728 static void
15729 OP_DSreg (int code, int sizeflag)
15730 {
15731   if (intel_syntax)
15732     {
15733       switch (codep[-1])
15734         {
15735         case 0x6f:      /* outsw/outsl */
15736           intel_operand_size (z_mode, sizeflag);
15737           break;
15738         case 0xa5:      /* movsw/movsl/movsq */
15739         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15740         case 0xad:      /* lodsw/lodsl/lodsq */
15741           intel_operand_size (v_mode, sizeflag);
15742           break;
15743         default:
15744           intel_operand_size (b_mode, sizeflag);
15745         }
15746     }
15747   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15748      default segment register DS is printed.  */
15749   if (!active_seg_prefix)
15750     active_seg_prefix = PREFIX_DS;
15751   append_seg ();
15752   ptr_reg (code, sizeflag);
15753 }
15754
15755 static void
15756 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15757 {
15758   int add;
15759   if (rex & REX_R)
15760     {
15761       USED_REX (REX_R);
15762       add = 8;
15763     }
15764   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15765     {
15766       all_prefixes[last_lock_prefix] = 0;
15767       used_prefixes |= PREFIX_LOCK;
15768       add = 8;
15769     }
15770   else
15771     add = 0;
15772   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15773   oappend_maybe_intel (scratchbuf);
15774 }
15775
15776 static void
15777 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15778 {
15779   int add;
15780   USED_REX (REX_R);
15781   if (rex & REX_R)
15782     add = 8;
15783   else
15784     add = 0;
15785   if (intel_syntax)
15786     sprintf (scratchbuf, "db%d", modrm.reg + add);
15787   else
15788     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15789   oappend (scratchbuf);
15790 }
15791
15792 static void
15793 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15794 {
15795   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15796   oappend_maybe_intel (scratchbuf);
15797 }
15798
15799 static void
15800 OP_R (int bytemode, int sizeflag)
15801 {
15802   if (modrm.mod == 3)
15803     OP_E (bytemode, sizeflag);
15804   else
15805     BadOp ();
15806 }
15807
15808 static void
15809 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15810 {
15811   int reg = modrm.reg;
15812   const char **names;
15813
15814   used_prefixes |= (prefixes & PREFIX_DATA);
15815   if (prefixes & PREFIX_DATA)
15816     {
15817       names = names_xmm;
15818       USED_REX (REX_R);
15819       if (rex & REX_R)
15820         reg += 8;
15821     }
15822   else
15823     names = names_mm;
15824   oappend (names[reg]);
15825 }
15826
15827 static void
15828 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15829 {
15830   int reg = modrm.reg;
15831   const char **names;
15832
15833   USED_REX (REX_R);
15834   if (rex & REX_R)
15835     reg += 8;
15836   if (vex.evex)
15837     {
15838       if (!vex.r)
15839         reg += 16;
15840     }
15841
15842   if (need_vex
15843       && bytemode != xmm_mode
15844       && bytemode != xmmq_mode
15845       && bytemode != evex_half_bcst_xmmq_mode
15846       && bytemode != ymm_mode
15847       && bytemode != scalar_mode)
15848     {
15849       switch (vex.length)
15850         {
15851         case 128:
15852           names = names_xmm;
15853           break;
15854         case 256:
15855           if (vex.w
15856               || (bytemode != vex_vsib_q_w_dq_mode
15857                   && bytemode != vex_vsib_q_w_d_mode))
15858             names = names_ymm;
15859           else
15860             names = names_xmm;
15861           break;
15862         case 512:
15863           names = names_zmm;
15864           break;
15865         default:
15866           abort ();
15867         }
15868     }
15869   else if (bytemode == xmmq_mode
15870            || bytemode == evex_half_bcst_xmmq_mode)
15871     {
15872       switch (vex.length)
15873         {
15874         case 128:
15875         case 256:
15876           names = names_xmm;
15877           break;
15878         case 512:
15879           names = names_ymm;
15880           break;
15881         default:
15882           abort ();
15883         }
15884     }
15885   else if (bytemode == ymm_mode)
15886     names = names_ymm;
15887   else
15888     names = names_xmm;
15889   oappend (names[reg]);
15890 }
15891
15892 static void
15893 OP_EM (int bytemode, int sizeflag)
15894 {
15895   int reg;
15896   const char **names;
15897
15898   if (modrm.mod != 3)
15899     {
15900       if (intel_syntax
15901           && (bytemode == v_mode || bytemode == v_swap_mode))
15902         {
15903           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15904           used_prefixes |= (prefixes & PREFIX_DATA);
15905         }
15906       OP_E (bytemode, sizeflag);
15907       return;
15908     }
15909
15910   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15911     swap_operand ();
15912
15913   /* Skip mod/rm byte.  */
15914   MODRM_CHECK;
15915   codep++;
15916   used_prefixes |= (prefixes & PREFIX_DATA);
15917   reg = modrm.rm;
15918   if (prefixes & PREFIX_DATA)
15919     {
15920       names = names_xmm;
15921       USED_REX (REX_B);
15922       if (rex & REX_B)
15923         reg += 8;
15924     }
15925   else
15926     names = names_mm;
15927   oappend (names[reg]);
15928 }
15929
15930 /* cvt* are the only instructions in sse2 which have
15931    both SSE and MMX operands and also have 0x66 prefix
15932    in their opcode. 0x66 was originally used to differentiate
15933    between SSE and MMX instruction(operands). So we have to handle the
15934    cvt* separately using OP_EMC and OP_MXC */
15935 static void
15936 OP_EMC (int bytemode, int sizeflag)
15937 {
15938   if (modrm.mod != 3)
15939     {
15940       if (intel_syntax && bytemode == v_mode)
15941         {
15942           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15943           used_prefixes |= (prefixes & PREFIX_DATA);
15944         }
15945       OP_E (bytemode, sizeflag);
15946       return;
15947     }
15948
15949   /* Skip mod/rm byte.  */
15950   MODRM_CHECK;
15951   codep++;
15952   used_prefixes |= (prefixes & PREFIX_DATA);
15953   oappend (names_mm[modrm.rm]);
15954 }
15955
15956 static void
15957 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15958 {
15959   used_prefixes |= (prefixes & PREFIX_DATA);
15960   oappend (names_mm[modrm.reg]);
15961 }
15962
15963 static void
15964 OP_EX (int bytemode, int sizeflag)
15965 {
15966   int reg;
15967   const char **names;
15968
15969   /* Skip mod/rm byte.  */
15970   MODRM_CHECK;
15971   codep++;
15972
15973   if (modrm.mod != 3)
15974     {
15975       OP_E_memory (bytemode, sizeflag);
15976       return;
15977     }
15978
15979   reg = modrm.rm;
15980   USED_REX (REX_B);
15981   if (rex & REX_B)
15982     reg += 8;
15983   if (vex.evex)
15984     {
15985       USED_REX (REX_X);
15986       if ((rex & REX_X))
15987         reg += 16;
15988     }
15989
15990   if ((sizeflag & SUFFIX_ALWAYS)
15991       && (bytemode == x_swap_mode
15992           || bytemode == d_swap_mode
15993           || bytemode == dqw_swap_mode
15994           || bytemode == d_scalar_swap_mode
15995           || bytemode == q_swap_mode
15996           || bytemode == q_scalar_swap_mode))
15997     swap_operand ();
15998
15999   if (need_vex
16000       && bytemode != xmm_mode
16001       && bytemode != xmmdw_mode
16002       && bytemode != xmmqd_mode
16003       && bytemode != xmm_mb_mode
16004       && bytemode != xmm_mw_mode
16005       && bytemode != xmm_md_mode
16006       && bytemode != xmm_mq_mode
16007       && bytemode != xmm_mdq_mode
16008       && bytemode != xmmq_mode
16009       && bytemode != evex_half_bcst_xmmq_mode
16010       && bytemode != ymm_mode
16011       && bytemode != d_scalar_mode
16012       && bytemode != d_scalar_swap_mode
16013       && bytemode != q_scalar_mode
16014       && bytemode != q_scalar_swap_mode
16015       && bytemode != vex_scalar_w_dq_mode)
16016     {
16017       switch (vex.length)
16018         {
16019         case 128:
16020           names = names_xmm;
16021           break;
16022         case 256:
16023           names = names_ymm;
16024           break;
16025         case 512:
16026           names = names_zmm;
16027           break;
16028         default:
16029           abort ();
16030         }
16031     }
16032   else if (bytemode == xmmq_mode
16033            || bytemode == evex_half_bcst_xmmq_mode)
16034     {
16035       switch (vex.length)
16036         {
16037         case 128:
16038         case 256:
16039           names = names_xmm;
16040           break;
16041         case 512:
16042           names = names_ymm;
16043           break;
16044         default:
16045           abort ();
16046         }
16047     }
16048   else if (bytemode == ymm_mode)
16049     names = names_ymm;
16050   else
16051     names = names_xmm;
16052   oappend (names[reg]);
16053 }
16054
16055 static void
16056 OP_MS (int bytemode, int sizeflag)
16057 {
16058   if (modrm.mod == 3)
16059     OP_EM (bytemode, sizeflag);
16060   else
16061     BadOp ();
16062 }
16063
16064 static void
16065 OP_XS (int bytemode, int sizeflag)
16066 {
16067   if (modrm.mod == 3)
16068     OP_EX (bytemode, sizeflag);
16069   else
16070     BadOp ();
16071 }
16072
16073 static void
16074 OP_M (int bytemode, int sizeflag)
16075 {
16076   if (modrm.mod == 3)
16077     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16078     BadOp ();
16079   else
16080     OP_E (bytemode, sizeflag);
16081 }
16082
16083 static void
16084 OP_0f07 (int bytemode, int sizeflag)
16085 {
16086   if (modrm.mod != 3 || modrm.rm != 0)
16087     BadOp ();
16088   else
16089     OP_E (bytemode, sizeflag);
16090 }
16091
16092 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16093    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16094
16095 static void
16096 NOP_Fixup1 (int bytemode, int sizeflag)
16097 {
16098   if ((prefixes & PREFIX_DATA) != 0
16099       || (rex != 0
16100           && rex != 0x48
16101           && address_mode == mode_64bit))
16102     OP_REG (bytemode, sizeflag);
16103   else
16104     strcpy (obuf, "nop");
16105 }
16106
16107 static void
16108 NOP_Fixup2 (int bytemode, int sizeflag)
16109 {
16110   if ((prefixes & PREFIX_DATA) != 0
16111       || (rex != 0
16112           && rex != 0x48
16113           && address_mode == mode_64bit))
16114     OP_IMREG (bytemode, sizeflag);
16115 }
16116
16117 static const char *const Suffix3DNow[] = {
16118 /* 00 */        NULL,           NULL,           NULL,           NULL,
16119 /* 04 */        NULL,           NULL,           NULL,           NULL,
16120 /* 08 */        NULL,           NULL,           NULL,           NULL,
16121 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16122 /* 10 */        NULL,           NULL,           NULL,           NULL,
16123 /* 14 */        NULL,           NULL,           NULL,           NULL,
16124 /* 18 */        NULL,           NULL,           NULL,           NULL,
16125 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16126 /* 20 */        NULL,           NULL,           NULL,           NULL,
16127 /* 24 */        NULL,           NULL,           NULL,           NULL,
16128 /* 28 */        NULL,           NULL,           NULL,           NULL,
16129 /* 2C */        NULL,           NULL,           NULL,           NULL,
16130 /* 30 */        NULL,           NULL,           NULL,           NULL,
16131 /* 34 */        NULL,           NULL,           NULL,           NULL,
16132 /* 38 */        NULL,           NULL,           NULL,           NULL,
16133 /* 3C */        NULL,           NULL,           NULL,           NULL,
16134 /* 40 */        NULL,           NULL,           NULL,           NULL,
16135 /* 44 */        NULL,           NULL,           NULL,           NULL,
16136 /* 48 */        NULL,           NULL,           NULL,           NULL,
16137 /* 4C */        NULL,           NULL,           NULL,           NULL,
16138 /* 50 */        NULL,           NULL,           NULL,           NULL,
16139 /* 54 */        NULL,           NULL,           NULL,           NULL,
16140 /* 58 */        NULL,           NULL,           NULL,           NULL,
16141 /* 5C */        NULL,           NULL,           NULL,           NULL,
16142 /* 60 */        NULL,           NULL,           NULL,           NULL,
16143 /* 64 */        NULL,           NULL,           NULL,           NULL,
16144 /* 68 */        NULL,           NULL,           NULL,           NULL,
16145 /* 6C */        NULL,           NULL,           NULL,           NULL,
16146 /* 70 */        NULL,           NULL,           NULL,           NULL,
16147 /* 74 */        NULL,           NULL,           NULL,           NULL,
16148 /* 78 */        NULL,           NULL,           NULL,           NULL,
16149 /* 7C */        NULL,           NULL,           NULL,           NULL,
16150 /* 80 */        NULL,           NULL,           NULL,           NULL,
16151 /* 84 */        NULL,           NULL,           NULL,           NULL,
16152 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16153 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16154 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16155 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16156 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16157 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16158 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16159 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16160 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16161 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16162 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16163 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16164 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16165 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16166 /* C0 */        NULL,           NULL,           NULL,           NULL,
16167 /* C4 */        NULL,           NULL,           NULL,           NULL,
16168 /* C8 */        NULL,           NULL,           NULL,           NULL,
16169 /* CC */        NULL,           NULL,           NULL,           NULL,
16170 /* D0 */        NULL,           NULL,           NULL,           NULL,
16171 /* D4 */        NULL,           NULL,           NULL,           NULL,
16172 /* D8 */        NULL,           NULL,           NULL,           NULL,
16173 /* DC */        NULL,           NULL,           NULL,           NULL,
16174 /* E0 */        NULL,           NULL,           NULL,           NULL,
16175 /* E4 */        NULL,           NULL,           NULL,           NULL,
16176 /* E8 */        NULL,           NULL,           NULL,           NULL,
16177 /* EC */        NULL,           NULL,           NULL,           NULL,
16178 /* F0 */        NULL,           NULL,           NULL,           NULL,
16179 /* F4 */        NULL,           NULL,           NULL,           NULL,
16180 /* F8 */        NULL,           NULL,           NULL,           NULL,
16181 /* FC */        NULL,           NULL,           NULL,           NULL,
16182 };
16183
16184 static void
16185 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16186 {
16187   const char *mnemonic;
16188
16189   FETCH_DATA (the_info, codep + 1);
16190   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16191      place where an 8-bit immediate would normally go.  ie. the last
16192      byte of the instruction.  */
16193   obufp = mnemonicendp;
16194   mnemonic = Suffix3DNow[*codep++ & 0xff];
16195   if (mnemonic)
16196     oappend (mnemonic);
16197   else
16198     {
16199       /* Since a variable sized modrm/sib chunk is between the start
16200          of the opcode (0x0f0f) and the opcode suffix, we need to do
16201          all the modrm processing first, and don't know until now that
16202          we have a bad opcode.  This necessitates some cleaning up.  */
16203       op_out[0][0] = '\0';
16204       op_out[1][0] = '\0';
16205       BadOp ();
16206     }
16207   mnemonicendp = obufp;
16208 }
16209
16210 static struct op simd_cmp_op[] =
16211 {
16212   { STRING_COMMA_LEN ("eq") },
16213   { STRING_COMMA_LEN ("lt") },
16214   { STRING_COMMA_LEN ("le") },
16215   { STRING_COMMA_LEN ("unord") },
16216   { STRING_COMMA_LEN ("neq") },
16217   { STRING_COMMA_LEN ("nlt") },
16218   { STRING_COMMA_LEN ("nle") },
16219   { STRING_COMMA_LEN ("ord") }
16220 };
16221
16222 static void
16223 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16224 {
16225   unsigned int cmp_type;
16226
16227   FETCH_DATA (the_info, codep + 1);
16228   cmp_type = *codep++ & 0xff;
16229   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16230     {
16231       char suffix [3];
16232       char *p = mnemonicendp - 2;
16233       suffix[0] = p[0];
16234       suffix[1] = p[1];
16235       suffix[2] = '\0';
16236       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16237       mnemonicendp += simd_cmp_op[cmp_type].len;
16238     }
16239   else
16240     {
16241       /* We have a reserved extension byte.  Output it directly.  */
16242       scratchbuf[0] = '$';
16243       print_operand_value (scratchbuf + 1, 1, cmp_type);
16244       oappend_maybe_intel (scratchbuf);
16245       scratchbuf[0] = '\0';
16246     }
16247 }
16248
16249 static void
16250 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16251           int sizeflag ATTRIBUTE_UNUSED)
16252 {
16253   /* mwait %eax,%ecx  */
16254   if (!intel_syntax)
16255     {
16256       const char **names = (address_mode == mode_64bit
16257                             ? names64 : names32);
16258       strcpy (op_out[0], names[0]);
16259       strcpy (op_out[1], names[1]);
16260       two_source_ops = 1;
16261     }
16262   /* Skip mod/rm byte.  */
16263   MODRM_CHECK;
16264   codep++;
16265 }
16266
16267 static void
16268 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16269             int sizeflag ATTRIBUTE_UNUSED)
16270 {
16271   /* monitor %eax,%ecx,%edx"  */
16272   if (!intel_syntax)
16273     {
16274       const char **op1_names;
16275       const char **names = (address_mode == mode_64bit
16276                             ? names64 : names32);
16277
16278       if (!(prefixes & PREFIX_ADDR))
16279         op1_names = (address_mode == mode_16bit
16280                      ? names16 : names);
16281       else
16282         {
16283           /* Remove "addr16/addr32".  */
16284           all_prefixes[last_addr_prefix] = 0;
16285           op1_names = (address_mode != mode_32bit
16286                        ? names32 : names16);
16287           used_prefixes |= PREFIX_ADDR;
16288         }
16289       strcpy (op_out[0], op1_names[0]);
16290       strcpy (op_out[1], names[1]);
16291       strcpy (op_out[2], names[2]);
16292       two_source_ops = 1;
16293     }
16294   /* Skip mod/rm byte.  */
16295   MODRM_CHECK;
16296   codep++;
16297 }
16298
16299 static void
16300 BadOp (void)
16301 {
16302   /* Throw away prefixes and 1st. opcode byte.  */
16303   codep = insn_codep + 1;
16304   oappend ("(bad)");
16305 }
16306
16307 static void
16308 REP_Fixup (int bytemode, int sizeflag)
16309 {
16310   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16311      lods and stos.  */
16312   if (prefixes & PREFIX_REPZ)
16313     all_prefixes[last_repz_prefix] = REP_PREFIX;
16314
16315   switch (bytemode)
16316     {
16317     case al_reg:
16318     case eAX_reg:
16319     case indir_dx_reg:
16320       OP_IMREG (bytemode, sizeflag);
16321       break;
16322     case eDI_reg:
16323       OP_ESreg (bytemode, sizeflag);
16324       break;
16325     case eSI_reg:
16326       OP_DSreg (bytemode, sizeflag);
16327       break;
16328     default:
16329       abort ();
16330       break;
16331     }
16332 }
16333
16334 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16335    "bnd".  */
16336
16337 static void
16338 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16339 {
16340   if (prefixes & PREFIX_REPNZ)
16341     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16342 }
16343
16344 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16345    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16346  */
16347
16348 static void
16349 HLE_Fixup1 (int bytemode, int sizeflag)
16350 {
16351   if (modrm.mod != 3
16352       && (prefixes & PREFIX_LOCK) != 0)
16353     {
16354       if (prefixes & PREFIX_REPZ)
16355         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16356       if (prefixes & PREFIX_REPNZ)
16357         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16358     }
16359
16360   OP_E (bytemode, sizeflag);
16361 }
16362
16363 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16364    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16365  */
16366
16367 static void
16368 HLE_Fixup2 (int bytemode, int sizeflag)
16369 {
16370   if (modrm.mod != 3)
16371     {
16372       if (prefixes & PREFIX_REPZ)
16373         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16374       if (prefixes & PREFIX_REPNZ)
16375         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16376     }
16377
16378   OP_E (bytemode, sizeflag);
16379 }
16380
16381 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16382    "xrelease" for memory operand.  No check for LOCK prefix.   */
16383
16384 static void
16385 HLE_Fixup3 (int bytemode, int sizeflag)
16386 {
16387   if (modrm.mod != 3
16388       && last_repz_prefix > last_repnz_prefix
16389       && (prefixes & PREFIX_REPZ) != 0)
16390     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16391
16392   OP_E (bytemode, sizeflag);
16393 }
16394
16395 static void
16396 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16397 {
16398   USED_REX (REX_W);
16399   if (rex & REX_W)
16400     {
16401       /* Change cmpxchg8b to cmpxchg16b.  */
16402       char *p = mnemonicendp - 2;
16403       mnemonicendp = stpcpy (p, "16b");
16404       bytemode = o_mode;
16405     }
16406   else if ((prefixes & PREFIX_LOCK) != 0)
16407     {
16408       if (prefixes & PREFIX_REPZ)
16409         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16410       if (prefixes & PREFIX_REPNZ)
16411         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16412     }
16413
16414   OP_M (bytemode, sizeflag);
16415 }
16416
16417 static void
16418 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16419 {
16420   const char **names;
16421
16422   if (need_vex)
16423     {
16424       switch (vex.length)
16425         {
16426         case 128:
16427           names = names_xmm;
16428           break;
16429         case 256:
16430           names = names_ymm;
16431           break;
16432         default:
16433           abort ();
16434         }
16435     }
16436   else
16437     names = names_xmm;
16438   oappend (names[reg]);
16439 }
16440
16441 static void
16442 CRC32_Fixup (int bytemode, int sizeflag)
16443 {
16444   /* Add proper suffix to "crc32".  */
16445   char *p = mnemonicendp;
16446
16447   switch (bytemode)
16448     {
16449     case b_mode:
16450       if (intel_syntax)
16451         goto skip;
16452
16453       *p++ = 'b';
16454       break;
16455     case v_mode:
16456       if (intel_syntax)
16457         goto skip;
16458
16459       USED_REX (REX_W);
16460       if (rex & REX_W)
16461         *p++ = 'q';
16462       else
16463         {
16464           if (sizeflag & DFLAG)
16465             *p++ = 'l';
16466           else
16467             *p++ = 'w';
16468           used_prefixes |= (prefixes & PREFIX_DATA);
16469         }
16470       break;
16471     default:
16472       oappend (INTERNAL_DISASSEMBLER_ERROR);
16473       break;
16474     }
16475   mnemonicendp = p;
16476   *p = '\0';
16477
16478 skip:
16479   if (modrm.mod == 3)
16480     {
16481       int add;
16482
16483       /* Skip mod/rm byte.  */
16484       MODRM_CHECK;
16485       codep++;
16486
16487       USED_REX (REX_B);
16488       add = (rex & REX_B) ? 8 : 0;
16489       if (bytemode == b_mode)
16490         {
16491           USED_REX (0);
16492           if (rex)
16493             oappend (names8rex[modrm.rm + add]);
16494           else
16495             oappend (names8[modrm.rm + add]);
16496         }
16497       else
16498         {
16499           USED_REX (REX_W);
16500           if (rex & REX_W)
16501             oappend (names64[modrm.rm + add]);
16502           else if ((prefixes & PREFIX_DATA))
16503             oappend (names16[modrm.rm + add]);
16504           else
16505             oappend (names32[modrm.rm + add]);
16506         }
16507     }
16508   else
16509     OP_E (bytemode, sizeflag);
16510 }
16511
16512 static void
16513 FXSAVE_Fixup (int bytemode, int sizeflag)
16514 {
16515   /* Add proper suffix to "fxsave" and "fxrstor".  */
16516   USED_REX (REX_W);
16517   if (rex & REX_W)
16518     {
16519       char *p = mnemonicendp;
16520       *p++ = '6';
16521       *p++ = '4';
16522       *p = '\0';
16523       mnemonicendp = p;
16524     }
16525   OP_M (bytemode, sizeflag);
16526 }
16527
16528 /* Display the destination register operand for instructions with
16529    VEX. */
16530
16531 static void
16532 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16533 {
16534   int reg;
16535   const char **names;
16536
16537   if (!need_vex)
16538     abort ();
16539
16540   if (!need_vex_reg)
16541     return;
16542
16543   reg = vex.register_specifier;
16544   if (vex.evex)
16545     {
16546       if (!vex.v)
16547         reg += 16;
16548     }
16549
16550   if (bytemode == vex_scalar_mode)
16551     {
16552       oappend (names_xmm[reg]);
16553       return;
16554     }
16555
16556   switch (vex.length)
16557     {
16558     case 128:
16559       switch (bytemode)
16560         {
16561         case vex_mode:
16562         case vex128_mode:
16563         case vex_vsib_q_w_dq_mode:
16564         case vex_vsib_q_w_d_mode:
16565           names = names_xmm;
16566           break;
16567         case dq_mode:
16568           if (vex.w)
16569             names = names64;
16570           else
16571             names = names32;
16572           break;
16573         case mask_bd_mode:
16574         case mask_mode:
16575           names = names_mask;
16576           break;
16577         default:
16578           abort ();
16579           return;
16580         }
16581       break;
16582     case 256:
16583       switch (bytemode)
16584         {
16585         case vex_mode:
16586         case vex256_mode:
16587           names = names_ymm;
16588           break;
16589         case vex_vsib_q_w_dq_mode:
16590         case vex_vsib_q_w_d_mode:
16591           names = vex.w ? names_ymm : names_xmm;
16592           break;
16593         case mask_bd_mode:
16594         case mask_mode:
16595           names = names_mask;
16596           break;
16597         default:
16598           abort ();
16599           return;
16600         }
16601       break;
16602     case 512:
16603       names = names_zmm;
16604       break;
16605     default:
16606       abort ();
16607       break;
16608     }
16609   oappend (names[reg]);
16610 }
16611
16612 /* Get the VEX immediate byte without moving codep.  */
16613
16614 static unsigned char
16615 get_vex_imm8 (int sizeflag, int opnum)
16616 {
16617   int bytes_before_imm = 0;
16618
16619   if (modrm.mod != 3)
16620     {
16621       /* There are SIB/displacement bytes.  */
16622       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16623         {
16624           /* 32/64 bit address mode */
16625           int base = modrm.rm;
16626
16627           /* Check SIB byte.  */
16628           if (base == 4)
16629             {
16630               FETCH_DATA (the_info, codep + 1);
16631               base = *codep & 7;
16632               /* When decoding the third source, don't increase
16633                  bytes_before_imm as this has already been incremented
16634                  by one in OP_E_memory while decoding the second
16635                  source operand.  */
16636               if (opnum == 0)
16637                 bytes_before_imm++;
16638             }
16639
16640           /* Don't increase bytes_before_imm when decoding the third source,
16641              it has already been incremented by OP_E_memory while decoding
16642              the second source operand.  */
16643           if (opnum == 0)
16644             {
16645               switch (modrm.mod)
16646                 {
16647                   case 0:
16648                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16649                        SIB == 5, there is a 4 byte displacement.  */
16650                     if (base != 5)
16651                       /* No displacement. */
16652                       break;
16653                   case 2:
16654                     /* 4 byte displacement.  */
16655                     bytes_before_imm += 4;
16656                     break;
16657                   case 1:
16658                     /* 1 byte displacement.  */
16659                     bytes_before_imm++;
16660                     break;
16661                 }
16662             }
16663         }
16664       else
16665         {
16666           /* 16 bit address mode */
16667           /* Don't increase bytes_before_imm when decoding the third source,
16668              it has already been incremented by OP_E_memory while decoding
16669              the second source operand.  */
16670           if (opnum == 0)
16671             {
16672               switch (modrm.mod)
16673                 {
16674                 case 0:
16675                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16676                   if (modrm.rm != 6)
16677                     /* No displacement. */
16678                     break;
16679                 case 2:
16680                   /* 2 byte displacement.  */
16681                   bytes_before_imm += 2;
16682                   break;
16683                 case 1:
16684                   /* 1 byte displacement: when decoding the third source,
16685                      don't increase bytes_before_imm as this has already
16686                      been incremented by one in OP_E_memory while decoding
16687                      the second source operand.  */
16688                   if (opnum == 0)
16689                     bytes_before_imm++;
16690
16691                   break;
16692                 }
16693             }
16694         }
16695     }
16696
16697   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16698   return codep [bytes_before_imm];
16699 }
16700
16701 static void
16702 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16703 {
16704   const char **names;
16705
16706   if (reg == -1 && modrm.mod != 3)
16707     {
16708       OP_E_memory (bytemode, sizeflag);
16709       return;
16710     }
16711   else
16712     {
16713       if (reg == -1)
16714         {
16715           reg = modrm.rm;
16716           USED_REX (REX_B);
16717           if (rex & REX_B)
16718             reg += 8;
16719         }
16720       else if (reg > 7 && address_mode != mode_64bit)
16721         BadOp ();
16722     }
16723
16724   switch (vex.length)
16725     {
16726     case 128:
16727       names = names_xmm;
16728       break;
16729     case 256:
16730       names = names_ymm;
16731       break;
16732     default:
16733       abort ();
16734     }
16735   oappend (names[reg]);
16736 }
16737
16738 static void
16739 OP_EX_VexImmW (int bytemode, int sizeflag)
16740 {
16741   int reg = -1;
16742   static unsigned char vex_imm8;
16743
16744   if (vex_w_done == 0)
16745     {
16746       vex_w_done = 1;
16747
16748       /* Skip mod/rm byte.  */
16749       MODRM_CHECK;
16750       codep++;
16751
16752       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16753
16754       if (vex.w)
16755           reg = vex_imm8 >> 4;
16756
16757       OP_EX_VexReg (bytemode, sizeflag, reg);
16758     }
16759   else if (vex_w_done == 1)
16760     {
16761       vex_w_done = 2;
16762
16763       if (!vex.w)
16764           reg = vex_imm8 >> 4;
16765
16766       OP_EX_VexReg (bytemode, sizeflag, reg);
16767     }
16768   else
16769     {
16770       /* Output the imm8 directly.  */
16771       scratchbuf[0] = '$';
16772       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16773       oappend_maybe_intel (scratchbuf);
16774       scratchbuf[0] = '\0';
16775       codep++;
16776     }
16777 }
16778
16779 static void
16780 OP_Vex_2src (int bytemode, int sizeflag)
16781 {
16782   if (modrm.mod == 3)
16783     {
16784       int reg = modrm.rm;
16785       USED_REX (REX_B);
16786       if (rex & REX_B)
16787         reg += 8;
16788       oappend (names_xmm[reg]);
16789     }
16790   else
16791     {
16792       if (intel_syntax
16793           && (bytemode == v_mode || bytemode == v_swap_mode))
16794         {
16795           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16796           used_prefixes |= (prefixes & PREFIX_DATA);
16797         }
16798       OP_E (bytemode, sizeflag);
16799     }
16800 }
16801
16802 static void
16803 OP_Vex_2src_1 (int bytemode, int sizeflag)
16804 {
16805   if (modrm.mod == 3)
16806     {
16807       /* Skip mod/rm byte.   */
16808       MODRM_CHECK;
16809       codep++;
16810     }
16811
16812   if (vex.w)
16813     oappend (names_xmm[vex.register_specifier]);
16814   else
16815     OP_Vex_2src (bytemode, sizeflag);
16816 }
16817
16818 static void
16819 OP_Vex_2src_2 (int bytemode, int sizeflag)
16820 {
16821   if (vex.w)
16822     OP_Vex_2src (bytemode, sizeflag);
16823   else
16824     oappend (names_xmm[vex.register_specifier]);
16825 }
16826
16827 static void
16828 OP_EX_VexW (int bytemode, int sizeflag)
16829 {
16830   int reg = -1;
16831
16832   if (!vex_w_done)
16833     {
16834       vex_w_done = 1;
16835
16836       /* Skip mod/rm byte.  */
16837       MODRM_CHECK;
16838       codep++;
16839
16840       if (vex.w)
16841         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16842     }
16843   else
16844     {
16845       if (!vex.w)
16846         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16847     }
16848
16849   OP_EX_VexReg (bytemode, sizeflag, reg);
16850 }
16851
16852 static void
16853 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16854              int sizeflag ATTRIBUTE_UNUSED)
16855 {
16856   /* Skip the immediate byte and check for invalid bits.  */
16857   FETCH_DATA (the_info, codep + 1);
16858   if (*codep++ & 0xf)
16859     BadOp ();
16860 }
16861
16862 static void
16863 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16864 {
16865   int reg;
16866   const char **names;
16867
16868   FETCH_DATA (the_info, codep + 1);
16869   reg = *codep++;
16870
16871   if (bytemode != x_mode)
16872     abort ();
16873
16874   if (reg & 0xf)
16875       BadOp ();
16876
16877   reg >>= 4;
16878   if (reg > 7 && address_mode != mode_64bit)
16879     BadOp ();
16880
16881   switch (vex.length)
16882     {
16883     case 128:
16884       names = names_xmm;
16885       break;
16886     case 256:
16887       names = names_ymm;
16888       break;
16889     default:
16890       abort ();
16891     }
16892   oappend (names[reg]);
16893 }
16894
16895 static void
16896 OP_XMM_VexW (int bytemode, int sizeflag)
16897 {
16898   /* Turn off the REX.W bit since it is used for swapping operands
16899      now.  */
16900   rex &= ~REX_W;
16901   OP_XMM (bytemode, sizeflag);
16902 }
16903
16904 static void
16905 OP_EX_Vex (int bytemode, int sizeflag)
16906 {
16907   if (modrm.mod != 3)
16908     {
16909       if (vex.register_specifier != 0)
16910         BadOp ();
16911       need_vex_reg = 0;
16912     }
16913   OP_EX (bytemode, sizeflag);
16914 }
16915
16916 static void
16917 OP_XMM_Vex (int bytemode, int sizeflag)
16918 {
16919   if (modrm.mod != 3)
16920     {
16921       if (vex.register_specifier != 0)
16922         BadOp ();
16923       need_vex_reg = 0;
16924     }
16925   OP_XMM (bytemode, sizeflag);
16926 }
16927
16928 static void
16929 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16930 {
16931   switch (vex.length)
16932     {
16933     case 128:
16934       mnemonicendp = stpcpy (obuf, "vzeroupper");
16935       break;
16936     case 256:
16937       mnemonicendp = stpcpy (obuf, "vzeroall");
16938       break;
16939     default:
16940       abort ();
16941     }
16942 }
16943
16944 static struct op vex_cmp_op[] =
16945 {
16946   { STRING_COMMA_LEN ("eq") },
16947   { STRING_COMMA_LEN ("lt") },
16948   { STRING_COMMA_LEN ("le") },
16949   { STRING_COMMA_LEN ("unord") },
16950   { STRING_COMMA_LEN ("neq") },
16951   { STRING_COMMA_LEN ("nlt") },
16952   { STRING_COMMA_LEN ("nle") },
16953   { STRING_COMMA_LEN ("ord") },
16954   { STRING_COMMA_LEN ("eq_uq") },
16955   { STRING_COMMA_LEN ("nge") },
16956   { STRING_COMMA_LEN ("ngt") },
16957   { STRING_COMMA_LEN ("false") },
16958   { STRING_COMMA_LEN ("neq_oq") },
16959   { STRING_COMMA_LEN ("ge") },
16960   { STRING_COMMA_LEN ("gt") },
16961   { STRING_COMMA_LEN ("true") },
16962   { STRING_COMMA_LEN ("eq_os") },
16963   { STRING_COMMA_LEN ("lt_oq") },
16964   { STRING_COMMA_LEN ("le_oq") },
16965   { STRING_COMMA_LEN ("unord_s") },
16966   { STRING_COMMA_LEN ("neq_us") },
16967   { STRING_COMMA_LEN ("nlt_uq") },
16968   { STRING_COMMA_LEN ("nle_uq") },
16969   { STRING_COMMA_LEN ("ord_s") },
16970   { STRING_COMMA_LEN ("eq_us") },
16971   { STRING_COMMA_LEN ("nge_uq") },
16972   { STRING_COMMA_LEN ("ngt_uq") },
16973   { STRING_COMMA_LEN ("false_os") },
16974   { STRING_COMMA_LEN ("neq_os") },
16975   { STRING_COMMA_LEN ("ge_oq") },
16976   { STRING_COMMA_LEN ("gt_oq") },
16977   { STRING_COMMA_LEN ("true_us") },
16978 };
16979
16980 static void
16981 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16982 {
16983   unsigned int cmp_type;
16984
16985   FETCH_DATA (the_info, codep + 1);
16986   cmp_type = *codep++ & 0xff;
16987   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16988     {
16989       char suffix [3];
16990       char *p = mnemonicendp - 2;
16991       suffix[0] = p[0];
16992       suffix[1] = p[1];
16993       suffix[2] = '\0';
16994       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16995       mnemonicendp += vex_cmp_op[cmp_type].len;
16996     }
16997   else
16998     {
16999       /* We have a reserved extension byte.  Output it directly.  */
17000       scratchbuf[0] = '$';
17001       print_operand_value (scratchbuf + 1, 1, cmp_type);
17002       oappend_maybe_intel (scratchbuf);
17003       scratchbuf[0] = '\0';
17004     }
17005 }
17006
17007 static void
17008 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17009              int sizeflag ATTRIBUTE_UNUSED)
17010 {
17011   unsigned int cmp_type;
17012
17013   if (!vex.evex)
17014     abort ();
17015
17016   FETCH_DATA (the_info, codep + 1);
17017   cmp_type = *codep++ & 0xff;
17018   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17019      If it's the case, print suffix, otherwise - print the immediate.  */
17020   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17021       && cmp_type != 3
17022       && cmp_type != 7)
17023     {
17024       char suffix [3];
17025       char *p = mnemonicendp - 2;
17026
17027       /* vpcmp* can have both one- and two-lettered suffix.  */
17028       if (p[0] == 'p')
17029         {
17030           p++;
17031           suffix[0] = p[0];
17032           suffix[1] = '\0';
17033         }
17034       else
17035         {
17036           suffix[0] = p[0];
17037           suffix[1] = p[1];
17038           suffix[2] = '\0';
17039         }
17040
17041       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17042       mnemonicendp += simd_cmp_op[cmp_type].len;
17043     }
17044   else
17045     {
17046       /* We have a reserved extension byte.  Output it directly.  */
17047       scratchbuf[0] = '$';
17048       print_operand_value (scratchbuf + 1, 1, cmp_type);
17049       oappend_maybe_intel (scratchbuf);
17050       scratchbuf[0] = '\0';
17051     }
17052 }
17053
17054 static const struct op pclmul_op[] =
17055 {
17056   { STRING_COMMA_LEN ("lql") },
17057   { STRING_COMMA_LEN ("hql") },
17058   { STRING_COMMA_LEN ("lqh") },
17059   { STRING_COMMA_LEN ("hqh") }
17060 };
17061
17062 static void
17063 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17064               int sizeflag ATTRIBUTE_UNUSED)
17065 {
17066   unsigned int pclmul_type;
17067
17068   FETCH_DATA (the_info, codep + 1);
17069   pclmul_type = *codep++ & 0xff;
17070   switch (pclmul_type)
17071     {
17072     case 0x10:
17073       pclmul_type = 2;
17074       break;
17075     case 0x11:
17076       pclmul_type = 3;
17077       break;
17078     default:
17079       break;
17080     }
17081   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17082     {
17083       char suffix [4];
17084       char *p = mnemonicendp - 3;
17085       suffix[0] = p[0];
17086       suffix[1] = p[1];
17087       suffix[2] = p[2];
17088       suffix[3] = '\0';
17089       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17090       mnemonicendp += pclmul_op[pclmul_type].len;
17091     }
17092   else
17093     {
17094       /* We have a reserved extension byte.  Output it directly.  */
17095       scratchbuf[0] = '$';
17096       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17097       oappend_maybe_intel (scratchbuf);
17098       scratchbuf[0] = '\0';
17099     }
17100 }
17101
17102 static void
17103 MOVBE_Fixup (int bytemode, int sizeflag)
17104 {
17105   /* Add proper suffix to "movbe".  */
17106   char *p = mnemonicendp;
17107
17108   switch (bytemode)
17109     {
17110     case v_mode:
17111       if (intel_syntax)
17112         goto skip;
17113
17114       USED_REX (REX_W);
17115       if (sizeflag & SUFFIX_ALWAYS)
17116         {
17117           if (rex & REX_W)
17118             *p++ = 'q';
17119           else
17120             {
17121               if (sizeflag & DFLAG)
17122                 *p++ = 'l';
17123               else
17124                 *p++ = 'w';
17125               used_prefixes |= (prefixes & PREFIX_DATA);
17126             }
17127         }
17128       break;
17129     default:
17130       oappend (INTERNAL_DISASSEMBLER_ERROR);
17131       break;
17132     }
17133   mnemonicendp = p;
17134   *p = '\0';
17135
17136 skip:
17137   OP_M (bytemode, sizeflag);
17138 }
17139
17140 static void
17141 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17142 {
17143   int reg;
17144   const char **names;
17145
17146   /* Skip mod/rm byte.  */
17147   MODRM_CHECK;
17148   codep++;
17149
17150   if (vex.w)
17151     names = names64;
17152   else
17153     names = names32;
17154
17155   reg = modrm.rm;
17156   USED_REX (REX_B);
17157   if (rex & REX_B)
17158     reg += 8;
17159
17160   oappend (names[reg]);
17161 }
17162
17163 static void
17164 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17165 {
17166   const char **names;
17167
17168   if (vex.w)
17169     names = names64;
17170   else
17171     names = names32;
17172
17173   oappend (names[vex.register_specifier]);
17174 }
17175
17176 static void
17177 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17178 {
17179   if (!vex.evex
17180       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17181     abort ();
17182
17183   USED_REX (REX_R);
17184   if ((rex & REX_R) != 0 || !vex.r)
17185     {
17186       BadOp ();
17187       return;
17188     }
17189
17190   oappend (names_mask [modrm.reg]);
17191 }
17192
17193 static void
17194 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17195 {
17196   if (!vex.evex
17197       || (bytemode != evex_rounding_mode
17198           && bytemode != evex_sae_mode))
17199     abort ();
17200   if (modrm.mod == 3 && vex.b)
17201     switch (bytemode)
17202       {
17203       case evex_rounding_mode:
17204         oappend (names_rounding[vex.ll]);
17205         break;
17206       case evex_sae_mode:
17207         oappend ("{sae}");
17208         break;
17209       default:
17210         break;
17211       }
17212 }