opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Cm { OP_C, m_mode }
 301 #define Dm { OP_D, m_mode }
 302 #define Td { OP_T, d_mode }
 303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 304
 305 #define RMeAX { OP_REG, eAX_reg }
 306 #define RMeBX { OP_REG, eBX_reg }
 307 #define RMeCX { OP_REG, eCX_reg }
 308 #define RMeDX { OP_REG, eDX_reg }
 309 #define RMeSP { OP_REG, eSP_reg }
 310 #define RMeBP { OP_REG, eBP_reg }
 311 #define RMeSI { OP_REG, eSI_reg }
 312 #define RMeDI { OP_REG, eDI_reg }
 313 #define RMrAX { OP_REG, rAX_reg }
 314 #define RMrBX { OP_REG, rBX_reg }
 315 #define RMrCX { OP_REG, rCX_reg }
 316 #define RMrDX { OP_REG, rDX_reg }
 317 #define RMrSP { OP_REG, rSP_reg }
 318 #define RMrBP { OP_REG, rBP_reg }
 319 #define RMrSI { OP_REG, rSI_reg }
 320 #define RMrDI { OP_REG, rDI_reg }
 321 #define RMAL { OP_REG, al_reg }
 322 #define RMCL { OP_REG, cl_reg }
 323 #define RMDL { OP_REG, dl_reg }
 324 #define RMBL { OP_REG, bl_reg }
 325 #define RMAH { OP_REG, ah_reg }
 326 #define RMCH { OP_REG, ch_reg }
 327 #define RMDH { OP_REG, dh_reg }
 328 #define RMBH { OP_REG, bh_reg }
 329 #define RMAX { OP_REG, ax_reg }
 330 #define RMDX { OP_REG, dx_reg }
 331
 332 #define eAX { OP_IMREG, eAX_reg }
 333 #define eBX { OP_IMREG, eBX_reg }
 334 #define eCX { OP_IMREG, eCX_reg }
 335 #define eDX { OP_IMREG, eDX_reg }
 336 #define eSP { OP_IMREG, eSP_reg }
 337 #define eBP { OP_IMREG, eBP_reg }
 338 #define eSI { OP_IMREG, eSI_reg }
 339 #define eDI { OP_IMREG, eDI_reg }
 340 #define AL { OP_IMREG, al_reg }
 341 #define CL { OP_IMREG, cl_reg }
 342 #define DL { OP_IMREG, dl_reg }
 343 #define BL { OP_IMREG, bl_reg }
 344 #define AH { OP_IMREG, ah_reg }
 345 #define CH { OP_IMREG, ch_reg }
 346 #define DH { OP_IMREG, dh_reg }
 347 #define BH { OP_IMREG, bh_reg }
 348 #define AX { OP_IMREG, ax_reg }
 349 #define DX { OP_IMREG, dx_reg }
 350 #define zAX { OP_IMREG, z_mode_ax_reg }
 351 #define indirDX { OP_IMREG, indir_dx_reg }
 352
 353 #define Sw { OP_SEG, w_mode }
 354 #define Sv { OP_SEG, v_mode }
 355 #define Ap { OP_DIR, 0 }
 356 #define Ob { OP_OFF64, b_mode }
 357 #define Ov { OP_OFF64, v_mode }
 358 #define Xb { OP_DSreg, eSI_reg }
 359 #define Xv { OP_DSreg, eSI_reg }
 360 #define Xz { OP_DSreg, eSI_reg }
 361 #define Yb { OP_ESreg, eDI_reg }
 362 #define Yv { OP_ESreg, eDI_reg }
 363 #define DSBX { OP_DSreg, eBX_reg }
 364
 365 #define es { OP_REG, es_reg }
 366 #define ss { OP_REG, ss_reg }
 367 #define cs { OP_REG, cs_reg }
 368 #define ds { OP_REG, ds_reg }
 369 #define fs { OP_REG, fs_reg }
 370 #define gs { OP_REG, gs_reg }
 371
 372 #define MX { OP_MMX, 0 }
 373 #define XM { OP_XMM, 0 }
 374 #define XMScalar { OP_XMM, scalar_mode }
 375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 376 #define XMM { OP_XMM, xmm_mode }
 377 #define XMxmmq { OP_XMM, xmmq_mode }
 378 #define EM { OP_EM, v_mode }
 379 #define EMS { OP_EM, v_swap_mode }
 380 #define EMd { OP_EM, d_mode }
 381 #define EMx { OP_EM, x_mode }
 382 #define EXbScalar { OP_EX, b_scalar_mode }
 383 #define EXw { OP_EX, w_mode }
 384 #define EXwScalar { OP_EX, w_scalar_mode }
 385 #define EXd { OP_EX, d_mode }
 386 #define EXdScalar { OP_EX, d_scalar_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 389 #define EXq { OP_EX, q_mode }
 390 #define EXqScalar { OP_EX, q_scalar_mode }
 391 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 392 #define EXqS { OP_EX, q_swap_mode }
 393 #define EXx { OP_EX, x_mode }
 394 #define EXxS { OP_EX, x_swap_mode }
 395 #define EXxmm { OP_EX, xmm_mode }
 396 #define EXymm { OP_EX, ymm_mode }
 397 #define EXxmmq { OP_EX, xmmq_mode }
 398 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 399 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 400 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 401 #define EXxmm_md { OP_EX, xmm_md_mode }
 402 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 403 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 404 #define EXxmmdw { OP_EX, xmmdw_mode }
 405 #define EXxmmqd { OP_EX, xmmqd_mode }
 406 #define EXymmq { OP_EX, ymmq_mode }
 407 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 408 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 409 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 410 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 411 #define MS { OP_MS, v_mode }
 412 #define XS { OP_XS, v_mode }
 413 #define EMCq { OP_EMC, q_mode }
 414 #define MXC { OP_MXC, 0 }
 415 #define OPSUF { OP_3DNowSuffix, 0 }
 416 #define CMP { CMP_Fixup, 0 }
 417 #define XMM0 { XMM_Fixup, 0 }
 418 #define FXSAVE { FXSAVE_Fixup, 0 }
 419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 421
 422 #define Vex { OP_VEX, vex_mode }
 423 #define VexScalar { OP_VEX, vex_scalar_mode }
 424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 425 #define Vex128 { OP_VEX, vex128_mode }
 426 #define Vex256 { OP_VEX, vex256_mode }
 427 #define VexGdq { OP_VEX, dq_mode }
 428 #define EXdVex { OP_EX_Vex, d_mode }
 429 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 431 #define EXqVex { OP_EX_Vex, q_mode }
 432 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 433 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 434 #define EXVexW { OP_EX_VexW, x_mode }
 435 #define EXdVexW { OP_EX_VexW, d_mode }
 436 #define EXqVexW { OP_EX_VexW, q_mode }
 437 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 438 #define XMVex { OP_XMM_Vex, 0 }
 439 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 440 #define XMVexW { OP_XMM_VexW, 0 }
 441 #define XMVexI4 { OP_REG_VexI4, x_mode }
 442 #define PCLMUL { PCLMUL_Fixup, 0 }
 443 #define VCMP { VCMP_Fixup, 0 }
 444 #define VPCMP { VPCMP_Fixup, 0 }
 445 #define VPCOM { VPCOM_Fixup, 0 }
 446
 447 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 448 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 449 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 450
 451 #define XMask { OP_Mask, mask_mode }
 452 #define MaskG { OP_G, mask_mode }
 453 #define MaskE { OP_E, mask_mode }
 454 #define MaskBDE { OP_E, mask_bd_mode }
 455 #define MaskR { OP_R, mask_mode }
 456 #define MaskVex { OP_VEX, mask_mode }
 457
 458 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 459 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 460 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 461 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 462
 463 /* Used handle "rep" prefix for string instructions.  */
 464 #define Xbr { REP_Fixup, eSI_reg }
 465 #define Xvr { REP_Fixup, eSI_reg }
 466 #define Ybr { REP_Fixup, eDI_reg }
 467 #define Yvr { REP_Fixup, eDI_reg }
 468 #define Yzr { REP_Fixup, eDI_reg }
 469 #define indirDXr { REP_Fixup, indir_dx_reg }
 470 #define ALr { REP_Fixup, al_reg }
 471 #define eAXr { REP_Fixup, eAX_reg }
 472
 473 /* Used handle HLE prefix for lockable instructions.  */
 474 #define Ebh1 { HLE_Fixup1, b_mode }
 475 #define Evh1 { HLE_Fixup1, v_mode }
 476 #define Ebh2 { HLE_Fixup2, b_mode }
 477 #define Evh2 { HLE_Fixup2, v_mode }
 478 #define Ebh3 { HLE_Fixup3, b_mode }
 479 #define Evh3 { HLE_Fixup3, v_mode }
 480
 481 #define BND { BND_Fixup, 0 }
 482 #define NOTRACK { NOTRACK_Fixup, 0 }
 483
 484 #define cond_jump_flag { NULL, cond_jump_mode }
 485 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 486
 487 /* bits in sizeflag */
 488 #define SUFFIX_ALWAYS 4
 489 #define AFLAG 2
 490 #define DFLAG 1
 491
 492 enum
 493 {
 494   /* byte operand */
 495   b_mode = 1,
 496   /* byte operand with operand swapped */
 497   b_swap_mode,
 498   /* byte operand, sign extend like 'T' suffix */
 499   b_T_mode,
 500   /* operand size depends on prefixes */
 501   v_mode,
 502   /* operand size depends on prefixes with operand swapped */
 503   v_swap_mode,
 504   /* operand size depends on address prefix */
 505   va_mode,
 506   /* word operand */
 507   w_mode,
 508   /* double word operand  */
 509   d_mode,
 510   /* double word operand with operand swapped */
 511   d_swap_mode,
 512   /* quad word operand */
 513   q_mode,
 514   /* quad word operand with operand swapped */
 515   q_swap_mode,
 516   /* ten-byte operand */
 517   t_mode,
 518   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 519      broadcast enabled.  */
 520   x_mode,
 521   /* Similar to x_mode, but with different EVEX mem shifts.  */
 522   evex_x_gscat_mode,
 523   /* Similar to x_mode, but with disabled broadcast.  */
 524   evex_x_nobcst_mode,
 525   /* Similar to x_mode, but with operands swapped and disabled broadcast
 526      in EVEX.  */
 527   x_swap_mode,
 528   /* 16-byte XMM operand */
 529   xmm_mode,
 530   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 531      memory operand (depending on vector length).  Broadcast isn't
 532      allowed.  */
 533   xmmq_mode,
 534   /* Same as xmmq_mode, but broadcast is allowed.  */
 535   evex_half_bcst_xmmq_mode,
 536   /* XMM register or byte memory operand */
 537   xmm_mb_mode,
 538   /* XMM register or word memory operand */
 539   xmm_mw_mode,
 540   /* XMM register or double word memory operand */
 541   xmm_md_mode,
 542   /* XMM register or quad word memory operand */
 543   xmm_mq_mode,
 544   /* XMM register or double/quad word memory operand, depending on
 545      VEX.W.  */
 546   xmm_mdq_mode,
 547   /* 16-byte XMM, word, double word or quad word operand.  */
 548   xmmdw_mode,
 549   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 550   xmmqd_mode,
 551   /* 32-byte YMM operand */
 552   ymm_mode,
 553   /* quad word, ymmword or zmmword memory operand.  */
 554   ymmq_mode,
 555   /* 32-byte YMM or 16-byte word operand */
 556   ymmxmm_mode,
 557   /* d_mode in 32bit, q_mode in 64bit mode.  */
 558   m_mode,
 559   /* pair of v_mode operands */
 560   a_mode,
 561   cond_jump_mode,
 562   loop_jcxz_mode,
 563   v_bnd_mode,
 564   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 565   v_bndmk_mode,
 566   /* operand size depends on REX prefixes.  */
 567   dq_mode,
 568   /* registers like dq_mode, memory like w_mode.  */
 569   dqw_mode,
 570   /* bounds operand */
 571   bnd_mode,
 572   /* bounds operand with operand swapped */
 573   bnd_swap_mode,
 574   /* 4- or 6-byte pointer operand */
 575   f_mode,
 576   const_1_mode,
 577   /* v_mode for indirect branch opcodes.  */
 578   indir_v_mode,
 579   /* v_mode for stack-related opcodes.  */
 580   stack_v_mode,
 581   /* non-quad operand size depends on prefixes */
 582   z_mode,
 583   /* 16-byte operand */
 584   o_mode,
 585   /* registers like dq_mode, memory like b_mode.  */
 586   dqb_mode,
 587   /* registers like d_mode, memory like b_mode.  */
 588   db_mode,
 589   /* registers like d_mode, memory like w_mode.  */
 590   dw_mode,
 591   /* registers like dq_mode, memory like d_mode.  */
 592   dqd_mode,
 593   /* normal vex mode */
 594   vex_mode,
 595   /* 128bit vex mode */
 596   vex128_mode,
 597   /* 256bit vex mode */
 598   vex256_mode,
 599   /* operand size depends on the VEX.W bit.  */
 600   vex_w_dq_mode,
 601
 602   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 603   vex_vsib_d_w_dq_mode,
 604   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 605   vex_vsib_d_w_d_mode,
 606   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 607   vex_vsib_q_w_dq_mode,
 608   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 609   vex_vsib_q_w_d_mode,
 610
 611   /* scalar, ignore vector length.  */
 612   scalar_mode,
 613   /* like b_mode, ignore vector length.  */
 614   b_scalar_mode,
 615   /* like w_mode, ignore vector length.  */
 616   w_scalar_mode,
 617   /* like d_mode, ignore vector length.  */
 618   d_scalar_mode,
 619   /* like d_swap_mode, ignore vector length.  */
 620   d_scalar_swap_mode,
 621   /* like q_mode, ignore vector length.  */
 622   q_scalar_mode,
 623   /* like q_swap_mode, ignore vector length.  */
 624   q_scalar_swap_mode,
 625   /* like vex_mode, ignore vector length.  */
 626   vex_scalar_mode,
 627   /* like vex_w_dq_mode, ignore vector length.  */
 628   vex_scalar_w_dq_mode,
 629
 630   /* Static rounding.  */
 631   evex_rounding_mode,
 632   /* Static rounding, 64-bit mode only.  */
 633   evex_rounding_64_mode,
 634   /* Supress all exceptions.  */
 635   evex_sae_mode,
 636
 637   /* Mask register operand.  */
 638   mask_mode,
 639   /* Mask register operand.  */
 640   mask_bd_mode,
 641
 642   es_reg,
 643   cs_reg,
 644   ss_reg,
 645   ds_reg,
 646   fs_reg,
 647   gs_reg,
 648
 649   eAX_reg,
 650   eCX_reg,
 651   eDX_reg,
 652   eBX_reg,
 653   eSP_reg,
 654   eBP_reg,
 655   eSI_reg,
 656   eDI_reg,
 657
 658   al_reg,
 659   cl_reg,
 660   dl_reg,
 661   bl_reg,
 662   ah_reg,
 663   ch_reg,
 664   dh_reg,
 665   bh_reg,
 666
 667   ax_reg,
 668   cx_reg,
 669   dx_reg,
 670   bx_reg,
 671   sp_reg,
 672   bp_reg,
 673   si_reg,
 674   di_reg,
 675
 676   rAX_reg,
 677   rCX_reg,
 678   rDX_reg,
 679   rBX_reg,
 680   rSP_reg,
 681   rBP_reg,
 682   rSI_reg,
 683   rDI_reg,
 684
 685   z_mode_ax_reg,
 686   indir_dx_reg
 687 };
 688
 689 enum
 690 {
 691   FLOATCODE = 1,
 692   USE_REG_TABLE,
 693   USE_MOD_TABLE,
 694   USE_RM_TABLE,
 695   USE_PREFIX_TABLE,
 696   USE_X86_64_TABLE,
 697   USE_3BYTE_TABLE,
 698   USE_XOP_8F_TABLE,
 699   USE_VEX_C4_TABLE,
 700   USE_VEX_C5_TABLE,
 701   USE_VEX_LEN_TABLE,
 702   USE_VEX_W_TABLE,
 703   USE_EVEX_TABLE,
 704   USE_EVEX_LEN_TABLE
 705 };
 706
 707 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 708
 709 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 710 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 711 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 712 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 713 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 714 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 715 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 716 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 717 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 718 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 719 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 720 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 721 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 722 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 723 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 724 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 725
 726 enum
 727 {
 728   REG_80 = 0,
 729   REG_81,
 730   REG_83,
 731   REG_8F,
 732   REG_C0,
 733   REG_C1,
 734   REG_C6,
 735   REG_C7,
 736   REG_D0,
 737   REG_D1,
 738   REG_D2,
 739   REG_D3,
 740   REG_F6,
 741   REG_F7,
 742   REG_FE,
 743   REG_FF,
 744   REG_0F00,
 745   REG_0F01,
 746   REG_0F0D,
 747   REG_0F18,
 748   REG_0F1C_MOD_0,
 749   REG_0F1E_MOD_3,
 750   REG_0F71,
 751   REG_0F72,
 752   REG_0F73,
 753   REG_0FA6,
 754   REG_0FA7,
 755   REG_0FAE,
 756   REG_0FBA,
 757   REG_0FC7,
 758   REG_VEX_0F71,
 759   REG_VEX_0F72,
 760   REG_VEX_0F73,
 761   REG_VEX_0FAE,
 762   REG_VEX_0F38F3,
 763   REG_XOP_LWPCB,
 764   REG_XOP_LWP,
 765   REG_XOP_TBM_01,
 766   REG_XOP_TBM_02,
 767
 768   REG_EVEX_0F71,
 769   REG_EVEX_0F72,
 770   REG_EVEX_0F73,
 771   REG_EVEX_0F38C6,
 772   REG_EVEX_0F38C7
 773 };
 774
 775 enum
 776 {
 777   MOD_8D = 0,
 778   MOD_C6_REG_7,
 779   MOD_C7_REG_7,
 780   MOD_FF_REG_3,
 781   MOD_FF_REG_5,
 782   MOD_0F01_REG_0,
 783   MOD_0F01_REG_1,
 784   MOD_0F01_REG_2,
 785   MOD_0F01_REG_3,
 786   MOD_0F01_REG_5,
 787   MOD_0F01_REG_7,
 788   MOD_0F12_PREFIX_0,
 789   MOD_0F13,
 790   MOD_0F16_PREFIX_0,
 791   MOD_0F17,
 792   MOD_0F18_REG_0,
 793   MOD_0F18_REG_1,
 794   MOD_0F18_REG_2,
 795   MOD_0F18_REG_3,
 796   MOD_0F18_REG_4,
 797   MOD_0F18_REG_5,
 798   MOD_0F18_REG_6,
 799   MOD_0F18_REG_7,
 800   MOD_0F1A_PREFIX_0,
 801   MOD_0F1B_PREFIX_0,
 802   MOD_0F1B_PREFIX_1,
 803   MOD_0F1C_PREFIX_0,
 804   MOD_0F1E_PREFIX_1,
 805   MOD_0F24,
 806   MOD_0F26,
 807   MOD_0F2B_PREFIX_0,
 808   MOD_0F2B_PREFIX_1,
 809   MOD_0F2B_PREFIX_2,
 810   MOD_0F2B_PREFIX_3,
 811   MOD_0F51,
 812   MOD_0F71_REG_2,
 813   MOD_0F71_REG_4,
 814   MOD_0F71_REG_6,
 815   MOD_0F72_REG_2,
 816   MOD_0F72_REG_4,
 817   MOD_0F72_REG_6,
 818   MOD_0F73_REG_2,
 819   MOD_0F73_REG_3,
 820   MOD_0F73_REG_6,
 821   MOD_0F73_REG_7,
 822   MOD_0FAE_REG_0,
 823   MOD_0FAE_REG_1,
 824   MOD_0FAE_REG_2,
 825   MOD_0FAE_REG_3,
 826   MOD_0FAE_REG_4,
 827   MOD_0FAE_REG_5,
 828   MOD_0FAE_REG_6,
 829   MOD_0FAE_REG_7,
 830   MOD_0FB2,
 831   MOD_0FB4,
 832   MOD_0FB5,
 833   MOD_0FC3,
 834   MOD_0FC7_REG_3,
 835   MOD_0FC7_REG_4,
 836   MOD_0FC7_REG_5,
 837   MOD_0FC7_REG_6,
 838   MOD_0FC7_REG_7,
 839   MOD_0FD7,
 840   MOD_0FE7_PREFIX_2,
 841   MOD_0FF0_PREFIX_3,
 842   MOD_0F382A_PREFIX_2,
 843   MOD_0F38F5_PREFIX_2,
 844   MOD_0F38F6_PREFIX_0,
 845   MOD_0F38F8_PREFIX_1,
 846   MOD_0F38F8_PREFIX_2,
 847   MOD_0F38F8_PREFIX_3,
 848   MOD_0F38F9_PREFIX_0,
 849   MOD_62_32BIT,
 850   MOD_C4_32BIT,
 851   MOD_C5_32BIT,
 852   MOD_VEX_0F12_PREFIX_0,
 853   MOD_VEX_0F13,
 854   MOD_VEX_0F16_PREFIX_0,
 855   MOD_VEX_0F17,
 856   MOD_VEX_0F2B,
 857   MOD_VEX_W_0_0F41_P_0_LEN_1,
 858   MOD_VEX_W_1_0F41_P_0_LEN_1,
 859   MOD_VEX_W_0_0F41_P_2_LEN_1,
 860   MOD_VEX_W_1_0F41_P_2_LEN_1,
 861   MOD_VEX_W_0_0F42_P_0_LEN_1,
 862   MOD_VEX_W_1_0F42_P_0_LEN_1,
 863   MOD_VEX_W_0_0F42_P_2_LEN_1,
 864   MOD_VEX_W_1_0F42_P_2_LEN_1,
 865   MOD_VEX_W_0_0F44_P_0_LEN_1,
 866   MOD_VEX_W_1_0F44_P_0_LEN_1,
 867   MOD_VEX_W_0_0F44_P_2_LEN_1,
 868   MOD_VEX_W_1_0F44_P_2_LEN_1,
 869   MOD_VEX_W_0_0F45_P_0_LEN_1,
 870   MOD_VEX_W_1_0F45_P_0_LEN_1,
 871   MOD_VEX_W_0_0F45_P_2_LEN_1,
 872   MOD_VEX_W_1_0F45_P_2_LEN_1,
 873   MOD_VEX_W_0_0F46_P_0_LEN_1,
 874   MOD_VEX_W_1_0F46_P_0_LEN_1,
 875   MOD_VEX_W_0_0F46_P_2_LEN_1,
 876   MOD_VEX_W_1_0F46_P_2_LEN_1,
 877   MOD_VEX_W_0_0F47_P_0_LEN_1,
 878   MOD_VEX_W_1_0F47_P_0_LEN_1,
 879   MOD_VEX_W_0_0F47_P_2_LEN_1,
 880   MOD_VEX_W_1_0F47_P_2_LEN_1,
 881   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 882   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 883   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 884   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 885   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 886   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 887   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 888   MOD_VEX_0F50,
 889   MOD_VEX_0F71_REG_2,
 890   MOD_VEX_0F71_REG_4,
 891   MOD_VEX_0F71_REG_6,
 892   MOD_VEX_0F72_REG_2,
 893   MOD_VEX_0F72_REG_4,
 894   MOD_VEX_0F72_REG_6,
 895   MOD_VEX_0F73_REG_2,
 896   MOD_VEX_0F73_REG_3,
 897   MOD_VEX_0F73_REG_6,
 898   MOD_VEX_0F73_REG_7,
 899   MOD_VEX_W_0_0F91_P_0_LEN_0,
 900   MOD_VEX_W_1_0F91_P_0_LEN_0,
 901   MOD_VEX_W_0_0F91_P_2_LEN_0,
 902   MOD_VEX_W_1_0F91_P_2_LEN_0,
 903   MOD_VEX_W_0_0F92_P_0_LEN_0,
 904   MOD_VEX_W_0_0F92_P_2_LEN_0,
 905   MOD_VEX_0F92_P_3_LEN_0,
 906   MOD_VEX_W_0_0F93_P_0_LEN_0,
 907   MOD_VEX_W_0_0F93_P_2_LEN_0,
 908   MOD_VEX_0F93_P_3_LEN_0,
 909   MOD_VEX_W_0_0F98_P_0_LEN_0,
 910   MOD_VEX_W_1_0F98_P_0_LEN_0,
 911   MOD_VEX_W_0_0F98_P_2_LEN_0,
 912   MOD_VEX_W_1_0F98_P_2_LEN_0,
 913   MOD_VEX_W_0_0F99_P_0_LEN_0,
 914   MOD_VEX_W_1_0F99_P_0_LEN_0,
 915   MOD_VEX_W_0_0F99_P_2_LEN_0,
 916   MOD_VEX_W_1_0F99_P_2_LEN_0,
 917   MOD_VEX_0FAE_REG_2,
 918   MOD_VEX_0FAE_REG_3,
 919   MOD_VEX_0FD7_PREFIX_2,
 920   MOD_VEX_0FE7_PREFIX_2,
 921   MOD_VEX_0FF0_PREFIX_3,
 922   MOD_VEX_0F381A_PREFIX_2,
 923   MOD_VEX_0F382A_PREFIX_2,
 924   MOD_VEX_0F382C_PREFIX_2,
 925   MOD_VEX_0F382D_PREFIX_2,
 926   MOD_VEX_0F382E_PREFIX_2,
 927   MOD_VEX_0F382F_PREFIX_2,
 928   MOD_VEX_0F385A_PREFIX_2,
 929   MOD_VEX_0F388C_PREFIX_2,
 930   MOD_VEX_0F388E_PREFIX_2,
 931   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 932   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 933   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 934   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 935   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 936   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 937   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 938   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 939
 940   MOD_EVEX_0F10_PREFIX_1,
 941   MOD_EVEX_0F10_PREFIX_3,
 942   MOD_EVEX_0F11_PREFIX_1,
 943   MOD_EVEX_0F11_PREFIX_3,
 944   MOD_EVEX_0F12_PREFIX_0,
 945   MOD_EVEX_0F16_PREFIX_0,
 946   MOD_EVEX_0F38C6_REG_1,
 947   MOD_EVEX_0F38C6_REG_2,
 948   MOD_EVEX_0F38C6_REG_5,
 949   MOD_EVEX_0F38C6_REG_6,
 950   MOD_EVEX_0F38C7_REG_1,
 951   MOD_EVEX_0F38C7_REG_2,
 952   MOD_EVEX_0F38C7_REG_5,
 953   MOD_EVEX_0F38C7_REG_6
 954 };
 955
 956 enum
 957 {
 958   RM_C6_REG_7 = 0,
 959   RM_C7_REG_7,
 960   RM_0F01_REG_0,
 961   RM_0F01_REG_1,
 962   RM_0F01_REG_2,
 963   RM_0F01_REG_3,
 964   RM_0F01_REG_5,
 965   RM_0F01_REG_7,
 966   RM_0F1E_MOD_3_REG_7,
 967   RM_0FAE_REG_6,
 968   RM_0FAE_REG_7
 969 };
 970
 971 enum
 972 {
 973   PREFIX_90 = 0,
 974   PREFIX_MOD_0_0F01_REG_5,
 975   PREFIX_MOD_3_0F01_REG_5_RM_0,
 976   PREFIX_MOD_3_0F01_REG_5_RM_2,
 977   PREFIX_0F09,
 978   PREFIX_0F10,
 979   PREFIX_0F11,
 980   PREFIX_0F12,
 981   PREFIX_0F16,
 982   PREFIX_0F1A,
 983   PREFIX_0F1B,
 984   PREFIX_0F1C,
 985   PREFIX_0F1E,
 986   PREFIX_0F2A,
 987   PREFIX_0F2B,
 988   PREFIX_0F2C,
 989   PREFIX_0F2D,
 990   PREFIX_0F2E,
 991   PREFIX_0F2F,
 992   PREFIX_0F51,
 993   PREFIX_0F52,
 994   PREFIX_0F53,
 995   PREFIX_0F58,
 996   PREFIX_0F59,
 997   PREFIX_0F5A,
 998   PREFIX_0F5B,
 999   PREFIX_0F5C,
1000   PREFIX_0F5D,
1001   PREFIX_0F5E,
1002   PREFIX_0F5F,
1003   PREFIX_0F60,
1004   PREFIX_0F61,
1005   PREFIX_0F62,
1006   PREFIX_0F6C,
1007   PREFIX_0F6D,
1008   PREFIX_0F6F,
1009   PREFIX_0F70,
1010   PREFIX_0F73_REG_3,
1011   PREFIX_0F73_REG_7,
1012   PREFIX_0F78,
1013   PREFIX_0F79,
1014   PREFIX_0F7C,
1015   PREFIX_0F7D,
1016   PREFIX_0F7E,
1017   PREFIX_0F7F,
1018   PREFIX_0FAE_REG_0,
1019   PREFIX_0FAE_REG_1,
1020   PREFIX_0FAE_REG_2,
1021   PREFIX_0FAE_REG_3,
1022   PREFIX_MOD_0_0FAE_REG_4,
1023   PREFIX_MOD_3_0FAE_REG_4,
1024   PREFIX_MOD_0_0FAE_REG_5,
1025   PREFIX_MOD_3_0FAE_REG_5,
1026   PREFIX_MOD_0_0FAE_REG_6,
1027   PREFIX_MOD_1_0FAE_REG_6,
1028   PREFIX_0FAE_REG_7,
1029   PREFIX_0FB8,
1030   PREFIX_0FBC,
1031   PREFIX_0FBD,
1032   PREFIX_0FC2,
1033   PREFIX_MOD_0_0FC3,
1034   PREFIX_MOD_0_0FC7_REG_6,
1035   PREFIX_MOD_3_0FC7_REG_6,
1036   PREFIX_MOD_3_0FC7_REG_7,
1037   PREFIX_0FD0,
1038   PREFIX_0FD6,
1039   PREFIX_0FE6,
1040   PREFIX_0FE7,
1041   PREFIX_0FF0,
1042   PREFIX_0FF7,
1043   PREFIX_0F3810,
1044   PREFIX_0F3814,
1045   PREFIX_0F3815,
1046   PREFIX_0F3817,
1047   PREFIX_0F3820,
1048   PREFIX_0F3821,
1049   PREFIX_0F3822,
1050   PREFIX_0F3823,
1051   PREFIX_0F3824,
1052   PREFIX_0F3825,
1053   PREFIX_0F3828,
1054   PREFIX_0F3829,
1055   PREFIX_0F382A,
1056   PREFIX_0F382B,
1057   PREFIX_0F3830,
1058   PREFIX_0F3831,
1059   PREFIX_0F3832,
1060   PREFIX_0F3833,
1061   PREFIX_0F3834,
1062   PREFIX_0F3835,
1063   PREFIX_0F3837,
1064   PREFIX_0F3838,
1065   PREFIX_0F3839,
1066   PREFIX_0F383A,
1067   PREFIX_0F383B,
1068   PREFIX_0F383C,
1069   PREFIX_0F383D,
1070   PREFIX_0F383E,
1071   PREFIX_0F383F,
1072   PREFIX_0F3840,
1073   PREFIX_0F3841,
1074   PREFIX_0F3880,
1075   PREFIX_0F3881,
1076   PREFIX_0F3882,
1077   PREFIX_0F38C8,
1078   PREFIX_0F38C9,
1079   PREFIX_0F38CA,
1080   PREFIX_0F38CB,
1081   PREFIX_0F38CC,
1082   PREFIX_0F38CD,
1083   PREFIX_0F38CF,
1084   PREFIX_0F38DB,
1085   PREFIX_0F38DC,
1086   PREFIX_0F38DD,
1087   PREFIX_0F38DE,
1088   PREFIX_0F38DF,
1089   PREFIX_0F38F0,
1090   PREFIX_0F38F1,
1091   PREFIX_0F38F5,
1092   PREFIX_0F38F6,
1093   PREFIX_0F38F8,
1094   PREFIX_0F38F9,
1095   PREFIX_0F3A08,
1096   PREFIX_0F3A09,
1097   PREFIX_0F3A0A,
1098   PREFIX_0F3A0B,
1099   PREFIX_0F3A0C,
1100   PREFIX_0F3A0D,
1101   PREFIX_0F3A0E,
1102   PREFIX_0F3A14,
1103   PREFIX_0F3A15,
1104   PREFIX_0F3A16,
1105   PREFIX_0F3A17,
1106   PREFIX_0F3A20,
1107   PREFIX_0F3A21,
1108   PREFIX_0F3A22,
1109   PREFIX_0F3A40,
1110   PREFIX_0F3A41,
1111   PREFIX_0F3A42,
1112   PREFIX_0F3A44,
1113   PREFIX_0F3A60,
1114   PREFIX_0F3A61,
1115   PREFIX_0F3A62,
1116   PREFIX_0F3A63,
1117   PREFIX_0F3ACC,
1118   PREFIX_0F3ACE,
1119   PREFIX_0F3ACF,
1120   PREFIX_0F3ADF,
1121   PREFIX_VEX_0F10,
1122   PREFIX_VEX_0F11,
1123   PREFIX_VEX_0F12,
1124   PREFIX_VEX_0F16,
1125   PREFIX_VEX_0F2A,
1126   PREFIX_VEX_0F2C,
1127   PREFIX_VEX_0F2D,
1128   PREFIX_VEX_0F2E,
1129   PREFIX_VEX_0F2F,
1130   PREFIX_VEX_0F41,
1131   PREFIX_VEX_0F42,
1132   PREFIX_VEX_0F44,
1133   PREFIX_VEX_0F45,
1134   PREFIX_VEX_0F46,
1135   PREFIX_VEX_0F47,
1136   PREFIX_VEX_0F4A,
1137   PREFIX_VEX_0F4B,
1138   PREFIX_VEX_0F51,
1139   PREFIX_VEX_0F52,
1140   PREFIX_VEX_0F53,
1141   PREFIX_VEX_0F58,
1142   PREFIX_VEX_0F59,
1143   PREFIX_VEX_0F5A,
1144   PREFIX_VEX_0F5B,
1145   PREFIX_VEX_0F5C,
1146   PREFIX_VEX_0F5D,
1147   PREFIX_VEX_0F5E,
1148   PREFIX_VEX_0F5F,
1149   PREFIX_VEX_0F60,
1150   PREFIX_VEX_0F61,
1151   PREFIX_VEX_0F62,
1152   PREFIX_VEX_0F63,
1153   PREFIX_VEX_0F64,
1154   PREFIX_VEX_0F65,
1155   PREFIX_VEX_0F66,
1156   PREFIX_VEX_0F67,
1157   PREFIX_VEX_0F68,
1158   PREFIX_VEX_0F69,
1159   PREFIX_VEX_0F6A,
1160   PREFIX_VEX_0F6B,
1161   PREFIX_VEX_0F6C,
1162   PREFIX_VEX_0F6D,
1163   PREFIX_VEX_0F6E,
1164   PREFIX_VEX_0F6F,
1165   PREFIX_VEX_0F70,
1166   PREFIX_VEX_0F71_REG_2,
1167   PREFIX_VEX_0F71_REG_4,
1168   PREFIX_VEX_0F71_REG_6,
1169   PREFIX_VEX_0F72_REG_2,
1170   PREFIX_VEX_0F72_REG_4,
1171   PREFIX_VEX_0F72_REG_6,
1172   PREFIX_VEX_0F73_REG_2,
1173   PREFIX_VEX_0F73_REG_3,
1174   PREFIX_VEX_0F73_REG_6,
1175   PREFIX_VEX_0F73_REG_7,
1176   PREFIX_VEX_0F74,
1177   PREFIX_VEX_0F75,
1178   PREFIX_VEX_0F76,
1179   PREFIX_VEX_0F77,
1180   PREFIX_VEX_0F7C,
1181   PREFIX_VEX_0F7D,
1182   PREFIX_VEX_0F7E,
1183   PREFIX_VEX_0F7F,
1184   PREFIX_VEX_0F90,
1185   PREFIX_VEX_0F91,
1186   PREFIX_VEX_0F92,
1187   PREFIX_VEX_0F93,
1188   PREFIX_VEX_0F98,
1189   PREFIX_VEX_0F99,
1190   PREFIX_VEX_0FC2,
1191   PREFIX_VEX_0FC4,
1192   PREFIX_VEX_0FC5,
1193   PREFIX_VEX_0FD0,
1194   PREFIX_VEX_0FD1,
1195   PREFIX_VEX_0FD2,
1196   PREFIX_VEX_0FD3,
1197   PREFIX_VEX_0FD4,
1198   PREFIX_VEX_0FD5,
1199   PREFIX_VEX_0FD6,
1200   PREFIX_VEX_0FD7,
1201   PREFIX_VEX_0FD8,
1202   PREFIX_VEX_0FD9,
1203   PREFIX_VEX_0FDA,
1204   PREFIX_VEX_0FDB,
1205   PREFIX_VEX_0FDC,
1206   PREFIX_VEX_0FDD,
1207   PREFIX_VEX_0FDE,
1208   PREFIX_VEX_0FDF,
1209   PREFIX_VEX_0FE0,
1210   PREFIX_VEX_0FE1,
1211   PREFIX_VEX_0FE2,
1212   PREFIX_VEX_0FE3,
1213   PREFIX_VEX_0FE4,
1214   PREFIX_VEX_0FE5,
1215   PREFIX_VEX_0FE6,
1216   PREFIX_VEX_0FE7,
1217   PREFIX_VEX_0FE8,
1218   PREFIX_VEX_0FE9,
1219   PREFIX_VEX_0FEA,
1220   PREFIX_VEX_0FEB,
1221   PREFIX_VEX_0FEC,
1222   PREFIX_VEX_0FED,
1223   PREFIX_VEX_0FEE,
1224   PREFIX_VEX_0FEF,
1225   PREFIX_VEX_0FF0,
1226   PREFIX_VEX_0FF1,
1227   PREFIX_VEX_0FF2,
1228   PREFIX_VEX_0FF3,
1229   PREFIX_VEX_0FF4,
1230   PREFIX_VEX_0FF5,
1231   PREFIX_VEX_0FF6,
1232   PREFIX_VEX_0FF7,
1233   PREFIX_VEX_0FF8,
1234   PREFIX_VEX_0FF9,
1235   PREFIX_VEX_0FFA,
1236   PREFIX_VEX_0FFB,
1237   PREFIX_VEX_0FFC,
1238   PREFIX_VEX_0FFD,
1239   PREFIX_VEX_0FFE,
1240   PREFIX_VEX_0F3800,
1241   PREFIX_VEX_0F3801,
1242   PREFIX_VEX_0F3802,
1243   PREFIX_VEX_0F3803,
1244   PREFIX_VEX_0F3804,
1245   PREFIX_VEX_0F3805,
1246   PREFIX_VEX_0F3806,
1247   PREFIX_VEX_0F3807,
1248   PREFIX_VEX_0F3808,
1249   PREFIX_VEX_0F3809,
1250   PREFIX_VEX_0F380A,
1251   PREFIX_VEX_0F380B,
1252   PREFIX_VEX_0F380C,
1253   PREFIX_VEX_0F380D,
1254   PREFIX_VEX_0F380E,
1255   PREFIX_VEX_0F380F,
1256   PREFIX_VEX_0F3813,
1257   PREFIX_VEX_0F3816,
1258   PREFIX_VEX_0F3817,
1259   PREFIX_VEX_0F3818,
1260   PREFIX_VEX_0F3819,
1261   PREFIX_VEX_0F381A,
1262   PREFIX_VEX_0F381C,
1263   PREFIX_VEX_0F381D,
1264   PREFIX_VEX_0F381E,
1265   PREFIX_VEX_0F3820,
1266   PREFIX_VEX_0F3821,
1267   PREFIX_VEX_0F3822,
1268   PREFIX_VEX_0F3823,
1269   PREFIX_VEX_0F3824,
1270   PREFIX_VEX_0F3825,
1271   PREFIX_VEX_0F3828,
1272   PREFIX_VEX_0F3829,
1273   PREFIX_VEX_0F382A,
1274   PREFIX_VEX_0F382B,
1275   PREFIX_VEX_0F382C,
1276   PREFIX_VEX_0F382D,
1277   PREFIX_VEX_0F382E,
1278   PREFIX_VEX_0F382F,
1279   PREFIX_VEX_0F3830,
1280   PREFIX_VEX_0F3831,
1281   PREFIX_VEX_0F3832,
1282   PREFIX_VEX_0F3833,
1283   PREFIX_VEX_0F3834,
1284   PREFIX_VEX_0F3835,
1285   PREFIX_VEX_0F3836,
1286   PREFIX_VEX_0F3837,
1287   PREFIX_VEX_0F3838,
1288   PREFIX_VEX_0F3839,
1289   PREFIX_VEX_0F383A,
1290   PREFIX_VEX_0F383B,
1291   PREFIX_VEX_0F383C,
1292   PREFIX_VEX_0F383D,
1293   PREFIX_VEX_0F383E,
1294   PREFIX_VEX_0F383F,
1295   PREFIX_VEX_0F3840,
1296   PREFIX_VEX_0F3841,
1297   PREFIX_VEX_0F3845,
1298   PREFIX_VEX_0F3846,
1299   PREFIX_VEX_0F3847,
1300   PREFIX_VEX_0F3858,
1301   PREFIX_VEX_0F3859,
1302   PREFIX_VEX_0F385A,
1303   PREFIX_VEX_0F3878,
1304   PREFIX_VEX_0F3879,
1305   PREFIX_VEX_0F388C,
1306   PREFIX_VEX_0F388E,
1307   PREFIX_VEX_0F3890,
1308   PREFIX_VEX_0F3891,
1309   PREFIX_VEX_0F3892,
1310   PREFIX_VEX_0F3893,
1311   PREFIX_VEX_0F3896,
1312   PREFIX_VEX_0F3897,
1313   PREFIX_VEX_0F3898,
1314   PREFIX_VEX_0F3899,
1315   PREFIX_VEX_0F389A,
1316   PREFIX_VEX_0F389B,
1317   PREFIX_VEX_0F389C,
1318   PREFIX_VEX_0F389D,
1319   PREFIX_VEX_0F389E,
1320   PREFIX_VEX_0F389F,
1321   PREFIX_VEX_0F38A6,
1322   PREFIX_VEX_0F38A7,
1323   PREFIX_VEX_0F38A8,
1324   PREFIX_VEX_0F38A9,
1325   PREFIX_VEX_0F38AA,
1326   PREFIX_VEX_0F38AB,
1327   PREFIX_VEX_0F38AC,
1328   PREFIX_VEX_0F38AD,
1329   PREFIX_VEX_0F38AE,
1330   PREFIX_VEX_0F38AF,
1331   PREFIX_VEX_0F38B6,
1332   PREFIX_VEX_0F38B7,
1333   PREFIX_VEX_0F38B8,
1334   PREFIX_VEX_0F38B9,
1335   PREFIX_VEX_0F38BA,
1336   PREFIX_VEX_0F38BB,
1337   PREFIX_VEX_0F38BC,
1338   PREFIX_VEX_0F38BD,
1339   PREFIX_VEX_0F38BE,
1340   PREFIX_VEX_0F38BF,
1341   PREFIX_VEX_0F38CF,
1342   PREFIX_VEX_0F38DB,
1343   PREFIX_VEX_0F38DC,
1344   PREFIX_VEX_0F38DD,
1345   PREFIX_VEX_0F38DE,
1346   PREFIX_VEX_0F38DF,
1347   PREFIX_VEX_0F38F2,
1348   PREFIX_VEX_0F38F3_REG_1,
1349   PREFIX_VEX_0F38F3_REG_2,
1350   PREFIX_VEX_0F38F3_REG_3,
1351   PREFIX_VEX_0F38F5,
1352   PREFIX_VEX_0F38F6,
1353   PREFIX_VEX_0F38F7,
1354   PREFIX_VEX_0F3A00,
1355   PREFIX_VEX_0F3A01,
1356   PREFIX_VEX_0F3A02,
1357   PREFIX_VEX_0F3A04,
1358   PREFIX_VEX_0F3A05,
1359   PREFIX_VEX_0F3A06,
1360   PREFIX_VEX_0F3A08,
1361   PREFIX_VEX_0F3A09,
1362   PREFIX_VEX_0F3A0A,
1363   PREFIX_VEX_0F3A0B,
1364   PREFIX_VEX_0F3A0C,
1365   PREFIX_VEX_0F3A0D,
1366   PREFIX_VEX_0F3A0E,
1367   PREFIX_VEX_0F3A0F,
1368   PREFIX_VEX_0F3A14,
1369   PREFIX_VEX_0F3A15,
1370   PREFIX_VEX_0F3A16,
1371   PREFIX_VEX_0F3A17,
1372   PREFIX_VEX_0F3A18,
1373   PREFIX_VEX_0F3A19,
1374   PREFIX_VEX_0F3A1D,
1375   PREFIX_VEX_0F3A20,
1376   PREFIX_VEX_0F3A21,
1377   PREFIX_VEX_0F3A22,
1378   PREFIX_VEX_0F3A30,
1379   PREFIX_VEX_0F3A31,
1380   PREFIX_VEX_0F3A32,
1381   PREFIX_VEX_0F3A33,
1382   PREFIX_VEX_0F3A38,
1383   PREFIX_VEX_0F3A39,
1384   PREFIX_VEX_0F3A40,
1385   PREFIX_VEX_0F3A41,
1386   PREFIX_VEX_0F3A42,
1387   PREFIX_VEX_0F3A44,
1388   PREFIX_VEX_0F3A46,
1389   PREFIX_VEX_0F3A48,
1390   PREFIX_VEX_0F3A49,
1391   PREFIX_VEX_0F3A4A,
1392   PREFIX_VEX_0F3A4B,
1393   PREFIX_VEX_0F3A4C,
1394   PREFIX_VEX_0F3A5C,
1395   PREFIX_VEX_0F3A5D,
1396   PREFIX_VEX_0F3A5E,
1397   PREFIX_VEX_0F3A5F,
1398   PREFIX_VEX_0F3A60,
1399   PREFIX_VEX_0F3A61,
1400   PREFIX_VEX_0F3A62,
1401   PREFIX_VEX_0F3A63,
1402   PREFIX_VEX_0F3A68,
1403   PREFIX_VEX_0F3A69,
1404   PREFIX_VEX_0F3A6A,
1405   PREFIX_VEX_0F3A6B,
1406   PREFIX_VEX_0F3A6C,
1407   PREFIX_VEX_0F3A6D,
1408   PREFIX_VEX_0F3A6E,
1409   PREFIX_VEX_0F3A6F,
1410   PREFIX_VEX_0F3A78,
1411   PREFIX_VEX_0F3A79,
1412   PREFIX_VEX_0F3A7A,
1413   PREFIX_VEX_0F3A7B,
1414   PREFIX_VEX_0F3A7C,
1415   PREFIX_VEX_0F3A7D,
1416   PREFIX_VEX_0F3A7E,
1417   PREFIX_VEX_0F3A7F,
1418   PREFIX_VEX_0F3ACE,
1419   PREFIX_VEX_0F3ACF,
1420   PREFIX_VEX_0F3ADF,
1421   PREFIX_VEX_0F3AF0,
1422
1423   PREFIX_EVEX_0F10,
1424   PREFIX_EVEX_0F11,
1425   PREFIX_EVEX_0F12,
1426   PREFIX_EVEX_0F13,
1427   PREFIX_EVEX_0F14,
1428   PREFIX_EVEX_0F15,
1429   PREFIX_EVEX_0F16,
1430   PREFIX_EVEX_0F17,
1431   PREFIX_EVEX_0F28,
1432   PREFIX_EVEX_0F29,
1433   PREFIX_EVEX_0F2A,
1434   PREFIX_EVEX_0F2B,
1435   PREFIX_EVEX_0F2C,
1436   PREFIX_EVEX_0F2D,
1437   PREFIX_EVEX_0F2E,
1438   PREFIX_EVEX_0F2F,
1439   PREFIX_EVEX_0F51,
1440   PREFIX_EVEX_0F54,
1441   PREFIX_EVEX_0F55,
1442   PREFIX_EVEX_0F56,
1443   PREFIX_EVEX_0F57,
1444   PREFIX_EVEX_0F58,
1445   PREFIX_EVEX_0F59,
1446   PREFIX_EVEX_0F5A,
1447   PREFIX_EVEX_0F5B,
1448   PREFIX_EVEX_0F5C,
1449   PREFIX_EVEX_0F5D,
1450   PREFIX_EVEX_0F5E,
1451   PREFIX_EVEX_0F5F,
1452   PREFIX_EVEX_0F60,
1453   PREFIX_EVEX_0F61,
1454   PREFIX_EVEX_0F62,
1455   PREFIX_EVEX_0F63,
1456   PREFIX_EVEX_0F64,
1457   PREFIX_EVEX_0F65,
1458   PREFIX_EVEX_0F66,
1459   PREFIX_EVEX_0F67,
1460   PREFIX_EVEX_0F68,
1461   PREFIX_EVEX_0F69,
1462   PREFIX_EVEX_0F6A,
1463   PREFIX_EVEX_0F6B,
1464   PREFIX_EVEX_0F6C,
1465   PREFIX_EVEX_0F6D,
1466   PREFIX_EVEX_0F6E,
1467   PREFIX_EVEX_0F6F,
1468   PREFIX_EVEX_0F70,
1469   PREFIX_EVEX_0F71_REG_2,
1470   PREFIX_EVEX_0F71_REG_4,
1471   PREFIX_EVEX_0F71_REG_6,
1472   PREFIX_EVEX_0F72_REG_0,
1473   PREFIX_EVEX_0F72_REG_1,
1474   PREFIX_EVEX_0F72_REG_2,
1475   PREFIX_EVEX_0F72_REG_4,
1476   PREFIX_EVEX_0F72_REG_6,
1477   PREFIX_EVEX_0F73_REG_2,
1478   PREFIX_EVEX_0F73_REG_3,
1479   PREFIX_EVEX_0F73_REG_6,
1480   PREFIX_EVEX_0F73_REG_7,
1481   PREFIX_EVEX_0F74,
1482   PREFIX_EVEX_0F75,
1483   PREFIX_EVEX_0F76,
1484   PREFIX_EVEX_0F78,
1485   PREFIX_EVEX_0F79,
1486   PREFIX_EVEX_0F7A,
1487   PREFIX_EVEX_0F7B,
1488   PREFIX_EVEX_0F7E,
1489   PREFIX_EVEX_0F7F,
1490   PREFIX_EVEX_0FC2,
1491   PREFIX_EVEX_0FC4,
1492   PREFIX_EVEX_0FC5,
1493   PREFIX_EVEX_0FC6,
1494   PREFIX_EVEX_0FD1,
1495   PREFIX_EVEX_0FD2,
1496   PREFIX_EVEX_0FD3,
1497   PREFIX_EVEX_0FD4,
1498   PREFIX_EVEX_0FD5,
1499   PREFIX_EVEX_0FD6,
1500   PREFIX_EVEX_0FD8,
1501   PREFIX_EVEX_0FD9,
1502   PREFIX_EVEX_0FDA,
1503   PREFIX_EVEX_0FDB,
1504   PREFIX_EVEX_0FDC,
1505   PREFIX_EVEX_0FDD,
1506   PREFIX_EVEX_0FDE,
1507   PREFIX_EVEX_0FDF,
1508   PREFIX_EVEX_0FE0,
1509   PREFIX_EVEX_0FE1,
1510   PREFIX_EVEX_0FE2,
1511   PREFIX_EVEX_0FE3,
1512   PREFIX_EVEX_0FE4,
1513   PREFIX_EVEX_0FE5,
1514   PREFIX_EVEX_0FE6,
1515   PREFIX_EVEX_0FE7,
1516   PREFIX_EVEX_0FE8,
1517   PREFIX_EVEX_0FE9,
1518   PREFIX_EVEX_0FEA,
1519   PREFIX_EVEX_0FEB,
1520   PREFIX_EVEX_0FEC,
1521   PREFIX_EVEX_0FED,
1522   PREFIX_EVEX_0FEE,
1523   PREFIX_EVEX_0FEF,
1524   PREFIX_EVEX_0FF1,
1525   PREFIX_EVEX_0FF2,
1526   PREFIX_EVEX_0FF3,
1527   PREFIX_EVEX_0FF4,
1528   PREFIX_EVEX_0FF5,
1529   PREFIX_EVEX_0FF6,
1530   PREFIX_EVEX_0FF8,
1531   PREFIX_EVEX_0FF9,
1532   PREFIX_EVEX_0FFA,
1533   PREFIX_EVEX_0FFB,
1534   PREFIX_EVEX_0FFC,
1535   PREFIX_EVEX_0FFD,
1536   PREFIX_EVEX_0FFE,
1537   PREFIX_EVEX_0F3800,
1538   PREFIX_EVEX_0F3804,
1539   PREFIX_EVEX_0F380B,
1540   PREFIX_EVEX_0F380C,
1541   PREFIX_EVEX_0F380D,
1542   PREFIX_EVEX_0F3810,
1543   PREFIX_EVEX_0F3811,
1544   PREFIX_EVEX_0F3812,
1545   PREFIX_EVEX_0F3813,
1546   PREFIX_EVEX_0F3814,
1547   PREFIX_EVEX_0F3815,
1548   PREFIX_EVEX_0F3816,
1549   PREFIX_EVEX_0F3818,
1550   PREFIX_EVEX_0F3819,
1551   PREFIX_EVEX_0F381A,
1552   PREFIX_EVEX_0F381B,
1553   PREFIX_EVEX_0F381C,
1554   PREFIX_EVEX_0F381D,
1555   PREFIX_EVEX_0F381E,
1556   PREFIX_EVEX_0F381F,
1557   PREFIX_EVEX_0F3820,
1558   PREFIX_EVEX_0F3821,
1559   PREFIX_EVEX_0F3822,
1560   PREFIX_EVEX_0F3823,
1561   PREFIX_EVEX_0F3824,
1562   PREFIX_EVEX_0F3825,
1563   PREFIX_EVEX_0F3826,
1564   PREFIX_EVEX_0F3827,
1565   PREFIX_EVEX_0F3828,
1566   PREFIX_EVEX_0F3829,
1567   PREFIX_EVEX_0F382A,
1568   PREFIX_EVEX_0F382B,
1569   PREFIX_EVEX_0F382C,
1570   PREFIX_EVEX_0F382D,
1571   PREFIX_EVEX_0F3830,
1572   PREFIX_EVEX_0F3831,
1573   PREFIX_EVEX_0F3832,
1574   PREFIX_EVEX_0F3833,
1575   PREFIX_EVEX_0F3834,
1576   PREFIX_EVEX_0F3835,
1577   PREFIX_EVEX_0F3836,
1578   PREFIX_EVEX_0F3837,
1579   PREFIX_EVEX_0F3838,
1580   PREFIX_EVEX_0F3839,
1581   PREFIX_EVEX_0F383A,
1582   PREFIX_EVEX_0F383B,
1583   PREFIX_EVEX_0F383C,
1584   PREFIX_EVEX_0F383D,
1585   PREFIX_EVEX_0F383E,
1586   PREFIX_EVEX_0F383F,
1587   PREFIX_EVEX_0F3840,
1588   PREFIX_EVEX_0F3842,
1589   PREFIX_EVEX_0F3843,
1590   PREFIX_EVEX_0F3844,
1591   PREFIX_EVEX_0F3845,
1592   PREFIX_EVEX_0F3846,
1593   PREFIX_EVEX_0F3847,
1594   PREFIX_EVEX_0F384C,
1595   PREFIX_EVEX_0F384D,
1596   PREFIX_EVEX_0F384E,
1597   PREFIX_EVEX_0F384F,
1598   PREFIX_EVEX_0F3850,
1599   PREFIX_EVEX_0F3851,
1600   PREFIX_EVEX_0F3852,
1601   PREFIX_EVEX_0F3853,
1602   PREFIX_EVEX_0F3854,
1603   PREFIX_EVEX_0F3855,
1604   PREFIX_EVEX_0F3858,
1605   PREFIX_EVEX_0F3859,
1606   PREFIX_EVEX_0F385A,
1607   PREFIX_EVEX_0F385B,
1608   PREFIX_EVEX_0F3862,
1609   PREFIX_EVEX_0F3863,
1610   PREFIX_EVEX_0F3864,
1611   PREFIX_EVEX_0F3865,
1612   PREFIX_EVEX_0F3866,
1613   PREFIX_EVEX_0F3868,
1614   PREFIX_EVEX_0F3870,
1615   PREFIX_EVEX_0F3871,
1616   PREFIX_EVEX_0F3872,
1617   PREFIX_EVEX_0F3873,
1618   PREFIX_EVEX_0F3875,
1619   PREFIX_EVEX_0F3876,
1620   PREFIX_EVEX_0F3877,
1621   PREFIX_EVEX_0F3878,
1622   PREFIX_EVEX_0F3879,
1623   PREFIX_EVEX_0F387A,
1624   PREFIX_EVEX_0F387B,
1625   PREFIX_EVEX_0F387C,
1626   PREFIX_EVEX_0F387D,
1627   PREFIX_EVEX_0F387E,
1628   PREFIX_EVEX_0F387F,
1629   PREFIX_EVEX_0F3883,
1630   PREFIX_EVEX_0F3888,
1631   PREFIX_EVEX_0F3889,
1632   PREFIX_EVEX_0F388A,
1633   PREFIX_EVEX_0F388B,
1634   PREFIX_EVEX_0F388D,
1635   PREFIX_EVEX_0F388F,
1636   PREFIX_EVEX_0F3890,
1637   PREFIX_EVEX_0F3891,
1638   PREFIX_EVEX_0F3892,
1639   PREFIX_EVEX_0F3893,
1640   PREFIX_EVEX_0F3896,
1641   PREFIX_EVEX_0F3897,
1642   PREFIX_EVEX_0F3898,
1643   PREFIX_EVEX_0F3899,
1644   PREFIX_EVEX_0F389A,
1645   PREFIX_EVEX_0F389B,
1646   PREFIX_EVEX_0F389C,
1647   PREFIX_EVEX_0F389D,
1648   PREFIX_EVEX_0F389E,
1649   PREFIX_EVEX_0F389F,
1650   PREFIX_EVEX_0F38A0,
1651   PREFIX_EVEX_0F38A1,
1652   PREFIX_EVEX_0F38A2,
1653   PREFIX_EVEX_0F38A3,
1654   PREFIX_EVEX_0F38A6,
1655   PREFIX_EVEX_0F38A7,
1656   PREFIX_EVEX_0F38A8,
1657   PREFIX_EVEX_0F38A9,
1658   PREFIX_EVEX_0F38AA,
1659   PREFIX_EVEX_0F38AB,
1660   PREFIX_EVEX_0F38AC,
1661   PREFIX_EVEX_0F38AD,
1662   PREFIX_EVEX_0F38AE,
1663   PREFIX_EVEX_0F38AF,
1664   PREFIX_EVEX_0F38B4,
1665   PREFIX_EVEX_0F38B5,
1666   PREFIX_EVEX_0F38B6,
1667   PREFIX_EVEX_0F38B7,
1668   PREFIX_EVEX_0F38B8,
1669   PREFIX_EVEX_0F38B9,
1670   PREFIX_EVEX_0F38BA,
1671   PREFIX_EVEX_0F38BB,
1672   PREFIX_EVEX_0F38BC,
1673   PREFIX_EVEX_0F38BD,
1674   PREFIX_EVEX_0F38BE,
1675   PREFIX_EVEX_0F38BF,
1676   PREFIX_EVEX_0F38C4,
1677   PREFIX_EVEX_0F38C6_REG_1,
1678   PREFIX_EVEX_0F38C6_REG_2,
1679   PREFIX_EVEX_0F38C6_REG_5,
1680   PREFIX_EVEX_0F38C6_REG_6,
1681   PREFIX_EVEX_0F38C7_REG_1,
1682   PREFIX_EVEX_0F38C7_REG_2,
1683   PREFIX_EVEX_0F38C7_REG_5,
1684   PREFIX_EVEX_0F38C7_REG_6,
1685   PREFIX_EVEX_0F38C8,
1686   PREFIX_EVEX_0F38CA,
1687   PREFIX_EVEX_0F38CB,
1688   PREFIX_EVEX_0F38CC,
1689   PREFIX_EVEX_0F38CD,
1690   PREFIX_EVEX_0F38CF,
1691   PREFIX_EVEX_0F38DC,
1692   PREFIX_EVEX_0F38DD,
1693   PREFIX_EVEX_0F38DE,
1694   PREFIX_EVEX_0F38DF,
1695
1696   PREFIX_EVEX_0F3A00,
1697   PREFIX_EVEX_0F3A01,
1698   PREFIX_EVEX_0F3A03,
1699   PREFIX_EVEX_0F3A04,
1700   PREFIX_EVEX_0F3A05,
1701   PREFIX_EVEX_0F3A08,
1702   PREFIX_EVEX_0F3A09,
1703   PREFIX_EVEX_0F3A0A,
1704   PREFIX_EVEX_0F3A0B,
1705   PREFIX_EVEX_0F3A0F,
1706   PREFIX_EVEX_0F3A14,
1707   PREFIX_EVEX_0F3A15,
1708   PREFIX_EVEX_0F3A16,
1709   PREFIX_EVEX_0F3A17,
1710   PREFIX_EVEX_0F3A18,
1711   PREFIX_EVEX_0F3A19,
1712   PREFIX_EVEX_0F3A1A,
1713   PREFIX_EVEX_0F3A1B,
1714   PREFIX_EVEX_0F3A1D,
1715   PREFIX_EVEX_0F3A1E,
1716   PREFIX_EVEX_0F3A1F,
1717   PREFIX_EVEX_0F3A20,
1718   PREFIX_EVEX_0F3A21,
1719   PREFIX_EVEX_0F3A22,
1720   PREFIX_EVEX_0F3A23,
1721   PREFIX_EVEX_0F3A25,
1722   PREFIX_EVEX_0F3A26,
1723   PREFIX_EVEX_0F3A27,
1724   PREFIX_EVEX_0F3A38,
1725   PREFIX_EVEX_0F3A39,
1726   PREFIX_EVEX_0F3A3A,
1727   PREFIX_EVEX_0F3A3B,
1728   PREFIX_EVEX_0F3A3E,
1729   PREFIX_EVEX_0F3A3F,
1730   PREFIX_EVEX_0F3A42,
1731   PREFIX_EVEX_0F3A43,
1732   PREFIX_EVEX_0F3A44,
1733   PREFIX_EVEX_0F3A50,
1734   PREFIX_EVEX_0F3A51,
1735   PREFIX_EVEX_0F3A54,
1736   PREFIX_EVEX_0F3A55,
1737   PREFIX_EVEX_0F3A56,
1738   PREFIX_EVEX_0F3A57,
1739   PREFIX_EVEX_0F3A66,
1740   PREFIX_EVEX_0F3A67,
1741   PREFIX_EVEX_0F3A70,
1742   PREFIX_EVEX_0F3A71,
1743   PREFIX_EVEX_0F3A72,
1744   PREFIX_EVEX_0F3A73,
1745   PREFIX_EVEX_0F3ACE,
1746   PREFIX_EVEX_0F3ACF
1747 };
1748
1749 enum
1750 {
1751   X86_64_06 = 0,
1752   X86_64_07,
1753   X86_64_0D,
1754   X86_64_16,
1755   X86_64_17,
1756   X86_64_1E,
1757   X86_64_1F,
1758   X86_64_27,
1759   X86_64_2F,
1760   X86_64_37,
1761   X86_64_3F,
1762   X86_64_60,
1763   X86_64_61,
1764   X86_64_62,
1765   X86_64_63,
1766   X86_64_6D,
1767   X86_64_6F,
1768   X86_64_82,
1769   X86_64_9A,
1770   X86_64_C4,
1771   X86_64_C5,
1772   X86_64_CE,
1773   X86_64_D4,
1774   X86_64_D5,
1775   X86_64_E8,
1776   X86_64_E9,
1777   X86_64_EA,
1778   X86_64_0F01_REG_0,
1779   X86_64_0F01_REG_1,
1780   X86_64_0F01_REG_2,
1781   X86_64_0F01_REG_3
1782 };
1783
1784 enum
1785 {
1786   THREE_BYTE_0F38 = 0,
1787   THREE_BYTE_0F3A
1788 };
1789
1790 enum
1791 {
1792   XOP_08 = 0,
1793   XOP_09,
1794   XOP_0A
1795 };
1796
1797 enum
1798 {
1799   VEX_0F = 0,
1800   VEX_0F38,
1801   VEX_0F3A
1802 };
1803
1804 enum
1805 {
1806   EVEX_0F = 0,
1807   EVEX_0F38,
1808   EVEX_0F3A
1809 };
1810
1811 enum
1812 {
1813   VEX_LEN_0F12_P_0_M_0 = 0,
1814   VEX_LEN_0F12_P_0_M_1,
1815   VEX_LEN_0F12_P_2,
1816   VEX_LEN_0F13_M_0,
1817   VEX_LEN_0F16_P_0_M_0,
1818   VEX_LEN_0F16_P_0_M_1,
1819   VEX_LEN_0F16_P_2,
1820   VEX_LEN_0F17_M_0,
1821   VEX_LEN_0F41_P_0,
1822   VEX_LEN_0F41_P_2,
1823   VEX_LEN_0F42_P_0,
1824   VEX_LEN_0F42_P_2,
1825   VEX_LEN_0F44_P_0,
1826   VEX_LEN_0F44_P_2,
1827   VEX_LEN_0F45_P_0,
1828   VEX_LEN_0F45_P_2,
1829   VEX_LEN_0F46_P_0,
1830   VEX_LEN_0F46_P_2,
1831   VEX_LEN_0F47_P_0,
1832   VEX_LEN_0F47_P_2,
1833   VEX_LEN_0F4A_P_0,
1834   VEX_LEN_0F4A_P_2,
1835   VEX_LEN_0F4B_P_0,
1836   VEX_LEN_0F4B_P_2,
1837   VEX_LEN_0F6E_P_2,
1838   VEX_LEN_0F77_P_0,
1839   VEX_LEN_0F7E_P_1,
1840   VEX_LEN_0F7E_P_2,
1841   VEX_LEN_0F90_P_0,
1842   VEX_LEN_0F90_P_2,
1843   VEX_LEN_0F91_P_0,
1844   VEX_LEN_0F91_P_2,
1845   VEX_LEN_0F92_P_0,
1846   VEX_LEN_0F92_P_2,
1847   VEX_LEN_0F92_P_3,
1848   VEX_LEN_0F93_P_0,
1849   VEX_LEN_0F93_P_2,
1850   VEX_LEN_0F93_P_3,
1851   VEX_LEN_0F98_P_0,
1852   VEX_LEN_0F98_P_2,
1853   VEX_LEN_0F99_P_0,
1854   VEX_LEN_0F99_P_2,
1855   VEX_LEN_0FAE_R_2_M_0,
1856   VEX_LEN_0FAE_R_3_M_0,
1857   VEX_LEN_0FC4_P_2,
1858   VEX_LEN_0FC5_P_2,
1859   VEX_LEN_0FD6_P_2,
1860   VEX_LEN_0FF7_P_2,
1861   VEX_LEN_0F3816_P_2,
1862   VEX_LEN_0F3819_P_2,
1863   VEX_LEN_0F381A_P_2_M_0,
1864   VEX_LEN_0F3836_P_2,
1865   VEX_LEN_0F3841_P_2,
1866   VEX_LEN_0F385A_P_2_M_0,
1867   VEX_LEN_0F38DB_P_2,
1868   VEX_LEN_0F38F2_P_0,
1869   VEX_LEN_0F38F3_R_1_P_0,
1870   VEX_LEN_0F38F3_R_2_P_0,
1871   VEX_LEN_0F38F3_R_3_P_0,
1872   VEX_LEN_0F38F5_P_0,
1873   VEX_LEN_0F38F5_P_1,
1874   VEX_LEN_0F38F5_P_3,
1875   VEX_LEN_0F38F6_P_3,
1876   VEX_LEN_0F38F7_P_0,
1877   VEX_LEN_0F38F7_P_1,
1878   VEX_LEN_0F38F7_P_2,
1879   VEX_LEN_0F38F7_P_3,
1880   VEX_LEN_0F3A00_P_2,
1881   VEX_LEN_0F3A01_P_2,
1882   VEX_LEN_0F3A06_P_2,
1883   VEX_LEN_0F3A14_P_2,
1884   VEX_LEN_0F3A15_P_2,
1885   VEX_LEN_0F3A16_P_2,
1886   VEX_LEN_0F3A17_P_2,
1887   VEX_LEN_0F3A18_P_2,
1888   VEX_LEN_0F3A19_P_2,
1889   VEX_LEN_0F3A20_P_2,
1890   VEX_LEN_0F3A21_P_2,
1891   VEX_LEN_0F3A22_P_2,
1892   VEX_LEN_0F3A30_P_2,
1893   VEX_LEN_0F3A31_P_2,
1894   VEX_LEN_0F3A32_P_2,
1895   VEX_LEN_0F3A33_P_2,
1896   VEX_LEN_0F3A38_P_2,
1897   VEX_LEN_0F3A39_P_2,
1898   VEX_LEN_0F3A41_P_2,
1899   VEX_LEN_0F3A46_P_2,
1900   VEX_LEN_0F3A60_P_2,
1901   VEX_LEN_0F3A61_P_2,
1902   VEX_LEN_0F3A62_P_2,
1903   VEX_LEN_0F3A63_P_2,
1904   VEX_LEN_0F3A6A_P_2,
1905   VEX_LEN_0F3A6B_P_2,
1906   VEX_LEN_0F3A6E_P_2,
1907   VEX_LEN_0F3A6F_P_2,
1908   VEX_LEN_0F3A7A_P_2,
1909   VEX_LEN_0F3A7B_P_2,
1910   VEX_LEN_0F3A7E_P_2,
1911   VEX_LEN_0F3A7F_P_2,
1912   VEX_LEN_0F3ADF_P_2,
1913   VEX_LEN_0F3AF0_P_3,
1914   VEX_LEN_0FXOP_08_CC,
1915   VEX_LEN_0FXOP_08_CD,
1916   VEX_LEN_0FXOP_08_CE,
1917   VEX_LEN_0FXOP_08_CF,
1918   VEX_LEN_0FXOP_08_EC,
1919   VEX_LEN_0FXOP_08_ED,
1920   VEX_LEN_0FXOP_08_EE,
1921   VEX_LEN_0FXOP_08_EF,
1922   VEX_LEN_0FXOP_09_80,
1923   VEX_LEN_0FXOP_09_81
1924 };
1925
1926 enum
1927 {
1928   EVEX_LEN_0F6E_P_2 = 0,
1929   EVEX_LEN_0F7E_P_1,
1930   EVEX_LEN_0F7E_P_2,
1931   EVEX_LEN_0FD6_P_2,
1932   EVEX_LEN_0F3819_P_2_W_0,
1933   EVEX_LEN_0F3819_P_2_W_1,
1934   EVEX_LEN_0F381A_P_2_W_0,
1935   EVEX_LEN_0F381A_P_2_W_1,
1936   EVEX_LEN_0F381B_P_2_W_0,
1937   EVEX_LEN_0F381B_P_2_W_1,
1938   EVEX_LEN_0F385A_P_2_W_0,
1939   EVEX_LEN_0F385A_P_2_W_1,
1940   EVEX_LEN_0F385B_P_2_W_0,
1941   EVEX_LEN_0F385B_P_2_W_1,
1942   EVEX_LEN_0F3A18_P_2_W_0,
1943   EVEX_LEN_0F3A18_P_2_W_1,
1944   EVEX_LEN_0F3A19_P_2_W_0,
1945   EVEX_LEN_0F3A19_P_2_W_1,
1946   EVEX_LEN_0F3A1A_P_2_W_0,
1947   EVEX_LEN_0F3A1A_P_2_W_1,
1948   EVEX_LEN_0F3A1B_P_2_W_0,
1949   EVEX_LEN_0F3A1B_P_2_W_1,
1950   EVEX_LEN_0F3A23_P_2_W_0,
1951   EVEX_LEN_0F3A23_P_2_W_1,
1952   EVEX_LEN_0F3A38_P_2_W_0,
1953   EVEX_LEN_0F3A38_P_2_W_1,
1954   EVEX_LEN_0F3A39_P_2_W_0,
1955   EVEX_LEN_0F3A39_P_2_W_1,
1956   EVEX_LEN_0F3A3A_P_2_W_0,
1957   EVEX_LEN_0F3A3A_P_2_W_1,
1958   EVEX_LEN_0F3A3B_P_2_W_0,
1959   EVEX_LEN_0F3A3B_P_2_W_1,
1960   EVEX_LEN_0F3A43_P_2_W_0,
1961   EVEX_LEN_0F3A43_P_2_W_1
1962 };
1963
1964 enum
1965 {
1966   VEX_W_0F41_P_0_LEN_1 = 0,
1967   VEX_W_0F41_P_2_LEN_1,
1968   VEX_W_0F42_P_0_LEN_1,
1969   VEX_W_0F42_P_2_LEN_1,
1970   VEX_W_0F44_P_0_LEN_0,
1971   VEX_W_0F44_P_2_LEN_0,
1972   VEX_W_0F45_P_0_LEN_1,
1973   VEX_W_0F45_P_2_LEN_1,
1974   VEX_W_0F46_P_0_LEN_1,
1975   VEX_W_0F46_P_2_LEN_1,
1976   VEX_W_0F47_P_0_LEN_1,
1977   VEX_W_0F47_P_2_LEN_1,
1978   VEX_W_0F4A_P_0_LEN_1,
1979   VEX_W_0F4A_P_2_LEN_1,
1980   VEX_W_0F4B_P_0_LEN_1,
1981   VEX_W_0F4B_P_2_LEN_1,
1982   VEX_W_0F90_P_0_LEN_0,
1983   VEX_W_0F90_P_2_LEN_0,
1984   VEX_W_0F91_P_0_LEN_0,
1985   VEX_W_0F91_P_2_LEN_0,
1986   VEX_W_0F92_P_0_LEN_0,
1987   VEX_W_0F92_P_2_LEN_0,
1988   VEX_W_0F93_P_0_LEN_0,
1989   VEX_W_0F93_P_2_LEN_0,
1990   VEX_W_0F98_P_0_LEN_0,
1991   VEX_W_0F98_P_2_LEN_0,
1992   VEX_W_0F99_P_0_LEN_0,
1993   VEX_W_0F99_P_2_LEN_0,
1994   VEX_W_0F380C_P_2,
1995   VEX_W_0F380D_P_2,
1996   VEX_W_0F380E_P_2,
1997   VEX_W_0F380F_P_2,
1998   VEX_W_0F3816_P_2,
1999   VEX_W_0F3818_P_2,
2000   VEX_W_0F3819_P_2,
2001   VEX_W_0F381A_P_2_M_0,
2002   VEX_W_0F382C_P_2_M_0,
2003   VEX_W_0F382D_P_2_M_0,
2004   VEX_W_0F382E_P_2_M_0,
2005   VEX_W_0F382F_P_2_M_0,
2006   VEX_W_0F3836_P_2,
2007   VEX_W_0F3846_P_2,
2008   VEX_W_0F3858_P_2,
2009   VEX_W_0F3859_P_2,
2010   VEX_W_0F385A_P_2_M_0,
2011   VEX_W_0F3878_P_2,
2012   VEX_W_0F3879_P_2,
2013   VEX_W_0F38CF_P_2,
2014   VEX_W_0F3A00_P_2,
2015   VEX_W_0F3A01_P_2,
2016   VEX_W_0F3A02_P_2,
2017   VEX_W_0F3A04_P_2,
2018   VEX_W_0F3A05_P_2,
2019   VEX_W_0F3A06_P_2,
2020   VEX_W_0F3A18_P_2,
2021   VEX_W_0F3A19_P_2,
2022   VEX_W_0F3A30_P_2_LEN_0,
2023   VEX_W_0F3A31_P_2_LEN_0,
2024   VEX_W_0F3A32_P_2_LEN_0,
2025   VEX_W_0F3A33_P_2_LEN_0,
2026   VEX_W_0F3A38_P_2,
2027   VEX_W_0F3A39_P_2,
2028   VEX_W_0F3A46_P_2,
2029   VEX_W_0F3A48_P_2,
2030   VEX_W_0F3A49_P_2,
2031   VEX_W_0F3A4A_P_2,
2032   VEX_W_0F3A4B_P_2,
2033   VEX_W_0F3A4C_P_2,
2034   VEX_W_0F3ACE_P_2,
2035   VEX_W_0F3ACF_P_2,
2036
2037   EVEX_W_0F10_P_0,
2038   EVEX_W_0F10_P_1_M_0,
2039   EVEX_W_0F10_P_1_M_1,
2040   EVEX_W_0F10_P_2,
2041   EVEX_W_0F10_P_3_M_0,
2042   EVEX_W_0F10_P_3_M_1,
2043   EVEX_W_0F11_P_0,
2044   EVEX_W_0F11_P_1_M_0,
2045   EVEX_W_0F11_P_1_M_1,
2046   EVEX_W_0F11_P_2,
2047   EVEX_W_0F11_P_3_M_0,
2048   EVEX_W_0F11_P_3_M_1,
2049   EVEX_W_0F12_P_0_M_0,
2050   EVEX_W_0F12_P_0_M_1,
2051   EVEX_W_0F12_P_1,
2052   EVEX_W_0F12_P_2,
2053   EVEX_W_0F12_P_3,
2054   EVEX_W_0F13_P_0,
2055   EVEX_W_0F13_P_2,
2056   EVEX_W_0F14_P_0,
2057   EVEX_W_0F14_P_2,
2058   EVEX_W_0F15_P_0,
2059   EVEX_W_0F15_P_2,
2060   EVEX_W_0F16_P_0_M_0,
2061   EVEX_W_0F16_P_0_M_1,
2062   EVEX_W_0F16_P_1,
2063   EVEX_W_0F16_P_2,
2064   EVEX_W_0F17_P_0,
2065   EVEX_W_0F17_P_2,
2066   EVEX_W_0F28_P_0,
2067   EVEX_W_0F28_P_2,
2068   EVEX_W_0F29_P_0,
2069   EVEX_W_0F29_P_2,
2070   EVEX_W_0F2A_P_3,
2071   EVEX_W_0F2B_P_0,
2072   EVEX_W_0F2B_P_2,
2073   EVEX_W_0F2E_P_0,
2074   EVEX_W_0F2E_P_2,
2075   EVEX_W_0F2F_P_0,
2076   EVEX_W_0F2F_P_2,
2077   EVEX_W_0F51_P_0,
2078   EVEX_W_0F51_P_1,
2079   EVEX_W_0F51_P_2,
2080   EVEX_W_0F51_P_3,
2081   EVEX_W_0F54_P_0,
2082   EVEX_W_0F54_P_2,
2083   EVEX_W_0F55_P_0,
2084   EVEX_W_0F55_P_2,
2085   EVEX_W_0F56_P_0,
2086   EVEX_W_0F56_P_2,
2087   EVEX_W_0F57_P_0,
2088   EVEX_W_0F57_P_2,
2089   EVEX_W_0F58_P_0,
2090   EVEX_W_0F58_P_1,
2091   EVEX_W_0F58_P_2,
2092   EVEX_W_0F58_P_3,
2093   EVEX_W_0F59_P_0,
2094   EVEX_W_0F59_P_1,
2095   EVEX_W_0F59_P_2,
2096   EVEX_W_0F59_P_3,
2097   EVEX_W_0F5A_P_0,
2098   EVEX_W_0F5A_P_1,
2099   EVEX_W_0F5A_P_2,
2100   EVEX_W_0F5A_P_3,
2101   EVEX_W_0F5B_P_0,
2102   EVEX_W_0F5B_P_1,
2103   EVEX_W_0F5B_P_2,
2104   EVEX_W_0F5C_P_0,
2105   EVEX_W_0F5C_P_1,
2106   EVEX_W_0F5C_P_2,
2107   EVEX_W_0F5C_P_3,
2108   EVEX_W_0F5D_P_0,
2109   EVEX_W_0F5D_P_1,
2110   EVEX_W_0F5D_P_2,
2111   EVEX_W_0F5D_P_3,
2112   EVEX_W_0F5E_P_0,
2113   EVEX_W_0F5E_P_1,
2114   EVEX_W_0F5E_P_2,
2115   EVEX_W_0F5E_P_3,
2116   EVEX_W_0F5F_P_0,
2117   EVEX_W_0F5F_P_1,
2118   EVEX_W_0F5F_P_2,
2119   EVEX_W_0F5F_P_3,
2120   EVEX_W_0F62_P_2,
2121   EVEX_W_0F66_P_2,
2122   EVEX_W_0F6A_P_2,
2123   EVEX_W_0F6B_P_2,
2124   EVEX_W_0F6C_P_2,
2125   EVEX_W_0F6D_P_2,
2126   EVEX_W_0F6F_P_1,
2127   EVEX_W_0F6F_P_2,
2128   EVEX_W_0F6F_P_3,
2129   EVEX_W_0F70_P_2,
2130   EVEX_W_0F72_R_2_P_2,
2131   EVEX_W_0F72_R_6_P_2,
2132   EVEX_W_0F73_R_2_P_2,
2133   EVEX_W_0F73_R_6_P_2,
2134   EVEX_W_0F76_P_2,
2135   EVEX_W_0F78_P_0,
2136   EVEX_W_0F78_P_2,
2137   EVEX_W_0F79_P_0,
2138   EVEX_W_0F79_P_2,
2139   EVEX_W_0F7A_P_1,
2140   EVEX_W_0F7A_P_2,
2141   EVEX_W_0F7A_P_3,
2142   EVEX_W_0F7B_P_2,
2143   EVEX_W_0F7B_P_3,
2144   EVEX_W_0F7E_P_1,
2145   EVEX_W_0F7F_P_1,
2146   EVEX_W_0F7F_P_2,
2147   EVEX_W_0F7F_P_3,
2148   EVEX_W_0FC2_P_0,
2149   EVEX_W_0FC2_P_1,
2150   EVEX_W_0FC2_P_2,
2151   EVEX_W_0FC2_P_3,
2152   EVEX_W_0FC6_P_0,
2153   EVEX_W_0FC6_P_2,
2154   EVEX_W_0FD2_P_2,
2155   EVEX_W_0FD3_P_2,
2156   EVEX_W_0FD4_P_2,
2157   EVEX_W_0FD6_P_2,
2158   EVEX_W_0FE6_P_1,
2159   EVEX_W_0FE6_P_2,
2160   EVEX_W_0FE6_P_3,
2161   EVEX_W_0FE7_P_2,
2162   EVEX_W_0FF2_P_2,
2163   EVEX_W_0FF3_P_2,
2164   EVEX_W_0FF4_P_2,
2165   EVEX_W_0FFA_P_2,
2166   EVEX_W_0FFB_P_2,
2167   EVEX_W_0FFE_P_2,
2168   EVEX_W_0F380C_P_2,
2169   EVEX_W_0F380D_P_2,
2170   EVEX_W_0F3810_P_1,
2171   EVEX_W_0F3810_P_2,
2172   EVEX_W_0F3811_P_1,
2173   EVEX_W_0F3811_P_2,
2174   EVEX_W_0F3812_P_1,
2175   EVEX_W_0F3812_P_2,
2176   EVEX_W_0F3813_P_1,
2177   EVEX_W_0F3813_P_2,
2178   EVEX_W_0F3814_P_1,
2179   EVEX_W_0F3815_P_1,
2180   EVEX_W_0F3818_P_2,
2181   EVEX_W_0F3819_P_2,
2182   EVEX_W_0F381A_P_2,
2183   EVEX_W_0F381B_P_2,
2184   EVEX_W_0F381E_P_2,
2185   EVEX_W_0F381F_P_2,
2186   EVEX_W_0F3820_P_1,
2187   EVEX_W_0F3821_P_1,
2188   EVEX_W_0F3822_P_1,
2189   EVEX_W_0F3823_P_1,
2190   EVEX_W_0F3824_P_1,
2191   EVEX_W_0F3825_P_1,
2192   EVEX_W_0F3825_P_2,
2193   EVEX_W_0F3826_P_1,
2194   EVEX_W_0F3826_P_2,
2195   EVEX_W_0F3828_P_1,
2196   EVEX_W_0F3828_P_2,
2197   EVEX_W_0F3829_P_1,
2198   EVEX_W_0F3829_P_2,
2199   EVEX_W_0F382A_P_1,
2200   EVEX_W_0F382A_P_2,
2201   EVEX_W_0F382B_P_2,
2202   EVEX_W_0F3830_P_1,
2203   EVEX_W_0F3831_P_1,
2204   EVEX_W_0F3832_P_1,
2205   EVEX_W_0F3833_P_1,
2206   EVEX_W_0F3834_P_1,
2207   EVEX_W_0F3835_P_1,
2208   EVEX_W_0F3835_P_2,
2209   EVEX_W_0F3837_P_2,
2210   EVEX_W_0F3838_P_1,
2211   EVEX_W_0F3839_P_1,
2212   EVEX_W_0F383A_P_1,
2213   EVEX_W_0F3840_P_2,
2214   EVEX_W_0F3852_P_1,
2215   EVEX_W_0F3854_P_2,
2216   EVEX_W_0F3855_P_2,
2217   EVEX_W_0F3858_P_2,
2218   EVEX_W_0F3859_P_2,
2219   EVEX_W_0F385A_P_2,
2220   EVEX_W_0F385B_P_2,
2221   EVEX_W_0F3862_P_2,
2222   EVEX_W_0F3863_P_2,
2223   EVEX_W_0F3866_P_2,
2224   EVEX_W_0F3868_P_3,
2225   EVEX_W_0F3870_P_2,
2226   EVEX_W_0F3871_P_2,
2227   EVEX_W_0F3872_P_1,
2228   EVEX_W_0F3872_P_2,
2229   EVEX_W_0F3872_P_3,
2230   EVEX_W_0F3873_P_2,
2231   EVEX_W_0F3875_P_2,
2232   EVEX_W_0F3878_P_2,
2233   EVEX_W_0F3879_P_2,
2234   EVEX_W_0F387A_P_2,
2235   EVEX_W_0F387B_P_2,
2236   EVEX_W_0F387D_P_2,
2237   EVEX_W_0F3883_P_2,
2238   EVEX_W_0F388D_P_2,
2239   EVEX_W_0F3891_P_2,
2240   EVEX_W_0F3893_P_2,
2241   EVEX_W_0F38A1_P_2,
2242   EVEX_W_0F38A3_P_2,
2243   EVEX_W_0F38C7_R_1_P_2,
2244   EVEX_W_0F38C7_R_2_P_2,
2245   EVEX_W_0F38C7_R_5_P_2,
2246   EVEX_W_0F38C7_R_6_P_2,
2247
2248   EVEX_W_0F3A00_P_2,
2249   EVEX_W_0F3A01_P_2,
2250   EVEX_W_0F3A04_P_2,
2251   EVEX_W_0F3A05_P_2,
2252   EVEX_W_0F3A08_P_2,
2253   EVEX_W_0F3A09_P_2,
2254   EVEX_W_0F3A0A_P_2,
2255   EVEX_W_0F3A0B_P_2,
2256   EVEX_W_0F3A18_P_2,
2257   EVEX_W_0F3A19_P_2,
2258   EVEX_W_0F3A1A_P_2,
2259   EVEX_W_0F3A1B_P_2,
2260   EVEX_W_0F3A1D_P_2,
2261   EVEX_W_0F3A21_P_2,
2262   EVEX_W_0F3A23_P_2,
2263   EVEX_W_0F3A38_P_2,
2264   EVEX_W_0F3A39_P_2,
2265   EVEX_W_0F3A3A_P_2,
2266   EVEX_W_0F3A3B_P_2,
2267   EVEX_W_0F3A3E_P_2,
2268   EVEX_W_0F3A3F_P_2,
2269   EVEX_W_0F3A42_P_2,
2270   EVEX_W_0F3A43_P_2,
2271   EVEX_W_0F3A50_P_2,
2272   EVEX_W_0F3A51_P_2,
2273   EVEX_W_0F3A56_P_2,
2274   EVEX_W_0F3A57_P_2,
2275   EVEX_W_0F3A66_P_2,
2276   EVEX_W_0F3A67_P_2,
2277   EVEX_W_0F3A70_P_2,
2278   EVEX_W_0F3A71_P_2,
2279   EVEX_W_0F3A72_P_2,
2280   EVEX_W_0F3A73_P_2,
2281   EVEX_W_0F3ACE_P_2,
2282   EVEX_W_0F3ACF_P_2
2283 };
2284
2285 typedef void (*op_rtn) (int bytemode, int sizeflag);
2286
2287 struct dis386 {
2288   const char *name;
2289   struct
2290     {
2291       op_rtn rtn;
2292       int bytemode;
2293     } op[MAX_OPERANDS];
2294   unsigned int prefix_requirement;
2295 };
2296
2297 /* Upper case letters in the instruction names here are macros.
2298    'A' => print 'b' if no register operands or suffix_always is true
2299    'B' => print 'b' if suffix_always is true
2300    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2301           size prefix
2302    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2303           suffix_always is true
2304    'E' => print 'e' if 32-bit form of jcxz
2305    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2306    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2307    'H' => print ",pt" or ",pn" branch hint
2308    'I' => honor following macro letter even in Intel mode (implemented only
2309           for some of the macro letters)
2310    'J' => print 'l'
2311    'K' => print 'd' or 'q' if rex prefix is present.
2312    'L' => print 'l' if suffix_always is true
2313    'M' => print 'r' if intel_mnemonic is false.
2314    'N' => print 'n' if instruction has no wait "prefix"
2315    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2316    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2317           or suffix_always is true.  print 'q' if rex prefix is present.
2318    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2319           is true
2320    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2321    'S' => print 'w', 'l' or 'q' if suffix_always is true
2322    'T' => print 'q' in 64bit mode if instruction has no operand size
2323           prefix and behave as 'P' otherwise
2324    'U' => print 'q' in 64bit mode if instruction has no operand size
2325           prefix and behave as 'Q' otherwise
2326    'V' => print 'q' in 64bit mode if instruction has no operand size
2327           prefix and behave as 'S' otherwise
2328    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2329    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2330    'Y' unused.
2331    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2332    '!' => change condition from true to false or from false to true.
2333    '%' => add 1 upper case letter to the macro.
2334    '^' => print 'w' or 'l' depending on operand size prefix or
2335           suffix_always is true (lcall/ljmp).
2336    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2337           on operand size prefix.
2338    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2339           has no operand size prefix for AMD64 ISA, behave as 'P'
2340           otherwise
2341
2342    2 upper case letter macros:
2343    "XY" => print 'x' or 'y' if suffix_always is true or no register
2344            operands and no broadcast.
2345    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2346            register operands and no broadcast.
2347    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2348    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2349            or suffix_always is true
2350    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2351    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2352    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2353    "LW" => print 'd', 'q' depending on the VEX.W bit
2354    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2355            an operand size prefix, or suffix_always is true.  print
2356            'q' if rex prefix is present.
2357
2358    Many of the above letters print nothing in Intel mode.  See "putop"
2359    for the details.
2360
2361    Braces '{' and '}', and vertical bars '|', indicate alternative
2362    mnemonic strings for AT&T and Intel.  */
2363
2364 static const struct dis386 dis386[] = {
2365   /* 00 */
2366   { "addB",             { Ebh1, Gb }, 0 },
2367   { "addS",             { Evh1, Gv }, 0 },
2368   { "addB",             { Gb, EbS }, 0 },
2369   { "addS",             { Gv, EvS }, 0 },
2370   { "addB",             { AL, Ib }, 0 },
2371   { "addS",             { eAX, Iv }, 0 },
2372   { X86_64_TABLE (X86_64_06) },
2373   { X86_64_TABLE (X86_64_07) },
2374   /* 08 */
2375   { "orB",              { Ebh1, Gb }, 0 },
2376   { "orS",              { Evh1, Gv }, 0 },
2377   { "orB",              { Gb, EbS }, 0 },
2378   { "orS",              { Gv, EvS }, 0 },
2379   { "orB",              { AL, Ib }, 0 },
2380   { "orS",              { eAX, Iv }, 0 },
2381   { X86_64_TABLE (X86_64_0D) },
2382   { Bad_Opcode },       /* 0x0f extended opcode escape */
2383   /* 10 */
2384   { "adcB",             { Ebh1, Gb }, 0 },
2385   { "adcS",             { Evh1, Gv }, 0 },
2386   { "adcB",             { Gb, EbS }, 0 },
2387   { "adcS",             { Gv, EvS }, 0 },
2388   { "adcB",             { AL, Ib }, 0 },
2389   { "adcS",             { eAX, Iv }, 0 },
2390   { X86_64_TABLE (X86_64_16) },
2391   { X86_64_TABLE (X86_64_17) },
2392   /* 18 */
2393   { "sbbB",             { Ebh1, Gb }, 0 },
2394   { "sbbS",             { Evh1, Gv }, 0 },
2395   { "sbbB",             { Gb, EbS }, 0 },
2396   { "sbbS",             { Gv, EvS }, 0 },
2397   { "sbbB",             { AL, Ib }, 0 },
2398   { "sbbS",             { eAX, Iv }, 0 },
2399   { X86_64_TABLE (X86_64_1E) },
2400   { X86_64_TABLE (X86_64_1F) },
2401   /* 20 */
2402   { "andB",             { Ebh1, Gb }, 0 },
2403   { "andS",             { Evh1, Gv }, 0 },
2404   { "andB",             { Gb, EbS }, 0 },
2405   { "andS",             { Gv, EvS }, 0 },
2406   { "andB",             { AL, Ib }, 0 },
2407   { "andS",             { eAX, Iv }, 0 },
2408   { Bad_Opcode },       /* SEG ES prefix */
2409   { X86_64_TABLE (X86_64_27) },
2410   /* 28 */
2411   { "subB",             { Ebh1, Gb }, 0 },
2412   { "subS",             { Evh1, Gv }, 0 },
2413   { "subB",             { Gb, EbS }, 0 },
2414   { "subS",             { Gv, EvS }, 0 },
2415   { "subB",             { AL, Ib }, 0 },
2416   { "subS",             { eAX, Iv }, 0 },
2417   { Bad_Opcode },       /* SEG CS prefix */
2418   { X86_64_TABLE (X86_64_2F) },
2419   /* 30 */
2420   { "xorB",             { Ebh1, Gb }, 0 },
2421   { "xorS",             { Evh1, Gv }, 0 },
2422   { "xorB",             { Gb, EbS }, 0 },
2423   { "xorS",             { Gv, EvS }, 0 },
2424   { "xorB",             { AL, Ib }, 0 },
2425   { "xorS",             { eAX, Iv }, 0 },
2426   { Bad_Opcode },       /* SEG SS prefix */
2427   { X86_64_TABLE (X86_64_37) },
2428   /* 38 */
2429   { "cmpB",             { Eb, Gb }, 0 },
2430   { "cmpS",             { Ev, Gv }, 0 },
2431   { "cmpB",             { Gb, EbS }, 0 },
2432   { "cmpS",             { Gv, EvS }, 0 },
2433   { "cmpB",             { AL, Ib }, 0 },
2434   { "cmpS",             { eAX, Iv }, 0 },
2435   { Bad_Opcode },       /* SEG DS prefix */
2436   { X86_64_TABLE (X86_64_3F) },
2437   /* 40 */
2438   { "inc{S|}",          { RMeAX }, 0 },
2439   { "inc{S|}",          { RMeCX }, 0 },
2440   { "inc{S|}",          { RMeDX }, 0 },
2441   { "inc{S|}",          { RMeBX }, 0 },
2442   { "inc{S|}",          { RMeSP }, 0 },
2443   { "inc{S|}",          { RMeBP }, 0 },
2444   { "inc{S|}",          { RMeSI }, 0 },
2445   { "inc{S|}",          { RMeDI }, 0 },
2446   /* 48 */
2447   { "dec{S|}",          { RMeAX }, 0 },
2448   { "dec{S|}",          { RMeCX }, 0 },
2449   { "dec{S|}",          { RMeDX }, 0 },
2450   { "dec{S|}",          { RMeBX }, 0 },
2451   { "dec{S|}",          { RMeSP }, 0 },
2452   { "dec{S|}",          { RMeBP }, 0 },
2453   { "dec{S|}",          { RMeSI }, 0 },
2454   { "dec{S|}",          { RMeDI }, 0 },
2455   /* 50 */
2456   { "pushV",            { RMrAX }, 0 },
2457   { "pushV",            { RMrCX }, 0 },
2458   { "pushV",            { RMrDX }, 0 },
2459   { "pushV",            { RMrBX }, 0 },
2460   { "pushV",            { RMrSP }, 0 },
2461   { "pushV",            { RMrBP }, 0 },
2462   { "pushV",            { RMrSI }, 0 },
2463   { "pushV",            { RMrDI }, 0 },
2464   /* 58 */
2465   { "popV",             { RMrAX }, 0 },
2466   { "popV",             { RMrCX }, 0 },
2467   { "popV",             { RMrDX }, 0 },
2468   { "popV",             { RMrBX }, 0 },
2469   { "popV",             { RMrSP }, 0 },
2470   { "popV",             { RMrBP }, 0 },
2471   { "popV",             { RMrSI }, 0 },
2472   { "popV",             { RMrDI }, 0 },
2473   /* 60 */
2474   { X86_64_TABLE (X86_64_60) },
2475   { X86_64_TABLE (X86_64_61) },
2476   { X86_64_TABLE (X86_64_62) },
2477   { X86_64_TABLE (X86_64_63) },
2478   { Bad_Opcode },       /* seg fs */
2479   { Bad_Opcode },       /* seg gs */
2480   { Bad_Opcode },       /* op size prefix */
2481   { Bad_Opcode },       /* adr size prefix */
2482   /* 68 */
2483   { "pushT",            { sIv }, 0 },
2484   { "imulS",            { Gv, Ev, Iv }, 0 },
2485   { "pushT",            { sIbT }, 0 },
2486   { "imulS",            { Gv, Ev, sIb }, 0 },
2487   { "ins{b|}",          { Ybr, indirDX }, 0 },
2488   { X86_64_TABLE (X86_64_6D) },
2489   { "outs{b|}",         { indirDXr, Xb }, 0 },
2490   { X86_64_TABLE (X86_64_6F) },
2491   /* 70 */
2492   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2493   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2494   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2495   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2496   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2497   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2498   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2499   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2500   /* 78 */
2501   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2502   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2503   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2504   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2505   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2506   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2507   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2508   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2509   /* 80 */
2510   { REG_TABLE (REG_80) },
2511   { REG_TABLE (REG_81) },
2512   { X86_64_TABLE (X86_64_82) },
2513   { REG_TABLE (REG_83) },
2514   { "testB",            { Eb, Gb }, 0 },
2515   { "testS",            { Ev, Gv }, 0 },
2516   { "xchgB",            { Ebh2, Gb }, 0 },
2517   { "xchgS",            { Evh2, Gv }, 0 },
2518   /* 88 */
2519   { "movB",             { Ebh3, Gb }, 0 },
2520   { "movS",             { Evh3, Gv }, 0 },
2521   { "movB",             { Gb, EbS }, 0 },
2522   { "movS",             { Gv, EvS }, 0 },
2523   { "movD",             { Sv, Sw }, 0 },
2524   { MOD_TABLE (MOD_8D) },
2525   { "movD",             { Sw, Sv }, 0 },
2526   { REG_TABLE (REG_8F) },
2527   /* 90 */
2528   { PREFIX_TABLE (PREFIX_90) },
2529   { "xchgS",            { RMeCX, eAX }, 0 },
2530   { "xchgS",            { RMeDX, eAX }, 0 },
2531   { "xchgS",            { RMeBX, eAX }, 0 },
2532   { "xchgS",            { RMeSP, eAX }, 0 },
2533   { "xchgS",            { RMeBP, eAX }, 0 },
2534   { "xchgS",            { RMeSI, eAX }, 0 },
2535   { "xchgS",            { RMeDI, eAX }, 0 },
2536   /* 98 */
2537   { "cW{t|}R",          { XX }, 0 },
2538   { "cR{t|}O",          { XX }, 0 },
2539   { X86_64_TABLE (X86_64_9A) },
2540   { Bad_Opcode },       /* fwait */
2541   { "pushfT",           { XX }, 0 },
2542   { "popfT",            { XX }, 0 },
2543   { "sahf",             { XX }, 0 },
2544   { "lahf",             { XX }, 0 },
2545   /* a0 */
2546   { "mov%LB",           { AL, Ob }, 0 },
2547   { "mov%LS",           { eAX, Ov }, 0 },
2548   { "mov%LB",           { Ob, AL }, 0 },
2549   { "mov%LS",           { Ov, eAX }, 0 },
2550   { "movs{b|}",         { Ybr, Xb }, 0 },
2551   { "movs{R|}",         { Yvr, Xv }, 0 },
2552   { "cmps{b|}",         { Xb, Yb }, 0 },
2553   { "cmps{R|}",         { Xv, Yv }, 0 },
2554   /* a8 */
2555   { "testB",            { AL, Ib }, 0 },
2556   { "testS",            { eAX, Iv }, 0 },
2557   { "stosB",            { Ybr, AL }, 0 },
2558   { "stosS",            { Yvr, eAX }, 0 },
2559   { "lodsB",            { ALr, Xb }, 0 },
2560   { "lodsS",            { eAXr, Xv }, 0 },
2561   { "scasB",            { AL, Yb }, 0 },
2562   { "scasS",            { eAX, Yv }, 0 },
2563   /* b0 */
2564   { "movB",             { RMAL, Ib }, 0 },
2565   { "movB",             { RMCL, Ib }, 0 },
2566   { "movB",             { RMDL, Ib }, 0 },
2567   { "movB",             { RMBL, Ib }, 0 },
2568   { "movB",             { RMAH, Ib }, 0 },
2569   { "movB",             { RMCH, Ib }, 0 },
2570   { "movB",             { RMDH, Ib }, 0 },
2571   { "movB",             { RMBH, Ib }, 0 },
2572   /* b8 */
2573   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2574   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2575   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2576   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2577   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2578   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2579   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2580   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2581   /* c0 */
2582   { REG_TABLE (REG_C0) },
2583   { REG_TABLE (REG_C1) },
2584   { "retT",             { Iw, BND }, 0 },
2585   { "retT",             { BND }, 0 },
2586   { X86_64_TABLE (X86_64_C4) },
2587   { X86_64_TABLE (X86_64_C5) },
2588   { REG_TABLE (REG_C6) },
2589   { REG_TABLE (REG_C7) },
2590   /* c8 */
2591   { "enterT",           { Iw, Ib }, 0 },
2592   { "leaveT",           { XX }, 0 },
2593   { "Jret{|f}P",        { Iw }, 0 },
2594   { "Jret{|f}P",        { XX }, 0 },
2595   { "int3",             { XX }, 0 },
2596   { "int",              { Ib }, 0 },
2597   { X86_64_TABLE (X86_64_CE) },
2598   { "iret%LP",          { XX }, 0 },
2599   /* d0 */
2600   { REG_TABLE (REG_D0) },
2601   { REG_TABLE (REG_D1) },
2602   { REG_TABLE (REG_D2) },
2603   { REG_TABLE (REG_D3) },
2604   { X86_64_TABLE (X86_64_D4) },
2605   { X86_64_TABLE (X86_64_D5) },
2606   { Bad_Opcode },
2607   { "xlat",             { DSBX }, 0 },
2608   /* d8 */
2609   { FLOAT },
2610   { FLOAT },
2611   { FLOAT },
2612   { FLOAT },
2613   { FLOAT },
2614   { FLOAT },
2615   { FLOAT },
2616   { FLOAT },
2617   /* e0 */
2618   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2619   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2620   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2621   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2622   { "inB",              { AL, Ib }, 0 },
2623   { "inG",              { zAX, Ib }, 0 },
2624   { "outB",             { Ib, AL }, 0 },
2625   { "outG",             { Ib, zAX }, 0 },
2626   /* e8 */
2627   { X86_64_TABLE (X86_64_E8) },
2628   { X86_64_TABLE (X86_64_E9) },
2629   { X86_64_TABLE (X86_64_EA) },
2630   { "jmp",              { Jb, BND }, 0 },
2631   { "inB",              { AL, indirDX }, 0 },
2632   { "inG",              { zAX, indirDX }, 0 },
2633   { "outB",             { indirDX, AL }, 0 },
2634   { "outG",             { indirDX, zAX }, 0 },
2635   /* f0 */
2636   { Bad_Opcode },       /* lock prefix */
2637   { "icebp",            { XX }, 0 },
2638   { Bad_Opcode },       /* repne */
2639   { Bad_Opcode },       /* repz */
2640   { "hlt",              { XX }, 0 },
2641   { "cmc",              { XX }, 0 },
2642   { REG_TABLE (REG_F6) },
2643   { REG_TABLE (REG_F7) },
2644   /* f8 */
2645   { "clc",              { XX }, 0 },
2646   { "stc",              { XX }, 0 },
2647   { "cli",              { XX }, 0 },
2648   { "sti",              { XX }, 0 },
2649   { "cld",              { XX }, 0 },
2650   { "std",              { XX }, 0 },
2651   { REG_TABLE (REG_FE) },
2652   { REG_TABLE (REG_FF) },
2653 };
2654
2655 static const struct dis386 dis386_twobyte[] = {
2656   /* 00 */
2657   { REG_TABLE (REG_0F00 ) },
2658   { REG_TABLE (REG_0F01 ) },
2659   { "larS",             { Gv, Ew }, 0 },
2660   { "lslS",             { Gv, Ew }, 0 },
2661   { Bad_Opcode },
2662   { "syscall",          { XX }, 0 },
2663   { "clts",             { XX }, 0 },
2664   { "sysret%LP",                { XX }, 0 },
2665   /* 08 */
2666   { "invd",             { XX }, 0 },
2667   { PREFIX_TABLE (PREFIX_0F09) },
2668   { Bad_Opcode },
2669   { "ud2",              { XX }, 0 },
2670   { Bad_Opcode },
2671   { REG_TABLE (REG_0F0D) },
2672   { "femms",            { XX }, 0 },
2673   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2674   /* 10 */
2675   { PREFIX_TABLE (PREFIX_0F10) },
2676   { PREFIX_TABLE (PREFIX_0F11) },
2677   { PREFIX_TABLE (PREFIX_0F12) },
2678   { MOD_TABLE (MOD_0F13) },
2679   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2680   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2681   { PREFIX_TABLE (PREFIX_0F16) },
2682   { MOD_TABLE (MOD_0F17) },
2683   /* 18 */
2684   { REG_TABLE (REG_0F18) },
2685   { "nopQ",             { Ev }, 0 },
2686   { PREFIX_TABLE (PREFIX_0F1A) },
2687   { PREFIX_TABLE (PREFIX_0F1B) },
2688   { PREFIX_TABLE (PREFIX_0F1C) },
2689   { "nopQ",             { Ev }, 0 },
2690   { PREFIX_TABLE (PREFIX_0F1E) },
2691   { "nopQ",             { Ev }, 0 },
2692   /* 20 */
2693   { "movZ",             { Rm, Cm }, 0 },
2694   { "movZ",             { Rm, Dm }, 0 },
2695   { "movZ",             { Cm, Rm }, 0 },
2696   { "movZ",             { Dm, Rm }, 0 },
2697   { MOD_TABLE (MOD_0F24) },
2698   { Bad_Opcode },
2699   { MOD_TABLE (MOD_0F26) },
2700   { Bad_Opcode },
2701   /* 28 */
2702   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2703   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2704   { PREFIX_TABLE (PREFIX_0F2A) },
2705   { PREFIX_TABLE (PREFIX_0F2B) },
2706   { PREFIX_TABLE (PREFIX_0F2C) },
2707   { PREFIX_TABLE (PREFIX_0F2D) },
2708   { PREFIX_TABLE (PREFIX_0F2E) },
2709   { PREFIX_TABLE (PREFIX_0F2F) },
2710   /* 30 */
2711   { "wrmsr",            { XX }, 0 },
2712   { "rdtsc",            { XX }, 0 },
2713   { "rdmsr",            { XX }, 0 },
2714   { "rdpmc",            { XX }, 0 },
2715   { "sysenter",         { XX }, 0 },
2716   { "sysexit",          { XX }, 0 },
2717   { Bad_Opcode },
2718   { "getsec",           { XX }, 0 },
2719   /* 38 */
2720   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2721   { Bad_Opcode },
2722   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2723   { Bad_Opcode },
2724   { Bad_Opcode },
2725   { Bad_Opcode },
2726   { Bad_Opcode },
2727   { Bad_Opcode },
2728   /* 40 */
2729   { "cmovoS",           { Gv, Ev }, 0 },
2730   { "cmovnoS",          { Gv, Ev }, 0 },
2731   { "cmovbS",           { Gv, Ev }, 0 },
2732   { "cmovaeS",          { Gv, Ev }, 0 },
2733   { "cmoveS",           { Gv, Ev }, 0 },
2734   { "cmovneS",          { Gv, Ev }, 0 },
2735   { "cmovbeS",          { Gv, Ev }, 0 },
2736   { "cmovaS",           { Gv, Ev }, 0 },
2737   /* 48 */
2738   { "cmovsS",           { Gv, Ev }, 0 },
2739   { "cmovnsS",          { Gv, Ev }, 0 },
2740   { "cmovpS",           { Gv, Ev }, 0 },
2741   { "cmovnpS",          { Gv, Ev }, 0 },
2742   { "cmovlS",           { Gv, Ev }, 0 },
2743   { "cmovgeS",          { Gv, Ev }, 0 },
2744   { "cmovleS",          { Gv, Ev }, 0 },
2745   { "cmovgS",           { Gv, Ev }, 0 },
2746   /* 50 */
2747   { MOD_TABLE (MOD_0F51) },
2748   { PREFIX_TABLE (PREFIX_0F51) },
2749   { PREFIX_TABLE (PREFIX_0F52) },
2750   { PREFIX_TABLE (PREFIX_0F53) },
2751   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2752   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2753   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2754   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2755   /* 58 */
2756   { PREFIX_TABLE (PREFIX_0F58) },
2757   { PREFIX_TABLE (PREFIX_0F59) },
2758   { PREFIX_TABLE (PREFIX_0F5A) },
2759   { PREFIX_TABLE (PREFIX_0F5B) },
2760   { PREFIX_TABLE (PREFIX_0F5C) },
2761   { PREFIX_TABLE (PREFIX_0F5D) },
2762   { PREFIX_TABLE (PREFIX_0F5E) },
2763   { PREFIX_TABLE (PREFIX_0F5F) },
2764   /* 60 */
2765   { PREFIX_TABLE (PREFIX_0F60) },
2766   { PREFIX_TABLE (PREFIX_0F61) },
2767   { PREFIX_TABLE (PREFIX_0F62) },
2768   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2769   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2770   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2771   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2772   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2773   /* 68 */
2774   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2775   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2776   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2777   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2778   { PREFIX_TABLE (PREFIX_0F6C) },
2779   { PREFIX_TABLE (PREFIX_0F6D) },
2780   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2781   { PREFIX_TABLE (PREFIX_0F6F) },
2782   /* 70 */
2783   { PREFIX_TABLE (PREFIX_0F70) },
2784   { REG_TABLE (REG_0F71) },
2785   { REG_TABLE (REG_0F72) },
2786   { REG_TABLE (REG_0F73) },
2787   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2788   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2789   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2790   { "emms",             { XX }, PREFIX_OPCODE },
2791   /* 78 */
2792   { PREFIX_TABLE (PREFIX_0F78) },
2793   { PREFIX_TABLE (PREFIX_0F79) },
2794   { Bad_Opcode },
2795   { Bad_Opcode },
2796   { PREFIX_TABLE (PREFIX_0F7C) },
2797   { PREFIX_TABLE (PREFIX_0F7D) },
2798   { PREFIX_TABLE (PREFIX_0F7E) },
2799   { PREFIX_TABLE (PREFIX_0F7F) },
2800   /* 80 */
2801   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2802   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2803   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2804   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2805   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2806   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2807   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2808   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2809   /* 88 */
2810   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2811   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2812   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2813   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2814   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2815   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2816   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2817   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2818   /* 90 */
2819   { "seto",             { Eb }, 0 },
2820   { "setno",            { Eb }, 0 },
2821   { "setb",             { Eb }, 0 },
2822   { "setae",            { Eb }, 0 },
2823   { "sete",             { Eb }, 0 },
2824   { "setne",            { Eb }, 0 },
2825   { "setbe",            { Eb }, 0 },
2826   { "seta",             { Eb }, 0 },
2827   /* 98 */
2828   { "sets",             { Eb }, 0 },
2829   { "setns",            { Eb }, 0 },
2830   { "setp",             { Eb }, 0 },
2831   { "setnp",            { Eb }, 0 },
2832   { "setl",             { Eb }, 0 },
2833   { "setge",            { Eb }, 0 },
2834   { "setle",            { Eb }, 0 },
2835   { "setg",             { Eb }, 0 },
2836   /* a0 */
2837   { "pushT",            { fs }, 0 },
2838   { "popT",             { fs }, 0 },
2839   { "cpuid",            { XX }, 0 },
2840   { "btS",              { Ev, Gv }, 0 },
2841   { "shldS",            { Ev, Gv, Ib }, 0 },
2842   { "shldS",            { Ev, Gv, CL }, 0 },
2843   { REG_TABLE (REG_0FA6) },
2844   { REG_TABLE (REG_0FA7) },
2845   /* a8 */
2846   { "pushT",            { gs }, 0 },
2847   { "popT",             { gs }, 0 },
2848   { "rsm",              { XX }, 0 },
2849   { "btsS",             { Evh1, Gv }, 0 },
2850   { "shrdS",            { Ev, Gv, Ib }, 0 },
2851   { "shrdS",            { Ev, Gv, CL }, 0 },
2852   { REG_TABLE (REG_0FAE) },
2853   { "imulS",            { Gv, Ev }, 0 },
2854   /* b0 */
2855   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2856   { "cmpxchgS",         { Evh1, Gv }, 0 },
2857   { MOD_TABLE (MOD_0FB2) },
2858   { "btrS",             { Evh1, Gv }, 0 },
2859   { MOD_TABLE (MOD_0FB4) },
2860   { MOD_TABLE (MOD_0FB5) },
2861   { "movz{bR|x}",       { Gv, Eb }, 0 },
2862   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2863   /* b8 */
2864   { PREFIX_TABLE (PREFIX_0FB8) },
2865   { "ud1S",             { Gv, Ev }, 0 },
2866   { REG_TABLE (REG_0FBA) },
2867   { "btcS",             { Evh1, Gv }, 0 },
2868   { PREFIX_TABLE (PREFIX_0FBC) },
2869   { PREFIX_TABLE (PREFIX_0FBD) },
2870   { "movs{bR|x}",       { Gv, Eb }, 0 },
2871   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2872   /* c0 */
2873   { "xaddB",            { Ebh1, Gb }, 0 },
2874   { "xaddS",            { Evh1, Gv }, 0 },
2875   { PREFIX_TABLE (PREFIX_0FC2) },
2876   { MOD_TABLE (MOD_0FC3) },
2877   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2878   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2879   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2880   { REG_TABLE (REG_0FC7) },
2881   /* c8 */
2882   { "bswap",            { RMeAX }, 0 },
2883   { "bswap",            { RMeCX }, 0 },
2884   { "bswap",            { RMeDX }, 0 },
2885   { "bswap",            { RMeBX }, 0 },
2886   { "bswap",            { RMeSP }, 0 },
2887   { "bswap",            { RMeBP }, 0 },
2888   { "bswap",            { RMeSI }, 0 },
2889   { "bswap",            { RMeDI }, 0 },
2890   /* d0 */
2891   { PREFIX_TABLE (PREFIX_0FD0) },
2892   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2893   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2894   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2895   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2896   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2897   { PREFIX_TABLE (PREFIX_0FD6) },
2898   { MOD_TABLE (MOD_0FD7) },
2899   /* d8 */
2900   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2901   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2902   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2903   { "pand",             { MX, EM }, PREFIX_OPCODE },
2904   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2905   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2906   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2907   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2908   /* e0 */
2909   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2910   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2911   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2912   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2913   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2914   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2915   { PREFIX_TABLE (PREFIX_0FE6) },
2916   { PREFIX_TABLE (PREFIX_0FE7) },
2917   /* e8 */
2918   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2919   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2920   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2921   { "por",              { MX, EM }, PREFIX_OPCODE },
2922   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2923   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2924   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2925   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2926   /* f0 */
2927   { PREFIX_TABLE (PREFIX_0FF0) },
2928   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2929   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2930   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2931   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2932   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2933   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2934   { PREFIX_TABLE (PREFIX_0FF7) },
2935   /* f8 */
2936   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2937   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2938   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2939   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2940   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2941   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2942   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2943   { "ud0S",             { Gv, Ev }, 0 },
2944 };
2945
2946 static const unsigned char onebyte_has_modrm[256] = {
2947   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2948   /*       -------------------------------        */
2949   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2950   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2951   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2952   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2953   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2954   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2955   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2956   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2957   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2958   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2959   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2960   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2961   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2962   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2963   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2964   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2965   /*       -------------------------------        */
2966   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2967 };
2968
2969 static const unsigned char twobyte_has_modrm[256] = {
2970   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2971   /*       -------------------------------        */
2972   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2973   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2974   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2975   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2976   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2977   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2978   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2979   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2980   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2981   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2982   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2983   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2984   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2985   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2986   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2987   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2988   /*       -------------------------------        */
2989   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2990 };
2991
2992 static char obuf[100];
2993 static char *obufp;
2994 static char *mnemonicendp;
2995 static char scratchbuf[100];
2996 static unsigned char *start_codep;
2997 static unsigned char *insn_codep;
2998 static unsigned char *codep;
2999 static unsigned char *end_codep;
3000 static int last_lock_prefix;
3001 static int last_repz_prefix;
3002 static int last_repnz_prefix;
3003 static int last_data_prefix;
3004 static int last_addr_prefix;
3005 static int last_rex_prefix;
3006 static int last_seg_prefix;
3007 static int fwait_prefix;
3008 /* The active segment register prefix.  */
3009 static int active_seg_prefix;
3010 #define MAX_CODE_LENGTH 15
3011 /* We can up to 14 prefixes since the maximum instruction length is
3012    15bytes.  */
3013 static int all_prefixes[MAX_CODE_LENGTH - 1];
3014 static disassemble_info *the_info;
3015 static struct
3016   {
3017     int mod;
3018     int reg;
3019     int rm;
3020   }
3021 modrm;
3022 static unsigned char need_modrm;
3023 static struct
3024   {
3025     int scale;
3026     int index;
3027     int base;
3028   }
3029 sib;
3030 static struct
3031   {
3032     int register_specifier;
3033     int length;
3034     int prefix;
3035     int w;
3036     int evex;
3037     int r;
3038     int v;
3039     int mask_register_specifier;
3040     int zeroing;
3041     int ll;
3042     int b;
3043   }
3044 vex;
3045 static unsigned char need_vex;
3046 static unsigned char need_vex_reg;
3047 static unsigned char vex_w_done;
3048
3049 struct op
3050   {
3051     const char *name;
3052     unsigned int len;
3053   };
3054
3055 /* If we are accessing mod/rm/reg without need_modrm set, then the
3056    values are stale.  Hitting this abort likely indicates that you
3057    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3058 #define MODRM_CHECK  if (!need_modrm) abort ()
3059
3060 static const char **names64;
3061 static const char **names32;
3062 static const char **names16;
3063 static const char **names8;
3064 static const char **names8rex;
3065 static const char **names_seg;
3066 static const char *index64;
3067 static const char *index32;
3068 static const char **index16;
3069 static const char **names_bnd;
3070
3071 static const char *intel_names64[] = {
3072   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3073   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3074 };
3075 static const char *intel_names32[] = {
3076   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3077   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3078 };
3079 static const char *intel_names16[] = {
3080   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3081   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3082 };
3083 static const char *intel_names8[] = {
3084   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3085 };
3086 static const char *intel_names8rex[] = {
3087   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3088   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3089 };
3090 static const char *intel_names_seg[] = {
3091   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3092 };
3093 static const char *intel_index64 = "riz";
3094 static const char *intel_index32 = "eiz";
3095 static const char *intel_index16[] = {
3096   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3097 };
3098
3099 static const char *att_names64[] = {
3100   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3101   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3102 };
3103 static const char *att_names32[] = {
3104   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3105   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3106 };
3107 static const char *att_names16[] = {
3108   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3109   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3110 };
3111 static const char *att_names8[] = {
3112   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3113 };
3114 static const char *att_names8rex[] = {
3115   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3116   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3117 };
3118 static const char *att_names_seg[] = {
3119   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3120 };
3121 static const char *att_index64 = "%riz";
3122 static const char *att_index32 = "%eiz";
3123 static const char *att_index16[] = {
3124   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3125 };
3126
3127 static const char **names_mm;
3128 static const char *intel_names_mm[] = {
3129   "mm0", "mm1", "mm2", "mm3",
3130   "mm4", "mm5", "mm6", "mm7"
3131 };
3132 static const char *att_names_mm[] = {
3133   "%mm0", "%mm1", "%mm2", "%mm3",
3134   "%mm4", "%mm5", "%mm6", "%mm7"
3135 };
3136
3137 static const char *intel_names_bnd[] = {
3138   "bnd0", "bnd1", "bnd2", "bnd3"
3139 };
3140
3141 static const char *att_names_bnd[] = {
3142   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3143 };
3144
3145 static const char **names_xmm;
3146 static const char *intel_names_xmm[] = {
3147   "xmm0", "xmm1", "xmm2", "xmm3",
3148   "xmm4", "xmm5", "xmm6", "xmm7",
3149   "xmm8", "xmm9", "xmm10", "xmm11",
3150   "xmm12", "xmm13", "xmm14", "xmm15",
3151   "xmm16", "xmm17", "xmm18", "xmm19",
3152   "xmm20", "xmm21", "xmm22", "xmm23",
3153   "xmm24", "xmm25", "xmm26", "xmm27",
3154   "xmm28", "xmm29", "xmm30", "xmm31"
3155 };
3156 static const char *att_names_xmm[] = {
3157   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3158   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3159   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3160   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3161   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3162   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3163   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3164   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3165 };
3166
3167 static const char **names_ymm;
3168 static const char *intel_names_ymm[] = {
3169   "ymm0", "ymm1", "ymm2", "ymm3",
3170   "ymm4", "ymm5", "ymm6", "ymm7",
3171   "ymm8", "ymm9", "ymm10", "ymm11",
3172   "ymm12", "ymm13", "ymm14", "ymm15",
3173   "ymm16", "ymm17", "ymm18", "ymm19",
3174   "ymm20", "ymm21", "ymm22", "ymm23",
3175   "ymm24", "ymm25", "ymm26", "ymm27",
3176   "ymm28", "ymm29", "ymm30", "ymm31"
3177 };
3178 static const char *att_names_ymm[] = {
3179   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3180   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3181   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3182   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3183   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3184   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3185   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3186   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3187 };
3188
3189 static const char **names_zmm;
3190 static const char *intel_names_zmm[] = {
3191   "zmm0", "zmm1", "zmm2", "zmm3",
3192   "zmm4", "zmm5", "zmm6", "zmm7",
3193   "zmm8", "zmm9", "zmm10", "zmm11",
3194   "zmm12", "zmm13", "zmm14", "zmm15",
3195   "zmm16", "zmm17", "zmm18", "zmm19",
3196   "zmm20", "zmm21", "zmm22", "zmm23",
3197   "zmm24", "zmm25", "zmm26", "zmm27",
3198   "zmm28", "zmm29", "zmm30", "zmm31"
3199 };
3200 static const char *att_names_zmm[] = {
3201   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3202   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3203   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3204   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3205   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3206   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3207   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3208   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3209 };
3210
3211 static const char **names_mask;
3212 static const char *intel_names_mask[] = {
3213   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3214 };
3215 static const char *att_names_mask[] = {
3216   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3217 };
3218
3219 static const char *names_rounding[] =
3220 {
3221   "{rn-sae}",
3222   "{rd-sae}",
3223   "{ru-sae}",
3224   "{rz-sae}"
3225 };
3226
3227 static const struct dis386 reg_table[][8] = {
3228   /* REG_80 */
3229   {
3230     { "addA",   { Ebh1, Ib }, 0 },
3231     { "orA",    { Ebh1, Ib }, 0 },
3232     { "adcA",   { Ebh1, Ib }, 0 },
3233     { "sbbA",   { Ebh1, Ib }, 0 },
3234     { "andA",   { Ebh1, Ib }, 0 },
3235     { "subA",   { Ebh1, Ib }, 0 },
3236     { "xorA",   { Ebh1, Ib }, 0 },
3237     { "cmpA",   { Eb, Ib }, 0 },
3238   },
3239   /* REG_81 */
3240   {
3241     { "addQ",   { Evh1, Iv }, 0 },
3242     { "orQ",    { Evh1, Iv }, 0 },
3243     { "adcQ",   { Evh1, Iv }, 0 },
3244     { "sbbQ",   { Evh1, Iv }, 0 },
3245     { "andQ",   { Evh1, Iv }, 0 },
3246     { "subQ",   { Evh1, Iv }, 0 },
3247     { "xorQ",   { Evh1, Iv }, 0 },
3248     { "cmpQ",   { Ev, Iv }, 0 },
3249   },
3250   /* REG_83 */
3251   {
3252     { "addQ",   { Evh1, sIb }, 0 },
3253     { "orQ",    { Evh1, sIb }, 0 },
3254     { "adcQ",   { Evh1, sIb }, 0 },
3255     { "sbbQ",   { Evh1, sIb }, 0 },
3256     { "andQ",   { Evh1, sIb }, 0 },
3257     { "subQ",   { Evh1, sIb }, 0 },
3258     { "xorQ",   { Evh1, sIb }, 0 },
3259     { "cmpQ",   { Ev, sIb }, 0 },
3260   },
3261   /* REG_8F */
3262   {
3263     { "popU",   { stackEv }, 0 },
3264     { XOP_8F_TABLE (XOP_09) },
3265     { Bad_Opcode },
3266     { Bad_Opcode },
3267     { Bad_Opcode },
3268     { XOP_8F_TABLE (XOP_09) },
3269   },
3270   /* REG_C0 */
3271   {
3272     { "rolA",   { Eb, Ib }, 0 },
3273     { "rorA",   { Eb, Ib }, 0 },
3274     { "rclA",   { Eb, Ib }, 0 },
3275     { "rcrA",   { Eb, Ib }, 0 },
3276     { "shlA",   { Eb, Ib }, 0 },
3277     { "shrA",   { Eb, Ib }, 0 },
3278     { "shlA",   { Eb, Ib }, 0 },
3279     { "sarA",   { Eb, Ib }, 0 },
3280   },
3281   /* REG_C1 */
3282   {
3283     { "rolQ",   { Ev, Ib }, 0 },
3284     { "rorQ",   { Ev, Ib }, 0 },
3285     { "rclQ",   { Ev, Ib }, 0 },
3286     { "rcrQ",   { Ev, Ib }, 0 },
3287     { "shlQ",   { Ev, Ib }, 0 },
3288     { "shrQ",   { Ev, Ib }, 0 },
3289     { "shlQ",   { Ev, Ib }, 0 },
3290     { "sarQ",   { Ev, Ib }, 0 },
3291   },
3292   /* REG_C6 */
3293   {
3294     { "movA",   { Ebh3, Ib }, 0 },
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { MOD_TABLE (MOD_C6_REG_7) },
3302   },
3303   /* REG_C7 */
3304   {
3305     { "movQ",   { Evh3, Iv }, 0 },
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { MOD_TABLE (MOD_C7_REG_7) },
3313   },
3314   /* REG_D0 */
3315   {
3316     { "rolA",   { Eb, I1 }, 0 },
3317     { "rorA",   { Eb, I1 }, 0 },
3318     { "rclA",   { Eb, I1 }, 0 },
3319     { "rcrA",   { Eb, I1 }, 0 },
3320     { "shlA",   { Eb, I1 }, 0 },
3321     { "shrA",   { Eb, I1 }, 0 },
3322     { "shlA",   { Eb, I1 }, 0 },
3323     { "sarA",   { Eb, I1 }, 0 },
3324   },
3325   /* REG_D1 */
3326   {
3327     { "rolQ",   { Ev, I1 }, 0 },
3328     { "rorQ",   { Ev, I1 }, 0 },
3329     { "rclQ",   { Ev, I1 }, 0 },
3330     { "rcrQ",   { Ev, I1 }, 0 },
3331     { "shlQ",   { Ev, I1 }, 0 },
3332     { "shrQ",   { Ev, I1 }, 0 },
3333     { "shlQ",   { Ev, I1 }, 0 },
3334     { "sarQ",   { Ev, I1 }, 0 },
3335   },
3336   /* REG_D2 */
3337   {
3338     { "rolA",   { Eb, CL }, 0 },
3339     { "rorA",   { Eb, CL }, 0 },
3340     { "rclA",   { Eb, CL }, 0 },
3341     { "rcrA",   { Eb, CL }, 0 },
3342     { "shlA",   { Eb, CL }, 0 },
3343     { "shrA",   { Eb, CL }, 0 },
3344     { "shlA",   { Eb, CL }, 0 },
3345     { "sarA",   { Eb, CL }, 0 },
3346   },
3347   /* REG_D3 */
3348   {
3349     { "rolQ",   { Ev, CL }, 0 },
3350     { "rorQ",   { Ev, CL }, 0 },
3351     { "rclQ",   { Ev, CL }, 0 },
3352     { "rcrQ",   { Ev, CL }, 0 },
3353     { "shlQ",   { Ev, CL }, 0 },
3354     { "shrQ",   { Ev, CL }, 0 },
3355     { "shlQ",   { Ev, CL }, 0 },
3356     { "sarQ",   { Ev, CL }, 0 },
3357   },
3358   /* REG_F6 */
3359   {
3360     { "testA",  { Eb, Ib }, 0 },
3361     { "testA",  { Eb, Ib }, 0 },
3362     { "notA",   { Ebh1 }, 0 },
3363     { "negA",   { Ebh1 }, 0 },
3364     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3365     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3366     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3367     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3368   },
3369   /* REG_F7 */
3370   {
3371     { "testQ",  { Ev, Iv }, 0 },
3372     { "testQ",  { Ev, Iv }, 0 },
3373     { "notQ",   { Evh1 }, 0 },
3374     { "negQ",   { Evh1 }, 0 },
3375     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3376     { "imulQ",  { Ev }, 0 },
3377     { "divQ",   { Ev }, 0 },
3378     { "idivQ",  { Ev }, 0 },
3379   },
3380   /* REG_FE */
3381   {
3382     { "incA",   { Ebh1 }, 0 },
3383     { "decA",   { Ebh1 }, 0 },
3384   },
3385   /* REG_FF */
3386   {
3387     { "incQ",   { Evh1 }, 0 },
3388     { "decQ",   { Evh1 }, 0 },
3389     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3390     { MOD_TABLE (MOD_FF_REG_3) },
3391     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3392     { MOD_TABLE (MOD_FF_REG_5) },
3393     { "pushU",  { stackEv }, 0 },
3394     { Bad_Opcode },
3395   },
3396   /* REG_0F00 */
3397   {
3398     { "sldtD",  { Sv }, 0 },
3399     { "strD",   { Sv }, 0 },
3400     { "lldt",   { Ew }, 0 },
3401     { "ltr",    { Ew }, 0 },
3402     { "verr",   { Ew }, 0 },
3403     { "verw",   { Ew }, 0 },
3404     { Bad_Opcode },
3405     { Bad_Opcode },
3406   },
3407   /* REG_0F01 */
3408   {
3409     { MOD_TABLE (MOD_0F01_REG_0) },
3410     { MOD_TABLE (MOD_0F01_REG_1) },
3411     { MOD_TABLE (MOD_0F01_REG_2) },
3412     { MOD_TABLE (MOD_0F01_REG_3) },
3413     { "smswD",  { Sv }, 0 },
3414     { MOD_TABLE (MOD_0F01_REG_5) },
3415     { "lmsw",   { Ew }, 0 },
3416     { MOD_TABLE (MOD_0F01_REG_7) },
3417   },
3418   /* REG_0F0D */
3419   {
3420     { "prefetch",       { Mb }, 0 },
3421     { "prefetchw",      { Mb }, 0 },
3422     { "prefetchwt1",    { Mb }, 0 },
3423     { "prefetch",       { Mb }, 0 },
3424     { "prefetch",       { Mb }, 0 },
3425     { "prefetch",       { Mb }, 0 },
3426     { "prefetch",       { Mb }, 0 },
3427     { "prefetch",       { Mb }, 0 },
3428   },
3429   /* REG_0F18 */
3430   {
3431     { MOD_TABLE (MOD_0F18_REG_0) },
3432     { MOD_TABLE (MOD_0F18_REG_1) },
3433     { MOD_TABLE (MOD_0F18_REG_2) },
3434     { MOD_TABLE (MOD_0F18_REG_3) },
3435     { MOD_TABLE (MOD_0F18_REG_4) },
3436     { MOD_TABLE (MOD_0F18_REG_5) },
3437     { MOD_TABLE (MOD_0F18_REG_6) },
3438     { MOD_TABLE (MOD_0F18_REG_7) },
3439   },
3440   /* REG_0F1C_MOD_0 */
3441   {
3442     { "cldemote",       { Mb }, 0 },
3443     { "nopQ",           { Ev }, 0 },
3444     { "nopQ",           { Ev }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449     { "nopQ",           { Ev }, 0 },
3450   },
3451   /* REG_0F1E_MOD_3 */
3452   {
3453     { "nopQ",           { Ev }, 0 },
3454     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { "nopQ",           { Ev }, 0 },
3460     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3461   },
3462   /* REG_0F71 */
3463   {
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { MOD_TABLE (MOD_0F71_REG_2) },
3467     { Bad_Opcode },
3468     { MOD_TABLE (MOD_0F71_REG_4) },
3469     { Bad_Opcode },
3470     { MOD_TABLE (MOD_0F71_REG_6) },
3471   },
3472   /* REG_0F72 */
3473   {
3474     { Bad_Opcode },
3475     { Bad_Opcode },
3476     { MOD_TABLE (MOD_0F72_REG_2) },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_0F72_REG_4) },
3479     { Bad_Opcode },
3480     { MOD_TABLE (MOD_0F72_REG_6) },
3481   },
3482   /* REG_0F73 */
3483   {
3484     { Bad_Opcode },
3485     { Bad_Opcode },
3486     { MOD_TABLE (MOD_0F73_REG_2) },
3487     { MOD_TABLE (MOD_0F73_REG_3) },
3488     { Bad_Opcode },
3489     { Bad_Opcode },
3490     { MOD_TABLE (MOD_0F73_REG_6) },
3491     { MOD_TABLE (MOD_0F73_REG_7) },
3492   },
3493   /* REG_0FA6 */
3494   {
3495     { "montmul",        { { OP_0f07, 0 } }, 0 },
3496     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3497     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3498   },
3499   /* REG_0FA7 */
3500   {
3501     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3502     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3503     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3504     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3505     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3506     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3507   },
3508   /* REG_0FAE */
3509   {
3510     { MOD_TABLE (MOD_0FAE_REG_0) },
3511     { MOD_TABLE (MOD_0FAE_REG_1) },
3512     { MOD_TABLE (MOD_0FAE_REG_2) },
3513     { MOD_TABLE (MOD_0FAE_REG_3) },
3514     { MOD_TABLE (MOD_0FAE_REG_4) },
3515     { MOD_TABLE (MOD_0FAE_REG_5) },
3516     { MOD_TABLE (MOD_0FAE_REG_6) },
3517     { MOD_TABLE (MOD_0FAE_REG_7) },
3518   },
3519   /* REG_0FBA */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { "btQ",    { Ev, Ib }, 0 },
3526     { "btsQ",   { Evh1, Ib }, 0 },
3527     { "btrQ",   { Evh1, Ib }, 0 },
3528     { "btcQ",   { Evh1, Ib }, 0 },
3529   },
3530   /* REG_0FC7 */
3531   {
3532     { Bad_Opcode },
3533     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_0FC7_REG_3) },
3536     { MOD_TABLE (MOD_0FC7_REG_4) },
3537     { MOD_TABLE (MOD_0FC7_REG_5) },
3538     { MOD_TABLE (MOD_0FC7_REG_6) },
3539     { MOD_TABLE (MOD_0FC7_REG_7) },
3540   },
3541   /* REG_VEX_0F71 */
3542   {
3543     { Bad_Opcode },
3544     { Bad_Opcode },
3545     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3548     { Bad_Opcode },
3549     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3550   },
3551   /* REG_VEX_0F72 */
3552   {
3553     { Bad_Opcode },
3554     { Bad_Opcode },
3555     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3556     { Bad_Opcode },
3557     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3558     { Bad_Opcode },
3559     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3560   },
3561   /* REG_VEX_0F73 */
3562   {
3563     { Bad_Opcode },
3564     { Bad_Opcode },
3565     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3566     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3567     { Bad_Opcode },
3568     { Bad_Opcode },
3569     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3570     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3571   },
3572   /* REG_VEX_0FAE */
3573   {
3574     { Bad_Opcode },
3575     { Bad_Opcode },
3576     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3577     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3578   },
3579   /* REG_VEX_0F38F3 */
3580   {
3581     { Bad_Opcode },
3582     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3583     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3584     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3585   },
3586   /* REG_XOP_LWPCB */
3587   {
3588     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3589     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3590   },
3591   /* REG_XOP_LWP */
3592   {
3593     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3594     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3595   },
3596   /* REG_XOP_TBM_01 */
3597   {
3598     { Bad_Opcode },
3599     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3600     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3601     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3602     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3603     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3604     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3605     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3606   },
3607   /* REG_XOP_TBM_02 */
3608   {
3609     { Bad_Opcode },
3610     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3616   },
3617
3618 #include "i386-dis-evex-reg.h"
3619 };
3620
3621 static const struct dis386 prefix_table[][4] = {
3622   /* PREFIX_90 */
3623   {
3624     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3625     { "pause", { XX }, 0 },
3626     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3627     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3628   },
3629
3630   /* PREFIX_MOD_0_0F01_REG_5 */
3631   {
3632     { Bad_Opcode },
3633     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3634   },
3635
3636   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3637   {
3638     { Bad_Opcode },
3639     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3640   },
3641
3642   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3643   {
3644     { Bad_Opcode },
3645     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3646   },
3647
3648   /* PREFIX_0F09 */
3649   {
3650     { "wbinvd",   { XX }, 0 },
3651     { "wbnoinvd", { XX }, 0 },
3652   },
3653
3654   /* PREFIX_0F10 */
3655   {
3656     { "movups", { XM, EXx }, PREFIX_OPCODE },
3657     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3658     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3659     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3660   },
3661
3662   /* PREFIX_0F11 */
3663   {
3664     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3665     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3666     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3667     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3668   },
3669
3670   /* PREFIX_0F12 */
3671   {
3672     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3673     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3674     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3675     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3676   },
3677
3678   /* PREFIX_0F16 */
3679   {
3680     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3681     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3682     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3683   },
3684
3685   /* PREFIX_0F1A */
3686   {
3687     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3688     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3689     { "bndmov", { Gbnd, Ebnd }, 0 },
3690     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3691   },
3692
3693   /* PREFIX_0F1B */
3694   {
3695     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3696     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3697     { "bndmov", { EbndS, Gbnd }, 0 },
3698     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3699   },
3700
3701   /* PREFIX_0F1C */
3702   {
3703     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3704     { "nopQ",   { Ev }, PREFIX_OPCODE },
3705     { "nopQ",   { Ev }, PREFIX_OPCODE },
3706     { "nopQ",   { Ev }, PREFIX_OPCODE },
3707   },
3708
3709   /* PREFIX_0F1E */
3710   {
3711     { "nopQ",   { Ev }, PREFIX_OPCODE },
3712     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3713     { "nopQ",   { Ev }, PREFIX_OPCODE },
3714     { "nopQ",   { Ev }, PREFIX_OPCODE },
3715   },
3716
3717   /* PREFIX_0F2A */
3718   {
3719     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3720     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3721     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3722     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3723   },
3724
3725   /* PREFIX_0F2B */
3726   {
3727     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3728     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3729     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3730     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3731   },
3732
3733   /* PREFIX_0F2C */
3734   {
3735     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3736     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3737     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3738     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3739   },
3740
3741   /* PREFIX_0F2D */
3742   {
3743     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3744     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3745     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3746     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3747   },
3748
3749   /* PREFIX_0F2E */
3750   {
3751     { "ucomiss",{ XM, EXd }, 0 },
3752     { Bad_Opcode },
3753     { "ucomisd",{ XM, EXq }, 0 },
3754   },
3755
3756   /* PREFIX_0F2F */
3757   {
3758     { "comiss", { XM, EXd }, 0 },
3759     { Bad_Opcode },
3760     { "comisd", { XM, EXq }, 0 },
3761   },
3762
3763   /* PREFIX_0F51 */
3764   {
3765     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3766     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3767     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3768     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3769   },
3770
3771   /* PREFIX_0F52 */
3772   {
3773     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3774     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3775   },
3776
3777   /* PREFIX_0F53 */
3778   {
3779     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3780     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3781   },
3782
3783   /* PREFIX_0F58 */
3784   {
3785     { "addps", { XM, EXx }, PREFIX_OPCODE },
3786     { "addss", { XM, EXd }, PREFIX_OPCODE },
3787     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3788     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3789   },
3790
3791   /* PREFIX_0F59 */
3792   {
3793     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3794     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3795     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3796     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3797   },
3798
3799   /* PREFIX_0F5A */
3800   {
3801     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3802     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3803     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3804     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3805   },
3806
3807   /* PREFIX_0F5B */
3808   {
3809     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3810     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3811     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3812   },
3813
3814   /* PREFIX_0F5C */
3815   {
3816     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3817     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3818     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3819     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3820   },
3821
3822   /* PREFIX_0F5D */
3823   {
3824     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3825     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3826     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3827     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3828   },
3829
3830   /* PREFIX_0F5E */
3831   {
3832     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3833     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3834     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3835     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3836   },
3837
3838   /* PREFIX_0F5F */
3839   {
3840     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3841     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3842     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3843     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3844   },
3845
3846   /* PREFIX_0F60 */
3847   {
3848     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3849     { Bad_Opcode },
3850     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3851   },
3852
3853   /* PREFIX_0F61 */
3854   {
3855     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3856     { Bad_Opcode },
3857     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3858   },
3859
3860   /* PREFIX_0F62 */
3861   {
3862     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3863     { Bad_Opcode },
3864     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_0F6C */
3868   {
3869     { Bad_Opcode },
3870     { Bad_Opcode },
3871     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0F6D */
3875   {
3876     { Bad_Opcode },
3877     { Bad_Opcode },
3878     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3879   },
3880
3881   /* PREFIX_0F6F */
3882   {
3883     { "movq",   { MX, EM }, PREFIX_OPCODE },
3884     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3885     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3886   },
3887
3888   /* PREFIX_0F70 */
3889   {
3890     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3891     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3892     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3893     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3894   },
3895
3896   /* PREFIX_0F73_REG_3 */
3897   {
3898     { Bad_Opcode },
3899     { Bad_Opcode },
3900     { "psrldq", { XS, Ib }, 0 },
3901   },
3902
3903   /* PREFIX_0F73_REG_7 */
3904   {
3905     { Bad_Opcode },
3906     { Bad_Opcode },
3907     { "pslldq", { XS, Ib }, 0 },
3908   },
3909
3910   /* PREFIX_0F78 */
3911   {
3912     {"vmread",  { Em, Gm }, 0 },
3913     { Bad_Opcode },
3914     {"extrq",   { XS, Ib, Ib }, 0 },
3915     {"insertq", { XM, XS, Ib, Ib }, 0 },
3916   },
3917
3918   /* PREFIX_0F79 */
3919   {
3920     {"vmwrite", { Gm, Em }, 0 },
3921     { Bad_Opcode },
3922     {"extrq",   { XM, XS }, 0 },
3923     {"insertq", { XM, XS }, 0 },
3924   },
3925
3926   /* PREFIX_0F7C */
3927   {
3928     { Bad_Opcode },
3929     { Bad_Opcode },
3930     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3931     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3932   },
3933
3934   /* PREFIX_0F7D */
3935   {
3936     { Bad_Opcode },
3937     { Bad_Opcode },
3938     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3939     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3940   },
3941
3942   /* PREFIX_0F7E */
3943   {
3944     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3945     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3946     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3947   },
3948
3949   /* PREFIX_0F7F */
3950   {
3951     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3952     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3953     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3954   },
3955
3956   /* PREFIX_0FAE_REG_0 */
3957   {
3958     { Bad_Opcode },
3959     { "rdfsbase", { Ev }, 0 },
3960   },
3961
3962   /* PREFIX_0FAE_REG_1 */
3963   {
3964     { Bad_Opcode },
3965     { "rdgsbase", { Ev }, 0 },
3966   },
3967
3968   /* PREFIX_0FAE_REG_2 */
3969   {
3970     { Bad_Opcode },
3971     { "wrfsbase", { Ev }, 0 },
3972   },
3973
3974   /* PREFIX_0FAE_REG_3 */
3975   {
3976     { Bad_Opcode },
3977     { "wrgsbase", { Ev }, 0 },
3978   },
3979
3980   /* PREFIX_MOD_0_0FAE_REG_4 */
3981   {
3982     { "xsave",  { FXSAVE }, 0 },
3983     { "ptwrite%LQ", { Edq }, 0 },
3984   },
3985
3986   /* PREFIX_MOD_3_0FAE_REG_4 */
3987   {
3988     { Bad_Opcode },
3989     { "ptwrite%LQ", { Edq }, 0 },
3990   },
3991
3992   /* PREFIX_MOD_0_0FAE_REG_5 */
3993   {
3994     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3995   },
3996
3997   /* PREFIX_MOD_3_0FAE_REG_5 */
3998   {
3999     { "lfence",         { Skip_MODRM }, 0 },
4000     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4001   },
4002
4003   /* PREFIX_MOD_0_0FAE_REG_6 */
4004   {
4005     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4006     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4007     { "clwb",   { Mb }, PREFIX_OPCODE },
4008   },
4009
4010   /* PREFIX_MOD_1_0FAE_REG_6 */
4011   {
4012     { RM_TABLE (RM_0FAE_REG_6) },
4013     { "umonitor",       { Eva }, PREFIX_OPCODE },
4014     { "tpause", { Edq }, PREFIX_OPCODE },
4015     { "umwait", { Edq }, PREFIX_OPCODE },
4016   },
4017
4018   /* PREFIX_0FAE_REG_7 */
4019   {
4020     { "clflush",        { Mb }, 0 },
4021     { Bad_Opcode },
4022     { "clflushopt",     { Mb }, 0 },
4023   },
4024
4025   /* PREFIX_0FB8 */
4026   {
4027     { Bad_Opcode },
4028     { "popcntS", { Gv, Ev }, 0 },
4029   },
4030
4031   /* PREFIX_0FBC */
4032   {
4033     { "bsfS",   { Gv, Ev }, 0 },
4034     { "tzcntS", { Gv, Ev }, 0 },
4035     { "bsfS",   { Gv, Ev }, 0 },
4036   },
4037
4038   /* PREFIX_0FBD */
4039   {
4040     { "bsrS",   { Gv, Ev }, 0 },
4041     { "lzcntS", { Gv, Ev }, 0 },
4042     { "bsrS",   { Gv, Ev }, 0 },
4043   },
4044
4045   /* PREFIX_0FC2 */
4046   {
4047     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4048     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4049     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4050     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4051   },
4052
4053   /* PREFIX_MOD_0_0FC3 */
4054   {
4055     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4056   },
4057
4058   /* PREFIX_MOD_0_0FC7_REG_6 */
4059   {
4060     { "vmptrld",{ Mq }, 0 },
4061     { "vmxon",  { Mq }, 0 },
4062     { "vmclear",{ Mq }, 0 },
4063   },
4064
4065   /* PREFIX_MOD_3_0FC7_REG_6 */
4066   {
4067     { "rdrand", { Ev }, 0 },
4068     { Bad_Opcode },
4069     { "rdrand", { Ev }, 0 }
4070   },
4071
4072   /* PREFIX_MOD_3_0FC7_REG_7 */
4073   {
4074     { "rdseed", { Ev }, 0 },
4075     { "rdpid",  { Em }, 0 },
4076     { "rdseed", { Ev }, 0 },
4077   },
4078
4079   /* PREFIX_0FD0 */
4080   {
4081     { Bad_Opcode },
4082     { Bad_Opcode },
4083     { "addsubpd", { XM, EXx }, 0 },
4084     { "addsubps", { XM, EXx }, 0 },
4085   },
4086
4087   /* PREFIX_0FD6 */
4088   {
4089     { Bad_Opcode },
4090     { "movq2dq",{ XM, MS }, 0 },
4091     { "movq",   { EXqS, XM }, 0 },
4092     { "movdq2q",{ MX, XS }, 0 },
4093   },
4094
4095   /* PREFIX_0FE6 */
4096   {
4097     { Bad_Opcode },
4098     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4099     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4100     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4101   },
4102
4103   /* PREFIX_0FE7 */
4104   {
4105     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4106     { Bad_Opcode },
4107     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4108   },
4109
4110   /* PREFIX_0FF0 */
4111   {
4112     { Bad_Opcode },
4113     { Bad_Opcode },
4114     { Bad_Opcode },
4115     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4116   },
4117
4118   /* PREFIX_0FF7 */
4119   {
4120     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4121     { Bad_Opcode },
4122     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4123   },
4124
4125   /* PREFIX_0F3810 */
4126   {
4127     { Bad_Opcode },
4128     { Bad_Opcode },
4129     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4130   },
4131
4132   /* PREFIX_0F3814 */
4133   {
4134     { Bad_Opcode },
4135     { Bad_Opcode },
4136     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4137   },
4138
4139   /* PREFIX_0F3815 */
4140   {
4141     { Bad_Opcode },
4142     { Bad_Opcode },
4143     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4144   },
4145
4146   /* PREFIX_0F3817 */
4147   {
4148     { Bad_Opcode },
4149     { Bad_Opcode },
4150     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4151   },
4152
4153   /* PREFIX_0F3820 */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4158   },
4159
4160   /* PREFIX_0F3821 */
4161   {
4162     { Bad_Opcode },
4163     { Bad_Opcode },
4164     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4165   },
4166
4167   /* PREFIX_0F3822 */
4168   {
4169     { Bad_Opcode },
4170     { Bad_Opcode },
4171     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4172   },
4173
4174   /* PREFIX_0F3823 */
4175   {
4176     { Bad_Opcode },
4177     { Bad_Opcode },
4178     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4179   },
4180
4181   /* PREFIX_0F3824 */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4186   },
4187
4188   /* PREFIX_0F3825 */
4189   {
4190     { Bad_Opcode },
4191     { Bad_Opcode },
4192     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4193   },
4194
4195   /* PREFIX_0F3828 */
4196   {
4197     { Bad_Opcode },
4198     { Bad_Opcode },
4199     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4200   },
4201
4202   /* PREFIX_0F3829 */
4203   {
4204     { Bad_Opcode },
4205     { Bad_Opcode },
4206     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4207   },
4208
4209   /* PREFIX_0F382A */
4210   {
4211     { Bad_Opcode },
4212     { Bad_Opcode },
4213     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4214   },
4215
4216   /* PREFIX_0F382B */
4217   {
4218     { Bad_Opcode },
4219     { Bad_Opcode },
4220     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4221   },
4222
4223   /* PREFIX_0F3830 */
4224   {
4225     { Bad_Opcode },
4226     { Bad_Opcode },
4227     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4228   },
4229
4230   /* PREFIX_0F3831 */
4231   {
4232     { Bad_Opcode },
4233     { Bad_Opcode },
4234     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4235   },
4236
4237   /* PREFIX_0F3832 */
4238   {
4239     { Bad_Opcode },
4240     { Bad_Opcode },
4241     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4242   },
4243
4244   /* PREFIX_0F3833 */
4245   {
4246     { Bad_Opcode },
4247     { Bad_Opcode },
4248     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4249   },
4250
4251   /* PREFIX_0F3834 */
4252   {
4253     { Bad_Opcode },
4254     { Bad_Opcode },
4255     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4256   },
4257
4258   /* PREFIX_0F3835 */
4259   {
4260     { Bad_Opcode },
4261     { Bad_Opcode },
4262     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4263   },
4264
4265   /* PREFIX_0F3837 */
4266   {
4267     { Bad_Opcode },
4268     { Bad_Opcode },
4269     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4270   },
4271
4272   /* PREFIX_0F3838 */
4273   {
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4277   },
4278
4279   /* PREFIX_0F3839 */
4280   {
4281     { Bad_Opcode },
4282     { Bad_Opcode },
4283     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4284   },
4285
4286   /* PREFIX_0F383A */
4287   {
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4291   },
4292
4293   /* PREFIX_0F383B */
4294   {
4295     { Bad_Opcode },
4296     { Bad_Opcode },
4297     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4298   },
4299
4300   /* PREFIX_0F383C */
4301   {
4302     { Bad_Opcode },
4303     { Bad_Opcode },
4304     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4305   },
4306
4307   /* PREFIX_0F383D */
4308   {
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4312   },
4313
4314   /* PREFIX_0F383E */
4315   {
4316     { Bad_Opcode },
4317     { Bad_Opcode },
4318     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4319   },
4320
4321   /* PREFIX_0F383F */
4322   {
4323     { Bad_Opcode },
4324     { Bad_Opcode },
4325     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4326   },
4327
4328   /* PREFIX_0F3840 */
4329   {
4330     { Bad_Opcode },
4331     { Bad_Opcode },
4332     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4333   },
4334
4335   /* PREFIX_0F3841 */
4336   {
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4340   },
4341
4342   /* PREFIX_0F3880 */
4343   {
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4347   },
4348
4349   /* PREFIX_0F3881 */
4350   {
4351     { Bad_Opcode },
4352     { Bad_Opcode },
4353     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F3882 */
4357   {
4358     { Bad_Opcode },
4359     { Bad_Opcode },
4360     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F38C8 */
4364   {
4365     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F38C9 */
4369   {
4370     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F38CA */
4374   {
4375     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F38CB */
4379   {
4380     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F38CC */
4384   {
4385     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38CD */
4389   {
4390     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F38CF */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F38DB */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4405   },
4406
4407   /* PREFIX_0F38DC */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F38DD */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4419   },
4420
4421   /* PREFIX_0F38DE */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F38DF */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4433   },
4434
4435   /* PREFIX_0F38F0 */
4436   {
4437     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4438     { Bad_Opcode },
4439     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4440     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4441   },
4442
4443   /* PREFIX_0F38F1 */
4444   {
4445     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4446     { Bad_Opcode },
4447     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4448     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4449   },
4450
4451   /* PREFIX_0F38F5 */
4452   {
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4456   },
4457
4458   /* PREFIX_0F38F6 */
4459   {
4460     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4461     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4462     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4463     { Bad_Opcode },
4464   },
4465
4466   /* PREFIX_0F38F8 */
4467   {
4468     { Bad_Opcode },
4469     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4470     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4471     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4472   },
4473
4474   /* PREFIX_0F38F9 */
4475   {
4476     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4477   },
4478
4479   /* PREFIX_0F3A08 */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4484   },
4485
4486   /* PREFIX_0F3A09 */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F3A0A */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F3A0B */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F3A0C */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_0F3A0D */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4519   },
4520
4521   /* PREFIX_0F3A0E */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4526   },
4527
4528   /* PREFIX_0F3A14 */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4533   },
4534
4535   /* PREFIX_0F3A15 */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4540   },
4541
4542   /* PREFIX_0F3A16 */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4547   },
4548
4549   /* PREFIX_0F3A17 */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4554   },
4555
4556   /* PREFIX_0F3A20 */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4561   },
4562
4563   /* PREFIX_0F3A21 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4568   },
4569
4570   /* PREFIX_0F3A22 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4575   },
4576
4577   /* PREFIX_0F3A40 */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4582   },
4583
4584   /* PREFIX_0F3A41 */
4585   {
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4589   },
4590
4591   /* PREFIX_0F3A42 */
4592   {
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4596   },
4597
4598   /* PREFIX_0F3A44 */
4599   {
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4603   },
4604
4605   /* PREFIX_0F3A60 */
4606   {
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4610   },
4611
4612   /* PREFIX_0F3A61 */
4613   {
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4617   },
4618
4619   /* PREFIX_0F3A62 */
4620   {
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4624   },
4625
4626   /* PREFIX_0F3A63 */
4627   {
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4631   },
4632
4633   /* PREFIX_0F3ACC */
4634   {
4635     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4636   },
4637
4638   /* PREFIX_0F3ACE */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4643   },
4644
4645   /* PREFIX_0F3ACF */
4646   {
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4650   },
4651
4652   /* PREFIX_0F3ADF */
4653   {
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4657   },
4658
4659   /* PREFIX_VEX_0F10 */
4660   {
4661     { "vmovups",        { XM, EXx }, 0 },
4662     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4663     { "vmovupd",        { XM, EXx }, 0 },
4664     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4665   },
4666
4667   /* PREFIX_VEX_0F11 */
4668   {
4669     { "vmovups",        { EXxS, XM }, 0 },
4670     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4671     { "vmovupd",        { EXxS, XM }, 0 },
4672     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4673   },
4674
4675   /* PREFIX_VEX_0F12 */
4676   {
4677     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4678     { "vmovsldup",      { XM, EXx }, 0 },
4679     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4680     { "vmovddup",       { XM, EXymmq }, 0 },
4681   },
4682
4683   /* PREFIX_VEX_0F16 */
4684   {
4685     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4686     { "vmovshdup",      { XM, EXx }, 0 },
4687     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4688   },
4689
4690   /* PREFIX_VEX_0F2A */
4691   {
4692     { Bad_Opcode },
4693     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4694     { Bad_Opcode },
4695     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4696   },
4697
4698   /* PREFIX_VEX_0F2C */
4699   {
4700     { Bad_Opcode },
4701     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4702     { Bad_Opcode },
4703     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4704   },
4705
4706   /* PREFIX_VEX_0F2D */
4707   {
4708     { Bad_Opcode },
4709     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4710     { Bad_Opcode },
4711     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4712   },
4713
4714   /* PREFIX_VEX_0F2E */
4715   {
4716     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4717     { Bad_Opcode },
4718     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4719   },
4720
4721   /* PREFIX_VEX_0F2F */
4722   {
4723     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4724     { Bad_Opcode },
4725     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4726   },
4727
4728   /* PREFIX_VEX_0F41 */
4729   {
4730     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4731     { Bad_Opcode },
4732     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4733   },
4734
4735   /* PREFIX_VEX_0F42 */
4736   {
4737     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4738     { Bad_Opcode },
4739     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4740   },
4741
4742   /* PREFIX_VEX_0F44 */
4743   {
4744     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4745     { Bad_Opcode },
4746     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4747   },
4748
4749   /* PREFIX_VEX_0F45 */
4750   {
4751     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4752     { Bad_Opcode },
4753     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4754   },
4755
4756   /* PREFIX_VEX_0F46 */
4757   {
4758     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4759     { Bad_Opcode },
4760     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4761   },
4762
4763   /* PREFIX_VEX_0F47 */
4764   {
4765     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4766     { Bad_Opcode },
4767     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4768   },
4769
4770   /* PREFIX_VEX_0F4A */
4771   {
4772     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4773     { Bad_Opcode },
4774     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4775   },
4776
4777   /* PREFIX_VEX_0F4B */
4778   {
4779     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4780     { Bad_Opcode },
4781     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4782   },
4783
4784   /* PREFIX_VEX_0F51 */
4785   {
4786     { "vsqrtps",        { XM, EXx }, 0 },
4787     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4788     { "vsqrtpd",        { XM, EXx }, 0 },
4789     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4790   },
4791
4792   /* PREFIX_VEX_0F52 */
4793   {
4794     { "vrsqrtps",       { XM, EXx }, 0 },
4795     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4796   },
4797
4798   /* PREFIX_VEX_0F53 */
4799   {
4800     { "vrcpps",         { XM, EXx }, 0 },
4801     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4802   },
4803
4804   /* PREFIX_VEX_0F58 */
4805   {
4806     { "vaddps",         { XM, Vex, EXx }, 0 },
4807     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4808     { "vaddpd",         { XM, Vex, EXx }, 0 },
4809     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4810   },
4811
4812   /* PREFIX_VEX_0F59 */
4813   {
4814     { "vmulps",         { XM, Vex, EXx }, 0 },
4815     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4816     { "vmulpd",         { XM, Vex, EXx }, 0 },
4817     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4818   },
4819
4820   /* PREFIX_VEX_0F5A */
4821   {
4822     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4823     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4824     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4825     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4826   },
4827
4828   /* PREFIX_VEX_0F5B */
4829   {
4830     { "vcvtdq2ps",      { XM, EXx }, 0 },
4831     { "vcvttps2dq",     { XM, EXx }, 0 },
4832     { "vcvtps2dq",      { XM, EXx }, 0 },
4833   },
4834
4835   /* PREFIX_VEX_0F5C */
4836   {
4837     { "vsubps",         { XM, Vex, EXx }, 0 },
4838     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4839     { "vsubpd",         { XM, Vex, EXx }, 0 },
4840     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4841   },
4842
4843   /* PREFIX_VEX_0F5D */
4844   {
4845     { "vminps",         { XM, Vex, EXx }, 0 },
4846     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4847     { "vminpd",         { XM, Vex, EXx }, 0 },
4848     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4849   },
4850
4851   /* PREFIX_VEX_0F5E */
4852   {
4853     { "vdivps",         { XM, Vex, EXx }, 0 },
4854     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4855     { "vdivpd",         { XM, Vex, EXx }, 0 },
4856     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4857   },
4858
4859   /* PREFIX_VEX_0F5F */
4860   {
4861     { "vmaxps",         { XM, Vex, EXx }, 0 },
4862     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4863     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4864     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4865   },
4866
4867   /* PREFIX_VEX_0F60 */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4872   },
4873
4874   /* PREFIX_VEX_0F61 */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4879   },
4880
4881   /* PREFIX_VEX_0F62 */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4886   },
4887
4888   /* PREFIX_VEX_0F63 */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4893   },
4894
4895   /* PREFIX_VEX_0F64 */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4900   },
4901
4902   /* PREFIX_VEX_0F65 */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4907   },
4908
4909   /* PREFIX_VEX_0F66 */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4914   },
4915
4916   /* PREFIX_VEX_0F67 */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4921   },
4922
4923   /* PREFIX_VEX_0F68 */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4928   },
4929
4930   /* PREFIX_VEX_0F69 */
4931   {
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4935   },
4936
4937   /* PREFIX_VEX_0F6A */
4938   {
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4942   },
4943
4944   /* PREFIX_VEX_0F6B */
4945   {
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4949   },
4950
4951   /* PREFIX_VEX_0F6C */
4952   {
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4956   },
4957
4958   /* PREFIX_VEX_0F6D */
4959   {
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4963   },
4964
4965   /* PREFIX_VEX_0F6E */
4966   {
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4970   },
4971
4972   /* PREFIX_VEX_0F6F */
4973   {
4974     { Bad_Opcode },
4975     { "vmovdqu",        { XM, EXx }, 0 },
4976     { "vmovdqa",        { XM, EXx }, 0 },
4977   },
4978
4979   /* PREFIX_VEX_0F70 */
4980   {
4981     { Bad_Opcode },
4982     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4983     { "vpshufd",        { XM, EXx, Ib }, 0 },
4984     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4985   },
4986
4987   /* PREFIX_VEX_0F71_REG_2 */
4988   {
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4992   },
4993
4994   /* PREFIX_VEX_0F71_REG_4 */
4995   {
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { "vpsraw",         { Vex, XS, Ib }, 0 },
4999   },
5000
5001   /* PREFIX_VEX_0F71_REG_6 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { "vpsllw",         { Vex, XS, Ib }, 0 },
5006   },
5007
5008   /* PREFIX_VEX_0F72_REG_2 */
5009   {
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { "vpsrld",         { Vex, XS, Ib }, 0 },
5013   },
5014
5015   /* PREFIX_VEX_0F72_REG_4 */
5016   {
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { "vpsrad",         { Vex, XS, Ib }, 0 },
5020   },
5021
5022   /* PREFIX_VEX_0F72_REG_6 */
5023   {
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { "vpslld",         { Vex, XS, Ib }, 0 },
5027   },
5028
5029   /* PREFIX_VEX_0F73_REG_2 */
5030   {
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5034   },
5035
5036   /* PREFIX_VEX_0F73_REG_3 */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5041   },
5042
5043   /* PREFIX_VEX_0F73_REG_6 */
5044   {
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { "vpsllq",         { Vex, XS, Ib }, 0 },
5048   },
5049
5050   /* PREFIX_VEX_0F73_REG_7 */
5051   {
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { "vpslldq",        { Vex, XS, Ib }, 0 },
5055   },
5056
5057   /* PREFIX_VEX_0F74 */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5062   },
5063
5064   /* PREFIX_VEX_0F75 */
5065   {
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5069   },
5070
5071   /* PREFIX_VEX_0F76 */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5076   },
5077
5078   /* PREFIX_VEX_0F77 */
5079   {
5080     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5081   },
5082
5083   /* PREFIX_VEX_0F7C */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5088     { "vhaddps",        { XM, Vex, EXx }, 0 },
5089   },
5090
5091   /* PREFIX_VEX_0F7D */
5092   {
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5096     { "vhsubps",        { XM, Vex, EXx }, 0 },
5097   },
5098
5099   /* PREFIX_VEX_0F7E */
5100   {
5101     { Bad_Opcode },
5102     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5103     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5104   },
5105
5106   /* PREFIX_VEX_0F7F */
5107   {
5108     { Bad_Opcode },
5109     { "vmovdqu",        { EXxS, XM }, 0 },
5110     { "vmovdqa",        { EXxS, XM }, 0 },
5111   },
5112
5113   /* PREFIX_VEX_0F90 */
5114   {
5115     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5116     { Bad_Opcode },
5117     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5118   },
5119
5120   /* PREFIX_VEX_0F91 */
5121   {
5122     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5123     { Bad_Opcode },
5124     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5125   },
5126
5127   /* PREFIX_VEX_0F92 */
5128   {
5129     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5130     { Bad_Opcode },
5131     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5132     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5133   },
5134
5135   /* PREFIX_VEX_0F93 */
5136   {
5137     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5138     { Bad_Opcode },
5139     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5140     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5141   },
5142
5143   /* PREFIX_VEX_0F98 */
5144   {
5145     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5146     { Bad_Opcode },
5147     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0F99 */
5151   {
5152     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5153     { Bad_Opcode },
5154     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0FC2 */
5158   {
5159     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5160     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5161     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5162     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5163   },
5164
5165   /* PREFIX_VEX_0FC4 */
5166   {
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5170   },
5171
5172   /* PREFIX_VEX_0FC5 */
5173   {
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5177   },
5178
5179   /* PREFIX_VEX_0FD0 */
5180   {
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5184     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5185   },
5186
5187   /* PREFIX_VEX_0FD1 */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5192   },
5193
5194   /* PREFIX_VEX_0FD2 */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5199   },
5200
5201   /* PREFIX_VEX_0FD3 */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5206   },
5207
5208   /* PREFIX_VEX_0FD4 */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { "vpaddq",         { XM, Vex, EXx }, 0 },
5213   },
5214
5215   /* PREFIX_VEX_0FD5 */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { "vpmullw",        { XM, Vex, EXx }, 0 },
5220   },
5221
5222   /* PREFIX_VEX_0FD6 */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5227   },
5228
5229   /* PREFIX_VEX_0FD7 */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5234   },
5235
5236   /* PREFIX_VEX_0FD8 */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5241   },
5242
5243   /* PREFIX_VEX_0FD9 */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5248   },
5249
5250   /* PREFIX_VEX_0FDA */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { "vpminub",        { XM, Vex, EXx }, 0 },
5255   },
5256
5257   /* PREFIX_VEX_0FDB */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { "vpand",          { XM, Vex, EXx }, 0 },
5262   },
5263
5264   /* PREFIX_VEX_0FDC */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5269   },
5270
5271   /* PREFIX_VEX_0FDD */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5276   },
5277
5278   /* PREFIX_VEX_0FDE */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5283   },
5284
5285   /* PREFIX_VEX_0FDF */
5286   {
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { "vpandn",         { XM, Vex, EXx }, 0 },
5290   },
5291
5292   /* PREFIX_VEX_0FE0 */
5293   {
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { "vpavgb",         { XM, Vex, EXx }, 0 },
5297   },
5298
5299   /* PREFIX_VEX_0FE1 */
5300   {
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5304   },
5305
5306   /* PREFIX_VEX_0FE2 */
5307   {
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5311   },
5312
5313   /* PREFIX_VEX_0FE3 */
5314   {
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { "vpavgw",         { XM, Vex, EXx }, 0 },
5318   },
5319
5320   /* PREFIX_VEX_0FE4 */
5321   {
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5325   },
5326
5327   /* PREFIX_VEX_0FE5 */
5328   {
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5332   },
5333
5334   /* PREFIX_VEX_0FE6 */
5335   {
5336     { Bad_Opcode },
5337     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5338     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5339     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5340   },
5341
5342   /* PREFIX_VEX_0FE7 */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5347   },
5348
5349   /* PREFIX_VEX_0FE8 */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5354   },
5355
5356   /* PREFIX_VEX_0FE9 */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5361   },
5362
5363   /* PREFIX_VEX_0FEA */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { "vpminsw",        { XM, Vex, EXx }, 0 },
5368   },
5369
5370   /* PREFIX_VEX_0FEB */
5371   {
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { "vpor",           { XM, Vex, EXx }, 0 },
5375   },
5376
5377   /* PREFIX_VEX_0FEC */
5378   {
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5382   },
5383
5384   /* PREFIX_VEX_0FED */
5385   {
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5389   },
5390
5391   /* PREFIX_VEX_0FEE */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5396   },
5397
5398   /* PREFIX_VEX_0FEF */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { "vpxor",          { XM, Vex, EXx }, 0 },
5403   },
5404
5405   /* PREFIX_VEX_0FF0 */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5411   },
5412
5413   /* PREFIX_VEX_0FF1 */
5414   {
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5418   },
5419
5420   /* PREFIX_VEX_0FF2 */
5421   {
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5425   },
5426
5427   /* PREFIX_VEX_0FF3 */
5428   {
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5432   },
5433
5434   /* PREFIX_VEX_0FF4 */
5435   {
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5439   },
5440
5441   /* PREFIX_VEX_0FF5 */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5446   },
5447
5448   /* PREFIX_VEX_0FF6 */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5453   },
5454
5455   /* PREFIX_VEX_0FF7 */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5460   },
5461
5462   /* PREFIX_VEX_0FF8 */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { "vpsubb",         { XM, Vex, EXx }, 0 },
5467   },
5468
5469   /* PREFIX_VEX_0FF9 */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { "vpsubw",         { XM, Vex, EXx }, 0 },
5474   },
5475
5476   /* PREFIX_VEX_0FFA */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { "vpsubd",         { XM, Vex, EXx }, 0 },
5481   },
5482
5483   /* PREFIX_VEX_0FFB */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { "vpsubq",         { XM, Vex, EXx }, 0 },
5488   },
5489
5490   /* PREFIX_VEX_0FFC */
5491   {
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { "vpaddb",         { XM, Vex, EXx }, 0 },
5495   },
5496
5497   /* PREFIX_VEX_0FFD */
5498   {
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { "vpaddw",         { XM, Vex, EXx }, 0 },
5502   },
5503
5504   /* PREFIX_VEX_0FFE */
5505   {
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { "vpaddd",         { XM, Vex, EXx }, 0 },
5509   },
5510
5511   /* PREFIX_VEX_0F3800 */
5512   {
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { "vpshufb",        { XM, Vex, EXx }, 0 },
5516   },
5517
5518   /* PREFIX_VEX_0F3801 */
5519   {
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { "vphaddw",        { XM, Vex, EXx }, 0 },
5523   },
5524
5525   /* PREFIX_VEX_0F3802 */
5526   {
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { "vphaddd",        { XM, Vex, EXx }, 0 },
5530   },
5531
5532   /* PREFIX_VEX_0F3803 */
5533   {
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5537   },
5538
5539   /* PREFIX_VEX_0F3804 */
5540   {
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5544   },
5545
5546   /* PREFIX_VEX_0F3805 */
5547   {
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { "vphsubw",        { XM, Vex, EXx }, 0 },
5551   },
5552
5553   /* PREFIX_VEX_0F3806 */
5554   {
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { "vphsubd",        { XM, Vex, EXx }, 0 },
5558   },
5559
5560   /* PREFIX_VEX_0F3807 */
5561   {
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5565   },
5566
5567   /* PREFIX_VEX_0F3808 */
5568   {
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { "vpsignb",        { XM, Vex, EXx }, 0 },
5572   },
5573
5574   /* PREFIX_VEX_0F3809 */
5575   {
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { "vpsignw",        { XM, Vex, EXx }, 0 },
5579   },
5580
5581   /* PREFIX_VEX_0F380A */
5582   {
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { "vpsignd",        { XM, Vex, EXx }, 0 },
5586   },
5587
5588   /* PREFIX_VEX_0F380B */
5589   {
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5593   },
5594
5595   /* PREFIX_VEX_0F380C */
5596   {
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5600   },
5601
5602   /* PREFIX_VEX_0F380D */
5603   {
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5607   },
5608
5609   /* PREFIX_VEX_0F380E */
5610   {
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5614   },
5615
5616   /* PREFIX_VEX_0F380F */
5617   {
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5621   },
5622
5623   /* PREFIX_VEX_0F3813 */
5624   {
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5628   },
5629
5630   /* PREFIX_VEX_0F3816 */
5631   {
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5635   },
5636
5637   /* PREFIX_VEX_0F3817 */
5638   {
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { "vptest",         { XM, EXx }, 0 },
5642   },
5643
5644   /* PREFIX_VEX_0F3818 */
5645   {
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5649   },
5650
5651   /* PREFIX_VEX_0F3819 */
5652   {
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5656   },
5657
5658   /* PREFIX_VEX_0F381A */
5659   {
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5663   },
5664
5665   /* PREFIX_VEX_0F381C */
5666   {
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { "vpabsb",         { XM, EXx }, 0 },
5670   },
5671
5672   /* PREFIX_VEX_0F381D */
5673   {
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { "vpabsw",         { XM, EXx }, 0 },
5677   },
5678
5679   /* PREFIX_VEX_0F381E */
5680   {
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { "vpabsd",         { XM, EXx }, 0 },
5684   },
5685
5686   /* PREFIX_VEX_0F3820 */
5687   {
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5691   },
5692
5693   /* PREFIX_VEX_0F3821 */
5694   {
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5698   },
5699
5700   /* PREFIX_VEX_0F3822 */
5701   {
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5705   },
5706
5707   /* PREFIX_VEX_0F3823 */
5708   {
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5712   },
5713
5714   /* PREFIX_VEX_0F3824 */
5715   {
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5719   },
5720
5721   /* PREFIX_VEX_0F3825 */
5722   {
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5726   },
5727
5728   /* PREFIX_VEX_0F3828 */
5729   {
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5733   },
5734
5735   /* PREFIX_VEX_0F3829 */
5736   {
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5740   },
5741
5742   /* PREFIX_VEX_0F382A */
5743   {
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5747   },
5748
5749   /* PREFIX_VEX_0F382B */
5750   {
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5754   },
5755
5756   /* PREFIX_VEX_0F382C */
5757   {
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5761   },
5762
5763   /* PREFIX_VEX_0F382D */
5764   {
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5768   },
5769
5770   /* PREFIX_VEX_0F382E */
5771   {
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5775   },
5776
5777   /* PREFIX_VEX_0F382F */
5778   {
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5782   },
5783
5784   /* PREFIX_VEX_0F3830 */
5785   {
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5789   },
5790
5791   /* PREFIX_VEX_0F3831 */
5792   {
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5796   },
5797
5798   /* PREFIX_VEX_0F3832 */
5799   {
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5803   },
5804
5805   /* PREFIX_VEX_0F3833 */
5806   {
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5810   },
5811
5812   /* PREFIX_VEX_0F3834 */
5813   {
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5817   },
5818
5819   /* PREFIX_VEX_0F3835 */
5820   {
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5824   },
5825
5826   /* PREFIX_VEX_0F3836 */
5827   {
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5831   },
5832
5833   /* PREFIX_VEX_0F3837 */
5834   {
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5838   },
5839
5840   /* PREFIX_VEX_0F3838 */
5841   {
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { "vpminsb",        { XM, Vex, EXx }, 0 },
5845   },
5846
5847   /* PREFIX_VEX_0F3839 */
5848   {
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { "vpminsd",        { XM, Vex, EXx }, 0 },
5852   },
5853
5854   /* PREFIX_VEX_0F383A */
5855   {
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { "vpminuw",        { XM, Vex, EXx }, 0 },
5859   },
5860
5861   /* PREFIX_VEX_0F383B */
5862   {
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { "vpminud",        { XM, Vex, EXx }, 0 },
5866   },
5867
5868   /* PREFIX_VEX_0F383C */
5869   {
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5873   },
5874
5875   /* PREFIX_VEX_0F383D */
5876   {
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5880   },
5881
5882   /* PREFIX_VEX_0F383E */
5883   {
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5887   },
5888
5889   /* PREFIX_VEX_0F383F */
5890   {
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5894   },
5895
5896   /* PREFIX_VEX_0F3840 */
5897   {
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { "vpmulld",        { XM, Vex, EXx }, 0 },
5901   },
5902
5903   /* PREFIX_VEX_0F3841 */
5904   {
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5908   },
5909
5910   /* PREFIX_VEX_0F3845 */
5911   {
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5915   },
5916
5917   /* PREFIX_VEX_0F3846 */
5918   {
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5922   },
5923
5924   /* PREFIX_VEX_0F3847 */
5925   {
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5929   },
5930
5931   /* PREFIX_VEX_0F3858 */
5932   {
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5936   },
5937
5938   /* PREFIX_VEX_0F3859 */
5939   {
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5943   },
5944
5945   /* PREFIX_VEX_0F385A */
5946   {
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5950   },
5951
5952   /* PREFIX_VEX_0F3878 */
5953   {
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5957   },
5958
5959   /* PREFIX_VEX_0F3879 */
5960   {
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5964   },
5965
5966   /* PREFIX_VEX_0F388C */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5971   },
5972
5973   /* PREFIX_VEX_0F388E */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5978   },
5979
5980   /* PREFIX_VEX_0F3890 */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5985   },
5986
5987   /* PREFIX_VEX_0F3891 */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5992   },
5993
5994   /* PREFIX_VEX_0F3892 */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5999   },
6000
6001   /* PREFIX_VEX_0F3893 */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6006   },
6007
6008   /* PREFIX_VEX_0F3896 */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6013   },
6014
6015   /* PREFIX_VEX_0F3897 */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6020   },
6021
6022   /* PREFIX_VEX_0F3898 */
6023   {
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6027   },
6028
6029   /* PREFIX_VEX_0F3899 */
6030   {
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6034   },
6035
6036   /* PREFIX_VEX_0F389A */
6037   {
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6041   },
6042
6043   /* PREFIX_VEX_0F389B */
6044   {
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6048   },
6049
6050   /* PREFIX_VEX_0F389C */
6051   {
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6055   },
6056
6057   /* PREFIX_VEX_0F389D */
6058   {
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6062   },
6063
6064   /* PREFIX_VEX_0F389E */
6065   {
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6069   },
6070
6071   /* PREFIX_VEX_0F389F */
6072   {
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6076   },
6077
6078   /* PREFIX_VEX_0F38A6 */
6079   {
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6083     { Bad_Opcode },
6084   },
6085
6086   /* PREFIX_VEX_0F38A7 */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6091   },
6092
6093   /* PREFIX_VEX_0F38A8 */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6098   },
6099
6100   /* PREFIX_VEX_0F38A9 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6105   },
6106
6107   /* PREFIX_VEX_0F38AA */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6112   },
6113
6114   /* PREFIX_VEX_0F38AB */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6119   },
6120
6121   /* PREFIX_VEX_0F38AC */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6126   },
6127
6128   /* PREFIX_VEX_0F38AD */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6133   },
6134
6135   /* PREFIX_VEX_0F38AE */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6140   },
6141
6142   /* PREFIX_VEX_0F38AF */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6147   },
6148
6149   /* PREFIX_VEX_0F38B6 */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6154   },
6155
6156   /* PREFIX_VEX_0F38B7 */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6161   },
6162
6163   /* PREFIX_VEX_0F38B8 */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6168   },
6169
6170   /* PREFIX_VEX_0F38B9 */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6175   },
6176
6177   /* PREFIX_VEX_0F38BA */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6182   },
6183
6184   /* PREFIX_VEX_0F38BB */
6185   {
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6189   },
6190
6191   /* PREFIX_VEX_0F38BC */
6192   {
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6196   },
6197
6198   /* PREFIX_VEX_0F38BD */
6199   {
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6203   },
6204
6205   /* PREFIX_VEX_0F38BE */
6206   {
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6210   },
6211
6212   /* PREFIX_VEX_0F38BF */
6213   {
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6217   },
6218
6219   /* PREFIX_VEX_0F38CF */
6220   {
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6224   },
6225
6226   /* PREFIX_VEX_0F38DB */
6227   {
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6231   },
6232
6233   /* PREFIX_VEX_0F38DC */
6234   {
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { "vaesenc",        { XM, Vex, EXx }, 0 },
6238   },
6239
6240   /* PREFIX_VEX_0F38DD */
6241   {
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6245   },
6246
6247   /* PREFIX_VEX_0F38DE */
6248   {
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { "vaesdec",        { XM, Vex, EXx }, 0 },
6252   },
6253
6254   /* PREFIX_VEX_0F38DF */
6255   {
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6259   },
6260
6261   /* PREFIX_VEX_0F38F2 */
6262   {
6263     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6264   },
6265
6266   /* PREFIX_VEX_0F38F3_REG_1 */
6267   {
6268     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6269   },
6270
6271   /* PREFIX_VEX_0F38F3_REG_2 */
6272   {
6273     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6274   },
6275
6276   /* PREFIX_VEX_0F38F3_REG_3 */
6277   {
6278     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6279   },
6280
6281   /* PREFIX_VEX_0F38F5 */
6282   {
6283     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6284     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6285     { Bad_Opcode },
6286     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6287   },
6288
6289   /* PREFIX_VEX_0F38F6 */
6290   {
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6295   },
6296
6297   /* PREFIX_VEX_0F38F7 */
6298   {
6299     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6300     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6301     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6302     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6303   },
6304
6305   /* PREFIX_VEX_0F3A00 */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6310   },
6311
6312   /* PREFIX_VEX_0F3A01 */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6317   },
6318
6319   /* PREFIX_VEX_0F3A02 */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6324   },
6325
6326   /* PREFIX_VEX_0F3A04 */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6331   },
6332
6333   /* PREFIX_VEX_0F3A05 */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6338   },
6339
6340   /* PREFIX_VEX_0F3A06 */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6345   },
6346
6347   /* PREFIX_VEX_0F3A08 */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { "vroundps",       { XM, EXx, Ib }, 0 },
6352   },
6353
6354   /* PREFIX_VEX_0F3A09 */
6355   {
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { "vroundpd",       { XM, EXx, Ib }, 0 },
6359   },
6360
6361   /* PREFIX_VEX_0F3A0A */
6362   {
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6366   },
6367
6368   /* PREFIX_VEX_0F3A0B */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6373   },
6374
6375   /* PREFIX_VEX_0F3A0C */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6380   },
6381
6382   /* PREFIX_VEX_0F3A0D */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6387   },
6388
6389   /* PREFIX_VEX_0F3A0E */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6394   },
6395
6396   /* PREFIX_VEX_0F3A0F */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6401   },
6402
6403   /* PREFIX_VEX_0F3A14 */
6404   {
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6408   },
6409
6410   /* PREFIX_VEX_0F3A15 */
6411   {
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6415   },
6416
6417   /* PREFIX_VEX_0F3A16 */
6418   {
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6422   },
6423
6424   /* PREFIX_VEX_0F3A17 */
6425   {
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6429   },
6430
6431   /* PREFIX_VEX_0F3A18 */
6432   {
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6436   },
6437
6438   /* PREFIX_VEX_0F3A19 */
6439   {
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6443   },
6444
6445   /* PREFIX_VEX_0F3A1D */
6446   {
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6450   },
6451
6452   /* PREFIX_VEX_0F3A20 */
6453   {
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6457   },
6458
6459   /* PREFIX_VEX_0F3A21 */
6460   {
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6464   },
6465
6466   /* PREFIX_VEX_0F3A22 */
6467   {
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6471   },
6472
6473   /* PREFIX_VEX_0F3A30 */
6474   {
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6478   },
6479
6480   /* PREFIX_VEX_0F3A31 */
6481   {
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6485   },
6486
6487   /* PREFIX_VEX_0F3A32 */
6488   {
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6492   },
6493
6494   /* PREFIX_VEX_0F3A33 */
6495   {
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6499   },
6500
6501   /* PREFIX_VEX_0F3A38 */
6502   {
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6506   },
6507
6508   /* PREFIX_VEX_0F3A39 */
6509   {
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6513   },
6514
6515   /* PREFIX_VEX_0F3A40 */
6516   {
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6520   },
6521
6522   /* PREFIX_VEX_0F3A41 */
6523   {
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6527   },
6528
6529   /* PREFIX_VEX_0F3A42 */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6534   },
6535
6536   /* PREFIX_VEX_0F3A44 */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6541   },
6542
6543   /* PREFIX_VEX_0F3A46 */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6548   },
6549
6550   /* PREFIX_VEX_0F3A48 */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6555   },
6556
6557   /* PREFIX_VEX_0F3A49 */
6558   {
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6562   },
6563
6564   /* PREFIX_VEX_0F3A4A */
6565   {
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6569   },
6570
6571   /* PREFIX_VEX_0F3A4B */
6572   {
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6576   },
6577
6578   /* PREFIX_VEX_0F3A4C */
6579   {
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6583   },
6584
6585   /* PREFIX_VEX_0F3A5C */
6586   {
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6590   },
6591
6592   /* PREFIX_VEX_0F3A5D */
6593   {
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6597   },
6598
6599   /* PREFIX_VEX_0F3A5E */
6600   {
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6604   },
6605
6606   /* PREFIX_VEX_0F3A5F */
6607   {
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6611   },
6612
6613   /* PREFIX_VEX_0F3A60 */
6614   {
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6618     { Bad_Opcode },
6619   },
6620
6621   /* PREFIX_VEX_0F3A61 */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6626   },
6627
6628   /* PREFIX_VEX_0F3A62 */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6633   },
6634
6635   /* PREFIX_VEX_0F3A63 */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3A68 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6647   },
6648
6649   /* PREFIX_VEX_0F3A69 */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6654   },
6655
6656   /* PREFIX_VEX_0F3A6A */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6661   },
6662
6663   /* PREFIX_VEX_0F3A6B */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6668   },
6669
6670   /* PREFIX_VEX_0F3A6C */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6675   },
6676
6677   /* PREFIX_VEX_0F3A6D */
6678   {
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6682   },
6683
6684   /* PREFIX_VEX_0F3A6E */
6685   {
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6689   },
6690
6691   /* PREFIX_VEX_0F3A6F */
6692   {
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6696   },
6697
6698   /* PREFIX_VEX_0F3A78 */
6699   {
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6703   },
6704
6705   /* PREFIX_VEX_0F3A79 */
6706   {
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6710   },
6711
6712   /* PREFIX_VEX_0F3A7A */
6713   {
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6717   },
6718
6719   /* PREFIX_VEX_0F3A7B */
6720   {
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6724   },
6725
6726   /* PREFIX_VEX_0F3A7C */
6727   {
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6731     { Bad_Opcode },
6732   },
6733
6734   /* PREFIX_VEX_0F3A7D */
6735   {
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6739   },
6740
6741   /* PREFIX_VEX_0F3A7E */
6742   {
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6746   },
6747
6748   /* PREFIX_VEX_0F3A7F */
6749   {
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6753   },
6754
6755   /* PREFIX_VEX_0F3ACE */
6756   {
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6760   },
6761
6762   /* PREFIX_VEX_0F3ACF */
6763   {
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6767   },
6768
6769   /* PREFIX_VEX_0F3ADF */
6770   {
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6774   },
6775
6776   /* PREFIX_VEX_0F3AF0 */
6777   {
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6782   },
6783
6784 #include "i386-dis-evex-prefix.h"
6785 };
6786
6787 static const struct dis386 x86_64_table[][2] = {
6788   /* X86_64_06 */
6789   {
6790     { "pushP", { es }, 0 },
6791   },
6792
6793   /* X86_64_07 */
6794   {
6795     { "popP", { es }, 0 },
6796   },
6797
6798   /* X86_64_0D */
6799   {
6800     { "pushP", { cs }, 0 },
6801   },
6802
6803   /* X86_64_16 */
6804   {
6805     { "pushP", { ss }, 0 },
6806   },
6807
6808   /* X86_64_17 */
6809   {
6810     { "popP", { ss }, 0 },
6811   },
6812
6813   /* X86_64_1E */
6814   {
6815     { "pushP", { ds }, 0 },
6816   },
6817
6818   /* X86_64_1F */
6819   {
6820     { "popP", { ds }, 0 },
6821   },
6822
6823   /* X86_64_27 */
6824   {
6825     { "daa", { XX }, 0 },
6826   },
6827
6828   /* X86_64_2F */
6829   {
6830     { "das", { XX }, 0 },
6831   },
6832
6833   /* X86_64_37 */
6834   {
6835     { "aaa", { XX }, 0 },
6836   },
6837
6838   /* X86_64_3F */
6839   {
6840     { "aas", { XX }, 0 },
6841   },
6842
6843   /* X86_64_60 */
6844   {
6845     { "pushaP", { XX }, 0 },
6846   },
6847
6848   /* X86_64_61 */
6849   {
6850     { "popaP", { XX }, 0 },
6851   },
6852
6853   /* X86_64_62 */
6854   {
6855     { MOD_TABLE (MOD_62_32BIT) },
6856     { EVEX_TABLE (EVEX_0F) },
6857   },
6858
6859   /* X86_64_63 */
6860   {
6861     { "arpl", { Ew, Gw }, 0 },
6862     { "movs{lq|xd}", { Gv, Ed }, 0 },
6863   },
6864
6865   /* X86_64_6D */
6866   {
6867     { "ins{R|}", { Yzr, indirDX }, 0 },
6868     { "ins{G|}", { Yzr, indirDX }, 0 },
6869   },
6870
6871   /* X86_64_6F */
6872   {
6873     { "outs{R|}", { indirDXr, Xz }, 0 },
6874     { "outs{G|}", { indirDXr, Xz }, 0 },
6875   },
6876
6877   /* X86_64_82 */
6878   {
6879     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6880     { REG_TABLE (REG_80) },
6881   },
6882
6883   /* X86_64_9A */
6884   {
6885     { "Jcall{T|}", { Ap }, 0 },
6886   },
6887
6888   /* X86_64_C4 */
6889   {
6890     { MOD_TABLE (MOD_C4_32BIT) },
6891     { VEX_C4_TABLE (VEX_0F) },
6892   },
6893
6894   /* X86_64_C5 */
6895   {
6896     { MOD_TABLE (MOD_C5_32BIT) },
6897     { VEX_C5_TABLE (VEX_0F) },
6898   },
6899
6900   /* X86_64_CE */
6901   {
6902     { "into", { XX }, 0 },
6903   },
6904
6905   /* X86_64_D4 */
6906   {
6907     { "aam", { Ib }, 0 },
6908   },
6909
6910   /* X86_64_D5 */
6911   {
6912     { "aad", { Ib }, 0 },
6913   },
6914
6915   /* X86_64_E8 */
6916   {
6917     { "callP",          { Jv, BND }, 0 },
6918     { "call@",          { Jv, BND }, 0 }
6919   },
6920
6921   /* X86_64_E9 */
6922   {
6923     { "jmpP",           { Jv, BND }, 0 },
6924     { "jmp@",           { Jv, BND }, 0 }
6925   },
6926
6927   /* X86_64_EA */
6928   {
6929     { "Jjmp{T|}", { Ap }, 0 },
6930   },
6931
6932   /* X86_64_0F01_REG_0 */
6933   {
6934     { "sgdt{Q|IQ}", { M }, 0 },
6935     { "sgdt", { M }, 0 },
6936   },
6937
6938   /* X86_64_0F01_REG_1 */
6939   {
6940     { "sidt{Q|IQ}", { M }, 0 },
6941     { "sidt", { M }, 0 },
6942   },
6943
6944   /* X86_64_0F01_REG_2 */
6945   {
6946     { "lgdt{Q|Q}", { M }, 0 },
6947     { "lgdt", { M }, 0 },
6948   },
6949
6950   /* X86_64_0F01_REG_3 */
6951   {
6952     { "lidt{Q|Q}", { M }, 0 },
6953     { "lidt", { M }, 0 },
6954   },
6955 };
6956
6957 static const struct dis386 three_byte_table[][256] = {
6958
6959   /* THREE_BYTE_0F38 */
6960   {
6961     /* 00 */
6962     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6963     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6964     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6965     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6966     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6967     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6968     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6969     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6970     /* 08 */
6971     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6972     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6973     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6974     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* 10 */
6980     { PREFIX_TABLE (PREFIX_0F3810) },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { PREFIX_TABLE (PREFIX_0F3814) },
6985     { PREFIX_TABLE (PREFIX_0F3815) },
6986     { Bad_Opcode },
6987     { PREFIX_TABLE (PREFIX_0F3817) },
6988     /* 18 */
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6994     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6995     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6996     { Bad_Opcode },
6997     /* 20 */
6998     { PREFIX_TABLE (PREFIX_0F3820) },
6999     { PREFIX_TABLE (PREFIX_0F3821) },
7000     { PREFIX_TABLE (PREFIX_0F3822) },
7001     { PREFIX_TABLE (PREFIX_0F3823) },
7002     { PREFIX_TABLE (PREFIX_0F3824) },
7003     { PREFIX_TABLE (PREFIX_0F3825) },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 28 */
7007     { PREFIX_TABLE (PREFIX_0F3828) },
7008     { PREFIX_TABLE (PREFIX_0F3829) },
7009     { PREFIX_TABLE (PREFIX_0F382A) },
7010     { PREFIX_TABLE (PREFIX_0F382B) },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 30 */
7016     { PREFIX_TABLE (PREFIX_0F3830) },
7017     { PREFIX_TABLE (PREFIX_0F3831) },
7018     { PREFIX_TABLE (PREFIX_0F3832) },
7019     { PREFIX_TABLE (PREFIX_0F3833) },
7020     { PREFIX_TABLE (PREFIX_0F3834) },
7021     { PREFIX_TABLE (PREFIX_0F3835) },
7022     { Bad_Opcode },
7023     { PREFIX_TABLE (PREFIX_0F3837) },
7024     /* 38 */
7025     { PREFIX_TABLE (PREFIX_0F3838) },
7026     { PREFIX_TABLE (PREFIX_0F3839) },
7027     { PREFIX_TABLE (PREFIX_0F383A) },
7028     { PREFIX_TABLE (PREFIX_0F383B) },
7029     { PREFIX_TABLE (PREFIX_0F383C) },
7030     { PREFIX_TABLE (PREFIX_0F383D) },
7031     { PREFIX_TABLE (PREFIX_0F383E) },
7032     { PREFIX_TABLE (PREFIX_0F383F) },
7033     /* 40 */
7034     { PREFIX_TABLE (PREFIX_0F3840) },
7035     { PREFIX_TABLE (PREFIX_0F3841) },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* 48 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* 50 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* 58 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* 60 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* 68 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* 70 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* 78 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* 80 */
7106     { PREFIX_TABLE (PREFIX_0F3880) },
7107     { PREFIX_TABLE (PREFIX_0F3881) },
7108     { PREFIX_TABLE (PREFIX_0F3882) },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* 88 */
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* 90 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     /* 98 */
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     /* a0 */
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     /* a8 */
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     /* b0 */
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     /* b8 */
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     /* c0 */
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     /* c8 */
7187     { PREFIX_TABLE (PREFIX_0F38C8) },
7188     { PREFIX_TABLE (PREFIX_0F38C9) },
7189     { PREFIX_TABLE (PREFIX_0F38CA) },
7190     { PREFIX_TABLE (PREFIX_0F38CB) },
7191     { PREFIX_TABLE (PREFIX_0F38CC) },
7192     { PREFIX_TABLE (PREFIX_0F38CD) },
7193     { Bad_Opcode },
7194     { PREFIX_TABLE (PREFIX_0F38CF) },
7195     /* d0 */
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     /* d8 */
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { PREFIX_TABLE (PREFIX_0F38DB) },
7209     { PREFIX_TABLE (PREFIX_0F38DC) },
7210     { PREFIX_TABLE (PREFIX_0F38DD) },
7211     { PREFIX_TABLE (PREFIX_0F38DE) },
7212     { PREFIX_TABLE (PREFIX_0F38DF) },
7213     /* e0 */
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     /* e8 */
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     /* f0 */
7232     { PREFIX_TABLE (PREFIX_0F38F0) },
7233     { PREFIX_TABLE (PREFIX_0F38F1) },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { PREFIX_TABLE (PREFIX_0F38F5) },
7238     { PREFIX_TABLE (PREFIX_0F38F6) },
7239     { Bad_Opcode },
7240     /* f8 */
7241     { PREFIX_TABLE (PREFIX_0F38F8) },
7242     { PREFIX_TABLE (PREFIX_0F38F9) },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249   },
7250   /* THREE_BYTE_0F3A */
7251   {
7252     /* 00 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* 08 */
7262     { PREFIX_TABLE (PREFIX_0F3A08) },
7263     { PREFIX_TABLE (PREFIX_0F3A09) },
7264     { PREFIX_TABLE (PREFIX_0F3A0A) },
7265     { PREFIX_TABLE (PREFIX_0F3A0B) },
7266     { PREFIX_TABLE (PREFIX_0F3A0C) },
7267     { PREFIX_TABLE (PREFIX_0F3A0D) },
7268     { PREFIX_TABLE (PREFIX_0F3A0E) },
7269     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7270     /* 10 */
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { PREFIX_TABLE (PREFIX_0F3A14) },
7276     { PREFIX_TABLE (PREFIX_0F3A15) },
7277     { PREFIX_TABLE (PREFIX_0F3A16) },
7278     { PREFIX_TABLE (PREFIX_0F3A17) },
7279     /* 18 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 20 */
7289     { PREFIX_TABLE (PREFIX_0F3A20) },
7290     { PREFIX_TABLE (PREFIX_0F3A21) },
7291     { PREFIX_TABLE (PREFIX_0F3A22) },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 28 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 30 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* 38 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* 40 */
7325     { PREFIX_TABLE (PREFIX_0F3A40) },
7326     { PREFIX_TABLE (PREFIX_0F3A41) },
7327     { PREFIX_TABLE (PREFIX_0F3A42) },
7328     { Bad_Opcode },
7329     { PREFIX_TABLE (PREFIX_0F3A44) },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* 48 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* 50 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* 58 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* 60 */
7361     { PREFIX_TABLE (PREFIX_0F3A60) },
7362     { PREFIX_TABLE (PREFIX_0F3A61) },
7363     { PREFIX_TABLE (PREFIX_0F3A62) },
7364     { PREFIX_TABLE (PREFIX_0F3A63) },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* 68 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* 70 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* 78 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* 80 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* 88 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* 90 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* 98 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     /* a0 */
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     /* a8 */
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     /* b0 */
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     /* b8 */
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     /* c0 */
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     /* c8 */
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { PREFIX_TABLE (PREFIX_0F3ACC) },
7483     { Bad_Opcode },
7484     { PREFIX_TABLE (PREFIX_0F3ACE) },
7485     { PREFIX_TABLE (PREFIX_0F3ACF) },
7486     /* d0 */
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     /* d8 */
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { PREFIX_TABLE (PREFIX_0F3ADF) },
7504     /* e0 */
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     /* e8 */
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     /* f0 */
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     /* f8 */
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540   },
7541 };
7542
7543 static const struct dis386 xop_table[][256] = {
7544   /* XOP_08 */
7545   {
7546     /* 00 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* 08 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 10 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 18 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     /* 20 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     /* 28 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     /* 30 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     /* 38 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     /* 40 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     /* 48 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     /* 50 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     /* 58 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     /* 60 */
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     /* 68 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     /* 70 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     /* 78 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* 80 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7697     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7698     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7699     /* 88 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7707     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7708     /* 90 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7715     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7716     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7717     /* 98 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7725     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7726     /* a0 */
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7730     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7734     { Bad_Opcode },
7735     /* a8 */
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     /* b0 */
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7752     { Bad_Opcode },
7753     /* b8 */
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     /* c0 */
7763     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7764     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7765     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7766     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     /* c8 */
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7777     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7778     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7779     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7780     /* d0 */
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     /* d8 */
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     /* e0 */
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     /* e8 */
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7813     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7814     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7815     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7816     /* f0 */
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     /* f8 */
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834   },
7835   /* XOP_09 */
7836   {
7837     /* 00 */
7838     { Bad_Opcode },
7839     { REG_TABLE (REG_XOP_TBM_01) },
7840     { REG_TABLE (REG_XOP_TBM_02) },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     /* 08 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 10 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { REG_TABLE (REG_XOP_LWPCB) },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     /* 18 */
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 20 */
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     /* 28 */
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     /* 30 */
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     /* 38 */
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     /* 40 */
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* 48 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* 50 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* 58 */
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* 60 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* 68 */
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     /* 70 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* 78 */
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* 80 */
7982     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7983     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7984     { "vfrczss",        { XM, EXd }, 0 },
7985     { "vfrczsd",        { XM, EXq }, 0 },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* 88 */
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* 90 */
8000     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8001     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8002     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8003     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8004     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8005     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8006     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8007     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8008     /* 98 */
8009     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8010     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8011     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8012     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     /* a0 */
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     /* a8 */
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     /* b0 */
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     /* b8 */
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     /* c0 */
8054     { Bad_Opcode },
8055     { "vphaddbw",       { XM, EXxmm }, 0 },
8056     { "vphaddbd",       { XM, EXxmm }, 0 },
8057     { "vphaddbq",       { XM, EXxmm }, 0 },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { "vphaddwd",       { XM, EXxmm }, 0 },
8061     { "vphaddwq",       { XM, EXxmm }, 0 },
8062     /* c8 */
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { "vphadddq",       { XM, EXxmm }, 0 },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     /* d0 */
8072     { Bad_Opcode },
8073     { "vphaddubw",      { XM, EXxmm }, 0 },
8074     { "vphaddubd",      { XM, EXxmm }, 0 },
8075     { "vphaddubq",      { XM, EXxmm }, 0 },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { "vphadduwd",      { XM, EXxmm }, 0 },
8079     { "vphadduwq",      { XM, EXxmm }, 0 },
8080     /* d8 */
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { "vphaddudq",      { XM, EXxmm }, 0 },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     /* e0 */
8090     { Bad_Opcode },
8091     { "vphsubbw",       { XM, EXxmm }, 0 },
8092     { "vphsubwd",       { XM, EXxmm }, 0 },
8093     { "vphsubdq",       { XM, EXxmm }, 0 },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     /* e8 */
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     /* f0 */
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     /* f8 */
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125   },
8126   /* XOP_0A */
8127   {
8128     /* 00 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     /* 08 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     /* 10 */
8147     { "bextrS", { Gdq, Edq, Id }, 0 },
8148     { Bad_Opcode },
8149     { REG_TABLE (REG_XOP_LWP) },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     /* 18 */
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* 20 */
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     /* 28 */
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     /* 30 */
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     /* 38 */
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     /* 40 */
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     /* 48 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* 50 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* 58 */
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* 60 */
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     /* 68 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* 70 */
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     /* 78 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* 80 */
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* 88 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* 90 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     /* 98 */
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     /* a0 */
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     /* a8 */
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     /* b0 */
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     /* b8 */
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     /* c0 */
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     /* c8 */
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     /* d0 */
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     /* d8 */
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     /* e0 */
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     /* e8 */
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     /* f0 */
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     /* f8 */
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416   },
8417 };
8418
8419 static const struct dis386 vex_table[][256] = {
8420   /* VEX_0F */
8421   {
8422     /* 00 */
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     /* 08 */
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     /* 10 */
8441     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8442     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8443     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8444     { MOD_TABLE (MOD_VEX_0F13) },
8445     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8446     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8447     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8448     { MOD_TABLE (MOD_VEX_0F17) },
8449     /* 18 */
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     /* 20 */
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     /* 28 */
8468     { "vmovapX",        { XM, EXx }, 0 },
8469     { "vmovapX",        { EXxS, XM }, 0 },
8470     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8471     { MOD_TABLE (MOD_VEX_0F2B) },
8472     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8473     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8474     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8475     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8476     /* 30 */
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     /* 38 */
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     /* 40 */
8495     { Bad_Opcode },
8496     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8497     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8498     { Bad_Opcode },
8499     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8500     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8501     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8502     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8503     /* 48 */
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     /* 50 */
8513     { MOD_TABLE (MOD_VEX_0F50) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8517     { "vandpX",         { XM, Vex, EXx }, 0 },
8518     { "vandnpX",        { XM, Vex, EXx }, 0 },
8519     { "vorpX",          { XM, Vex, EXx }, 0 },
8520     { "vxorpX",         { XM, Vex, EXx }, 0 },
8521     /* 58 */
8522     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8530     /* 60 */
8531     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8539     /* 68 */
8540     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8548     /* 70 */
8549     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8550     { REG_TABLE (REG_VEX_0F71) },
8551     { REG_TABLE (REG_VEX_0F72) },
8552     { REG_TABLE (REG_VEX_0F73) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8557     /* 78 */
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8566     /* 80 */
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     /* 88 */
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     /* 90 */
8585     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     /* 98 */
8594     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     /* a0 */
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     /* a8 */
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { REG_TABLE (REG_VEX_0FAE) },
8619     { Bad_Opcode },
8620     /* b0 */
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     /* b8 */
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     /* c0 */
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8642     { Bad_Opcode },
8643     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8644     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8645     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8646     { Bad_Opcode },
8647     /* c8 */
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     /* d0 */
8657     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8662     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8663     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8664     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8665     /* d8 */
8666     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8674     /* e0 */
8675     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8683     /* e8 */
8684     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8692     /* f0 */
8693     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8701     /* f8 */
8702     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8709     { Bad_Opcode },
8710   },
8711   /* VEX_0F38 */
8712   {
8713     /* 00 */
8714     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8722     /* 08 */
8723     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8731     /* 10 */
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8740     /* 18 */
8741     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8744     { Bad_Opcode },
8745     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8748     { Bad_Opcode },
8749     /* 20 */
8750     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     /* 28 */
8759     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8767     /* 30 */
8768     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8776     /* 38 */
8777     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8785     /* 40 */
8786     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8794     /* 48 */
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     /* 50 */
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     /* 58 */
8813     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     /* 60 */
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     /* 68 */
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     /* 70 */
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     /* 78 */
8849     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     /* 80 */
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     /* 88 */
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8872     { Bad_Opcode },
8873     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8874     { Bad_Opcode },
8875     /* 90 */
8876     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8884     /* 98 */
8885     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8893     /* a0 */
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8902     /* a8 */
8903     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8911     /* b0 */
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8920     /* b8 */
8921     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8929     /* c0 */
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     /* c8 */
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8947     /* d0 */
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     /* d8 */
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8965     /* e0 */
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     /* e8 */
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     /* f0 */
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8987     { REG_TABLE (REG_VEX_0F38F3) },
8988     { Bad_Opcode },
8989     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8992     /* f8 */
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001   },
9002   /* VEX_0F3A */
9003   {
9004     /* 00 */
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9008     { Bad_Opcode },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9012     { Bad_Opcode },
9013     /* 08 */
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9022     /* 10 */
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9031     /* 18 */
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     /* 20 */
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     /* 28 */
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     /* 30 */
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     /* 38 */
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     /* 40 */
9077     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9080     { Bad_Opcode },
9081     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9082     { Bad_Opcode },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9084     { Bad_Opcode },
9085     /* 48 */
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     /* 50 */
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     /* 58 */
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9112     /* 60 */
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     /* 68 */
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9130     /* 70 */
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     /* 78 */
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9144     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9148     /* 80 */
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     /* 88 */
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     /* 90 */
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     /* 98 */
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     /* a0 */
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     /* a8 */
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     /* b0 */
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     /* b8 */
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     /* c0 */
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     /* c8 */
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9237     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9238     /* d0 */
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     /* d8 */
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9256     /* e0 */
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     /* e8 */
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     /* f0 */
9275     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     /* f8 */
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292   },
9293 };
9294
9295 #include "i386-dis-evex.h"
9296
9297 static const struct dis386 vex_len_table[][2] = {
9298   /* VEX_LEN_0F12_P_0_M_0 */
9299   {
9300     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9301   },
9302
9303   /* VEX_LEN_0F12_P_0_M_1 */
9304   {
9305     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9306   },
9307
9308   /* VEX_LEN_0F12_P_2 */
9309   {
9310     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9311   },
9312
9313   /* VEX_LEN_0F13_M_0 */
9314   {
9315     { "vmovlpX",        { EXq, XM }, 0 },
9316   },
9317
9318   /* VEX_LEN_0F16_P_0_M_0 */
9319   {
9320     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9321   },
9322
9323   /* VEX_LEN_0F16_P_0_M_1 */
9324   {
9325     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9326   },
9327
9328   /* VEX_LEN_0F16_P_2 */
9329   {
9330     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9331   },
9332
9333   /* VEX_LEN_0F17_M_0 */
9334   {
9335     { "vmovhpX",        { EXq, XM }, 0 },
9336   },
9337
9338   /* VEX_LEN_0F41_P_0 */
9339   {
9340     { Bad_Opcode },
9341     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9342   },
9343   /* VEX_LEN_0F41_P_2 */
9344   {
9345     { Bad_Opcode },
9346     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9347   },
9348   /* VEX_LEN_0F42_P_0 */
9349   {
9350     { Bad_Opcode },
9351     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9352   },
9353   /* VEX_LEN_0F42_P_2 */
9354   {
9355     { Bad_Opcode },
9356     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9357   },
9358   /* VEX_LEN_0F44_P_0 */
9359   {
9360     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9361   },
9362   /* VEX_LEN_0F44_P_2 */
9363   {
9364     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9365   },
9366   /* VEX_LEN_0F45_P_0 */
9367   {
9368     { Bad_Opcode },
9369     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9370   },
9371   /* VEX_LEN_0F45_P_2 */
9372   {
9373     { Bad_Opcode },
9374     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9375   },
9376   /* VEX_LEN_0F46_P_0 */
9377   {
9378     { Bad_Opcode },
9379     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9380   },
9381   /* VEX_LEN_0F46_P_2 */
9382   {
9383     { Bad_Opcode },
9384     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9385   },
9386   /* VEX_LEN_0F47_P_0 */
9387   {
9388     { Bad_Opcode },
9389     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9390   },
9391   /* VEX_LEN_0F47_P_2 */
9392   {
9393     { Bad_Opcode },
9394     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9395   },
9396   /* VEX_LEN_0F4A_P_0 */
9397   {
9398     { Bad_Opcode },
9399     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9400   },
9401   /* VEX_LEN_0F4A_P_2 */
9402   {
9403     { Bad_Opcode },
9404     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9405   },
9406   /* VEX_LEN_0F4B_P_0 */
9407   {
9408     { Bad_Opcode },
9409     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9410   },
9411   /* VEX_LEN_0F4B_P_2 */
9412   {
9413     { Bad_Opcode },
9414     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9415   },
9416
9417   /* VEX_LEN_0F6E_P_2 */
9418   {
9419     { "vmovK",          { XMScalar, Edq }, 0 },
9420   },
9421
9422   /* VEX_LEN_0F77_P_1 */
9423   {
9424     { "vzeroupper",     { XX }, 0 },
9425     { "vzeroall",       { XX }, 0 },
9426   },
9427
9428   /* VEX_LEN_0F7E_P_1 */
9429   {
9430     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9431   },
9432
9433   /* VEX_LEN_0F7E_P_2 */
9434   {
9435     { "vmovK",          { Edq, XMScalar }, 0 },
9436   },
9437
9438   /* VEX_LEN_0F90_P_0 */
9439   {
9440     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9441   },
9442
9443   /* VEX_LEN_0F90_P_2 */
9444   {
9445     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9446   },
9447
9448   /* VEX_LEN_0F91_P_0 */
9449   {
9450     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9451   },
9452
9453   /* VEX_LEN_0F91_P_2 */
9454   {
9455     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9456   },
9457
9458   /* VEX_LEN_0F92_P_0 */
9459   {
9460     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9461   },
9462
9463   /* VEX_LEN_0F92_P_2 */
9464   {
9465     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9466   },
9467
9468   /* VEX_LEN_0F92_P_3 */
9469   {
9470     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9471   },
9472
9473   /* VEX_LEN_0F93_P_0 */
9474   {
9475     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9476   },
9477
9478   /* VEX_LEN_0F93_P_2 */
9479   {
9480     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9481   },
9482
9483   /* VEX_LEN_0F93_P_3 */
9484   {
9485     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9486   },
9487
9488   /* VEX_LEN_0F98_P_0 */
9489   {
9490     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9491   },
9492
9493   /* VEX_LEN_0F98_P_2 */
9494   {
9495     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9496   },
9497
9498   /* VEX_LEN_0F99_P_0 */
9499   {
9500     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9501   },
9502
9503   /* VEX_LEN_0F99_P_2 */
9504   {
9505     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9506   },
9507
9508   /* VEX_LEN_0FAE_R_2_M_0 */
9509   {
9510     { "vldmxcsr",       { Md }, 0 },
9511   },
9512
9513   /* VEX_LEN_0FAE_R_3_M_0 */
9514   {
9515     { "vstmxcsr",       { Md }, 0 },
9516   },
9517
9518   /* VEX_LEN_0FC4_P_2 */
9519   {
9520     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9521   },
9522
9523   /* VEX_LEN_0FC5_P_2 */
9524   {
9525     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9526   },
9527
9528   /* VEX_LEN_0FD6_P_2 */
9529   {
9530     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9531   },
9532
9533   /* VEX_LEN_0FF7_P_2 */
9534   {
9535     { "vmaskmovdqu",    { XM, XS }, 0 },
9536   },
9537
9538   /* VEX_LEN_0F3816_P_2 */
9539   {
9540     { Bad_Opcode },
9541     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9542   },
9543
9544   /* VEX_LEN_0F3819_P_2 */
9545   {
9546     { Bad_Opcode },
9547     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9548   },
9549
9550   /* VEX_LEN_0F381A_P_2_M_0 */
9551   {
9552     { Bad_Opcode },
9553     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9554   },
9555
9556   /* VEX_LEN_0F3836_P_2 */
9557   {
9558     { Bad_Opcode },
9559     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9560   },
9561
9562   /* VEX_LEN_0F3841_P_2 */
9563   {
9564     { "vphminposuw",    { XM, EXx }, 0 },
9565   },
9566
9567   /* VEX_LEN_0F385A_P_2_M_0 */
9568   {
9569     { Bad_Opcode },
9570     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9571   },
9572
9573   /* VEX_LEN_0F38DB_P_2 */
9574   {
9575     { "vaesimc",        { XM, EXx }, 0 },
9576   },
9577
9578   /* VEX_LEN_0F38F2_P_0 */
9579   {
9580     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9581   },
9582
9583   /* VEX_LEN_0F38F3_R_1_P_0 */
9584   {
9585     { "blsrS",          { VexGdq, Edq }, 0 },
9586   },
9587
9588   /* VEX_LEN_0F38F3_R_2_P_0 */
9589   {
9590     { "blsmskS",        { VexGdq, Edq }, 0 },
9591   },
9592
9593   /* VEX_LEN_0F38F3_R_3_P_0 */
9594   {
9595     { "blsiS",          { VexGdq, Edq }, 0 },
9596   },
9597
9598   /* VEX_LEN_0F38F5_P_0 */
9599   {
9600     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9601   },
9602
9603   /* VEX_LEN_0F38F5_P_1 */
9604   {
9605     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9606   },
9607
9608   /* VEX_LEN_0F38F5_P_3 */
9609   {
9610     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9611   },
9612
9613   /* VEX_LEN_0F38F6_P_3 */
9614   {
9615     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F38F7_P_0 */
9619   {
9620     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9621   },
9622
9623   /* VEX_LEN_0F38F7_P_1 */
9624   {
9625     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9626   },
9627
9628   /* VEX_LEN_0F38F7_P_2 */
9629   {
9630     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9631   },
9632
9633   /* VEX_LEN_0F38F7_P_3 */
9634   {
9635     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9636   },
9637
9638   /* VEX_LEN_0F3A00_P_2 */
9639   {
9640     { Bad_Opcode },
9641     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9642   },
9643
9644   /* VEX_LEN_0F3A01_P_2 */
9645   {
9646     { Bad_Opcode },
9647     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9648   },
9649
9650   /* VEX_LEN_0F3A06_P_2 */
9651   {
9652     { Bad_Opcode },
9653     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9654   },
9655
9656   /* VEX_LEN_0F3A14_P_2 */
9657   {
9658     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9659   },
9660
9661   /* VEX_LEN_0F3A15_P_2 */
9662   {
9663     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9664   },
9665
9666   /* VEX_LEN_0F3A16_P_2  */
9667   {
9668     { "vpextrK",        { Edq, XM, Ib }, 0 },
9669   },
9670
9671   /* VEX_LEN_0F3A17_P_2 */
9672   {
9673     { "vextractps",     { Edqd, XM, Ib }, 0 },
9674   },
9675
9676   /* VEX_LEN_0F3A18_P_2 */
9677   {
9678     { Bad_Opcode },
9679     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9680   },
9681
9682   /* VEX_LEN_0F3A19_P_2 */
9683   {
9684     { Bad_Opcode },
9685     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9686   },
9687
9688   /* VEX_LEN_0F3A20_P_2 */
9689   {
9690     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9691   },
9692
9693   /* VEX_LEN_0F3A21_P_2 */
9694   {
9695     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9696   },
9697
9698   /* VEX_LEN_0F3A22_P_2 */
9699   {
9700     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9701   },
9702
9703   /* VEX_LEN_0F3A30_P_2 */
9704   {
9705     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9706   },
9707
9708   /* VEX_LEN_0F3A31_P_2 */
9709   {
9710     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9711   },
9712
9713   /* VEX_LEN_0F3A32_P_2 */
9714   {
9715     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9716   },
9717
9718   /* VEX_LEN_0F3A33_P_2 */
9719   {
9720     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9721   },
9722
9723   /* VEX_LEN_0F3A38_P_2 */
9724   {
9725     { Bad_Opcode },
9726     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9727   },
9728
9729   /* VEX_LEN_0F3A39_P_2 */
9730   {
9731     { Bad_Opcode },
9732     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9733   },
9734
9735   /* VEX_LEN_0F3A41_P_2 */
9736   {
9737     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9738   },
9739
9740   /* VEX_LEN_0F3A46_P_2 */
9741   {
9742     { Bad_Opcode },
9743     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9744   },
9745
9746   /* VEX_LEN_0F3A60_P_2 */
9747   {
9748     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9749   },
9750
9751   /* VEX_LEN_0F3A61_P_2 */
9752   {
9753     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9754   },
9755
9756   /* VEX_LEN_0F3A62_P_2 */
9757   {
9758     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9759   },
9760
9761   /* VEX_LEN_0F3A63_P_2 */
9762   {
9763     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9764   },
9765
9766   /* VEX_LEN_0F3A6A_P_2 */
9767   {
9768     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9769   },
9770
9771   /* VEX_LEN_0F3A6B_P_2 */
9772   {
9773     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9774   },
9775
9776   /* VEX_LEN_0F3A6E_P_2 */
9777   {
9778     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9779   },
9780
9781   /* VEX_LEN_0F3A6F_P_2 */
9782   {
9783     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9784   },
9785
9786   /* VEX_LEN_0F3A7A_P_2 */
9787   {
9788     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9789   },
9790
9791   /* VEX_LEN_0F3A7B_P_2 */
9792   {
9793     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9794   },
9795
9796   /* VEX_LEN_0F3A7E_P_2 */
9797   {
9798     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9799   },
9800
9801   /* VEX_LEN_0F3A7F_P_2 */
9802   {
9803     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9804   },
9805
9806   /* VEX_LEN_0F3ADF_P_2 */
9807   {
9808     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9809   },
9810
9811   /* VEX_LEN_0F3AF0_P_3 */
9812   {
9813     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9814   },
9815
9816   /* VEX_LEN_0FXOP_08_CC */
9817   {
9818      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9819   },
9820
9821   /* VEX_LEN_0FXOP_08_CD */
9822   {
9823      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9824   },
9825
9826   /* VEX_LEN_0FXOP_08_CE */
9827   {
9828      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9829   },
9830
9831   /* VEX_LEN_0FXOP_08_CF */
9832   {
9833      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9834   },
9835
9836   /* VEX_LEN_0FXOP_08_EC */
9837   {
9838      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9839   },
9840
9841   /* VEX_LEN_0FXOP_08_ED */
9842   {
9843      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9844   },
9845
9846   /* VEX_LEN_0FXOP_08_EE */
9847   {
9848      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9849   },
9850
9851   /* VEX_LEN_0FXOP_08_EF */
9852   {
9853      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9854   },
9855
9856   /* VEX_LEN_0FXOP_09_80 */
9857   {
9858     { "vfrczps",        { XM, EXxmm }, 0 },
9859     { "vfrczps",        { XM, EXymmq }, 0 },
9860   },
9861
9862   /* VEX_LEN_0FXOP_09_81 */
9863   {
9864     { "vfrczpd",        { XM, EXxmm }, 0 },
9865     { "vfrczpd",        { XM, EXymmq }, 0 },
9866   },
9867 };
9868
9869 #include "i386-dis-evex-len.h"
9870
9871 static const struct dis386 vex_w_table[][2] = {
9872   {
9873     /* VEX_W_0F41_P_0_LEN_1 */
9874     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9875     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9876   },
9877   {
9878     /* VEX_W_0F41_P_2_LEN_1 */
9879     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9880     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9881   },
9882   {
9883     /* VEX_W_0F42_P_0_LEN_1 */
9884     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9885     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9886   },
9887   {
9888     /* VEX_W_0F42_P_2_LEN_1 */
9889     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9890     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9891   },
9892   {
9893     /* VEX_W_0F44_P_0_LEN_0 */
9894     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9895     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9896   },
9897   {
9898     /* VEX_W_0F44_P_2_LEN_0 */
9899     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9900     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9901   },
9902   {
9903     /* VEX_W_0F45_P_0_LEN_1 */
9904     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9905     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9906   },
9907   {
9908     /* VEX_W_0F45_P_2_LEN_1 */
9909     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9910     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9911   },
9912   {
9913     /* VEX_W_0F46_P_0_LEN_1 */
9914     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9915     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9916   },
9917   {
9918     /* VEX_W_0F46_P_2_LEN_1 */
9919     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9920     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9921   },
9922   {
9923     /* VEX_W_0F47_P_0_LEN_1 */
9924     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9925     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9926   },
9927   {
9928     /* VEX_W_0F47_P_2_LEN_1 */
9929     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9930     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9931   },
9932   {
9933     /* VEX_W_0F4A_P_0_LEN_1 */
9934     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9935     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9936   },
9937   {
9938     /* VEX_W_0F4A_P_2_LEN_1 */
9939     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9940     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9941   },
9942   {
9943     /* VEX_W_0F4B_P_0_LEN_1 */
9944     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9945     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9946   },
9947   {
9948     /* VEX_W_0F4B_P_2_LEN_1 */
9949     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9950   },
9951   {
9952     /* VEX_W_0F90_P_0_LEN_0 */
9953     { "kmovw",          { MaskG, MaskE }, 0 },
9954     { "kmovq",          { MaskG, MaskE }, 0 },
9955   },
9956   {
9957     /* VEX_W_0F90_P_2_LEN_0 */
9958     { "kmovb",          { MaskG, MaskBDE }, 0 },
9959     { "kmovd",          { MaskG, MaskBDE }, 0 },
9960   },
9961   {
9962     /* VEX_W_0F91_P_0_LEN_0 */
9963     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9964     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9965   },
9966   {
9967     /* VEX_W_0F91_P_2_LEN_0 */
9968     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9969     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9970   },
9971   {
9972     /* VEX_W_0F92_P_0_LEN_0 */
9973     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9974   },
9975   {
9976     /* VEX_W_0F92_P_2_LEN_0 */
9977     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9978   },
9979   {
9980     /* VEX_W_0F93_P_0_LEN_0 */
9981     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9982   },
9983   {
9984     /* VEX_W_0F93_P_2_LEN_0 */
9985     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9986   },
9987   {
9988     /* VEX_W_0F98_P_0_LEN_0 */
9989     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9990     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9991   },
9992   {
9993     /* VEX_W_0F98_P_2_LEN_0 */
9994     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9995     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9996   },
9997   {
9998     /* VEX_W_0F99_P_0_LEN_0 */
9999     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10000     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10001   },
10002   {
10003     /* VEX_W_0F99_P_2_LEN_0 */
10004     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10005     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10006   },
10007   {
10008     /* VEX_W_0F380C_P_2  */
10009     { "vpermilps",      { XM, Vex, EXx }, 0 },
10010   },
10011   {
10012     /* VEX_W_0F380D_P_2  */
10013     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10014   },
10015   {
10016     /* VEX_W_0F380E_P_2  */
10017     { "vtestps",        { XM, EXx }, 0 },
10018   },
10019   {
10020     /* VEX_W_0F380F_P_2  */
10021     { "vtestpd",        { XM, EXx }, 0 },
10022   },
10023   {
10024     /* VEX_W_0F3816_P_2  */
10025     { "vpermps",        { XM, Vex, EXx }, 0 },
10026   },
10027   {
10028     /* VEX_W_0F3818_P_2 */
10029     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10030   },
10031   {
10032     /* VEX_W_0F3819_P_2 */
10033     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10034   },
10035   {
10036     /* VEX_W_0F381A_P_2_M_0 */
10037     { "vbroadcastf128", { XM, Mxmm }, 0 },
10038   },
10039   {
10040     /* VEX_W_0F382C_P_2_M_0 */
10041     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10042   },
10043   {
10044     /* VEX_W_0F382D_P_2_M_0 */
10045     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10046   },
10047   {
10048     /* VEX_W_0F382E_P_2_M_0 */
10049     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10050   },
10051   {
10052     /* VEX_W_0F382F_P_2_M_0 */
10053     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10054   },
10055   {
10056     /* VEX_W_0F3836_P_2  */
10057     { "vpermd",         { XM, Vex, EXx }, 0 },
10058   },
10059   {
10060     /* VEX_W_0F3846_P_2 */
10061     { "vpsravd",        { XM, Vex, EXx }, 0 },
10062   },
10063   {
10064     /* VEX_W_0F3858_P_2 */
10065     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10066   },
10067   {
10068     /* VEX_W_0F3859_P_2 */
10069     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10070   },
10071   {
10072     /* VEX_W_0F385A_P_2_M_0 */
10073     { "vbroadcasti128", { XM, Mxmm }, 0 },
10074   },
10075   {
10076     /* VEX_W_0F3878_P_2 */
10077     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10078   },
10079   {
10080     /* VEX_W_0F3879_P_2 */
10081     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10082   },
10083   {
10084     /* VEX_W_0F38CF_P_2 */
10085     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10086   },
10087   {
10088     /* VEX_W_0F3A00_P_2 */
10089     { Bad_Opcode },
10090     { "vpermq",         { XM, EXx, Ib }, 0 },
10091   },
10092   {
10093     /* VEX_W_0F3A01_P_2 */
10094     { Bad_Opcode },
10095     { "vpermpd",        { XM, EXx, Ib }, 0 },
10096   },
10097   {
10098     /* VEX_W_0F3A02_P_2 */
10099     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10100   },
10101   {
10102     /* VEX_W_0F3A04_P_2 */
10103     { "vpermilps",      { XM, EXx, Ib }, 0 },
10104   },
10105   {
10106     /* VEX_W_0F3A05_P_2 */
10107     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10108   },
10109   {
10110     /* VEX_W_0F3A06_P_2 */
10111     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10112   },
10113   {
10114     /* VEX_W_0F3A18_P_2 */
10115     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10116   },
10117   {
10118     /* VEX_W_0F3A19_P_2 */
10119     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10120   },
10121   {
10122     /* VEX_W_0F3A30_P_2_LEN_0 */
10123     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10124     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10125   },
10126   {
10127     /* VEX_W_0F3A31_P_2_LEN_0 */
10128     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10129     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10130   },
10131   {
10132     /* VEX_W_0F3A32_P_2_LEN_0 */
10133     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10134     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10135   },
10136   {
10137     /* VEX_W_0F3A33_P_2_LEN_0 */
10138     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10139     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10140   },
10141   {
10142     /* VEX_W_0F3A38_P_2 */
10143     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10144   },
10145   {
10146     /* VEX_W_0F3A39_P_2 */
10147     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10148   },
10149   {
10150     /* VEX_W_0F3A46_P_2 */
10151     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10152   },
10153   {
10154     /* VEX_W_0F3A48_P_2 */
10155     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10156     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10157   },
10158   {
10159     /* VEX_W_0F3A49_P_2 */
10160     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10161     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10162   },
10163   {
10164     /* VEX_W_0F3A4A_P_2 */
10165     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10166   },
10167   {
10168     /* VEX_W_0F3A4B_P_2 */
10169     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10170   },
10171   {
10172     /* VEX_W_0F3A4C_P_2 */
10173     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10174   },
10175   {
10176     /* VEX_W_0F3ACE_P_2 */
10177     { Bad_Opcode },
10178     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10179   },
10180   {
10181     /* VEX_W_0F3ACF_P_2 */
10182     { Bad_Opcode },
10183     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10184   },
10185
10186 #include "i386-dis-evex-w.h"
10187 };
10188
10189 static const struct dis386 mod_table[][2] = {
10190   {
10191     /* MOD_8D */
10192     { "leaS",           { Gv, M }, 0 },
10193   },
10194   {
10195     /* MOD_C6_REG_7 */
10196     { Bad_Opcode },
10197     { RM_TABLE (RM_C6_REG_7) },
10198   },
10199   {
10200     /* MOD_C7_REG_7 */
10201     { Bad_Opcode },
10202     { RM_TABLE (RM_C7_REG_7) },
10203   },
10204   {
10205     /* MOD_FF_REG_3 */
10206     { "Jcall^", { indirEp }, 0 },
10207   },
10208   {
10209     /* MOD_FF_REG_5 */
10210     { "Jjmp^", { indirEp }, 0 },
10211   },
10212   {
10213     /* MOD_0F01_REG_0 */
10214     { X86_64_TABLE (X86_64_0F01_REG_0) },
10215     { RM_TABLE (RM_0F01_REG_0) },
10216   },
10217   {
10218     /* MOD_0F01_REG_1 */
10219     { X86_64_TABLE (X86_64_0F01_REG_1) },
10220     { RM_TABLE (RM_0F01_REG_1) },
10221   },
10222   {
10223     /* MOD_0F01_REG_2 */
10224     { X86_64_TABLE (X86_64_0F01_REG_2) },
10225     { RM_TABLE (RM_0F01_REG_2) },
10226   },
10227   {
10228     /* MOD_0F01_REG_3 */
10229     { X86_64_TABLE (X86_64_0F01_REG_3) },
10230     { RM_TABLE (RM_0F01_REG_3) },
10231   },
10232   {
10233     /* MOD_0F01_REG_5 */
10234     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10235     { RM_TABLE (RM_0F01_REG_5) },
10236   },
10237   {
10238     /* MOD_0F01_REG_7 */
10239     { "invlpg",         { Mb }, 0 },
10240     { RM_TABLE (RM_0F01_REG_7) },
10241   },
10242   {
10243     /* MOD_0F12_PREFIX_0 */
10244     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10245     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10246   },
10247   {
10248     /* MOD_0F13 */
10249     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10250   },
10251   {
10252     /* MOD_0F16_PREFIX_0 */
10253     { "movhps",         { XM, EXq }, 0 },
10254     { "movlhps",        { XM, EXq }, 0 },
10255   },
10256   {
10257     /* MOD_0F17 */
10258     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10259   },
10260   {
10261     /* MOD_0F18_REG_0 */
10262     { "prefetchnta",    { Mb }, 0 },
10263   },
10264   {
10265     /* MOD_0F18_REG_1 */
10266     { "prefetcht0",     { Mb }, 0 },
10267   },
10268   {
10269     /* MOD_0F18_REG_2 */
10270     { "prefetcht1",     { Mb }, 0 },
10271   },
10272   {
10273     /* MOD_0F18_REG_3 */
10274     { "prefetcht2",     { Mb }, 0 },
10275   },
10276   {
10277     /* MOD_0F18_REG_4 */
10278     { "nop/reserved",   { Mb }, 0 },
10279   },
10280   {
10281     /* MOD_0F18_REG_5 */
10282     { "nop/reserved",   { Mb }, 0 },
10283   },
10284   {
10285     /* MOD_0F18_REG_6 */
10286     { "nop/reserved",   { Mb }, 0 },
10287   },
10288   {
10289     /* MOD_0F18_REG_7 */
10290     { "nop/reserved",   { Mb }, 0 },
10291   },
10292   {
10293     /* MOD_0F1A_PREFIX_0 */
10294     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10295     { "nopQ",           { Ev }, 0 },
10296   },
10297   {
10298     /* MOD_0F1B_PREFIX_0 */
10299     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10300     { "nopQ",           { Ev }, 0 },
10301   },
10302   {
10303     /* MOD_0F1B_PREFIX_1 */
10304     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10305     { "nopQ",           { Ev }, 0 },
10306   },
10307   {
10308     /* MOD_0F1C_PREFIX_0 */
10309     { REG_TABLE (REG_0F1C_MOD_0) },
10310     { "nopQ",           { Ev }, 0 },
10311   },
10312   {
10313     /* MOD_0F1E_PREFIX_1 */
10314     { "nopQ",           { Ev }, 0 },
10315     { REG_TABLE (REG_0F1E_MOD_3) },
10316   },
10317   {
10318     /* MOD_0F24 */
10319     { Bad_Opcode },
10320     { "movL",           { Rd, Td }, 0 },
10321   },
10322   {
10323     /* MOD_0F26 */
10324     { Bad_Opcode },
10325     { "movL",           { Td, Rd }, 0 },
10326   },
10327   {
10328     /* MOD_0F2B_PREFIX_0 */
10329     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10330   },
10331   {
10332     /* MOD_0F2B_PREFIX_1 */
10333     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10334   },
10335   {
10336     /* MOD_0F2B_PREFIX_2 */
10337     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10338   },
10339   {
10340     /* MOD_0F2B_PREFIX_3 */
10341     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10342   },
10343   {
10344     /* MOD_0F51 */
10345     { Bad_Opcode },
10346     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10347   },
10348   {
10349     /* MOD_0F71_REG_2 */
10350     { Bad_Opcode },
10351     { "psrlw",          { MS, Ib }, 0 },
10352   },
10353   {
10354     /* MOD_0F71_REG_4 */
10355     { Bad_Opcode },
10356     { "psraw",          { MS, Ib }, 0 },
10357   },
10358   {
10359     /* MOD_0F71_REG_6 */
10360     { Bad_Opcode },
10361     { "psllw",          { MS, Ib }, 0 },
10362   },
10363   {
10364     /* MOD_0F72_REG_2 */
10365     { Bad_Opcode },
10366     { "psrld",          { MS, Ib }, 0 },
10367   },
10368   {
10369     /* MOD_0F72_REG_4 */
10370     { Bad_Opcode },
10371     { "psrad",          { MS, Ib }, 0 },
10372   },
10373   {
10374     /* MOD_0F72_REG_6 */
10375     { Bad_Opcode },
10376     { "pslld",          { MS, Ib }, 0 },
10377   },
10378   {
10379     /* MOD_0F73_REG_2 */
10380     { Bad_Opcode },
10381     { "psrlq",          { MS, Ib }, 0 },
10382   },
10383   {
10384     /* MOD_0F73_REG_3 */
10385     { Bad_Opcode },
10386     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10387   },
10388   {
10389     /* MOD_0F73_REG_6 */
10390     { Bad_Opcode },
10391     { "psllq",          { MS, Ib }, 0 },
10392   },
10393   {
10394     /* MOD_0F73_REG_7 */
10395     { Bad_Opcode },
10396     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10397   },
10398   {
10399     /* MOD_0FAE_REG_0 */
10400     { "fxsave",         { FXSAVE }, 0 },
10401     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10402   },
10403   {
10404     /* MOD_0FAE_REG_1 */
10405     { "fxrstor",        { FXSAVE }, 0 },
10406     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10407   },
10408   {
10409     /* MOD_0FAE_REG_2 */
10410     { "ldmxcsr",        { Md }, 0 },
10411     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10412   },
10413   {
10414     /* MOD_0FAE_REG_3 */
10415     { "stmxcsr",        { Md }, 0 },
10416     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10417   },
10418   {
10419     /* MOD_0FAE_REG_4 */
10420     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10421     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10422   },
10423   {
10424     /* MOD_0FAE_REG_5 */
10425     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10426     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10427   },
10428   {
10429     /* MOD_0FAE_REG_6 */
10430     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10431     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10432   },
10433   {
10434     /* MOD_0FAE_REG_7 */
10435     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10436     { RM_TABLE (RM_0FAE_REG_7) },
10437   },
10438   {
10439     /* MOD_0FB2 */
10440     { "lssS",           { Gv, Mp }, 0 },
10441   },
10442   {
10443     /* MOD_0FB4 */
10444     { "lfsS",           { Gv, Mp }, 0 },
10445   },
10446   {
10447     /* MOD_0FB5 */
10448     { "lgsS",           { Gv, Mp }, 0 },
10449   },
10450   {
10451     /* MOD_0FC3 */
10452     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10453   },
10454   {
10455     /* MOD_0FC7_REG_3 */
10456     { "xrstors",        { FXSAVE }, 0 },
10457   },
10458   {
10459     /* MOD_0FC7_REG_4 */
10460     { "xsavec",         { FXSAVE }, 0 },
10461   },
10462   {
10463     /* MOD_0FC7_REG_5 */
10464     { "xsaves",         { FXSAVE }, 0 },
10465   },
10466   {
10467     /* MOD_0FC7_REG_6 */
10468     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10469     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10470   },
10471   {
10472     /* MOD_0FC7_REG_7 */
10473     { "vmptrst",        { Mq }, 0 },
10474     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10475   },
10476   {
10477     /* MOD_0FD7 */
10478     { Bad_Opcode },
10479     { "pmovmskb",       { Gdq, MS }, 0 },
10480   },
10481   {
10482     /* MOD_0FE7_PREFIX_2 */
10483     { "movntdq",        { Mx, XM }, 0 },
10484   },
10485   {
10486     /* MOD_0FF0_PREFIX_3 */
10487     { "lddqu",          { XM, M }, 0 },
10488   },
10489   {
10490     /* MOD_0F382A_PREFIX_2 */
10491     { "movntdqa",       { XM, Mx }, 0 },
10492   },
10493   {
10494     /* MOD_0F38F5_PREFIX_2 */
10495     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10496   },
10497   {
10498     /* MOD_0F38F6_PREFIX_0 */
10499     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10500   },
10501   {
10502     /* MOD_0F38F8_PREFIX_1 */
10503     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10504   },
10505   {
10506     /* MOD_0F38F8_PREFIX_2 */
10507     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10508   },
10509   {
10510     /* MOD_0F38F8_PREFIX_3 */
10511     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10512   },
10513   {
10514     /* MOD_0F38F9_PREFIX_0 */
10515     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10516   },
10517   {
10518     /* MOD_62_32BIT */
10519     { "bound{S|}",      { Gv, Ma }, 0 },
10520     { EVEX_TABLE (EVEX_0F) },
10521   },
10522   {
10523     /* MOD_C4_32BIT */
10524     { "lesS",           { Gv, Mp }, 0 },
10525     { VEX_C4_TABLE (VEX_0F) },
10526   },
10527   {
10528     /* MOD_C5_32BIT */
10529     { "ldsS",           { Gv, Mp }, 0 },
10530     { VEX_C5_TABLE (VEX_0F) },
10531   },
10532   {
10533     /* MOD_VEX_0F12_PREFIX_0 */
10534     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10535     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10536   },
10537   {
10538     /* MOD_VEX_0F13 */
10539     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10540   },
10541   {
10542     /* MOD_VEX_0F16_PREFIX_0 */
10543     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10544     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10545   },
10546   {
10547     /* MOD_VEX_0F17 */
10548     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10549   },
10550   {
10551     /* MOD_VEX_0F2B */
10552     { "vmovntpX",       { Mx, XM }, 0 },
10553   },
10554   {
10555     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10556     { Bad_Opcode },
10557     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10558   },
10559   {
10560     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10561     { Bad_Opcode },
10562     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10563   },
10564   {
10565     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10566     { Bad_Opcode },
10567     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10568   },
10569   {
10570     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10571     { Bad_Opcode },
10572     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10573   },
10574   {
10575     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10576     { Bad_Opcode },
10577     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10578   },
10579   {
10580     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10581     { Bad_Opcode },
10582     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10583   },
10584   {
10585     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10586     { Bad_Opcode },
10587     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10588   },
10589   {
10590     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10591     { Bad_Opcode },
10592     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10593   },
10594   {
10595     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10596     { Bad_Opcode },
10597     { "knotw",          { MaskG, MaskR }, 0 },
10598   },
10599   {
10600     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10601     { Bad_Opcode },
10602     { "knotq",          { MaskG, MaskR }, 0 },
10603   },
10604   {
10605     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10606     { Bad_Opcode },
10607     { "knotb",          { MaskG, MaskR }, 0 },
10608   },
10609   {
10610     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10611     { Bad_Opcode },
10612     { "knotd",          { MaskG, MaskR }, 0 },
10613   },
10614   {
10615     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10616     { Bad_Opcode },
10617     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10618   },
10619   {
10620     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10621     { Bad_Opcode },
10622     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10623   },
10624   {
10625     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10626     { Bad_Opcode },
10627     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10628   },
10629   {
10630     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10631     { Bad_Opcode },
10632     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10633   },
10634  {
10635     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10636     { Bad_Opcode },
10637     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10638   },
10639   {
10640     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10641     { Bad_Opcode },
10642     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10643   },
10644   {
10645     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10646     { Bad_Opcode },
10647     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10648   },
10649   {
10650     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10651     { Bad_Opcode },
10652     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10653   },
10654   {
10655     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10656     { Bad_Opcode },
10657     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10658   },
10659   {
10660     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10661     { Bad_Opcode },
10662     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10663   },
10664   {
10665     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10666     { Bad_Opcode },
10667     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10668   },
10669   {
10670     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10671     { Bad_Opcode },
10672     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10673   },
10674   {
10675     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10676     { Bad_Opcode },
10677     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10678   },
10679   {
10680     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10681     { Bad_Opcode },
10682     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10683   },
10684   {
10685     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10686     { Bad_Opcode },
10687     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10688   },
10689   {
10690     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10691     { Bad_Opcode },
10692     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10693   },
10694   {
10695     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10696     { Bad_Opcode },
10697     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10698   },
10699   {
10700     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10701     { Bad_Opcode },
10702     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10703   },
10704   {
10705     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10706     { Bad_Opcode },
10707     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10708   },
10709   {
10710     /* MOD_VEX_0F50 */
10711     { Bad_Opcode },
10712     { "vmovmskpX",      { Gdq, XS }, 0 },
10713   },
10714   {
10715     /* MOD_VEX_0F71_REG_2 */
10716     { Bad_Opcode },
10717     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10718   },
10719   {
10720     /* MOD_VEX_0F71_REG_4 */
10721     { Bad_Opcode },
10722     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10723   },
10724   {
10725     /* MOD_VEX_0F71_REG_6 */
10726     { Bad_Opcode },
10727     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10728   },
10729   {
10730     /* MOD_VEX_0F72_REG_2 */
10731     { Bad_Opcode },
10732     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10733   },
10734   {
10735     /* MOD_VEX_0F72_REG_4 */
10736     { Bad_Opcode },
10737     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10738   },
10739   {
10740     /* MOD_VEX_0F72_REG_6 */
10741     { Bad_Opcode },
10742     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10743   },
10744   {
10745     /* MOD_VEX_0F73_REG_2 */
10746     { Bad_Opcode },
10747     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10748   },
10749   {
10750     /* MOD_VEX_0F73_REG_3 */
10751     { Bad_Opcode },
10752     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10753   },
10754   {
10755     /* MOD_VEX_0F73_REG_6 */
10756     { Bad_Opcode },
10757     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10758   },
10759   {
10760     /* MOD_VEX_0F73_REG_7 */
10761     { Bad_Opcode },
10762     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10763   },
10764   {
10765     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10766     { "kmovw",          { Ew, MaskG }, 0 },
10767     { Bad_Opcode },
10768   },
10769   {
10770     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10771     { "kmovq",          { Eq, MaskG }, 0 },
10772     { Bad_Opcode },
10773   },
10774   {
10775     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10776     { "kmovb",          { Eb, MaskG }, 0 },
10777     { Bad_Opcode },
10778   },
10779   {
10780     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10781     { "kmovd",          { Ed, MaskG }, 0 },
10782     { Bad_Opcode },
10783   },
10784   {
10785     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10786     { Bad_Opcode },
10787     { "kmovw",          { MaskG, Rdq }, 0 },
10788   },
10789   {
10790     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10791     { Bad_Opcode },
10792     { "kmovb",          { MaskG, Rdq }, 0 },
10793   },
10794   {
10795     /* MOD_VEX_0F92_P_3_LEN_0 */
10796     { Bad_Opcode },
10797     { "kmovK",          { MaskG, Rdq }, 0 },
10798   },
10799   {
10800     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10801     { Bad_Opcode },
10802     { "kmovw",          { Gdq, MaskR }, 0 },
10803   },
10804   {
10805     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10806     { Bad_Opcode },
10807     { "kmovb",          { Gdq, MaskR }, 0 },
10808   },
10809   {
10810     /* MOD_VEX_0F93_P_3_LEN_0 */
10811     { Bad_Opcode },
10812     { "kmovK",          { Gdq, MaskR }, 0 },
10813   },
10814   {
10815     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10816     { Bad_Opcode },
10817     { "kortestw", { MaskG, MaskR }, 0 },
10818   },
10819   {
10820     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10821     { Bad_Opcode },
10822     { "kortestq", { MaskG, MaskR }, 0 },
10823   },
10824   {
10825     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10826     { Bad_Opcode },
10827     { "kortestb", { MaskG, MaskR }, 0 },
10828   },
10829   {
10830     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10831     { Bad_Opcode },
10832     { "kortestd", { MaskG, MaskR }, 0 },
10833   },
10834   {
10835     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10836     { Bad_Opcode },
10837     { "ktestw", { MaskG, MaskR }, 0 },
10838   },
10839   {
10840     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10841     { Bad_Opcode },
10842     { "ktestq", { MaskG, MaskR }, 0 },
10843   },
10844   {
10845     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10846     { Bad_Opcode },
10847     { "ktestb", { MaskG, MaskR }, 0 },
10848   },
10849   {
10850     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10851     { Bad_Opcode },
10852     { "ktestd", { MaskG, MaskR }, 0 },
10853   },
10854   {
10855     /* MOD_VEX_0FAE_REG_2 */
10856     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10857   },
10858   {
10859     /* MOD_VEX_0FAE_REG_3 */
10860     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10861   },
10862   {
10863     /* MOD_VEX_0FD7_PREFIX_2 */
10864     { Bad_Opcode },
10865     { "vpmovmskb",      { Gdq, XS }, 0 },
10866   },
10867   {
10868     /* MOD_VEX_0FE7_PREFIX_2 */
10869     { "vmovntdq",       { Mx, XM }, 0 },
10870   },
10871   {
10872     /* MOD_VEX_0FF0_PREFIX_3 */
10873     { "vlddqu",         { XM, M }, 0 },
10874   },
10875   {
10876     /* MOD_VEX_0F381A_PREFIX_2 */
10877     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10878   },
10879   {
10880     /* MOD_VEX_0F382A_PREFIX_2 */
10881     { "vmovntdqa",      { XM, Mx }, 0 },
10882   },
10883   {
10884     /* MOD_VEX_0F382C_PREFIX_2 */
10885     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10886   },
10887   {
10888     /* MOD_VEX_0F382D_PREFIX_2 */
10889     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10890   },
10891   {
10892     /* MOD_VEX_0F382E_PREFIX_2 */
10893     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10894   },
10895   {
10896     /* MOD_VEX_0F382F_PREFIX_2 */
10897     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10898   },
10899   {
10900     /* MOD_VEX_0F385A_PREFIX_2 */
10901     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10902   },
10903   {
10904     /* MOD_VEX_0F388C_PREFIX_2 */
10905     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10906   },
10907   {
10908     /* MOD_VEX_0F388E_PREFIX_2 */
10909     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10910   },
10911   {
10912     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10913     { Bad_Opcode },
10914     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10915   },
10916   {
10917     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10918     { Bad_Opcode },
10919     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10920   },
10921   {
10922     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10923     { Bad_Opcode },
10924     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10925   },
10926   {
10927     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10928     { Bad_Opcode },
10929     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10930   },
10931   {
10932     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10933     { Bad_Opcode },
10934     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10935   },
10936   {
10937     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10938     { Bad_Opcode },
10939     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10940   },
10941   {
10942     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10943     { Bad_Opcode },
10944     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10945   },
10946   {
10947     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10948     { Bad_Opcode },
10949     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10950   },
10951
10952 #include "i386-dis-evex-mod.h"
10953 };
10954
10955 static const struct dis386 rm_table[][8] = {
10956   {
10957     /* RM_C6_REG_7 */
10958     { "xabort",         { Skip_MODRM, Ib }, 0 },
10959   },
10960   {
10961     /* RM_C7_REG_7 */
10962     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10963   },
10964   {
10965     /* RM_0F01_REG_0 */
10966     { "enclv",          { Skip_MODRM }, 0 },
10967     { "vmcall",         { Skip_MODRM }, 0 },
10968     { "vmlaunch",       { Skip_MODRM }, 0 },
10969     { "vmresume",       { Skip_MODRM }, 0 },
10970     { "vmxoff",         { Skip_MODRM }, 0 },
10971     { "pconfig",        { Skip_MODRM }, 0 },
10972   },
10973   {
10974     /* RM_0F01_REG_1 */
10975     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10976     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10977     { "clac",           { Skip_MODRM }, 0 },
10978     { "stac",           { Skip_MODRM }, 0 },
10979     { Bad_Opcode },
10980     { Bad_Opcode },
10981     { Bad_Opcode },
10982     { "encls",          { Skip_MODRM }, 0 },
10983   },
10984   {
10985     /* RM_0F01_REG_2 */
10986     { "xgetbv",         { Skip_MODRM }, 0 },
10987     { "xsetbv",         { Skip_MODRM }, 0 },
10988     { Bad_Opcode },
10989     { Bad_Opcode },
10990     { "vmfunc",         { Skip_MODRM }, 0 },
10991     { "xend",           { Skip_MODRM }, 0 },
10992     { "xtest",          { Skip_MODRM }, 0 },
10993     { "enclu",          { Skip_MODRM }, 0 },
10994   },
10995   {
10996     /* RM_0F01_REG_3 */
10997     { "vmrun",          { Skip_MODRM }, 0 },
10998     { "vmmcall",        { Skip_MODRM }, 0 },
10999     { "vmload",         { Skip_MODRM }, 0 },
11000     { "vmsave",         { Skip_MODRM }, 0 },
11001     { "stgi",           { Skip_MODRM }, 0 },
11002     { "clgi",           { Skip_MODRM }, 0 },
11003     { "skinit",         { Skip_MODRM }, 0 },
11004     { "invlpga",        { Skip_MODRM }, 0 },
11005   },
11006   {
11007     /* RM_0F01_REG_5 */
11008     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11009     { Bad_Opcode },
11010     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11011     { Bad_Opcode },
11012     { Bad_Opcode },
11013     { Bad_Opcode },
11014     { "rdpkru",         { Skip_MODRM }, 0 },
11015     { "wrpkru",         { Skip_MODRM }, 0 },
11016   },
11017   {
11018     /* RM_0F01_REG_7 */
11019     { "swapgs",         { Skip_MODRM }, 0  },
11020     { "rdtscp",         { Skip_MODRM }, 0  },
11021     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11022     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11023     { "clzero",         { Skip_MODRM }, 0  },
11024   },
11025   {
11026     /* RM_0F1E_MOD_3_REG_7 */
11027     { "nopQ",           { Ev }, 0 },
11028     { "nopQ",           { Ev }, 0 },
11029     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11030     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11031     { "nopQ",           { Ev }, 0 },
11032     { "nopQ",           { Ev }, 0 },
11033     { "nopQ",           { Ev }, 0 },
11034     { "nopQ",           { Ev }, 0 },
11035   },
11036   {
11037     /* RM_0FAE_REG_6 */
11038     { "mfence",         { Skip_MODRM }, 0 },
11039   },
11040   {
11041     /* RM_0FAE_REG_7 */
11042     { "sfence",         { Skip_MODRM }, 0 },
11043
11044   },
11045 };
11046
11047 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11048
11049 /* We use the high bit to indicate different name for the same
11050    prefix.  */
11051 #define REP_PREFIX      (0xf3 | 0x100)
11052 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11053 #define XRELEASE_PREFIX (0xf3 | 0x400)
11054 #define BND_PREFIX      (0xf2 | 0x400)
11055 #define NOTRACK_PREFIX  (0x3e | 0x100)
11056
11057 static int
11058 ckprefix (void)
11059 {
11060   int newrex, i, length;
11061   rex = 0;
11062   rex_ignored = 0;
11063   prefixes = 0;
11064   used_prefixes = 0;
11065   rex_used = 0;
11066   last_lock_prefix = -1;
11067   last_repz_prefix = -1;
11068   last_repnz_prefix = -1;
11069   last_data_prefix = -1;
11070   last_addr_prefix = -1;
11071   last_rex_prefix = -1;
11072   last_seg_prefix = -1;
11073   fwait_prefix = -1;
11074   active_seg_prefix = 0;
11075   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11076     all_prefixes[i] = 0;
11077   i = 0;
11078   length = 0;
11079   /* The maximum instruction length is 15bytes.  */
11080   while (length < MAX_CODE_LENGTH - 1)
11081     {
11082       FETCH_DATA (the_info, codep + 1);
11083       newrex = 0;
11084       switch (*codep)
11085         {
11086         /* REX prefixes family.  */
11087         case 0x40:
11088         case 0x41:
11089         case 0x42:
11090         case 0x43:
11091         case 0x44:
11092         case 0x45:
11093         case 0x46:
11094         case 0x47:
11095         case 0x48:
11096         case 0x49:
11097         case 0x4a:
11098         case 0x4b:
11099         case 0x4c:
11100         case 0x4d:
11101         case 0x4e:
11102         case 0x4f:
11103           if (address_mode == mode_64bit)
11104             newrex = *codep;
11105           else
11106             return 1;
11107           last_rex_prefix = i;
11108           break;
11109         case 0xf3:
11110           prefixes |= PREFIX_REPZ;
11111           last_repz_prefix = i;
11112           break;
11113         case 0xf2:
11114           prefixes |= PREFIX_REPNZ;
11115           last_repnz_prefix = i;
11116           break;
11117         case 0xf0:
11118           prefixes |= PREFIX_LOCK;
11119           last_lock_prefix = i;
11120           break;
11121         case 0x2e:
11122           prefixes |= PREFIX_CS;
11123           last_seg_prefix = i;
11124           active_seg_prefix = PREFIX_CS;
11125           break;
11126         case 0x36:
11127           prefixes |= PREFIX_SS;
11128           last_seg_prefix = i;
11129           active_seg_prefix = PREFIX_SS;
11130           break;
11131         case 0x3e:
11132           prefixes |= PREFIX_DS;
11133           last_seg_prefix = i;
11134           active_seg_prefix = PREFIX_DS;
11135           break;
11136         case 0x26:
11137           prefixes |= PREFIX_ES;
11138           last_seg_prefix = i;
11139           active_seg_prefix = PREFIX_ES;
11140           break;
11141         case 0x64:
11142           prefixes |= PREFIX_FS;
11143           last_seg_prefix = i;
11144           active_seg_prefix = PREFIX_FS;
11145           break;
11146         case 0x65:
11147           prefixes |= PREFIX_GS;
11148           last_seg_prefix = i;
11149           active_seg_prefix = PREFIX_GS;
11150           break;
11151         case 0x66:
11152           prefixes |= PREFIX_DATA;
11153           last_data_prefix = i;
11154           break;
11155         case 0x67:
11156           prefixes |= PREFIX_ADDR;
11157           last_addr_prefix = i;
11158           break;
11159         case FWAIT_OPCODE:
11160           /* fwait is really an instruction.  If there are prefixes
11161              before the fwait, they belong to the fwait, *not* to the
11162              following instruction.  */
11163           fwait_prefix = i;
11164           if (prefixes || rex)
11165             {
11166               prefixes |= PREFIX_FWAIT;
11167               codep++;
11168               /* This ensures that the previous REX prefixes are noticed
11169                  as unused prefixes, as in the return case below.  */
11170               rex_used = rex;
11171               return 1;
11172             }
11173           prefixes = PREFIX_FWAIT;
11174           break;
11175         default:
11176           return 1;
11177         }
11178       /* Rex is ignored when followed by another prefix.  */
11179       if (rex)
11180         {
11181           rex_used = rex;
11182           return 1;
11183         }
11184       if (*codep != FWAIT_OPCODE)
11185         all_prefixes[i++] = *codep;
11186       rex = newrex;
11187       codep++;
11188       length++;
11189     }
11190   return 0;
11191 }
11192
11193 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11194    prefix byte.  */
11195
11196 static const char *
11197 prefix_name (int pref, int sizeflag)
11198 {
11199   static const char *rexes [16] =
11200     {
11201       "rex",            /* 0x40 */
11202       "rex.B",          /* 0x41 */
11203       "rex.X",          /* 0x42 */
11204       "rex.XB",         /* 0x43 */
11205       "rex.R",          /* 0x44 */
11206       "rex.RB",         /* 0x45 */
11207       "rex.RX",         /* 0x46 */
11208       "rex.RXB",        /* 0x47 */
11209       "rex.W",          /* 0x48 */
11210       "rex.WB",         /* 0x49 */
11211       "rex.WX",         /* 0x4a */
11212       "rex.WXB",        /* 0x4b */
11213       "rex.WR",         /* 0x4c */
11214       "rex.WRB",        /* 0x4d */
11215       "rex.WRX",        /* 0x4e */
11216       "rex.WRXB",       /* 0x4f */
11217     };
11218
11219   switch (pref)
11220     {
11221     /* REX prefixes family.  */
11222     case 0x40:
11223     case 0x41:
11224     case 0x42:
11225     case 0x43:
11226     case 0x44:
11227     case 0x45:
11228     case 0x46:
11229     case 0x47:
11230     case 0x48:
11231     case 0x49:
11232     case 0x4a:
11233     case 0x4b:
11234     case 0x4c:
11235     case 0x4d:
11236     case 0x4e:
11237     case 0x4f:
11238       return rexes [pref - 0x40];
11239     case 0xf3:
11240       return "repz";
11241     case 0xf2:
11242       return "repnz";
11243     case 0xf0:
11244       return "lock";
11245     case 0x2e:
11246       return "cs";
11247     case 0x36:
11248       return "ss";
11249     case 0x3e:
11250       return "ds";
11251     case 0x26:
11252       return "es";
11253     case 0x64:
11254       return "fs";
11255     case 0x65:
11256       return "gs";
11257     case 0x66:
11258       return (sizeflag & DFLAG) ? "data16" : "data32";
11259     case 0x67:
11260       if (address_mode == mode_64bit)
11261         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11262       else
11263         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11264     case FWAIT_OPCODE:
11265       return "fwait";
11266     case REP_PREFIX:
11267       return "rep";
11268     case XACQUIRE_PREFIX:
11269       return "xacquire";
11270     case XRELEASE_PREFIX:
11271       return "xrelease";
11272     case BND_PREFIX:
11273       return "bnd";
11274     case NOTRACK_PREFIX:
11275       return "notrack";
11276     default:
11277       return NULL;
11278     }
11279 }
11280
11281 static char op_out[MAX_OPERANDS][100];
11282 static int op_ad, op_index[MAX_OPERANDS];
11283 static int two_source_ops;
11284 static bfd_vma op_address[MAX_OPERANDS];
11285 static bfd_vma op_riprel[MAX_OPERANDS];
11286 static bfd_vma start_pc;
11287
11288 /*
11289  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11290  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11291  *   section of the "Virtual 8086 Mode" chapter.)
11292  * 'pc' should be the address of this instruction, it will
11293  *   be used to print the target address if this is a relative jump or call
11294  * The function returns the length of this instruction in bytes.
11295  */
11296
11297 static char intel_syntax;
11298 static char intel_mnemonic = !SYSV386_COMPAT;
11299 static char open_char;
11300 static char close_char;
11301 static char separator_char;
11302 static char scale_char;
11303
11304 enum x86_64_isa
11305 {
11306   amd64 = 0,
11307   intel64
11308 };
11309
11310 static enum x86_64_isa isa64;
11311
11312 /* Here for backwards compatibility.  When gdb stops using
11313    print_insn_i386_att and print_insn_i386_intel these functions can
11314    disappear, and print_insn_i386 be merged into print_insn.  */
11315 int
11316 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11317 {
11318   intel_syntax = 0;
11319
11320   return print_insn (pc, info);
11321 }
11322
11323 int
11324 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11325 {
11326   intel_syntax = 1;
11327
11328   return print_insn (pc, info);
11329 }
11330
11331 int
11332 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11333 {
11334   intel_syntax = -1;
11335
11336   return print_insn (pc, info);
11337 }
11338
11339 void
11340 print_i386_disassembler_options (FILE *stream)
11341 {
11342   fprintf (stream, _("\n\
11343 The following i386/x86-64 specific disassembler options are supported for use\n\
11344 with the -M switch (multiple options should be separated by commas):\n"));
11345
11346   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11347   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11348   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11349   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11350   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11351   fprintf (stream, _("  att-mnemonic\n"
11352                      "              Display instruction in AT&T mnemonic\n"));
11353   fprintf (stream, _("  intel-mnemonic\n"
11354                      "              Display instruction in Intel mnemonic\n"));
11355   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11356   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11357   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11358   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11359   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11360   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11361   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11362   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11363 }
11364
11365 /* Bad opcode.  */
11366 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11367
11368 /* Get a pointer to struct dis386 with a valid name.  */
11369
11370 static const struct dis386 *
11371 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11372 {
11373   int vindex, vex_table_index;
11374
11375   if (dp->name != NULL)
11376     return dp;
11377
11378   switch (dp->op[0].bytemode)
11379     {
11380     case USE_REG_TABLE:
11381       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11382       break;
11383
11384     case USE_MOD_TABLE:
11385       vindex = modrm.mod == 0x3 ? 1 : 0;
11386       dp = &mod_table[dp->op[1].bytemode][vindex];
11387       break;
11388
11389     case USE_RM_TABLE:
11390       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11391       break;
11392
11393     case USE_PREFIX_TABLE:
11394       if (need_vex)
11395         {
11396           /* The prefix in VEX is implicit.  */
11397           switch (vex.prefix)
11398             {
11399             case 0:
11400               vindex = 0;
11401               break;
11402             case REPE_PREFIX_OPCODE:
11403               vindex = 1;
11404               break;
11405             case DATA_PREFIX_OPCODE:
11406               vindex = 2;
11407               break;
11408             case REPNE_PREFIX_OPCODE:
11409               vindex = 3;
11410               break;
11411             default:
11412               abort ();
11413               break;
11414             }
11415         }
11416       else
11417         {
11418           int last_prefix = -1;
11419           int prefix = 0;
11420           vindex = 0;
11421           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11422              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11423              last one wins.  */
11424           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11425             {
11426               if (last_repz_prefix > last_repnz_prefix)
11427                 {
11428                   vindex = 1;
11429                   prefix = PREFIX_REPZ;
11430                   last_prefix = last_repz_prefix;
11431                 }
11432               else
11433                 {
11434                   vindex = 3;
11435                   prefix = PREFIX_REPNZ;
11436                   last_prefix = last_repnz_prefix;
11437                 }
11438
11439               /* Check if prefix should be ignored.  */
11440               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11441                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11442                    & prefix) != 0)
11443                 vindex = 0;
11444             }
11445
11446           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11447             {
11448               vindex = 2;
11449               prefix = PREFIX_DATA;
11450               last_prefix = last_data_prefix;
11451             }
11452
11453           if (vindex != 0)
11454             {
11455               used_prefixes |= prefix;
11456               all_prefixes[last_prefix] = 0;
11457             }
11458         }
11459       dp = &prefix_table[dp->op[1].bytemode][vindex];
11460       break;
11461
11462     case USE_X86_64_TABLE:
11463       vindex = address_mode == mode_64bit ? 1 : 0;
11464       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11465       break;
11466
11467     case USE_3BYTE_TABLE:
11468       FETCH_DATA (info, codep + 2);
11469       vindex = *codep++;
11470       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11471       end_codep = codep;
11472       modrm.mod = (*codep >> 6) & 3;
11473       modrm.reg = (*codep >> 3) & 7;
11474       modrm.rm = *codep & 7;
11475       break;
11476
11477     case USE_VEX_LEN_TABLE:
11478       if (!need_vex)
11479         abort ();
11480
11481       switch (vex.length)
11482         {
11483         case 128:
11484           vindex = 0;
11485           break;
11486         case 256:
11487           vindex = 1;
11488           break;
11489         default:
11490           abort ();
11491           break;
11492         }
11493
11494       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11495       break;
11496
11497     case USE_EVEX_LEN_TABLE:
11498       if (!vex.evex)
11499         abort ();
11500
11501       switch (vex.length)
11502         {
11503         case 128:
11504           vindex = 0;
11505           break;
11506         case 256:
11507           vindex = 1;
11508           break;
11509         case 512:
11510           vindex = 2;
11511           break;
11512         default:
11513           abort ();
11514           break;
11515         }
11516
11517       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11518       break;
11519
11520     case USE_XOP_8F_TABLE:
11521       FETCH_DATA (info, codep + 3);
11522       /* All bits in the REX prefix are ignored.  */
11523       rex_ignored = rex;
11524       rex = ~(*codep >> 5) & 0x7;
11525
11526       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11527       switch ((*codep & 0x1f))
11528         {
11529         default:
11530           dp = &bad_opcode;
11531           return dp;
11532         case 0x8:
11533           vex_table_index = XOP_08;
11534           break;
11535         case 0x9:
11536           vex_table_index = XOP_09;
11537           break;
11538         case 0xa:
11539           vex_table_index = XOP_0A;
11540           break;
11541         }
11542       codep++;
11543       vex.w = *codep & 0x80;
11544       if (vex.w && address_mode == mode_64bit)
11545         rex |= REX_W;
11546
11547       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11548       if (address_mode != mode_64bit)
11549         {
11550           /* In 16/32-bit mode REX_B is silently ignored.  */
11551           rex &= ~REX_B;
11552         }
11553
11554       vex.length = (*codep & 0x4) ? 256 : 128;
11555       switch ((*codep & 0x3))
11556         {
11557         case 0:
11558           break;
11559         case 1:
11560           vex.prefix = DATA_PREFIX_OPCODE;
11561           break;
11562         case 2:
11563           vex.prefix = REPE_PREFIX_OPCODE;
11564           break;
11565         case 3:
11566           vex.prefix = REPNE_PREFIX_OPCODE;
11567           break;
11568         }
11569       need_vex = 1;
11570       need_vex_reg = 1;
11571       codep++;
11572       vindex = *codep++;
11573       dp = &xop_table[vex_table_index][vindex];
11574
11575       end_codep = codep;
11576       FETCH_DATA (info, codep + 1);
11577       modrm.mod = (*codep >> 6) & 3;
11578       modrm.reg = (*codep >> 3) & 7;
11579       modrm.rm = *codep & 7;
11580       break;
11581
11582     case USE_VEX_C4_TABLE:
11583       /* VEX prefix.  */
11584       FETCH_DATA (info, codep + 3);
11585       /* All bits in the REX prefix are ignored.  */
11586       rex_ignored = rex;
11587       rex = ~(*codep >> 5) & 0x7;
11588       switch ((*codep & 0x1f))
11589         {
11590         default:
11591           dp = &bad_opcode;
11592           return dp;
11593         case 0x1:
11594           vex_table_index = VEX_0F;
11595           break;
11596         case 0x2:
11597           vex_table_index = VEX_0F38;
11598           break;
11599         case 0x3:
11600           vex_table_index = VEX_0F3A;
11601           break;
11602         }
11603       codep++;
11604       vex.w = *codep & 0x80;
11605       if (address_mode == mode_64bit)
11606         {
11607           if (vex.w)
11608             rex |= REX_W;
11609         }
11610       else
11611         {
11612           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11613              is ignored, other REX bits are 0 and the highest bit in
11614              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11615           rex = 0;
11616         }
11617       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11618       vex.length = (*codep & 0x4) ? 256 : 128;
11619       switch ((*codep & 0x3))
11620         {
11621         case 0:
11622           break;
11623         case 1:
11624           vex.prefix = DATA_PREFIX_OPCODE;
11625           break;
11626         case 2:
11627           vex.prefix = REPE_PREFIX_OPCODE;
11628           break;
11629         case 3:
11630           vex.prefix = REPNE_PREFIX_OPCODE;
11631           break;
11632         }
11633       need_vex = 1;
11634       need_vex_reg = 1;
11635       codep++;
11636       vindex = *codep++;
11637       dp = &vex_table[vex_table_index][vindex];
11638       end_codep = codep;
11639       /* There is no MODRM byte for VEX0F 77.  */
11640       if (vex_table_index != VEX_0F || vindex != 0x77)
11641         {
11642           FETCH_DATA (info, codep + 1);
11643           modrm.mod = (*codep >> 6) & 3;
11644           modrm.reg = (*codep >> 3) & 7;
11645           modrm.rm = *codep & 7;
11646         }
11647       break;
11648
11649     case USE_VEX_C5_TABLE:
11650       /* VEX prefix.  */
11651       FETCH_DATA (info, codep + 2);
11652       /* All bits in the REX prefix are ignored.  */
11653       rex_ignored = rex;
11654       rex = (*codep & 0x80) ? 0 : REX_R;
11655
11656       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11657          VEX.vvvv is 1.  */
11658       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11659       vex.length = (*codep & 0x4) ? 256 : 128;
11660       switch ((*codep & 0x3))
11661         {
11662         case 0:
11663           break;
11664         case 1:
11665           vex.prefix = DATA_PREFIX_OPCODE;
11666           break;
11667         case 2:
11668           vex.prefix = REPE_PREFIX_OPCODE;
11669           break;
11670         case 3:
11671           vex.prefix = REPNE_PREFIX_OPCODE;
11672           break;
11673         }
11674       need_vex = 1;
11675       need_vex_reg = 1;
11676       codep++;
11677       vindex = *codep++;
11678       dp = &vex_table[dp->op[1].bytemode][vindex];
11679       end_codep = codep;
11680       /* There is no MODRM byte for VEX 77.  */
11681       if (vindex != 0x77)
11682         {
11683           FETCH_DATA (info, codep + 1);
11684           modrm.mod = (*codep >> 6) & 3;
11685           modrm.reg = (*codep >> 3) & 7;
11686           modrm.rm = *codep & 7;
11687         }
11688       break;
11689
11690     case USE_VEX_W_TABLE:
11691       if (!need_vex)
11692         abort ();
11693
11694       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11695       break;
11696
11697     case USE_EVEX_TABLE:
11698       two_source_ops = 0;
11699       /* EVEX prefix.  */
11700       vex.evex = 1;
11701       FETCH_DATA (info, codep + 4);
11702       /* All bits in the REX prefix are ignored.  */
11703       rex_ignored = rex;
11704       /* The first byte after 0x62.  */
11705       rex = ~(*codep >> 5) & 0x7;
11706       vex.r = *codep & 0x10;
11707       switch ((*codep & 0xf))
11708         {
11709         default:
11710           return &bad_opcode;
11711         case 0x1:
11712           vex_table_index = EVEX_0F;
11713           break;
11714         case 0x2:
11715           vex_table_index = EVEX_0F38;
11716           break;
11717         case 0x3:
11718           vex_table_index = EVEX_0F3A;
11719           break;
11720         }
11721
11722       /* The second byte after 0x62.  */
11723       codep++;
11724       vex.w = *codep & 0x80;
11725       if (vex.w && address_mode == mode_64bit)
11726         rex |= REX_W;
11727
11728       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11729
11730       /* The U bit.  */
11731       if (!(*codep & 0x4))
11732         return &bad_opcode;
11733
11734       switch ((*codep & 0x3))
11735         {
11736         case 0:
11737           break;
11738         case 1:
11739           vex.prefix = DATA_PREFIX_OPCODE;
11740           break;
11741         case 2:
11742           vex.prefix = REPE_PREFIX_OPCODE;
11743           break;
11744         case 3:
11745           vex.prefix = REPNE_PREFIX_OPCODE;
11746           break;
11747         }
11748
11749       /* The third byte after 0x62.  */
11750       codep++;
11751
11752       /* Remember the static rounding bits.  */
11753       vex.ll = (*codep >> 5) & 3;
11754       vex.b = (*codep & 0x10) != 0;
11755
11756       vex.v = *codep & 0x8;
11757       vex.mask_register_specifier = *codep & 0x7;
11758       vex.zeroing = *codep & 0x80;
11759
11760       if (address_mode != mode_64bit)
11761         {
11762           /* In 16/32-bit mode silently ignore following bits.  */
11763           rex &= ~REX_B;
11764           vex.r = 1;
11765           vex.v = 1;
11766         }
11767
11768       need_vex = 1;
11769       need_vex_reg = 1;
11770       codep++;
11771       vindex = *codep++;
11772       dp = &evex_table[vex_table_index][vindex];
11773       end_codep = codep;
11774       FETCH_DATA (info, codep + 1);
11775       modrm.mod = (*codep >> 6) & 3;
11776       modrm.reg = (*codep >> 3) & 7;
11777       modrm.rm = *codep & 7;
11778
11779       /* Set vector length.  */
11780       if (modrm.mod == 3 && vex.b)
11781         vex.length = 512;
11782       else
11783         {
11784           switch (vex.ll)
11785             {
11786             case 0x0:
11787               vex.length = 128;
11788               break;
11789             case 0x1:
11790               vex.length = 256;
11791               break;
11792             case 0x2:
11793               vex.length = 512;
11794               break;
11795             default:
11796               return &bad_opcode;
11797             }
11798         }
11799       break;
11800
11801     case 0:
11802       dp = &bad_opcode;
11803       break;
11804
11805     default:
11806       abort ();
11807     }
11808
11809   if (dp->name != NULL)
11810     return dp;
11811   else
11812     return get_valid_dis386 (dp, info);
11813 }
11814
11815 static void
11816 get_sib (disassemble_info *info, int sizeflag)
11817 {
11818   /* If modrm.mod == 3, operand must be register.  */
11819   if (need_modrm
11820       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11821       && modrm.mod != 3
11822       && modrm.rm == 4)
11823     {
11824       FETCH_DATA (info, codep + 2);
11825       sib.index = (codep [1] >> 3) & 7;
11826       sib.scale = (codep [1] >> 6) & 3;
11827       sib.base = codep [1] & 7;
11828     }
11829 }
11830
11831 static int
11832 print_insn (bfd_vma pc, disassemble_info *info)
11833 {
11834   const struct dis386 *dp;
11835   int i;
11836   char *op_txt[MAX_OPERANDS];
11837   int needcomma;
11838   int sizeflag, orig_sizeflag;
11839   const char *p;
11840   struct dis_private priv;
11841   int prefix_length;
11842
11843   priv.orig_sizeflag = AFLAG | DFLAG;
11844   if ((info->mach & bfd_mach_i386_i386) != 0)
11845     address_mode = mode_32bit;
11846   else if (info->mach == bfd_mach_i386_i8086)
11847     {
11848       address_mode = mode_16bit;
11849       priv.orig_sizeflag = 0;
11850     }
11851   else
11852     address_mode = mode_64bit;
11853
11854   if (intel_syntax == (char) -1)
11855     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11856
11857   for (p = info->disassembler_options; p != NULL; )
11858     {
11859       if (CONST_STRNEQ (p, "amd64"))
11860         isa64 = amd64;
11861       else if (CONST_STRNEQ (p, "intel64"))
11862         isa64 = intel64;
11863       else if (CONST_STRNEQ (p, "x86-64"))
11864         {
11865           address_mode = mode_64bit;
11866           priv.orig_sizeflag = AFLAG | DFLAG;
11867         }
11868       else if (CONST_STRNEQ (p, "i386"))
11869         {
11870           address_mode = mode_32bit;
11871           priv.orig_sizeflag = AFLAG | DFLAG;
11872         }
11873       else if (CONST_STRNEQ (p, "i8086"))
11874         {
11875           address_mode = mode_16bit;
11876           priv.orig_sizeflag = 0;
11877         }
11878       else if (CONST_STRNEQ (p, "intel"))
11879         {
11880           intel_syntax = 1;
11881           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11882             intel_mnemonic = 1;
11883         }
11884       else if (CONST_STRNEQ (p, "att"))
11885         {
11886           intel_syntax = 0;
11887           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11888             intel_mnemonic = 0;
11889         }
11890       else if (CONST_STRNEQ (p, "addr"))
11891         {
11892           if (address_mode == mode_64bit)
11893             {
11894               if (p[4] == '3' && p[5] == '2')
11895                 priv.orig_sizeflag &= ~AFLAG;
11896               else if (p[4] == '6' && p[5] == '4')
11897                 priv.orig_sizeflag |= AFLAG;
11898             }
11899           else
11900             {
11901               if (p[4] == '1' && p[5] == '6')
11902                 priv.orig_sizeflag &= ~AFLAG;
11903               else if (p[4] == '3' && p[5] == '2')
11904                 priv.orig_sizeflag |= AFLAG;
11905             }
11906         }
11907       else if (CONST_STRNEQ (p, "data"))
11908         {
11909           if (p[4] == '1' && p[5] == '6')
11910             priv.orig_sizeflag &= ~DFLAG;
11911           else if (p[4] == '3' && p[5] == '2')
11912             priv.orig_sizeflag |= DFLAG;
11913         }
11914       else if (CONST_STRNEQ (p, "suffix"))
11915         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11916
11917       p = strchr (p, ',');
11918       if (p != NULL)
11919         p++;
11920     }
11921
11922   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11923     {
11924       (*info->fprintf_func) (info->stream,
11925                              _("64-bit address is disabled"));
11926       return -1;
11927     }
11928
11929   if (intel_syntax)
11930     {
11931       names64 = intel_names64;
11932       names32 = intel_names32;
11933       names16 = intel_names16;
11934       names8 = intel_names8;
11935       names8rex = intel_names8rex;
11936       names_seg = intel_names_seg;
11937       names_mm = intel_names_mm;
11938       names_bnd = intel_names_bnd;
11939       names_xmm = intel_names_xmm;
11940       names_ymm = intel_names_ymm;
11941       names_zmm = intel_names_zmm;
11942       index64 = intel_index64;
11943       index32 = intel_index32;
11944       names_mask = intel_names_mask;
11945       index16 = intel_index16;
11946       open_char = '[';
11947       close_char = ']';
11948       separator_char = '+';
11949       scale_char = '*';
11950     }
11951   else
11952     {
11953       names64 = att_names64;
11954       names32 = att_names32;
11955       names16 = att_names16;
11956       names8 = att_names8;
11957       names8rex = att_names8rex;
11958       names_seg = att_names_seg;
11959       names_mm = att_names_mm;
11960       names_bnd = att_names_bnd;
11961       names_xmm = att_names_xmm;
11962       names_ymm = att_names_ymm;
11963       names_zmm = att_names_zmm;
11964       index64 = att_index64;
11965       index32 = att_index32;
11966       names_mask = att_names_mask;
11967       index16 = att_index16;
11968       open_char = '(';
11969       close_char =  ')';
11970       separator_char = ',';
11971       scale_char = ',';
11972     }
11973
11974   /* The output looks better if we put 7 bytes on a line, since that
11975      puts most long word instructions on a single line.  Use 8 bytes
11976      for Intel L1OM.  */
11977   if ((info->mach & bfd_mach_l1om) != 0)
11978     info->bytes_per_line = 8;
11979   else
11980     info->bytes_per_line = 7;
11981
11982   info->private_data = &priv;
11983   priv.max_fetched = priv.the_buffer;
11984   priv.insn_start = pc;
11985
11986   obuf[0] = 0;
11987   for (i = 0; i < MAX_OPERANDS; ++i)
11988     {
11989       op_out[i][0] = 0;
11990       op_index[i] = -1;
11991     }
11992
11993   the_info = info;
11994   start_pc = pc;
11995   start_codep = priv.the_buffer;
11996   codep = priv.the_buffer;
11997
11998   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11999     {
12000       const char *name;
12001
12002       /* Getting here means we tried for data but didn't get it.  That
12003          means we have an incomplete instruction of some sort.  Just
12004          print the first byte as a prefix or a .byte pseudo-op.  */
12005       if (codep > priv.the_buffer)
12006         {
12007           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12008           if (name != NULL)
12009             (*info->fprintf_func) (info->stream, "%s", name);
12010           else
12011             {
12012               /* Just print the first byte as a .byte instruction.  */
12013               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12014                                      (unsigned int) priv.the_buffer[0]);
12015             }
12016
12017           return 1;
12018         }
12019
12020       return -1;
12021     }
12022
12023   obufp = obuf;
12024   sizeflag = priv.orig_sizeflag;
12025
12026   if (!ckprefix () || rex_used)
12027     {
12028       /* Too many prefixes or unused REX prefixes.  */
12029       for (i = 0;
12030            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12031            i++)
12032         (*info->fprintf_func) (info->stream, "%s%s",
12033                                i == 0 ? "" : " ",
12034                                prefix_name (all_prefixes[i], sizeflag));
12035       return i;
12036     }
12037
12038   insn_codep = codep;
12039
12040   FETCH_DATA (info, codep + 1);
12041   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12042
12043   if (((prefixes & PREFIX_FWAIT)
12044        && ((*codep < 0xd8) || (*codep > 0xdf))))
12045     {
12046       /* Handle prefixes before fwait.  */
12047       for (i = 0; i < fwait_prefix && all_prefixes[i];
12048            i++)
12049         (*info->fprintf_func) (info->stream, "%s ",
12050                                prefix_name (all_prefixes[i], sizeflag));
12051       (*info->fprintf_func) (info->stream, "fwait");
12052       return i + 1;
12053     }
12054
12055   if (*codep == 0x0f)
12056     {
12057       unsigned char threebyte;
12058
12059       codep++;
12060       FETCH_DATA (info, codep + 1);
12061       threebyte = *codep;
12062       dp = &dis386_twobyte[threebyte];
12063       need_modrm = twobyte_has_modrm[*codep];
12064       codep++;
12065     }
12066   else
12067     {
12068       dp = &dis386[*codep];
12069       need_modrm = onebyte_has_modrm[*codep];
12070       codep++;
12071     }
12072
12073   /* Save sizeflag for printing the extra prefixes later before updating
12074      it for mnemonic and operand processing.  The prefix names depend
12075      only on the address mode.  */
12076   orig_sizeflag = sizeflag;
12077   if (prefixes & PREFIX_ADDR)
12078     sizeflag ^= AFLAG;
12079   if ((prefixes & PREFIX_DATA))
12080     sizeflag ^= DFLAG;
12081
12082   end_codep = codep;
12083   if (need_modrm)
12084     {
12085       FETCH_DATA (info, codep + 1);
12086       modrm.mod = (*codep >> 6) & 3;
12087       modrm.reg = (*codep >> 3) & 7;
12088       modrm.rm = *codep & 7;
12089     }
12090
12091   need_vex = 0;
12092   need_vex_reg = 0;
12093   vex_w_done = 0;
12094   memset (&vex, 0, sizeof (vex));
12095
12096   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12097     {
12098       get_sib (info, sizeflag);
12099       dofloat (sizeflag);
12100     }
12101   else
12102     {
12103       dp = get_valid_dis386 (dp, info);
12104       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12105         {
12106           get_sib (info, sizeflag);
12107           for (i = 0; i < MAX_OPERANDS; ++i)
12108             {
12109               obufp = op_out[i];
12110               op_ad = MAX_OPERANDS - 1 - i;
12111               if (dp->op[i].rtn)
12112                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12113               /* For EVEX instruction after the last operand masking
12114                  should be printed.  */
12115               if (i == 0 && vex.evex)
12116                 {
12117                   /* Don't print {%k0}.  */
12118                   if (vex.mask_register_specifier)
12119                     {
12120                       oappend ("{");
12121                       oappend (names_mask[vex.mask_register_specifier]);
12122                       oappend ("}");
12123                     }
12124                   if (vex.zeroing)
12125                     oappend ("{z}");
12126                 }
12127             }
12128         }
12129     }
12130
12131   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12132      are all 0s in inverted form.  */
12133   if (need_vex && vex.register_specifier != 0)
12134     {
12135       (*info->fprintf_func) (info->stream, "(bad)");
12136       return end_codep - priv.the_buffer;
12137     }
12138
12139   /* Check if the REX prefix is used.  */
12140   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12141     all_prefixes[last_rex_prefix] = 0;
12142
12143   /* Check if the SEG prefix is used.  */
12144   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12145                    | PREFIX_FS | PREFIX_GS)) != 0
12146       && (used_prefixes & active_seg_prefix) != 0)
12147     all_prefixes[last_seg_prefix] = 0;
12148
12149   /* Check if the ADDR prefix is used.  */
12150   if ((prefixes & PREFIX_ADDR) != 0
12151       && (used_prefixes & PREFIX_ADDR) != 0)
12152     all_prefixes[last_addr_prefix] = 0;
12153
12154   /* Check if the DATA prefix is used.  */
12155   if ((prefixes & PREFIX_DATA) != 0
12156       && (used_prefixes & PREFIX_DATA) != 0)
12157     all_prefixes[last_data_prefix] = 0;
12158
12159   /* Print the extra prefixes.  */
12160   prefix_length = 0;
12161   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12162     if (all_prefixes[i])
12163       {
12164         const char *name;
12165         name = prefix_name (all_prefixes[i], orig_sizeflag);
12166         if (name == NULL)
12167           abort ();
12168         prefix_length += strlen (name) + 1;
12169         (*info->fprintf_func) (info->stream, "%s ", name);
12170       }
12171
12172   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12173      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12174      used by putop and MMX/SSE operand and may be overriden by the
12175      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12176      separately.  */
12177   if (dp->prefix_requirement == PREFIX_OPCODE
12178       && dp != &bad_opcode
12179       && (((prefixes
12180             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12181            && (used_prefixes
12182                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12183           || ((((prefixes
12184                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12185                 == PREFIX_DATA)
12186                && (used_prefixes & PREFIX_DATA) == 0))))
12187     {
12188       (*info->fprintf_func) (info->stream, "(bad)");
12189       return end_codep - priv.the_buffer;
12190     }
12191
12192   /* Check maximum code length.  */
12193   if ((codep - start_codep) > MAX_CODE_LENGTH)
12194     {
12195       (*info->fprintf_func) (info->stream, "(bad)");
12196       return MAX_CODE_LENGTH;
12197     }
12198
12199   obufp = mnemonicendp;
12200   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12201     oappend (" ");
12202   oappend (" ");
12203   (*info->fprintf_func) (info->stream, "%s", obuf);
12204
12205   /* The enter and bound instructions are printed with operands in the same
12206      order as the intel book; everything else is printed in reverse order.  */
12207   if (intel_syntax || two_source_ops)
12208     {
12209       bfd_vma riprel;
12210
12211       for (i = 0; i < MAX_OPERANDS; ++i)
12212         op_txt[i] = op_out[i];
12213
12214       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12215           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12216         {
12217           op_txt[2] = op_out[3];
12218           op_txt[3] = op_out[2];
12219         }
12220
12221       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12222         {
12223           op_ad = op_index[i];
12224           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12225           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12226           riprel = op_riprel[i];
12227           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12228           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12229         }
12230     }
12231   else
12232     {
12233       for (i = 0; i < MAX_OPERANDS; ++i)
12234         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12235     }
12236
12237   needcomma = 0;
12238   for (i = 0; i < MAX_OPERANDS; ++i)
12239     if (*op_txt[i])
12240       {
12241         if (needcomma)
12242           (*info->fprintf_func) (info->stream, ",");
12243         if (op_index[i] != -1 && !op_riprel[i])
12244           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12245         else
12246           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12247         needcomma = 1;
12248       }
12249
12250   for (i = 0; i < MAX_OPERANDS; i++)
12251     if (op_index[i] != -1 && op_riprel[i])
12252       {
12253         (*info->fprintf_func) (info->stream, "        # ");
12254         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12255                                                 + op_address[op_index[i]]), info);
12256         break;
12257       }
12258   return codep - priv.the_buffer;
12259 }
12260
12261 static const char *float_mem[] = {
12262   /* d8 */
12263   "fadd{s|}",
12264   "fmul{s|}",
12265   "fcom{s|}",
12266   "fcomp{s|}",
12267   "fsub{s|}",
12268   "fsubr{s|}",
12269   "fdiv{s|}",
12270   "fdivr{s|}",
12271   /* d9 */
12272   "fld{s|}",
12273   "(bad)",
12274   "fst{s|}",
12275   "fstp{s|}",
12276   "fldenvIC",
12277   "fldcw",
12278   "fNstenvIC",
12279   "fNstcw",
12280   /* da */
12281   "fiadd{l|}",
12282   "fimul{l|}",
12283   "ficom{l|}",
12284   "ficomp{l|}",
12285   "fisub{l|}",
12286   "fisubr{l|}",
12287   "fidiv{l|}",
12288   "fidivr{l|}",
12289   /* db */
12290   "fild{l|}",
12291   "fisttp{l|}",
12292   "fist{l|}",
12293   "fistp{l|}",
12294   "(bad)",
12295   "fld{t||t|}",
12296   "(bad)",
12297   "fstp{t||t|}",
12298   /* dc */
12299   "fadd{l|}",
12300   "fmul{l|}",
12301   "fcom{l|}",
12302   "fcomp{l|}",
12303   "fsub{l|}",
12304   "fsubr{l|}",
12305   "fdiv{l|}",
12306   "fdivr{l|}",
12307   /* dd */
12308   "fld{l|}",
12309   "fisttp{ll|}",
12310   "fst{l||}",
12311   "fstp{l|}",
12312   "frstorIC",
12313   "(bad)",
12314   "fNsaveIC",
12315   "fNstsw",
12316   /* de */
12317   "fiadd{s|}",
12318   "fimul{s|}",
12319   "ficom{s|}",
12320   "ficomp{s|}",
12321   "fisub{s|}",
12322   "fisubr{s|}",
12323   "fidiv{s|}",
12324   "fidivr{s|}",
12325   /* df */
12326   "fild{s|}",
12327   "fisttp{s|}",
12328   "fist{s|}",
12329   "fistp{s|}",
12330   "fbld",
12331   "fild{ll|}",
12332   "fbstp",
12333   "fistp{ll|}",
12334 };
12335
12336 static const unsigned char float_mem_mode[] = {
12337   /* d8 */
12338   d_mode,
12339   d_mode,
12340   d_mode,
12341   d_mode,
12342   d_mode,
12343   d_mode,
12344   d_mode,
12345   d_mode,
12346   /* d9 */
12347   d_mode,
12348   0,
12349   d_mode,
12350   d_mode,
12351   0,
12352   w_mode,
12353   0,
12354   w_mode,
12355   /* da */
12356   d_mode,
12357   d_mode,
12358   d_mode,
12359   d_mode,
12360   d_mode,
12361   d_mode,
12362   d_mode,
12363   d_mode,
12364   /* db */
12365   d_mode,
12366   d_mode,
12367   d_mode,
12368   d_mode,
12369   0,
12370   t_mode,
12371   0,
12372   t_mode,
12373   /* dc */
12374   q_mode,
12375   q_mode,
12376   q_mode,
12377   q_mode,
12378   q_mode,
12379   q_mode,
12380   q_mode,
12381   q_mode,
12382   /* dd */
12383   q_mode,
12384   q_mode,
12385   q_mode,
12386   q_mode,
12387   0,
12388   0,
12389   0,
12390   w_mode,
12391   /* de */
12392   w_mode,
12393   w_mode,
12394   w_mode,
12395   w_mode,
12396   w_mode,
12397   w_mode,
12398   w_mode,
12399   w_mode,
12400   /* df */
12401   w_mode,
12402   w_mode,
12403   w_mode,
12404   w_mode,
12405   t_mode,
12406   q_mode,
12407   t_mode,
12408   q_mode
12409 };
12410
12411 #define ST { OP_ST, 0 }
12412 #define STi { OP_STi, 0 }
12413
12414 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12415 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12416 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12417 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12418 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12419 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12420 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12421 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12422 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12423
12424 static const struct dis386 float_reg[][8] = {
12425   /* d8 */
12426   {
12427     { "fadd",   { ST, STi }, 0 },
12428     { "fmul",   { ST, STi }, 0 },
12429     { "fcom",   { STi }, 0 },
12430     { "fcomp",  { STi }, 0 },
12431     { "fsub",   { ST, STi }, 0 },
12432     { "fsubr",  { ST, STi }, 0 },
12433     { "fdiv",   { ST, STi }, 0 },
12434     { "fdivr",  { ST, STi }, 0 },
12435   },
12436   /* d9 */
12437   {
12438     { "fld",    { STi }, 0 },
12439     { "fxch",   { STi }, 0 },
12440     { FGRPd9_2 },
12441     { Bad_Opcode },
12442     { FGRPd9_4 },
12443     { FGRPd9_5 },
12444     { FGRPd9_6 },
12445     { FGRPd9_7 },
12446   },
12447   /* da */
12448   {
12449     { "fcmovb", { ST, STi }, 0 },
12450     { "fcmove", { ST, STi }, 0 },
12451     { "fcmovbe",{ ST, STi }, 0 },
12452     { "fcmovu", { ST, STi }, 0 },
12453     { Bad_Opcode },
12454     { FGRPda_5 },
12455     { Bad_Opcode },
12456     { Bad_Opcode },
12457   },
12458   /* db */
12459   {
12460     { "fcmovnb",{ ST, STi }, 0 },
12461     { "fcmovne",{ ST, STi }, 0 },
12462     { "fcmovnbe",{ ST, STi }, 0 },
12463     { "fcmovnu",{ ST, STi }, 0 },
12464     { FGRPdb_4 },
12465     { "fucomi", { ST, STi }, 0 },
12466     { "fcomi",  { ST, STi }, 0 },
12467     { Bad_Opcode },
12468   },
12469   /* dc */
12470   {
12471     { "fadd",   { STi, ST }, 0 },
12472     { "fmul",   { STi, ST }, 0 },
12473     { Bad_Opcode },
12474     { Bad_Opcode },
12475     { "fsub{!M|r}",     { STi, ST }, 0 },
12476     { "fsub{M|}",       { STi, ST }, 0 },
12477     { "fdiv{!M|r}",     { STi, ST }, 0 },
12478     { "fdiv{M|}",       { STi, ST }, 0 },
12479   },
12480   /* dd */
12481   {
12482     { "ffree",  { STi }, 0 },
12483     { Bad_Opcode },
12484     { "fst",    { STi }, 0 },
12485     { "fstp",   { STi }, 0 },
12486     { "fucom",  { STi }, 0 },
12487     { "fucomp", { STi }, 0 },
12488     { Bad_Opcode },
12489     { Bad_Opcode },
12490   },
12491   /* de */
12492   {
12493     { "faddp",  { STi, ST }, 0 },
12494     { "fmulp",  { STi, ST }, 0 },
12495     { Bad_Opcode },
12496     { FGRPde_3 },
12497     { "fsub{!M|r}p",    { STi, ST }, 0 },
12498     { "fsub{M|}p",      { STi, ST }, 0 },
12499     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12500     { "fdiv{M|}p",      { STi, ST }, 0 },
12501   },
12502   /* df */
12503   {
12504     { "ffreep", { STi }, 0 },
12505     { Bad_Opcode },
12506     { Bad_Opcode },
12507     { Bad_Opcode },
12508     { FGRPdf_4 },
12509     { "fucomip", { ST, STi }, 0 },
12510     { "fcomip", { ST, STi }, 0 },
12511     { Bad_Opcode },
12512   },
12513 };
12514
12515 static char *fgrps[][8] = {
12516   /* Bad opcode 0 */
12517   {
12518     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12519   },
12520
12521   /* d9_2  1 */
12522   {
12523     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12524   },
12525
12526   /* d9_4  2 */
12527   {
12528     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12529   },
12530
12531   /* d9_5  3 */
12532   {
12533     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12534   },
12535
12536   /* d9_6  4 */
12537   {
12538     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12539   },
12540
12541   /* d9_7  5 */
12542   {
12543     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12544   },
12545
12546   /* da_5  6 */
12547   {
12548     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12549   },
12550
12551   /* db_4  7 */
12552   {
12553     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12554     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12555   },
12556
12557   /* de_3  8 */
12558   {
12559     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12560   },
12561
12562   /* df_4  9 */
12563   {
12564     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12565   },
12566 };
12567
12568 static void
12569 swap_operand (void)
12570 {
12571   mnemonicendp[0] = '.';
12572   mnemonicendp[1] = 's';
12573   mnemonicendp += 2;
12574 }
12575
12576 static void
12577 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12578                int sizeflag ATTRIBUTE_UNUSED)
12579 {
12580   /* Skip mod/rm byte.  */
12581   MODRM_CHECK;
12582   codep++;
12583 }
12584
12585 static void
12586 dofloat (int sizeflag)
12587 {
12588   const struct dis386 *dp;
12589   unsigned char floatop;
12590
12591   floatop = codep[-1];
12592
12593   if (modrm.mod != 3)
12594     {
12595       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12596
12597       putop (float_mem[fp_indx], sizeflag);
12598       obufp = op_out[0];
12599       op_ad = 2;
12600       OP_E (float_mem_mode[fp_indx], sizeflag);
12601       return;
12602     }
12603   /* Skip mod/rm byte.  */
12604   MODRM_CHECK;
12605   codep++;
12606
12607   dp = &float_reg[floatop - 0xd8][modrm.reg];
12608   if (dp->name == NULL)
12609     {
12610       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12611
12612       /* Instruction fnstsw is only one with strange arg.  */
12613       if (floatop == 0xdf && codep[-1] == 0xe0)
12614         strcpy (op_out[0], names16[0]);
12615     }
12616   else
12617     {
12618       putop (dp->name, sizeflag);
12619
12620       obufp = op_out[0];
12621       op_ad = 2;
12622       if (dp->op[0].rtn)
12623         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12624
12625       obufp = op_out[1];
12626       op_ad = 1;
12627       if (dp->op[1].rtn)
12628         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12629     }
12630 }
12631
12632 /* Like oappend (below), but S is a string starting with '%'.
12633    In Intel syntax, the '%' is elided.  */
12634 static void
12635 oappend_maybe_intel (const char *s)
12636 {
12637   oappend (s + intel_syntax);
12638 }
12639
12640 static void
12641 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12642 {
12643   oappend_maybe_intel ("%st");
12644 }
12645
12646 static void
12647 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12648 {
12649   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12650   oappend_maybe_intel (scratchbuf);
12651 }
12652
12653 /* Capital letters in template are macros.  */
12654 static int
12655 putop (const char *in_template, int sizeflag)
12656 {
12657   const char *p;
12658   int alt = 0;
12659   int cond = 1;
12660   unsigned int l = 0, len = 1;
12661   char last[4];
12662
12663 #define SAVE_LAST(c)                    \
12664   if (l < len && l < sizeof (last))     \
12665     last[l++] = c;                      \
12666   else                                  \
12667     abort ();
12668
12669   for (p = in_template; *p; p++)
12670     {
12671       switch (*p)
12672         {
12673         default:
12674           *obufp++ = *p;
12675           break;
12676         case '%':
12677           len++;
12678           break;
12679         case '!':
12680           cond = 0;
12681           break;
12682         case '{':
12683           if (intel_syntax)
12684             {
12685               while (*++p != '|')
12686                 if (*p == '}' || *p == '\0')
12687                   abort ();
12688             }
12689           /* Fall through.  */
12690         case 'I':
12691           alt = 1;
12692           continue;
12693         case '|':
12694           while (*++p != '}')
12695             {
12696               if (*p == '\0')
12697                 abort ();
12698             }
12699           break;
12700         case '}':
12701           break;
12702         case 'A':
12703           if (intel_syntax)
12704             break;
12705           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12706             *obufp++ = 'b';
12707           break;
12708         case 'B':
12709           if (l == 0 && len == 1)
12710             {
12711 case_B:
12712               if (intel_syntax)
12713                 break;
12714               if (sizeflag & SUFFIX_ALWAYS)
12715                 *obufp++ = 'b';
12716             }
12717           else
12718             {
12719               if (l != 1
12720                   || len != 2
12721                   || last[0] != 'L')
12722                 {
12723                   SAVE_LAST (*p);
12724                   break;
12725                 }
12726
12727               if (address_mode == mode_64bit
12728                   && !(prefixes & PREFIX_ADDR))
12729                 {
12730                   *obufp++ = 'a';
12731                   *obufp++ = 'b';
12732                   *obufp++ = 's';
12733                 }
12734
12735               goto case_B;
12736             }
12737           break;
12738         case 'C':
12739           if (intel_syntax && !alt)
12740             break;
12741           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12742             {
12743               if (sizeflag & DFLAG)
12744                 *obufp++ = intel_syntax ? 'd' : 'l';
12745               else
12746                 *obufp++ = intel_syntax ? 'w' : 's';
12747               used_prefixes |= (prefixes & PREFIX_DATA);
12748             }
12749           break;
12750         case 'D':
12751           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12752             break;
12753           USED_REX (REX_W);
12754           if (modrm.mod == 3)
12755             {
12756               if (rex & REX_W)
12757                 *obufp++ = 'q';
12758               else
12759                 {
12760                   if (sizeflag & DFLAG)
12761                     *obufp++ = intel_syntax ? 'd' : 'l';
12762                   else
12763                     *obufp++ = 'w';
12764                   used_prefixes |= (prefixes & PREFIX_DATA);
12765                 }
12766             }
12767           else
12768             *obufp++ = 'w';
12769           break;
12770         case 'E':               /* For jcxz/jecxz */
12771           if (address_mode == mode_64bit)
12772             {
12773               if (sizeflag & AFLAG)
12774                 *obufp++ = 'r';
12775               else
12776                 *obufp++ = 'e';
12777             }
12778           else
12779             if (sizeflag & AFLAG)
12780               *obufp++ = 'e';
12781           used_prefixes |= (prefixes & PREFIX_ADDR);
12782           break;
12783         case 'F':
12784           if (intel_syntax)
12785             break;
12786           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12787             {
12788               if (sizeflag & AFLAG)
12789                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12790               else
12791                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12792               used_prefixes |= (prefixes & PREFIX_ADDR);
12793             }
12794           break;
12795         case 'G':
12796           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12797             break;
12798           if ((rex & REX_W) || (sizeflag & DFLAG))
12799             *obufp++ = 'l';
12800           else
12801             *obufp++ = 'w';
12802           if (!(rex & REX_W))
12803             used_prefixes |= (prefixes & PREFIX_DATA);
12804           break;
12805         case 'H':
12806           if (intel_syntax)
12807             break;
12808           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12809               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12810             {
12811               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12812               *obufp++ = ',';
12813               *obufp++ = 'p';
12814               if (prefixes & PREFIX_DS)
12815                 *obufp++ = 't';
12816               else
12817                 *obufp++ = 'n';
12818             }
12819           break;
12820         case 'J':
12821           if (intel_syntax)
12822             break;
12823           *obufp++ = 'l';
12824           break;
12825         case 'K':
12826           USED_REX (REX_W);
12827           if (rex & REX_W)
12828             *obufp++ = 'q';
12829           else
12830             *obufp++ = 'd';
12831           break;
12832         case 'Z':
12833           if (l != 0 || len != 1)
12834             {
12835               if (l != 1 || len != 2 || last[0] != 'X')
12836                 {
12837                   SAVE_LAST (*p);
12838                   break;
12839                 }
12840               if (!need_vex || !vex.evex)
12841                 abort ();
12842               if (intel_syntax
12843                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12844                 break;
12845               switch (vex.length)
12846                 {
12847                 case 128:
12848                   *obufp++ = 'x';
12849                   break;
12850                 case 256:
12851                   *obufp++ = 'y';
12852                   break;
12853                 case 512:
12854                   *obufp++ = 'z';
12855                   break;
12856                 default:
12857                   abort ();
12858                 }
12859               break;
12860             }
12861           if (intel_syntax)
12862             break;
12863           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12864             {
12865               *obufp++ = 'q';
12866               break;
12867             }
12868           /* Fall through.  */
12869           goto case_L;
12870         case 'L':
12871           if (l != 0 || len != 1)
12872             {
12873               SAVE_LAST (*p);
12874               break;
12875             }
12876 case_L:
12877           if (intel_syntax)
12878             break;
12879           if (sizeflag & SUFFIX_ALWAYS)
12880             *obufp++ = 'l';
12881           break;
12882         case 'M':
12883           if (intel_mnemonic != cond)
12884             *obufp++ = 'r';
12885           break;
12886         case 'N':
12887           if ((prefixes & PREFIX_FWAIT) == 0)
12888             *obufp++ = 'n';
12889           else
12890             used_prefixes |= PREFIX_FWAIT;
12891           break;
12892         case 'O':
12893           USED_REX (REX_W);
12894           if (rex & REX_W)
12895             *obufp++ = 'o';
12896           else if (intel_syntax && (sizeflag & DFLAG))
12897             *obufp++ = 'q';
12898           else
12899             *obufp++ = 'd';
12900           if (!(rex & REX_W))
12901             used_prefixes |= (prefixes & PREFIX_DATA);
12902           break;
12903         case '&':
12904           if (!intel_syntax
12905               && address_mode == mode_64bit
12906               && isa64 == intel64)
12907             {
12908               *obufp++ = 'q';
12909               break;
12910             }
12911           /* Fall through.  */
12912         case 'T':
12913           if (!intel_syntax
12914               && address_mode == mode_64bit
12915               && ((sizeflag & DFLAG) || (rex & REX_W)))
12916             {
12917               *obufp++ = 'q';
12918               break;
12919             }
12920           /* Fall through.  */
12921           goto case_P;
12922         case 'P':
12923           if (l == 0 && len == 1)
12924             {
12925 case_P:
12926               if (intel_syntax)
12927                 {
12928                   if ((rex & REX_W) == 0
12929                       && (prefixes & PREFIX_DATA))
12930                     {
12931                       if ((sizeflag & DFLAG) == 0)
12932                         *obufp++ = 'w';
12933                       used_prefixes |= (prefixes & PREFIX_DATA);
12934                     }
12935                   break;
12936                 }
12937               if ((prefixes & PREFIX_DATA)
12938                   || (rex & REX_W)
12939                   || (sizeflag & SUFFIX_ALWAYS))
12940                 {
12941                   USED_REX (REX_W);
12942                   if (rex & REX_W)
12943                     *obufp++ = 'q';
12944                   else
12945                     {
12946                       if (sizeflag & DFLAG)
12947                         *obufp++ = 'l';
12948                       else
12949                         *obufp++ = 'w';
12950                       used_prefixes |= (prefixes & PREFIX_DATA);
12951                     }
12952                 }
12953             }
12954           else
12955             {
12956               if (l != 1 || len != 2 || last[0] != 'L')
12957                 {
12958                   SAVE_LAST (*p);
12959                   break;
12960                 }
12961
12962               if ((prefixes & PREFIX_DATA)
12963                   || (rex & REX_W)
12964                   || (sizeflag & SUFFIX_ALWAYS))
12965                 {
12966                   USED_REX (REX_W);
12967                   if (rex & REX_W)
12968                     *obufp++ = 'q';
12969                   else
12970                     {
12971                       if (sizeflag & DFLAG)
12972                         *obufp++ = intel_syntax ? 'd' : 'l';
12973                       else
12974                         *obufp++ = 'w';
12975                       used_prefixes |= (prefixes & PREFIX_DATA);
12976                     }
12977                 }
12978             }
12979           break;
12980         case 'U':
12981           if (intel_syntax)
12982             break;
12983           if (address_mode == mode_64bit
12984               && ((sizeflag & DFLAG) || (rex & REX_W)))
12985             {
12986               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12987                 *obufp++ = 'q';
12988               break;
12989             }
12990           /* Fall through.  */
12991           goto case_Q;
12992         case 'Q':
12993           if (l == 0 && len == 1)
12994             {
12995 case_Q:
12996               if (intel_syntax && !alt)
12997                 break;
12998               USED_REX (REX_W);
12999               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13000                 {
13001                   if (rex & REX_W)
13002                     *obufp++ = 'q';
13003                   else
13004                     {
13005                       if (sizeflag & DFLAG)
13006                         *obufp++ = intel_syntax ? 'd' : 'l';
13007                       else
13008                         *obufp++ = 'w';
13009                       used_prefixes |= (prefixes & PREFIX_DATA);
13010                     }
13011                 }
13012             }
13013           else
13014             {
13015               if (l != 1 || len != 2 || last[0] != 'L')
13016                 {
13017                   SAVE_LAST (*p);
13018                   break;
13019                 }
13020               if (intel_syntax
13021                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13022                 break;
13023               if ((rex & REX_W))
13024                 {
13025                   USED_REX (REX_W);
13026                   *obufp++ = 'q';
13027                 }
13028               else
13029                 *obufp++ = 'l';
13030             }
13031           break;
13032         case 'R':
13033           USED_REX (REX_W);
13034           if (rex & REX_W)
13035             *obufp++ = 'q';
13036           else if (sizeflag & DFLAG)
13037             {
13038               if (intel_syntax)
13039                   *obufp++ = 'd';
13040               else
13041                   *obufp++ = 'l';
13042             }
13043           else
13044             *obufp++ = 'w';
13045           if (intel_syntax && !p[1]
13046               && ((rex & REX_W) || (sizeflag & DFLAG)))
13047             *obufp++ = 'e';
13048           if (!(rex & REX_W))
13049             used_prefixes |= (prefixes & PREFIX_DATA);
13050           break;
13051         case 'V':
13052           if (l == 0 && len == 1)
13053             {
13054               if (intel_syntax)
13055                 break;
13056               if (address_mode == mode_64bit
13057                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13058                 {
13059                   if (sizeflag & SUFFIX_ALWAYS)
13060                     *obufp++ = 'q';
13061                   break;
13062                 }
13063             }
13064           else
13065             {
13066               if (l != 1
13067                   || len != 2
13068                   || last[0] != 'L')
13069                 {
13070                   SAVE_LAST (*p);
13071                   break;
13072                 }
13073
13074               if (rex & REX_W)
13075                 {
13076                   *obufp++ = 'a';
13077                   *obufp++ = 'b';
13078                   *obufp++ = 's';
13079                 }
13080             }
13081           /* Fall through.  */
13082           goto case_S;
13083         case 'S':
13084           if (l == 0 && len == 1)
13085             {
13086 case_S:
13087               if (intel_syntax)
13088                 break;
13089               if (sizeflag & SUFFIX_ALWAYS)
13090                 {
13091                   if (rex & REX_W)
13092                     *obufp++ = 'q';
13093                   else
13094                     {
13095                       if (sizeflag & DFLAG)
13096                         *obufp++ = 'l';
13097                       else
13098                         *obufp++ = 'w';
13099                       used_prefixes |= (prefixes & PREFIX_DATA);
13100                     }
13101                 }
13102             }
13103           else
13104             {
13105               if (l != 1
13106                   || len != 2
13107                   || last[0] != 'L')
13108                 {
13109                   SAVE_LAST (*p);
13110                   break;
13111                 }
13112
13113               if (address_mode == mode_64bit
13114                   && !(prefixes & PREFIX_ADDR))
13115                 {
13116                   *obufp++ = 'a';
13117                   *obufp++ = 'b';
13118                   *obufp++ = 's';
13119                 }
13120
13121               goto case_S;
13122             }
13123           break;
13124         case 'X':
13125           if (l != 0 || len != 1)
13126             {
13127               SAVE_LAST (*p);
13128               break;
13129             }
13130           if (need_vex && vex.prefix)
13131             {
13132               if (vex.prefix == DATA_PREFIX_OPCODE)
13133                 *obufp++ = 'd';
13134               else
13135                 *obufp++ = 's';
13136             }
13137           else
13138             {
13139               if (prefixes & PREFIX_DATA)
13140                 *obufp++ = 'd';
13141               else
13142                 *obufp++ = 's';
13143               used_prefixes |= (prefixes & PREFIX_DATA);
13144             }
13145           break;
13146         case 'Y':
13147           if (l == 0 && len == 1)
13148             abort ();
13149           else
13150             {
13151               if (l != 1 || len != 2 || last[0] != 'X')
13152                 {
13153                   SAVE_LAST (*p);
13154                   break;
13155                 }
13156               if (!need_vex)
13157                 abort ();
13158               if (intel_syntax
13159                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13160                 break;
13161               switch (vex.length)
13162                 {
13163                 case 128:
13164                   *obufp++ = 'x';
13165                   break;
13166                 case 256:
13167                   *obufp++ = 'y';
13168                   break;
13169                 case 512:
13170                   if (!vex.evex)
13171                 default:
13172                     abort ();
13173                 }
13174             }
13175           break;
13176         case 'W':
13177           if (l == 0 && len == 1)
13178             {
13179               /* operand size flag for cwtl, cbtw */
13180               USED_REX (REX_W);
13181               if (rex & REX_W)
13182                 {
13183                   if (intel_syntax)
13184                     *obufp++ = 'd';
13185                   else
13186                     *obufp++ = 'l';
13187                 }
13188               else if (sizeflag & DFLAG)
13189                 *obufp++ = 'w';
13190               else
13191                 *obufp++ = 'b';
13192               if (!(rex & REX_W))
13193                 used_prefixes |= (prefixes & PREFIX_DATA);
13194             }
13195           else
13196             {
13197               if (l != 1
13198                   || len != 2
13199                   || (last[0] != 'X'
13200                       && last[0] != 'L'))
13201                 {
13202                   SAVE_LAST (*p);
13203                   break;
13204                 }
13205               if (!need_vex)
13206                 abort ();
13207               if (last[0] == 'X')
13208                 *obufp++ = vex.w ? 'd': 's';
13209               else
13210                 *obufp++ = vex.w ? 'q': 'd';
13211             }
13212           break;
13213         case '^':
13214           if (intel_syntax)
13215             break;
13216           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13217             {
13218               if (sizeflag & DFLAG)
13219                 *obufp++ = 'l';
13220               else
13221                 *obufp++ = 'w';
13222               used_prefixes |= (prefixes & PREFIX_DATA);
13223             }
13224           break;
13225         case '@':
13226           if (intel_syntax)
13227             break;
13228           if (address_mode == mode_64bit
13229               && (isa64 == intel64
13230                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13231               *obufp++ = 'q';
13232           else if ((prefixes & PREFIX_DATA))
13233             {
13234               if (!(sizeflag & DFLAG))
13235                 *obufp++ = 'w';
13236               used_prefixes |= (prefixes & PREFIX_DATA);
13237             }
13238           break;
13239         }
13240       alt = 0;
13241     }
13242   *obufp = 0;
13243   mnemonicendp = obufp;
13244   return 0;
13245 }
13246
13247 static void
13248 oappend (const char *s)
13249 {
13250   obufp = stpcpy (obufp, s);
13251 }
13252
13253 static void
13254 append_seg (void)
13255 {
13256   /* Only print the active segment register.  */
13257   if (!active_seg_prefix)
13258     return;
13259
13260   used_prefixes |= active_seg_prefix;
13261   switch (active_seg_prefix)
13262     {
13263     case PREFIX_CS:
13264       oappend_maybe_intel ("%cs:");
13265       break;
13266     case PREFIX_DS:
13267       oappend_maybe_intel ("%ds:");
13268       break;
13269     case PREFIX_SS:
13270       oappend_maybe_intel ("%ss:");
13271       break;
13272     case PREFIX_ES:
13273       oappend_maybe_intel ("%es:");
13274       break;
13275     case PREFIX_FS:
13276       oappend_maybe_intel ("%fs:");
13277       break;
13278     case PREFIX_GS:
13279       oappend_maybe_intel ("%gs:");
13280       break;
13281     default:
13282       break;
13283     }
13284 }
13285
13286 static void
13287 OP_indirE (int bytemode, int sizeflag)
13288 {
13289   if (!intel_syntax)
13290     oappend ("*");
13291   OP_E (bytemode, sizeflag);
13292 }
13293
13294 static void
13295 print_operand_value (char *buf, int hex, bfd_vma disp)
13296 {
13297   if (address_mode == mode_64bit)
13298     {
13299       if (hex)
13300         {
13301           char tmp[30];
13302           int i;
13303           buf[0] = '0';
13304           buf[1] = 'x';
13305           sprintf_vma (tmp, disp);
13306           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13307           strcpy (buf + 2, tmp + i);
13308         }
13309       else
13310         {
13311           bfd_signed_vma v = disp;
13312           char tmp[30];
13313           int i;
13314           if (v < 0)
13315             {
13316               *(buf++) = '-';
13317               v = -disp;
13318               /* Check for possible overflow on 0x8000000000000000.  */
13319               if (v < 0)
13320                 {
13321                   strcpy (buf, "9223372036854775808");
13322                   return;
13323                 }
13324             }
13325           if (!v)
13326             {
13327               strcpy (buf, "0");
13328               return;
13329             }
13330
13331           i = 0;
13332           tmp[29] = 0;
13333           while (v)
13334             {
13335               tmp[28 - i] = (v % 10) + '0';
13336               v /= 10;
13337               i++;
13338             }
13339           strcpy (buf, tmp + 29 - i);
13340         }
13341     }
13342   else
13343     {
13344       if (hex)
13345         sprintf (buf, "0x%x", (unsigned int) disp);
13346       else
13347         sprintf (buf, "%d", (int) disp);
13348     }
13349 }
13350
13351 /* Put DISP in BUF as signed hex number.  */
13352
13353 static void
13354 print_displacement (char *buf, bfd_vma disp)
13355 {
13356   bfd_signed_vma val = disp;
13357   char tmp[30];
13358   int i, j = 0;
13359
13360   if (val < 0)
13361     {
13362       buf[j++] = '-';
13363       val = -disp;
13364
13365       /* Check for possible overflow.  */
13366       if (val < 0)
13367         {
13368           switch (address_mode)
13369             {
13370             case mode_64bit:
13371               strcpy (buf + j, "0x8000000000000000");
13372               break;
13373             case mode_32bit:
13374               strcpy (buf + j, "0x80000000");
13375               break;
13376             case mode_16bit:
13377               strcpy (buf + j, "0x8000");
13378               break;
13379             }
13380           return;
13381         }
13382     }
13383
13384   buf[j++] = '0';
13385   buf[j++] = 'x';
13386
13387   sprintf_vma (tmp, (bfd_vma) val);
13388   for (i = 0; tmp[i] == '0'; i++)
13389     continue;
13390   if (tmp[i] == '\0')
13391     i--;
13392   strcpy (buf + j, tmp + i);
13393 }
13394
13395 static void
13396 intel_operand_size (int bytemode, int sizeflag)
13397 {
13398   if (vex.evex
13399       && vex.b
13400       && (bytemode == x_mode
13401           || bytemode == evex_half_bcst_xmmq_mode))
13402     {
13403       if (vex.w)
13404         oappend ("QWORD PTR ");
13405       else
13406         oappend ("DWORD PTR ");
13407       return;
13408     }
13409   switch (bytemode)
13410     {
13411     case b_mode:
13412     case b_swap_mode:
13413     case dqb_mode:
13414     case db_mode:
13415       oappend ("BYTE PTR ");
13416       break;
13417     case w_mode:
13418     case dw_mode:
13419     case dqw_mode:
13420       oappend ("WORD PTR ");
13421       break;
13422     case indir_v_mode:
13423       if (address_mode == mode_64bit && isa64 == intel64)
13424         {
13425           oappend ("QWORD PTR ");
13426           break;
13427         }
13428       /* Fall through.  */
13429     case stack_v_mode:
13430       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13431         {
13432           oappend ("QWORD PTR ");
13433           break;
13434         }
13435       /* Fall through.  */
13436     case v_mode:
13437     case v_swap_mode:
13438     case dq_mode:
13439       USED_REX (REX_W);
13440       if (rex & REX_W)
13441         oappend ("QWORD PTR ");
13442       else
13443         {
13444           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13445             oappend ("DWORD PTR ");
13446           else
13447             oappend ("WORD PTR ");
13448           used_prefixes |= (prefixes & PREFIX_DATA);
13449         }
13450       break;
13451     case z_mode:
13452       if ((rex & REX_W) || (sizeflag & DFLAG))
13453         *obufp++ = 'D';
13454       oappend ("WORD PTR ");
13455       if (!(rex & REX_W))
13456         used_prefixes |= (prefixes & PREFIX_DATA);
13457       break;
13458     case a_mode:
13459       if (sizeflag & DFLAG)
13460         oappend ("QWORD PTR ");
13461       else
13462         oappend ("DWORD PTR ");
13463       used_prefixes |= (prefixes & PREFIX_DATA);
13464       break;
13465     case d_mode:
13466     case d_scalar_mode:
13467     case d_scalar_swap_mode:
13468     case d_swap_mode:
13469     case dqd_mode:
13470       oappend ("DWORD PTR ");
13471       break;
13472     case q_mode:
13473     case q_scalar_mode:
13474     case q_scalar_swap_mode:
13475     case q_swap_mode:
13476       oappend ("QWORD PTR ");
13477       break;
13478     case m_mode:
13479       if (address_mode == mode_64bit)
13480         oappend ("QWORD PTR ");
13481       else
13482         oappend ("DWORD PTR ");
13483       break;
13484     case f_mode:
13485       if (sizeflag & DFLAG)
13486         oappend ("FWORD PTR ");
13487       else
13488         oappend ("DWORD PTR ");
13489       used_prefixes |= (prefixes & PREFIX_DATA);
13490       break;
13491     case t_mode:
13492       oappend ("TBYTE PTR ");
13493       break;
13494     case x_mode:
13495     case x_swap_mode:
13496     case evex_x_gscat_mode:
13497     case evex_x_nobcst_mode:
13498     case b_scalar_mode:
13499     case w_scalar_mode:
13500       if (need_vex)
13501         {
13502           switch (vex.length)
13503             {
13504             case 128:
13505               oappend ("XMMWORD PTR ");
13506               break;
13507             case 256:
13508               oappend ("YMMWORD PTR ");
13509               break;
13510             case 512:
13511               oappend ("ZMMWORD PTR ");
13512               break;
13513             default:
13514               abort ();
13515             }
13516         }
13517       else
13518         oappend ("XMMWORD PTR ");
13519       break;
13520     case xmm_mode:
13521       oappend ("XMMWORD PTR ");
13522       break;
13523     case ymm_mode:
13524       oappend ("YMMWORD PTR ");
13525       break;
13526     case xmmq_mode:
13527     case evex_half_bcst_xmmq_mode:
13528       if (!need_vex)
13529         abort ();
13530
13531       switch (vex.length)
13532         {
13533         case 128:
13534           oappend ("QWORD PTR ");
13535           break;
13536         case 256:
13537           oappend ("XMMWORD PTR ");
13538           break;
13539         case 512:
13540           oappend ("YMMWORD PTR ");
13541           break;
13542         default:
13543           abort ();
13544         }
13545       break;
13546     case xmm_mb_mode:
13547       if (!need_vex)
13548         abort ();
13549
13550       switch (vex.length)
13551         {
13552         case 128:
13553         case 256:
13554         case 512:
13555           oappend ("BYTE PTR ");
13556           break;
13557         default:
13558           abort ();
13559         }
13560       break;
13561     case xmm_mw_mode:
13562       if (!need_vex)
13563         abort ();
13564
13565       switch (vex.length)
13566         {
13567         case 128:
13568         case 256:
13569         case 512:
13570           oappend ("WORD PTR ");
13571           break;
13572         default:
13573           abort ();
13574         }
13575       break;
13576     case xmm_md_mode:
13577       if (!need_vex)
13578         abort ();
13579
13580       switch (vex.length)
13581         {
13582         case 128:
13583         case 256:
13584         case 512:
13585           oappend ("DWORD PTR ");
13586           break;
13587         default:
13588           abort ();
13589         }
13590       break;
13591     case xmm_mq_mode:
13592       if (!need_vex)
13593         abort ();
13594
13595       switch (vex.length)
13596         {
13597         case 128:
13598         case 256:
13599         case 512:
13600           oappend ("QWORD PTR ");
13601           break;
13602         default:
13603           abort ();
13604         }
13605       break;
13606     case xmmdw_mode:
13607       if (!need_vex)
13608         abort ();
13609
13610       switch (vex.length)
13611         {
13612         case 128:
13613           oappend ("WORD PTR ");
13614           break;
13615         case 256:
13616           oappend ("DWORD PTR ");
13617           break;
13618         case 512:
13619           oappend ("QWORD PTR ");
13620           break;
13621         default:
13622           abort ();
13623         }
13624       break;
13625     case xmmqd_mode:
13626       if (!need_vex)
13627         abort ();
13628
13629       switch (vex.length)
13630         {
13631         case 128:
13632           oappend ("DWORD PTR ");
13633           break;
13634         case 256:
13635           oappend ("QWORD PTR ");
13636           break;
13637         case 512:
13638           oappend ("XMMWORD PTR ");
13639           break;
13640         default:
13641           abort ();
13642         }
13643       break;
13644     case ymmq_mode:
13645       if (!need_vex)
13646         abort ();
13647
13648       switch (vex.length)
13649         {
13650         case 128:
13651           oappend ("QWORD PTR ");
13652           break;
13653         case 256:
13654           oappend ("YMMWORD PTR ");
13655           break;
13656         case 512:
13657           oappend ("ZMMWORD PTR ");
13658           break;
13659         default:
13660           abort ();
13661         }
13662       break;
13663     case ymmxmm_mode:
13664       if (!need_vex)
13665         abort ();
13666
13667       switch (vex.length)
13668         {
13669         case 128:
13670         case 256:
13671           oappend ("XMMWORD PTR ");
13672           break;
13673         default:
13674           abort ();
13675         }
13676       break;
13677     case o_mode:
13678       oappend ("OWORD PTR ");
13679       break;
13680     case xmm_mdq_mode:
13681     case vex_w_dq_mode:
13682     case vex_scalar_w_dq_mode:
13683       if (!need_vex)
13684         abort ();
13685
13686       if (vex.w)
13687         oappend ("QWORD PTR ");
13688       else
13689         oappend ("DWORD PTR ");
13690       break;
13691     case vex_vsib_d_w_dq_mode:
13692     case vex_vsib_q_w_dq_mode:
13693       if (!need_vex)
13694         abort ();
13695
13696       if (!vex.evex)
13697         {
13698           if (vex.w)
13699             oappend ("QWORD PTR ");
13700           else
13701             oappend ("DWORD PTR ");
13702         }
13703       else
13704         {
13705           switch (vex.length)
13706             {
13707             case 128:
13708               oappend ("XMMWORD PTR ");
13709               break;
13710             case 256:
13711               oappend ("YMMWORD PTR ");
13712               break;
13713             case 512:
13714               oappend ("ZMMWORD PTR ");
13715               break;
13716             default:
13717               abort ();
13718             }
13719         }
13720       break;
13721     case vex_vsib_q_w_d_mode:
13722     case vex_vsib_d_w_d_mode:
13723       if (!need_vex || !vex.evex)
13724         abort ();
13725
13726       switch (vex.length)
13727         {
13728         case 128:
13729           oappend ("QWORD PTR ");
13730           break;
13731         case 256:
13732           oappend ("XMMWORD PTR ");
13733           break;
13734         case 512:
13735           oappend ("YMMWORD PTR ");
13736           break;
13737         default:
13738           abort ();
13739         }
13740
13741       break;
13742     case mask_bd_mode:
13743       if (!need_vex || vex.length != 128)
13744         abort ();
13745       if (vex.w)
13746         oappend ("DWORD PTR ");
13747       else
13748         oappend ("BYTE PTR ");
13749       break;
13750     case mask_mode:
13751       if (!need_vex)
13752         abort ();
13753       if (vex.w)
13754         oappend ("QWORD PTR ");
13755       else
13756         oappend ("WORD PTR ");
13757       break;
13758     case v_bnd_mode:
13759     case v_bndmk_mode:
13760     default:
13761       break;
13762     }
13763 }
13764
13765 static void
13766 OP_E_register (int bytemode, int sizeflag)
13767 {
13768   int reg = modrm.rm;
13769   const char **names;
13770
13771   USED_REX (REX_B);
13772   if ((rex & REX_B))
13773     reg += 8;
13774
13775   if ((sizeflag & SUFFIX_ALWAYS)
13776       && (bytemode == b_swap_mode
13777           || bytemode == bnd_swap_mode
13778           || bytemode == v_swap_mode))
13779     swap_operand ();
13780
13781   switch (bytemode)
13782     {
13783     case b_mode:
13784     case b_swap_mode:
13785       USED_REX (0);
13786       if (rex)
13787         names = names8rex;
13788       else
13789         names = names8;
13790       break;
13791     case w_mode:
13792       names = names16;
13793       break;
13794     case d_mode:
13795     case dw_mode:
13796     case db_mode:
13797       names = names32;
13798       break;
13799     case q_mode:
13800       names = names64;
13801       break;
13802     case m_mode:
13803     case v_bnd_mode:
13804       names = address_mode == mode_64bit ? names64 : names32;
13805       break;
13806     case bnd_mode:
13807     case bnd_swap_mode:
13808       if (reg > 0x3)
13809         {
13810           oappend ("(bad)");
13811           return;
13812         }
13813       names = names_bnd;
13814       break;
13815     case indir_v_mode:
13816       if (address_mode == mode_64bit && isa64 == intel64)
13817         {
13818           names = names64;
13819           break;
13820         }
13821       /* Fall through.  */
13822     case stack_v_mode:
13823       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13824         {
13825           names = names64;
13826           break;
13827         }
13828       bytemode = v_mode;
13829       /* Fall through.  */
13830     case v_mode:
13831     case v_swap_mode:
13832     case dq_mode:
13833     case dqb_mode:
13834     case dqd_mode:
13835     case dqw_mode:
13836       USED_REX (REX_W);
13837       if (rex & REX_W)
13838         names = names64;
13839       else
13840         {
13841           if ((sizeflag & DFLAG)
13842               || (bytemode != v_mode
13843                   && bytemode != v_swap_mode))
13844             names = names32;
13845           else
13846             names = names16;
13847           used_prefixes |= (prefixes & PREFIX_DATA);
13848         }
13849       break;
13850     case va_mode:
13851       names = (address_mode == mode_64bit
13852                ? names64 : names32);
13853       if (!(prefixes & PREFIX_ADDR))
13854         names = (address_mode == mode_16bit
13855                      ? names16 : names);
13856       else
13857         {
13858           /* Remove "addr16/addr32".  */
13859           all_prefixes[last_addr_prefix] = 0;
13860           names = (address_mode != mode_32bit
13861                        ? names32 : names16);
13862           used_prefixes |= PREFIX_ADDR;
13863         }
13864       break;
13865     case mask_bd_mode:
13866     case mask_mode:
13867       if (reg > 0x7)
13868         {
13869           oappend ("(bad)");
13870           return;
13871         }
13872       names = names_mask;
13873       break;
13874     case 0:
13875       return;
13876     default:
13877       oappend (INTERNAL_DISASSEMBLER_ERROR);
13878       return;
13879     }
13880   oappend (names[reg]);
13881 }
13882
13883 static void
13884 OP_E_memory (int bytemode, int sizeflag)
13885 {
13886   bfd_vma disp = 0;
13887   int add = (rex & REX_B) ? 8 : 0;
13888   int riprel = 0;
13889   int shift;
13890
13891   if (vex.evex)
13892     {
13893       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13894       if (vex.b
13895           && bytemode != x_mode
13896           && bytemode != xmmq_mode
13897           && bytemode != evex_half_bcst_xmmq_mode)
13898         {
13899           BadOp ();
13900           return;
13901         }
13902       switch (bytemode)
13903         {
13904         case dqw_mode:
13905         case dw_mode:
13906           shift = 1;
13907           break;
13908         case dqb_mode:
13909         case db_mode:
13910           shift = 0;
13911           break;
13912         case dq_mode:
13913           if (address_mode != mode_64bit)
13914             {
13915               shift = 2;
13916               break;
13917             }
13918             /* fall through */
13919         case vex_vsib_d_w_dq_mode:
13920         case vex_vsib_d_w_d_mode:
13921         case vex_vsib_q_w_dq_mode:
13922         case vex_vsib_q_w_d_mode:
13923         case evex_x_gscat_mode:
13924         case xmm_mdq_mode:
13925           shift = vex.w ? 3 : 2;
13926           break;
13927         case x_mode:
13928         case evex_half_bcst_xmmq_mode:
13929         case xmmq_mode:
13930           if (vex.b)
13931             {
13932               shift = vex.w ? 3 : 2;
13933               break;
13934             }
13935           /* Fall through.  */
13936         case xmmqd_mode:
13937         case xmmdw_mode:
13938         case ymmq_mode:
13939         case evex_x_nobcst_mode:
13940         case x_swap_mode:
13941           switch (vex.length)
13942             {
13943             case 128:
13944               shift = 4;
13945               break;
13946             case 256:
13947               shift = 5;
13948               break;
13949             case 512:
13950               shift = 6;
13951               break;
13952             default:
13953               abort ();
13954             }
13955           break;
13956         case ymm_mode:
13957           shift = 5;
13958           break;
13959         case xmm_mode:
13960           shift = 4;
13961           break;
13962         case xmm_mq_mode:
13963         case q_mode:
13964         case q_scalar_mode:
13965         case q_swap_mode:
13966         case q_scalar_swap_mode:
13967           shift = 3;
13968           break;
13969         case dqd_mode:
13970         case xmm_md_mode:
13971         case d_mode:
13972         case d_scalar_mode:
13973         case d_swap_mode:
13974         case d_scalar_swap_mode:
13975           shift = 2;
13976           break;
13977         case w_scalar_mode:
13978         case xmm_mw_mode:
13979           shift = 1;
13980           break;
13981         case b_scalar_mode:
13982         case xmm_mb_mode:
13983           shift = 0;
13984           break;
13985         default:
13986           abort ();
13987         }
13988       /* Make necessary corrections to shift for modes that need it.
13989          For these modes we currently have shift 4, 5 or 6 depending on
13990          vex.length (it corresponds to xmmword, ymmword or zmmword
13991          operand).  We might want to make it 3, 4 or 5 (e.g. for
13992          xmmq_mode).  In case of broadcast enabled the corrections
13993          aren't needed, as element size is always 32 or 64 bits.  */
13994       if (!vex.b
13995           && (bytemode == xmmq_mode
13996               || bytemode == evex_half_bcst_xmmq_mode))
13997         shift -= 1;
13998       else if (bytemode == xmmqd_mode)
13999         shift -= 2;
14000       else if (bytemode == xmmdw_mode)
14001         shift -= 3;
14002       else if (bytemode == ymmq_mode && vex.length == 128)
14003         shift -= 1;
14004     }
14005   else
14006     shift = 0;
14007
14008   USED_REX (REX_B);
14009   if (intel_syntax)
14010     intel_operand_size (bytemode, sizeflag);
14011   append_seg ();
14012
14013   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14014     {
14015       /* 32/64 bit address mode */
14016       int havedisp;
14017       int havesib;
14018       int havebase;
14019       int haveindex;
14020       int needindex;
14021       int needaddr32;
14022       int base, rbase;
14023       int vindex = 0;
14024       int scale = 0;
14025       int addr32flag = !((sizeflag & AFLAG)
14026                          || bytemode == v_bnd_mode
14027                          || bytemode == v_bndmk_mode
14028                          || bytemode == bnd_mode
14029                          || bytemode == bnd_swap_mode);
14030       const char **indexes64 = names64;
14031       const char **indexes32 = names32;
14032
14033       havesib = 0;
14034       havebase = 1;
14035       haveindex = 0;
14036       base = modrm.rm;
14037
14038       if (base == 4)
14039         {
14040           havesib = 1;
14041           vindex = sib.index;
14042           USED_REX (REX_X);
14043           if (rex & REX_X)
14044             vindex += 8;
14045           switch (bytemode)
14046             {
14047             case vex_vsib_d_w_dq_mode:
14048             case vex_vsib_d_w_d_mode:
14049             case vex_vsib_q_w_dq_mode:
14050             case vex_vsib_q_w_d_mode:
14051               if (!need_vex)
14052                 abort ();
14053               if (vex.evex)
14054                 {
14055                   if (!vex.v)
14056                     vindex += 16;
14057                 }
14058
14059               haveindex = 1;
14060               switch (vex.length)
14061                 {
14062                 case 128:
14063                   indexes64 = indexes32 = names_xmm;
14064                   break;
14065                 case 256:
14066                   if (!vex.w
14067                       || bytemode == vex_vsib_q_w_dq_mode
14068                       || bytemode == vex_vsib_q_w_d_mode)
14069                     indexes64 = indexes32 = names_ymm;
14070                   else
14071                     indexes64 = indexes32 = names_xmm;
14072                   break;
14073                 case 512:
14074                   if (!vex.w
14075                       || bytemode == vex_vsib_q_w_dq_mode
14076                       || bytemode == vex_vsib_q_w_d_mode)
14077                     indexes64 = indexes32 = names_zmm;
14078                   else
14079                     indexes64 = indexes32 = names_ymm;
14080                   break;
14081                 default:
14082                   abort ();
14083                 }
14084               break;
14085             default:
14086               haveindex = vindex != 4;
14087               break;
14088             }
14089           scale = sib.scale;
14090           base = sib.base;
14091           codep++;
14092         }
14093       rbase = base + add;
14094
14095       switch (modrm.mod)
14096         {
14097         case 0:
14098           if (base == 5)
14099             {
14100               havebase = 0;
14101               if (address_mode == mode_64bit && !havesib)
14102                 riprel = 1;
14103               disp = get32s ();
14104               if (riprel && bytemode == v_bndmk_mode)
14105                 {
14106                   oappend ("(bad)");
14107                   return;
14108                 }
14109             }
14110           break;
14111         case 1:
14112           FETCH_DATA (the_info, codep + 1);
14113           disp = *codep++;
14114           if ((disp & 0x80) != 0)
14115             disp -= 0x100;
14116           if (vex.evex && shift > 0)
14117             disp <<= shift;
14118           break;
14119         case 2:
14120           disp = get32s ();
14121           break;
14122         }
14123
14124       needindex = 0;
14125       needaddr32 = 0;
14126       if (havesib
14127           && !havebase
14128           && !haveindex
14129           && address_mode != mode_16bit)
14130         {
14131           if (address_mode == mode_64bit)
14132             {
14133               /* Display eiz instead of addr32.  */
14134               needindex = addr32flag;
14135               needaddr32 = 1;
14136             }
14137           else
14138             {
14139               /* In 32-bit mode, we need index register to tell [offset]
14140                  from [eiz*1 + offset].  */
14141               needindex = 1;
14142             }
14143         }
14144
14145       havedisp = (havebase
14146                   || needindex
14147                   || (havesib && (haveindex || scale != 0)));
14148
14149       if (!intel_syntax)
14150         if (modrm.mod != 0 || base == 5)
14151           {
14152             if (havedisp || riprel)
14153               print_displacement (scratchbuf, disp);
14154             else
14155               print_operand_value (scratchbuf, 1, disp);
14156             oappend (scratchbuf);
14157             if (riprel)
14158               {
14159                 set_op (disp, 1);
14160                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14161               }
14162           }
14163
14164       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14165           && (bytemode != v_bnd_mode)
14166           && (bytemode != v_bndmk_mode)
14167           && (bytemode != bnd_mode)
14168           && (bytemode != bnd_swap_mode))
14169         used_prefixes |= PREFIX_ADDR;
14170
14171       if (havedisp || (intel_syntax && riprel))
14172         {
14173           *obufp++ = open_char;
14174           if (intel_syntax && riprel)
14175             {
14176               set_op (disp, 1);
14177               oappend (!addr32flag ? "rip" : "eip");
14178             }
14179           *obufp = '\0';
14180           if (havebase)
14181             oappend (address_mode == mode_64bit && !addr32flag
14182                      ? names64[rbase] : names32[rbase]);
14183           if (havesib)
14184             {
14185               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14186                  print index to tell base + index from base.  */
14187               if (scale != 0
14188                   || needindex
14189                   || haveindex
14190                   || (havebase && base != ESP_REG_NUM))
14191                 {
14192                   if (!intel_syntax || havebase)
14193                     {
14194                       *obufp++ = separator_char;
14195                       *obufp = '\0';
14196                     }
14197                   if (haveindex)
14198                     oappend (address_mode == mode_64bit && !addr32flag
14199                              ? indexes64[vindex] : indexes32[vindex]);
14200                   else
14201                     oappend (address_mode == mode_64bit && !addr32flag
14202                              ? index64 : index32);
14203
14204                   *obufp++ = scale_char;
14205                   *obufp = '\0';
14206                   sprintf (scratchbuf, "%d", 1 << scale);
14207                   oappend (scratchbuf);
14208                 }
14209             }
14210           if (intel_syntax
14211               && (disp || modrm.mod != 0 || base == 5))
14212             {
14213               if (!havedisp || (bfd_signed_vma) disp >= 0)
14214                 {
14215                   *obufp++ = '+';
14216                   *obufp = '\0';
14217                 }
14218               else if (modrm.mod != 1 && disp != -disp)
14219                 {
14220                   *obufp++ = '-';
14221                   *obufp = '\0';
14222                   disp = - (bfd_signed_vma) disp;
14223                 }
14224
14225               if (havedisp)
14226                 print_displacement (scratchbuf, disp);
14227               else
14228                 print_operand_value (scratchbuf, 1, disp);
14229               oappend (scratchbuf);
14230             }
14231
14232           *obufp++ = close_char;
14233           *obufp = '\0';
14234         }
14235       else if (intel_syntax)
14236         {
14237           if (modrm.mod != 0 || base == 5)
14238             {
14239               if (!active_seg_prefix)
14240                 {
14241                   oappend (names_seg[ds_reg - es_reg]);
14242                   oappend (":");
14243                 }
14244               print_operand_value (scratchbuf, 1, disp);
14245               oappend (scratchbuf);
14246             }
14247         }
14248     }
14249   else
14250     {
14251       /* 16 bit address mode */
14252       used_prefixes |= prefixes & PREFIX_ADDR;
14253       switch (modrm.mod)
14254         {
14255         case 0:
14256           if (modrm.rm == 6)
14257             {
14258               disp = get16 ();
14259               if ((disp & 0x8000) != 0)
14260                 disp -= 0x10000;
14261             }
14262           break;
14263         case 1:
14264           FETCH_DATA (the_info, codep + 1);
14265           disp = *codep++;
14266           if ((disp & 0x80) != 0)
14267             disp -= 0x100;
14268           if (vex.evex && shift > 0)
14269             disp <<= shift;
14270           break;
14271         case 2:
14272           disp = get16 ();
14273           if ((disp & 0x8000) != 0)
14274             disp -= 0x10000;
14275           break;
14276         }
14277
14278       if (!intel_syntax)
14279         if (modrm.mod != 0 || modrm.rm == 6)
14280           {
14281             print_displacement (scratchbuf, disp);
14282             oappend (scratchbuf);
14283           }
14284
14285       if (modrm.mod != 0 || modrm.rm != 6)
14286         {
14287           *obufp++ = open_char;
14288           *obufp = '\0';
14289           oappend (index16[modrm.rm]);
14290           if (intel_syntax
14291               && (disp || modrm.mod != 0 || modrm.rm == 6))
14292             {
14293               if ((bfd_signed_vma) disp >= 0)
14294                 {
14295                   *obufp++ = '+';
14296                   *obufp = '\0';
14297                 }
14298               else if (modrm.mod != 1)
14299                 {
14300                   *obufp++ = '-';
14301                   *obufp = '\0';
14302                   disp = - (bfd_signed_vma) disp;
14303                 }
14304
14305               print_displacement (scratchbuf, disp);
14306               oappend (scratchbuf);
14307             }
14308
14309           *obufp++ = close_char;
14310           *obufp = '\0';
14311         }
14312       else if (intel_syntax)
14313         {
14314           if (!active_seg_prefix)
14315             {
14316               oappend (names_seg[ds_reg - es_reg]);
14317               oappend (":");
14318             }
14319           print_operand_value (scratchbuf, 1, disp & 0xffff);
14320           oappend (scratchbuf);
14321         }
14322     }
14323   if (vex.evex && vex.b
14324       && (bytemode == x_mode
14325           || bytemode == xmmq_mode
14326           || bytemode == evex_half_bcst_xmmq_mode))
14327     {
14328       if (vex.w
14329           || bytemode == xmmq_mode
14330           || bytemode == evex_half_bcst_xmmq_mode)
14331         {
14332           switch (vex.length)
14333             {
14334             case 128:
14335               oappend ("{1to2}");
14336               break;
14337             case 256:
14338               oappend ("{1to4}");
14339               break;
14340             case 512:
14341               oappend ("{1to8}");
14342               break;
14343             default:
14344               abort ();
14345             }
14346         }
14347       else
14348         {
14349           switch (vex.length)
14350             {
14351             case 128:
14352               oappend ("{1to4}");
14353               break;
14354             case 256:
14355               oappend ("{1to8}");
14356               break;
14357             case 512:
14358               oappend ("{1to16}");
14359               break;
14360             default:
14361               abort ();
14362             }
14363         }
14364     }
14365 }
14366
14367 static void
14368 OP_E (int bytemode, int sizeflag)
14369 {
14370   /* Skip mod/rm byte.  */
14371   MODRM_CHECK;
14372   codep++;
14373
14374   if (modrm.mod == 3)
14375     OP_E_register (bytemode, sizeflag);
14376   else
14377     OP_E_memory (bytemode, sizeflag);
14378 }
14379
14380 static void
14381 OP_G (int bytemode, int sizeflag)
14382 {
14383   int add = 0;
14384   const char **names;
14385   USED_REX (REX_R);
14386   if (rex & REX_R)
14387     add += 8;
14388   switch (bytemode)
14389     {
14390     case b_mode:
14391       USED_REX (0);
14392       if (rex)
14393         oappend (names8rex[modrm.reg + add]);
14394       else
14395         oappend (names8[modrm.reg + add]);
14396       break;
14397     case w_mode:
14398       oappend (names16[modrm.reg + add]);
14399       break;
14400     case d_mode:
14401     case db_mode:
14402     case dw_mode:
14403       oappend (names32[modrm.reg + add]);
14404       break;
14405     case q_mode:
14406       oappend (names64[modrm.reg + add]);
14407       break;
14408     case bnd_mode:
14409       if (modrm.reg > 0x3)
14410         {
14411           oappend ("(bad)");
14412           return;
14413         }
14414       oappend (names_bnd[modrm.reg]);
14415       break;
14416     case v_mode:
14417     case dq_mode:
14418     case dqb_mode:
14419     case dqd_mode:
14420     case dqw_mode:
14421       USED_REX (REX_W);
14422       if (rex & REX_W)
14423         oappend (names64[modrm.reg + add]);
14424       else
14425         {
14426           if ((sizeflag & DFLAG) || bytemode != v_mode)
14427             oappend (names32[modrm.reg + add]);
14428           else
14429             oappend (names16[modrm.reg + add]);
14430           used_prefixes |= (prefixes & PREFIX_DATA);
14431         }
14432       break;
14433     case va_mode:
14434       names = (address_mode == mode_64bit
14435                ? names64 : names32);
14436       if (!(prefixes & PREFIX_ADDR))
14437         {
14438           if (address_mode == mode_16bit)
14439             names = names16;
14440         }
14441       else
14442         {
14443           /* Remove "addr16/addr32".  */
14444           all_prefixes[last_addr_prefix] = 0;
14445           names = (address_mode != mode_32bit
14446                        ? names32 : names16);
14447           used_prefixes |= PREFIX_ADDR;
14448         }
14449       oappend (names[modrm.reg + add]);
14450       break;
14451     case m_mode:
14452       if (address_mode == mode_64bit)
14453         oappend (names64[modrm.reg + add]);
14454       else
14455         oappend (names32[modrm.reg + add]);
14456       break;
14457     case mask_bd_mode:
14458     case mask_mode:
14459       if ((modrm.reg + add) > 0x7)
14460         {
14461           oappend ("(bad)");
14462           return;
14463         }
14464       oappend (names_mask[modrm.reg + add]);
14465       break;
14466     default:
14467       oappend (INTERNAL_DISASSEMBLER_ERROR);
14468       break;
14469     }
14470 }
14471
14472 static bfd_vma
14473 get64 (void)
14474 {
14475   bfd_vma x;
14476 #ifdef BFD64
14477   unsigned int a;
14478   unsigned int b;
14479
14480   FETCH_DATA (the_info, codep + 8);
14481   a = *codep++ & 0xff;
14482   a |= (*codep++ & 0xff) << 8;
14483   a |= (*codep++ & 0xff) << 16;
14484   a |= (*codep++ & 0xffu) << 24;
14485   b = *codep++ & 0xff;
14486   b |= (*codep++ & 0xff) << 8;
14487   b |= (*codep++ & 0xff) << 16;
14488   b |= (*codep++ & 0xffu) << 24;
14489   x = a + ((bfd_vma) b << 32);
14490 #else
14491   abort ();
14492   x = 0;
14493 #endif
14494   return x;
14495 }
14496
14497 static bfd_signed_vma
14498 get32 (void)
14499 {
14500   bfd_signed_vma x = 0;
14501
14502   FETCH_DATA (the_info, codep + 4);
14503   x = *codep++ & (bfd_signed_vma) 0xff;
14504   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14505   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14506   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14507   return x;
14508 }
14509
14510 static bfd_signed_vma
14511 get32s (void)
14512 {
14513   bfd_signed_vma x = 0;
14514
14515   FETCH_DATA (the_info, codep + 4);
14516   x = *codep++ & (bfd_signed_vma) 0xff;
14517   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14518   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14519   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14520
14521   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14522
14523   return x;
14524 }
14525
14526 static int
14527 get16 (void)
14528 {
14529   int x = 0;
14530
14531   FETCH_DATA (the_info, codep + 2);
14532   x = *codep++ & 0xff;
14533   x |= (*codep++ & 0xff) << 8;
14534   return x;
14535 }
14536
14537 static void
14538 set_op (bfd_vma op, int riprel)
14539 {
14540   op_index[op_ad] = op_ad;
14541   if (address_mode == mode_64bit)
14542     {
14543       op_address[op_ad] = op;
14544       op_riprel[op_ad] = riprel;
14545     }
14546   else
14547     {
14548       /* Mask to get a 32-bit address.  */
14549       op_address[op_ad] = op & 0xffffffff;
14550       op_riprel[op_ad] = riprel & 0xffffffff;
14551     }
14552 }
14553
14554 static void
14555 OP_REG (int code, int sizeflag)
14556 {
14557   const char *s;
14558   int add;
14559
14560   switch (code)
14561     {
14562     case es_reg: case ss_reg: case cs_reg:
14563     case ds_reg: case fs_reg: case gs_reg:
14564       oappend (names_seg[code - es_reg]);
14565       return;
14566     }
14567
14568   USED_REX (REX_B);
14569   if (rex & REX_B)
14570     add = 8;
14571   else
14572     add = 0;
14573
14574   switch (code)
14575     {
14576     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14577     case sp_reg: case bp_reg: case si_reg: case di_reg:
14578       s = names16[code - ax_reg + add];
14579       break;
14580     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14581     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14582       USED_REX (0);
14583       if (rex)
14584         s = names8rex[code - al_reg + add];
14585       else
14586         s = names8[code - al_reg];
14587       break;
14588     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14589     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14590       if (address_mode == mode_64bit
14591           && ((sizeflag & DFLAG) || (rex & REX_W)))
14592         {
14593           s = names64[code - rAX_reg + add];
14594           break;
14595         }
14596       code += eAX_reg - rAX_reg;
14597       /* Fall through.  */
14598     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14599     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14600       USED_REX (REX_W);
14601       if (rex & REX_W)
14602         s = names64[code - eAX_reg + add];
14603       else
14604         {
14605           if (sizeflag & DFLAG)
14606             s = names32[code - eAX_reg + add];
14607           else
14608             s = names16[code - eAX_reg + add];
14609           used_prefixes |= (prefixes & PREFIX_DATA);
14610         }
14611       break;
14612     default:
14613       s = INTERNAL_DISASSEMBLER_ERROR;
14614       break;
14615     }
14616   oappend (s);
14617 }
14618
14619 static void
14620 OP_IMREG (int code, int sizeflag)
14621 {
14622   const char *s;
14623
14624   switch (code)
14625     {
14626     case indir_dx_reg:
14627       if (intel_syntax)
14628         s = "dx";
14629       else
14630         s = "(%dx)";
14631       break;
14632     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14633     case sp_reg: case bp_reg: case si_reg: case di_reg:
14634       s = names16[code - ax_reg];
14635       break;
14636     case es_reg: case ss_reg: case cs_reg:
14637     case ds_reg: case fs_reg: case gs_reg:
14638       s = names_seg[code - es_reg];
14639       break;
14640     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14641     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14642       USED_REX (0);
14643       if (rex)
14644         s = names8rex[code - al_reg];
14645       else
14646         s = names8[code - al_reg];
14647       break;
14648     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14649     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14650       USED_REX (REX_W);
14651       if (rex & REX_W)
14652         s = names64[code - eAX_reg];
14653       else
14654         {
14655           if (sizeflag & DFLAG)
14656             s = names32[code - eAX_reg];
14657           else
14658             s = names16[code - eAX_reg];
14659           used_prefixes |= (prefixes & PREFIX_DATA);
14660         }
14661       break;
14662     case z_mode_ax_reg:
14663       if ((rex & REX_W) || (sizeflag & DFLAG))
14664         s = *names32;
14665       else
14666         s = *names16;
14667       if (!(rex & REX_W))
14668         used_prefixes |= (prefixes & PREFIX_DATA);
14669       break;
14670     default:
14671       s = INTERNAL_DISASSEMBLER_ERROR;
14672       break;
14673     }
14674   oappend (s);
14675 }
14676
14677 static void
14678 OP_I (int bytemode, int sizeflag)
14679 {
14680   bfd_signed_vma op;
14681   bfd_signed_vma mask = -1;
14682
14683   switch (bytemode)
14684     {
14685     case b_mode:
14686       FETCH_DATA (the_info, codep + 1);
14687       op = *codep++;
14688       mask = 0xff;
14689       break;
14690     case v_mode:
14691       USED_REX (REX_W);
14692       if (rex & REX_W)
14693         op = get32s ();
14694       else
14695         {
14696           if (sizeflag & DFLAG)
14697             {
14698               op = get32 ();
14699               mask = 0xffffffff;
14700             }
14701           else
14702             {
14703               op = get16 ();
14704               mask = 0xfffff;
14705             }
14706           used_prefixes |= (prefixes & PREFIX_DATA);
14707         }
14708       break;
14709     case d_mode:
14710       mask = 0xffffffff;
14711       op = get32 ();
14712       break;
14713     case w_mode:
14714       mask = 0xfffff;
14715       op = get16 ();
14716       break;
14717     case const_1_mode:
14718       if (intel_syntax)
14719         oappend ("1");
14720       return;
14721     default:
14722       oappend (INTERNAL_DISASSEMBLER_ERROR);
14723       return;
14724     }
14725
14726   op &= mask;
14727   scratchbuf[0] = '$';
14728   print_operand_value (scratchbuf + 1, 1, op);
14729   oappend_maybe_intel (scratchbuf);
14730   scratchbuf[0] = '\0';
14731 }
14732
14733 static void
14734 OP_I64 (int bytemode, int sizeflag)
14735 {
14736   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14737     {
14738       OP_I (bytemode, sizeflag);
14739       return;
14740     }
14741
14742   USED_REX (REX_W);
14743
14744   scratchbuf[0] = '$';
14745   print_operand_value (scratchbuf + 1, 1, get64 ());
14746   oappend_maybe_intel (scratchbuf);
14747   scratchbuf[0] = '\0';
14748 }
14749
14750 static void
14751 OP_sI (int bytemode, int sizeflag)
14752 {
14753   bfd_signed_vma op;
14754
14755   switch (bytemode)
14756     {
14757     case b_mode:
14758     case b_T_mode:
14759       FETCH_DATA (the_info, codep + 1);
14760       op = *codep++;
14761       if ((op & 0x80) != 0)
14762         op -= 0x100;
14763       if (bytemode == b_T_mode)
14764         {
14765           if (address_mode != mode_64bit
14766               || !((sizeflag & DFLAG) || (rex & REX_W)))
14767             {
14768               /* The operand-size prefix is overridden by a REX prefix.  */
14769               if ((sizeflag & DFLAG) || (rex & REX_W))
14770                 op &= 0xffffffff;
14771               else
14772                 op &= 0xffff;
14773           }
14774         }
14775       else
14776         {
14777           if (!(rex & REX_W))
14778             {
14779               if (sizeflag & DFLAG)
14780                 op &= 0xffffffff;
14781               else
14782                 op &= 0xffff;
14783             }
14784         }
14785       break;
14786     case v_mode:
14787       /* The operand-size prefix is overridden by a REX prefix.  */
14788       if ((sizeflag & DFLAG) || (rex & REX_W))
14789         op = get32s ();
14790       else
14791         op = get16 ();
14792       break;
14793     default:
14794       oappend (INTERNAL_DISASSEMBLER_ERROR);
14795       return;
14796     }
14797
14798   scratchbuf[0] = '$';
14799   print_operand_value (scratchbuf + 1, 1, op);
14800   oappend_maybe_intel (scratchbuf);
14801 }
14802
14803 static void
14804 OP_J (int bytemode, int sizeflag)
14805 {
14806   bfd_vma disp;
14807   bfd_vma mask = -1;
14808   bfd_vma segment = 0;
14809
14810   switch (bytemode)
14811     {
14812     case b_mode:
14813       FETCH_DATA (the_info, codep + 1);
14814       disp = *codep++;
14815       if ((disp & 0x80) != 0)
14816         disp -= 0x100;
14817       break;
14818     case v_mode:
14819       if (isa64 == amd64)
14820         USED_REX (REX_W);
14821       if ((sizeflag & DFLAG)
14822           || (address_mode == mode_64bit
14823               && (isa64 != amd64 || (rex & REX_W))))
14824         disp = get32s ();
14825       else
14826         {
14827           disp = get16 ();
14828           if ((disp & 0x8000) != 0)
14829             disp -= 0x10000;
14830           /* In 16bit mode, address is wrapped around at 64k within
14831              the same segment.  Otherwise, a data16 prefix on a jump
14832              instruction means that the pc is masked to 16 bits after
14833              the displacement is added!  */
14834           mask = 0xffff;
14835           if ((prefixes & PREFIX_DATA) == 0)
14836             segment = ((start_pc + (codep - start_codep))
14837                        & ~((bfd_vma) 0xffff));
14838         }
14839       if (address_mode != mode_64bit
14840           || (isa64 == amd64 && !(rex & REX_W)))
14841         used_prefixes |= (prefixes & PREFIX_DATA);
14842       break;
14843     default:
14844       oappend (INTERNAL_DISASSEMBLER_ERROR);
14845       return;
14846     }
14847   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14848   set_op (disp, 0);
14849   print_operand_value (scratchbuf, 1, disp);
14850   oappend (scratchbuf);
14851 }
14852
14853 static void
14854 OP_SEG (int bytemode, int sizeflag)
14855 {
14856   if (bytemode == w_mode)
14857     oappend (names_seg[modrm.reg]);
14858   else
14859     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14860 }
14861
14862 static void
14863 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14864 {
14865   int seg, offset;
14866
14867   if (sizeflag & DFLAG)
14868     {
14869       offset = get32 ();
14870       seg = get16 ();
14871     }
14872   else
14873     {
14874       offset = get16 ();
14875       seg = get16 ();
14876     }
14877   used_prefixes |= (prefixes & PREFIX_DATA);
14878   if (intel_syntax)
14879     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14880   else
14881     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14882   oappend (scratchbuf);
14883 }
14884
14885 static void
14886 OP_OFF (int bytemode, int sizeflag)
14887 {
14888   bfd_vma off;
14889
14890   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14891     intel_operand_size (bytemode, sizeflag);
14892   append_seg ();
14893
14894   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14895     off = get32 ();
14896   else
14897     off = get16 ();
14898
14899   if (intel_syntax)
14900     {
14901       if (!active_seg_prefix)
14902         {
14903           oappend (names_seg[ds_reg - es_reg]);
14904           oappend (":");
14905         }
14906     }
14907   print_operand_value (scratchbuf, 1, off);
14908   oappend (scratchbuf);
14909 }
14910
14911 static void
14912 OP_OFF64 (int bytemode, int sizeflag)
14913 {
14914   bfd_vma off;
14915
14916   if (address_mode != mode_64bit
14917       || (prefixes & PREFIX_ADDR))
14918     {
14919       OP_OFF (bytemode, sizeflag);
14920       return;
14921     }
14922
14923   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14924     intel_operand_size (bytemode, sizeflag);
14925   append_seg ();
14926
14927   off = get64 ();
14928
14929   if (intel_syntax)
14930     {
14931       if (!active_seg_prefix)
14932         {
14933           oappend (names_seg[ds_reg - es_reg]);
14934           oappend (":");
14935         }
14936     }
14937   print_operand_value (scratchbuf, 1, off);
14938   oappend (scratchbuf);
14939 }
14940
14941 static void
14942 ptr_reg (int code, int sizeflag)
14943 {
14944   const char *s;
14945
14946   *obufp++ = open_char;
14947   used_prefixes |= (prefixes & PREFIX_ADDR);
14948   if (address_mode == mode_64bit)
14949     {
14950       if (!(sizeflag & AFLAG))
14951         s = names32[code - eAX_reg];
14952       else
14953         s = names64[code - eAX_reg];
14954     }
14955   else if (sizeflag & AFLAG)
14956     s = names32[code - eAX_reg];
14957   else
14958     s = names16[code - eAX_reg];
14959   oappend (s);
14960   *obufp++ = close_char;
14961   *obufp = 0;
14962 }
14963
14964 static void
14965 OP_ESreg (int code, int sizeflag)
14966 {
14967   if (intel_syntax)
14968     {
14969       switch (codep[-1])
14970         {
14971         case 0x6d:      /* insw/insl */
14972           intel_operand_size (z_mode, sizeflag);
14973           break;
14974         case 0xa5:      /* movsw/movsl/movsq */
14975         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14976         case 0xab:      /* stosw/stosl */
14977         case 0xaf:      /* scasw/scasl */
14978           intel_operand_size (v_mode, sizeflag);
14979           break;
14980         default:
14981           intel_operand_size (b_mode, sizeflag);
14982         }
14983     }
14984   oappend_maybe_intel ("%es:");
14985   ptr_reg (code, sizeflag);
14986 }
14987
14988 static void
14989 OP_DSreg (int code, int sizeflag)
14990 {
14991   if (intel_syntax)
14992     {
14993       switch (codep[-1])
14994         {
14995         case 0x6f:      /* outsw/outsl */
14996           intel_operand_size (z_mode, sizeflag);
14997           break;
14998         case 0xa5:      /* movsw/movsl/movsq */
14999         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15000         case 0xad:      /* lodsw/lodsl/lodsq */
15001           intel_operand_size (v_mode, sizeflag);
15002           break;
15003         default:
15004           intel_operand_size (b_mode, sizeflag);
15005         }
15006     }
15007   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15008      default segment register DS is printed.  */
15009   if (!active_seg_prefix)
15010     active_seg_prefix = PREFIX_DS;
15011   append_seg ();
15012   ptr_reg (code, sizeflag);
15013 }
15014
15015 static void
15016 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15017 {
15018   int add;
15019   if (rex & REX_R)
15020     {
15021       USED_REX (REX_R);
15022       add = 8;
15023     }
15024   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15025     {
15026       all_prefixes[last_lock_prefix] = 0;
15027       used_prefixes |= PREFIX_LOCK;
15028       add = 8;
15029     }
15030   else
15031     add = 0;
15032   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15033   oappend_maybe_intel (scratchbuf);
15034 }
15035
15036 static void
15037 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15038 {
15039   int add;
15040   USED_REX (REX_R);
15041   if (rex & REX_R)
15042     add = 8;
15043   else
15044     add = 0;
15045   if (intel_syntax)
15046     sprintf (scratchbuf, "db%d", modrm.reg + add);
15047   else
15048     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15049   oappend (scratchbuf);
15050 }
15051
15052 static void
15053 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15054 {
15055   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15056   oappend_maybe_intel (scratchbuf);
15057 }
15058
15059 static void
15060 OP_R (int bytemode, int sizeflag)
15061 {
15062   /* Skip mod/rm byte.  */
15063   MODRM_CHECK;
15064   codep++;
15065   OP_E_register (bytemode, sizeflag);
15066 }
15067
15068 static void
15069 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15070 {
15071   int reg = modrm.reg;
15072   const char **names;
15073
15074   used_prefixes |= (prefixes & PREFIX_DATA);
15075   if (prefixes & PREFIX_DATA)
15076     {
15077       names = names_xmm;
15078       USED_REX (REX_R);
15079       if (rex & REX_R)
15080         reg += 8;
15081     }
15082   else
15083     names = names_mm;
15084   oappend (names[reg]);
15085 }
15086
15087 static void
15088 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15089 {
15090   int reg = modrm.reg;
15091   const char **names;
15092
15093   USED_REX (REX_R);
15094   if (rex & REX_R)
15095     reg += 8;
15096   if (vex.evex)
15097     {
15098       if (!vex.r)
15099         reg += 16;
15100     }
15101
15102   if (need_vex
15103       && bytemode != xmm_mode
15104       && bytemode != xmmq_mode
15105       && bytemode != evex_half_bcst_xmmq_mode
15106       && bytemode != ymm_mode
15107       && bytemode != scalar_mode)
15108     {
15109       switch (vex.length)
15110         {
15111         case 128:
15112           names = names_xmm;
15113           break;
15114         case 256:
15115           if (vex.w
15116               || (bytemode != vex_vsib_q_w_dq_mode
15117                   && bytemode != vex_vsib_q_w_d_mode))
15118             names = names_ymm;
15119           else
15120             names = names_xmm;
15121           break;
15122         case 512:
15123           names = names_zmm;
15124           break;
15125         default:
15126           abort ();
15127         }
15128     }
15129   else if (bytemode == xmmq_mode
15130            || bytemode == evex_half_bcst_xmmq_mode)
15131     {
15132       switch (vex.length)
15133         {
15134         case 128:
15135         case 256:
15136           names = names_xmm;
15137           break;
15138         case 512:
15139           names = names_ymm;
15140           break;
15141         default:
15142           abort ();
15143         }
15144     }
15145   else if (bytemode == ymm_mode)
15146     names = names_ymm;
15147   else
15148     names = names_xmm;
15149   oappend (names[reg]);
15150 }
15151
15152 static void
15153 OP_EM (int bytemode, int sizeflag)
15154 {
15155   int reg;
15156   const char **names;
15157
15158   if (modrm.mod != 3)
15159     {
15160       if (intel_syntax
15161           && (bytemode == v_mode || bytemode == v_swap_mode))
15162         {
15163           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15164           used_prefixes |= (prefixes & PREFIX_DATA);
15165         }
15166       OP_E (bytemode, sizeflag);
15167       return;
15168     }
15169
15170   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15171     swap_operand ();
15172
15173   /* Skip mod/rm byte.  */
15174   MODRM_CHECK;
15175   codep++;
15176   used_prefixes |= (prefixes & PREFIX_DATA);
15177   reg = modrm.rm;
15178   if (prefixes & PREFIX_DATA)
15179     {
15180       names = names_xmm;
15181       USED_REX (REX_B);
15182       if (rex & REX_B)
15183         reg += 8;
15184     }
15185   else
15186     names = names_mm;
15187   oappend (names[reg]);
15188 }
15189
15190 /* cvt* are the only instructions in sse2 which have
15191    both SSE and MMX operands and also have 0x66 prefix
15192    in their opcode. 0x66 was originally used to differentiate
15193    between SSE and MMX instruction(operands). So we have to handle the
15194    cvt* separately using OP_EMC and OP_MXC */
15195 static void
15196 OP_EMC (int bytemode, int sizeflag)
15197 {
15198   if (modrm.mod != 3)
15199     {
15200       if (intel_syntax && bytemode == v_mode)
15201         {
15202           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15203           used_prefixes |= (prefixes & PREFIX_DATA);
15204         }
15205       OP_E (bytemode, sizeflag);
15206       return;
15207     }
15208
15209   /* Skip mod/rm byte.  */
15210   MODRM_CHECK;
15211   codep++;
15212   used_prefixes |= (prefixes & PREFIX_DATA);
15213   oappend (names_mm[modrm.rm]);
15214 }
15215
15216 static void
15217 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15218 {
15219   used_prefixes |= (prefixes & PREFIX_DATA);
15220   oappend (names_mm[modrm.reg]);
15221 }
15222
15223 static void
15224 OP_EX (int bytemode, int sizeflag)
15225 {
15226   int reg;
15227   const char **names;
15228
15229   /* Skip mod/rm byte.  */
15230   MODRM_CHECK;
15231   codep++;
15232
15233   if (modrm.mod != 3)
15234     {
15235       OP_E_memory (bytemode, sizeflag);
15236       return;
15237     }
15238
15239   reg = modrm.rm;
15240   USED_REX (REX_B);
15241   if (rex & REX_B)
15242     reg += 8;
15243   if (vex.evex)
15244     {
15245       USED_REX (REX_X);
15246       if ((rex & REX_X))
15247         reg += 16;
15248     }
15249
15250   if ((sizeflag & SUFFIX_ALWAYS)
15251       && (bytemode == x_swap_mode
15252           || bytemode == d_swap_mode
15253           || bytemode == d_scalar_swap_mode
15254           || bytemode == q_swap_mode
15255           || bytemode == q_scalar_swap_mode))
15256     swap_operand ();
15257
15258   if (need_vex
15259       && bytemode != xmm_mode
15260       && bytemode != xmmdw_mode
15261       && bytemode != xmmqd_mode
15262       && bytemode != xmm_mb_mode
15263       && bytemode != xmm_mw_mode
15264       && bytemode != xmm_md_mode
15265       && bytemode != xmm_mq_mode
15266       && bytemode != xmm_mdq_mode
15267       && bytemode != xmmq_mode
15268       && bytemode != evex_half_bcst_xmmq_mode
15269       && bytemode != ymm_mode
15270       && bytemode != d_scalar_mode
15271       && bytemode != d_scalar_swap_mode
15272       && bytemode != q_scalar_mode
15273       && bytemode != q_scalar_swap_mode
15274       && bytemode != vex_scalar_w_dq_mode)
15275     {
15276       switch (vex.length)
15277         {
15278         case 128:
15279           names = names_xmm;
15280           break;
15281         case 256:
15282           names = names_ymm;
15283           break;
15284         case 512:
15285           names = names_zmm;
15286           break;
15287         default:
15288           abort ();
15289         }
15290     }
15291   else if (bytemode == xmmq_mode
15292            || bytemode == evex_half_bcst_xmmq_mode)
15293     {
15294       switch (vex.length)
15295         {
15296         case 128:
15297         case 256:
15298           names = names_xmm;
15299           break;
15300         case 512:
15301           names = names_ymm;
15302           break;
15303         default:
15304           abort ();
15305         }
15306     }
15307   else if (bytemode == ymm_mode)
15308     names = names_ymm;
15309   else
15310     names = names_xmm;
15311   oappend (names[reg]);
15312 }
15313
15314 static void
15315 OP_MS (int bytemode, int sizeflag)
15316 {
15317   if (modrm.mod == 3)
15318     OP_EM (bytemode, sizeflag);
15319   else
15320     BadOp ();
15321 }
15322
15323 static void
15324 OP_XS (int bytemode, int sizeflag)
15325 {
15326   if (modrm.mod == 3)
15327     OP_EX (bytemode, sizeflag);
15328   else
15329     BadOp ();
15330 }
15331
15332 static void
15333 OP_M (int bytemode, int sizeflag)
15334 {
15335   if (modrm.mod == 3)
15336     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15337     BadOp ();
15338   else
15339     OP_E (bytemode, sizeflag);
15340 }
15341
15342 static void
15343 OP_0f07 (int bytemode, int sizeflag)
15344 {
15345   if (modrm.mod != 3 || modrm.rm != 0)
15346     BadOp ();
15347   else
15348     OP_E (bytemode, sizeflag);
15349 }
15350
15351 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15352    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15353
15354 static void
15355 NOP_Fixup1 (int bytemode, int sizeflag)
15356 {
15357   if ((prefixes & PREFIX_DATA) != 0
15358       || (rex != 0
15359           && rex != 0x48
15360           && address_mode == mode_64bit))
15361     OP_REG (bytemode, sizeflag);
15362   else
15363     strcpy (obuf, "nop");
15364 }
15365
15366 static void
15367 NOP_Fixup2 (int bytemode, int sizeflag)
15368 {
15369   if ((prefixes & PREFIX_DATA) != 0
15370       || (rex != 0
15371           && rex != 0x48
15372           && address_mode == mode_64bit))
15373     OP_IMREG (bytemode, sizeflag);
15374 }
15375
15376 static const char *const Suffix3DNow[] = {
15377 /* 00 */        NULL,           NULL,           NULL,           NULL,
15378 /* 04 */        NULL,           NULL,           NULL,           NULL,
15379 /* 08 */        NULL,           NULL,           NULL,           NULL,
15380 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15381 /* 10 */        NULL,           NULL,           NULL,           NULL,
15382 /* 14 */        NULL,           NULL,           NULL,           NULL,
15383 /* 18 */        NULL,           NULL,           NULL,           NULL,
15384 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15385 /* 20 */        NULL,           NULL,           NULL,           NULL,
15386 /* 24 */        NULL,           NULL,           NULL,           NULL,
15387 /* 28 */        NULL,           NULL,           NULL,           NULL,
15388 /* 2C */        NULL,           NULL,           NULL,           NULL,
15389 /* 30 */        NULL,           NULL,           NULL,           NULL,
15390 /* 34 */        NULL,           NULL,           NULL,           NULL,
15391 /* 38 */        NULL,           NULL,           NULL,           NULL,
15392 /* 3C */        NULL,           NULL,           NULL,           NULL,
15393 /* 40 */        NULL,           NULL,           NULL,           NULL,
15394 /* 44 */        NULL,           NULL,           NULL,           NULL,
15395 /* 48 */        NULL,           NULL,           NULL,           NULL,
15396 /* 4C */        NULL,           NULL,           NULL,           NULL,
15397 /* 50 */        NULL,           NULL,           NULL,           NULL,
15398 /* 54 */        NULL,           NULL,           NULL,           NULL,
15399 /* 58 */        NULL,           NULL,           NULL,           NULL,
15400 /* 5C */        NULL,           NULL,           NULL,           NULL,
15401 /* 60 */        NULL,           NULL,           NULL,           NULL,
15402 /* 64 */        NULL,           NULL,           NULL,           NULL,
15403 /* 68 */        NULL,           NULL,           NULL,           NULL,
15404 /* 6C */        NULL,           NULL,           NULL,           NULL,
15405 /* 70 */        NULL,           NULL,           NULL,           NULL,
15406 /* 74 */        NULL,           NULL,           NULL,           NULL,
15407 /* 78 */        NULL,           NULL,           NULL,           NULL,
15408 /* 7C */        NULL,           NULL,           NULL,           NULL,
15409 /* 80 */        NULL,           NULL,           NULL,           NULL,
15410 /* 84 */        NULL,           NULL,           NULL,           NULL,
15411 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15412 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15413 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15414 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15415 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15416 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15417 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15418 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15419 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15420 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15421 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15422 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15423 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15424 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15425 /* C0 */        NULL,           NULL,           NULL,           NULL,
15426 /* C4 */        NULL,           NULL,           NULL,           NULL,
15427 /* C8 */        NULL,           NULL,           NULL,           NULL,
15428 /* CC */        NULL,           NULL,           NULL,           NULL,
15429 /* D0 */        NULL,           NULL,           NULL,           NULL,
15430 /* D4 */        NULL,           NULL,           NULL,           NULL,
15431 /* D8 */        NULL,           NULL,           NULL,           NULL,
15432 /* DC */        NULL,           NULL,           NULL,           NULL,
15433 /* E0 */        NULL,           NULL,           NULL,           NULL,
15434 /* E4 */        NULL,           NULL,           NULL,           NULL,
15435 /* E8 */        NULL,           NULL,           NULL,           NULL,
15436 /* EC */        NULL,           NULL,           NULL,           NULL,
15437 /* F0 */        NULL,           NULL,           NULL,           NULL,
15438 /* F4 */        NULL,           NULL,           NULL,           NULL,
15439 /* F8 */        NULL,           NULL,           NULL,           NULL,
15440 /* FC */        NULL,           NULL,           NULL,           NULL,
15441 };
15442
15443 static void
15444 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15445 {
15446   const char *mnemonic;
15447
15448   FETCH_DATA (the_info, codep + 1);
15449   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15450      place where an 8-bit immediate would normally go.  ie. the last
15451      byte of the instruction.  */
15452   obufp = mnemonicendp;
15453   mnemonic = Suffix3DNow[*codep++ & 0xff];
15454   if (mnemonic)
15455     oappend (mnemonic);
15456   else
15457     {
15458       /* Since a variable sized modrm/sib chunk is between the start
15459          of the opcode (0x0f0f) and the opcode suffix, we need to do
15460          all the modrm processing first, and don't know until now that
15461          we have a bad opcode.  This necessitates some cleaning up.  */
15462       op_out[0][0] = '\0';
15463       op_out[1][0] = '\0';
15464       BadOp ();
15465     }
15466   mnemonicendp = obufp;
15467 }
15468
15469 static struct op simd_cmp_op[] =
15470 {
15471   { STRING_COMMA_LEN ("eq") },
15472   { STRING_COMMA_LEN ("lt") },
15473   { STRING_COMMA_LEN ("le") },
15474   { STRING_COMMA_LEN ("unord") },
15475   { STRING_COMMA_LEN ("neq") },
15476   { STRING_COMMA_LEN ("nlt") },
15477   { STRING_COMMA_LEN ("nle") },
15478   { STRING_COMMA_LEN ("ord") }
15479 };
15480
15481 static void
15482 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15483 {
15484   unsigned int cmp_type;
15485
15486   FETCH_DATA (the_info, codep + 1);
15487   cmp_type = *codep++ & 0xff;
15488   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15489     {
15490       char suffix [3];
15491       char *p = mnemonicendp - 2;
15492       suffix[0] = p[0];
15493       suffix[1] = p[1];
15494       suffix[2] = '\0';
15495       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15496       mnemonicendp += simd_cmp_op[cmp_type].len;
15497     }
15498   else
15499     {
15500       /* We have a reserved extension byte.  Output it directly.  */
15501       scratchbuf[0] = '$';
15502       print_operand_value (scratchbuf + 1, 1, cmp_type);
15503       oappend_maybe_intel (scratchbuf);
15504       scratchbuf[0] = '\0';
15505     }
15506 }
15507
15508 static void
15509 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15510           int sizeflag ATTRIBUTE_UNUSED)
15511 {
15512   /* mwaitx %eax,%ecx,%ebx */
15513   if (!intel_syntax)
15514     {
15515       const char **names = (address_mode == mode_64bit
15516                             ? names64 : names32);
15517       strcpy (op_out[0], names[0]);
15518       strcpy (op_out[1], names[1]);
15519       strcpy (op_out[2], names[3]);
15520       two_source_ops = 1;
15521     }
15522   /* Skip mod/rm byte.  */
15523   MODRM_CHECK;
15524   codep++;
15525 }
15526
15527 static void
15528 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15529           int sizeflag ATTRIBUTE_UNUSED)
15530 {
15531   /* mwait %eax,%ecx  */
15532   if (!intel_syntax)
15533     {
15534       const char **names = (address_mode == mode_64bit
15535                             ? names64 : names32);
15536       strcpy (op_out[0], names[0]);
15537       strcpy (op_out[1], names[1]);
15538       two_source_ops = 1;
15539     }
15540   /* Skip mod/rm byte.  */
15541   MODRM_CHECK;
15542   codep++;
15543 }
15544
15545 static void
15546 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15547             int sizeflag ATTRIBUTE_UNUSED)
15548 {
15549   /* monitor %eax,%ecx,%edx"  */
15550   if (!intel_syntax)
15551     {
15552       const char **op1_names;
15553       const char **names = (address_mode == mode_64bit
15554                             ? names64 : names32);
15555
15556       if (!(prefixes & PREFIX_ADDR))
15557         op1_names = (address_mode == mode_16bit
15558                      ? names16 : names);
15559       else
15560         {
15561           /* Remove "addr16/addr32".  */
15562           all_prefixes[last_addr_prefix] = 0;
15563           op1_names = (address_mode != mode_32bit
15564                        ? names32 : names16);
15565           used_prefixes |= PREFIX_ADDR;
15566         }
15567       strcpy (op_out[0], op1_names[0]);
15568       strcpy (op_out[1], names[1]);
15569       strcpy (op_out[2], names[2]);
15570       two_source_ops = 1;
15571     }
15572   /* Skip mod/rm byte.  */
15573   MODRM_CHECK;
15574   codep++;
15575 }
15576
15577 static void
15578 BadOp (void)
15579 {
15580   /* Throw away prefixes and 1st. opcode byte.  */
15581   codep = insn_codep + 1;
15582   oappend ("(bad)");
15583 }
15584
15585 static void
15586 REP_Fixup (int bytemode, int sizeflag)
15587 {
15588   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15589      lods and stos.  */
15590   if (prefixes & PREFIX_REPZ)
15591     all_prefixes[last_repz_prefix] = REP_PREFIX;
15592
15593   switch (bytemode)
15594     {
15595     case al_reg:
15596     case eAX_reg:
15597     case indir_dx_reg:
15598       OP_IMREG (bytemode, sizeflag);
15599       break;
15600     case eDI_reg:
15601       OP_ESreg (bytemode, sizeflag);
15602       break;
15603     case eSI_reg:
15604       OP_DSreg (bytemode, sizeflag);
15605       break;
15606     default:
15607       abort ();
15608       break;
15609     }
15610 }
15611
15612 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15613    "bnd".  */
15614
15615 static void
15616 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15617 {
15618   if (prefixes & PREFIX_REPNZ)
15619     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15620 }
15621
15622 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15623    "notrack".  */
15624
15625 static void
15626 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15627                int sizeflag ATTRIBUTE_UNUSED)
15628 {
15629   if (active_seg_prefix == PREFIX_DS
15630       && (address_mode != mode_64bit || last_data_prefix < 0))
15631     {
15632       /* NOTRACK prefix is only valid on indirect branch instructions.
15633          NB: DATA prefix is unsupported for Intel64.  */
15634       active_seg_prefix = 0;
15635       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15636     }
15637 }
15638
15639 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15640    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15641  */
15642
15643 static void
15644 HLE_Fixup1 (int bytemode, int sizeflag)
15645 {
15646   if (modrm.mod != 3
15647       && (prefixes & PREFIX_LOCK) != 0)
15648     {
15649       if (prefixes & PREFIX_REPZ)
15650         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15651       if (prefixes & PREFIX_REPNZ)
15652         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15653     }
15654
15655   OP_E (bytemode, sizeflag);
15656 }
15657
15658 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15659    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15660  */
15661
15662 static void
15663 HLE_Fixup2 (int bytemode, int sizeflag)
15664 {
15665   if (modrm.mod != 3)
15666     {
15667       if (prefixes & PREFIX_REPZ)
15668         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15669       if (prefixes & PREFIX_REPNZ)
15670         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15671     }
15672
15673   OP_E (bytemode, sizeflag);
15674 }
15675
15676 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15677    "xrelease" for memory operand.  No check for LOCK prefix.   */
15678
15679 static void
15680 HLE_Fixup3 (int bytemode, int sizeflag)
15681 {
15682   if (modrm.mod != 3
15683       && last_repz_prefix > last_repnz_prefix
15684       && (prefixes & PREFIX_REPZ) != 0)
15685     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15686
15687   OP_E (bytemode, sizeflag);
15688 }
15689
15690 static void
15691 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15692 {
15693   USED_REX (REX_W);
15694   if (rex & REX_W)
15695     {
15696       /* Change cmpxchg8b to cmpxchg16b.  */
15697       char *p = mnemonicendp - 2;
15698       mnemonicendp = stpcpy (p, "16b");
15699       bytemode = o_mode;
15700     }
15701   else if ((prefixes & PREFIX_LOCK) != 0)
15702     {
15703       if (prefixes & PREFIX_REPZ)
15704         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15705       if (prefixes & PREFIX_REPNZ)
15706         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15707     }
15708
15709   OP_M (bytemode, sizeflag);
15710 }
15711
15712 static void
15713 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15714 {
15715   const char **names;
15716
15717   if (need_vex)
15718     {
15719       switch (vex.length)
15720         {
15721         case 128:
15722           names = names_xmm;
15723           break;
15724         case 256:
15725           names = names_ymm;
15726           break;
15727         default:
15728           abort ();
15729         }
15730     }
15731   else
15732     names = names_xmm;
15733   oappend (names[reg]);
15734 }
15735
15736 static void
15737 CRC32_Fixup (int bytemode, int sizeflag)
15738 {
15739   /* Add proper suffix to "crc32".  */
15740   char *p = mnemonicendp;
15741
15742   switch (bytemode)
15743     {
15744     case b_mode:
15745       if (intel_syntax)
15746         goto skip;
15747
15748       *p++ = 'b';
15749       break;
15750     case v_mode:
15751       if (intel_syntax)
15752         goto skip;
15753
15754       USED_REX (REX_W);
15755       if (rex & REX_W)
15756         *p++ = 'q';
15757       else
15758         {
15759           if (sizeflag & DFLAG)
15760             *p++ = 'l';
15761           else
15762             *p++ = 'w';
15763           used_prefixes |= (prefixes & PREFIX_DATA);
15764         }
15765       break;
15766     default:
15767       oappend (INTERNAL_DISASSEMBLER_ERROR);
15768       break;
15769     }
15770   mnemonicendp = p;
15771   *p = '\0';
15772
15773 skip:
15774   if (modrm.mod == 3)
15775     {
15776       int add;
15777
15778       /* Skip mod/rm byte.  */
15779       MODRM_CHECK;
15780       codep++;
15781
15782       USED_REX (REX_B);
15783       add = (rex & REX_B) ? 8 : 0;
15784       if (bytemode == b_mode)
15785         {
15786           USED_REX (0);
15787           if (rex)
15788             oappend (names8rex[modrm.rm + add]);
15789           else
15790             oappend (names8[modrm.rm + add]);
15791         }
15792       else
15793         {
15794           USED_REX (REX_W);
15795           if (rex & REX_W)
15796             oappend (names64[modrm.rm + add]);
15797           else if ((prefixes & PREFIX_DATA))
15798             oappend (names16[modrm.rm + add]);
15799           else
15800             oappend (names32[modrm.rm + add]);
15801         }
15802     }
15803   else
15804     OP_E (bytemode, sizeflag);
15805 }
15806
15807 static void
15808 FXSAVE_Fixup (int bytemode, int sizeflag)
15809 {
15810   /* Add proper suffix to "fxsave" and "fxrstor".  */
15811   USED_REX (REX_W);
15812   if (rex & REX_W)
15813     {
15814       char *p = mnemonicendp;
15815       *p++ = '6';
15816       *p++ = '4';
15817       *p = '\0';
15818       mnemonicendp = p;
15819     }
15820   OP_M (bytemode, sizeflag);
15821 }
15822
15823 static void
15824 PCMPESTR_Fixup (int bytemode, int sizeflag)
15825 {
15826   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15827   if (!intel_syntax)
15828     {
15829       char *p = mnemonicendp;
15830
15831       USED_REX (REX_W);
15832       if (rex & REX_W)
15833         *p++ = 'q';
15834       else if (sizeflag & SUFFIX_ALWAYS)
15835         *p++ = 'l';
15836
15837       *p = '\0';
15838       mnemonicendp = p;
15839     }
15840
15841   OP_EX (bytemode, sizeflag);
15842 }
15843
15844 /* Display the destination register operand for instructions with
15845    VEX. */
15846
15847 static void
15848 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15849 {
15850   int reg;
15851   const char **names;
15852
15853   if (!need_vex)
15854     abort ();
15855
15856   if (!need_vex_reg)
15857     return;
15858
15859   reg = vex.register_specifier;
15860   vex.register_specifier = 0;
15861   if (address_mode != mode_64bit)
15862     reg &= 7;
15863   else if (vex.evex && !vex.v)
15864     reg += 16;
15865
15866   if (bytemode == vex_scalar_mode)
15867     {
15868       oappend (names_xmm[reg]);
15869       return;
15870     }
15871
15872   switch (vex.length)
15873     {
15874     case 128:
15875       switch (bytemode)
15876         {
15877         case vex_mode:
15878         case vex128_mode:
15879         case vex_vsib_q_w_dq_mode:
15880         case vex_vsib_q_w_d_mode:
15881           names = names_xmm;
15882           break;
15883         case dq_mode:
15884           if (rex & REX_W)
15885             names = names64;
15886           else
15887             names = names32;
15888           break;
15889         case mask_bd_mode:
15890         case mask_mode:
15891           if (reg > 0x7)
15892             {
15893               oappend ("(bad)");
15894               return;
15895             }
15896           names = names_mask;
15897           break;
15898         default:
15899           abort ();
15900           return;
15901         }
15902       break;
15903     case 256:
15904       switch (bytemode)
15905         {
15906         case vex_mode:
15907         case vex256_mode:
15908           names = names_ymm;
15909           break;
15910         case vex_vsib_q_w_dq_mode:
15911         case vex_vsib_q_w_d_mode:
15912           names = vex.w ? names_ymm : names_xmm;
15913           break;
15914         case mask_bd_mode:
15915         case mask_mode:
15916           if (reg > 0x7)
15917             {
15918               oappend ("(bad)");
15919               return;
15920             }
15921           names = names_mask;
15922           break;
15923         default:
15924           /* See PR binutils/20893 for a reproducer.  */
15925           oappend ("(bad)");
15926           return;
15927         }
15928       break;
15929     case 512:
15930       names = names_zmm;
15931       break;
15932     default:
15933       abort ();
15934       break;
15935     }
15936   oappend (names[reg]);
15937 }
15938
15939 /* Get the VEX immediate byte without moving codep.  */
15940
15941 static unsigned char
15942 get_vex_imm8 (int sizeflag, int opnum)
15943 {
15944   int bytes_before_imm = 0;
15945
15946   if (modrm.mod != 3)
15947     {
15948       /* There are SIB/displacement bytes.  */
15949       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15950         {
15951           /* 32/64 bit address mode */
15952           int base = modrm.rm;
15953
15954           /* Check SIB byte.  */
15955           if (base == 4)
15956             {
15957               FETCH_DATA (the_info, codep + 1);
15958               base = *codep & 7;
15959               /* When decoding the third source, don't increase
15960                  bytes_before_imm as this has already been incremented
15961                  by one in OP_E_memory while decoding the second
15962                  source operand.  */
15963               if (opnum == 0)
15964                 bytes_before_imm++;
15965             }
15966
15967           /* Don't increase bytes_before_imm when decoding the third source,
15968              it has already been incremented by OP_E_memory while decoding
15969              the second source operand.  */
15970           if (opnum == 0)
15971             {
15972               switch (modrm.mod)
15973                 {
15974                   case 0:
15975                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15976                        SIB == 5, there is a 4 byte displacement.  */
15977                     if (base != 5)
15978                       /* No displacement. */
15979                       break;
15980                     /* Fall through.  */
15981                   case 2:
15982                     /* 4 byte displacement.  */
15983                     bytes_before_imm += 4;
15984                     break;
15985                   case 1:
15986                     /* 1 byte displacement.  */
15987                     bytes_before_imm++;
15988                     break;
15989                 }
15990             }
15991         }
15992       else
15993         {
15994           /* 16 bit address mode */
15995           /* Don't increase bytes_before_imm when decoding the third source,
15996              it has already been incremented by OP_E_memory while decoding
15997              the second source operand.  */
15998           if (opnum == 0)
15999             {
16000               switch (modrm.mod)
16001                 {
16002                 case 0:
16003                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16004                   if (modrm.rm != 6)
16005                     /* No displacement. */
16006                     break;
16007                   /* Fall through.  */
16008                 case 2:
16009                   /* 2 byte displacement.  */
16010                   bytes_before_imm += 2;
16011                   break;
16012                 case 1:
16013                   /* 1 byte displacement: when decoding the third source,
16014                      don't increase bytes_before_imm as this has already
16015                      been incremented by one in OP_E_memory while decoding
16016                      the second source operand.  */
16017                   if (opnum == 0)
16018                     bytes_before_imm++;
16019
16020                   break;
16021                 }
16022             }
16023         }
16024     }
16025
16026   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16027   return codep [bytes_before_imm];
16028 }
16029
16030 static void
16031 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16032 {
16033   const char **names;
16034
16035   if (reg == -1 && modrm.mod != 3)
16036     {
16037       OP_E_memory (bytemode, sizeflag);
16038       return;
16039     }
16040   else
16041     {
16042       if (reg == -1)
16043         {
16044           reg = modrm.rm;
16045           USED_REX (REX_B);
16046           if (rex & REX_B)
16047             reg += 8;
16048         }
16049       if (address_mode != mode_64bit)
16050         reg &= 7;
16051     }
16052
16053   switch (vex.length)
16054     {
16055     case 128:
16056       names = names_xmm;
16057       break;
16058     case 256:
16059       names = names_ymm;
16060       break;
16061     default:
16062       abort ();
16063     }
16064   oappend (names[reg]);
16065 }
16066
16067 static void
16068 OP_EX_VexImmW (int bytemode, int sizeflag)
16069 {
16070   int reg = -1;
16071   static unsigned char vex_imm8;
16072
16073   if (vex_w_done == 0)
16074     {
16075       vex_w_done = 1;
16076
16077       /* Skip mod/rm byte.  */
16078       MODRM_CHECK;
16079       codep++;
16080
16081       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16082
16083       if (vex.w)
16084           reg = vex_imm8 >> 4;
16085
16086       OP_EX_VexReg (bytemode, sizeflag, reg);
16087     }
16088   else if (vex_w_done == 1)
16089     {
16090       vex_w_done = 2;
16091
16092       if (!vex.w)
16093           reg = vex_imm8 >> 4;
16094
16095       OP_EX_VexReg (bytemode, sizeflag, reg);
16096     }
16097   else
16098     {
16099       /* Output the imm8 directly.  */
16100       scratchbuf[0] = '$';
16101       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16102       oappend_maybe_intel (scratchbuf);
16103       scratchbuf[0] = '\0';
16104       codep++;
16105     }
16106 }
16107
16108 static void
16109 OP_Vex_2src (int bytemode, int sizeflag)
16110 {
16111   if (modrm.mod == 3)
16112     {
16113       int reg = modrm.rm;
16114       USED_REX (REX_B);
16115       if (rex & REX_B)
16116         reg += 8;
16117       oappend (names_xmm[reg]);
16118     }
16119   else
16120     {
16121       if (intel_syntax
16122           && (bytemode == v_mode || bytemode == v_swap_mode))
16123         {
16124           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16125           used_prefixes |= (prefixes & PREFIX_DATA);
16126         }
16127       OP_E (bytemode, sizeflag);
16128     }
16129 }
16130
16131 static void
16132 OP_Vex_2src_1 (int bytemode, int sizeflag)
16133 {
16134   if (modrm.mod == 3)
16135     {
16136       /* Skip mod/rm byte.   */
16137       MODRM_CHECK;
16138       codep++;
16139     }
16140
16141   if (vex.w)
16142     {
16143       unsigned int reg = vex.register_specifier;
16144       vex.register_specifier = 0;
16145
16146       if (address_mode != mode_64bit)
16147         reg &= 7;
16148       oappend (names_xmm[reg]);
16149     }
16150   else
16151     OP_Vex_2src (bytemode, sizeflag);
16152 }
16153
16154 static void
16155 OP_Vex_2src_2 (int bytemode, int sizeflag)
16156 {
16157   if (vex.w)
16158     OP_Vex_2src (bytemode, sizeflag);
16159   else
16160     {
16161       unsigned int reg = vex.register_specifier;
16162       vex.register_specifier = 0;
16163
16164       if (address_mode != mode_64bit)
16165         reg &= 7;
16166       oappend (names_xmm[reg]);
16167     }
16168 }
16169
16170 static void
16171 OP_EX_VexW (int bytemode, int sizeflag)
16172 {
16173   int reg = -1;
16174
16175   if (!vex_w_done)
16176     {
16177       /* Skip mod/rm byte.  */
16178       MODRM_CHECK;
16179       codep++;
16180
16181       if (vex.w)
16182         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16183     }
16184   else
16185     {
16186       if (!vex.w)
16187         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16188     }
16189
16190   OP_EX_VexReg (bytemode, sizeflag, reg);
16191
16192   if (vex_w_done)
16193     codep++;
16194   vex_w_done = 1;
16195 }
16196
16197 static void
16198 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16199 {
16200   int reg;
16201   const char **names;
16202
16203   FETCH_DATA (the_info, codep + 1);
16204   reg = *codep++;
16205
16206   if (bytemode != x_mode)
16207     abort ();
16208
16209   reg >>= 4;
16210   if (address_mode != mode_64bit)
16211     reg &= 7;
16212
16213   switch (vex.length)
16214     {
16215     case 128:
16216       names = names_xmm;
16217       break;
16218     case 256:
16219       names = names_ymm;
16220       break;
16221     default:
16222       abort ();
16223     }
16224   oappend (names[reg]);
16225 }
16226
16227 static void
16228 OP_XMM_VexW (int bytemode, int sizeflag)
16229 {
16230   /* Turn off the REX.W bit since it is used for swapping operands
16231      now.  */
16232   rex &= ~REX_W;
16233   OP_XMM (bytemode, sizeflag);
16234 }
16235
16236 static void
16237 OP_EX_Vex (int bytemode, int sizeflag)
16238 {
16239   if (modrm.mod != 3)
16240     need_vex_reg = 0;
16241   OP_EX (bytemode, sizeflag);
16242 }
16243
16244 static void
16245 OP_XMM_Vex (int bytemode, int sizeflag)
16246 {
16247   if (modrm.mod != 3)
16248     need_vex_reg = 0;
16249   OP_XMM (bytemode, sizeflag);
16250 }
16251
16252 static struct op vex_cmp_op[] =
16253 {
16254   { STRING_COMMA_LEN ("eq") },
16255   { STRING_COMMA_LEN ("lt") },
16256   { STRING_COMMA_LEN ("le") },
16257   { STRING_COMMA_LEN ("unord") },
16258   { STRING_COMMA_LEN ("neq") },
16259   { STRING_COMMA_LEN ("nlt") },
16260   { STRING_COMMA_LEN ("nle") },
16261   { STRING_COMMA_LEN ("ord") },
16262   { STRING_COMMA_LEN ("eq_uq") },
16263   { STRING_COMMA_LEN ("nge") },
16264   { STRING_COMMA_LEN ("ngt") },
16265   { STRING_COMMA_LEN ("false") },
16266   { STRING_COMMA_LEN ("neq_oq") },
16267   { STRING_COMMA_LEN ("ge") },
16268   { STRING_COMMA_LEN ("gt") },
16269   { STRING_COMMA_LEN ("true") },
16270   { STRING_COMMA_LEN ("eq_os") },
16271   { STRING_COMMA_LEN ("lt_oq") },
16272   { STRING_COMMA_LEN ("le_oq") },
16273   { STRING_COMMA_LEN ("unord_s") },
16274   { STRING_COMMA_LEN ("neq_us") },
16275   { STRING_COMMA_LEN ("nlt_uq") },
16276   { STRING_COMMA_LEN ("nle_uq") },
16277   { STRING_COMMA_LEN ("ord_s") },
16278   { STRING_COMMA_LEN ("eq_us") },
16279   { STRING_COMMA_LEN ("nge_uq") },
16280   { STRING_COMMA_LEN ("ngt_uq") },
16281   { STRING_COMMA_LEN ("false_os") },
16282   { STRING_COMMA_LEN ("neq_os") },
16283   { STRING_COMMA_LEN ("ge_oq") },
16284   { STRING_COMMA_LEN ("gt_oq") },
16285   { STRING_COMMA_LEN ("true_us") },
16286 };
16287
16288 static void
16289 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16290 {
16291   unsigned int cmp_type;
16292
16293   FETCH_DATA (the_info, codep + 1);
16294   cmp_type = *codep++ & 0xff;
16295   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16296     {
16297       char suffix [3];
16298       char *p = mnemonicendp - 2;
16299       suffix[0] = p[0];
16300       suffix[1] = p[1];
16301       suffix[2] = '\0';
16302       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16303       mnemonicendp += vex_cmp_op[cmp_type].len;
16304     }
16305   else
16306     {
16307       /* We have a reserved extension byte.  Output it directly.  */
16308       scratchbuf[0] = '$';
16309       print_operand_value (scratchbuf + 1, 1, cmp_type);
16310       oappend_maybe_intel (scratchbuf);
16311       scratchbuf[0] = '\0';
16312     }
16313 }
16314
16315 static void
16316 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16317              int sizeflag ATTRIBUTE_UNUSED)
16318 {
16319   unsigned int cmp_type;
16320
16321   if (!vex.evex)
16322     abort ();
16323
16324   FETCH_DATA (the_info, codep + 1);
16325   cmp_type = *codep++ & 0xff;
16326   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16327      If it's the case, print suffix, otherwise - print the immediate.  */
16328   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16329       && cmp_type != 3
16330       && cmp_type != 7)
16331     {
16332       char suffix [3];
16333       char *p = mnemonicendp - 2;
16334
16335       /* vpcmp* can have both one- and two-lettered suffix.  */
16336       if (p[0] == 'p')
16337         {
16338           p++;
16339           suffix[0] = p[0];
16340           suffix[1] = '\0';
16341         }
16342       else
16343         {
16344           suffix[0] = p[0];
16345           suffix[1] = p[1];
16346           suffix[2] = '\0';
16347         }
16348
16349       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16350       mnemonicendp += simd_cmp_op[cmp_type].len;
16351     }
16352   else
16353     {
16354       /* We have a reserved extension byte.  Output it directly.  */
16355       scratchbuf[0] = '$';
16356       print_operand_value (scratchbuf + 1, 1, cmp_type);
16357       oappend_maybe_intel (scratchbuf);
16358       scratchbuf[0] = '\0';
16359     }
16360 }
16361
16362 static const struct op xop_cmp_op[] =
16363 {
16364   { STRING_COMMA_LEN ("lt") },
16365   { STRING_COMMA_LEN ("le") },
16366   { STRING_COMMA_LEN ("gt") },
16367   { STRING_COMMA_LEN ("ge") },
16368   { STRING_COMMA_LEN ("eq") },
16369   { STRING_COMMA_LEN ("neq") },
16370   { STRING_COMMA_LEN ("false") },
16371   { STRING_COMMA_LEN ("true") }
16372 };
16373
16374 static void
16375 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16376              int sizeflag ATTRIBUTE_UNUSED)
16377 {
16378   unsigned int cmp_type;
16379
16380   FETCH_DATA (the_info, codep + 1);
16381   cmp_type = *codep++ & 0xff;
16382   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16383     {
16384       char suffix[3];
16385       char *p = mnemonicendp - 2;
16386
16387       /* vpcom* can have both one- and two-lettered suffix.  */
16388       if (p[0] == 'm')
16389         {
16390           p++;
16391           suffix[0] = p[0];
16392           suffix[1] = '\0';
16393         }
16394       else
16395         {
16396           suffix[0] = p[0];
16397           suffix[1] = p[1];
16398           suffix[2] = '\0';
16399         }
16400
16401       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16402       mnemonicendp += xop_cmp_op[cmp_type].len;
16403     }
16404   else
16405     {
16406       /* We have a reserved extension byte.  Output it directly.  */
16407       scratchbuf[0] = '$';
16408       print_operand_value (scratchbuf + 1, 1, cmp_type);
16409       oappend_maybe_intel (scratchbuf);
16410       scratchbuf[0] = '\0';
16411     }
16412 }
16413
16414 static const struct op pclmul_op[] =
16415 {
16416   { STRING_COMMA_LEN ("lql") },
16417   { STRING_COMMA_LEN ("hql") },
16418   { STRING_COMMA_LEN ("lqh") },
16419   { STRING_COMMA_LEN ("hqh") }
16420 };
16421
16422 static void
16423 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16424               int sizeflag ATTRIBUTE_UNUSED)
16425 {
16426   unsigned int pclmul_type;
16427
16428   FETCH_DATA (the_info, codep + 1);
16429   pclmul_type = *codep++ & 0xff;
16430   switch (pclmul_type)
16431     {
16432     case 0x10:
16433       pclmul_type = 2;
16434       break;
16435     case 0x11:
16436       pclmul_type = 3;
16437       break;
16438     default:
16439       break;
16440     }
16441   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16442     {
16443       char suffix [4];
16444       char *p = mnemonicendp - 3;
16445       suffix[0] = p[0];
16446       suffix[1] = p[1];
16447       suffix[2] = p[2];
16448       suffix[3] = '\0';
16449       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16450       mnemonicendp += pclmul_op[pclmul_type].len;
16451     }
16452   else
16453     {
16454       /* We have a reserved extension byte.  Output it directly.  */
16455       scratchbuf[0] = '$';
16456       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16457       oappend_maybe_intel (scratchbuf);
16458       scratchbuf[0] = '\0';
16459     }
16460 }
16461
16462 static void
16463 MOVBE_Fixup (int bytemode, int sizeflag)
16464 {
16465   /* Add proper suffix to "movbe".  */
16466   char *p = mnemonicendp;
16467
16468   switch (bytemode)
16469     {
16470     case v_mode:
16471       if (intel_syntax)
16472         goto skip;
16473
16474       USED_REX (REX_W);
16475       if (sizeflag & SUFFIX_ALWAYS)
16476         {
16477           if (rex & REX_W)
16478             *p++ = 'q';
16479           else
16480             {
16481               if (sizeflag & DFLAG)
16482                 *p++ = 'l';
16483               else
16484                 *p++ = 'w';
16485               used_prefixes |= (prefixes & PREFIX_DATA);
16486             }
16487         }
16488       break;
16489     default:
16490       oappend (INTERNAL_DISASSEMBLER_ERROR);
16491       break;
16492     }
16493   mnemonicendp = p;
16494   *p = '\0';
16495
16496 skip:
16497   OP_M (bytemode, sizeflag);
16498 }
16499
16500 static void
16501 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16502 {
16503   int reg;
16504   const char **names;
16505
16506   /* Skip mod/rm byte.  */
16507   MODRM_CHECK;
16508   codep++;
16509
16510   if (rex & REX_W)
16511     names = names64;
16512   else
16513     names = names32;
16514
16515   reg = modrm.rm;
16516   USED_REX (REX_B);
16517   if (rex & REX_B)
16518     reg += 8;
16519
16520   oappend (names[reg]);
16521 }
16522
16523 static void
16524 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16525 {
16526   const char **names;
16527   unsigned int reg = vex.register_specifier;
16528   vex.register_specifier = 0;
16529
16530   if (rex & REX_W)
16531     names = names64;
16532   else
16533     names = names32;
16534
16535   if (address_mode != mode_64bit)
16536     reg &= 7;
16537   oappend (names[reg]);
16538 }
16539
16540 static void
16541 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16542 {
16543   if (!vex.evex
16544       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16545     abort ();
16546
16547   USED_REX (REX_R);
16548   if ((rex & REX_R) != 0 || !vex.r)
16549     {
16550       BadOp ();
16551       return;
16552     }
16553
16554   oappend (names_mask [modrm.reg]);
16555 }
16556
16557 static void
16558 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16559 {
16560   if (!vex.evex
16561       || (bytemode != evex_rounding_mode
16562           && bytemode != evex_rounding_64_mode
16563           && bytemode != evex_sae_mode))
16564     abort ();
16565   if (modrm.mod == 3 && vex.b)
16566     switch (bytemode)
16567       {
16568       case evex_rounding_64_mode:
16569         if (address_mode != mode_64bit)
16570           {
16571             oappend ("(bad)");
16572             break;
16573           }
16574         /* Fall through.  */
16575       case evex_rounding_mode:
16576         oappend (names_rounding[vex.ll]);
16577         break;
16578       case evex_sae_mode:
16579         oappend ("{sae}");
16580         break;
16581       default:
16582         break;
16583       }
16584 }