opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_EX_Vex (int, int);
  92 static void OP_EX_VexW (int, int);
  93 static void OP_EX_VexImmW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_Rounding (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void SEP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128 static void MOVSXD_Fixup (int, int);
 129
 130 static void OP_Mask (int, int);
 131
 132 struct dis_private {
 133   /* Points to first byte not fetched.  */
 134   bfd_byte *max_fetched;
 135   bfd_byte the_buffer[MAX_MNEM_SIZE];
 136   bfd_vma insn_start;
 137   int orig_sizeflag;
 138   OPCODES_SIGJMP_BUF bailout;
 139 };
 140
 141 enum address_mode
 142 {
 143   mode_16bit,
 144   mode_32bit,
 145   mode_64bit
 146 };
 147
 148 enum address_mode address_mode;
 149
 150 /* Flags for the prefixes for the current instruction.  See below.  */
 151 static int prefixes;
 152
 153 /* REX prefix the current instruction.  See below.  */
 154 static int rex;
 155 /* Bits of REX we've already used.  */
 156 static int rex_used;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Jdqw { OP_J, dqw_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmmdw { OP_EX, xmmdw_mode }
 401 #define EXxmmqd { OP_EX, xmmqd_mode }
 402 #define EXymmq { OP_EX, ymmq_mode }
 403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 406 #define MS { OP_MS, v_mode }
 407 #define XS { OP_XS, v_mode }
 408 #define EMCq { OP_EMC, q_mode }
 409 #define MXC { OP_MXC, 0 }
 410 #define OPSUF { OP_3DNowSuffix, 0 }
 411 #define SEP { SEP_Fixup, 0 }
 412 #define CMP { CMP_Fixup, 0 }
 413 #define XMM0 { XMM_Fixup, 0 }
 414 #define FXSAVE { FXSAVE_Fixup, 0 }
 415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 417
 418 #define Vex { OP_VEX, vex_mode }
 419 #define VexScalar { OP_VEX, vex_scalar_mode }
 420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 421 #define Vex128 { OP_VEX, vex128_mode }
 422 #define Vex256 { OP_VEX, vex256_mode }
 423 #define VexGdq { OP_VEX, dq_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 426 #define EXVexW { OP_EX_VexW, x_mode }
 427 #define EXdVexW { OP_EX_VexW, d_mode }
 428 #define EXqVexW { OP_EX_VexW, q_mode }
 429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 431 #define XMVexW { OP_XMM_VexW, 0 }
 432 #define XMVexI4 { OP_REG_VexI4, x_mode }
 433 #define PCLMUL { PCLMUL_Fixup, 0 }
 434 #define VCMP { VCMP_Fixup, 0 }
 435 #define VPCMP { VPCMP_Fixup, 0 }
 436 #define VPCOM { VPCOM_Fixup, 0 }
 437
 438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 441
 442 #define XMask { OP_Mask, mask_mode }
 443 #define MaskG { OP_G, mask_mode }
 444 #define MaskE { OP_E, mask_mode }
 445 #define MaskBDE { OP_E, mask_bd_mode }
 446 #define MaskR { OP_R, mask_mode }
 447 #define MaskVex { OP_VEX, mask_mode }
 448
 449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 453
 454 /* Used handle "rep" prefix for string instructions.  */
 455 #define Xbr { REP_Fixup, eSI_reg }
 456 #define Xvr { REP_Fixup, eSI_reg }
 457 #define Ybr { REP_Fixup, eDI_reg }
 458 #define Yvr { REP_Fixup, eDI_reg }
 459 #define Yzr { REP_Fixup, eDI_reg }
 460 #define indirDXr { REP_Fixup, indir_dx_reg }
 461 #define ALr { REP_Fixup, al_reg }
 462 #define eAXr { REP_Fixup, eAX_reg }
 463
 464 /* Used handle HLE prefix for lockable instructions.  */
 465 #define Ebh1 { HLE_Fixup1, b_mode }
 466 #define Evh1 { HLE_Fixup1, v_mode }
 467 #define Ebh2 { HLE_Fixup2, b_mode }
 468 #define Evh2 { HLE_Fixup2, v_mode }
 469 #define Ebh3 { HLE_Fixup3, b_mode }
 470 #define Evh3 { HLE_Fixup3, v_mode }
 471
 472 #define BND { BND_Fixup, 0 }
 473 #define NOTRACK { NOTRACK_Fixup, 0 }
 474
 475 #define cond_jump_flag { NULL, cond_jump_mode }
 476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 477
 478 /* bits in sizeflag */
 479 #define SUFFIX_ALWAYS 4
 480 #define AFLAG 2
 481 #define DFLAG 1
 482
 483 enum
 484 {
 485   /* byte operand */
 486   b_mode = 1,
 487   /* byte operand with operand swapped */
 488   b_swap_mode,
 489   /* byte operand, sign extend like 'T' suffix */
 490   b_T_mode,
 491   /* operand size depends on prefixes */
 492   v_mode,
 493   /* operand size depends on prefixes with operand swapped */
 494   v_swap_mode,
 495   /* operand size depends on address prefix */
 496   va_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* 16-byte XMM, word, double word or quad word operand.  */
 536   xmmdw_mode,
 537   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 538   xmmqd_mode,
 539   /* 32-byte YMM operand */
 540   ymm_mode,
 541   /* quad word, ymmword or zmmword memory operand.  */
 542   ymmq_mode,
 543   /* 32-byte YMM or 16-byte word operand */
 544   ymmxmm_mode,
 545   /* d_mode in 32bit, q_mode in 64bit mode.  */
 546   m_mode,
 547   /* pair of v_mode operands */
 548   a_mode,
 549   cond_jump_mode,
 550   loop_jcxz_mode,
 551   movsxd_mode,
 552   v_bnd_mode,
 553   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 554   v_bndmk_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode, displacements like
 558      v_mode without considering Intel64 ISA.  */
 559   dqw_mode,
 560   /* bounds operand */
 561   bnd_mode,
 562   /* bounds operand with operand swapped */
 563   bnd_swap_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589
 590   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 591   vex_vsib_d_w_dq_mode,
 592   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 593   vex_vsib_d_w_d_mode,
 594   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 595   vex_vsib_q_w_dq_mode,
 596   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 597   vex_vsib_q_w_d_mode,
 598
 599   /* scalar, ignore vector length.  */
 600   scalar_mode,
 601   /* like b_mode, ignore vector length.  */
 602   b_scalar_mode,
 603   /* like w_mode, ignore vector length.  */
 604   w_scalar_mode,
 605   /* like d_swap_mode, ignore vector length.  */
 606   d_scalar_swap_mode,
 607   /* like q_swap_mode, ignore vector length.  */
 608   q_scalar_swap_mode,
 609   /* like vex_mode, ignore vector length.  */
 610   vex_scalar_mode,
 611   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 612   vex_scalar_w_dq_mode,
 613
 614   /* Static rounding.  */
 615   evex_rounding_mode,
 616   /* Static rounding, 64-bit mode only.  */
 617   evex_rounding_64_mode,
 618   /* Supress all exceptions.  */
 619   evex_sae_mode,
 620
 621   /* Mask register operand.  */
 622   mask_mode,
 623   /* Mask register operand.  */
 624   mask_bd_mode,
 625
 626   es_reg,
 627   cs_reg,
 628   ss_reg,
 629   ds_reg,
 630   fs_reg,
 631   gs_reg,
 632
 633   eAX_reg,
 634   eCX_reg,
 635   eDX_reg,
 636   eBX_reg,
 637   eSP_reg,
 638   eBP_reg,
 639   eSI_reg,
 640   eDI_reg,
 641
 642   al_reg,
 643   cl_reg,
 644   dl_reg,
 645   bl_reg,
 646   ah_reg,
 647   ch_reg,
 648   dh_reg,
 649   bh_reg,
 650
 651   ax_reg,
 652   cx_reg,
 653   dx_reg,
 654   bx_reg,
 655   sp_reg,
 656   bp_reg,
 657   si_reg,
 658   di_reg,
 659
 660   rAX_reg,
 661   rCX_reg,
 662   rDX_reg,
 663   rBX_reg,
 664   rSP_reg,
 665   rBP_reg,
 666   rSI_reg,
 667   rDI_reg,
 668
 669   z_mode_ax_reg,
 670   indir_dx_reg
 671 };
 672
 673 enum
 674 {
 675   FLOATCODE = 1,
 676   USE_REG_TABLE,
 677   USE_MOD_TABLE,
 678   USE_RM_TABLE,
 679   USE_PREFIX_TABLE,
 680   USE_X86_64_TABLE,
 681   USE_3BYTE_TABLE,
 682   USE_XOP_8F_TABLE,
 683   USE_VEX_C4_TABLE,
 684   USE_VEX_C5_TABLE,
 685   USE_VEX_LEN_TABLE,
 686   USE_VEX_W_TABLE,
 687   USE_EVEX_TABLE,
 688   USE_EVEX_LEN_TABLE
 689 };
 690
 691 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 692
 693 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 694 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 695 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 696 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 697 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 698 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 699 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 700 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 701 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 702 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 703 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 704 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 705 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 706 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 707 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 708 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 709
 710 enum
 711 {
 712   REG_80 = 0,
 713   REG_81,
 714   REG_83,
 715   REG_8F,
 716   REG_C0,
 717   REG_C1,
 718   REG_C6,
 719   REG_C7,
 720   REG_D0,
 721   REG_D1,
 722   REG_D2,
 723   REG_D3,
 724   REG_F6,
 725   REG_F7,
 726   REG_FE,
 727   REG_FF,
 728   REG_0F00,
 729   REG_0F01,
 730   REG_0F0D,
 731   REG_0F18,
 732   REG_0F1C_P_0_MOD_0,
 733   REG_0F1E_P_1_MOD_3,
 734   REG_0F71,
 735   REG_0F72,
 736   REG_0F73,
 737   REG_0FA6,
 738   REG_0FA7,
 739   REG_0FAE,
 740   REG_0FBA,
 741   REG_0FC7,
 742   REG_VEX_0F71,
 743   REG_VEX_0F72,
 744   REG_VEX_0F73,
 745   REG_VEX_0FAE,
 746   REG_VEX_0F38F3,
 747   REG_XOP_LWPCB,
 748   REG_XOP_LWP,
 749   REG_XOP_TBM_01,
 750   REG_XOP_TBM_02,
 751
 752   REG_EVEX_0F71,
 753   REG_EVEX_0F72,
 754   REG_EVEX_0F73,
 755   REG_EVEX_0F38C6,
 756   REG_EVEX_0F38C7
 757 };
 758
 759 enum
 760 {
 761   MOD_8D = 0,
 762   MOD_C6_REG_7,
 763   MOD_C7_REG_7,
 764   MOD_FF_REG_3,
 765   MOD_FF_REG_5,
 766   MOD_0F01_REG_0,
 767   MOD_0F01_REG_1,
 768   MOD_0F01_REG_2,
 769   MOD_0F01_REG_3,
 770   MOD_0F01_REG_5,
 771   MOD_0F01_REG_7,
 772   MOD_0F12_PREFIX_0,
 773   MOD_0F12_PREFIX_2,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F16_PREFIX_2,
 777   MOD_0F17,
 778   MOD_0F18_REG_0,
 779   MOD_0F18_REG_1,
 780   MOD_0F18_REG_2,
 781   MOD_0F18_REG_3,
 782   MOD_0F18_REG_4,
 783   MOD_0F18_REG_5,
 784   MOD_0F18_REG_6,
 785   MOD_0F18_REG_7,
 786   MOD_0F1A_PREFIX_0,
 787   MOD_0F1B_PREFIX_0,
 788   MOD_0F1B_PREFIX_1,
 789   MOD_0F1C_PREFIX_0,
 790   MOD_0F1E_PREFIX_1,
 791   MOD_0F24,
 792   MOD_0F26,
 793   MOD_0F2B_PREFIX_0,
 794   MOD_0F2B_PREFIX_1,
 795   MOD_0F2B_PREFIX_2,
 796   MOD_0F2B_PREFIX_3,
 797   MOD_0F50,
 798   MOD_0F71_REG_2,
 799   MOD_0F71_REG_4,
 800   MOD_0F71_REG_6,
 801   MOD_0F72_REG_2,
 802   MOD_0F72_REG_4,
 803   MOD_0F72_REG_6,
 804   MOD_0F73_REG_2,
 805   MOD_0F73_REG_3,
 806   MOD_0F73_REG_6,
 807   MOD_0F73_REG_7,
 808   MOD_0FAE_REG_0,
 809   MOD_0FAE_REG_1,
 810   MOD_0FAE_REG_2,
 811   MOD_0FAE_REG_3,
 812   MOD_0FAE_REG_4,
 813   MOD_0FAE_REG_5,
 814   MOD_0FAE_REG_6,
 815   MOD_0FAE_REG_7,
 816   MOD_0FB2,
 817   MOD_0FB4,
 818   MOD_0FB5,
 819   MOD_0FC3,
 820   MOD_0FC7_REG_3,
 821   MOD_0FC7_REG_4,
 822   MOD_0FC7_REG_5,
 823   MOD_0FC7_REG_6,
 824   MOD_0FC7_REG_7,
 825   MOD_0FD7,
 826   MOD_0FE7_PREFIX_2,
 827   MOD_0FF0_PREFIX_3,
 828   MOD_0F382A_PREFIX_2,
 829   MOD_0F38F5_PREFIX_2,
 830   MOD_0F38F6_PREFIX_0,
 831   MOD_0F38F8_PREFIX_1,
 832   MOD_0F38F8_PREFIX_2,
 833   MOD_0F38F8_PREFIX_3,
 834   MOD_0F38F9_PREFIX_0,
 835   MOD_62_32BIT,
 836   MOD_C4_32BIT,
 837   MOD_C5_32BIT,
 838   MOD_VEX_0F12_PREFIX_0,
 839   MOD_VEX_0F12_PREFIX_2,
 840   MOD_VEX_0F13,
 841   MOD_VEX_0F16_PREFIX_0,
 842   MOD_VEX_0F16_PREFIX_2,
 843   MOD_VEX_0F17,
 844   MOD_VEX_0F2B,
 845   MOD_VEX_W_0_0F41_P_0_LEN_1,
 846   MOD_VEX_W_1_0F41_P_0_LEN_1,
 847   MOD_VEX_W_0_0F41_P_2_LEN_1,
 848   MOD_VEX_W_1_0F41_P_2_LEN_1,
 849   MOD_VEX_W_0_0F42_P_0_LEN_1,
 850   MOD_VEX_W_1_0F42_P_0_LEN_1,
 851   MOD_VEX_W_0_0F42_P_2_LEN_1,
 852   MOD_VEX_W_1_0F42_P_2_LEN_1,
 853   MOD_VEX_W_0_0F44_P_0_LEN_1,
 854   MOD_VEX_W_1_0F44_P_0_LEN_1,
 855   MOD_VEX_W_0_0F44_P_2_LEN_1,
 856   MOD_VEX_W_1_0F44_P_2_LEN_1,
 857   MOD_VEX_W_0_0F45_P_0_LEN_1,
 858   MOD_VEX_W_1_0F45_P_0_LEN_1,
 859   MOD_VEX_W_0_0F45_P_2_LEN_1,
 860   MOD_VEX_W_1_0F45_P_2_LEN_1,
 861   MOD_VEX_W_0_0F46_P_0_LEN_1,
 862   MOD_VEX_W_1_0F46_P_0_LEN_1,
 863   MOD_VEX_W_0_0F46_P_2_LEN_1,
 864   MOD_VEX_W_1_0F46_P_2_LEN_1,
 865   MOD_VEX_W_0_0F47_P_0_LEN_1,
 866   MOD_VEX_W_1_0F47_P_0_LEN_1,
 867   MOD_VEX_W_0_0F47_P_2_LEN_1,
 868   MOD_VEX_W_1_0F47_P_2_LEN_1,
 869   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 870   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 871   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 872   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 873   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 874   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 875   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 876   MOD_VEX_0F50,
 877   MOD_VEX_0F71_REG_2,
 878   MOD_VEX_0F71_REG_4,
 879   MOD_VEX_0F71_REG_6,
 880   MOD_VEX_0F72_REG_2,
 881   MOD_VEX_0F72_REG_4,
 882   MOD_VEX_0F72_REG_6,
 883   MOD_VEX_0F73_REG_2,
 884   MOD_VEX_0F73_REG_3,
 885   MOD_VEX_0F73_REG_6,
 886   MOD_VEX_0F73_REG_7,
 887   MOD_VEX_W_0_0F91_P_0_LEN_0,
 888   MOD_VEX_W_1_0F91_P_0_LEN_0,
 889   MOD_VEX_W_0_0F91_P_2_LEN_0,
 890   MOD_VEX_W_1_0F91_P_2_LEN_0,
 891   MOD_VEX_W_0_0F92_P_0_LEN_0,
 892   MOD_VEX_W_0_0F92_P_2_LEN_0,
 893   MOD_VEX_0F92_P_3_LEN_0,
 894   MOD_VEX_W_0_0F93_P_0_LEN_0,
 895   MOD_VEX_W_0_0F93_P_2_LEN_0,
 896   MOD_VEX_0F93_P_3_LEN_0,
 897   MOD_VEX_W_0_0F98_P_0_LEN_0,
 898   MOD_VEX_W_1_0F98_P_0_LEN_0,
 899   MOD_VEX_W_0_0F98_P_2_LEN_0,
 900   MOD_VEX_W_1_0F98_P_2_LEN_0,
 901   MOD_VEX_W_0_0F99_P_0_LEN_0,
 902   MOD_VEX_W_1_0F99_P_0_LEN_0,
 903   MOD_VEX_W_0_0F99_P_2_LEN_0,
 904   MOD_VEX_W_1_0F99_P_2_LEN_0,
 905   MOD_VEX_0FAE_REG_2,
 906   MOD_VEX_0FAE_REG_3,
 907   MOD_VEX_0FD7_PREFIX_2,
 908   MOD_VEX_0FE7_PREFIX_2,
 909   MOD_VEX_0FF0_PREFIX_3,
 910   MOD_VEX_0F381A_PREFIX_2,
 911   MOD_VEX_0F382A_PREFIX_2,
 912   MOD_VEX_0F382C_PREFIX_2,
 913   MOD_VEX_0F382D_PREFIX_2,
 914   MOD_VEX_0F382E_PREFIX_2,
 915   MOD_VEX_0F382F_PREFIX_2,
 916   MOD_VEX_0F385A_PREFIX_2,
 917   MOD_VEX_0F388C_PREFIX_2,
 918   MOD_VEX_0F388E_PREFIX_2,
 919   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 923   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 925   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 927
 928   MOD_EVEX_0F12_PREFIX_0,
 929   MOD_EVEX_0F12_PREFIX_2,
 930   MOD_EVEX_0F13,
 931   MOD_EVEX_0F16_PREFIX_0,
 932   MOD_EVEX_0F16_PREFIX_2,
 933   MOD_EVEX_0F17,
 934   MOD_EVEX_0F2B,
 935   MOD_EVEX_0F38C6_REG_1,
 936   MOD_EVEX_0F38C6_REG_2,
 937   MOD_EVEX_0F38C6_REG_5,
 938   MOD_EVEX_0F38C6_REG_6,
 939   MOD_EVEX_0F38C7_REG_1,
 940   MOD_EVEX_0F38C7_REG_2,
 941   MOD_EVEX_0F38C7_REG_5,
 942   MOD_EVEX_0F38C7_REG_6
 943 };
 944
 945 enum
 946 {
 947   RM_C6_REG_7 = 0,
 948   RM_C7_REG_7,
 949   RM_0F01_REG_0,
 950   RM_0F01_REG_1,
 951   RM_0F01_REG_2,
 952   RM_0F01_REG_3,
 953   RM_0F01_REG_5_MOD_3,
 954   RM_0F01_REG_7_MOD_3,
 955   RM_0F1E_P_1_MOD_3_REG_7,
 956   RM_0FAE_REG_6_MOD_3_P_0,
 957   RM_0FAE_REG_7_MOD_3,
 958 };
 959
 960 enum
 961 {
 962   PREFIX_90 = 0,
 963   PREFIX_0F01_REG_3_RM_1,
 964   PREFIX_0F01_REG_5_MOD_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_0,
 966   PREFIX_0F01_REG_5_MOD_3_RM_1,
 967   PREFIX_0F01_REG_5_MOD_3_RM_2,
 968   PREFIX_0F01_REG_7_MOD_3_RM_2,
 969   PREFIX_0F01_REG_7_MOD_3_RM_3,
 970   PREFIX_0F09,
 971   PREFIX_0F10,
 972   PREFIX_0F11,
 973   PREFIX_0F12,
 974   PREFIX_0F16,
 975   PREFIX_0F1A,
 976   PREFIX_0F1B,
 977   PREFIX_0F1C,
 978   PREFIX_0F1E,
 979   PREFIX_0F2A,
 980   PREFIX_0F2B,
 981   PREFIX_0F2C,
 982   PREFIX_0F2D,
 983   PREFIX_0F2E,
 984   PREFIX_0F2F,
 985   PREFIX_0F51,
 986   PREFIX_0F52,
 987   PREFIX_0F53,
 988   PREFIX_0F58,
 989   PREFIX_0F59,
 990   PREFIX_0F5A,
 991   PREFIX_0F5B,
 992   PREFIX_0F5C,
 993   PREFIX_0F5D,
 994   PREFIX_0F5E,
 995   PREFIX_0F5F,
 996   PREFIX_0F60,
 997   PREFIX_0F61,
 998   PREFIX_0F62,
 999   PREFIX_0F6C,
1000   PREFIX_0F6D,
1001   PREFIX_0F6F,
1002   PREFIX_0F70,
1003   PREFIX_0F73_REG_3,
1004   PREFIX_0F73_REG_7,
1005   PREFIX_0F78,
1006   PREFIX_0F79,
1007   PREFIX_0F7C,
1008   PREFIX_0F7D,
1009   PREFIX_0F7E,
1010   PREFIX_0F7F,
1011   PREFIX_0FAE_REG_0_MOD_3,
1012   PREFIX_0FAE_REG_1_MOD_3,
1013   PREFIX_0FAE_REG_2_MOD_3,
1014   PREFIX_0FAE_REG_3_MOD_3,
1015   PREFIX_0FAE_REG_4_MOD_0,
1016   PREFIX_0FAE_REG_4_MOD_3,
1017   PREFIX_0FAE_REG_5_MOD_0,
1018   PREFIX_0FAE_REG_5_MOD_3,
1019   PREFIX_0FAE_REG_6_MOD_0,
1020   PREFIX_0FAE_REG_6_MOD_3,
1021   PREFIX_0FAE_REG_7_MOD_0,
1022   PREFIX_0FB8,
1023   PREFIX_0FBC,
1024   PREFIX_0FBD,
1025   PREFIX_0FC2,
1026   PREFIX_0FC3_MOD_0,
1027   PREFIX_0FC7_REG_6_MOD_0,
1028   PREFIX_0FC7_REG_6_MOD_3,
1029   PREFIX_0FC7_REG_7_MOD_3,
1030   PREFIX_0FD0,
1031   PREFIX_0FD6,
1032   PREFIX_0FE6,
1033   PREFIX_0FE7,
1034   PREFIX_0FF0,
1035   PREFIX_0FF7,
1036   PREFIX_0F3810,
1037   PREFIX_0F3814,
1038   PREFIX_0F3815,
1039   PREFIX_0F3817,
1040   PREFIX_0F3820,
1041   PREFIX_0F3821,
1042   PREFIX_0F3822,
1043   PREFIX_0F3823,
1044   PREFIX_0F3824,
1045   PREFIX_0F3825,
1046   PREFIX_0F3828,
1047   PREFIX_0F3829,
1048   PREFIX_0F382A,
1049   PREFIX_0F382B,
1050   PREFIX_0F3830,
1051   PREFIX_0F3831,
1052   PREFIX_0F3832,
1053   PREFIX_0F3833,
1054   PREFIX_0F3834,
1055   PREFIX_0F3835,
1056   PREFIX_0F3837,
1057   PREFIX_0F3838,
1058   PREFIX_0F3839,
1059   PREFIX_0F383A,
1060   PREFIX_0F383B,
1061   PREFIX_0F383C,
1062   PREFIX_0F383D,
1063   PREFIX_0F383E,
1064   PREFIX_0F383F,
1065   PREFIX_0F3840,
1066   PREFIX_0F3841,
1067   PREFIX_0F3880,
1068   PREFIX_0F3881,
1069   PREFIX_0F3882,
1070   PREFIX_0F38C8,
1071   PREFIX_0F38C9,
1072   PREFIX_0F38CA,
1073   PREFIX_0F38CB,
1074   PREFIX_0F38CC,
1075   PREFIX_0F38CD,
1076   PREFIX_0F38CF,
1077   PREFIX_0F38DB,
1078   PREFIX_0F38DC,
1079   PREFIX_0F38DD,
1080   PREFIX_0F38DE,
1081   PREFIX_0F38DF,
1082   PREFIX_0F38F0,
1083   PREFIX_0F38F1,
1084   PREFIX_0F38F5,
1085   PREFIX_0F38F6,
1086   PREFIX_0F38F8,
1087   PREFIX_0F38F9,
1088   PREFIX_0F3A08,
1089   PREFIX_0F3A09,
1090   PREFIX_0F3A0A,
1091   PREFIX_0F3A0B,
1092   PREFIX_0F3A0C,
1093   PREFIX_0F3A0D,
1094   PREFIX_0F3A0E,
1095   PREFIX_0F3A14,
1096   PREFIX_0F3A15,
1097   PREFIX_0F3A16,
1098   PREFIX_0F3A17,
1099   PREFIX_0F3A20,
1100   PREFIX_0F3A21,
1101   PREFIX_0F3A22,
1102   PREFIX_0F3A40,
1103   PREFIX_0F3A41,
1104   PREFIX_0F3A42,
1105   PREFIX_0F3A44,
1106   PREFIX_0F3A60,
1107   PREFIX_0F3A61,
1108   PREFIX_0F3A62,
1109   PREFIX_0F3A63,
1110   PREFIX_0F3ACC,
1111   PREFIX_0F3ACE,
1112   PREFIX_0F3ACF,
1113   PREFIX_0F3ADF,
1114   PREFIX_VEX_0F10,
1115   PREFIX_VEX_0F11,
1116   PREFIX_VEX_0F12,
1117   PREFIX_VEX_0F16,
1118   PREFIX_VEX_0F2A,
1119   PREFIX_VEX_0F2C,
1120   PREFIX_VEX_0F2D,
1121   PREFIX_VEX_0F2E,
1122   PREFIX_VEX_0F2F,
1123   PREFIX_VEX_0F41,
1124   PREFIX_VEX_0F42,
1125   PREFIX_VEX_0F44,
1126   PREFIX_VEX_0F45,
1127   PREFIX_VEX_0F46,
1128   PREFIX_VEX_0F47,
1129   PREFIX_VEX_0F4A,
1130   PREFIX_VEX_0F4B,
1131   PREFIX_VEX_0F51,
1132   PREFIX_VEX_0F52,
1133   PREFIX_VEX_0F53,
1134   PREFIX_VEX_0F58,
1135   PREFIX_VEX_0F59,
1136   PREFIX_VEX_0F5A,
1137   PREFIX_VEX_0F5B,
1138   PREFIX_VEX_0F5C,
1139   PREFIX_VEX_0F5D,
1140   PREFIX_VEX_0F5E,
1141   PREFIX_VEX_0F5F,
1142   PREFIX_VEX_0F60,
1143   PREFIX_VEX_0F61,
1144   PREFIX_VEX_0F62,
1145   PREFIX_VEX_0F63,
1146   PREFIX_VEX_0F64,
1147   PREFIX_VEX_0F65,
1148   PREFIX_VEX_0F66,
1149   PREFIX_VEX_0F67,
1150   PREFIX_VEX_0F68,
1151   PREFIX_VEX_0F69,
1152   PREFIX_VEX_0F6A,
1153   PREFIX_VEX_0F6B,
1154   PREFIX_VEX_0F6C,
1155   PREFIX_VEX_0F6D,
1156   PREFIX_VEX_0F6E,
1157   PREFIX_VEX_0F6F,
1158   PREFIX_VEX_0F70,
1159   PREFIX_VEX_0F71_REG_2,
1160   PREFIX_VEX_0F71_REG_4,
1161   PREFIX_VEX_0F71_REG_6,
1162   PREFIX_VEX_0F72_REG_2,
1163   PREFIX_VEX_0F72_REG_4,
1164   PREFIX_VEX_0F72_REG_6,
1165   PREFIX_VEX_0F73_REG_2,
1166   PREFIX_VEX_0F73_REG_3,
1167   PREFIX_VEX_0F73_REG_6,
1168   PREFIX_VEX_0F73_REG_7,
1169   PREFIX_VEX_0F74,
1170   PREFIX_VEX_0F75,
1171   PREFIX_VEX_0F76,
1172   PREFIX_VEX_0F77,
1173   PREFIX_VEX_0F7C,
1174   PREFIX_VEX_0F7D,
1175   PREFIX_VEX_0F7E,
1176   PREFIX_VEX_0F7F,
1177   PREFIX_VEX_0F90,
1178   PREFIX_VEX_0F91,
1179   PREFIX_VEX_0F92,
1180   PREFIX_VEX_0F93,
1181   PREFIX_VEX_0F98,
1182   PREFIX_VEX_0F99,
1183   PREFIX_VEX_0FC2,
1184   PREFIX_VEX_0FC4,
1185   PREFIX_VEX_0FC5,
1186   PREFIX_VEX_0FD0,
1187   PREFIX_VEX_0FD1,
1188   PREFIX_VEX_0FD2,
1189   PREFIX_VEX_0FD3,
1190   PREFIX_VEX_0FD4,
1191   PREFIX_VEX_0FD5,
1192   PREFIX_VEX_0FD6,
1193   PREFIX_VEX_0FD7,
1194   PREFIX_VEX_0FD8,
1195   PREFIX_VEX_0FD9,
1196   PREFIX_VEX_0FDA,
1197   PREFIX_VEX_0FDB,
1198   PREFIX_VEX_0FDC,
1199   PREFIX_VEX_0FDD,
1200   PREFIX_VEX_0FDE,
1201   PREFIX_VEX_0FDF,
1202   PREFIX_VEX_0FE0,
1203   PREFIX_VEX_0FE1,
1204   PREFIX_VEX_0FE2,
1205   PREFIX_VEX_0FE3,
1206   PREFIX_VEX_0FE4,
1207   PREFIX_VEX_0FE5,
1208   PREFIX_VEX_0FE6,
1209   PREFIX_VEX_0FE7,
1210   PREFIX_VEX_0FE8,
1211   PREFIX_VEX_0FE9,
1212   PREFIX_VEX_0FEA,
1213   PREFIX_VEX_0FEB,
1214   PREFIX_VEX_0FEC,
1215   PREFIX_VEX_0FED,
1216   PREFIX_VEX_0FEE,
1217   PREFIX_VEX_0FEF,
1218   PREFIX_VEX_0FF0,
1219   PREFIX_VEX_0FF1,
1220   PREFIX_VEX_0FF2,
1221   PREFIX_VEX_0FF3,
1222   PREFIX_VEX_0FF4,
1223   PREFIX_VEX_0FF5,
1224   PREFIX_VEX_0FF6,
1225   PREFIX_VEX_0FF7,
1226   PREFIX_VEX_0FF8,
1227   PREFIX_VEX_0FF9,
1228   PREFIX_VEX_0FFA,
1229   PREFIX_VEX_0FFB,
1230   PREFIX_VEX_0FFC,
1231   PREFIX_VEX_0FFD,
1232   PREFIX_VEX_0FFE,
1233   PREFIX_VEX_0F3800,
1234   PREFIX_VEX_0F3801,
1235   PREFIX_VEX_0F3802,
1236   PREFIX_VEX_0F3803,
1237   PREFIX_VEX_0F3804,
1238   PREFIX_VEX_0F3805,
1239   PREFIX_VEX_0F3806,
1240   PREFIX_VEX_0F3807,
1241   PREFIX_VEX_0F3808,
1242   PREFIX_VEX_0F3809,
1243   PREFIX_VEX_0F380A,
1244   PREFIX_VEX_0F380B,
1245   PREFIX_VEX_0F380C,
1246   PREFIX_VEX_0F380D,
1247   PREFIX_VEX_0F380E,
1248   PREFIX_VEX_0F380F,
1249   PREFIX_VEX_0F3813,
1250   PREFIX_VEX_0F3816,
1251   PREFIX_VEX_0F3817,
1252   PREFIX_VEX_0F3818,
1253   PREFIX_VEX_0F3819,
1254   PREFIX_VEX_0F381A,
1255   PREFIX_VEX_0F381C,
1256   PREFIX_VEX_0F381D,
1257   PREFIX_VEX_0F381E,
1258   PREFIX_VEX_0F3820,
1259   PREFIX_VEX_0F3821,
1260   PREFIX_VEX_0F3822,
1261   PREFIX_VEX_0F3823,
1262   PREFIX_VEX_0F3824,
1263   PREFIX_VEX_0F3825,
1264   PREFIX_VEX_0F3828,
1265   PREFIX_VEX_0F3829,
1266   PREFIX_VEX_0F382A,
1267   PREFIX_VEX_0F382B,
1268   PREFIX_VEX_0F382C,
1269   PREFIX_VEX_0F382D,
1270   PREFIX_VEX_0F382E,
1271   PREFIX_VEX_0F382F,
1272   PREFIX_VEX_0F3830,
1273   PREFIX_VEX_0F3831,
1274   PREFIX_VEX_0F3832,
1275   PREFIX_VEX_0F3833,
1276   PREFIX_VEX_0F3834,
1277   PREFIX_VEX_0F3835,
1278   PREFIX_VEX_0F3836,
1279   PREFIX_VEX_0F3837,
1280   PREFIX_VEX_0F3838,
1281   PREFIX_VEX_0F3839,
1282   PREFIX_VEX_0F383A,
1283   PREFIX_VEX_0F383B,
1284   PREFIX_VEX_0F383C,
1285   PREFIX_VEX_0F383D,
1286   PREFIX_VEX_0F383E,
1287   PREFIX_VEX_0F383F,
1288   PREFIX_VEX_0F3840,
1289   PREFIX_VEX_0F3841,
1290   PREFIX_VEX_0F3845,
1291   PREFIX_VEX_0F3846,
1292   PREFIX_VEX_0F3847,
1293   PREFIX_VEX_0F3858,
1294   PREFIX_VEX_0F3859,
1295   PREFIX_VEX_0F385A,
1296   PREFIX_VEX_0F3878,
1297   PREFIX_VEX_0F3879,
1298   PREFIX_VEX_0F388C,
1299   PREFIX_VEX_0F388E,
1300   PREFIX_VEX_0F3890,
1301   PREFIX_VEX_0F3891,
1302   PREFIX_VEX_0F3892,
1303   PREFIX_VEX_0F3893,
1304   PREFIX_VEX_0F3896,
1305   PREFIX_VEX_0F3897,
1306   PREFIX_VEX_0F3898,
1307   PREFIX_VEX_0F3899,
1308   PREFIX_VEX_0F389A,
1309   PREFIX_VEX_0F389B,
1310   PREFIX_VEX_0F389C,
1311   PREFIX_VEX_0F389D,
1312   PREFIX_VEX_0F389E,
1313   PREFIX_VEX_0F389F,
1314   PREFIX_VEX_0F38A6,
1315   PREFIX_VEX_0F38A7,
1316   PREFIX_VEX_0F38A8,
1317   PREFIX_VEX_0F38A9,
1318   PREFIX_VEX_0F38AA,
1319   PREFIX_VEX_0F38AB,
1320   PREFIX_VEX_0F38AC,
1321   PREFIX_VEX_0F38AD,
1322   PREFIX_VEX_0F38AE,
1323   PREFIX_VEX_0F38AF,
1324   PREFIX_VEX_0F38B6,
1325   PREFIX_VEX_0F38B7,
1326   PREFIX_VEX_0F38B8,
1327   PREFIX_VEX_0F38B9,
1328   PREFIX_VEX_0F38BA,
1329   PREFIX_VEX_0F38BB,
1330   PREFIX_VEX_0F38BC,
1331   PREFIX_VEX_0F38BD,
1332   PREFIX_VEX_0F38BE,
1333   PREFIX_VEX_0F38BF,
1334   PREFIX_VEX_0F38CF,
1335   PREFIX_VEX_0F38DB,
1336   PREFIX_VEX_0F38DC,
1337   PREFIX_VEX_0F38DD,
1338   PREFIX_VEX_0F38DE,
1339   PREFIX_VEX_0F38DF,
1340   PREFIX_VEX_0F38F2,
1341   PREFIX_VEX_0F38F3_REG_1,
1342   PREFIX_VEX_0F38F3_REG_2,
1343   PREFIX_VEX_0F38F3_REG_3,
1344   PREFIX_VEX_0F38F5,
1345   PREFIX_VEX_0F38F6,
1346   PREFIX_VEX_0F38F7,
1347   PREFIX_VEX_0F3A00,
1348   PREFIX_VEX_0F3A01,
1349   PREFIX_VEX_0F3A02,
1350   PREFIX_VEX_0F3A04,
1351   PREFIX_VEX_0F3A05,
1352   PREFIX_VEX_0F3A06,
1353   PREFIX_VEX_0F3A08,
1354   PREFIX_VEX_0F3A09,
1355   PREFIX_VEX_0F3A0A,
1356   PREFIX_VEX_0F3A0B,
1357   PREFIX_VEX_0F3A0C,
1358   PREFIX_VEX_0F3A0D,
1359   PREFIX_VEX_0F3A0E,
1360   PREFIX_VEX_0F3A0F,
1361   PREFIX_VEX_0F3A14,
1362   PREFIX_VEX_0F3A15,
1363   PREFIX_VEX_0F3A16,
1364   PREFIX_VEX_0F3A17,
1365   PREFIX_VEX_0F3A18,
1366   PREFIX_VEX_0F3A19,
1367   PREFIX_VEX_0F3A1D,
1368   PREFIX_VEX_0F3A20,
1369   PREFIX_VEX_0F3A21,
1370   PREFIX_VEX_0F3A22,
1371   PREFIX_VEX_0F3A30,
1372   PREFIX_VEX_0F3A31,
1373   PREFIX_VEX_0F3A32,
1374   PREFIX_VEX_0F3A33,
1375   PREFIX_VEX_0F3A38,
1376   PREFIX_VEX_0F3A39,
1377   PREFIX_VEX_0F3A40,
1378   PREFIX_VEX_0F3A41,
1379   PREFIX_VEX_0F3A42,
1380   PREFIX_VEX_0F3A44,
1381   PREFIX_VEX_0F3A46,
1382   PREFIX_VEX_0F3A48,
1383   PREFIX_VEX_0F3A49,
1384   PREFIX_VEX_0F3A4A,
1385   PREFIX_VEX_0F3A4B,
1386   PREFIX_VEX_0F3A4C,
1387   PREFIX_VEX_0F3A5C,
1388   PREFIX_VEX_0F3A5D,
1389   PREFIX_VEX_0F3A5E,
1390   PREFIX_VEX_0F3A5F,
1391   PREFIX_VEX_0F3A60,
1392   PREFIX_VEX_0F3A61,
1393   PREFIX_VEX_0F3A62,
1394   PREFIX_VEX_0F3A63,
1395   PREFIX_VEX_0F3A68,
1396   PREFIX_VEX_0F3A69,
1397   PREFIX_VEX_0F3A6A,
1398   PREFIX_VEX_0F3A6B,
1399   PREFIX_VEX_0F3A6C,
1400   PREFIX_VEX_0F3A6D,
1401   PREFIX_VEX_0F3A6E,
1402   PREFIX_VEX_0F3A6F,
1403   PREFIX_VEX_0F3A78,
1404   PREFIX_VEX_0F3A79,
1405   PREFIX_VEX_0F3A7A,
1406   PREFIX_VEX_0F3A7B,
1407   PREFIX_VEX_0F3A7C,
1408   PREFIX_VEX_0F3A7D,
1409   PREFIX_VEX_0F3A7E,
1410   PREFIX_VEX_0F3A7F,
1411   PREFIX_VEX_0F3ACE,
1412   PREFIX_VEX_0F3ACF,
1413   PREFIX_VEX_0F3ADF,
1414   PREFIX_VEX_0F3AF0,
1415
1416   PREFIX_EVEX_0F10,
1417   PREFIX_EVEX_0F11,
1418   PREFIX_EVEX_0F12,
1419   PREFIX_EVEX_0F16,
1420   PREFIX_EVEX_0F2A,
1421   PREFIX_EVEX_0F2C,
1422   PREFIX_EVEX_0F2D,
1423   PREFIX_EVEX_0F2E,
1424   PREFIX_EVEX_0F2F,
1425   PREFIX_EVEX_0F51,
1426   PREFIX_EVEX_0F58,
1427   PREFIX_EVEX_0F59,
1428   PREFIX_EVEX_0F5A,
1429   PREFIX_EVEX_0F5B,
1430   PREFIX_EVEX_0F5C,
1431   PREFIX_EVEX_0F5D,
1432   PREFIX_EVEX_0F5E,
1433   PREFIX_EVEX_0F5F,
1434   PREFIX_EVEX_0F62,
1435   PREFIX_EVEX_0F64,
1436   PREFIX_EVEX_0F65,
1437   PREFIX_EVEX_0F66,
1438   PREFIX_EVEX_0F6A,
1439   PREFIX_EVEX_0F6B,
1440   PREFIX_EVEX_0F6C,
1441   PREFIX_EVEX_0F6D,
1442   PREFIX_EVEX_0F6E,
1443   PREFIX_EVEX_0F6F,
1444   PREFIX_EVEX_0F70,
1445   PREFIX_EVEX_0F71_REG_2,
1446   PREFIX_EVEX_0F71_REG_4,
1447   PREFIX_EVEX_0F71_REG_6,
1448   PREFIX_EVEX_0F72_REG_0,
1449   PREFIX_EVEX_0F72_REG_1,
1450   PREFIX_EVEX_0F72_REG_2,
1451   PREFIX_EVEX_0F72_REG_4,
1452   PREFIX_EVEX_0F72_REG_6,
1453   PREFIX_EVEX_0F73_REG_2,
1454   PREFIX_EVEX_0F73_REG_3,
1455   PREFIX_EVEX_0F73_REG_6,
1456   PREFIX_EVEX_0F73_REG_7,
1457   PREFIX_EVEX_0F74,
1458   PREFIX_EVEX_0F75,
1459   PREFIX_EVEX_0F76,
1460   PREFIX_EVEX_0F78,
1461   PREFIX_EVEX_0F79,
1462   PREFIX_EVEX_0F7A,
1463   PREFIX_EVEX_0F7B,
1464   PREFIX_EVEX_0F7E,
1465   PREFIX_EVEX_0F7F,
1466   PREFIX_EVEX_0FC2,
1467   PREFIX_EVEX_0FC4,
1468   PREFIX_EVEX_0FC5,
1469   PREFIX_EVEX_0FD2,
1470   PREFIX_EVEX_0FD3,
1471   PREFIX_EVEX_0FD4,
1472   PREFIX_EVEX_0FD6,
1473   PREFIX_EVEX_0FDB,
1474   PREFIX_EVEX_0FDF,
1475   PREFIX_EVEX_0FE2,
1476   PREFIX_EVEX_0FE6,
1477   PREFIX_EVEX_0FE7,
1478   PREFIX_EVEX_0FEB,
1479   PREFIX_EVEX_0FEF,
1480   PREFIX_EVEX_0FF2,
1481   PREFIX_EVEX_0FF3,
1482   PREFIX_EVEX_0FF4,
1483   PREFIX_EVEX_0FFA,
1484   PREFIX_EVEX_0FFB,
1485   PREFIX_EVEX_0FFE,
1486   PREFIX_EVEX_0F380D,
1487   PREFIX_EVEX_0F3810,
1488   PREFIX_EVEX_0F3811,
1489   PREFIX_EVEX_0F3812,
1490   PREFIX_EVEX_0F3813,
1491   PREFIX_EVEX_0F3814,
1492   PREFIX_EVEX_0F3815,
1493   PREFIX_EVEX_0F3816,
1494   PREFIX_EVEX_0F3819,
1495   PREFIX_EVEX_0F381A,
1496   PREFIX_EVEX_0F381B,
1497   PREFIX_EVEX_0F381E,
1498   PREFIX_EVEX_0F381F,
1499   PREFIX_EVEX_0F3820,
1500   PREFIX_EVEX_0F3821,
1501   PREFIX_EVEX_0F3822,
1502   PREFIX_EVEX_0F3823,
1503   PREFIX_EVEX_0F3824,
1504   PREFIX_EVEX_0F3825,
1505   PREFIX_EVEX_0F3826,
1506   PREFIX_EVEX_0F3827,
1507   PREFIX_EVEX_0F3828,
1508   PREFIX_EVEX_0F3829,
1509   PREFIX_EVEX_0F382A,
1510   PREFIX_EVEX_0F382B,
1511   PREFIX_EVEX_0F382C,
1512   PREFIX_EVEX_0F382D,
1513   PREFIX_EVEX_0F3830,
1514   PREFIX_EVEX_0F3831,
1515   PREFIX_EVEX_0F3832,
1516   PREFIX_EVEX_0F3833,
1517   PREFIX_EVEX_0F3834,
1518   PREFIX_EVEX_0F3835,
1519   PREFIX_EVEX_0F3836,
1520   PREFIX_EVEX_0F3837,
1521   PREFIX_EVEX_0F3838,
1522   PREFIX_EVEX_0F3839,
1523   PREFIX_EVEX_0F383A,
1524   PREFIX_EVEX_0F383B,
1525   PREFIX_EVEX_0F383D,
1526   PREFIX_EVEX_0F383F,
1527   PREFIX_EVEX_0F3840,
1528   PREFIX_EVEX_0F3842,
1529   PREFIX_EVEX_0F3843,
1530   PREFIX_EVEX_0F3844,
1531   PREFIX_EVEX_0F3845,
1532   PREFIX_EVEX_0F3846,
1533   PREFIX_EVEX_0F3847,
1534   PREFIX_EVEX_0F384C,
1535   PREFIX_EVEX_0F384D,
1536   PREFIX_EVEX_0F384E,
1537   PREFIX_EVEX_0F384F,
1538   PREFIX_EVEX_0F3850,
1539   PREFIX_EVEX_0F3851,
1540   PREFIX_EVEX_0F3852,
1541   PREFIX_EVEX_0F3853,
1542   PREFIX_EVEX_0F3854,
1543   PREFIX_EVEX_0F3855,
1544   PREFIX_EVEX_0F3859,
1545   PREFIX_EVEX_0F385A,
1546   PREFIX_EVEX_0F385B,
1547   PREFIX_EVEX_0F3862,
1548   PREFIX_EVEX_0F3863,
1549   PREFIX_EVEX_0F3864,
1550   PREFIX_EVEX_0F3865,
1551   PREFIX_EVEX_0F3866,
1552   PREFIX_EVEX_0F3868,
1553   PREFIX_EVEX_0F3870,
1554   PREFIX_EVEX_0F3871,
1555   PREFIX_EVEX_0F3872,
1556   PREFIX_EVEX_0F3873,
1557   PREFIX_EVEX_0F3875,
1558   PREFIX_EVEX_0F3876,
1559   PREFIX_EVEX_0F3877,
1560   PREFIX_EVEX_0F387A,
1561   PREFIX_EVEX_0F387B,
1562   PREFIX_EVEX_0F387C,
1563   PREFIX_EVEX_0F387D,
1564   PREFIX_EVEX_0F387E,
1565   PREFIX_EVEX_0F387F,
1566   PREFIX_EVEX_0F3883,
1567   PREFIX_EVEX_0F3888,
1568   PREFIX_EVEX_0F3889,
1569   PREFIX_EVEX_0F388A,
1570   PREFIX_EVEX_0F388B,
1571   PREFIX_EVEX_0F388D,
1572   PREFIX_EVEX_0F388F,
1573   PREFIX_EVEX_0F3890,
1574   PREFIX_EVEX_0F3891,
1575   PREFIX_EVEX_0F3892,
1576   PREFIX_EVEX_0F3893,
1577   PREFIX_EVEX_0F389A,
1578   PREFIX_EVEX_0F389B,
1579   PREFIX_EVEX_0F38A0,
1580   PREFIX_EVEX_0F38A1,
1581   PREFIX_EVEX_0F38A2,
1582   PREFIX_EVEX_0F38A3,
1583   PREFIX_EVEX_0F38AA,
1584   PREFIX_EVEX_0F38AB,
1585   PREFIX_EVEX_0F38B4,
1586   PREFIX_EVEX_0F38B5,
1587   PREFIX_EVEX_0F38C4,
1588   PREFIX_EVEX_0F38C6_REG_1,
1589   PREFIX_EVEX_0F38C6_REG_2,
1590   PREFIX_EVEX_0F38C6_REG_5,
1591   PREFIX_EVEX_0F38C6_REG_6,
1592   PREFIX_EVEX_0F38C7_REG_1,
1593   PREFIX_EVEX_0F38C7_REG_2,
1594   PREFIX_EVEX_0F38C7_REG_5,
1595   PREFIX_EVEX_0F38C7_REG_6,
1596   PREFIX_EVEX_0F38C8,
1597   PREFIX_EVEX_0F38CA,
1598   PREFIX_EVEX_0F38CB,
1599   PREFIX_EVEX_0F38CC,
1600   PREFIX_EVEX_0F38CD,
1601
1602   PREFIX_EVEX_0F3A00,
1603   PREFIX_EVEX_0F3A01,
1604   PREFIX_EVEX_0F3A03,
1605   PREFIX_EVEX_0F3A05,
1606   PREFIX_EVEX_0F3A08,
1607   PREFIX_EVEX_0F3A09,
1608   PREFIX_EVEX_0F3A0A,
1609   PREFIX_EVEX_0F3A0B,
1610   PREFIX_EVEX_0F3A14,
1611   PREFIX_EVEX_0F3A15,
1612   PREFIX_EVEX_0F3A16,
1613   PREFIX_EVEX_0F3A17,
1614   PREFIX_EVEX_0F3A18,
1615   PREFIX_EVEX_0F3A19,
1616   PREFIX_EVEX_0F3A1A,
1617   PREFIX_EVEX_0F3A1B,
1618   PREFIX_EVEX_0F3A1E,
1619   PREFIX_EVEX_0F3A1F,
1620   PREFIX_EVEX_0F3A20,
1621   PREFIX_EVEX_0F3A21,
1622   PREFIX_EVEX_0F3A22,
1623   PREFIX_EVEX_0F3A23,
1624   PREFIX_EVEX_0F3A25,
1625   PREFIX_EVEX_0F3A26,
1626   PREFIX_EVEX_0F3A27,
1627   PREFIX_EVEX_0F3A38,
1628   PREFIX_EVEX_0F3A39,
1629   PREFIX_EVEX_0F3A3A,
1630   PREFIX_EVEX_0F3A3B,
1631   PREFIX_EVEX_0F3A3E,
1632   PREFIX_EVEX_0F3A3F,
1633   PREFIX_EVEX_0F3A42,
1634   PREFIX_EVEX_0F3A43,
1635   PREFIX_EVEX_0F3A50,
1636   PREFIX_EVEX_0F3A51,
1637   PREFIX_EVEX_0F3A54,
1638   PREFIX_EVEX_0F3A55,
1639   PREFIX_EVEX_0F3A56,
1640   PREFIX_EVEX_0F3A57,
1641   PREFIX_EVEX_0F3A66,
1642   PREFIX_EVEX_0F3A67,
1643   PREFIX_EVEX_0F3A70,
1644   PREFIX_EVEX_0F3A71,
1645   PREFIX_EVEX_0F3A72,
1646   PREFIX_EVEX_0F3A73,
1647 };
1648
1649 enum
1650 {
1651   X86_64_06 = 0,
1652   X86_64_07,
1653   X86_64_0E,
1654   X86_64_16,
1655   X86_64_17,
1656   X86_64_1E,
1657   X86_64_1F,
1658   X86_64_27,
1659   X86_64_2F,
1660   X86_64_37,
1661   X86_64_3F,
1662   X86_64_60,
1663   X86_64_61,
1664   X86_64_62,
1665   X86_64_63,
1666   X86_64_6D,
1667   X86_64_6F,
1668   X86_64_82,
1669   X86_64_9A,
1670   X86_64_C2,
1671   X86_64_C3,
1672   X86_64_C4,
1673   X86_64_C5,
1674   X86_64_CE,
1675   X86_64_D4,
1676   X86_64_D5,
1677   X86_64_E8,
1678   X86_64_E9,
1679   X86_64_EA,
1680   X86_64_0F01_REG_0,
1681   X86_64_0F01_REG_1,
1682   X86_64_0F01_REG_2,
1683   X86_64_0F01_REG_3
1684 };
1685
1686 enum
1687 {
1688   THREE_BYTE_0F38 = 0,
1689   THREE_BYTE_0F3A
1690 };
1691
1692 enum
1693 {
1694   XOP_08 = 0,
1695   XOP_09,
1696   XOP_0A
1697 };
1698
1699 enum
1700 {
1701   VEX_0F = 0,
1702   VEX_0F38,
1703   VEX_0F3A
1704 };
1705
1706 enum
1707 {
1708   EVEX_0F = 0,
1709   EVEX_0F38,
1710   EVEX_0F3A
1711 };
1712
1713 enum
1714 {
1715   VEX_LEN_0F12_P_0_M_0 = 0,
1716   VEX_LEN_0F12_P_0_M_1,
1717 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1718   VEX_LEN_0F13_M_0,
1719   VEX_LEN_0F16_P_0_M_0,
1720   VEX_LEN_0F16_P_0_M_1,
1721 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1722   VEX_LEN_0F17_M_0,
1723   VEX_LEN_0F41_P_0,
1724   VEX_LEN_0F41_P_2,
1725   VEX_LEN_0F42_P_0,
1726   VEX_LEN_0F42_P_2,
1727   VEX_LEN_0F44_P_0,
1728   VEX_LEN_0F44_P_2,
1729   VEX_LEN_0F45_P_0,
1730   VEX_LEN_0F45_P_2,
1731   VEX_LEN_0F46_P_0,
1732   VEX_LEN_0F46_P_2,
1733   VEX_LEN_0F47_P_0,
1734   VEX_LEN_0F47_P_2,
1735   VEX_LEN_0F4A_P_0,
1736   VEX_LEN_0F4A_P_2,
1737   VEX_LEN_0F4B_P_0,
1738   VEX_LEN_0F4B_P_2,
1739   VEX_LEN_0F6E_P_2,
1740   VEX_LEN_0F77_P_0,
1741   VEX_LEN_0F7E_P_1,
1742   VEX_LEN_0F7E_P_2,
1743   VEX_LEN_0F90_P_0,
1744   VEX_LEN_0F90_P_2,
1745   VEX_LEN_0F91_P_0,
1746   VEX_LEN_0F91_P_2,
1747   VEX_LEN_0F92_P_0,
1748   VEX_LEN_0F92_P_2,
1749   VEX_LEN_0F92_P_3,
1750   VEX_LEN_0F93_P_0,
1751   VEX_LEN_0F93_P_2,
1752   VEX_LEN_0F93_P_3,
1753   VEX_LEN_0F98_P_0,
1754   VEX_LEN_0F98_P_2,
1755   VEX_LEN_0F99_P_0,
1756   VEX_LEN_0F99_P_2,
1757   VEX_LEN_0FAE_R_2_M_0,
1758   VEX_LEN_0FAE_R_3_M_0,
1759   VEX_LEN_0FC4_P_2,
1760   VEX_LEN_0FC5_P_2,
1761   VEX_LEN_0FD6_P_2,
1762   VEX_LEN_0FF7_P_2,
1763   VEX_LEN_0F3816_P_2,
1764   VEX_LEN_0F3819_P_2,
1765   VEX_LEN_0F381A_P_2_M_0,
1766   VEX_LEN_0F3836_P_2,
1767   VEX_LEN_0F3841_P_2,
1768   VEX_LEN_0F385A_P_2_M_0,
1769   VEX_LEN_0F38DB_P_2,
1770   VEX_LEN_0F38F2_P_0,
1771   VEX_LEN_0F38F3_R_1_P_0,
1772   VEX_LEN_0F38F3_R_2_P_0,
1773   VEX_LEN_0F38F3_R_3_P_0,
1774   VEX_LEN_0F38F5_P_0,
1775   VEX_LEN_0F38F5_P_1,
1776   VEX_LEN_0F38F5_P_3,
1777   VEX_LEN_0F38F6_P_3,
1778   VEX_LEN_0F38F7_P_0,
1779   VEX_LEN_0F38F7_P_1,
1780   VEX_LEN_0F38F7_P_2,
1781   VEX_LEN_0F38F7_P_3,
1782   VEX_LEN_0F3A00_P_2,
1783   VEX_LEN_0F3A01_P_2,
1784   VEX_LEN_0F3A06_P_2,
1785   VEX_LEN_0F3A14_P_2,
1786   VEX_LEN_0F3A15_P_2,
1787   VEX_LEN_0F3A16_P_2,
1788   VEX_LEN_0F3A17_P_2,
1789   VEX_LEN_0F3A18_P_2,
1790   VEX_LEN_0F3A19_P_2,
1791   VEX_LEN_0F3A20_P_2,
1792   VEX_LEN_0F3A21_P_2,
1793   VEX_LEN_0F3A22_P_2,
1794   VEX_LEN_0F3A30_P_2,
1795   VEX_LEN_0F3A31_P_2,
1796   VEX_LEN_0F3A32_P_2,
1797   VEX_LEN_0F3A33_P_2,
1798   VEX_LEN_0F3A38_P_2,
1799   VEX_LEN_0F3A39_P_2,
1800   VEX_LEN_0F3A41_P_2,
1801   VEX_LEN_0F3A46_P_2,
1802   VEX_LEN_0F3A60_P_2,
1803   VEX_LEN_0F3A61_P_2,
1804   VEX_LEN_0F3A62_P_2,
1805   VEX_LEN_0F3A63_P_2,
1806   VEX_LEN_0F3A6A_P_2,
1807   VEX_LEN_0F3A6B_P_2,
1808   VEX_LEN_0F3A6E_P_2,
1809   VEX_LEN_0F3A6F_P_2,
1810   VEX_LEN_0F3A7A_P_2,
1811   VEX_LEN_0F3A7B_P_2,
1812   VEX_LEN_0F3A7E_P_2,
1813   VEX_LEN_0F3A7F_P_2,
1814   VEX_LEN_0F3ADF_P_2,
1815   VEX_LEN_0F3AF0_P_3,
1816   VEX_LEN_0FXOP_08_CC,
1817   VEX_LEN_0FXOP_08_CD,
1818   VEX_LEN_0FXOP_08_CE,
1819   VEX_LEN_0FXOP_08_CF,
1820   VEX_LEN_0FXOP_08_EC,
1821   VEX_LEN_0FXOP_08_ED,
1822   VEX_LEN_0FXOP_08_EE,
1823   VEX_LEN_0FXOP_08_EF,
1824   VEX_LEN_0FXOP_09_80,
1825   VEX_LEN_0FXOP_09_81
1826 };
1827
1828 enum
1829 {
1830   EVEX_LEN_0F6E_P_2 = 0,
1831   EVEX_LEN_0F7E_P_1,
1832   EVEX_LEN_0F7E_P_2,
1833   EVEX_LEN_0FC4_P_2,
1834   EVEX_LEN_0FC5_P_2,
1835   EVEX_LEN_0FD6_P_2,
1836   EVEX_LEN_0F3816_P_2,
1837   EVEX_LEN_0F3819_P_2_W_0,
1838   EVEX_LEN_0F3819_P_2_W_1,
1839   EVEX_LEN_0F381A_P_2_W_0,
1840   EVEX_LEN_0F381A_P_2_W_1,
1841   EVEX_LEN_0F381B_P_2_W_0,
1842   EVEX_LEN_0F381B_P_2_W_1,
1843   EVEX_LEN_0F3836_P_2,
1844   EVEX_LEN_0F385A_P_2_W_0,
1845   EVEX_LEN_0F385A_P_2_W_1,
1846   EVEX_LEN_0F385B_P_2_W_0,
1847   EVEX_LEN_0F385B_P_2_W_1,
1848   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1849   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1850   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1851   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1852   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1853   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1854   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1855   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1856   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1857   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1858   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1859   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1860   EVEX_LEN_0F3A00_P_2_W_1,
1861   EVEX_LEN_0F3A01_P_2_W_1,
1862   EVEX_LEN_0F3A14_P_2,
1863   EVEX_LEN_0F3A15_P_2,
1864   EVEX_LEN_0F3A16_P_2,
1865   EVEX_LEN_0F3A17_P_2,
1866   EVEX_LEN_0F3A18_P_2_W_0,
1867   EVEX_LEN_0F3A18_P_2_W_1,
1868   EVEX_LEN_0F3A19_P_2_W_0,
1869   EVEX_LEN_0F3A19_P_2_W_1,
1870   EVEX_LEN_0F3A1A_P_2_W_0,
1871   EVEX_LEN_0F3A1A_P_2_W_1,
1872   EVEX_LEN_0F3A1B_P_2_W_0,
1873   EVEX_LEN_0F3A1B_P_2_W_1,
1874   EVEX_LEN_0F3A20_P_2,
1875   EVEX_LEN_0F3A21_P_2_W_0,
1876   EVEX_LEN_0F3A22_P_2,
1877   EVEX_LEN_0F3A23_P_2_W_0,
1878   EVEX_LEN_0F3A23_P_2_W_1,
1879   EVEX_LEN_0F3A38_P_2_W_0,
1880   EVEX_LEN_0F3A38_P_2_W_1,
1881   EVEX_LEN_0F3A39_P_2_W_0,
1882   EVEX_LEN_0F3A39_P_2_W_1,
1883   EVEX_LEN_0F3A3A_P_2_W_0,
1884   EVEX_LEN_0F3A3A_P_2_W_1,
1885   EVEX_LEN_0F3A3B_P_2_W_0,
1886   EVEX_LEN_0F3A3B_P_2_W_1,
1887   EVEX_LEN_0F3A43_P_2_W_0,
1888   EVEX_LEN_0F3A43_P_2_W_1
1889 };
1890
1891 enum
1892 {
1893   VEX_W_0F41_P_0_LEN_1 = 0,
1894   VEX_W_0F41_P_2_LEN_1,
1895   VEX_W_0F42_P_0_LEN_1,
1896   VEX_W_0F42_P_2_LEN_1,
1897   VEX_W_0F44_P_0_LEN_0,
1898   VEX_W_0F44_P_2_LEN_0,
1899   VEX_W_0F45_P_0_LEN_1,
1900   VEX_W_0F45_P_2_LEN_1,
1901   VEX_W_0F46_P_0_LEN_1,
1902   VEX_W_0F46_P_2_LEN_1,
1903   VEX_W_0F47_P_0_LEN_1,
1904   VEX_W_0F47_P_2_LEN_1,
1905   VEX_W_0F4A_P_0_LEN_1,
1906   VEX_W_0F4A_P_2_LEN_1,
1907   VEX_W_0F4B_P_0_LEN_1,
1908   VEX_W_0F4B_P_2_LEN_1,
1909   VEX_W_0F90_P_0_LEN_0,
1910   VEX_W_0F90_P_2_LEN_0,
1911   VEX_W_0F91_P_0_LEN_0,
1912   VEX_W_0F91_P_2_LEN_0,
1913   VEX_W_0F92_P_0_LEN_0,
1914   VEX_W_0F92_P_2_LEN_0,
1915   VEX_W_0F93_P_0_LEN_0,
1916   VEX_W_0F93_P_2_LEN_0,
1917   VEX_W_0F98_P_0_LEN_0,
1918   VEX_W_0F98_P_2_LEN_0,
1919   VEX_W_0F99_P_0_LEN_0,
1920   VEX_W_0F99_P_2_LEN_0,
1921   VEX_W_0F380C_P_2,
1922   VEX_W_0F380D_P_2,
1923   VEX_W_0F380E_P_2,
1924   VEX_W_0F380F_P_2,
1925   VEX_W_0F3813_P_2,
1926   VEX_W_0F3816_P_2,
1927   VEX_W_0F3818_P_2,
1928   VEX_W_0F3819_P_2,
1929   VEX_W_0F381A_P_2_M_0,
1930   VEX_W_0F382C_P_2_M_0,
1931   VEX_W_0F382D_P_2_M_0,
1932   VEX_W_0F382E_P_2_M_0,
1933   VEX_W_0F382F_P_2_M_0,
1934   VEX_W_0F3836_P_2,
1935   VEX_W_0F3846_P_2,
1936   VEX_W_0F3858_P_2,
1937   VEX_W_0F3859_P_2,
1938   VEX_W_0F385A_P_2_M_0,
1939   VEX_W_0F3878_P_2,
1940   VEX_W_0F3879_P_2,
1941   VEX_W_0F38CF_P_2,
1942   VEX_W_0F3A00_P_2,
1943   VEX_W_0F3A01_P_2,
1944   VEX_W_0F3A02_P_2,
1945   VEX_W_0F3A04_P_2,
1946   VEX_W_0F3A05_P_2,
1947   VEX_W_0F3A06_P_2,
1948   VEX_W_0F3A18_P_2,
1949   VEX_W_0F3A19_P_2,
1950   VEX_W_0F3A1D_P_2,
1951   VEX_W_0F3A30_P_2_LEN_0,
1952   VEX_W_0F3A31_P_2_LEN_0,
1953   VEX_W_0F3A32_P_2_LEN_0,
1954   VEX_W_0F3A33_P_2_LEN_0,
1955   VEX_W_0F3A38_P_2,
1956   VEX_W_0F3A39_P_2,
1957   VEX_W_0F3A46_P_2,
1958   VEX_W_0F3A48_P_2,
1959   VEX_W_0F3A49_P_2,
1960   VEX_W_0F3A4A_P_2,
1961   VEX_W_0F3A4B_P_2,
1962   VEX_W_0F3A4C_P_2,
1963   VEX_W_0F3ACE_P_2,
1964   VEX_W_0F3ACF_P_2,
1965
1966   EVEX_W_0F10_P_1,
1967   EVEX_W_0F10_P_3,
1968   EVEX_W_0F11_P_1,
1969   EVEX_W_0F11_P_3,
1970   EVEX_W_0F12_P_0_M_1,
1971   EVEX_W_0F12_P_1,
1972   EVEX_W_0F12_P_3,
1973   EVEX_W_0F16_P_0_M_1,
1974   EVEX_W_0F16_P_1,
1975   EVEX_W_0F2A_P_3,
1976   EVEX_W_0F51_P_1,
1977   EVEX_W_0F51_P_3,
1978   EVEX_W_0F58_P_1,
1979   EVEX_W_0F58_P_3,
1980   EVEX_W_0F59_P_1,
1981   EVEX_W_0F59_P_3,
1982   EVEX_W_0F5A_P_0,
1983   EVEX_W_0F5A_P_1,
1984   EVEX_W_0F5A_P_2,
1985   EVEX_W_0F5A_P_3,
1986   EVEX_W_0F5B_P_0,
1987   EVEX_W_0F5B_P_1,
1988   EVEX_W_0F5B_P_2,
1989   EVEX_W_0F5C_P_1,
1990   EVEX_W_0F5C_P_3,
1991   EVEX_W_0F5D_P_1,
1992   EVEX_W_0F5D_P_3,
1993   EVEX_W_0F5E_P_1,
1994   EVEX_W_0F5E_P_3,
1995   EVEX_W_0F5F_P_1,
1996   EVEX_W_0F5F_P_3,
1997   EVEX_W_0F62_P_2,
1998   EVEX_W_0F66_P_2,
1999   EVEX_W_0F6A_P_2,
2000   EVEX_W_0F6B_P_2,
2001   EVEX_W_0F6C_P_2,
2002   EVEX_W_0F6D_P_2,
2003   EVEX_W_0F6F_P_1,
2004   EVEX_W_0F6F_P_2,
2005   EVEX_W_0F6F_P_3,
2006   EVEX_W_0F70_P_2,
2007   EVEX_W_0F72_R_2_P_2,
2008   EVEX_W_0F72_R_6_P_2,
2009   EVEX_W_0F73_R_2_P_2,
2010   EVEX_W_0F73_R_6_P_2,
2011   EVEX_W_0F76_P_2,
2012   EVEX_W_0F78_P_0,
2013   EVEX_W_0F78_P_2,
2014   EVEX_W_0F79_P_0,
2015   EVEX_W_0F79_P_2,
2016   EVEX_W_0F7A_P_1,
2017   EVEX_W_0F7A_P_2,
2018   EVEX_W_0F7A_P_3,
2019   EVEX_W_0F7B_P_2,
2020   EVEX_W_0F7B_P_3,
2021   EVEX_W_0F7E_P_1,
2022   EVEX_W_0F7F_P_1,
2023   EVEX_W_0F7F_P_2,
2024   EVEX_W_0F7F_P_3,
2025   EVEX_W_0FC2_P_1,
2026   EVEX_W_0FC2_P_3,
2027   EVEX_W_0FD2_P_2,
2028   EVEX_W_0FD3_P_2,
2029   EVEX_W_0FD4_P_2,
2030   EVEX_W_0FD6_P_2,
2031   EVEX_W_0FE6_P_1,
2032   EVEX_W_0FE6_P_2,
2033   EVEX_W_0FE6_P_3,
2034   EVEX_W_0FE7_P_2,
2035   EVEX_W_0FF2_P_2,
2036   EVEX_W_0FF3_P_2,
2037   EVEX_W_0FF4_P_2,
2038   EVEX_W_0FFA_P_2,
2039   EVEX_W_0FFB_P_2,
2040   EVEX_W_0FFE_P_2,
2041   EVEX_W_0F380D_P_2,
2042   EVEX_W_0F3810_P_1,
2043   EVEX_W_0F3810_P_2,
2044   EVEX_W_0F3811_P_1,
2045   EVEX_W_0F3811_P_2,
2046   EVEX_W_0F3812_P_1,
2047   EVEX_W_0F3812_P_2,
2048   EVEX_W_0F3813_P_1,
2049   EVEX_W_0F3813_P_2,
2050   EVEX_W_0F3814_P_1,
2051   EVEX_W_0F3815_P_1,
2052   EVEX_W_0F3819_P_2,
2053   EVEX_W_0F381A_P_2,
2054   EVEX_W_0F381B_P_2,
2055   EVEX_W_0F381E_P_2,
2056   EVEX_W_0F381F_P_2,
2057   EVEX_W_0F3820_P_1,
2058   EVEX_W_0F3821_P_1,
2059   EVEX_W_0F3822_P_1,
2060   EVEX_W_0F3823_P_1,
2061   EVEX_W_0F3824_P_1,
2062   EVEX_W_0F3825_P_1,
2063   EVEX_W_0F3825_P_2,
2064   EVEX_W_0F3826_P_1,
2065   EVEX_W_0F3826_P_2,
2066   EVEX_W_0F3828_P_1,
2067   EVEX_W_0F3828_P_2,
2068   EVEX_W_0F3829_P_1,
2069   EVEX_W_0F3829_P_2,
2070   EVEX_W_0F382A_P_1,
2071   EVEX_W_0F382A_P_2,
2072   EVEX_W_0F382B_P_2,
2073   EVEX_W_0F3830_P_1,
2074   EVEX_W_0F3831_P_1,
2075   EVEX_W_0F3832_P_1,
2076   EVEX_W_0F3833_P_1,
2077   EVEX_W_0F3834_P_1,
2078   EVEX_W_0F3835_P_1,
2079   EVEX_W_0F3835_P_2,
2080   EVEX_W_0F3837_P_2,
2081   EVEX_W_0F3838_P_1,
2082   EVEX_W_0F3839_P_1,
2083   EVEX_W_0F383A_P_1,
2084   EVEX_W_0F3840_P_2,
2085   EVEX_W_0F3852_P_1,
2086   EVEX_W_0F3854_P_2,
2087   EVEX_W_0F3855_P_2,
2088   EVEX_W_0F3859_P_2,
2089   EVEX_W_0F385A_P_2,
2090   EVEX_W_0F385B_P_2,
2091   EVEX_W_0F3862_P_2,
2092   EVEX_W_0F3863_P_2,
2093   EVEX_W_0F3866_P_2,
2094   EVEX_W_0F3868_P_3,
2095   EVEX_W_0F3870_P_2,
2096   EVEX_W_0F3871_P_2,
2097   EVEX_W_0F3872_P_1,
2098   EVEX_W_0F3872_P_2,
2099   EVEX_W_0F3872_P_3,
2100   EVEX_W_0F3873_P_2,
2101   EVEX_W_0F3875_P_2,
2102   EVEX_W_0F387A_P_2,
2103   EVEX_W_0F387B_P_2,
2104   EVEX_W_0F387D_P_2,
2105   EVEX_W_0F3883_P_2,
2106   EVEX_W_0F388D_P_2,
2107   EVEX_W_0F3891_P_2,
2108   EVEX_W_0F3893_P_2,
2109   EVEX_W_0F38A1_P_2,
2110   EVEX_W_0F38A3_P_2,
2111   EVEX_W_0F38C7_R_1_P_2,
2112   EVEX_W_0F38C7_R_2_P_2,
2113   EVEX_W_0F38C7_R_5_P_2,
2114   EVEX_W_0F38C7_R_6_P_2,
2115
2116   EVEX_W_0F3A00_P_2,
2117   EVEX_W_0F3A01_P_2,
2118   EVEX_W_0F3A05_P_2,
2119   EVEX_W_0F3A08_P_2,
2120   EVEX_W_0F3A09_P_2,
2121   EVEX_W_0F3A0A_P_2,
2122   EVEX_W_0F3A0B_P_2,
2123   EVEX_W_0F3A18_P_2,
2124   EVEX_W_0F3A19_P_2,
2125   EVEX_W_0F3A1A_P_2,
2126   EVEX_W_0F3A1B_P_2,
2127   EVEX_W_0F3A21_P_2,
2128   EVEX_W_0F3A23_P_2,
2129   EVEX_W_0F3A38_P_2,
2130   EVEX_W_0F3A39_P_2,
2131   EVEX_W_0F3A3A_P_2,
2132   EVEX_W_0F3A3B_P_2,
2133   EVEX_W_0F3A3E_P_2,
2134   EVEX_W_0F3A3F_P_2,
2135   EVEX_W_0F3A42_P_2,
2136   EVEX_W_0F3A43_P_2,
2137   EVEX_W_0F3A50_P_2,
2138   EVEX_W_0F3A51_P_2,
2139   EVEX_W_0F3A56_P_2,
2140   EVEX_W_0F3A57_P_2,
2141   EVEX_W_0F3A66_P_2,
2142   EVEX_W_0F3A67_P_2,
2143   EVEX_W_0F3A70_P_2,
2144   EVEX_W_0F3A71_P_2,
2145   EVEX_W_0F3A72_P_2,
2146   EVEX_W_0F3A73_P_2,
2147 };
2148
2149 typedef void (*op_rtn) (int bytemode, int sizeflag);
2150
2151 struct dis386 {
2152   const char *name;
2153   struct
2154     {
2155       op_rtn rtn;
2156       int bytemode;
2157     } op[MAX_OPERANDS];
2158   unsigned int prefix_requirement;
2159 };
2160
2161 /* Upper case letters in the instruction names here are macros.
2162    'A' => print 'b' if no register operands or suffix_always is true
2163    'B' => print 'b' if suffix_always is true
2164    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2165           size prefix
2166    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2167           suffix_always is true
2168    'E' => print 'e' if 32-bit form of jcxz
2169    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2170    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2171    'H' => print ",pt" or ",pn" branch hint
2172    'I' unused.
2173    'J' unused.
2174    'K' => print 'd' or 'q' if rex prefix is present.
2175    'L' => print 'l' if suffix_always is true
2176    'M' => print 'r' if intel_mnemonic is false.
2177    'N' => print 'n' if instruction has no wait "prefix"
2178    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2179    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2180           or suffix_always is true.  print 'q' if rex prefix is present.
2181    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2182           is true
2183    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2184    'S' => print 'w', 'l' or 'q' if suffix_always is true
2185    'T' => print 'q' in 64bit mode if instruction has no operand size
2186           prefix and behave as 'P' otherwise
2187    'U' => print 'q' in 64bit mode if instruction has no operand size
2188           prefix and behave as 'Q' otherwise
2189    'V' => print 'q' in 64bit mode if instruction has no operand size
2190           prefix and behave as 'S' otherwise
2191    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2192    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2193    'Y' unused.
2194    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2195    '!' => change condition from true to false or from false to true.
2196    '%' => add 1 upper case letter to the macro.
2197    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2198           prefix or suffix_always is true (lcall/ljmp).
2199    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2200           on operand size prefix.
2201    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2202           has no operand size prefix for AMD64 ISA, behave as 'P'
2203           otherwise
2204
2205    2 upper case letter macros:
2206    "XY" => print 'x' or 'y' if suffix_always is true or no register
2207            operands and no broadcast.
2208    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2209            register operands and no broadcast.
2210    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2211    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2212            operand or no operand at all in 64bit mode, or if suffix_always
2213            is true.
2214    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2215    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2216    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2217    "LW" => print 'd', 'q' depending on the VEX.W bit
2218    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2219            an operand size prefix, or suffix_always is true.  print
2220            'q' if rex prefix is present.
2221
2222    Many of the above letters print nothing in Intel mode.  See "putop"
2223    for the details.
2224
2225    Braces '{' and '}', and vertical bars '|', indicate alternative
2226    mnemonic strings for AT&T and Intel.  */
2227
2228 static const struct dis386 dis386[] = {
2229   /* 00 */
2230   { "addB",             { Ebh1, Gb }, 0 },
2231   { "addS",             { Evh1, Gv }, 0 },
2232   { "addB",             { Gb, EbS }, 0 },
2233   { "addS",             { Gv, EvS }, 0 },
2234   { "addB",             { AL, Ib }, 0 },
2235   { "addS",             { eAX, Iv }, 0 },
2236   { X86_64_TABLE (X86_64_06) },
2237   { X86_64_TABLE (X86_64_07) },
2238   /* 08 */
2239   { "orB",              { Ebh1, Gb }, 0 },
2240   { "orS",              { Evh1, Gv }, 0 },
2241   { "orB",              { Gb, EbS }, 0 },
2242   { "orS",              { Gv, EvS }, 0 },
2243   { "orB",              { AL, Ib }, 0 },
2244   { "orS",              { eAX, Iv }, 0 },
2245   { X86_64_TABLE (X86_64_0E) },
2246   { Bad_Opcode },       /* 0x0f extended opcode escape */
2247   /* 10 */
2248   { "adcB",             { Ebh1, Gb }, 0 },
2249   { "adcS",             { Evh1, Gv }, 0 },
2250   { "adcB",             { Gb, EbS }, 0 },
2251   { "adcS",             { Gv, EvS }, 0 },
2252   { "adcB",             { AL, Ib }, 0 },
2253   { "adcS",             { eAX, Iv }, 0 },
2254   { X86_64_TABLE (X86_64_16) },
2255   { X86_64_TABLE (X86_64_17) },
2256   /* 18 */
2257   { "sbbB",             { Ebh1, Gb }, 0 },
2258   { "sbbS",             { Evh1, Gv }, 0 },
2259   { "sbbB",             { Gb, EbS }, 0 },
2260   { "sbbS",             { Gv, EvS }, 0 },
2261   { "sbbB",             { AL, Ib }, 0 },
2262   { "sbbS",             { eAX, Iv }, 0 },
2263   { X86_64_TABLE (X86_64_1E) },
2264   { X86_64_TABLE (X86_64_1F) },
2265   /* 20 */
2266   { "andB",             { Ebh1, Gb }, 0 },
2267   { "andS",             { Evh1, Gv }, 0 },
2268   { "andB",             { Gb, EbS }, 0 },
2269   { "andS",             { Gv, EvS }, 0 },
2270   { "andB",             { AL, Ib }, 0 },
2271   { "andS",             { eAX, Iv }, 0 },
2272   { Bad_Opcode },       /* SEG ES prefix */
2273   { X86_64_TABLE (X86_64_27) },
2274   /* 28 */
2275   { "subB",             { Ebh1, Gb }, 0 },
2276   { "subS",             { Evh1, Gv }, 0 },
2277   { "subB",             { Gb, EbS }, 0 },
2278   { "subS",             { Gv, EvS }, 0 },
2279   { "subB",             { AL, Ib }, 0 },
2280   { "subS",             { eAX, Iv }, 0 },
2281   { Bad_Opcode },       /* SEG CS prefix */
2282   { X86_64_TABLE (X86_64_2F) },
2283   /* 30 */
2284   { "xorB",             { Ebh1, Gb }, 0 },
2285   { "xorS",             { Evh1, Gv }, 0 },
2286   { "xorB",             { Gb, EbS }, 0 },
2287   { "xorS",             { Gv, EvS }, 0 },
2288   { "xorB",             { AL, Ib }, 0 },
2289   { "xorS",             { eAX, Iv }, 0 },
2290   { Bad_Opcode },       /* SEG SS prefix */
2291   { X86_64_TABLE (X86_64_37) },
2292   /* 38 */
2293   { "cmpB",             { Eb, Gb }, 0 },
2294   { "cmpS",             { Ev, Gv }, 0 },
2295   { "cmpB",             { Gb, EbS }, 0 },
2296   { "cmpS",             { Gv, EvS }, 0 },
2297   { "cmpB",             { AL, Ib }, 0 },
2298   { "cmpS",             { eAX, Iv }, 0 },
2299   { Bad_Opcode },       /* SEG DS prefix */
2300   { X86_64_TABLE (X86_64_3F) },
2301   /* 40 */
2302   { "inc{S|}",          { RMeAX }, 0 },
2303   { "inc{S|}",          { RMeCX }, 0 },
2304   { "inc{S|}",          { RMeDX }, 0 },
2305   { "inc{S|}",          { RMeBX }, 0 },
2306   { "inc{S|}",          { RMeSP }, 0 },
2307   { "inc{S|}",          { RMeBP }, 0 },
2308   { "inc{S|}",          { RMeSI }, 0 },
2309   { "inc{S|}",          { RMeDI }, 0 },
2310   /* 48 */
2311   { "dec{S|}",          { RMeAX }, 0 },
2312   { "dec{S|}",          { RMeCX }, 0 },
2313   { "dec{S|}",          { RMeDX }, 0 },
2314   { "dec{S|}",          { RMeBX }, 0 },
2315   { "dec{S|}",          { RMeSP }, 0 },
2316   { "dec{S|}",          { RMeBP }, 0 },
2317   { "dec{S|}",          { RMeSI }, 0 },
2318   { "dec{S|}",          { RMeDI }, 0 },
2319   /* 50 */
2320   { "pushV",            { RMrAX }, 0 },
2321   { "pushV",            { RMrCX }, 0 },
2322   { "pushV",            { RMrDX }, 0 },
2323   { "pushV",            { RMrBX }, 0 },
2324   { "pushV",            { RMrSP }, 0 },
2325   { "pushV",            { RMrBP }, 0 },
2326   { "pushV",            { RMrSI }, 0 },
2327   { "pushV",            { RMrDI }, 0 },
2328   /* 58 */
2329   { "popV",             { RMrAX }, 0 },
2330   { "popV",             { RMrCX }, 0 },
2331   { "popV",             { RMrDX }, 0 },
2332   { "popV",             { RMrBX }, 0 },
2333   { "popV",             { RMrSP }, 0 },
2334   { "popV",             { RMrBP }, 0 },
2335   { "popV",             { RMrSI }, 0 },
2336   { "popV",             { RMrDI }, 0 },
2337   /* 60 */
2338   { X86_64_TABLE (X86_64_60) },
2339   { X86_64_TABLE (X86_64_61) },
2340   { X86_64_TABLE (X86_64_62) },
2341   { X86_64_TABLE (X86_64_63) },
2342   { Bad_Opcode },       /* seg fs */
2343   { Bad_Opcode },       /* seg gs */
2344   { Bad_Opcode },       /* op size prefix */
2345   { Bad_Opcode },       /* adr size prefix */
2346   /* 68 */
2347   { "pushT",            { sIv }, 0 },
2348   { "imulS",            { Gv, Ev, Iv }, 0 },
2349   { "pushT",            { sIbT }, 0 },
2350   { "imulS",            { Gv, Ev, sIb }, 0 },
2351   { "ins{b|}",          { Ybr, indirDX }, 0 },
2352   { X86_64_TABLE (X86_64_6D) },
2353   { "outs{b|}",         { indirDXr, Xb }, 0 },
2354   { X86_64_TABLE (X86_64_6F) },
2355   /* 70 */
2356   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2357   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2358   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2359   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2360   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2361   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2362   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2363   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2364   /* 78 */
2365   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2366   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2367   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2368   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2369   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2370   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2371   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2372   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2373   /* 80 */
2374   { REG_TABLE (REG_80) },
2375   { REG_TABLE (REG_81) },
2376   { X86_64_TABLE (X86_64_82) },
2377   { REG_TABLE (REG_83) },
2378   { "testB",            { Eb, Gb }, 0 },
2379   { "testS",            { Ev, Gv }, 0 },
2380   { "xchgB",            { Ebh2, Gb }, 0 },
2381   { "xchgS",            { Evh2, Gv }, 0 },
2382   /* 88 */
2383   { "movB",             { Ebh3, Gb }, 0 },
2384   { "movS",             { Evh3, Gv }, 0 },
2385   { "movB",             { Gb, EbS }, 0 },
2386   { "movS",             { Gv, EvS }, 0 },
2387   { "movD",             { Sv, Sw }, 0 },
2388   { MOD_TABLE (MOD_8D) },
2389   { "movD",             { Sw, Sv }, 0 },
2390   { REG_TABLE (REG_8F) },
2391   /* 90 */
2392   { PREFIX_TABLE (PREFIX_90) },
2393   { "xchgS",            { RMeCX, eAX }, 0 },
2394   { "xchgS",            { RMeDX, eAX }, 0 },
2395   { "xchgS",            { RMeBX, eAX }, 0 },
2396   { "xchgS",            { RMeSP, eAX }, 0 },
2397   { "xchgS",            { RMeBP, eAX }, 0 },
2398   { "xchgS",            { RMeSI, eAX }, 0 },
2399   { "xchgS",            { RMeDI, eAX }, 0 },
2400   /* 98 */
2401   { "cW{t|}R",          { XX }, 0 },
2402   { "cR{t|}O",          { XX }, 0 },
2403   { X86_64_TABLE (X86_64_9A) },
2404   { Bad_Opcode },       /* fwait */
2405   { "pushfT",           { XX }, 0 },
2406   { "popfT",            { XX }, 0 },
2407   { "sahf",             { XX }, 0 },
2408   { "lahf",             { XX }, 0 },
2409   /* a0 */
2410   { "mov%LB",           { AL, Ob }, 0 },
2411   { "mov%LS",           { eAX, Ov }, 0 },
2412   { "mov%LB",           { Ob, AL }, 0 },
2413   { "mov%LS",           { Ov, eAX }, 0 },
2414   { "movs{b|}",         { Ybr, Xb }, 0 },
2415   { "movs{R|}",         { Yvr, Xv }, 0 },
2416   { "cmps{b|}",         { Xb, Yb }, 0 },
2417   { "cmps{R|}",         { Xv, Yv }, 0 },
2418   /* a8 */
2419   { "testB",            { AL, Ib }, 0 },
2420   { "testS",            { eAX, Iv }, 0 },
2421   { "stosB",            { Ybr, AL }, 0 },
2422   { "stosS",            { Yvr, eAX }, 0 },
2423   { "lodsB",            { ALr, Xb }, 0 },
2424   { "lodsS",            { eAXr, Xv }, 0 },
2425   { "scasB",            { AL, Yb }, 0 },
2426   { "scasS",            { eAX, Yv }, 0 },
2427   /* b0 */
2428   { "movB",             { RMAL, Ib }, 0 },
2429   { "movB",             { RMCL, Ib }, 0 },
2430   { "movB",             { RMDL, Ib }, 0 },
2431   { "movB",             { RMBL, Ib }, 0 },
2432   { "movB",             { RMAH, Ib }, 0 },
2433   { "movB",             { RMCH, Ib }, 0 },
2434   { "movB",             { RMDH, Ib }, 0 },
2435   { "movB",             { RMBH, Ib }, 0 },
2436   /* b8 */
2437   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2438   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2439   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2440   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2441   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2442   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2443   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2444   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2445   /* c0 */
2446   { REG_TABLE (REG_C0) },
2447   { REG_TABLE (REG_C1) },
2448   { X86_64_TABLE (X86_64_C2) },
2449   { X86_64_TABLE (X86_64_C3) },
2450   { X86_64_TABLE (X86_64_C4) },
2451   { X86_64_TABLE (X86_64_C5) },
2452   { REG_TABLE (REG_C6) },
2453   { REG_TABLE (REG_C7) },
2454   /* c8 */
2455   { "enterT",           { Iw, Ib }, 0 },
2456   { "leaveT",           { XX }, 0 },
2457   { "{l|}ret{|f}P",     { Iw }, 0 },
2458   { "{l|}ret{|f}P",     { XX }, 0 },
2459   { "int3",             { XX }, 0 },
2460   { "int",              { Ib }, 0 },
2461   { X86_64_TABLE (X86_64_CE) },
2462   { "iret%LP",          { XX }, 0 },
2463   /* d0 */
2464   { REG_TABLE (REG_D0) },
2465   { REG_TABLE (REG_D1) },
2466   { REG_TABLE (REG_D2) },
2467   { REG_TABLE (REG_D3) },
2468   { X86_64_TABLE (X86_64_D4) },
2469   { X86_64_TABLE (X86_64_D5) },
2470   { Bad_Opcode },
2471   { "xlat",             { DSBX }, 0 },
2472   /* d8 */
2473   { FLOAT },
2474   { FLOAT },
2475   { FLOAT },
2476   { FLOAT },
2477   { FLOAT },
2478   { FLOAT },
2479   { FLOAT },
2480   { FLOAT },
2481   /* e0 */
2482   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2483   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2484   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2485   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2486   { "inB",              { AL, Ib }, 0 },
2487   { "inG",              { zAX, Ib }, 0 },
2488   { "outB",             { Ib, AL }, 0 },
2489   { "outG",             { Ib, zAX }, 0 },
2490   /* e8 */
2491   { X86_64_TABLE (X86_64_E8) },
2492   { X86_64_TABLE (X86_64_E9) },
2493   { X86_64_TABLE (X86_64_EA) },
2494   { "jmp",              { Jb, BND }, 0 },
2495   { "inB",              { AL, indirDX }, 0 },
2496   { "inG",              { zAX, indirDX }, 0 },
2497   { "outB",             { indirDX, AL }, 0 },
2498   { "outG",             { indirDX, zAX }, 0 },
2499   /* f0 */
2500   { Bad_Opcode },       /* lock prefix */
2501   { "icebp",            { XX }, 0 },
2502   { Bad_Opcode },       /* repne */
2503   { Bad_Opcode },       /* repz */
2504   { "hlt",              { XX }, 0 },
2505   { "cmc",              { XX }, 0 },
2506   { REG_TABLE (REG_F6) },
2507   { REG_TABLE (REG_F7) },
2508   /* f8 */
2509   { "clc",              { XX }, 0 },
2510   { "stc",              { XX }, 0 },
2511   { "cli",              { XX }, 0 },
2512   { "sti",              { XX }, 0 },
2513   { "cld",              { XX }, 0 },
2514   { "std",              { XX }, 0 },
2515   { REG_TABLE (REG_FE) },
2516   { REG_TABLE (REG_FF) },
2517 };
2518
2519 static const struct dis386 dis386_twobyte[] = {
2520   /* 00 */
2521   { REG_TABLE (REG_0F00 ) },
2522   { REG_TABLE (REG_0F01 ) },
2523   { "larS",             { Gv, Ew }, 0 },
2524   { "lslS",             { Gv, Ew }, 0 },
2525   { Bad_Opcode },
2526   { "syscall",          { XX }, 0 },
2527   { "clts",             { XX }, 0 },
2528   { "sysret%LQ",                { XX }, 0 },
2529   /* 08 */
2530   { "invd",             { XX }, 0 },
2531   { PREFIX_TABLE (PREFIX_0F09) },
2532   { Bad_Opcode },
2533   { "ud2",              { XX }, 0 },
2534   { Bad_Opcode },
2535   { REG_TABLE (REG_0F0D) },
2536   { "femms",            { XX }, 0 },
2537   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2538   /* 10 */
2539   { PREFIX_TABLE (PREFIX_0F10) },
2540   { PREFIX_TABLE (PREFIX_0F11) },
2541   { PREFIX_TABLE (PREFIX_0F12) },
2542   { MOD_TABLE (MOD_0F13) },
2543   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2544   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2545   { PREFIX_TABLE (PREFIX_0F16) },
2546   { MOD_TABLE (MOD_0F17) },
2547   /* 18 */
2548   { REG_TABLE (REG_0F18) },
2549   { "nopQ",             { Ev }, 0 },
2550   { PREFIX_TABLE (PREFIX_0F1A) },
2551   { PREFIX_TABLE (PREFIX_0F1B) },
2552   { PREFIX_TABLE (PREFIX_0F1C) },
2553   { "nopQ",             { Ev }, 0 },
2554   { PREFIX_TABLE (PREFIX_0F1E) },
2555   { "nopQ",             { Ev }, 0 },
2556   /* 20 */
2557   { "movZ",             { Rm, Cm }, 0 },
2558   { "movZ",             { Rm, Dm }, 0 },
2559   { "movZ",             { Cm, Rm }, 0 },
2560   { "movZ",             { Dm, Rm }, 0 },
2561   { MOD_TABLE (MOD_0F24) },
2562   { Bad_Opcode },
2563   { MOD_TABLE (MOD_0F26) },
2564   { Bad_Opcode },
2565   /* 28 */
2566   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2567   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2568   { PREFIX_TABLE (PREFIX_0F2A) },
2569   { PREFIX_TABLE (PREFIX_0F2B) },
2570   { PREFIX_TABLE (PREFIX_0F2C) },
2571   { PREFIX_TABLE (PREFIX_0F2D) },
2572   { PREFIX_TABLE (PREFIX_0F2E) },
2573   { PREFIX_TABLE (PREFIX_0F2F) },
2574   /* 30 */
2575   { "wrmsr",            { XX }, 0 },
2576   { "rdtsc",            { XX }, 0 },
2577   { "rdmsr",            { XX }, 0 },
2578   { "rdpmc",            { XX }, 0 },
2579   { "sysenter",         { SEP }, 0 },
2580   { "sysexit",          { SEP }, 0 },
2581   { Bad_Opcode },
2582   { "getsec",           { XX }, 0 },
2583   /* 38 */
2584   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2585   { Bad_Opcode },
2586   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2587   { Bad_Opcode },
2588   { Bad_Opcode },
2589   { Bad_Opcode },
2590   { Bad_Opcode },
2591   { Bad_Opcode },
2592   /* 40 */
2593   { "cmovoS",           { Gv, Ev }, 0 },
2594   { "cmovnoS",          { Gv, Ev }, 0 },
2595   { "cmovbS",           { Gv, Ev }, 0 },
2596   { "cmovaeS",          { Gv, Ev }, 0 },
2597   { "cmoveS",           { Gv, Ev }, 0 },
2598   { "cmovneS",          { Gv, Ev }, 0 },
2599   { "cmovbeS",          { Gv, Ev }, 0 },
2600   { "cmovaS",           { Gv, Ev }, 0 },
2601   /* 48 */
2602   { "cmovsS",           { Gv, Ev }, 0 },
2603   { "cmovnsS",          { Gv, Ev }, 0 },
2604   { "cmovpS",           { Gv, Ev }, 0 },
2605   { "cmovnpS",          { Gv, Ev }, 0 },
2606   { "cmovlS",           { Gv, Ev }, 0 },
2607   { "cmovgeS",          { Gv, Ev }, 0 },
2608   { "cmovleS",          { Gv, Ev }, 0 },
2609   { "cmovgS",           { Gv, Ev }, 0 },
2610   /* 50 */
2611   { MOD_TABLE (MOD_0F50) },
2612   { PREFIX_TABLE (PREFIX_0F51) },
2613   { PREFIX_TABLE (PREFIX_0F52) },
2614   { PREFIX_TABLE (PREFIX_0F53) },
2615   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2616   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2617   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2618   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2619   /* 58 */
2620   { PREFIX_TABLE (PREFIX_0F58) },
2621   { PREFIX_TABLE (PREFIX_0F59) },
2622   { PREFIX_TABLE (PREFIX_0F5A) },
2623   { PREFIX_TABLE (PREFIX_0F5B) },
2624   { PREFIX_TABLE (PREFIX_0F5C) },
2625   { PREFIX_TABLE (PREFIX_0F5D) },
2626   { PREFIX_TABLE (PREFIX_0F5E) },
2627   { PREFIX_TABLE (PREFIX_0F5F) },
2628   /* 60 */
2629   { PREFIX_TABLE (PREFIX_0F60) },
2630   { PREFIX_TABLE (PREFIX_0F61) },
2631   { PREFIX_TABLE (PREFIX_0F62) },
2632   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2633   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2634   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2635   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2636   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2637   /* 68 */
2638   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2639   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2640   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2641   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2642   { PREFIX_TABLE (PREFIX_0F6C) },
2643   { PREFIX_TABLE (PREFIX_0F6D) },
2644   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2645   { PREFIX_TABLE (PREFIX_0F6F) },
2646   /* 70 */
2647   { PREFIX_TABLE (PREFIX_0F70) },
2648   { REG_TABLE (REG_0F71) },
2649   { REG_TABLE (REG_0F72) },
2650   { REG_TABLE (REG_0F73) },
2651   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2652   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2653   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2654   { "emms",             { XX }, PREFIX_OPCODE },
2655   /* 78 */
2656   { PREFIX_TABLE (PREFIX_0F78) },
2657   { PREFIX_TABLE (PREFIX_0F79) },
2658   { Bad_Opcode },
2659   { Bad_Opcode },
2660   { PREFIX_TABLE (PREFIX_0F7C) },
2661   { PREFIX_TABLE (PREFIX_0F7D) },
2662   { PREFIX_TABLE (PREFIX_0F7E) },
2663   { PREFIX_TABLE (PREFIX_0F7F) },
2664   /* 80 */
2665   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2666   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2667   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2668   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2669   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2670   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2671   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2672   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2673   /* 88 */
2674   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2675   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2676   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2677   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2678   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2679   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2680   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2681   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2682   /* 90 */
2683   { "seto",             { Eb }, 0 },
2684   { "setno",            { Eb }, 0 },
2685   { "setb",             { Eb }, 0 },
2686   { "setae",            { Eb }, 0 },
2687   { "sete",             { Eb }, 0 },
2688   { "setne",            { Eb }, 0 },
2689   { "setbe",            { Eb }, 0 },
2690   { "seta",             { Eb }, 0 },
2691   /* 98 */
2692   { "sets",             { Eb }, 0 },
2693   { "setns",            { Eb }, 0 },
2694   { "setp",             { Eb }, 0 },
2695   { "setnp",            { Eb }, 0 },
2696   { "setl",             { Eb }, 0 },
2697   { "setge",            { Eb }, 0 },
2698   { "setle",            { Eb }, 0 },
2699   { "setg",             { Eb }, 0 },
2700   /* a0 */
2701   { "pushT",            { fs }, 0 },
2702   { "popT",             { fs }, 0 },
2703   { "cpuid",            { XX }, 0 },
2704   { "btS",              { Ev, Gv }, 0 },
2705   { "shldS",            { Ev, Gv, Ib }, 0 },
2706   { "shldS",            { Ev, Gv, CL }, 0 },
2707   { REG_TABLE (REG_0FA6) },
2708   { REG_TABLE (REG_0FA7) },
2709   /* a8 */
2710   { "pushT",            { gs }, 0 },
2711   { "popT",             { gs }, 0 },
2712   { "rsm",              { XX }, 0 },
2713   { "btsS",             { Evh1, Gv }, 0 },
2714   { "shrdS",            { Ev, Gv, Ib }, 0 },
2715   { "shrdS",            { Ev, Gv, CL }, 0 },
2716   { REG_TABLE (REG_0FAE) },
2717   { "imulS",            { Gv, Ev }, 0 },
2718   /* b0 */
2719   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2720   { "cmpxchgS",         { Evh1, Gv }, 0 },
2721   { MOD_TABLE (MOD_0FB2) },
2722   { "btrS",             { Evh1, Gv }, 0 },
2723   { MOD_TABLE (MOD_0FB4) },
2724   { MOD_TABLE (MOD_0FB5) },
2725   { "movz{bR|x}",       { Gv, Eb }, 0 },
2726   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2727   /* b8 */
2728   { PREFIX_TABLE (PREFIX_0FB8) },
2729   { "ud1S",             { Gv, Ev }, 0 },
2730   { REG_TABLE (REG_0FBA) },
2731   { "btcS",             { Evh1, Gv }, 0 },
2732   { PREFIX_TABLE (PREFIX_0FBC) },
2733   { PREFIX_TABLE (PREFIX_0FBD) },
2734   { "movs{bR|x}",       { Gv, Eb }, 0 },
2735   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2736   /* c0 */
2737   { "xaddB",            { Ebh1, Gb }, 0 },
2738   { "xaddS",            { Evh1, Gv }, 0 },
2739   { PREFIX_TABLE (PREFIX_0FC2) },
2740   { MOD_TABLE (MOD_0FC3) },
2741   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2742   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2743   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2744   { REG_TABLE (REG_0FC7) },
2745   /* c8 */
2746   { "bswap",            { RMeAX }, 0 },
2747   { "bswap",            { RMeCX }, 0 },
2748   { "bswap",            { RMeDX }, 0 },
2749   { "bswap",            { RMeBX }, 0 },
2750   { "bswap",            { RMeSP }, 0 },
2751   { "bswap",            { RMeBP }, 0 },
2752   { "bswap",            { RMeSI }, 0 },
2753   { "bswap",            { RMeDI }, 0 },
2754   /* d0 */
2755   { PREFIX_TABLE (PREFIX_0FD0) },
2756   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2757   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2758   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2759   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2760   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2761   { PREFIX_TABLE (PREFIX_0FD6) },
2762   { MOD_TABLE (MOD_0FD7) },
2763   /* d8 */
2764   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2765   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2766   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2767   { "pand",             { MX, EM }, PREFIX_OPCODE },
2768   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2769   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2770   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2771   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2772   /* e0 */
2773   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2774   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2775   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2776   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2777   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2778   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2779   { PREFIX_TABLE (PREFIX_0FE6) },
2780   { PREFIX_TABLE (PREFIX_0FE7) },
2781   /* e8 */
2782   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2783   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2784   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2785   { "por",              { MX, EM }, PREFIX_OPCODE },
2786   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2787   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2788   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2789   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2790   /* f0 */
2791   { PREFIX_TABLE (PREFIX_0FF0) },
2792   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2793   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2794   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2795   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2796   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2797   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2798   { PREFIX_TABLE (PREFIX_0FF7) },
2799   /* f8 */
2800   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2801   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2802   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2803   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2804   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2805   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2806   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2807   { "ud0S",             { Gv, Ev }, 0 },
2808 };
2809
2810 static const unsigned char onebyte_has_modrm[256] = {
2811   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2812   /*       -------------------------------        */
2813   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2814   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2815   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2816   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2817   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2818   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2819   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2820   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2821   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2822   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2823   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2824   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2825   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2826   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2827   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2828   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2829   /*       -------------------------------        */
2830   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2831 };
2832
2833 static const unsigned char twobyte_has_modrm[256] = {
2834   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2835   /*       -------------------------------        */
2836   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2837   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2838   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2839   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2840   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2841   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2842   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2843   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2844   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2845   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2846   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2847   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2848   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2849   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2850   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2851   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2852   /*       -------------------------------        */
2853   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2854 };
2855
2856 static char obuf[100];
2857 static char *obufp;
2858 static char *mnemonicendp;
2859 static char scratchbuf[100];
2860 static unsigned char *start_codep;
2861 static unsigned char *insn_codep;
2862 static unsigned char *codep;
2863 static unsigned char *end_codep;
2864 static int last_lock_prefix;
2865 static int last_repz_prefix;
2866 static int last_repnz_prefix;
2867 static int last_data_prefix;
2868 static int last_addr_prefix;
2869 static int last_rex_prefix;
2870 static int last_seg_prefix;
2871 static int fwait_prefix;
2872 /* The active segment register prefix.  */
2873 static int active_seg_prefix;
2874 #define MAX_CODE_LENGTH 15
2875 /* We can up to 14 prefixes since the maximum instruction length is
2876    15bytes.  */
2877 static int all_prefixes[MAX_CODE_LENGTH - 1];
2878 static disassemble_info *the_info;
2879 static struct
2880   {
2881     int mod;
2882     int reg;
2883     int rm;
2884   }
2885 modrm;
2886 static unsigned char need_modrm;
2887 static struct
2888   {
2889     int scale;
2890     int index;
2891     int base;
2892   }
2893 sib;
2894 static struct
2895   {
2896     int register_specifier;
2897     int length;
2898     int prefix;
2899     int w;
2900     int evex;
2901     int r;
2902     int v;
2903     int mask_register_specifier;
2904     int zeroing;
2905     int ll;
2906     int b;
2907   }
2908 vex;
2909 static unsigned char need_vex;
2910 static unsigned char need_vex_reg;
2911 static unsigned char vex_w_done;
2912
2913 struct op
2914   {
2915     const char *name;
2916     unsigned int len;
2917   };
2918
2919 /* If we are accessing mod/rm/reg without need_modrm set, then the
2920    values are stale.  Hitting this abort likely indicates that you
2921    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2922 #define MODRM_CHECK  if (!need_modrm) abort ()
2923
2924 static const char **names64;
2925 static const char **names32;
2926 static const char **names16;
2927 static const char **names8;
2928 static const char **names8rex;
2929 static const char **names_seg;
2930 static const char *index64;
2931 static const char *index32;
2932 static const char **index16;
2933 static const char **names_bnd;
2934
2935 static const char *intel_names64[] = {
2936   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2937   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2938 };
2939 static const char *intel_names32[] = {
2940   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2941   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2942 };
2943 static const char *intel_names16[] = {
2944   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2945   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2946 };
2947 static const char *intel_names8[] = {
2948   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2949 };
2950 static const char *intel_names8rex[] = {
2951   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2952   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2953 };
2954 static const char *intel_names_seg[] = {
2955   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2956 };
2957 static const char *intel_index64 = "riz";
2958 static const char *intel_index32 = "eiz";
2959 static const char *intel_index16[] = {
2960   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2961 };
2962
2963 static const char *att_names64[] = {
2964   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2965   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2966 };
2967 static const char *att_names32[] = {
2968   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2969   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2970 };
2971 static const char *att_names16[] = {
2972   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2973   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2974 };
2975 static const char *att_names8[] = {
2976   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2977 };
2978 static const char *att_names8rex[] = {
2979   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2980   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2981 };
2982 static const char *att_names_seg[] = {
2983   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2984 };
2985 static const char *att_index64 = "%riz";
2986 static const char *att_index32 = "%eiz";
2987 static const char *att_index16[] = {
2988   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2989 };
2990
2991 static const char **names_mm;
2992 static const char *intel_names_mm[] = {
2993   "mm0", "mm1", "mm2", "mm3",
2994   "mm4", "mm5", "mm6", "mm7"
2995 };
2996 static const char *att_names_mm[] = {
2997   "%mm0", "%mm1", "%mm2", "%mm3",
2998   "%mm4", "%mm5", "%mm6", "%mm7"
2999 };
3000
3001 static const char *intel_names_bnd[] = {
3002   "bnd0", "bnd1", "bnd2", "bnd3"
3003 };
3004
3005 static const char *att_names_bnd[] = {
3006   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3007 };
3008
3009 static const char **names_xmm;
3010 static const char *intel_names_xmm[] = {
3011   "xmm0", "xmm1", "xmm2", "xmm3",
3012   "xmm4", "xmm5", "xmm6", "xmm7",
3013   "xmm8", "xmm9", "xmm10", "xmm11",
3014   "xmm12", "xmm13", "xmm14", "xmm15",
3015   "xmm16", "xmm17", "xmm18", "xmm19",
3016   "xmm20", "xmm21", "xmm22", "xmm23",
3017   "xmm24", "xmm25", "xmm26", "xmm27",
3018   "xmm28", "xmm29", "xmm30", "xmm31"
3019 };
3020 static const char *att_names_xmm[] = {
3021   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3022   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3023   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3024   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3025   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3026   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3027   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3028   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3029 };
3030
3031 static const char **names_ymm;
3032 static const char *intel_names_ymm[] = {
3033   "ymm0", "ymm1", "ymm2", "ymm3",
3034   "ymm4", "ymm5", "ymm6", "ymm7",
3035   "ymm8", "ymm9", "ymm10", "ymm11",
3036   "ymm12", "ymm13", "ymm14", "ymm15",
3037   "ymm16", "ymm17", "ymm18", "ymm19",
3038   "ymm20", "ymm21", "ymm22", "ymm23",
3039   "ymm24", "ymm25", "ymm26", "ymm27",
3040   "ymm28", "ymm29", "ymm30", "ymm31"
3041 };
3042 static const char *att_names_ymm[] = {
3043   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3044   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3045   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3046   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3047   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3048   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3049   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3050   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3051 };
3052
3053 static const char **names_zmm;
3054 static const char *intel_names_zmm[] = {
3055   "zmm0", "zmm1", "zmm2", "zmm3",
3056   "zmm4", "zmm5", "zmm6", "zmm7",
3057   "zmm8", "zmm9", "zmm10", "zmm11",
3058   "zmm12", "zmm13", "zmm14", "zmm15",
3059   "zmm16", "zmm17", "zmm18", "zmm19",
3060   "zmm20", "zmm21", "zmm22", "zmm23",
3061   "zmm24", "zmm25", "zmm26", "zmm27",
3062   "zmm28", "zmm29", "zmm30", "zmm31"
3063 };
3064 static const char *att_names_zmm[] = {
3065   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3066   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3067   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3068   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3069   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3070   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3071   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3072   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3073 };
3074
3075 static const char **names_mask;
3076 static const char *intel_names_mask[] = {
3077   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3078 };
3079 static const char *att_names_mask[] = {
3080   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3081 };
3082
3083 static const char *names_rounding[] =
3084 {
3085   "{rn-sae}",
3086   "{rd-sae}",
3087   "{ru-sae}",
3088   "{rz-sae}"
3089 };
3090
3091 static const struct dis386 reg_table[][8] = {
3092   /* REG_80 */
3093   {
3094     { "addA",   { Ebh1, Ib }, 0 },
3095     { "orA",    { Ebh1, Ib }, 0 },
3096     { "adcA",   { Ebh1, Ib }, 0 },
3097     { "sbbA",   { Ebh1, Ib }, 0 },
3098     { "andA",   { Ebh1, Ib }, 0 },
3099     { "subA",   { Ebh1, Ib }, 0 },
3100     { "xorA",   { Ebh1, Ib }, 0 },
3101     { "cmpA",   { Eb, Ib }, 0 },
3102   },
3103   /* REG_81 */
3104   {
3105     { "addQ",   { Evh1, Iv }, 0 },
3106     { "orQ",    { Evh1, Iv }, 0 },
3107     { "adcQ",   { Evh1, Iv }, 0 },
3108     { "sbbQ",   { Evh1, Iv }, 0 },
3109     { "andQ",   { Evh1, Iv }, 0 },
3110     { "subQ",   { Evh1, Iv }, 0 },
3111     { "xorQ",   { Evh1, Iv }, 0 },
3112     { "cmpQ",   { Ev, Iv }, 0 },
3113   },
3114   /* REG_83 */
3115   {
3116     { "addQ",   { Evh1, sIb }, 0 },
3117     { "orQ",    { Evh1, sIb }, 0 },
3118     { "adcQ",   { Evh1, sIb }, 0 },
3119     { "sbbQ",   { Evh1, sIb }, 0 },
3120     { "andQ",   { Evh1, sIb }, 0 },
3121     { "subQ",   { Evh1, sIb }, 0 },
3122     { "xorQ",   { Evh1, sIb }, 0 },
3123     { "cmpQ",   { Ev, sIb }, 0 },
3124   },
3125   /* REG_8F */
3126   {
3127     { "popU",   { stackEv }, 0 },
3128     { XOP_8F_TABLE (XOP_09) },
3129     { Bad_Opcode },
3130     { Bad_Opcode },
3131     { Bad_Opcode },
3132     { XOP_8F_TABLE (XOP_09) },
3133   },
3134   /* REG_C0 */
3135   {
3136     { "rolA",   { Eb, Ib }, 0 },
3137     { "rorA",   { Eb, Ib }, 0 },
3138     { "rclA",   { Eb, Ib }, 0 },
3139     { "rcrA",   { Eb, Ib }, 0 },
3140     { "shlA",   { Eb, Ib }, 0 },
3141     { "shrA",   { Eb, Ib }, 0 },
3142     { "shlA",   { Eb, Ib }, 0 },
3143     { "sarA",   { Eb, Ib }, 0 },
3144   },
3145   /* REG_C1 */
3146   {
3147     { "rolQ",   { Ev, Ib }, 0 },
3148     { "rorQ",   { Ev, Ib }, 0 },
3149     { "rclQ",   { Ev, Ib }, 0 },
3150     { "rcrQ",   { Ev, Ib }, 0 },
3151     { "shlQ",   { Ev, Ib }, 0 },
3152     { "shrQ",   { Ev, Ib }, 0 },
3153     { "shlQ",   { Ev, Ib }, 0 },
3154     { "sarQ",   { Ev, Ib }, 0 },
3155   },
3156   /* REG_C6 */
3157   {
3158     { "movA",   { Ebh3, Ib }, 0 },
3159     { Bad_Opcode },
3160     { Bad_Opcode },
3161     { Bad_Opcode },
3162     { Bad_Opcode },
3163     { Bad_Opcode },
3164     { Bad_Opcode },
3165     { MOD_TABLE (MOD_C6_REG_7) },
3166   },
3167   /* REG_C7 */
3168   {
3169     { "movQ",   { Evh3, Iv }, 0 },
3170     { Bad_Opcode },
3171     { Bad_Opcode },
3172     { Bad_Opcode },
3173     { Bad_Opcode },
3174     { Bad_Opcode },
3175     { Bad_Opcode },
3176     { MOD_TABLE (MOD_C7_REG_7) },
3177   },
3178   /* REG_D0 */
3179   {
3180     { "rolA",   { Eb, I1 }, 0 },
3181     { "rorA",   { Eb, I1 }, 0 },
3182     { "rclA",   { Eb, I1 }, 0 },
3183     { "rcrA",   { Eb, I1 }, 0 },
3184     { "shlA",   { Eb, I1 }, 0 },
3185     { "shrA",   { Eb, I1 }, 0 },
3186     { "shlA",   { Eb, I1 }, 0 },
3187     { "sarA",   { Eb, I1 }, 0 },
3188   },
3189   /* REG_D1 */
3190   {
3191     { "rolQ",   { Ev, I1 }, 0 },
3192     { "rorQ",   { Ev, I1 }, 0 },
3193     { "rclQ",   { Ev, I1 }, 0 },
3194     { "rcrQ",   { Ev, I1 }, 0 },
3195     { "shlQ",   { Ev, I1 }, 0 },
3196     { "shrQ",   { Ev, I1 }, 0 },
3197     { "shlQ",   { Ev, I1 }, 0 },
3198     { "sarQ",   { Ev, I1 }, 0 },
3199   },
3200   /* REG_D2 */
3201   {
3202     { "rolA",   { Eb, CL }, 0 },
3203     { "rorA",   { Eb, CL }, 0 },
3204     { "rclA",   { Eb, CL }, 0 },
3205     { "rcrA",   { Eb, CL }, 0 },
3206     { "shlA",   { Eb, CL }, 0 },
3207     { "shrA",   { Eb, CL }, 0 },
3208     { "shlA",   { Eb, CL }, 0 },
3209     { "sarA",   { Eb, CL }, 0 },
3210   },
3211   /* REG_D3 */
3212   {
3213     { "rolQ",   { Ev, CL }, 0 },
3214     { "rorQ",   { Ev, CL }, 0 },
3215     { "rclQ",   { Ev, CL }, 0 },
3216     { "rcrQ",   { Ev, CL }, 0 },
3217     { "shlQ",   { Ev, CL }, 0 },
3218     { "shrQ",   { Ev, CL }, 0 },
3219     { "shlQ",   { Ev, CL }, 0 },
3220     { "sarQ",   { Ev, CL }, 0 },
3221   },
3222   /* REG_F6 */
3223   {
3224     { "testA",  { Eb, Ib }, 0 },
3225     { "testA",  { Eb, Ib }, 0 },
3226     { "notA",   { Ebh1 }, 0 },
3227     { "negA",   { Ebh1 }, 0 },
3228     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3229     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3230     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3231     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3232   },
3233   /* REG_F7 */
3234   {
3235     { "testQ",  { Ev, Iv }, 0 },
3236     { "testQ",  { Ev, Iv }, 0 },
3237     { "notQ",   { Evh1 }, 0 },
3238     { "negQ",   { Evh1 }, 0 },
3239     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3240     { "imulQ",  { Ev }, 0 },
3241     { "divQ",   { Ev }, 0 },
3242     { "idivQ",  { Ev }, 0 },
3243   },
3244   /* REG_FE */
3245   {
3246     { "incA",   { Ebh1 }, 0 },
3247     { "decA",   { Ebh1 }, 0 },
3248   },
3249   /* REG_FF */
3250   {
3251     { "incQ",   { Evh1 }, 0 },
3252     { "decQ",   { Evh1 }, 0 },
3253     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3254     { MOD_TABLE (MOD_FF_REG_3) },
3255     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3256     { MOD_TABLE (MOD_FF_REG_5) },
3257     { "pushU",  { stackEv }, 0 },
3258     { Bad_Opcode },
3259   },
3260   /* REG_0F00 */
3261   {
3262     { "sldtD",  { Sv }, 0 },
3263     { "strD",   { Sv }, 0 },
3264     { "lldt",   { Ew }, 0 },
3265     { "ltr",    { Ew }, 0 },
3266     { "verr",   { Ew }, 0 },
3267     { "verw",   { Ew }, 0 },
3268     { Bad_Opcode },
3269     { Bad_Opcode },
3270   },
3271   /* REG_0F01 */
3272   {
3273     { MOD_TABLE (MOD_0F01_REG_0) },
3274     { MOD_TABLE (MOD_0F01_REG_1) },
3275     { MOD_TABLE (MOD_0F01_REG_2) },
3276     { MOD_TABLE (MOD_0F01_REG_3) },
3277     { "smswD",  { Sv }, 0 },
3278     { MOD_TABLE (MOD_0F01_REG_5) },
3279     { "lmsw",   { Ew }, 0 },
3280     { MOD_TABLE (MOD_0F01_REG_7) },
3281   },
3282   /* REG_0F0D */
3283   {
3284     { "prefetch",       { Mb }, 0 },
3285     { "prefetchw",      { Mb }, 0 },
3286     { "prefetchwt1",    { Mb }, 0 },
3287     { "prefetch",       { Mb }, 0 },
3288     { "prefetch",       { Mb }, 0 },
3289     { "prefetch",       { Mb }, 0 },
3290     { "prefetch",       { Mb }, 0 },
3291     { "prefetch",       { Mb }, 0 },
3292   },
3293   /* REG_0F18 */
3294   {
3295     { MOD_TABLE (MOD_0F18_REG_0) },
3296     { MOD_TABLE (MOD_0F18_REG_1) },
3297     { MOD_TABLE (MOD_0F18_REG_2) },
3298     { MOD_TABLE (MOD_0F18_REG_3) },
3299     { MOD_TABLE (MOD_0F18_REG_4) },
3300     { MOD_TABLE (MOD_0F18_REG_5) },
3301     { MOD_TABLE (MOD_0F18_REG_6) },
3302     { MOD_TABLE (MOD_0F18_REG_7) },
3303   },
3304   /* REG_0F1C_P_0_MOD_0 */
3305   {
3306     { "cldemote",       { Mb }, 0 },
3307     { "nopQ",           { Ev }, 0 },
3308     { "nopQ",           { Ev }, 0 },
3309     { "nopQ",           { Ev }, 0 },
3310     { "nopQ",           { Ev }, 0 },
3311     { "nopQ",           { Ev }, 0 },
3312     { "nopQ",           { Ev }, 0 },
3313     { "nopQ",           { Ev }, 0 },
3314   },
3315   /* REG_0F1E_P_1_MOD_3 */
3316   {
3317     { "nopQ",           { Ev }, 0 },
3318     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3319     { "nopQ",           { Ev }, 0 },
3320     { "nopQ",           { Ev }, 0 },
3321     { "nopQ",           { Ev }, 0 },
3322     { "nopQ",           { Ev }, 0 },
3323     { "nopQ",           { Ev }, 0 },
3324     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3325   },
3326   /* REG_0F71 */
3327   {
3328     { Bad_Opcode },
3329     { Bad_Opcode },
3330     { MOD_TABLE (MOD_0F71_REG_2) },
3331     { Bad_Opcode },
3332     { MOD_TABLE (MOD_0F71_REG_4) },
3333     { Bad_Opcode },
3334     { MOD_TABLE (MOD_0F71_REG_6) },
3335   },
3336   /* REG_0F72 */
3337   {
3338     { Bad_Opcode },
3339     { Bad_Opcode },
3340     { MOD_TABLE (MOD_0F72_REG_2) },
3341     { Bad_Opcode },
3342     { MOD_TABLE (MOD_0F72_REG_4) },
3343     { Bad_Opcode },
3344     { MOD_TABLE (MOD_0F72_REG_6) },
3345   },
3346   /* REG_0F73 */
3347   {
3348     { Bad_Opcode },
3349     { Bad_Opcode },
3350     { MOD_TABLE (MOD_0F73_REG_2) },
3351     { MOD_TABLE (MOD_0F73_REG_3) },
3352     { Bad_Opcode },
3353     { Bad_Opcode },
3354     { MOD_TABLE (MOD_0F73_REG_6) },
3355     { MOD_TABLE (MOD_0F73_REG_7) },
3356   },
3357   /* REG_0FA6 */
3358   {
3359     { "montmul",        { { OP_0f07, 0 } }, 0 },
3360     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3361     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3362   },
3363   /* REG_0FA7 */
3364   {
3365     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3366     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3367     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3368     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3369     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3370     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3371   },
3372   /* REG_0FAE */
3373   {
3374     { MOD_TABLE (MOD_0FAE_REG_0) },
3375     { MOD_TABLE (MOD_0FAE_REG_1) },
3376     { MOD_TABLE (MOD_0FAE_REG_2) },
3377     { MOD_TABLE (MOD_0FAE_REG_3) },
3378     { MOD_TABLE (MOD_0FAE_REG_4) },
3379     { MOD_TABLE (MOD_0FAE_REG_5) },
3380     { MOD_TABLE (MOD_0FAE_REG_6) },
3381     { MOD_TABLE (MOD_0FAE_REG_7) },
3382   },
3383   /* REG_0FBA */
3384   {
3385     { Bad_Opcode },
3386     { Bad_Opcode },
3387     { Bad_Opcode },
3388     { Bad_Opcode },
3389     { "btQ",    { Ev, Ib }, 0 },
3390     { "btsQ",   { Evh1, Ib }, 0 },
3391     { "btrQ",   { Evh1, Ib }, 0 },
3392     { "btcQ",   { Evh1, Ib }, 0 },
3393   },
3394   /* REG_0FC7 */
3395   {
3396     { Bad_Opcode },
3397     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3398     { Bad_Opcode },
3399     { MOD_TABLE (MOD_0FC7_REG_3) },
3400     { MOD_TABLE (MOD_0FC7_REG_4) },
3401     { MOD_TABLE (MOD_0FC7_REG_5) },
3402     { MOD_TABLE (MOD_0FC7_REG_6) },
3403     { MOD_TABLE (MOD_0FC7_REG_7) },
3404   },
3405   /* REG_VEX_0F71 */
3406   {
3407     { Bad_Opcode },
3408     { Bad_Opcode },
3409     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3410     { Bad_Opcode },
3411     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3412     { Bad_Opcode },
3413     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3414   },
3415   /* REG_VEX_0F72 */
3416   {
3417     { Bad_Opcode },
3418     { Bad_Opcode },
3419     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3420     { Bad_Opcode },
3421     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3422     { Bad_Opcode },
3423     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3424   },
3425   /* REG_VEX_0F73 */
3426   {
3427     { Bad_Opcode },
3428     { Bad_Opcode },
3429     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3430     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3431     { Bad_Opcode },
3432     { Bad_Opcode },
3433     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3434     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3435   },
3436   /* REG_VEX_0FAE */
3437   {
3438     { Bad_Opcode },
3439     { Bad_Opcode },
3440     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3441     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3442   },
3443   /* REG_VEX_0F38F3 */
3444   {
3445     { Bad_Opcode },
3446     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3447     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3448     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3449   },
3450   /* REG_XOP_LWPCB */
3451   {
3452     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3453     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3454   },
3455   /* REG_XOP_LWP */
3456   {
3457     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3458     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3459   },
3460   /* REG_XOP_TBM_01 */
3461   {
3462     { Bad_Opcode },
3463     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3464     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3465     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3466     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3467     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3468     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3469     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3470   },
3471   /* REG_XOP_TBM_02 */
3472   {
3473     { Bad_Opcode },
3474     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { Bad_Opcode },
3479     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3480   },
3481
3482 #include "i386-dis-evex-reg.h"
3483 };
3484
3485 static const struct dis386 prefix_table[][4] = {
3486   /* PREFIX_90 */
3487   {
3488     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3489     { "pause", { XX }, 0 },
3490     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3491     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3492   },
3493
3494   /* PREFIX_0F01_REG_3_RM_1 */
3495   {
3496     { "vmmcall",        { Skip_MODRM }, 0 },
3497     { "vmgexit",        { Skip_MODRM }, 0 },
3498     { Bad_Opcode },
3499     { "vmgexit",        { Skip_MODRM }, 0 },
3500   },
3501
3502   /* PREFIX_0F01_REG_5_MOD_0 */
3503   {
3504     { Bad_Opcode },
3505     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3506   },
3507
3508   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3509   {
3510     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3511     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3512     { Bad_Opcode },
3513     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3514   },
3515
3516   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3517   {
3518     { Bad_Opcode },
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3522   },
3523
3524   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3525   {
3526     { Bad_Opcode },
3527     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3528   },
3529
3530   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3531   {
3532     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3533     { "mcommit",        { Skip_MODRM }, 0 },
3534   },
3535
3536   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3537   {
3538     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3539   },
3540
3541   /* PREFIX_0F09 */
3542   {
3543     { "wbinvd",   { XX }, 0 },
3544     { "wbnoinvd", { XX }, 0 },
3545   },
3546
3547   /* PREFIX_0F10 */
3548   {
3549     { "movups", { XM, EXx }, PREFIX_OPCODE },
3550     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3551     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3552     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3553   },
3554
3555   /* PREFIX_0F11 */
3556   {
3557     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3558     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3559     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3560     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3561   },
3562
3563   /* PREFIX_0F12 */
3564   {
3565     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3566     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3567     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3568     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3569   },
3570
3571   /* PREFIX_0F16 */
3572   {
3573     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3574     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3575     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3576   },
3577
3578   /* PREFIX_0F1A */
3579   {
3580     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3581     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3582     { "bndmov", { Gbnd, Ebnd }, 0 },
3583     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3584   },
3585
3586   /* PREFIX_0F1B */
3587   {
3588     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3589     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3590     { "bndmov", { EbndS, Gbnd }, 0 },
3591     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3592   },
3593
3594   /* PREFIX_0F1C */
3595   {
3596     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3597     { "nopQ",   { Ev }, PREFIX_OPCODE },
3598     { "nopQ",   { Ev }, PREFIX_OPCODE },
3599     { "nopQ",   { Ev }, PREFIX_OPCODE },
3600   },
3601
3602   /* PREFIX_0F1E */
3603   {
3604     { "nopQ",   { Ev }, PREFIX_OPCODE },
3605     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3606     { "nopQ",   { Ev }, PREFIX_OPCODE },
3607     { "nopQ",   { Ev }, PREFIX_OPCODE },
3608   },
3609
3610   /* PREFIX_0F2A */
3611   {
3612     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3613     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3614     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3615     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3616   },
3617
3618   /* PREFIX_0F2B */
3619   {
3620     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3621     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3622     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3623     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3624   },
3625
3626   /* PREFIX_0F2C */
3627   {
3628     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3629     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3630     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3631     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3632   },
3633
3634   /* PREFIX_0F2D */
3635   {
3636     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3637     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3638     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3639     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3640   },
3641
3642   /* PREFIX_0F2E */
3643   {
3644     { "ucomiss",{ XM, EXd }, 0 },
3645     { Bad_Opcode },
3646     { "ucomisd",{ XM, EXq }, 0 },
3647   },
3648
3649   /* PREFIX_0F2F */
3650   {
3651     { "comiss", { XM, EXd }, 0 },
3652     { Bad_Opcode },
3653     { "comisd", { XM, EXq }, 0 },
3654   },
3655
3656   /* PREFIX_0F51 */
3657   {
3658     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3659     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3660     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3661     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3662   },
3663
3664   /* PREFIX_0F52 */
3665   {
3666     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3667     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3668   },
3669
3670   /* PREFIX_0F53 */
3671   {
3672     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3673     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3674   },
3675
3676   /* PREFIX_0F58 */
3677   {
3678     { "addps", { XM, EXx }, PREFIX_OPCODE },
3679     { "addss", { XM, EXd }, PREFIX_OPCODE },
3680     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3681     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3682   },
3683
3684   /* PREFIX_0F59 */
3685   {
3686     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3687     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3688     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3689     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3690   },
3691
3692   /* PREFIX_0F5A */
3693   {
3694     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3695     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3696     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3697     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3698   },
3699
3700   /* PREFIX_0F5B */
3701   {
3702     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3703     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3704     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3705   },
3706
3707   /* PREFIX_0F5C */
3708   {
3709     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3710     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3711     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3712     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3713   },
3714
3715   /* PREFIX_0F5D */
3716   {
3717     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3718     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3719     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3720     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3721   },
3722
3723   /* PREFIX_0F5E */
3724   {
3725     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3726     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3727     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3728     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3729   },
3730
3731   /* PREFIX_0F5F */
3732   {
3733     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3734     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3735     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3736     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3737   },
3738
3739   /* PREFIX_0F60 */
3740   {
3741     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3742     { Bad_Opcode },
3743     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3744   },
3745
3746   /* PREFIX_0F61 */
3747   {
3748     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3749     { Bad_Opcode },
3750     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3751   },
3752
3753   /* PREFIX_0F62 */
3754   {
3755     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3756     { Bad_Opcode },
3757     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3758   },
3759
3760   /* PREFIX_0F6C */
3761   {
3762     { Bad_Opcode },
3763     { Bad_Opcode },
3764     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3765   },
3766
3767   /* PREFIX_0F6D */
3768   {
3769     { Bad_Opcode },
3770     { Bad_Opcode },
3771     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3772   },
3773
3774   /* PREFIX_0F6F */
3775   {
3776     { "movq",   { MX, EM }, PREFIX_OPCODE },
3777     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3778     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3779   },
3780
3781   /* PREFIX_0F70 */
3782   {
3783     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3784     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3785     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3786     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F73_REG_3 */
3790   {
3791     { Bad_Opcode },
3792     { Bad_Opcode },
3793     { "psrldq", { XS, Ib }, 0 },
3794   },
3795
3796   /* PREFIX_0F73_REG_7 */
3797   {
3798     { Bad_Opcode },
3799     { Bad_Opcode },
3800     { "pslldq", { XS, Ib }, 0 },
3801   },
3802
3803   /* PREFIX_0F78 */
3804   {
3805     {"vmread",  { Em, Gm }, 0 },
3806     { Bad_Opcode },
3807     {"extrq",   { XS, Ib, Ib }, 0 },
3808     {"insertq", { XM, XS, Ib, Ib }, 0 },
3809   },
3810
3811   /* PREFIX_0F79 */
3812   {
3813     {"vmwrite", { Gm, Em }, 0 },
3814     { Bad_Opcode },
3815     {"extrq",   { XM, XS }, 0 },
3816     {"insertq", { XM, XS }, 0 },
3817   },
3818
3819   /* PREFIX_0F7C */
3820   {
3821     { Bad_Opcode },
3822     { Bad_Opcode },
3823     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3824     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3825   },
3826
3827   /* PREFIX_0F7D */
3828   {
3829     { Bad_Opcode },
3830     { Bad_Opcode },
3831     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3832     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3833   },
3834
3835   /* PREFIX_0F7E */
3836   {
3837     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3838     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3839     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F7F */
3843   {
3844     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3845     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3846     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3847   },
3848
3849   /* PREFIX_0FAE_REG_0_MOD_3 */
3850   {
3851     { Bad_Opcode },
3852     { "rdfsbase", { Ev }, 0 },
3853   },
3854
3855   /* PREFIX_0FAE_REG_1_MOD_3 */
3856   {
3857     { Bad_Opcode },
3858     { "rdgsbase", { Ev }, 0 },
3859   },
3860
3861   /* PREFIX_0FAE_REG_2_MOD_3 */
3862   {
3863     { Bad_Opcode },
3864     { "wrfsbase", { Ev }, 0 },
3865   },
3866
3867   /* PREFIX_0FAE_REG_3_MOD_3 */
3868   {
3869     { Bad_Opcode },
3870     { "wrgsbase", { Ev }, 0 },
3871   },
3872
3873   /* PREFIX_0FAE_REG_4_MOD_0 */
3874   {
3875     { "xsave",  { FXSAVE }, 0 },
3876     { "ptwrite%LQ", { Edq }, 0 },
3877   },
3878
3879   /* PREFIX_0FAE_REG_4_MOD_3 */
3880   {
3881     { Bad_Opcode },
3882     { "ptwrite%LQ", { Edq }, 0 },
3883   },
3884
3885   /* PREFIX_0FAE_REG_5_MOD_0 */
3886   {
3887     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3888   },
3889
3890   /* PREFIX_0FAE_REG_5_MOD_3 */
3891   {
3892     { "lfence",         { Skip_MODRM }, 0 },
3893     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3894   },
3895
3896   /* PREFIX_0FAE_REG_6_MOD_0 */
3897   {
3898     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3899     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3900     { "clwb",   { Mb }, PREFIX_OPCODE },
3901   },
3902
3903   /* PREFIX_0FAE_REG_6_MOD_3 */
3904   {
3905     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3906     { "umonitor",       { Eva }, PREFIX_OPCODE },
3907     { "tpause", { Edq }, PREFIX_OPCODE },
3908     { "umwait", { Edq }, PREFIX_OPCODE },
3909   },
3910
3911   /* PREFIX_0FAE_REG_7_MOD_0 */
3912   {
3913     { "clflush",        { Mb }, 0 },
3914     { Bad_Opcode },
3915     { "clflushopt",     { Mb }, 0 },
3916   },
3917
3918   /* PREFIX_0FB8 */
3919   {
3920     { Bad_Opcode },
3921     { "popcntS", { Gv, Ev }, 0 },
3922   },
3923
3924   /* PREFIX_0FBC */
3925   {
3926     { "bsfS",   { Gv, Ev }, 0 },
3927     { "tzcntS", { Gv, Ev }, 0 },
3928     { "bsfS",   { Gv, Ev }, 0 },
3929   },
3930
3931   /* PREFIX_0FBD */
3932   {
3933     { "bsrS",   { Gv, Ev }, 0 },
3934     { "lzcntS", { Gv, Ev }, 0 },
3935     { "bsrS",   { Gv, Ev }, 0 },
3936   },
3937
3938   /* PREFIX_0FC2 */
3939   {
3940     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3941     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3942     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3943     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3944   },
3945
3946   /* PREFIX_0FC3_MOD_0 */
3947   {
3948     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3949   },
3950
3951   /* PREFIX_0FC7_REG_6_MOD_0 */
3952   {
3953     { "vmptrld",{ Mq }, 0 },
3954     { "vmxon",  { Mq }, 0 },
3955     { "vmclear",{ Mq }, 0 },
3956   },
3957
3958   /* PREFIX_0FC7_REG_6_MOD_3 */
3959   {
3960     { "rdrand", { Ev }, 0 },
3961     { Bad_Opcode },
3962     { "rdrand", { Ev }, 0 }
3963   },
3964
3965   /* PREFIX_0FC7_REG_7_MOD_3 */
3966   {
3967     { "rdseed", { Ev }, 0 },
3968     { "rdpid",  { Em }, 0 },
3969     { "rdseed", { Ev }, 0 },
3970   },
3971
3972   /* PREFIX_0FD0 */
3973   {
3974     { Bad_Opcode },
3975     { Bad_Opcode },
3976     { "addsubpd", { XM, EXx }, 0 },
3977     { "addsubps", { XM, EXx }, 0 },
3978   },
3979
3980   /* PREFIX_0FD6 */
3981   {
3982     { Bad_Opcode },
3983     { "movq2dq",{ XM, MS }, 0 },
3984     { "movq",   { EXqS, XM }, 0 },
3985     { "movdq2q",{ MX, XS }, 0 },
3986   },
3987
3988   /* PREFIX_0FE6 */
3989   {
3990     { Bad_Opcode },
3991     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3992     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3993     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3994   },
3995
3996   /* PREFIX_0FE7 */
3997   {
3998     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3999     { Bad_Opcode },
4000     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4001   },
4002
4003   /* PREFIX_0FF0 */
4004   {
4005     { Bad_Opcode },
4006     { Bad_Opcode },
4007     { Bad_Opcode },
4008     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4009   },
4010
4011   /* PREFIX_0FF7 */
4012   {
4013     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4014     { Bad_Opcode },
4015     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4016   },
4017
4018   /* PREFIX_0F3810 */
4019   {
4020     { Bad_Opcode },
4021     { Bad_Opcode },
4022     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4023   },
4024
4025   /* PREFIX_0F3814 */
4026   {
4027     { Bad_Opcode },
4028     { Bad_Opcode },
4029     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4030   },
4031
4032   /* PREFIX_0F3815 */
4033   {
4034     { Bad_Opcode },
4035     { Bad_Opcode },
4036     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4037   },
4038
4039   /* PREFIX_0F3817 */
4040   {
4041     { Bad_Opcode },
4042     { Bad_Opcode },
4043     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4044   },
4045
4046   /* PREFIX_0F3820 */
4047   {
4048     { Bad_Opcode },
4049     { Bad_Opcode },
4050     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4051   },
4052
4053   /* PREFIX_0F3821 */
4054   {
4055     { Bad_Opcode },
4056     { Bad_Opcode },
4057     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4058   },
4059
4060   /* PREFIX_0F3822 */
4061   {
4062     { Bad_Opcode },
4063     { Bad_Opcode },
4064     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4065   },
4066
4067   /* PREFIX_0F3823 */
4068   {
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4072   },
4073
4074   /* PREFIX_0F3824 */
4075   {
4076     { Bad_Opcode },
4077     { Bad_Opcode },
4078     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4079   },
4080
4081   /* PREFIX_0F3825 */
4082   {
4083     { Bad_Opcode },
4084     { Bad_Opcode },
4085     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4086   },
4087
4088   /* PREFIX_0F3828 */
4089   {
4090     { Bad_Opcode },
4091     { Bad_Opcode },
4092     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4093   },
4094
4095   /* PREFIX_0F3829 */
4096   {
4097     { Bad_Opcode },
4098     { Bad_Opcode },
4099     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4100   },
4101
4102   /* PREFIX_0F382A */
4103   {
4104     { Bad_Opcode },
4105     { Bad_Opcode },
4106     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4107   },
4108
4109   /* PREFIX_0F382B */
4110   {
4111     { Bad_Opcode },
4112     { Bad_Opcode },
4113     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4114   },
4115
4116   /* PREFIX_0F3830 */
4117   {
4118     { Bad_Opcode },
4119     { Bad_Opcode },
4120     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4121   },
4122
4123   /* PREFIX_0F3831 */
4124   {
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4128   },
4129
4130   /* PREFIX_0F3832 */
4131   {
4132     { Bad_Opcode },
4133     { Bad_Opcode },
4134     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_0F3833 */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4142   },
4143
4144   /* PREFIX_0F3834 */
4145   {
4146     { Bad_Opcode },
4147     { Bad_Opcode },
4148     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4149   },
4150
4151   /* PREFIX_0F3835 */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4156   },
4157
4158   /* PREFIX_0F3837 */
4159   {
4160     { Bad_Opcode },
4161     { Bad_Opcode },
4162     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4163   },
4164
4165   /* PREFIX_0F3838 */
4166   {
4167     { Bad_Opcode },
4168     { Bad_Opcode },
4169     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4170   },
4171
4172   /* PREFIX_0F3839 */
4173   {
4174     { Bad_Opcode },
4175     { Bad_Opcode },
4176     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4177   },
4178
4179   /* PREFIX_0F383A */
4180   {
4181     { Bad_Opcode },
4182     { Bad_Opcode },
4183     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4184   },
4185
4186   /* PREFIX_0F383B */
4187   {
4188     { Bad_Opcode },
4189     { Bad_Opcode },
4190     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4191   },
4192
4193   /* PREFIX_0F383C */
4194   {
4195     { Bad_Opcode },
4196     { Bad_Opcode },
4197     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4198   },
4199
4200   /* PREFIX_0F383D */
4201   {
4202     { Bad_Opcode },
4203     { Bad_Opcode },
4204     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4205   },
4206
4207   /* PREFIX_0F383E */
4208   {
4209     { Bad_Opcode },
4210     { Bad_Opcode },
4211     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4212   },
4213
4214   /* PREFIX_0F383F */
4215   {
4216     { Bad_Opcode },
4217     { Bad_Opcode },
4218     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4219   },
4220
4221   /* PREFIX_0F3840 */
4222   {
4223     { Bad_Opcode },
4224     { Bad_Opcode },
4225     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4226   },
4227
4228   /* PREFIX_0F3841 */
4229   {
4230     { Bad_Opcode },
4231     { Bad_Opcode },
4232     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4233   },
4234
4235   /* PREFIX_0F3880 */
4236   {
4237     { Bad_Opcode },
4238     { Bad_Opcode },
4239     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4240   },
4241
4242   /* PREFIX_0F3881 */
4243   {
4244     { Bad_Opcode },
4245     { Bad_Opcode },
4246     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4247   },
4248
4249   /* PREFIX_0F3882 */
4250   {
4251     { Bad_Opcode },
4252     { Bad_Opcode },
4253     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4254   },
4255
4256   /* PREFIX_0F38C8 */
4257   {
4258     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F38C9 */
4262   {
4263     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4264   },
4265
4266   /* PREFIX_0F38CA */
4267   {
4268     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4269   },
4270
4271   /* PREFIX_0F38CB */
4272   {
4273     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F38CC */
4277   {
4278     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F38CD */
4282   {
4283     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4284   },
4285
4286   /* PREFIX_0F38CF */
4287   {
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4291   },
4292
4293   /* PREFIX_0F38DB */
4294   {
4295     { Bad_Opcode },
4296     { Bad_Opcode },
4297     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4298   },
4299
4300   /* PREFIX_0F38DC */
4301   {
4302     { Bad_Opcode },
4303     { Bad_Opcode },
4304     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4305   },
4306
4307   /* PREFIX_0F38DD */
4308   {
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4312   },
4313
4314   /* PREFIX_0F38DE */
4315   {
4316     { Bad_Opcode },
4317     { Bad_Opcode },
4318     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4319   },
4320
4321   /* PREFIX_0F38DF */
4322   {
4323     { Bad_Opcode },
4324     { Bad_Opcode },
4325     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4326   },
4327
4328   /* PREFIX_0F38F0 */
4329   {
4330     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4331     { Bad_Opcode },
4332     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4333     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4334   },
4335
4336   /* PREFIX_0F38F1 */
4337   {
4338     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4339     { Bad_Opcode },
4340     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4341     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F38F5 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4349   },
4350
4351   /* PREFIX_0F38F6 */
4352   {
4353     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4354     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4355     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4356     { Bad_Opcode },
4357   },
4358
4359   /* PREFIX_0F38F8 */
4360   {
4361     { Bad_Opcode },
4362     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4363     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4364     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4365   },
4366
4367   /* PREFIX_0F38F9 */
4368   {
4369     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4370   },
4371
4372   /* PREFIX_0F3A08 */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4377   },
4378
4379   /* PREFIX_0F3A09 */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4384   },
4385
4386   /* PREFIX_0F3A0A */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F3A0B */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F3A0C */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4405   },
4406
4407   /* PREFIX_0F3A0D */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F3A0E */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4419   },
4420
4421   /* PREFIX_0F3A14 */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F3A15 */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4433   },
4434
4435   /* PREFIX_0F3A16 */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4440   },
4441
4442   /* PREFIX_0F3A17 */
4443   {
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4447   },
4448
4449   /* PREFIX_0F3A20 */
4450   {
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4454   },
4455
4456   /* PREFIX_0F3A21 */
4457   {
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4461   },
4462
4463   /* PREFIX_0F3A22 */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4468   },
4469
4470   /* PREFIX_0F3A40 */
4471   {
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4475   },
4476
4477   /* PREFIX_0F3A41 */
4478   {
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4482   },
4483
4484   /* PREFIX_0F3A42 */
4485   {
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4489   },
4490
4491   /* PREFIX_0F3A44 */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4496   },
4497
4498   /* PREFIX_0F3A60 */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4503   },
4504
4505   /* PREFIX_0F3A61 */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4510   },
4511
4512   /* PREFIX_0F3A62 */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4517   },
4518
4519   /* PREFIX_0F3A63 */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F3ACC */
4527   {
4528     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3ACE */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3ACF */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3ADF */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_VEX_0F10 */
4553   {
4554     { "vmovups",        { XM, EXx }, 0 },
4555     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4556     { "vmovupd",        { XM, EXx }, 0 },
4557     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4558   },
4559
4560   /* PREFIX_VEX_0F11 */
4561   {
4562     { "vmovups",        { EXxS, XM }, 0 },
4563     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4564     { "vmovupd",        { EXxS, XM }, 0 },
4565     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4566   },
4567
4568   /* PREFIX_VEX_0F12 */
4569   {
4570     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4571     { "vmovsldup",      { XM, EXx }, 0 },
4572     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4573     { "vmovddup",       { XM, EXymmq }, 0 },
4574   },
4575
4576   /* PREFIX_VEX_0F16 */
4577   {
4578     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4579     { "vmovshdup",      { XM, EXx }, 0 },
4580     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4581   },
4582
4583   /* PREFIX_VEX_0F2A */
4584   {
4585     { Bad_Opcode },
4586     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4587     { Bad_Opcode },
4588     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4589   },
4590
4591   /* PREFIX_VEX_0F2C */
4592   {
4593     { Bad_Opcode },
4594     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4595     { Bad_Opcode },
4596     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4597   },
4598
4599   /* PREFIX_VEX_0F2D */
4600   {
4601     { Bad_Opcode },
4602     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4603     { Bad_Opcode },
4604     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4605   },
4606
4607   /* PREFIX_VEX_0F2E */
4608   {
4609     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4610     { Bad_Opcode },
4611     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4612   },
4613
4614   /* PREFIX_VEX_0F2F */
4615   {
4616     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4617     { Bad_Opcode },
4618     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4619   },
4620
4621   /* PREFIX_VEX_0F41 */
4622   {
4623     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4624     { Bad_Opcode },
4625     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4626   },
4627
4628   /* PREFIX_VEX_0F42 */
4629   {
4630     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4631     { Bad_Opcode },
4632     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4633   },
4634
4635   /* PREFIX_VEX_0F44 */
4636   {
4637     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4638     { Bad_Opcode },
4639     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4640   },
4641
4642   /* PREFIX_VEX_0F45 */
4643   {
4644     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4645     { Bad_Opcode },
4646     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4647   },
4648
4649   /* PREFIX_VEX_0F46 */
4650   {
4651     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4652     { Bad_Opcode },
4653     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4654   },
4655
4656   /* PREFIX_VEX_0F47 */
4657   {
4658     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4659     { Bad_Opcode },
4660     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4661   },
4662
4663   /* PREFIX_VEX_0F4A */
4664   {
4665     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4666     { Bad_Opcode },
4667     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4668   },
4669
4670   /* PREFIX_VEX_0F4B */
4671   {
4672     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4673     { Bad_Opcode },
4674     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4675   },
4676
4677   /* PREFIX_VEX_0F51 */
4678   {
4679     { "vsqrtps",        { XM, EXx }, 0 },
4680     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4681     { "vsqrtpd",        { XM, EXx }, 0 },
4682     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4683   },
4684
4685   /* PREFIX_VEX_0F52 */
4686   {
4687     { "vrsqrtps",       { XM, EXx }, 0 },
4688     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4689   },
4690
4691   /* PREFIX_VEX_0F53 */
4692   {
4693     { "vrcpps",         { XM, EXx }, 0 },
4694     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4695   },
4696
4697   /* PREFIX_VEX_0F58 */
4698   {
4699     { "vaddps",         { XM, Vex, EXx }, 0 },
4700     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4701     { "vaddpd",         { XM, Vex, EXx }, 0 },
4702     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4703   },
4704
4705   /* PREFIX_VEX_0F59 */
4706   {
4707     { "vmulps",         { XM, Vex, EXx }, 0 },
4708     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4709     { "vmulpd",         { XM, Vex, EXx }, 0 },
4710     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4711   },
4712
4713   /* PREFIX_VEX_0F5A */
4714   {
4715     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4716     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4717     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4718     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4719   },
4720
4721   /* PREFIX_VEX_0F5B */
4722   {
4723     { "vcvtdq2ps",      { XM, EXx }, 0 },
4724     { "vcvttps2dq",     { XM, EXx }, 0 },
4725     { "vcvtps2dq",      { XM, EXx }, 0 },
4726   },
4727
4728   /* PREFIX_VEX_0F5C */
4729   {
4730     { "vsubps",         { XM, Vex, EXx }, 0 },
4731     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4732     { "vsubpd",         { XM, Vex, EXx }, 0 },
4733     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4734   },
4735
4736   /* PREFIX_VEX_0F5D */
4737   {
4738     { "vminps",         { XM, Vex, EXx }, 0 },
4739     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4740     { "vminpd",         { XM, Vex, EXx }, 0 },
4741     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4742   },
4743
4744   /* PREFIX_VEX_0F5E */
4745   {
4746     { "vdivps",         { XM, Vex, EXx }, 0 },
4747     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4748     { "vdivpd",         { XM, Vex, EXx }, 0 },
4749     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4750   },
4751
4752   /* PREFIX_VEX_0F5F */
4753   {
4754     { "vmaxps",         { XM, Vex, EXx }, 0 },
4755     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4756     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4757     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4758   },
4759
4760   /* PREFIX_VEX_0F60 */
4761   {
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4765   },
4766
4767   /* PREFIX_VEX_0F61 */
4768   {
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4772   },
4773
4774   /* PREFIX_VEX_0F62 */
4775   {
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4779   },
4780
4781   /* PREFIX_VEX_0F63 */
4782   {
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4786   },
4787
4788   /* PREFIX_VEX_0F64 */
4789   {
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4793   },
4794
4795   /* PREFIX_VEX_0F65 */
4796   {
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4800   },
4801
4802   /* PREFIX_VEX_0F66 */
4803   {
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4807   },
4808
4809   /* PREFIX_VEX_0F67 */
4810   {
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4814   },
4815
4816   /* PREFIX_VEX_0F68 */
4817   {
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4821   },
4822
4823   /* PREFIX_VEX_0F69 */
4824   {
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4828   },
4829
4830   /* PREFIX_VEX_0F6A */
4831   {
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4835   },
4836
4837   /* PREFIX_VEX_0F6B */
4838   {
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4842   },
4843
4844   /* PREFIX_VEX_0F6C */
4845   {
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4849   },
4850
4851   /* PREFIX_VEX_0F6D */
4852   {
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4856   },
4857
4858   /* PREFIX_VEX_0F6E */
4859   {
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4863   },
4864
4865   /* PREFIX_VEX_0F6F */
4866   {
4867     { Bad_Opcode },
4868     { "vmovdqu",        { XM, EXx }, 0 },
4869     { "vmovdqa",        { XM, EXx }, 0 },
4870   },
4871
4872   /* PREFIX_VEX_0F70 */
4873   {
4874     { Bad_Opcode },
4875     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4876     { "vpshufd",        { XM, EXx, Ib }, 0 },
4877     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4878   },
4879
4880   /* PREFIX_VEX_0F71_REG_2 */
4881   {
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4885   },
4886
4887   /* PREFIX_VEX_0F71_REG_4 */
4888   {
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { "vpsraw",         { Vex, XS, Ib }, 0 },
4892   },
4893
4894   /* PREFIX_VEX_0F71_REG_6 */
4895   {
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { "vpsllw",         { Vex, XS, Ib }, 0 },
4899   },
4900
4901   /* PREFIX_VEX_0F72_REG_2 */
4902   {
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { "vpsrld",         { Vex, XS, Ib }, 0 },
4906   },
4907
4908   /* PREFIX_VEX_0F72_REG_4 */
4909   {
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { "vpsrad",         { Vex, XS, Ib }, 0 },
4913   },
4914
4915   /* PREFIX_VEX_0F72_REG_6 */
4916   {
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { "vpslld",         { Vex, XS, Ib }, 0 },
4920   },
4921
4922   /* PREFIX_VEX_0F73_REG_2 */
4923   {
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4927   },
4928
4929   /* PREFIX_VEX_0F73_REG_3 */
4930   {
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { "vpsrldq",        { Vex, XS, Ib }, 0 },
4934   },
4935
4936   /* PREFIX_VEX_0F73_REG_6 */
4937   {
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { "vpsllq",         { Vex, XS, Ib }, 0 },
4941   },
4942
4943   /* PREFIX_VEX_0F73_REG_7 */
4944   {
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { "vpslldq",        { Vex, XS, Ib }, 0 },
4948   },
4949
4950   /* PREFIX_VEX_0F74 */
4951   {
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
4955   },
4956
4957   /* PREFIX_VEX_0F75 */
4958   {
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
4962   },
4963
4964   /* PREFIX_VEX_0F76 */
4965   {
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
4969   },
4970
4971   /* PREFIX_VEX_0F77 */
4972   {
4973     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
4974   },
4975
4976   /* PREFIX_VEX_0F7C */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { "vhaddpd",        { XM, Vex, EXx }, 0 },
4981     { "vhaddps",        { XM, Vex, EXx }, 0 },
4982   },
4983
4984   /* PREFIX_VEX_0F7D */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { "vhsubpd",        { XM, Vex, EXx }, 0 },
4989     { "vhsubps",        { XM, Vex, EXx }, 0 },
4990   },
4991
4992   /* PREFIX_VEX_0F7E */
4993   {
4994     { Bad_Opcode },
4995     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4996     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4997   },
4998
4999   /* PREFIX_VEX_0F7F */
5000   {
5001     { Bad_Opcode },
5002     { "vmovdqu",        { EXxS, XM }, 0 },
5003     { "vmovdqa",        { EXxS, XM }, 0 },
5004   },
5005
5006   /* PREFIX_VEX_0F90 */
5007   {
5008     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5009     { Bad_Opcode },
5010     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5011   },
5012
5013   /* PREFIX_VEX_0F91 */
5014   {
5015     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5016     { Bad_Opcode },
5017     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5018   },
5019
5020   /* PREFIX_VEX_0F92 */
5021   {
5022     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5023     { Bad_Opcode },
5024     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5025     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5026   },
5027
5028   /* PREFIX_VEX_0F93 */
5029   {
5030     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5031     { Bad_Opcode },
5032     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5033     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5034   },
5035
5036   /* PREFIX_VEX_0F98 */
5037   {
5038     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5039     { Bad_Opcode },
5040     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5041   },
5042
5043   /* PREFIX_VEX_0F99 */
5044   {
5045     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5046     { Bad_Opcode },
5047     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5048   },
5049
5050   /* PREFIX_VEX_0FC2 */
5051   {
5052     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5053     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5054     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5055     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5056   },
5057
5058   /* PREFIX_VEX_0FC4 */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5063   },
5064
5065   /* PREFIX_VEX_0FC5 */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5070   },
5071
5072   /* PREFIX_VEX_0FD0 */
5073   {
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5077     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5078   },
5079
5080   /* PREFIX_VEX_0FD1 */
5081   {
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5085   },
5086
5087   /* PREFIX_VEX_0FD2 */
5088   {
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5092   },
5093
5094   /* PREFIX_VEX_0FD3 */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5099   },
5100
5101   /* PREFIX_VEX_0FD4 */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { "vpaddq",         { XM, Vex, EXx }, 0 },
5106   },
5107
5108   /* PREFIX_VEX_0FD5 */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { "vpmullw",        { XM, Vex, EXx }, 0 },
5113   },
5114
5115   /* PREFIX_VEX_0FD6 */
5116   {
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5120   },
5121
5122   /* PREFIX_VEX_0FD7 */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5127   },
5128
5129   /* PREFIX_VEX_0FD8 */
5130   {
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5134   },
5135
5136   /* PREFIX_VEX_0FD9 */
5137   {
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5141   },
5142
5143   /* PREFIX_VEX_0FDA */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { "vpminub",        { XM, Vex, EXx }, 0 },
5148   },
5149
5150   /* PREFIX_VEX_0FDB */
5151   {
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { "vpand",          { XM, Vex, EXx }, 0 },
5155   },
5156
5157   /* PREFIX_VEX_0FDC */
5158   {
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5162   },
5163
5164   /* PREFIX_VEX_0FDD */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5169   },
5170
5171   /* PREFIX_VEX_0FDE */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5176   },
5177
5178   /* PREFIX_VEX_0FDF */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { "vpandn",         { XM, Vex, EXx }, 0 },
5183   },
5184
5185   /* PREFIX_VEX_0FE0 */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { "vpavgb",         { XM, Vex, EXx }, 0 },
5190   },
5191
5192   /* PREFIX_VEX_0FE1 */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5197   },
5198
5199   /* PREFIX_VEX_0FE2 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5204   },
5205
5206   /* PREFIX_VEX_0FE3 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { "vpavgw",         { XM, Vex, EXx }, 0 },
5211   },
5212
5213   /* PREFIX_VEX_0FE4 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5218   },
5219
5220   /* PREFIX_VEX_0FE5 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5225   },
5226
5227   /* PREFIX_VEX_0FE6 */
5228   {
5229     { Bad_Opcode },
5230     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5231     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5232     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5233   },
5234
5235   /* PREFIX_VEX_0FE7 */
5236   {
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5240   },
5241
5242   /* PREFIX_VEX_0FE8 */
5243   {
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5247   },
5248
5249   /* PREFIX_VEX_0FE9 */
5250   {
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5254   },
5255
5256   /* PREFIX_VEX_0FEA */
5257   {
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { "vpminsw",        { XM, Vex, EXx }, 0 },
5261   },
5262
5263   /* PREFIX_VEX_0FEB */
5264   {
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { "vpor",           { XM, Vex, EXx }, 0 },
5268   },
5269
5270   /* PREFIX_VEX_0FEC */
5271   {
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5275   },
5276
5277   /* PREFIX_VEX_0FED */
5278   {
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5282   },
5283
5284   /* PREFIX_VEX_0FEE */
5285   {
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5289   },
5290
5291   /* PREFIX_VEX_0FEF */
5292   {
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { "vpxor",          { XM, Vex, EXx }, 0 },
5296   },
5297
5298   /* PREFIX_VEX_0FF0 */
5299   {
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5304   },
5305
5306   /* PREFIX_VEX_0FF1 */
5307   {
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5311   },
5312
5313   /* PREFIX_VEX_0FF2 */
5314   {
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5318   },
5319
5320   /* PREFIX_VEX_0FF3 */
5321   {
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5325   },
5326
5327   /* PREFIX_VEX_0FF4 */
5328   {
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5332   },
5333
5334   /* PREFIX_VEX_0FF5 */
5335   {
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5339   },
5340
5341   /* PREFIX_VEX_0FF6 */
5342   {
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5346   },
5347
5348   /* PREFIX_VEX_0FF7 */
5349   {
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5353   },
5354
5355   /* PREFIX_VEX_0FF8 */
5356   {
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { "vpsubb",         { XM, Vex, EXx }, 0 },
5360   },
5361
5362   /* PREFIX_VEX_0FF9 */
5363   {
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { "vpsubw",         { XM, Vex, EXx }, 0 },
5367   },
5368
5369   /* PREFIX_VEX_0FFA */
5370   {
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { "vpsubd",         { XM, Vex, EXx }, 0 },
5374   },
5375
5376   /* PREFIX_VEX_0FFB */
5377   {
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { "vpsubq",         { XM, Vex, EXx }, 0 },
5381   },
5382
5383   /* PREFIX_VEX_0FFC */
5384   {
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { "vpaddb",         { XM, Vex, EXx }, 0 },
5388   },
5389
5390   /* PREFIX_VEX_0FFD */
5391   {
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { "vpaddw",         { XM, Vex, EXx }, 0 },
5395   },
5396
5397   /* PREFIX_VEX_0FFE */
5398   {
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { "vpaddd",         { XM, Vex, EXx }, 0 },
5402   },
5403
5404   /* PREFIX_VEX_0F3800 */
5405   {
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { "vpshufb",        { XM, Vex, EXx }, 0 },
5409   },
5410
5411   /* PREFIX_VEX_0F3801 */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { "vphaddw",        { XM, Vex, EXx }, 0 },
5416   },
5417
5418   /* PREFIX_VEX_0F3802 */
5419   {
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { "vphaddd",        { XM, Vex, EXx }, 0 },
5423   },
5424
5425   /* PREFIX_VEX_0F3803 */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5430   },
5431
5432   /* PREFIX_VEX_0F3804 */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5437   },
5438
5439   /* PREFIX_VEX_0F3805 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { "vphsubw",        { XM, Vex, EXx }, 0 },
5444   },
5445
5446   /* PREFIX_VEX_0F3806 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { "vphsubd",        { XM, Vex, EXx }, 0 },
5451   },
5452
5453   /* PREFIX_VEX_0F3807 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5458   },
5459
5460   /* PREFIX_VEX_0F3808 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { "vpsignb",        { XM, Vex, EXx }, 0 },
5465   },
5466
5467   /* PREFIX_VEX_0F3809 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { "vpsignw",        { XM, Vex, EXx }, 0 },
5472   },
5473
5474   /* PREFIX_VEX_0F380A */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { "vpsignd",        { XM, Vex, EXx }, 0 },
5479   },
5480
5481   /* PREFIX_VEX_0F380B */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5486   },
5487
5488   /* PREFIX_VEX_0F380C */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5493   },
5494
5495   /* PREFIX_VEX_0F380D */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5500   },
5501
5502   /* PREFIX_VEX_0F380E */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5507   },
5508
5509   /* PREFIX_VEX_0F380F */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5514   },
5515
5516   /* PREFIX_VEX_0F3813 */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0F3816 */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0F3817 */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { "vptest",         { XM, EXx }, 0 },
5535   },
5536
5537   /* PREFIX_VEX_0F3818 */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5542   },
5543
5544   /* PREFIX_VEX_0F3819 */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5549   },
5550
5551   /* PREFIX_VEX_0F381A */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5556   },
5557
5558   /* PREFIX_VEX_0F381C */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { "vpabsb",         { XM, EXx }, 0 },
5563   },
5564
5565   /* PREFIX_VEX_0F381D */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { "vpabsw",         { XM, EXx }, 0 },
5570   },
5571
5572   /* PREFIX_VEX_0F381E */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { "vpabsd",         { XM, EXx }, 0 },
5577   },
5578
5579   /* PREFIX_VEX_0F3820 */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5584   },
5585
5586   /* PREFIX_VEX_0F3821 */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5591   },
5592
5593   /* PREFIX_VEX_0F3822 */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5598   },
5599
5600   /* PREFIX_VEX_0F3823 */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5605   },
5606
5607   /* PREFIX_VEX_0F3824 */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5612   },
5613
5614   /* PREFIX_VEX_0F3825 */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5619   },
5620
5621   /* PREFIX_VEX_0F3828 */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5626   },
5627
5628   /* PREFIX_VEX_0F3829 */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5633   },
5634
5635   /* PREFIX_VEX_0F382A */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5640   },
5641
5642   /* PREFIX_VEX_0F382B */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5647   },
5648
5649   /* PREFIX_VEX_0F382C */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5654   },
5655
5656   /* PREFIX_VEX_0F382D */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5661   },
5662
5663   /* PREFIX_VEX_0F382E */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5668   },
5669
5670   /* PREFIX_VEX_0F382F */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5675   },
5676
5677   /* PREFIX_VEX_0F3830 */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5682   },
5683
5684   /* PREFIX_VEX_0F3831 */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5689   },
5690
5691   /* PREFIX_VEX_0F3832 */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5696   },
5697
5698   /* PREFIX_VEX_0F3833 */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5703   },
5704
5705   /* PREFIX_VEX_0F3834 */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5710   },
5711
5712   /* PREFIX_VEX_0F3835 */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5717   },
5718
5719   /* PREFIX_VEX_0F3836 */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5724   },
5725
5726   /* PREFIX_VEX_0F3837 */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5731   },
5732
5733   /* PREFIX_VEX_0F3838 */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { "vpminsb",        { XM, Vex, EXx }, 0 },
5738   },
5739
5740   /* PREFIX_VEX_0F3839 */
5741   {
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { "vpminsd",        { XM, Vex, EXx }, 0 },
5745   },
5746
5747   /* PREFIX_VEX_0F383A */
5748   {
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { "vpminuw",        { XM, Vex, EXx }, 0 },
5752   },
5753
5754   /* PREFIX_VEX_0F383B */
5755   {
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { "vpminud",        { XM, Vex, EXx }, 0 },
5759   },
5760
5761   /* PREFIX_VEX_0F383C */
5762   {
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5766   },
5767
5768   /* PREFIX_VEX_0F383D */
5769   {
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5773   },
5774
5775   /* PREFIX_VEX_0F383E */
5776   {
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5780   },
5781
5782   /* PREFIX_VEX_0F383F */
5783   {
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5787   },
5788
5789   /* PREFIX_VEX_0F3840 */
5790   {
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { "vpmulld",        { XM, Vex, EXx }, 0 },
5794   },
5795
5796   /* PREFIX_VEX_0F3841 */
5797   {
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5801   },
5802
5803   /* PREFIX_VEX_0F3845 */
5804   {
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5808   },
5809
5810   /* PREFIX_VEX_0F3846 */
5811   {
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5815   },
5816
5817   /* PREFIX_VEX_0F3847 */
5818   {
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5822   },
5823
5824   /* PREFIX_VEX_0F3858 */
5825   {
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5829   },
5830
5831   /* PREFIX_VEX_0F3859 */
5832   {
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5836   },
5837
5838   /* PREFIX_VEX_0F385A */
5839   {
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5843   },
5844
5845   /* PREFIX_VEX_0F3878 */
5846   {
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5850   },
5851
5852   /* PREFIX_VEX_0F3879 */
5853   {
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5857   },
5858
5859   /* PREFIX_VEX_0F388C */
5860   {
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5864   },
5865
5866   /* PREFIX_VEX_0F388E */
5867   {
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5871   },
5872
5873   /* PREFIX_VEX_0F3890 */
5874   {
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5878   },
5879
5880   /* PREFIX_VEX_0F3891 */
5881   {
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5885   },
5886
5887   /* PREFIX_VEX_0F3892 */
5888   {
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5892   },
5893
5894   /* PREFIX_VEX_0F3893 */
5895   {
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5899   },
5900
5901   /* PREFIX_VEX_0F3896 */
5902   {
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5906   },
5907
5908   /* PREFIX_VEX_0F3897 */
5909   {
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5913   },
5914
5915   /* PREFIX_VEX_0F3898 */
5916   {
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5920   },
5921
5922   /* PREFIX_VEX_0F3899 */
5923   {
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5927   },
5928
5929   /* PREFIX_VEX_0F389A */
5930   {
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5934   },
5935
5936   /* PREFIX_VEX_0F389B */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5941   },
5942
5943   /* PREFIX_VEX_0F389C */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5948   },
5949
5950   /* PREFIX_VEX_0F389D */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5955   },
5956
5957   /* PREFIX_VEX_0F389E */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5962   },
5963
5964   /* PREFIX_VEX_0F389F */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5969   },
5970
5971   /* PREFIX_VEX_0F38A6 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5976     { Bad_Opcode },
5977   },
5978
5979   /* PREFIX_VEX_0F38A7 */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5984   },
5985
5986   /* PREFIX_VEX_0F38A8 */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5991   },
5992
5993   /* PREFIX_VEX_0F38A9 */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5998   },
5999
6000   /* PREFIX_VEX_0F38AA */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6005   },
6006
6007   /* PREFIX_VEX_0F38AB */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6012   },
6013
6014   /* PREFIX_VEX_0F38AC */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6019   },
6020
6021   /* PREFIX_VEX_0F38AD */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6026   },
6027
6028   /* PREFIX_VEX_0F38AE */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6033   },
6034
6035   /* PREFIX_VEX_0F38AF */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6040   },
6041
6042   /* PREFIX_VEX_0F38B6 */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6047   },
6048
6049   /* PREFIX_VEX_0F38B7 */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6054   },
6055
6056   /* PREFIX_VEX_0F38B8 */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6061   },
6062
6063   /* PREFIX_VEX_0F38B9 */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6068   },
6069
6070   /* PREFIX_VEX_0F38BA */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6075   },
6076
6077   /* PREFIX_VEX_0F38BB */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6082   },
6083
6084   /* PREFIX_VEX_0F38BC */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6089   },
6090
6091   /* PREFIX_VEX_0F38BD */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6096   },
6097
6098   /* PREFIX_VEX_0F38BE */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6103   },
6104
6105   /* PREFIX_VEX_0F38BF */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F38CF */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6117   },
6118
6119   /* PREFIX_VEX_0F38DB */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6124   },
6125
6126   /* PREFIX_VEX_0F38DC */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vaesenc",        { XM, Vex, EXx }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38DD */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38DE */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vaesdec",        { XM, Vex, EXx }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38DF */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38F2 */
6155   {
6156     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6157   },
6158
6159   /* PREFIX_VEX_0F38F3_REG_1 */
6160   {
6161     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6162   },
6163
6164   /* PREFIX_VEX_0F38F3_REG_2 */
6165   {
6166     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6167   },
6168
6169   /* PREFIX_VEX_0F38F3_REG_3 */
6170   {
6171     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6172   },
6173
6174   /* PREFIX_VEX_0F38F5 */
6175   {
6176     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6177     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6178     { Bad_Opcode },
6179     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6180   },
6181
6182   /* PREFIX_VEX_0F38F6 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6188   },
6189
6190   /* PREFIX_VEX_0F38F7 */
6191   {
6192     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6193     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6194     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6195     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6196   },
6197
6198   /* PREFIX_VEX_0F3A00 */
6199   {
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6203   },
6204
6205   /* PREFIX_VEX_0F3A01 */
6206   {
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6210   },
6211
6212   /* PREFIX_VEX_0F3A02 */
6213   {
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6217   },
6218
6219   /* PREFIX_VEX_0F3A04 */
6220   {
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6224   },
6225
6226   /* PREFIX_VEX_0F3A05 */
6227   {
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6231   },
6232
6233   /* PREFIX_VEX_0F3A06 */
6234   {
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6238   },
6239
6240   /* PREFIX_VEX_0F3A08 */
6241   {
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { "vroundps",       { XM, EXx, Ib }, 0 },
6245   },
6246
6247   /* PREFIX_VEX_0F3A09 */
6248   {
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { "vroundpd",       { XM, EXx, Ib }, 0 },
6252   },
6253
6254   /* PREFIX_VEX_0F3A0A */
6255   {
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6259   },
6260
6261   /* PREFIX_VEX_0F3A0B */
6262   {
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6266   },
6267
6268   /* PREFIX_VEX_0F3A0C */
6269   {
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6273   },
6274
6275   /* PREFIX_VEX_0F3A0D */
6276   {
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6280   },
6281
6282   /* PREFIX_VEX_0F3A0E */
6283   {
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6287   },
6288
6289   /* PREFIX_VEX_0F3A0F */
6290   {
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6294   },
6295
6296   /* PREFIX_VEX_0F3A14 */
6297   {
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6301   },
6302
6303   /* PREFIX_VEX_0F3A15 */
6304   {
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6308   },
6309
6310   /* PREFIX_VEX_0F3A16 */
6311   {
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6315   },
6316
6317   /* PREFIX_VEX_0F3A17 */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A18 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A19 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A1D */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A20 */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6350   },
6351
6352   /* PREFIX_VEX_0F3A21 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6357   },
6358
6359   /* PREFIX_VEX_0F3A22 */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6364   },
6365
6366   /* PREFIX_VEX_0F3A30 */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6371   },
6372
6373   /* PREFIX_VEX_0F3A31 */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6378   },
6379
6380   /* PREFIX_VEX_0F3A32 */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6385   },
6386
6387   /* PREFIX_VEX_0F3A33 */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6392   },
6393
6394   /* PREFIX_VEX_0F3A38 */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6399   },
6400
6401   /* PREFIX_VEX_0F3A39 */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6406   },
6407
6408   /* PREFIX_VEX_0F3A40 */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6413   },
6414
6415   /* PREFIX_VEX_0F3A41 */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A42 */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6427   },
6428
6429   /* PREFIX_VEX_0F3A44 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6434   },
6435
6436   /* PREFIX_VEX_0F3A46 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A48 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A49 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A4A */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6462   },
6463
6464   /* PREFIX_VEX_0F3A4B */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A4C */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A5C */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6483   },
6484
6485   /* PREFIX_VEX_0F3A5D */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6490   },
6491
6492   /* PREFIX_VEX_0F3A5E */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6497   },
6498
6499   /* PREFIX_VEX_0F3A5F */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6504   },
6505
6506   /* PREFIX_VEX_0F3A60 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6511     { Bad_Opcode },
6512   },
6513
6514   /* PREFIX_VEX_0F3A61 */
6515   {
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6519   },
6520
6521   /* PREFIX_VEX_0F3A62 */
6522   {
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6526   },
6527
6528   /* PREFIX_VEX_0F3A63 */
6529   {
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6533   },
6534
6535   /* PREFIX_VEX_0F3A68 */
6536   {
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6540   },
6541
6542   /* PREFIX_VEX_0F3A69 */
6543   {
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6547   },
6548
6549   /* PREFIX_VEX_0F3A6A */
6550   {
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6554   },
6555
6556   /* PREFIX_VEX_0F3A6B */
6557   {
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6561   },
6562
6563   /* PREFIX_VEX_0F3A6C */
6564   {
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6568   },
6569
6570   /* PREFIX_VEX_0F3A6D */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6575   },
6576
6577   /* PREFIX_VEX_0F3A6E */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6582   },
6583
6584   /* PREFIX_VEX_0F3A6F */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A78 */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6596   },
6597
6598   /* PREFIX_VEX_0F3A79 */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6603   },
6604
6605   /* PREFIX_VEX_0F3A7A */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6610   },
6611
6612   /* PREFIX_VEX_0F3A7B */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6617   },
6618
6619   /* PREFIX_VEX_0F3A7C */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6624     { Bad_Opcode },
6625   },
6626
6627   /* PREFIX_VEX_0F3A7D */
6628   {
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6632   },
6633
6634   /* PREFIX_VEX_0F3A7E */
6635   {
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6639   },
6640
6641   /* PREFIX_VEX_0F3A7F */
6642   {
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6646   },
6647
6648   /* PREFIX_VEX_0F3ACE */
6649   {
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6653   },
6654
6655   /* PREFIX_VEX_0F3ACF */
6656   {
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6660   },
6661
6662   /* PREFIX_VEX_0F3ADF */
6663   {
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6667   },
6668
6669   /* PREFIX_VEX_0F3AF0 */
6670   {
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6675   },
6676
6677 #include "i386-dis-evex-prefix.h"
6678 };
6679
6680 static const struct dis386 x86_64_table[][2] = {
6681   /* X86_64_06 */
6682   {
6683     { "pushP", { es }, 0 },
6684   },
6685
6686   /* X86_64_07 */
6687   {
6688     { "popP", { es }, 0 },
6689   },
6690
6691   /* X86_64_0E */
6692   {
6693     { "pushP", { cs }, 0 },
6694   },
6695
6696   /* X86_64_16 */
6697   {
6698     { "pushP", { ss }, 0 },
6699   },
6700
6701   /* X86_64_17 */
6702   {
6703     { "popP", { ss }, 0 },
6704   },
6705
6706   /* X86_64_1E */
6707   {
6708     { "pushP", { ds }, 0 },
6709   },
6710
6711   /* X86_64_1F */
6712   {
6713     { "popP", { ds }, 0 },
6714   },
6715
6716   /* X86_64_27 */
6717   {
6718     { "daa", { XX }, 0 },
6719   },
6720
6721   /* X86_64_2F */
6722   {
6723     { "das", { XX }, 0 },
6724   },
6725
6726   /* X86_64_37 */
6727   {
6728     { "aaa", { XX }, 0 },
6729   },
6730
6731   /* X86_64_3F */
6732   {
6733     { "aas", { XX }, 0 },
6734   },
6735
6736   /* X86_64_60 */
6737   {
6738     { "pushaP", { XX }, 0 },
6739   },
6740
6741   /* X86_64_61 */
6742   {
6743     { "popaP", { XX }, 0 },
6744   },
6745
6746   /* X86_64_62 */
6747   {
6748     { MOD_TABLE (MOD_62_32BIT) },
6749     { EVEX_TABLE (EVEX_0F) },
6750   },
6751
6752   /* X86_64_63 */
6753   {
6754     { "arpl", { Ew, Gw }, 0 },
6755     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6756   },
6757
6758   /* X86_64_6D */
6759   {
6760     { "ins{R|}", { Yzr, indirDX }, 0 },
6761     { "ins{G|}", { Yzr, indirDX }, 0 },
6762   },
6763
6764   /* X86_64_6F */
6765   {
6766     { "outs{R|}", { indirDXr, Xz }, 0 },
6767     { "outs{G|}", { indirDXr, Xz }, 0 },
6768   },
6769
6770   /* X86_64_82 */
6771   {
6772     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6773     { REG_TABLE (REG_80) },
6774   },
6775
6776   /* X86_64_9A */
6777   {
6778     { "{l|}call{T|}", { Ap }, 0 },
6779   },
6780
6781   /* X86_64_C2 */
6782   {
6783     { "retP",           { Iw, BND }, 0 },
6784     { "ret@",           { Iw, BND }, 0 },
6785   },
6786
6787   /* X86_64_C3 */
6788   {
6789     { "retP",           { BND }, 0 },
6790     { "ret@",           { BND }, 0 },
6791   },
6792
6793   /* X86_64_C4 */
6794   {
6795     { MOD_TABLE (MOD_C4_32BIT) },
6796     { VEX_C4_TABLE (VEX_0F) },
6797   },
6798
6799   /* X86_64_C5 */
6800   {
6801     { MOD_TABLE (MOD_C5_32BIT) },
6802     { VEX_C5_TABLE (VEX_0F) },
6803   },
6804
6805   /* X86_64_CE */
6806   {
6807     { "into", { XX }, 0 },
6808   },
6809
6810   /* X86_64_D4 */
6811   {
6812     { "aam", { Ib }, 0 },
6813   },
6814
6815   /* X86_64_D5 */
6816   {
6817     { "aad", { Ib }, 0 },
6818   },
6819
6820   /* X86_64_E8 */
6821   {
6822     { "callP",          { Jv, BND }, 0 },
6823     { "call@",          { Jv, BND }, 0 }
6824   },
6825
6826   /* X86_64_E9 */
6827   {
6828     { "jmpP",           { Jv, BND }, 0 },
6829     { "jmp@",           { Jv, BND }, 0 }
6830   },
6831
6832   /* X86_64_EA */
6833   {
6834     { "{l|}jmp{T|}", { Ap }, 0 },
6835   },
6836
6837   /* X86_64_0F01_REG_0 */
6838   {
6839     { "sgdt{Q|Q}", { M }, 0 },
6840     { "sgdt", { M }, 0 },
6841   },
6842
6843   /* X86_64_0F01_REG_1 */
6844   {
6845     { "sidt{Q|Q}", { M }, 0 },
6846     { "sidt", { M }, 0 },
6847   },
6848
6849   /* X86_64_0F01_REG_2 */
6850   {
6851     { "lgdt{Q|Q}", { M }, 0 },
6852     { "lgdt", { M }, 0 },
6853   },
6854
6855   /* X86_64_0F01_REG_3 */
6856   {
6857     { "lidt{Q|Q}", { M }, 0 },
6858     { "lidt", { M }, 0 },
6859   },
6860 };
6861
6862 static const struct dis386 three_byte_table[][256] = {
6863
6864   /* THREE_BYTE_0F38 */
6865   {
6866     /* 00 */
6867     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6868     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6869     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6870     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6871     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6872     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6873     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6874     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6875     /* 08 */
6876     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6877     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6878     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6879     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     /* 10 */
6885     { PREFIX_TABLE (PREFIX_0F3810) },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { PREFIX_TABLE (PREFIX_0F3814) },
6890     { PREFIX_TABLE (PREFIX_0F3815) },
6891     { Bad_Opcode },
6892     { PREFIX_TABLE (PREFIX_0F3817) },
6893     /* 18 */
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6899     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6900     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6901     { Bad_Opcode },
6902     /* 20 */
6903     { PREFIX_TABLE (PREFIX_0F3820) },
6904     { PREFIX_TABLE (PREFIX_0F3821) },
6905     { PREFIX_TABLE (PREFIX_0F3822) },
6906     { PREFIX_TABLE (PREFIX_0F3823) },
6907     { PREFIX_TABLE (PREFIX_0F3824) },
6908     { PREFIX_TABLE (PREFIX_0F3825) },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     /* 28 */
6912     { PREFIX_TABLE (PREFIX_0F3828) },
6913     { PREFIX_TABLE (PREFIX_0F3829) },
6914     { PREFIX_TABLE (PREFIX_0F382A) },
6915     { PREFIX_TABLE (PREFIX_0F382B) },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     /* 30 */
6921     { PREFIX_TABLE (PREFIX_0F3830) },
6922     { PREFIX_TABLE (PREFIX_0F3831) },
6923     { PREFIX_TABLE (PREFIX_0F3832) },
6924     { PREFIX_TABLE (PREFIX_0F3833) },
6925     { PREFIX_TABLE (PREFIX_0F3834) },
6926     { PREFIX_TABLE (PREFIX_0F3835) },
6927     { Bad_Opcode },
6928     { PREFIX_TABLE (PREFIX_0F3837) },
6929     /* 38 */
6930     { PREFIX_TABLE (PREFIX_0F3838) },
6931     { PREFIX_TABLE (PREFIX_0F3839) },
6932     { PREFIX_TABLE (PREFIX_0F383A) },
6933     { PREFIX_TABLE (PREFIX_0F383B) },
6934     { PREFIX_TABLE (PREFIX_0F383C) },
6935     { PREFIX_TABLE (PREFIX_0F383D) },
6936     { PREFIX_TABLE (PREFIX_0F383E) },
6937     { PREFIX_TABLE (PREFIX_0F383F) },
6938     /* 40 */
6939     { PREFIX_TABLE (PREFIX_0F3840) },
6940     { PREFIX_TABLE (PREFIX_0F3841) },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     /* 48 */
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     /* 50 */
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     /* 58 */
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     /* 60 */
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     /* 68 */
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     /* 70 */
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     /* 78 */
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     /* 80 */
7011     { PREFIX_TABLE (PREFIX_0F3880) },
7012     { PREFIX_TABLE (PREFIX_0F3881) },
7013     { PREFIX_TABLE (PREFIX_0F3882) },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     /* 88 */
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     /* 90 */
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     /* 98 */
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     /* a0 */
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     /* a8 */
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     /* b0 */
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     /* b8 */
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* c0 */
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     /* c8 */
7092     { PREFIX_TABLE (PREFIX_0F38C8) },
7093     { PREFIX_TABLE (PREFIX_0F38C9) },
7094     { PREFIX_TABLE (PREFIX_0F38CA) },
7095     { PREFIX_TABLE (PREFIX_0F38CB) },
7096     { PREFIX_TABLE (PREFIX_0F38CC) },
7097     { PREFIX_TABLE (PREFIX_0F38CD) },
7098     { Bad_Opcode },
7099     { PREFIX_TABLE (PREFIX_0F38CF) },
7100     /* d0 */
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     /* d8 */
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { PREFIX_TABLE (PREFIX_0F38DB) },
7114     { PREFIX_TABLE (PREFIX_0F38DC) },
7115     { PREFIX_TABLE (PREFIX_0F38DD) },
7116     { PREFIX_TABLE (PREFIX_0F38DE) },
7117     { PREFIX_TABLE (PREFIX_0F38DF) },
7118     /* e0 */
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     /* e8 */
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     /* f0 */
7137     { PREFIX_TABLE (PREFIX_0F38F0) },
7138     { PREFIX_TABLE (PREFIX_0F38F1) },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { PREFIX_TABLE (PREFIX_0F38F5) },
7143     { PREFIX_TABLE (PREFIX_0F38F6) },
7144     { Bad_Opcode },
7145     /* f8 */
7146     { PREFIX_TABLE (PREFIX_0F38F8) },
7147     { PREFIX_TABLE (PREFIX_0F38F9) },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154   },
7155   /* THREE_BYTE_0F3A */
7156   {
7157     /* 00 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* 08 */
7167     { PREFIX_TABLE (PREFIX_0F3A08) },
7168     { PREFIX_TABLE (PREFIX_0F3A09) },
7169     { PREFIX_TABLE (PREFIX_0F3A0A) },
7170     { PREFIX_TABLE (PREFIX_0F3A0B) },
7171     { PREFIX_TABLE (PREFIX_0F3A0C) },
7172     { PREFIX_TABLE (PREFIX_0F3A0D) },
7173     { PREFIX_TABLE (PREFIX_0F3A0E) },
7174     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7175     /* 10 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { PREFIX_TABLE (PREFIX_0F3A14) },
7181     { PREFIX_TABLE (PREFIX_0F3A15) },
7182     { PREFIX_TABLE (PREFIX_0F3A16) },
7183     { PREFIX_TABLE (PREFIX_0F3A17) },
7184     /* 18 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* 20 */
7194     { PREFIX_TABLE (PREFIX_0F3A20) },
7195     { PREFIX_TABLE (PREFIX_0F3A21) },
7196     { PREFIX_TABLE (PREFIX_0F3A22) },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* 28 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 30 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 38 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* 40 */
7230     { PREFIX_TABLE (PREFIX_0F3A40) },
7231     { PREFIX_TABLE (PREFIX_0F3A41) },
7232     { PREFIX_TABLE (PREFIX_0F3A42) },
7233     { Bad_Opcode },
7234     { PREFIX_TABLE (PREFIX_0F3A44) },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 48 */
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* 50 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* 58 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* 60 */
7266     { PREFIX_TABLE (PREFIX_0F3A60) },
7267     { PREFIX_TABLE (PREFIX_0F3A61) },
7268     { PREFIX_TABLE (PREFIX_0F3A62) },
7269     { PREFIX_TABLE (PREFIX_0F3A63) },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 68 */
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* 70 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* 78 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* 80 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* 88 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* 90 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* 98 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* a0 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* a8 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* b0 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* b8 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* c0 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* c8 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { PREFIX_TABLE (PREFIX_0F3ACC) },
7388     { Bad_Opcode },
7389     { PREFIX_TABLE (PREFIX_0F3ACE) },
7390     { PREFIX_TABLE (PREFIX_0F3ACF) },
7391     /* d0 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* d8 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { PREFIX_TABLE (PREFIX_0F3ADF) },
7409     /* e0 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     /* e8 */
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     /* f0 */
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     /* f8 */
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445   },
7446 };
7447
7448 static const struct dis386 xop_table[][256] = {
7449   /* XOP_08 */
7450   {
7451     /* 00 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* 08 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* 10 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* 18 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* 20 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     /* 28 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* 30 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* 38 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* 40 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* 48 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* 50 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* 58 */
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     /* 60 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     /* 68 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     /* 70 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     /* 78 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     /* 80 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7602     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7603     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7604     /* 88 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7612     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7613     /* 90 */
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7620     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7621     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7622     /* 98 */
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7630     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7631     /* a0 */
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7635     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7639     { Bad_Opcode },
7640     /* a8 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     /* b0 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7657     { Bad_Opcode },
7658     /* b8 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* c0 */
7668     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7669     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7670     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7671     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     /* c8 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7682     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7683     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7684     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7685     /* d0 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* d8 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     /* e0 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     /* e8 */
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7718     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7719     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7720     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7721     /* f0 */
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     /* f8 */
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739   },
7740   /* XOP_09 */
7741   {
7742     /* 00 */
7743     { Bad_Opcode },
7744     { REG_TABLE (REG_XOP_TBM_01) },
7745     { REG_TABLE (REG_XOP_TBM_02) },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* 08 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* 10 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { REG_TABLE (REG_XOP_LWPCB) },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* 18 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* 20 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* 28 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* 30 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* 38 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* 40 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     /* 48 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* 50 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 58 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 60 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 68 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* 70 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     /* 78 */
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* 80 */
7887     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7888     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7889     { "vfrczss",        { XM, EXd }, 0 },
7890     { "vfrczsd",        { XM, EXq }, 0 },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* 88 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* 90 */
7905     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7906     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7907     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7908     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7909     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7910     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7911     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7912     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7913     /* 98 */
7914     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7915     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7916     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7917     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* a0 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* a8 */
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* b0 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     /* b8 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     /* c0 */
7959     { Bad_Opcode },
7960     { "vphaddbw",       { XM, EXxmm }, 0 },
7961     { "vphaddbd",       { XM, EXxmm }, 0 },
7962     { "vphaddbq",       { XM, EXxmm }, 0 },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { "vphaddwd",       { XM, EXxmm }, 0 },
7966     { "vphaddwq",       { XM, EXxmm }, 0 },
7967     /* c8 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { "vphadddq",       { XM, EXxmm }, 0 },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* d0 */
7977     { Bad_Opcode },
7978     { "vphaddubw",      { XM, EXxmm }, 0 },
7979     { "vphaddubd",      { XM, EXxmm }, 0 },
7980     { "vphaddubq",      { XM, EXxmm }, 0 },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { "vphadduwd",      { XM, EXxmm }, 0 },
7984     { "vphadduwq",      { XM, EXxmm }, 0 },
7985     /* d8 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { "vphaddudq",      { XM, EXxmm }, 0 },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* e0 */
7995     { Bad_Opcode },
7996     { "vphsubbw",       { XM, EXxmm }, 0 },
7997     { "vphsubwd",       { XM, EXxmm }, 0 },
7998     { "vphsubdq",       { XM, EXxmm }, 0 },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     /* e8 */
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     /* f0 */
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     /* f8 */
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030   },
8031   /* XOP_0A */
8032   {
8033     /* 00 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* 08 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* 10 */
8052     { "bextrS", { Gdq, Edq, Id }, 0 },
8053     { Bad_Opcode },
8054     { REG_TABLE (REG_XOP_LWP) },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* 18 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* 20 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* 28 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* 30 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* 38 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* 40 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* 48 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* 50 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 58 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 60 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 68 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 70 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* 78 */
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* 80 */
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* 88 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* 90 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* 98 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* a0 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* a8 */
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     /* b0 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* b8 */
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* c0 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* c8 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* d0 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* d8 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* e0 */
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     /* e8 */
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     /* f0 */
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     /* f8 */
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321   },
8322 };
8323
8324 static const struct dis386 vex_table[][256] = {
8325   /* VEX_0F */
8326   {
8327     /* 00 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* 08 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* 10 */
8346     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8347     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8348     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8349     { MOD_TABLE (MOD_VEX_0F13) },
8350     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8351     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8352     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8353     { MOD_TABLE (MOD_VEX_0F17) },
8354     /* 18 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* 20 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* 28 */
8373     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8374     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8375     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8376     { MOD_TABLE (MOD_VEX_0F2B) },
8377     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8378     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8379     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8380     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8381     /* 30 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* 38 */
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     /* 40 */
8400     { Bad_Opcode },
8401     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8402     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8403     { Bad_Opcode },
8404     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8405     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8406     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8407     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8408     /* 48 */
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8412     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     /* 50 */
8418     { MOD_TABLE (MOD_VEX_0F50) },
8419     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8422     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8423     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8424     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8425     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8426     /* 58 */
8427     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8433     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8434     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8435     /* 60 */
8436     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8437     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8438     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8439     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8440     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8441     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8442     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8443     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8444     /* 68 */
8445     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8446     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8447     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8449     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8450     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8451     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8453     /* 70 */
8454     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8455     { REG_TABLE (REG_VEX_0F71) },
8456     { REG_TABLE (REG_VEX_0F72) },
8457     { REG_TABLE (REG_VEX_0F73) },
8458     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8459     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8460     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8461     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8462     /* 78 */
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8468     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8469     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8470     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8471     /* 80 */
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     /* 88 */
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     /* 90 */
8490     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8491     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8492     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8493     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     /* 98 */
8499     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8500     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     /* a0 */
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     /* a8 */
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { REG_TABLE (REG_VEX_0FAE) },
8524     { Bad_Opcode },
8525     /* b0 */
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     /* b8 */
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     /* c0 */
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8547     { Bad_Opcode },
8548     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8549     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8550     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8551     { Bad_Opcode },
8552     /* c8 */
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     /* d0 */
8562     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8566     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8569     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8570     /* d8 */
8571     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8575     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8576     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8577     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8578     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8579     /* e0 */
8580     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8584     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8585     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8586     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8587     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8588     /* e8 */
8589     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8592     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8593     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8594     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8595     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8596     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8597     /* f0 */
8598     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8599     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8600     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8601     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8602     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8603     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8604     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8605     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8606     /* f8 */
8607     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8608     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8609     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8610     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8611     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8612     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8613     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8614     { Bad_Opcode },
8615   },
8616   /* VEX_0F38 */
8617   {
8618     /* 00 */
8619     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8623     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8627     /* 08 */
8628     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8633     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8636     /* 10 */
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8645     /* 18 */
8646     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8649     { Bad_Opcode },
8650     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8653     { Bad_Opcode },
8654     /* 20 */
8655     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     /* 28 */
8664     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8672     /* 30 */
8673     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8677     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8681     /* 38 */
8682     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8686     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8687     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8688     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8689     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8690     /* 40 */
8691     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8699     /* 48 */
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     /* 50 */
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     /* 58 */
8718     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     /* 60 */
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     /* 68 */
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     /* 70 */
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     /* 78 */
8754     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     /* 80 */
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     /* 88 */
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8777     { Bad_Opcode },
8778     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8779     { Bad_Opcode },
8780     /* 90 */
8781     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8789     /* 98 */
8790     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8798     /* a0 */
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8807     /* a8 */
8808     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8816     /* b0 */
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8825     /* b8 */
8826     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8834     /* c0 */
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     /* c8 */
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8852     /* d0 */
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     /* d8 */
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8870     /* e0 */
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     /* e8 */
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     /* f0 */
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8892     { REG_TABLE (REG_VEX_0F38F3) },
8893     { Bad_Opcode },
8894     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8897     /* f8 */
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906   },
8907   /* VEX_0F3A */
8908   {
8909     /* 00 */
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8913     { Bad_Opcode },
8914     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8917     { Bad_Opcode },
8918     /* 08 */
8919     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8927     /* 10 */
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8936     /* 18 */
8937     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     /* 20 */
8946     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     /* 28 */
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     /* 30 */
8964     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     /* 38 */
8973     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     /* 40 */
8982     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8985     { Bad_Opcode },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8987     { Bad_Opcode },
8988     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8989     { Bad_Opcode },
8990     /* 48 */
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     /* 50 */
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     /* 58 */
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9017     /* 60 */
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     /* 68 */
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9035     /* 70 */
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     /* 78 */
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9053     /* 80 */
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     /* 88 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     /* 90 */
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     /* 98 */
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     /* a0 */
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     /* a8 */
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     /* b0 */
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     /* b8 */
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     /* c0 */
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     /* c8 */
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9142     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9143     /* d0 */
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     /* d8 */
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9161     /* e0 */
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     /* e8 */
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     /* f0 */
9180     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     /* f8 */
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197   },
9198 };
9199
9200 #include "i386-dis-evex.h"
9201
9202 static const struct dis386 vex_len_table[][2] = {
9203   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9204   {
9205     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9206   },
9207
9208   /* VEX_LEN_0F12_P_0_M_1 */
9209   {
9210     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9211   },
9212
9213   /* VEX_LEN_0F13_M_0 */
9214   {
9215     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9216   },
9217
9218   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9219   {
9220     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9221   },
9222
9223   /* VEX_LEN_0F16_P_0_M_1 */
9224   {
9225     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9226   },
9227
9228   /* VEX_LEN_0F17_M_0 */
9229   {
9230     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9231   },
9232
9233   /* VEX_LEN_0F41_P_0 */
9234   {
9235     { Bad_Opcode },
9236     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9237   },
9238   /* VEX_LEN_0F41_P_2 */
9239   {
9240     { Bad_Opcode },
9241     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9242   },
9243   /* VEX_LEN_0F42_P_0 */
9244   {
9245     { Bad_Opcode },
9246     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9247   },
9248   /* VEX_LEN_0F42_P_2 */
9249   {
9250     { Bad_Opcode },
9251     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9252   },
9253   /* VEX_LEN_0F44_P_0 */
9254   {
9255     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9256   },
9257   /* VEX_LEN_0F44_P_2 */
9258   {
9259     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9260   },
9261   /* VEX_LEN_0F45_P_0 */
9262   {
9263     { Bad_Opcode },
9264     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9265   },
9266   /* VEX_LEN_0F45_P_2 */
9267   {
9268     { Bad_Opcode },
9269     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9270   },
9271   /* VEX_LEN_0F46_P_0 */
9272   {
9273     { Bad_Opcode },
9274     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9275   },
9276   /* VEX_LEN_0F46_P_2 */
9277   {
9278     { Bad_Opcode },
9279     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9280   },
9281   /* VEX_LEN_0F47_P_0 */
9282   {
9283     { Bad_Opcode },
9284     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9285   },
9286   /* VEX_LEN_0F47_P_2 */
9287   {
9288     { Bad_Opcode },
9289     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9290   },
9291   /* VEX_LEN_0F4A_P_0 */
9292   {
9293     { Bad_Opcode },
9294     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9295   },
9296   /* VEX_LEN_0F4A_P_2 */
9297   {
9298     { Bad_Opcode },
9299     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9300   },
9301   /* VEX_LEN_0F4B_P_0 */
9302   {
9303     { Bad_Opcode },
9304     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9305   },
9306   /* VEX_LEN_0F4B_P_2 */
9307   {
9308     { Bad_Opcode },
9309     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9310   },
9311
9312   /* VEX_LEN_0F6E_P_2 */
9313   {
9314     { "vmovK",          { XMScalar, Edq }, 0 },
9315   },
9316
9317   /* VEX_LEN_0F77_P_1 */
9318   {
9319     { "vzeroupper",     { XX }, 0 },
9320     { "vzeroall",       { XX }, 0 },
9321   },
9322
9323   /* VEX_LEN_0F7E_P_1 */
9324   {
9325     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9326   },
9327
9328   /* VEX_LEN_0F7E_P_2 */
9329   {
9330     { "vmovK",          { Edq, XMScalar }, 0 },
9331   },
9332
9333   /* VEX_LEN_0F90_P_0 */
9334   {
9335     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9336   },
9337
9338   /* VEX_LEN_0F90_P_2 */
9339   {
9340     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9341   },
9342
9343   /* VEX_LEN_0F91_P_0 */
9344   {
9345     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9346   },
9347
9348   /* VEX_LEN_0F91_P_2 */
9349   {
9350     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9351   },
9352
9353   /* VEX_LEN_0F92_P_0 */
9354   {
9355     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9356   },
9357
9358   /* VEX_LEN_0F92_P_2 */
9359   {
9360     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9361   },
9362
9363   /* VEX_LEN_0F92_P_3 */
9364   {
9365     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9366   },
9367
9368   /* VEX_LEN_0F93_P_0 */
9369   {
9370     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9371   },
9372
9373   /* VEX_LEN_0F93_P_2 */
9374   {
9375     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9376   },
9377
9378   /* VEX_LEN_0F93_P_3 */
9379   {
9380     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9381   },
9382
9383   /* VEX_LEN_0F98_P_0 */
9384   {
9385     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9386   },
9387
9388   /* VEX_LEN_0F98_P_2 */
9389   {
9390     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9391   },
9392
9393   /* VEX_LEN_0F99_P_0 */
9394   {
9395     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9396   },
9397
9398   /* VEX_LEN_0F99_P_2 */
9399   {
9400     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9401   },
9402
9403   /* VEX_LEN_0FAE_R_2_M_0 */
9404   {
9405     { "vldmxcsr",       { Md }, 0 },
9406   },
9407
9408   /* VEX_LEN_0FAE_R_3_M_0 */
9409   {
9410     { "vstmxcsr",       { Md }, 0 },
9411   },
9412
9413   /* VEX_LEN_0FC4_P_2 */
9414   {
9415     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9416   },
9417
9418   /* VEX_LEN_0FC5_P_2 */
9419   {
9420     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9421   },
9422
9423   /* VEX_LEN_0FD6_P_2 */
9424   {
9425     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9426   },
9427
9428   /* VEX_LEN_0FF7_P_2 */
9429   {
9430     { "vmaskmovdqu",    { XM, XS }, 0 },
9431   },
9432
9433   /* VEX_LEN_0F3816_P_2 */
9434   {
9435     { Bad_Opcode },
9436     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9437   },
9438
9439   /* VEX_LEN_0F3819_P_2 */
9440   {
9441     { Bad_Opcode },
9442     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9443   },
9444
9445   /* VEX_LEN_0F381A_P_2_M_0 */
9446   {
9447     { Bad_Opcode },
9448     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9449   },
9450
9451   /* VEX_LEN_0F3836_P_2 */
9452   {
9453     { Bad_Opcode },
9454     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9455   },
9456
9457   /* VEX_LEN_0F3841_P_2 */
9458   {
9459     { "vphminposuw",    { XM, EXx }, 0 },
9460   },
9461
9462   /* VEX_LEN_0F385A_P_2_M_0 */
9463   {
9464     { Bad_Opcode },
9465     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9466   },
9467
9468   /* VEX_LEN_0F38DB_P_2 */
9469   {
9470     { "vaesimc",        { XM, EXx }, 0 },
9471   },
9472
9473   /* VEX_LEN_0F38F2_P_0 */
9474   {
9475     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9476   },
9477
9478   /* VEX_LEN_0F38F3_R_1_P_0 */
9479   {
9480     { "blsrS",          { VexGdq, Edq }, 0 },
9481   },
9482
9483   /* VEX_LEN_0F38F3_R_2_P_0 */
9484   {
9485     { "blsmskS",        { VexGdq, Edq }, 0 },
9486   },
9487
9488   /* VEX_LEN_0F38F3_R_3_P_0 */
9489   {
9490     { "blsiS",          { VexGdq, Edq }, 0 },
9491   },
9492
9493   /* VEX_LEN_0F38F5_P_0 */
9494   {
9495     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9496   },
9497
9498   /* VEX_LEN_0F38F5_P_1 */
9499   {
9500     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9501   },
9502
9503   /* VEX_LEN_0F38F5_P_3 */
9504   {
9505     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9506   },
9507
9508   /* VEX_LEN_0F38F6_P_3 */
9509   {
9510     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9511   },
9512
9513   /* VEX_LEN_0F38F7_P_0 */
9514   {
9515     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9516   },
9517
9518   /* VEX_LEN_0F38F7_P_1 */
9519   {
9520     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9521   },
9522
9523   /* VEX_LEN_0F38F7_P_2 */
9524   {
9525     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9526   },
9527
9528   /* VEX_LEN_0F38F7_P_3 */
9529   {
9530     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9531   },
9532
9533   /* VEX_LEN_0F3A00_P_2 */
9534   {
9535     { Bad_Opcode },
9536     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9537   },
9538
9539   /* VEX_LEN_0F3A01_P_2 */
9540   {
9541     { Bad_Opcode },
9542     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9543   },
9544
9545   /* VEX_LEN_0F3A06_P_2 */
9546   {
9547     { Bad_Opcode },
9548     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9549   },
9550
9551   /* VEX_LEN_0F3A14_P_2 */
9552   {
9553     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9554   },
9555
9556   /* VEX_LEN_0F3A15_P_2 */
9557   {
9558     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9559   },
9560
9561   /* VEX_LEN_0F3A16_P_2  */
9562   {
9563     { "vpextrK",        { Edq, XM, Ib }, 0 },
9564   },
9565
9566   /* VEX_LEN_0F3A17_P_2 */
9567   {
9568     { "vextractps",     { Edqd, XM, Ib }, 0 },
9569   },
9570
9571   /* VEX_LEN_0F3A18_P_2 */
9572   {
9573     { Bad_Opcode },
9574     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9575   },
9576
9577   /* VEX_LEN_0F3A19_P_2 */
9578   {
9579     { Bad_Opcode },
9580     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9581   },
9582
9583   /* VEX_LEN_0F3A20_P_2 */
9584   {
9585     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9586   },
9587
9588   /* VEX_LEN_0F3A21_P_2 */
9589   {
9590     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9591   },
9592
9593   /* VEX_LEN_0F3A22_P_2 */
9594   {
9595     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9596   },
9597
9598   /* VEX_LEN_0F3A30_P_2 */
9599   {
9600     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9601   },
9602
9603   /* VEX_LEN_0F3A31_P_2 */
9604   {
9605     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9606   },
9607
9608   /* VEX_LEN_0F3A32_P_2 */
9609   {
9610     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9611   },
9612
9613   /* VEX_LEN_0F3A33_P_2 */
9614   {
9615     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9616   },
9617
9618   /* VEX_LEN_0F3A38_P_2 */
9619   {
9620     { Bad_Opcode },
9621     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9622   },
9623
9624   /* VEX_LEN_0F3A39_P_2 */
9625   {
9626     { Bad_Opcode },
9627     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9628   },
9629
9630   /* VEX_LEN_0F3A41_P_2 */
9631   {
9632     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9633   },
9634
9635   /* VEX_LEN_0F3A46_P_2 */
9636   {
9637     { Bad_Opcode },
9638     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9639   },
9640
9641   /* VEX_LEN_0F3A60_P_2 */
9642   {
9643     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9644   },
9645
9646   /* VEX_LEN_0F3A61_P_2 */
9647   {
9648     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9649   },
9650
9651   /* VEX_LEN_0F3A62_P_2 */
9652   {
9653     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9654   },
9655
9656   /* VEX_LEN_0F3A63_P_2 */
9657   {
9658     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9659   },
9660
9661   /* VEX_LEN_0F3A6A_P_2 */
9662   {
9663     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9664   },
9665
9666   /* VEX_LEN_0F3A6B_P_2 */
9667   {
9668     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9669   },
9670
9671   /* VEX_LEN_0F3A6E_P_2 */
9672   {
9673     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9674   },
9675
9676   /* VEX_LEN_0F3A6F_P_2 */
9677   {
9678     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9679   },
9680
9681   /* VEX_LEN_0F3A7A_P_2 */
9682   {
9683     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9684   },
9685
9686   /* VEX_LEN_0F3A7B_P_2 */
9687   {
9688     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9689   },
9690
9691   /* VEX_LEN_0F3A7E_P_2 */
9692   {
9693     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9694   },
9695
9696   /* VEX_LEN_0F3A7F_P_2 */
9697   {
9698     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9699   },
9700
9701   /* VEX_LEN_0F3ADF_P_2 */
9702   {
9703     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9704   },
9705
9706   /* VEX_LEN_0F3AF0_P_3 */
9707   {
9708     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9709   },
9710
9711   /* VEX_LEN_0FXOP_08_CC */
9712   {
9713      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9714   },
9715
9716   /* VEX_LEN_0FXOP_08_CD */
9717   {
9718      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9719   },
9720
9721   /* VEX_LEN_0FXOP_08_CE */
9722   {
9723      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9724   },
9725
9726   /* VEX_LEN_0FXOP_08_CF */
9727   {
9728      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9729   },
9730
9731   /* VEX_LEN_0FXOP_08_EC */
9732   {
9733      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9734   },
9735
9736   /* VEX_LEN_0FXOP_08_ED */
9737   {
9738      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9739   },
9740
9741   /* VEX_LEN_0FXOP_08_EE */
9742   {
9743      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9744   },
9745
9746   /* VEX_LEN_0FXOP_08_EF */
9747   {
9748      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9749   },
9750
9751   /* VEX_LEN_0FXOP_09_80 */
9752   {
9753     { "vfrczps",        { XM, EXxmm }, 0 },
9754     { "vfrczps",        { XM, EXymmq }, 0 },
9755   },
9756
9757   /* VEX_LEN_0FXOP_09_81 */
9758   {
9759     { "vfrczpd",        { XM, EXxmm }, 0 },
9760     { "vfrczpd",        { XM, EXymmq }, 0 },
9761   },
9762 };
9763
9764 #include "i386-dis-evex-len.h"
9765
9766 static const struct dis386 vex_w_table[][2] = {
9767   {
9768     /* VEX_W_0F41_P_0_LEN_1 */
9769     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9770     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9771   },
9772   {
9773     /* VEX_W_0F41_P_2_LEN_1 */
9774     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9775     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9776   },
9777   {
9778     /* VEX_W_0F42_P_0_LEN_1 */
9779     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9780     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9781   },
9782   {
9783     /* VEX_W_0F42_P_2_LEN_1 */
9784     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9785     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9786   },
9787   {
9788     /* VEX_W_0F44_P_0_LEN_0 */
9789     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9790     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9791   },
9792   {
9793     /* VEX_W_0F44_P_2_LEN_0 */
9794     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9795     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9796   },
9797   {
9798     /* VEX_W_0F45_P_0_LEN_1 */
9799     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9800     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9801   },
9802   {
9803     /* VEX_W_0F45_P_2_LEN_1 */
9804     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9805     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9806   },
9807   {
9808     /* VEX_W_0F46_P_0_LEN_1 */
9809     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9810     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9811   },
9812   {
9813     /* VEX_W_0F46_P_2_LEN_1 */
9814     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9815     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9816   },
9817   {
9818     /* VEX_W_0F47_P_0_LEN_1 */
9819     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9820     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9821   },
9822   {
9823     /* VEX_W_0F47_P_2_LEN_1 */
9824     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9825     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9826   },
9827   {
9828     /* VEX_W_0F4A_P_0_LEN_1 */
9829     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9830     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9831   },
9832   {
9833     /* VEX_W_0F4A_P_2_LEN_1 */
9834     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9835     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9836   },
9837   {
9838     /* VEX_W_0F4B_P_0_LEN_1 */
9839     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9840     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9841   },
9842   {
9843     /* VEX_W_0F4B_P_2_LEN_1 */
9844     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9845   },
9846   {
9847     /* VEX_W_0F90_P_0_LEN_0 */
9848     { "kmovw",          { MaskG, MaskE }, 0 },
9849     { "kmovq",          { MaskG, MaskE }, 0 },
9850   },
9851   {
9852     /* VEX_W_0F90_P_2_LEN_0 */
9853     { "kmovb",          { MaskG, MaskBDE }, 0 },
9854     { "kmovd",          { MaskG, MaskBDE }, 0 },
9855   },
9856   {
9857     /* VEX_W_0F91_P_0_LEN_0 */
9858     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9859     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9860   },
9861   {
9862     /* VEX_W_0F91_P_2_LEN_0 */
9863     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9864     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9865   },
9866   {
9867     /* VEX_W_0F92_P_0_LEN_0 */
9868     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9869   },
9870   {
9871     /* VEX_W_0F92_P_2_LEN_0 */
9872     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9873   },
9874   {
9875     /* VEX_W_0F93_P_0_LEN_0 */
9876     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9877   },
9878   {
9879     /* VEX_W_0F93_P_2_LEN_0 */
9880     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9881   },
9882   {
9883     /* VEX_W_0F98_P_0_LEN_0 */
9884     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9885     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9886   },
9887   {
9888     /* VEX_W_0F98_P_2_LEN_0 */
9889     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9890     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9891   },
9892   {
9893     /* VEX_W_0F99_P_0_LEN_0 */
9894     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9895     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9896   },
9897   {
9898     /* VEX_W_0F99_P_2_LEN_0 */
9899     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9900     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9901   },
9902   {
9903     /* VEX_W_0F380C_P_2  */
9904     { "vpermilps",      { XM, Vex, EXx }, 0 },
9905   },
9906   {
9907     /* VEX_W_0F380D_P_2  */
9908     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9909   },
9910   {
9911     /* VEX_W_0F380E_P_2  */
9912     { "vtestps",        { XM, EXx }, 0 },
9913   },
9914   {
9915     /* VEX_W_0F380F_P_2  */
9916     { "vtestpd",        { XM, EXx }, 0 },
9917   },
9918   {
9919     /* VEX_W_0F3813_P_2 */
9920     { "vcvtph2ps", { XM, EXxmmq }, 0 },
9921   },
9922   {
9923     /* VEX_W_0F3816_P_2  */
9924     { "vpermps",        { XM, Vex, EXx }, 0 },
9925   },
9926   {
9927     /* VEX_W_0F3818_P_2 */
9928     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
9929   },
9930   {
9931     /* VEX_W_0F3819_P_2 */
9932     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
9933   },
9934   {
9935     /* VEX_W_0F381A_P_2_M_0 */
9936     { "vbroadcastf128", { XM, Mxmm }, 0 },
9937   },
9938   {
9939     /* VEX_W_0F382C_P_2_M_0 */
9940     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
9941   },
9942   {
9943     /* VEX_W_0F382D_P_2_M_0 */
9944     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
9945   },
9946   {
9947     /* VEX_W_0F382E_P_2_M_0 */
9948     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
9949   },
9950   {
9951     /* VEX_W_0F382F_P_2_M_0 */
9952     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
9953   },
9954   {
9955     /* VEX_W_0F3836_P_2  */
9956     { "vpermd",         { XM, Vex, EXx }, 0 },
9957   },
9958   {
9959     /* VEX_W_0F3846_P_2 */
9960     { "vpsravd",        { XM, Vex, EXx }, 0 },
9961   },
9962   {
9963     /* VEX_W_0F3858_P_2 */
9964     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
9965   },
9966   {
9967     /* VEX_W_0F3859_P_2 */
9968     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
9969   },
9970   {
9971     /* VEX_W_0F385A_P_2_M_0 */
9972     { "vbroadcasti128", { XM, Mxmm }, 0 },
9973   },
9974   {
9975     /* VEX_W_0F3878_P_2 */
9976     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
9977   },
9978   {
9979     /* VEX_W_0F3879_P_2 */
9980     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
9981   },
9982   {
9983     /* VEX_W_0F38CF_P_2 */
9984     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
9985   },
9986   {
9987     /* VEX_W_0F3A00_P_2 */
9988     { Bad_Opcode },
9989     { "vpermq",         { XM, EXx, Ib }, 0 },
9990   },
9991   {
9992     /* VEX_W_0F3A01_P_2 */
9993     { Bad_Opcode },
9994     { "vpermpd",        { XM, EXx, Ib }, 0 },
9995   },
9996   {
9997     /* VEX_W_0F3A02_P_2 */
9998     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
9999   },
10000   {
10001     /* VEX_W_0F3A04_P_2 */
10002     { "vpermilps",      { XM, EXx, Ib }, 0 },
10003   },
10004   {
10005     /* VEX_W_0F3A05_P_2 */
10006     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10007   },
10008   {
10009     /* VEX_W_0F3A06_P_2 */
10010     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10011   },
10012   {
10013     /* VEX_W_0F3A18_P_2 */
10014     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10015   },
10016   {
10017     /* VEX_W_0F3A19_P_2 */
10018     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10019   },
10020   {
10021     /* VEX_W_0F3A1D_P_2 */
10022     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10023   },
10024   {
10025     /* VEX_W_0F3A30_P_2_LEN_0 */
10026     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10027     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10028   },
10029   {
10030     /* VEX_W_0F3A31_P_2_LEN_0 */
10031     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10032     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10033   },
10034   {
10035     /* VEX_W_0F3A32_P_2_LEN_0 */
10036     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10037     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10038   },
10039   {
10040     /* VEX_W_0F3A33_P_2_LEN_0 */
10041     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10042     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10043   },
10044   {
10045     /* VEX_W_0F3A38_P_2 */
10046     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10047   },
10048   {
10049     /* VEX_W_0F3A39_P_2 */
10050     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10051   },
10052   {
10053     /* VEX_W_0F3A46_P_2 */
10054     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10055   },
10056   {
10057     /* VEX_W_0F3A48_P_2 */
10058     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10059     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10060   },
10061   {
10062     /* VEX_W_0F3A49_P_2 */
10063     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10064     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10065   },
10066   {
10067     /* VEX_W_0F3A4A_P_2 */
10068     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10069   },
10070   {
10071     /* VEX_W_0F3A4B_P_2 */
10072     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10073   },
10074   {
10075     /* VEX_W_0F3A4C_P_2 */
10076     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10077   },
10078   {
10079     /* VEX_W_0F3ACE_P_2 */
10080     { Bad_Opcode },
10081     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10082   },
10083   {
10084     /* VEX_W_0F3ACF_P_2 */
10085     { Bad_Opcode },
10086     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10087   },
10088
10089 #include "i386-dis-evex-w.h"
10090 };
10091
10092 static const struct dis386 mod_table[][2] = {
10093   {
10094     /* MOD_8D */
10095     { "leaS",           { Gv, M }, 0 },
10096   },
10097   {
10098     /* MOD_C6_REG_7 */
10099     { Bad_Opcode },
10100     { RM_TABLE (RM_C6_REG_7) },
10101   },
10102   {
10103     /* MOD_C7_REG_7 */
10104     { Bad_Opcode },
10105     { RM_TABLE (RM_C7_REG_7) },
10106   },
10107   {
10108     /* MOD_FF_REG_3 */
10109     { "{l|}call^", { indirEp }, 0 },
10110   },
10111   {
10112     /* MOD_FF_REG_5 */
10113     { "{l|}jmp^", { indirEp }, 0 },
10114   },
10115   {
10116     /* MOD_0F01_REG_0 */
10117     { X86_64_TABLE (X86_64_0F01_REG_0) },
10118     { RM_TABLE (RM_0F01_REG_0) },
10119   },
10120   {
10121     /* MOD_0F01_REG_1 */
10122     { X86_64_TABLE (X86_64_0F01_REG_1) },
10123     { RM_TABLE (RM_0F01_REG_1) },
10124   },
10125   {
10126     /* MOD_0F01_REG_2 */
10127     { X86_64_TABLE (X86_64_0F01_REG_2) },
10128     { RM_TABLE (RM_0F01_REG_2) },
10129   },
10130   {
10131     /* MOD_0F01_REG_3 */
10132     { X86_64_TABLE (X86_64_0F01_REG_3) },
10133     { RM_TABLE (RM_0F01_REG_3) },
10134   },
10135   {
10136     /* MOD_0F01_REG_5 */
10137     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10138     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10139   },
10140   {
10141     /* MOD_0F01_REG_7 */
10142     { "invlpg",         { Mb }, 0 },
10143     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10144   },
10145   {
10146     /* MOD_0F12_PREFIX_0 */
10147     { "movlpX",         { XM, EXq }, 0 },
10148     { "movhlps",        { XM, EXq }, 0 },
10149   },
10150   {
10151     /* MOD_0F12_PREFIX_2 */
10152     { "movlpX", { XM, EXq }, 0 },
10153   },
10154   {
10155     /* MOD_0F13 */
10156     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10157   },
10158   {
10159     /* MOD_0F16_PREFIX_0 */
10160     { "movhpX",         { XM, EXq }, 0 },
10161     { "movlhps",        { XM, EXq }, 0 },
10162   },
10163   {
10164     /* MOD_0F16_PREFIX_2 */
10165     { "movhpX", { XM, EXq }, 0 },
10166   },
10167   {
10168     /* MOD_0F17 */
10169     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10170   },
10171   {
10172     /* MOD_0F18_REG_0 */
10173     { "prefetchnta",    { Mb }, 0 },
10174   },
10175   {
10176     /* MOD_0F18_REG_1 */
10177     { "prefetcht0",     { Mb }, 0 },
10178   },
10179   {
10180     /* MOD_0F18_REG_2 */
10181     { "prefetcht1",     { Mb }, 0 },
10182   },
10183   {
10184     /* MOD_0F18_REG_3 */
10185     { "prefetcht2",     { Mb }, 0 },
10186   },
10187   {
10188     /* MOD_0F18_REG_4 */
10189     { "nop/reserved",   { Mb }, 0 },
10190   },
10191   {
10192     /* MOD_0F18_REG_5 */
10193     { "nop/reserved",   { Mb }, 0 },
10194   },
10195   {
10196     /* MOD_0F18_REG_6 */
10197     { "nop/reserved",   { Mb }, 0 },
10198   },
10199   {
10200     /* MOD_0F18_REG_7 */
10201     { "nop/reserved",   { Mb }, 0 },
10202   },
10203   {
10204     /* MOD_0F1A_PREFIX_0 */
10205     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10206     { "nopQ",           { Ev }, 0 },
10207   },
10208   {
10209     /* MOD_0F1B_PREFIX_0 */
10210     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10211     { "nopQ",           { Ev }, 0 },
10212   },
10213   {
10214     /* MOD_0F1B_PREFIX_1 */
10215     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10216     { "nopQ",           { Ev }, 0 },
10217   },
10218   {
10219     /* MOD_0F1C_PREFIX_0 */
10220     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10221     { "nopQ",           { Ev }, 0 },
10222   },
10223   {
10224     /* MOD_0F1E_PREFIX_1 */
10225     { "nopQ",           { Ev }, 0 },
10226     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10227   },
10228   {
10229     /* MOD_0F24 */
10230     { Bad_Opcode },
10231     { "movL",           { Rd, Td }, 0 },
10232   },
10233   {
10234     /* MOD_0F26 */
10235     { Bad_Opcode },
10236     { "movL",           { Td, Rd }, 0 },
10237   },
10238   {
10239     /* MOD_0F2B_PREFIX_0 */
10240     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10241   },
10242   {
10243     /* MOD_0F2B_PREFIX_1 */
10244     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10245   },
10246   {
10247     /* MOD_0F2B_PREFIX_2 */
10248     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10249   },
10250   {
10251     /* MOD_0F2B_PREFIX_3 */
10252     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10253   },
10254   {
10255     /* MOD_0F50 */
10256     { Bad_Opcode },
10257     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10258   },
10259   {
10260     /* MOD_0F71_REG_2 */
10261     { Bad_Opcode },
10262     { "psrlw",          { MS, Ib }, 0 },
10263   },
10264   {
10265     /* MOD_0F71_REG_4 */
10266     { Bad_Opcode },
10267     { "psraw",          { MS, Ib }, 0 },
10268   },
10269   {
10270     /* MOD_0F71_REG_6 */
10271     { Bad_Opcode },
10272     { "psllw",          { MS, Ib }, 0 },
10273   },
10274   {
10275     /* MOD_0F72_REG_2 */
10276     { Bad_Opcode },
10277     { "psrld",          { MS, Ib }, 0 },
10278   },
10279   {
10280     /* MOD_0F72_REG_4 */
10281     { Bad_Opcode },
10282     { "psrad",          { MS, Ib }, 0 },
10283   },
10284   {
10285     /* MOD_0F72_REG_6 */
10286     { Bad_Opcode },
10287     { "pslld",          { MS, Ib }, 0 },
10288   },
10289   {
10290     /* MOD_0F73_REG_2 */
10291     { Bad_Opcode },
10292     { "psrlq",          { MS, Ib }, 0 },
10293   },
10294   {
10295     /* MOD_0F73_REG_3 */
10296     { Bad_Opcode },
10297     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10298   },
10299   {
10300     /* MOD_0F73_REG_6 */
10301     { Bad_Opcode },
10302     { "psllq",          { MS, Ib }, 0 },
10303   },
10304   {
10305     /* MOD_0F73_REG_7 */
10306     { Bad_Opcode },
10307     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10308   },
10309   {
10310     /* MOD_0FAE_REG_0 */
10311     { "fxsave",         { FXSAVE }, 0 },
10312     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10313   },
10314   {
10315     /* MOD_0FAE_REG_1 */
10316     { "fxrstor",        { FXSAVE }, 0 },
10317     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10318   },
10319   {
10320     /* MOD_0FAE_REG_2 */
10321     { "ldmxcsr",        { Md }, 0 },
10322     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10323   },
10324   {
10325     /* MOD_0FAE_REG_3 */
10326     { "stmxcsr",        { Md }, 0 },
10327     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10328   },
10329   {
10330     /* MOD_0FAE_REG_4 */
10331     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10332     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10333   },
10334   {
10335     /* MOD_0FAE_REG_5 */
10336     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10337     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10338   },
10339   {
10340     /* MOD_0FAE_REG_6 */
10341     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10342     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10343   },
10344   {
10345     /* MOD_0FAE_REG_7 */
10346     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10347     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10348   },
10349   {
10350     /* MOD_0FB2 */
10351     { "lssS",           { Gv, Mp }, 0 },
10352   },
10353   {
10354     /* MOD_0FB4 */
10355     { "lfsS",           { Gv, Mp }, 0 },
10356   },
10357   {
10358     /* MOD_0FB5 */
10359     { "lgsS",           { Gv, Mp }, 0 },
10360   },
10361   {
10362     /* MOD_0FC3 */
10363     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10364   },
10365   {
10366     /* MOD_0FC7_REG_3 */
10367     { "xrstors",        { FXSAVE }, 0 },
10368   },
10369   {
10370     /* MOD_0FC7_REG_4 */
10371     { "xsavec",         { FXSAVE }, 0 },
10372   },
10373   {
10374     /* MOD_0FC7_REG_5 */
10375     { "xsaves",         { FXSAVE }, 0 },
10376   },
10377   {
10378     /* MOD_0FC7_REG_6 */
10379     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10380     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10381   },
10382   {
10383     /* MOD_0FC7_REG_7 */
10384     { "vmptrst",        { Mq }, 0 },
10385     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10386   },
10387   {
10388     /* MOD_0FD7 */
10389     { Bad_Opcode },
10390     { "pmovmskb",       { Gdq, MS }, 0 },
10391   },
10392   {
10393     /* MOD_0FE7_PREFIX_2 */
10394     { "movntdq",        { Mx, XM }, 0 },
10395   },
10396   {
10397     /* MOD_0FF0_PREFIX_3 */
10398     { "lddqu",          { XM, M }, 0 },
10399   },
10400   {
10401     /* MOD_0F382A_PREFIX_2 */
10402     { "movntdqa",       { XM, Mx }, 0 },
10403   },
10404   {
10405     /* MOD_0F38F5_PREFIX_2 */
10406     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10407   },
10408   {
10409     /* MOD_0F38F6_PREFIX_0 */
10410     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10411   },
10412   {
10413     /* MOD_0F38F8_PREFIX_1 */
10414     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10415   },
10416   {
10417     /* MOD_0F38F8_PREFIX_2 */
10418     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10419   },
10420   {
10421     /* MOD_0F38F8_PREFIX_3 */
10422     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10423   },
10424   {
10425     /* MOD_0F38F9_PREFIX_0 */
10426     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10427   },
10428   {
10429     /* MOD_62_32BIT */
10430     { "bound{S|}",      { Gv, Ma }, 0 },
10431     { EVEX_TABLE (EVEX_0F) },
10432   },
10433   {
10434     /* MOD_C4_32BIT */
10435     { "lesS",           { Gv, Mp }, 0 },
10436     { VEX_C4_TABLE (VEX_0F) },
10437   },
10438   {
10439     /* MOD_C5_32BIT */
10440     { "ldsS",           { Gv, Mp }, 0 },
10441     { VEX_C5_TABLE (VEX_0F) },
10442   },
10443   {
10444     /* MOD_VEX_0F12_PREFIX_0 */
10445     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10446     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10447   },
10448   {
10449     /* MOD_VEX_0F12_PREFIX_2 */
10450     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10451   },
10452   {
10453     /* MOD_VEX_0F13 */
10454     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10455   },
10456   {
10457     /* MOD_VEX_0F16_PREFIX_0 */
10458     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10459     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10460   },
10461   {
10462     /* MOD_VEX_0F16_PREFIX_2 */
10463     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10464   },
10465   {
10466     /* MOD_VEX_0F17 */
10467     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10468   },
10469   {
10470     /* MOD_VEX_0F2B */
10471     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10472   },
10473   {
10474     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10475     { Bad_Opcode },
10476     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10477   },
10478   {
10479     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10480     { Bad_Opcode },
10481     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10482   },
10483   {
10484     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10485     { Bad_Opcode },
10486     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10487   },
10488   {
10489     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10490     { Bad_Opcode },
10491     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10492   },
10493   {
10494     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10495     { Bad_Opcode },
10496     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10497   },
10498   {
10499     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10500     { Bad_Opcode },
10501     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10502   },
10503   {
10504     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10505     { Bad_Opcode },
10506     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10507   },
10508   {
10509     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10510     { Bad_Opcode },
10511     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10512   },
10513   {
10514     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10515     { Bad_Opcode },
10516     { "knotw",          { MaskG, MaskR }, 0 },
10517   },
10518   {
10519     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10520     { Bad_Opcode },
10521     { "knotq",          { MaskG, MaskR }, 0 },
10522   },
10523   {
10524     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10525     { Bad_Opcode },
10526     { "knotb",          { MaskG, MaskR }, 0 },
10527   },
10528   {
10529     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10530     { Bad_Opcode },
10531     { "knotd",          { MaskG, MaskR }, 0 },
10532   },
10533   {
10534     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10535     { Bad_Opcode },
10536     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10537   },
10538   {
10539     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10540     { Bad_Opcode },
10541     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10542   },
10543   {
10544     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10545     { Bad_Opcode },
10546     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10547   },
10548   {
10549     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10550     { Bad_Opcode },
10551     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10552   },
10553  {
10554     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10555     { Bad_Opcode },
10556     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10557   },
10558   {
10559     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10560     { Bad_Opcode },
10561     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10562   },
10563   {
10564     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10565     { Bad_Opcode },
10566     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10567   },
10568   {
10569     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10570     { Bad_Opcode },
10571     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10572   },
10573   {
10574     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10575     { Bad_Opcode },
10576     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10577   },
10578   {
10579     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10580     { Bad_Opcode },
10581     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10582   },
10583   {
10584     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10585     { Bad_Opcode },
10586     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10587   },
10588   {
10589     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10590     { Bad_Opcode },
10591     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10592   },
10593   {
10594     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10595     { Bad_Opcode },
10596     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10597   },
10598   {
10599     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10600     { Bad_Opcode },
10601     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10602   },
10603   {
10604     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10605     { Bad_Opcode },
10606     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10607   },
10608   {
10609     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10610     { Bad_Opcode },
10611     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10612   },
10613   {
10614     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10615     { Bad_Opcode },
10616     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10617   },
10618   {
10619     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10620     { Bad_Opcode },
10621     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10622   },
10623   {
10624     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10625     { Bad_Opcode },
10626     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10627   },
10628   {
10629     /* MOD_VEX_0F50 */
10630     { Bad_Opcode },
10631     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10632   },
10633   {
10634     /* MOD_VEX_0F71_REG_2 */
10635     { Bad_Opcode },
10636     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10637   },
10638   {
10639     /* MOD_VEX_0F71_REG_4 */
10640     { Bad_Opcode },
10641     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10642   },
10643   {
10644     /* MOD_VEX_0F71_REG_6 */
10645     { Bad_Opcode },
10646     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10647   },
10648   {
10649     /* MOD_VEX_0F72_REG_2 */
10650     { Bad_Opcode },
10651     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10652   },
10653   {
10654     /* MOD_VEX_0F72_REG_4 */
10655     { Bad_Opcode },
10656     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10657   },
10658   {
10659     /* MOD_VEX_0F72_REG_6 */
10660     { Bad_Opcode },
10661     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10662   },
10663   {
10664     /* MOD_VEX_0F73_REG_2 */
10665     { Bad_Opcode },
10666     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10667   },
10668   {
10669     /* MOD_VEX_0F73_REG_3 */
10670     { Bad_Opcode },
10671     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10672   },
10673   {
10674     /* MOD_VEX_0F73_REG_6 */
10675     { Bad_Opcode },
10676     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10677   },
10678   {
10679     /* MOD_VEX_0F73_REG_7 */
10680     { Bad_Opcode },
10681     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10682   },
10683   {
10684     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10685     { "kmovw",          { Ew, MaskG }, 0 },
10686     { Bad_Opcode },
10687   },
10688   {
10689     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10690     { "kmovq",          { Eq, MaskG }, 0 },
10691     { Bad_Opcode },
10692   },
10693   {
10694     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10695     { "kmovb",          { Eb, MaskG }, 0 },
10696     { Bad_Opcode },
10697   },
10698   {
10699     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10700     { "kmovd",          { Ed, MaskG }, 0 },
10701     { Bad_Opcode },
10702   },
10703   {
10704     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10705     { Bad_Opcode },
10706     { "kmovw",          { MaskG, Rdq }, 0 },
10707   },
10708   {
10709     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10710     { Bad_Opcode },
10711     { "kmovb",          { MaskG, Rdq }, 0 },
10712   },
10713   {
10714     /* MOD_VEX_0F92_P_3_LEN_0 */
10715     { Bad_Opcode },
10716     { "kmovK",          { MaskG, Rdq }, 0 },
10717   },
10718   {
10719     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10720     { Bad_Opcode },
10721     { "kmovw",          { Gdq, MaskR }, 0 },
10722   },
10723   {
10724     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10725     { Bad_Opcode },
10726     { "kmovb",          { Gdq, MaskR }, 0 },
10727   },
10728   {
10729     /* MOD_VEX_0F93_P_3_LEN_0 */
10730     { Bad_Opcode },
10731     { "kmovK",          { Gdq, MaskR }, 0 },
10732   },
10733   {
10734     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10735     { Bad_Opcode },
10736     { "kortestw", { MaskG, MaskR }, 0 },
10737   },
10738   {
10739     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10740     { Bad_Opcode },
10741     { "kortestq", { MaskG, MaskR }, 0 },
10742   },
10743   {
10744     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10745     { Bad_Opcode },
10746     { "kortestb", { MaskG, MaskR }, 0 },
10747   },
10748   {
10749     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10750     { Bad_Opcode },
10751     { "kortestd", { MaskG, MaskR }, 0 },
10752   },
10753   {
10754     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10755     { Bad_Opcode },
10756     { "ktestw", { MaskG, MaskR }, 0 },
10757   },
10758   {
10759     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10760     { Bad_Opcode },
10761     { "ktestq", { MaskG, MaskR }, 0 },
10762   },
10763   {
10764     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10765     { Bad_Opcode },
10766     { "ktestb", { MaskG, MaskR }, 0 },
10767   },
10768   {
10769     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10770     { Bad_Opcode },
10771     { "ktestd", { MaskG, MaskR }, 0 },
10772   },
10773   {
10774     /* MOD_VEX_0FAE_REG_2 */
10775     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10776   },
10777   {
10778     /* MOD_VEX_0FAE_REG_3 */
10779     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10780   },
10781   {
10782     /* MOD_VEX_0FD7_PREFIX_2 */
10783     { Bad_Opcode },
10784     { "vpmovmskb",      { Gdq, XS }, 0 },
10785   },
10786   {
10787     /* MOD_VEX_0FE7_PREFIX_2 */
10788     { "vmovntdq",       { Mx, XM }, 0 },
10789   },
10790   {
10791     /* MOD_VEX_0FF0_PREFIX_3 */
10792     { "vlddqu",         { XM, M }, 0 },
10793   },
10794   {
10795     /* MOD_VEX_0F381A_PREFIX_2 */
10796     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10797   },
10798   {
10799     /* MOD_VEX_0F382A_PREFIX_2 */
10800     { "vmovntdqa",      { XM, Mx }, 0 },
10801   },
10802   {
10803     /* MOD_VEX_0F382C_PREFIX_2 */
10804     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10805   },
10806   {
10807     /* MOD_VEX_0F382D_PREFIX_2 */
10808     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10809   },
10810   {
10811     /* MOD_VEX_0F382E_PREFIX_2 */
10812     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10813   },
10814   {
10815     /* MOD_VEX_0F382F_PREFIX_2 */
10816     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10817   },
10818   {
10819     /* MOD_VEX_0F385A_PREFIX_2 */
10820     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10821   },
10822   {
10823     /* MOD_VEX_0F388C_PREFIX_2 */
10824     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_0F388E_PREFIX_2 */
10828     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10829   },
10830   {
10831     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10832     { Bad_Opcode },
10833     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10834   },
10835   {
10836     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10837     { Bad_Opcode },
10838     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10839   },
10840   {
10841     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10842     { Bad_Opcode },
10843     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10844   },
10845   {
10846     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10847     { Bad_Opcode },
10848     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10849   },
10850   {
10851     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10852     { Bad_Opcode },
10853     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10854   },
10855   {
10856     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10857     { Bad_Opcode },
10858     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10859   },
10860   {
10861     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10862     { Bad_Opcode },
10863     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10864   },
10865   {
10866     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10867     { Bad_Opcode },
10868     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10869   },
10870
10871 #include "i386-dis-evex-mod.h"
10872 };
10873
10874 static const struct dis386 rm_table[][8] = {
10875   {
10876     /* RM_C6_REG_7 */
10877     { "xabort",         { Skip_MODRM, Ib }, 0 },
10878   },
10879   {
10880     /* RM_C7_REG_7 */
10881     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10882   },
10883   {
10884     /* RM_0F01_REG_0 */
10885     { "enclv",          { Skip_MODRM }, 0 },
10886     { "vmcall",         { Skip_MODRM }, 0 },
10887     { "vmlaunch",       { Skip_MODRM }, 0 },
10888     { "vmresume",       { Skip_MODRM }, 0 },
10889     { "vmxoff",         { Skip_MODRM }, 0 },
10890     { "pconfig",        { Skip_MODRM }, 0 },
10891   },
10892   {
10893     /* RM_0F01_REG_1 */
10894     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10895     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10896     { "clac",           { Skip_MODRM }, 0 },
10897     { "stac",           { Skip_MODRM }, 0 },
10898     { Bad_Opcode },
10899     { Bad_Opcode },
10900     { Bad_Opcode },
10901     { "encls",          { Skip_MODRM }, 0 },
10902   },
10903   {
10904     /* RM_0F01_REG_2 */
10905     { "xgetbv",         { Skip_MODRM }, 0 },
10906     { "xsetbv",         { Skip_MODRM }, 0 },
10907     { Bad_Opcode },
10908     { Bad_Opcode },
10909     { "vmfunc",         { Skip_MODRM }, 0 },
10910     { "xend",           { Skip_MODRM }, 0 },
10911     { "xtest",          { Skip_MODRM }, 0 },
10912     { "enclu",          { Skip_MODRM }, 0 },
10913   },
10914   {
10915     /* RM_0F01_REG_3 */
10916     { "vmrun",          { Skip_MODRM }, 0 },
10917     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10918     { "vmload",         { Skip_MODRM }, 0 },
10919     { "vmsave",         { Skip_MODRM }, 0 },
10920     { "stgi",           { Skip_MODRM }, 0 },
10921     { "clgi",           { Skip_MODRM }, 0 },
10922     { "skinit",         { Skip_MODRM }, 0 },
10923     { "invlpga",        { Skip_MODRM }, 0 },
10924   },
10925   {
10926     /* RM_0F01_REG_5_MOD_3 */
10927     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10928     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10929     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10930     { Bad_Opcode },
10931     { Bad_Opcode },
10932     { Bad_Opcode },
10933     { "rdpkru",         { Skip_MODRM }, 0 },
10934     { "wrpkru",         { Skip_MODRM }, 0 },
10935   },
10936   {
10937     /* RM_0F01_REG_7_MOD_3 */
10938     { "swapgs",         { Skip_MODRM }, 0  },
10939     { "rdtscp",         { Skip_MODRM }, 0  },
10940     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
10941     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
10942     { "clzero",         { Skip_MODRM }, 0  },
10943     { "rdpru",          { Skip_MODRM }, 0  },
10944   },
10945   {
10946     /* RM_0F1E_P_1_MOD_3_REG_7 */
10947     { "nopQ",           { Ev }, 0 },
10948     { "nopQ",           { Ev }, 0 },
10949     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
10950     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
10951     { "nopQ",           { Ev }, 0 },
10952     { "nopQ",           { Ev }, 0 },
10953     { "nopQ",           { Ev }, 0 },
10954     { "nopQ",           { Ev }, 0 },
10955   },
10956   {
10957     /* RM_0FAE_REG_6_MOD_3 */
10958     { "mfence",         { Skip_MODRM }, 0 },
10959   },
10960   {
10961     /* RM_0FAE_REG_7_MOD_3 */
10962     { "sfence",         { Skip_MODRM }, 0 },
10963
10964   },
10965 };
10966
10967 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10968
10969 /* We use the high bit to indicate different name for the same
10970    prefix.  */
10971 #define REP_PREFIX      (0xf3 | 0x100)
10972 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10973 #define XRELEASE_PREFIX (0xf3 | 0x400)
10974 #define BND_PREFIX      (0xf2 | 0x400)
10975 #define NOTRACK_PREFIX  (0x3e | 0x100)
10976
10977 /* Remember if the current op is a jump instruction.  */
10978 static bfd_boolean op_is_jump = FALSE;
10979
10980 static int
10981 ckprefix (void)
10982 {
10983   int newrex, i, length;
10984   rex = 0;
10985   prefixes = 0;
10986   used_prefixes = 0;
10987   rex_used = 0;
10988   last_lock_prefix = -1;
10989   last_repz_prefix = -1;
10990   last_repnz_prefix = -1;
10991   last_data_prefix = -1;
10992   last_addr_prefix = -1;
10993   last_rex_prefix = -1;
10994   last_seg_prefix = -1;
10995   fwait_prefix = -1;
10996   active_seg_prefix = 0;
10997   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10998     all_prefixes[i] = 0;
10999   i = 0;
11000   length = 0;
11001   /* The maximum instruction length is 15bytes.  */
11002   while (length < MAX_CODE_LENGTH - 1)
11003     {
11004       FETCH_DATA (the_info, codep + 1);
11005       newrex = 0;
11006       switch (*codep)
11007         {
11008         /* REX prefixes family.  */
11009         case 0x40:
11010         case 0x41:
11011         case 0x42:
11012         case 0x43:
11013         case 0x44:
11014         case 0x45:
11015         case 0x46:
11016         case 0x47:
11017         case 0x48:
11018         case 0x49:
11019         case 0x4a:
11020         case 0x4b:
11021         case 0x4c:
11022         case 0x4d:
11023         case 0x4e:
11024         case 0x4f:
11025           if (address_mode == mode_64bit)
11026             newrex = *codep;
11027           else
11028             return 1;
11029           last_rex_prefix = i;
11030           break;
11031         case 0xf3:
11032           prefixes |= PREFIX_REPZ;
11033           last_repz_prefix = i;
11034           break;
11035         case 0xf2:
11036           prefixes |= PREFIX_REPNZ;
11037           last_repnz_prefix = i;
11038           break;
11039         case 0xf0:
11040           prefixes |= PREFIX_LOCK;
11041           last_lock_prefix = i;
11042           break;
11043         case 0x2e:
11044           prefixes |= PREFIX_CS;
11045           last_seg_prefix = i;
11046           active_seg_prefix = PREFIX_CS;
11047           break;
11048         case 0x36:
11049           prefixes |= PREFIX_SS;
11050           last_seg_prefix = i;
11051           active_seg_prefix = PREFIX_SS;
11052           break;
11053         case 0x3e:
11054           prefixes |= PREFIX_DS;
11055           last_seg_prefix = i;
11056           active_seg_prefix = PREFIX_DS;
11057           break;
11058         case 0x26:
11059           prefixes |= PREFIX_ES;
11060           last_seg_prefix = i;
11061           active_seg_prefix = PREFIX_ES;
11062           break;
11063         case 0x64:
11064           prefixes |= PREFIX_FS;
11065           last_seg_prefix = i;
11066           active_seg_prefix = PREFIX_FS;
11067           break;
11068         case 0x65:
11069           prefixes |= PREFIX_GS;
11070           last_seg_prefix = i;
11071           active_seg_prefix = PREFIX_GS;
11072           break;
11073         case 0x66:
11074           prefixes |= PREFIX_DATA;
11075           last_data_prefix = i;
11076           break;
11077         case 0x67:
11078           prefixes |= PREFIX_ADDR;
11079           last_addr_prefix = i;
11080           break;
11081         case FWAIT_OPCODE:
11082           /* fwait is really an instruction.  If there are prefixes
11083              before the fwait, they belong to the fwait, *not* to the
11084              following instruction.  */
11085           fwait_prefix = i;
11086           if (prefixes || rex)
11087             {
11088               prefixes |= PREFIX_FWAIT;
11089               codep++;
11090               /* This ensures that the previous REX prefixes are noticed
11091                  as unused prefixes, as in the return case below.  */
11092               rex_used = rex;
11093               return 1;
11094             }
11095           prefixes = PREFIX_FWAIT;
11096           break;
11097         default:
11098           return 1;
11099         }
11100       /* Rex is ignored when followed by another prefix.  */
11101       if (rex)
11102         {
11103           rex_used = rex;
11104           return 1;
11105         }
11106       if (*codep != FWAIT_OPCODE)
11107         all_prefixes[i++] = *codep;
11108       rex = newrex;
11109       codep++;
11110       length++;
11111     }
11112   return 0;
11113 }
11114
11115 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11116    prefix byte.  */
11117
11118 static const char *
11119 prefix_name (int pref, int sizeflag)
11120 {
11121   static const char *rexes [16] =
11122     {
11123       "rex",            /* 0x40 */
11124       "rex.B",          /* 0x41 */
11125       "rex.X",          /* 0x42 */
11126       "rex.XB",         /* 0x43 */
11127       "rex.R",          /* 0x44 */
11128       "rex.RB",         /* 0x45 */
11129       "rex.RX",         /* 0x46 */
11130       "rex.RXB",        /* 0x47 */
11131       "rex.W",          /* 0x48 */
11132       "rex.WB",         /* 0x49 */
11133       "rex.WX",         /* 0x4a */
11134       "rex.WXB",        /* 0x4b */
11135       "rex.WR",         /* 0x4c */
11136       "rex.WRB",        /* 0x4d */
11137       "rex.WRX",        /* 0x4e */
11138       "rex.WRXB",       /* 0x4f */
11139     };
11140
11141   switch (pref)
11142     {
11143     /* REX prefixes family.  */
11144     case 0x40:
11145     case 0x41:
11146     case 0x42:
11147     case 0x43:
11148     case 0x44:
11149     case 0x45:
11150     case 0x46:
11151     case 0x47:
11152     case 0x48:
11153     case 0x49:
11154     case 0x4a:
11155     case 0x4b:
11156     case 0x4c:
11157     case 0x4d:
11158     case 0x4e:
11159     case 0x4f:
11160       return rexes [pref - 0x40];
11161     case 0xf3:
11162       return "repz";
11163     case 0xf2:
11164       return "repnz";
11165     case 0xf0:
11166       return "lock";
11167     case 0x2e:
11168       return "cs";
11169     case 0x36:
11170       return "ss";
11171     case 0x3e:
11172       return "ds";
11173     case 0x26:
11174       return "es";
11175     case 0x64:
11176       return "fs";
11177     case 0x65:
11178       return "gs";
11179     case 0x66:
11180       return (sizeflag & DFLAG) ? "data16" : "data32";
11181     case 0x67:
11182       if (address_mode == mode_64bit)
11183         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11184       else
11185         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11186     case FWAIT_OPCODE:
11187       return "fwait";
11188     case REP_PREFIX:
11189       return "rep";
11190     case XACQUIRE_PREFIX:
11191       return "xacquire";
11192     case XRELEASE_PREFIX:
11193       return "xrelease";
11194     case BND_PREFIX:
11195       return "bnd";
11196     case NOTRACK_PREFIX:
11197       return "notrack";
11198     default:
11199       return NULL;
11200     }
11201 }
11202
11203 static char op_out[MAX_OPERANDS][100];
11204 static int op_ad, op_index[MAX_OPERANDS];
11205 static int two_source_ops;
11206 static bfd_vma op_address[MAX_OPERANDS];
11207 static bfd_vma op_riprel[MAX_OPERANDS];
11208 static bfd_vma start_pc;
11209
11210 /*
11211  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11212  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11213  *   section of the "Virtual 8086 Mode" chapter.)
11214  * 'pc' should be the address of this instruction, it will
11215  *   be used to print the target address if this is a relative jump or call
11216  * The function returns the length of this instruction in bytes.
11217  */
11218
11219 static char intel_syntax;
11220 static char intel_mnemonic = !SYSV386_COMPAT;
11221 static char open_char;
11222 static char close_char;
11223 static char separator_char;
11224 static char scale_char;
11225
11226 enum x86_64_isa
11227 {
11228   amd64 = 1,
11229   intel64
11230 };
11231
11232 static enum x86_64_isa isa64;
11233
11234 /* Here for backwards compatibility.  When gdb stops using
11235    print_insn_i386_att and print_insn_i386_intel these functions can
11236    disappear, and print_insn_i386 be merged into print_insn.  */
11237 int
11238 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11239 {
11240   intel_syntax = 0;
11241
11242   return print_insn (pc, info);
11243 }
11244
11245 int
11246 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11247 {
11248   intel_syntax = 1;
11249
11250   return print_insn (pc, info);
11251 }
11252
11253 int
11254 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11255 {
11256   intel_syntax = -1;
11257
11258   return print_insn (pc, info);
11259 }
11260
11261 void
11262 print_i386_disassembler_options (FILE *stream)
11263 {
11264   fprintf (stream, _("\n\
11265 The following i386/x86-64 specific disassembler options are supported for use\n\
11266 with the -M switch (multiple options should be separated by commas):\n"));
11267
11268   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11269   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11270   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11271   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11272   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11273   fprintf (stream, _("  att-mnemonic\n"
11274                      "              Display instruction in AT&T mnemonic\n"));
11275   fprintf (stream, _("  intel-mnemonic\n"
11276                      "              Display instruction in Intel mnemonic\n"));
11277   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11278   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11279   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11280   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11281   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11282   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11283   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11284   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11285 }
11286
11287 /* Bad opcode.  */
11288 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11289
11290 /* Get a pointer to struct dis386 with a valid name.  */
11291
11292 static const struct dis386 *
11293 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11294 {
11295   int vindex, vex_table_index;
11296
11297   if (dp->name != NULL)
11298     return dp;
11299
11300   switch (dp->op[0].bytemode)
11301     {
11302     case USE_REG_TABLE:
11303       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11304       break;
11305
11306     case USE_MOD_TABLE:
11307       vindex = modrm.mod == 0x3 ? 1 : 0;
11308       dp = &mod_table[dp->op[1].bytemode][vindex];
11309       break;
11310
11311     case USE_RM_TABLE:
11312       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11313       break;
11314
11315     case USE_PREFIX_TABLE:
11316       if (need_vex)
11317         {
11318           /* The prefix in VEX is implicit.  */
11319           switch (vex.prefix)
11320             {
11321             case 0:
11322               vindex = 0;
11323               break;
11324             case REPE_PREFIX_OPCODE:
11325               vindex = 1;
11326               break;
11327             case DATA_PREFIX_OPCODE:
11328               vindex = 2;
11329               break;
11330             case REPNE_PREFIX_OPCODE:
11331               vindex = 3;
11332               break;
11333             default:
11334               abort ();
11335               break;
11336             }
11337         }
11338       else
11339         {
11340           int last_prefix = -1;
11341           int prefix = 0;
11342           vindex = 0;
11343           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11344              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11345              last one wins.  */
11346           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11347             {
11348               if (last_repz_prefix > last_repnz_prefix)
11349                 {
11350                   vindex = 1;
11351                   prefix = PREFIX_REPZ;
11352                   last_prefix = last_repz_prefix;
11353                 }
11354               else
11355                 {
11356                   vindex = 3;
11357                   prefix = PREFIX_REPNZ;
11358                   last_prefix = last_repnz_prefix;
11359                 }
11360
11361               /* Check if prefix should be ignored.  */
11362               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11363                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11364                    & prefix) != 0)
11365                 vindex = 0;
11366             }
11367
11368           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11369             {
11370               vindex = 2;
11371               prefix = PREFIX_DATA;
11372               last_prefix = last_data_prefix;
11373             }
11374
11375           if (vindex != 0)
11376             {
11377               used_prefixes |= prefix;
11378               all_prefixes[last_prefix] = 0;
11379             }
11380         }
11381       dp = &prefix_table[dp->op[1].bytemode][vindex];
11382       break;
11383
11384     case USE_X86_64_TABLE:
11385       vindex = address_mode == mode_64bit ? 1 : 0;
11386       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11387       break;
11388
11389     case USE_3BYTE_TABLE:
11390       FETCH_DATA (info, codep + 2);
11391       vindex = *codep++;
11392       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11393       end_codep = codep;
11394       modrm.mod = (*codep >> 6) & 3;
11395       modrm.reg = (*codep >> 3) & 7;
11396       modrm.rm = *codep & 7;
11397       break;
11398
11399     case USE_VEX_LEN_TABLE:
11400       if (!need_vex)
11401         abort ();
11402
11403       switch (vex.length)
11404         {
11405         case 128:
11406           vindex = 0;
11407           break;
11408         case 256:
11409           vindex = 1;
11410           break;
11411         default:
11412           abort ();
11413           break;
11414         }
11415
11416       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11417       break;
11418
11419     case USE_EVEX_LEN_TABLE:
11420       if (!vex.evex)
11421         abort ();
11422
11423       switch (vex.length)
11424         {
11425         case 128:
11426           vindex = 0;
11427           break;
11428         case 256:
11429           vindex = 1;
11430           break;
11431         case 512:
11432           vindex = 2;
11433           break;
11434         default:
11435           abort ();
11436           break;
11437         }
11438
11439       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11440       break;
11441
11442     case USE_XOP_8F_TABLE:
11443       FETCH_DATA (info, codep + 3);
11444       rex = ~(*codep >> 5) & 0x7;
11445
11446       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11447       switch ((*codep & 0x1f))
11448         {
11449         default:
11450           dp = &bad_opcode;
11451           return dp;
11452         case 0x8:
11453           vex_table_index = XOP_08;
11454           break;
11455         case 0x9:
11456           vex_table_index = XOP_09;
11457           break;
11458         case 0xa:
11459           vex_table_index = XOP_0A;
11460           break;
11461         }
11462       codep++;
11463       vex.w = *codep & 0x80;
11464       if (vex.w && address_mode == mode_64bit)
11465         rex |= REX_W;
11466
11467       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11468       if (address_mode != mode_64bit)
11469         {
11470           /* In 16/32-bit mode REX_B is silently ignored.  */
11471           rex &= ~REX_B;
11472         }
11473
11474       vex.length = (*codep & 0x4) ? 256 : 128;
11475       switch ((*codep & 0x3))
11476         {
11477         case 0:
11478           break;
11479         case 1:
11480           vex.prefix = DATA_PREFIX_OPCODE;
11481           break;
11482         case 2:
11483           vex.prefix = REPE_PREFIX_OPCODE;
11484           break;
11485         case 3:
11486           vex.prefix = REPNE_PREFIX_OPCODE;
11487           break;
11488         }
11489       need_vex = 1;
11490       need_vex_reg = 1;
11491       codep++;
11492       vindex = *codep++;
11493       dp = &xop_table[vex_table_index][vindex];
11494
11495       end_codep = codep;
11496       FETCH_DATA (info, codep + 1);
11497       modrm.mod = (*codep >> 6) & 3;
11498       modrm.reg = (*codep >> 3) & 7;
11499       modrm.rm = *codep & 7;
11500       break;
11501
11502     case USE_VEX_C4_TABLE:
11503       /* VEX prefix.  */
11504       FETCH_DATA (info, codep + 3);
11505       rex = ~(*codep >> 5) & 0x7;
11506       switch ((*codep & 0x1f))
11507         {
11508         default:
11509           dp = &bad_opcode;
11510           return dp;
11511         case 0x1:
11512           vex_table_index = VEX_0F;
11513           break;
11514         case 0x2:
11515           vex_table_index = VEX_0F38;
11516           break;
11517         case 0x3:
11518           vex_table_index = VEX_0F3A;
11519           break;
11520         }
11521       codep++;
11522       vex.w = *codep & 0x80;
11523       if (address_mode == mode_64bit)
11524         {
11525           if (vex.w)
11526             rex |= REX_W;
11527         }
11528       else
11529         {
11530           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11531              is ignored, other REX bits are 0 and the highest bit in
11532              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11533           rex = 0;
11534         }
11535       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11536       vex.length = (*codep & 0x4) ? 256 : 128;
11537       switch ((*codep & 0x3))
11538         {
11539         case 0:
11540           break;
11541         case 1:
11542           vex.prefix = DATA_PREFIX_OPCODE;
11543           break;
11544         case 2:
11545           vex.prefix = REPE_PREFIX_OPCODE;
11546           break;
11547         case 3:
11548           vex.prefix = REPNE_PREFIX_OPCODE;
11549           break;
11550         }
11551       need_vex = 1;
11552       need_vex_reg = 1;
11553       codep++;
11554       vindex = *codep++;
11555       dp = &vex_table[vex_table_index][vindex];
11556       end_codep = codep;
11557       /* There is no MODRM byte for VEX0F 77.  */
11558       if (vex_table_index != VEX_0F || vindex != 0x77)
11559         {
11560           FETCH_DATA (info, codep + 1);
11561           modrm.mod = (*codep >> 6) & 3;
11562           modrm.reg = (*codep >> 3) & 7;
11563           modrm.rm = *codep & 7;
11564         }
11565       break;
11566
11567     case USE_VEX_C5_TABLE:
11568       /* VEX prefix.  */
11569       FETCH_DATA (info, codep + 2);
11570       rex = (*codep & 0x80) ? 0 : REX_R;
11571
11572       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11573          VEX.vvvv is 1.  */
11574       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11575       vex.length = (*codep & 0x4) ? 256 : 128;
11576       switch ((*codep & 0x3))
11577         {
11578         case 0:
11579           break;
11580         case 1:
11581           vex.prefix = DATA_PREFIX_OPCODE;
11582           break;
11583         case 2:
11584           vex.prefix = REPE_PREFIX_OPCODE;
11585           break;
11586         case 3:
11587           vex.prefix = REPNE_PREFIX_OPCODE;
11588           break;
11589         }
11590       need_vex = 1;
11591       need_vex_reg = 1;
11592       codep++;
11593       vindex = *codep++;
11594       dp = &vex_table[dp->op[1].bytemode][vindex];
11595       end_codep = codep;
11596       /* There is no MODRM byte for VEX 77.  */
11597       if (vindex != 0x77)
11598         {
11599           FETCH_DATA (info, codep + 1);
11600           modrm.mod = (*codep >> 6) & 3;
11601           modrm.reg = (*codep >> 3) & 7;
11602           modrm.rm = *codep & 7;
11603         }
11604       break;
11605
11606     case USE_VEX_W_TABLE:
11607       if (!need_vex)
11608         abort ();
11609
11610       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11611       break;
11612
11613     case USE_EVEX_TABLE:
11614       two_source_ops = 0;
11615       /* EVEX prefix.  */
11616       vex.evex = 1;
11617       FETCH_DATA (info, codep + 4);
11618       /* The first byte after 0x62.  */
11619       rex = ~(*codep >> 5) & 0x7;
11620       vex.r = *codep & 0x10;
11621       switch ((*codep & 0xf))
11622         {
11623         default:
11624           return &bad_opcode;
11625         case 0x1:
11626           vex_table_index = EVEX_0F;
11627           break;
11628         case 0x2:
11629           vex_table_index = EVEX_0F38;
11630           break;
11631         case 0x3:
11632           vex_table_index = EVEX_0F3A;
11633           break;
11634         }
11635
11636       /* The second byte after 0x62.  */
11637       codep++;
11638       vex.w = *codep & 0x80;
11639       if (vex.w && address_mode == mode_64bit)
11640         rex |= REX_W;
11641
11642       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11643
11644       /* The U bit.  */
11645       if (!(*codep & 0x4))
11646         return &bad_opcode;
11647
11648       switch ((*codep & 0x3))
11649         {
11650         case 0:
11651           break;
11652         case 1:
11653           vex.prefix = DATA_PREFIX_OPCODE;
11654           break;
11655         case 2:
11656           vex.prefix = REPE_PREFIX_OPCODE;
11657           break;
11658         case 3:
11659           vex.prefix = REPNE_PREFIX_OPCODE;
11660           break;
11661         }
11662
11663       /* The third byte after 0x62.  */
11664       codep++;
11665
11666       /* Remember the static rounding bits.  */
11667       vex.ll = (*codep >> 5) & 3;
11668       vex.b = (*codep & 0x10) != 0;
11669
11670       vex.v = *codep & 0x8;
11671       vex.mask_register_specifier = *codep & 0x7;
11672       vex.zeroing = *codep & 0x80;
11673
11674       if (address_mode != mode_64bit)
11675         {
11676           /* In 16/32-bit mode silently ignore following bits.  */
11677           rex &= ~REX_B;
11678           vex.r = 1;
11679           vex.v = 1;
11680         }
11681
11682       need_vex = 1;
11683       need_vex_reg = 1;
11684       codep++;
11685       vindex = *codep++;
11686       dp = &evex_table[vex_table_index][vindex];
11687       end_codep = codep;
11688       FETCH_DATA (info, codep + 1);
11689       modrm.mod = (*codep >> 6) & 3;
11690       modrm.reg = (*codep >> 3) & 7;
11691       modrm.rm = *codep & 7;
11692
11693       /* Set vector length.  */
11694       if (modrm.mod == 3 && vex.b)
11695         vex.length = 512;
11696       else
11697         {
11698           switch (vex.ll)
11699             {
11700             case 0x0:
11701               vex.length = 128;
11702               break;
11703             case 0x1:
11704               vex.length = 256;
11705               break;
11706             case 0x2:
11707               vex.length = 512;
11708               break;
11709             default:
11710               return &bad_opcode;
11711             }
11712         }
11713       break;
11714
11715     case 0:
11716       dp = &bad_opcode;
11717       break;
11718
11719     default:
11720       abort ();
11721     }
11722
11723   if (dp->name != NULL)
11724     return dp;
11725   else
11726     return get_valid_dis386 (dp, info);
11727 }
11728
11729 static void
11730 get_sib (disassemble_info *info, int sizeflag)
11731 {
11732   /* If modrm.mod == 3, operand must be register.  */
11733   if (need_modrm
11734       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11735       && modrm.mod != 3
11736       && modrm.rm == 4)
11737     {
11738       FETCH_DATA (info, codep + 2);
11739       sib.index = (codep [1] >> 3) & 7;
11740       sib.scale = (codep [1] >> 6) & 3;
11741       sib.base = codep [1] & 7;
11742     }
11743 }
11744
11745 static int
11746 print_insn (bfd_vma pc, disassemble_info *info)
11747 {
11748   const struct dis386 *dp;
11749   int i;
11750   char *op_txt[MAX_OPERANDS];
11751   int needcomma;
11752   int sizeflag, orig_sizeflag;
11753   const char *p;
11754   struct dis_private priv;
11755   int prefix_length;
11756
11757   priv.orig_sizeflag = AFLAG | DFLAG;
11758   if ((info->mach & bfd_mach_i386_i386) != 0)
11759     address_mode = mode_32bit;
11760   else if (info->mach == bfd_mach_i386_i8086)
11761     {
11762       address_mode = mode_16bit;
11763       priv.orig_sizeflag = 0;
11764     }
11765   else
11766     address_mode = mode_64bit;
11767
11768   if (intel_syntax == (char) -1)
11769     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11770
11771   for (p = info->disassembler_options; p != NULL; )
11772     {
11773       if (CONST_STRNEQ (p, "amd64"))
11774         isa64 = amd64;
11775       else if (CONST_STRNEQ (p, "intel64"))
11776         isa64 = intel64;
11777       else if (CONST_STRNEQ (p, "x86-64"))
11778         {
11779           address_mode = mode_64bit;
11780           priv.orig_sizeflag |= AFLAG | DFLAG;
11781         }
11782       else if (CONST_STRNEQ (p, "i386"))
11783         {
11784           address_mode = mode_32bit;
11785           priv.orig_sizeflag |= AFLAG | DFLAG;
11786         }
11787       else if (CONST_STRNEQ (p, "i8086"))
11788         {
11789           address_mode = mode_16bit;
11790           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11791         }
11792       else if (CONST_STRNEQ (p, "intel"))
11793         {
11794           intel_syntax = 1;
11795           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11796             intel_mnemonic = 1;
11797         }
11798       else if (CONST_STRNEQ (p, "att"))
11799         {
11800           intel_syntax = 0;
11801           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11802             intel_mnemonic = 0;
11803         }
11804       else if (CONST_STRNEQ (p, "addr"))
11805         {
11806           if (address_mode == mode_64bit)
11807             {
11808               if (p[4] == '3' && p[5] == '2')
11809                 priv.orig_sizeflag &= ~AFLAG;
11810               else if (p[4] == '6' && p[5] == '4')
11811                 priv.orig_sizeflag |= AFLAG;
11812             }
11813           else
11814             {
11815               if (p[4] == '1' && p[5] == '6')
11816                 priv.orig_sizeflag &= ~AFLAG;
11817               else if (p[4] == '3' && p[5] == '2')
11818                 priv.orig_sizeflag |= AFLAG;
11819             }
11820         }
11821       else if (CONST_STRNEQ (p, "data"))
11822         {
11823           if (p[4] == '1' && p[5] == '6')
11824             priv.orig_sizeflag &= ~DFLAG;
11825           else if (p[4] == '3' && p[5] == '2')
11826             priv.orig_sizeflag |= DFLAG;
11827         }
11828       else if (CONST_STRNEQ (p, "suffix"))
11829         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11830
11831       p = strchr (p, ',');
11832       if (p != NULL)
11833         p++;
11834     }
11835
11836   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11837     {
11838       (*info->fprintf_func) (info->stream,
11839                              _("64-bit address is disabled"));
11840       return -1;
11841     }
11842
11843   if (intel_syntax)
11844     {
11845       names64 = intel_names64;
11846       names32 = intel_names32;
11847       names16 = intel_names16;
11848       names8 = intel_names8;
11849       names8rex = intel_names8rex;
11850       names_seg = intel_names_seg;
11851       names_mm = intel_names_mm;
11852       names_bnd = intel_names_bnd;
11853       names_xmm = intel_names_xmm;
11854       names_ymm = intel_names_ymm;
11855       names_zmm = intel_names_zmm;
11856       index64 = intel_index64;
11857       index32 = intel_index32;
11858       names_mask = intel_names_mask;
11859       index16 = intel_index16;
11860       open_char = '[';
11861       close_char = ']';
11862       separator_char = '+';
11863       scale_char = '*';
11864     }
11865   else
11866     {
11867       names64 = att_names64;
11868       names32 = att_names32;
11869       names16 = att_names16;
11870       names8 = att_names8;
11871       names8rex = att_names8rex;
11872       names_seg = att_names_seg;
11873       names_mm = att_names_mm;
11874       names_bnd = att_names_bnd;
11875       names_xmm = att_names_xmm;
11876       names_ymm = att_names_ymm;
11877       names_zmm = att_names_zmm;
11878       index64 = att_index64;
11879       index32 = att_index32;
11880       names_mask = att_names_mask;
11881       index16 = att_index16;
11882       open_char = '(';
11883       close_char =  ')';
11884       separator_char = ',';
11885       scale_char = ',';
11886     }
11887
11888   /* The output looks better if we put 7 bytes on a line, since that
11889      puts most long word instructions on a single line.  Use 8 bytes
11890      for Intel L1OM.  */
11891   if ((info->mach & bfd_mach_l1om) != 0)
11892     info->bytes_per_line = 8;
11893   else
11894     info->bytes_per_line = 7;
11895
11896   info->private_data = &priv;
11897   priv.max_fetched = priv.the_buffer;
11898   priv.insn_start = pc;
11899
11900   obuf[0] = 0;
11901   for (i = 0; i < MAX_OPERANDS; ++i)
11902     {
11903       op_out[i][0] = 0;
11904       op_index[i] = -1;
11905     }
11906
11907   the_info = info;
11908   start_pc = pc;
11909   start_codep = priv.the_buffer;
11910   codep = priv.the_buffer;
11911
11912   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11913     {
11914       const char *name;
11915
11916       /* Getting here means we tried for data but didn't get it.  That
11917          means we have an incomplete instruction of some sort.  Just
11918          print the first byte as a prefix or a .byte pseudo-op.  */
11919       if (codep > priv.the_buffer)
11920         {
11921           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11922           if (name != NULL)
11923             (*info->fprintf_func) (info->stream, "%s", name);
11924           else
11925             {
11926               /* Just print the first byte as a .byte instruction.  */
11927               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11928                                      (unsigned int) priv.the_buffer[0]);
11929             }
11930
11931           return 1;
11932         }
11933
11934       return -1;
11935     }
11936
11937   obufp = obuf;
11938   sizeflag = priv.orig_sizeflag;
11939
11940   if (!ckprefix () || rex_used)
11941     {
11942       /* Too many prefixes or unused REX prefixes.  */
11943       for (i = 0;
11944            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11945            i++)
11946         (*info->fprintf_func) (info->stream, "%s%s",
11947                                i == 0 ? "" : " ",
11948                                prefix_name (all_prefixes[i], sizeflag));
11949       return i;
11950     }
11951
11952   insn_codep = codep;
11953
11954   FETCH_DATA (info, codep + 1);
11955   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11956
11957   if (((prefixes & PREFIX_FWAIT)
11958        && ((*codep < 0xd8) || (*codep > 0xdf))))
11959     {
11960       /* Handle prefixes before fwait.  */
11961       for (i = 0; i < fwait_prefix && all_prefixes[i];
11962            i++)
11963         (*info->fprintf_func) (info->stream, "%s ",
11964                                prefix_name (all_prefixes[i], sizeflag));
11965       (*info->fprintf_func) (info->stream, "fwait");
11966       return i + 1;
11967     }
11968
11969   if (*codep == 0x0f)
11970     {
11971       unsigned char threebyte;
11972
11973       codep++;
11974       FETCH_DATA (info, codep + 1);
11975       threebyte = *codep;
11976       dp = &dis386_twobyte[threebyte];
11977       need_modrm = twobyte_has_modrm[*codep];
11978       codep++;
11979     }
11980   else
11981     {
11982       dp = &dis386[*codep];
11983       need_modrm = onebyte_has_modrm[*codep];
11984       codep++;
11985     }
11986
11987   /* Save sizeflag for printing the extra prefixes later before updating
11988      it for mnemonic and operand processing.  The prefix names depend
11989      only on the address mode.  */
11990   orig_sizeflag = sizeflag;
11991   if (prefixes & PREFIX_ADDR)
11992     sizeflag ^= AFLAG;
11993   if ((prefixes & PREFIX_DATA))
11994     sizeflag ^= DFLAG;
11995
11996   end_codep = codep;
11997   if (need_modrm)
11998     {
11999       FETCH_DATA (info, codep + 1);
12000       modrm.mod = (*codep >> 6) & 3;
12001       modrm.reg = (*codep >> 3) & 7;
12002       modrm.rm = *codep & 7;
12003     }
12004
12005   need_vex = 0;
12006   need_vex_reg = 0;
12007   vex_w_done = 0;
12008   memset (&vex, 0, sizeof (vex));
12009
12010   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12011     {
12012       get_sib (info, sizeflag);
12013       dofloat (sizeflag);
12014     }
12015   else
12016     {
12017       dp = get_valid_dis386 (dp, info);
12018       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12019         {
12020           get_sib (info, sizeflag);
12021           for (i = 0; i < MAX_OPERANDS; ++i)
12022             {
12023               obufp = op_out[i];
12024               op_ad = MAX_OPERANDS - 1 - i;
12025               if (dp->op[i].rtn)
12026                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12027               /* For EVEX instruction after the last operand masking
12028                  should be printed.  */
12029               if (i == 0 && vex.evex)
12030                 {
12031                   /* Don't print {%k0}.  */
12032                   if (vex.mask_register_specifier)
12033                     {
12034                       oappend ("{");
12035                       oappend (names_mask[vex.mask_register_specifier]);
12036                       oappend ("}");
12037                     }
12038                   if (vex.zeroing)
12039                     oappend ("{z}");
12040                 }
12041             }
12042         }
12043     }
12044
12045   /* Clear instruction information.  */
12046   if (the_info)
12047     {
12048       the_info->insn_info_valid = 0;
12049       the_info->branch_delay_insns = 0;
12050       the_info->data_size = 0;
12051       the_info->insn_type = dis_noninsn;
12052       the_info->target = 0;
12053       the_info->target2 = 0;
12054     }
12055
12056   /* Reset jump operation indicator.  */
12057   op_is_jump = FALSE;
12058
12059   {
12060     int jump_detection = 0;
12061
12062     /* Extract flags.  */
12063     for (i = 0; i < MAX_OPERANDS; ++i)
12064       {
12065         if ((dp->op[i].rtn == OP_J)
12066             || (dp->op[i].rtn == OP_indirE))
12067           jump_detection |= 1;
12068         else if ((dp->op[i].rtn == BND_Fixup)
12069                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12070           jump_detection |= 2;
12071         else if ((dp->op[i].bytemode == cond_jump_mode)
12072                  || (dp->op[i].bytemode == loop_jcxz_mode))
12073           jump_detection |= 4;
12074       }
12075
12076     /* Determine if this is a jump or branch.  */
12077     if ((jump_detection & 0x3) == 0x3)
12078       {
12079         op_is_jump = TRUE;
12080         if (jump_detection & 0x4)
12081           the_info->insn_type = dis_condbranch;
12082         else
12083           the_info->insn_type =
12084             (dp->name && !strncmp(dp->name, "call", 4))
12085             ? dis_jsr : dis_branch;
12086       }
12087   }
12088
12089   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12090      are all 0s in inverted form.  */
12091   if (need_vex && vex.register_specifier != 0)
12092     {
12093       (*info->fprintf_func) (info->stream, "(bad)");
12094       return end_codep - priv.the_buffer;
12095     }
12096
12097   /* Check if the REX prefix is used.  */
12098   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12099     all_prefixes[last_rex_prefix] = 0;
12100
12101   /* Check if the SEG prefix is used.  */
12102   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12103                    | PREFIX_FS | PREFIX_GS)) != 0
12104       && (used_prefixes & active_seg_prefix) != 0)
12105     all_prefixes[last_seg_prefix] = 0;
12106
12107   /* Check if the ADDR prefix is used.  */
12108   if ((prefixes & PREFIX_ADDR) != 0
12109       && (used_prefixes & PREFIX_ADDR) != 0)
12110     all_prefixes[last_addr_prefix] = 0;
12111
12112   /* Check if the DATA prefix is used.  */
12113   if ((prefixes & PREFIX_DATA) != 0
12114       && (used_prefixes & PREFIX_DATA) != 0
12115       && !need_vex)
12116     all_prefixes[last_data_prefix] = 0;
12117
12118   /* Print the extra prefixes.  */
12119   prefix_length = 0;
12120   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12121     if (all_prefixes[i])
12122       {
12123         const char *name;
12124         name = prefix_name (all_prefixes[i], orig_sizeflag);
12125         if (name == NULL)
12126           abort ();
12127         prefix_length += strlen (name) + 1;
12128         (*info->fprintf_func) (info->stream, "%s ", name);
12129       }
12130
12131   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12132      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12133      used by putop and MMX/SSE operand and may be overriden by the
12134      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12135      separately.  */
12136   if (dp->prefix_requirement == PREFIX_OPCODE
12137       && (((need_vex
12138             ? vex.prefix == REPE_PREFIX_OPCODE
12139               || vex.prefix == REPNE_PREFIX_OPCODE
12140             : (prefixes
12141                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12142            && (used_prefixes
12143                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12144           || (((need_vex
12145                 ? vex.prefix == DATA_PREFIX_OPCODE
12146                 : ((prefixes
12147                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12148                    == PREFIX_DATA))
12149                && (used_prefixes & PREFIX_DATA) == 0))
12150           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12151     {
12152       (*info->fprintf_func) (info->stream, "(bad)");
12153       return end_codep - priv.the_buffer;
12154     }
12155
12156   /* Check maximum code length.  */
12157   if ((codep - start_codep) > MAX_CODE_LENGTH)
12158     {
12159       (*info->fprintf_func) (info->stream, "(bad)");
12160       return MAX_CODE_LENGTH;
12161     }
12162
12163   obufp = mnemonicendp;
12164   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12165     oappend (" ");
12166   oappend (" ");
12167   (*info->fprintf_func) (info->stream, "%s", obuf);
12168
12169   /* The enter and bound instructions are printed with operands in the same
12170      order as the intel book; everything else is printed in reverse order.  */
12171   if (intel_syntax || two_source_ops)
12172     {
12173       bfd_vma riprel;
12174
12175       for (i = 0; i < MAX_OPERANDS; ++i)
12176         op_txt[i] = op_out[i];
12177
12178       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12179           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12180         {
12181           op_txt[2] = op_out[3];
12182           op_txt[3] = op_out[2];
12183         }
12184
12185       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12186         {
12187           op_ad = op_index[i];
12188           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12189           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12190           riprel = op_riprel[i];
12191           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12192           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12193         }
12194     }
12195   else
12196     {
12197       for (i = 0; i < MAX_OPERANDS; ++i)
12198         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12199     }
12200
12201   needcomma = 0;
12202   for (i = 0; i < MAX_OPERANDS; ++i)
12203     if (*op_txt[i])
12204       {
12205         if (needcomma)
12206           (*info->fprintf_func) (info->stream, ",");
12207         if (op_index[i] != -1 && !op_riprel[i])
12208           {
12209             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12210
12211             if (the_info && op_is_jump)
12212               {
12213                 the_info->insn_info_valid = 1;
12214                 the_info->branch_delay_insns = 0;
12215                 the_info->data_size = 0;
12216                 the_info->target = target;
12217                 the_info->target2 = 0;
12218               }
12219             (*info->print_address_func) (target, info);
12220           }
12221         else
12222           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12223         needcomma = 1;
12224       }
12225
12226   for (i = 0; i < MAX_OPERANDS; i++)
12227     if (op_index[i] != -1 && op_riprel[i])
12228       {
12229         (*info->fprintf_func) (info->stream, "        # ");
12230         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12231                                                 + op_address[op_index[i]]), info);
12232         break;
12233       }
12234   return codep - priv.the_buffer;
12235 }
12236
12237 static const char *float_mem[] = {
12238   /* d8 */
12239   "fadd{s|}",
12240   "fmul{s|}",
12241   "fcom{s|}",
12242   "fcomp{s|}",
12243   "fsub{s|}",
12244   "fsubr{s|}",
12245   "fdiv{s|}",
12246   "fdivr{s|}",
12247   /* d9 */
12248   "fld{s|}",
12249   "(bad)",
12250   "fst{s|}",
12251   "fstp{s|}",
12252   "fldenv{C|C}",
12253   "fldcw",
12254   "fNstenv{C|C}",
12255   "fNstcw",
12256   /* da */
12257   "fiadd{l|}",
12258   "fimul{l|}",
12259   "ficom{l|}",
12260   "ficomp{l|}",
12261   "fisub{l|}",
12262   "fisubr{l|}",
12263   "fidiv{l|}",
12264   "fidivr{l|}",
12265   /* db */
12266   "fild{l|}",
12267   "fisttp{l|}",
12268   "fist{l|}",
12269   "fistp{l|}",
12270   "(bad)",
12271   "fld{t|}",
12272   "(bad)",
12273   "fstp{t|}",
12274   /* dc */
12275   "fadd{l|}",
12276   "fmul{l|}",
12277   "fcom{l|}",
12278   "fcomp{l|}",
12279   "fsub{l|}",
12280   "fsubr{l|}",
12281   "fdiv{l|}",
12282   "fdivr{l|}",
12283   /* dd */
12284   "fld{l|}",
12285   "fisttp{ll|}",
12286   "fst{l||}",
12287   "fstp{l|}",
12288   "frstor{C|C}",
12289   "(bad)",
12290   "fNsave{C|C}",
12291   "fNstsw",
12292   /* de */
12293   "fiadd{s|}",
12294   "fimul{s|}",
12295   "ficom{s|}",
12296   "ficomp{s|}",
12297   "fisub{s|}",
12298   "fisubr{s|}",
12299   "fidiv{s|}",
12300   "fidivr{s|}",
12301   /* df */
12302   "fild{s|}",
12303   "fisttp{s|}",
12304   "fist{s|}",
12305   "fistp{s|}",
12306   "fbld",
12307   "fild{ll|}",
12308   "fbstp",
12309   "fistp{ll|}",
12310 };
12311
12312 static const unsigned char float_mem_mode[] = {
12313   /* d8 */
12314   d_mode,
12315   d_mode,
12316   d_mode,
12317   d_mode,
12318   d_mode,
12319   d_mode,
12320   d_mode,
12321   d_mode,
12322   /* d9 */
12323   d_mode,
12324   0,
12325   d_mode,
12326   d_mode,
12327   0,
12328   w_mode,
12329   0,
12330   w_mode,
12331   /* da */
12332   d_mode,
12333   d_mode,
12334   d_mode,
12335   d_mode,
12336   d_mode,
12337   d_mode,
12338   d_mode,
12339   d_mode,
12340   /* db */
12341   d_mode,
12342   d_mode,
12343   d_mode,
12344   d_mode,
12345   0,
12346   t_mode,
12347   0,
12348   t_mode,
12349   /* dc */
12350   q_mode,
12351   q_mode,
12352   q_mode,
12353   q_mode,
12354   q_mode,
12355   q_mode,
12356   q_mode,
12357   q_mode,
12358   /* dd */
12359   q_mode,
12360   q_mode,
12361   q_mode,
12362   q_mode,
12363   0,
12364   0,
12365   0,
12366   w_mode,
12367   /* de */
12368   w_mode,
12369   w_mode,
12370   w_mode,
12371   w_mode,
12372   w_mode,
12373   w_mode,
12374   w_mode,
12375   w_mode,
12376   /* df */
12377   w_mode,
12378   w_mode,
12379   w_mode,
12380   w_mode,
12381   t_mode,
12382   q_mode,
12383   t_mode,
12384   q_mode
12385 };
12386
12387 #define ST { OP_ST, 0 }
12388 #define STi { OP_STi, 0 }
12389
12390 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12391 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12392 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12393 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12394 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12395 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12396 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12397 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12398 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12399
12400 static const struct dis386 float_reg[][8] = {
12401   /* d8 */
12402   {
12403     { "fadd",   { ST, STi }, 0 },
12404     { "fmul",   { ST, STi }, 0 },
12405     { "fcom",   { STi }, 0 },
12406     { "fcomp",  { STi }, 0 },
12407     { "fsub",   { ST, STi }, 0 },
12408     { "fsubr",  { ST, STi }, 0 },
12409     { "fdiv",   { ST, STi }, 0 },
12410     { "fdivr",  { ST, STi }, 0 },
12411   },
12412   /* d9 */
12413   {
12414     { "fld",    { STi }, 0 },
12415     { "fxch",   { STi }, 0 },
12416     { FGRPd9_2 },
12417     { Bad_Opcode },
12418     { FGRPd9_4 },
12419     { FGRPd9_5 },
12420     { FGRPd9_6 },
12421     { FGRPd9_7 },
12422   },
12423   /* da */
12424   {
12425     { "fcmovb", { ST, STi }, 0 },
12426     { "fcmove", { ST, STi }, 0 },
12427     { "fcmovbe",{ ST, STi }, 0 },
12428     { "fcmovu", { ST, STi }, 0 },
12429     { Bad_Opcode },
12430     { FGRPda_5 },
12431     { Bad_Opcode },
12432     { Bad_Opcode },
12433   },
12434   /* db */
12435   {
12436     { "fcmovnb",{ ST, STi }, 0 },
12437     { "fcmovne",{ ST, STi }, 0 },
12438     { "fcmovnbe",{ ST, STi }, 0 },
12439     { "fcmovnu",{ ST, STi }, 0 },
12440     { FGRPdb_4 },
12441     { "fucomi", { ST, STi }, 0 },
12442     { "fcomi",  { ST, STi }, 0 },
12443     { Bad_Opcode },
12444   },
12445   /* dc */
12446   {
12447     { "fadd",   { STi, ST }, 0 },
12448     { "fmul",   { STi, ST }, 0 },
12449     { Bad_Opcode },
12450     { Bad_Opcode },
12451     { "fsub{!M|r}",     { STi, ST }, 0 },
12452     { "fsub{M|}",       { STi, ST }, 0 },
12453     { "fdiv{!M|r}",     { STi, ST }, 0 },
12454     { "fdiv{M|}",       { STi, ST }, 0 },
12455   },
12456   /* dd */
12457   {
12458     { "ffree",  { STi }, 0 },
12459     { Bad_Opcode },
12460     { "fst",    { STi }, 0 },
12461     { "fstp",   { STi }, 0 },
12462     { "fucom",  { STi }, 0 },
12463     { "fucomp", { STi }, 0 },
12464     { Bad_Opcode },
12465     { Bad_Opcode },
12466   },
12467   /* de */
12468   {
12469     { "faddp",  { STi, ST }, 0 },
12470     { "fmulp",  { STi, ST }, 0 },
12471     { Bad_Opcode },
12472     { FGRPde_3 },
12473     { "fsub{!M|r}p",    { STi, ST }, 0 },
12474     { "fsub{M|}p",      { STi, ST }, 0 },
12475     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12476     { "fdiv{M|}p",      { STi, ST }, 0 },
12477   },
12478   /* df */
12479   {
12480     { "ffreep", { STi }, 0 },
12481     { Bad_Opcode },
12482     { Bad_Opcode },
12483     { Bad_Opcode },
12484     { FGRPdf_4 },
12485     { "fucomip", { ST, STi }, 0 },
12486     { "fcomip", { ST, STi }, 0 },
12487     { Bad_Opcode },
12488   },
12489 };
12490
12491 static char *fgrps[][8] = {
12492   /* Bad opcode 0 */
12493   {
12494     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12495   },
12496
12497   /* d9_2  1 */
12498   {
12499     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12500   },
12501
12502   /* d9_4  2 */
12503   {
12504     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12505   },
12506
12507   /* d9_5  3 */
12508   {
12509     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12510   },
12511
12512   /* d9_6  4 */
12513   {
12514     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12515   },
12516
12517   /* d9_7  5 */
12518   {
12519     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12520   },
12521
12522   /* da_5  6 */
12523   {
12524     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12525   },
12526
12527   /* db_4  7 */
12528   {
12529     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12530     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12531   },
12532
12533   /* de_3  8 */
12534   {
12535     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12536   },
12537
12538   /* df_4  9 */
12539   {
12540     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12541   },
12542 };
12543
12544 static void
12545 swap_operand (void)
12546 {
12547   mnemonicendp[0] = '.';
12548   mnemonicendp[1] = 's';
12549   mnemonicendp += 2;
12550 }
12551
12552 static void
12553 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12554                int sizeflag ATTRIBUTE_UNUSED)
12555 {
12556   /* Skip mod/rm byte.  */
12557   MODRM_CHECK;
12558   codep++;
12559 }
12560
12561 static void
12562 dofloat (int sizeflag)
12563 {
12564   const struct dis386 *dp;
12565   unsigned char floatop;
12566
12567   floatop = codep[-1];
12568
12569   if (modrm.mod != 3)
12570     {
12571       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12572
12573       putop (float_mem[fp_indx], sizeflag);
12574       obufp = op_out[0];
12575       op_ad = 2;
12576       OP_E (float_mem_mode[fp_indx], sizeflag);
12577       return;
12578     }
12579   /* Skip mod/rm byte.  */
12580   MODRM_CHECK;
12581   codep++;
12582
12583   dp = &float_reg[floatop - 0xd8][modrm.reg];
12584   if (dp->name == NULL)
12585     {
12586       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12587
12588       /* Instruction fnstsw is only one with strange arg.  */
12589       if (floatop == 0xdf && codep[-1] == 0xe0)
12590         strcpy (op_out[0], names16[0]);
12591     }
12592   else
12593     {
12594       putop (dp->name, sizeflag);
12595
12596       obufp = op_out[0];
12597       op_ad = 2;
12598       if (dp->op[0].rtn)
12599         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12600
12601       obufp = op_out[1];
12602       op_ad = 1;
12603       if (dp->op[1].rtn)
12604         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12605     }
12606 }
12607
12608 /* Like oappend (below), but S is a string starting with '%'.
12609    In Intel syntax, the '%' is elided.  */
12610 static void
12611 oappend_maybe_intel (const char *s)
12612 {
12613   oappend (s + intel_syntax);
12614 }
12615
12616 static void
12617 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12618 {
12619   oappend_maybe_intel ("%st");
12620 }
12621
12622 static void
12623 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12624 {
12625   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12626   oappend_maybe_intel (scratchbuf);
12627 }
12628
12629 /* Capital letters in template are macros.  */
12630 static int
12631 putop (const char *in_template, int sizeflag)
12632 {
12633   const char *p;
12634   int alt = 0;
12635   int cond = 1;
12636   unsigned int l = 0, len = 1;
12637   char last[4];
12638
12639 #define SAVE_LAST(c)                    \
12640   if (l < len && l < sizeof (last))     \
12641     last[l++] = c;                      \
12642   else                                  \
12643     abort ();
12644
12645   for (p = in_template; *p; p++)
12646     {
12647       switch (*p)
12648         {
12649         default:
12650           *obufp++ = *p;
12651           break;
12652         case '%':
12653           len++;
12654           break;
12655         case '!':
12656           cond = 0;
12657           break;
12658         case '{':
12659           if (intel_syntax)
12660             {
12661               while (*++p != '|')
12662                 if (*p == '}' || *p == '\0')
12663                   abort ();
12664               alt = 1;
12665             }
12666           break;
12667         case '|':
12668           while (*++p != '}')
12669             {
12670               if (*p == '\0')
12671                 abort ();
12672             }
12673           break;
12674         case '}':
12675           alt = 0;
12676           break;
12677         case 'A':
12678           if (intel_syntax)
12679             break;
12680           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12681             *obufp++ = 'b';
12682           break;
12683         case 'B':
12684           if (l == 0 && len == 1)
12685             {
12686             case_B:
12687               if (intel_syntax)
12688                 break;
12689               if (sizeflag & SUFFIX_ALWAYS)
12690                 *obufp++ = 'b';
12691             }
12692           else
12693             {
12694               if (l != 1
12695                   || len != 2
12696                   || last[0] != 'L')
12697                 {
12698                   SAVE_LAST (*p);
12699                   break;
12700                 }
12701
12702               if (address_mode == mode_64bit
12703                   && !(prefixes & PREFIX_ADDR))
12704                 {
12705                   *obufp++ = 'a';
12706                   *obufp++ = 'b';
12707                   *obufp++ = 's';
12708                 }
12709
12710               goto case_B;
12711             }
12712           break;
12713         case 'C':
12714           if (intel_syntax && !alt)
12715             break;
12716           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12717             {
12718               if (sizeflag & DFLAG)
12719                 *obufp++ = intel_syntax ? 'd' : 'l';
12720               else
12721                 *obufp++ = intel_syntax ? 'w' : 's';
12722               used_prefixes |= (prefixes & PREFIX_DATA);
12723             }
12724           break;
12725         case 'D':
12726           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12727             break;
12728           USED_REX (REX_W);
12729           if (modrm.mod == 3)
12730             {
12731               if (rex & REX_W)
12732                 *obufp++ = 'q';
12733               else
12734                 {
12735                   if (sizeflag & DFLAG)
12736                     *obufp++ = intel_syntax ? 'd' : 'l';
12737                   else
12738                     *obufp++ = 'w';
12739                   used_prefixes |= (prefixes & PREFIX_DATA);
12740                 }
12741             }
12742           else
12743             *obufp++ = 'w';
12744           break;
12745         case 'E':               /* For jcxz/jecxz */
12746           if (address_mode == mode_64bit)
12747             {
12748               if (sizeflag & AFLAG)
12749                 *obufp++ = 'r';
12750               else
12751                 *obufp++ = 'e';
12752             }
12753           else
12754             if (sizeflag & AFLAG)
12755               *obufp++ = 'e';
12756           used_prefixes |= (prefixes & PREFIX_ADDR);
12757           break;
12758         case 'F':
12759           if (intel_syntax)
12760             break;
12761           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12762             {
12763               if (sizeflag & AFLAG)
12764                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12765               else
12766                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12767               used_prefixes |= (prefixes & PREFIX_ADDR);
12768             }
12769           break;
12770         case 'G':
12771           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12772             break;
12773           if ((rex & REX_W) || (sizeflag & DFLAG))
12774             *obufp++ = 'l';
12775           else
12776             *obufp++ = 'w';
12777           if (!(rex & REX_W))
12778             used_prefixes |= (prefixes & PREFIX_DATA);
12779           break;
12780         case 'H':
12781           if (intel_syntax)
12782             break;
12783           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12784               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12785             {
12786               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12787               *obufp++ = ',';
12788               *obufp++ = 'p';
12789               if (prefixes & PREFIX_DS)
12790                 *obufp++ = 't';
12791               else
12792                 *obufp++ = 'n';
12793             }
12794           break;
12795         case 'K':
12796           USED_REX (REX_W);
12797           if (rex & REX_W)
12798             *obufp++ = 'q';
12799           else
12800             *obufp++ = 'd';
12801           break;
12802         case 'Z':
12803           if (l != 0 || len != 1)
12804             {
12805               if (l != 1 || len != 2 || last[0] != 'X')
12806                 {
12807                   SAVE_LAST (*p);
12808                   break;
12809                 }
12810               if (!need_vex || !vex.evex)
12811                 abort ();
12812               if (intel_syntax
12813                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12814                 break;
12815               switch (vex.length)
12816                 {
12817                 case 128:
12818                   *obufp++ = 'x';
12819                   break;
12820                 case 256:
12821                   *obufp++ = 'y';
12822                   break;
12823                 case 512:
12824                   *obufp++ = 'z';
12825                   break;
12826                 default:
12827                   abort ();
12828                 }
12829               break;
12830             }
12831           if (intel_syntax)
12832             break;
12833           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12834             {
12835               *obufp++ = 'q';
12836               break;
12837             }
12838           /* Fall through.  */
12839           goto case_L;
12840         case 'L':
12841           if (l != 0 || len != 1)
12842             {
12843               SAVE_LAST (*p);
12844               break;
12845             }
12846         case_L:
12847           if (intel_syntax)
12848             break;
12849           if (sizeflag & SUFFIX_ALWAYS)
12850             *obufp++ = 'l';
12851           break;
12852         case 'M':
12853           if (intel_mnemonic != cond)
12854             *obufp++ = 'r';
12855           break;
12856         case 'N':
12857           if ((prefixes & PREFIX_FWAIT) == 0)
12858             *obufp++ = 'n';
12859           else
12860             used_prefixes |= PREFIX_FWAIT;
12861           break;
12862         case 'O':
12863           USED_REX (REX_W);
12864           if (rex & REX_W)
12865             *obufp++ = 'o';
12866           else if (intel_syntax && (sizeflag & DFLAG))
12867             *obufp++ = 'q';
12868           else
12869             *obufp++ = 'd';
12870           if (!(rex & REX_W))
12871             used_prefixes |= (prefixes & PREFIX_DATA);
12872           break;
12873         case '&':
12874           if (!intel_syntax
12875               && address_mode == mode_64bit
12876               && isa64 == intel64)
12877             {
12878               *obufp++ = 'q';
12879               break;
12880             }
12881           /* Fall through.  */
12882         case 'T':
12883           if (!intel_syntax
12884               && address_mode == mode_64bit
12885               && ((sizeflag & DFLAG) || (rex & REX_W)))
12886             {
12887               *obufp++ = 'q';
12888               break;
12889             }
12890           /* Fall through.  */
12891           goto case_P;
12892         case 'P':
12893           if (l == 0 && len == 1)
12894             {
12895             case_P:
12896               if (intel_syntax)
12897                 {
12898                   if ((rex & REX_W) == 0
12899                       && (prefixes & PREFIX_DATA))
12900                     {
12901                       if ((sizeflag & DFLAG) == 0)
12902                         *obufp++ = 'w';
12903                       used_prefixes |= (prefixes & PREFIX_DATA);
12904                     }
12905                   break;
12906                 }
12907               if ((prefixes & PREFIX_DATA)
12908                   || (rex & REX_W)
12909                   || (sizeflag & SUFFIX_ALWAYS))
12910                 {
12911                   USED_REX (REX_W);
12912                   if (rex & REX_W)
12913                     *obufp++ = 'q';
12914                   else
12915                     {
12916                       if (sizeflag & DFLAG)
12917                         *obufp++ = 'l';
12918                       else
12919                         *obufp++ = 'w';
12920                       used_prefixes |= (prefixes & PREFIX_DATA);
12921                     }
12922                 }
12923             }
12924           else
12925             {
12926               if (l != 1 || len != 2 || last[0] != 'L')
12927                 {
12928                   SAVE_LAST (*p);
12929                   break;
12930                 }
12931
12932               if ((prefixes & PREFIX_DATA)
12933                   || (rex & REX_W)
12934                   || (sizeflag & SUFFIX_ALWAYS))
12935                 {
12936                   USED_REX (REX_W);
12937                   if (rex & REX_W)
12938                     *obufp++ = 'q';
12939                   else
12940                     {
12941                       if (sizeflag & DFLAG)
12942                         *obufp++ = intel_syntax ? 'd' : 'l';
12943                       else
12944                         *obufp++ = 'w';
12945                       used_prefixes |= (prefixes & PREFIX_DATA);
12946                     }
12947                 }
12948             }
12949           break;
12950         case 'U':
12951           if (intel_syntax)
12952             break;
12953           if (address_mode == mode_64bit
12954               && ((sizeflag & DFLAG) || (rex & REX_W)))
12955             {
12956               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12957                 *obufp++ = 'q';
12958               break;
12959             }
12960           /* Fall through.  */
12961           goto case_Q;
12962         case 'Q':
12963           if (l == 0 && len == 1)
12964             {
12965             case_Q:
12966               if (intel_syntax && !alt)
12967                 break;
12968               USED_REX (REX_W);
12969               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12970                 {
12971                   if (rex & REX_W)
12972                     *obufp++ = 'q';
12973                   else
12974                     {
12975                       if (sizeflag & DFLAG)
12976                         *obufp++ = intel_syntax ? 'd' : 'l';
12977                       else
12978                         *obufp++ = 'w';
12979                       used_prefixes |= (prefixes & PREFIX_DATA);
12980                     }
12981                 }
12982             }
12983           else
12984             {
12985               if (l != 1 || len != 2 || last[0] != 'L')
12986                 {
12987                   SAVE_LAST (*p);
12988                   break;
12989                 }
12990               if ((intel_syntax && need_modrm)
12991                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12992                 break;
12993               if ((rex & REX_W))
12994                 {
12995                   USED_REX (REX_W);
12996                   *obufp++ = 'q';
12997                 }
12998               else if((address_mode == mode_64bit && need_modrm)
12999                       || (sizeflag & SUFFIX_ALWAYS))
13000                 *obufp++ = intel_syntax? 'd' : 'l';
13001             }
13002           break;
13003         case 'R':
13004           USED_REX (REX_W);
13005           if (rex & REX_W)
13006             *obufp++ = 'q';
13007           else if (sizeflag & DFLAG)
13008             {
13009               if (intel_syntax)
13010                   *obufp++ = 'd';
13011               else
13012                   *obufp++ = 'l';
13013             }
13014           else
13015             *obufp++ = 'w';
13016           if (intel_syntax && !p[1]
13017               && ((rex & REX_W) || (sizeflag & DFLAG)))
13018             *obufp++ = 'e';
13019           if (!(rex & REX_W))
13020             used_prefixes |= (prefixes & PREFIX_DATA);
13021           break;
13022         case 'V':
13023           if (l == 0 && len == 1)
13024             {
13025               if (intel_syntax)
13026                 break;
13027               if (address_mode == mode_64bit
13028                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13029                 {
13030                   if (sizeflag & SUFFIX_ALWAYS)
13031                     *obufp++ = 'q';
13032                   break;
13033                 }
13034             }
13035           else
13036             {
13037               if (l != 1
13038                   || len != 2
13039                   || last[0] != 'L')
13040                 {
13041                   SAVE_LAST (*p);
13042                   break;
13043                 }
13044
13045               if (rex & REX_W)
13046                 {
13047                   *obufp++ = 'a';
13048                   *obufp++ = 'b';
13049                   *obufp++ = 's';
13050                 }
13051             }
13052           /* Fall through.  */
13053           goto case_S;
13054         case 'S':
13055           if (l == 0 && len == 1)
13056             {
13057             case_S:
13058               if (intel_syntax)
13059                 break;
13060               if (sizeflag & SUFFIX_ALWAYS)
13061                 {
13062                   if (rex & REX_W)
13063                     *obufp++ = 'q';
13064                   else
13065                     {
13066                       if (sizeflag & DFLAG)
13067                         *obufp++ = 'l';
13068                       else
13069                         *obufp++ = 'w';
13070                       used_prefixes |= (prefixes & PREFIX_DATA);
13071                     }
13072                 }
13073             }
13074           else
13075             {
13076               if (l != 1
13077                   || len != 2
13078                   || last[0] != 'L')
13079                 {
13080                   SAVE_LAST (*p);
13081                   break;
13082                 }
13083
13084               if (address_mode == mode_64bit
13085                   && !(prefixes & PREFIX_ADDR))
13086                 {
13087                   *obufp++ = 'a';
13088                   *obufp++ = 'b';
13089                   *obufp++ = 's';
13090                 }
13091
13092               goto case_S;
13093             }
13094           break;
13095         case 'X':
13096           if (l != 0 || len != 1)
13097             {
13098               SAVE_LAST (*p);
13099               break;
13100             }
13101           if (need_vex
13102               ? vex.prefix == DATA_PREFIX_OPCODE
13103               : prefixes & PREFIX_DATA)
13104             {
13105               *obufp++ = 'd';
13106               used_prefixes |= PREFIX_DATA;
13107             }
13108           else
13109             *obufp++ = 's';
13110           break;
13111         case 'Y':
13112           if (l == 0 && len == 1)
13113             abort ();
13114           else
13115             {
13116               if (l != 1 || len != 2 || last[0] != 'X')
13117                 {
13118                   SAVE_LAST (*p);
13119                   break;
13120                 }
13121               if (!need_vex)
13122                 abort ();
13123               if (intel_syntax
13124                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13125                 break;
13126               switch (vex.length)
13127                 {
13128                 case 128:
13129                   *obufp++ = 'x';
13130                   break;
13131                 case 256:
13132                   *obufp++ = 'y';
13133                   break;
13134                 case 512:
13135                   if (!vex.evex)
13136                 default:
13137                     abort ();
13138                 }
13139             }
13140           break;
13141         case 'W':
13142           if (l == 0 && len == 1)
13143             {
13144               /* operand size flag for cwtl, cbtw */
13145               USED_REX (REX_W);
13146               if (rex & REX_W)
13147                 {
13148                   if (intel_syntax)
13149                     *obufp++ = 'd';
13150                   else
13151                     *obufp++ = 'l';
13152                 }
13153               else if (sizeflag & DFLAG)
13154                 *obufp++ = 'w';
13155               else
13156                 *obufp++ = 'b';
13157               if (!(rex & REX_W))
13158                 used_prefixes |= (prefixes & PREFIX_DATA);
13159             }
13160           else
13161             {
13162               if (l != 1
13163                   || len != 2
13164                   || (last[0] != 'X'
13165                       && last[0] != 'L'))
13166                 {
13167                   SAVE_LAST (*p);
13168                   break;
13169                 }
13170               if (!need_vex)
13171                 abort ();
13172               if (last[0] == 'X')
13173                 *obufp++ = vex.w ? 'd': 's';
13174               else
13175                 *obufp++ = vex.w ? 'q': 'd';
13176             }
13177           break;
13178         case '^':
13179           if (intel_syntax)
13180             break;
13181           if (isa64 == intel64 && (rex & REX_W))
13182             {
13183               USED_REX (REX_W);
13184               *obufp++ = 'q';
13185               break;
13186             }
13187           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13188             {
13189               if (sizeflag & DFLAG)
13190                 *obufp++ = 'l';
13191               else
13192                 *obufp++ = 'w';
13193               used_prefixes |= (prefixes & PREFIX_DATA);
13194             }
13195           break;
13196         case '@':
13197           if (intel_syntax)
13198             break;
13199           if (address_mode == mode_64bit
13200               && (isa64 == intel64
13201                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13202               *obufp++ = 'q';
13203           else if ((prefixes & PREFIX_DATA))
13204             {
13205               if (!(sizeflag & DFLAG))
13206                 *obufp++ = 'w';
13207               used_prefixes |= (prefixes & PREFIX_DATA);
13208             }
13209           break;
13210         }
13211     }
13212   *obufp = 0;
13213   mnemonicendp = obufp;
13214   return 0;
13215 }
13216
13217 static void
13218 oappend (const char *s)
13219 {
13220   obufp = stpcpy (obufp, s);
13221 }
13222
13223 static void
13224 append_seg (void)
13225 {
13226   /* Only print the active segment register.  */
13227   if (!active_seg_prefix)
13228     return;
13229
13230   used_prefixes |= active_seg_prefix;
13231   switch (active_seg_prefix)
13232     {
13233     case PREFIX_CS:
13234       oappend_maybe_intel ("%cs:");
13235       break;
13236     case PREFIX_DS:
13237       oappend_maybe_intel ("%ds:");
13238       break;
13239     case PREFIX_SS:
13240       oappend_maybe_intel ("%ss:");
13241       break;
13242     case PREFIX_ES:
13243       oappend_maybe_intel ("%es:");
13244       break;
13245     case PREFIX_FS:
13246       oappend_maybe_intel ("%fs:");
13247       break;
13248     case PREFIX_GS:
13249       oappend_maybe_intel ("%gs:");
13250       break;
13251     default:
13252       break;
13253     }
13254 }
13255
13256 static void
13257 OP_indirE (int bytemode, int sizeflag)
13258 {
13259   if (!intel_syntax)
13260     oappend ("*");
13261   OP_E (bytemode, sizeflag);
13262 }
13263
13264 static void
13265 print_operand_value (char *buf, int hex, bfd_vma disp)
13266 {
13267   if (address_mode == mode_64bit)
13268     {
13269       if (hex)
13270         {
13271           char tmp[30];
13272           int i;
13273           buf[0] = '0';
13274           buf[1] = 'x';
13275           sprintf_vma (tmp, disp);
13276           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13277           strcpy (buf + 2, tmp + i);
13278         }
13279       else
13280         {
13281           bfd_signed_vma v = disp;
13282           char tmp[30];
13283           int i;
13284           if (v < 0)
13285             {
13286               *(buf++) = '-';
13287               v = -disp;
13288               /* Check for possible overflow on 0x8000000000000000.  */
13289               if (v < 0)
13290                 {
13291                   strcpy (buf, "9223372036854775808");
13292                   return;
13293                 }
13294             }
13295           if (!v)
13296             {
13297               strcpy (buf, "0");
13298               return;
13299             }
13300
13301           i = 0;
13302           tmp[29] = 0;
13303           while (v)
13304             {
13305               tmp[28 - i] = (v % 10) + '0';
13306               v /= 10;
13307               i++;
13308             }
13309           strcpy (buf, tmp + 29 - i);
13310         }
13311     }
13312   else
13313     {
13314       if (hex)
13315         sprintf (buf, "0x%x", (unsigned int) disp);
13316       else
13317         sprintf (buf, "%d", (int) disp);
13318     }
13319 }
13320
13321 /* Put DISP in BUF as signed hex number.  */
13322
13323 static void
13324 print_displacement (char *buf, bfd_vma disp)
13325 {
13326   bfd_signed_vma val = disp;
13327   char tmp[30];
13328   int i, j = 0;
13329
13330   if (val < 0)
13331     {
13332       buf[j++] = '-';
13333       val = -disp;
13334
13335       /* Check for possible overflow.  */
13336       if (val < 0)
13337         {
13338           switch (address_mode)
13339             {
13340             case mode_64bit:
13341               strcpy (buf + j, "0x8000000000000000");
13342               break;
13343             case mode_32bit:
13344               strcpy (buf + j, "0x80000000");
13345               break;
13346             case mode_16bit:
13347               strcpy (buf + j, "0x8000");
13348               break;
13349             }
13350           return;
13351         }
13352     }
13353
13354   buf[j++] = '0';
13355   buf[j++] = 'x';
13356
13357   sprintf_vma (tmp, (bfd_vma) val);
13358   for (i = 0; tmp[i] == '0'; i++)
13359     continue;
13360   if (tmp[i] == '\0')
13361     i--;
13362   strcpy (buf + j, tmp + i);
13363 }
13364
13365 static void
13366 intel_operand_size (int bytemode, int sizeflag)
13367 {
13368   if (vex.evex
13369       && vex.b
13370       && (bytemode == x_mode
13371           || bytemode == evex_half_bcst_xmmq_mode))
13372     {
13373       if (vex.w)
13374         oappend ("QWORD PTR ");
13375       else
13376         oappend ("DWORD PTR ");
13377       return;
13378     }
13379   switch (bytemode)
13380     {
13381     case b_mode:
13382     case b_swap_mode:
13383     case dqb_mode:
13384     case db_mode:
13385       oappend ("BYTE PTR ");
13386       break;
13387     case w_mode:
13388     case dw_mode:
13389     case dqw_mode:
13390       oappend ("WORD PTR ");
13391       break;
13392     case indir_v_mode:
13393       if (address_mode == mode_64bit && isa64 == intel64)
13394         {
13395           oappend ("QWORD PTR ");
13396           break;
13397         }
13398       /* Fall through.  */
13399     case stack_v_mode:
13400       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13401         {
13402           oappend ("QWORD PTR ");
13403           break;
13404         }
13405       /* Fall through.  */
13406     case v_mode:
13407     case v_swap_mode:
13408     case dq_mode:
13409       USED_REX (REX_W);
13410       if (rex & REX_W)
13411         oappend ("QWORD PTR ");
13412       else
13413         {
13414           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13415             oappend ("DWORD PTR ");
13416           else
13417             oappend ("WORD PTR ");
13418           used_prefixes |= (prefixes & PREFIX_DATA);
13419         }
13420       break;
13421     case z_mode:
13422       if ((rex & REX_W) || (sizeflag & DFLAG))
13423         *obufp++ = 'D';
13424       oappend ("WORD PTR ");
13425       if (!(rex & REX_W))
13426         used_prefixes |= (prefixes & PREFIX_DATA);
13427       break;
13428     case a_mode:
13429       if (sizeflag & DFLAG)
13430         oappend ("QWORD PTR ");
13431       else
13432         oappend ("DWORD PTR ");
13433       used_prefixes |= (prefixes & PREFIX_DATA);
13434       break;
13435     case movsxd_mode:
13436       if (!(sizeflag & DFLAG) && isa64 == intel64)
13437         oappend ("WORD PTR ");
13438       else
13439         oappend ("DWORD PTR ");
13440       used_prefixes |= (prefixes & PREFIX_DATA);
13441       break;
13442     case d_mode:
13443     case d_scalar_swap_mode:
13444     case d_swap_mode:
13445     case dqd_mode:
13446       oappend ("DWORD PTR ");
13447       break;
13448     case q_mode:
13449     case q_scalar_swap_mode:
13450     case q_swap_mode:
13451       oappend ("QWORD PTR ");
13452       break;
13453     case m_mode:
13454       if (address_mode == mode_64bit)
13455         oappend ("QWORD PTR ");
13456       else
13457         oappend ("DWORD PTR ");
13458       break;
13459     case f_mode:
13460       if (sizeflag & DFLAG)
13461         oappend ("FWORD PTR ");
13462       else
13463         oappend ("DWORD PTR ");
13464       used_prefixes |= (prefixes & PREFIX_DATA);
13465       break;
13466     case t_mode:
13467       oappend ("TBYTE PTR ");
13468       break;
13469     case x_mode:
13470     case x_swap_mode:
13471     case evex_x_gscat_mode:
13472     case evex_x_nobcst_mode:
13473     case b_scalar_mode:
13474     case w_scalar_mode:
13475       if (need_vex)
13476         {
13477           switch (vex.length)
13478             {
13479             case 128:
13480               oappend ("XMMWORD PTR ");
13481               break;
13482             case 256:
13483               oappend ("YMMWORD PTR ");
13484               break;
13485             case 512:
13486               oappend ("ZMMWORD PTR ");
13487               break;
13488             default:
13489               abort ();
13490             }
13491         }
13492       else
13493         oappend ("XMMWORD PTR ");
13494       break;
13495     case xmm_mode:
13496       oappend ("XMMWORD PTR ");
13497       break;
13498     case ymm_mode:
13499       oappend ("YMMWORD PTR ");
13500       break;
13501     case xmmq_mode:
13502     case evex_half_bcst_xmmq_mode:
13503       if (!need_vex)
13504         abort ();
13505
13506       switch (vex.length)
13507         {
13508         case 128:
13509           oappend ("QWORD PTR ");
13510           break;
13511         case 256:
13512           oappend ("XMMWORD PTR ");
13513           break;
13514         case 512:
13515           oappend ("YMMWORD PTR ");
13516           break;
13517         default:
13518           abort ();
13519         }
13520       break;
13521     case xmm_mb_mode:
13522       if (!need_vex)
13523         abort ();
13524
13525       switch (vex.length)
13526         {
13527         case 128:
13528         case 256:
13529         case 512:
13530           oappend ("BYTE PTR ");
13531           break;
13532         default:
13533           abort ();
13534         }
13535       break;
13536     case xmm_mw_mode:
13537       if (!need_vex)
13538         abort ();
13539
13540       switch (vex.length)
13541         {
13542         case 128:
13543         case 256:
13544         case 512:
13545           oappend ("WORD PTR ");
13546           break;
13547         default:
13548           abort ();
13549         }
13550       break;
13551     case xmm_md_mode:
13552       if (!need_vex)
13553         abort ();
13554
13555       switch (vex.length)
13556         {
13557         case 128:
13558         case 256:
13559         case 512:
13560           oappend ("DWORD PTR ");
13561           break;
13562         default:
13563           abort ();
13564         }
13565       break;
13566     case xmm_mq_mode:
13567       if (!need_vex)
13568         abort ();
13569
13570       switch (vex.length)
13571         {
13572         case 128:
13573         case 256:
13574         case 512:
13575           oappend ("QWORD PTR ");
13576           break;
13577         default:
13578           abort ();
13579         }
13580       break;
13581     case xmmdw_mode:
13582       if (!need_vex)
13583         abort ();
13584
13585       switch (vex.length)
13586         {
13587         case 128:
13588           oappend ("WORD PTR ");
13589           break;
13590         case 256:
13591           oappend ("DWORD PTR ");
13592           break;
13593         case 512:
13594           oappend ("QWORD PTR ");
13595           break;
13596         default:
13597           abort ();
13598         }
13599       break;
13600     case xmmqd_mode:
13601       if (!need_vex)
13602         abort ();
13603
13604       switch (vex.length)
13605         {
13606         case 128:
13607           oappend ("DWORD PTR ");
13608           break;
13609         case 256:
13610           oappend ("QWORD PTR ");
13611           break;
13612         case 512:
13613           oappend ("XMMWORD PTR ");
13614           break;
13615         default:
13616           abort ();
13617         }
13618       break;
13619     case ymmq_mode:
13620       if (!need_vex)
13621         abort ();
13622
13623       switch (vex.length)
13624         {
13625         case 128:
13626           oappend ("QWORD PTR ");
13627           break;
13628         case 256:
13629           oappend ("YMMWORD PTR ");
13630           break;
13631         case 512:
13632           oappend ("ZMMWORD PTR ");
13633           break;
13634         default:
13635           abort ();
13636         }
13637       break;
13638     case ymmxmm_mode:
13639       if (!need_vex)
13640         abort ();
13641
13642       switch (vex.length)
13643         {
13644         case 128:
13645         case 256:
13646           oappend ("XMMWORD PTR ");
13647           break;
13648         default:
13649           abort ();
13650         }
13651       break;
13652     case o_mode:
13653       oappend ("OWORD PTR ");
13654       break;
13655     case vex_scalar_w_dq_mode:
13656       if (!need_vex)
13657         abort ();
13658
13659       if (vex.w)
13660         oappend ("QWORD PTR ");
13661       else
13662         oappend ("DWORD PTR ");
13663       break;
13664     case vex_vsib_d_w_dq_mode:
13665     case vex_vsib_q_w_dq_mode:
13666       if (!need_vex)
13667         abort ();
13668
13669       if (!vex.evex)
13670         {
13671           if (vex.w)
13672             oappend ("QWORD PTR ");
13673           else
13674             oappend ("DWORD PTR ");
13675         }
13676       else
13677         {
13678           switch (vex.length)
13679             {
13680             case 128:
13681               oappend ("XMMWORD PTR ");
13682               break;
13683             case 256:
13684               oappend ("YMMWORD PTR ");
13685               break;
13686             case 512:
13687               oappend ("ZMMWORD PTR ");
13688               break;
13689             default:
13690               abort ();
13691             }
13692         }
13693       break;
13694     case vex_vsib_q_w_d_mode:
13695     case vex_vsib_d_w_d_mode:
13696       if (!need_vex || !vex.evex)
13697         abort ();
13698
13699       switch (vex.length)
13700         {
13701         case 128:
13702           oappend ("QWORD PTR ");
13703           break;
13704         case 256:
13705           oappend ("XMMWORD PTR ");
13706           break;
13707         case 512:
13708           oappend ("YMMWORD PTR ");
13709           break;
13710         default:
13711           abort ();
13712         }
13713
13714       break;
13715     case mask_bd_mode:
13716       if (!need_vex || vex.length != 128)
13717         abort ();
13718       if (vex.w)
13719         oappend ("DWORD PTR ");
13720       else
13721         oappend ("BYTE PTR ");
13722       break;
13723     case mask_mode:
13724       if (!need_vex)
13725         abort ();
13726       if (vex.w)
13727         oappend ("QWORD PTR ");
13728       else
13729         oappend ("WORD PTR ");
13730       break;
13731     case v_bnd_mode:
13732     case v_bndmk_mode:
13733     default:
13734       break;
13735     }
13736 }
13737
13738 static void
13739 OP_E_register (int bytemode, int sizeflag)
13740 {
13741   int reg = modrm.rm;
13742   const char **names;
13743
13744   USED_REX (REX_B);
13745   if ((rex & REX_B))
13746     reg += 8;
13747
13748   if ((sizeflag & SUFFIX_ALWAYS)
13749       && (bytemode == b_swap_mode
13750           || bytemode == bnd_swap_mode
13751           || bytemode == v_swap_mode))
13752     swap_operand ();
13753
13754   switch (bytemode)
13755     {
13756     case b_mode:
13757     case b_swap_mode:
13758       USED_REX (0);
13759       if (rex)
13760         names = names8rex;
13761       else
13762         names = names8;
13763       break;
13764     case w_mode:
13765       names = names16;
13766       break;
13767     case d_mode:
13768     case dw_mode:
13769     case db_mode:
13770       names = names32;
13771       break;
13772     case q_mode:
13773       names = names64;
13774       break;
13775     case m_mode:
13776     case v_bnd_mode:
13777       names = address_mode == mode_64bit ? names64 : names32;
13778       break;
13779     case bnd_mode:
13780     case bnd_swap_mode:
13781       if (reg > 0x3)
13782         {
13783           oappend ("(bad)");
13784           return;
13785         }
13786       names = names_bnd;
13787       break;
13788     case indir_v_mode:
13789       if (address_mode == mode_64bit && isa64 == intel64)
13790         {
13791           names = names64;
13792           break;
13793         }
13794       /* Fall through.  */
13795     case stack_v_mode:
13796       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13797         {
13798           names = names64;
13799           break;
13800         }
13801       bytemode = v_mode;
13802       /* Fall through.  */
13803     case v_mode:
13804     case v_swap_mode:
13805     case dq_mode:
13806     case dqb_mode:
13807     case dqd_mode:
13808     case dqw_mode:
13809       USED_REX (REX_W);
13810       if (rex & REX_W)
13811         names = names64;
13812       else
13813         {
13814           if ((sizeflag & DFLAG)
13815               || (bytemode != v_mode
13816                   && bytemode != v_swap_mode))
13817             names = names32;
13818           else
13819             names = names16;
13820           used_prefixes |= (prefixes & PREFIX_DATA);
13821         }
13822       break;
13823     case movsxd_mode:
13824       if (!(sizeflag & DFLAG) && isa64 == intel64)
13825         names = names16;
13826       else
13827         names = names32;
13828       used_prefixes |= (prefixes & PREFIX_DATA);
13829       break;
13830     case va_mode:
13831       names = (address_mode == mode_64bit
13832                ? names64 : names32);
13833       if (!(prefixes & PREFIX_ADDR))
13834         names = (address_mode == mode_16bit
13835                      ? names16 : names);
13836       else
13837         {
13838           /* Remove "addr16/addr32".  */
13839           all_prefixes[last_addr_prefix] = 0;
13840           names = (address_mode != mode_32bit
13841                        ? names32 : names16);
13842           used_prefixes |= PREFIX_ADDR;
13843         }
13844       break;
13845     case mask_bd_mode:
13846     case mask_mode:
13847       if (reg > 0x7)
13848         {
13849           oappend ("(bad)");
13850           return;
13851         }
13852       names = names_mask;
13853       break;
13854     case 0:
13855       return;
13856     default:
13857       oappend (INTERNAL_DISASSEMBLER_ERROR);
13858       return;
13859     }
13860   oappend (names[reg]);
13861 }
13862
13863 static void
13864 OP_E_memory (int bytemode, int sizeflag)
13865 {
13866   bfd_vma disp = 0;
13867   int add = (rex & REX_B) ? 8 : 0;
13868   int riprel = 0;
13869   int shift;
13870
13871   if (vex.evex)
13872     {
13873       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13874       if (vex.b
13875           && bytemode != x_mode
13876           && bytemode != xmmq_mode
13877           && bytemode != evex_half_bcst_xmmq_mode)
13878         {
13879           BadOp ();
13880           return;
13881         }
13882       switch (bytemode)
13883         {
13884         case dqw_mode:
13885         case dw_mode:
13886           shift = 1;
13887           break;
13888         case dqb_mode:
13889         case db_mode:
13890           shift = 0;
13891           break;
13892         case dq_mode:
13893           if (address_mode != mode_64bit)
13894             {
13895               shift = 2;
13896               break;
13897             }
13898             /* fall through */
13899         case vex_scalar_w_dq_mode:
13900         case vex_vsib_d_w_dq_mode:
13901         case vex_vsib_d_w_d_mode:
13902         case vex_vsib_q_w_dq_mode:
13903         case vex_vsib_q_w_d_mode:
13904         case evex_x_gscat_mode:
13905           shift = vex.w ? 3 : 2;
13906           break;
13907         case x_mode:
13908         case evex_half_bcst_xmmq_mode:
13909         case xmmq_mode:
13910           if (vex.b)
13911             {
13912               shift = vex.w ? 3 : 2;
13913               break;
13914             }
13915           /* Fall through.  */
13916         case xmmqd_mode:
13917         case xmmdw_mode:
13918         case ymmq_mode:
13919         case evex_x_nobcst_mode:
13920         case x_swap_mode:
13921           switch (vex.length)
13922             {
13923             case 128:
13924               shift = 4;
13925               break;
13926             case 256:
13927               shift = 5;
13928               break;
13929             case 512:
13930               shift = 6;
13931               break;
13932             default:
13933               abort ();
13934             }
13935           break;
13936         case ymm_mode:
13937           shift = 5;
13938           break;
13939         case xmm_mode:
13940           shift = 4;
13941           break;
13942         case xmm_mq_mode:
13943         case q_mode:
13944         case q_swap_mode:
13945         case q_scalar_swap_mode:
13946           shift = 3;
13947           break;
13948         case dqd_mode:
13949         case xmm_md_mode:
13950         case d_mode:
13951         case d_swap_mode:
13952         case d_scalar_swap_mode:
13953           shift = 2;
13954           break;
13955         case w_scalar_mode:
13956         case xmm_mw_mode:
13957           shift = 1;
13958           break;
13959         case b_scalar_mode:
13960         case xmm_mb_mode:
13961           shift = 0;
13962           break;
13963         default:
13964           abort ();
13965         }
13966       /* Make necessary corrections to shift for modes that need it.
13967          For these modes we currently have shift 4, 5 or 6 depending on
13968          vex.length (it corresponds to xmmword, ymmword or zmmword
13969          operand).  We might want to make it 3, 4 or 5 (e.g. for
13970          xmmq_mode).  In case of broadcast enabled the corrections
13971          aren't needed, as element size is always 32 or 64 bits.  */
13972       if (!vex.b
13973           && (bytemode == xmmq_mode
13974               || bytemode == evex_half_bcst_xmmq_mode))
13975         shift -= 1;
13976       else if (bytemode == xmmqd_mode)
13977         shift -= 2;
13978       else if (bytemode == xmmdw_mode)
13979         shift -= 3;
13980       else if (bytemode == ymmq_mode && vex.length == 128)
13981         shift -= 1;
13982     }
13983   else
13984     shift = 0;
13985
13986   USED_REX (REX_B);
13987   if (intel_syntax)
13988     intel_operand_size (bytemode, sizeflag);
13989   append_seg ();
13990
13991   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13992     {
13993       /* 32/64 bit address mode */
13994       int havedisp;
13995       int havesib;
13996       int havebase;
13997       int haveindex;
13998       int needindex;
13999       int needaddr32;
14000       int base, rbase;
14001       int vindex = 0;
14002       int scale = 0;
14003       int addr32flag = !((sizeflag & AFLAG)
14004                          || bytemode == v_bnd_mode
14005                          || bytemode == v_bndmk_mode
14006                          || bytemode == bnd_mode
14007                          || bytemode == bnd_swap_mode);
14008       const char **indexes64 = names64;
14009       const char **indexes32 = names32;
14010
14011       havesib = 0;
14012       havebase = 1;
14013       haveindex = 0;
14014       base = modrm.rm;
14015
14016       if (base == 4)
14017         {
14018           havesib = 1;
14019           vindex = sib.index;
14020           USED_REX (REX_X);
14021           if (rex & REX_X)
14022             vindex += 8;
14023           switch (bytemode)
14024             {
14025             case vex_vsib_d_w_dq_mode:
14026             case vex_vsib_d_w_d_mode:
14027             case vex_vsib_q_w_dq_mode:
14028             case vex_vsib_q_w_d_mode:
14029               if (!need_vex)
14030                 abort ();
14031               if (vex.evex)
14032                 {
14033                   if (!vex.v)
14034                     vindex += 16;
14035                 }
14036
14037               haveindex = 1;
14038               switch (vex.length)
14039                 {
14040                 case 128:
14041                   indexes64 = indexes32 = names_xmm;
14042                   break;
14043                 case 256:
14044                   if (!vex.w
14045                       || bytemode == vex_vsib_q_w_dq_mode
14046                       || bytemode == vex_vsib_q_w_d_mode)
14047                     indexes64 = indexes32 = names_ymm;
14048                   else
14049                     indexes64 = indexes32 = names_xmm;
14050                   break;
14051                 case 512:
14052                   if (!vex.w
14053                       || bytemode == vex_vsib_q_w_dq_mode
14054                       || bytemode == vex_vsib_q_w_d_mode)
14055                     indexes64 = indexes32 = names_zmm;
14056                   else
14057                     indexes64 = indexes32 = names_ymm;
14058                   break;
14059                 default:
14060                   abort ();
14061                 }
14062               break;
14063             default:
14064               haveindex = vindex != 4;
14065               break;
14066             }
14067           scale = sib.scale;
14068           base = sib.base;
14069           codep++;
14070         }
14071       rbase = base + add;
14072
14073       switch (modrm.mod)
14074         {
14075         case 0:
14076           if (base == 5)
14077             {
14078               havebase = 0;
14079               if (address_mode == mode_64bit && !havesib)
14080                 riprel = 1;
14081               disp = get32s ();
14082               if (riprel && bytemode == v_bndmk_mode)
14083                 {
14084                   oappend ("(bad)");
14085                   return;
14086                 }
14087             }
14088           break;
14089         case 1:
14090           FETCH_DATA (the_info, codep + 1);
14091           disp = *codep++;
14092           if ((disp & 0x80) != 0)
14093             disp -= 0x100;
14094           if (vex.evex && shift > 0)
14095             disp <<= shift;
14096           break;
14097         case 2:
14098           disp = get32s ();
14099           break;
14100         }
14101
14102       needindex = 0;
14103       needaddr32 = 0;
14104       if (havesib
14105           && !havebase
14106           && !haveindex
14107           && address_mode != mode_16bit)
14108         {
14109           if (address_mode == mode_64bit)
14110             {
14111               /* Display eiz instead of addr32.  */
14112               needindex = addr32flag;
14113               needaddr32 = 1;
14114             }
14115           else
14116             {
14117               /* In 32-bit mode, we need index register to tell [offset]
14118                  from [eiz*1 + offset].  */
14119               needindex = 1;
14120             }
14121         }
14122
14123       havedisp = (havebase
14124                   || needindex
14125                   || (havesib && (haveindex || scale != 0)));
14126
14127       if (!intel_syntax)
14128         if (modrm.mod != 0 || base == 5)
14129           {
14130             if (havedisp || riprel)
14131               print_displacement (scratchbuf, disp);
14132             else
14133               print_operand_value (scratchbuf, 1, disp);
14134             oappend (scratchbuf);
14135             if (riprel)
14136               {
14137                 set_op (disp, 1);
14138                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14139               }
14140           }
14141
14142       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14143           && (address_mode != mode_64bit
14144               || ((bytemode != v_bnd_mode)
14145                   && (bytemode != v_bndmk_mode)
14146                   && (bytemode != bnd_mode)
14147                   && (bytemode != bnd_swap_mode))))
14148         used_prefixes |= PREFIX_ADDR;
14149
14150       if (havedisp || (intel_syntax && riprel))
14151         {
14152           *obufp++ = open_char;
14153           if (intel_syntax && riprel)
14154             {
14155               set_op (disp, 1);
14156               oappend (!addr32flag ? "rip" : "eip");
14157             }
14158           *obufp = '\0';
14159           if (havebase)
14160             oappend (address_mode == mode_64bit && !addr32flag
14161                      ? names64[rbase] : names32[rbase]);
14162           if (havesib)
14163             {
14164               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14165                  print index to tell base + index from base.  */
14166               if (scale != 0
14167                   || needindex
14168                   || haveindex
14169                   || (havebase && base != ESP_REG_NUM))
14170                 {
14171                   if (!intel_syntax || havebase)
14172                     {
14173                       *obufp++ = separator_char;
14174                       *obufp = '\0';
14175                     }
14176                   if (haveindex)
14177                     oappend (address_mode == mode_64bit && !addr32flag
14178                              ? indexes64[vindex] : indexes32[vindex]);
14179                   else
14180                     oappend (address_mode == mode_64bit && !addr32flag
14181                              ? index64 : index32);
14182
14183                   *obufp++ = scale_char;
14184                   *obufp = '\0';
14185                   sprintf (scratchbuf, "%d", 1 << scale);
14186                   oappend (scratchbuf);
14187                 }
14188             }
14189           if (intel_syntax
14190               && (disp || modrm.mod != 0 || base == 5))
14191             {
14192               if (!havedisp || (bfd_signed_vma) disp >= 0)
14193                 {
14194                   *obufp++ = '+';
14195                   *obufp = '\0';
14196                 }
14197               else if (modrm.mod != 1 && disp != -disp)
14198                 {
14199                   *obufp++ = '-';
14200                   *obufp = '\0';
14201                   disp = - (bfd_signed_vma) disp;
14202                 }
14203
14204               if (havedisp)
14205                 print_displacement (scratchbuf, disp);
14206               else
14207                 print_operand_value (scratchbuf, 1, disp);
14208               oappend (scratchbuf);
14209             }
14210
14211           *obufp++ = close_char;
14212           *obufp = '\0';
14213         }
14214       else if (intel_syntax)
14215         {
14216           if (modrm.mod != 0 || base == 5)
14217             {
14218               if (!active_seg_prefix)
14219                 {
14220                   oappend (names_seg[ds_reg - es_reg]);
14221                   oappend (":");
14222                 }
14223               print_operand_value (scratchbuf, 1, disp);
14224               oappend (scratchbuf);
14225             }
14226         }
14227     }
14228   else if (bytemode == v_bnd_mode
14229            || bytemode == v_bndmk_mode
14230            || bytemode == bnd_mode
14231            || bytemode == bnd_swap_mode)
14232     {
14233       oappend ("(bad)");
14234       return;
14235     }
14236   else
14237     {
14238       /* 16 bit address mode */
14239       used_prefixes |= prefixes & PREFIX_ADDR;
14240       switch (modrm.mod)
14241         {
14242         case 0:
14243           if (modrm.rm == 6)
14244             {
14245               disp = get16 ();
14246               if ((disp & 0x8000) != 0)
14247                 disp -= 0x10000;
14248             }
14249           break;
14250         case 1:
14251           FETCH_DATA (the_info, codep + 1);
14252           disp = *codep++;
14253           if ((disp & 0x80) != 0)
14254             disp -= 0x100;
14255           if (vex.evex && shift > 0)
14256             disp <<= shift;
14257           break;
14258         case 2:
14259           disp = get16 ();
14260           if ((disp & 0x8000) != 0)
14261             disp -= 0x10000;
14262           break;
14263         }
14264
14265       if (!intel_syntax)
14266         if (modrm.mod != 0 || modrm.rm == 6)
14267           {
14268             print_displacement (scratchbuf, disp);
14269             oappend (scratchbuf);
14270           }
14271
14272       if (modrm.mod != 0 || modrm.rm != 6)
14273         {
14274           *obufp++ = open_char;
14275           *obufp = '\0';
14276           oappend (index16[modrm.rm]);
14277           if (intel_syntax
14278               && (disp || modrm.mod != 0 || modrm.rm == 6))
14279             {
14280               if ((bfd_signed_vma) disp >= 0)
14281                 {
14282                   *obufp++ = '+';
14283                   *obufp = '\0';
14284                 }
14285               else if (modrm.mod != 1)
14286                 {
14287                   *obufp++ = '-';
14288                   *obufp = '\0';
14289                   disp = - (bfd_signed_vma) disp;
14290                 }
14291
14292               print_displacement (scratchbuf, disp);
14293               oappend (scratchbuf);
14294             }
14295
14296           *obufp++ = close_char;
14297           *obufp = '\0';
14298         }
14299       else if (intel_syntax)
14300         {
14301           if (!active_seg_prefix)
14302             {
14303               oappend (names_seg[ds_reg - es_reg]);
14304               oappend (":");
14305             }
14306           print_operand_value (scratchbuf, 1, disp & 0xffff);
14307           oappend (scratchbuf);
14308         }
14309     }
14310   if (vex.evex && vex.b
14311       && (bytemode == x_mode
14312           || bytemode == xmmq_mode
14313           || bytemode == evex_half_bcst_xmmq_mode))
14314     {
14315       if (vex.w
14316           || bytemode == xmmq_mode
14317           || bytemode == evex_half_bcst_xmmq_mode)
14318         {
14319           switch (vex.length)
14320             {
14321             case 128:
14322               oappend ("{1to2}");
14323               break;
14324             case 256:
14325               oappend ("{1to4}");
14326               break;
14327             case 512:
14328               oappend ("{1to8}");
14329               break;
14330             default:
14331               abort ();
14332             }
14333         }
14334       else
14335         {
14336           switch (vex.length)
14337             {
14338             case 128:
14339               oappend ("{1to4}");
14340               break;
14341             case 256:
14342               oappend ("{1to8}");
14343               break;
14344             case 512:
14345               oappend ("{1to16}");
14346               break;
14347             default:
14348               abort ();
14349             }
14350         }
14351     }
14352 }
14353
14354 static void
14355 OP_E (int bytemode, int sizeflag)
14356 {
14357   /* Skip mod/rm byte.  */
14358   MODRM_CHECK;
14359   codep++;
14360
14361   if (modrm.mod == 3)
14362     OP_E_register (bytemode, sizeflag);
14363   else
14364     OP_E_memory (bytemode, sizeflag);
14365 }
14366
14367 static void
14368 OP_G (int bytemode, int sizeflag)
14369 {
14370   int add = 0;
14371   const char **names;
14372   USED_REX (REX_R);
14373   if (rex & REX_R)
14374     add += 8;
14375   switch (bytemode)
14376     {
14377     case b_mode:
14378       USED_REX (0);
14379       if (rex)
14380         oappend (names8rex[modrm.reg + add]);
14381       else
14382         oappend (names8[modrm.reg + add]);
14383       break;
14384     case w_mode:
14385       oappend (names16[modrm.reg + add]);
14386       break;
14387     case d_mode:
14388     case db_mode:
14389     case dw_mode:
14390       oappend (names32[modrm.reg + add]);
14391       break;
14392     case q_mode:
14393       oappend (names64[modrm.reg + add]);
14394       break;
14395     case bnd_mode:
14396       if (modrm.reg > 0x3)
14397         {
14398           oappend ("(bad)");
14399           return;
14400         }
14401       oappend (names_bnd[modrm.reg]);
14402       break;
14403     case v_mode:
14404     case dq_mode:
14405     case dqb_mode:
14406     case dqd_mode:
14407     case dqw_mode:
14408     case movsxd_mode:
14409       USED_REX (REX_W);
14410       if (rex & REX_W)
14411         oappend (names64[modrm.reg + add]);
14412       else
14413         {
14414           if ((sizeflag & DFLAG)
14415               || (bytemode != v_mode && bytemode != movsxd_mode))
14416             oappend (names32[modrm.reg + add]);
14417           else
14418             oappend (names16[modrm.reg + add]);
14419           used_prefixes |= (prefixes & PREFIX_DATA);
14420         }
14421       break;
14422     case va_mode:
14423       names = (address_mode == mode_64bit
14424                ? names64 : names32);
14425       if (!(prefixes & PREFIX_ADDR))
14426         {
14427           if (address_mode == mode_16bit)
14428             names = names16;
14429         }
14430       else
14431         {
14432           /* Remove "addr16/addr32".  */
14433           all_prefixes[last_addr_prefix] = 0;
14434           names = (address_mode != mode_32bit
14435                        ? names32 : names16);
14436           used_prefixes |= PREFIX_ADDR;
14437         }
14438       oappend (names[modrm.reg + add]);
14439       break;
14440     case m_mode:
14441       if (address_mode == mode_64bit)
14442         oappend (names64[modrm.reg + add]);
14443       else
14444         oappend (names32[modrm.reg + add]);
14445       break;
14446     case mask_bd_mode:
14447     case mask_mode:
14448       if ((modrm.reg + add) > 0x7)
14449         {
14450           oappend ("(bad)");
14451           return;
14452         }
14453       oappend (names_mask[modrm.reg + add]);
14454       break;
14455     default:
14456       oappend (INTERNAL_DISASSEMBLER_ERROR);
14457       break;
14458     }
14459 }
14460
14461 static bfd_vma
14462 get64 (void)
14463 {
14464   bfd_vma x;
14465 #ifdef BFD64
14466   unsigned int a;
14467   unsigned int b;
14468
14469   FETCH_DATA (the_info, codep + 8);
14470   a = *codep++ & 0xff;
14471   a |= (*codep++ & 0xff) << 8;
14472   a |= (*codep++ & 0xff) << 16;
14473   a |= (*codep++ & 0xffu) << 24;
14474   b = *codep++ & 0xff;
14475   b |= (*codep++ & 0xff) << 8;
14476   b |= (*codep++ & 0xff) << 16;
14477   b |= (*codep++ & 0xffu) << 24;
14478   x = a + ((bfd_vma) b << 32);
14479 #else
14480   abort ();
14481   x = 0;
14482 #endif
14483   return x;
14484 }
14485
14486 static bfd_signed_vma
14487 get32 (void)
14488 {
14489   bfd_signed_vma x = 0;
14490
14491   FETCH_DATA (the_info, codep + 4);
14492   x = *codep++ & (bfd_signed_vma) 0xff;
14493   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14494   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14495   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14496   return x;
14497 }
14498
14499 static bfd_signed_vma
14500 get32s (void)
14501 {
14502   bfd_signed_vma x = 0;
14503
14504   FETCH_DATA (the_info, codep + 4);
14505   x = *codep++ & (bfd_signed_vma) 0xff;
14506   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14507   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14508   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14509
14510   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14511
14512   return x;
14513 }
14514
14515 static int
14516 get16 (void)
14517 {
14518   int x = 0;
14519
14520   FETCH_DATA (the_info, codep + 2);
14521   x = *codep++ & 0xff;
14522   x |= (*codep++ & 0xff) << 8;
14523   return x;
14524 }
14525
14526 static void
14527 set_op (bfd_vma op, int riprel)
14528 {
14529   op_index[op_ad] = op_ad;
14530   if (address_mode == mode_64bit)
14531     {
14532       op_address[op_ad] = op;
14533       op_riprel[op_ad] = riprel;
14534     }
14535   else
14536     {
14537       /* Mask to get a 32-bit address.  */
14538       op_address[op_ad] = op & 0xffffffff;
14539       op_riprel[op_ad] = riprel & 0xffffffff;
14540     }
14541 }
14542
14543 static void
14544 OP_REG (int code, int sizeflag)
14545 {
14546   const char *s;
14547   int add;
14548
14549   switch (code)
14550     {
14551     case es_reg: case ss_reg: case cs_reg:
14552     case ds_reg: case fs_reg: case gs_reg:
14553       oappend (names_seg[code - es_reg]);
14554       return;
14555     }
14556
14557   USED_REX (REX_B);
14558   if (rex & REX_B)
14559     add = 8;
14560   else
14561     add = 0;
14562
14563   switch (code)
14564     {
14565     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14566     case sp_reg: case bp_reg: case si_reg: case di_reg:
14567       s = names16[code - ax_reg + add];
14568       break;
14569     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14570     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14571       USED_REX (0);
14572       if (rex)
14573         s = names8rex[code - al_reg + add];
14574       else
14575         s = names8[code - al_reg];
14576       break;
14577     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14578     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14579       if (address_mode == mode_64bit
14580           && ((sizeflag & DFLAG) || (rex & REX_W)))
14581         {
14582           s = names64[code - rAX_reg + add];
14583           break;
14584         }
14585       code += eAX_reg - rAX_reg;
14586       /* Fall through.  */
14587     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14588     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14589       USED_REX (REX_W);
14590       if (rex & REX_W)
14591         s = names64[code - eAX_reg + add];
14592       else
14593         {
14594           if (sizeflag & DFLAG)
14595             s = names32[code - eAX_reg + add];
14596           else
14597             s = names16[code - eAX_reg + add];
14598           used_prefixes |= (prefixes & PREFIX_DATA);
14599         }
14600       break;
14601     default:
14602       s = INTERNAL_DISASSEMBLER_ERROR;
14603       break;
14604     }
14605   oappend (s);
14606 }
14607
14608 static void
14609 OP_IMREG (int code, int sizeflag)
14610 {
14611   const char *s;
14612
14613   switch (code)
14614     {
14615     case indir_dx_reg:
14616       if (intel_syntax)
14617         s = "dx";
14618       else
14619         s = "(%dx)";
14620       break;
14621     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14622     case sp_reg: case bp_reg: case si_reg: case di_reg:
14623       s = names16[code - ax_reg];
14624       break;
14625     case es_reg: case ss_reg: case cs_reg:
14626     case ds_reg: case fs_reg: case gs_reg:
14627       s = names_seg[code - es_reg];
14628       break;
14629     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14630     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14631       USED_REX (0);
14632       if (rex)
14633         s = names8rex[code - al_reg];
14634       else
14635         s = names8[code - al_reg];
14636       break;
14637     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14638     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14639       USED_REX (REX_W);
14640       if (rex & REX_W)
14641         s = names64[code - eAX_reg];
14642       else
14643         {
14644           if (sizeflag & DFLAG)
14645             s = names32[code - eAX_reg];
14646           else
14647             s = names16[code - eAX_reg];
14648           used_prefixes |= (prefixes & PREFIX_DATA);
14649         }
14650       break;
14651     case z_mode_ax_reg:
14652       if ((rex & REX_W) || (sizeflag & DFLAG))
14653         s = *names32;
14654       else
14655         s = *names16;
14656       if (!(rex & REX_W))
14657         used_prefixes |= (prefixes & PREFIX_DATA);
14658       break;
14659     default:
14660       s = INTERNAL_DISASSEMBLER_ERROR;
14661       break;
14662     }
14663   oappend (s);
14664 }
14665
14666 static void
14667 OP_I (int bytemode, int sizeflag)
14668 {
14669   bfd_signed_vma op;
14670   bfd_signed_vma mask = -1;
14671
14672   switch (bytemode)
14673     {
14674     case b_mode:
14675       FETCH_DATA (the_info, codep + 1);
14676       op = *codep++;
14677       mask = 0xff;
14678       break;
14679     case v_mode:
14680       USED_REX (REX_W);
14681       if (rex & REX_W)
14682         op = get32s ();
14683       else
14684         {
14685           if (sizeflag & DFLAG)
14686             {
14687               op = get32 ();
14688               mask = 0xffffffff;
14689             }
14690           else
14691             {
14692               op = get16 ();
14693               mask = 0xfffff;
14694             }
14695           used_prefixes |= (prefixes & PREFIX_DATA);
14696         }
14697       break;
14698     case d_mode:
14699       mask = 0xffffffff;
14700       op = get32 ();
14701       break;
14702     case w_mode:
14703       mask = 0xfffff;
14704       op = get16 ();
14705       break;
14706     case const_1_mode:
14707       if (intel_syntax)
14708         oappend ("1");
14709       return;
14710     default:
14711       oappend (INTERNAL_DISASSEMBLER_ERROR);
14712       return;
14713     }
14714
14715   op &= mask;
14716   scratchbuf[0] = '$';
14717   print_operand_value (scratchbuf + 1, 1, op);
14718   oappend_maybe_intel (scratchbuf);
14719   scratchbuf[0] = '\0';
14720 }
14721
14722 static void
14723 OP_I64 (int bytemode, int sizeflag)
14724 {
14725   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14726     {
14727       OP_I (bytemode, sizeflag);
14728       return;
14729     }
14730
14731   USED_REX (REX_W);
14732
14733   scratchbuf[0] = '$';
14734   print_operand_value (scratchbuf + 1, 1, get64 ());
14735   oappend_maybe_intel (scratchbuf);
14736   scratchbuf[0] = '\0';
14737 }
14738
14739 static void
14740 OP_sI (int bytemode, int sizeflag)
14741 {
14742   bfd_signed_vma op;
14743
14744   switch (bytemode)
14745     {
14746     case b_mode:
14747     case b_T_mode:
14748       FETCH_DATA (the_info, codep + 1);
14749       op = *codep++;
14750       if ((op & 0x80) != 0)
14751         op -= 0x100;
14752       if (bytemode == b_T_mode)
14753         {
14754           if (address_mode != mode_64bit
14755               || !((sizeflag & DFLAG) || (rex & REX_W)))
14756             {
14757               /* The operand-size prefix is overridden by a REX prefix.  */
14758               if ((sizeflag & DFLAG) || (rex & REX_W))
14759                 op &= 0xffffffff;
14760               else
14761                 op &= 0xffff;
14762           }
14763         }
14764       else
14765         {
14766           if (!(rex & REX_W))
14767             {
14768               if (sizeflag & DFLAG)
14769                 op &= 0xffffffff;
14770               else
14771                 op &= 0xffff;
14772             }
14773         }
14774       break;
14775     case v_mode:
14776       /* The operand-size prefix is overridden by a REX prefix.  */
14777       if ((sizeflag & DFLAG) || (rex & REX_W))
14778         op = get32s ();
14779       else
14780         op = get16 ();
14781       break;
14782     default:
14783       oappend (INTERNAL_DISASSEMBLER_ERROR);
14784       return;
14785     }
14786
14787   scratchbuf[0] = '$';
14788   print_operand_value (scratchbuf + 1, 1, op);
14789   oappend_maybe_intel (scratchbuf);
14790 }
14791
14792 static void
14793 OP_J (int bytemode, int sizeflag)
14794 {
14795   bfd_vma disp;
14796   bfd_vma mask = -1;
14797   bfd_vma segment = 0;
14798
14799   switch (bytemode)
14800     {
14801     case b_mode:
14802       FETCH_DATA (the_info, codep + 1);
14803       disp = *codep++;
14804       if ((disp & 0x80) != 0)
14805         disp -= 0x100;
14806       break;
14807     case v_mode:
14808       if (isa64 != intel64)
14809     case dqw_mode:
14810         USED_REX (REX_W);
14811       if ((sizeflag & DFLAG)
14812           || (address_mode == mode_64bit
14813               && ((isa64 == intel64 && bytemode != dqw_mode)
14814                   || (rex & REX_W))))
14815         disp = get32s ();
14816       else
14817         {
14818           disp = get16 ();
14819           if ((disp & 0x8000) != 0)
14820             disp -= 0x10000;
14821           /* In 16bit mode, address is wrapped around at 64k within
14822              the same segment.  Otherwise, a data16 prefix on a jump
14823              instruction means that the pc is masked to 16 bits after
14824              the displacement is added!  */
14825           mask = 0xffff;
14826           if ((prefixes & PREFIX_DATA) == 0)
14827             segment = ((start_pc + (codep - start_codep))
14828                        & ~((bfd_vma) 0xffff));
14829         }
14830       if (address_mode != mode_64bit
14831           || (isa64 != intel64 && !(rex & REX_W)))
14832         used_prefixes |= (prefixes & PREFIX_DATA);
14833       break;
14834     default:
14835       oappend (INTERNAL_DISASSEMBLER_ERROR);
14836       return;
14837     }
14838   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14839   set_op (disp, 0);
14840   print_operand_value (scratchbuf, 1, disp);
14841   oappend (scratchbuf);
14842 }
14843
14844 static void
14845 OP_SEG (int bytemode, int sizeflag)
14846 {
14847   if (bytemode == w_mode)
14848     oappend (names_seg[modrm.reg]);
14849   else
14850     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14851 }
14852
14853 static void
14854 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14855 {
14856   int seg, offset;
14857
14858   if (sizeflag & DFLAG)
14859     {
14860       offset = get32 ();
14861       seg = get16 ();
14862     }
14863   else
14864     {
14865       offset = get16 ();
14866       seg = get16 ();
14867     }
14868   used_prefixes |= (prefixes & PREFIX_DATA);
14869   if (intel_syntax)
14870     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14871   else
14872     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14873   oappend (scratchbuf);
14874 }
14875
14876 static void
14877 OP_OFF (int bytemode, int sizeflag)
14878 {
14879   bfd_vma off;
14880
14881   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14882     intel_operand_size (bytemode, sizeflag);
14883   append_seg ();
14884
14885   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14886     off = get32 ();
14887   else
14888     off = get16 ();
14889
14890   if (intel_syntax)
14891     {
14892       if (!active_seg_prefix)
14893         {
14894           oappend (names_seg[ds_reg - es_reg]);
14895           oappend (":");
14896         }
14897     }
14898   print_operand_value (scratchbuf, 1, off);
14899   oappend (scratchbuf);
14900 }
14901
14902 static void
14903 OP_OFF64 (int bytemode, int sizeflag)
14904 {
14905   bfd_vma off;
14906
14907   if (address_mode != mode_64bit
14908       || (prefixes & PREFIX_ADDR))
14909     {
14910       OP_OFF (bytemode, sizeflag);
14911       return;
14912     }
14913
14914   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14915     intel_operand_size (bytemode, sizeflag);
14916   append_seg ();
14917
14918   off = get64 ();
14919
14920   if (intel_syntax)
14921     {
14922       if (!active_seg_prefix)
14923         {
14924           oappend (names_seg[ds_reg - es_reg]);
14925           oappend (":");
14926         }
14927     }
14928   print_operand_value (scratchbuf, 1, off);
14929   oappend (scratchbuf);
14930 }
14931
14932 static void
14933 ptr_reg (int code, int sizeflag)
14934 {
14935   const char *s;
14936
14937   *obufp++ = open_char;
14938   used_prefixes |= (prefixes & PREFIX_ADDR);
14939   if (address_mode == mode_64bit)
14940     {
14941       if (!(sizeflag & AFLAG))
14942         s = names32[code - eAX_reg];
14943       else
14944         s = names64[code - eAX_reg];
14945     }
14946   else if (sizeflag & AFLAG)
14947     s = names32[code - eAX_reg];
14948   else
14949     s = names16[code - eAX_reg];
14950   oappend (s);
14951   *obufp++ = close_char;
14952   *obufp = 0;
14953 }
14954
14955 static void
14956 OP_ESreg (int code, int sizeflag)
14957 {
14958   if (intel_syntax)
14959     {
14960       switch (codep[-1])
14961         {
14962         case 0x6d:      /* insw/insl */
14963           intel_operand_size (z_mode, sizeflag);
14964           break;
14965         case 0xa5:      /* movsw/movsl/movsq */
14966         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14967         case 0xab:      /* stosw/stosl */
14968         case 0xaf:      /* scasw/scasl */
14969           intel_operand_size (v_mode, sizeflag);
14970           break;
14971         default:
14972           intel_operand_size (b_mode, sizeflag);
14973         }
14974     }
14975   oappend_maybe_intel ("%es:");
14976   ptr_reg (code, sizeflag);
14977 }
14978
14979 static void
14980 OP_DSreg (int code, int sizeflag)
14981 {
14982   if (intel_syntax)
14983     {
14984       switch (codep[-1])
14985         {
14986         case 0x6f:      /* outsw/outsl */
14987           intel_operand_size (z_mode, sizeflag);
14988           break;
14989         case 0xa5:      /* movsw/movsl/movsq */
14990         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14991         case 0xad:      /* lodsw/lodsl/lodsq */
14992           intel_operand_size (v_mode, sizeflag);
14993           break;
14994         default:
14995           intel_operand_size (b_mode, sizeflag);
14996         }
14997     }
14998   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14999      default segment register DS is printed.  */
15000   if (!active_seg_prefix)
15001     active_seg_prefix = PREFIX_DS;
15002   append_seg ();
15003   ptr_reg (code, sizeflag);
15004 }
15005
15006 static void
15007 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15008 {
15009   int add;
15010   if (rex & REX_R)
15011     {
15012       USED_REX (REX_R);
15013       add = 8;
15014     }
15015   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15016     {
15017       all_prefixes[last_lock_prefix] = 0;
15018       used_prefixes |= PREFIX_LOCK;
15019       add = 8;
15020     }
15021   else
15022     add = 0;
15023   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15024   oappend_maybe_intel (scratchbuf);
15025 }
15026
15027 static void
15028 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15029 {
15030   int add;
15031   USED_REX (REX_R);
15032   if (rex & REX_R)
15033     add = 8;
15034   else
15035     add = 0;
15036   if (intel_syntax)
15037     sprintf (scratchbuf, "db%d", modrm.reg + add);
15038   else
15039     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15040   oappend (scratchbuf);
15041 }
15042
15043 static void
15044 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15045 {
15046   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15047   oappend_maybe_intel (scratchbuf);
15048 }
15049
15050 static void
15051 OP_R (int bytemode, int sizeflag)
15052 {
15053   /* Skip mod/rm byte.  */
15054   MODRM_CHECK;
15055   codep++;
15056   OP_E_register (bytemode, sizeflag);
15057 }
15058
15059 static void
15060 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15061 {
15062   int reg = modrm.reg;
15063   const char **names;
15064
15065   used_prefixes |= (prefixes & PREFIX_DATA);
15066   if (prefixes & PREFIX_DATA)
15067     {
15068       names = names_xmm;
15069       USED_REX (REX_R);
15070       if (rex & REX_R)
15071         reg += 8;
15072     }
15073   else
15074     names = names_mm;
15075   oappend (names[reg]);
15076 }
15077
15078 static void
15079 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15080 {
15081   int reg = modrm.reg;
15082   const char **names;
15083
15084   USED_REX (REX_R);
15085   if (rex & REX_R)
15086     reg += 8;
15087   if (vex.evex)
15088     {
15089       if (!vex.r)
15090         reg += 16;
15091     }
15092
15093   if (need_vex
15094       && bytemode != xmm_mode
15095       && bytemode != xmmq_mode
15096       && bytemode != evex_half_bcst_xmmq_mode
15097       && bytemode != ymm_mode
15098       && bytemode != scalar_mode)
15099     {
15100       switch (vex.length)
15101         {
15102         case 128:
15103           names = names_xmm;
15104           break;
15105         case 256:
15106           if (vex.w
15107               || (bytemode != vex_vsib_q_w_dq_mode
15108                   && bytemode != vex_vsib_q_w_d_mode))
15109             names = names_ymm;
15110           else
15111             names = names_xmm;
15112           break;
15113         case 512:
15114           names = names_zmm;
15115           break;
15116         default:
15117           abort ();
15118         }
15119     }
15120   else if (bytemode == xmmq_mode
15121            || bytemode == evex_half_bcst_xmmq_mode)
15122     {
15123       switch (vex.length)
15124         {
15125         case 128:
15126         case 256:
15127           names = names_xmm;
15128           break;
15129         case 512:
15130           names = names_ymm;
15131           break;
15132         default:
15133           abort ();
15134         }
15135     }
15136   else if (bytemode == ymm_mode)
15137     names = names_ymm;
15138   else
15139     names = names_xmm;
15140   oappend (names[reg]);
15141 }
15142
15143 static void
15144 OP_EM (int bytemode, int sizeflag)
15145 {
15146   int reg;
15147   const char **names;
15148
15149   if (modrm.mod != 3)
15150     {
15151       if (intel_syntax
15152           && (bytemode == v_mode || bytemode == v_swap_mode))
15153         {
15154           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15155           used_prefixes |= (prefixes & PREFIX_DATA);
15156         }
15157       OP_E (bytemode, sizeflag);
15158       return;
15159     }
15160
15161   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15162     swap_operand ();
15163
15164   /* Skip mod/rm byte.  */
15165   MODRM_CHECK;
15166   codep++;
15167   used_prefixes |= (prefixes & PREFIX_DATA);
15168   reg = modrm.rm;
15169   if (prefixes & PREFIX_DATA)
15170     {
15171       names = names_xmm;
15172       USED_REX (REX_B);
15173       if (rex & REX_B)
15174         reg += 8;
15175     }
15176   else
15177     names = names_mm;
15178   oappend (names[reg]);
15179 }
15180
15181 /* cvt* are the only instructions in sse2 which have
15182    both SSE and MMX operands and also have 0x66 prefix
15183    in their opcode. 0x66 was originally used to differentiate
15184    between SSE and MMX instruction(operands). So we have to handle the
15185    cvt* separately using OP_EMC and OP_MXC */
15186 static void
15187 OP_EMC (int bytemode, int sizeflag)
15188 {
15189   if (modrm.mod != 3)
15190     {
15191       if (intel_syntax && bytemode == v_mode)
15192         {
15193           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15194           used_prefixes |= (prefixes & PREFIX_DATA);
15195         }
15196       OP_E (bytemode, sizeflag);
15197       return;
15198     }
15199
15200   /* Skip mod/rm byte.  */
15201   MODRM_CHECK;
15202   codep++;
15203   used_prefixes |= (prefixes & PREFIX_DATA);
15204   oappend (names_mm[modrm.rm]);
15205 }
15206
15207 static void
15208 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15209 {
15210   used_prefixes |= (prefixes & PREFIX_DATA);
15211   oappend (names_mm[modrm.reg]);
15212 }
15213
15214 static void
15215 OP_EX (int bytemode, int sizeflag)
15216 {
15217   int reg;
15218   const char **names;
15219
15220   /* Skip mod/rm byte.  */
15221   MODRM_CHECK;
15222   codep++;
15223
15224   if (modrm.mod != 3)
15225     {
15226       OP_E_memory (bytemode, sizeflag);
15227       return;
15228     }
15229
15230   reg = modrm.rm;
15231   USED_REX (REX_B);
15232   if (rex & REX_B)
15233     reg += 8;
15234   if (vex.evex)
15235     {
15236       USED_REX (REX_X);
15237       if ((rex & REX_X))
15238         reg += 16;
15239     }
15240
15241   if ((sizeflag & SUFFIX_ALWAYS)
15242       && (bytemode == x_swap_mode
15243           || bytemode == d_swap_mode
15244           || bytemode == d_scalar_swap_mode
15245           || bytemode == q_swap_mode
15246           || bytemode == q_scalar_swap_mode))
15247     swap_operand ();
15248
15249   if (need_vex
15250       && bytemode != xmm_mode
15251       && bytemode != xmmdw_mode
15252       && bytemode != xmmqd_mode
15253       && bytemode != xmm_mb_mode
15254       && bytemode != xmm_mw_mode
15255       && bytemode != xmm_md_mode
15256       && bytemode != xmm_mq_mode
15257       && bytemode != xmmq_mode
15258       && bytemode != evex_half_bcst_xmmq_mode
15259       && bytemode != ymm_mode
15260       && bytemode != d_scalar_swap_mode
15261       && bytemode != q_scalar_swap_mode
15262       && bytemode != vex_scalar_w_dq_mode)
15263     {
15264       switch (vex.length)
15265         {
15266         case 128:
15267           names = names_xmm;
15268           break;
15269         case 256:
15270           names = names_ymm;
15271           break;
15272         case 512:
15273           names = names_zmm;
15274           break;
15275         default:
15276           abort ();
15277         }
15278     }
15279   else if (bytemode == xmmq_mode
15280            || bytemode == evex_half_bcst_xmmq_mode)
15281     {
15282       switch (vex.length)
15283         {
15284         case 128:
15285         case 256:
15286           names = names_xmm;
15287           break;
15288         case 512:
15289           names = names_ymm;
15290           break;
15291         default:
15292           abort ();
15293         }
15294     }
15295   else if (bytemode == ymm_mode)
15296     names = names_ymm;
15297   else
15298     names = names_xmm;
15299   oappend (names[reg]);
15300 }
15301
15302 static void
15303 OP_MS (int bytemode, int sizeflag)
15304 {
15305   if (modrm.mod == 3)
15306     OP_EM (bytemode, sizeflag);
15307   else
15308     BadOp ();
15309 }
15310
15311 static void
15312 OP_XS (int bytemode, int sizeflag)
15313 {
15314   if (modrm.mod == 3)
15315     OP_EX (bytemode, sizeflag);
15316   else
15317     BadOp ();
15318 }
15319
15320 static void
15321 OP_M (int bytemode, int sizeflag)
15322 {
15323   if (modrm.mod == 3)
15324     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15325     BadOp ();
15326   else
15327     OP_E (bytemode, sizeflag);
15328 }
15329
15330 static void
15331 OP_0f07 (int bytemode, int sizeflag)
15332 {
15333   if (modrm.mod != 3 || modrm.rm != 0)
15334     BadOp ();
15335   else
15336     OP_E (bytemode, sizeflag);
15337 }
15338
15339 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15340    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15341
15342 static void
15343 NOP_Fixup1 (int bytemode, int sizeflag)
15344 {
15345   if ((prefixes & PREFIX_DATA) != 0
15346       || (rex != 0
15347           && rex != 0x48
15348           && address_mode == mode_64bit))
15349     OP_REG (bytemode, sizeflag);
15350   else
15351     strcpy (obuf, "nop");
15352 }
15353
15354 static void
15355 NOP_Fixup2 (int bytemode, int sizeflag)
15356 {
15357   if ((prefixes & PREFIX_DATA) != 0
15358       || (rex != 0
15359           && rex != 0x48
15360           && address_mode == mode_64bit))
15361     OP_IMREG (bytemode, sizeflag);
15362 }
15363
15364 static const char *const Suffix3DNow[] = {
15365 /* 00 */        NULL,           NULL,           NULL,           NULL,
15366 /* 04 */        NULL,           NULL,           NULL,           NULL,
15367 /* 08 */        NULL,           NULL,           NULL,           NULL,
15368 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15369 /* 10 */        NULL,           NULL,           NULL,           NULL,
15370 /* 14 */        NULL,           NULL,           NULL,           NULL,
15371 /* 18 */        NULL,           NULL,           NULL,           NULL,
15372 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15373 /* 20 */        NULL,           NULL,           NULL,           NULL,
15374 /* 24 */        NULL,           NULL,           NULL,           NULL,
15375 /* 28 */        NULL,           NULL,           NULL,           NULL,
15376 /* 2C */        NULL,           NULL,           NULL,           NULL,
15377 /* 30 */        NULL,           NULL,           NULL,           NULL,
15378 /* 34 */        NULL,           NULL,           NULL,           NULL,
15379 /* 38 */        NULL,           NULL,           NULL,           NULL,
15380 /* 3C */        NULL,           NULL,           NULL,           NULL,
15381 /* 40 */        NULL,           NULL,           NULL,           NULL,
15382 /* 44 */        NULL,           NULL,           NULL,           NULL,
15383 /* 48 */        NULL,           NULL,           NULL,           NULL,
15384 /* 4C */        NULL,           NULL,           NULL,           NULL,
15385 /* 50 */        NULL,           NULL,           NULL,           NULL,
15386 /* 54 */        NULL,           NULL,           NULL,           NULL,
15387 /* 58 */        NULL,           NULL,           NULL,           NULL,
15388 /* 5C */        NULL,           NULL,           NULL,           NULL,
15389 /* 60 */        NULL,           NULL,           NULL,           NULL,
15390 /* 64 */        NULL,           NULL,           NULL,           NULL,
15391 /* 68 */        NULL,           NULL,           NULL,           NULL,
15392 /* 6C */        NULL,           NULL,           NULL,           NULL,
15393 /* 70 */        NULL,           NULL,           NULL,           NULL,
15394 /* 74 */        NULL,           NULL,           NULL,           NULL,
15395 /* 78 */        NULL,           NULL,           NULL,           NULL,
15396 /* 7C */        NULL,           NULL,           NULL,           NULL,
15397 /* 80 */        NULL,           NULL,           NULL,           NULL,
15398 /* 84 */        NULL,           NULL,           NULL,           NULL,
15399 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15400 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15401 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15402 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15403 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15404 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15405 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15406 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15407 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15408 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15409 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15410 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15411 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15412 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15413 /* C0 */        NULL,           NULL,           NULL,           NULL,
15414 /* C4 */        NULL,           NULL,           NULL,           NULL,
15415 /* C8 */        NULL,           NULL,           NULL,           NULL,
15416 /* CC */        NULL,           NULL,           NULL,           NULL,
15417 /* D0 */        NULL,           NULL,           NULL,           NULL,
15418 /* D4 */        NULL,           NULL,           NULL,           NULL,
15419 /* D8 */        NULL,           NULL,           NULL,           NULL,
15420 /* DC */        NULL,           NULL,           NULL,           NULL,
15421 /* E0 */        NULL,           NULL,           NULL,           NULL,
15422 /* E4 */        NULL,           NULL,           NULL,           NULL,
15423 /* E8 */        NULL,           NULL,           NULL,           NULL,
15424 /* EC */        NULL,           NULL,           NULL,           NULL,
15425 /* F0 */        NULL,           NULL,           NULL,           NULL,
15426 /* F4 */        NULL,           NULL,           NULL,           NULL,
15427 /* F8 */        NULL,           NULL,           NULL,           NULL,
15428 /* FC */        NULL,           NULL,           NULL,           NULL,
15429 };
15430
15431 static void
15432 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15433 {
15434   const char *mnemonic;
15435
15436   FETCH_DATA (the_info, codep + 1);
15437   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15438      place where an 8-bit immediate would normally go.  ie. the last
15439      byte of the instruction.  */
15440   obufp = mnemonicendp;
15441   mnemonic = Suffix3DNow[*codep++ & 0xff];
15442   if (mnemonic)
15443     oappend (mnemonic);
15444   else
15445     {
15446       /* Since a variable sized modrm/sib chunk is between the start
15447          of the opcode (0x0f0f) and the opcode suffix, we need to do
15448          all the modrm processing first, and don't know until now that
15449          we have a bad opcode.  This necessitates some cleaning up.  */
15450       op_out[0][0] = '\0';
15451       op_out[1][0] = '\0';
15452       BadOp ();
15453     }
15454   mnemonicendp = obufp;
15455 }
15456
15457 static struct op simd_cmp_op[] =
15458 {
15459   { STRING_COMMA_LEN ("eq") },
15460   { STRING_COMMA_LEN ("lt") },
15461   { STRING_COMMA_LEN ("le") },
15462   { STRING_COMMA_LEN ("unord") },
15463   { STRING_COMMA_LEN ("neq") },
15464   { STRING_COMMA_LEN ("nlt") },
15465   { STRING_COMMA_LEN ("nle") },
15466   { STRING_COMMA_LEN ("ord") }
15467 };
15468
15469 static void
15470 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15471 {
15472   unsigned int cmp_type;
15473
15474   FETCH_DATA (the_info, codep + 1);
15475   cmp_type = *codep++ & 0xff;
15476   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15477     {
15478       char suffix [3];
15479       char *p = mnemonicendp - 2;
15480       suffix[0] = p[0];
15481       suffix[1] = p[1];
15482       suffix[2] = '\0';
15483       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15484       mnemonicendp += simd_cmp_op[cmp_type].len;
15485     }
15486   else
15487     {
15488       /* We have a reserved extension byte.  Output it directly.  */
15489       scratchbuf[0] = '$';
15490       print_operand_value (scratchbuf + 1, 1, cmp_type);
15491       oappend_maybe_intel (scratchbuf);
15492       scratchbuf[0] = '\0';
15493     }
15494 }
15495
15496 static void
15497 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15498 {
15499   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15500   if (!intel_syntax)
15501     {
15502       strcpy (op_out[0], names32[0]);
15503       strcpy (op_out[1], names32[1]);
15504       if (bytemode == eBX_reg)
15505         strcpy (op_out[2], names32[3]);
15506       two_source_ops = 1;
15507     }
15508   /* Skip mod/rm byte.  */
15509   MODRM_CHECK;
15510   codep++;
15511 }
15512
15513 static void
15514 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15515             int sizeflag ATTRIBUTE_UNUSED)
15516 {
15517   /* monitor %{e,r,}ax,%ecx,%edx"  */
15518   if (!intel_syntax)
15519     {
15520       const char **names = (address_mode == mode_64bit
15521                             ? names64 : names32);
15522
15523       if (prefixes & PREFIX_ADDR)
15524         {
15525           /* Remove "addr16/addr32".  */
15526           all_prefixes[last_addr_prefix] = 0;
15527           names = (address_mode != mode_32bit
15528                    ? names32 : names16);
15529           used_prefixes |= PREFIX_ADDR;
15530         }
15531       else if (address_mode == mode_16bit)
15532         names = names16;
15533       strcpy (op_out[0], names[0]);
15534       strcpy (op_out[1], names32[1]);
15535       strcpy (op_out[2], names32[2]);
15536       two_source_ops = 1;
15537     }
15538   /* Skip mod/rm byte.  */
15539   MODRM_CHECK;
15540   codep++;
15541 }
15542
15543 static void
15544 BadOp (void)
15545 {
15546   /* Throw away prefixes and 1st. opcode byte.  */
15547   codep = insn_codep + 1;
15548   oappend ("(bad)");
15549 }
15550
15551 static void
15552 REP_Fixup (int bytemode, int sizeflag)
15553 {
15554   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15555      lods and stos.  */
15556   if (prefixes & PREFIX_REPZ)
15557     all_prefixes[last_repz_prefix] = REP_PREFIX;
15558
15559   switch (bytemode)
15560     {
15561     case al_reg:
15562     case eAX_reg:
15563     case indir_dx_reg:
15564       OP_IMREG (bytemode, sizeflag);
15565       break;
15566     case eDI_reg:
15567       OP_ESreg (bytemode, sizeflag);
15568       break;
15569     case eSI_reg:
15570       OP_DSreg (bytemode, sizeflag);
15571       break;
15572     default:
15573       abort ();
15574       break;
15575     }
15576 }
15577
15578 static void
15579 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15580 {
15581   if ( isa64 != amd64 )
15582     return;
15583
15584   obufp = obuf;
15585   BadOp ();
15586   mnemonicendp = obufp;
15587   ++codep;
15588 }
15589
15590 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15591    "bnd".  */
15592
15593 static void
15594 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15595 {
15596   if (prefixes & PREFIX_REPNZ)
15597     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15598 }
15599
15600 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15601    "notrack".  */
15602
15603 static void
15604 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15605                int sizeflag ATTRIBUTE_UNUSED)
15606 {
15607   if (active_seg_prefix == PREFIX_DS
15608       && (address_mode != mode_64bit || last_data_prefix < 0))
15609     {
15610       /* NOTRACK prefix is only valid on indirect branch instructions.
15611          NB: DATA prefix is unsupported for Intel64.  */
15612       active_seg_prefix = 0;
15613       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15614     }
15615 }
15616
15617 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15618    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15619  */
15620
15621 static void
15622 HLE_Fixup1 (int bytemode, int sizeflag)
15623 {
15624   if (modrm.mod != 3
15625       && (prefixes & PREFIX_LOCK) != 0)
15626     {
15627       if (prefixes & PREFIX_REPZ)
15628         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15629       if (prefixes & PREFIX_REPNZ)
15630         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15631     }
15632
15633   OP_E (bytemode, sizeflag);
15634 }
15635
15636 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15637    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15638  */
15639
15640 static void
15641 HLE_Fixup2 (int bytemode, int sizeflag)
15642 {
15643   if (modrm.mod != 3)
15644     {
15645       if (prefixes & PREFIX_REPZ)
15646         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15647       if (prefixes & PREFIX_REPNZ)
15648         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15649     }
15650
15651   OP_E (bytemode, sizeflag);
15652 }
15653
15654 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15655    "xrelease" for memory operand.  No check for LOCK prefix.   */
15656
15657 static void
15658 HLE_Fixup3 (int bytemode, int sizeflag)
15659 {
15660   if (modrm.mod != 3
15661       && last_repz_prefix > last_repnz_prefix
15662       && (prefixes & PREFIX_REPZ) != 0)
15663     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15664
15665   OP_E (bytemode, sizeflag);
15666 }
15667
15668 static void
15669 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15670 {
15671   USED_REX (REX_W);
15672   if (rex & REX_W)
15673     {
15674       /* Change cmpxchg8b to cmpxchg16b.  */
15675       char *p = mnemonicendp - 2;
15676       mnemonicendp = stpcpy (p, "16b");
15677       bytemode = o_mode;
15678     }
15679   else if ((prefixes & PREFIX_LOCK) != 0)
15680     {
15681       if (prefixes & PREFIX_REPZ)
15682         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15683       if (prefixes & PREFIX_REPNZ)
15684         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15685     }
15686
15687   OP_M (bytemode, sizeflag);
15688 }
15689
15690 static void
15691 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15692 {
15693   const char **names;
15694
15695   if (need_vex)
15696     {
15697       switch (vex.length)
15698         {
15699         case 128:
15700           names = names_xmm;
15701           break;
15702         case 256:
15703           names = names_ymm;
15704           break;
15705         default:
15706           abort ();
15707         }
15708     }
15709   else
15710     names = names_xmm;
15711   oappend (names[reg]);
15712 }
15713
15714 static void
15715 CRC32_Fixup (int bytemode, int sizeflag)
15716 {
15717   /* Add proper suffix to "crc32".  */
15718   char *p = mnemonicendp;
15719
15720   switch (bytemode)
15721     {
15722     case b_mode:
15723       if (intel_syntax)
15724         goto skip;
15725
15726       *p++ = 'b';
15727       break;
15728     case v_mode:
15729       if (intel_syntax)
15730         goto skip;
15731
15732       USED_REX (REX_W);
15733       if (rex & REX_W)
15734         *p++ = 'q';
15735       else
15736         {
15737           if (sizeflag & DFLAG)
15738             *p++ = 'l';
15739           else
15740             *p++ = 'w';
15741           used_prefixes |= (prefixes & PREFIX_DATA);
15742         }
15743       break;
15744     default:
15745       oappend (INTERNAL_DISASSEMBLER_ERROR);
15746       break;
15747     }
15748   mnemonicendp = p;
15749   *p = '\0';
15750
15751  skip:
15752   if (modrm.mod == 3)
15753     {
15754       int add;
15755
15756       /* Skip mod/rm byte.  */
15757       MODRM_CHECK;
15758       codep++;
15759
15760       USED_REX (REX_B);
15761       add = (rex & REX_B) ? 8 : 0;
15762       if (bytemode == b_mode)
15763         {
15764           USED_REX (0);
15765           if (rex)
15766             oappend (names8rex[modrm.rm + add]);
15767           else
15768             oappend (names8[modrm.rm + add]);
15769         }
15770       else
15771         {
15772           USED_REX (REX_W);
15773           if (rex & REX_W)
15774             oappend (names64[modrm.rm + add]);
15775           else if ((prefixes & PREFIX_DATA))
15776             oappend (names16[modrm.rm + add]);
15777           else
15778             oappend (names32[modrm.rm + add]);
15779         }
15780     }
15781   else
15782     OP_E (bytemode, sizeflag);
15783 }
15784
15785 static void
15786 FXSAVE_Fixup (int bytemode, int sizeflag)
15787 {
15788   /* Add proper suffix to "fxsave" and "fxrstor".  */
15789   USED_REX (REX_W);
15790   if (rex & REX_W)
15791     {
15792       char *p = mnemonicendp;
15793       *p++ = '6';
15794       *p++ = '4';
15795       *p = '\0';
15796       mnemonicendp = p;
15797     }
15798   OP_M (bytemode, sizeflag);
15799 }
15800
15801 static void
15802 PCMPESTR_Fixup (int bytemode, int sizeflag)
15803 {
15804   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15805   if (!intel_syntax)
15806     {
15807       char *p = mnemonicendp;
15808
15809       USED_REX (REX_W);
15810       if (rex & REX_W)
15811         *p++ = 'q';
15812       else if (sizeflag & SUFFIX_ALWAYS)
15813         *p++ = 'l';
15814
15815       *p = '\0';
15816       mnemonicendp = p;
15817     }
15818
15819   OP_EX (bytemode, sizeflag);
15820 }
15821
15822 /* Display the destination register operand for instructions with
15823    VEX. */
15824
15825 static void
15826 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15827 {
15828   int reg;
15829   const char **names;
15830
15831   if (!need_vex)
15832     abort ();
15833
15834   if (!need_vex_reg)
15835     return;
15836
15837   reg = vex.register_specifier;
15838   vex.register_specifier = 0;
15839   if (address_mode != mode_64bit)
15840     reg &= 7;
15841   else if (vex.evex && !vex.v)
15842     reg += 16;
15843
15844   if (bytemode == vex_scalar_mode)
15845     {
15846       oappend (names_xmm[reg]);
15847       return;
15848     }
15849
15850   switch (vex.length)
15851     {
15852     case 128:
15853       switch (bytemode)
15854         {
15855         case vex_mode:
15856         case vex128_mode:
15857         case vex_vsib_q_w_dq_mode:
15858         case vex_vsib_q_w_d_mode:
15859           names = names_xmm;
15860           break;
15861         case dq_mode:
15862           if (rex & REX_W)
15863             names = names64;
15864           else
15865             names = names32;
15866           break;
15867         case mask_bd_mode:
15868         case mask_mode:
15869           if (reg > 0x7)
15870             {
15871               oappend ("(bad)");
15872               return;
15873             }
15874           names = names_mask;
15875           break;
15876         default:
15877           abort ();
15878           return;
15879         }
15880       break;
15881     case 256:
15882       switch (bytemode)
15883         {
15884         case vex_mode:
15885         case vex256_mode:
15886           names = names_ymm;
15887           break;
15888         case vex_vsib_q_w_dq_mode:
15889         case vex_vsib_q_w_d_mode:
15890           names = vex.w ? names_ymm : names_xmm;
15891           break;
15892         case mask_bd_mode:
15893         case mask_mode:
15894           if (reg > 0x7)
15895             {
15896               oappend ("(bad)");
15897               return;
15898             }
15899           names = names_mask;
15900           break;
15901         default:
15902           /* See PR binutils/20893 for a reproducer.  */
15903           oappend ("(bad)");
15904           return;
15905         }
15906       break;
15907     case 512:
15908       names = names_zmm;
15909       break;
15910     default:
15911       abort ();
15912       break;
15913     }
15914   oappend (names[reg]);
15915 }
15916
15917 /* Get the VEX immediate byte without moving codep.  */
15918
15919 static unsigned char
15920 get_vex_imm8 (int sizeflag, int opnum)
15921 {
15922   int bytes_before_imm = 0;
15923
15924   if (modrm.mod != 3)
15925     {
15926       /* There are SIB/displacement bytes.  */
15927       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15928         {
15929           /* 32/64 bit address mode */
15930           int base = modrm.rm;
15931
15932           /* Check SIB byte.  */
15933           if (base == 4)
15934             {
15935               FETCH_DATA (the_info, codep + 1);
15936               base = *codep & 7;
15937               /* When decoding the third source, don't increase
15938                  bytes_before_imm as this has already been incremented
15939                  by one in OP_E_memory while decoding the second
15940                  source operand.  */
15941               if (opnum == 0)
15942                 bytes_before_imm++;
15943             }
15944
15945           /* Don't increase bytes_before_imm when decoding the third source,
15946              it has already been incremented by OP_E_memory while decoding
15947              the second source operand.  */
15948           if (opnum == 0)
15949             {
15950               switch (modrm.mod)
15951                 {
15952                   case 0:
15953                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15954                        SIB == 5, there is a 4 byte displacement.  */
15955                     if (base != 5)
15956                       /* No displacement. */
15957                       break;
15958                     /* Fall through.  */
15959                   case 2:
15960                     /* 4 byte displacement.  */
15961                     bytes_before_imm += 4;
15962                     break;
15963                   case 1:
15964                     /* 1 byte displacement.  */
15965                     bytes_before_imm++;
15966                     break;
15967                 }
15968             }
15969         }
15970       else
15971         {
15972           /* 16 bit address mode */
15973           /* Don't increase bytes_before_imm when decoding the third source,
15974              it has already been incremented by OP_E_memory while decoding
15975              the second source operand.  */
15976           if (opnum == 0)
15977             {
15978               switch (modrm.mod)
15979                 {
15980                 case 0:
15981                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
15982                   if (modrm.rm != 6)
15983                     /* No displacement. */
15984                     break;
15985                   /* Fall through.  */
15986                 case 2:
15987                   /* 2 byte displacement.  */
15988                   bytes_before_imm += 2;
15989                   break;
15990                 case 1:
15991                   /* 1 byte displacement: when decoding the third source,
15992                      don't increase bytes_before_imm as this has already
15993                      been incremented by one in OP_E_memory while decoding
15994                      the second source operand.  */
15995                   if (opnum == 0)
15996                     bytes_before_imm++;
15997
15998                   break;
15999                 }
16000             }
16001         }
16002     }
16003
16004   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16005   return codep [bytes_before_imm];
16006 }
16007
16008 static void
16009 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16010 {
16011   const char **names;
16012
16013   if (reg == -1 && modrm.mod != 3)
16014     {
16015       OP_E_memory (bytemode, sizeflag);
16016       return;
16017     }
16018   else
16019     {
16020       if (reg == -1)
16021         {
16022           reg = modrm.rm;
16023           USED_REX (REX_B);
16024           if (rex & REX_B)
16025             reg += 8;
16026         }
16027       if (address_mode != mode_64bit)
16028         reg &= 7;
16029     }
16030
16031   switch (vex.length)
16032     {
16033     case 128:
16034       names = names_xmm;
16035       break;
16036     case 256:
16037       names = names_ymm;
16038       break;
16039     default:
16040       abort ();
16041     }
16042   oappend (names[reg]);
16043 }
16044
16045 static void
16046 OP_EX_VexImmW (int bytemode, int sizeflag)
16047 {
16048   int reg = -1;
16049   static unsigned char vex_imm8;
16050
16051   if (vex_w_done == 0)
16052     {
16053       vex_w_done = 1;
16054
16055       /* Skip mod/rm byte.  */
16056       MODRM_CHECK;
16057       codep++;
16058
16059       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16060
16061       if (vex.w)
16062           reg = vex_imm8 >> 4;
16063
16064       OP_EX_VexReg (bytemode, sizeflag, reg);
16065     }
16066   else if (vex_w_done == 1)
16067     {
16068       vex_w_done = 2;
16069
16070       if (!vex.w)
16071           reg = vex_imm8 >> 4;
16072
16073       OP_EX_VexReg (bytemode, sizeflag, reg);
16074     }
16075   else
16076     {
16077       /* Output the imm8 directly.  */
16078       scratchbuf[0] = '$';
16079       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16080       oappend_maybe_intel (scratchbuf);
16081       scratchbuf[0] = '\0';
16082       codep++;
16083     }
16084 }
16085
16086 static void
16087 OP_Vex_2src (int bytemode, int sizeflag)
16088 {
16089   if (modrm.mod == 3)
16090     {
16091       int reg = modrm.rm;
16092       USED_REX (REX_B);
16093       if (rex & REX_B)
16094         reg += 8;
16095       oappend (names_xmm[reg]);
16096     }
16097   else
16098     {
16099       if (intel_syntax
16100           && (bytemode == v_mode || bytemode == v_swap_mode))
16101         {
16102           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16103           used_prefixes |= (prefixes & PREFIX_DATA);
16104         }
16105       OP_E (bytemode, sizeflag);
16106     }
16107 }
16108
16109 static void
16110 OP_Vex_2src_1 (int bytemode, int sizeflag)
16111 {
16112   if (modrm.mod == 3)
16113     {
16114       /* Skip mod/rm byte.   */
16115       MODRM_CHECK;
16116       codep++;
16117     }
16118
16119   if (vex.w)
16120     {
16121       unsigned int reg = vex.register_specifier;
16122       vex.register_specifier = 0;
16123
16124       if (address_mode != mode_64bit)
16125         reg &= 7;
16126       oappend (names_xmm[reg]);
16127     }
16128   else
16129     OP_Vex_2src (bytemode, sizeflag);
16130 }
16131
16132 static void
16133 OP_Vex_2src_2 (int bytemode, int sizeflag)
16134 {
16135   if (vex.w)
16136     OP_Vex_2src (bytemode, sizeflag);
16137   else
16138     {
16139       unsigned int reg = vex.register_specifier;
16140       vex.register_specifier = 0;
16141
16142       if (address_mode != mode_64bit)
16143         reg &= 7;
16144       oappend (names_xmm[reg]);
16145     }
16146 }
16147
16148 static void
16149 OP_EX_VexW (int bytemode, int sizeflag)
16150 {
16151   int reg = -1;
16152
16153   if (!vex_w_done)
16154     {
16155       /* Skip mod/rm byte.  */
16156       MODRM_CHECK;
16157       codep++;
16158
16159       if (vex.w)
16160         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16161     }
16162   else
16163     {
16164       if (!vex.w)
16165         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16166     }
16167
16168   OP_EX_VexReg (bytemode, sizeflag, reg);
16169
16170   if (vex_w_done)
16171     codep++;
16172   vex_w_done = 1;
16173 }
16174
16175 static void
16176 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16177 {
16178   int reg;
16179   const char **names;
16180
16181   FETCH_DATA (the_info, codep + 1);
16182   reg = *codep++;
16183
16184   if (bytemode != x_mode)
16185     abort ();
16186
16187   reg >>= 4;
16188   if (address_mode != mode_64bit)
16189     reg &= 7;
16190
16191   switch (vex.length)
16192     {
16193     case 128:
16194       names = names_xmm;
16195       break;
16196     case 256:
16197       names = names_ymm;
16198       break;
16199     default:
16200       abort ();
16201     }
16202   oappend (names[reg]);
16203 }
16204
16205 static void
16206 OP_XMM_VexW (int bytemode, int sizeflag)
16207 {
16208   /* Turn off the REX.W bit since it is used for swapping operands
16209      now.  */
16210   rex &= ~REX_W;
16211   OP_XMM (bytemode, sizeflag);
16212 }
16213
16214 static void
16215 OP_EX_Vex (int bytemode, int sizeflag)
16216 {
16217   if (modrm.mod != 3)
16218     need_vex_reg = 0;
16219   OP_EX (bytemode, sizeflag);
16220 }
16221
16222 static void
16223 OP_XMM_Vex (int bytemode, int sizeflag)
16224 {
16225   if (modrm.mod != 3)
16226     need_vex_reg = 0;
16227   OP_XMM (bytemode, sizeflag);
16228 }
16229
16230 static struct op vex_cmp_op[] =
16231 {
16232   { STRING_COMMA_LEN ("eq") },
16233   { STRING_COMMA_LEN ("lt") },
16234   { STRING_COMMA_LEN ("le") },
16235   { STRING_COMMA_LEN ("unord") },
16236   { STRING_COMMA_LEN ("neq") },
16237   { STRING_COMMA_LEN ("nlt") },
16238   { STRING_COMMA_LEN ("nle") },
16239   { STRING_COMMA_LEN ("ord") },
16240   { STRING_COMMA_LEN ("eq_uq") },
16241   { STRING_COMMA_LEN ("nge") },
16242   { STRING_COMMA_LEN ("ngt") },
16243   { STRING_COMMA_LEN ("false") },
16244   { STRING_COMMA_LEN ("neq_oq") },
16245   { STRING_COMMA_LEN ("ge") },
16246   { STRING_COMMA_LEN ("gt") },
16247   { STRING_COMMA_LEN ("true") },
16248   { STRING_COMMA_LEN ("eq_os") },
16249   { STRING_COMMA_LEN ("lt_oq") },
16250   { STRING_COMMA_LEN ("le_oq") },
16251   { STRING_COMMA_LEN ("unord_s") },
16252   { STRING_COMMA_LEN ("neq_us") },
16253   { STRING_COMMA_LEN ("nlt_uq") },
16254   { STRING_COMMA_LEN ("nle_uq") },
16255   { STRING_COMMA_LEN ("ord_s") },
16256   { STRING_COMMA_LEN ("eq_us") },
16257   { STRING_COMMA_LEN ("nge_uq") },
16258   { STRING_COMMA_LEN ("ngt_uq") },
16259   { STRING_COMMA_LEN ("false_os") },
16260   { STRING_COMMA_LEN ("neq_os") },
16261   { STRING_COMMA_LEN ("ge_oq") },
16262   { STRING_COMMA_LEN ("gt_oq") },
16263   { STRING_COMMA_LEN ("true_us") },
16264 };
16265
16266 static void
16267 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16268 {
16269   unsigned int cmp_type;
16270
16271   FETCH_DATA (the_info, codep + 1);
16272   cmp_type = *codep++ & 0xff;
16273   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16274     {
16275       char suffix [3];
16276       char *p = mnemonicendp - 2;
16277       suffix[0] = p[0];
16278       suffix[1] = p[1];
16279       suffix[2] = '\0';
16280       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16281       mnemonicendp += vex_cmp_op[cmp_type].len;
16282     }
16283   else
16284     {
16285       /* We have a reserved extension byte.  Output it directly.  */
16286       scratchbuf[0] = '$';
16287       print_operand_value (scratchbuf + 1, 1, cmp_type);
16288       oappend_maybe_intel (scratchbuf);
16289       scratchbuf[0] = '\0';
16290     }
16291 }
16292
16293 static void
16294 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16295              int sizeflag ATTRIBUTE_UNUSED)
16296 {
16297   unsigned int cmp_type;
16298
16299   if (!vex.evex)
16300     abort ();
16301
16302   FETCH_DATA (the_info, codep + 1);
16303   cmp_type = *codep++ & 0xff;
16304   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16305      If it's the case, print suffix, otherwise - print the immediate.  */
16306   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16307       && cmp_type != 3
16308       && cmp_type != 7)
16309     {
16310       char suffix [3];
16311       char *p = mnemonicendp - 2;
16312
16313       /* vpcmp* can have both one- and two-lettered suffix.  */
16314       if (p[0] == 'p')
16315         {
16316           p++;
16317           suffix[0] = p[0];
16318           suffix[1] = '\0';
16319         }
16320       else
16321         {
16322           suffix[0] = p[0];
16323           suffix[1] = p[1];
16324           suffix[2] = '\0';
16325         }
16326
16327       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16328       mnemonicendp += simd_cmp_op[cmp_type].len;
16329     }
16330   else
16331     {
16332       /* We have a reserved extension byte.  Output it directly.  */
16333       scratchbuf[0] = '$';
16334       print_operand_value (scratchbuf + 1, 1, cmp_type);
16335       oappend_maybe_intel (scratchbuf);
16336       scratchbuf[0] = '\0';
16337     }
16338 }
16339
16340 static const struct op xop_cmp_op[] =
16341 {
16342   { STRING_COMMA_LEN ("lt") },
16343   { STRING_COMMA_LEN ("le") },
16344   { STRING_COMMA_LEN ("gt") },
16345   { STRING_COMMA_LEN ("ge") },
16346   { STRING_COMMA_LEN ("eq") },
16347   { STRING_COMMA_LEN ("neq") },
16348   { STRING_COMMA_LEN ("false") },
16349   { STRING_COMMA_LEN ("true") }
16350 };
16351
16352 static void
16353 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16354              int sizeflag ATTRIBUTE_UNUSED)
16355 {
16356   unsigned int cmp_type;
16357
16358   FETCH_DATA (the_info, codep + 1);
16359   cmp_type = *codep++ & 0xff;
16360   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16361     {
16362       char suffix[3];
16363       char *p = mnemonicendp - 2;
16364
16365       /* vpcom* can have both one- and two-lettered suffix.  */
16366       if (p[0] == 'm')
16367         {
16368           p++;
16369           suffix[0] = p[0];
16370           suffix[1] = '\0';
16371         }
16372       else
16373         {
16374           suffix[0] = p[0];
16375           suffix[1] = p[1];
16376           suffix[2] = '\0';
16377         }
16378
16379       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16380       mnemonicendp += xop_cmp_op[cmp_type].len;
16381     }
16382   else
16383     {
16384       /* We have a reserved extension byte.  Output it directly.  */
16385       scratchbuf[0] = '$';
16386       print_operand_value (scratchbuf + 1, 1, cmp_type);
16387       oappend_maybe_intel (scratchbuf);
16388       scratchbuf[0] = '\0';
16389     }
16390 }
16391
16392 static const struct op pclmul_op[] =
16393 {
16394   { STRING_COMMA_LEN ("lql") },
16395   { STRING_COMMA_LEN ("hql") },
16396   { STRING_COMMA_LEN ("lqh") },
16397   { STRING_COMMA_LEN ("hqh") }
16398 };
16399
16400 static void
16401 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16402               int sizeflag ATTRIBUTE_UNUSED)
16403 {
16404   unsigned int pclmul_type;
16405
16406   FETCH_DATA (the_info, codep + 1);
16407   pclmul_type = *codep++ & 0xff;
16408   switch (pclmul_type)
16409     {
16410     case 0x10:
16411       pclmul_type = 2;
16412       break;
16413     case 0x11:
16414       pclmul_type = 3;
16415       break;
16416     default:
16417       break;
16418     }
16419   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16420     {
16421       char suffix [4];
16422       char *p = mnemonicendp - 3;
16423       suffix[0] = p[0];
16424       suffix[1] = p[1];
16425       suffix[2] = p[2];
16426       suffix[3] = '\0';
16427       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16428       mnemonicendp += pclmul_op[pclmul_type].len;
16429     }
16430   else
16431     {
16432       /* We have a reserved extension byte.  Output it directly.  */
16433       scratchbuf[0] = '$';
16434       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16435       oappend_maybe_intel (scratchbuf);
16436       scratchbuf[0] = '\0';
16437     }
16438 }
16439
16440 static void
16441 MOVBE_Fixup (int bytemode, int sizeflag)
16442 {
16443   /* Add proper suffix to "movbe".  */
16444   char *p = mnemonicendp;
16445
16446   switch (bytemode)
16447     {
16448     case v_mode:
16449       if (intel_syntax)
16450         goto skip;
16451
16452       USED_REX (REX_W);
16453       if (sizeflag & SUFFIX_ALWAYS)
16454         {
16455           if (rex & REX_W)
16456             *p++ = 'q';
16457           else
16458             {
16459               if (sizeflag & DFLAG)
16460                 *p++ = 'l';
16461               else
16462                 *p++ = 'w';
16463               used_prefixes |= (prefixes & PREFIX_DATA);
16464             }
16465         }
16466       break;
16467     default:
16468       oappend (INTERNAL_DISASSEMBLER_ERROR);
16469       break;
16470     }
16471   mnemonicendp = p;
16472   *p = '\0';
16473
16474  skip:
16475   OP_M (bytemode, sizeflag);
16476 }
16477
16478 static void
16479 MOVSXD_Fixup (int bytemode, int sizeflag)
16480 {
16481   /* Add proper suffix to "movsxd".  */
16482   char *p = mnemonicendp;
16483
16484   switch (bytemode)
16485     {
16486     case movsxd_mode:
16487       if (intel_syntax)
16488         {
16489           *p++ = 'x';
16490           *p++ = 'd';
16491           goto skip;
16492         }
16493
16494       USED_REX (REX_W);
16495       if (rex & REX_W)
16496         {
16497           *p++ = 'l';
16498           *p++ = 'q';
16499         }
16500       else
16501         {
16502           *p++ = 'x';
16503           *p++ = 'd';
16504         }
16505       break;
16506     default:
16507       oappend (INTERNAL_DISASSEMBLER_ERROR);
16508       break;
16509     }
16510
16511  skip:
16512   mnemonicendp = p;
16513   *p = '\0';
16514   OP_E (bytemode, sizeflag);
16515 }
16516
16517 static void
16518 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16519 {
16520   int reg;
16521   const char **names;
16522
16523   /* Skip mod/rm byte.  */
16524   MODRM_CHECK;
16525   codep++;
16526
16527   if (rex & REX_W)
16528     names = names64;
16529   else
16530     names = names32;
16531
16532   reg = modrm.rm;
16533   USED_REX (REX_B);
16534   if (rex & REX_B)
16535     reg += 8;
16536
16537   oappend (names[reg]);
16538 }
16539
16540 static void
16541 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16542 {
16543   const char **names;
16544   unsigned int reg = vex.register_specifier;
16545   vex.register_specifier = 0;
16546
16547   if (rex & REX_W)
16548     names = names64;
16549   else
16550     names = names32;
16551
16552   if (address_mode != mode_64bit)
16553     reg &= 7;
16554   oappend (names[reg]);
16555 }
16556
16557 static void
16558 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16559 {
16560   if (!vex.evex
16561       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16562     abort ();
16563
16564   USED_REX (REX_R);
16565   if ((rex & REX_R) != 0 || !vex.r)
16566     {
16567       BadOp ();
16568       return;
16569     }
16570
16571   oappend (names_mask [modrm.reg]);
16572 }
16573
16574 static void
16575 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16576 {
16577   if (modrm.mod == 3 && vex.b)
16578     switch (bytemode)
16579       {
16580       case evex_rounding_64_mode:
16581         if (address_mode != mode_64bit)
16582           {
16583             oappend ("(bad)");
16584             break;
16585           }
16586         /* Fall through.  */
16587       case evex_rounding_mode:
16588         oappend (names_rounding[vex.ll]);
16589         break;
16590       case evex_sae_mode:
16591         oappend ("{sae}");
16592         break;
16593       default:
16594         abort ();
16595         break;
16596       }
16597 }