opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_Rounding (int, int);
  98 static void OP_REG_VexI4 (int, int);
  99 static void PCLMUL_Fixup (int, int);
 100 static void VEXI4_Fixup (int, int);
 101 static void VZERO_Fixup (int, int);
 102 static void VCMP_Fixup (int, int);
 103 static void VPCMP_Fixup (int, int);
 104 static void OP_0f07 (int, int);
 105 static void OP_Monitor (int, int);
 106 static void OP_Mwait (int, int);
 107 static void NOP_Fixup1 (int, int);
 108 static void NOP_Fixup2 (int, int);
 109 static void OP_3DNowSuffix (int, int);
 110 static void CMP_Fixup (int, int);
 111 static void BadOp (void);
 112 static void REP_Fixup (int, int);
 113 static void BND_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   jmp_buf bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       longjmp (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 #define XX { NULL, 0 }
 227 #define Bad_Opcode NULL, { { NULL, 0 } }
 228
 229 #define Eb { OP_E, b_mode }
 230 #define Ebnd { OP_E, bnd_mode }
 231 #define EbS { OP_E, b_swap_mode }
 232 #define Ev { OP_E, v_mode }
 233 #define Ev_bnd { OP_E, v_bnd_mode }
 234 #define EvS { OP_E, v_swap_mode }
 235 #define Ed { OP_E, d_mode }
 236 #define Edq { OP_E, dq_mode }
 237 #define Edqw { OP_E, dqw_mode }
 238 #define Edqb { OP_E, dqb_mode }
 239 #define Edqd { OP_E, dqd_mode }
 240 #define Eq { OP_E, q_mode }
 241 #define indirEv { OP_indirE, stack_v_mode }
 242 #define indirEp { OP_indirE, f_mode }
 243 #define stackEv { OP_E, stack_v_mode }
 244 #define Em { OP_E, m_mode }
 245 #define Ew { OP_E, w_mode }
 246 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 247 #define Ma { OP_M, a_mode }
 248 #define Mb { OP_M, b_mode }
 249 #define Md { OP_M, d_mode }
 250 #define Mo { OP_M, o_mode }
 251 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 252 #define Mq { OP_M, q_mode }
 253 #define Mx { OP_M, x_mode }
 254 #define Mxmm { OP_M, xmm_mode }
 255 #define Gb { OP_G, b_mode }
 256 #define Gbnd { OP_G, bnd_mode }
 257 #define Gv { OP_G, v_mode }
 258 #define Gd { OP_G, d_mode }
 259 #define Gdq { OP_G, dq_mode }
 260 #define Gm { OP_G, m_mode }
 261 #define Gw { OP_G, w_mode }
 262 #define Rd { OP_R, d_mode }
 263 #define Rdq { OP_R, dq_mode }
 264 #define Rm { OP_R, m_mode }
 265 #define Ib { OP_I, b_mode }
 266 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 267 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 268 #define Iv { OP_I, v_mode }
 269 #define sIv { OP_sI, v_mode }
 270 #define Iq { OP_I, q_mode }
 271 #define Iv64 { OP_I64, v_mode }
 272 #define Iw { OP_I, w_mode }
 273 #define I1 { OP_I, const_1_mode }
 274 #define Jb { OP_J, b_mode }
 275 #define Jv { OP_J, v_mode }
 276 #define Cm { OP_C, m_mode }
 277 #define Dm { OP_D, m_mode }
 278 #define Td { OP_T, d_mode }
 279 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 280
 281 #define RMeAX { OP_REG, eAX_reg }
 282 #define RMeBX { OP_REG, eBX_reg }
 283 #define RMeCX { OP_REG, eCX_reg }
 284 #define RMeDX { OP_REG, eDX_reg }
 285 #define RMeSP { OP_REG, eSP_reg }
 286 #define RMeBP { OP_REG, eBP_reg }
 287 #define RMeSI { OP_REG, eSI_reg }
 288 #define RMeDI { OP_REG, eDI_reg }
 289 #define RMrAX { OP_REG, rAX_reg }
 290 #define RMrBX { OP_REG, rBX_reg }
 291 #define RMrCX { OP_REG, rCX_reg }
 292 #define RMrDX { OP_REG, rDX_reg }
 293 #define RMrSP { OP_REG, rSP_reg }
 294 #define RMrBP { OP_REG, rBP_reg }
 295 #define RMrSI { OP_REG, rSI_reg }
 296 #define RMrDI { OP_REG, rDI_reg }
 297 #define RMAL { OP_REG, al_reg }
 298 #define RMCL { OP_REG, cl_reg }
 299 #define RMDL { OP_REG, dl_reg }
 300 #define RMBL { OP_REG, bl_reg }
 301 #define RMAH { OP_REG, ah_reg }
 302 #define RMCH { OP_REG, ch_reg }
 303 #define RMDH { OP_REG, dh_reg }
 304 #define RMBH { OP_REG, bh_reg }
 305 #define RMAX { OP_REG, ax_reg }
 306 #define RMDX { OP_REG, dx_reg }
 307
 308 #define eAX { OP_IMREG, eAX_reg }
 309 #define eBX { OP_IMREG, eBX_reg }
 310 #define eCX { OP_IMREG, eCX_reg }
 311 #define eDX { OP_IMREG, eDX_reg }
 312 #define eSP { OP_IMREG, eSP_reg }
 313 #define eBP { OP_IMREG, eBP_reg }
 314 #define eSI { OP_IMREG, eSI_reg }
 315 #define eDI { OP_IMREG, eDI_reg }
 316 #define AL { OP_IMREG, al_reg }
 317 #define CL { OP_IMREG, cl_reg }
 318 #define DL { OP_IMREG, dl_reg }
 319 #define BL { OP_IMREG, bl_reg }
 320 #define AH { OP_IMREG, ah_reg }
 321 #define CH { OP_IMREG, ch_reg }
 322 #define DH { OP_IMREG, dh_reg }
 323 #define BH { OP_IMREG, bh_reg }
 324 #define AX { OP_IMREG, ax_reg }
 325 #define DX { OP_IMREG, dx_reg }
 326 #define zAX { OP_IMREG, z_mode_ax_reg }
 327 #define indirDX { OP_IMREG, indir_dx_reg }
 328
 329 #define Sw { OP_SEG, w_mode }
 330 #define Sv { OP_SEG, v_mode }
 331 #define Ap { OP_DIR, 0 }
 332 #define Ob { OP_OFF64, b_mode }
 333 #define Ov { OP_OFF64, v_mode }
 334 #define Xb { OP_DSreg, eSI_reg }
 335 #define Xv { OP_DSreg, eSI_reg }
 336 #define Xz { OP_DSreg, eSI_reg }
 337 #define Yb { OP_ESreg, eDI_reg }
 338 #define Yv { OP_ESreg, eDI_reg }
 339 #define DSBX { OP_DSreg, eBX_reg }
 340
 341 #define es { OP_REG, es_reg }
 342 #define ss { OP_REG, ss_reg }
 343 #define cs { OP_REG, cs_reg }
 344 #define ds { OP_REG, ds_reg }
 345 #define fs { OP_REG, fs_reg }
 346 #define gs { OP_REG, gs_reg }
 347
 348 #define MX { OP_MMX, 0 }
 349 #define XM { OP_XMM, 0 }
 350 #define XMScalar { OP_XMM, scalar_mode }
 351 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 352 #define XMM { OP_XMM, xmm_mode }
 353 #define XMxmmq { OP_XMM, xmmq_mode }
 354 #define EM { OP_EM, v_mode }
 355 #define EMS { OP_EM, v_swap_mode }
 356 #define EMd { OP_EM, d_mode }
 357 #define EMx { OP_EM, x_mode }
 358 #define EXw { OP_EX, w_mode }
 359 #define EXd { OP_EX, d_mode }
 360 #define EXdScalar { OP_EX, d_scalar_mode }
 361 #define EXdS { OP_EX, d_swap_mode }
 362 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 363 #define EXq { OP_EX, q_mode }
 364 #define EXqScalar { OP_EX, q_scalar_mode }
 365 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 366 #define EXqS { OP_EX, q_swap_mode }
 367 #define EXx { OP_EX, x_mode }
 368 #define EXxS { OP_EX, x_swap_mode }
 369 #define EXxmm { OP_EX, xmm_mode }
 370 #define EXymm { OP_EX, ymm_mode }
 371 #define EXxmmq { OP_EX, xmmq_mode }
 372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 375 #define EXxmm_md { OP_EX, xmm_md_mode }
 376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 377 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 378 #define EXxmmdw { OP_EX, xmmdw_mode }
 379 #define EXxmmqd { OP_EX, xmmqd_mode }
 380 #define EXymmq { OP_EX, ymmq_mode }
 381 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 382 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 383 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 384 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 385 #define MS { OP_MS, v_mode }
 386 #define XS { OP_XS, v_mode }
 387 #define EMCq { OP_EMC, q_mode }
 388 #define MXC { OP_MXC, 0 }
 389 #define OPSUF { OP_3DNowSuffix, 0 }
 390 #define CMP { CMP_Fixup, 0 }
 391 #define XMM0 { XMM_Fixup, 0 }
 392 #define FXSAVE { FXSAVE_Fixup, 0 }
 393 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 394 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 395
 396 #define Vex { OP_VEX, vex_mode }
 397 #define VexScalar { OP_VEX, vex_scalar_mode }
 398 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 399 #define Vex128 { OP_VEX, vex128_mode }
 400 #define Vex256 { OP_VEX, vex256_mode }
 401 #define VexGdq { OP_VEX, dq_mode }
 402 #define VexI4 { VEXI4_Fixup, 0}
 403 #define EXdVex { OP_EX_Vex, d_mode }
 404 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 405 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 406 #define EXqVex { OP_EX_Vex, q_mode }
 407 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 408 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 409 #define EXVexW { OP_EX_VexW, x_mode }
 410 #define EXdVexW { OP_EX_VexW, d_mode }
 411 #define EXqVexW { OP_EX_VexW, q_mode }
 412 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 413 #define XMVex { OP_XMM_Vex, 0 }
 414 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 415 #define XMVexW { OP_XMM_VexW, 0 }
 416 #define XMVexI4 { OP_REG_VexI4, x_mode }
 417 #define PCLMUL { PCLMUL_Fixup, 0 }
 418 #define VZERO { VZERO_Fixup, 0 }
 419 #define VCMP { VCMP_Fixup, 0 }
 420 #define VPCMP { VPCMP_Fixup, 0 }
 421
 422 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 423 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 424
 425 #define XMask { OP_Mask, mask_mode }
 426 #define MaskG { OP_G, mask_mode }
 427 #define MaskE { OP_E, mask_mode }
 428 #define MaskR { OP_R, mask_mode }
 429 #define MaskVex { OP_VEX, mask_mode }
 430
 431 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 432 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 433
 434 /* Used handle "rep" prefix for string instructions.  */
 435 #define Xbr { REP_Fixup, eSI_reg }
 436 #define Xvr { REP_Fixup, eSI_reg }
 437 #define Ybr { REP_Fixup, eDI_reg }
 438 #define Yvr { REP_Fixup, eDI_reg }
 439 #define Yzr { REP_Fixup, eDI_reg }
 440 #define indirDXr { REP_Fixup, indir_dx_reg }
 441 #define ALr { REP_Fixup, al_reg }
 442 #define eAXr { REP_Fixup, eAX_reg }
 443
 444 /* Used handle HLE prefix for lockable instructions.  */
 445 #define Ebh1 { HLE_Fixup1, b_mode }
 446 #define Evh1 { HLE_Fixup1, v_mode }
 447 #define Ebh2 { HLE_Fixup2, b_mode }
 448 #define Evh2 { HLE_Fixup2, v_mode }
 449 #define Ebh3 { HLE_Fixup3, b_mode }
 450 #define Evh3 { HLE_Fixup3, v_mode }
 451
 452 #define BND { BND_Fixup, 0 }
 453
 454 #define cond_jump_flag { NULL, cond_jump_mode }
 455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 456
 457 /* bits in sizeflag */
 458 #define SUFFIX_ALWAYS 4
 459 #define AFLAG 2
 460 #define DFLAG 1
 461
 462 enum
 463 {
 464   /* byte operand */
 465   b_mode = 1,
 466   /* byte operand with operand swapped */
 467   b_swap_mode,
 468   /* byte operand, sign extend like 'T' suffix */
 469   b_T_mode,
 470   /* operand size depends on prefixes */
 471   v_mode,
 472   /* operand size depends on prefixes with operand swapped */
 473   v_swap_mode,
 474   /* word operand */
 475   w_mode,
 476   /* double word operand  */
 477   d_mode,
 478   /* double word operand with operand swapped */
 479   d_swap_mode,
 480   /* quad word operand */
 481   q_mode,
 482   /* quad word operand with operand swapped */
 483   q_swap_mode,
 484   /* ten-byte operand */
 485   t_mode,
 486   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 487      broadcast enabled.  */
 488   x_mode,
 489   /* Similar to x_mode, but with different EVEX mem shifts.  */
 490   evex_x_gscat_mode,
 491   /* Similar to x_mode, but with disabled broadcast.  */
 492   evex_x_nobcst_mode,
 493   /* Similar to x_mode, but with operands swapped and disabled broadcast
 494      in EVEX.  */
 495   x_swap_mode,
 496   /* 16-byte XMM operand */
 497   xmm_mode,
 498   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 499      memory operand (depending on vector length).  Broadcast isn't
 500      allowed.  */
 501   xmmq_mode,
 502   /* Same as xmmq_mode, but broadcast is allowed.  */
 503   evex_half_bcst_xmmq_mode,
 504   /* XMM register or byte memory operand */
 505   xmm_mb_mode,
 506   /* XMM register or word memory operand */
 507   xmm_mw_mode,
 508   /* XMM register or double word memory operand */
 509   xmm_md_mode,
 510   /* XMM register or quad word memory operand */
 511   xmm_mq_mode,
 512   /* XMM register or double/quad word memory operand, depending on
 513      VEX.W.  */
 514   xmm_mdq_mode,
 515   /* 16-byte XMM, word, double word or quad word operand.  */
 516   xmmdw_mode,
 517   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 518   xmmqd_mode,
 519   /* 32-byte YMM operand */
 520   ymm_mode,
 521   /* quad word, ymmword or zmmword memory operand.  */
 522   ymmq_mode,
 523   /* 32-byte YMM or 16-byte word operand */
 524   ymmxmm_mode,
 525   /* d_mode in 32bit, q_mode in 64bit mode.  */
 526   m_mode,
 527   /* pair of v_mode operands */
 528   a_mode,
 529   cond_jump_mode,
 530   loop_jcxz_mode,
 531   v_bnd_mode,
 532   /* operand size depends on REX prefixes.  */
 533   dq_mode,
 534   /* registers like dq_mode, memory like w_mode.  */
 535   dqw_mode,
 536   bnd_mode,
 537   /* 4- or 6-byte pointer operand */
 538   f_mode,
 539   const_1_mode,
 540   /* v_mode for stack-related opcodes.  */
 541   stack_v_mode,
 542   /* non-quad operand size depends on prefixes */
 543   z_mode,
 544   /* 16-byte operand */
 545   o_mode,
 546   /* registers like dq_mode, memory like b_mode.  */
 547   dqb_mode,
 548   /* registers like dq_mode, memory like d_mode.  */
 549   dqd_mode,
 550   /* normal vex mode */
 551   vex_mode,
 552   /* 128bit vex mode */
 553   vex128_mode,
 554   /* 256bit vex mode */
 555   vex256_mode,
 556   /* operand size depends on the VEX.W bit.  */
 557   vex_w_dq_mode,
 558
 559   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 560   vex_vsib_d_w_dq_mode,
 561   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 562   vex_vsib_q_w_dq_mode,
 563
 564   /* scalar, ignore vector length.  */
 565   scalar_mode,
 566   /* like d_mode, ignore vector length.  */
 567   d_scalar_mode,
 568   /* like d_swap_mode, ignore vector length.  */
 569   d_scalar_swap_mode,
 570   /* like q_mode, ignore vector length.  */
 571   q_scalar_mode,
 572   /* like q_swap_mode, ignore vector length.  */
 573   q_scalar_swap_mode,
 574   /* like vex_mode, ignore vector length.  */
 575   vex_scalar_mode,
 576   /* like vex_w_dq_mode, ignore vector length.  */
 577   vex_scalar_w_dq_mode,
 578
 579   /* Static rounding.  */
 580   evex_rounding_mode,
 581   /* Supress all exceptions.  */
 582   evex_sae_mode,
 583
 584   /* Mask register operand.  */
 585   mask_mode,
 586
 587   es_reg,
 588   cs_reg,
 589   ss_reg,
 590   ds_reg,
 591   fs_reg,
 592   gs_reg,
 593
 594   eAX_reg,
 595   eCX_reg,
 596   eDX_reg,
 597   eBX_reg,
 598   eSP_reg,
 599   eBP_reg,
 600   eSI_reg,
 601   eDI_reg,
 602
 603   al_reg,
 604   cl_reg,
 605   dl_reg,
 606   bl_reg,
 607   ah_reg,
 608   ch_reg,
 609   dh_reg,
 610   bh_reg,
 611
 612   ax_reg,
 613   cx_reg,
 614   dx_reg,
 615   bx_reg,
 616   sp_reg,
 617   bp_reg,
 618   si_reg,
 619   di_reg,
 620
 621   rAX_reg,
 622   rCX_reg,
 623   rDX_reg,
 624   rBX_reg,
 625   rSP_reg,
 626   rBP_reg,
 627   rSI_reg,
 628   rDI_reg,
 629
 630   z_mode_ax_reg,
 631   indir_dx_reg
 632 };
 633
 634 enum
 635 {
 636   FLOATCODE = 1,
 637   USE_REG_TABLE,
 638   USE_MOD_TABLE,
 639   USE_RM_TABLE,
 640   USE_PREFIX_TABLE,
 641   USE_X86_64_TABLE,
 642   USE_3BYTE_TABLE,
 643   USE_XOP_8F_TABLE,
 644   USE_VEX_C4_TABLE,
 645   USE_VEX_C5_TABLE,
 646   USE_VEX_LEN_TABLE,
 647   USE_VEX_W_TABLE,
 648   USE_EVEX_TABLE
 649 };
 650
 651 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 652
 653 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 654 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 655 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 656 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 657 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 658 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 659 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 660 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 661 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 662 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 663 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 664 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 665 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 666
 667 enum
 668 {
 669   REG_80 = 0,
 670   REG_81,
 671   REG_82,
 672   REG_8F,
 673   REG_C0,
 674   REG_C1,
 675   REG_C6,
 676   REG_C7,
 677   REG_D0,
 678   REG_D1,
 679   REG_D2,
 680   REG_D3,
 681   REG_F6,
 682   REG_F7,
 683   REG_FE,
 684   REG_FF,
 685   REG_0F00,
 686   REG_0F01,
 687   REG_0F0D,
 688   REG_0F18,
 689   REG_0F71,
 690   REG_0F72,
 691   REG_0F73,
 692   REG_0FA6,
 693   REG_0FA7,
 694   REG_0FAE,
 695   REG_0FBA,
 696   REG_0FC7,
 697   REG_VEX_0F71,
 698   REG_VEX_0F72,
 699   REG_VEX_0F73,
 700   REG_VEX_0FAE,
 701   REG_VEX_0F38F3,
 702   REG_XOP_LWPCB,
 703   REG_XOP_LWP,
 704   REG_XOP_TBM_01,
 705   REG_XOP_TBM_02,
 706
 707   REG_EVEX_0F72,
 708   REG_EVEX_0F73,
 709   REG_EVEX_0F38C6,
 710   REG_EVEX_0F38C7
 711 };
 712
 713 enum
 714 {
 715   MOD_8D = 0,
 716   MOD_C6_REG_7,
 717   MOD_C7_REG_7,
 718   MOD_0F01_REG_0,
 719   MOD_0F01_REG_1,
 720   MOD_0F01_REG_2,
 721   MOD_0F01_REG_3,
 722   MOD_0F01_REG_7,
 723   MOD_0F12_PREFIX_0,
 724   MOD_0F13,
 725   MOD_0F16_PREFIX_0,
 726   MOD_0F17,
 727   MOD_0F18_REG_0,
 728   MOD_0F18_REG_1,
 729   MOD_0F18_REG_2,
 730   MOD_0F18_REG_3,
 731   MOD_0F18_REG_4,
 732   MOD_0F18_REG_5,
 733   MOD_0F18_REG_6,
 734   MOD_0F18_REG_7,
 735   MOD_0F1A_PREFIX_0,
 736   MOD_0F1B_PREFIX_0,
 737   MOD_0F1B_PREFIX_1,
 738   MOD_0F20,
 739   MOD_0F21,
 740   MOD_0F22,
 741   MOD_0F23,
 742   MOD_0F24,
 743   MOD_0F26,
 744   MOD_0F2B_PREFIX_0,
 745   MOD_0F2B_PREFIX_1,
 746   MOD_0F2B_PREFIX_2,
 747   MOD_0F2B_PREFIX_3,
 748   MOD_0F51,
 749   MOD_0F71_REG_2,
 750   MOD_0F71_REG_4,
 751   MOD_0F71_REG_6,
 752   MOD_0F72_REG_2,
 753   MOD_0F72_REG_4,
 754   MOD_0F72_REG_6,
 755   MOD_0F73_REG_2,
 756   MOD_0F73_REG_3,
 757   MOD_0F73_REG_6,
 758   MOD_0F73_REG_7,
 759   MOD_0FAE_REG_0,
 760   MOD_0FAE_REG_1,
 761   MOD_0FAE_REG_2,
 762   MOD_0FAE_REG_3,
 763   MOD_0FAE_REG_4,
 764   MOD_0FAE_REG_5,
 765   MOD_0FAE_REG_6,
 766   MOD_0FAE_REG_7,
 767   MOD_0FB2,
 768   MOD_0FB4,
 769   MOD_0FB5,
 770   MOD_0FC7_REG_6,
 771   MOD_0FC7_REG_7,
 772   MOD_0FD7,
 773   MOD_0FE7_PREFIX_2,
 774   MOD_0FF0_PREFIX_3,
 775   MOD_0F382A_PREFIX_2,
 776   MOD_62_32BIT,
 777   MOD_C4_32BIT,
 778   MOD_C5_32BIT,
 779   MOD_VEX_0F12_PREFIX_0,
 780   MOD_VEX_0F13,
 781   MOD_VEX_0F16_PREFIX_0,
 782   MOD_VEX_0F17,
 783   MOD_VEX_0F2B,
 784   MOD_VEX_0F50,
 785   MOD_VEX_0F71_REG_2,
 786   MOD_VEX_0F71_REG_4,
 787   MOD_VEX_0F71_REG_6,
 788   MOD_VEX_0F72_REG_2,
 789   MOD_VEX_0F72_REG_4,
 790   MOD_VEX_0F72_REG_6,
 791   MOD_VEX_0F73_REG_2,
 792   MOD_VEX_0F73_REG_3,
 793   MOD_VEX_0F73_REG_6,
 794   MOD_VEX_0F73_REG_7,
 795   MOD_VEX_0FAE_REG_2,
 796   MOD_VEX_0FAE_REG_3,
 797   MOD_VEX_0FD7_PREFIX_2,
 798   MOD_VEX_0FE7_PREFIX_2,
 799   MOD_VEX_0FF0_PREFIX_3,
 800   MOD_VEX_0F381A_PREFIX_2,
 801   MOD_VEX_0F382A_PREFIX_2,
 802   MOD_VEX_0F382C_PREFIX_2,
 803   MOD_VEX_0F382D_PREFIX_2,
 804   MOD_VEX_0F382E_PREFIX_2,
 805   MOD_VEX_0F382F_PREFIX_2,
 806   MOD_VEX_0F385A_PREFIX_2,
 807   MOD_VEX_0F388C_PREFIX_2,
 808   MOD_VEX_0F388E_PREFIX_2,
 809
 810   MOD_EVEX_0F10_PREFIX_1,
 811   MOD_EVEX_0F10_PREFIX_3,
 812   MOD_EVEX_0F11_PREFIX_1,
 813   MOD_EVEX_0F11_PREFIX_3,
 814   MOD_EVEX_0F12_PREFIX_0,
 815   MOD_EVEX_0F16_PREFIX_0,
 816   MOD_EVEX_0F38C6_REG_1,
 817   MOD_EVEX_0F38C6_REG_2,
 818   MOD_EVEX_0F38C6_REG_5,
 819   MOD_EVEX_0F38C6_REG_6,
 820   MOD_EVEX_0F38C7_REG_1,
 821   MOD_EVEX_0F38C7_REG_2,
 822   MOD_EVEX_0F38C7_REG_5,
 823   MOD_EVEX_0F38C7_REG_6
 824 };
 825
 826 enum
 827 {
 828   RM_C6_REG_7 = 0,
 829   RM_C7_REG_7,
 830   RM_0F01_REG_0,
 831   RM_0F01_REG_1,
 832   RM_0F01_REG_2,
 833   RM_0F01_REG_3,
 834   RM_0F01_REG_7,
 835   RM_0FAE_REG_5,
 836   RM_0FAE_REG_6,
 837   RM_0FAE_REG_7
 838 };
 839
 840 enum
 841 {
 842   PREFIX_90 = 0,
 843   PREFIX_0F10,
 844   PREFIX_0F11,
 845   PREFIX_0F12,
 846   PREFIX_0F16,
 847   PREFIX_0F1A,
 848   PREFIX_0F1B,
 849   PREFIX_0F2A,
 850   PREFIX_0F2B,
 851   PREFIX_0F2C,
 852   PREFIX_0F2D,
 853   PREFIX_0F2E,
 854   PREFIX_0F2F,
 855   PREFIX_0F51,
 856   PREFIX_0F52,
 857   PREFIX_0F53,
 858   PREFIX_0F58,
 859   PREFIX_0F59,
 860   PREFIX_0F5A,
 861   PREFIX_0F5B,
 862   PREFIX_0F5C,
 863   PREFIX_0F5D,
 864   PREFIX_0F5E,
 865   PREFIX_0F5F,
 866   PREFIX_0F60,
 867   PREFIX_0F61,
 868   PREFIX_0F62,
 869   PREFIX_0F6C,
 870   PREFIX_0F6D,
 871   PREFIX_0F6F,
 872   PREFIX_0F70,
 873   PREFIX_0F73_REG_3,
 874   PREFIX_0F73_REG_7,
 875   PREFIX_0F78,
 876   PREFIX_0F79,
 877   PREFIX_0F7C,
 878   PREFIX_0F7D,
 879   PREFIX_0F7E,
 880   PREFIX_0F7F,
 881   PREFIX_0FAE_REG_0,
 882   PREFIX_0FAE_REG_1,
 883   PREFIX_0FAE_REG_2,
 884   PREFIX_0FAE_REG_3,
 885   PREFIX_0FB8,
 886   PREFIX_0FBC,
 887   PREFIX_0FBD,
 888   PREFIX_0FC2,
 889   PREFIX_0FC3,
 890   PREFIX_0FC7_REG_6,
 891   PREFIX_0FD0,
 892   PREFIX_0FD6,
 893   PREFIX_0FE6,
 894   PREFIX_0FE7,
 895   PREFIX_0FF0,
 896   PREFIX_0FF7,
 897   PREFIX_0F3810,
 898   PREFIX_0F3814,
 899   PREFIX_0F3815,
 900   PREFIX_0F3817,
 901   PREFIX_0F3820,
 902   PREFIX_0F3821,
 903   PREFIX_0F3822,
 904   PREFIX_0F3823,
 905   PREFIX_0F3824,
 906   PREFIX_0F3825,
 907   PREFIX_0F3828,
 908   PREFIX_0F3829,
 909   PREFIX_0F382A,
 910   PREFIX_0F382B,
 911   PREFIX_0F3830,
 912   PREFIX_0F3831,
 913   PREFIX_0F3832,
 914   PREFIX_0F3833,
 915   PREFIX_0F3834,
 916   PREFIX_0F3835,
 917   PREFIX_0F3837,
 918   PREFIX_0F3838,
 919   PREFIX_0F3839,
 920   PREFIX_0F383A,
 921   PREFIX_0F383B,
 922   PREFIX_0F383C,
 923   PREFIX_0F383D,
 924   PREFIX_0F383E,
 925   PREFIX_0F383F,
 926   PREFIX_0F3840,
 927   PREFIX_0F3841,
 928   PREFIX_0F3880,
 929   PREFIX_0F3881,
 930   PREFIX_0F3882,
 931   PREFIX_0F38C8,
 932   PREFIX_0F38C9,
 933   PREFIX_0F38CA,
 934   PREFIX_0F38CB,
 935   PREFIX_0F38CC,
 936   PREFIX_0F38CD,
 937   PREFIX_0F38DB,
 938   PREFIX_0F38DC,
 939   PREFIX_0F38DD,
 940   PREFIX_0F38DE,
 941   PREFIX_0F38DF,
 942   PREFIX_0F38F0,
 943   PREFIX_0F38F1,
 944   PREFIX_0F38F6,
 945   PREFIX_0F3A08,
 946   PREFIX_0F3A09,
 947   PREFIX_0F3A0A,
 948   PREFIX_0F3A0B,
 949   PREFIX_0F3A0C,
 950   PREFIX_0F3A0D,
 951   PREFIX_0F3A0E,
 952   PREFIX_0F3A14,
 953   PREFIX_0F3A15,
 954   PREFIX_0F3A16,
 955   PREFIX_0F3A17,
 956   PREFIX_0F3A20,
 957   PREFIX_0F3A21,
 958   PREFIX_0F3A22,
 959   PREFIX_0F3A40,
 960   PREFIX_0F3A41,
 961   PREFIX_0F3A42,
 962   PREFIX_0F3A44,
 963   PREFIX_0F3A60,
 964   PREFIX_0F3A61,
 965   PREFIX_0F3A62,
 966   PREFIX_0F3A63,
 967   PREFIX_0F3ACC,
 968   PREFIX_0F3ADF,
 969   PREFIX_VEX_0F10,
 970   PREFIX_VEX_0F11,
 971   PREFIX_VEX_0F12,
 972   PREFIX_VEX_0F16,
 973   PREFIX_VEX_0F2A,
 974   PREFIX_VEX_0F2C,
 975   PREFIX_VEX_0F2D,
 976   PREFIX_VEX_0F2E,
 977   PREFIX_VEX_0F2F,
 978   PREFIX_VEX_0F41,
 979   PREFIX_VEX_0F42,
 980   PREFIX_VEX_0F44,
 981   PREFIX_VEX_0F45,
 982   PREFIX_VEX_0F46,
 983   PREFIX_VEX_0F47,
 984   PREFIX_VEX_0F4B,
 985   PREFIX_VEX_0F51,
 986   PREFIX_VEX_0F52,
 987   PREFIX_VEX_0F53,
 988   PREFIX_VEX_0F58,
 989   PREFIX_VEX_0F59,
 990   PREFIX_VEX_0F5A,
 991   PREFIX_VEX_0F5B,
 992   PREFIX_VEX_0F5C,
 993   PREFIX_VEX_0F5D,
 994   PREFIX_VEX_0F5E,
 995   PREFIX_VEX_0F5F,
 996   PREFIX_VEX_0F60,
 997   PREFIX_VEX_0F61,
 998   PREFIX_VEX_0F62,
 999   PREFIX_VEX_0F63,
1000   PREFIX_VEX_0F64,
1001   PREFIX_VEX_0F65,
1002   PREFIX_VEX_0F66,
1003   PREFIX_VEX_0F67,
1004   PREFIX_VEX_0F68,
1005   PREFIX_VEX_0F69,
1006   PREFIX_VEX_0F6A,
1007   PREFIX_VEX_0F6B,
1008   PREFIX_VEX_0F6C,
1009   PREFIX_VEX_0F6D,
1010   PREFIX_VEX_0F6E,
1011   PREFIX_VEX_0F6F,
1012   PREFIX_VEX_0F70,
1013   PREFIX_VEX_0F71_REG_2,
1014   PREFIX_VEX_0F71_REG_4,
1015   PREFIX_VEX_0F71_REG_6,
1016   PREFIX_VEX_0F72_REG_2,
1017   PREFIX_VEX_0F72_REG_4,
1018   PREFIX_VEX_0F72_REG_6,
1019   PREFIX_VEX_0F73_REG_2,
1020   PREFIX_VEX_0F73_REG_3,
1021   PREFIX_VEX_0F73_REG_6,
1022   PREFIX_VEX_0F73_REG_7,
1023   PREFIX_VEX_0F74,
1024   PREFIX_VEX_0F75,
1025   PREFIX_VEX_0F76,
1026   PREFIX_VEX_0F77,
1027   PREFIX_VEX_0F7C,
1028   PREFIX_VEX_0F7D,
1029   PREFIX_VEX_0F7E,
1030   PREFIX_VEX_0F7F,
1031   PREFIX_VEX_0F90,
1032   PREFIX_VEX_0F91,
1033   PREFIX_VEX_0F92,
1034   PREFIX_VEX_0F93,
1035   PREFIX_VEX_0F98,
1036   PREFIX_VEX_0FC2,
1037   PREFIX_VEX_0FC4,
1038   PREFIX_VEX_0FC5,
1039   PREFIX_VEX_0FD0,
1040   PREFIX_VEX_0FD1,
1041   PREFIX_VEX_0FD2,
1042   PREFIX_VEX_0FD3,
1043   PREFIX_VEX_0FD4,
1044   PREFIX_VEX_0FD5,
1045   PREFIX_VEX_0FD6,
1046   PREFIX_VEX_0FD7,
1047   PREFIX_VEX_0FD8,
1048   PREFIX_VEX_0FD9,
1049   PREFIX_VEX_0FDA,
1050   PREFIX_VEX_0FDB,
1051   PREFIX_VEX_0FDC,
1052   PREFIX_VEX_0FDD,
1053   PREFIX_VEX_0FDE,
1054   PREFIX_VEX_0FDF,
1055   PREFIX_VEX_0FE0,
1056   PREFIX_VEX_0FE1,
1057   PREFIX_VEX_0FE2,
1058   PREFIX_VEX_0FE3,
1059   PREFIX_VEX_0FE4,
1060   PREFIX_VEX_0FE5,
1061   PREFIX_VEX_0FE6,
1062   PREFIX_VEX_0FE7,
1063   PREFIX_VEX_0FE8,
1064   PREFIX_VEX_0FE9,
1065   PREFIX_VEX_0FEA,
1066   PREFIX_VEX_0FEB,
1067   PREFIX_VEX_0FEC,
1068   PREFIX_VEX_0FED,
1069   PREFIX_VEX_0FEE,
1070   PREFIX_VEX_0FEF,
1071   PREFIX_VEX_0FF0,
1072   PREFIX_VEX_0FF1,
1073   PREFIX_VEX_0FF2,
1074   PREFIX_VEX_0FF3,
1075   PREFIX_VEX_0FF4,
1076   PREFIX_VEX_0FF5,
1077   PREFIX_VEX_0FF6,
1078   PREFIX_VEX_0FF7,
1079   PREFIX_VEX_0FF8,
1080   PREFIX_VEX_0FF9,
1081   PREFIX_VEX_0FFA,
1082   PREFIX_VEX_0FFB,
1083   PREFIX_VEX_0FFC,
1084   PREFIX_VEX_0FFD,
1085   PREFIX_VEX_0FFE,
1086   PREFIX_VEX_0F3800,
1087   PREFIX_VEX_0F3801,
1088   PREFIX_VEX_0F3802,
1089   PREFIX_VEX_0F3803,
1090   PREFIX_VEX_0F3804,
1091   PREFIX_VEX_0F3805,
1092   PREFIX_VEX_0F3806,
1093   PREFIX_VEX_0F3807,
1094   PREFIX_VEX_0F3808,
1095   PREFIX_VEX_0F3809,
1096   PREFIX_VEX_0F380A,
1097   PREFIX_VEX_0F380B,
1098   PREFIX_VEX_0F380C,
1099   PREFIX_VEX_0F380D,
1100   PREFIX_VEX_0F380E,
1101   PREFIX_VEX_0F380F,
1102   PREFIX_VEX_0F3813,
1103   PREFIX_VEX_0F3816,
1104   PREFIX_VEX_0F3817,
1105   PREFIX_VEX_0F3818,
1106   PREFIX_VEX_0F3819,
1107   PREFIX_VEX_0F381A,
1108   PREFIX_VEX_0F381C,
1109   PREFIX_VEX_0F381D,
1110   PREFIX_VEX_0F381E,
1111   PREFIX_VEX_0F3820,
1112   PREFIX_VEX_0F3821,
1113   PREFIX_VEX_0F3822,
1114   PREFIX_VEX_0F3823,
1115   PREFIX_VEX_0F3824,
1116   PREFIX_VEX_0F3825,
1117   PREFIX_VEX_0F3828,
1118   PREFIX_VEX_0F3829,
1119   PREFIX_VEX_0F382A,
1120   PREFIX_VEX_0F382B,
1121   PREFIX_VEX_0F382C,
1122   PREFIX_VEX_0F382D,
1123   PREFIX_VEX_0F382E,
1124   PREFIX_VEX_0F382F,
1125   PREFIX_VEX_0F3830,
1126   PREFIX_VEX_0F3831,
1127   PREFIX_VEX_0F3832,
1128   PREFIX_VEX_0F3833,
1129   PREFIX_VEX_0F3834,
1130   PREFIX_VEX_0F3835,
1131   PREFIX_VEX_0F3836,
1132   PREFIX_VEX_0F3837,
1133   PREFIX_VEX_0F3838,
1134   PREFIX_VEX_0F3839,
1135   PREFIX_VEX_0F383A,
1136   PREFIX_VEX_0F383B,
1137   PREFIX_VEX_0F383C,
1138   PREFIX_VEX_0F383D,
1139   PREFIX_VEX_0F383E,
1140   PREFIX_VEX_0F383F,
1141   PREFIX_VEX_0F3840,
1142   PREFIX_VEX_0F3841,
1143   PREFIX_VEX_0F3845,
1144   PREFIX_VEX_0F3846,
1145   PREFIX_VEX_0F3847,
1146   PREFIX_VEX_0F3858,
1147   PREFIX_VEX_0F3859,
1148   PREFIX_VEX_0F385A,
1149   PREFIX_VEX_0F3878,
1150   PREFIX_VEX_0F3879,
1151   PREFIX_VEX_0F388C,
1152   PREFIX_VEX_0F388E,
1153   PREFIX_VEX_0F3890,
1154   PREFIX_VEX_0F3891,
1155   PREFIX_VEX_0F3892,
1156   PREFIX_VEX_0F3893,
1157   PREFIX_VEX_0F3896,
1158   PREFIX_VEX_0F3897,
1159   PREFIX_VEX_0F3898,
1160   PREFIX_VEX_0F3899,
1161   PREFIX_VEX_0F389A,
1162   PREFIX_VEX_0F389B,
1163   PREFIX_VEX_0F389C,
1164   PREFIX_VEX_0F389D,
1165   PREFIX_VEX_0F389E,
1166   PREFIX_VEX_0F389F,
1167   PREFIX_VEX_0F38A6,
1168   PREFIX_VEX_0F38A7,
1169   PREFIX_VEX_0F38A8,
1170   PREFIX_VEX_0F38A9,
1171   PREFIX_VEX_0F38AA,
1172   PREFIX_VEX_0F38AB,
1173   PREFIX_VEX_0F38AC,
1174   PREFIX_VEX_0F38AD,
1175   PREFIX_VEX_0F38AE,
1176   PREFIX_VEX_0F38AF,
1177   PREFIX_VEX_0F38B6,
1178   PREFIX_VEX_0F38B7,
1179   PREFIX_VEX_0F38B8,
1180   PREFIX_VEX_0F38B9,
1181   PREFIX_VEX_0F38BA,
1182   PREFIX_VEX_0F38BB,
1183   PREFIX_VEX_0F38BC,
1184   PREFIX_VEX_0F38BD,
1185   PREFIX_VEX_0F38BE,
1186   PREFIX_VEX_0F38BF,
1187   PREFIX_VEX_0F38DB,
1188   PREFIX_VEX_0F38DC,
1189   PREFIX_VEX_0F38DD,
1190   PREFIX_VEX_0F38DE,
1191   PREFIX_VEX_0F38DF,
1192   PREFIX_VEX_0F38F2,
1193   PREFIX_VEX_0F38F3_REG_1,
1194   PREFIX_VEX_0F38F3_REG_2,
1195   PREFIX_VEX_0F38F3_REG_3,
1196   PREFIX_VEX_0F38F5,
1197   PREFIX_VEX_0F38F6,
1198   PREFIX_VEX_0F38F7,
1199   PREFIX_VEX_0F3A00,
1200   PREFIX_VEX_0F3A01,
1201   PREFIX_VEX_0F3A02,
1202   PREFIX_VEX_0F3A04,
1203   PREFIX_VEX_0F3A05,
1204   PREFIX_VEX_0F3A06,
1205   PREFIX_VEX_0F3A08,
1206   PREFIX_VEX_0F3A09,
1207   PREFIX_VEX_0F3A0A,
1208   PREFIX_VEX_0F3A0B,
1209   PREFIX_VEX_0F3A0C,
1210   PREFIX_VEX_0F3A0D,
1211   PREFIX_VEX_0F3A0E,
1212   PREFIX_VEX_0F3A0F,
1213   PREFIX_VEX_0F3A14,
1214   PREFIX_VEX_0F3A15,
1215   PREFIX_VEX_0F3A16,
1216   PREFIX_VEX_0F3A17,
1217   PREFIX_VEX_0F3A18,
1218   PREFIX_VEX_0F3A19,
1219   PREFIX_VEX_0F3A1D,
1220   PREFIX_VEX_0F3A20,
1221   PREFIX_VEX_0F3A21,
1222   PREFIX_VEX_0F3A22,
1223   PREFIX_VEX_0F3A30,
1224   PREFIX_VEX_0F3A32,
1225   PREFIX_VEX_0F3A38,
1226   PREFIX_VEX_0F3A39,
1227   PREFIX_VEX_0F3A40,
1228   PREFIX_VEX_0F3A41,
1229   PREFIX_VEX_0F3A42,
1230   PREFIX_VEX_0F3A44,
1231   PREFIX_VEX_0F3A46,
1232   PREFIX_VEX_0F3A48,
1233   PREFIX_VEX_0F3A49,
1234   PREFIX_VEX_0F3A4A,
1235   PREFIX_VEX_0F3A4B,
1236   PREFIX_VEX_0F3A4C,
1237   PREFIX_VEX_0F3A5C,
1238   PREFIX_VEX_0F3A5D,
1239   PREFIX_VEX_0F3A5E,
1240   PREFIX_VEX_0F3A5F,
1241   PREFIX_VEX_0F3A60,
1242   PREFIX_VEX_0F3A61,
1243   PREFIX_VEX_0F3A62,
1244   PREFIX_VEX_0F3A63,
1245   PREFIX_VEX_0F3A68,
1246   PREFIX_VEX_0F3A69,
1247   PREFIX_VEX_0F3A6A,
1248   PREFIX_VEX_0F3A6B,
1249   PREFIX_VEX_0F3A6C,
1250   PREFIX_VEX_0F3A6D,
1251   PREFIX_VEX_0F3A6E,
1252   PREFIX_VEX_0F3A6F,
1253   PREFIX_VEX_0F3A78,
1254   PREFIX_VEX_0F3A79,
1255   PREFIX_VEX_0F3A7A,
1256   PREFIX_VEX_0F3A7B,
1257   PREFIX_VEX_0F3A7C,
1258   PREFIX_VEX_0F3A7D,
1259   PREFIX_VEX_0F3A7E,
1260   PREFIX_VEX_0F3A7F,
1261   PREFIX_VEX_0F3ADF,
1262   PREFIX_VEX_0F3AF0,
1263
1264   PREFIX_EVEX_0F10,
1265   PREFIX_EVEX_0F11,
1266   PREFIX_EVEX_0F12,
1267   PREFIX_EVEX_0F13,
1268   PREFIX_EVEX_0F14,
1269   PREFIX_EVEX_0F15,
1270   PREFIX_EVEX_0F16,
1271   PREFIX_EVEX_0F17,
1272   PREFIX_EVEX_0F28,
1273   PREFIX_EVEX_0F29,
1274   PREFIX_EVEX_0F2A,
1275   PREFIX_EVEX_0F2B,
1276   PREFIX_EVEX_0F2C,
1277   PREFIX_EVEX_0F2D,
1278   PREFIX_EVEX_0F2E,
1279   PREFIX_EVEX_0F2F,
1280   PREFIX_EVEX_0F51,
1281   PREFIX_EVEX_0F58,
1282   PREFIX_EVEX_0F59,
1283   PREFIX_EVEX_0F5A,
1284   PREFIX_EVEX_0F5B,
1285   PREFIX_EVEX_0F5C,
1286   PREFIX_EVEX_0F5D,
1287   PREFIX_EVEX_0F5E,
1288   PREFIX_EVEX_0F5F,
1289   PREFIX_EVEX_0F62,
1290   PREFIX_EVEX_0F66,
1291   PREFIX_EVEX_0F6A,
1292   PREFIX_EVEX_0F6C,
1293   PREFIX_EVEX_0F6D,
1294   PREFIX_EVEX_0F6E,
1295   PREFIX_EVEX_0F6F,
1296   PREFIX_EVEX_0F70,
1297   PREFIX_EVEX_0F72_REG_0,
1298   PREFIX_EVEX_0F72_REG_1,
1299   PREFIX_EVEX_0F72_REG_2,
1300   PREFIX_EVEX_0F72_REG_4,
1301   PREFIX_EVEX_0F72_REG_6,
1302   PREFIX_EVEX_0F73_REG_2,
1303   PREFIX_EVEX_0F73_REG_6,
1304   PREFIX_EVEX_0F76,
1305   PREFIX_EVEX_0F78,
1306   PREFIX_EVEX_0F79,
1307   PREFIX_EVEX_0F7A,
1308   PREFIX_EVEX_0F7B,
1309   PREFIX_EVEX_0F7E,
1310   PREFIX_EVEX_0F7F,
1311   PREFIX_EVEX_0FC2,
1312   PREFIX_EVEX_0FC6,
1313   PREFIX_EVEX_0FD2,
1314   PREFIX_EVEX_0FD3,
1315   PREFIX_EVEX_0FD4,
1316   PREFIX_EVEX_0FD6,
1317   PREFIX_EVEX_0FDB,
1318   PREFIX_EVEX_0FDF,
1319   PREFIX_EVEX_0FE2,
1320   PREFIX_EVEX_0FE6,
1321   PREFIX_EVEX_0FE7,
1322   PREFIX_EVEX_0FEB,
1323   PREFIX_EVEX_0FEF,
1324   PREFIX_EVEX_0FF2,
1325   PREFIX_EVEX_0FF3,
1326   PREFIX_EVEX_0FF4,
1327   PREFIX_EVEX_0FFA,
1328   PREFIX_EVEX_0FFB,
1329   PREFIX_EVEX_0FFE,
1330   PREFIX_EVEX_0F380C,
1331   PREFIX_EVEX_0F380D,
1332   PREFIX_EVEX_0F3811,
1333   PREFIX_EVEX_0F3812,
1334   PREFIX_EVEX_0F3813,
1335   PREFIX_EVEX_0F3814,
1336   PREFIX_EVEX_0F3815,
1337   PREFIX_EVEX_0F3816,
1338   PREFIX_EVEX_0F3818,
1339   PREFIX_EVEX_0F3819,
1340   PREFIX_EVEX_0F381A,
1341   PREFIX_EVEX_0F381B,
1342   PREFIX_EVEX_0F381E,
1343   PREFIX_EVEX_0F381F,
1344   PREFIX_EVEX_0F3821,
1345   PREFIX_EVEX_0F3822,
1346   PREFIX_EVEX_0F3823,
1347   PREFIX_EVEX_0F3824,
1348   PREFIX_EVEX_0F3825,
1349   PREFIX_EVEX_0F3827,
1350   PREFIX_EVEX_0F3828,
1351   PREFIX_EVEX_0F3829,
1352   PREFIX_EVEX_0F382A,
1353   PREFIX_EVEX_0F382C,
1354   PREFIX_EVEX_0F382D,
1355   PREFIX_EVEX_0F3831,
1356   PREFIX_EVEX_0F3832,
1357   PREFIX_EVEX_0F3833,
1358   PREFIX_EVEX_0F3834,
1359   PREFIX_EVEX_0F3835,
1360   PREFIX_EVEX_0F3836,
1361   PREFIX_EVEX_0F3837,
1362   PREFIX_EVEX_0F3839,
1363   PREFIX_EVEX_0F383A,
1364   PREFIX_EVEX_0F383B,
1365   PREFIX_EVEX_0F383D,
1366   PREFIX_EVEX_0F383F,
1367   PREFIX_EVEX_0F3840,
1368   PREFIX_EVEX_0F3842,
1369   PREFIX_EVEX_0F3843,
1370   PREFIX_EVEX_0F3844,
1371   PREFIX_EVEX_0F3845,
1372   PREFIX_EVEX_0F3846,
1373   PREFIX_EVEX_0F3847,
1374   PREFIX_EVEX_0F384C,
1375   PREFIX_EVEX_0F384D,
1376   PREFIX_EVEX_0F384E,
1377   PREFIX_EVEX_0F384F,
1378   PREFIX_EVEX_0F3858,
1379   PREFIX_EVEX_0F3859,
1380   PREFIX_EVEX_0F385A,
1381   PREFIX_EVEX_0F385B,
1382   PREFIX_EVEX_0F3864,
1383   PREFIX_EVEX_0F3865,
1384   PREFIX_EVEX_0F3876,
1385   PREFIX_EVEX_0F3877,
1386   PREFIX_EVEX_0F387C,
1387   PREFIX_EVEX_0F387E,
1388   PREFIX_EVEX_0F387F,
1389   PREFIX_EVEX_0F3888,
1390   PREFIX_EVEX_0F3889,
1391   PREFIX_EVEX_0F388A,
1392   PREFIX_EVEX_0F388B,
1393   PREFIX_EVEX_0F3890,
1394   PREFIX_EVEX_0F3891,
1395   PREFIX_EVEX_0F3892,
1396   PREFIX_EVEX_0F3893,
1397   PREFIX_EVEX_0F3896,
1398   PREFIX_EVEX_0F3897,
1399   PREFIX_EVEX_0F3898,
1400   PREFIX_EVEX_0F3899,
1401   PREFIX_EVEX_0F389A,
1402   PREFIX_EVEX_0F389B,
1403   PREFIX_EVEX_0F389C,
1404   PREFIX_EVEX_0F389D,
1405   PREFIX_EVEX_0F389E,
1406   PREFIX_EVEX_0F389F,
1407   PREFIX_EVEX_0F38A0,
1408   PREFIX_EVEX_0F38A1,
1409   PREFIX_EVEX_0F38A2,
1410   PREFIX_EVEX_0F38A3,
1411   PREFIX_EVEX_0F38A6,
1412   PREFIX_EVEX_0F38A7,
1413   PREFIX_EVEX_0F38A8,
1414   PREFIX_EVEX_0F38A9,
1415   PREFIX_EVEX_0F38AA,
1416   PREFIX_EVEX_0F38AB,
1417   PREFIX_EVEX_0F38AC,
1418   PREFIX_EVEX_0F38AD,
1419   PREFIX_EVEX_0F38AE,
1420   PREFIX_EVEX_0F38AF,
1421   PREFIX_EVEX_0F38B6,
1422   PREFIX_EVEX_0F38B7,
1423   PREFIX_EVEX_0F38B8,
1424   PREFIX_EVEX_0F38B9,
1425   PREFIX_EVEX_0F38BA,
1426   PREFIX_EVEX_0F38BB,
1427   PREFIX_EVEX_0F38BC,
1428   PREFIX_EVEX_0F38BD,
1429   PREFIX_EVEX_0F38BE,
1430   PREFIX_EVEX_0F38BF,
1431   PREFIX_EVEX_0F38C4,
1432   PREFIX_EVEX_0F38C6_REG_1,
1433   PREFIX_EVEX_0F38C6_REG_2,
1434   PREFIX_EVEX_0F38C6_REG_5,
1435   PREFIX_EVEX_0F38C6_REG_6,
1436   PREFIX_EVEX_0F38C7_REG_1,
1437   PREFIX_EVEX_0F38C7_REG_2,
1438   PREFIX_EVEX_0F38C7_REG_5,
1439   PREFIX_EVEX_0F38C7_REG_6,
1440   PREFIX_EVEX_0F38C8,
1441   PREFIX_EVEX_0F38CA,
1442   PREFIX_EVEX_0F38CB,
1443   PREFIX_EVEX_0F38CC,
1444   PREFIX_EVEX_0F38CD,
1445
1446   PREFIX_EVEX_0F3A00,
1447   PREFIX_EVEX_0F3A01,
1448   PREFIX_EVEX_0F3A03,
1449   PREFIX_EVEX_0F3A04,
1450   PREFIX_EVEX_0F3A05,
1451   PREFIX_EVEX_0F3A08,
1452   PREFIX_EVEX_0F3A09,
1453   PREFIX_EVEX_0F3A0A,
1454   PREFIX_EVEX_0F3A0B,
1455   PREFIX_EVEX_0F3A17,
1456   PREFIX_EVEX_0F3A18,
1457   PREFIX_EVEX_0F3A19,
1458   PREFIX_EVEX_0F3A1A,
1459   PREFIX_EVEX_0F3A1B,
1460   PREFIX_EVEX_0F3A1D,
1461   PREFIX_EVEX_0F3A1E,
1462   PREFIX_EVEX_0F3A1F,
1463   PREFIX_EVEX_0F3A21,
1464   PREFIX_EVEX_0F3A23,
1465   PREFIX_EVEX_0F3A25,
1466   PREFIX_EVEX_0F3A26,
1467   PREFIX_EVEX_0F3A27,
1468   PREFIX_EVEX_0F3A38,
1469   PREFIX_EVEX_0F3A39,
1470   PREFIX_EVEX_0F3A3A,
1471   PREFIX_EVEX_0F3A3B,
1472   PREFIX_EVEX_0F3A3E,
1473   PREFIX_EVEX_0F3A3F,
1474   PREFIX_EVEX_0F3A43,
1475   PREFIX_EVEX_0F3A54,
1476   PREFIX_EVEX_0F3A55,
1477 };
1478
1479 enum
1480 {
1481   X86_64_06 = 0,
1482   X86_64_07,
1483   X86_64_0D,
1484   X86_64_16,
1485   X86_64_17,
1486   X86_64_1E,
1487   X86_64_1F,
1488   X86_64_27,
1489   X86_64_2F,
1490   X86_64_37,
1491   X86_64_3F,
1492   X86_64_60,
1493   X86_64_61,
1494   X86_64_62,
1495   X86_64_63,
1496   X86_64_6D,
1497   X86_64_6F,
1498   X86_64_9A,
1499   X86_64_C4,
1500   X86_64_C5,
1501   X86_64_CE,
1502   X86_64_D4,
1503   X86_64_D5,
1504   X86_64_EA,
1505   X86_64_0F01_REG_0,
1506   X86_64_0F01_REG_1,
1507   X86_64_0F01_REG_2,
1508   X86_64_0F01_REG_3
1509 };
1510
1511 enum
1512 {
1513   THREE_BYTE_0F38 = 0,
1514   THREE_BYTE_0F3A,
1515   THREE_BYTE_0F7A
1516 };
1517
1518 enum
1519 {
1520   XOP_08 = 0,
1521   XOP_09,
1522   XOP_0A
1523 };
1524
1525 enum
1526 {
1527   VEX_0F = 0,
1528   VEX_0F38,
1529   VEX_0F3A
1530 };
1531
1532 enum
1533 {
1534   EVEX_0F = 0,
1535   EVEX_0F38,
1536   EVEX_0F3A
1537 };
1538
1539 enum
1540 {
1541   VEX_LEN_0F10_P_1 = 0,
1542   VEX_LEN_0F10_P_3,
1543   VEX_LEN_0F11_P_1,
1544   VEX_LEN_0F11_P_3,
1545   VEX_LEN_0F12_P_0_M_0,
1546   VEX_LEN_0F12_P_0_M_1,
1547   VEX_LEN_0F12_P_2,
1548   VEX_LEN_0F13_M_0,
1549   VEX_LEN_0F16_P_0_M_0,
1550   VEX_LEN_0F16_P_0_M_1,
1551   VEX_LEN_0F16_P_2,
1552   VEX_LEN_0F17_M_0,
1553   VEX_LEN_0F2A_P_1,
1554   VEX_LEN_0F2A_P_3,
1555   VEX_LEN_0F2C_P_1,
1556   VEX_LEN_0F2C_P_3,
1557   VEX_LEN_0F2D_P_1,
1558   VEX_LEN_0F2D_P_3,
1559   VEX_LEN_0F2E_P_0,
1560   VEX_LEN_0F2E_P_2,
1561   VEX_LEN_0F2F_P_0,
1562   VEX_LEN_0F2F_P_2,
1563   VEX_LEN_0F41_P_0,
1564   VEX_LEN_0F42_P_0,
1565   VEX_LEN_0F44_P_0,
1566   VEX_LEN_0F45_P_0,
1567   VEX_LEN_0F46_P_0,
1568   VEX_LEN_0F47_P_0,
1569   VEX_LEN_0F4B_P_2,
1570   VEX_LEN_0F51_P_1,
1571   VEX_LEN_0F51_P_3,
1572   VEX_LEN_0F52_P_1,
1573   VEX_LEN_0F53_P_1,
1574   VEX_LEN_0F58_P_1,
1575   VEX_LEN_0F58_P_3,
1576   VEX_LEN_0F59_P_1,
1577   VEX_LEN_0F59_P_3,
1578   VEX_LEN_0F5A_P_1,
1579   VEX_LEN_0F5A_P_3,
1580   VEX_LEN_0F5C_P_1,
1581   VEX_LEN_0F5C_P_3,
1582   VEX_LEN_0F5D_P_1,
1583   VEX_LEN_0F5D_P_3,
1584   VEX_LEN_0F5E_P_1,
1585   VEX_LEN_0F5E_P_3,
1586   VEX_LEN_0F5F_P_1,
1587   VEX_LEN_0F5F_P_3,
1588   VEX_LEN_0F6E_P_2,
1589   VEX_LEN_0F7E_P_1,
1590   VEX_LEN_0F7E_P_2,
1591   VEX_LEN_0F90_P_0,
1592   VEX_LEN_0F91_P_0,
1593   VEX_LEN_0F92_P_0,
1594   VEX_LEN_0F93_P_0,
1595   VEX_LEN_0F98_P_0,
1596   VEX_LEN_0FAE_R_2_M_0,
1597   VEX_LEN_0FAE_R_3_M_0,
1598   VEX_LEN_0FC2_P_1,
1599   VEX_LEN_0FC2_P_3,
1600   VEX_LEN_0FC4_P_2,
1601   VEX_LEN_0FC5_P_2,
1602   VEX_LEN_0FD6_P_2,
1603   VEX_LEN_0FF7_P_2,
1604   VEX_LEN_0F3816_P_2,
1605   VEX_LEN_0F3819_P_2,
1606   VEX_LEN_0F381A_P_2_M_0,
1607   VEX_LEN_0F3836_P_2,
1608   VEX_LEN_0F3841_P_2,
1609   VEX_LEN_0F385A_P_2_M_0,
1610   VEX_LEN_0F38DB_P_2,
1611   VEX_LEN_0F38DC_P_2,
1612   VEX_LEN_0F38DD_P_2,
1613   VEX_LEN_0F38DE_P_2,
1614   VEX_LEN_0F38DF_P_2,
1615   VEX_LEN_0F38F2_P_0,
1616   VEX_LEN_0F38F3_R_1_P_0,
1617   VEX_LEN_0F38F3_R_2_P_0,
1618   VEX_LEN_0F38F3_R_3_P_0,
1619   VEX_LEN_0F38F5_P_0,
1620   VEX_LEN_0F38F5_P_1,
1621   VEX_LEN_0F38F5_P_3,
1622   VEX_LEN_0F38F6_P_3,
1623   VEX_LEN_0F38F7_P_0,
1624   VEX_LEN_0F38F7_P_1,
1625   VEX_LEN_0F38F7_P_2,
1626   VEX_LEN_0F38F7_P_3,
1627   VEX_LEN_0F3A00_P_2,
1628   VEX_LEN_0F3A01_P_2,
1629   VEX_LEN_0F3A06_P_2,
1630   VEX_LEN_0F3A0A_P_2,
1631   VEX_LEN_0F3A0B_P_2,
1632   VEX_LEN_0F3A14_P_2,
1633   VEX_LEN_0F3A15_P_2,
1634   VEX_LEN_0F3A16_P_2,
1635   VEX_LEN_0F3A17_P_2,
1636   VEX_LEN_0F3A18_P_2,
1637   VEX_LEN_0F3A19_P_2,
1638   VEX_LEN_0F3A20_P_2,
1639   VEX_LEN_0F3A21_P_2,
1640   VEX_LEN_0F3A22_P_2,
1641   VEX_LEN_0F3A30_P_2,
1642   VEX_LEN_0F3A32_P_2,
1643   VEX_LEN_0F3A38_P_2,
1644   VEX_LEN_0F3A39_P_2,
1645   VEX_LEN_0F3A41_P_2,
1646   VEX_LEN_0F3A44_P_2,
1647   VEX_LEN_0F3A46_P_2,
1648   VEX_LEN_0F3A60_P_2,
1649   VEX_LEN_0F3A61_P_2,
1650   VEX_LEN_0F3A62_P_2,
1651   VEX_LEN_0F3A63_P_2,
1652   VEX_LEN_0F3A6A_P_2,
1653   VEX_LEN_0F3A6B_P_2,
1654   VEX_LEN_0F3A6E_P_2,
1655   VEX_LEN_0F3A6F_P_2,
1656   VEX_LEN_0F3A7A_P_2,
1657   VEX_LEN_0F3A7B_P_2,
1658   VEX_LEN_0F3A7E_P_2,
1659   VEX_LEN_0F3A7F_P_2,
1660   VEX_LEN_0F3ADF_P_2,
1661   VEX_LEN_0F3AF0_P_3,
1662   VEX_LEN_0FXOP_08_CC,
1663   VEX_LEN_0FXOP_08_CD,
1664   VEX_LEN_0FXOP_08_CE,
1665   VEX_LEN_0FXOP_08_CF,
1666   VEX_LEN_0FXOP_08_EC,
1667   VEX_LEN_0FXOP_08_ED,
1668   VEX_LEN_0FXOP_08_EE,
1669   VEX_LEN_0FXOP_08_EF,
1670   VEX_LEN_0FXOP_09_80,
1671   VEX_LEN_0FXOP_09_81
1672 };
1673
1674 enum
1675 {
1676   VEX_W_0F10_P_0 = 0,
1677   VEX_W_0F10_P_1,
1678   VEX_W_0F10_P_2,
1679   VEX_W_0F10_P_3,
1680   VEX_W_0F11_P_0,
1681   VEX_W_0F11_P_1,
1682   VEX_W_0F11_P_2,
1683   VEX_W_0F11_P_3,
1684   VEX_W_0F12_P_0_M_0,
1685   VEX_W_0F12_P_0_M_1,
1686   VEX_W_0F12_P_1,
1687   VEX_W_0F12_P_2,
1688   VEX_W_0F12_P_3,
1689   VEX_W_0F13_M_0,
1690   VEX_W_0F14,
1691   VEX_W_0F15,
1692   VEX_W_0F16_P_0_M_0,
1693   VEX_W_0F16_P_0_M_1,
1694   VEX_W_0F16_P_1,
1695   VEX_W_0F16_P_2,
1696   VEX_W_0F17_M_0,
1697   VEX_W_0F28,
1698   VEX_W_0F29,
1699   VEX_W_0F2B_M_0,
1700   VEX_W_0F2E_P_0,
1701   VEX_W_0F2E_P_2,
1702   VEX_W_0F2F_P_0,
1703   VEX_W_0F2F_P_2,
1704   VEX_W_0F41_P_0_LEN_1,
1705   VEX_W_0F42_P_0_LEN_1,
1706   VEX_W_0F44_P_0_LEN_0,
1707   VEX_W_0F45_P_0_LEN_1,
1708   VEX_W_0F46_P_0_LEN_1,
1709   VEX_W_0F47_P_0_LEN_1,
1710   VEX_W_0F4B_P_2_LEN_1,
1711   VEX_W_0F50_M_0,
1712   VEX_W_0F51_P_0,
1713   VEX_W_0F51_P_1,
1714   VEX_W_0F51_P_2,
1715   VEX_W_0F51_P_3,
1716   VEX_W_0F52_P_0,
1717   VEX_W_0F52_P_1,
1718   VEX_W_0F53_P_0,
1719   VEX_W_0F53_P_1,
1720   VEX_W_0F58_P_0,
1721   VEX_W_0F58_P_1,
1722   VEX_W_0F58_P_2,
1723   VEX_W_0F58_P_3,
1724   VEX_W_0F59_P_0,
1725   VEX_W_0F59_P_1,
1726   VEX_W_0F59_P_2,
1727   VEX_W_0F59_P_3,
1728   VEX_W_0F5A_P_0,
1729   VEX_W_0F5A_P_1,
1730   VEX_W_0F5A_P_3,
1731   VEX_W_0F5B_P_0,
1732   VEX_W_0F5B_P_1,
1733   VEX_W_0F5B_P_2,
1734   VEX_W_0F5C_P_0,
1735   VEX_W_0F5C_P_1,
1736   VEX_W_0F5C_P_2,
1737   VEX_W_0F5C_P_3,
1738   VEX_W_0F5D_P_0,
1739   VEX_W_0F5D_P_1,
1740   VEX_W_0F5D_P_2,
1741   VEX_W_0F5D_P_3,
1742   VEX_W_0F5E_P_0,
1743   VEX_W_0F5E_P_1,
1744   VEX_W_0F5E_P_2,
1745   VEX_W_0F5E_P_3,
1746   VEX_W_0F5F_P_0,
1747   VEX_W_0F5F_P_1,
1748   VEX_W_0F5F_P_2,
1749   VEX_W_0F5F_P_3,
1750   VEX_W_0F60_P_2,
1751   VEX_W_0F61_P_2,
1752   VEX_W_0F62_P_2,
1753   VEX_W_0F63_P_2,
1754   VEX_W_0F64_P_2,
1755   VEX_W_0F65_P_2,
1756   VEX_W_0F66_P_2,
1757   VEX_W_0F67_P_2,
1758   VEX_W_0F68_P_2,
1759   VEX_W_0F69_P_2,
1760   VEX_W_0F6A_P_2,
1761   VEX_W_0F6B_P_2,
1762   VEX_W_0F6C_P_2,
1763   VEX_W_0F6D_P_2,
1764   VEX_W_0F6F_P_1,
1765   VEX_W_0F6F_P_2,
1766   VEX_W_0F70_P_1,
1767   VEX_W_0F70_P_2,
1768   VEX_W_0F70_P_3,
1769   VEX_W_0F71_R_2_P_2,
1770   VEX_W_0F71_R_4_P_2,
1771   VEX_W_0F71_R_6_P_2,
1772   VEX_W_0F72_R_2_P_2,
1773   VEX_W_0F72_R_4_P_2,
1774   VEX_W_0F72_R_6_P_2,
1775   VEX_W_0F73_R_2_P_2,
1776   VEX_W_0F73_R_3_P_2,
1777   VEX_W_0F73_R_6_P_2,
1778   VEX_W_0F73_R_7_P_2,
1779   VEX_W_0F74_P_2,
1780   VEX_W_0F75_P_2,
1781   VEX_W_0F76_P_2,
1782   VEX_W_0F77_P_0,
1783   VEX_W_0F7C_P_2,
1784   VEX_W_0F7C_P_3,
1785   VEX_W_0F7D_P_2,
1786   VEX_W_0F7D_P_3,
1787   VEX_W_0F7E_P_1,
1788   VEX_W_0F7F_P_1,
1789   VEX_W_0F7F_P_2,
1790   VEX_W_0F90_P_0_LEN_0,
1791   VEX_W_0F91_P_0_LEN_0,
1792   VEX_W_0F92_P_0_LEN_0,
1793   VEX_W_0F93_P_0_LEN_0,
1794   VEX_W_0F98_P_0_LEN_0,
1795   VEX_W_0FAE_R_2_M_0,
1796   VEX_W_0FAE_R_3_M_0,
1797   VEX_W_0FC2_P_0,
1798   VEX_W_0FC2_P_1,
1799   VEX_W_0FC2_P_2,
1800   VEX_W_0FC2_P_3,
1801   VEX_W_0FC4_P_2,
1802   VEX_W_0FC5_P_2,
1803   VEX_W_0FD0_P_2,
1804   VEX_W_0FD0_P_3,
1805   VEX_W_0FD1_P_2,
1806   VEX_W_0FD2_P_2,
1807   VEX_W_0FD3_P_2,
1808   VEX_W_0FD4_P_2,
1809   VEX_W_0FD5_P_2,
1810   VEX_W_0FD6_P_2,
1811   VEX_W_0FD7_P_2_M_1,
1812   VEX_W_0FD8_P_2,
1813   VEX_W_0FD9_P_2,
1814   VEX_W_0FDA_P_2,
1815   VEX_W_0FDB_P_2,
1816   VEX_W_0FDC_P_2,
1817   VEX_W_0FDD_P_2,
1818   VEX_W_0FDE_P_2,
1819   VEX_W_0FDF_P_2,
1820   VEX_W_0FE0_P_2,
1821   VEX_W_0FE1_P_2,
1822   VEX_W_0FE2_P_2,
1823   VEX_W_0FE3_P_2,
1824   VEX_W_0FE4_P_2,
1825   VEX_W_0FE5_P_2,
1826   VEX_W_0FE6_P_1,
1827   VEX_W_0FE6_P_2,
1828   VEX_W_0FE6_P_3,
1829   VEX_W_0FE7_P_2_M_0,
1830   VEX_W_0FE8_P_2,
1831   VEX_W_0FE9_P_2,
1832   VEX_W_0FEA_P_2,
1833   VEX_W_0FEB_P_2,
1834   VEX_W_0FEC_P_2,
1835   VEX_W_0FED_P_2,
1836   VEX_W_0FEE_P_2,
1837   VEX_W_0FEF_P_2,
1838   VEX_W_0FF0_P_3_M_0,
1839   VEX_W_0FF1_P_2,
1840   VEX_W_0FF2_P_2,
1841   VEX_W_0FF3_P_2,
1842   VEX_W_0FF4_P_2,
1843   VEX_W_0FF5_P_2,
1844   VEX_W_0FF6_P_2,
1845   VEX_W_0FF7_P_2,
1846   VEX_W_0FF8_P_2,
1847   VEX_W_0FF9_P_2,
1848   VEX_W_0FFA_P_2,
1849   VEX_W_0FFB_P_2,
1850   VEX_W_0FFC_P_2,
1851   VEX_W_0FFD_P_2,
1852   VEX_W_0FFE_P_2,
1853   VEX_W_0F3800_P_2,
1854   VEX_W_0F3801_P_2,
1855   VEX_W_0F3802_P_2,
1856   VEX_W_0F3803_P_2,
1857   VEX_W_0F3804_P_2,
1858   VEX_W_0F3805_P_2,
1859   VEX_W_0F3806_P_2,
1860   VEX_W_0F3807_P_2,
1861   VEX_W_0F3808_P_2,
1862   VEX_W_0F3809_P_2,
1863   VEX_W_0F380A_P_2,
1864   VEX_W_0F380B_P_2,
1865   VEX_W_0F380C_P_2,
1866   VEX_W_0F380D_P_2,
1867   VEX_W_0F380E_P_2,
1868   VEX_W_0F380F_P_2,
1869   VEX_W_0F3816_P_2,
1870   VEX_W_0F3817_P_2,
1871   VEX_W_0F3818_P_2,
1872   VEX_W_0F3819_P_2,
1873   VEX_W_0F381A_P_2_M_0,
1874   VEX_W_0F381C_P_2,
1875   VEX_W_0F381D_P_2,
1876   VEX_W_0F381E_P_2,
1877   VEX_W_0F3820_P_2,
1878   VEX_W_0F3821_P_2,
1879   VEX_W_0F3822_P_2,
1880   VEX_W_0F3823_P_2,
1881   VEX_W_0F3824_P_2,
1882   VEX_W_0F3825_P_2,
1883   VEX_W_0F3828_P_2,
1884   VEX_W_0F3829_P_2,
1885   VEX_W_0F382A_P_2_M_0,
1886   VEX_W_0F382B_P_2,
1887   VEX_W_0F382C_P_2_M_0,
1888   VEX_W_0F382D_P_2_M_0,
1889   VEX_W_0F382E_P_2_M_0,
1890   VEX_W_0F382F_P_2_M_0,
1891   VEX_W_0F3830_P_2,
1892   VEX_W_0F3831_P_2,
1893   VEX_W_0F3832_P_2,
1894   VEX_W_0F3833_P_2,
1895   VEX_W_0F3834_P_2,
1896   VEX_W_0F3835_P_2,
1897   VEX_W_0F3836_P_2,
1898   VEX_W_0F3837_P_2,
1899   VEX_W_0F3838_P_2,
1900   VEX_W_0F3839_P_2,
1901   VEX_W_0F383A_P_2,
1902   VEX_W_0F383B_P_2,
1903   VEX_W_0F383C_P_2,
1904   VEX_W_0F383D_P_2,
1905   VEX_W_0F383E_P_2,
1906   VEX_W_0F383F_P_2,
1907   VEX_W_0F3840_P_2,
1908   VEX_W_0F3841_P_2,
1909   VEX_W_0F3846_P_2,
1910   VEX_W_0F3858_P_2,
1911   VEX_W_0F3859_P_2,
1912   VEX_W_0F385A_P_2_M_0,
1913   VEX_W_0F3878_P_2,
1914   VEX_W_0F3879_P_2,
1915   VEX_W_0F38DB_P_2,
1916   VEX_W_0F38DC_P_2,
1917   VEX_W_0F38DD_P_2,
1918   VEX_W_0F38DE_P_2,
1919   VEX_W_0F38DF_P_2,
1920   VEX_W_0F3A00_P_2,
1921   VEX_W_0F3A01_P_2,
1922   VEX_W_0F3A02_P_2,
1923   VEX_W_0F3A04_P_2,
1924   VEX_W_0F3A05_P_2,
1925   VEX_W_0F3A06_P_2,
1926   VEX_W_0F3A08_P_2,
1927   VEX_W_0F3A09_P_2,
1928   VEX_W_0F3A0A_P_2,
1929   VEX_W_0F3A0B_P_2,
1930   VEX_W_0F3A0C_P_2,
1931   VEX_W_0F3A0D_P_2,
1932   VEX_W_0F3A0E_P_2,
1933   VEX_W_0F3A0F_P_2,
1934   VEX_W_0F3A14_P_2,
1935   VEX_W_0F3A15_P_2,
1936   VEX_W_0F3A18_P_2,
1937   VEX_W_0F3A19_P_2,
1938   VEX_W_0F3A20_P_2,
1939   VEX_W_0F3A21_P_2,
1940   VEX_W_0F3A30_P_2_LEN_0,
1941   VEX_W_0F3A32_P_2_LEN_0,
1942   VEX_W_0F3A38_P_2,
1943   VEX_W_0F3A39_P_2,
1944   VEX_W_0F3A40_P_2,
1945   VEX_W_0F3A41_P_2,
1946   VEX_W_0F3A42_P_2,
1947   VEX_W_0F3A44_P_2,
1948   VEX_W_0F3A46_P_2,
1949   VEX_W_0F3A48_P_2,
1950   VEX_W_0F3A49_P_2,
1951   VEX_W_0F3A4A_P_2,
1952   VEX_W_0F3A4B_P_2,
1953   VEX_W_0F3A4C_P_2,
1954   VEX_W_0F3A60_P_2,
1955   VEX_W_0F3A61_P_2,
1956   VEX_W_0F3A62_P_2,
1957   VEX_W_0F3A63_P_2,
1958   VEX_W_0F3ADF_P_2,
1959
1960   EVEX_W_0F10_P_0,
1961   EVEX_W_0F10_P_1_M_0,
1962   EVEX_W_0F10_P_1_M_1,
1963   EVEX_W_0F10_P_2,
1964   EVEX_W_0F10_P_3_M_0,
1965   EVEX_W_0F10_P_3_M_1,
1966   EVEX_W_0F11_P_0,
1967   EVEX_W_0F11_P_1_M_0,
1968   EVEX_W_0F11_P_1_M_1,
1969   EVEX_W_0F11_P_2,
1970   EVEX_W_0F11_P_3_M_0,
1971   EVEX_W_0F11_P_3_M_1,
1972   EVEX_W_0F12_P_0_M_0,
1973   EVEX_W_0F12_P_0_M_1,
1974   EVEX_W_0F12_P_1,
1975   EVEX_W_0F12_P_2,
1976   EVEX_W_0F12_P_3,
1977   EVEX_W_0F13_P_0,
1978   EVEX_W_0F13_P_2,
1979   EVEX_W_0F14_P_0,
1980   EVEX_W_0F14_P_2,
1981   EVEX_W_0F15_P_0,
1982   EVEX_W_0F15_P_2,
1983   EVEX_W_0F16_P_0_M_0,
1984   EVEX_W_0F16_P_0_M_1,
1985   EVEX_W_0F16_P_1,
1986   EVEX_W_0F16_P_2,
1987   EVEX_W_0F17_P_0,
1988   EVEX_W_0F17_P_2,
1989   EVEX_W_0F28_P_0,
1990   EVEX_W_0F28_P_2,
1991   EVEX_W_0F29_P_0,
1992   EVEX_W_0F29_P_2,
1993   EVEX_W_0F2A_P_1,
1994   EVEX_W_0F2A_P_3,
1995   EVEX_W_0F2B_P_0,
1996   EVEX_W_0F2B_P_2,
1997   EVEX_W_0F2E_P_0,
1998   EVEX_W_0F2E_P_2,
1999   EVEX_W_0F2F_P_0,
2000   EVEX_W_0F2F_P_2,
2001   EVEX_W_0F51_P_0,
2002   EVEX_W_0F51_P_1,
2003   EVEX_W_0F51_P_2,
2004   EVEX_W_0F51_P_3,
2005   EVEX_W_0F58_P_0,
2006   EVEX_W_0F58_P_1,
2007   EVEX_W_0F58_P_2,
2008   EVEX_W_0F58_P_3,
2009   EVEX_W_0F59_P_0,
2010   EVEX_W_0F59_P_1,
2011   EVEX_W_0F59_P_2,
2012   EVEX_W_0F59_P_3,
2013   EVEX_W_0F5A_P_0,
2014   EVEX_W_0F5A_P_1,
2015   EVEX_W_0F5A_P_2,
2016   EVEX_W_0F5A_P_3,
2017   EVEX_W_0F5B_P_0,
2018   EVEX_W_0F5B_P_1,
2019   EVEX_W_0F5B_P_2,
2020   EVEX_W_0F5C_P_0,
2021   EVEX_W_0F5C_P_1,
2022   EVEX_W_0F5C_P_2,
2023   EVEX_W_0F5C_P_3,
2024   EVEX_W_0F5D_P_0,
2025   EVEX_W_0F5D_P_1,
2026   EVEX_W_0F5D_P_2,
2027   EVEX_W_0F5D_P_3,
2028   EVEX_W_0F5E_P_0,
2029   EVEX_W_0F5E_P_1,
2030   EVEX_W_0F5E_P_2,
2031   EVEX_W_0F5E_P_3,
2032   EVEX_W_0F5F_P_0,
2033   EVEX_W_0F5F_P_1,
2034   EVEX_W_0F5F_P_2,
2035   EVEX_W_0F5F_P_3,
2036   EVEX_W_0F62_P_2,
2037   EVEX_W_0F66_P_2,
2038   EVEX_W_0F6A_P_2,
2039   EVEX_W_0F6C_P_2,
2040   EVEX_W_0F6D_P_2,
2041   EVEX_W_0F6E_P_2,
2042   EVEX_W_0F6F_P_1,
2043   EVEX_W_0F6F_P_2,
2044   EVEX_W_0F70_P_2,
2045   EVEX_W_0F72_R_2_P_2,
2046   EVEX_W_0F72_R_6_P_2,
2047   EVEX_W_0F73_R_2_P_2,
2048   EVEX_W_0F73_R_6_P_2,
2049   EVEX_W_0F76_P_2,
2050   EVEX_W_0F78_P_0,
2051   EVEX_W_0F79_P_0,
2052   EVEX_W_0F7A_P_1,
2053   EVEX_W_0F7A_P_3,
2054   EVEX_W_0F7B_P_1,
2055   EVEX_W_0F7B_P_3,
2056   EVEX_W_0F7E_P_1,
2057   EVEX_W_0F7E_P_2,
2058   EVEX_W_0F7F_P_1,
2059   EVEX_W_0F7F_P_2,
2060   EVEX_W_0FC2_P_0,
2061   EVEX_W_0FC2_P_1,
2062   EVEX_W_0FC2_P_2,
2063   EVEX_W_0FC2_P_3,
2064   EVEX_W_0FC6_P_0,
2065   EVEX_W_0FC6_P_2,
2066   EVEX_W_0FD2_P_2,
2067   EVEX_W_0FD3_P_2,
2068   EVEX_W_0FD4_P_2,
2069   EVEX_W_0FD6_P_2,
2070   EVEX_W_0FE6_P_1,
2071   EVEX_W_0FE6_P_2,
2072   EVEX_W_0FE6_P_3,
2073   EVEX_W_0FE7_P_2,
2074   EVEX_W_0FF2_P_2,
2075   EVEX_W_0FF3_P_2,
2076   EVEX_W_0FF4_P_2,
2077   EVEX_W_0FFA_P_2,
2078   EVEX_W_0FFB_P_2,
2079   EVEX_W_0FFE_P_2,
2080   EVEX_W_0F380C_P_2,
2081   EVEX_W_0F380D_P_2,
2082   EVEX_W_0F3811_P_1,
2083   EVEX_W_0F3812_P_1,
2084   EVEX_W_0F3813_P_1,
2085   EVEX_W_0F3813_P_2,
2086   EVEX_W_0F3814_P_1,
2087   EVEX_W_0F3815_P_1,
2088   EVEX_W_0F3818_P_2,
2089   EVEX_W_0F3819_P_2,
2090   EVEX_W_0F381A_P_2,
2091   EVEX_W_0F381B_P_2,
2092   EVEX_W_0F381E_P_2,
2093   EVEX_W_0F381F_P_2,
2094   EVEX_W_0F3821_P_1,
2095   EVEX_W_0F3822_P_1,
2096   EVEX_W_0F3823_P_1,
2097   EVEX_W_0F3824_P_1,
2098   EVEX_W_0F3825_P_1,
2099   EVEX_W_0F3825_P_2,
2100   EVEX_W_0F3828_P_2,
2101   EVEX_W_0F3829_P_2,
2102   EVEX_W_0F382A_P_1,
2103   EVEX_W_0F382A_P_2,
2104   EVEX_W_0F3831_P_1,
2105   EVEX_W_0F3832_P_1,
2106   EVEX_W_0F3833_P_1,
2107   EVEX_W_0F3834_P_1,
2108   EVEX_W_0F3835_P_1,
2109   EVEX_W_0F3835_P_2,
2110   EVEX_W_0F3837_P_2,
2111   EVEX_W_0F383A_P_1,
2112   EVEX_W_0F3840_P_2,
2113   EVEX_W_0F3858_P_2,
2114   EVEX_W_0F3859_P_2,
2115   EVEX_W_0F385A_P_2,
2116   EVEX_W_0F385B_P_2,
2117   EVEX_W_0F3891_P_2,
2118   EVEX_W_0F3893_P_2,
2119   EVEX_W_0F38A1_P_2,
2120   EVEX_W_0F38A3_P_2,
2121   EVEX_W_0F38C7_R_1_P_2,
2122   EVEX_W_0F38C7_R_2_P_2,
2123   EVEX_W_0F38C7_R_5_P_2,
2124   EVEX_W_0F38C7_R_6_P_2,
2125
2126   EVEX_W_0F3A00_P_2,
2127   EVEX_W_0F3A01_P_2,
2128   EVEX_W_0F3A04_P_2,
2129   EVEX_W_0F3A05_P_2,
2130   EVEX_W_0F3A08_P_2,
2131   EVEX_W_0F3A09_P_2,
2132   EVEX_W_0F3A0A_P_2,
2133   EVEX_W_0F3A0B_P_2,
2134   EVEX_W_0F3A18_P_2,
2135   EVEX_W_0F3A19_P_2,
2136   EVEX_W_0F3A1A_P_2,
2137   EVEX_W_0F3A1B_P_2,
2138   EVEX_W_0F3A1D_P_2,
2139   EVEX_W_0F3A21_P_2,
2140   EVEX_W_0F3A23_P_2,
2141   EVEX_W_0F3A38_P_2,
2142   EVEX_W_0F3A39_P_2,
2143   EVEX_W_0F3A3A_P_2,
2144   EVEX_W_0F3A3B_P_2,
2145   EVEX_W_0F3A43_P_2,
2146 };
2147
2148 typedef void (*op_rtn) (int bytemode, int sizeflag);
2149
2150 struct dis386 {
2151   const char *name;
2152   struct
2153     {
2154       op_rtn rtn;
2155       int bytemode;
2156     } op[MAX_OPERANDS];
2157 };
2158
2159 /* Upper case letters in the instruction names here are macros.
2160    'A' => print 'b' if no register operands or suffix_always is true
2161    'B' => print 'b' if suffix_always is true
2162    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2163           size prefix
2164    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2165           suffix_always is true
2166    'E' => print 'e' if 32-bit form of jcxz
2167    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2168    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2169    'H' => print ",pt" or ",pn" branch hint
2170    'I' => honor following macro letter even in Intel mode (implemented only
2171           for some of the macro letters)
2172    'J' => print 'l'
2173    'K' => print 'd' or 'q' if rex prefix is present.
2174    'L' => print 'l' if suffix_always is true
2175    'M' => print 'r' if intel_mnemonic is false.
2176    'N' => print 'n' if instruction has no wait "prefix"
2177    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2178    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2179           or suffix_always is true.  print 'q' if rex prefix is present.
2180    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2181           is true
2182    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2183    'S' => print 'w', 'l' or 'q' if suffix_always is true
2184    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2185    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2186    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2187    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2188    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2189    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2190           suffix_always is true.
2191    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2192    '!' => change condition from true to false or from false to true.
2193    '%' => add 1 upper case letter to the macro.
2194
2195    2 upper case letter macros:
2196    "XY" => print 'x' or 'y' if no register operands or suffix_always
2197            is true.
2198    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2199    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2200            or suffix_always is true
2201    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2202    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2203    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2204    "LW" => print 'd', 'q' depending on the VEX.W bit
2205
2206    Many of the above letters print nothing in Intel mode.  See "putop"
2207    for the details.
2208
2209    Braces '{' and '}', and vertical bars '|', indicate alternative
2210    mnemonic strings for AT&T and Intel.  */
2211
2212 static const struct dis386 dis386[] = {
2213   /* 00 */
2214   { "addB",             { Ebh1, Gb } },
2215   { "addS",             { Evh1, Gv } },
2216   { "addB",             { Gb, EbS } },
2217   { "addS",             { Gv, EvS } },
2218   { "addB",             { AL, Ib } },
2219   { "addS",             { eAX, Iv } },
2220   { X86_64_TABLE (X86_64_06) },
2221   { X86_64_TABLE (X86_64_07) },
2222   /* 08 */
2223   { "orB",              { Ebh1, Gb } },
2224   { "orS",              { Evh1, Gv } },
2225   { "orB",              { Gb, EbS } },
2226   { "orS",              { Gv, EvS } },
2227   { "orB",              { AL, Ib } },
2228   { "orS",              { eAX, Iv } },
2229   { X86_64_TABLE (X86_64_0D) },
2230   { Bad_Opcode },       /* 0x0f extended opcode escape */
2231   /* 10 */
2232   { "adcB",             { Ebh1, Gb } },
2233   { "adcS",             { Evh1, Gv } },
2234   { "adcB",             { Gb, EbS } },
2235   { "adcS",             { Gv, EvS } },
2236   { "adcB",             { AL, Ib } },
2237   { "adcS",             { eAX, Iv } },
2238   { X86_64_TABLE (X86_64_16) },
2239   { X86_64_TABLE (X86_64_17) },
2240   /* 18 */
2241   { "sbbB",             { Ebh1, Gb } },
2242   { "sbbS",             { Evh1, Gv } },
2243   { "sbbB",             { Gb, EbS } },
2244   { "sbbS",             { Gv, EvS } },
2245   { "sbbB",             { AL, Ib } },
2246   { "sbbS",             { eAX, Iv } },
2247   { X86_64_TABLE (X86_64_1E) },
2248   { X86_64_TABLE (X86_64_1F) },
2249   /* 20 */
2250   { "andB",             { Ebh1, Gb } },
2251   { "andS",             { Evh1, Gv } },
2252   { "andB",             { Gb, EbS } },
2253   { "andS",             { Gv, EvS } },
2254   { "andB",             { AL, Ib } },
2255   { "andS",             { eAX, Iv } },
2256   { Bad_Opcode },       /* SEG ES prefix */
2257   { X86_64_TABLE (X86_64_27) },
2258   /* 28 */
2259   { "subB",             { Ebh1, Gb } },
2260   { "subS",             { Evh1, Gv } },
2261   { "subB",             { Gb, EbS } },
2262   { "subS",             { Gv, EvS } },
2263   { "subB",             { AL, Ib } },
2264   { "subS",             { eAX, Iv } },
2265   { Bad_Opcode },       /* SEG CS prefix */
2266   { X86_64_TABLE (X86_64_2F) },
2267   /* 30 */
2268   { "xorB",             { Ebh1, Gb } },
2269   { "xorS",             { Evh1, Gv } },
2270   { "xorB",             { Gb, EbS } },
2271   { "xorS",             { Gv, EvS } },
2272   { "xorB",             { AL, Ib } },
2273   { "xorS",             { eAX, Iv } },
2274   { Bad_Opcode },       /* SEG SS prefix */
2275   { X86_64_TABLE (X86_64_37) },
2276   /* 38 */
2277   { "cmpB",             { Eb, Gb } },
2278   { "cmpS",             { Ev, Gv } },
2279   { "cmpB",             { Gb, EbS } },
2280   { "cmpS",             { Gv, EvS } },
2281   { "cmpB",             { AL, Ib } },
2282   { "cmpS",             { eAX, Iv } },
2283   { Bad_Opcode },       /* SEG DS prefix */
2284   { X86_64_TABLE (X86_64_3F) },
2285   /* 40 */
2286   { "inc{S|}",          { RMeAX } },
2287   { "inc{S|}",          { RMeCX } },
2288   { "inc{S|}",          { RMeDX } },
2289   { "inc{S|}",          { RMeBX } },
2290   { "inc{S|}",          { RMeSP } },
2291   { "inc{S|}",          { RMeBP } },
2292   { "inc{S|}",          { RMeSI } },
2293   { "inc{S|}",          { RMeDI } },
2294   /* 48 */
2295   { "dec{S|}",          { RMeAX } },
2296   { "dec{S|}",          { RMeCX } },
2297   { "dec{S|}",          { RMeDX } },
2298   { "dec{S|}",          { RMeBX } },
2299   { "dec{S|}",          { RMeSP } },
2300   { "dec{S|}",          { RMeBP } },
2301   { "dec{S|}",          { RMeSI } },
2302   { "dec{S|}",          { RMeDI } },
2303   /* 50 */
2304   { "pushV",            { RMrAX } },
2305   { "pushV",            { RMrCX } },
2306   { "pushV",            { RMrDX } },
2307   { "pushV",            { RMrBX } },
2308   { "pushV",            { RMrSP } },
2309   { "pushV",            { RMrBP } },
2310   { "pushV",            { RMrSI } },
2311   { "pushV",            { RMrDI } },
2312   /* 58 */
2313   { "popV",             { RMrAX } },
2314   { "popV",             { RMrCX } },
2315   { "popV",             { RMrDX } },
2316   { "popV",             { RMrBX } },
2317   { "popV",             { RMrSP } },
2318   { "popV",             { RMrBP } },
2319   { "popV",             { RMrSI } },
2320   { "popV",             { RMrDI } },
2321   /* 60 */
2322   { X86_64_TABLE (X86_64_60) },
2323   { X86_64_TABLE (X86_64_61) },
2324   { X86_64_TABLE (X86_64_62) },
2325   { X86_64_TABLE (X86_64_63) },
2326   { Bad_Opcode },       /* seg fs */
2327   { Bad_Opcode },       /* seg gs */
2328   { Bad_Opcode },       /* op size prefix */
2329   { Bad_Opcode },       /* adr size prefix */
2330   /* 68 */
2331   { "pushT",            { sIv } },
2332   { "imulS",            { Gv, Ev, Iv } },
2333   { "pushT",            { sIbT } },
2334   { "imulS",            { Gv, Ev, sIb } },
2335   { "ins{b|}",          { Ybr, indirDX } },
2336   { X86_64_TABLE (X86_64_6D) },
2337   { "outs{b|}",         { indirDXr, Xb } },
2338   { X86_64_TABLE (X86_64_6F) },
2339   /* 70 */
2340   { "joH",              { Jb, BND, cond_jump_flag } },
2341   { "jnoH",             { Jb, BND, cond_jump_flag } },
2342   { "jbH",              { Jb, BND, cond_jump_flag } },
2343   { "jaeH",             { Jb, BND, cond_jump_flag } },
2344   { "jeH",              { Jb, BND, cond_jump_flag } },
2345   { "jneH",             { Jb, BND, cond_jump_flag } },
2346   { "jbeH",             { Jb, BND, cond_jump_flag } },
2347   { "jaH",              { Jb, BND, cond_jump_flag } },
2348   /* 78 */
2349   { "jsH",              { Jb, BND, cond_jump_flag } },
2350   { "jnsH",             { Jb, BND, cond_jump_flag } },
2351   { "jpH",              { Jb, BND, cond_jump_flag } },
2352   { "jnpH",             { Jb, BND, cond_jump_flag } },
2353   { "jlH",              { Jb, BND, cond_jump_flag } },
2354   { "jgeH",             { Jb, BND, cond_jump_flag } },
2355   { "jleH",             { Jb, BND, cond_jump_flag } },
2356   { "jgH",              { Jb, BND, cond_jump_flag } },
2357   /* 80 */
2358   { REG_TABLE (REG_80) },
2359   { REG_TABLE (REG_81) },
2360   { Bad_Opcode },
2361   { REG_TABLE (REG_82) },
2362   { "testB",            { Eb, Gb } },
2363   { "testS",            { Ev, Gv } },
2364   { "xchgB",            { Ebh2, Gb } },
2365   { "xchgS",            { Evh2, Gv } },
2366   /* 88 */
2367   { "movB",             { Ebh3, Gb } },
2368   { "movS",             { Evh3, Gv } },
2369   { "movB",             { Gb, EbS } },
2370   { "movS",             { Gv, EvS } },
2371   { "movD",             { Sv, Sw } },
2372   { MOD_TABLE (MOD_8D) },
2373   { "movD",             { Sw, Sv } },
2374   { REG_TABLE (REG_8F) },
2375   /* 90 */
2376   { PREFIX_TABLE (PREFIX_90) },
2377   { "xchgS",            { RMeCX, eAX } },
2378   { "xchgS",            { RMeDX, eAX } },
2379   { "xchgS",            { RMeBX, eAX } },
2380   { "xchgS",            { RMeSP, eAX } },
2381   { "xchgS",            { RMeBP, eAX } },
2382   { "xchgS",            { RMeSI, eAX } },
2383   { "xchgS",            { RMeDI, eAX } },
2384   /* 98 */
2385   { "cW{t|}R",          { XX } },
2386   { "cR{t|}O",          { XX } },
2387   { X86_64_TABLE (X86_64_9A) },
2388   { Bad_Opcode },       /* fwait */
2389   { "pushfT",           { XX } },
2390   { "popfT",            { XX } },
2391   { "sahf",             { XX } },
2392   { "lahf",             { XX } },
2393   /* a0 */
2394   { "mov%LB",           { AL, Ob } },
2395   { "mov%LS",           { eAX, Ov } },
2396   { "mov%LB",           { Ob, AL } },
2397   { "mov%LS",           { Ov, eAX } },
2398   { "movs{b|}",         { Ybr, Xb } },
2399   { "movs{R|}",         { Yvr, Xv } },
2400   { "cmps{b|}",         { Xb, Yb } },
2401   { "cmps{R|}",         { Xv, Yv } },
2402   /* a8 */
2403   { "testB",            { AL, Ib } },
2404   { "testS",            { eAX, Iv } },
2405   { "stosB",            { Ybr, AL } },
2406   { "stosS",            { Yvr, eAX } },
2407   { "lodsB",            { ALr, Xb } },
2408   { "lodsS",            { eAXr, Xv } },
2409   { "scasB",            { AL, Yb } },
2410   { "scasS",            { eAX, Yv } },
2411   /* b0 */
2412   { "movB",             { RMAL, Ib } },
2413   { "movB",             { RMCL, Ib } },
2414   { "movB",             { RMDL, Ib } },
2415   { "movB",             { RMBL, Ib } },
2416   { "movB",             { RMAH, Ib } },
2417   { "movB",             { RMCH, Ib } },
2418   { "movB",             { RMDH, Ib } },
2419   { "movB",             { RMBH, Ib } },
2420   /* b8 */
2421   { "mov%LV",           { RMeAX, Iv64 } },
2422   { "mov%LV",           { RMeCX, Iv64 } },
2423   { "mov%LV",           { RMeDX, Iv64 } },
2424   { "mov%LV",           { RMeBX, Iv64 } },
2425   { "mov%LV",           { RMeSP, Iv64 } },
2426   { "mov%LV",           { RMeBP, Iv64 } },
2427   { "mov%LV",           { RMeSI, Iv64 } },
2428   { "mov%LV",           { RMeDI, Iv64 } },
2429   /* c0 */
2430   { REG_TABLE (REG_C0) },
2431   { REG_TABLE (REG_C1) },
2432   { "retT",             { Iw, BND } },
2433   { "retT",             { BND } },
2434   { X86_64_TABLE (X86_64_C4) },
2435   { X86_64_TABLE (X86_64_C5) },
2436   { REG_TABLE (REG_C6) },
2437   { REG_TABLE (REG_C7) },
2438   /* c8 */
2439   { "enterT",           { Iw, Ib } },
2440   { "leaveT",           { XX } },
2441   { "Jret{|f}P",        { Iw } },
2442   { "Jret{|f}P",        { XX } },
2443   { "int3",             { XX } },
2444   { "int",              { Ib } },
2445   { X86_64_TABLE (X86_64_CE) },
2446   { "iretP",            { XX } },
2447   /* d0 */
2448   { REG_TABLE (REG_D0) },
2449   { REG_TABLE (REG_D1) },
2450   { REG_TABLE (REG_D2) },
2451   { REG_TABLE (REG_D3) },
2452   { X86_64_TABLE (X86_64_D4) },
2453   { X86_64_TABLE (X86_64_D5) },
2454   { Bad_Opcode },
2455   { "xlat",             { DSBX } },
2456   /* d8 */
2457   { FLOAT },
2458   { FLOAT },
2459   { FLOAT },
2460   { FLOAT },
2461   { FLOAT },
2462   { FLOAT },
2463   { FLOAT },
2464   { FLOAT },
2465   /* e0 */
2466   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2467   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2468   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2469   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2470   { "inB",              { AL, Ib } },
2471   { "inG",              { zAX, Ib } },
2472   { "outB",             { Ib, AL } },
2473   { "outG",             { Ib, zAX } },
2474   /* e8 */
2475   { "callT",            { Jv, BND } },
2476   { "jmpT",             { Jv, BND } },
2477   { X86_64_TABLE (X86_64_EA) },
2478   { "jmp",              { Jb, BND } },
2479   { "inB",              { AL, indirDX } },
2480   { "inG",              { zAX, indirDX } },
2481   { "outB",             { indirDX, AL } },
2482   { "outG",             { indirDX, zAX } },
2483   /* f0 */
2484   { Bad_Opcode },       /* lock prefix */
2485   { "icebp",            { XX } },
2486   { Bad_Opcode },       /* repne */
2487   { Bad_Opcode },       /* repz */
2488   { "hlt",              { XX } },
2489   { "cmc",              { XX } },
2490   { REG_TABLE (REG_F6) },
2491   { REG_TABLE (REG_F7) },
2492   /* f8 */
2493   { "clc",              { XX } },
2494   { "stc",              { XX } },
2495   { "cli",              { XX } },
2496   { "sti",              { XX } },
2497   { "cld",              { XX } },
2498   { "std",              { XX } },
2499   { REG_TABLE (REG_FE) },
2500   { REG_TABLE (REG_FF) },
2501 };
2502
2503 static const struct dis386 dis386_twobyte[] = {
2504   /* 00 */
2505   { REG_TABLE (REG_0F00 ) },
2506   { REG_TABLE (REG_0F01 ) },
2507   { "larS",             { Gv, Ew } },
2508   { "lslS",             { Gv, Ew } },
2509   { Bad_Opcode },
2510   { "syscall",          { XX } },
2511   { "clts",             { XX } },
2512   { "sysretP",          { XX } },
2513   /* 08 */
2514   { "invd",             { XX } },
2515   { "wbinvd",           { XX } },
2516   { Bad_Opcode },
2517   { "ud2",              { XX } },
2518   { Bad_Opcode },
2519   { REG_TABLE (REG_0F0D) },
2520   { "femms",            { XX } },
2521   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2522   /* 10 */
2523   { PREFIX_TABLE (PREFIX_0F10) },
2524   { PREFIX_TABLE (PREFIX_0F11) },
2525   { PREFIX_TABLE (PREFIX_0F12) },
2526   { MOD_TABLE (MOD_0F13) },
2527   { "unpcklpX",         { XM, EXx } },
2528   { "unpckhpX",         { XM, EXx } },
2529   { PREFIX_TABLE (PREFIX_0F16) },
2530   { MOD_TABLE (MOD_0F17) },
2531   /* 18 */
2532   { REG_TABLE (REG_0F18) },
2533   { "nopQ",             { Ev } },
2534   { PREFIX_TABLE (PREFIX_0F1A) },
2535   { PREFIX_TABLE (PREFIX_0F1B) },
2536   { "nopQ",             { Ev } },
2537   { "nopQ",             { Ev } },
2538   { "nopQ",             { Ev } },
2539   { "nopQ",             { Ev } },
2540   /* 20 */
2541   { MOD_TABLE (MOD_0F20) },
2542   { MOD_TABLE (MOD_0F21) },
2543   { MOD_TABLE (MOD_0F22) },
2544   { MOD_TABLE (MOD_0F23) },
2545   { MOD_TABLE (MOD_0F24) },
2546   { Bad_Opcode },
2547   { MOD_TABLE (MOD_0F26) },
2548   { Bad_Opcode },
2549   /* 28 */
2550   { "movapX",           { XM, EXx } },
2551   { "movapX",           { EXxS, XM } },
2552   { PREFIX_TABLE (PREFIX_0F2A) },
2553   { PREFIX_TABLE (PREFIX_0F2B) },
2554   { PREFIX_TABLE (PREFIX_0F2C) },
2555   { PREFIX_TABLE (PREFIX_0F2D) },
2556   { PREFIX_TABLE (PREFIX_0F2E) },
2557   { PREFIX_TABLE (PREFIX_0F2F) },
2558   /* 30 */
2559   { "wrmsr",            { XX } },
2560   { "rdtsc",            { XX } },
2561   { "rdmsr",            { XX } },
2562   { "rdpmc",            { XX } },
2563   { "sysenter",         { XX } },
2564   { "sysexit",          { XX } },
2565   { Bad_Opcode },
2566   { "getsec",           { XX } },
2567   /* 38 */
2568   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2569   { Bad_Opcode },
2570   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2571   { Bad_Opcode },
2572   { Bad_Opcode },
2573   { Bad_Opcode },
2574   { Bad_Opcode },
2575   { Bad_Opcode },
2576   /* 40 */
2577   { "cmovoS",           { Gv, Ev } },
2578   { "cmovnoS",          { Gv, Ev } },
2579   { "cmovbS",           { Gv, Ev } },
2580   { "cmovaeS",          { Gv, Ev } },
2581   { "cmoveS",           { Gv, Ev } },
2582   { "cmovneS",          { Gv, Ev } },
2583   { "cmovbeS",          { Gv, Ev } },
2584   { "cmovaS",           { Gv, Ev } },
2585   /* 48 */
2586   { "cmovsS",           { Gv, Ev } },
2587   { "cmovnsS",          { Gv, Ev } },
2588   { "cmovpS",           { Gv, Ev } },
2589   { "cmovnpS",          { Gv, Ev } },
2590   { "cmovlS",           { Gv, Ev } },
2591   { "cmovgeS",          { Gv, Ev } },
2592   { "cmovleS",          { Gv, Ev } },
2593   { "cmovgS",           { Gv, Ev } },
2594   /* 50 */
2595   { MOD_TABLE (MOD_0F51) },
2596   { PREFIX_TABLE (PREFIX_0F51) },
2597   { PREFIX_TABLE (PREFIX_0F52) },
2598   { PREFIX_TABLE (PREFIX_0F53) },
2599   { "andpX",            { XM, EXx } },
2600   { "andnpX",           { XM, EXx } },
2601   { "orpX",             { XM, EXx } },
2602   { "xorpX",            { XM, EXx } },
2603   /* 58 */
2604   { PREFIX_TABLE (PREFIX_0F58) },
2605   { PREFIX_TABLE (PREFIX_0F59) },
2606   { PREFIX_TABLE (PREFIX_0F5A) },
2607   { PREFIX_TABLE (PREFIX_0F5B) },
2608   { PREFIX_TABLE (PREFIX_0F5C) },
2609   { PREFIX_TABLE (PREFIX_0F5D) },
2610   { PREFIX_TABLE (PREFIX_0F5E) },
2611   { PREFIX_TABLE (PREFIX_0F5F) },
2612   /* 60 */
2613   { PREFIX_TABLE (PREFIX_0F60) },
2614   { PREFIX_TABLE (PREFIX_0F61) },
2615   { PREFIX_TABLE (PREFIX_0F62) },
2616   { "packsswb",         { MX, EM } },
2617   { "pcmpgtb",          { MX, EM } },
2618   { "pcmpgtw",          { MX, EM } },
2619   { "pcmpgtd",          { MX, EM } },
2620   { "packuswb",         { MX, EM } },
2621   /* 68 */
2622   { "punpckhbw",        { MX, EM } },
2623   { "punpckhwd",        { MX, EM } },
2624   { "punpckhdq",        { MX, EM } },
2625   { "packssdw",         { MX, EM } },
2626   { PREFIX_TABLE (PREFIX_0F6C) },
2627   { PREFIX_TABLE (PREFIX_0F6D) },
2628   { "movK",             { MX, Edq } },
2629   { PREFIX_TABLE (PREFIX_0F6F) },
2630   /* 70 */
2631   { PREFIX_TABLE (PREFIX_0F70) },
2632   { REG_TABLE (REG_0F71) },
2633   { REG_TABLE (REG_0F72) },
2634   { REG_TABLE (REG_0F73) },
2635   { "pcmpeqb",          { MX, EM } },
2636   { "pcmpeqw",          { MX, EM } },
2637   { "pcmpeqd",          { MX, EM } },
2638   { "emms",             { XX } },
2639   /* 78 */
2640   { PREFIX_TABLE (PREFIX_0F78) },
2641   { PREFIX_TABLE (PREFIX_0F79) },
2642   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2643   { Bad_Opcode },
2644   { PREFIX_TABLE (PREFIX_0F7C) },
2645   { PREFIX_TABLE (PREFIX_0F7D) },
2646   { PREFIX_TABLE (PREFIX_0F7E) },
2647   { PREFIX_TABLE (PREFIX_0F7F) },
2648   /* 80 */
2649   { "joH",              { Jv, BND, cond_jump_flag } },
2650   { "jnoH",             { Jv, BND, cond_jump_flag } },
2651   { "jbH",              { Jv, BND, cond_jump_flag } },
2652   { "jaeH",             { Jv, BND, cond_jump_flag } },
2653   { "jeH",              { Jv, BND, cond_jump_flag } },
2654   { "jneH",             { Jv, BND, cond_jump_flag } },
2655   { "jbeH",             { Jv, BND, cond_jump_flag } },
2656   { "jaH",              { Jv, BND, cond_jump_flag } },
2657   /* 88 */
2658   { "jsH",              { Jv, BND, cond_jump_flag } },
2659   { "jnsH",             { Jv, BND, cond_jump_flag } },
2660   { "jpH",              { Jv, BND, cond_jump_flag } },
2661   { "jnpH",             { Jv, BND, cond_jump_flag } },
2662   { "jlH",              { Jv, BND, cond_jump_flag } },
2663   { "jgeH",             { Jv, BND, cond_jump_flag } },
2664   { "jleH",             { Jv, BND, cond_jump_flag } },
2665   { "jgH",              { Jv, BND, cond_jump_flag } },
2666   /* 90 */
2667   { "seto",             { Eb } },
2668   { "setno",            { Eb } },
2669   { "setb",             { Eb } },
2670   { "setae",            { Eb } },
2671   { "sete",             { Eb } },
2672   { "setne",            { Eb } },
2673   { "setbe",            { Eb } },
2674   { "seta",             { Eb } },
2675   /* 98 */
2676   { "sets",             { Eb } },
2677   { "setns",            { Eb } },
2678   { "setp",             { Eb } },
2679   { "setnp",            { Eb } },
2680   { "setl",             { Eb } },
2681   { "setge",            { Eb } },
2682   { "setle",            { Eb } },
2683   { "setg",             { Eb } },
2684   /* a0 */
2685   { "pushT",            { fs } },
2686   { "popT",             { fs } },
2687   { "cpuid",            { XX } },
2688   { "btS",              { Ev, Gv } },
2689   { "shldS",            { Ev, Gv, Ib } },
2690   { "shldS",            { Ev, Gv, CL } },
2691   { REG_TABLE (REG_0FA6) },
2692   { REG_TABLE (REG_0FA7) },
2693   /* a8 */
2694   { "pushT",            { gs } },
2695   { "popT",             { gs } },
2696   { "rsm",              { XX } },
2697   { "btsS",             { Evh1, Gv } },
2698   { "shrdS",            { Ev, Gv, Ib } },
2699   { "shrdS",            { Ev, Gv, CL } },
2700   { REG_TABLE (REG_0FAE) },
2701   { "imulS",            { Gv, Ev } },
2702   /* b0 */
2703   { "cmpxchgB",         { Ebh1, Gb } },
2704   { "cmpxchgS",         { Evh1, Gv } },
2705   { MOD_TABLE (MOD_0FB2) },
2706   { "btrS",             { Evh1, Gv } },
2707   { MOD_TABLE (MOD_0FB4) },
2708   { MOD_TABLE (MOD_0FB5) },
2709   { "movz{bR|x}",       { Gv, Eb } },
2710   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2711   /* b8 */
2712   { PREFIX_TABLE (PREFIX_0FB8) },
2713   { "ud1",              { XX } },
2714   { REG_TABLE (REG_0FBA) },
2715   { "btcS",             { Evh1, Gv } },
2716   { PREFIX_TABLE (PREFIX_0FBC) },
2717   { PREFIX_TABLE (PREFIX_0FBD) },
2718   { "movs{bR|x}",       { Gv, Eb } },
2719   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2720   /* c0 */
2721   { "xaddB",            { Ebh1, Gb } },
2722   { "xaddS",            { Evh1, Gv } },
2723   { PREFIX_TABLE (PREFIX_0FC2) },
2724   { PREFIX_TABLE (PREFIX_0FC3) },
2725   { "pinsrw",           { MX, Edqw, Ib } },
2726   { "pextrw",           { Gdq, MS, Ib } },
2727   { "shufpX",           { XM, EXx, Ib } },
2728   { REG_TABLE (REG_0FC7) },
2729   /* c8 */
2730   { "bswap",            { RMeAX } },
2731   { "bswap",            { RMeCX } },
2732   { "bswap",            { RMeDX } },
2733   { "bswap",            { RMeBX } },
2734   { "bswap",            { RMeSP } },
2735   { "bswap",            { RMeBP } },
2736   { "bswap",            { RMeSI } },
2737   { "bswap",            { RMeDI } },
2738   /* d0 */
2739   { PREFIX_TABLE (PREFIX_0FD0) },
2740   { "psrlw",            { MX, EM } },
2741   { "psrld",            { MX, EM } },
2742   { "psrlq",            { MX, EM } },
2743   { "paddq",            { MX, EM } },
2744   { "pmullw",           { MX, EM } },
2745   { PREFIX_TABLE (PREFIX_0FD6) },
2746   { MOD_TABLE (MOD_0FD7) },
2747   /* d8 */
2748   { "psubusb",          { MX, EM } },
2749   { "psubusw",          { MX, EM } },
2750   { "pminub",           { MX, EM } },
2751   { "pand",             { MX, EM } },
2752   { "paddusb",          { MX, EM } },
2753   { "paddusw",          { MX, EM } },
2754   { "pmaxub",           { MX, EM } },
2755   { "pandn",            { MX, EM } },
2756   /* e0 */
2757   { "pavgb",            { MX, EM } },
2758   { "psraw",            { MX, EM } },
2759   { "psrad",            { MX, EM } },
2760   { "pavgw",            { MX, EM } },
2761   { "pmulhuw",          { MX, EM } },
2762   { "pmulhw",           { MX, EM } },
2763   { PREFIX_TABLE (PREFIX_0FE6) },
2764   { PREFIX_TABLE (PREFIX_0FE7) },
2765   /* e8 */
2766   { "psubsb",           { MX, EM } },
2767   { "psubsw",           { MX, EM } },
2768   { "pminsw",           { MX, EM } },
2769   { "por",              { MX, EM } },
2770   { "paddsb",           { MX, EM } },
2771   { "paddsw",           { MX, EM } },
2772   { "pmaxsw",           { MX, EM } },
2773   { "pxor",             { MX, EM } },
2774   /* f0 */
2775   { PREFIX_TABLE (PREFIX_0FF0) },
2776   { "psllw",            { MX, EM } },
2777   { "pslld",            { MX, EM } },
2778   { "psllq",            { MX, EM } },
2779   { "pmuludq",          { MX, EM } },
2780   { "pmaddwd",          { MX, EM } },
2781   { "psadbw",           { MX, EM } },
2782   { PREFIX_TABLE (PREFIX_0FF7) },
2783   /* f8 */
2784   { "psubb",            { MX, EM } },
2785   { "psubw",            { MX, EM } },
2786   { "psubd",            { MX, EM } },
2787   { "psubq",            { MX, EM } },
2788   { "paddb",            { MX, EM } },
2789   { "paddw",            { MX, EM } },
2790   { "paddd",            { MX, EM } },
2791   { Bad_Opcode },
2792 };
2793
2794 static const unsigned char onebyte_has_modrm[256] = {
2795   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2796   /*       -------------------------------        */
2797   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2798   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2799   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2800   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2801   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2802   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2803   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2804   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2805   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2806   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2807   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2808   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2809   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2810   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2811   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2812   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2813   /*       -------------------------------        */
2814   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2815 };
2816
2817 static const unsigned char twobyte_has_modrm[256] = {
2818   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2819   /*       -------------------------------        */
2820   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2821   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2822   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2823   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2824   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2825   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2826   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2827   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2828   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2829   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2830   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2831   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2832   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2833   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2834   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2835   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2836   /*       -------------------------------        */
2837   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2838 };
2839
2840 static char obuf[100];
2841 static char *obufp;
2842 static char *mnemonicendp;
2843 static char scratchbuf[100];
2844 static unsigned char *start_codep;
2845 static unsigned char *insn_codep;
2846 static unsigned char *codep;
2847 static int last_lock_prefix;
2848 static int last_repz_prefix;
2849 static int last_repnz_prefix;
2850 static int last_data_prefix;
2851 static int last_addr_prefix;
2852 static int last_rex_prefix;
2853 static int last_seg_prefix;
2854 #define MAX_CODE_LENGTH 15
2855 /* We can up to 14 prefixes since the maximum instruction length is
2856    15bytes.  */
2857 static int all_prefixes[MAX_CODE_LENGTH - 1];
2858 static disassemble_info *the_info;
2859 static struct
2860   {
2861     int mod;
2862     int reg;
2863     int rm;
2864   }
2865 modrm;
2866 static unsigned char need_modrm;
2867 static struct
2868   {
2869     int scale;
2870     int index;
2871     int base;
2872   }
2873 sib;
2874 static struct
2875   {
2876     int register_specifier;
2877     int length;
2878     int prefix;
2879     int w;
2880     int evex;
2881     int r;
2882     int v;
2883     int mask_register_specifier;
2884     int zeroing;
2885     int ll;
2886     int b;
2887   }
2888 vex;
2889 static unsigned char need_vex;
2890 static unsigned char need_vex_reg;
2891 static unsigned char vex_w_done;
2892
2893 struct op
2894   {
2895     const char *name;
2896     unsigned int len;
2897   };
2898
2899 /* If we are accessing mod/rm/reg without need_modrm set, then the
2900    values are stale.  Hitting this abort likely indicates that you
2901    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2902 #define MODRM_CHECK  if (!need_modrm) abort ()
2903
2904 static const char **names64;
2905 static const char **names32;
2906 static const char **names16;
2907 static const char **names8;
2908 static const char **names8rex;
2909 static const char **names_seg;
2910 static const char *index64;
2911 static const char *index32;
2912 static const char **index16;
2913 static const char **names_bnd;
2914
2915 static const char *intel_names64[] = {
2916   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2917   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2918 };
2919 static const char *intel_names32[] = {
2920   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2921   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2922 };
2923 static const char *intel_names16[] = {
2924   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2925   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2926 };
2927 static const char *intel_names8[] = {
2928   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2929 };
2930 static const char *intel_names8rex[] = {
2931   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2932   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2933 };
2934 static const char *intel_names_seg[] = {
2935   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2936 };
2937 static const char *intel_index64 = "riz";
2938 static const char *intel_index32 = "eiz";
2939 static const char *intel_index16[] = {
2940   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2941 };
2942
2943 static const char *att_names64[] = {
2944   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2945   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2946 };
2947 static const char *att_names32[] = {
2948   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2949   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2950 };
2951 static const char *att_names16[] = {
2952   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2953   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2954 };
2955 static const char *att_names8[] = {
2956   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2957 };
2958 static const char *att_names8rex[] = {
2959   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2960   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2961 };
2962 static const char *att_names_seg[] = {
2963   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2964 };
2965 static const char *att_index64 = "%riz";
2966 static const char *att_index32 = "%eiz";
2967 static const char *att_index16[] = {
2968   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2969 };
2970
2971 static const char **names_mm;
2972 static const char *intel_names_mm[] = {
2973   "mm0", "mm1", "mm2", "mm3",
2974   "mm4", "mm5", "mm6", "mm7"
2975 };
2976 static const char *att_names_mm[] = {
2977   "%mm0", "%mm1", "%mm2", "%mm3",
2978   "%mm4", "%mm5", "%mm6", "%mm7"
2979 };
2980
2981 static const char *intel_names_bnd[] = {
2982   "bnd0", "bnd1", "bnd2", "bnd3"
2983 };
2984
2985 static const char *att_names_bnd[] = {
2986   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2987 };
2988
2989 static const char **names_xmm;
2990 static const char *intel_names_xmm[] = {
2991   "xmm0", "xmm1", "xmm2", "xmm3",
2992   "xmm4", "xmm5", "xmm6", "xmm7",
2993   "xmm8", "xmm9", "xmm10", "xmm11",
2994   "xmm12", "xmm13", "xmm14", "xmm15",
2995   "xmm16", "xmm17", "xmm18", "xmm19",
2996   "xmm20", "xmm21", "xmm22", "xmm23",
2997   "xmm24", "xmm25", "xmm26", "xmm27",
2998   "xmm28", "xmm29", "xmm30", "xmm31"
2999 };
3000 static const char *att_names_xmm[] = {
3001   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3002   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3003   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3004   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3005   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3006   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3007   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3008   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3009 };
3010
3011 static const char **names_ymm;
3012 static const char *intel_names_ymm[] = {
3013   "ymm0", "ymm1", "ymm2", "ymm3",
3014   "ymm4", "ymm5", "ymm6", "ymm7",
3015   "ymm8", "ymm9", "ymm10", "ymm11",
3016   "ymm12", "ymm13", "ymm14", "ymm15",
3017   "ymm16", "ymm17", "ymm18", "ymm19",
3018   "ymm20", "ymm21", "ymm22", "ymm23",
3019   "ymm24", "ymm25", "ymm26", "ymm27",
3020   "ymm28", "ymm29", "ymm30", "ymm31"
3021 };
3022 static const char *att_names_ymm[] = {
3023   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3024   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3025   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3026   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3027   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3028   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3029   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3030   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3031 };
3032
3033 static const char **names_zmm;
3034 static const char *intel_names_zmm[] = {
3035   "zmm0", "zmm1", "zmm2", "zmm3",
3036   "zmm4", "zmm5", "zmm6", "zmm7",
3037   "zmm8", "zmm9", "zmm10", "zmm11",
3038   "zmm12", "zmm13", "zmm14", "zmm15",
3039   "zmm16", "zmm17", "zmm18", "zmm19",
3040   "zmm20", "zmm21", "zmm22", "zmm23",
3041   "zmm24", "zmm25", "zmm26", "zmm27",
3042   "zmm28", "zmm29", "zmm30", "zmm31"
3043 };
3044 static const char *att_names_zmm[] = {
3045   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3046   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3047   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3048   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3049   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3050   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3051   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3052   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3053 };
3054
3055 static const char **names_mask;
3056 static const char *intel_names_mask[] = {
3057   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3058 };
3059 static const char *att_names_mask[] = {
3060   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3061 };
3062
3063 static const char *names_rounding[] =
3064 {
3065   "{rn-sae}",
3066   "{rd-sae}",
3067   "{ru-sae}",
3068   "{rz-sae}"
3069 };
3070
3071 static const struct dis386 reg_table[][8] = {
3072   /* REG_80 */
3073   {
3074     { "addA",   { Ebh1, Ib } },
3075     { "orA",    { Ebh1, Ib } },
3076     { "adcA",   { Ebh1, Ib } },
3077     { "sbbA",   { Ebh1, Ib } },
3078     { "andA",   { Ebh1, Ib } },
3079     { "subA",   { Ebh1, Ib } },
3080     { "xorA",   { Ebh1, Ib } },
3081     { "cmpA",   { Eb, Ib } },
3082   },
3083   /* REG_81 */
3084   {
3085     { "addQ",   { Evh1, Iv } },
3086     { "orQ",    { Evh1, Iv } },
3087     { "adcQ",   { Evh1, Iv } },
3088     { "sbbQ",   { Evh1, Iv } },
3089     { "andQ",   { Evh1, Iv } },
3090     { "subQ",   { Evh1, Iv } },
3091     { "xorQ",   { Evh1, Iv } },
3092     { "cmpQ",   { Ev, Iv } },
3093   },
3094   /* REG_82 */
3095   {
3096     { "addQ",   { Evh1, sIb } },
3097     { "orQ",    { Evh1, sIb } },
3098     { "adcQ",   { Evh1, sIb } },
3099     { "sbbQ",   { Evh1, sIb } },
3100     { "andQ",   { Evh1, sIb } },
3101     { "subQ",   { Evh1, sIb } },
3102     { "xorQ",   { Evh1, sIb } },
3103     { "cmpQ",   { Ev, sIb } },
3104   },
3105   /* REG_8F */
3106   {
3107     { "popU",   { stackEv } },
3108     { XOP_8F_TABLE (XOP_09) },
3109     { Bad_Opcode },
3110     { Bad_Opcode },
3111     { Bad_Opcode },
3112     { XOP_8F_TABLE (XOP_09) },
3113   },
3114   /* REG_C0 */
3115   {
3116     { "rolA",   { Eb, Ib } },
3117     { "rorA",   { Eb, Ib } },
3118     { "rclA",   { Eb, Ib } },
3119     { "rcrA",   { Eb, Ib } },
3120     { "shlA",   { Eb, Ib } },
3121     { "shrA",   { Eb, Ib } },
3122     { Bad_Opcode },
3123     { "sarA",   { Eb, Ib } },
3124   },
3125   /* REG_C1 */
3126   {
3127     { "rolQ",   { Ev, Ib } },
3128     { "rorQ",   { Ev, Ib } },
3129     { "rclQ",   { Ev, Ib } },
3130     { "rcrQ",   { Ev, Ib } },
3131     { "shlQ",   { Ev, Ib } },
3132     { "shrQ",   { Ev, Ib } },
3133     { Bad_Opcode },
3134     { "sarQ",   { Ev, Ib } },
3135   },
3136   /* REG_C6 */
3137   {
3138     { "movA",   { Ebh3, Ib } },
3139     { Bad_Opcode },
3140     { Bad_Opcode },
3141     { Bad_Opcode },
3142     { Bad_Opcode },
3143     { Bad_Opcode },
3144     { Bad_Opcode },
3145     { MOD_TABLE (MOD_C6_REG_7) },
3146   },
3147   /* REG_C7 */
3148   {
3149     { "movQ",   { Evh3, Iv } },
3150     { Bad_Opcode },
3151     { Bad_Opcode },
3152     { Bad_Opcode },
3153     { Bad_Opcode },
3154     { Bad_Opcode },
3155     { Bad_Opcode },
3156     { MOD_TABLE (MOD_C7_REG_7) },
3157   },
3158   /* REG_D0 */
3159   {
3160     { "rolA",   { Eb, I1 } },
3161     { "rorA",   { Eb, I1 } },
3162     { "rclA",   { Eb, I1 } },
3163     { "rcrA",   { Eb, I1 } },
3164     { "shlA",   { Eb, I1 } },
3165     { "shrA",   { Eb, I1 } },
3166     { Bad_Opcode },
3167     { "sarA",   { Eb, I1 } },
3168   },
3169   /* REG_D1 */
3170   {
3171     { "rolQ",   { Ev, I1 } },
3172     { "rorQ",   { Ev, I1 } },
3173     { "rclQ",   { Ev, I1 } },
3174     { "rcrQ",   { Ev, I1 } },
3175     { "shlQ",   { Ev, I1 } },
3176     { "shrQ",   { Ev, I1 } },
3177     { Bad_Opcode },
3178     { "sarQ",   { Ev, I1 } },
3179   },
3180   /* REG_D2 */
3181   {
3182     { "rolA",   { Eb, CL } },
3183     { "rorA",   { Eb, CL } },
3184     { "rclA",   { Eb, CL } },
3185     { "rcrA",   { Eb, CL } },
3186     { "shlA",   { Eb, CL } },
3187     { "shrA",   { Eb, CL } },
3188     { Bad_Opcode },
3189     { "sarA",   { Eb, CL } },
3190   },
3191   /* REG_D3 */
3192   {
3193     { "rolQ",   { Ev, CL } },
3194     { "rorQ",   { Ev, CL } },
3195     { "rclQ",   { Ev, CL } },
3196     { "rcrQ",   { Ev, CL } },
3197     { "shlQ",   { Ev, CL } },
3198     { "shrQ",   { Ev, CL } },
3199     { Bad_Opcode },
3200     { "sarQ",   { Ev, CL } },
3201   },
3202   /* REG_F6 */
3203   {
3204     { "testA",  { Eb, Ib } },
3205     { Bad_Opcode },
3206     { "notA",   { Ebh1 } },
3207     { "negA",   { Ebh1 } },
3208     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3209     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3210     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3211     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3212   },
3213   /* REG_F7 */
3214   {
3215     { "testQ",  { Ev, Iv } },
3216     { Bad_Opcode },
3217     { "notQ",   { Evh1 } },
3218     { "negQ",   { Evh1 } },
3219     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3220     { "imulQ",  { Ev } },
3221     { "divQ",   { Ev } },
3222     { "idivQ",  { Ev } },
3223   },
3224   /* REG_FE */
3225   {
3226     { "incA",   { Ebh1 } },
3227     { "decA",   { Ebh1 } },
3228   },
3229   /* REG_FF */
3230   {
3231     { "incQ",   { Evh1 } },
3232     { "decQ",   { Evh1 } },
3233     { "call{T|}", { indirEv, BND } },
3234     { "Jcall{T|}", { indirEp } },
3235     { "jmp{T|}", { indirEv, BND } },
3236     { "Jjmp{T|}", { indirEp } },
3237     { "pushU",  { stackEv } },
3238     { Bad_Opcode },
3239   },
3240   /* REG_0F00 */
3241   {
3242     { "sldtD",  { Sv } },
3243     { "strD",   { Sv } },
3244     { "lldt",   { Ew } },
3245     { "ltr",    { Ew } },
3246     { "verr",   { Ew } },
3247     { "verw",   { Ew } },
3248     { Bad_Opcode },
3249     { Bad_Opcode },
3250   },
3251   /* REG_0F01 */
3252   {
3253     { MOD_TABLE (MOD_0F01_REG_0) },
3254     { MOD_TABLE (MOD_0F01_REG_1) },
3255     { MOD_TABLE (MOD_0F01_REG_2) },
3256     { MOD_TABLE (MOD_0F01_REG_3) },
3257     { "smswD",  { Sv } },
3258     { Bad_Opcode },
3259     { "lmsw",   { Ew } },
3260     { MOD_TABLE (MOD_0F01_REG_7) },
3261   },
3262   /* REG_0F0D */
3263   {
3264     { "prefetch",       { Mb } },
3265     { "prefetchw",      { Mb } },
3266     { "prefetchwt1",    { Mb } },
3267     { "prefetch",       { Mb } },
3268     { "prefetch",       { Mb } },
3269     { "prefetch",       { Mb } },
3270     { "prefetch",       { Mb } },
3271     { "prefetch",       { Mb } },
3272   },
3273   /* REG_0F18 */
3274   {
3275     { MOD_TABLE (MOD_0F18_REG_0) },
3276     { MOD_TABLE (MOD_0F18_REG_1) },
3277     { MOD_TABLE (MOD_0F18_REG_2) },
3278     { MOD_TABLE (MOD_0F18_REG_3) },
3279     { MOD_TABLE (MOD_0F18_REG_4) },
3280     { MOD_TABLE (MOD_0F18_REG_5) },
3281     { MOD_TABLE (MOD_0F18_REG_6) },
3282     { MOD_TABLE (MOD_0F18_REG_7) },
3283   },
3284   /* REG_0F71 */
3285   {
3286     { Bad_Opcode },
3287     { Bad_Opcode },
3288     { MOD_TABLE (MOD_0F71_REG_2) },
3289     { Bad_Opcode },
3290     { MOD_TABLE (MOD_0F71_REG_4) },
3291     { Bad_Opcode },
3292     { MOD_TABLE (MOD_0F71_REG_6) },
3293   },
3294   /* REG_0F72 */
3295   {
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { MOD_TABLE (MOD_0F72_REG_2) },
3299     { Bad_Opcode },
3300     { MOD_TABLE (MOD_0F72_REG_4) },
3301     { Bad_Opcode },
3302     { MOD_TABLE (MOD_0F72_REG_6) },
3303   },
3304   /* REG_0F73 */
3305   {
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { MOD_TABLE (MOD_0F73_REG_2) },
3309     { MOD_TABLE (MOD_0F73_REG_3) },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { MOD_TABLE (MOD_0F73_REG_6) },
3313     { MOD_TABLE (MOD_0F73_REG_7) },
3314   },
3315   /* REG_0FA6 */
3316   {
3317     { "montmul",        { { OP_0f07, 0 } } },
3318     { "xsha1",          { { OP_0f07, 0 } } },
3319     { "xsha256",        { { OP_0f07, 0 } } },
3320   },
3321   /* REG_0FA7 */
3322   {
3323     { "xstore-rng",     { { OP_0f07, 0 } } },
3324     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3325     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3326     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3327     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3328     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3329   },
3330   /* REG_0FAE */
3331   {
3332     { MOD_TABLE (MOD_0FAE_REG_0) },
3333     { MOD_TABLE (MOD_0FAE_REG_1) },
3334     { MOD_TABLE (MOD_0FAE_REG_2) },
3335     { MOD_TABLE (MOD_0FAE_REG_3) },
3336     { MOD_TABLE (MOD_0FAE_REG_4) },
3337     { MOD_TABLE (MOD_0FAE_REG_5) },
3338     { MOD_TABLE (MOD_0FAE_REG_6) },
3339     { MOD_TABLE (MOD_0FAE_REG_7) },
3340   },
3341   /* REG_0FBA */
3342   {
3343     { Bad_Opcode },
3344     { Bad_Opcode },
3345     { Bad_Opcode },
3346     { Bad_Opcode },
3347     { "btQ",    { Ev, Ib } },
3348     { "btsQ",   { Evh1, Ib } },
3349     { "btrQ",   { Evh1, Ib } },
3350     { "btcQ",   { Evh1, Ib } },
3351   },
3352   /* REG_0FC7 */
3353   {
3354     { Bad_Opcode },
3355     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3356     { Bad_Opcode },
3357     { Bad_Opcode },
3358     { Bad_Opcode },
3359     { Bad_Opcode },
3360     { MOD_TABLE (MOD_0FC7_REG_6) },
3361     { MOD_TABLE (MOD_0FC7_REG_7) },
3362   },
3363   /* REG_VEX_0F71 */
3364   {
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3368     { Bad_Opcode },
3369     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3370     { Bad_Opcode },
3371     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3372   },
3373   /* REG_VEX_0F72 */
3374   {
3375     { Bad_Opcode },
3376     { Bad_Opcode },
3377     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3378     { Bad_Opcode },
3379     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3380     { Bad_Opcode },
3381     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3382   },
3383   /* REG_VEX_0F73 */
3384   {
3385     { Bad_Opcode },
3386     { Bad_Opcode },
3387     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3388     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3389     { Bad_Opcode },
3390     { Bad_Opcode },
3391     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3392     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3393   },
3394   /* REG_VEX_0FAE */
3395   {
3396     { Bad_Opcode },
3397     { Bad_Opcode },
3398     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3399     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3400   },
3401   /* REG_VEX_0F38F3 */
3402   {
3403     { Bad_Opcode },
3404     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3405     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3406     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3407   },
3408   /* REG_XOP_LWPCB */
3409   {
3410     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3411     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3412   },
3413   /* REG_XOP_LWP */
3414   {
3415     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3416     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3417   },
3418   /* REG_XOP_TBM_01 */
3419   {
3420     { Bad_Opcode },
3421     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3422     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3423     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3424     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3425     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3426     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3427     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3428   },
3429   /* REG_XOP_TBM_02 */
3430   {
3431     { Bad_Opcode },
3432     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3433     { Bad_Opcode },
3434     { Bad_Opcode },
3435     { Bad_Opcode },
3436     { Bad_Opcode },
3437     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3438   },
3439 #define NEED_REG_TABLE
3440 #include "i386-dis-evex.h"
3441 #undef NEED_REG_TABLE
3442 };
3443
3444 static const struct dis386 prefix_table[][4] = {
3445   /* PREFIX_90 */
3446   {
3447     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3448     { "pause", { XX } },
3449     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3450   },
3451
3452   /* PREFIX_0F10 */
3453   {
3454     { "movups", { XM, EXx } },
3455     { "movss",  { XM, EXd } },
3456     { "movupd", { XM, EXx } },
3457     { "movsd",  { XM, EXq } },
3458   },
3459
3460   /* PREFIX_0F11 */
3461   {
3462     { "movups", { EXxS, XM } },
3463     { "movss",  { EXdS, XM } },
3464     { "movupd", { EXxS, XM } },
3465     { "movsd",  { EXqS, XM } },
3466   },
3467
3468   /* PREFIX_0F12 */
3469   {
3470     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3471     { "movsldup", { XM, EXx } },
3472     { "movlpd", { XM, EXq } },
3473     { "movddup", { XM, EXq } },
3474   },
3475
3476   /* PREFIX_0F16 */
3477   {
3478     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3479     { "movshdup", { XM, EXx } },
3480     { "movhpd", { XM, EXq } },
3481   },
3482
3483   /* PREFIX_0F1A */
3484   {
3485     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3486     { "bndcl",  { Gbnd, Ev_bnd } },
3487     { "bndmov", { Gbnd, Ebnd } },
3488     { "bndcu",  { Gbnd, Ev_bnd } },
3489   },
3490
3491   /* PREFIX_0F1B */
3492   {
3493     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3494     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3495     { "bndmov", { Ebnd, Gbnd } },
3496     { "bndcn",  { Gbnd, Ev_bnd } },
3497   },
3498
3499   /* PREFIX_0F2A */
3500   {
3501     { "cvtpi2ps", { XM, EMCq } },
3502     { "cvtsi2ss%LQ", { XM, Ev } },
3503     { "cvtpi2pd", { XM, EMCq } },
3504     { "cvtsi2sd%LQ", { XM, Ev } },
3505   },
3506
3507   /* PREFIX_0F2B */
3508   {
3509     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3510     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3511     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3512     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3513   },
3514
3515   /* PREFIX_0F2C */
3516   {
3517     { "cvttps2pi", { MXC, EXq } },
3518     { "cvttss2siY", { Gv, EXd } },
3519     { "cvttpd2pi", { MXC, EXx } },
3520     { "cvttsd2siY", { Gv, EXq } },
3521   },
3522
3523   /* PREFIX_0F2D */
3524   {
3525     { "cvtps2pi", { MXC, EXq } },
3526     { "cvtss2siY", { Gv, EXd } },
3527     { "cvtpd2pi", { MXC, EXx } },
3528     { "cvtsd2siY", { Gv, EXq } },
3529   },
3530
3531   /* PREFIX_0F2E */
3532   {
3533     { "ucomiss",{ XM, EXd } },
3534     { Bad_Opcode },
3535     { "ucomisd",{ XM, EXq } },
3536   },
3537
3538   /* PREFIX_0F2F */
3539   {
3540     { "comiss", { XM, EXd } },
3541     { Bad_Opcode },
3542     { "comisd", { XM, EXq } },
3543   },
3544
3545   /* PREFIX_0F51 */
3546   {
3547     { "sqrtps", { XM, EXx } },
3548     { "sqrtss", { XM, EXd } },
3549     { "sqrtpd", { XM, EXx } },
3550     { "sqrtsd", { XM, EXq } },
3551   },
3552
3553   /* PREFIX_0F52 */
3554   {
3555     { "rsqrtps",{ XM, EXx } },
3556     { "rsqrtss",{ XM, EXd } },
3557   },
3558
3559   /* PREFIX_0F53 */
3560   {
3561     { "rcpps",  { XM, EXx } },
3562     { "rcpss",  { XM, EXd } },
3563   },
3564
3565   /* PREFIX_0F58 */
3566   {
3567     { "addps", { XM, EXx } },
3568     { "addss", { XM, EXd } },
3569     { "addpd", { XM, EXx } },
3570     { "addsd", { XM, EXq } },
3571   },
3572
3573   /* PREFIX_0F59 */
3574   {
3575     { "mulps",  { XM, EXx } },
3576     { "mulss",  { XM, EXd } },
3577     { "mulpd",  { XM, EXx } },
3578     { "mulsd",  { XM, EXq } },
3579   },
3580
3581   /* PREFIX_0F5A */
3582   {
3583     { "cvtps2pd", { XM, EXq } },
3584     { "cvtss2sd", { XM, EXd } },
3585     { "cvtpd2ps", { XM, EXx } },
3586     { "cvtsd2ss", { XM, EXq } },
3587   },
3588
3589   /* PREFIX_0F5B */
3590   {
3591     { "cvtdq2ps", { XM, EXx } },
3592     { "cvttps2dq", { XM, EXx } },
3593     { "cvtps2dq", { XM, EXx } },
3594   },
3595
3596   /* PREFIX_0F5C */
3597   {
3598     { "subps",  { XM, EXx } },
3599     { "subss",  { XM, EXd } },
3600     { "subpd",  { XM, EXx } },
3601     { "subsd",  { XM, EXq } },
3602   },
3603
3604   /* PREFIX_0F5D */
3605   {
3606     { "minps",  { XM, EXx } },
3607     { "minss",  { XM, EXd } },
3608     { "minpd",  { XM, EXx } },
3609     { "minsd",  { XM, EXq } },
3610   },
3611
3612   /* PREFIX_0F5E */
3613   {
3614     { "divps",  { XM, EXx } },
3615     { "divss",  { XM, EXd } },
3616     { "divpd",  { XM, EXx } },
3617     { "divsd",  { XM, EXq } },
3618   },
3619
3620   /* PREFIX_0F5F */
3621   {
3622     { "maxps",  { XM, EXx } },
3623     { "maxss",  { XM, EXd } },
3624     { "maxpd",  { XM, EXx } },
3625     { "maxsd",  { XM, EXq } },
3626   },
3627
3628   /* PREFIX_0F60 */
3629   {
3630     { "punpcklbw",{ MX, EMd } },
3631     { Bad_Opcode },
3632     { "punpcklbw",{ MX, EMx } },
3633   },
3634
3635   /* PREFIX_0F61 */
3636   {
3637     { "punpcklwd",{ MX, EMd } },
3638     { Bad_Opcode },
3639     { "punpcklwd",{ MX, EMx } },
3640   },
3641
3642   /* PREFIX_0F62 */
3643   {
3644     { "punpckldq",{ MX, EMd } },
3645     { Bad_Opcode },
3646     { "punpckldq",{ MX, EMx } },
3647   },
3648
3649   /* PREFIX_0F6C */
3650   {
3651     { Bad_Opcode },
3652     { Bad_Opcode },
3653     { "punpcklqdq", { XM, EXx } },
3654   },
3655
3656   /* PREFIX_0F6D */
3657   {
3658     { Bad_Opcode },
3659     { Bad_Opcode },
3660     { "punpckhqdq", { XM, EXx } },
3661   },
3662
3663   /* PREFIX_0F6F */
3664   {
3665     { "movq",   { MX, EM } },
3666     { "movdqu", { XM, EXx } },
3667     { "movdqa", { XM, EXx } },
3668   },
3669
3670   /* PREFIX_0F70 */
3671   {
3672     { "pshufw", { MX, EM, Ib } },
3673     { "pshufhw",{ XM, EXx, Ib } },
3674     { "pshufd", { XM, EXx, Ib } },
3675     { "pshuflw",{ XM, EXx, Ib } },
3676   },
3677
3678   /* PREFIX_0F73_REG_3 */
3679   {
3680     { Bad_Opcode },
3681     { Bad_Opcode },
3682     { "psrldq", { XS, Ib } },
3683   },
3684
3685   /* PREFIX_0F73_REG_7 */
3686   {
3687     { Bad_Opcode },
3688     { Bad_Opcode },
3689     { "pslldq", { XS, Ib } },
3690   },
3691
3692   /* PREFIX_0F78 */
3693   {
3694     {"vmread",  { Em, Gm } },
3695     { Bad_Opcode },
3696     {"extrq",   { XS, Ib, Ib } },
3697     {"insertq", { XM, XS, Ib, Ib } },
3698   },
3699
3700   /* PREFIX_0F79 */
3701   {
3702     {"vmwrite", { Gm, Em } },
3703     { Bad_Opcode },
3704     {"extrq",   { XM, XS } },
3705     {"insertq", { XM, XS } },
3706   },
3707
3708   /* PREFIX_0F7C */
3709   {
3710     { Bad_Opcode },
3711     { Bad_Opcode },
3712     { "haddpd", { XM, EXx } },
3713     { "haddps", { XM, EXx } },
3714   },
3715
3716   /* PREFIX_0F7D */
3717   {
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { "hsubpd", { XM, EXx } },
3721     { "hsubps", { XM, EXx } },
3722   },
3723
3724   /* PREFIX_0F7E */
3725   {
3726     { "movK",   { Edq, MX } },
3727     { "movq",   { XM, EXq } },
3728     { "movK",   { Edq, XM } },
3729   },
3730
3731   /* PREFIX_0F7F */
3732   {
3733     { "movq",   { EMS, MX } },
3734     { "movdqu", { EXxS, XM } },
3735     { "movdqa", { EXxS, XM } },
3736   },
3737
3738   /* PREFIX_0FAE_REG_0 */
3739   {
3740     { Bad_Opcode },
3741     { "rdfsbase", { Ev } },
3742   },
3743
3744   /* PREFIX_0FAE_REG_1 */
3745   {
3746     { Bad_Opcode },
3747     { "rdgsbase", { Ev } },
3748   },
3749
3750   /* PREFIX_0FAE_REG_2 */
3751   {
3752     { Bad_Opcode },
3753     { "wrfsbase", { Ev } },
3754   },
3755
3756   /* PREFIX_0FAE_REG_3 */
3757   {
3758     { Bad_Opcode },
3759     { "wrgsbase", { Ev } },
3760   },
3761
3762   /* PREFIX_0FB8 */
3763   {
3764     { Bad_Opcode },
3765     { "popcntS", { Gv, Ev } },
3766   },
3767
3768   /* PREFIX_0FBC */
3769   {
3770     { "bsfS",   { Gv, Ev } },
3771     { "tzcntS", { Gv, Ev } },
3772     { "bsfS",   { Gv, Ev } },
3773   },
3774
3775   /* PREFIX_0FBD */
3776   {
3777     { "bsrS",   { Gv, Ev } },
3778     { "lzcntS", { Gv, Ev } },
3779     { "bsrS",   { Gv, Ev } },
3780   },
3781
3782   /* PREFIX_0FC2 */
3783   {
3784     { "cmpps",  { XM, EXx, CMP } },
3785     { "cmpss",  { XM, EXd, CMP } },
3786     { "cmppd",  { XM, EXx, CMP } },
3787     { "cmpsd",  { XM, EXq, CMP } },
3788   },
3789
3790   /* PREFIX_0FC3 */
3791   {
3792     { "movntiS", { Ma, Gv } },
3793   },
3794
3795   /* PREFIX_0FC7_REG_6 */
3796   {
3797     { "vmptrld",{ Mq } },
3798     { "vmxon",  { Mq } },
3799     { "vmclear",{ Mq } },
3800   },
3801
3802   /* PREFIX_0FD0 */
3803   {
3804     { Bad_Opcode },
3805     { Bad_Opcode },
3806     { "addsubpd", { XM, EXx } },
3807     { "addsubps", { XM, EXx } },
3808   },
3809
3810   /* PREFIX_0FD6 */
3811   {
3812     { Bad_Opcode },
3813     { "movq2dq",{ XM, MS } },
3814     { "movq",   { EXqS, XM } },
3815     { "movdq2q",{ MX, XS } },
3816   },
3817
3818   /* PREFIX_0FE6 */
3819   {
3820     { Bad_Opcode },
3821     { "cvtdq2pd", { XM, EXq } },
3822     { "cvttpd2dq", { XM, EXx } },
3823     { "cvtpd2dq", { XM, EXx } },
3824   },
3825
3826   /* PREFIX_0FE7 */
3827   {
3828     { "movntq", { Mq, MX } },
3829     { Bad_Opcode },
3830     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3831   },
3832
3833   /* PREFIX_0FF0 */
3834   {
3835     { Bad_Opcode },
3836     { Bad_Opcode },
3837     { Bad_Opcode },
3838     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3839   },
3840
3841   /* PREFIX_0FF7 */
3842   {
3843     { "maskmovq", { MX, MS } },
3844     { Bad_Opcode },
3845     { "maskmovdqu", { XM, XS } },
3846   },
3847
3848   /* PREFIX_0F3810 */
3849   {
3850     { Bad_Opcode },
3851     { Bad_Opcode },
3852     { "pblendvb", { XM, EXx, XMM0 } },
3853   },
3854
3855   /* PREFIX_0F3814 */
3856   {
3857     { Bad_Opcode },
3858     { Bad_Opcode },
3859     { "blendvps", { XM, EXx, XMM0 } },
3860   },
3861
3862   /* PREFIX_0F3815 */
3863   {
3864     { Bad_Opcode },
3865     { Bad_Opcode },
3866     { "blendvpd", { XM, EXx, XMM0 } },
3867   },
3868
3869   /* PREFIX_0F3817 */
3870   {
3871     { Bad_Opcode },
3872     { Bad_Opcode },
3873     { "ptest",  { XM, EXx } },
3874   },
3875
3876   /* PREFIX_0F3820 */
3877   {
3878     { Bad_Opcode },
3879     { Bad_Opcode },
3880     { "pmovsxbw", { XM, EXq } },
3881   },
3882
3883   /* PREFIX_0F3821 */
3884   {
3885     { Bad_Opcode },
3886     { Bad_Opcode },
3887     { "pmovsxbd", { XM, EXd } },
3888   },
3889
3890   /* PREFIX_0F3822 */
3891   {
3892     { Bad_Opcode },
3893     { Bad_Opcode },
3894     { "pmovsxbq", { XM, EXw } },
3895   },
3896
3897   /* PREFIX_0F3823 */
3898   {
3899     { Bad_Opcode },
3900     { Bad_Opcode },
3901     { "pmovsxwd", { XM, EXq } },
3902   },
3903
3904   /* PREFIX_0F3824 */
3905   {
3906     { Bad_Opcode },
3907     { Bad_Opcode },
3908     { "pmovsxwq", { XM, EXd } },
3909   },
3910
3911   /* PREFIX_0F3825 */
3912   {
3913     { Bad_Opcode },
3914     { Bad_Opcode },
3915     { "pmovsxdq", { XM, EXq } },
3916   },
3917
3918   /* PREFIX_0F3828 */
3919   {
3920     { Bad_Opcode },
3921     { Bad_Opcode },
3922     { "pmuldq", { XM, EXx } },
3923   },
3924
3925   /* PREFIX_0F3829 */
3926   {
3927     { Bad_Opcode },
3928     { Bad_Opcode },
3929     { "pcmpeqq", { XM, EXx } },
3930   },
3931
3932   /* PREFIX_0F382A */
3933   {
3934     { Bad_Opcode },
3935     { Bad_Opcode },
3936     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3937   },
3938
3939   /* PREFIX_0F382B */
3940   {
3941     { Bad_Opcode },
3942     { Bad_Opcode },
3943     { "packusdw", { XM, EXx } },
3944   },
3945
3946   /* PREFIX_0F3830 */
3947   {
3948     { Bad_Opcode },
3949     { Bad_Opcode },
3950     { "pmovzxbw", { XM, EXq } },
3951   },
3952
3953   /* PREFIX_0F3831 */
3954   {
3955     { Bad_Opcode },
3956     { Bad_Opcode },
3957     { "pmovzxbd", { XM, EXd } },
3958   },
3959
3960   /* PREFIX_0F3832 */
3961   {
3962     { Bad_Opcode },
3963     { Bad_Opcode },
3964     { "pmovzxbq", { XM, EXw } },
3965   },
3966
3967   /* PREFIX_0F3833 */
3968   {
3969     { Bad_Opcode },
3970     { Bad_Opcode },
3971     { "pmovzxwd", { XM, EXq } },
3972   },
3973
3974   /* PREFIX_0F3834 */
3975   {
3976     { Bad_Opcode },
3977     { Bad_Opcode },
3978     { "pmovzxwq", { XM, EXd } },
3979   },
3980
3981   /* PREFIX_0F3835 */
3982   {
3983     { Bad_Opcode },
3984     { Bad_Opcode },
3985     { "pmovzxdq", { XM, EXq } },
3986   },
3987
3988   /* PREFIX_0F3837 */
3989   {
3990     { Bad_Opcode },
3991     { Bad_Opcode },
3992     { "pcmpgtq", { XM, EXx } },
3993   },
3994
3995   /* PREFIX_0F3838 */
3996   {
3997     { Bad_Opcode },
3998     { Bad_Opcode },
3999     { "pminsb", { XM, EXx } },
4000   },
4001
4002   /* PREFIX_0F3839 */
4003   {
4004     { Bad_Opcode },
4005     { Bad_Opcode },
4006     { "pminsd", { XM, EXx } },
4007   },
4008
4009   /* PREFIX_0F383A */
4010   {
4011     { Bad_Opcode },
4012     { Bad_Opcode },
4013     { "pminuw", { XM, EXx } },
4014   },
4015
4016   /* PREFIX_0F383B */
4017   {
4018     { Bad_Opcode },
4019     { Bad_Opcode },
4020     { "pminud", { XM, EXx } },
4021   },
4022
4023   /* PREFIX_0F383C */
4024   {
4025     { Bad_Opcode },
4026     { Bad_Opcode },
4027     { "pmaxsb", { XM, EXx } },
4028   },
4029
4030   /* PREFIX_0F383D */
4031   {
4032     { Bad_Opcode },
4033     { Bad_Opcode },
4034     { "pmaxsd", { XM, EXx } },
4035   },
4036
4037   /* PREFIX_0F383E */
4038   {
4039     { Bad_Opcode },
4040     { Bad_Opcode },
4041     { "pmaxuw", { XM, EXx } },
4042   },
4043
4044   /* PREFIX_0F383F */
4045   {
4046     { Bad_Opcode },
4047     { Bad_Opcode },
4048     { "pmaxud", { XM, EXx } },
4049   },
4050
4051   /* PREFIX_0F3840 */
4052   {
4053     { Bad_Opcode },
4054     { Bad_Opcode },
4055     { "pmulld", { XM, EXx } },
4056   },
4057
4058   /* PREFIX_0F3841 */
4059   {
4060     { Bad_Opcode },
4061     { Bad_Opcode },
4062     { "phminposuw", { XM, EXx } },
4063   },
4064
4065   /* PREFIX_0F3880 */
4066   {
4067     { Bad_Opcode },
4068     { Bad_Opcode },
4069     { "invept", { Gm, Mo } },
4070   },
4071
4072   /* PREFIX_0F3881 */
4073   {
4074     { Bad_Opcode },
4075     { Bad_Opcode },
4076     { "invvpid", { Gm, Mo } },
4077   },
4078
4079   /* PREFIX_0F3882 */
4080   {
4081     { Bad_Opcode },
4082     { Bad_Opcode },
4083     { "invpcid", { Gm, M } },
4084   },
4085
4086   /* PREFIX_0F38C8 */
4087   {
4088     { "sha1nexte", { XM, EXxmm } },
4089   },
4090
4091   /* PREFIX_0F38C9 */
4092   {
4093     { "sha1msg1", { XM, EXxmm } },
4094   },
4095
4096   /* PREFIX_0F38CA */
4097   {
4098     { "sha1msg2", { XM, EXxmm } },
4099   },
4100
4101   /* PREFIX_0F38CB */
4102   {
4103     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4104   },
4105
4106   /* PREFIX_0F38CC */
4107   {
4108     { "sha256msg1", { XM, EXxmm } },
4109   },
4110
4111   /* PREFIX_0F38CD */
4112   {
4113     { "sha256msg2", { XM, EXxmm } },
4114   },
4115
4116   /* PREFIX_0F38DB */
4117   {
4118     { Bad_Opcode },
4119     { Bad_Opcode },
4120     { "aesimc", { XM, EXx } },
4121   },
4122
4123   /* PREFIX_0F38DC */
4124   {
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { "aesenc", { XM, EXx } },
4128   },
4129
4130   /* PREFIX_0F38DD */
4131   {
4132     { Bad_Opcode },
4133     { Bad_Opcode },
4134     { "aesenclast", { XM, EXx } },
4135   },
4136
4137   /* PREFIX_0F38DE */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { "aesdec", { XM, EXx } },
4142   },
4143
4144   /* PREFIX_0F38DF */
4145   {
4146     { Bad_Opcode },
4147     { Bad_Opcode },
4148     { "aesdeclast", { XM, EXx } },
4149   },
4150
4151   /* PREFIX_0F38F0 */
4152   {
4153     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4154     { Bad_Opcode },
4155     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4156     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4157   },
4158
4159   /* PREFIX_0F38F1 */
4160   {
4161     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4162     { Bad_Opcode },
4163     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4164     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4165   },
4166
4167   /* PREFIX_0F38F6 */
4168   {
4169     { Bad_Opcode },
4170     { "adoxS",  { Gdq, Edq} },
4171     { "adcxS",  { Gdq, Edq} },
4172     { Bad_Opcode },
4173   },
4174
4175   /* PREFIX_0F3A08 */
4176   {
4177     { Bad_Opcode },
4178     { Bad_Opcode },
4179     { "roundps", { XM, EXx, Ib } },
4180   },
4181
4182   /* PREFIX_0F3A09 */
4183   {
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { "roundpd", { XM, EXx, Ib } },
4187   },
4188
4189   /* PREFIX_0F3A0A */
4190   {
4191     { Bad_Opcode },
4192     { Bad_Opcode },
4193     { "roundss", { XM, EXd, Ib } },
4194   },
4195
4196   /* PREFIX_0F3A0B */
4197   {
4198     { Bad_Opcode },
4199     { Bad_Opcode },
4200     { "roundsd", { XM, EXq, Ib } },
4201   },
4202
4203   /* PREFIX_0F3A0C */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { "blendps", { XM, EXx, Ib } },
4208   },
4209
4210   /* PREFIX_0F3A0D */
4211   {
4212     { Bad_Opcode },
4213     { Bad_Opcode },
4214     { "blendpd", { XM, EXx, Ib } },
4215   },
4216
4217   /* PREFIX_0F3A0E */
4218   {
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { "pblendw", { XM, EXx, Ib } },
4222   },
4223
4224   /* PREFIX_0F3A14 */
4225   {
4226     { Bad_Opcode },
4227     { Bad_Opcode },
4228     { "pextrb", { Edqb, XM, Ib } },
4229   },
4230
4231   /* PREFIX_0F3A15 */
4232   {
4233     { Bad_Opcode },
4234     { Bad_Opcode },
4235     { "pextrw", { Edqw, XM, Ib } },
4236   },
4237
4238   /* PREFIX_0F3A16 */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { "pextrK", { Edq, XM, Ib } },
4243   },
4244
4245   /* PREFIX_0F3A17 */
4246   {
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { "extractps", { Edqd, XM, Ib } },
4250   },
4251
4252   /* PREFIX_0F3A20 */
4253   {
4254     { Bad_Opcode },
4255     { Bad_Opcode },
4256     { "pinsrb", { XM, Edqb, Ib } },
4257   },
4258
4259   /* PREFIX_0F3A21 */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "insertps", { XM, EXd, Ib } },
4264   },
4265
4266   /* PREFIX_0F3A22 */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { "pinsrK", { XM, Edq, Ib } },
4271   },
4272
4273   /* PREFIX_0F3A40 */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "dpps",   { XM, EXx, Ib } },
4278   },
4279
4280   /* PREFIX_0F3A41 */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { "dppd",   { XM, EXx, Ib } },
4285   },
4286
4287   /* PREFIX_0F3A42 */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "mpsadbw", { XM, EXx, Ib } },
4292   },
4293
4294   /* PREFIX_0F3A44 */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "pclmulqdq", { XM, EXx, PCLMUL } },
4299   },
4300
4301   /* PREFIX_0F3A60 */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "pcmpestrm", { XM, EXx, Ib } },
4306   },
4307
4308   /* PREFIX_0F3A61 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "pcmpestri", { XM, EXx, Ib } },
4313   },
4314
4315   /* PREFIX_0F3A62 */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "pcmpistrm", { XM, EXx, Ib } },
4320   },
4321
4322   /* PREFIX_0F3A63 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "pcmpistri", { XM, EXx, Ib } },
4327   },
4328
4329   /* PREFIX_0F3ACC */
4330   {
4331     { "sha1rnds4", { XM, EXxmm, Ib } },
4332   },
4333
4334   /* PREFIX_0F3ADF */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { "aeskeygenassist", { XM, EXx, Ib } },
4339   },
4340
4341   /* PREFIX_VEX_0F10 */
4342   {
4343     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4344     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4345     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4346     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4347   },
4348
4349   /* PREFIX_VEX_0F11 */
4350   {
4351     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4352     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4353     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4354     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4355   },
4356
4357   /* PREFIX_VEX_0F12 */
4358   {
4359     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4360     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4361     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4362     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4363   },
4364
4365   /* PREFIX_VEX_0F16 */
4366   {
4367     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4368     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4369     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4370   },
4371
4372   /* PREFIX_VEX_0F2A */
4373   {
4374     { Bad_Opcode },
4375     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4376     { Bad_Opcode },
4377     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4378   },
4379
4380   /* PREFIX_VEX_0F2C */
4381   {
4382     { Bad_Opcode },
4383     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4384     { Bad_Opcode },
4385     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4386   },
4387
4388   /* PREFIX_VEX_0F2D */
4389   {
4390     { Bad_Opcode },
4391     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4392     { Bad_Opcode },
4393     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4394   },
4395
4396   /* PREFIX_VEX_0F2E */
4397   {
4398     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4399     { Bad_Opcode },
4400     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4401   },
4402
4403   /* PREFIX_VEX_0F2F */
4404   {
4405     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4406     { Bad_Opcode },
4407     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4408   },
4409
4410   /* PREFIX_VEX_0F41 */
4411   {
4412     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4413   },
4414
4415   /* PREFIX_VEX_0F42 */
4416   {
4417     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4418   },
4419
4420   /* PREFIX_VEX_0F44 */
4421   {
4422     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4423   },
4424
4425   /* PREFIX_VEX_0F45 */
4426   {
4427     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4428   },
4429
4430   /* PREFIX_VEX_0F46 */
4431   {
4432     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4433   },
4434
4435   /* PREFIX_VEX_0F47 */
4436   {
4437     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4438   },
4439
4440   /* PREFIX_VEX_0F4B */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4445   },
4446
4447   /* PREFIX_VEX_0F51 */
4448   {
4449     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4450     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4451     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4452     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4453   },
4454
4455   /* PREFIX_VEX_0F52 */
4456   {
4457     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4458     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4459   },
4460
4461   /* PREFIX_VEX_0F53 */
4462   {
4463     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4464     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4465   },
4466
4467   /* PREFIX_VEX_0F58 */
4468   {
4469     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4470     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4471     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4472     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4473   },
4474
4475   /* PREFIX_VEX_0F59 */
4476   {
4477     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4478     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4479     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4480     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4481   },
4482
4483   /* PREFIX_VEX_0F5A */
4484   {
4485     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4486     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4487     { "vcvtpd2ps%XY", { XMM, EXx } },
4488     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4489   },
4490
4491   /* PREFIX_VEX_0F5B */
4492   {
4493     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4494     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4495     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4496   },
4497
4498   /* PREFIX_VEX_0F5C */
4499   {
4500     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4501     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4502     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4503     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4504   },
4505
4506   /* PREFIX_VEX_0F5D */
4507   {
4508     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4509     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4510     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4511     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4512   },
4513
4514   /* PREFIX_VEX_0F5E */
4515   {
4516     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4517     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4518     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4519     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4520   },
4521
4522   /* PREFIX_VEX_0F5F */
4523   {
4524     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4525     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4526     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4527     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4528   },
4529
4530   /* PREFIX_VEX_0F60 */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4535   },
4536
4537   /* PREFIX_VEX_0F61 */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4542   },
4543
4544   /* PREFIX_VEX_0F62 */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4549   },
4550
4551   /* PREFIX_VEX_0F63 */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4556   },
4557
4558   /* PREFIX_VEX_0F64 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4563   },
4564
4565   /* PREFIX_VEX_0F65 */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4570   },
4571
4572   /* PREFIX_VEX_0F66 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4577   },
4578
4579   /* PREFIX_VEX_0F67 */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4584   },
4585
4586   /* PREFIX_VEX_0F68 */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4591   },
4592
4593   /* PREFIX_VEX_0F69 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4598   },
4599
4600   /* PREFIX_VEX_0F6A */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4605   },
4606
4607   /* PREFIX_VEX_0F6B */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4612   },
4613
4614   /* PREFIX_VEX_0F6C */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4619   },
4620
4621   /* PREFIX_VEX_0F6D */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4626   },
4627
4628   /* PREFIX_VEX_0F6E */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4633   },
4634
4635   /* PREFIX_VEX_0F6F */
4636   {
4637     { Bad_Opcode },
4638     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4639     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4640   },
4641
4642   /* PREFIX_VEX_0F70 */
4643   {
4644     { Bad_Opcode },
4645     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4646     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4647     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4648   },
4649
4650   /* PREFIX_VEX_0F71_REG_2 */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4655   },
4656
4657   /* PREFIX_VEX_0F71_REG_4 */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4662   },
4663
4664   /* PREFIX_VEX_0F71_REG_6 */
4665   {
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4669   },
4670
4671   /* PREFIX_VEX_0F72_REG_2 */
4672   {
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4676   },
4677
4678   /* PREFIX_VEX_0F72_REG_4 */
4679   {
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4683   },
4684
4685   /* PREFIX_VEX_0F72_REG_6 */
4686   {
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4690   },
4691
4692   /* PREFIX_VEX_0F73_REG_2 */
4693   {
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4697   },
4698
4699   /* PREFIX_VEX_0F73_REG_3 */
4700   {
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4704   },
4705
4706   /* PREFIX_VEX_0F73_REG_6 */
4707   {
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4711   },
4712
4713   /* PREFIX_VEX_0F73_REG_7 */
4714   {
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4718   },
4719
4720   /* PREFIX_VEX_0F74 */
4721   {
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4725   },
4726
4727   /* PREFIX_VEX_0F75 */
4728   {
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4732   },
4733
4734   /* PREFIX_VEX_0F76 */
4735   {
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4739   },
4740
4741   /* PREFIX_VEX_0F77 */
4742   {
4743     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4744   },
4745
4746   /* PREFIX_VEX_0F7C */
4747   {
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4751     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4752   },
4753
4754   /* PREFIX_VEX_0F7D */
4755   {
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4759     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4760   },
4761
4762   /* PREFIX_VEX_0F7E */
4763   {
4764     { Bad_Opcode },
4765     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4766     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4767   },
4768
4769   /* PREFIX_VEX_0F7F */
4770   {
4771     { Bad_Opcode },
4772     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4773     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4774   },
4775
4776   /* PREFIX_VEX_0F90 */
4777   {
4778     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4779   },
4780
4781   /* PREFIX_VEX_0F91 */
4782   {
4783     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4784   },
4785
4786   /* PREFIX_VEX_0F92 */
4787   {
4788     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4789   },
4790
4791   /* PREFIX_VEX_0F93 */
4792   {
4793     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4794   },
4795
4796   /* PREFIX_VEX_0F98 */
4797   {
4798     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4799   },
4800
4801   /* PREFIX_VEX_0FC2 */
4802   {
4803     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4804     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4805     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4806     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4807   },
4808
4809   /* PREFIX_VEX_0FC4 */
4810   {
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4814   },
4815
4816   /* PREFIX_VEX_0FC5 */
4817   {
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4821   },
4822
4823   /* PREFIX_VEX_0FD0 */
4824   {
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4828     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4829   },
4830
4831   /* PREFIX_VEX_0FD1 */
4832   {
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4836   },
4837
4838   /* PREFIX_VEX_0FD2 */
4839   {
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4843   },
4844
4845   /* PREFIX_VEX_0FD3 */
4846   {
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4850   },
4851
4852   /* PREFIX_VEX_0FD4 */
4853   {
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4857   },
4858
4859   /* PREFIX_VEX_0FD5 */
4860   {
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4864   },
4865
4866   /* PREFIX_VEX_0FD6 */
4867   {
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4871   },
4872
4873   /* PREFIX_VEX_0FD7 */
4874   {
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4878   },
4879
4880   /* PREFIX_VEX_0FD8 */
4881   {
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4885   },
4886
4887   /* PREFIX_VEX_0FD9 */
4888   {
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4892   },
4893
4894   /* PREFIX_VEX_0FDA */
4895   {
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4899   },
4900
4901   /* PREFIX_VEX_0FDB */
4902   {
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4906   },
4907
4908   /* PREFIX_VEX_0FDC */
4909   {
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4913   },
4914
4915   /* PREFIX_VEX_0FDD */
4916   {
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4920   },
4921
4922   /* PREFIX_VEX_0FDE */
4923   {
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4927   },
4928
4929   /* PREFIX_VEX_0FDF */
4930   {
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4934   },
4935
4936   /* PREFIX_VEX_0FE0 */
4937   {
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4941   },
4942
4943   /* PREFIX_VEX_0FE1 */
4944   {
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4948   },
4949
4950   /* PREFIX_VEX_0FE2 */
4951   {
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4955   },
4956
4957   /* PREFIX_VEX_0FE3 */
4958   {
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4962   },
4963
4964   /* PREFIX_VEX_0FE4 */
4965   {
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4969   },
4970
4971   /* PREFIX_VEX_0FE5 */
4972   {
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4976   },
4977
4978   /* PREFIX_VEX_0FE6 */
4979   {
4980     { Bad_Opcode },
4981     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4982     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4983     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4984   },
4985
4986   /* PREFIX_VEX_0FE7 */
4987   {
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4991   },
4992
4993   /* PREFIX_VEX_0FE8 */
4994   {
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4998   },
4999
5000   /* PREFIX_VEX_0FE9 */
5001   {
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5005   },
5006
5007   /* PREFIX_VEX_0FEA */
5008   {
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5012   },
5013
5014   /* PREFIX_VEX_0FEB */
5015   {
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5019   },
5020
5021   /* PREFIX_VEX_0FEC */
5022   {
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5026   },
5027
5028   /* PREFIX_VEX_0FED */
5029   {
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5033   },
5034
5035   /* PREFIX_VEX_0FEE */
5036   {
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5040   },
5041
5042   /* PREFIX_VEX_0FEF */
5043   {
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5047   },
5048
5049   /* PREFIX_VEX_0FF0 */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5055   },
5056
5057   /* PREFIX_VEX_0FF1 */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5062   },
5063
5064   /* PREFIX_VEX_0FF2 */
5065   {
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5069   },
5070
5071   /* PREFIX_VEX_0FF3 */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5076   },
5077
5078   /* PREFIX_VEX_0FF4 */
5079   {
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5083   },
5084
5085   /* PREFIX_VEX_0FF5 */
5086   {
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5090   },
5091
5092   /* PREFIX_VEX_0FF6 */
5093   {
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5097   },
5098
5099   /* PREFIX_VEX_0FF7 */
5100   {
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5104   },
5105
5106   /* PREFIX_VEX_0FF8 */
5107   {
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5111   },
5112
5113   /* PREFIX_VEX_0FF9 */
5114   {
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5118   },
5119
5120   /* PREFIX_VEX_0FFA */
5121   {
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5125   },
5126
5127   /* PREFIX_VEX_0FFB */
5128   {
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5132   },
5133
5134   /* PREFIX_VEX_0FFC */
5135   {
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5139   },
5140
5141   /* PREFIX_VEX_0FFD */
5142   {
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5146   },
5147
5148   /* PREFIX_VEX_0FFE */
5149   {
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5153   },
5154
5155   /* PREFIX_VEX_0F3800 */
5156   {
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5160   },
5161
5162   /* PREFIX_VEX_0F3801 */
5163   {
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0F3802 */
5170   {
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5174   },
5175
5176   /* PREFIX_VEX_0F3803 */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5181   },
5182
5183   /* PREFIX_VEX_0F3804 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5188   },
5189
5190   /* PREFIX_VEX_0F3805 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5195   },
5196
5197   /* PREFIX_VEX_0F3806 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5202   },
5203
5204   /* PREFIX_VEX_0F3807 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5209   },
5210
5211   /* PREFIX_VEX_0F3808 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5216   },
5217
5218   /* PREFIX_VEX_0F3809 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5223   },
5224
5225   /* PREFIX_VEX_0F380A */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0F380B */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0F380C */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0F380D */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5251   },
5252
5253   /* PREFIX_VEX_0F380E */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0F380F */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0F3813 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vcvtph2ps", { XM, EXxmmq } },
5272   },
5273
5274   /* PREFIX_VEX_0F3816 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5279   },
5280
5281   /* PREFIX_VEX_0F3817 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5286   },
5287
5288   /* PREFIX_VEX_0F3818 */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5293   },
5294
5295   /* PREFIX_VEX_0F3819 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5300   },
5301
5302   /* PREFIX_VEX_0F381A */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5307   },
5308
5309   /* PREFIX_VEX_0F381C */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5314   },
5315
5316   /* PREFIX_VEX_0F381D */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5321   },
5322
5323   /* PREFIX_VEX_0F381E */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5328   },
5329
5330   /* PREFIX_VEX_0F3820 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5335   },
5336
5337   /* PREFIX_VEX_0F3821 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5342   },
5343
5344   /* PREFIX_VEX_0F3822 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0F3823 */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5356   },
5357
5358   /* PREFIX_VEX_0F3824 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5363   },
5364
5365   /* PREFIX_VEX_0F3825 */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5370   },
5371
5372   /* PREFIX_VEX_0F3828 */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5377   },
5378
5379   /* PREFIX_VEX_0F3829 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5384   },
5385
5386   /* PREFIX_VEX_0F382A */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5391   },
5392
5393   /* PREFIX_VEX_0F382B */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5398   },
5399
5400   /* PREFIX_VEX_0F382C */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5405   },
5406
5407   /* PREFIX_VEX_0F382D */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5412   },
5413
5414   /* PREFIX_VEX_0F382E */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5419   },
5420
5421   /* PREFIX_VEX_0F382F */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5426   },
5427
5428   /* PREFIX_VEX_0F3830 */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5433   },
5434
5435   /* PREFIX_VEX_0F3831 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5440   },
5441
5442   /* PREFIX_VEX_0F3832 */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5447   },
5448
5449   /* PREFIX_VEX_0F3833 */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5454   },
5455
5456   /* PREFIX_VEX_0F3834 */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5461   },
5462
5463   /* PREFIX_VEX_0F3835 */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5468   },
5469
5470   /* PREFIX_VEX_0F3836 */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5475   },
5476
5477   /* PREFIX_VEX_0F3837 */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5482   },
5483
5484   /* PREFIX_VEX_0F3838 */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5489   },
5490
5491   /* PREFIX_VEX_0F3839 */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5496   },
5497
5498   /* PREFIX_VEX_0F383A */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5503   },
5504
5505   /* PREFIX_VEX_0F383B */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5510   },
5511
5512   /* PREFIX_VEX_0F383C */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5517   },
5518
5519   /* PREFIX_VEX_0F383D */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5524   },
5525
5526   /* PREFIX_VEX_0F383E */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5531   },
5532
5533   /* PREFIX_VEX_0F383F */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5538   },
5539
5540   /* PREFIX_VEX_0F3840 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5545   },
5546
5547   /* PREFIX_VEX_0F3841 */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5552   },
5553
5554   /* PREFIX_VEX_0F3845 */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { "vpsrlv%LW", { XM, Vex, EXx } },
5559   },
5560
5561   /* PREFIX_VEX_0F3846 */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5566   },
5567
5568   /* PREFIX_VEX_0F3847 */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { "vpsllv%LW", { XM, Vex, EXx } },
5573   },
5574
5575   /* PREFIX_VEX_0F3858 */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5580   },
5581
5582   /* PREFIX_VEX_0F3859 */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0F385A */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5594   },
5595
5596   /* PREFIX_VEX_0F3878 */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0F3879 */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5608   },
5609
5610   /* PREFIX_VEX_0F388C */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5615   },
5616
5617   /* PREFIX_VEX_0F388E */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5622   },
5623
5624   /* PREFIX_VEX_0F3890 */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5629   },
5630
5631   /* PREFIX_VEX_0F3891 */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5636   },
5637
5638   /* PREFIX_VEX_0F3892 */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5643   },
5644
5645   /* PREFIX_VEX_0F3893 */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5650   },
5651
5652   /* PREFIX_VEX_0F3896 */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5657   },
5658
5659   /* PREFIX_VEX_0F3897 */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5664   },
5665
5666   /* PREFIX_VEX_0F3898 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { "vfmadd132p%XW", { XM, Vex, EXx } },
5671   },
5672
5673   /* PREFIX_VEX_0F3899 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5678   },
5679
5680   /* PREFIX_VEX_0F389A */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { "vfmsub132p%XW", { XM, Vex, EXx } },
5685   },
5686
5687   /* PREFIX_VEX_0F389B */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5692   },
5693
5694   /* PREFIX_VEX_0F389C */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5699   },
5700
5701   /* PREFIX_VEX_0F389D */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5706   },
5707
5708   /* PREFIX_VEX_0F389E */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5713   },
5714
5715   /* PREFIX_VEX_0F389F */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5720   },
5721
5722   /* PREFIX_VEX_0F38A6 */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5727     { Bad_Opcode },
5728   },
5729
5730   /* PREFIX_VEX_0F38A7 */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5735   },
5736
5737   /* PREFIX_VEX_0F38A8 */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { "vfmadd213p%XW", { XM, Vex, EXx } },
5742   },
5743
5744   /* PREFIX_VEX_0F38A9 */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5749   },
5750
5751   /* PREFIX_VEX_0F38AA */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { "vfmsub213p%XW", { XM, Vex, EXx } },
5756   },
5757
5758   /* PREFIX_VEX_0F38AB */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5763   },
5764
5765   /* PREFIX_VEX_0F38AC */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5770   },
5771
5772   /* PREFIX_VEX_0F38AD */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5777   },
5778
5779   /* PREFIX_VEX_0F38AE */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5784   },
5785
5786   /* PREFIX_VEX_0F38AF */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5791   },
5792
5793   /* PREFIX_VEX_0F38B6 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5798   },
5799
5800   /* PREFIX_VEX_0F38B7 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5805   },
5806
5807   /* PREFIX_VEX_0F38B8 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { "vfmadd231p%XW", { XM, Vex, EXx } },
5812   },
5813
5814   /* PREFIX_VEX_0F38B9 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5819   },
5820
5821   /* PREFIX_VEX_0F38BA */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { "vfmsub231p%XW", { XM, Vex, EXx } },
5826   },
5827
5828   /* PREFIX_VEX_0F38BB */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5833   },
5834
5835   /* PREFIX_VEX_0F38BC */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5840   },
5841
5842   /* PREFIX_VEX_0F38BD */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5847   },
5848
5849   /* PREFIX_VEX_0F38BE */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5854   },
5855
5856   /* PREFIX_VEX_0F38BF */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5861   },
5862
5863   /* PREFIX_VEX_0F38DB */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5868   },
5869
5870   /* PREFIX_VEX_0F38DC */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5875   },
5876
5877   /* PREFIX_VEX_0F38DD */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5882   },
5883
5884   /* PREFIX_VEX_0F38DE */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5889   },
5890
5891   /* PREFIX_VEX_0F38DF */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F38F2 */
5899   {
5900     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5901   },
5902
5903   /* PREFIX_VEX_0F38F3_REG_1 */
5904   {
5905     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5906   },
5907
5908   /* PREFIX_VEX_0F38F3_REG_2 */
5909   {
5910     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5911   },
5912
5913   /* PREFIX_VEX_0F38F3_REG_3 */
5914   {
5915     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5916   },
5917
5918   /* PREFIX_VEX_0F38F5 */
5919   {
5920     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5921     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5922     { Bad_Opcode },
5923     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5924   },
5925
5926   /* PREFIX_VEX_0F38F6 */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5932   },
5933
5934   /* PREFIX_VEX_0F38F7 */
5935   {
5936     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5937     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5938     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5939     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5940   },
5941
5942   /* PREFIX_VEX_0F3A00 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5947   },
5948
5949   /* PREFIX_VEX_0F3A01 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F3A02 */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5961   },
5962
5963   /* PREFIX_VEX_0F3A04 */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5968   },
5969
5970   /* PREFIX_VEX_0F3A05 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5975   },
5976
5977   /* PREFIX_VEX_0F3A06 */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5982   },
5983
5984   /* PREFIX_VEX_0F3A08 */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5989   },
5990
5991   /* PREFIX_VEX_0F3A09 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5996   },
5997
5998   /* PREFIX_VEX_0F3A0A */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6003   },
6004
6005   /* PREFIX_VEX_0F3A0B */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6010   },
6011
6012   /* PREFIX_VEX_0F3A0C */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6017   },
6018
6019   /* PREFIX_VEX_0F3A0D */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6024   },
6025
6026   /* PREFIX_VEX_0F3A0E */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6031   },
6032
6033   /* PREFIX_VEX_0F3A0F */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6038   },
6039
6040   /* PREFIX_VEX_0F3A14 */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6045   },
6046
6047   /* PREFIX_VEX_0F3A15 */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6052   },
6053
6054   /* PREFIX_VEX_0F3A16 */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6059   },
6060
6061   /* PREFIX_VEX_0F3A17 */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6066   },
6067
6068   /* PREFIX_VEX_0F3A18 */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6073   },
6074
6075   /* PREFIX_VEX_0F3A19 */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6080   },
6081
6082   /* PREFIX_VEX_0F3A1D */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6087   },
6088
6089   /* PREFIX_VEX_0F3A20 */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6094   },
6095
6096   /* PREFIX_VEX_0F3A21 */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6101   },
6102
6103   /* PREFIX_VEX_0F3A22 */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6108   },
6109
6110   /* PREFIX_VEX_0F3A30 */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6115   },
6116
6117   /* PREFIX_VEX_0F3A32 */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6122   },
6123
6124   /* PREFIX_VEX_0F3A38 */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6129   },
6130
6131   /* PREFIX_VEX_0F3A39 */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6136   },
6137
6138   /* PREFIX_VEX_0F3A40 */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6143   },
6144
6145   /* PREFIX_VEX_0F3A41 */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6150   },
6151
6152   /* PREFIX_VEX_0F3A42 */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6157   },
6158
6159   /* PREFIX_VEX_0F3A44 */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6164   },
6165
6166   /* PREFIX_VEX_0F3A46 */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6171   },
6172
6173   /* PREFIX_VEX_0F3A48 */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6178   },
6179
6180   /* PREFIX_VEX_0F3A49 */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6185   },
6186
6187   /* PREFIX_VEX_0F3A4A */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6192   },
6193
6194   /* PREFIX_VEX_0F3A4B */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6199   },
6200
6201   /* PREFIX_VEX_0F3A4C */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6206   },
6207
6208   /* PREFIX_VEX_0F3A5C */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6213   },
6214
6215   /* PREFIX_VEX_0F3A5D */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6220   },
6221
6222   /* PREFIX_VEX_0F3A5E */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6227   },
6228
6229   /* PREFIX_VEX_0F3A5F */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6234   },
6235
6236   /* PREFIX_VEX_0F3A60 */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6241     { Bad_Opcode },
6242   },
6243
6244   /* PREFIX_VEX_0F3A61 */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6249   },
6250
6251   /* PREFIX_VEX_0F3A62 */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6256   },
6257
6258   /* PREFIX_VEX_0F3A63 */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6263   },
6264
6265   /* PREFIX_VEX_0F3A68 */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6270   },
6271
6272   /* PREFIX_VEX_0F3A69 */
6273   {
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6277   },
6278
6279   /* PREFIX_VEX_0F3A6A */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6284   },
6285
6286   /* PREFIX_VEX_0F3A6B */
6287   {
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6291   },
6292
6293   /* PREFIX_VEX_0F3A6C */
6294   {
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6298   },
6299
6300   /* PREFIX_VEX_0F3A6D */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6305   },
6306
6307   /* PREFIX_VEX_0F3A6E */
6308   {
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6312   },
6313
6314   /* PREFIX_VEX_0F3A6F */
6315   {
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6319   },
6320
6321   /* PREFIX_VEX_0F3A78 */
6322   {
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6326   },
6327
6328   /* PREFIX_VEX_0F3A79 */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6333   },
6334
6335   /* PREFIX_VEX_0F3A7A */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6340   },
6341
6342   /* PREFIX_VEX_0F3A7B */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6347   },
6348
6349   /* PREFIX_VEX_0F3A7C */
6350   {
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6354     { Bad_Opcode },
6355   },
6356
6357   /* PREFIX_VEX_0F3A7D */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6362   },
6363
6364   /* PREFIX_VEX_0F3A7E */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6369   },
6370
6371   /* PREFIX_VEX_0F3A7F */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3ADF */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3AF0 */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6391   },
6392
6393 #define NEED_PREFIX_TABLE
6394 #include "i386-dis-evex.h"
6395 #undef NEED_PREFIX_TABLE
6396 };
6397
6398 static const struct dis386 x86_64_table[][2] = {
6399   /* X86_64_06 */
6400   {
6401     { "pushP", { es } },
6402   },
6403
6404   /* X86_64_07 */
6405   {
6406     { "popP", { es } },
6407   },
6408
6409   /* X86_64_0D */
6410   {
6411     { "pushP", { cs } },
6412   },
6413
6414   /* X86_64_16 */
6415   {
6416     { "pushP", { ss } },
6417   },
6418
6419   /* X86_64_17 */
6420   {
6421     { "popP", { ss } },
6422   },
6423
6424   /* X86_64_1E */
6425   {
6426     { "pushP", { ds } },
6427   },
6428
6429   /* X86_64_1F */
6430   {
6431     { "popP", { ds } },
6432   },
6433
6434   /* X86_64_27 */
6435   {
6436     { "daa", { XX } },
6437   },
6438
6439   /* X86_64_2F */
6440   {
6441     { "das", { XX } },
6442   },
6443
6444   /* X86_64_37 */
6445   {
6446     { "aaa", { XX } },
6447   },
6448
6449   /* X86_64_3F */
6450   {
6451     { "aas", { XX } },
6452   },
6453
6454   /* X86_64_60 */
6455   {
6456     { "pushaP", { XX } },
6457   },
6458
6459   /* X86_64_61 */
6460   {
6461     { "popaP", { XX } },
6462   },
6463
6464   /* X86_64_62 */
6465   {
6466     { MOD_TABLE (MOD_62_32BIT) },
6467     { EVEX_TABLE (EVEX_0F) },
6468   },
6469
6470   /* X86_64_63 */
6471   {
6472     { "arpl", { Ew, Gw } },
6473     { "movs{lq|xd}", { Gv, Ed } },
6474   },
6475
6476   /* X86_64_6D */
6477   {
6478     { "ins{R|}", { Yzr, indirDX } },
6479     { "ins{G|}", { Yzr, indirDX } },
6480   },
6481
6482   /* X86_64_6F */
6483   {
6484     { "outs{R|}", { indirDXr, Xz } },
6485     { "outs{G|}", { indirDXr, Xz } },
6486   },
6487
6488   /* X86_64_9A */
6489   {
6490     { "Jcall{T|}", { Ap } },
6491   },
6492
6493   /* X86_64_C4 */
6494   {
6495     { MOD_TABLE (MOD_C4_32BIT) },
6496     { VEX_C4_TABLE (VEX_0F) },
6497   },
6498
6499   /* X86_64_C5 */
6500   {
6501     { MOD_TABLE (MOD_C5_32BIT) },
6502     { VEX_C5_TABLE (VEX_0F) },
6503   },
6504
6505   /* X86_64_CE */
6506   {
6507     { "into", { XX } },
6508   },
6509
6510   /* X86_64_D4 */
6511   {
6512     { "aam", { Ib } },
6513   },
6514
6515   /* X86_64_D5 */
6516   {
6517     { "aad", { Ib } },
6518   },
6519
6520   /* X86_64_EA */
6521   {
6522     { "Jjmp{T|}", { Ap } },
6523   },
6524
6525   /* X86_64_0F01_REG_0 */
6526   {
6527     { "sgdt{Q|IQ}", { M } },
6528     { "sgdt", { M } },
6529   },
6530
6531   /* X86_64_0F01_REG_1 */
6532   {
6533     { "sidt{Q|IQ}", { M } },
6534     { "sidt", { M } },
6535   },
6536
6537   /* X86_64_0F01_REG_2 */
6538   {
6539     { "lgdt{Q|Q}", { M } },
6540     { "lgdt", { M } },
6541   },
6542
6543   /* X86_64_0F01_REG_3 */
6544   {
6545     { "lidt{Q|Q}", { M } },
6546     { "lidt", { M } },
6547   },
6548 };
6549
6550 static const struct dis386 three_byte_table[][256] = {
6551
6552   /* THREE_BYTE_0F38 */
6553   {
6554     /* 00 */
6555     { "pshufb",         { MX, EM } },
6556     { "phaddw",         { MX, EM } },
6557     { "phaddd",         { MX, EM } },
6558     { "phaddsw",        { MX, EM } },
6559     { "pmaddubsw",      { MX, EM } },
6560     { "phsubw",         { MX, EM } },
6561     { "phsubd",         { MX, EM } },
6562     { "phsubsw",        { MX, EM } },
6563     /* 08 */
6564     { "psignb",         { MX, EM } },
6565     { "psignw",         { MX, EM } },
6566     { "psignd",         { MX, EM } },
6567     { "pmulhrsw",       { MX, EM } },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     /* 10 */
6573     { PREFIX_TABLE (PREFIX_0F3810) },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { PREFIX_TABLE (PREFIX_0F3814) },
6578     { PREFIX_TABLE (PREFIX_0F3815) },
6579     { Bad_Opcode },
6580     { PREFIX_TABLE (PREFIX_0F3817) },
6581     /* 18 */
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { "pabsb",          { MX, EM } },
6587     { "pabsw",          { MX, EM } },
6588     { "pabsd",          { MX, EM } },
6589     { Bad_Opcode },
6590     /* 20 */
6591     { PREFIX_TABLE (PREFIX_0F3820) },
6592     { PREFIX_TABLE (PREFIX_0F3821) },
6593     { PREFIX_TABLE (PREFIX_0F3822) },
6594     { PREFIX_TABLE (PREFIX_0F3823) },
6595     { PREFIX_TABLE (PREFIX_0F3824) },
6596     { PREFIX_TABLE (PREFIX_0F3825) },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     /* 28 */
6600     { PREFIX_TABLE (PREFIX_0F3828) },
6601     { PREFIX_TABLE (PREFIX_0F3829) },
6602     { PREFIX_TABLE (PREFIX_0F382A) },
6603     { PREFIX_TABLE (PREFIX_0F382B) },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     /* 30 */
6609     { PREFIX_TABLE (PREFIX_0F3830) },
6610     { PREFIX_TABLE (PREFIX_0F3831) },
6611     { PREFIX_TABLE (PREFIX_0F3832) },
6612     { PREFIX_TABLE (PREFIX_0F3833) },
6613     { PREFIX_TABLE (PREFIX_0F3834) },
6614     { PREFIX_TABLE (PREFIX_0F3835) },
6615     { Bad_Opcode },
6616     { PREFIX_TABLE (PREFIX_0F3837) },
6617     /* 38 */
6618     { PREFIX_TABLE (PREFIX_0F3838) },
6619     { PREFIX_TABLE (PREFIX_0F3839) },
6620     { PREFIX_TABLE (PREFIX_0F383A) },
6621     { PREFIX_TABLE (PREFIX_0F383B) },
6622     { PREFIX_TABLE (PREFIX_0F383C) },
6623     { PREFIX_TABLE (PREFIX_0F383D) },
6624     { PREFIX_TABLE (PREFIX_0F383E) },
6625     { PREFIX_TABLE (PREFIX_0F383F) },
6626     /* 40 */
6627     { PREFIX_TABLE (PREFIX_0F3840) },
6628     { PREFIX_TABLE (PREFIX_0F3841) },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     /* 48 */
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     /* 50 */
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     /* 58 */
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     /* 60 */
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     /* 68 */
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     /* 70 */
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     /* 78 */
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     /* 80 */
6699     { PREFIX_TABLE (PREFIX_0F3880) },
6700     { PREFIX_TABLE (PREFIX_0F3881) },
6701     { PREFIX_TABLE (PREFIX_0F3882) },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     /* 88 */
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     /* 90 */
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     /* 98 */
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     /* a0 */
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     /* a8 */
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     /* b0 */
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     /* b8 */
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     /* c0 */
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     /* c8 */
6780     { PREFIX_TABLE (PREFIX_0F38C8) },
6781     { PREFIX_TABLE (PREFIX_0F38C9) },
6782     { PREFIX_TABLE (PREFIX_0F38CA) },
6783     { PREFIX_TABLE (PREFIX_0F38CB) },
6784     { PREFIX_TABLE (PREFIX_0F38CC) },
6785     { PREFIX_TABLE (PREFIX_0F38CD) },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     /* d0 */
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     /* d8 */
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { PREFIX_TABLE (PREFIX_0F38DB) },
6802     { PREFIX_TABLE (PREFIX_0F38DC) },
6803     { PREFIX_TABLE (PREFIX_0F38DD) },
6804     { PREFIX_TABLE (PREFIX_0F38DE) },
6805     { PREFIX_TABLE (PREFIX_0F38DF) },
6806     /* e0 */
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     /* e8 */
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     /* f0 */
6825     { PREFIX_TABLE (PREFIX_0F38F0) },
6826     { PREFIX_TABLE (PREFIX_0F38F1) },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { PREFIX_TABLE (PREFIX_0F38F6) },
6832     { Bad_Opcode },
6833     /* f8 */
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842   },
6843   /* THREE_BYTE_0F3A */
6844   {
6845     /* 00 */
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     /* 08 */
6855     { PREFIX_TABLE (PREFIX_0F3A08) },
6856     { PREFIX_TABLE (PREFIX_0F3A09) },
6857     { PREFIX_TABLE (PREFIX_0F3A0A) },
6858     { PREFIX_TABLE (PREFIX_0F3A0B) },
6859     { PREFIX_TABLE (PREFIX_0F3A0C) },
6860     { PREFIX_TABLE (PREFIX_0F3A0D) },
6861     { PREFIX_TABLE (PREFIX_0F3A0E) },
6862     { "palignr",        { MX, EM, Ib } },
6863     /* 10 */
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { PREFIX_TABLE (PREFIX_0F3A14) },
6869     { PREFIX_TABLE (PREFIX_0F3A15) },
6870     { PREFIX_TABLE (PREFIX_0F3A16) },
6871     { PREFIX_TABLE (PREFIX_0F3A17) },
6872     /* 18 */
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     /* 20 */
6882     { PREFIX_TABLE (PREFIX_0F3A20) },
6883     { PREFIX_TABLE (PREFIX_0F3A21) },
6884     { PREFIX_TABLE (PREFIX_0F3A22) },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     /* 28 */
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     /* 30 */
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     /* 38 */
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     /* 40 */
6918     { PREFIX_TABLE (PREFIX_0F3A40) },
6919     { PREFIX_TABLE (PREFIX_0F3A41) },
6920     { PREFIX_TABLE (PREFIX_0F3A42) },
6921     { Bad_Opcode },
6922     { PREFIX_TABLE (PREFIX_0F3A44) },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     /* 48 */
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     /* 50 */
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     /* 58 */
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     /* 60 */
6954     { PREFIX_TABLE (PREFIX_0F3A60) },
6955     { PREFIX_TABLE (PREFIX_0F3A61) },
6956     { PREFIX_TABLE (PREFIX_0F3A62) },
6957     { PREFIX_TABLE (PREFIX_0F3A63) },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     /* 68 */
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     /* 70 */
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     /* 78 */
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     /* 80 */
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     /* 88 */
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     /* 90 */
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     /* 98 */
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     /* a0 */
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* a8 */
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* b0 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* b8 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* c0 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* c8 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { PREFIX_TABLE (PREFIX_0F3ACC) },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* d0 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* d8 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { PREFIX_TABLE (PREFIX_0F3ADF) },
7097     /* e0 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* e8 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* f0 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* f8 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133   },
7134
7135   /* THREE_BYTE_0F7A */
7136   {
7137     /* 00 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* 08 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* 10 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* 18 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* 20 */
7174     { "ptest",          { XX } },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* 28 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* 30 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* 38 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* 40 */
7210     { Bad_Opcode },
7211     { "phaddbw",        { XM, EXq } },
7212     { "phaddbd",        { XM, EXq } },
7213     { "phaddbq",        { XM, EXq } },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { "phaddwd",        { XM, EXq } },
7217     { "phaddwq",        { XM, EXq } },
7218     /* 48 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { "phadddq",        { XM, EXq } },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     /* 50 */
7228     { Bad_Opcode },
7229     { "phaddubw",       { XM, EXq } },
7230     { "phaddubd",       { XM, EXq } },
7231     { "phaddubq",       { XM, EXq } },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { "phadduwd",       { XM, EXq } },
7235     { "phadduwq",       { XM, EXq } },
7236     /* 58 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { "phaddudq",       { XM, EXq } },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* 60 */
7246     { Bad_Opcode },
7247     { "phsubbw",        { XM, EXq } },
7248     { "phsubbd",        { XM, EXq } },
7249     { "phsubbq",        { XM, EXq } },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     /* 68 */
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     /* 70 */
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     /* 78 */
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     /* 80 */
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     /* 88 */
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     /* 90 */
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     /* 98 */
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* a0 */
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     /* a8 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* b0 */
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* b8 */
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     /* c0 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* c8 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     /* d0 */
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* d8 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* e0 */
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* e8 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     /* f0 */
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     /* f8 */
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425   },
7426 };
7427
7428 static const struct dis386 xop_table[][256] = {
7429   /* XOP_08 */
7430   {
7431     /* 00 */
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     /* 08 */
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     /* 10 */
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     /* 18 */
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     /* 20 */
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     /* 28 */
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     /* 30 */
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     /* 38 */
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     /* 40 */
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     /* 48 */
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     /* 50 */
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     /* 58 */
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     /* 60 */
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     /* 68 */
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     /* 70 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* 78 */
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* 80 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7582     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7583     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7584     /* 88 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7592     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7593     /* 90 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7600     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7601     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7602     /* 98 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7610     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7611     /* a0 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7615     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7619     { Bad_Opcode },
7620     /* a8 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* b0 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7637     { Bad_Opcode },
7638     /* b8 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* c0 */
7648     { "vprotb",         { XM, Vex_2src_1, Ib } },
7649     { "vprotw",         { XM, Vex_2src_1, Ib } },
7650     { "vprotd",         { XM, Vex_2src_1, Ib } },
7651     { "vprotq",         { XM, Vex_2src_1, Ib } },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* c8 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7662     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7663     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7664     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7665     /* d0 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* d8 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* e0 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* e8 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7698     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7699     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7700     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7701     /* f0 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     /* f8 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719   },
7720   /* XOP_09 */
7721   {
7722     /* 00 */
7723     { Bad_Opcode },
7724     { REG_TABLE (REG_XOP_TBM_01) },
7725     { REG_TABLE (REG_XOP_TBM_02) },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     /* 08 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     /* 10 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { REG_TABLE (REG_XOP_LWPCB) },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     /* 18 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* 20 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     /* 28 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* 30 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* 38 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* 40 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* 48 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* 50 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* 58 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* 60 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 68 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 70 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 78 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 80 */
7867     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7868     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7869     { "vfrczss",        { XM, EXd } },
7870     { "vfrczsd",        { XM, EXq } },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 88 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     /* 90 */
7885     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7886     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7887     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7888     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7889     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7890     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7891     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7892     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7893     /* 98 */
7894     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7895     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7896     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7897     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* a0 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* a8 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* b0 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* b8 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* c0 */
7939     { Bad_Opcode },
7940     { "vphaddbw",       { XM, EXxmm } },
7941     { "vphaddbd",       { XM, EXxmm } },
7942     { "vphaddbq",       { XM, EXxmm } },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { "vphaddwd",       { XM, EXxmm } },
7946     { "vphaddwq",       { XM, EXxmm } },
7947     /* c8 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { "vphadddq",       { XM, EXxmm } },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* d0 */
7957     { Bad_Opcode },
7958     { "vphaddubw",      { XM, EXxmm } },
7959     { "vphaddubd",      { XM, EXxmm } },
7960     { "vphaddubq",      { XM, EXxmm } },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { "vphadduwd",      { XM, EXxmm } },
7964     { "vphadduwq",      { XM, EXxmm } },
7965     /* d8 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { "vphaddudq",      { XM, EXxmm } },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* e0 */
7975     { Bad_Opcode },
7976     { "vphsubbw",       { XM, EXxmm } },
7977     { "vphsubwd",       { XM, EXxmm } },
7978     { "vphsubdq",       { XM, EXxmm } },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* e8 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* f0 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     /* f8 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010   },
8011   /* XOP_0A */
8012   {
8013     /* 00 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* 08 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* 10 */
8032     { "bextr",  { Gv, Ev, Iq } },
8033     { Bad_Opcode },
8034     { REG_TABLE (REG_XOP_LWP) },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* 18 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* 20 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* 28 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* 30 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* 38 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* 40 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* 48 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* 50 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* 58 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* 60 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* 68 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* 70 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 78 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 80 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 88 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* 90 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 98 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* a0 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* a8 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* b0 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* b8 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* c0 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* c8 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* d0 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* d8 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* e0 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* e8 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* f0 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* f8 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301   },
8302 };
8303
8304 static const struct dis386 vex_table[][256] = {
8305   /* VEX_0F */
8306   {
8307     /* 00 */
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     /* 08 */
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     /* 10 */
8326     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8327     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8328     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8329     { MOD_TABLE (MOD_VEX_0F13) },
8330     { VEX_W_TABLE (VEX_W_0F14) },
8331     { VEX_W_TABLE (VEX_W_0F15) },
8332     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8333     { MOD_TABLE (MOD_VEX_0F17) },
8334     /* 18 */
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     /* 20 */
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     /* 28 */
8353     { VEX_W_TABLE (VEX_W_0F28) },
8354     { VEX_W_TABLE (VEX_W_0F29) },
8355     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8356     { MOD_TABLE (MOD_VEX_0F2B) },
8357     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8358     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8359     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8360     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8361     /* 30 */
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     /* 38 */
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     /* 40 */
8380     { Bad_Opcode },
8381     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8382     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8383     { Bad_Opcode },
8384     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8385     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8386     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8387     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8388     /* 48 */
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     /* 50 */
8398     { MOD_TABLE (MOD_VEX_0F50) },
8399     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8400     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8401     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8402     { "vandpX",         { XM, Vex, EXx } },
8403     { "vandnpX",        { XM, Vex, EXx } },
8404     { "vorpX",          { XM, Vex, EXx } },
8405     { "vxorpX",         { XM, Vex, EXx } },
8406     /* 58 */
8407     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8408     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8409     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8410     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8411     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8412     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8413     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8414     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8415     /* 60 */
8416     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8417     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8418     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8419     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8424     /* 68 */
8425     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8427     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8433     /* 70 */
8434     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8435     { REG_TABLE (REG_VEX_0F71) },
8436     { REG_TABLE (REG_VEX_0F72) },
8437     { REG_TABLE (REG_VEX_0F73) },
8438     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8439     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8440     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8441     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8442     /* 78 */
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8449     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8450     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8451     /* 80 */
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     /* 88 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* 90 */
8470     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8471     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8472     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8473     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* 98 */
8479     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     /* a0 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* a8 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { REG_TABLE (REG_VEX_0FAE) },
8504     { Bad_Opcode },
8505     /* b0 */
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     /* b8 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* c0 */
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8527     { Bad_Opcode },
8528     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8529     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8530     { "vshufpX",        { XM, Vex, EXx, Ib } },
8531     { Bad_Opcode },
8532     /* c8 */
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     /* d0 */
8542     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8543     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8544     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8545     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8546     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8547     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8548     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8549     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8550     /* d8 */
8551     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8552     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8553     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8557     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8558     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8559     /* e0 */
8560     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8561     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8562     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8566     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8568     /* e8 */
8569     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8570     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8571     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8575     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8576     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8577     /* f0 */
8578     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8579     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8580     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8584     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8585     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8586     /* f8 */
8587     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8589     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8592     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8593     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8594     { Bad_Opcode },
8595   },
8596   /* VEX_0F38 */
8597   {
8598     /* 00 */
8599     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8607     /* 08 */
8608     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8616     /* 10 */
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8625     /* 18 */
8626     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8629     { Bad_Opcode },
8630     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8633     { Bad_Opcode },
8634     /* 20 */
8635     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     /* 28 */
8644     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8652     /* 30 */
8653     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8661     /* 38 */
8662     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8670     /* 40 */
8671     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8677     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8679     /* 48 */
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     /* 50 */
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     /* 58 */
8698     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     /* 60 */
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     /* 68 */
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     /* 70 */
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     /* 78 */
8734     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     /* 80 */
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     /* 88 */
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8757     { Bad_Opcode },
8758     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8759     { Bad_Opcode },
8760     /* 90 */
8761     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8769     /* 98 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8778     /* a0 */
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8787     /* a8 */
8788     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8796     /* b0 */
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8805     /* b8 */
8806     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8814     /* c0 */
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     /* c8 */
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     /* d0 */
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     /* d8 */
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8850     /* e0 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     /* e8 */
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     /* f0 */
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8872     { REG_TABLE (REG_VEX_0F38F3) },
8873     { Bad_Opcode },
8874     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8877     /* f8 */
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886   },
8887   /* VEX_0F3A */
8888   {
8889     /* 00 */
8890     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8893     { Bad_Opcode },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8897     { Bad_Opcode },
8898     /* 08 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8907     /* 10 */
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8916     /* 18 */
8917     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     /* 20 */
8926     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     /* 28 */
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     /* 30 */
8944     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8945     { Bad_Opcode },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     /* 38 */
8953     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     /* 40 */
8962     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8965     { Bad_Opcode },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8967     { Bad_Opcode },
8968     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8969     { Bad_Opcode },
8970     /* 48 */
8971     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     /* 50 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* 58 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8997     /* 60 */
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     /* 68 */
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9015     /* 70 */
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     /* 78 */
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9033     /* 80 */
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     /* 88 */
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     /* 90 */
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     /* 98 */
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     /* a0 */
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     /* a8 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* b0 */
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     /* b8 */
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* c0 */
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* c8 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     /* d0 */
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* d8 */
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9141     /* e0 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* e8 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     /* f0 */
9160     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     /* f8 */
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177   },
9178 };
9179
9180 #define NEED_OPCODE_TABLE
9181 #include "i386-dis-evex.h"
9182 #undef NEED_OPCODE_TABLE
9183 static const struct dis386 vex_len_table[][2] = {
9184   /* VEX_LEN_0F10_P_1 */
9185   {
9186     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9187     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9188   },
9189
9190   /* VEX_LEN_0F10_P_3 */
9191   {
9192     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9193     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9194   },
9195
9196   /* VEX_LEN_0F11_P_1 */
9197   {
9198     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9199     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9200   },
9201
9202   /* VEX_LEN_0F11_P_3 */
9203   {
9204     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9205     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9206   },
9207
9208   /* VEX_LEN_0F12_P_0_M_0 */
9209   {
9210     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9211   },
9212
9213   /* VEX_LEN_0F12_P_0_M_1 */
9214   {
9215     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9216   },
9217
9218   /* VEX_LEN_0F12_P_2 */
9219   {
9220     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9221   },
9222
9223   /* VEX_LEN_0F13_M_0 */
9224   {
9225     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9226   },
9227
9228   /* VEX_LEN_0F16_P_0_M_0 */
9229   {
9230     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9231   },
9232
9233   /* VEX_LEN_0F16_P_0_M_1 */
9234   {
9235     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9236   },
9237
9238   /* VEX_LEN_0F16_P_2 */
9239   {
9240     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9241   },
9242
9243   /* VEX_LEN_0F17_M_0 */
9244   {
9245     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9246   },
9247
9248   /* VEX_LEN_0F2A_P_1 */
9249   {
9250     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9251     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9252   },
9253
9254   /* VEX_LEN_0F2A_P_3 */
9255   {
9256     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9257     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9258   },
9259
9260   /* VEX_LEN_0F2C_P_1 */
9261   {
9262     { "vcvttss2siY",    { Gv, EXdScalar } },
9263     { "vcvttss2siY",    { Gv, EXdScalar } },
9264   },
9265
9266   /* VEX_LEN_0F2C_P_3 */
9267   {
9268     { "vcvttsd2siY",    { Gv, EXqScalar } },
9269     { "vcvttsd2siY",    { Gv, EXqScalar } },
9270   },
9271
9272   /* VEX_LEN_0F2D_P_1 */
9273   {
9274     { "vcvtss2siY",     { Gv, EXdScalar } },
9275     { "vcvtss2siY",     { Gv, EXdScalar } },
9276   },
9277
9278   /* VEX_LEN_0F2D_P_3 */
9279   {
9280     { "vcvtsd2siY",     { Gv, EXqScalar } },
9281     { "vcvtsd2siY",     { Gv, EXqScalar } },
9282   },
9283
9284   /* VEX_LEN_0F2E_P_0 */
9285   {
9286     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9287     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9288   },
9289
9290   /* VEX_LEN_0F2E_P_2 */
9291   {
9292     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9293     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9294   },
9295
9296   /* VEX_LEN_0F2F_P_0 */
9297   {
9298     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9299     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9300   },
9301
9302   /* VEX_LEN_0F2F_P_2 */
9303   {
9304     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9305     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9306   },
9307
9308   /* VEX_LEN_0F41_P_0 */
9309   {
9310     { Bad_Opcode },
9311     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9312   },
9313   /* VEX_LEN_0F42_P_0 */
9314   {
9315     { Bad_Opcode },
9316     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9317   },
9318   /* VEX_LEN_0F44_P_0 */
9319   {
9320     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9321   },
9322   /* VEX_LEN_0F45_P_0 */
9323   {
9324     { Bad_Opcode },
9325     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9326   },
9327   /* VEX_LEN_0F46_P_0 */
9328   {
9329     { Bad_Opcode },
9330     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9331   },
9332   /* VEX_LEN_0F47_P_0 */
9333   {
9334     { Bad_Opcode },
9335     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9336   },
9337   /* VEX_LEN_0F4B_P_2 */
9338   {
9339     { Bad_Opcode },
9340     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9341   },
9342
9343   /* VEX_LEN_0F51_P_1 */
9344   {
9345     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9346     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9347   },
9348
9349   /* VEX_LEN_0F51_P_3 */
9350   {
9351     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9352     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9353   },
9354
9355   /* VEX_LEN_0F52_P_1 */
9356   {
9357     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9358     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9359   },
9360
9361   /* VEX_LEN_0F53_P_1 */
9362   {
9363     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9364     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9365   },
9366
9367   /* VEX_LEN_0F58_P_1 */
9368   {
9369     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9370     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9371   },
9372
9373   /* VEX_LEN_0F58_P_3 */
9374   {
9375     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9376     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9377   },
9378
9379   /* VEX_LEN_0F59_P_1 */
9380   {
9381     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9382     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9383   },
9384
9385   /* VEX_LEN_0F59_P_3 */
9386   {
9387     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9388     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9389   },
9390
9391   /* VEX_LEN_0F5A_P_1 */
9392   {
9393     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9394     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9395   },
9396
9397   /* VEX_LEN_0F5A_P_3 */
9398   {
9399     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9400     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9401   },
9402
9403   /* VEX_LEN_0F5C_P_1 */
9404   {
9405     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9406     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9407   },
9408
9409   /* VEX_LEN_0F5C_P_3 */
9410   {
9411     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9412     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9413   },
9414
9415   /* VEX_LEN_0F5D_P_1 */
9416   {
9417     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9418     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9419   },
9420
9421   /* VEX_LEN_0F5D_P_3 */
9422   {
9423     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9424     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9425   },
9426
9427   /* VEX_LEN_0F5E_P_1 */
9428   {
9429     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9430     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9431   },
9432
9433   /* VEX_LEN_0F5E_P_3 */
9434   {
9435     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9436     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9437   },
9438
9439   /* VEX_LEN_0F5F_P_1 */
9440   {
9441     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9442     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9443   },
9444
9445   /* VEX_LEN_0F5F_P_3 */
9446   {
9447     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9448     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9449   },
9450
9451   /* VEX_LEN_0F6E_P_2 */
9452   {
9453     { "vmovK",          { XMScalar, Edq } },
9454     { "vmovK",          { XMScalar, Edq } },
9455   },
9456
9457   /* VEX_LEN_0F7E_P_1 */
9458   {
9459     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9460     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9461   },
9462
9463   /* VEX_LEN_0F7E_P_2 */
9464   {
9465     { "vmovK",          { Edq, XMScalar } },
9466     { "vmovK",          { Edq, XMScalar } },
9467   },
9468
9469   /* VEX_LEN_0F90_P_0 */
9470   {
9471     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9472   },
9473
9474   /* VEX_LEN_0F91_P_0 */
9475   {
9476     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9477   },
9478
9479   /* VEX_LEN_0F92_P_0 */
9480   {
9481     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9482   },
9483
9484   /* VEX_LEN_0F93_P_0 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9487   },
9488
9489   /* VEX_LEN_0F98_P_0 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9492   },
9493
9494   /* VEX_LEN_0FAE_R_2_M_0 */
9495   {
9496     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9497   },
9498
9499   /* VEX_LEN_0FAE_R_3_M_0 */
9500   {
9501     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9502   },
9503
9504   /* VEX_LEN_0FC2_P_1 */
9505   {
9506     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9507     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9508   },
9509
9510   /* VEX_LEN_0FC2_P_3 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9513     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9514   },
9515
9516   /* VEX_LEN_0FC4_P_2 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9519   },
9520
9521   /* VEX_LEN_0FC5_P_2 */
9522   {
9523     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9524   },
9525
9526   /* VEX_LEN_0FD6_P_2 */
9527   {
9528     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9529     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9530   },
9531
9532   /* VEX_LEN_0FF7_P_2 */
9533   {
9534     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9535   },
9536
9537   /* VEX_LEN_0F3816_P_2 */
9538   {
9539     { Bad_Opcode },
9540     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9541   },
9542
9543   /* VEX_LEN_0F3819_P_2 */
9544   {
9545     { Bad_Opcode },
9546     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9547   },
9548
9549   /* VEX_LEN_0F381A_P_2_M_0 */
9550   {
9551     { Bad_Opcode },
9552     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9553   },
9554
9555   /* VEX_LEN_0F3836_P_2 */
9556   {
9557     { Bad_Opcode },
9558     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9559   },
9560
9561   /* VEX_LEN_0F3841_P_2 */
9562   {
9563     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9564   },
9565
9566   /* VEX_LEN_0F385A_P_2_M_0 */
9567   {
9568     { Bad_Opcode },
9569     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9570   },
9571
9572   /* VEX_LEN_0F38DB_P_2 */
9573   {
9574     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9575   },
9576
9577   /* VEX_LEN_0F38DC_P_2 */
9578   {
9579     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9580   },
9581
9582   /* VEX_LEN_0F38DD_P_2 */
9583   {
9584     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9585   },
9586
9587   /* VEX_LEN_0F38DE_P_2 */
9588   {
9589     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9590   },
9591
9592   /* VEX_LEN_0F38DF_P_2 */
9593   {
9594     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9595   },
9596
9597   /* VEX_LEN_0F38F2_P_0 */
9598   {
9599     { "andnS",          { Gdq, VexGdq, Edq } },
9600   },
9601
9602   /* VEX_LEN_0F38F3_R_1_P_0 */
9603   {
9604     { "blsrS",          { VexGdq, Edq } },
9605   },
9606
9607   /* VEX_LEN_0F38F3_R_2_P_0 */
9608   {
9609     { "blsmskS",        { VexGdq, Edq } },
9610   },
9611
9612   /* VEX_LEN_0F38F3_R_3_P_0 */
9613   {
9614     { "blsiS",          { VexGdq, Edq } },
9615   },
9616
9617   /* VEX_LEN_0F38F5_P_0 */
9618   {
9619     { "bzhiS",          { Gdq, Edq, VexGdq } },
9620   },
9621
9622   /* VEX_LEN_0F38F5_P_1 */
9623   {
9624     { "pextS",          { Gdq, VexGdq, Edq } },
9625   },
9626
9627   /* VEX_LEN_0F38F5_P_3 */
9628   {
9629     { "pdepS",          { Gdq, VexGdq, Edq } },
9630   },
9631
9632   /* VEX_LEN_0F38F6_P_3 */
9633   {
9634     { "mulxS",          { Gdq, VexGdq, Edq } },
9635   },
9636
9637   /* VEX_LEN_0F38F7_P_0 */
9638   {
9639     { "bextrS",         { Gdq, Edq, VexGdq } },
9640   },
9641
9642   /* VEX_LEN_0F38F7_P_1 */
9643   {
9644     { "sarxS",          { Gdq, Edq, VexGdq } },
9645   },
9646
9647   /* VEX_LEN_0F38F7_P_2 */
9648   {
9649     { "shlxS",          { Gdq, Edq, VexGdq } },
9650   },
9651
9652   /* VEX_LEN_0F38F7_P_3 */
9653   {
9654     { "shrxS",          { Gdq, Edq, VexGdq } },
9655   },
9656
9657   /* VEX_LEN_0F3A00_P_2 */
9658   {
9659     { Bad_Opcode },
9660     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9661   },
9662
9663   /* VEX_LEN_0F3A01_P_2 */
9664   {
9665     { Bad_Opcode },
9666     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9667   },
9668
9669   /* VEX_LEN_0F3A06_P_2 */
9670   {
9671     { Bad_Opcode },
9672     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9673   },
9674
9675   /* VEX_LEN_0F3A0A_P_2 */
9676   {
9677     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9678     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9679   },
9680
9681   /* VEX_LEN_0F3A0B_P_2 */
9682   {
9683     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9684     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9685   },
9686
9687   /* VEX_LEN_0F3A14_P_2 */
9688   {
9689     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9690   },
9691
9692   /* VEX_LEN_0F3A15_P_2 */
9693   {
9694     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9695   },
9696
9697   /* VEX_LEN_0F3A16_P_2  */
9698   {
9699     { "vpextrK",        { Edq, XM, Ib } },
9700   },
9701
9702   /* VEX_LEN_0F3A17_P_2 */
9703   {
9704     { "vextractps",     { Edqd, XM, Ib } },
9705   },
9706
9707   /* VEX_LEN_0F3A18_P_2 */
9708   {
9709     { Bad_Opcode },
9710     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9711   },
9712
9713   /* VEX_LEN_0F3A19_P_2 */
9714   {
9715     { Bad_Opcode },
9716     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9717   },
9718
9719   /* VEX_LEN_0F3A20_P_2 */
9720   {
9721     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9722   },
9723
9724   /* VEX_LEN_0F3A21_P_2 */
9725   {
9726     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9727   },
9728
9729   /* VEX_LEN_0F3A22_P_2 */
9730   {
9731     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9732   },
9733
9734   /* VEX_LEN_0F3A30_P_2 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9737   },
9738
9739   /* VEX_LEN_0F3A32_P_2 */
9740   {
9741     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9742   },
9743
9744   /* VEX_LEN_0F3A38_P_2 */
9745   {
9746     { Bad_Opcode },
9747     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9748   },
9749
9750   /* VEX_LEN_0F3A39_P_2 */
9751   {
9752     { Bad_Opcode },
9753     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9754   },
9755
9756   /* VEX_LEN_0F3A41_P_2 */
9757   {
9758     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9759   },
9760
9761   /* VEX_LEN_0F3A44_P_2 */
9762   {
9763     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9764   },
9765
9766   /* VEX_LEN_0F3A46_P_2 */
9767   {
9768     { Bad_Opcode },
9769     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9770   },
9771
9772   /* VEX_LEN_0F3A60_P_2 */
9773   {
9774     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9775   },
9776
9777   /* VEX_LEN_0F3A61_P_2 */
9778   {
9779     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9780   },
9781
9782   /* VEX_LEN_0F3A62_P_2 */
9783   {
9784     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9785   },
9786
9787   /* VEX_LEN_0F3A63_P_2 */
9788   {
9789     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9790   },
9791
9792   /* VEX_LEN_0F3A6A_P_2 */
9793   {
9794     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9795   },
9796
9797   /* VEX_LEN_0F3A6B_P_2 */
9798   {
9799     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9800   },
9801
9802   /* VEX_LEN_0F3A6E_P_2 */
9803   {
9804     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9805   },
9806
9807   /* VEX_LEN_0F3A6F_P_2 */
9808   {
9809     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9810   },
9811
9812   /* VEX_LEN_0F3A7A_P_2 */
9813   {
9814     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9815   },
9816
9817   /* VEX_LEN_0F3A7B_P_2 */
9818   {
9819     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9820   },
9821
9822   /* VEX_LEN_0F3A7E_P_2 */
9823   {
9824     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9825   },
9826
9827   /* VEX_LEN_0F3A7F_P_2 */
9828   {
9829     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9830   },
9831
9832   /* VEX_LEN_0F3ADF_P_2 */
9833   {
9834     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9835   },
9836
9837   /* VEX_LEN_0F3AF0_P_3 */
9838   {
9839     { "rorxS",          { Gdq, Edq, Ib } },
9840   },
9841
9842   /* VEX_LEN_0FXOP_08_CC */
9843   {
9844      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9845   },
9846
9847   /* VEX_LEN_0FXOP_08_CD */
9848   {
9849      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9850   },
9851
9852   /* VEX_LEN_0FXOP_08_CE */
9853   {
9854      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9855   },
9856
9857   /* VEX_LEN_0FXOP_08_CF */
9858   {
9859      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9860   },
9861
9862   /* VEX_LEN_0FXOP_08_EC */
9863   {
9864      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9865   },
9866
9867   /* VEX_LEN_0FXOP_08_ED */
9868   {
9869      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9870   },
9871
9872   /* VEX_LEN_0FXOP_08_EE */
9873   {
9874      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9875   },
9876
9877   /* VEX_LEN_0FXOP_08_EF */
9878   {
9879      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9880   },
9881
9882   /* VEX_LEN_0FXOP_09_80 */
9883   {
9884     { "vfrczps",        { XM, EXxmm } },
9885     { "vfrczps",        { XM, EXymmq } },
9886   },
9887
9888   /* VEX_LEN_0FXOP_09_81 */
9889   {
9890     { "vfrczpd",        { XM, EXxmm } },
9891     { "vfrczpd",        { XM, EXymmq } },
9892   },
9893 };
9894
9895 static const struct dis386 vex_w_table[][2] = {
9896   {
9897     /* VEX_W_0F10_P_0 */
9898     { "vmovups",        { XM, EXx } },
9899   },
9900   {
9901     /* VEX_W_0F10_P_1 */
9902     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9903   },
9904   {
9905     /* VEX_W_0F10_P_2 */
9906     { "vmovupd",        { XM, EXx } },
9907   },
9908   {
9909     /* VEX_W_0F10_P_3 */
9910     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9911   },
9912   {
9913     /* VEX_W_0F11_P_0 */
9914     { "vmovups",        { EXxS, XM } },
9915   },
9916   {
9917     /* VEX_W_0F11_P_1 */
9918     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9919   },
9920   {
9921     /* VEX_W_0F11_P_2 */
9922     { "vmovupd",        { EXxS, XM } },
9923   },
9924   {
9925     /* VEX_W_0F11_P_3 */
9926     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9927   },
9928   {
9929     /* VEX_W_0F12_P_0_M_0 */
9930     { "vmovlps",        { XM, Vex128, EXq } },
9931   },
9932   {
9933     /* VEX_W_0F12_P_0_M_1 */
9934     { "vmovhlps",       { XM, Vex128, EXq } },
9935   },
9936   {
9937     /* VEX_W_0F12_P_1 */
9938     { "vmovsldup",      { XM, EXx } },
9939   },
9940   {
9941     /* VEX_W_0F12_P_2 */
9942     { "vmovlpd",        { XM, Vex128, EXq } },
9943   },
9944   {
9945     /* VEX_W_0F12_P_3 */
9946     { "vmovddup",       { XM, EXymmq } },
9947   },
9948   {
9949     /* VEX_W_0F13_M_0 */
9950     { "vmovlpX",        { EXq, XM } },
9951   },
9952   {
9953     /* VEX_W_0F14 */
9954     { "vunpcklpX",      { XM, Vex, EXx } },
9955   },
9956   {
9957     /* VEX_W_0F15 */
9958     { "vunpckhpX",      { XM, Vex, EXx } },
9959   },
9960   {
9961     /* VEX_W_0F16_P_0_M_0 */
9962     { "vmovhps",        { XM, Vex128, EXq } },
9963   },
9964   {
9965     /* VEX_W_0F16_P_0_M_1 */
9966     { "vmovlhps",       { XM, Vex128, EXq } },
9967   },
9968   {
9969     /* VEX_W_0F16_P_1 */
9970     { "vmovshdup",      { XM, EXx } },
9971   },
9972   {
9973     /* VEX_W_0F16_P_2 */
9974     { "vmovhpd",        { XM, Vex128, EXq } },
9975   },
9976   {
9977     /* VEX_W_0F17_M_0 */
9978     { "vmovhpX",        { EXq, XM } },
9979   },
9980   {
9981     /* VEX_W_0F28 */
9982     { "vmovapX",        { XM, EXx } },
9983   },
9984   {
9985     /* VEX_W_0F29 */
9986     { "vmovapX",        { EXxS, XM } },
9987   },
9988   {
9989     /* VEX_W_0F2B_M_0 */
9990     { "vmovntpX",       { Mx, XM } },
9991   },
9992   {
9993     /* VEX_W_0F2E_P_0 */
9994     { "vucomiss",       { XMScalar, EXdScalar } },
9995   },
9996   {
9997     /* VEX_W_0F2E_P_2 */
9998     { "vucomisd",       { XMScalar, EXqScalar } },
9999   },
10000   {
10001     /* VEX_W_0F2F_P_0 */
10002     { "vcomiss",        { XMScalar, EXdScalar } },
10003   },
10004   {
10005     /* VEX_W_0F2F_P_2 */
10006     { "vcomisd",        { XMScalar, EXqScalar } },
10007   },
10008   {
10009     /* VEX_W_0F41_P_0_LEN_1 */
10010     { "kandw",          { MaskG, MaskVex, MaskR } },
10011   },
10012   {
10013     /* VEX_W_0F42_P_0_LEN_1 */
10014     { "kandnw",         { MaskG, MaskVex, MaskR } },
10015   },
10016   {
10017     /* VEX_W_0F44_P_0_LEN_0 */
10018     { "knotw",          { MaskG, MaskR } },
10019   },
10020   {
10021     /* VEX_W_0F45_P_0_LEN_1 */
10022     { "korw",           { MaskG, MaskVex, MaskR } },
10023   },
10024   {
10025     /* VEX_W_0F46_P_0_LEN_1 */
10026     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10027   },
10028   {
10029     /* VEX_W_0F47_P_0_LEN_1 */
10030     { "kxorw",          { MaskG, MaskVex, MaskR } },
10031   },
10032   {
10033     /* VEX_W_0F4B_P_2_LEN_1 */
10034     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10035   },
10036   {
10037     /* VEX_W_0F50_M_0 */
10038     { "vmovmskpX",      { Gdq, XS } },
10039   },
10040   {
10041     /* VEX_W_0F51_P_0 */
10042     { "vsqrtps",        { XM, EXx } },
10043   },
10044   {
10045     /* VEX_W_0F51_P_1 */
10046     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10047   },
10048   {
10049     /* VEX_W_0F51_P_2  */
10050     { "vsqrtpd",        { XM, EXx } },
10051   },
10052   {
10053     /* VEX_W_0F51_P_3 */
10054     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10055   },
10056   {
10057     /* VEX_W_0F52_P_0 */
10058     { "vrsqrtps",       { XM, EXx } },
10059   },
10060   {
10061     /* VEX_W_0F52_P_1 */
10062     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10063   },
10064   {
10065     /* VEX_W_0F53_P_0  */
10066     { "vrcpps",         { XM, EXx } },
10067   },
10068   {
10069     /* VEX_W_0F53_P_1  */
10070     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10071   },
10072   {
10073     /* VEX_W_0F58_P_0  */
10074     { "vaddps",         { XM, Vex, EXx } },
10075   },
10076   {
10077     /* VEX_W_0F58_P_1  */
10078     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10079   },
10080   {
10081     /* VEX_W_0F58_P_2  */
10082     { "vaddpd",         { XM, Vex, EXx } },
10083   },
10084   {
10085     /* VEX_W_0F58_P_3  */
10086     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10087   },
10088   {
10089     /* VEX_W_0F59_P_0  */
10090     { "vmulps",         { XM, Vex, EXx } },
10091   },
10092   {
10093     /* VEX_W_0F59_P_1  */
10094     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10095   },
10096   {
10097     /* VEX_W_0F59_P_2  */
10098     { "vmulpd",         { XM, Vex, EXx } },
10099   },
10100   {
10101     /* VEX_W_0F59_P_3  */
10102     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10103   },
10104   {
10105     /* VEX_W_0F5A_P_0  */
10106     { "vcvtps2pd",      { XM, EXxmmq } },
10107   },
10108   {
10109     /* VEX_W_0F5A_P_1  */
10110     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10111   },
10112   {
10113     /* VEX_W_0F5A_P_3  */
10114     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10115   },
10116   {
10117     /* VEX_W_0F5B_P_0  */
10118     { "vcvtdq2ps",      { XM, EXx } },
10119   },
10120   {
10121     /* VEX_W_0F5B_P_1  */
10122     { "vcvttps2dq",     { XM, EXx } },
10123   },
10124   {
10125     /* VEX_W_0F5B_P_2  */
10126     { "vcvtps2dq",      { XM, EXx } },
10127   },
10128   {
10129     /* VEX_W_0F5C_P_0  */
10130     { "vsubps",         { XM, Vex, EXx } },
10131   },
10132   {
10133     /* VEX_W_0F5C_P_1  */
10134     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10135   },
10136   {
10137     /* VEX_W_0F5C_P_2  */
10138     { "vsubpd",         { XM, Vex, EXx } },
10139   },
10140   {
10141     /* VEX_W_0F5C_P_3  */
10142     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10143   },
10144   {
10145     /* VEX_W_0F5D_P_0  */
10146     { "vminps",         { XM, Vex, EXx } },
10147   },
10148   {
10149     /* VEX_W_0F5D_P_1  */
10150     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10151   },
10152   {
10153     /* VEX_W_0F5D_P_2  */
10154     { "vminpd",         { XM, Vex, EXx } },
10155   },
10156   {
10157     /* VEX_W_0F5D_P_3  */
10158     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10159   },
10160   {
10161     /* VEX_W_0F5E_P_0  */
10162     { "vdivps",         { XM, Vex, EXx } },
10163   },
10164   {
10165     /* VEX_W_0F5E_P_1  */
10166     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10167   },
10168   {
10169     /* VEX_W_0F5E_P_2  */
10170     { "vdivpd",         { XM, Vex, EXx } },
10171   },
10172   {
10173     /* VEX_W_0F5E_P_3  */
10174     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10175   },
10176   {
10177     /* VEX_W_0F5F_P_0  */
10178     { "vmaxps",         { XM, Vex, EXx } },
10179   },
10180   {
10181     /* VEX_W_0F5F_P_1  */
10182     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10183   },
10184   {
10185     /* VEX_W_0F5F_P_2  */
10186     { "vmaxpd",         { XM, Vex, EXx } },
10187   },
10188   {
10189     /* VEX_W_0F5F_P_3  */
10190     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10191   },
10192   {
10193     /* VEX_W_0F60_P_2  */
10194     { "vpunpcklbw",     { XM, Vex, EXx } },
10195   },
10196   {
10197     /* VEX_W_0F61_P_2  */
10198     { "vpunpcklwd",     { XM, Vex, EXx } },
10199   },
10200   {
10201     /* VEX_W_0F62_P_2  */
10202     { "vpunpckldq",     { XM, Vex, EXx } },
10203   },
10204   {
10205     /* VEX_W_0F63_P_2  */
10206     { "vpacksswb",      { XM, Vex, EXx } },
10207   },
10208   {
10209     /* VEX_W_0F64_P_2  */
10210     { "vpcmpgtb",       { XM, Vex, EXx } },
10211   },
10212   {
10213     /* VEX_W_0F65_P_2  */
10214     { "vpcmpgtw",       { XM, Vex, EXx } },
10215   },
10216   {
10217     /* VEX_W_0F66_P_2  */
10218     { "vpcmpgtd",       { XM, Vex, EXx } },
10219   },
10220   {
10221     /* VEX_W_0F67_P_2  */
10222     { "vpackuswb",      { XM, Vex, EXx } },
10223   },
10224   {
10225     /* VEX_W_0F68_P_2  */
10226     { "vpunpckhbw",     { XM, Vex, EXx } },
10227   },
10228   {
10229     /* VEX_W_0F69_P_2  */
10230     { "vpunpckhwd",     { XM, Vex, EXx } },
10231   },
10232   {
10233     /* VEX_W_0F6A_P_2  */
10234     { "vpunpckhdq",     { XM, Vex, EXx } },
10235   },
10236   {
10237     /* VEX_W_0F6B_P_2  */
10238     { "vpackssdw",      { XM, Vex, EXx } },
10239   },
10240   {
10241     /* VEX_W_0F6C_P_2  */
10242     { "vpunpcklqdq",    { XM, Vex, EXx } },
10243   },
10244   {
10245     /* VEX_W_0F6D_P_2  */
10246     { "vpunpckhqdq",    { XM, Vex, EXx } },
10247   },
10248   {
10249     /* VEX_W_0F6F_P_1  */
10250     { "vmovdqu",        { XM, EXx } },
10251   },
10252   {
10253     /* VEX_W_0F6F_P_2  */
10254     { "vmovdqa",        { XM, EXx } },
10255   },
10256   {
10257     /* VEX_W_0F70_P_1 */
10258     { "vpshufhw",       { XM, EXx, Ib } },
10259   },
10260   {
10261     /* VEX_W_0F70_P_2 */
10262     { "vpshufd",        { XM, EXx, Ib } },
10263   },
10264   {
10265     /* VEX_W_0F70_P_3 */
10266     { "vpshuflw",       { XM, EXx, Ib } },
10267   },
10268   {
10269     /* VEX_W_0F71_R_2_P_2  */
10270     { "vpsrlw",         { Vex, XS, Ib } },
10271   },
10272   {
10273     /* VEX_W_0F71_R_4_P_2  */
10274     { "vpsraw",         { Vex, XS, Ib } },
10275   },
10276   {
10277     /* VEX_W_0F71_R_6_P_2  */
10278     { "vpsllw",         { Vex, XS, Ib } },
10279   },
10280   {
10281     /* VEX_W_0F72_R_2_P_2  */
10282     { "vpsrld",         { Vex, XS, Ib } },
10283   },
10284   {
10285     /* VEX_W_0F72_R_4_P_2  */
10286     { "vpsrad",         { Vex, XS, Ib } },
10287   },
10288   {
10289     /* VEX_W_0F72_R_6_P_2  */
10290     { "vpslld",         { Vex, XS, Ib } },
10291   },
10292   {
10293     /* VEX_W_0F73_R_2_P_2  */
10294     { "vpsrlq",         { Vex, XS, Ib } },
10295   },
10296   {
10297     /* VEX_W_0F73_R_3_P_2  */
10298     { "vpsrldq",        { Vex, XS, Ib } },
10299   },
10300   {
10301     /* VEX_W_0F73_R_6_P_2  */
10302     { "vpsllq",         { Vex, XS, Ib } },
10303   },
10304   {
10305     /* VEX_W_0F73_R_7_P_2  */
10306     { "vpslldq",        { Vex, XS, Ib } },
10307   },
10308   {
10309     /* VEX_W_0F74_P_2 */
10310     { "vpcmpeqb",       { XM, Vex, EXx } },
10311   },
10312   {
10313     /* VEX_W_0F75_P_2 */
10314     { "vpcmpeqw",       { XM, Vex, EXx } },
10315   },
10316   {
10317     /* VEX_W_0F76_P_2 */
10318     { "vpcmpeqd",       { XM, Vex, EXx } },
10319   },
10320   {
10321     /* VEX_W_0F77_P_0 */
10322     { "",               { VZERO } },
10323   },
10324   {
10325     /* VEX_W_0F7C_P_2 */
10326     { "vhaddpd",        { XM, Vex, EXx } },
10327   },
10328   {
10329     /* VEX_W_0F7C_P_3 */
10330     { "vhaddps",        { XM, Vex, EXx } },
10331   },
10332   {
10333     /* VEX_W_0F7D_P_2 */
10334     { "vhsubpd",        { XM, Vex, EXx } },
10335   },
10336   {
10337     /* VEX_W_0F7D_P_3 */
10338     { "vhsubps",        { XM, Vex, EXx } },
10339   },
10340   {
10341     /* VEX_W_0F7E_P_1 */
10342     { "vmovq",          { XMScalar, EXqScalar } },
10343   },
10344   {
10345     /* VEX_W_0F7F_P_1 */
10346     { "vmovdqu",        { EXxS, XM } },
10347   },
10348   {
10349     /* VEX_W_0F7F_P_2 */
10350     { "vmovdqa",        { EXxS, XM } },
10351   },
10352   {
10353     /* VEX_W_0F90_P_0_LEN_0 */
10354     { "kmovw",          { MaskG, MaskE } },
10355   },
10356   {
10357     /* VEX_W_0F91_P_0_LEN_0 */
10358     { "kmovw",          { Ew, MaskG } },
10359   },
10360   {
10361     /* VEX_W_0F92_P_0_LEN_0 */
10362     { "kmovw",          { MaskG, Rdq } },
10363   },
10364   {
10365     /* VEX_W_0F93_P_0_LEN_0 */
10366     { "kmovw",          { Gdq, MaskR } },
10367   },
10368   {
10369     /* VEX_W_0F98_P_0_LEN_0 */
10370     { "kortestw",       { MaskG, MaskR } },
10371   },
10372   {
10373     /* VEX_W_0FAE_R_2_M_0 */
10374     { "vldmxcsr",       { Md } },
10375   },
10376   {
10377     /* VEX_W_0FAE_R_3_M_0 */
10378     { "vstmxcsr",       { Md } },
10379   },
10380   {
10381     /* VEX_W_0FC2_P_0 */
10382     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10383   },
10384   {
10385     /* VEX_W_0FC2_P_1 */
10386     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10387   },
10388   {
10389     /* VEX_W_0FC2_P_2 */
10390     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10391   },
10392   {
10393     /* VEX_W_0FC2_P_3 */
10394     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10395   },
10396   {
10397     /* VEX_W_0FC4_P_2 */
10398     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10399   },
10400   {
10401     /* VEX_W_0FC5_P_2 */
10402     { "vpextrw",        { Gdq, XS, Ib } },
10403   },
10404   {
10405     /* VEX_W_0FD0_P_2 */
10406     { "vaddsubpd",      { XM, Vex, EXx } },
10407   },
10408   {
10409     /* VEX_W_0FD0_P_3 */
10410     { "vaddsubps",      { XM, Vex, EXx } },
10411   },
10412   {
10413     /* VEX_W_0FD1_P_2 */
10414     { "vpsrlw",         { XM, Vex, EXxmm } },
10415   },
10416   {
10417     /* VEX_W_0FD2_P_2 */
10418     { "vpsrld",         { XM, Vex, EXxmm } },
10419   },
10420   {
10421     /* VEX_W_0FD3_P_2 */
10422     { "vpsrlq",         { XM, Vex, EXxmm } },
10423   },
10424   {
10425     /* VEX_W_0FD4_P_2 */
10426     { "vpaddq",         { XM, Vex, EXx } },
10427   },
10428   {
10429     /* VEX_W_0FD5_P_2 */
10430     { "vpmullw",        { XM, Vex, EXx } },
10431   },
10432   {
10433     /* VEX_W_0FD6_P_2 */
10434     { "vmovq",          { EXqScalarS, XMScalar } },
10435   },
10436   {
10437     /* VEX_W_0FD7_P_2_M_1 */
10438     { "vpmovmskb",      { Gdq, XS } },
10439   },
10440   {
10441     /* VEX_W_0FD8_P_2 */
10442     { "vpsubusb",       { XM, Vex, EXx } },
10443   },
10444   {
10445     /* VEX_W_0FD9_P_2 */
10446     { "vpsubusw",       { XM, Vex, EXx } },
10447   },
10448   {
10449     /* VEX_W_0FDA_P_2 */
10450     { "vpminub",        { XM, Vex, EXx } },
10451   },
10452   {
10453     /* VEX_W_0FDB_P_2 */
10454     { "vpand",          { XM, Vex, EXx } },
10455   },
10456   {
10457     /* VEX_W_0FDC_P_2 */
10458     { "vpaddusb",       { XM, Vex, EXx } },
10459   },
10460   {
10461     /* VEX_W_0FDD_P_2 */
10462     { "vpaddusw",       { XM, Vex, EXx } },
10463   },
10464   {
10465     /* VEX_W_0FDE_P_2 */
10466     { "vpmaxub",        { XM, Vex, EXx } },
10467   },
10468   {
10469     /* VEX_W_0FDF_P_2 */
10470     { "vpandn",         { XM, Vex, EXx } },
10471   },
10472   {
10473     /* VEX_W_0FE0_P_2  */
10474     { "vpavgb",         { XM, Vex, EXx } },
10475   },
10476   {
10477     /* VEX_W_0FE1_P_2  */
10478     { "vpsraw",         { XM, Vex, EXxmm } },
10479   },
10480   {
10481     /* VEX_W_0FE2_P_2  */
10482     { "vpsrad",         { XM, Vex, EXxmm } },
10483   },
10484   {
10485     /* VEX_W_0FE3_P_2  */
10486     { "vpavgw",         { XM, Vex, EXx } },
10487   },
10488   {
10489     /* VEX_W_0FE4_P_2  */
10490     { "vpmulhuw",       { XM, Vex, EXx } },
10491   },
10492   {
10493     /* VEX_W_0FE5_P_2  */
10494     { "vpmulhw",        { XM, Vex, EXx } },
10495   },
10496   {
10497     /* VEX_W_0FE6_P_1  */
10498     { "vcvtdq2pd",      { XM, EXxmmq } },
10499   },
10500   {
10501     /* VEX_W_0FE6_P_2  */
10502     { "vcvttpd2dq%XY",  { XMM, EXx } },
10503   },
10504   {
10505     /* VEX_W_0FE6_P_3  */
10506     { "vcvtpd2dq%XY",   { XMM, EXx } },
10507   },
10508   {
10509     /* VEX_W_0FE7_P_2_M_0 */
10510     { "vmovntdq",       { Mx, XM } },
10511   },
10512   {
10513     /* VEX_W_0FE8_P_2  */
10514     { "vpsubsb",        { XM, Vex, EXx } },
10515   },
10516   {
10517     /* VEX_W_0FE9_P_2  */
10518     { "vpsubsw",        { XM, Vex, EXx } },
10519   },
10520   {
10521     /* VEX_W_0FEA_P_2  */
10522     { "vpminsw",        { XM, Vex, EXx } },
10523   },
10524   {
10525     /* VEX_W_0FEB_P_2  */
10526     { "vpor",           { XM, Vex, EXx } },
10527   },
10528   {
10529     /* VEX_W_0FEC_P_2  */
10530     { "vpaddsb",        { XM, Vex, EXx } },
10531   },
10532   {
10533     /* VEX_W_0FED_P_2  */
10534     { "vpaddsw",        { XM, Vex, EXx } },
10535   },
10536   {
10537     /* VEX_W_0FEE_P_2  */
10538     { "vpmaxsw",        { XM, Vex, EXx } },
10539   },
10540   {
10541     /* VEX_W_0FEF_P_2  */
10542     { "vpxor",          { XM, Vex, EXx } },
10543   },
10544   {
10545     /* VEX_W_0FF0_P_3_M_0 */
10546     { "vlddqu",         { XM, M } },
10547   },
10548   {
10549     /* VEX_W_0FF1_P_2 */
10550     { "vpsllw",         { XM, Vex, EXxmm } },
10551   },
10552   {
10553     /* VEX_W_0FF2_P_2 */
10554     { "vpslld",         { XM, Vex, EXxmm } },
10555   },
10556   {
10557     /* VEX_W_0FF3_P_2 */
10558     { "vpsllq",         { XM, Vex, EXxmm } },
10559   },
10560   {
10561     /* VEX_W_0FF4_P_2 */
10562     { "vpmuludq",       { XM, Vex, EXx } },
10563   },
10564   {
10565     /* VEX_W_0FF5_P_2 */
10566     { "vpmaddwd",       { XM, Vex, EXx } },
10567   },
10568   {
10569     /* VEX_W_0FF6_P_2 */
10570     { "vpsadbw",        { XM, Vex, EXx } },
10571   },
10572   {
10573     /* VEX_W_0FF7_P_2 */
10574     { "vmaskmovdqu",    { XM, XS } },
10575   },
10576   {
10577     /* VEX_W_0FF8_P_2 */
10578     { "vpsubb",         { XM, Vex, EXx } },
10579   },
10580   {
10581     /* VEX_W_0FF9_P_2 */
10582     { "vpsubw",         { XM, Vex, EXx } },
10583   },
10584   {
10585     /* VEX_W_0FFA_P_2 */
10586     { "vpsubd",         { XM, Vex, EXx } },
10587   },
10588   {
10589     /* VEX_W_0FFB_P_2 */
10590     { "vpsubq",         { XM, Vex, EXx } },
10591   },
10592   {
10593     /* VEX_W_0FFC_P_2 */
10594     { "vpaddb",         { XM, Vex, EXx } },
10595   },
10596   {
10597     /* VEX_W_0FFD_P_2 */
10598     { "vpaddw",         { XM, Vex, EXx } },
10599   },
10600   {
10601     /* VEX_W_0FFE_P_2 */
10602     { "vpaddd",         { XM, Vex, EXx } },
10603   },
10604   {
10605     /* VEX_W_0F3800_P_2  */
10606     { "vpshufb",        { XM, Vex, EXx } },
10607   },
10608   {
10609     /* VEX_W_0F3801_P_2  */
10610     { "vphaddw",        { XM, Vex, EXx } },
10611   },
10612   {
10613     /* VEX_W_0F3802_P_2  */
10614     { "vphaddd",        { XM, Vex, EXx } },
10615   },
10616   {
10617     /* VEX_W_0F3803_P_2  */
10618     { "vphaddsw",       { XM, Vex, EXx } },
10619   },
10620   {
10621     /* VEX_W_0F3804_P_2  */
10622     { "vpmaddubsw",     { XM, Vex, EXx } },
10623   },
10624   {
10625     /* VEX_W_0F3805_P_2  */
10626     { "vphsubw",        { XM, Vex, EXx } },
10627   },
10628   {
10629     /* VEX_W_0F3806_P_2  */
10630     { "vphsubd",        { XM, Vex, EXx } },
10631   },
10632   {
10633     /* VEX_W_0F3807_P_2  */
10634     { "vphsubsw",       { XM, Vex, EXx } },
10635   },
10636   {
10637     /* VEX_W_0F3808_P_2  */
10638     { "vpsignb",        { XM, Vex, EXx } },
10639   },
10640   {
10641     /* VEX_W_0F3809_P_2  */
10642     { "vpsignw",        { XM, Vex, EXx } },
10643   },
10644   {
10645     /* VEX_W_0F380A_P_2  */
10646     { "vpsignd",        { XM, Vex, EXx } },
10647   },
10648   {
10649     /* VEX_W_0F380B_P_2  */
10650     { "vpmulhrsw",      { XM, Vex, EXx } },
10651   },
10652   {
10653     /* VEX_W_0F380C_P_2  */
10654     { "vpermilps",      { XM, Vex, EXx } },
10655   },
10656   {
10657     /* VEX_W_0F380D_P_2  */
10658     { "vpermilpd",      { XM, Vex, EXx } },
10659   },
10660   {
10661     /* VEX_W_0F380E_P_2  */
10662     { "vtestps",        { XM, EXx } },
10663   },
10664   {
10665     /* VEX_W_0F380F_P_2  */
10666     { "vtestpd",        { XM, EXx } },
10667   },
10668   {
10669     /* VEX_W_0F3816_P_2  */
10670     { "vpermps",        { XM, Vex, EXx } },
10671   },
10672   {
10673     /* VEX_W_0F3817_P_2 */
10674     { "vptest",         { XM, EXx } },
10675   },
10676   {
10677     /* VEX_W_0F3818_P_2 */
10678     { "vbroadcastss",   { XM, EXxmm_md } },
10679   },
10680   {
10681     /* VEX_W_0F3819_P_2 */
10682     { "vbroadcastsd",   { XM, EXxmm_mq } },
10683   },
10684   {
10685     /* VEX_W_0F381A_P_2_M_0 */
10686     { "vbroadcastf128", { XM, Mxmm } },
10687   },
10688   {
10689     /* VEX_W_0F381C_P_2 */
10690     { "vpabsb",         { XM, EXx } },
10691   },
10692   {
10693     /* VEX_W_0F381D_P_2 */
10694     { "vpabsw",         { XM, EXx } },
10695   },
10696   {
10697     /* VEX_W_0F381E_P_2 */
10698     { "vpabsd",         { XM, EXx } },
10699   },
10700   {
10701     /* VEX_W_0F3820_P_2 */
10702     { "vpmovsxbw",      { XM, EXxmmq } },
10703   },
10704   {
10705     /* VEX_W_0F3821_P_2 */
10706     { "vpmovsxbd",      { XM, EXxmmqd } },
10707   },
10708   {
10709     /* VEX_W_0F3822_P_2 */
10710     { "vpmovsxbq",      { XM, EXxmmdw } },
10711   },
10712   {
10713     /* VEX_W_0F3823_P_2 */
10714     { "vpmovsxwd",      { XM, EXxmmq } },
10715   },
10716   {
10717     /* VEX_W_0F3824_P_2 */
10718     { "vpmovsxwq",      { XM, EXxmmqd } },
10719   },
10720   {
10721     /* VEX_W_0F3825_P_2 */
10722     { "vpmovsxdq",      { XM, EXxmmq } },
10723   },
10724   {
10725     /* VEX_W_0F3828_P_2 */
10726     { "vpmuldq",        { XM, Vex, EXx } },
10727   },
10728   {
10729     /* VEX_W_0F3829_P_2 */
10730     { "vpcmpeqq",       { XM, Vex, EXx } },
10731   },
10732   {
10733     /* VEX_W_0F382A_P_2_M_0 */
10734     { "vmovntdqa",      { XM, Mx } },
10735   },
10736   {
10737     /* VEX_W_0F382B_P_2 */
10738     { "vpackusdw",      { XM, Vex, EXx } },
10739   },
10740   {
10741     /* VEX_W_0F382C_P_2_M_0 */
10742     { "vmaskmovps",     { XM, Vex, Mx } },
10743   },
10744   {
10745     /* VEX_W_0F382D_P_2_M_0 */
10746     { "vmaskmovpd",     { XM, Vex, Mx } },
10747   },
10748   {
10749     /* VEX_W_0F382E_P_2_M_0 */
10750     { "vmaskmovps",     { Mx, Vex, XM } },
10751   },
10752   {
10753     /* VEX_W_0F382F_P_2_M_0 */
10754     { "vmaskmovpd",     { Mx, Vex, XM } },
10755   },
10756   {
10757     /* VEX_W_0F3830_P_2 */
10758     { "vpmovzxbw",      { XM, EXxmmq } },
10759   },
10760   {
10761     /* VEX_W_0F3831_P_2 */
10762     { "vpmovzxbd",      { XM, EXxmmqd } },
10763   },
10764   {
10765     /* VEX_W_0F3832_P_2 */
10766     { "vpmovzxbq",      { XM, EXxmmdw } },
10767   },
10768   {
10769     /* VEX_W_0F3833_P_2 */
10770     { "vpmovzxwd",      { XM, EXxmmq } },
10771   },
10772   {
10773     /* VEX_W_0F3834_P_2 */
10774     { "vpmovzxwq",      { XM, EXxmmqd } },
10775   },
10776   {
10777     /* VEX_W_0F3835_P_2 */
10778     { "vpmovzxdq",      { XM, EXxmmq } },
10779   },
10780   {
10781     /* VEX_W_0F3836_P_2  */
10782     { "vpermd",         { XM, Vex, EXx } },
10783   },
10784   {
10785     /* VEX_W_0F3837_P_2 */
10786     { "vpcmpgtq",       { XM, Vex, EXx } },
10787   },
10788   {
10789     /* VEX_W_0F3838_P_2 */
10790     { "vpminsb",        { XM, Vex, EXx } },
10791   },
10792   {
10793     /* VEX_W_0F3839_P_2 */
10794     { "vpminsd",        { XM, Vex, EXx } },
10795   },
10796   {
10797     /* VEX_W_0F383A_P_2 */
10798     { "vpminuw",        { XM, Vex, EXx } },
10799   },
10800   {
10801     /* VEX_W_0F383B_P_2 */
10802     { "vpminud",        { XM, Vex, EXx } },
10803   },
10804   {
10805     /* VEX_W_0F383C_P_2 */
10806     { "vpmaxsb",        { XM, Vex, EXx } },
10807   },
10808   {
10809     /* VEX_W_0F383D_P_2 */
10810     { "vpmaxsd",        { XM, Vex, EXx } },
10811   },
10812   {
10813     /* VEX_W_0F383E_P_2 */
10814     { "vpmaxuw",        { XM, Vex, EXx } },
10815   },
10816   {
10817     /* VEX_W_0F383F_P_2 */
10818     { "vpmaxud",        { XM, Vex, EXx } },
10819   },
10820   {
10821     /* VEX_W_0F3840_P_2 */
10822     { "vpmulld",        { XM, Vex, EXx } },
10823   },
10824   {
10825     /* VEX_W_0F3841_P_2 */
10826     { "vphminposuw",    { XM, EXx } },
10827   },
10828   {
10829     /* VEX_W_0F3846_P_2 */
10830     { "vpsravd",        { XM, Vex, EXx } },
10831   },
10832   {
10833     /* VEX_W_0F3858_P_2 */
10834     { "vpbroadcastd", { XM, EXxmm_md } },
10835   },
10836   {
10837     /* VEX_W_0F3859_P_2 */
10838     { "vpbroadcastq",   { XM, EXxmm_mq } },
10839   },
10840   {
10841     /* VEX_W_0F385A_P_2_M_0 */
10842     { "vbroadcasti128", { XM, Mxmm } },
10843   },
10844   {
10845     /* VEX_W_0F3878_P_2 */
10846     { "vpbroadcastb",   { XM, EXxmm_mb } },
10847   },
10848   {
10849     /* VEX_W_0F3879_P_2 */
10850     { "vpbroadcastw",   { XM, EXxmm_mw } },
10851   },
10852   {
10853     /* VEX_W_0F38DB_P_2 */
10854     { "vaesimc",        { XM, EXx } },
10855   },
10856   {
10857     /* VEX_W_0F38DC_P_2 */
10858     { "vaesenc",        { XM, Vex128, EXx } },
10859   },
10860   {
10861     /* VEX_W_0F38DD_P_2 */
10862     { "vaesenclast",    { XM, Vex128, EXx } },
10863   },
10864   {
10865     /* VEX_W_0F38DE_P_2 */
10866     { "vaesdec",        { XM, Vex128, EXx } },
10867   },
10868   {
10869     /* VEX_W_0F38DF_P_2 */
10870     { "vaesdeclast",    { XM, Vex128, EXx } },
10871   },
10872   {
10873     /* VEX_W_0F3A00_P_2 */
10874     { Bad_Opcode },
10875     { "vpermq",         { XM, EXx, Ib } },
10876   },
10877   {
10878     /* VEX_W_0F3A01_P_2 */
10879     { Bad_Opcode },
10880     { "vpermpd",        { XM, EXx, Ib } },
10881   },
10882   {
10883     /* VEX_W_0F3A02_P_2 */
10884     { "vpblendd",       { XM, Vex, EXx, Ib } },
10885   },
10886   {
10887     /* VEX_W_0F3A04_P_2 */
10888     { "vpermilps",      { XM, EXx, Ib } },
10889   },
10890   {
10891     /* VEX_W_0F3A05_P_2 */
10892     { "vpermilpd",      { XM, EXx, Ib } },
10893   },
10894   {
10895     /* VEX_W_0F3A06_P_2 */
10896     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10897   },
10898   {
10899     /* VEX_W_0F3A08_P_2 */
10900     { "vroundps",       { XM, EXx, Ib } },
10901   },
10902   {
10903     /* VEX_W_0F3A09_P_2 */
10904     { "vroundpd",       { XM, EXx, Ib } },
10905   },
10906   {
10907     /* VEX_W_0F3A0A_P_2 */
10908     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10909   },
10910   {
10911     /* VEX_W_0F3A0B_P_2 */
10912     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10913   },
10914   {
10915     /* VEX_W_0F3A0C_P_2 */
10916     { "vblendps",       { XM, Vex, EXx, Ib } },
10917   },
10918   {
10919     /* VEX_W_0F3A0D_P_2 */
10920     { "vblendpd",       { XM, Vex, EXx, Ib } },
10921   },
10922   {
10923     /* VEX_W_0F3A0E_P_2 */
10924     { "vpblendw",       { XM, Vex, EXx, Ib } },
10925   },
10926   {
10927     /* VEX_W_0F3A0F_P_2 */
10928     { "vpalignr",       { XM, Vex, EXx, Ib } },
10929   },
10930   {
10931     /* VEX_W_0F3A14_P_2 */
10932     { "vpextrb",        { Edqb, XM, Ib } },
10933   },
10934   {
10935     /* VEX_W_0F3A15_P_2 */
10936     { "vpextrw",        { Edqw, XM, Ib } },
10937   },
10938   {
10939     /* VEX_W_0F3A18_P_2 */
10940     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10941   },
10942   {
10943     /* VEX_W_0F3A19_P_2 */
10944     { "vextractf128",   { EXxmm, XM, Ib } },
10945   },
10946   {
10947     /* VEX_W_0F3A20_P_2 */
10948     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10949   },
10950   {
10951     /* VEX_W_0F3A21_P_2 */
10952     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10953   },
10954   {
10955     /* VEX_W_0F3A30_P_2 */
10956     { Bad_Opcode },
10957     { "kshiftrw",       { MaskG, MaskR, Ib } },
10958   },
10959   {
10960     /* VEX_W_0F3A32_P_2 */
10961     { Bad_Opcode },
10962     { "kshiftlw",       { MaskG, MaskR, Ib } },
10963   },
10964   {
10965     /* VEX_W_0F3A38_P_2 */
10966     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
10967   },
10968   {
10969     /* VEX_W_0F3A39_P_2 */
10970     { "vextracti128",   { EXxmm, XM, Ib } },
10971   },
10972   {
10973     /* VEX_W_0F3A40_P_2 */
10974     { "vdpps",          { XM, Vex, EXx, Ib } },
10975   },
10976   {
10977     /* VEX_W_0F3A41_P_2 */
10978     { "vdppd",          { XM, Vex128, EXx, Ib } },
10979   },
10980   {
10981     /* VEX_W_0F3A42_P_2 */
10982     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10983   },
10984   {
10985     /* VEX_W_0F3A44_P_2 */
10986     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10987   },
10988   {
10989     /* VEX_W_0F3A46_P_2 */
10990     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
10991   },
10992   {
10993     /* VEX_W_0F3A48_P_2 */
10994     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10995     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10996   },
10997   {
10998     /* VEX_W_0F3A49_P_2 */
10999     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11000     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11001   },
11002   {
11003     /* VEX_W_0F3A4A_P_2 */
11004     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11005   },
11006   {
11007     /* VEX_W_0F3A4B_P_2 */
11008     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11009   },
11010   {
11011     /* VEX_W_0F3A4C_P_2 */
11012     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11013   },
11014   {
11015     /* VEX_W_0F3A60_P_2 */
11016     { "vpcmpestrm",     { XM, EXx, Ib } },
11017   },
11018   {
11019     /* VEX_W_0F3A61_P_2 */
11020     { "vpcmpestri",     { XM, EXx, Ib } },
11021   },
11022   {
11023     /* VEX_W_0F3A62_P_2 */
11024     { "vpcmpistrm",     { XM, EXx, Ib } },
11025   },
11026   {
11027     /* VEX_W_0F3A63_P_2 */
11028     { "vpcmpistri",     { XM, EXx, Ib } },
11029   },
11030   {
11031     /* VEX_W_0F3ADF_P_2 */
11032     { "vaeskeygenassist", { XM, EXx, Ib } },
11033   },
11034 #define NEED_VEX_W_TABLE
11035 #include "i386-dis-evex.h"
11036 #undef NEED_VEX_W_TABLE
11037 };
11038
11039 static const struct dis386 mod_table[][2] = {
11040   {
11041     /* MOD_8D */
11042     { "leaS",           { Gv, M } },
11043   },
11044   {
11045     /* MOD_C6_REG_7 */
11046     { Bad_Opcode },
11047     { RM_TABLE (RM_C6_REG_7) },
11048   },
11049   {
11050     /* MOD_C7_REG_7 */
11051     { Bad_Opcode },
11052     { RM_TABLE (RM_C7_REG_7) },
11053   },
11054   {
11055     /* MOD_0F01_REG_0 */
11056     { X86_64_TABLE (X86_64_0F01_REG_0) },
11057     { RM_TABLE (RM_0F01_REG_0) },
11058   },
11059   {
11060     /* MOD_0F01_REG_1 */
11061     { X86_64_TABLE (X86_64_0F01_REG_1) },
11062     { RM_TABLE (RM_0F01_REG_1) },
11063   },
11064   {
11065     /* MOD_0F01_REG_2 */
11066     { X86_64_TABLE (X86_64_0F01_REG_2) },
11067     { RM_TABLE (RM_0F01_REG_2) },
11068   },
11069   {
11070     /* MOD_0F01_REG_3 */
11071     { X86_64_TABLE (X86_64_0F01_REG_3) },
11072     { RM_TABLE (RM_0F01_REG_3) },
11073   },
11074   {
11075     /* MOD_0F01_REG_7 */
11076     { "invlpg",         { Mb } },
11077     { RM_TABLE (RM_0F01_REG_7) },
11078   },
11079   {
11080     /* MOD_0F12_PREFIX_0 */
11081     { "movlps",         { XM, EXq } },
11082     { "movhlps",        { XM, EXq } },
11083   },
11084   {
11085     /* MOD_0F13 */
11086     { "movlpX",         { EXq, XM } },
11087   },
11088   {
11089     /* MOD_0F16_PREFIX_0 */
11090     { "movhps",         { XM, EXq } },
11091     { "movlhps",        { XM, EXq } },
11092   },
11093   {
11094     /* MOD_0F17 */
11095     { "movhpX",         { EXq, XM } },
11096   },
11097   {
11098     /* MOD_0F18_REG_0 */
11099     { "prefetchnta",    { Mb } },
11100   },
11101   {
11102     /* MOD_0F18_REG_1 */
11103     { "prefetcht0",     { Mb } },
11104   },
11105   {
11106     /* MOD_0F18_REG_2 */
11107     { "prefetcht1",     { Mb } },
11108   },
11109   {
11110     /* MOD_0F18_REG_3 */
11111     { "prefetcht2",     { Mb } },
11112   },
11113   {
11114     /* MOD_0F18_REG_4 */
11115     { "nop/reserved",   { Mb } },
11116   },
11117   {
11118     /* MOD_0F18_REG_5 */
11119     { "nop/reserved",   { Mb } },
11120   },
11121   {
11122     /* MOD_0F18_REG_6 */
11123     { "nop/reserved",   { Mb } },
11124   },
11125   {
11126     /* MOD_0F18_REG_7 */
11127     { "nop/reserved",   { Mb } },
11128   },
11129   {
11130     /* MOD_0F1A_PREFIX_0 */
11131     { "bndldx",         { Gbnd, Ev_bnd } },
11132     { "nopQ",           { Ev } },
11133   },
11134   {
11135     /* MOD_0F1B_PREFIX_0 */
11136     { "bndstx",         { Ev_bnd, Gbnd } },
11137     { "nopQ",           { Ev } },
11138   },
11139   {
11140     /* MOD_0F1B_PREFIX_1 */
11141     { "bndmk",          { Gbnd, Ev_bnd } },
11142     { "nopQ",           { Ev } },
11143   },
11144   {
11145     /* MOD_0F20 */
11146     { Bad_Opcode },
11147     { "movZ",           { Rm, Cm } },
11148   },
11149   {
11150     /* MOD_0F21 */
11151     { Bad_Opcode },
11152     { "movZ",           { Rm, Dm } },
11153   },
11154   {
11155     /* MOD_0F22 */
11156     { Bad_Opcode },
11157     { "movZ",           { Cm, Rm } },
11158   },
11159   {
11160     /* MOD_0F23 */
11161     { Bad_Opcode },
11162     { "movZ",           { Dm, Rm } },
11163   },
11164   {
11165     /* MOD_0F24 */
11166     { Bad_Opcode },
11167     { "movL",           { Rd, Td } },
11168   },
11169   {
11170     /* MOD_0F26 */
11171     { Bad_Opcode },
11172     { "movL",           { Td, Rd } },
11173   },
11174   {
11175     /* MOD_0F2B_PREFIX_0 */
11176     {"movntps",         { Mx, XM } },
11177   },
11178   {
11179     /* MOD_0F2B_PREFIX_1 */
11180     {"movntss",         { Md, XM } },
11181   },
11182   {
11183     /* MOD_0F2B_PREFIX_2 */
11184     {"movntpd",         { Mx, XM } },
11185   },
11186   {
11187     /* MOD_0F2B_PREFIX_3 */
11188     {"movntsd",         { Mq, XM } },
11189   },
11190   {
11191     /* MOD_0F51 */
11192     { Bad_Opcode },
11193     { "movmskpX",       { Gdq, XS } },
11194   },
11195   {
11196     /* MOD_0F71_REG_2 */
11197     { Bad_Opcode },
11198     { "psrlw",          { MS, Ib } },
11199   },
11200   {
11201     /* MOD_0F71_REG_4 */
11202     { Bad_Opcode },
11203     { "psraw",          { MS, Ib } },
11204   },
11205   {
11206     /* MOD_0F71_REG_6 */
11207     { Bad_Opcode },
11208     { "psllw",          { MS, Ib } },
11209   },
11210   {
11211     /* MOD_0F72_REG_2 */
11212     { Bad_Opcode },
11213     { "psrld",          { MS, Ib } },
11214   },
11215   {
11216     /* MOD_0F72_REG_4 */
11217     { Bad_Opcode },
11218     { "psrad",          { MS, Ib } },
11219   },
11220   {
11221     /* MOD_0F72_REG_6 */
11222     { Bad_Opcode },
11223     { "pslld",          { MS, Ib } },
11224   },
11225   {
11226     /* MOD_0F73_REG_2 */
11227     { Bad_Opcode },
11228     { "psrlq",          { MS, Ib } },
11229   },
11230   {
11231     /* MOD_0F73_REG_3 */
11232     { Bad_Opcode },
11233     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11234   },
11235   {
11236     /* MOD_0F73_REG_6 */
11237     { Bad_Opcode },
11238     { "psllq",          { MS, Ib } },
11239   },
11240   {
11241     /* MOD_0F73_REG_7 */
11242     { Bad_Opcode },
11243     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11244   },
11245   {
11246     /* MOD_0FAE_REG_0 */
11247     { "fxsave",         { FXSAVE } },
11248     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11249   },
11250   {
11251     /* MOD_0FAE_REG_1 */
11252     { "fxrstor",        { FXSAVE } },
11253     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11254   },
11255   {
11256     /* MOD_0FAE_REG_2 */
11257     { "ldmxcsr",        { Md } },
11258     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11259   },
11260   {
11261     /* MOD_0FAE_REG_3 */
11262     { "stmxcsr",        { Md } },
11263     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11264   },
11265   {
11266     /* MOD_0FAE_REG_4 */
11267     { "xsave",          { FXSAVE } },
11268   },
11269   {
11270     /* MOD_0FAE_REG_5 */
11271     { "xrstor",         { FXSAVE } },
11272     { RM_TABLE (RM_0FAE_REG_5) },
11273   },
11274   {
11275     /* MOD_0FAE_REG_6 */
11276     { "xsaveopt",       { FXSAVE } },
11277     { RM_TABLE (RM_0FAE_REG_6) },
11278   },
11279   {
11280     /* MOD_0FAE_REG_7 */
11281     { "clflush",        { Mb } },
11282     { RM_TABLE (RM_0FAE_REG_7) },
11283   },
11284   {
11285     /* MOD_0FB2 */
11286     { "lssS",           { Gv, Mp } },
11287   },
11288   {
11289     /* MOD_0FB4 */
11290     { "lfsS",           { Gv, Mp } },
11291   },
11292   {
11293     /* MOD_0FB5 */
11294     { "lgsS",           { Gv, Mp } },
11295   },
11296   {
11297     /* MOD_0FC7_REG_6 */
11298     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11299     { "rdrand",         { Ev } },
11300   },
11301   {
11302     /* MOD_0FC7_REG_7 */
11303     { "vmptrst",        { Mq } },
11304     { "rdseed",         { Ev } },
11305   },
11306   {
11307     /* MOD_0FD7 */
11308     { Bad_Opcode },
11309     { "pmovmskb",       { Gdq, MS } },
11310   },
11311   {
11312     /* MOD_0FE7_PREFIX_2 */
11313     { "movntdq",        { Mx, XM } },
11314   },
11315   {
11316     /* MOD_0FF0_PREFIX_3 */
11317     { "lddqu",          { XM, M } },
11318   },
11319   {
11320     /* MOD_0F382A_PREFIX_2 */
11321     { "movntdqa",       { XM, Mx } },
11322   },
11323   {
11324     /* MOD_62_32BIT */
11325     { "bound{S|}",      { Gv, Ma } },
11326     { EVEX_TABLE (EVEX_0F) },
11327   },
11328   {
11329     /* MOD_C4_32BIT */
11330     { "lesS",           { Gv, Mp } },
11331     { VEX_C4_TABLE (VEX_0F) },
11332   },
11333   {
11334     /* MOD_C5_32BIT */
11335     { "ldsS",           { Gv, Mp } },
11336     { VEX_C5_TABLE (VEX_0F) },
11337   },
11338   {
11339     /* MOD_VEX_0F12_PREFIX_0 */
11340     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11341     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11342   },
11343   {
11344     /* MOD_VEX_0F13 */
11345     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11346   },
11347   {
11348     /* MOD_VEX_0F16_PREFIX_0 */
11349     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11350     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11351   },
11352   {
11353     /* MOD_VEX_0F17 */
11354     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11355   },
11356   {
11357     /* MOD_VEX_0F2B */
11358     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11359   },
11360   {
11361     /* MOD_VEX_0F50 */
11362     { Bad_Opcode },
11363     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11364   },
11365   {
11366     /* MOD_VEX_0F71_REG_2 */
11367     { Bad_Opcode },
11368     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11369   },
11370   {
11371     /* MOD_VEX_0F71_REG_4 */
11372     { Bad_Opcode },
11373     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11374   },
11375   {
11376     /* MOD_VEX_0F71_REG_6 */
11377     { Bad_Opcode },
11378     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11379   },
11380   {
11381     /* MOD_VEX_0F72_REG_2 */
11382     { Bad_Opcode },
11383     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11384   },
11385   {
11386     /* MOD_VEX_0F72_REG_4 */
11387     { Bad_Opcode },
11388     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11389   },
11390   {
11391     /* MOD_VEX_0F72_REG_6 */
11392     { Bad_Opcode },
11393     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11394   },
11395   {
11396     /* MOD_VEX_0F73_REG_2 */
11397     { Bad_Opcode },
11398     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11399   },
11400   {
11401     /* MOD_VEX_0F73_REG_3 */
11402     { Bad_Opcode },
11403     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11404   },
11405   {
11406     /* MOD_VEX_0F73_REG_6 */
11407     { Bad_Opcode },
11408     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11409   },
11410   {
11411     /* MOD_VEX_0F73_REG_7 */
11412     { Bad_Opcode },
11413     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11414   },
11415   {
11416     /* MOD_VEX_0FAE_REG_2 */
11417     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11418   },
11419   {
11420     /* MOD_VEX_0FAE_REG_3 */
11421     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11422   },
11423   {
11424     /* MOD_VEX_0FD7_PREFIX_2 */
11425     { Bad_Opcode },
11426     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11427   },
11428   {
11429     /* MOD_VEX_0FE7_PREFIX_2 */
11430     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11431   },
11432   {
11433     /* MOD_VEX_0FF0_PREFIX_3 */
11434     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11435   },
11436   {
11437     /* MOD_VEX_0F381A_PREFIX_2 */
11438     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11439   },
11440   {
11441     /* MOD_VEX_0F382A_PREFIX_2 */
11442     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11443   },
11444   {
11445     /* MOD_VEX_0F382C_PREFIX_2 */
11446     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11447   },
11448   {
11449     /* MOD_VEX_0F382D_PREFIX_2 */
11450     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11451   },
11452   {
11453     /* MOD_VEX_0F382E_PREFIX_2 */
11454     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11455   },
11456   {
11457     /* MOD_VEX_0F382F_PREFIX_2 */
11458     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11459   },
11460   {
11461     /* MOD_VEX_0F385A_PREFIX_2 */
11462     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11463   },
11464   {
11465     /* MOD_VEX_0F388C_PREFIX_2 */
11466     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11467   },
11468   {
11469     /* MOD_VEX_0F388E_PREFIX_2 */
11470     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11471   },
11472 #define NEED_MOD_TABLE
11473 #include "i386-dis-evex.h"
11474 #undef NEED_MOD_TABLE
11475 };
11476
11477 static const struct dis386 rm_table[][8] = {
11478   {
11479     /* RM_C6_REG_7 */
11480     { "xabort",         { Skip_MODRM, Ib } },
11481   },
11482   {
11483     /* RM_C7_REG_7 */
11484     { "xbeginT",        { Skip_MODRM, Jv } },
11485   },
11486   {
11487     /* RM_0F01_REG_0 */
11488     { Bad_Opcode },
11489     { "vmcall",         { Skip_MODRM } },
11490     { "vmlaunch",       { Skip_MODRM } },
11491     { "vmresume",       { Skip_MODRM } },
11492     { "vmxoff",         { Skip_MODRM } },
11493   },
11494   {
11495     /* RM_0F01_REG_1 */
11496     { "monitor",        { { OP_Monitor, 0 } } },
11497     { "mwait",          { { OP_Mwait, 0 } } },
11498     { "clac",           { Skip_MODRM } },
11499     { "stac",           { Skip_MODRM } },
11500   },
11501   {
11502     /* RM_0F01_REG_2 */
11503     { "xgetbv",         { Skip_MODRM } },
11504     { "xsetbv",         { Skip_MODRM } },
11505     { Bad_Opcode },
11506     { Bad_Opcode },
11507     { "vmfunc",         { Skip_MODRM } },
11508     { "xend",           { Skip_MODRM } },
11509     { "xtest",          { Skip_MODRM } },
11510     { Bad_Opcode },
11511   },
11512   {
11513     /* RM_0F01_REG_3 */
11514     { "vmrun",          { Skip_MODRM } },
11515     { "vmmcall",        { Skip_MODRM } },
11516     { "vmload",         { Skip_MODRM } },
11517     { "vmsave",         { Skip_MODRM } },
11518     { "stgi",           { Skip_MODRM } },
11519     { "clgi",           { Skip_MODRM } },
11520     { "skinit",         { Skip_MODRM } },
11521     { "invlpga",        { Skip_MODRM } },
11522   },
11523   {
11524     /* RM_0F01_REG_7 */
11525     { "swapgs",         { Skip_MODRM } },
11526     { "rdtscp",         { Skip_MODRM } },
11527   },
11528   {
11529     /* RM_0FAE_REG_5 */
11530     { "lfence",         { Skip_MODRM } },
11531   },
11532   {
11533     /* RM_0FAE_REG_6 */
11534     { "mfence",         { Skip_MODRM } },
11535   },
11536   {
11537     /* RM_0FAE_REG_7 */
11538     { "sfence",         { Skip_MODRM } },
11539   },
11540 };
11541
11542 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11543
11544 /* We use the high bit to indicate different name for the same
11545    prefix.  */
11546 #define ADDR16_PREFIX   (0x67 | 0x100)
11547 #define ADDR32_PREFIX   (0x67 | 0x200)
11548 #define DATA16_PREFIX   (0x66 | 0x100)
11549 #define DATA32_PREFIX   (0x66 | 0x200)
11550 #define REP_PREFIX      (0xf3 | 0x100)
11551 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11552 #define XRELEASE_PREFIX (0xf3 | 0x400)
11553 #define BND_PREFIX      (0xf2 | 0x400)
11554
11555 static int
11556 ckprefix (void)
11557 {
11558   int newrex, i, length;
11559   rex = 0;
11560   rex_ignored = 0;
11561   prefixes = 0;
11562   used_prefixes = 0;
11563   rex_used = 0;
11564   last_lock_prefix = -1;
11565   last_repz_prefix = -1;
11566   last_repnz_prefix = -1;
11567   last_data_prefix = -1;
11568   last_addr_prefix = -1;
11569   last_rex_prefix = -1;
11570   last_seg_prefix = -1;
11571   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11572     all_prefixes[i] = 0;
11573   i = 0;
11574   length = 0;
11575   /* The maximum instruction length is 15bytes.  */
11576   while (length < MAX_CODE_LENGTH - 1)
11577     {
11578       FETCH_DATA (the_info, codep + 1);
11579       newrex = 0;
11580       switch (*codep)
11581         {
11582         /* REX prefixes family.  */
11583         case 0x40:
11584         case 0x41:
11585         case 0x42:
11586         case 0x43:
11587         case 0x44:
11588         case 0x45:
11589         case 0x46:
11590         case 0x47:
11591         case 0x48:
11592         case 0x49:
11593         case 0x4a:
11594         case 0x4b:
11595         case 0x4c:
11596         case 0x4d:
11597         case 0x4e:
11598         case 0x4f:
11599           if (address_mode == mode_64bit)
11600             newrex = *codep;
11601           else
11602             return 1;
11603           last_rex_prefix = i;
11604           break;
11605         case 0xf3:
11606           prefixes |= PREFIX_REPZ;
11607           last_repz_prefix = i;
11608           break;
11609         case 0xf2:
11610           prefixes |= PREFIX_REPNZ;
11611           last_repnz_prefix = i;
11612           break;
11613         case 0xf0:
11614           prefixes |= PREFIX_LOCK;
11615           last_lock_prefix = i;
11616           break;
11617         case 0x2e:
11618           prefixes |= PREFIX_CS;
11619           last_seg_prefix = i;
11620           break;
11621         case 0x36:
11622           prefixes |= PREFIX_SS;
11623           last_seg_prefix = i;
11624           break;
11625         case 0x3e:
11626           prefixes |= PREFIX_DS;
11627           last_seg_prefix = i;
11628           break;
11629         case 0x26:
11630           prefixes |= PREFIX_ES;
11631           last_seg_prefix = i;
11632           break;
11633         case 0x64:
11634           prefixes |= PREFIX_FS;
11635           last_seg_prefix = i;
11636           break;
11637         case 0x65:
11638           prefixes |= PREFIX_GS;
11639           last_seg_prefix = i;
11640           break;
11641         case 0x66:
11642           prefixes |= PREFIX_DATA;
11643           last_data_prefix = i;
11644           break;
11645         case 0x67:
11646           prefixes |= PREFIX_ADDR;
11647           last_addr_prefix = i;
11648           break;
11649         case FWAIT_OPCODE:
11650           /* fwait is really an instruction.  If there are prefixes
11651              before the fwait, they belong to the fwait, *not* to the
11652              following instruction.  */
11653           if (prefixes || rex)
11654             {
11655               prefixes |= PREFIX_FWAIT;
11656               codep++;
11657               /* This ensures that the previous REX prefixes are noticed
11658                  as unused prefixes, as in the return case below.  */
11659               rex_used = rex;
11660               return 1;
11661             }
11662           prefixes = PREFIX_FWAIT;
11663           break;
11664         default:
11665           return 1;
11666         }
11667       /* Rex is ignored when followed by another prefix.  */
11668       if (rex)
11669         {
11670           rex_used = rex;
11671           return 1;
11672         }
11673       if (*codep != FWAIT_OPCODE)
11674         all_prefixes[i++] = *codep;
11675       rex = newrex;
11676       codep++;
11677       length++;
11678     }
11679   return 0;
11680 }
11681
11682 static int
11683 seg_prefix (int pref)
11684 {
11685   switch (pref)
11686     {
11687     case 0x2e:
11688       return PREFIX_CS;
11689     case 0x36:
11690       return PREFIX_SS;
11691     case 0x3e:
11692       return PREFIX_DS;
11693     case 0x26:
11694       return PREFIX_ES;
11695     case 0x64:
11696       return PREFIX_FS;
11697     case 0x65:
11698       return PREFIX_GS;
11699     default:
11700       return 0;
11701     }
11702 }
11703
11704 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11705    prefix byte.  */
11706
11707 static const char *
11708 prefix_name (int pref, int sizeflag)
11709 {
11710   static const char *rexes [16] =
11711     {
11712       "rex",            /* 0x40 */
11713       "rex.B",          /* 0x41 */
11714       "rex.X",          /* 0x42 */
11715       "rex.XB",         /* 0x43 */
11716       "rex.R",          /* 0x44 */
11717       "rex.RB",         /* 0x45 */
11718       "rex.RX",         /* 0x46 */
11719       "rex.RXB",        /* 0x47 */
11720       "rex.W",          /* 0x48 */
11721       "rex.WB",         /* 0x49 */
11722       "rex.WX",         /* 0x4a */
11723       "rex.WXB",        /* 0x4b */
11724       "rex.WR",         /* 0x4c */
11725       "rex.WRB",        /* 0x4d */
11726       "rex.WRX",        /* 0x4e */
11727       "rex.WRXB",       /* 0x4f */
11728     };
11729
11730   switch (pref)
11731     {
11732     /* REX prefixes family.  */
11733     case 0x40:
11734     case 0x41:
11735     case 0x42:
11736     case 0x43:
11737     case 0x44:
11738     case 0x45:
11739     case 0x46:
11740     case 0x47:
11741     case 0x48:
11742     case 0x49:
11743     case 0x4a:
11744     case 0x4b:
11745     case 0x4c:
11746     case 0x4d:
11747     case 0x4e:
11748     case 0x4f:
11749       return rexes [pref - 0x40];
11750     case 0xf3:
11751       return "repz";
11752     case 0xf2:
11753       return "repnz";
11754     case 0xf0:
11755       return "lock";
11756     case 0x2e:
11757       return "cs";
11758     case 0x36:
11759       return "ss";
11760     case 0x3e:
11761       return "ds";
11762     case 0x26:
11763       return "es";
11764     case 0x64:
11765       return "fs";
11766     case 0x65:
11767       return "gs";
11768     case 0x66:
11769       return (sizeflag & DFLAG) ? "data16" : "data32";
11770     case 0x67:
11771       if (address_mode == mode_64bit)
11772         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11773       else
11774         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11775     case FWAIT_OPCODE:
11776       return "fwait";
11777     case ADDR16_PREFIX:
11778       return "addr16";
11779     case ADDR32_PREFIX:
11780       return "addr32";
11781     case DATA16_PREFIX:
11782       return "data16";
11783     case DATA32_PREFIX:
11784       return "data32";
11785     case REP_PREFIX:
11786       return "rep";
11787     case XACQUIRE_PREFIX:
11788       return "xacquire";
11789     case XRELEASE_PREFIX:
11790       return "xrelease";
11791     case BND_PREFIX:
11792       return "bnd";
11793     default:
11794       return NULL;
11795     }
11796 }
11797
11798 static char op_out[MAX_OPERANDS][100];
11799 static int op_ad, op_index[MAX_OPERANDS];
11800 static int two_source_ops;
11801 static bfd_vma op_address[MAX_OPERANDS];
11802 static bfd_vma op_riprel[MAX_OPERANDS];
11803 static bfd_vma start_pc;
11804
11805 /*
11806  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11807  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11808  *   section of the "Virtual 8086 Mode" chapter.)
11809  * 'pc' should be the address of this instruction, it will
11810  *   be used to print the target address if this is a relative jump or call
11811  * The function returns the length of this instruction in bytes.
11812  */
11813
11814 static char intel_syntax;
11815 static char intel_mnemonic = !SYSV386_COMPAT;
11816 static char open_char;
11817 static char close_char;
11818 static char separator_char;
11819 static char scale_char;
11820
11821 /* Here for backwards compatibility.  When gdb stops using
11822    print_insn_i386_att and print_insn_i386_intel these functions can
11823    disappear, and print_insn_i386 be merged into print_insn.  */
11824 int
11825 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11826 {
11827   intel_syntax = 0;
11828
11829   return print_insn (pc, info);
11830 }
11831
11832 int
11833 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11834 {
11835   intel_syntax = 1;
11836
11837   return print_insn (pc, info);
11838 }
11839
11840 int
11841 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11842 {
11843   intel_syntax = -1;
11844
11845   return print_insn (pc, info);
11846 }
11847
11848 void
11849 print_i386_disassembler_options (FILE *stream)
11850 {
11851   fprintf (stream, _("\n\
11852 The following i386/x86-64 specific disassembler options are supported for use\n\
11853 with the -M switch (multiple options should be separated by commas):\n"));
11854
11855   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11856   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11857   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11858   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11859   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11860   fprintf (stream, _("  att-mnemonic\n"
11861                      "              Display instruction in AT&T mnemonic\n"));
11862   fprintf (stream, _("  intel-mnemonic\n"
11863                      "              Display instruction in Intel mnemonic\n"));
11864   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11865   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11866   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11867   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11868   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11869   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11870 }
11871
11872 /* Bad opcode.  */
11873 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11874
11875 /* Get a pointer to struct dis386 with a valid name.  */
11876
11877 static const struct dis386 *
11878 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11879 {
11880   int vindex, vex_table_index;
11881
11882   if (dp->name != NULL)
11883     return dp;
11884
11885   switch (dp->op[0].bytemode)
11886     {
11887     case USE_REG_TABLE:
11888       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11889       break;
11890
11891     case USE_MOD_TABLE:
11892       vindex = modrm.mod == 0x3 ? 1 : 0;
11893       dp = &mod_table[dp->op[1].bytemode][vindex];
11894       break;
11895
11896     case USE_RM_TABLE:
11897       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11898       break;
11899
11900     case USE_PREFIX_TABLE:
11901       if (need_vex)
11902         {
11903           /* The prefix in VEX is implicit.  */
11904           switch (vex.prefix)
11905             {
11906             case 0:
11907               vindex = 0;
11908               break;
11909             case REPE_PREFIX_OPCODE:
11910               vindex = 1;
11911               break;
11912             case DATA_PREFIX_OPCODE:
11913               vindex = 2;
11914               break;
11915             case REPNE_PREFIX_OPCODE:
11916               vindex = 3;
11917               break;
11918             default:
11919               abort ();
11920               break;
11921             }
11922         }
11923       else
11924         {
11925           vindex = 0;
11926           used_prefixes |= (prefixes & PREFIX_REPZ);
11927           if (prefixes & PREFIX_REPZ)
11928             {
11929               vindex = 1;
11930               all_prefixes[last_repz_prefix] = 0;
11931             }
11932           else
11933             {
11934               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11935                  PREFIX_DATA.  */
11936               used_prefixes |= (prefixes & PREFIX_REPNZ);
11937               if (prefixes & PREFIX_REPNZ)
11938                 {
11939                   vindex = 3;
11940                   all_prefixes[last_repnz_prefix] = 0;
11941                 }
11942               else
11943                 {
11944                   used_prefixes |= (prefixes & PREFIX_DATA);
11945                   if (prefixes & PREFIX_DATA)
11946                     {
11947                       vindex = 2;
11948                       all_prefixes[last_data_prefix] = 0;
11949                     }
11950                 }
11951             }
11952         }
11953       dp = &prefix_table[dp->op[1].bytemode][vindex];
11954       break;
11955
11956     case USE_X86_64_TABLE:
11957       vindex = address_mode == mode_64bit ? 1 : 0;
11958       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11959       break;
11960
11961     case USE_3BYTE_TABLE:
11962       FETCH_DATA (info, codep + 2);
11963       vindex = *codep++;
11964       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11965       modrm.mod = (*codep >> 6) & 3;
11966       modrm.reg = (*codep >> 3) & 7;
11967       modrm.rm = *codep & 7;
11968       break;
11969
11970     case USE_VEX_LEN_TABLE:
11971       if (!need_vex)
11972         abort ();
11973
11974       switch (vex.length)
11975         {
11976         case 128:
11977           vindex = 0;
11978           break;
11979         case 256:
11980           vindex = 1;
11981           break;
11982         default:
11983           abort ();
11984           break;
11985         }
11986
11987       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11988       break;
11989
11990     case USE_XOP_8F_TABLE:
11991       FETCH_DATA (info, codep + 3);
11992       /* All bits in the REX prefix are ignored.  */
11993       rex_ignored = rex;
11994       rex = ~(*codep >> 5) & 0x7;
11995
11996       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11997       switch ((*codep & 0x1f))
11998         {
11999         default:
12000           dp = &bad_opcode;
12001           return dp;
12002         case 0x8:
12003           vex_table_index = XOP_08;
12004           break;
12005         case 0x9:
12006           vex_table_index = XOP_09;
12007           break;
12008         case 0xa:
12009           vex_table_index = XOP_0A;
12010           break;
12011         }
12012       codep++;
12013       vex.w = *codep & 0x80;
12014       if (vex.w && address_mode == mode_64bit)
12015         rex |= REX_W;
12016
12017       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12018       if (address_mode != mode_64bit
12019           && vex.register_specifier > 0x7)
12020         {
12021           dp = &bad_opcode;
12022           return dp;
12023         }
12024
12025       vex.length = (*codep & 0x4) ? 256 : 128;
12026       switch ((*codep & 0x3))
12027         {
12028         case 0:
12029           vex.prefix = 0;
12030           break;
12031         case 1:
12032           vex.prefix = DATA_PREFIX_OPCODE;
12033           break;
12034         case 2:
12035           vex.prefix = REPE_PREFIX_OPCODE;
12036           break;
12037         case 3:
12038           vex.prefix = REPNE_PREFIX_OPCODE;
12039           break;
12040         }
12041       need_vex = 1;
12042       need_vex_reg = 1;
12043       codep++;
12044       vindex = *codep++;
12045       dp = &xop_table[vex_table_index][vindex];
12046
12047       FETCH_DATA (info, codep + 1);
12048       modrm.mod = (*codep >> 6) & 3;
12049       modrm.reg = (*codep >> 3) & 7;
12050       modrm.rm = *codep & 7;
12051       break;
12052
12053     case USE_VEX_C4_TABLE:
12054       /* VEX prefix.  */
12055       FETCH_DATA (info, codep + 3);
12056       /* All bits in the REX prefix are ignored.  */
12057       rex_ignored = rex;
12058       rex = ~(*codep >> 5) & 0x7;
12059       switch ((*codep & 0x1f))
12060         {
12061         default:
12062           dp = &bad_opcode;
12063           return dp;
12064         case 0x1:
12065           vex_table_index = VEX_0F;
12066           break;
12067         case 0x2:
12068           vex_table_index = VEX_0F38;
12069           break;
12070         case 0x3:
12071           vex_table_index = VEX_0F3A;
12072           break;
12073         }
12074       codep++;
12075       vex.w = *codep & 0x80;
12076       if (vex.w && address_mode == mode_64bit)
12077         rex |= REX_W;
12078
12079       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12080       if (address_mode != mode_64bit
12081           && vex.register_specifier > 0x7)
12082         {
12083           dp = &bad_opcode;
12084           return dp;
12085         }
12086
12087       vex.length = (*codep & 0x4) ? 256 : 128;
12088       switch ((*codep & 0x3))
12089         {
12090         case 0:
12091           vex.prefix = 0;
12092           break;
12093         case 1:
12094           vex.prefix = DATA_PREFIX_OPCODE;
12095           break;
12096         case 2:
12097           vex.prefix = REPE_PREFIX_OPCODE;
12098           break;
12099         case 3:
12100           vex.prefix = REPNE_PREFIX_OPCODE;
12101           break;
12102         }
12103       need_vex = 1;
12104       need_vex_reg = 1;
12105       codep++;
12106       vindex = *codep++;
12107       dp = &vex_table[vex_table_index][vindex];
12108       /* There is no MODRM byte for VEX [82|77].  */
12109       if (vindex != 0x77 && vindex != 0x82)
12110         {
12111           FETCH_DATA (info, codep + 1);
12112           modrm.mod = (*codep >> 6) & 3;
12113           modrm.reg = (*codep >> 3) & 7;
12114           modrm.rm = *codep & 7;
12115         }
12116       break;
12117
12118     case USE_VEX_C5_TABLE:
12119       /* VEX prefix.  */
12120       FETCH_DATA (info, codep + 2);
12121       /* All bits in the REX prefix are ignored.  */
12122       rex_ignored = rex;
12123       rex = (*codep & 0x80) ? 0 : REX_R;
12124
12125       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12126       if (address_mode != mode_64bit
12127           && vex.register_specifier > 0x7)
12128         {
12129           dp = &bad_opcode;
12130           return dp;
12131         }
12132
12133       vex.w = 0;
12134
12135       vex.length = (*codep & 0x4) ? 256 : 128;
12136       switch ((*codep & 0x3))
12137         {
12138         case 0:
12139           vex.prefix = 0;
12140           break;
12141         case 1:
12142           vex.prefix = DATA_PREFIX_OPCODE;
12143           break;
12144         case 2:
12145           vex.prefix = REPE_PREFIX_OPCODE;
12146           break;
12147         case 3:
12148           vex.prefix = REPNE_PREFIX_OPCODE;
12149           break;
12150         }
12151       need_vex = 1;
12152       need_vex_reg = 1;
12153       codep++;
12154       vindex = *codep++;
12155       dp = &vex_table[dp->op[1].bytemode][vindex];
12156       /* There is no MODRM byte for VEX [82|77].  */
12157       if (vindex != 0x77 && vindex != 0x82)
12158         {
12159           FETCH_DATA (info, codep + 1);
12160           modrm.mod = (*codep >> 6) & 3;
12161           modrm.reg = (*codep >> 3) & 7;
12162           modrm.rm = *codep & 7;
12163         }
12164       break;
12165
12166     case USE_VEX_W_TABLE:
12167       if (!need_vex)
12168         abort ();
12169
12170       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12171       break;
12172
12173     case USE_EVEX_TABLE:
12174       two_source_ops = 0;
12175       /* EVEX prefix.  */
12176       vex.evex = 1;
12177       FETCH_DATA (info, codep + 4);
12178       /* All bits in the REX prefix are ignored.  */
12179       rex_ignored = rex;
12180       /* The first byte after 0x62.  */
12181       rex = ~(*codep >> 5) & 0x7;
12182       vex.r = *codep & 0x10;
12183       switch ((*codep & 0xf))
12184         {
12185         default:
12186           return &bad_opcode;
12187         case 0x1:
12188           vex_table_index = EVEX_0F;
12189           break;
12190         case 0x2:
12191           vex_table_index = EVEX_0F38;
12192           break;
12193         case 0x3:
12194           vex_table_index = EVEX_0F3A;
12195           break;
12196         }
12197
12198       /* The second byte after 0x62.  */
12199       codep++;
12200       vex.w = *codep & 0x80;
12201       if (vex.w && address_mode == mode_64bit)
12202         rex |= REX_W;
12203
12204       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12205       if (address_mode != mode_64bit)
12206         {
12207           /* In 16/32-bit mode silently ignore following bits.  */
12208           rex &= ~REX_B;
12209           vex.r = 1;
12210           vex.v = 1;
12211           vex.register_specifier &= 0x7;
12212         }
12213
12214       /* The U bit.  */
12215       if (!(*codep & 0x4))
12216         return &bad_opcode;
12217
12218       switch ((*codep & 0x3))
12219         {
12220         case 0:
12221           vex.prefix = 0;
12222           break;
12223         case 1:
12224           vex.prefix = DATA_PREFIX_OPCODE;
12225           break;
12226         case 2:
12227           vex.prefix = REPE_PREFIX_OPCODE;
12228           break;
12229         case 3:
12230           vex.prefix = REPNE_PREFIX_OPCODE;
12231           break;
12232         }
12233
12234       /* The third byte after 0x62.  */
12235       codep++;
12236
12237       /* Remember the static rounding bits.  */
12238       vex.ll = (*codep >> 5) & 3;
12239       vex.b = (*codep & 0x10) != 0;
12240
12241       vex.v = *codep & 0x8;
12242       vex.mask_register_specifier = *codep & 0x7;
12243       vex.zeroing = *codep & 0x80;
12244
12245       need_vex = 1;
12246       need_vex_reg = 1;
12247       codep++;
12248       vindex = *codep++;
12249       dp = &evex_table[vex_table_index][vindex];
12250       FETCH_DATA (info, codep + 1);
12251       modrm.mod = (*codep >> 6) & 3;
12252       modrm.reg = (*codep >> 3) & 7;
12253       modrm.rm = *codep & 7;
12254
12255       /* Set vector length.  */
12256       if (modrm.mod == 3 && vex.b)
12257         vex.length = 512;
12258       else
12259         {
12260           switch (vex.ll)
12261             {
12262             case 0x0:
12263               vex.length = 128;
12264               break;
12265             case 0x1:
12266               vex.length = 256;
12267               break;
12268             case 0x2:
12269               vex.length = 512;
12270               break;
12271             default:
12272               return &bad_opcode;
12273             }
12274         }
12275       break;
12276
12277     case 0:
12278       dp = &bad_opcode;
12279       break;
12280
12281     default:
12282       abort ();
12283     }
12284
12285   if (dp->name != NULL)
12286     return dp;
12287   else
12288     return get_valid_dis386 (dp, info);
12289 }
12290
12291 static void
12292 get_sib (disassemble_info *info, int sizeflag)
12293 {
12294   /* If modrm.mod == 3, operand must be register.  */
12295   if (need_modrm
12296       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12297       && modrm.mod != 3
12298       && modrm.rm == 4)
12299     {
12300       FETCH_DATA (info, codep + 2);
12301       sib.index = (codep [1] >> 3) & 7;
12302       sib.scale = (codep [1] >> 6) & 3;
12303       sib.base = codep [1] & 7;
12304     }
12305 }
12306
12307 static int
12308 print_insn (bfd_vma pc, disassemble_info *info)
12309 {
12310   const struct dis386 *dp;
12311   int i;
12312   char *op_txt[MAX_OPERANDS];
12313   int needcomma;
12314   int sizeflag;
12315   const char *p;
12316   struct dis_private priv;
12317   int prefix_length;
12318   int default_prefixes;
12319
12320   priv.orig_sizeflag = AFLAG | DFLAG;
12321   if ((info->mach & bfd_mach_i386_i386) != 0)
12322     address_mode = mode_32bit;
12323   else if (info->mach == bfd_mach_i386_i8086)
12324     {
12325       address_mode = mode_16bit;
12326       priv.orig_sizeflag = 0;
12327     }
12328   else
12329     address_mode = mode_64bit;
12330
12331   if (intel_syntax == (char) -1)
12332     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12333
12334   for (p = info->disassembler_options; p != NULL; )
12335     {
12336       if (CONST_STRNEQ (p, "x86-64"))
12337         {
12338           address_mode = mode_64bit;
12339           priv.orig_sizeflag = AFLAG | DFLAG;
12340         }
12341       else if (CONST_STRNEQ (p, "i386"))
12342         {
12343           address_mode = mode_32bit;
12344           priv.orig_sizeflag = AFLAG | DFLAG;
12345         }
12346       else if (CONST_STRNEQ (p, "i8086"))
12347         {
12348           address_mode = mode_16bit;
12349           priv.orig_sizeflag = 0;
12350         }
12351       else if (CONST_STRNEQ (p, "intel"))
12352         {
12353           intel_syntax = 1;
12354           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12355             intel_mnemonic = 1;
12356         }
12357       else if (CONST_STRNEQ (p, "att"))
12358         {
12359           intel_syntax = 0;
12360           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12361             intel_mnemonic = 0;
12362         }
12363       else if (CONST_STRNEQ (p, "addr"))
12364         {
12365           if (address_mode == mode_64bit)
12366             {
12367               if (p[4] == '3' && p[5] == '2')
12368                 priv.orig_sizeflag &= ~AFLAG;
12369               else if (p[4] == '6' && p[5] == '4')
12370                 priv.orig_sizeflag |= AFLAG;
12371             }
12372           else
12373             {
12374               if (p[4] == '1' && p[5] == '6')
12375                 priv.orig_sizeflag &= ~AFLAG;
12376               else if (p[4] == '3' && p[5] == '2')
12377                 priv.orig_sizeflag |= AFLAG;
12378             }
12379         }
12380       else if (CONST_STRNEQ (p, "data"))
12381         {
12382           if (p[4] == '1' && p[5] == '6')
12383             priv.orig_sizeflag &= ~DFLAG;
12384           else if (p[4] == '3' && p[5] == '2')
12385             priv.orig_sizeflag |= DFLAG;
12386         }
12387       else if (CONST_STRNEQ (p, "suffix"))
12388         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12389
12390       p = strchr (p, ',');
12391       if (p != NULL)
12392         p++;
12393     }
12394
12395   if (intel_syntax)
12396     {
12397       names64 = intel_names64;
12398       names32 = intel_names32;
12399       names16 = intel_names16;
12400       names8 = intel_names8;
12401       names8rex = intel_names8rex;
12402       names_seg = intel_names_seg;
12403       names_mm = intel_names_mm;
12404       names_bnd = intel_names_bnd;
12405       names_xmm = intel_names_xmm;
12406       names_ymm = intel_names_ymm;
12407       names_zmm = intel_names_zmm;
12408       index64 = intel_index64;
12409       index32 = intel_index32;
12410       names_mask = intel_names_mask;
12411       index16 = intel_index16;
12412       open_char = '[';
12413       close_char = ']';
12414       separator_char = '+';
12415       scale_char = '*';
12416     }
12417   else
12418     {
12419       names64 = att_names64;
12420       names32 = att_names32;
12421       names16 = att_names16;
12422       names8 = att_names8;
12423       names8rex = att_names8rex;
12424       names_seg = att_names_seg;
12425       names_mm = att_names_mm;
12426       names_bnd = att_names_bnd;
12427       names_xmm = att_names_xmm;
12428       names_ymm = att_names_ymm;
12429       names_zmm = att_names_zmm;
12430       index64 = att_index64;
12431       index32 = att_index32;
12432       names_mask = att_names_mask;
12433       index16 = att_index16;
12434       open_char = '(';
12435       close_char =  ')';
12436       separator_char = ',';
12437       scale_char = ',';
12438     }
12439
12440   /* The output looks better if we put 7 bytes on a line, since that
12441      puts most long word instructions on a single line.  Use 8 bytes
12442      for Intel L1OM.  */
12443   if ((info->mach & bfd_mach_l1om) != 0)
12444     info->bytes_per_line = 8;
12445   else
12446     info->bytes_per_line = 7;
12447
12448   info->private_data = &priv;
12449   priv.max_fetched = priv.the_buffer;
12450   priv.insn_start = pc;
12451
12452   obuf[0] = 0;
12453   for (i = 0; i < MAX_OPERANDS; ++i)
12454     {
12455       op_out[i][0] = 0;
12456       op_index[i] = -1;
12457     }
12458
12459   the_info = info;
12460   start_pc = pc;
12461   start_codep = priv.the_buffer;
12462   codep = priv.the_buffer;
12463
12464   if (setjmp (priv.bailout) != 0)
12465     {
12466       const char *name;
12467
12468       /* Getting here means we tried for data but didn't get it.  That
12469          means we have an incomplete instruction of some sort.  Just
12470          print the first byte as a prefix or a .byte pseudo-op.  */
12471       if (codep > priv.the_buffer)
12472         {
12473           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12474           if (name != NULL)
12475             (*info->fprintf_func) (info->stream, "%s", name);
12476           else
12477             {
12478               /* Just print the first byte as a .byte instruction.  */
12479               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12480                                      (unsigned int) priv.the_buffer[0]);
12481             }
12482
12483           return 1;
12484         }
12485
12486       return -1;
12487     }
12488
12489   obufp = obuf;
12490   sizeflag = priv.orig_sizeflag;
12491
12492   if (!ckprefix () || rex_used)
12493     {
12494       /* Too many prefixes or unused REX prefixes.  */
12495       for (i = 0;
12496            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12497            i++)
12498         (*info->fprintf_func) (info->stream, "%s%s",
12499                                i == 0 ? "" : " ",
12500                                prefix_name (all_prefixes[i], sizeflag));
12501       return i;
12502     }
12503
12504   insn_codep = codep;
12505
12506   FETCH_DATA (info, codep + 1);
12507   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12508
12509   if (((prefixes & PREFIX_FWAIT)
12510        && ((*codep < 0xd8) || (*codep > 0xdf))))
12511     {
12512       (*info->fprintf_func) (info->stream, "fwait");
12513       return 1;
12514     }
12515
12516   if (*codep == 0x0f)
12517     {
12518       unsigned char threebyte;
12519       FETCH_DATA (info, codep + 2);
12520       threebyte = *++codep;
12521       dp = &dis386_twobyte[threebyte];
12522       need_modrm = twobyte_has_modrm[*codep];
12523       codep++;
12524     }
12525   else
12526     {
12527       dp = &dis386[*codep];
12528       need_modrm = onebyte_has_modrm[*codep];
12529       codep++;
12530     }
12531
12532   if ((prefixes & PREFIX_REPZ))
12533     used_prefixes |= PREFIX_REPZ;
12534   if ((prefixes & PREFIX_REPNZ))
12535     used_prefixes |= PREFIX_REPNZ;
12536   if ((prefixes & PREFIX_LOCK))
12537     used_prefixes |= PREFIX_LOCK;
12538
12539   default_prefixes = 0;
12540   if (prefixes & PREFIX_ADDR)
12541     {
12542       sizeflag ^= AFLAG;
12543       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
12544         {
12545           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12546             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
12547           else
12548             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12549           default_prefixes |= PREFIX_ADDR;
12550         }
12551     }
12552
12553   if ((prefixes & PREFIX_DATA))
12554     {
12555       sizeflag ^= DFLAG;
12556       if (dp->op[2].bytemode == cond_jump_mode
12557           && dp->op[0].bytemode == v_mode
12558           && !intel_syntax)
12559         {
12560           if (sizeflag & DFLAG)
12561             all_prefixes[last_data_prefix] = DATA32_PREFIX;
12562           else
12563             all_prefixes[last_data_prefix] = DATA16_PREFIX;
12564           default_prefixes |= PREFIX_DATA;
12565         }
12566       else if (rex & REX_W)
12567         {
12568           /* REX_W will override PREFIX_DATA.  */
12569           default_prefixes |= PREFIX_DATA;
12570         }
12571     }
12572
12573   if (need_modrm)
12574     {
12575       FETCH_DATA (info, codep + 1);
12576       modrm.mod = (*codep >> 6) & 3;
12577       modrm.reg = (*codep >> 3) & 7;
12578       modrm.rm = *codep & 7;
12579     }
12580
12581   need_vex = 0;
12582   need_vex_reg = 0;
12583   vex_w_done = 0;
12584   vex.evex = 0;
12585
12586   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12587     {
12588       get_sib (info, sizeflag);
12589       dofloat (sizeflag);
12590     }
12591   else
12592     {
12593       dp = get_valid_dis386 (dp, info);
12594       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12595         {
12596           get_sib (info, sizeflag);
12597           for (i = 0; i < MAX_OPERANDS; ++i)
12598             {
12599               obufp = op_out[i];
12600               op_ad = MAX_OPERANDS - 1 - i;
12601               if (dp->op[i].rtn)
12602                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12603               /* For EVEX instruction after the last operand masking
12604                  should be printed.  */
12605               if (i == 0 && vex.evex)
12606                 {
12607                   /* Don't print {%k0}.  */
12608                   if (vex.mask_register_specifier)
12609                     {
12610                       oappend ("{");
12611                       oappend (names_mask[vex.mask_register_specifier]);
12612                       oappend ("}");
12613                     }
12614                   if (vex.zeroing)
12615                     oappend ("{z}");
12616                 }
12617             }
12618         }
12619     }
12620
12621   /* See if any prefixes were not used.  If so, print the first one
12622      separately.  If we don't do this, we'll wind up printing an
12623      instruction stream which does not precisely correspond to the
12624      bytes we are disassembling.  */
12625   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
12626     {
12627       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12628         if (all_prefixes[i])
12629           {
12630             const char *name;
12631             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
12632             if (name == NULL)
12633               name = INTERNAL_DISASSEMBLER_ERROR;
12634             (*info->fprintf_func) (info->stream, "%s", name);
12635             return 1;
12636           }
12637     }
12638
12639   /* Check if the REX prefix is used.  */
12640   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
12641     all_prefixes[last_rex_prefix] = 0;
12642
12643   /* Check if the SEG prefix is used.  */
12644   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12645                    | PREFIX_FS | PREFIX_GS)) != 0
12646       && (used_prefixes
12647           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
12648     all_prefixes[last_seg_prefix] = 0;
12649
12650   /* Check if the ADDR prefix is used.  */
12651   if ((prefixes & PREFIX_ADDR) != 0
12652       && (used_prefixes & PREFIX_ADDR) != 0)
12653     all_prefixes[last_addr_prefix] = 0;
12654
12655   /* Check if the DATA prefix is used.  */
12656   if ((prefixes & PREFIX_DATA) != 0
12657       && (used_prefixes & PREFIX_DATA) != 0)
12658     all_prefixes[last_data_prefix] = 0;
12659
12660   prefix_length = 0;
12661   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12662     if (all_prefixes[i])
12663       {
12664         const char *name;
12665         name = prefix_name (all_prefixes[i], sizeflag);
12666         if (name == NULL)
12667           abort ();
12668         prefix_length += strlen (name) + 1;
12669         (*info->fprintf_func) (info->stream, "%s ", name);
12670       }
12671
12672   /* Check maximum code length.  */
12673   if ((codep - start_codep) > MAX_CODE_LENGTH)
12674     {
12675       (*info->fprintf_func) (info->stream, "(bad)");
12676       return MAX_CODE_LENGTH;
12677     }
12678
12679   obufp = mnemonicendp;
12680   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12681     oappend (" ");
12682   oappend (" ");
12683   (*info->fprintf_func) (info->stream, "%s", obuf);
12684
12685   /* The enter and bound instructions are printed with operands in the same
12686      order as the intel book; everything else is printed in reverse order.  */
12687   if (intel_syntax || two_source_ops)
12688     {
12689       bfd_vma riprel;
12690
12691       for (i = 0; i < MAX_OPERANDS; ++i)
12692         op_txt[i] = op_out[i];
12693
12694       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12695         {
12696           op_ad = op_index[i];
12697           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12698           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12699           riprel = op_riprel[i];
12700           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12701           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12702         }
12703     }
12704   else
12705     {
12706       for (i = 0; i < MAX_OPERANDS; ++i)
12707         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12708     }
12709
12710   needcomma = 0;
12711   for (i = 0; i < MAX_OPERANDS; ++i)
12712     if (*op_txt[i])
12713       {
12714         if (needcomma)
12715           (*info->fprintf_func) (info->stream, ",");
12716         if (op_index[i] != -1 && !op_riprel[i])
12717           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12718         else
12719           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12720         needcomma = 1;
12721       }
12722
12723   for (i = 0; i < MAX_OPERANDS; i++)
12724     if (op_index[i] != -1 && op_riprel[i])
12725       {
12726         (*info->fprintf_func) (info->stream, "        # ");
12727         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12728                                                 + op_address[op_index[i]]), info);
12729         break;
12730       }
12731   return codep - priv.the_buffer;
12732 }
12733
12734 static const char *float_mem[] = {
12735   /* d8 */
12736   "fadd{s|}",
12737   "fmul{s|}",
12738   "fcom{s|}",
12739   "fcomp{s|}",
12740   "fsub{s|}",
12741   "fsubr{s|}",
12742   "fdiv{s|}",
12743   "fdivr{s|}",
12744   /* d9 */
12745   "fld{s|}",
12746   "(bad)",
12747   "fst{s|}",
12748   "fstp{s|}",
12749   "fldenvIC",
12750   "fldcw",
12751   "fNstenvIC",
12752   "fNstcw",
12753   /* da */
12754   "fiadd{l|}",
12755   "fimul{l|}",
12756   "ficom{l|}",
12757   "ficomp{l|}",
12758   "fisub{l|}",
12759   "fisubr{l|}",
12760   "fidiv{l|}",
12761   "fidivr{l|}",
12762   /* db */
12763   "fild{l|}",
12764   "fisttp{l|}",
12765   "fist{l|}",
12766   "fistp{l|}",
12767   "(bad)",
12768   "fld{t||t|}",
12769   "(bad)",
12770   "fstp{t||t|}",
12771   /* dc */
12772   "fadd{l|}",
12773   "fmul{l|}",
12774   "fcom{l|}",
12775   "fcomp{l|}",
12776   "fsub{l|}",
12777   "fsubr{l|}",
12778   "fdiv{l|}",
12779   "fdivr{l|}",
12780   /* dd */
12781   "fld{l|}",
12782   "fisttp{ll|}",
12783   "fst{l||}",
12784   "fstp{l|}",
12785   "frstorIC",
12786   "(bad)",
12787   "fNsaveIC",
12788   "fNstsw",
12789   /* de */
12790   "fiadd",
12791   "fimul",
12792   "ficom",
12793   "ficomp",
12794   "fisub",
12795   "fisubr",
12796   "fidiv",
12797   "fidivr",
12798   /* df */
12799   "fild",
12800   "fisttp",
12801   "fist",
12802   "fistp",
12803   "fbld",
12804   "fild{ll|}",
12805   "fbstp",
12806   "fistp{ll|}",
12807 };
12808
12809 static const unsigned char float_mem_mode[] = {
12810   /* d8 */
12811   d_mode,
12812   d_mode,
12813   d_mode,
12814   d_mode,
12815   d_mode,
12816   d_mode,
12817   d_mode,
12818   d_mode,
12819   /* d9 */
12820   d_mode,
12821   0,
12822   d_mode,
12823   d_mode,
12824   0,
12825   w_mode,
12826   0,
12827   w_mode,
12828   /* da */
12829   d_mode,
12830   d_mode,
12831   d_mode,
12832   d_mode,
12833   d_mode,
12834   d_mode,
12835   d_mode,
12836   d_mode,
12837   /* db */
12838   d_mode,
12839   d_mode,
12840   d_mode,
12841   d_mode,
12842   0,
12843   t_mode,
12844   0,
12845   t_mode,
12846   /* dc */
12847   q_mode,
12848   q_mode,
12849   q_mode,
12850   q_mode,
12851   q_mode,
12852   q_mode,
12853   q_mode,
12854   q_mode,
12855   /* dd */
12856   q_mode,
12857   q_mode,
12858   q_mode,
12859   q_mode,
12860   0,
12861   0,
12862   0,
12863   w_mode,
12864   /* de */
12865   w_mode,
12866   w_mode,
12867   w_mode,
12868   w_mode,
12869   w_mode,
12870   w_mode,
12871   w_mode,
12872   w_mode,
12873   /* df */
12874   w_mode,
12875   w_mode,
12876   w_mode,
12877   w_mode,
12878   t_mode,
12879   q_mode,
12880   t_mode,
12881   q_mode
12882 };
12883
12884 #define ST { OP_ST, 0 }
12885 #define STi { OP_STi, 0 }
12886
12887 #define FGRPd9_2 NULL, { { NULL, 0 } }
12888 #define FGRPd9_4 NULL, { { NULL, 1 } }
12889 #define FGRPd9_5 NULL, { { NULL, 2 } }
12890 #define FGRPd9_6 NULL, { { NULL, 3 } }
12891 #define FGRPd9_7 NULL, { { NULL, 4 } }
12892 #define FGRPda_5 NULL, { { NULL, 5 } }
12893 #define FGRPdb_4 NULL, { { NULL, 6 } }
12894 #define FGRPde_3 NULL, { { NULL, 7 } }
12895 #define FGRPdf_4 NULL, { { NULL, 8 } }
12896
12897 static const struct dis386 float_reg[][8] = {
12898   /* d8 */
12899   {
12900     { "fadd",   { ST, STi } },
12901     { "fmul",   { ST, STi } },
12902     { "fcom",   { STi } },
12903     { "fcomp",  { STi } },
12904     { "fsub",   { ST, STi } },
12905     { "fsubr",  { ST, STi } },
12906     { "fdiv",   { ST, STi } },
12907     { "fdivr",  { ST, STi } },
12908   },
12909   /* d9 */
12910   {
12911     { "fld",    { STi } },
12912     { "fxch",   { STi } },
12913     { FGRPd9_2 },
12914     { Bad_Opcode },
12915     { FGRPd9_4 },
12916     { FGRPd9_5 },
12917     { FGRPd9_6 },
12918     { FGRPd9_7 },
12919   },
12920   /* da */
12921   {
12922     { "fcmovb", { ST, STi } },
12923     { "fcmove", { ST, STi } },
12924     { "fcmovbe",{ ST, STi } },
12925     { "fcmovu", { ST, STi } },
12926     { Bad_Opcode },
12927     { FGRPda_5 },
12928     { Bad_Opcode },
12929     { Bad_Opcode },
12930   },
12931   /* db */
12932   {
12933     { "fcmovnb",{ ST, STi } },
12934     { "fcmovne",{ ST, STi } },
12935     { "fcmovnbe",{ ST, STi } },
12936     { "fcmovnu",{ ST, STi } },
12937     { FGRPdb_4 },
12938     { "fucomi", { ST, STi } },
12939     { "fcomi",  { ST, STi } },
12940     { Bad_Opcode },
12941   },
12942   /* dc */
12943   {
12944     { "fadd",   { STi, ST } },
12945     { "fmul",   { STi, ST } },
12946     { Bad_Opcode },
12947     { Bad_Opcode },
12948     { "fsub!M", { STi, ST } },
12949     { "fsubM",  { STi, ST } },
12950     { "fdiv!M", { STi, ST } },
12951     { "fdivM",  { STi, ST } },
12952   },
12953   /* dd */
12954   {
12955     { "ffree",  { STi } },
12956     { Bad_Opcode },
12957     { "fst",    { STi } },
12958     { "fstp",   { STi } },
12959     { "fucom",  { STi } },
12960     { "fucomp", { STi } },
12961     { Bad_Opcode },
12962     { Bad_Opcode },
12963   },
12964   /* de */
12965   {
12966     { "faddp",  { STi, ST } },
12967     { "fmulp",  { STi, ST } },
12968     { Bad_Opcode },
12969     { FGRPde_3 },
12970     { "fsub!Mp", { STi, ST } },
12971     { "fsubMp", { STi, ST } },
12972     { "fdiv!Mp", { STi, ST } },
12973     { "fdivMp", { STi, ST } },
12974   },
12975   /* df */
12976   {
12977     { "ffreep", { STi } },
12978     { Bad_Opcode },
12979     { Bad_Opcode },
12980     { Bad_Opcode },
12981     { FGRPdf_4 },
12982     { "fucomip", { ST, STi } },
12983     { "fcomip", { ST, STi } },
12984     { Bad_Opcode },
12985   },
12986 };
12987
12988 static char *fgrps[][8] = {
12989   /* d9_2  0 */
12990   {
12991     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12992   },
12993
12994   /* d9_4  1 */
12995   {
12996     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12997   },
12998
12999   /* d9_5  2 */
13000   {
13001     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13002   },
13003
13004   /* d9_6  3 */
13005   {
13006     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13007   },
13008
13009   /* d9_7  4 */
13010   {
13011     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13012   },
13013
13014   /* da_5  5 */
13015   {
13016     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13017   },
13018
13019   /* db_4  6 */
13020   {
13021     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13022     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13023   },
13024
13025   /* de_3  7 */
13026   {
13027     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13028   },
13029
13030   /* df_4  8 */
13031   {
13032     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13033   },
13034 };
13035
13036 static void
13037 swap_operand (void)
13038 {
13039   mnemonicendp[0] = '.';
13040   mnemonicendp[1] = 's';
13041   mnemonicendp += 2;
13042 }
13043
13044 static void
13045 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13046                int sizeflag ATTRIBUTE_UNUSED)
13047 {
13048   /* Skip mod/rm byte.  */
13049   MODRM_CHECK;
13050   codep++;
13051 }
13052
13053 static void
13054 dofloat (int sizeflag)
13055 {
13056   const struct dis386 *dp;
13057   unsigned char floatop;
13058
13059   floatop = codep[-1];
13060
13061   if (modrm.mod != 3)
13062     {
13063       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13064
13065       putop (float_mem[fp_indx], sizeflag);
13066       obufp = op_out[0];
13067       op_ad = 2;
13068       OP_E (float_mem_mode[fp_indx], sizeflag);
13069       return;
13070     }
13071   /* Skip mod/rm byte.  */
13072   MODRM_CHECK;
13073   codep++;
13074
13075   dp = &float_reg[floatop - 0xd8][modrm.reg];
13076   if (dp->name == NULL)
13077     {
13078       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13079
13080       /* Instruction fnstsw is only one with strange arg.  */
13081       if (floatop == 0xdf && codep[-1] == 0xe0)
13082         strcpy (op_out[0], names16[0]);
13083     }
13084   else
13085     {
13086       putop (dp->name, sizeflag);
13087
13088       obufp = op_out[0];
13089       op_ad = 2;
13090       if (dp->op[0].rtn)
13091         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13092
13093       obufp = op_out[1];
13094       op_ad = 1;
13095       if (dp->op[1].rtn)
13096         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13097     }
13098 }
13099
13100 static void
13101 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13102 {
13103   oappend ("%st" + intel_syntax);
13104 }
13105
13106 static void
13107 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13108 {
13109   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13110   oappend (scratchbuf + intel_syntax);
13111 }
13112
13113 /* Capital letters in template are macros.  */
13114 static int
13115 putop (const char *in_template, int sizeflag)
13116 {
13117   const char *p;
13118   int alt = 0;
13119   int cond = 1;
13120   unsigned int l = 0, len = 1;
13121   char last[4];
13122
13123 #define SAVE_LAST(c)                    \
13124   if (l < len && l < sizeof (last))     \
13125     last[l++] = c;                      \
13126   else                                  \
13127     abort ();
13128
13129   for (p = in_template; *p; p++)
13130     {
13131       switch (*p)
13132         {
13133         default:
13134           *obufp++ = *p;
13135           break;
13136         case '%':
13137           len++;
13138           break;
13139         case '!':
13140           cond = 0;
13141           break;
13142         case '{':
13143           alt = 0;
13144           if (intel_syntax)
13145             {
13146               while (*++p != '|')
13147                 if (*p == '}' || *p == '\0')
13148                   abort ();
13149             }
13150           /* Fall through.  */
13151         case 'I':
13152           alt = 1;
13153           continue;
13154         case '|':
13155           while (*++p != '}')
13156             {
13157               if (*p == '\0')
13158                 abort ();
13159             }
13160           break;
13161         case '}':
13162           break;
13163         case 'A':
13164           if (intel_syntax)
13165             break;
13166           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13167             *obufp++ = 'b';
13168           break;
13169         case 'B':
13170           if (l == 0 && len == 1)
13171             {
13172 case_B:
13173               if (intel_syntax)
13174                 break;
13175               if (sizeflag & SUFFIX_ALWAYS)
13176                 *obufp++ = 'b';
13177             }
13178           else
13179             {
13180               if (l != 1
13181                   || len != 2
13182                   || last[0] != 'L')
13183                 {
13184                   SAVE_LAST (*p);
13185                   break;
13186                 }
13187
13188               if (address_mode == mode_64bit
13189                   && !(prefixes & PREFIX_ADDR))
13190                 {
13191                   *obufp++ = 'a';
13192                   *obufp++ = 'b';
13193                   *obufp++ = 's';
13194                 }
13195
13196               goto case_B;
13197             }
13198           break;
13199         case 'C':
13200           if (intel_syntax && !alt)
13201             break;
13202           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13203             {
13204               if (sizeflag & DFLAG)
13205                 *obufp++ = intel_syntax ? 'd' : 'l';
13206               else
13207                 *obufp++ = intel_syntax ? 'w' : 's';
13208               used_prefixes |= (prefixes & PREFIX_DATA);
13209             }
13210           break;
13211         case 'D':
13212           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13213             break;
13214           USED_REX (REX_W);
13215           if (modrm.mod == 3)
13216             {
13217               if (rex & REX_W)
13218                 *obufp++ = 'q';
13219               else
13220                 {
13221                   if (sizeflag & DFLAG)
13222                     *obufp++ = intel_syntax ? 'd' : 'l';
13223                   else
13224                     *obufp++ = 'w';
13225                   used_prefixes |= (prefixes & PREFIX_DATA);
13226                 }
13227             }
13228           else
13229             *obufp++ = 'w';
13230           break;
13231         case 'E':               /* For jcxz/jecxz */
13232           if (address_mode == mode_64bit)
13233             {
13234               if (sizeflag & AFLAG)
13235                 *obufp++ = 'r';
13236               else
13237                 *obufp++ = 'e';
13238             }
13239           else
13240             if (sizeflag & AFLAG)
13241               *obufp++ = 'e';
13242           used_prefixes |= (prefixes & PREFIX_ADDR);
13243           break;
13244         case 'F':
13245           if (intel_syntax)
13246             break;
13247           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13248             {
13249               if (sizeflag & AFLAG)
13250                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13251               else
13252                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13253               used_prefixes |= (prefixes & PREFIX_ADDR);
13254             }
13255           break;
13256         case 'G':
13257           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13258             break;
13259           if ((rex & REX_W) || (sizeflag & DFLAG))
13260             *obufp++ = 'l';
13261           else
13262             *obufp++ = 'w';
13263           if (!(rex & REX_W))
13264             used_prefixes |= (prefixes & PREFIX_DATA);
13265           break;
13266         case 'H':
13267           if (intel_syntax)
13268             break;
13269           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13270               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13271             {
13272               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13273               *obufp++ = ',';
13274               *obufp++ = 'p';
13275               if (prefixes & PREFIX_DS)
13276                 *obufp++ = 't';
13277               else
13278                 *obufp++ = 'n';
13279             }
13280           break;
13281         case 'J':
13282           if (intel_syntax)
13283             break;
13284           *obufp++ = 'l';
13285           break;
13286         case 'K':
13287           USED_REX (REX_W);
13288           if (rex & REX_W)
13289             *obufp++ = 'q';
13290           else
13291             *obufp++ = 'd';
13292           break;
13293         case 'Z':
13294           if (intel_syntax)
13295             break;
13296           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13297             {
13298               *obufp++ = 'q';
13299               break;
13300             }
13301           /* Fall through.  */
13302           goto case_L;
13303         case 'L':
13304           if (l != 0 || len != 1)
13305             {
13306               SAVE_LAST (*p);
13307               break;
13308             }
13309 case_L:
13310           if (intel_syntax)
13311             break;
13312           if (sizeflag & SUFFIX_ALWAYS)
13313             *obufp++ = 'l';
13314           break;
13315         case 'M':
13316           if (intel_mnemonic != cond)
13317             *obufp++ = 'r';
13318           break;
13319         case 'N':
13320           if ((prefixes & PREFIX_FWAIT) == 0)
13321             *obufp++ = 'n';
13322           else
13323             used_prefixes |= PREFIX_FWAIT;
13324           break;
13325         case 'O':
13326           USED_REX (REX_W);
13327           if (rex & REX_W)
13328             *obufp++ = 'o';
13329           else if (intel_syntax && (sizeflag & DFLAG))
13330             *obufp++ = 'q';
13331           else
13332             *obufp++ = 'd';
13333           if (!(rex & REX_W))
13334             used_prefixes |= (prefixes & PREFIX_DATA);
13335           break;
13336         case 'T':
13337           if (!intel_syntax
13338               && address_mode == mode_64bit
13339               && ((sizeflag & DFLAG) || (rex & REX_W)))
13340             {
13341               *obufp++ = 'q';
13342               break;
13343             }
13344           /* Fall through.  */
13345         case 'P':
13346           if (intel_syntax)
13347             {
13348               if ((rex & REX_W) == 0
13349                   && (prefixes & PREFIX_DATA))
13350                 {
13351                   if ((sizeflag & DFLAG) == 0)
13352                     *obufp++ = 'w';
13353                    used_prefixes |= (prefixes & PREFIX_DATA);
13354                 }
13355               break;
13356             }
13357           if ((prefixes & PREFIX_DATA)
13358               || (rex & REX_W)
13359               || (sizeflag & SUFFIX_ALWAYS))
13360             {
13361               USED_REX (REX_W);
13362               if (rex & REX_W)
13363                 *obufp++ = 'q';
13364               else
13365                 {
13366                    if (sizeflag & DFLAG)
13367                       *obufp++ = 'l';
13368                    else
13369                      *obufp++ = 'w';
13370                    used_prefixes |= (prefixes & PREFIX_DATA);
13371                 }
13372             }
13373           break;
13374         case 'U':
13375           if (intel_syntax)
13376             break;
13377           if (address_mode == mode_64bit
13378               && ((sizeflag & DFLAG) || (rex & REX_W)))
13379             {
13380               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13381                 *obufp++ = 'q';
13382               break;
13383             }
13384           /* Fall through.  */
13385           goto case_Q;
13386         case 'Q':
13387           if (l == 0 && len == 1)
13388             {
13389 case_Q:
13390               if (intel_syntax && !alt)
13391                 break;
13392               USED_REX (REX_W);
13393               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13394                 {
13395                   if (rex & REX_W)
13396                     *obufp++ = 'q';
13397                   else
13398                     {
13399                       if (sizeflag & DFLAG)
13400                         *obufp++ = intel_syntax ? 'd' : 'l';
13401                       else
13402                         *obufp++ = 'w';
13403                       used_prefixes |= (prefixes & PREFIX_DATA);
13404                     }
13405                 }
13406             }
13407           else
13408             {
13409               if (l != 1 || len != 2 || last[0] != 'L')
13410                 {
13411                   SAVE_LAST (*p);
13412                   break;
13413                 }
13414               if (intel_syntax
13415                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13416                 break;
13417               if ((rex & REX_W))
13418                 {
13419                   USED_REX (REX_W);
13420                   *obufp++ = 'q';
13421                 }
13422               else
13423                 *obufp++ = 'l';
13424             }
13425           break;
13426         case 'R':
13427           USED_REX (REX_W);
13428           if (rex & REX_W)
13429             *obufp++ = 'q';
13430           else if (sizeflag & DFLAG)
13431             {
13432               if (intel_syntax)
13433                   *obufp++ = 'd';
13434               else
13435                   *obufp++ = 'l';
13436             }
13437           else
13438             *obufp++ = 'w';
13439           if (intel_syntax && !p[1]
13440               && ((rex & REX_W) || (sizeflag & DFLAG)))
13441             *obufp++ = 'e';
13442           if (!(rex & REX_W))
13443             used_prefixes |= (prefixes & PREFIX_DATA);
13444           break;
13445         case 'V':
13446           if (l == 0 && len == 1)
13447             {
13448               if (intel_syntax)
13449                 break;
13450               if (address_mode == mode_64bit
13451                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13452                 {
13453                   if (sizeflag & SUFFIX_ALWAYS)
13454                     *obufp++ = 'q';
13455                   break;
13456                 }
13457             }
13458           else
13459             {
13460               if (l != 1
13461                   || len != 2
13462                   || last[0] != 'L')
13463                 {
13464                   SAVE_LAST (*p);
13465                   break;
13466                 }
13467
13468               if (rex & REX_W)
13469                 {
13470                   *obufp++ = 'a';
13471                   *obufp++ = 'b';
13472                   *obufp++ = 's';
13473                 }
13474             }
13475           /* Fall through.  */
13476           goto case_S;
13477         case 'S':
13478           if (l == 0 && len == 1)
13479             {
13480 case_S:
13481               if (intel_syntax)
13482                 break;
13483               if (sizeflag & SUFFIX_ALWAYS)
13484                 {
13485                   if (rex & REX_W)
13486                     *obufp++ = 'q';
13487                   else
13488                     {
13489                       if (sizeflag & DFLAG)
13490                         *obufp++ = 'l';
13491                       else
13492                         *obufp++ = 'w';
13493                       used_prefixes |= (prefixes & PREFIX_DATA);
13494                     }
13495                 }
13496             }
13497           else
13498             {
13499               if (l != 1
13500                   || len != 2
13501                   || last[0] != 'L')
13502                 {
13503                   SAVE_LAST (*p);
13504                   break;
13505                 }
13506
13507               if (address_mode == mode_64bit
13508                   && !(prefixes & PREFIX_ADDR))
13509                 {
13510                   *obufp++ = 'a';
13511                   *obufp++ = 'b';
13512                   *obufp++ = 's';
13513                 }
13514
13515               goto case_S;
13516             }
13517           break;
13518         case 'X':
13519           if (l != 0 || len != 1)
13520             {
13521               SAVE_LAST (*p);
13522               break;
13523             }
13524           if (need_vex && vex.prefix)
13525             {
13526               if (vex.prefix == DATA_PREFIX_OPCODE)
13527                 *obufp++ = 'd';
13528               else
13529                 *obufp++ = 's';
13530             }
13531           else
13532             {
13533               if (prefixes & PREFIX_DATA)
13534                 *obufp++ = 'd';
13535               else
13536                 *obufp++ = 's';
13537               used_prefixes |= (prefixes & PREFIX_DATA);
13538             }
13539           break;
13540         case 'Y':
13541           if (l == 0 && len == 1)
13542             {
13543               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13544                 break;
13545               if (rex & REX_W)
13546                 {
13547                   USED_REX (REX_W);
13548                   *obufp++ = 'q';
13549                 }
13550               break;
13551             }
13552           else
13553             {
13554               if (l != 1 || len != 2 || last[0] != 'X')
13555                 {
13556                   SAVE_LAST (*p);
13557                   break;
13558                 }
13559               if (!need_vex)
13560                 abort ();
13561               if (intel_syntax
13562                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13563                 break;
13564               switch (vex.length)
13565                 {
13566                 case 128:
13567                   *obufp++ = 'x';
13568                   break;
13569                 case 256:
13570                   *obufp++ = 'y';
13571                   break;
13572                 default:
13573                   abort ();
13574                 }
13575             }
13576           break;
13577         case 'W':
13578           if (l == 0 && len == 1)
13579             {
13580               /* operand size flag for cwtl, cbtw */
13581               USED_REX (REX_W);
13582               if (rex & REX_W)
13583                 {
13584                   if (intel_syntax)
13585                     *obufp++ = 'd';
13586                   else
13587                     *obufp++ = 'l';
13588                 }
13589               else if (sizeflag & DFLAG)
13590                 *obufp++ = 'w';
13591               else
13592                 *obufp++ = 'b';
13593               if (!(rex & REX_W))
13594                 used_prefixes |= (prefixes & PREFIX_DATA);
13595             }
13596           else
13597             {
13598               if (l != 1
13599                   || len != 2
13600                   || (last[0] != 'X'
13601                       && last[0] != 'L'))
13602                 {
13603                   SAVE_LAST (*p);
13604                   break;
13605                 }
13606               if (!need_vex)
13607                 abort ();
13608               if (last[0] == 'X')
13609                 *obufp++ = vex.w ? 'd': 's';
13610               else
13611                 *obufp++ = vex.w ? 'q': 'd';
13612             }
13613           break;
13614         }
13615       alt = 0;
13616     }
13617   *obufp = 0;
13618   mnemonicendp = obufp;
13619   return 0;
13620 }
13621
13622 static void
13623 oappend (const char *s)
13624 {
13625   obufp = stpcpy (obufp, s);
13626 }
13627
13628 static void
13629 append_seg (void)
13630 {
13631   if (prefixes & PREFIX_CS)
13632     {
13633       used_prefixes |= PREFIX_CS;
13634       oappend ("%cs:" + intel_syntax);
13635     }
13636   if (prefixes & PREFIX_DS)
13637     {
13638       used_prefixes |= PREFIX_DS;
13639       oappend ("%ds:" + intel_syntax);
13640     }
13641   if (prefixes & PREFIX_SS)
13642     {
13643       used_prefixes |= PREFIX_SS;
13644       oappend ("%ss:" + intel_syntax);
13645     }
13646   if (prefixes & PREFIX_ES)
13647     {
13648       used_prefixes |= PREFIX_ES;
13649       oappend ("%es:" + intel_syntax);
13650     }
13651   if (prefixes & PREFIX_FS)
13652     {
13653       used_prefixes |= PREFIX_FS;
13654       oappend ("%fs:" + intel_syntax);
13655     }
13656   if (prefixes & PREFIX_GS)
13657     {
13658       used_prefixes |= PREFIX_GS;
13659       oappend ("%gs:" + intel_syntax);
13660     }
13661 }
13662
13663 static void
13664 OP_indirE (int bytemode, int sizeflag)
13665 {
13666   if (!intel_syntax)
13667     oappend ("*");
13668   OP_E (bytemode, sizeflag);
13669 }
13670
13671 static void
13672 print_operand_value (char *buf, int hex, bfd_vma disp)
13673 {
13674   if (address_mode == mode_64bit)
13675     {
13676       if (hex)
13677         {
13678           char tmp[30];
13679           int i;
13680           buf[0] = '0';
13681           buf[1] = 'x';
13682           sprintf_vma (tmp, disp);
13683           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13684           strcpy (buf + 2, tmp + i);
13685         }
13686       else
13687         {
13688           bfd_signed_vma v = disp;
13689           char tmp[30];
13690           int i;
13691           if (v < 0)
13692             {
13693               *(buf++) = '-';
13694               v = -disp;
13695               /* Check for possible overflow on 0x8000000000000000.  */
13696               if (v < 0)
13697                 {
13698                   strcpy (buf, "9223372036854775808");
13699                   return;
13700                 }
13701             }
13702           if (!v)
13703             {
13704               strcpy (buf, "0");
13705               return;
13706             }
13707
13708           i = 0;
13709           tmp[29] = 0;
13710           while (v)
13711             {
13712               tmp[28 - i] = (v % 10) + '0';
13713               v /= 10;
13714               i++;
13715             }
13716           strcpy (buf, tmp + 29 - i);
13717         }
13718     }
13719   else
13720     {
13721       if (hex)
13722         sprintf (buf, "0x%x", (unsigned int) disp);
13723       else
13724         sprintf (buf, "%d", (int) disp);
13725     }
13726 }
13727
13728 /* Put DISP in BUF as signed hex number.  */
13729
13730 static void
13731 print_displacement (char *buf, bfd_vma disp)
13732 {
13733   bfd_signed_vma val = disp;
13734   char tmp[30];
13735   int i, j = 0;
13736
13737   if (val < 0)
13738     {
13739       buf[j++] = '-';
13740       val = -disp;
13741
13742       /* Check for possible overflow.  */
13743       if (val < 0)
13744         {
13745           switch (address_mode)
13746             {
13747             case mode_64bit:
13748               strcpy (buf + j, "0x8000000000000000");
13749               break;
13750             case mode_32bit:
13751               strcpy (buf + j, "0x80000000");
13752               break;
13753             case mode_16bit:
13754               strcpy (buf + j, "0x8000");
13755               break;
13756             }
13757           return;
13758         }
13759     }
13760
13761   buf[j++] = '0';
13762   buf[j++] = 'x';
13763
13764   sprintf_vma (tmp, (bfd_vma) val);
13765   for (i = 0; tmp[i] == '0'; i++)
13766     continue;
13767   if (tmp[i] == '\0')
13768     i--;
13769   strcpy (buf + j, tmp + i);
13770 }
13771
13772 static void
13773 intel_operand_size (int bytemode, int sizeflag)
13774 {
13775   if (vex.evex
13776       && vex.b
13777       && (bytemode == x_mode
13778           || bytemode == evex_half_bcst_xmmq_mode))
13779     {
13780       if (vex.w)
13781         oappend ("QWORD PTR ");
13782       else
13783         oappend ("DWORD PTR ");
13784       return;
13785     }
13786   switch (bytemode)
13787     {
13788     case b_mode:
13789     case b_swap_mode:
13790     case dqb_mode:
13791       oappend ("BYTE PTR ");
13792       break;
13793     case w_mode:
13794     case dqw_mode:
13795       oappend ("WORD PTR ");
13796       break;
13797     case stack_v_mode:
13798       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13799         {
13800           oappend ("QWORD PTR ");
13801           break;
13802         }
13803       /* FALLTHRU */
13804     case v_mode:
13805     case v_bnd_mode:
13806     case v_swap_mode:
13807     case dq_mode:
13808       USED_REX (REX_W);
13809       if (rex & REX_W)
13810         oappend ("QWORD PTR ");
13811       else
13812         {
13813           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13814             oappend ("DWORD PTR ");
13815           else
13816             oappend ("WORD PTR ");
13817           used_prefixes |= (prefixes & PREFIX_DATA);
13818         }
13819       break;
13820     case z_mode:
13821       if ((rex & REX_W) || (sizeflag & DFLAG))
13822         *obufp++ = 'D';
13823       oappend ("WORD PTR ");
13824       if (!(rex & REX_W))
13825         used_prefixes |= (prefixes & PREFIX_DATA);
13826       break;
13827     case a_mode:
13828       if (sizeflag & DFLAG)
13829         oappend ("QWORD PTR ");
13830       else
13831         oappend ("DWORD PTR ");
13832       used_prefixes |= (prefixes & PREFIX_DATA);
13833       break;
13834     case d_mode:
13835     case d_scalar_mode:
13836     case d_scalar_swap_mode:
13837     case d_swap_mode:
13838     case dqd_mode:
13839       oappend ("DWORD PTR ");
13840       break;
13841     case q_mode:
13842     case q_scalar_mode:
13843     case q_scalar_swap_mode:
13844     case q_swap_mode:
13845       oappend ("QWORD PTR ");
13846       break;
13847     case m_mode:
13848       if (address_mode == mode_64bit)
13849         oappend ("QWORD PTR ");
13850       else
13851         oappend ("DWORD PTR ");
13852       break;
13853     case f_mode:
13854       if (sizeflag & DFLAG)
13855         oappend ("FWORD PTR ");
13856       else
13857         oappend ("DWORD PTR ");
13858       used_prefixes |= (prefixes & PREFIX_DATA);
13859       break;
13860     case t_mode:
13861       oappend ("TBYTE PTR ");
13862       break;
13863     case x_mode:
13864     case x_swap_mode:
13865     case evex_x_gscat_mode:
13866     case evex_x_nobcst_mode:
13867       if (need_vex)
13868         {
13869           switch (vex.length)
13870             {
13871             case 128:
13872               oappend ("XMMWORD PTR ");
13873               break;
13874             case 256:
13875               oappend ("YMMWORD PTR ");
13876               break;
13877             case 512:
13878               oappend ("ZMMWORD PTR ");
13879               break;
13880             default:
13881               abort ();
13882             }
13883         }
13884       else
13885         oappend ("XMMWORD PTR ");
13886       break;
13887     case xmm_mode:
13888       oappend ("XMMWORD PTR ");
13889       break;
13890     case ymm_mode:
13891       oappend ("YMMWORD PTR ");
13892       break;
13893     case xmmq_mode:
13894     case evex_half_bcst_xmmq_mode:
13895       if (!need_vex)
13896         abort ();
13897
13898       switch (vex.length)
13899         {
13900         case 128:
13901           oappend ("QWORD PTR ");
13902           break;
13903         case 256:
13904           oappend ("XMMWORD PTR ");
13905           break;
13906         case 512:
13907           oappend ("YMMWORD PTR ");
13908           break;
13909         default:
13910           abort ();
13911         }
13912       break;
13913     case xmm_mb_mode:
13914       if (!need_vex)
13915         abort ();
13916
13917       switch (vex.length)
13918         {
13919         case 128:
13920         case 256:
13921         case 512:
13922           oappend ("BYTE PTR ");
13923           break;
13924         default:
13925           abort ();
13926         }
13927       break;
13928     case xmm_mw_mode:
13929       if (!need_vex)
13930         abort ();
13931
13932       switch (vex.length)
13933         {
13934         case 128:
13935         case 256:
13936         case 512:
13937           oappend ("WORD PTR ");
13938           break;
13939         default:
13940           abort ();
13941         }
13942       break;
13943     case xmm_md_mode:
13944       if (!need_vex)
13945         abort ();
13946
13947       switch (vex.length)
13948         {
13949         case 128:
13950         case 256:
13951         case 512:
13952           oappend ("DWORD PTR ");
13953           break;
13954         default:
13955           abort ();
13956         }
13957       break;
13958     case xmm_mq_mode:
13959       if (!need_vex)
13960         abort ();
13961
13962       switch (vex.length)
13963         {
13964         case 128:
13965         case 256:
13966         case 512:
13967           oappend ("QWORD PTR ");
13968           break;
13969         default:
13970           abort ();
13971         }
13972       break;
13973     case xmmdw_mode:
13974       if (!need_vex)
13975         abort ();
13976
13977       switch (vex.length)
13978         {
13979         case 128:
13980           oappend ("WORD PTR ");
13981           break;
13982         case 256:
13983           oappend ("DWORD PTR ");
13984           break;
13985         case 512:
13986           oappend ("QWORD PTR ");
13987           break;
13988         default:
13989           abort ();
13990         }
13991       break;
13992     case xmmqd_mode:
13993       if (!need_vex)
13994         abort ();
13995
13996       switch (vex.length)
13997         {
13998         case 128:
13999           oappend ("DWORD PTR ");
14000           break;
14001         case 256:
14002           oappend ("QWORD PTR ");
14003           break;
14004         case 512:
14005           oappend ("XMMWORD PTR ");
14006           break;
14007         default:
14008           abort ();
14009         }
14010       break;
14011     case ymmq_mode:
14012       if (!need_vex)
14013         abort ();
14014
14015       switch (vex.length)
14016         {
14017         case 128:
14018           oappend ("QWORD PTR ");
14019           break;
14020         case 256:
14021           oappend ("YMMWORD PTR ");
14022           break;
14023         case 512:
14024           oappend ("ZMMWORD PTR ");
14025           break;
14026         default:
14027           abort ();
14028         }
14029       break;
14030     case ymmxmm_mode:
14031       if (!need_vex)
14032         abort ();
14033
14034       switch (vex.length)
14035         {
14036         case 128:
14037         case 256:
14038           oappend ("XMMWORD PTR ");
14039           break;
14040         default:
14041           abort ();
14042         }
14043       break;
14044     case o_mode:
14045       oappend ("OWORD PTR ");
14046       break;
14047     case xmm_mdq_mode:
14048     case vex_w_dq_mode:
14049     case vex_scalar_w_dq_mode:
14050       if (!need_vex)
14051         abort ();
14052
14053       if (vex.w)
14054         oappend ("QWORD PTR ");
14055       else
14056         oappend ("DWORD PTR ");
14057       break;
14058     case vex_vsib_d_w_dq_mode:
14059     case vex_vsib_q_w_dq_mode:
14060       if (!need_vex)
14061         abort ();
14062
14063       if (!vex.evex)
14064         {
14065           if (vex.w)
14066             oappend ("QWORD PTR ");
14067           else
14068             oappend ("DWORD PTR ");
14069         }
14070       else
14071         {
14072           if (vex.length != 512)
14073             abort ();
14074           oappend ("ZMMWORD PTR ");
14075         }
14076       break;
14077     case mask_mode:
14078       if (!need_vex)
14079         abort ();
14080       /* Currently the only instructions, which allows either mask or
14081          memory operand, are AVX512's KMOVW instructions.  They need
14082          Word-sized operand.  */
14083       if (vex.w || vex.length != 128)
14084         abort ();
14085       oappend ("WORD PTR ");
14086       break;
14087     default:
14088       break;
14089     }
14090 }
14091
14092 static void
14093 OP_E_register (int bytemode, int sizeflag)
14094 {
14095   int reg = modrm.rm;
14096   const char **names;
14097
14098   USED_REX (REX_B);
14099   if ((rex & REX_B))
14100     reg += 8;
14101
14102   if ((sizeflag & SUFFIX_ALWAYS)
14103       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14104     swap_operand ();
14105
14106   switch (bytemode)
14107     {
14108     case b_mode:
14109     case b_swap_mode:
14110       USED_REX (0);
14111       if (rex)
14112         names = names8rex;
14113       else
14114         names = names8;
14115       break;
14116     case w_mode:
14117       names = names16;
14118       break;
14119     case d_mode:
14120       names = names32;
14121       break;
14122     case q_mode:
14123       names = names64;
14124       break;
14125     case m_mode:
14126       names = address_mode == mode_64bit ? names64 : names32;
14127       break;
14128     case bnd_mode:
14129       names = names_bnd;
14130       break;
14131     case stack_v_mode:
14132       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14133         {
14134           names = names64;
14135           break;
14136         }
14137       bytemode = v_mode;
14138       /* FALLTHRU */
14139     case v_mode:
14140     case v_bnd_mode:
14141     case v_swap_mode:
14142     case dq_mode:
14143     case dqb_mode:
14144     case dqd_mode:
14145     case dqw_mode:
14146       USED_REX (REX_W);
14147       if (rex & REX_W)
14148         names = names64;
14149       else
14150         {
14151           if ((sizeflag & DFLAG)
14152               || (bytemode != v_mode
14153                   && bytemode != v_swap_mode))
14154             names = names32;
14155           else
14156             names = names16;
14157           used_prefixes |= (prefixes & PREFIX_DATA);
14158         }
14159       break;
14160     case mask_mode:
14161       names = names_mask;
14162       break;
14163     case 0:
14164       return;
14165     default:
14166       oappend (INTERNAL_DISASSEMBLER_ERROR);
14167       return;
14168     }
14169   oappend (names[reg]);
14170 }
14171
14172 static void
14173 OP_E_memory (int bytemode, int sizeflag)
14174 {
14175   bfd_vma disp = 0;
14176   int add = (rex & REX_B) ? 8 : 0;
14177   int riprel = 0;
14178   int shift;
14179
14180   if (vex.evex)
14181     {
14182       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14183       if (vex.b
14184           && bytemode != x_mode
14185           && bytemode != evex_half_bcst_xmmq_mode)
14186         {
14187           BadOp ();
14188           return;
14189         }
14190       switch (bytemode)
14191         {
14192         case vex_vsib_d_w_dq_mode:
14193         case evex_x_gscat_mode:
14194         case xmm_mdq_mode:
14195           shift = vex.w ? 3 : 2;
14196           break;
14197         case vex_vsib_q_w_dq_mode:
14198           shift = 3;
14199           break;
14200         case x_mode:
14201         case evex_half_bcst_xmmq_mode:
14202           if (vex.b)
14203             {
14204               shift = vex.w ? 3 : 2;
14205               break;
14206             }
14207           /* Fall through if vex.b == 0.  */
14208         case xmmqd_mode:
14209         case xmmdw_mode:
14210         case xmmq_mode:
14211         case ymmq_mode:
14212         case evex_x_nobcst_mode:
14213         case x_swap_mode:
14214           switch (vex.length)
14215             {
14216             case 128:
14217               shift = 4;
14218               break;
14219             case 256:
14220               shift = 5;
14221               break;
14222             case 512:
14223               shift = 6;
14224               break;
14225             default:
14226               abort ();
14227             }
14228           break;
14229         case ymm_mode:
14230           shift = 5;
14231           break;
14232         case xmm_mode:
14233           shift = 4;
14234           break;
14235         case xmm_mq_mode:
14236         case q_mode:
14237         case q_scalar_mode:
14238         case q_swap_mode:
14239         case q_scalar_swap_mode:
14240           shift = 3;
14241           break;
14242         case dqd_mode:
14243         case xmm_md_mode:
14244         case d_mode:
14245         case d_scalar_mode:
14246         case d_swap_mode:
14247         case d_scalar_swap_mode:
14248           shift = 2;
14249           break;
14250         case xmm_mw_mode:
14251           shift = 1;
14252           break;
14253         case xmm_mb_mode:
14254           shift = 0;
14255           break;
14256         default:
14257           abort ();
14258         }
14259       /* Make necessary corrections to shift for modes that need it.
14260          For these modes we currently have shift 4, 5 or 6 depending on
14261          vex.length (it corresponds to xmmword, ymmword or zmmword
14262          operand).  We might want to make it 3, 4 or 5 (e.g. for
14263          xmmq_mode).  In case of broadcast enabled the corrections
14264          aren't needed, as element size is always 32 or 64 bits.  */
14265       if (bytemode == xmmq_mode
14266           || (bytemode == evex_half_bcst_xmmq_mode
14267               && !vex.b))
14268         shift -= 1;
14269       else if (bytemode == xmmqd_mode)
14270         shift -= 2;
14271       else if (bytemode == xmmdw_mode)
14272         shift -= 3;
14273     }
14274   else
14275     shift = 0;
14276
14277   USED_REX (REX_B);
14278   if (intel_syntax)
14279     intel_operand_size (bytemode, sizeflag);
14280   append_seg ();
14281
14282   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14283     {
14284       /* 32/64 bit address mode */
14285       int havedisp;
14286       int havesib;
14287       int havebase;
14288       int haveindex;
14289       int needindex;
14290       int base, rbase;
14291       int vindex = 0;
14292       int scale = 0;
14293       int addr32flag = !((sizeflag & AFLAG)
14294                          || bytemode == v_bnd_mode
14295                          || bytemode == bnd_mode);
14296       const char **indexes64 = names64;
14297       const char **indexes32 = names32;
14298
14299       havesib = 0;
14300       havebase = 1;
14301       haveindex = 0;
14302       base = modrm.rm;
14303
14304       if (base == 4)
14305         {
14306           havesib = 1;
14307           vindex = sib.index;
14308           USED_REX (REX_X);
14309           if (rex & REX_X)
14310             vindex += 8;
14311           switch (bytemode)
14312             {
14313             case vex_vsib_d_w_dq_mode:
14314             case vex_vsib_q_w_dq_mode:
14315               if (!need_vex)
14316                 abort ();
14317               if (vex.evex)
14318                 {
14319                   if (!vex.v)
14320                     vindex += 16;
14321                 }
14322
14323               haveindex = 1;
14324               switch (vex.length)
14325                 {
14326                 case 128:
14327                   indexes64 = indexes32 = names_xmm;
14328                   break;
14329                 case 256:
14330                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14331                     indexes64 = indexes32 = names_ymm;
14332                   else
14333                     indexes64 = indexes32 = names_xmm;
14334                   break;
14335                 case 512:
14336                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14337                     indexes64 = indexes32 = names_zmm;
14338                   else
14339                     indexes64 = indexes32 = names_ymm;
14340                   break;
14341                 default:
14342                   abort ();
14343                 }
14344               break;
14345             default:
14346               haveindex = vindex != 4;
14347               break;
14348             }
14349           scale = sib.scale;
14350           base = sib.base;
14351           codep++;
14352         }
14353       rbase = base + add;
14354
14355       switch (modrm.mod)
14356         {
14357         case 0:
14358           if (base == 5)
14359             {
14360               havebase = 0;
14361               if (address_mode == mode_64bit && !havesib)
14362                 riprel = 1;
14363               disp = get32s ();
14364             }
14365           break;
14366         case 1:
14367           FETCH_DATA (the_info, codep + 1);
14368           disp = *codep++;
14369           if ((disp & 0x80) != 0)
14370             disp -= 0x100;
14371           if (vex.evex && shift > 0)
14372             disp <<= shift;
14373           break;
14374         case 2:
14375           disp = get32s ();
14376           break;
14377         }
14378
14379       /* In 32bit mode, we need index register to tell [offset] from
14380          [eiz*1 + offset].  */
14381       needindex = (havesib
14382                    && !havebase
14383                    && !haveindex
14384                    && address_mode == mode_32bit);
14385       havedisp = (havebase
14386                   || needindex
14387                   || (havesib && (haveindex || scale != 0)));
14388
14389       if (!intel_syntax)
14390         if (modrm.mod != 0 || base == 5)
14391           {
14392             if (havedisp || riprel)
14393               print_displacement (scratchbuf, disp);
14394             else
14395               print_operand_value (scratchbuf, 1, disp);
14396             oappend (scratchbuf);
14397             if (riprel)
14398               {
14399                 set_op (disp, 1);
14400                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14401               }
14402           }
14403
14404       if ((havebase || haveindex || riprel)
14405           && (bytemode != v_bnd_mode)
14406           && (bytemode != bnd_mode))
14407         used_prefixes |= PREFIX_ADDR;
14408
14409       if (havedisp || (intel_syntax && riprel))
14410         {
14411           *obufp++ = open_char;
14412           if (intel_syntax && riprel)
14413             {
14414               set_op (disp, 1);
14415               oappend (sizeflag & AFLAG ? "rip" : "eip");
14416             }
14417           *obufp = '\0';
14418           if (havebase)
14419             oappend (address_mode == mode_64bit && !addr32flag
14420                      ? names64[rbase] : names32[rbase]);
14421           if (havesib)
14422             {
14423               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14424                  print index to tell base + index from base.  */
14425               if (scale != 0
14426                   || needindex
14427                   || haveindex
14428                   || (havebase && base != ESP_REG_NUM))
14429                 {
14430                   if (!intel_syntax || havebase)
14431                     {
14432                       *obufp++ = separator_char;
14433                       *obufp = '\0';
14434                     }
14435                   if (haveindex)
14436                     oappend (address_mode == mode_64bit && !addr32flag
14437                              ? indexes64[vindex] : indexes32[vindex]);
14438                   else
14439                     oappend (address_mode == mode_64bit && !addr32flag
14440                              ? index64 : index32);
14441
14442                   *obufp++ = scale_char;
14443                   *obufp = '\0';
14444                   sprintf (scratchbuf, "%d", 1 << scale);
14445                   oappend (scratchbuf);
14446                 }
14447             }
14448           if (intel_syntax
14449               && (disp || modrm.mod != 0 || base == 5))
14450             {
14451               if (!havedisp || (bfd_signed_vma) disp >= 0)
14452                 {
14453                   *obufp++ = '+';
14454                   *obufp = '\0';
14455                 }
14456               else if (modrm.mod != 1 && disp != -disp)
14457                 {
14458                   *obufp++ = '-';
14459                   *obufp = '\0';
14460                   disp = - (bfd_signed_vma) disp;
14461                 }
14462
14463               if (havedisp)
14464                 print_displacement (scratchbuf, disp);
14465               else
14466                 print_operand_value (scratchbuf, 1, disp);
14467               oappend (scratchbuf);
14468             }
14469
14470           *obufp++ = close_char;
14471           *obufp = '\0';
14472         }
14473       else if (intel_syntax)
14474         {
14475           if (modrm.mod != 0 || base == 5)
14476             {
14477               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14478                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14479                 ;
14480               else
14481                 {
14482                   oappend (names_seg[ds_reg - es_reg]);
14483                   oappend (":");
14484                 }
14485               print_operand_value (scratchbuf, 1, disp);
14486               oappend (scratchbuf);
14487             }
14488         }
14489     }
14490   else
14491     {
14492       /* 16 bit address mode */
14493       used_prefixes |= prefixes & PREFIX_ADDR;
14494       switch (modrm.mod)
14495         {
14496         case 0:
14497           if (modrm.rm == 6)
14498             {
14499               disp = get16 ();
14500               if ((disp & 0x8000) != 0)
14501                 disp -= 0x10000;
14502             }
14503           break;
14504         case 1:
14505           FETCH_DATA (the_info, codep + 1);
14506           disp = *codep++;
14507           if ((disp & 0x80) != 0)
14508             disp -= 0x100;
14509           break;
14510         case 2:
14511           disp = get16 ();
14512           if ((disp & 0x8000) != 0)
14513             disp -= 0x10000;
14514           break;
14515         }
14516
14517       if (!intel_syntax)
14518         if (modrm.mod != 0 || modrm.rm == 6)
14519           {
14520             print_displacement (scratchbuf, disp);
14521             oappend (scratchbuf);
14522           }
14523
14524       if (modrm.mod != 0 || modrm.rm != 6)
14525         {
14526           *obufp++ = open_char;
14527           *obufp = '\0';
14528           oappend (index16[modrm.rm]);
14529           if (intel_syntax
14530               && (disp || modrm.mod != 0 || modrm.rm == 6))
14531             {
14532               if ((bfd_signed_vma) disp >= 0)
14533                 {
14534                   *obufp++ = '+';
14535                   *obufp = '\0';
14536                 }
14537               else if (modrm.mod != 1)
14538                 {
14539                   *obufp++ = '-';
14540                   *obufp = '\0';
14541                   disp = - (bfd_signed_vma) disp;
14542                 }
14543
14544               print_displacement (scratchbuf, disp);
14545               oappend (scratchbuf);
14546             }
14547
14548           *obufp++ = close_char;
14549           *obufp = '\0';
14550         }
14551       else if (intel_syntax)
14552         {
14553           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14554                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14555             ;
14556           else
14557             {
14558               oappend (names_seg[ds_reg - es_reg]);
14559               oappend (":");
14560             }
14561           print_operand_value (scratchbuf, 1, disp & 0xffff);
14562           oappend (scratchbuf);
14563         }
14564     }
14565   if (vex.evex && vex.b
14566       && (bytemode == x_mode
14567           || bytemode == evex_half_bcst_xmmq_mode))
14568     {
14569       if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14570         oappend ("{1to8}");
14571       else
14572         oappend ("{1to16}");
14573     }
14574 }
14575
14576 static void
14577 OP_E (int bytemode, int sizeflag)
14578 {
14579   /* Skip mod/rm byte.  */
14580   MODRM_CHECK;
14581   codep++;
14582
14583   if (modrm.mod == 3)
14584     OP_E_register (bytemode, sizeflag);
14585   else
14586     OP_E_memory (bytemode, sizeflag);
14587 }
14588
14589 static void
14590 OP_G (int bytemode, int sizeflag)
14591 {
14592   int add = 0;
14593   USED_REX (REX_R);
14594   if (rex & REX_R)
14595     add += 8;
14596   switch (bytemode)
14597     {
14598     case b_mode:
14599       USED_REX (0);
14600       if (rex)
14601         oappend (names8rex[modrm.reg + add]);
14602       else
14603         oappend (names8[modrm.reg + add]);
14604       break;
14605     case w_mode:
14606       oappend (names16[modrm.reg + add]);
14607       break;
14608     case d_mode:
14609       oappend (names32[modrm.reg + add]);
14610       break;
14611     case q_mode:
14612       oappend (names64[modrm.reg + add]);
14613       break;
14614     case bnd_mode:
14615       oappend (names_bnd[modrm.reg]);
14616       break;
14617     case v_mode:
14618     case dq_mode:
14619     case dqb_mode:
14620     case dqd_mode:
14621     case dqw_mode:
14622       USED_REX (REX_W);
14623       if (rex & REX_W)
14624         oappend (names64[modrm.reg + add]);
14625       else
14626         {
14627           if ((sizeflag & DFLAG) || bytemode != v_mode)
14628             oappend (names32[modrm.reg + add]);
14629           else
14630             oappend (names16[modrm.reg + add]);
14631           used_prefixes |= (prefixes & PREFIX_DATA);
14632         }
14633       break;
14634     case m_mode:
14635       if (address_mode == mode_64bit)
14636         oappend (names64[modrm.reg + add]);
14637       else
14638         oappend (names32[modrm.reg + add]);
14639       break;
14640     case mask_mode:
14641       oappend (names_mask[modrm.reg + add]);
14642       break;
14643     default:
14644       oappend (INTERNAL_DISASSEMBLER_ERROR);
14645       break;
14646     }
14647 }
14648
14649 static bfd_vma
14650 get64 (void)
14651 {
14652   bfd_vma x;
14653 #ifdef BFD64
14654   unsigned int a;
14655   unsigned int b;
14656
14657   FETCH_DATA (the_info, codep + 8);
14658   a = *codep++ & 0xff;
14659   a |= (*codep++ & 0xff) << 8;
14660   a |= (*codep++ & 0xff) << 16;
14661   a |= (*codep++ & 0xff) << 24;
14662   b = *codep++ & 0xff;
14663   b |= (*codep++ & 0xff) << 8;
14664   b |= (*codep++ & 0xff) << 16;
14665   b |= (*codep++ & 0xff) << 24;
14666   x = a + ((bfd_vma) b << 32);
14667 #else
14668   abort ();
14669   x = 0;
14670 #endif
14671   return x;
14672 }
14673
14674 static bfd_signed_vma
14675 get32 (void)
14676 {
14677   bfd_signed_vma x = 0;
14678
14679   FETCH_DATA (the_info, codep + 4);
14680   x = *codep++ & (bfd_signed_vma) 0xff;
14681   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14682   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14683   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14684   return x;
14685 }
14686
14687 static bfd_signed_vma
14688 get32s (void)
14689 {
14690   bfd_signed_vma x = 0;
14691
14692   FETCH_DATA (the_info, codep + 4);
14693   x = *codep++ & (bfd_signed_vma) 0xff;
14694   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14695   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14696   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14697
14698   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14699
14700   return x;
14701 }
14702
14703 static int
14704 get16 (void)
14705 {
14706   int x = 0;
14707
14708   FETCH_DATA (the_info, codep + 2);
14709   x = *codep++ & 0xff;
14710   x |= (*codep++ & 0xff) << 8;
14711   return x;
14712 }
14713
14714 static void
14715 set_op (bfd_vma op, int riprel)
14716 {
14717   op_index[op_ad] = op_ad;
14718   if (address_mode == mode_64bit)
14719     {
14720       op_address[op_ad] = op;
14721       op_riprel[op_ad] = riprel;
14722     }
14723   else
14724     {
14725       /* Mask to get a 32-bit address.  */
14726       op_address[op_ad] = op & 0xffffffff;
14727       op_riprel[op_ad] = riprel & 0xffffffff;
14728     }
14729 }
14730
14731 static void
14732 OP_REG (int code, int sizeflag)
14733 {
14734   const char *s;
14735   int add;
14736
14737   switch (code)
14738     {
14739     case es_reg: case ss_reg: case cs_reg:
14740     case ds_reg: case fs_reg: case gs_reg:
14741       oappend (names_seg[code - es_reg]);
14742       return;
14743     }
14744
14745   USED_REX (REX_B);
14746   if (rex & REX_B)
14747     add = 8;
14748   else
14749     add = 0;
14750
14751   switch (code)
14752     {
14753     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14754     case sp_reg: case bp_reg: case si_reg: case di_reg:
14755       s = names16[code - ax_reg + add];
14756       break;
14757     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14758     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14759       USED_REX (0);
14760       if (rex)
14761         s = names8rex[code - al_reg + add];
14762       else
14763         s = names8[code - al_reg];
14764       break;
14765     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14766     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14767       if (address_mode == mode_64bit
14768           && ((sizeflag & DFLAG) || (rex & REX_W)))
14769         {
14770           s = names64[code - rAX_reg + add];
14771           break;
14772         }
14773       code += eAX_reg - rAX_reg;
14774       /* Fall through.  */
14775     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14776     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14777       USED_REX (REX_W);
14778       if (rex & REX_W)
14779         s = names64[code - eAX_reg + add];
14780       else
14781         {
14782           if (sizeflag & DFLAG)
14783             s = names32[code - eAX_reg + add];
14784           else
14785             s = names16[code - eAX_reg + add];
14786           used_prefixes |= (prefixes & PREFIX_DATA);
14787         }
14788       break;
14789     default:
14790       s = INTERNAL_DISASSEMBLER_ERROR;
14791       break;
14792     }
14793   oappend (s);
14794 }
14795
14796 static void
14797 OP_IMREG (int code, int sizeflag)
14798 {
14799   const char *s;
14800
14801   switch (code)
14802     {
14803     case indir_dx_reg:
14804       if (intel_syntax)
14805         s = "dx";
14806       else
14807         s = "(%dx)";
14808       break;
14809     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14810     case sp_reg: case bp_reg: case si_reg: case di_reg:
14811       s = names16[code - ax_reg];
14812       break;
14813     case es_reg: case ss_reg: case cs_reg:
14814     case ds_reg: case fs_reg: case gs_reg:
14815       s = names_seg[code - es_reg];
14816       break;
14817     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14818     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14819       USED_REX (0);
14820       if (rex)
14821         s = names8rex[code - al_reg];
14822       else
14823         s = names8[code - al_reg];
14824       break;
14825     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14826     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14827       USED_REX (REX_W);
14828       if (rex & REX_W)
14829         s = names64[code - eAX_reg];
14830       else
14831         {
14832           if (sizeflag & DFLAG)
14833             s = names32[code - eAX_reg];
14834           else
14835             s = names16[code - eAX_reg];
14836           used_prefixes |= (prefixes & PREFIX_DATA);
14837         }
14838       break;
14839     case z_mode_ax_reg:
14840       if ((rex & REX_W) || (sizeflag & DFLAG))
14841         s = *names32;
14842       else
14843         s = *names16;
14844       if (!(rex & REX_W))
14845         used_prefixes |= (prefixes & PREFIX_DATA);
14846       break;
14847     default:
14848       s = INTERNAL_DISASSEMBLER_ERROR;
14849       break;
14850     }
14851   oappend (s);
14852 }
14853
14854 static void
14855 OP_I (int bytemode, int sizeflag)
14856 {
14857   bfd_signed_vma op;
14858   bfd_signed_vma mask = -1;
14859
14860   switch (bytemode)
14861     {
14862     case b_mode:
14863       FETCH_DATA (the_info, codep + 1);
14864       op = *codep++;
14865       mask = 0xff;
14866       break;
14867     case q_mode:
14868       if (address_mode == mode_64bit)
14869         {
14870           op = get32s ();
14871           break;
14872         }
14873       /* Fall through.  */
14874     case v_mode:
14875       USED_REX (REX_W);
14876       if (rex & REX_W)
14877         op = get32s ();
14878       else
14879         {
14880           if (sizeflag & DFLAG)
14881             {
14882               op = get32 ();
14883               mask = 0xffffffff;
14884             }
14885           else
14886             {
14887               op = get16 ();
14888               mask = 0xfffff;
14889             }
14890           used_prefixes |= (prefixes & PREFIX_DATA);
14891         }
14892       break;
14893     case w_mode:
14894       mask = 0xfffff;
14895       op = get16 ();
14896       break;
14897     case const_1_mode:
14898       if (intel_syntax)
14899         oappend ("1");
14900       return;
14901     default:
14902       oappend (INTERNAL_DISASSEMBLER_ERROR);
14903       return;
14904     }
14905
14906   op &= mask;
14907   scratchbuf[0] = '$';
14908   print_operand_value (scratchbuf + 1, 1, op);
14909   oappend (scratchbuf + intel_syntax);
14910   scratchbuf[0] = '\0';
14911 }
14912
14913 static void
14914 OP_I64 (int bytemode, int sizeflag)
14915 {
14916   bfd_signed_vma op;
14917   bfd_signed_vma mask = -1;
14918
14919   if (address_mode != mode_64bit)
14920     {
14921       OP_I (bytemode, sizeflag);
14922       return;
14923     }
14924
14925   switch (bytemode)
14926     {
14927     case b_mode:
14928       FETCH_DATA (the_info, codep + 1);
14929       op = *codep++;
14930       mask = 0xff;
14931       break;
14932     case v_mode:
14933       USED_REX (REX_W);
14934       if (rex & REX_W)
14935         op = get64 ();
14936       else
14937         {
14938           if (sizeflag & DFLAG)
14939             {
14940               op = get32 ();
14941               mask = 0xffffffff;
14942             }
14943           else
14944             {
14945               op = get16 ();
14946               mask = 0xfffff;
14947             }
14948           used_prefixes |= (prefixes & PREFIX_DATA);
14949         }
14950       break;
14951     case w_mode:
14952       mask = 0xfffff;
14953       op = get16 ();
14954       break;
14955     default:
14956       oappend (INTERNAL_DISASSEMBLER_ERROR);
14957       return;
14958     }
14959
14960   op &= mask;
14961   scratchbuf[0] = '$';
14962   print_operand_value (scratchbuf + 1, 1, op);
14963   oappend (scratchbuf + intel_syntax);
14964   scratchbuf[0] = '\0';
14965 }
14966
14967 static void
14968 OP_sI (int bytemode, int sizeflag)
14969 {
14970   bfd_signed_vma op;
14971
14972   switch (bytemode)
14973     {
14974     case b_mode:
14975     case b_T_mode:
14976       FETCH_DATA (the_info, codep + 1);
14977       op = *codep++;
14978       if ((op & 0x80) != 0)
14979         op -= 0x100;
14980       if (bytemode == b_T_mode)
14981         {
14982           if (address_mode != mode_64bit
14983               || !((sizeflag & DFLAG) || (rex & REX_W)))
14984             {
14985               /* The operand-size prefix is overridden by a REX prefix.  */
14986               if ((sizeflag & DFLAG) || (rex & REX_W))
14987                 op &= 0xffffffff;
14988               else
14989                 op &= 0xffff;
14990           }
14991         }
14992       else
14993         {
14994           if (!(rex & REX_W))
14995             {
14996               if (sizeflag & DFLAG)
14997                 op &= 0xffffffff;
14998               else
14999                 op &= 0xffff;
15000             }
15001         }
15002       break;
15003     case v_mode:
15004       /* The operand-size prefix is overridden by a REX prefix.  */
15005       if ((sizeflag & DFLAG) || (rex & REX_W))
15006         op = get32s ();
15007       else
15008         op = get16 ();
15009       break;
15010     default:
15011       oappend (INTERNAL_DISASSEMBLER_ERROR);
15012       return;
15013     }
15014
15015   scratchbuf[0] = '$';
15016   print_operand_value (scratchbuf + 1, 1, op);
15017   oappend (scratchbuf + intel_syntax);
15018 }
15019
15020 static void
15021 OP_J (int bytemode, int sizeflag)
15022 {
15023   bfd_vma disp;
15024   bfd_vma mask = -1;
15025   bfd_vma segment = 0;
15026
15027   switch (bytemode)
15028     {
15029     case b_mode:
15030       FETCH_DATA (the_info, codep + 1);
15031       disp = *codep++;
15032       if ((disp & 0x80) != 0)
15033         disp -= 0x100;
15034       break;
15035     case v_mode:
15036       USED_REX (REX_W);
15037       if ((sizeflag & DFLAG) || (rex & REX_W))
15038         disp = get32s ();
15039       else
15040         {
15041           disp = get16 ();
15042           if ((disp & 0x8000) != 0)
15043             disp -= 0x10000;
15044           /* In 16bit mode, address is wrapped around at 64k within
15045              the same segment.  Otherwise, a data16 prefix on a jump
15046              instruction means that the pc is masked to 16 bits after
15047              the displacement is added!  */
15048           mask = 0xffff;
15049           if ((prefixes & PREFIX_DATA) == 0)
15050             segment = ((start_pc + codep - start_codep)
15051                        & ~((bfd_vma) 0xffff));
15052         }
15053       if (!(rex & REX_W))
15054         used_prefixes |= (prefixes & PREFIX_DATA);
15055       break;
15056     default:
15057       oappend (INTERNAL_DISASSEMBLER_ERROR);
15058       return;
15059     }
15060   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15061   set_op (disp, 0);
15062   print_operand_value (scratchbuf, 1, disp);
15063   oappend (scratchbuf);
15064 }
15065
15066 static void
15067 OP_SEG (int bytemode, int sizeflag)
15068 {
15069   if (bytemode == w_mode)
15070     oappend (names_seg[modrm.reg]);
15071   else
15072     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15073 }
15074
15075 static void
15076 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15077 {
15078   int seg, offset;
15079
15080   if (sizeflag & DFLAG)
15081     {
15082       offset = get32 ();
15083       seg = get16 ();
15084     }
15085   else
15086     {
15087       offset = get16 ();
15088       seg = get16 ();
15089     }
15090   used_prefixes |= (prefixes & PREFIX_DATA);
15091   if (intel_syntax)
15092     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15093   else
15094     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15095   oappend (scratchbuf);
15096 }
15097
15098 static void
15099 OP_OFF (int bytemode, int sizeflag)
15100 {
15101   bfd_vma off;
15102
15103   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15104     intel_operand_size (bytemode, sizeflag);
15105   append_seg ();
15106
15107   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15108     off = get32 ();
15109   else
15110     off = get16 ();
15111
15112   if (intel_syntax)
15113     {
15114       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15115                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15116         {
15117           oappend (names_seg[ds_reg - es_reg]);
15118           oappend (":");
15119         }
15120     }
15121   print_operand_value (scratchbuf, 1, off);
15122   oappend (scratchbuf);
15123 }
15124
15125 static void
15126 OP_OFF64 (int bytemode, int sizeflag)
15127 {
15128   bfd_vma off;
15129
15130   if (address_mode != mode_64bit
15131       || (prefixes & PREFIX_ADDR))
15132     {
15133       OP_OFF (bytemode, sizeflag);
15134       return;
15135     }
15136
15137   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15138     intel_operand_size (bytemode, sizeflag);
15139   append_seg ();
15140
15141   off = get64 ();
15142
15143   if (intel_syntax)
15144     {
15145       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15146                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15147         {
15148           oappend (names_seg[ds_reg - es_reg]);
15149           oappend (":");
15150         }
15151     }
15152   print_operand_value (scratchbuf, 1, off);
15153   oappend (scratchbuf);
15154 }
15155
15156 static void
15157 ptr_reg (int code, int sizeflag)
15158 {
15159   const char *s;
15160
15161   *obufp++ = open_char;
15162   used_prefixes |= (prefixes & PREFIX_ADDR);
15163   if (address_mode == mode_64bit)
15164     {
15165       if (!(sizeflag & AFLAG))
15166         s = names32[code - eAX_reg];
15167       else
15168         s = names64[code - eAX_reg];
15169     }
15170   else if (sizeflag & AFLAG)
15171     s = names32[code - eAX_reg];
15172   else
15173     s = names16[code - eAX_reg];
15174   oappend (s);
15175   *obufp++ = close_char;
15176   *obufp = 0;
15177 }
15178
15179 static void
15180 OP_ESreg (int code, int sizeflag)
15181 {
15182   if (intel_syntax)
15183     {
15184       switch (codep[-1])
15185         {
15186         case 0x6d:      /* insw/insl */
15187           intel_operand_size (z_mode, sizeflag);
15188           break;
15189         case 0xa5:      /* movsw/movsl/movsq */
15190         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15191         case 0xab:      /* stosw/stosl */
15192         case 0xaf:      /* scasw/scasl */
15193           intel_operand_size (v_mode, sizeflag);
15194           break;
15195         default:
15196           intel_operand_size (b_mode, sizeflag);
15197         }
15198     }
15199   oappend ("%es:" + intel_syntax);
15200   ptr_reg (code, sizeflag);
15201 }
15202
15203 static void
15204 OP_DSreg (int code, int sizeflag)
15205 {
15206   if (intel_syntax)
15207     {
15208       switch (codep[-1])
15209         {
15210         case 0x6f:      /* outsw/outsl */
15211           intel_operand_size (z_mode, sizeflag);
15212           break;
15213         case 0xa5:      /* movsw/movsl/movsq */
15214         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15215         case 0xad:      /* lodsw/lodsl/lodsq */
15216           intel_operand_size (v_mode, sizeflag);
15217           break;
15218         default:
15219           intel_operand_size (b_mode, sizeflag);
15220         }
15221     }
15222   if ((prefixes
15223        & (PREFIX_CS
15224           | PREFIX_DS
15225           | PREFIX_SS
15226           | PREFIX_ES
15227           | PREFIX_FS
15228           | PREFIX_GS)) == 0)
15229     prefixes |= PREFIX_DS;
15230   append_seg ();
15231   ptr_reg (code, sizeflag);
15232 }
15233
15234 static void
15235 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15236 {
15237   int add;
15238   if (rex & REX_R)
15239     {
15240       USED_REX (REX_R);
15241       add = 8;
15242     }
15243   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15244     {
15245       all_prefixes[last_lock_prefix] = 0;
15246       used_prefixes |= PREFIX_LOCK;
15247       add = 8;
15248     }
15249   else
15250     add = 0;
15251   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15252   oappend (scratchbuf + intel_syntax);
15253 }
15254
15255 static void
15256 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15257 {
15258   int add;
15259   USED_REX (REX_R);
15260   if (rex & REX_R)
15261     add = 8;
15262   else
15263     add = 0;
15264   if (intel_syntax)
15265     sprintf (scratchbuf, "db%d", modrm.reg + add);
15266   else
15267     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15268   oappend (scratchbuf);
15269 }
15270
15271 static void
15272 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15273 {
15274   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15275   oappend (scratchbuf + intel_syntax);
15276 }
15277
15278 static void
15279 OP_R (int bytemode, int sizeflag)
15280 {
15281   if (modrm.mod == 3)
15282     OP_E (bytemode, sizeflag);
15283   else
15284     BadOp ();
15285 }
15286
15287 static void
15288 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15289 {
15290   int reg = modrm.reg;
15291   const char **names;
15292
15293   used_prefixes |= (prefixes & PREFIX_DATA);
15294   if (prefixes & PREFIX_DATA)
15295     {
15296       names = names_xmm;
15297       USED_REX (REX_R);
15298       if (rex & REX_R)
15299         reg += 8;
15300     }
15301   else
15302     names = names_mm;
15303   oappend (names[reg]);
15304 }
15305
15306 static void
15307 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15308 {
15309   int reg = modrm.reg;
15310   const char **names;
15311
15312   USED_REX (REX_R);
15313   if (rex & REX_R)
15314     reg += 8;
15315   if (vex.evex)
15316     {
15317       if (!vex.r)
15318         reg += 16;
15319     }
15320
15321   if (need_vex
15322       && bytemode != xmm_mode
15323       && bytemode != xmmq_mode
15324       && bytemode != evex_half_bcst_xmmq_mode
15325       && bytemode != ymm_mode
15326       && bytemode != scalar_mode)
15327     {
15328       switch (vex.length)
15329         {
15330         case 128:
15331           names = names_xmm;
15332           break;
15333         case 256:
15334           if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
15335             names = names_ymm;
15336           else
15337             names = names_xmm;
15338           break;
15339         case 512:
15340           names = names_zmm;
15341           break;
15342         default:
15343           abort ();
15344         }
15345     }
15346   else if (bytemode == xmmq_mode
15347            || bytemode == evex_half_bcst_xmmq_mode)
15348     {
15349       switch (vex.length)
15350         {
15351         case 128:
15352         case 256:
15353           names = names_xmm;
15354           break;
15355         case 512:
15356           names = names_ymm;
15357           break;
15358         default:
15359           abort ();
15360         }
15361     }
15362   else if (bytemode == ymm_mode)
15363     names = names_ymm;
15364   else
15365     names = names_xmm;
15366   oappend (names[reg]);
15367 }
15368
15369 static void
15370 OP_EM (int bytemode, int sizeflag)
15371 {
15372   int reg;
15373   const char **names;
15374
15375   if (modrm.mod != 3)
15376     {
15377       if (intel_syntax
15378           && (bytemode == v_mode || bytemode == v_swap_mode))
15379         {
15380           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15381           used_prefixes |= (prefixes & PREFIX_DATA);
15382         }
15383       OP_E (bytemode, sizeflag);
15384       return;
15385     }
15386
15387   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15388     swap_operand ();
15389
15390   /* Skip mod/rm byte.  */
15391   MODRM_CHECK;
15392   codep++;
15393   used_prefixes |= (prefixes & PREFIX_DATA);
15394   reg = modrm.rm;
15395   if (prefixes & PREFIX_DATA)
15396     {
15397       names = names_xmm;
15398       USED_REX (REX_B);
15399       if (rex & REX_B)
15400         reg += 8;
15401     }
15402   else
15403     names = names_mm;
15404   oappend (names[reg]);
15405 }
15406
15407 /* cvt* are the only instructions in sse2 which have
15408    both SSE and MMX operands and also have 0x66 prefix
15409    in their opcode. 0x66 was originally used to differentiate
15410    between SSE and MMX instruction(operands). So we have to handle the
15411    cvt* separately using OP_EMC and OP_MXC */
15412 static void
15413 OP_EMC (int bytemode, int sizeflag)
15414 {
15415   if (modrm.mod != 3)
15416     {
15417       if (intel_syntax && bytemode == v_mode)
15418         {
15419           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15420           used_prefixes |= (prefixes & PREFIX_DATA);
15421         }
15422       OP_E (bytemode, sizeflag);
15423       return;
15424     }
15425
15426   /* Skip mod/rm byte.  */
15427   MODRM_CHECK;
15428   codep++;
15429   used_prefixes |= (prefixes & PREFIX_DATA);
15430   oappend (names_mm[modrm.rm]);
15431 }
15432
15433 static void
15434 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15435 {
15436   used_prefixes |= (prefixes & PREFIX_DATA);
15437   oappend (names_mm[modrm.reg]);
15438 }
15439
15440 static void
15441 OP_EX (int bytemode, int sizeflag)
15442 {
15443   int reg;
15444   const char **names;
15445
15446   /* Skip mod/rm byte.  */
15447   MODRM_CHECK;
15448   codep++;
15449
15450   if (modrm.mod != 3)
15451     {
15452       OP_E_memory (bytemode, sizeflag);
15453       return;
15454     }
15455
15456   reg = modrm.rm;
15457   USED_REX (REX_B);
15458   if (rex & REX_B)
15459     reg += 8;
15460   if (vex.evex)
15461     {
15462       USED_REX (REX_X);
15463       if ((rex & REX_X))
15464         reg += 16;
15465     }
15466
15467   if ((sizeflag & SUFFIX_ALWAYS)
15468       && (bytemode == x_swap_mode
15469           || bytemode == d_swap_mode
15470           || bytemode == d_scalar_swap_mode
15471           || bytemode == q_swap_mode
15472           || bytemode == q_scalar_swap_mode))
15473     swap_operand ();
15474
15475   if (need_vex
15476       && bytemode != xmm_mode
15477       && bytemode != xmmdw_mode
15478       && bytemode != xmmqd_mode
15479       && bytemode != xmm_mb_mode
15480       && bytemode != xmm_mw_mode
15481       && bytemode != xmm_md_mode
15482       && bytemode != xmm_mq_mode
15483       && bytemode != xmm_mdq_mode
15484       && bytemode != xmmq_mode
15485       && bytemode != evex_half_bcst_xmmq_mode
15486       && bytemode != ymm_mode
15487       && bytemode != d_scalar_mode
15488       && bytemode != d_scalar_swap_mode
15489       && bytemode != q_scalar_mode
15490       && bytemode != q_scalar_swap_mode
15491       && bytemode != vex_scalar_w_dq_mode)
15492     {
15493       switch (vex.length)
15494         {
15495         case 128:
15496           names = names_xmm;
15497           break;
15498         case 256:
15499           names = names_ymm;
15500           break;
15501         case 512:
15502           names = names_zmm;
15503           break;
15504         default:
15505           abort ();
15506         }
15507     }
15508   else if (bytemode == xmmq_mode
15509            || bytemode == evex_half_bcst_xmmq_mode)
15510     {
15511       switch (vex.length)
15512         {
15513         case 128:
15514         case 256:
15515           names = names_xmm;
15516           break;
15517         case 512:
15518           names = names_ymm;
15519           break;
15520         default:
15521           abort ();
15522         }
15523     }
15524   else if (bytemode == ymm_mode)
15525     names = names_ymm;
15526   else
15527     names = names_xmm;
15528   oappend (names[reg]);
15529 }
15530
15531 static void
15532 OP_MS (int bytemode, int sizeflag)
15533 {
15534   if (modrm.mod == 3)
15535     OP_EM (bytemode, sizeflag);
15536   else
15537     BadOp ();
15538 }
15539
15540 static void
15541 OP_XS (int bytemode, int sizeflag)
15542 {
15543   if (modrm.mod == 3)
15544     OP_EX (bytemode, sizeflag);
15545   else
15546     BadOp ();
15547 }
15548
15549 static void
15550 OP_M (int bytemode, int sizeflag)
15551 {
15552   if (modrm.mod == 3)
15553     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15554     BadOp ();
15555   else
15556     OP_E (bytemode, sizeflag);
15557 }
15558
15559 static void
15560 OP_0f07 (int bytemode, int sizeflag)
15561 {
15562   if (modrm.mod != 3 || modrm.rm != 0)
15563     BadOp ();
15564   else
15565     OP_E (bytemode, sizeflag);
15566 }
15567
15568 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15569    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15570
15571 static void
15572 NOP_Fixup1 (int bytemode, int sizeflag)
15573 {
15574   if ((prefixes & PREFIX_DATA) != 0
15575       || (rex != 0
15576           && rex != 0x48
15577           && address_mode == mode_64bit))
15578     OP_REG (bytemode, sizeflag);
15579   else
15580     strcpy (obuf, "nop");
15581 }
15582
15583 static void
15584 NOP_Fixup2 (int bytemode, int sizeflag)
15585 {
15586   if ((prefixes & PREFIX_DATA) != 0
15587       || (rex != 0
15588           && rex != 0x48
15589           && address_mode == mode_64bit))
15590     OP_IMREG (bytemode, sizeflag);
15591 }
15592
15593 static const char *const Suffix3DNow[] = {
15594 /* 00 */        NULL,           NULL,           NULL,           NULL,
15595 /* 04 */        NULL,           NULL,           NULL,           NULL,
15596 /* 08 */        NULL,           NULL,           NULL,           NULL,
15597 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15598 /* 10 */        NULL,           NULL,           NULL,           NULL,
15599 /* 14 */        NULL,           NULL,           NULL,           NULL,
15600 /* 18 */        NULL,           NULL,           NULL,           NULL,
15601 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15602 /* 20 */        NULL,           NULL,           NULL,           NULL,
15603 /* 24 */        NULL,           NULL,           NULL,           NULL,
15604 /* 28 */        NULL,           NULL,           NULL,           NULL,
15605 /* 2C */        NULL,           NULL,           NULL,           NULL,
15606 /* 30 */        NULL,           NULL,           NULL,           NULL,
15607 /* 34 */        NULL,           NULL,           NULL,           NULL,
15608 /* 38 */        NULL,           NULL,           NULL,           NULL,
15609 /* 3C */        NULL,           NULL,           NULL,           NULL,
15610 /* 40 */        NULL,           NULL,           NULL,           NULL,
15611 /* 44 */        NULL,           NULL,           NULL,           NULL,
15612 /* 48 */        NULL,           NULL,           NULL,           NULL,
15613 /* 4C */        NULL,           NULL,           NULL,           NULL,
15614 /* 50 */        NULL,           NULL,           NULL,           NULL,
15615 /* 54 */        NULL,           NULL,           NULL,           NULL,
15616 /* 58 */        NULL,           NULL,           NULL,           NULL,
15617 /* 5C */        NULL,           NULL,           NULL,           NULL,
15618 /* 60 */        NULL,           NULL,           NULL,           NULL,
15619 /* 64 */        NULL,           NULL,           NULL,           NULL,
15620 /* 68 */        NULL,           NULL,           NULL,           NULL,
15621 /* 6C */        NULL,           NULL,           NULL,           NULL,
15622 /* 70 */        NULL,           NULL,           NULL,           NULL,
15623 /* 74 */        NULL,           NULL,           NULL,           NULL,
15624 /* 78 */        NULL,           NULL,           NULL,           NULL,
15625 /* 7C */        NULL,           NULL,           NULL,           NULL,
15626 /* 80 */        NULL,           NULL,           NULL,           NULL,
15627 /* 84 */        NULL,           NULL,           NULL,           NULL,
15628 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15629 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15630 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15631 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15632 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15633 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15634 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15635 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15636 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15637 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15638 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15639 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15640 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15641 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15642 /* C0 */        NULL,           NULL,           NULL,           NULL,
15643 /* C4 */        NULL,           NULL,           NULL,           NULL,
15644 /* C8 */        NULL,           NULL,           NULL,           NULL,
15645 /* CC */        NULL,           NULL,           NULL,           NULL,
15646 /* D0 */        NULL,           NULL,           NULL,           NULL,
15647 /* D4 */        NULL,           NULL,           NULL,           NULL,
15648 /* D8 */        NULL,           NULL,           NULL,           NULL,
15649 /* DC */        NULL,           NULL,           NULL,           NULL,
15650 /* E0 */        NULL,           NULL,           NULL,           NULL,
15651 /* E4 */        NULL,           NULL,           NULL,           NULL,
15652 /* E8 */        NULL,           NULL,           NULL,           NULL,
15653 /* EC */        NULL,           NULL,           NULL,           NULL,
15654 /* F0 */        NULL,           NULL,           NULL,           NULL,
15655 /* F4 */        NULL,           NULL,           NULL,           NULL,
15656 /* F8 */        NULL,           NULL,           NULL,           NULL,
15657 /* FC */        NULL,           NULL,           NULL,           NULL,
15658 };
15659
15660 static void
15661 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15662 {
15663   const char *mnemonic;
15664
15665   FETCH_DATA (the_info, codep + 1);
15666   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15667      place where an 8-bit immediate would normally go.  ie. the last
15668      byte of the instruction.  */
15669   obufp = mnemonicendp;
15670   mnemonic = Suffix3DNow[*codep++ & 0xff];
15671   if (mnemonic)
15672     oappend (mnemonic);
15673   else
15674     {
15675       /* Since a variable sized modrm/sib chunk is between the start
15676          of the opcode (0x0f0f) and the opcode suffix, we need to do
15677          all the modrm processing first, and don't know until now that
15678          we have a bad opcode.  This necessitates some cleaning up.  */
15679       op_out[0][0] = '\0';
15680       op_out[1][0] = '\0';
15681       BadOp ();
15682     }
15683   mnemonicendp = obufp;
15684 }
15685
15686 static struct op simd_cmp_op[] =
15687 {
15688   { STRING_COMMA_LEN ("eq") },
15689   { STRING_COMMA_LEN ("lt") },
15690   { STRING_COMMA_LEN ("le") },
15691   { STRING_COMMA_LEN ("unord") },
15692   { STRING_COMMA_LEN ("neq") },
15693   { STRING_COMMA_LEN ("nlt") },
15694   { STRING_COMMA_LEN ("nle") },
15695   { STRING_COMMA_LEN ("ord") }
15696 };
15697
15698 static void
15699 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15700 {
15701   unsigned int cmp_type;
15702
15703   FETCH_DATA (the_info, codep + 1);
15704   cmp_type = *codep++ & 0xff;
15705   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15706     {
15707       char suffix [3];
15708       char *p = mnemonicendp - 2;
15709       suffix[0] = p[0];
15710       suffix[1] = p[1];
15711       suffix[2] = '\0';
15712       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15713       mnemonicendp += simd_cmp_op[cmp_type].len;
15714     }
15715   else
15716     {
15717       /* We have a reserved extension byte.  Output it directly.  */
15718       scratchbuf[0] = '$';
15719       print_operand_value (scratchbuf + 1, 1, cmp_type);
15720       oappend (scratchbuf + intel_syntax);
15721       scratchbuf[0] = '\0';
15722     }
15723 }
15724
15725 static void
15726 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15727           int sizeflag ATTRIBUTE_UNUSED)
15728 {
15729   /* mwait %eax,%ecx  */
15730   if (!intel_syntax)
15731     {
15732       const char **names = (address_mode == mode_64bit
15733                             ? names64 : names32);
15734       strcpy (op_out[0], names[0]);
15735       strcpy (op_out[1], names[1]);
15736       two_source_ops = 1;
15737     }
15738   /* Skip mod/rm byte.  */
15739   MODRM_CHECK;
15740   codep++;
15741 }
15742
15743 static void
15744 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15745             int sizeflag ATTRIBUTE_UNUSED)
15746 {
15747   /* monitor %eax,%ecx,%edx"  */
15748   if (!intel_syntax)
15749     {
15750       const char **op1_names;
15751       const char **names = (address_mode == mode_64bit
15752                             ? names64 : names32);
15753
15754       if (!(prefixes & PREFIX_ADDR))
15755         op1_names = (address_mode == mode_16bit
15756                      ? names16 : names);
15757       else
15758         {
15759           /* Remove "addr16/addr32".  */
15760           all_prefixes[last_addr_prefix] = 0;
15761           op1_names = (address_mode != mode_32bit
15762                        ? names32 : names16);
15763           used_prefixes |= PREFIX_ADDR;
15764         }
15765       strcpy (op_out[0], op1_names[0]);
15766       strcpy (op_out[1], names[1]);
15767       strcpy (op_out[2], names[2]);
15768       two_source_ops = 1;
15769     }
15770   /* Skip mod/rm byte.  */
15771   MODRM_CHECK;
15772   codep++;
15773 }
15774
15775 static void
15776 BadOp (void)
15777 {
15778   /* Throw away prefixes and 1st. opcode byte.  */
15779   codep = insn_codep + 1;
15780   oappend ("(bad)");
15781 }
15782
15783 static void
15784 REP_Fixup (int bytemode, int sizeflag)
15785 {
15786   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15787      lods and stos.  */
15788   if (prefixes & PREFIX_REPZ)
15789     all_prefixes[last_repz_prefix] = REP_PREFIX;
15790
15791   switch (bytemode)
15792     {
15793     case al_reg:
15794     case eAX_reg:
15795     case indir_dx_reg:
15796       OP_IMREG (bytemode, sizeflag);
15797       break;
15798     case eDI_reg:
15799       OP_ESreg (bytemode, sizeflag);
15800       break;
15801     case eSI_reg:
15802       OP_DSreg (bytemode, sizeflag);
15803       break;
15804     default:
15805       abort ();
15806       break;
15807     }
15808 }
15809
15810 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15811    "bnd".  */
15812
15813 static void
15814 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15815 {
15816   if (prefixes & PREFIX_REPNZ)
15817     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15818 }
15819
15820 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15821    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15822  */
15823
15824 static void
15825 HLE_Fixup1 (int bytemode, int sizeflag)
15826 {
15827   if (modrm.mod != 3
15828       && (prefixes & PREFIX_LOCK) != 0)
15829     {
15830       if (prefixes & PREFIX_REPZ)
15831         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15832       if (prefixes & PREFIX_REPNZ)
15833         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15834     }
15835
15836   OP_E (bytemode, sizeflag);
15837 }
15838
15839 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15840    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15841  */
15842
15843 static void
15844 HLE_Fixup2 (int bytemode, int sizeflag)
15845 {
15846   if (modrm.mod != 3)
15847     {
15848       if (prefixes & PREFIX_REPZ)
15849         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15850       if (prefixes & PREFIX_REPNZ)
15851         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15852     }
15853
15854   OP_E (bytemode, sizeflag);
15855 }
15856
15857 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15858    "xrelease" for memory operand.  No check for LOCK prefix.   */
15859
15860 static void
15861 HLE_Fixup3 (int bytemode, int sizeflag)
15862 {
15863   if (modrm.mod != 3
15864       && last_repz_prefix > last_repnz_prefix
15865       && (prefixes & PREFIX_REPZ) != 0)
15866     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15867
15868   OP_E (bytemode, sizeflag);
15869 }
15870
15871 static void
15872 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15873 {
15874   USED_REX (REX_W);
15875   if (rex & REX_W)
15876     {
15877       /* Change cmpxchg8b to cmpxchg16b.  */
15878       char *p = mnemonicendp - 2;
15879       mnemonicendp = stpcpy (p, "16b");
15880       bytemode = o_mode;
15881     }
15882   else if ((prefixes & PREFIX_LOCK) != 0)
15883     {
15884       if (prefixes & PREFIX_REPZ)
15885         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15886       if (prefixes & PREFIX_REPNZ)
15887         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15888     }
15889
15890   OP_M (bytemode, sizeflag);
15891 }
15892
15893 static void
15894 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15895 {
15896   const char **names;
15897
15898   if (need_vex)
15899     {
15900       switch (vex.length)
15901         {
15902         case 128:
15903           names = names_xmm;
15904           break;
15905         case 256:
15906           names = names_ymm;
15907           break;
15908         default:
15909           abort ();
15910         }
15911     }
15912   else
15913     names = names_xmm;
15914   oappend (names[reg]);
15915 }
15916
15917 static void
15918 CRC32_Fixup (int bytemode, int sizeflag)
15919 {
15920   /* Add proper suffix to "crc32".  */
15921   char *p = mnemonicendp;
15922
15923   switch (bytemode)
15924     {
15925     case b_mode:
15926       if (intel_syntax)
15927         goto skip;
15928
15929       *p++ = 'b';
15930       break;
15931     case v_mode:
15932       if (intel_syntax)
15933         goto skip;
15934
15935       USED_REX (REX_W);
15936       if (rex & REX_W)
15937         *p++ = 'q';
15938       else
15939         {
15940           if (sizeflag & DFLAG)
15941             *p++ = 'l';
15942           else
15943             *p++ = 'w';
15944           used_prefixes |= (prefixes & PREFIX_DATA);
15945         }
15946       break;
15947     default:
15948       oappend (INTERNAL_DISASSEMBLER_ERROR);
15949       break;
15950     }
15951   mnemonicendp = p;
15952   *p = '\0';
15953
15954 skip:
15955   if (modrm.mod == 3)
15956     {
15957       int add;
15958
15959       /* Skip mod/rm byte.  */
15960       MODRM_CHECK;
15961       codep++;
15962
15963       USED_REX (REX_B);
15964       add = (rex & REX_B) ? 8 : 0;
15965       if (bytemode == b_mode)
15966         {
15967           USED_REX (0);
15968           if (rex)
15969             oappend (names8rex[modrm.rm + add]);
15970           else
15971             oappend (names8[modrm.rm + add]);
15972         }
15973       else
15974         {
15975           USED_REX (REX_W);
15976           if (rex & REX_W)
15977             oappend (names64[modrm.rm + add]);
15978           else if ((prefixes & PREFIX_DATA))
15979             oappend (names16[modrm.rm + add]);
15980           else
15981             oappend (names32[modrm.rm + add]);
15982         }
15983     }
15984   else
15985     OP_E (bytemode, sizeflag);
15986 }
15987
15988 static void
15989 FXSAVE_Fixup (int bytemode, int sizeflag)
15990 {
15991   /* Add proper suffix to "fxsave" and "fxrstor".  */
15992   USED_REX (REX_W);
15993   if (rex & REX_W)
15994     {
15995       char *p = mnemonicendp;
15996       *p++ = '6';
15997       *p++ = '4';
15998       *p = '\0';
15999       mnemonicendp = p;
16000     }
16001   OP_M (bytemode, sizeflag);
16002 }
16003
16004 /* Display the destination register operand for instructions with
16005    VEX. */
16006
16007 static void
16008 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16009 {
16010   int reg;
16011   const char **names;
16012
16013   if (!need_vex)
16014     abort ();
16015
16016   if (!need_vex_reg)
16017     return;
16018
16019   reg = vex.register_specifier;
16020   if (vex.evex)
16021     {
16022       if (!vex.v)
16023         reg += 16;
16024     }
16025
16026   if (bytemode == vex_scalar_mode)
16027     {
16028       oappend (names_xmm[reg]);
16029       return;
16030     }
16031
16032   switch (vex.length)
16033     {
16034     case 128:
16035       switch (bytemode)
16036         {
16037         case vex_mode:
16038         case vex128_mode:
16039         case vex_vsib_q_w_dq_mode:
16040           names = names_xmm;
16041           break;
16042         case dq_mode:
16043           if (vex.w)
16044             names = names64;
16045           else
16046             names = names32;
16047           break;
16048         case mask_mode:
16049           names = names_mask;
16050           break;
16051         default:
16052           abort ();
16053           return;
16054         }
16055       break;
16056     case 256:
16057       switch (bytemode)
16058         {
16059         case vex_mode:
16060         case vex256_mode:
16061           names = names_ymm;
16062           break;
16063         case vex_vsib_q_w_dq_mode:
16064           names = vex.w ? names_ymm : names_xmm;
16065           break;
16066         case mask_mode:
16067           names = names_mask;
16068           break;
16069         default:
16070           abort ();
16071           return;
16072         }
16073       break;
16074     case 512:
16075       names = names_zmm;
16076       break;
16077     default:
16078       abort ();
16079       break;
16080     }
16081   oappend (names[reg]);
16082 }
16083
16084 /* Get the VEX immediate byte without moving codep.  */
16085
16086 static unsigned char
16087 get_vex_imm8 (int sizeflag, int opnum)
16088 {
16089   int bytes_before_imm = 0;
16090
16091   if (modrm.mod != 3)
16092     {
16093       /* There are SIB/displacement bytes.  */
16094       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16095         {
16096           /* 32/64 bit address mode */
16097           int base = modrm.rm;
16098
16099           /* Check SIB byte.  */
16100           if (base == 4)
16101             {
16102               FETCH_DATA (the_info, codep + 1);
16103               base = *codep & 7;
16104               /* When decoding the third source, don't increase
16105                  bytes_before_imm as this has already been incremented
16106                  by one in OP_E_memory while decoding the second
16107                  source operand.  */
16108               if (opnum == 0)
16109                 bytes_before_imm++;
16110             }
16111
16112           /* Don't increase bytes_before_imm when decoding the third source,
16113              it has already been incremented by OP_E_memory while decoding
16114              the second source operand.  */
16115           if (opnum == 0)
16116             {
16117               switch (modrm.mod)
16118                 {
16119                   case 0:
16120                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16121                        SIB == 5, there is a 4 byte displacement.  */
16122                     if (base != 5)
16123                       /* No displacement. */
16124                       break;
16125                   case 2:
16126                     /* 4 byte displacement.  */
16127                     bytes_before_imm += 4;
16128                     break;
16129                   case 1:
16130                     /* 1 byte displacement.  */
16131                     bytes_before_imm++;
16132                     break;
16133                 }
16134             }
16135         }
16136       else
16137         {
16138           /* 16 bit address mode */
16139           /* Don't increase bytes_before_imm when decoding the third source,
16140              it has already been incremented by OP_E_memory while decoding
16141              the second source operand.  */
16142           if (opnum == 0)
16143             {
16144               switch (modrm.mod)
16145                 {
16146                 case 0:
16147                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16148                   if (modrm.rm != 6)
16149                     /* No displacement. */
16150                     break;
16151                 case 2:
16152                   /* 2 byte displacement.  */
16153                   bytes_before_imm += 2;
16154                   break;
16155                 case 1:
16156                   /* 1 byte displacement: when decoding the third source,
16157                      don't increase bytes_before_imm as this has already
16158                      been incremented by one in OP_E_memory while decoding
16159                      the second source operand.  */
16160                   if (opnum == 0)
16161                     bytes_before_imm++;
16162
16163                   break;
16164                 }
16165             }
16166         }
16167     }
16168
16169   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16170   return codep [bytes_before_imm];
16171 }
16172
16173 static void
16174 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16175 {
16176   const char **names;
16177
16178   if (reg == -1 && modrm.mod != 3)
16179     {
16180       OP_E_memory (bytemode, sizeflag);
16181       return;
16182     }
16183   else
16184     {
16185       if (reg == -1)
16186         {
16187           reg = modrm.rm;
16188           USED_REX (REX_B);
16189           if (rex & REX_B)
16190             reg += 8;
16191         }
16192       else if (reg > 7 && address_mode != mode_64bit)
16193         BadOp ();
16194     }
16195
16196   switch (vex.length)
16197     {
16198     case 128:
16199       names = names_xmm;
16200       break;
16201     case 256:
16202       names = names_ymm;
16203       break;
16204     default:
16205       abort ();
16206     }
16207   oappend (names[reg]);
16208 }
16209
16210 static void
16211 OP_EX_VexImmW (int bytemode, int sizeflag)
16212 {
16213   int reg = -1;
16214   static unsigned char vex_imm8;
16215
16216   if (vex_w_done == 0)
16217     {
16218       vex_w_done = 1;
16219
16220       /* Skip mod/rm byte.  */
16221       MODRM_CHECK;
16222       codep++;
16223
16224       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16225
16226       if (vex.w)
16227           reg = vex_imm8 >> 4;
16228
16229       OP_EX_VexReg (bytemode, sizeflag, reg);
16230     }
16231   else if (vex_w_done == 1)
16232     {
16233       vex_w_done = 2;
16234
16235       if (!vex.w)
16236           reg = vex_imm8 >> 4;
16237
16238       OP_EX_VexReg (bytemode, sizeflag, reg);
16239     }
16240   else
16241     {
16242       /* Output the imm8 directly.  */
16243       scratchbuf[0] = '$';
16244       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16245       oappend (scratchbuf + intel_syntax);
16246       scratchbuf[0] = '\0';
16247       codep++;
16248     }
16249 }
16250
16251 static void
16252 OP_Vex_2src (int bytemode, int sizeflag)
16253 {
16254   if (modrm.mod == 3)
16255     {
16256       int reg = modrm.rm;
16257       USED_REX (REX_B);
16258       if (rex & REX_B)
16259         reg += 8;
16260       oappend (names_xmm[reg]);
16261     }
16262   else
16263     {
16264       if (intel_syntax
16265           && (bytemode == v_mode || bytemode == v_swap_mode))
16266         {
16267           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16268           used_prefixes |= (prefixes & PREFIX_DATA);
16269         }
16270       OP_E (bytemode, sizeflag);
16271     }
16272 }
16273
16274 static void
16275 OP_Vex_2src_1 (int bytemode, int sizeflag)
16276 {
16277   if (modrm.mod == 3)
16278     {
16279       /* Skip mod/rm byte.   */
16280       MODRM_CHECK;
16281       codep++;
16282     }
16283
16284   if (vex.w)
16285     oappend (names_xmm[vex.register_specifier]);
16286   else
16287     OP_Vex_2src (bytemode, sizeflag);
16288 }
16289
16290 static void
16291 OP_Vex_2src_2 (int bytemode, int sizeflag)
16292 {
16293   if (vex.w)
16294     OP_Vex_2src (bytemode, sizeflag);
16295   else
16296     oappend (names_xmm[vex.register_specifier]);
16297 }
16298
16299 static void
16300 OP_EX_VexW (int bytemode, int sizeflag)
16301 {
16302   int reg = -1;
16303
16304   if (!vex_w_done)
16305     {
16306       vex_w_done = 1;
16307
16308       /* Skip mod/rm byte.  */
16309       MODRM_CHECK;
16310       codep++;
16311
16312       if (vex.w)
16313         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16314     }
16315   else
16316     {
16317       if (!vex.w)
16318         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16319     }
16320
16321   OP_EX_VexReg (bytemode, sizeflag, reg);
16322 }
16323
16324 static void
16325 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16326              int sizeflag ATTRIBUTE_UNUSED)
16327 {
16328   /* Skip the immediate byte and check for invalid bits.  */
16329   FETCH_DATA (the_info, codep + 1);
16330   if (*codep++ & 0xf)
16331     BadOp ();
16332 }
16333
16334 static void
16335 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16336 {
16337   int reg;
16338   const char **names;
16339
16340   FETCH_DATA (the_info, codep + 1);
16341   reg = *codep++;
16342
16343   if (bytemode != x_mode)
16344     abort ();
16345
16346   if (reg & 0xf)
16347       BadOp ();
16348
16349   reg >>= 4;
16350   if (reg > 7 && address_mode != mode_64bit)
16351     BadOp ();
16352
16353   switch (vex.length)
16354     {
16355     case 128:
16356       names = names_xmm;
16357       break;
16358     case 256:
16359       names = names_ymm;
16360       break;
16361     default:
16362       abort ();
16363     }
16364   oappend (names[reg]);
16365 }
16366
16367 static void
16368 OP_XMM_VexW (int bytemode, int sizeflag)
16369 {
16370   /* Turn off the REX.W bit since it is used for swapping operands
16371      now.  */
16372   rex &= ~REX_W;
16373   OP_XMM (bytemode, sizeflag);
16374 }
16375
16376 static void
16377 OP_EX_Vex (int bytemode, int sizeflag)
16378 {
16379   if (modrm.mod != 3)
16380     {
16381       if (vex.register_specifier != 0)
16382         BadOp ();
16383       need_vex_reg = 0;
16384     }
16385   OP_EX (bytemode, sizeflag);
16386 }
16387
16388 static void
16389 OP_XMM_Vex (int bytemode, int sizeflag)
16390 {
16391   if (modrm.mod != 3)
16392     {
16393       if (vex.register_specifier != 0)
16394         BadOp ();
16395       need_vex_reg = 0;
16396     }
16397   OP_XMM (bytemode, sizeflag);
16398 }
16399
16400 static void
16401 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16402 {
16403   switch (vex.length)
16404     {
16405     case 128:
16406       mnemonicendp = stpcpy (obuf, "vzeroupper");
16407       break;
16408     case 256:
16409       mnemonicendp = stpcpy (obuf, "vzeroall");
16410       break;
16411     default:
16412       abort ();
16413     }
16414 }
16415
16416 static struct op vex_cmp_op[] =
16417 {
16418   { STRING_COMMA_LEN ("eq") },
16419   { STRING_COMMA_LEN ("lt") },
16420   { STRING_COMMA_LEN ("le") },
16421   { STRING_COMMA_LEN ("unord") },
16422   { STRING_COMMA_LEN ("neq") },
16423   { STRING_COMMA_LEN ("nlt") },
16424   { STRING_COMMA_LEN ("nle") },
16425   { STRING_COMMA_LEN ("ord") },
16426   { STRING_COMMA_LEN ("eq_uq") },
16427   { STRING_COMMA_LEN ("nge") },
16428   { STRING_COMMA_LEN ("ngt") },
16429   { STRING_COMMA_LEN ("false") },
16430   { STRING_COMMA_LEN ("neq_oq") },
16431   { STRING_COMMA_LEN ("ge") },
16432   { STRING_COMMA_LEN ("gt") },
16433   { STRING_COMMA_LEN ("true") },
16434   { STRING_COMMA_LEN ("eq_os") },
16435   { STRING_COMMA_LEN ("lt_oq") },
16436   { STRING_COMMA_LEN ("le_oq") },
16437   { STRING_COMMA_LEN ("unord_s") },
16438   { STRING_COMMA_LEN ("neq_us") },
16439   { STRING_COMMA_LEN ("nlt_uq") },
16440   { STRING_COMMA_LEN ("nle_uq") },
16441   { STRING_COMMA_LEN ("ord_s") },
16442   { STRING_COMMA_LEN ("eq_us") },
16443   { STRING_COMMA_LEN ("nge_uq") },
16444   { STRING_COMMA_LEN ("ngt_uq") },
16445   { STRING_COMMA_LEN ("false_os") },
16446   { STRING_COMMA_LEN ("neq_os") },
16447   { STRING_COMMA_LEN ("ge_oq") },
16448   { STRING_COMMA_LEN ("gt_oq") },
16449   { STRING_COMMA_LEN ("true_us") },
16450 };
16451
16452 static void
16453 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16454 {
16455   unsigned int cmp_type;
16456
16457   FETCH_DATA (the_info, codep + 1);
16458   cmp_type = *codep++ & 0xff;
16459   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16460     {
16461       char suffix [3];
16462       char *p = mnemonicendp - 2;
16463       suffix[0] = p[0];
16464       suffix[1] = p[1];
16465       suffix[2] = '\0';
16466       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16467       mnemonicendp += vex_cmp_op[cmp_type].len;
16468     }
16469   else
16470     {
16471       /* We have a reserved extension byte.  Output it directly.  */
16472       scratchbuf[0] = '$';
16473       print_operand_value (scratchbuf + 1, 1, cmp_type);
16474       oappend (scratchbuf + intel_syntax);
16475       scratchbuf[0] = '\0';
16476     }
16477 }
16478
16479 static void
16480 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16481              int sizeflag ATTRIBUTE_UNUSED)
16482 {
16483   unsigned int cmp_type;
16484
16485   if (!vex.evex)
16486     abort ();
16487
16488   FETCH_DATA (the_info, codep + 1);
16489   cmp_type = *codep++ & 0xff;
16490   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16491      If it's the case, print suffix, otherwise - print the immediate.  */
16492   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16493       && cmp_type != 3
16494       && cmp_type != 7)
16495     {
16496       char suffix [3];
16497       char *p = mnemonicendp - 2;
16498
16499       /* vpcmp* can have both one- and two-lettered suffix.  */
16500       if (p[0] == 'p')
16501         {
16502           p++;
16503           suffix[0] = p[0];
16504           suffix[1] = '\0';
16505         }
16506       else
16507         {
16508           suffix[0] = p[0];
16509           suffix[1] = p[1];
16510           suffix[2] = '\0';
16511         }
16512
16513       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16514       mnemonicendp += simd_cmp_op[cmp_type].len;
16515     }
16516   else
16517     {
16518       /* We have a reserved extension byte.  Output it directly.  */
16519       scratchbuf[0] = '$';
16520       print_operand_value (scratchbuf + 1, 1, cmp_type);
16521       oappend (scratchbuf + intel_syntax);
16522       scratchbuf[0] = '\0';
16523     }
16524 }
16525
16526 static const struct op pclmul_op[] =
16527 {
16528   { STRING_COMMA_LEN ("lql") },
16529   { STRING_COMMA_LEN ("hql") },
16530   { STRING_COMMA_LEN ("lqh") },
16531   { STRING_COMMA_LEN ("hqh") }
16532 };
16533
16534 static void
16535 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16536               int sizeflag ATTRIBUTE_UNUSED)
16537 {
16538   unsigned int pclmul_type;
16539
16540   FETCH_DATA (the_info, codep + 1);
16541   pclmul_type = *codep++ & 0xff;
16542   switch (pclmul_type)
16543     {
16544     case 0x10:
16545       pclmul_type = 2;
16546       break;
16547     case 0x11:
16548       pclmul_type = 3;
16549       break;
16550     default:
16551       break;
16552     }
16553   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16554     {
16555       char suffix [4];
16556       char *p = mnemonicendp - 3;
16557       suffix[0] = p[0];
16558       suffix[1] = p[1];
16559       suffix[2] = p[2];
16560       suffix[3] = '\0';
16561       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16562       mnemonicendp += pclmul_op[pclmul_type].len;
16563     }
16564   else
16565     {
16566       /* We have a reserved extension byte.  Output it directly.  */
16567       scratchbuf[0] = '$';
16568       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16569       oappend (scratchbuf + intel_syntax);
16570       scratchbuf[0] = '\0';
16571     }
16572 }
16573
16574 static void
16575 MOVBE_Fixup (int bytemode, int sizeflag)
16576 {
16577   /* Add proper suffix to "movbe".  */
16578   char *p = mnemonicendp;
16579
16580   switch (bytemode)
16581     {
16582     case v_mode:
16583       if (intel_syntax)
16584         goto skip;
16585
16586       USED_REX (REX_W);
16587       if (sizeflag & SUFFIX_ALWAYS)
16588         {
16589           if (rex & REX_W)
16590             *p++ = 'q';
16591           else
16592             {
16593               if (sizeflag & DFLAG)
16594                 *p++ = 'l';
16595               else
16596                 *p++ = 'w';
16597               used_prefixes |= (prefixes & PREFIX_DATA);
16598             }
16599         }
16600       break;
16601     default:
16602       oappend (INTERNAL_DISASSEMBLER_ERROR);
16603       break;
16604     }
16605   mnemonicendp = p;
16606   *p = '\0';
16607
16608 skip:
16609   OP_M (bytemode, sizeflag);
16610 }
16611
16612 static void
16613 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16614 {
16615   int reg;
16616   const char **names;
16617
16618   /* Skip mod/rm byte.  */
16619   MODRM_CHECK;
16620   codep++;
16621
16622   if (vex.w)
16623     names = names64;
16624   else
16625     names = names32;
16626
16627   reg = modrm.rm;
16628   USED_REX (REX_B);
16629   if (rex & REX_B)
16630     reg += 8;
16631
16632   oappend (names[reg]);
16633 }
16634
16635 static void
16636 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16637 {
16638   const char **names;
16639
16640   if (vex.w)
16641     names = names64;
16642   else
16643     names = names32;
16644
16645   oappend (names[vex.register_specifier]);
16646 }
16647
16648 static void
16649 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16650 {
16651   if (!vex.evex
16652       || bytemode != mask_mode)
16653     abort ();
16654
16655   USED_REX (REX_R);
16656   if ((rex & REX_R) != 0 || !vex.r)
16657     {
16658       BadOp ();
16659       return;
16660     }
16661
16662   oappend (names_mask [modrm.reg]);
16663 }
16664
16665 static void
16666 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16667 {
16668   if (!vex.evex
16669       || (bytemode != evex_rounding_mode
16670           && bytemode != evex_sae_mode))
16671     abort ();
16672   if (modrm.mod == 3 && vex.b)
16673     switch (bytemode)
16674       {
16675       case evex_rounding_mode:
16676         oappend (names_rounding[vex.ll]);
16677         break;
16678       case evex_sae_mode:
16679         oappend ("{sae}");
16680         break;
16681       default:
16682         break;
16683       }
16684 }