opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void CMPXCHG8B_Fixup (int, int);
 111 static void XMM_Fixup (int, int);
 112 static void CRC32_Fixup (int, int);
 113 static void FXSAVE_Fixup (int, int);
 114 static void OP_LWPCB_E (int, int);
 115 static void OP_LWP_E (int, int);
 116 static void OP_LWP_I (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* REX bits in original REX prefix ignored.  */
 148 static int rex_ignored;
 149 /* Mark parts used in the REX prefix.  When we are testing for
 150    empty prefix (for 8bit register REX extension), just mask it
 151    out.  Otherwise test for REX bit is excuse for existence of REX
 152    only in case value is nonzero.  */
 153 #define USED_REX(value)                                 \
 154   {                                                     \
 155     if (value)                                          \
 156       {                                                 \
 157         if ((rex & value))                              \
 158           rex_used |= (value) | REX_OPCODE;             \
 159       }                                                 \
 160     else                                                \
 161       rex_used |= REX_OPCODE;                           \
 162   }
 163
 164 /* Flags for prefixes which we somehow handled when printing the
 165    current instruction.  */
 166 static int used_prefixes;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       longjmp (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 #define XX { NULL, 0 }
 219 #define Bad_Opcode NULL, { { NULL, 0 } }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define Iv { OP_I, v_mode }
 256 #define Iq { OP_I, q_mode }
 257 #define Iv64 { OP_I64, v_mode }
 258 #define Iw { OP_I, w_mode }
 259 #define I1 { OP_I, const_1_mode }
 260 #define Jb { OP_J, b_mode }
 261 #define Jv { OP_J, v_mode }
 262 #define Cm { OP_C, m_mode }
 263 #define Dm { OP_D, m_mode }
 264 #define Td { OP_T, d_mode }
 265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 266
 267 #define RMeAX { OP_REG, eAX_reg }
 268 #define RMeBX { OP_REG, eBX_reg }
 269 #define RMeCX { OP_REG, eCX_reg }
 270 #define RMeDX { OP_REG, eDX_reg }
 271 #define RMeSP { OP_REG, eSP_reg }
 272 #define RMeBP { OP_REG, eBP_reg }
 273 #define RMeSI { OP_REG, eSI_reg }
 274 #define RMeDI { OP_REG, eDI_reg }
 275 #define RMrAX { OP_REG, rAX_reg }
 276 #define RMrBX { OP_REG, rBX_reg }
 277 #define RMrCX { OP_REG, rCX_reg }
 278 #define RMrDX { OP_REG, rDX_reg }
 279 #define RMrSP { OP_REG, rSP_reg }
 280 #define RMrBP { OP_REG, rBP_reg }
 281 #define RMrSI { OP_REG, rSI_reg }
 282 #define RMrDI { OP_REG, rDI_reg }
 283 #define RMAL { OP_REG, al_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMCL { OP_REG, cl_reg }
 286 #define RMDL { OP_REG, dl_reg }
 287 #define RMBL { OP_REG, bl_reg }
 288 #define RMAH { OP_REG, ah_reg }
 289 #define RMCH { OP_REG, ch_reg }
 290 #define RMDH { OP_REG, dh_reg }
 291 #define RMBH { OP_REG, bh_reg }
 292 #define RMAX { OP_REG, ax_reg }
 293 #define RMDX { OP_REG, dx_reg }
 294
 295 #define eAX { OP_IMREG, eAX_reg }
 296 #define eBX { OP_IMREG, eBX_reg }
 297 #define eCX { OP_IMREG, eCX_reg }
 298 #define eDX { OP_IMREG, eDX_reg }
 299 #define eSP { OP_IMREG, eSP_reg }
 300 #define eBP { OP_IMREG, eBP_reg }
 301 #define eSI { OP_IMREG, eSI_reg }
 302 #define eDI { OP_IMREG, eDI_reg }
 303 #define AL { OP_IMREG, al_reg }
 304 #define CL { OP_IMREG, cl_reg }
 305 #define DL { OP_IMREG, dl_reg }
 306 #define BL { OP_IMREG, bl_reg }
 307 #define AH { OP_IMREG, ah_reg }
 308 #define CH { OP_IMREG, ch_reg }
 309 #define DH { OP_IMREG, dh_reg }
 310 #define BH { OP_IMREG, bh_reg }
 311 #define AX { OP_IMREG, ax_reg }
 312 #define DX { OP_IMREG, dx_reg }
 313 #define zAX { OP_IMREG, z_mode_ax_reg }
 314 #define indirDX { OP_IMREG, indir_dx_reg }
 315
 316 #define Sw { OP_SEG, w_mode }
 317 #define Sv { OP_SEG, v_mode }
 318 #define Ap { OP_DIR, 0 }
 319 #define Ob { OP_OFF64, b_mode }
 320 #define Ov { OP_OFF64, v_mode }
 321 #define Xb { OP_DSreg, eSI_reg }
 322 #define Xv { OP_DSreg, eSI_reg }
 323 #define Xz { OP_DSreg, eSI_reg }
 324 #define Yb { OP_ESreg, eDI_reg }
 325 #define Yv { OP_ESreg, eDI_reg }
 326 #define DSBX { OP_DSreg, eBX_reg }
 327
 328 #define es { OP_REG, es_reg }
 329 #define ss { OP_REG, ss_reg }
 330 #define cs { OP_REG, cs_reg }
 331 #define ds { OP_REG, ds_reg }
 332 #define fs { OP_REG, fs_reg }
 333 #define gs { OP_REG, gs_reg }
 334
 335 #define MX { OP_MMX, 0 }
 336 #define XM { OP_XMM, 0 }
 337 #define XMM { OP_XMM, xmm_mode }
 338 #define EM { OP_EM, v_mode }
 339 #define EMS { OP_EM, v_swap_mode }
 340 #define EMd { OP_EM, d_mode }
 341 #define EMx { OP_EM, x_mode }
 342 #define EXw { OP_EX, w_mode }
 343 #define EXd { OP_EX, d_mode }
 344 #define EXdS { OP_EX, d_swap_mode }
 345 #define EXq { OP_EX, q_mode }
 346 #define EXqS { OP_EX, q_swap_mode }
 347 #define EXx { OP_EX, x_mode }
 348 #define EXxS { OP_EX, x_swap_mode }
 349 #define EXxmm { OP_EX, xmm_mode }
 350 #define EXxmmq { OP_EX, xmmq_mode }
 351 #define EXymmq { OP_EX, ymmq_mode }
 352 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 353 #define MS { OP_MS, v_mode }
 354 #define XS { OP_XS, v_mode }
 355 #define EMCq { OP_EMC, q_mode }
 356 #define MXC { OP_MXC, 0 }
 357 #define OPSUF { OP_3DNowSuffix, 0 }
 358 #define CMP { CMP_Fixup, 0 }
 359 #define XMM0 { XMM_Fixup, 0 }
 360 #define FXSAVE { FXSAVE_Fixup, 0 }
 361 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 362 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 363
 364 #define Vex { OP_VEX, vex_mode }
 365 #define Vex128 { OP_VEX, vex128_mode }
 366 #define Vex256 { OP_VEX, vex256_mode }
 367 #define VexI4 { VEXI4_Fixup, 0}
 368 #define EXdVex { OP_EX_Vex, d_mode }
 369 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 370 #define EXqVex { OP_EX_Vex, q_mode }
 371 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 372 #define EXVexW { OP_EX_VexW, x_mode }
 373 #define EXdVexW { OP_EX_VexW, d_mode }
 374 #define EXqVexW { OP_EX_VexW, q_mode }
 375 #define XMVex { OP_XMM_Vex, 0 }
 376 #define XMVexW { OP_XMM_VexW, 0 }
 377 #define XMVexI4 { OP_REG_VexI4, x_mode }
 378 #define PCLMUL { PCLMUL_Fixup, 0 }
 379 #define VZERO { VZERO_Fixup, 0 }
 380 #define VCMP { VCMP_Fixup, 0 }
 381
 382 /* Used handle "rep" prefix for string instructions.  */
 383 #define Xbr { REP_Fixup, eSI_reg }
 384 #define Xvr { REP_Fixup, eSI_reg }
 385 #define Ybr { REP_Fixup, eDI_reg }
 386 #define Yvr { REP_Fixup, eDI_reg }
 387 #define Yzr { REP_Fixup, eDI_reg }
 388 #define indirDXr { REP_Fixup, indir_dx_reg }
 389 #define ALr { REP_Fixup, al_reg }
 390 #define eAXr { REP_Fixup, eAX_reg }
 391
 392 #define cond_jump_flag { NULL, cond_jump_mode }
 393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 394
 395 /* bits in sizeflag */
 396 #define SUFFIX_ALWAYS 4
 397 #define AFLAG 2
 398 #define DFLAG 1
 399
 400 enum
 401 {
 402   /* byte operand */
 403   b_mode = 1,
 404   /* byte operand with operand swapped */
 405   b_swap_mode,
 406   /* operand size depends on prefixes */
 407   v_mode,
 408   /* operand size depends on prefixes with operand swapped */
 409   v_swap_mode,
 410   /* word operand */
 411   w_mode,
 412   /* double word operand  */
 413   d_mode,
 414   /* double word operand with operand swapped */
 415   d_swap_mode,
 416   /* quad word operand */
 417   q_mode,
 418   /* quad word operand with operand swapped */
 419   q_swap_mode,
 420   /* ten-byte operand */
 421   t_mode,
 422   /* 16-byte XMM or 32-byte YMM operand */
 423   x_mode,
 424   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 425   x_swap_mode,
 426   /* 16-byte XMM operand */
 427   xmm_mode,
 428   /* 16-byte XMM or quad word operand */
 429   xmmq_mode,
 430   /* 32-byte YMM or quad word operand */
 431   ymmq_mode,
 432   /* d_mode in 32bit, q_mode in 64bit mode.  */
 433   m_mode,
 434   /* pair of v_mode operands */
 435   a_mode,
 436   cond_jump_mode,
 437   loop_jcxz_mode,
 438   /* operand size depends on REX prefixes.  */
 439   dq_mode,
 440   /* registers like dq_mode, memory like w_mode.  */
 441   dqw_mode,
 442   /* 4- or 6-byte pointer operand */
 443   f_mode,
 444   const_1_mode,
 445   /* v_mode for stack-related opcodes.  */
 446   stack_v_mode,
 447   /* non-quad operand size depends on prefixes */
 448   z_mode,
 449   /* 16-byte operand */
 450   o_mode,
 451   /* registers like dq_mode, memory like b_mode.  */
 452   dqb_mode,
 453   /* registers like dq_mode, memory like d_mode.  */
 454   dqd_mode,
 455   /* normal vex mode */
 456   vex_mode,
 457   /* 128bit vex mode */
 458   vex128_mode,
 459   /* 256bit vex mode */
 460   vex256_mode,
 461   /* operand size depends on the VEX.W bit.  */
 462   vex_w_dq_mode,
 463
 464   es_reg,
 465   cs_reg,
 466   ss_reg,
 467   ds_reg,
 468   fs_reg,
 469   gs_reg,
 470
 471   eAX_reg,
 472   eCX_reg,
 473   eDX_reg,
 474   eBX_reg,
 475   eSP_reg,
 476   eBP_reg,
 477   eSI_reg,
 478   eDI_reg,
 479
 480   al_reg,
 481   cl_reg,
 482   dl_reg,
 483   bl_reg,
 484   ah_reg,
 485   ch_reg,
 486   dh_reg,
 487   bh_reg,
 488
 489   ax_reg,
 490   cx_reg,
 491   dx_reg,
 492   bx_reg,
 493   sp_reg,
 494   bp_reg,
 495   si_reg,
 496   di_reg,
 497
 498   rAX_reg,
 499   rCX_reg,
 500   rDX_reg,
 501   rBX_reg,
 502   rSP_reg,
 503   rBP_reg,
 504   rSI_reg,
 505   rDI_reg,
 506
 507   z_mode_ax_reg,
 508   indir_dx_reg
 509 };
 510
 511 enum
 512 {
 513   FLOATCODE = 1,
 514   USE_REG_TABLE,
 515   USE_MOD_TABLE,
 516   USE_RM_TABLE,
 517   USE_PREFIX_TABLE,
 518   USE_X86_64_TABLE,
 519   USE_3BYTE_TABLE,
 520   USE_XOP_8F_TABLE,
 521   USE_VEX_C4_TABLE,
 522   USE_VEX_C5_TABLE,
 523   USE_VEX_LEN_TABLE,
 524   USE_VEX_W_TABLE
 525 };
 526
 527 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 528
 529 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 530 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 531 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 532 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 533 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 534 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 535 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 536 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 537 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 538 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 539 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 540 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 541
 542 enum
 543 {
 544   REG_80 = 0,
 545   REG_81,
 546   REG_82,
 547   REG_8F,
 548   REG_C0,
 549   REG_C1,
 550   REG_C6,
 551   REG_C7,
 552   REG_D0,
 553   REG_D1,
 554   REG_D2,
 555   REG_D3,
 556   REG_F6,
 557   REG_F7,
 558   REG_FE,
 559   REG_FF,
 560   REG_0F00,
 561   REG_0F01,
 562   REG_0F0D,
 563   REG_0F18,
 564   REG_0F71,
 565   REG_0F72,
 566   REG_0F73,
 567   REG_0FA6,
 568   REG_0FA7,
 569   REG_0FAE,
 570   REG_0FBA,
 571   REG_0FC7,
 572   REG_VEX_71,
 573   REG_VEX_72,
 574   REG_VEX_73,
 575   REG_VEX_AE,
 576   REG_XOP_LWPCB,
 577   REG_XOP_LWP
 578 };
 579
 580 enum
 581 {
 582   MOD_8D = 0,
 583   MOD_0F01_REG_0,
 584   MOD_0F01_REG_1,
 585   MOD_0F01_REG_2,
 586   MOD_0F01_REG_3,
 587   MOD_0F01_REG_7,
 588   MOD_0F12_PREFIX_0,
 589   MOD_0F13,
 590   MOD_0F16_PREFIX_0,
 591   MOD_0F17,
 592   MOD_0F18_REG_0,
 593   MOD_0F18_REG_1,
 594   MOD_0F18_REG_2,
 595   MOD_0F18_REG_3,
 596   MOD_0F20,
 597   MOD_0F21,
 598   MOD_0F22,
 599   MOD_0F23,
 600   MOD_0F24,
 601   MOD_0F26,
 602   MOD_0F2B_PREFIX_0,
 603   MOD_0F2B_PREFIX_1,
 604   MOD_0F2B_PREFIX_2,
 605   MOD_0F2B_PREFIX_3,
 606   MOD_0F51,
 607   MOD_0F71_REG_2,
 608   MOD_0F71_REG_4,
 609   MOD_0F71_REG_6,
 610   MOD_0F72_REG_2,
 611   MOD_0F72_REG_4,
 612   MOD_0F72_REG_6,
 613   MOD_0F73_REG_2,
 614   MOD_0F73_REG_3,
 615   MOD_0F73_REG_6,
 616   MOD_0F73_REG_7,
 617   MOD_0FAE_REG_0,
 618   MOD_0FAE_REG_1,
 619   MOD_0FAE_REG_2,
 620   MOD_0FAE_REG_3,
 621   MOD_0FAE_REG_4,
 622   MOD_0FAE_REG_5,
 623   MOD_0FAE_REG_6,
 624   MOD_0FAE_REG_7,
 625   MOD_0FB2,
 626   MOD_0FB4,
 627   MOD_0FB5,
 628   MOD_0FC7_REG_6,
 629   MOD_0FC7_REG_7,
 630   MOD_0FD7,
 631   MOD_0FE7_PREFIX_2,
 632   MOD_0FF0_PREFIX_3,
 633   MOD_0F382A_PREFIX_2,
 634   MOD_62_32BIT,
 635   MOD_C4_32BIT,
 636   MOD_C5_32BIT,
 637   MOD_VEX_12_PREFIX_0,
 638   MOD_VEX_13,
 639   MOD_VEX_16_PREFIX_0,
 640   MOD_VEX_17,
 641   MOD_VEX_2B,
 642   MOD_VEX_50,
 643   MOD_VEX_71_REG_2,
 644   MOD_VEX_71_REG_4,
 645   MOD_VEX_71_REG_6,
 646   MOD_VEX_72_REG_2,
 647   MOD_VEX_72_REG_4,
 648   MOD_VEX_72_REG_6,
 649   MOD_VEX_73_REG_2,
 650   MOD_VEX_73_REG_3,
 651   MOD_VEX_73_REG_6,
 652   MOD_VEX_73_REG_7,
 653   MOD_VEX_AE_REG_2,
 654   MOD_VEX_AE_REG_3,
 655   MOD_VEX_D7_PREFIX_2,
 656   MOD_VEX_E7_PREFIX_2,
 657   MOD_VEX_F0_PREFIX_3,
 658   MOD_VEX_3818_PREFIX_2,
 659   MOD_VEX_3819_PREFIX_2,
 660   MOD_VEX_381A_PREFIX_2,
 661   MOD_VEX_382A_PREFIX_2,
 662   MOD_VEX_382C_PREFIX_2,
 663   MOD_VEX_382D_PREFIX_2,
 664   MOD_VEX_382E_PREFIX_2,
 665   MOD_VEX_382F_PREFIX_2
 666 };
 667
 668 enum
 669 {
 670   RM_0F01_REG_0 = 0,
 671   RM_0F01_REG_1,
 672   RM_0F01_REG_2,
 673   RM_0F01_REG_3,
 674   RM_0F01_REG_7,
 675   RM_0FAE_REG_5,
 676   RM_0FAE_REG_6,
 677   RM_0FAE_REG_7
 678 };
 679
 680 enum
 681 {
 682   PREFIX_90 = 0,
 683   PREFIX_0F10,
 684   PREFIX_0F11,
 685   PREFIX_0F12,
 686   PREFIX_0F16,
 687   PREFIX_0F2A,
 688   PREFIX_0F2B,
 689   PREFIX_0F2C,
 690   PREFIX_0F2D,
 691   PREFIX_0F2E,
 692   PREFIX_0F2F,
 693   PREFIX_0F51,
 694   PREFIX_0F52,
 695   PREFIX_0F53,
 696   PREFIX_0F58,
 697   PREFIX_0F59,
 698   PREFIX_0F5A,
 699   PREFIX_0F5B,
 700   PREFIX_0F5C,
 701   PREFIX_0F5D,
 702   PREFIX_0F5E,
 703   PREFIX_0F5F,
 704   PREFIX_0F60,
 705   PREFIX_0F61,
 706   PREFIX_0F62,
 707   PREFIX_0F6C,
 708   PREFIX_0F6D,
 709   PREFIX_0F6F,
 710   PREFIX_0F70,
 711   PREFIX_0F73_REG_3,
 712   PREFIX_0F73_REG_7,
 713   PREFIX_0F78,
 714   PREFIX_0F79,
 715   PREFIX_0F7C,
 716   PREFIX_0F7D,
 717   PREFIX_0F7E,
 718   PREFIX_0F7F,
 719   PREFIX_0FB8,
 720   PREFIX_0FBD,
 721   PREFIX_0FC2,
 722   PREFIX_0FC3,
 723   PREFIX_0FC7_REG_6,
 724   PREFIX_0FD0,
 725   PREFIX_0FD6,
 726   PREFIX_0FE6,
 727   PREFIX_0FE7,
 728   PREFIX_0FF0,
 729   PREFIX_0FF7,
 730   PREFIX_0F3810,
 731   PREFIX_0F3814,
 732   PREFIX_0F3815,
 733   PREFIX_0F3817,
 734   PREFIX_0F3820,
 735   PREFIX_0F3821,
 736   PREFIX_0F3822,
 737   PREFIX_0F3823,
 738   PREFIX_0F3824,
 739   PREFIX_0F3825,
 740   PREFIX_0F3828,
 741   PREFIX_0F3829,
 742   PREFIX_0F382A,
 743   PREFIX_0F382B,
 744   PREFIX_0F3830,
 745   PREFIX_0F3831,
 746   PREFIX_0F3832,
 747   PREFIX_0F3833,
 748   PREFIX_0F3834,
 749   PREFIX_0F3835,
 750   PREFIX_0F3837,
 751   PREFIX_0F3838,
 752   PREFIX_0F3839,
 753   PREFIX_0F383A,
 754   PREFIX_0F383B,
 755   PREFIX_0F383C,
 756   PREFIX_0F383D,
 757   PREFIX_0F383E,
 758   PREFIX_0F383F,
 759   PREFIX_0F3840,
 760   PREFIX_0F3841,
 761   PREFIX_0F3880,
 762   PREFIX_0F3881,
 763   PREFIX_0F38DB,
 764   PREFIX_0F38DC,
 765   PREFIX_0F38DD,
 766   PREFIX_0F38DE,
 767   PREFIX_0F38DF,
 768   PREFIX_0F38F0,
 769   PREFIX_0F38F1,
 770   PREFIX_0F3A08,
 771   PREFIX_0F3A09,
 772   PREFIX_0F3A0A,
 773   PREFIX_0F3A0B,
 774   PREFIX_0F3A0C,
 775   PREFIX_0F3A0D,
 776   PREFIX_0F3A0E,
 777   PREFIX_0F3A14,
 778   PREFIX_0F3A15,
 779   PREFIX_0F3A16,
 780   PREFIX_0F3A17,
 781   PREFIX_0F3A20,
 782   PREFIX_0F3A21,
 783   PREFIX_0F3A22,
 784   PREFIX_0F3A40,
 785   PREFIX_0F3A41,
 786   PREFIX_0F3A42,
 787   PREFIX_0F3A44,
 788   PREFIX_0F3A60,
 789   PREFIX_0F3A61,
 790   PREFIX_0F3A62,
 791   PREFIX_0F3A63,
 792   PREFIX_0F3ADF,
 793   PREFIX_VEX_10,
 794   PREFIX_VEX_11,
 795   PREFIX_VEX_12,
 796   PREFIX_VEX_16,
 797   PREFIX_VEX_2A,
 798   PREFIX_VEX_2C,
 799   PREFIX_VEX_2D,
 800   PREFIX_VEX_2E,
 801   PREFIX_VEX_2F,
 802   PREFIX_VEX_51,
 803   PREFIX_VEX_52,
 804   PREFIX_VEX_53,
 805   PREFIX_VEX_58,
 806   PREFIX_VEX_59,
 807   PREFIX_VEX_5A,
 808   PREFIX_VEX_5B,
 809   PREFIX_VEX_5C,
 810   PREFIX_VEX_5D,
 811   PREFIX_VEX_5E,
 812   PREFIX_VEX_5F,
 813   PREFIX_VEX_60,
 814   PREFIX_VEX_61,
 815   PREFIX_VEX_62,
 816   PREFIX_VEX_63,
 817   PREFIX_VEX_64,
 818   PREFIX_VEX_65,
 819   PREFIX_VEX_66,
 820   PREFIX_VEX_67,
 821   PREFIX_VEX_68,
 822   PREFIX_VEX_69,
 823   PREFIX_VEX_6A,
 824   PREFIX_VEX_6B,
 825   PREFIX_VEX_6C,
 826   PREFIX_VEX_6D,
 827   PREFIX_VEX_6E,
 828   PREFIX_VEX_6F,
 829   PREFIX_VEX_70,
 830   PREFIX_VEX_71_REG_2,
 831   PREFIX_VEX_71_REG_4,
 832   PREFIX_VEX_71_REG_6,
 833   PREFIX_VEX_72_REG_2,
 834   PREFIX_VEX_72_REG_4,
 835   PREFIX_VEX_72_REG_6,
 836   PREFIX_VEX_73_REG_2,
 837   PREFIX_VEX_73_REG_3,
 838   PREFIX_VEX_73_REG_6,
 839   PREFIX_VEX_73_REG_7,
 840   PREFIX_VEX_74,
 841   PREFIX_VEX_75,
 842   PREFIX_VEX_76,
 843   PREFIX_VEX_77,
 844   PREFIX_VEX_7C,
 845   PREFIX_VEX_7D,
 846   PREFIX_VEX_7E,
 847   PREFIX_VEX_7F,
 848   PREFIX_VEX_C2,
 849   PREFIX_VEX_C4,
 850   PREFIX_VEX_C5,
 851   PREFIX_VEX_D0,
 852   PREFIX_VEX_D1,
 853   PREFIX_VEX_D2,
 854   PREFIX_VEX_D3,
 855   PREFIX_VEX_D4,
 856   PREFIX_VEX_D5,
 857   PREFIX_VEX_D6,
 858   PREFIX_VEX_D7,
 859   PREFIX_VEX_D8,
 860   PREFIX_VEX_D9,
 861   PREFIX_VEX_DA,
 862   PREFIX_VEX_DB,
 863   PREFIX_VEX_DC,
 864   PREFIX_VEX_DD,
 865   PREFIX_VEX_DE,
 866   PREFIX_VEX_DF,
 867   PREFIX_VEX_E0,
 868   PREFIX_VEX_E1,
 869   PREFIX_VEX_E2,
 870   PREFIX_VEX_E3,
 871   PREFIX_VEX_E4,
 872   PREFIX_VEX_E5,
 873   PREFIX_VEX_E6,
 874   PREFIX_VEX_E7,
 875   PREFIX_VEX_E8,
 876   PREFIX_VEX_E9,
 877   PREFIX_VEX_EA,
 878   PREFIX_VEX_EB,
 879   PREFIX_VEX_EC,
 880   PREFIX_VEX_ED,
 881   PREFIX_VEX_EE,
 882   PREFIX_VEX_EF,
 883   PREFIX_VEX_F0,
 884   PREFIX_VEX_F1,
 885   PREFIX_VEX_F2,
 886   PREFIX_VEX_F3,
 887   PREFIX_VEX_F4,
 888   PREFIX_VEX_F5,
 889   PREFIX_VEX_F6,
 890   PREFIX_VEX_F7,
 891   PREFIX_VEX_F8,
 892   PREFIX_VEX_F9,
 893   PREFIX_VEX_FA,
 894   PREFIX_VEX_FB,
 895   PREFIX_VEX_FC,
 896   PREFIX_VEX_FD,
 897   PREFIX_VEX_FE,
 898   PREFIX_VEX_3800,
 899   PREFIX_VEX_3801,
 900   PREFIX_VEX_3802,
 901   PREFIX_VEX_3803,
 902   PREFIX_VEX_3804,
 903   PREFIX_VEX_3805,
 904   PREFIX_VEX_3806,
 905   PREFIX_VEX_3807,
 906   PREFIX_VEX_3808,
 907   PREFIX_VEX_3809,
 908   PREFIX_VEX_380A,
 909   PREFIX_VEX_380B,
 910   PREFIX_VEX_380C,
 911   PREFIX_VEX_380D,
 912   PREFIX_VEX_380E,
 913   PREFIX_VEX_380F,
 914   PREFIX_VEX_3817,
 915   PREFIX_VEX_3818,
 916   PREFIX_VEX_3819,
 917   PREFIX_VEX_381A,
 918   PREFIX_VEX_381C,
 919   PREFIX_VEX_381D,
 920   PREFIX_VEX_381E,
 921   PREFIX_VEX_3820,
 922   PREFIX_VEX_3821,
 923   PREFIX_VEX_3822,
 924   PREFIX_VEX_3823,
 925   PREFIX_VEX_3824,
 926   PREFIX_VEX_3825,
 927   PREFIX_VEX_3828,
 928   PREFIX_VEX_3829,
 929   PREFIX_VEX_382A,
 930   PREFIX_VEX_382B,
 931   PREFIX_VEX_382C,
 932   PREFIX_VEX_382D,
 933   PREFIX_VEX_382E,
 934   PREFIX_VEX_382F,
 935   PREFIX_VEX_3830,
 936   PREFIX_VEX_3831,
 937   PREFIX_VEX_3832,
 938   PREFIX_VEX_3833,
 939   PREFIX_VEX_3834,
 940   PREFIX_VEX_3835,
 941   PREFIX_VEX_3837,
 942   PREFIX_VEX_3838,
 943   PREFIX_VEX_3839,
 944   PREFIX_VEX_383A,
 945   PREFIX_VEX_383B,
 946   PREFIX_VEX_383C,
 947   PREFIX_VEX_383D,
 948   PREFIX_VEX_383E,
 949   PREFIX_VEX_383F,
 950   PREFIX_VEX_3840,
 951   PREFIX_VEX_3841,
 952   PREFIX_VEX_3896,
 953   PREFIX_VEX_3897,
 954   PREFIX_VEX_3898,
 955   PREFIX_VEX_3899,
 956   PREFIX_VEX_389A,
 957   PREFIX_VEX_389B,
 958   PREFIX_VEX_389C,
 959   PREFIX_VEX_389D,
 960   PREFIX_VEX_389E,
 961   PREFIX_VEX_389F,
 962   PREFIX_VEX_38A6,
 963   PREFIX_VEX_38A7,
 964   PREFIX_VEX_38A8,
 965   PREFIX_VEX_38A9,
 966   PREFIX_VEX_38AA,
 967   PREFIX_VEX_38AB,
 968   PREFIX_VEX_38AC,
 969   PREFIX_VEX_38AD,
 970   PREFIX_VEX_38AE,
 971   PREFIX_VEX_38AF,
 972   PREFIX_VEX_38B6,
 973   PREFIX_VEX_38B7,
 974   PREFIX_VEX_38B8,
 975   PREFIX_VEX_38B9,
 976   PREFIX_VEX_38BA,
 977   PREFIX_VEX_38BB,
 978   PREFIX_VEX_38BC,
 979   PREFIX_VEX_38BD,
 980   PREFIX_VEX_38BE,
 981   PREFIX_VEX_38BF,
 982   PREFIX_VEX_38DB,
 983   PREFIX_VEX_38DC,
 984   PREFIX_VEX_38DD,
 985   PREFIX_VEX_38DE,
 986   PREFIX_VEX_38DF,
 987   PREFIX_VEX_3A04,
 988   PREFIX_VEX_3A05,
 989   PREFIX_VEX_3A06,
 990   PREFIX_VEX_3A08,
 991   PREFIX_VEX_3A09,
 992   PREFIX_VEX_3A0A,
 993   PREFIX_VEX_3A0B,
 994   PREFIX_VEX_3A0C,
 995   PREFIX_VEX_3A0D,
 996   PREFIX_VEX_3A0E,
 997   PREFIX_VEX_3A0F,
 998   PREFIX_VEX_3A14,
 999   PREFIX_VEX_3A15,
1000   PREFIX_VEX_3A16,
1001   PREFIX_VEX_3A17,
1002   PREFIX_VEX_3A18,
1003   PREFIX_VEX_3A19,
1004   PREFIX_VEX_3A20,
1005   PREFIX_VEX_3A21,
1006   PREFIX_VEX_3A22,
1007   PREFIX_VEX_3A40,
1008   PREFIX_VEX_3A41,
1009   PREFIX_VEX_3A42,
1010   PREFIX_VEX_3A44,
1011   PREFIX_VEX_3A4A,
1012   PREFIX_VEX_3A4B,
1013   PREFIX_VEX_3A4C,
1014   PREFIX_VEX_3A5C,
1015   PREFIX_VEX_3A5D,
1016   PREFIX_VEX_3A5E,
1017   PREFIX_VEX_3A5F,
1018   PREFIX_VEX_3A60,
1019   PREFIX_VEX_3A61,
1020   PREFIX_VEX_3A62,
1021   PREFIX_VEX_3A63,
1022   PREFIX_VEX_3A68,
1023   PREFIX_VEX_3A69,
1024   PREFIX_VEX_3A6A,
1025   PREFIX_VEX_3A6B,
1026   PREFIX_VEX_3A6C,
1027   PREFIX_VEX_3A6D,
1028   PREFIX_VEX_3A6E,
1029   PREFIX_VEX_3A6F,
1030   PREFIX_VEX_3A78,
1031   PREFIX_VEX_3A79,
1032   PREFIX_VEX_3A7A,
1033   PREFIX_VEX_3A7B,
1034   PREFIX_VEX_3A7C,
1035   PREFIX_VEX_3A7D,
1036   PREFIX_VEX_3A7E,
1037   PREFIX_VEX_3A7F,
1038   PREFIX_VEX_3ADF
1039 };
1040
1041 enum
1042 {
1043   X86_64_06 = 0,
1044   X86_64_07,
1045   X86_64_0D,
1046   X86_64_16,
1047   X86_64_17,
1048   X86_64_1E,
1049   X86_64_1F,
1050   X86_64_27,
1051   X86_64_2F,
1052   X86_64_37,
1053   X86_64_3F,
1054   X86_64_60,
1055   X86_64_61,
1056   X86_64_62,
1057   X86_64_63,
1058   X86_64_6D,
1059   X86_64_6F,
1060   X86_64_9A,
1061   X86_64_C4,
1062   X86_64_C5,
1063   X86_64_CE,
1064   X86_64_D4,
1065   X86_64_D5,
1066   X86_64_EA,
1067   X86_64_0F01_REG_0,
1068   X86_64_0F01_REG_1,
1069   X86_64_0F01_REG_2,
1070   X86_64_0F01_REG_3
1071 };
1072
1073 enum
1074 {
1075   THREE_BYTE_0F38 = 0,
1076   THREE_BYTE_0F3A,
1077   THREE_BYTE_0F7A
1078 };
1079
1080 enum
1081 {
1082   XOP_08 = 0,
1083   XOP_09,
1084   XOP_0A
1085 };
1086
1087 enum
1088 {
1089   VEX_0F = 0,
1090   VEX_0F38,
1091   VEX_0F3A
1092 };
1093
1094 enum
1095 {
1096   VEX_LEN_10_P_1 = 0,
1097   VEX_LEN_10_P_3,
1098   VEX_LEN_11_P_1,
1099   VEX_LEN_11_P_3,
1100   VEX_LEN_12_P_0_M_0,
1101   VEX_LEN_12_P_0_M_1,
1102   VEX_LEN_12_P_2,
1103   VEX_LEN_13_M_0,
1104   VEX_LEN_16_P_0_M_0,
1105   VEX_LEN_16_P_0_M_1,
1106   VEX_LEN_16_P_2,
1107   VEX_LEN_17_M_0,
1108   VEX_LEN_2A_P_1,
1109   VEX_LEN_2A_P_3,
1110   VEX_LEN_2C_P_1,
1111   VEX_LEN_2C_P_3,
1112   VEX_LEN_2D_P_1,
1113   VEX_LEN_2D_P_3,
1114   VEX_LEN_2E_P_0,
1115   VEX_LEN_2E_P_2,
1116   VEX_LEN_2F_P_0,
1117   VEX_LEN_2F_P_2,
1118   VEX_LEN_51_P_1,
1119   VEX_LEN_51_P_3,
1120   VEX_LEN_52_P_1,
1121   VEX_LEN_53_P_1,
1122   VEX_LEN_58_P_1,
1123   VEX_LEN_58_P_3,
1124   VEX_LEN_59_P_1,
1125   VEX_LEN_59_P_3,
1126   VEX_LEN_5A_P_1,
1127   VEX_LEN_5A_P_3,
1128   VEX_LEN_5C_P_1,
1129   VEX_LEN_5C_P_3,
1130   VEX_LEN_5D_P_1,
1131   VEX_LEN_5D_P_3,
1132   VEX_LEN_5E_P_1,
1133   VEX_LEN_5E_P_3,
1134   VEX_LEN_5F_P_1,
1135   VEX_LEN_5F_P_3,
1136   VEX_LEN_60_P_2,
1137   VEX_LEN_61_P_2,
1138   VEX_LEN_62_P_2,
1139   VEX_LEN_63_P_2,
1140   VEX_LEN_64_P_2,
1141   VEX_LEN_65_P_2,
1142   VEX_LEN_66_P_2,
1143   VEX_LEN_67_P_2,
1144   VEX_LEN_68_P_2,
1145   VEX_LEN_69_P_2,
1146   VEX_LEN_6A_P_2,
1147   VEX_LEN_6B_P_2,
1148   VEX_LEN_6C_P_2,
1149   VEX_LEN_6D_P_2,
1150   VEX_LEN_6E_P_2,
1151   VEX_LEN_70_P_1,
1152   VEX_LEN_70_P_2,
1153   VEX_LEN_70_P_3,
1154   VEX_LEN_71_R_2_P_2,
1155   VEX_LEN_71_R_4_P_2,
1156   VEX_LEN_71_R_6_P_2,
1157   VEX_LEN_72_R_2_P_2,
1158   VEX_LEN_72_R_4_P_2,
1159   VEX_LEN_72_R_6_P_2,
1160   VEX_LEN_73_R_2_P_2,
1161   VEX_LEN_73_R_3_P_2,
1162   VEX_LEN_73_R_6_P_2,
1163   VEX_LEN_73_R_7_P_2,
1164   VEX_LEN_74_P_2,
1165   VEX_LEN_75_P_2,
1166   VEX_LEN_76_P_2,
1167   VEX_LEN_7E_P_1,
1168   VEX_LEN_7E_P_2,
1169   VEX_LEN_AE_R_2_M_0,
1170   VEX_LEN_AE_R_3_M_0,
1171   VEX_LEN_C2_P_1,
1172   VEX_LEN_C2_P_3,
1173   VEX_LEN_C4_P_2,
1174   VEX_LEN_C5_P_2,
1175   VEX_LEN_D1_P_2,
1176   VEX_LEN_D2_P_2,
1177   VEX_LEN_D3_P_2,
1178   VEX_LEN_D4_P_2,
1179   VEX_LEN_D5_P_2,
1180   VEX_LEN_D6_P_2,
1181   VEX_LEN_D7_P_2_M_1,
1182   VEX_LEN_D8_P_2,
1183   VEX_LEN_D9_P_2,
1184   VEX_LEN_DA_P_2,
1185   VEX_LEN_DB_P_2,
1186   VEX_LEN_DC_P_2,
1187   VEX_LEN_DD_P_2,
1188   VEX_LEN_DE_P_2,
1189   VEX_LEN_DF_P_2,
1190   VEX_LEN_E0_P_2,
1191   VEX_LEN_E1_P_2,
1192   VEX_LEN_E2_P_2,
1193   VEX_LEN_E3_P_2,
1194   VEX_LEN_E4_P_2,
1195   VEX_LEN_E5_P_2,
1196   VEX_LEN_E8_P_2,
1197   VEX_LEN_E9_P_2,
1198   VEX_LEN_EA_P_2,
1199   VEX_LEN_EB_P_2,
1200   VEX_LEN_EC_P_2,
1201   VEX_LEN_ED_P_2,
1202   VEX_LEN_EE_P_2,
1203   VEX_LEN_EF_P_2,
1204   VEX_LEN_F1_P_2,
1205   VEX_LEN_F2_P_2,
1206   VEX_LEN_F3_P_2,
1207   VEX_LEN_F4_P_2,
1208   VEX_LEN_F5_P_2,
1209   VEX_LEN_F6_P_2,
1210   VEX_LEN_F7_P_2,
1211   VEX_LEN_F8_P_2,
1212   VEX_LEN_F9_P_2,
1213   VEX_LEN_FA_P_2,
1214   VEX_LEN_FB_P_2,
1215   VEX_LEN_FC_P_2,
1216   VEX_LEN_FD_P_2,
1217   VEX_LEN_FE_P_2,
1218   VEX_LEN_3800_P_2,
1219   VEX_LEN_3801_P_2,
1220   VEX_LEN_3802_P_2,
1221   VEX_LEN_3803_P_2,
1222   VEX_LEN_3804_P_2,
1223   VEX_LEN_3805_P_2,
1224   VEX_LEN_3806_P_2,
1225   VEX_LEN_3807_P_2,
1226   VEX_LEN_3808_P_2,
1227   VEX_LEN_3809_P_2,
1228   VEX_LEN_380A_P_2,
1229   VEX_LEN_380B_P_2,
1230   VEX_LEN_3819_P_2_M_0,
1231   VEX_LEN_381A_P_2_M_0,
1232   VEX_LEN_381C_P_2,
1233   VEX_LEN_381D_P_2,
1234   VEX_LEN_381E_P_2,
1235   VEX_LEN_3820_P_2,
1236   VEX_LEN_3821_P_2,
1237   VEX_LEN_3822_P_2,
1238   VEX_LEN_3823_P_2,
1239   VEX_LEN_3824_P_2,
1240   VEX_LEN_3825_P_2,
1241   VEX_LEN_3828_P_2,
1242   VEX_LEN_3829_P_2,
1243   VEX_LEN_382A_P_2_M_0,
1244   VEX_LEN_382B_P_2,
1245   VEX_LEN_3830_P_2,
1246   VEX_LEN_3831_P_2,
1247   VEX_LEN_3832_P_2,
1248   VEX_LEN_3833_P_2,
1249   VEX_LEN_3834_P_2,
1250   VEX_LEN_3835_P_2,
1251   VEX_LEN_3837_P_2,
1252   VEX_LEN_3838_P_2,
1253   VEX_LEN_3839_P_2,
1254   VEX_LEN_383A_P_2,
1255   VEX_LEN_383B_P_2,
1256   VEX_LEN_383C_P_2,
1257   VEX_LEN_383D_P_2,
1258   VEX_LEN_383E_P_2,
1259   VEX_LEN_383F_P_2,
1260   VEX_LEN_3840_P_2,
1261   VEX_LEN_3841_P_2,
1262   VEX_LEN_38DB_P_2,
1263   VEX_LEN_38DC_P_2,
1264   VEX_LEN_38DD_P_2,
1265   VEX_LEN_38DE_P_2,
1266   VEX_LEN_38DF_P_2,
1267   VEX_LEN_3A06_P_2,
1268   VEX_LEN_3A0A_P_2,
1269   VEX_LEN_3A0B_P_2,
1270   VEX_LEN_3A0E_P_2,
1271   VEX_LEN_3A0F_P_2,
1272   VEX_LEN_3A14_P_2,
1273   VEX_LEN_3A15_P_2,
1274   VEX_LEN_3A16_P_2,
1275   VEX_LEN_3A17_P_2,
1276   VEX_LEN_3A18_P_2,
1277   VEX_LEN_3A19_P_2,
1278   VEX_LEN_3A20_P_2,
1279   VEX_LEN_3A21_P_2,
1280   VEX_LEN_3A22_P_2,
1281   VEX_LEN_3A41_P_2,
1282   VEX_LEN_3A42_P_2,
1283   VEX_LEN_3A44_P_2,
1284   VEX_LEN_3A4C_P_2,
1285   VEX_LEN_3A60_P_2,
1286   VEX_LEN_3A61_P_2,
1287   VEX_LEN_3A62_P_2,
1288   VEX_LEN_3A63_P_2,
1289   VEX_LEN_3A6A_P_2,
1290   VEX_LEN_3A6B_P_2,
1291   VEX_LEN_3A6E_P_2,
1292   VEX_LEN_3A6F_P_2,
1293   VEX_LEN_3A7A_P_2,
1294   VEX_LEN_3A7B_P_2,
1295   VEX_LEN_3A7E_P_2,
1296   VEX_LEN_3A7F_P_2,
1297   VEX_LEN_3ADF_P_2,
1298   VEX_LEN_XOP_09_80,
1299   VEX_LEN_XOP_09_81
1300 };
1301
1302 enum
1303 {
1304   VEX_W_10_P_0 = 0,
1305   VEX_W_10_P_1,
1306   VEX_W_10_P_2,
1307   VEX_W_10_P_3,
1308   VEX_W_11_P_0,
1309   VEX_W_11_P_1,
1310   VEX_W_11_P_2,
1311   VEX_W_11_P_3,
1312   VEX_W_12_P_0_M_0,
1313   VEX_W_12_P_0_M_1,
1314   VEX_W_12_P_1,
1315   VEX_W_12_P_2,
1316   VEX_W_12_P_3,
1317   VEX_W_13_M_0,
1318   VEX_W_14,
1319   VEX_W_15,
1320   VEX_W_16_P_0_M_0,
1321   VEX_W_16_P_0_M_1,
1322   VEX_W_16_P_1,
1323   VEX_W_16_P_2,
1324   VEX_W_17_M_0,
1325   VEX_W_28,
1326   VEX_W_29,
1327   VEX_W_2B_M_0,
1328   VEX_W_2E_P_0,
1329   VEX_W_2E_P_2,
1330   VEX_W_2F_P_0,
1331   VEX_W_2F_P_2,
1332   VEX_W_50_M_0,
1333   VEX_W_51_P_0,
1334   VEX_W_51_P_1,
1335   VEX_W_51_P_2,
1336   VEX_W_51_P_3,
1337   VEX_W_52_P_0,
1338   VEX_W_52_P_1,
1339   VEX_W_53_P_0,
1340   VEX_W_53_P_1,
1341   VEX_W_58_P_0,
1342   VEX_W_58_P_1,
1343   VEX_W_58_P_2,
1344   VEX_W_58_P_3,
1345   VEX_W_59_P_0,
1346   VEX_W_59_P_1,
1347   VEX_W_59_P_2,
1348   VEX_W_59_P_3,
1349   VEX_W_5A_P_0,
1350   VEX_W_5A_P_1,
1351   VEX_W_5A_P_3,
1352   VEX_W_5B_P_0,
1353   VEX_W_5B_P_1,
1354   VEX_W_5B_P_2,
1355   VEX_W_5C_P_0,
1356   VEX_W_5C_P_1,
1357   VEX_W_5C_P_2,
1358   VEX_W_5C_P_3,
1359   VEX_W_5D_P_0,
1360   VEX_W_5D_P_1,
1361   VEX_W_5D_P_2,
1362   VEX_W_5D_P_3,
1363   VEX_W_5E_P_0,
1364   VEX_W_5E_P_1,
1365   VEX_W_5E_P_2,
1366   VEX_W_5E_P_3,
1367   VEX_W_5F_P_0,
1368   VEX_W_5F_P_1,
1369   VEX_W_5F_P_2,
1370   VEX_W_5F_P_3,
1371   VEX_W_60_P_2,
1372   VEX_W_61_P_2,
1373   VEX_W_62_P_2,
1374   VEX_W_63_P_2,
1375   VEX_W_64_P_2,
1376   VEX_W_65_P_2,
1377   VEX_W_66_P_2,
1378   VEX_W_67_P_2,
1379   VEX_W_68_P_2,
1380   VEX_W_69_P_2,
1381   VEX_W_6A_P_2,
1382   VEX_W_6B_P_2,
1383   VEX_W_6C_P_2,
1384   VEX_W_6D_P_2,
1385   VEX_W_6F_P_1,
1386   VEX_W_6F_P_2,
1387   VEX_W_70_P_1,
1388   VEX_W_70_P_2,
1389   VEX_W_70_P_3,
1390   VEX_W_71_R_2_P_2,
1391   VEX_W_71_R_4_P_2,
1392   VEX_W_71_R_6_P_2,
1393   VEX_W_72_R_2_P_2,
1394   VEX_W_72_R_4_P_2,
1395   VEX_W_72_R_6_P_2,
1396   VEX_W_73_R_2_P_2,
1397   VEX_W_73_R_3_P_2,
1398   VEX_W_73_R_6_P_2,
1399   VEX_W_73_R_7_P_2,
1400   VEX_W_74_P_2,
1401   VEX_W_75_P_2,
1402   VEX_W_76_P_2,
1403   VEX_W_77_P_0,
1404   VEX_W_7C_P_2,
1405   VEX_W_7C_P_3,
1406   VEX_W_7D_P_2,
1407   VEX_W_7D_P_3,
1408   VEX_W_7E_P_1,
1409   VEX_W_7F_P_1,
1410   VEX_W_7F_P_2,
1411   VEX_W_AE_R_2_M_0,
1412   VEX_W_AE_R_3_M_0,
1413   VEX_W_C2_P_0,
1414   VEX_W_C2_P_1,
1415   VEX_W_C2_P_2,
1416   VEX_W_C2_P_3,
1417   VEX_W_C4_P_2,
1418   VEX_W_C5_P_2,
1419   VEX_W_D0_P_2,
1420   VEX_W_D0_P_3,
1421   VEX_W_D1_P_2,
1422   VEX_W_D2_P_2,
1423   VEX_W_D3_P_2,
1424   VEX_W_D4_P_2,
1425   VEX_W_D5_P_2,
1426   VEX_W_D6_P_2,
1427   VEX_W_D7_P_2_M_1,
1428   VEX_W_D8_P_2,
1429   VEX_W_D9_P_2,
1430   VEX_W_DA_P_2,
1431   VEX_W_DB_P_2,
1432   VEX_W_DC_P_2,
1433   VEX_W_DD_P_2,
1434   VEX_W_DE_P_2,
1435   VEX_W_DF_P_2,
1436   VEX_W_E0_P_2,
1437   VEX_W_E1_P_2,
1438   VEX_W_E2_P_2,
1439   VEX_W_E3_P_2,
1440   VEX_W_E4_P_2,
1441   VEX_W_E5_P_2,
1442   VEX_W_E6_P_1,
1443   VEX_W_E6_P_2,
1444   VEX_W_E6_P_3,
1445   VEX_W_E7_P_2_M_0,
1446   VEX_W_E8_P_2,
1447   VEX_W_E9_P_2,
1448   VEX_W_EA_P_2,
1449   VEX_W_EB_P_2,
1450   VEX_W_EC_P_2,
1451   VEX_W_ED_P_2,
1452   VEX_W_EE_P_2,
1453   VEX_W_EF_P_2,
1454   VEX_W_F0_P_3_M_0,
1455   VEX_W_F1_P_2,
1456   VEX_W_F2_P_2,
1457   VEX_W_F3_P_2,
1458   VEX_W_F4_P_2,
1459   VEX_W_F5_P_2,
1460   VEX_W_F6_P_2,
1461   VEX_W_F7_P_2,
1462   VEX_W_F8_P_2,
1463   VEX_W_F9_P_2,
1464   VEX_W_FA_P_2,
1465   VEX_W_FB_P_2,
1466   VEX_W_FC_P_2,
1467   VEX_W_FD_P_2,
1468   VEX_W_FE_P_2,
1469   VEX_W_3800_P_2,
1470   VEX_W_3801_P_2,
1471   VEX_W_3802_P_2,
1472   VEX_W_3803_P_2,
1473   VEX_W_3804_P_2,
1474   VEX_W_3805_P_2,
1475   VEX_W_3806_P_2,
1476   VEX_W_3807_P_2,
1477   VEX_W_3808_P_2,
1478   VEX_W_3809_P_2,
1479   VEX_W_380A_P_2,
1480   VEX_W_380B_P_2,
1481   VEX_W_380C_P_2,
1482   VEX_W_380D_P_2,
1483   VEX_W_380E_P_2,
1484   VEX_W_380F_P_2,
1485   VEX_W_3817_P_2,
1486   VEX_W_3818_P_2_M_0,
1487   VEX_W_3819_P_2_M_0,
1488   VEX_W_381A_P_2_M_0,
1489   VEX_W_381C_P_2,
1490   VEX_W_381D_P_2,
1491   VEX_W_381E_P_2,
1492   VEX_W_3820_P_2,
1493   VEX_W_3821_P_2,
1494   VEX_W_3822_P_2,
1495   VEX_W_3823_P_2,
1496   VEX_W_3824_P_2,
1497   VEX_W_3825_P_2,
1498   VEX_W_3828_P_2,
1499   VEX_W_3829_P_2,
1500   VEX_W_382A_P_2_M_0,
1501   VEX_W_382B_P_2,
1502   VEX_W_382C_P_2_M_0,
1503   VEX_W_382D_P_2_M_0,
1504   VEX_W_382E_P_2_M_0,
1505   VEX_W_382F_P_2_M_0,
1506   VEX_W_3830_P_2,
1507   VEX_W_3831_P_2,
1508   VEX_W_3832_P_2,
1509   VEX_W_3833_P_2,
1510   VEX_W_3834_P_2,
1511   VEX_W_3835_P_2,
1512   VEX_W_3837_P_2,
1513   VEX_W_3838_P_2,
1514   VEX_W_3839_P_2,
1515   VEX_W_383A_P_2,
1516   VEX_W_383B_P_2,
1517   VEX_W_383C_P_2,
1518   VEX_W_383D_P_2,
1519   VEX_W_383E_P_2,
1520   VEX_W_383F_P_2,
1521   VEX_W_3840_P_2,
1522   VEX_W_3841_P_2,
1523   VEX_W_38DB_P_2,
1524   VEX_W_38DC_P_2,
1525   VEX_W_38DD_P_2,
1526   VEX_W_38DE_P_2,
1527   VEX_W_38DF_P_2,
1528   VEX_W_3A04_P_2,
1529   VEX_W_3A05_P_2,
1530   VEX_W_3A06_P_2,
1531   VEX_W_3A08_P_2,
1532   VEX_W_3A09_P_2,
1533   VEX_W_3A0A_P_2,
1534   VEX_W_3A0B_P_2,
1535   VEX_W_3A0C_P_2,
1536   VEX_W_3A0D_P_2,
1537   VEX_W_3A0E_P_2,
1538   VEX_W_3A0F_P_2,
1539   VEX_W_3A14_P_2,
1540   VEX_W_3A15_P_2,
1541   VEX_W_3A18_P_2,
1542   VEX_W_3A19_P_2,
1543   VEX_W_3A20_P_2,
1544   VEX_W_3A21_P_2,
1545   VEX_W_3A40_P_2,
1546   VEX_W_3A41_P_2,
1547   VEX_W_3A42_P_2,
1548   VEX_W_3A44_P_2,
1549   VEX_W_3A4A_P_2,
1550   VEX_W_3A4B_P_2,
1551   VEX_W_3A4C_P_2,
1552   VEX_W_3A60_P_2,
1553   VEX_W_3A61_P_2,
1554   VEX_W_3A62_P_2,
1555   VEX_W_3A63_P_2,
1556   VEX_W_3ADF_P_2
1557 };
1558
1559 typedef void (*op_rtn) (int bytemode, int sizeflag);
1560
1561 struct dis386 {
1562   const char *name;
1563   struct
1564     {
1565       op_rtn rtn;
1566       int bytemode;
1567     } op[MAX_OPERANDS];
1568 };
1569
1570 /* Upper case letters in the instruction names here are macros.
1571    'A' => print 'b' if no register operands or suffix_always is true
1572    'B' => print 'b' if suffix_always is true
1573    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1574           size prefix
1575    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1576           suffix_always is true
1577    'E' => print 'e' if 32-bit form of jcxz
1578    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1579    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1580    'H' => print ",pt" or ",pn" branch hint
1581    'I' => honor following macro letter even in Intel mode (implemented only
1582           for some of the macro letters)
1583    'J' => print 'l'
1584    'K' => print 'd' or 'q' if rex prefix is present.
1585    'L' => print 'l' if suffix_always is true
1586    'M' => print 'r' if intel_mnemonic is false.
1587    'N' => print 'n' if instruction has no wait "prefix"
1588    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1589    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1590           or suffix_always is true.  print 'q' if rex prefix is present.
1591    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1592           is true
1593    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1594    'S' => print 'w', 'l' or 'q' if suffix_always is true
1595    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1596    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1597    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1598    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1599    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1600    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1601           suffix_always is true.
1602    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1603    '!' => change condition from true to false or from false to true.
1604    '%' => add 1 upper case letter to the macro.
1605
1606    2 upper case letter macros:
1607    "XY" => print 'x' or 'y' if no register operands or suffix_always
1608            is true.
1609    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1610    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1611            or suffix_always is true
1612    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1613    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1614    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1615
1616    Many of the above letters print nothing in Intel mode.  See "putop"
1617    for the details.
1618
1619    Braces '{' and '}', and vertical bars '|', indicate alternative
1620    mnemonic strings for AT&T and Intel.  */
1621
1622 static const struct dis386 dis386[] = {
1623   /* 00 */
1624   { "addB",             { Eb, Gb } },
1625   { "addS",             { Ev, Gv } },
1626   { "addB",             { Gb, EbS } },
1627   { "addS",             { Gv, EvS } },
1628   { "addB",             { AL, Ib } },
1629   { "addS",             { eAX, Iv } },
1630   { X86_64_TABLE (X86_64_06) },
1631   { X86_64_TABLE (X86_64_07) },
1632   /* 08 */
1633   { "orB",              { Eb, Gb } },
1634   { "orS",              { Ev, Gv } },
1635   { "orB",              { Gb, EbS } },
1636   { "orS",              { Gv, EvS } },
1637   { "orB",              { AL, Ib } },
1638   { "orS",              { eAX, Iv } },
1639   { X86_64_TABLE (X86_64_0D) },
1640   { Bad_Opcode },       /* 0x0f extended opcode escape */
1641   /* 10 */
1642   { "adcB",             { Eb, Gb } },
1643   { "adcS",             { Ev, Gv } },
1644   { "adcB",             { Gb, EbS } },
1645   { "adcS",             { Gv, EvS } },
1646   { "adcB",             { AL, Ib } },
1647   { "adcS",             { eAX, Iv } },
1648   { X86_64_TABLE (X86_64_16) },
1649   { X86_64_TABLE (X86_64_17) },
1650   /* 18 */
1651   { "sbbB",             { Eb, Gb } },
1652   { "sbbS",             { Ev, Gv } },
1653   { "sbbB",             { Gb, EbS } },
1654   { "sbbS",             { Gv, EvS } },
1655   { "sbbB",             { AL, Ib } },
1656   { "sbbS",             { eAX, Iv } },
1657   { X86_64_TABLE (X86_64_1E) },
1658   { X86_64_TABLE (X86_64_1F) },
1659   /* 20 */
1660   { "andB",             { Eb, Gb } },
1661   { "andS",             { Ev, Gv } },
1662   { "andB",             { Gb, EbS } },
1663   { "andS",             { Gv, EvS } },
1664   { "andB",             { AL, Ib } },
1665   { "andS",             { eAX, Iv } },
1666   { Bad_Opcode },       /* SEG ES prefix */
1667   { X86_64_TABLE (X86_64_27) },
1668   /* 28 */
1669   { "subB",             { Eb, Gb } },
1670   { "subS",             { Ev, Gv } },
1671   { "subB",             { Gb, EbS } },
1672   { "subS",             { Gv, EvS } },
1673   { "subB",             { AL, Ib } },
1674   { "subS",             { eAX, Iv } },
1675   { Bad_Opcode },       /* SEG CS prefix */
1676   { X86_64_TABLE (X86_64_2F) },
1677   /* 30 */
1678   { "xorB",             { Eb, Gb } },
1679   { "xorS",             { Ev, Gv } },
1680   { "xorB",             { Gb, EbS } },
1681   { "xorS",             { Gv, EvS } },
1682   { "xorB",             { AL, Ib } },
1683   { "xorS",             { eAX, Iv } },
1684   { Bad_Opcode },       /* SEG SS prefix */
1685   { X86_64_TABLE (X86_64_37) },
1686   /* 38 */
1687   { "cmpB",             { Eb, Gb } },
1688   { "cmpS",             { Ev, Gv } },
1689   { "cmpB",             { Gb, EbS } },
1690   { "cmpS",             { Gv, EvS } },
1691   { "cmpB",             { AL, Ib } },
1692   { "cmpS",             { eAX, Iv } },
1693   { Bad_Opcode },       /* SEG DS prefix */
1694   { X86_64_TABLE (X86_64_3F) },
1695   /* 40 */
1696   { "inc{S|}",          { RMeAX } },
1697   { "inc{S|}",          { RMeCX } },
1698   { "inc{S|}",          { RMeDX } },
1699   { "inc{S|}",          { RMeBX } },
1700   { "inc{S|}",          { RMeSP } },
1701   { "inc{S|}",          { RMeBP } },
1702   { "inc{S|}",          { RMeSI } },
1703   { "inc{S|}",          { RMeDI } },
1704   /* 48 */
1705   { "dec{S|}",          { RMeAX } },
1706   { "dec{S|}",          { RMeCX } },
1707   { "dec{S|}",          { RMeDX } },
1708   { "dec{S|}",          { RMeBX } },
1709   { "dec{S|}",          { RMeSP } },
1710   { "dec{S|}",          { RMeBP } },
1711   { "dec{S|}",          { RMeSI } },
1712   { "dec{S|}",          { RMeDI } },
1713   /* 50 */
1714   { "pushV",            { RMrAX } },
1715   { "pushV",            { RMrCX } },
1716   { "pushV",            { RMrDX } },
1717   { "pushV",            { RMrBX } },
1718   { "pushV",            { RMrSP } },
1719   { "pushV",            { RMrBP } },
1720   { "pushV",            { RMrSI } },
1721   { "pushV",            { RMrDI } },
1722   /* 58 */
1723   { "popV",             { RMrAX } },
1724   { "popV",             { RMrCX } },
1725   { "popV",             { RMrDX } },
1726   { "popV",             { RMrBX } },
1727   { "popV",             { RMrSP } },
1728   { "popV",             { RMrBP } },
1729   { "popV",             { RMrSI } },
1730   { "popV",             { RMrDI } },
1731   /* 60 */
1732   { X86_64_TABLE (X86_64_60) },
1733   { X86_64_TABLE (X86_64_61) },
1734   { X86_64_TABLE (X86_64_62) },
1735   { X86_64_TABLE (X86_64_63) },
1736   { Bad_Opcode },       /* seg fs */
1737   { Bad_Opcode },       /* seg gs */
1738   { Bad_Opcode },       /* op size prefix */
1739   { Bad_Opcode },       /* adr size prefix */
1740   /* 68 */
1741   { "pushT",            { Iq } },
1742   { "imulS",            { Gv, Ev, Iv } },
1743   { "pushT",            { sIb } },
1744   { "imulS",            { Gv, Ev, sIb } },
1745   { "ins{b|}",          { Ybr, indirDX } },
1746   { X86_64_TABLE (X86_64_6D) },
1747   { "outs{b|}",         { indirDXr, Xb } },
1748   { X86_64_TABLE (X86_64_6F) },
1749   /* 70 */
1750   { "joH",              { Jb, XX, cond_jump_flag } },
1751   { "jnoH",             { Jb, XX, cond_jump_flag } },
1752   { "jbH",              { Jb, XX, cond_jump_flag } },
1753   { "jaeH",             { Jb, XX, cond_jump_flag } },
1754   { "jeH",              { Jb, XX, cond_jump_flag } },
1755   { "jneH",             { Jb, XX, cond_jump_flag } },
1756   { "jbeH",             { Jb, XX, cond_jump_flag } },
1757   { "jaH",              { Jb, XX, cond_jump_flag } },
1758   /* 78 */
1759   { "jsH",              { Jb, XX, cond_jump_flag } },
1760   { "jnsH",             { Jb, XX, cond_jump_flag } },
1761   { "jpH",              { Jb, XX, cond_jump_flag } },
1762   { "jnpH",             { Jb, XX, cond_jump_flag } },
1763   { "jlH",              { Jb, XX, cond_jump_flag } },
1764   { "jgeH",             { Jb, XX, cond_jump_flag } },
1765   { "jleH",             { Jb, XX, cond_jump_flag } },
1766   { "jgH",              { Jb, XX, cond_jump_flag } },
1767   /* 80 */
1768   { REG_TABLE (REG_80) },
1769   { REG_TABLE (REG_81) },
1770   { Bad_Opcode },
1771   { REG_TABLE (REG_82) },
1772   { "testB",            { Eb, Gb } },
1773   { "testS",            { Ev, Gv } },
1774   { "xchgB",            { Eb, Gb } },
1775   { "xchgS",            { Ev, Gv } },
1776   /* 88 */
1777   { "movB",             { Eb, Gb } },
1778   { "movS",             { Ev, Gv } },
1779   { "movB",             { Gb, EbS } },
1780   { "movS",             { Gv, EvS } },
1781   { "movD",             { Sv, Sw } },
1782   { MOD_TABLE (MOD_8D) },
1783   { "movD",             { Sw, Sv } },
1784   { REG_TABLE (REG_8F) },
1785   /* 90 */
1786   { PREFIX_TABLE (PREFIX_90) },
1787   { "xchgS",            { RMeCX, eAX } },
1788   { "xchgS",            { RMeDX, eAX } },
1789   { "xchgS",            { RMeBX, eAX } },
1790   { "xchgS",            { RMeSP, eAX } },
1791   { "xchgS",            { RMeBP, eAX } },
1792   { "xchgS",            { RMeSI, eAX } },
1793   { "xchgS",            { RMeDI, eAX } },
1794   /* 98 */
1795   { "cW{t|}R",          { XX } },
1796   { "cR{t|}O",          { XX } },
1797   { X86_64_TABLE (X86_64_9A) },
1798   { Bad_Opcode },       /* fwait */
1799   { "pushfT",           { XX } },
1800   { "popfT",            { XX } },
1801   { "sahf",             { XX } },
1802   { "lahf",             { XX } },
1803   /* a0 */
1804   { "mov%LB",           { AL, Ob } },
1805   { "mov%LS",           { eAX, Ov } },
1806   { "mov%LB",           { Ob, AL } },
1807   { "mov%LS",           { Ov, eAX } },
1808   { "movs{b|}",         { Ybr, Xb } },
1809   { "movs{R|}",         { Yvr, Xv } },
1810   { "cmps{b|}",         { Xb, Yb } },
1811   { "cmps{R|}",         { Xv, Yv } },
1812   /* a8 */
1813   { "testB",            { AL, Ib } },
1814   { "testS",            { eAX, Iv } },
1815   { "stosB",            { Ybr, AL } },
1816   { "stosS",            { Yvr, eAX } },
1817   { "lodsB",            { ALr, Xb } },
1818   { "lodsS",            { eAXr, Xv } },
1819   { "scasB",            { AL, Yb } },
1820   { "scasS",            { eAX, Yv } },
1821   /* b0 */
1822   { "movB",             { RMAL, Ib } },
1823   { "movB",             { RMCL, Ib } },
1824   { "movB",             { RMDL, Ib } },
1825   { "movB",             { RMBL, Ib } },
1826   { "movB",             { RMAH, Ib } },
1827   { "movB",             { RMCH, Ib } },
1828   { "movB",             { RMDH, Ib } },
1829   { "movB",             { RMBH, Ib } },
1830   /* b8 */
1831   { "mov%LV",           { RMeAX, Iv64 } },
1832   { "mov%LV",           { RMeCX, Iv64 } },
1833   { "mov%LV",           { RMeDX, Iv64 } },
1834   { "mov%LV",           { RMeBX, Iv64 } },
1835   { "mov%LV",           { RMeSP, Iv64 } },
1836   { "mov%LV",           { RMeBP, Iv64 } },
1837   { "mov%LV",           { RMeSI, Iv64 } },
1838   { "mov%LV",           { RMeDI, Iv64 } },
1839   /* c0 */
1840   { REG_TABLE (REG_C0) },
1841   { REG_TABLE (REG_C1) },
1842   { "retT",             { Iw } },
1843   { "retT",             { XX } },
1844   { X86_64_TABLE (X86_64_C4) },
1845   { X86_64_TABLE (X86_64_C5) },
1846   { REG_TABLE (REG_C6) },
1847   { REG_TABLE (REG_C7) },
1848   /* c8 */
1849   { "enterT",           { Iw, Ib } },
1850   { "leaveT",           { XX } },
1851   { "Jret{|f}P",        { Iw } },
1852   { "Jret{|f}P",        { XX } },
1853   { "int3",             { XX } },
1854   { "int",              { Ib } },
1855   { X86_64_TABLE (X86_64_CE) },
1856   { "iretP",            { XX } },
1857   /* d0 */
1858   { REG_TABLE (REG_D0) },
1859   { REG_TABLE (REG_D1) },
1860   { REG_TABLE (REG_D2) },
1861   { REG_TABLE (REG_D3) },
1862   { X86_64_TABLE (X86_64_D4) },
1863   { X86_64_TABLE (X86_64_D5) },
1864   { Bad_Opcode },
1865   { "xlat",             { DSBX } },
1866   /* d8 */
1867   { FLOAT },
1868   { FLOAT },
1869   { FLOAT },
1870   { FLOAT },
1871   { FLOAT },
1872   { FLOAT },
1873   { FLOAT },
1874   { FLOAT },
1875   /* e0 */
1876   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1877   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1878   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1879   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1880   { "inB",              { AL, Ib } },
1881   { "inG",              { zAX, Ib } },
1882   { "outB",             { Ib, AL } },
1883   { "outG",             { Ib, zAX } },
1884   /* e8 */
1885   { "callT",            { Jv } },
1886   { "jmpT",             { Jv } },
1887   { X86_64_TABLE (X86_64_EA) },
1888   { "jmp",              { Jb } },
1889   { "inB",              { AL, indirDX } },
1890   { "inG",              { zAX, indirDX } },
1891   { "outB",             { indirDX, AL } },
1892   { "outG",             { indirDX, zAX } },
1893   /* f0 */
1894   { Bad_Opcode },       /* lock prefix */
1895   { "icebp",            { XX } },
1896   { Bad_Opcode },       /* repne */
1897   { Bad_Opcode },       /* repz */
1898   { "hlt",              { XX } },
1899   { "cmc",              { XX } },
1900   { REG_TABLE (REG_F6) },
1901   { REG_TABLE (REG_F7) },
1902   /* f8 */
1903   { "clc",              { XX } },
1904   { "stc",              { XX } },
1905   { "cli",              { XX } },
1906   { "sti",              { XX } },
1907   { "cld",              { XX } },
1908   { "std",              { XX } },
1909   { REG_TABLE (REG_FE) },
1910   { REG_TABLE (REG_FF) },
1911 };
1912
1913 static const struct dis386 dis386_twobyte[] = {
1914   /* 00 */
1915   { REG_TABLE (REG_0F00 ) },
1916   { REG_TABLE (REG_0F01 ) },
1917   { "larS",             { Gv, Ew } },
1918   { "lslS",             { Gv, Ew } },
1919   { Bad_Opcode },
1920   { "syscall",          { XX } },
1921   { "clts",             { XX } },
1922   { "sysretP",          { XX } },
1923   /* 08 */
1924   { "invd",             { XX } },
1925   { "wbinvd",           { XX } },
1926   { Bad_Opcode },
1927   { "ud2a",             { XX } },
1928   { Bad_Opcode },
1929   { REG_TABLE (REG_0F0D) },
1930   { "femms",            { XX } },
1931   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1932   /* 10 */
1933   { PREFIX_TABLE (PREFIX_0F10) },
1934   { PREFIX_TABLE (PREFIX_0F11) },
1935   { PREFIX_TABLE (PREFIX_0F12) },
1936   { MOD_TABLE (MOD_0F13) },
1937   { "unpcklpX",         { XM, EXx } },
1938   { "unpckhpX",         { XM, EXx } },
1939   { PREFIX_TABLE (PREFIX_0F16) },
1940   { MOD_TABLE (MOD_0F17) },
1941   /* 18 */
1942   { REG_TABLE (REG_0F18) },
1943   { "nopQ",             { Ev } },
1944   { "nopQ",             { Ev } },
1945   { "nopQ",             { Ev } },
1946   { "nopQ",             { Ev } },
1947   { "nopQ",             { Ev } },
1948   { "nopQ",             { Ev } },
1949   { "nopQ",             { Ev } },
1950   /* 20 */
1951   { MOD_TABLE (MOD_0F20) },
1952   { MOD_TABLE (MOD_0F21) },
1953   { MOD_TABLE (MOD_0F22) },
1954   { MOD_TABLE (MOD_0F23) },
1955   { MOD_TABLE (MOD_0F24) },
1956   { Bad_Opcode },
1957   { MOD_TABLE (MOD_0F26) },
1958   { Bad_Opcode },
1959   /* 28 */
1960   { "movapX",           { XM, EXx } },
1961   { "movapX",           { EXxS, XM } },
1962   { PREFIX_TABLE (PREFIX_0F2A) },
1963   { PREFIX_TABLE (PREFIX_0F2B) },
1964   { PREFIX_TABLE (PREFIX_0F2C) },
1965   { PREFIX_TABLE (PREFIX_0F2D) },
1966   { PREFIX_TABLE (PREFIX_0F2E) },
1967   { PREFIX_TABLE (PREFIX_0F2F) },
1968   /* 30 */
1969   { "wrmsr",            { XX } },
1970   { "rdtsc",            { XX } },
1971   { "rdmsr",            { XX } },
1972   { "rdpmc",            { XX } },
1973   { "sysenter",         { XX } },
1974   { "sysexit",          { XX } },
1975   { Bad_Opcode },
1976   { "getsec",           { XX } },
1977   /* 38 */
1978   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1979   { Bad_Opcode },
1980   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1981   { Bad_Opcode },
1982   { Bad_Opcode },
1983   { Bad_Opcode },
1984   { Bad_Opcode },
1985   { Bad_Opcode },
1986   /* 40 */
1987   { "cmovoS",           { Gv, Ev } },
1988   { "cmovnoS",          { Gv, Ev } },
1989   { "cmovbS",           { Gv, Ev } },
1990   { "cmovaeS",          { Gv, Ev } },
1991   { "cmoveS",           { Gv, Ev } },
1992   { "cmovneS",          { Gv, Ev } },
1993   { "cmovbeS",          { Gv, Ev } },
1994   { "cmovaS",           { Gv, Ev } },
1995   /* 48 */
1996   { "cmovsS",           { Gv, Ev } },
1997   { "cmovnsS",          { Gv, Ev } },
1998   { "cmovpS",           { Gv, Ev } },
1999   { "cmovnpS",          { Gv, Ev } },
2000   { "cmovlS",           { Gv, Ev } },
2001   { "cmovgeS",          { Gv, Ev } },
2002   { "cmovleS",          { Gv, Ev } },
2003   { "cmovgS",           { Gv, Ev } },
2004   /* 50 */
2005   { MOD_TABLE (MOD_0F51) },
2006   { PREFIX_TABLE (PREFIX_0F51) },
2007   { PREFIX_TABLE (PREFIX_0F52) },
2008   { PREFIX_TABLE (PREFIX_0F53) },
2009   { "andpX",            { XM, EXx } },
2010   { "andnpX",           { XM, EXx } },
2011   { "orpX",             { XM, EXx } },
2012   { "xorpX",            { XM, EXx } },
2013   /* 58 */
2014   { PREFIX_TABLE (PREFIX_0F58) },
2015   { PREFIX_TABLE (PREFIX_0F59) },
2016   { PREFIX_TABLE (PREFIX_0F5A) },
2017   { PREFIX_TABLE (PREFIX_0F5B) },
2018   { PREFIX_TABLE (PREFIX_0F5C) },
2019   { PREFIX_TABLE (PREFIX_0F5D) },
2020   { PREFIX_TABLE (PREFIX_0F5E) },
2021   { PREFIX_TABLE (PREFIX_0F5F) },
2022   /* 60 */
2023   { PREFIX_TABLE (PREFIX_0F60) },
2024   { PREFIX_TABLE (PREFIX_0F61) },
2025   { PREFIX_TABLE (PREFIX_0F62) },
2026   { "packsswb",         { MX, EM } },
2027   { "pcmpgtb",          { MX, EM } },
2028   { "pcmpgtw",          { MX, EM } },
2029   { "pcmpgtd",          { MX, EM } },
2030   { "packuswb",         { MX, EM } },
2031   /* 68 */
2032   { "punpckhbw",        { MX, EM } },
2033   { "punpckhwd",        { MX, EM } },
2034   { "punpckhdq",        { MX, EM } },
2035   { "packssdw",         { MX, EM } },
2036   { PREFIX_TABLE (PREFIX_0F6C) },
2037   { PREFIX_TABLE (PREFIX_0F6D) },
2038   { "movK",             { MX, Edq } },
2039   { PREFIX_TABLE (PREFIX_0F6F) },
2040   /* 70 */
2041   { PREFIX_TABLE (PREFIX_0F70) },
2042   { REG_TABLE (REG_0F71) },
2043   { REG_TABLE (REG_0F72) },
2044   { REG_TABLE (REG_0F73) },
2045   { "pcmpeqb",          { MX, EM } },
2046   { "pcmpeqw",          { MX, EM } },
2047   { "pcmpeqd",          { MX, EM } },
2048   { "emms",             { XX } },
2049   /* 78 */
2050   { PREFIX_TABLE (PREFIX_0F78) },
2051   { PREFIX_TABLE (PREFIX_0F79) },
2052   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2053   { Bad_Opcode },
2054   { PREFIX_TABLE (PREFIX_0F7C) },
2055   { PREFIX_TABLE (PREFIX_0F7D) },
2056   { PREFIX_TABLE (PREFIX_0F7E) },
2057   { PREFIX_TABLE (PREFIX_0F7F) },
2058   /* 80 */
2059   { "joH",              { Jv, XX, cond_jump_flag } },
2060   { "jnoH",             { Jv, XX, cond_jump_flag } },
2061   { "jbH",              { Jv, XX, cond_jump_flag } },
2062   { "jaeH",             { Jv, XX, cond_jump_flag } },
2063   { "jeH",              { Jv, XX, cond_jump_flag } },
2064   { "jneH",             { Jv, XX, cond_jump_flag } },
2065   { "jbeH",             { Jv, XX, cond_jump_flag } },
2066   { "jaH",              { Jv, XX, cond_jump_flag } },
2067   /* 88 */
2068   { "jsH",              { Jv, XX, cond_jump_flag } },
2069   { "jnsH",             { Jv, XX, cond_jump_flag } },
2070   { "jpH",              { Jv, XX, cond_jump_flag } },
2071   { "jnpH",             { Jv, XX, cond_jump_flag } },
2072   { "jlH",              { Jv, XX, cond_jump_flag } },
2073   { "jgeH",             { Jv, XX, cond_jump_flag } },
2074   { "jleH",             { Jv, XX, cond_jump_flag } },
2075   { "jgH",              { Jv, XX, cond_jump_flag } },
2076   /* 90 */
2077   { "seto",             { Eb } },
2078   { "setno",            { Eb } },
2079   { "setb",             { Eb } },
2080   { "setae",            { Eb } },
2081   { "sete",             { Eb } },
2082   { "setne",            { Eb } },
2083   { "setbe",            { Eb } },
2084   { "seta",             { Eb } },
2085   /* 98 */
2086   { "sets",             { Eb } },
2087   { "setns",            { Eb } },
2088   { "setp",             { Eb } },
2089   { "setnp",            { Eb } },
2090   { "setl",             { Eb } },
2091   { "setge",            { Eb } },
2092   { "setle",            { Eb } },
2093   { "setg",             { Eb } },
2094   /* a0 */
2095   { "pushT",            { fs } },
2096   { "popT",             { fs } },
2097   { "cpuid",            { XX } },
2098   { "btS",              { Ev, Gv } },
2099   { "shldS",            { Ev, Gv, Ib } },
2100   { "shldS",            { Ev, Gv, CL } },
2101   { REG_TABLE (REG_0FA6) },
2102   { REG_TABLE (REG_0FA7) },
2103   /* a8 */
2104   { "pushT",            { gs } },
2105   { "popT",             { gs } },
2106   { "rsm",              { XX } },
2107   { "btsS",             { Ev, Gv } },
2108   { "shrdS",            { Ev, Gv, Ib } },
2109   { "shrdS",            { Ev, Gv, CL } },
2110   { REG_TABLE (REG_0FAE) },
2111   { "imulS",            { Gv, Ev } },
2112   /* b0 */
2113   { "cmpxchgB",         { Eb, Gb } },
2114   { "cmpxchgS",         { Ev, Gv } },
2115   { MOD_TABLE (MOD_0FB2) },
2116   { "btrS",             { Ev, Gv } },
2117   { MOD_TABLE (MOD_0FB4) },
2118   { MOD_TABLE (MOD_0FB5) },
2119   { "movz{bR|x}",       { Gv, Eb } },
2120   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2121   /* b8 */
2122   { PREFIX_TABLE (PREFIX_0FB8) },
2123   { "ud2b",             { XX } },
2124   { REG_TABLE (REG_0FBA) },
2125   { "btcS",             { Ev, Gv } },
2126   { "bsfS",             { Gv, Ev } },
2127   { PREFIX_TABLE (PREFIX_0FBD) },
2128   { "movs{bR|x}",       { Gv, Eb } },
2129   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2130   /* c0 */
2131   { "xaddB",            { Eb, Gb } },
2132   { "xaddS",            { Ev, Gv } },
2133   { PREFIX_TABLE (PREFIX_0FC2) },
2134   { PREFIX_TABLE (PREFIX_0FC3) },
2135   { "pinsrw",           { MX, Edqw, Ib } },
2136   { "pextrw",           { Gdq, MS, Ib } },
2137   { "shufpX",           { XM, EXx, Ib } },
2138   { REG_TABLE (REG_0FC7) },
2139   /* c8 */
2140   { "bswap",            { RMeAX } },
2141   { "bswap",            { RMeCX } },
2142   { "bswap",            { RMeDX } },
2143   { "bswap",            { RMeBX } },
2144   { "bswap",            { RMeSP } },
2145   { "bswap",            { RMeBP } },
2146   { "bswap",            { RMeSI } },
2147   { "bswap",            { RMeDI } },
2148   /* d0 */
2149   { PREFIX_TABLE (PREFIX_0FD0) },
2150   { "psrlw",            { MX, EM } },
2151   { "psrld",            { MX, EM } },
2152   { "psrlq",            { MX, EM } },
2153   { "paddq",            { MX, EM } },
2154   { "pmullw",           { MX, EM } },
2155   { PREFIX_TABLE (PREFIX_0FD6) },
2156   { MOD_TABLE (MOD_0FD7) },
2157   /* d8 */
2158   { "psubusb",          { MX, EM } },
2159   { "psubusw",          { MX, EM } },
2160   { "pminub",           { MX, EM } },
2161   { "pand",             { MX, EM } },
2162   { "paddusb",          { MX, EM } },
2163   { "paddusw",          { MX, EM } },
2164   { "pmaxub",           { MX, EM } },
2165   { "pandn",            { MX, EM } },
2166   /* e0 */
2167   { "pavgb",            { MX, EM } },
2168   { "psraw",            { MX, EM } },
2169   { "psrad",            { MX, EM } },
2170   { "pavgw",            { MX, EM } },
2171   { "pmulhuw",          { MX, EM } },
2172   { "pmulhw",           { MX, EM } },
2173   { PREFIX_TABLE (PREFIX_0FE6) },
2174   { PREFIX_TABLE (PREFIX_0FE7) },
2175   /* e8 */
2176   { "psubsb",           { MX, EM } },
2177   { "psubsw",           { MX, EM } },
2178   { "pminsw",           { MX, EM } },
2179   { "por",              { MX, EM } },
2180   { "paddsb",           { MX, EM } },
2181   { "paddsw",           { MX, EM } },
2182   { "pmaxsw",           { MX, EM } },
2183   { "pxor",             { MX, EM } },
2184   /* f0 */
2185   { PREFIX_TABLE (PREFIX_0FF0) },
2186   { "psllw",            { MX, EM } },
2187   { "pslld",            { MX, EM } },
2188   { "psllq",            { MX, EM } },
2189   { "pmuludq",          { MX, EM } },
2190   { "pmaddwd",          { MX, EM } },
2191   { "psadbw",           { MX, EM } },
2192   { PREFIX_TABLE (PREFIX_0FF7) },
2193   /* f8 */
2194   { "psubb",            { MX, EM } },
2195   { "psubw",            { MX, EM } },
2196   { "psubd",            { MX, EM } },
2197   { "psubq",            { MX, EM } },
2198   { "paddb",            { MX, EM } },
2199   { "paddw",            { MX, EM } },
2200   { "paddd",            { MX, EM } },
2201   { Bad_Opcode },
2202 };
2203
2204 static const unsigned char onebyte_has_modrm[256] = {
2205   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2206   /*       -------------------------------        */
2207   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2208   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2209   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2210   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2211   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2212   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2213   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2214   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2215   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2216   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2217   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2218   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2219   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2220   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2221   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2222   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2223   /*       -------------------------------        */
2224   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2225 };
2226
2227 static const unsigned char twobyte_has_modrm[256] = {
2228   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2229   /*       -------------------------------        */
2230   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2231   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2232   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2233   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2234   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2235   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2236   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2237   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2238   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2239   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2240   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2241   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2242   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2243   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2244   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2245   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2246   /*       -------------------------------        */
2247   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2248 };
2249
2250 static char obuf[100];
2251 static char *obufp;
2252 static char *mnemonicendp;
2253 static char scratchbuf[100];
2254 static unsigned char *start_codep;
2255 static unsigned char *insn_codep;
2256 static unsigned char *codep;
2257 static int last_lock_prefix;
2258 static int last_repz_prefix;
2259 static int last_repnz_prefix;
2260 static int last_data_prefix;
2261 static int last_addr_prefix;
2262 static int last_rex_prefix;
2263 static int last_seg_prefix;
2264 #define MAX_CODE_LENGTH 15
2265 /* We can up to 14 prefixes since the maximum instruction length is
2266    15bytes.  */
2267 static int all_prefixes[MAX_CODE_LENGTH - 1];
2268 static disassemble_info *the_info;
2269 static struct
2270   {
2271     int mod;
2272     int reg;
2273     int rm;
2274   }
2275 modrm;
2276 static unsigned char need_modrm;
2277 static struct
2278   {
2279     int register_specifier;
2280     int length;
2281     int prefix;
2282     int w;
2283   }
2284 vex;
2285 static unsigned char need_vex;
2286 static unsigned char need_vex_reg;
2287 static unsigned char vex_w_done;
2288
2289 struct op
2290   {
2291     const char *name;
2292     unsigned int len;
2293   };
2294
2295 /* If we are accessing mod/rm/reg without need_modrm set, then the
2296    values are stale.  Hitting this abort likely indicates that you
2297    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2298 #define MODRM_CHECK  if (!need_modrm) abort ()
2299
2300 static const char **names64;
2301 static const char **names32;
2302 static const char **names16;
2303 static const char **names8;
2304 static const char **names8rex;
2305 static const char **names_seg;
2306 static const char *index64;
2307 static const char *index32;
2308 static const char **index16;
2309
2310 static const char *intel_names64[] = {
2311   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2312   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2313 };
2314 static const char *intel_names32[] = {
2315   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2316   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2317 };
2318 static const char *intel_names16[] = {
2319   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2320   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2321 };
2322 static const char *intel_names8[] = {
2323   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2324 };
2325 static const char *intel_names8rex[] = {
2326   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2327   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2328 };
2329 static const char *intel_names_seg[] = {
2330   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2331 };
2332 static const char *intel_index64 = "riz";
2333 static const char *intel_index32 = "eiz";
2334 static const char *intel_index16[] = {
2335   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2336 };
2337
2338 static const char *att_names64[] = {
2339   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2340   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2341 };
2342 static const char *att_names32[] = {
2343   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2344   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2345 };
2346 static const char *att_names16[] = {
2347   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2348   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2349 };
2350 static const char *att_names8[] = {
2351   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2352 };
2353 static const char *att_names8rex[] = {
2354   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2355   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2356 };
2357 static const char *att_names_seg[] = {
2358   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2359 };
2360 static const char *att_index64 = "%riz";
2361 static const char *att_index32 = "%eiz";
2362 static const char *att_index16[] = {
2363   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2364 };
2365
2366 static const char **names_mm;
2367 static const char *intel_names_mm[] = {
2368   "mm0", "mm1", "mm2", "mm3",
2369   "mm4", "mm5", "mm6", "mm7"
2370 };
2371 static const char *att_names_mm[] = {
2372   "%mm0", "%mm1", "%mm2", "%mm3",
2373   "%mm4", "%mm5", "%mm6", "%mm7"
2374 };
2375
2376 static const char **names_xmm;
2377 static const char *intel_names_xmm[] = {
2378   "xmm0", "xmm1", "xmm2", "xmm3",
2379   "xmm4", "xmm5", "xmm6", "xmm7",
2380   "xmm8", "xmm9", "xmm10", "xmm11",
2381   "xmm12", "xmm13", "xmm14", "xmm15"
2382 };
2383 static const char *att_names_xmm[] = {
2384   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2385   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2386   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2387   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2388 };
2389
2390 static const char **names_ymm;
2391 static const char *intel_names_ymm[] = {
2392   "ymm0", "ymm1", "ymm2", "ymm3",
2393   "ymm4", "ymm5", "ymm6", "ymm7",
2394   "ymm8", "ymm9", "ymm10", "ymm11",
2395   "ymm12", "ymm13", "ymm14", "ymm15"
2396 };
2397 static const char *att_names_ymm[] = {
2398   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2399   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2400   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2401   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2402 };
2403
2404 static const struct dis386 reg_table[][8] = {
2405   /* REG_80 */
2406   {
2407     { "addA",   { Eb, Ib } },
2408     { "orA",    { Eb, Ib } },
2409     { "adcA",   { Eb, Ib } },
2410     { "sbbA",   { Eb, Ib } },
2411     { "andA",   { Eb, Ib } },
2412     { "subA",   { Eb, Ib } },
2413     { "xorA",   { Eb, Ib } },
2414     { "cmpA",   { Eb, Ib } },
2415   },
2416   /* REG_81 */
2417   {
2418     { "addQ",   { Ev, Iv } },
2419     { "orQ",    { Ev, Iv } },
2420     { "adcQ",   { Ev, Iv } },
2421     { "sbbQ",   { Ev, Iv } },
2422     { "andQ",   { Ev, Iv } },
2423     { "subQ",   { Ev, Iv } },
2424     { "xorQ",   { Ev, Iv } },
2425     { "cmpQ",   { Ev, Iv } },
2426   },
2427   /* REG_82 */
2428   {
2429     { "addQ",   { Ev, sIb } },
2430     { "orQ",    { Ev, sIb } },
2431     { "adcQ",   { Ev, sIb } },
2432     { "sbbQ",   { Ev, sIb } },
2433     { "andQ",   { Ev, sIb } },
2434     { "subQ",   { Ev, sIb } },
2435     { "xorQ",   { Ev, sIb } },
2436     { "cmpQ",   { Ev, sIb } },
2437   },
2438   /* REG_8F */
2439   {
2440     { "popU",   { stackEv } },
2441     { XOP_8F_TABLE (XOP_09) },
2442     { Bad_Opcode },
2443     { Bad_Opcode },
2444     { Bad_Opcode },
2445     { XOP_8F_TABLE (XOP_09) },
2446   },
2447   /* REG_C0 */
2448   {
2449     { "rolA",   { Eb, Ib } },
2450     { "rorA",   { Eb, Ib } },
2451     { "rclA",   { Eb, Ib } },
2452     { "rcrA",   { Eb, Ib } },
2453     { "shlA",   { Eb, Ib } },
2454     { "shrA",   { Eb, Ib } },
2455     { Bad_Opcode },
2456     { "sarA",   { Eb, Ib } },
2457   },
2458   /* REG_C1 */
2459   {
2460     { "rolQ",   { Ev, Ib } },
2461     { "rorQ",   { Ev, Ib } },
2462     { "rclQ",   { Ev, Ib } },
2463     { "rcrQ",   { Ev, Ib } },
2464     { "shlQ",   { Ev, Ib } },
2465     { "shrQ",   { Ev, Ib } },
2466     { Bad_Opcode },
2467     { "sarQ",   { Ev, Ib } },
2468   },
2469   /* REG_C6 */
2470   {
2471     { "movA",   { Eb, Ib } },
2472   },
2473   /* REG_C7 */
2474   {
2475     { "movQ",   { Ev, Iv } },
2476   },
2477   /* REG_D0 */
2478   {
2479     { "rolA",   { Eb, I1 } },
2480     { "rorA",   { Eb, I1 } },
2481     { "rclA",   { Eb, I1 } },
2482     { "rcrA",   { Eb, I1 } },
2483     { "shlA",   { Eb, I1 } },
2484     { "shrA",   { Eb, I1 } },
2485     { Bad_Opcode },
2486     { "sarA",   { Eb, I1 } },
2487   },
2488   /* REG_D1 */
2489   {
2490     { "rolQ",   { Ev, I1 } },
2491     { "rorQ",   { Ev, I1 } },
2492     { "rclQ",   { Ev, I1 } },
2493     { "rcrQ",   { Ev, I1 } },
2494     { "shlQ",   { Ev, I1 } },
2495     { "shrQ",   { Ev, I1 } },
2496     { Bad_Opcode },
2497     { "sarQ",   { Ev, I1 } },
2498   },
2499   /* REG_D2 */
2500   {
2501     { "rolA",   { Eb, CL } },
2502     { "rorA",   { Eb, CL } },
2503     { "rclA",   { Eb, CL } },
2504     { "rcrA",   { Eb, CL } },
2505     { "shlA",   { Eb, CL } },
2506     { "shrA",   { Eb, CL } },
2507     { Bad_Opcode },
2508     { "sarA",   { Eb, CL } },
2509   },
2510   /* REG_D3 */
2511   {
2512     { "rolQ",   { Ev, CL } },
2513     { "rorQ",   { Ev, CL } },
2514     { "rclQ",   { Ev, CL } },
2515     { "rcrQ",   { Ev, CL } },
2516     { "shlQ",   { Ev, CL } },
2517     { "shrQ",   { Ev, CL } },
2518     { Bad_Opcode },
2519     { "sarQ",   { Ev, CL } },
2520   },
2521   /* REG_F6 */
2522   {
2523     { "testA",  { Eb, Ib } },
2524     { Bad_Opcode },
2525     { "notA",   { Eb } },
2526     { "negA",   { Eb } },
2527     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2528     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2529     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2530     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2531   },
2532   /* REG_F7 */
2533   {
2534     { "testQ",  { Ev, Iv } },
2535     { Bad_Opcode },
2536     { "notQ",   { Ev } },
2537     { "negQ",   { Ev } },
2538     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2539     { "imulQ",  { Ev } },
2540     { "divQ",   { Ev } },
2541     { "idivQ",  { Ev } },
2542   },
2543   /* REG_FE */
2544   {
2545     { "incA",   { Eb } },
2546     { "decA",   { Eb } },
2547   },
2548   /* REG_FF */
2549   {
2550     { "incQ",   { Ev } },
2551     { "decQ",   { Ev } },
2552     { "callT",  { indirEv } },
2553     { "JcallT", { indirEp } },
2554     { "jmpT",   { indirEv } },
2555     { "JjmpT",  { indirEp } },
2556     { "pushU",  { stackEv } },
2557     { Bad_Opcode },
2558   },
2559   /* REG_0F00 */
2560   {
2561     { "sldtD",  { Sv } },
2562     { "strD",   { Sv } },
2563     { "lldt",   { Ew } },
2564     { "ltr",    { Ew } },
2565     { "verr",   { Ew } },
2566     { "verw",   { Ew } },
2567     { Bad_Opcode },
2568     { Bad_Opcode },
2569   },
2570   /* REG_0F01 */
2571   {
2572     { MOD_TABLE (MOD_0F01_REG_0) },
2573     { MOD_TABLE (MOD_0F01_REG_1) },
2574     { MOD_TABLE (MOD_0F01_REG_2) },
2575     { MOD_TABLE (MOD_0F01_REG_3) },
2576     { "smswD",  { Sv } },
2577     { Bad_Opcode },
2578     { "lmsw",   { Ew } },
2579     { MOD_TABLE (MOD_0F01_REG_7) },
2580   },
2581   /* REG_0F0D */
2582   {
2583     { "prefetch",       { Eb } },
2584     { "prefetchw",      { Eb } },
2585   },
2586   /* REG_0F18 */
2587   {
2588     { MOD_TABLE (MOD_0F18_REG_0) },
2589     { MOD_TABLE (MOD_0F18_REG_1) },
2590     { MOD_TABLE (MOD_0F18_REG_2) },
2591     { MOD_TABLE (MOD_0F18_REG_3) },
2592   },
2593   /* REG_0F71 */
2594   {
2595     { Bad_Opcode },
2596     { Bad_Opcode },
2597     { MOD_TABLE (MOD_0F71_REG_2) },
2598     { Bad_Opcode },
2599     { MOD_TABLE (MOD_0F71_REG_4) },
2600     { Bad_Opcode },
2601     { MOD_TABLE (MOD_0F71_REG_6) },
2602   },
2603   /* REG_0F72 */
2604   {
2605     { Bad_Opcode },
2606     { Bad_Opcode },
2607     { MOD_TABLE (MOD_0F72_REG_2) },
2608     { Bad_Opcode },
2609     { MOD_TABLE (MOD_0F72_REG_4) },
2610     { Bad_Opcode },
2611     { MOD_TABLE (MOD_0F72_REG_6) },
2612   },
2613   /* REG_0F73 */
2614   {
2615     { Bad_Opcode },
2616     { Bad_Opcode },
2617     { MOD_TABLE (MOD_0F73_REG_2) },
2618     { MOD_TABLE (MOD_0F73_REG_3) },
2619     { Bad_Opcode },
2620     { Bad_Opcode },
2621     { MOD_TABLE (MOD_0F73_REG_6) },
2622     { MOD_TABLE (MOD_0F73_REG_7) },
2623   },
2624   /* REG_0FA6 */
2625   {
2626     { "montmul",        { { OP_0f07, 0 } } },
2627     { "xsha1",          { { OP_0f07, 0 } } },
2628     { "xsha256",        { { OP_0f07, 0 } } },
2629   },
2630   /* REG_0FA7 */
2631   {
2632     { "xstore-rng",     { { OP_0f07, 0 } } },
2633     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2634     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2635     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2636     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2637     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2638   },
2639   /* REG_0FAE */
2640   {
2641     { MOD_TABLE (MOD_0FAE_REG_0) },
2642     { MOD_TABLE (MOD_0FAE_REG_1) },
2643     { MOD_TABLE (MOD_0FAE_REG_2) },
2644     { MOD_TABLE (MOD_0FAE_REG_3) },
2645     { MOD_TABLE (MOD_0FAE_REG_4) },
2646     { MOD_TABLE (MOD_0FAE_REG_5) },
2647     { MOD_TABLE (MOD_0FAE_REG_6) },
2648     { MOD_TABLE (MOD_0FAE_REG_7) },
2649   },
2650   /* REG_0FBA */
2651   {
2652     { Bad_Opcode },
2653     { Bad_Opcode },
2654     { Bad_Opcode },
2655     { Bad_Opcode },
2656     { "btQ",    { Ev, Ib } },
2657     { "btsQ",   { Ev, Ib } },
2658     { "btrQ",   { Ev, Ib } },
2659     { "btcQ",   { Ev, Ib } },
2660   },
2661   /* REG_0FC7 */
2662   {
2663     { Bad_Opcode },
2664     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2665     { Bad_Opcode },
2666     { Bad_Opcode },
2667     { Bad_Opcode },
2668     { Bad_Opcode },
2669     { MOD_TABLE (MOD_0FC7_REG_6) },
2670     { MOD_TABLE (MOD_0FC7_REG_7) },
2671   },
2672   /* REG_VEX_71 */
2673   {
2674     { Bad_Opcode },
2675     { Bad_Opcode },
2676     { MOD_TABLE (MOD_VEX_71_REG_2) },
2677     { Bad_Opcode },
2678     { MOD_TABLE (MOD_VEX_71_REG_4) },
2679     { Bad_Opcode },
2680     { MOD_TABLE (MOD_VEX_71_REG_6) },
2681   },
2682   /* REG_VEX_72 */
2683   {
2684     { Bad_Opcode },
2685     { Bad_Opcode },
2686     { MOD_TABLE (MOD_VEX_72_REG_2) },
2687     { Bad_Opcode },
2688     { MOD_TABLE (MOD_VEX_72_REG_4) },
2689     { Bad_Opcode },
2690     { MOD_TABLE (MOD_VEX_72_REG_6) },
2691   },
2692   /* REG_VEX_73 */
2693   {
2694     { Bad_Opcode },
2695     { Bad_Opcode },
2696     { MOD_TABLE (MOD_VEX_73_REG_2) },
2697     { MOD_TABLE (MOD_VEX_73_REG_3) },
2698     { Bad_Opcode },
2699     { Bad_Opcode },
2700     { MOD_TABLE (MOD_VEX_73_REG_6) },
2701     { MOD_TABLE (MOD_VEX_73_REG_7) },
2702   },
2703   /* REG_VEX_AE */
2704   {
2705     { Bad_Opcode },
2706     { Bad_Opcode },
2707     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2708     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2709   },
2710   /* REG_XOP_LWPCB */
2711   {
2712     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2713     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2714   },
2715   /* REG_XOP_LWP */
2716   {
2717     { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2718     { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2719   },
2720 };
2721
2722 static const struct dis386 prefix_table[][4] = {
2723   /* PREFIX_90 */
2724   {
2725     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2726     { "pause", { XX } },
2727     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2728   },
2729
2730   /* PREFIX_0F10 */
2731   {
2732     { "movups", { XM, EXx } },
2733     { "movss",  { XM, EXd } },
2734     { "movupd", { XM, EXx } },
2735     { "movsd",  { XM, EXq } },
2736   },
2737
2738   /* PREFIX_0F11 */
2739   {
2740     { "movups", { EXxS, XM } },
2741     { "movss",  { EXdS, XM } },
2742     { "movupd", { EXxS, XM } },
2743     { "movsd",  { EXqS, XM } },
2744   },
2745
2746   /* PREFIX_0F12 */
2747   {
2748     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2749     { "movsldup", { XM, EXx } },
2750     { "movlpd", { XM, EXq } },
2751     { "movddup", { XM, EXq } },
2752   },
2753
2754   /* PREFIX_0F16 */
2755   {
2756     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2757     { "movshdup", { XM, EXx } },
2758     { "movhpd", { XM, EXq } },
2759   },
2760
2761   /* PREFIX_0F2A */
2762   {
2763     { "cvtpi2ps", { XM, EMCq } },
2764     { "cvtsi2ss%LQ", { XM, Ev } },
2765     { "cvtpi2pd", { XM, EMCq } },
2766     { "cvtsi2sd%LQ", { XM, Ev } },
2767   },
2768
2769   /* PREFIX_0F2B */
2770   {
2771     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2772     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2773     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2774     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2775   },
2776
2777   /* PREFIX_0F2C */
2778   {
2779     { "cvttps2pi", { MXC, EXq } },
2780     { "cvttss2siY", { Gv, EXd } },
2781     { "cvttpd2pi", { MXC, EXx } },
2782     { "cvttsd2siY", { Gv, EXq } },
2783   },
2784
2785   /* PREFIX_0F2D */
2786   {
2787     { "cvtps2pi", { MXC, EXq } },
2788     { "cvtss2siY", { Gv, EXd } },
2789     { "cvtpd2pi", { MXC, EXx } },
2790     { "cvtsd2siY", { Gv, EXq } },
2791   },
2792
2793   /* PREFIX_0F2E */
2794   {
2795     { "ucomiss",{ XM, EXd } },
2796     { Bad_Opcode },
2797     { "ucomisd",{ XM, EXq } },
2798   },
2799
2800   /* PREFIX_0F2F */
2801   {
2802     { "comiss", { XM, EXd } },
2803     { Bad_Opcode },
2804     { "comisd", { XM, EXq } },
2805   },
2806
2807   /* PREFIX_0F51 */
2808   {
2809     { "sqrtps", { XM, EXx } },
2810     { "sqrtss", { XM, EXd } },
2811     { "sqrtpd", { XM, EXx } },
2812     { "sqrtsd", { XM, EXq } },
2813   },
2814
2815   /* PREFIX_0F52 */
2816   {
2817     { "rsqrtps",{ XM, EXx } },
2818     { "rsqrtss",{ XM, EXd } },
2819   },
2820
2821   /* PREFIX_0F53 */
2822   {
2823     { "rcpps",  { XM, EXx } },
2824     { "rcpss",  { XM, EXd } },
2825   },
2826
2827   /* PREFIX_0F58 */
2828   {
2829     { "addps", { XM, EXx } },
2830     { "addss", { XM, EXd } },
2831     { "addpd", { XM, EXx } },
2832     { "addsd", { XM, EXq } },
2833   },
2834
2835   /* PREFIX_0F59 */
2836   {
2837     { "mulps",  { XM, EXx } },
2838     { "mulss",  { XM, EXd } },
2839     { "mulpd",  { XM, EXx } },
2840     { "mulsd",  { XM, EXq } },
2841   },
2842
2843   /* PREFIX_0F5A */
2844   {
2845     { "cvtps2pd", { XM, EXq } },
2846     { "cvtss2sd", { XM, EXd } },
2847     { "cvtpd2ps", { XM, EXx } },
2848     { "cvtsd2ss", { XM, EXq } },
2849   },
2850
2851   /* PREFIX_0F5B */
2852   {
2853     { "cvtdq2ps", { XM, EXx } },
2854     { "cvttps2dq", { XM, EXx } },
2855     { "cvtps2dq", { XM, EXx } },
2856   },
2857
2858   /* PREFIX_0F5C */
2859   {
2860     { "subps",  { XM, EXx } },
2861     { "subss",  { XM, EXd } },
2862     { "subpd",  { XM, EXx } },
2863     { "subsd",  { XM, EXq } },
2864   },
2865
2866   /* PREFIX_0F5D */
2867   {
2868     { "minps",  { XM, EXx } },
2869     { "minss",  { XM, EXd } },
2870     { "minpd",  { XM, EXx } },
2871     { "minsd",  { XM, EXq } },
2872   },
2873
2874   /* PREFIX_0F5E */
2875   {
2876     { "divps",  { XM, EXx } },
2877     { "divss",  { XM, EXd } },
2878     { "divpd",  { XM, EXx } },
2879     { "divsd",  { XM, EXq } },
2880   },
2881
2882   /* PREFIX_0F5F */
2883   {
2884     { "maxps",  { XM, EXx } },
2885     { "maxss",  { XM, EXd } },
2886     { "maxpd",  { XM, EXx } },
2887     { "maxsd",  { XM, EXq } },
2888   },
2889
2890   /* PREFIX_0F60 */
2891   {
2892     { "punpcklbw",{ MX, EMd } },
2893     { Bad_Opcode },
2894     { "punpcklbw",{ MX, EMx } },
2895   },
2896
2897   /* PREFIX_0F61 */
2898   {
2899     { "punpcklwd",{ MX, EMd } },
2900     { Bad_Opcode },
2901     { "punpcklwd",{ MX, EMx } },
2902   },
2903
2904   /* PREFIX_0F62 */
2905   {
2906     { "punpckldq",{ MX, EMd } },
2907     { Bad_Opcode },
2908     { "punpckldq",{ MX, EMx } },
2909   },
2910
2911   /* PREFIX_0F6C */
2912   {
2913     { Bad_Opcode },
2914     { Bad_Opcode },
2915     { "punpcklqdq", { XM, EXx } },
2916   },
2917
2918   /* PREFIX_0F6D */
2919   {
2920     { Bad_Opcode },
2921     { Bad_Opcode },
2922     { "punpckhqdq", { XM, EXx } },
2923   },
2924
2925   /* PREFIX_0F6F */
2926   {
2927     { "movq",   { MX, EM } },
2928     { "movdqu", { XM, EXx } },
2929     { "movdqa", { XM, EXx } },
2930   },
2931
2932   /* PREFIX_0F70 */
2933   {
2934     { "pshufw", { MX, EM, Ib } },
2935     { "pshufhw",{ XM, EXx, Ib } },
2936     { "pshufd", { XM, EXx, Ib } },
2937     { "pshuflw",{ XM, EXx, Ib } },
2938   },
2939
2940   /* PREFIX_0F73_REG_3 */
2941   {
2942     { Bad_Opcode },
2943     { Bad_Opcode },
2944     { "psrldq", { XS, Ib } },
2945   },
2946
2947   /* PREFIX_0F73_REG_7 */
2948   {
2949     { Bad_Opcode },
2950     { Bad_Opcode },
2951     { "pslldq", { XS, Ib } },
2952   },
2953
2954   /* PREFIX_0F78 */
2955   {
2956     {"vmread",  { Em, Gm } },
2957     { Bad_Opcode },
2958     {"extrq",   { XS, Ib, Ib } },
2959     {"insertq", { XM, XS, Ib, Ib } },
2960   },
2961
2962   /* PREFIX_0F79 */
2963   {
2964     {"vmwrite", { Gm, Em } },
2965     { Bad_Opcode },
2966     {"extrq",   { XM, XS } },
2967     {"insertq", { XM, XS } },
2968   },
2969
2970   /* PREFIX_0F7C */
2971   {
2972     { Bad_Opcode },
2973     { Bad_Opcode },
2974     { "haddpd", { XM, EXx } },
2975     { "haddps", { XM, EXx } },
2976   },
2977
2978   /* PREFIX_0F7D */
2979   {
2980     { Bad_Opcode },
2981     { Bad_Opcode },
2982     { "hsubpd", { XM, EXx } },
2983     { "hsubps", { XM, EXx } },
2984   },
2985
2986   /* PREFIX_0F7E */
2987   {
2988     { "movK",   { Edq, MX } },
2989     { "movq",   { XM, EXq } },
2990     { "movK",   { Edq, XM } },
2991   },
2992
2993   /* PREFIX_0F7F */
2994   {
2995     { "movq",   { EMS, MX } },
2996     { "movdqu", { EXxS, XM } },
2997     { "movdqa", { EXxS, XM } },
2998   },
2999
3000   /* PREFIX_0FB8 */
3001   {
3002     { Bad_Opcode },
3003     { "popcntS", { Gv, Ev } },
3004   },
3005
3006   /* PREFIX_0FBD */
3007   {
3008     { "bsrS",   { Gv, Ev } },
3009     { "lzcntS", { Gv, Ev } },
3010     { "bsrS",   { Gv, Ev } },
3011   },
3012
3013   /* PREFIX_0FC2 */
3014   {
3015     { "cmpps",  { XM, EXx, CMP } },
3016     { "cmpss",  { XM, EXd, CMP } },
3017     { "cmppd",  { XM, EXx, CMP } },
3018     { "cmpsd",  { XM, EXq, CMP } },
3019   },
3020
3021   /* PREFIX_0FC3 */
3022   {
3023     { "movntiS", { Ma, Gv } },
3024   },
3025
3026   /* PREFIX_0FC7_REG_6 */
3027   {
3028     { "vmptrld",{ Mq } },
3029     { "vmxon",  { Mq } },
3030     { "vmclear",{ Mq } },
3031   },
3032
3033   /* PREFIX_0FD0 */
3034   {
3035     { Bad_Opcode },
3036     { Bad_Opcode },
3037     { "addsubpd", { XM, EXx } },
3038     { "addsubps", { XM, EXx } },
3039   },
3040
3041   /* PREFIX_0FD6 */
3042   {
3043     { Bad_Opcode },
3044     { "movq2dq",{ XM, MS } },
3045     { "movq",   { EXqS, XM } },
3046     { "movdq2q",{ MX, XS } },
3047   },
3048
3049   /* PREFIX_0FE6 */
3050   {
3051     { Bad_Opcode },
3052     { "cvtdq2pd", { XM, EXq } },
3053     { "cvttpd2dq", { XM, EXx } },
3054     { "cvtpd2dq", { XM, EXx } },
3055   },
3056
3057   /* PREFIX_0FE7 */
3058   {
3059     { "movntq", { Mq, MX } },
3060     { Bad_Opcode },
3061     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3062   },
3063
3064   /* PREFIX_0FF0 */
3065   {
3066     { Bad_Opcode },
3067     { Bad_Opcode },
3068     { Bad_Opcode },
3069     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3070   },
3071
3072   /* PREFIX_0FF7 */
3073   {
3074     { "maskmovq", { MX, MS } },
3075     { Bad_Opcode },
3076     { "maskmovdqu", { XM, XS } },
3077   },
3078
3079   /* PREFIX_0F3810 */
3080   {
3081     { Bad_Opcode },
3082     { Bad_Opcode },
3083     { "pblendvb", { XM, EXx, XMM0 } },
3084   },
3085
3086   /* PREFIX_0F3814 */
3087   {
3088     { Bad_Opcode },
3089     { Bad_Opcode },
3090     { "blendvps", { XM, EXx, XMM0 } },
3091   },
3092
3093   /* PREFIX_0F3815 */
3094   {
3095     { Bad_Opcode },
3096     { Bad_Opcode },
3097     { "blendvpd", { XM, EXx, XMM0 } },
3098   },
3099
3100   /* PREFIX_0F3817 */
3101   {
3102     { Bad_Opcode },
3103     { Bad_Opcode },
3104     { "ptest",  { XM, EXx } },
3105   },
3106
3107   /* PREFIX_0F3820 */
3108   {
3109     { Bad_Opcode },
3110     { Bad_Opcode },
3111     { "pmovsxbw", { XM, EXq } },
3112   },
3113
3114   /* PREFIX_0F3821 */
3115   {
3116     { Bad_Opcode },
3117     { Bad_Opcode },
3118     { "pmovsxbd", { XM, EXd } },
3119   },
3120
3121   /* PREFIX_0F3822 */
3122   {
3123     { Bad_Opcode },
3124     { Bad_Opcode },
3125     { "pmovsxbq", { XM, EXw } },
3126   },
3127
3128   /* PREFIX_0F3823 */
3129   {
3130     { Bad_Opcode },
3131     { Bad_Opcode },
3132     { "pmovsxwd", { XM, EXq } },
3133   },
3134
3135   /* PREFIX_0F3824 */
3136   {
3137     { Bad_Opcode },
3138     { Bad_Opcode },
3139     { "pmovsxwq", { XM, EXd } },
3140   },
3141
3142   /* PREFIX_0F3825 */
3143   {
3144     { Bad_Opcode },
3145     { Bad_Opcode },
3146     { "pmovsxdq", { XM, EXq } },
3147   },
3148
3149   /* PREFIX_0F3828 */
3150   {
3151     { Bad_Opcode },
3152     { Bad_Opcode },
3153     { "pmuldq", { XM, EXx } },
3154   },
3155
3156   /* PREFIX_0F3829 */
3157   {
3158     { Bad_Opcode },
3159     { Bad_Opcode },
3160     { "pcmpeqq", { XM, EXx } },
3161   },
3162
3163   /* PREFIX_0F382A */
3164   {
3165     { Bad_Opcode },
3166     { Bad_Opcode },
3167     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3168   },
3169
3170   /* PREFIX_0F382B */
3171   {
3172     { Bad_Opcode },
3173     { Bad_Opcode },
3174     { "packusdw", { XM, EXx } },
3175   },
3176
3177   /* PREFIX_0F3830 */
3178   {
3179     { Bad_Opcode },
3180     { Bad_Opcode },
3181     { "pmovzxbw", { XM, EXq } },
3182   },
3183
3184   /* PREFIX_0F3831 */
3185   {
3186     { Bad_Opcode },
3187     { Bad_Opcode },
3188     { "pmovzxbd", { XM, EXd } },
3189   },
3190
3191   /* PREFIX_0F3832 */
3192   {
3193     { Bad_Opcode },
3194     { Bad_Opcode },
3195     { "pmovzxbq", { XM, EXw } },
3196   },
3197
3198   /* PREFIX_0F3833 */
3199   {
3200     { Bad_Opcode },
3201     { Bad_Opcode },
3202     { "pmovzxwd", { XM, EXq } },
3203   },
3204
3205   /* PREFIX_0F3834 */
3206   {
3207     { Bad_Opcode },
3208     { Bad_Opcode },
3209     { "pmovzxwq", { XM, EXd } },
3210   },
3211
3212   /* PREFIX_0F3835 */
3213   {
3214     { Bad_Opcode },
3215     { Bad_Opcode },
3216     { "pmovzxdq", { XM, EXq } },
3217   },
3218
3219   /* PREFIX_0F3837 */
3220   {
3221     { Bad_Opcode },
3222     { Bad_Opcode },
3223     { "pcmpgtq", { XM, EXx } },
3224   },
3225
3226   /* PREFIX_0F3838 */
3227   {
3228     { Bad_Opcode },
3229     { Bad_Opcode },
3230     { "pminsb", { XM, EXx } },
3231   },
3232
3233   /* PREFIX_0F3839 */
3234   {
3235     { Bad_Opcode },
3236     { Bad_Opcode },
3237     { "pminsd", { XM, EXx } },
3238   },
3239
3240   /* PREFIX_0F383A */
3241   {
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { "pminuw", { XM, EXx } },
3245   },
3246
3247   /* PREFIX_0F383B */
3248   {
3249     { Bad_Opcode },
3250     { Bad_Opcode },
3251     { "pminud", { XM, EXx } },
3252   },
3253
3254   /* PREFIX_0F383C */
3255   {
3256     { Bad_Opcode },
3257     { Bad_Opcode },
3258     { "pmaxsb", { XM, EXx } },
3259   },
3260
3261   /* PREFIX_0F383D */
3262   {
3263     { Bad_Opcode },
3264     { Bad_Opcode },
3265     { "pmaxsd", { XM, EXx } },
3266   },
3267
3268   /* PREFIX_0F383E */
3269   {
3270     { Bad_Opcode },
3271     { Bad_Opcode },
3272     { "pmaxuw", { XM, EXx } },
3273   },
3274
3275   /* PREFIX_0F383F */
3276   {
3277     { Bad_Opcode },
3278     { Bad_Opcode },
3279     { "pmaxud", { XM, EXx } },
3280   },
3281
3282   /* PREFIX_0F3840 */
3283   {
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { "pmulld", { XM, EXx } },
3287   },
3288
3289   /* PREFIX_0F3841 */
3290   {
3291     { Bad_Opcode },
3292     { Bad_Opcode },
3293     { "phminposuw", { XM, EXx } },
3294   },
3295
3296   /* PREFIX_0F3880 */
3297   {
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { "invept", { Gm, Mo } },
3301   },
3302
3303   /* PREFIX_0F3881 */
3304   {
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { "invvpid", { Gm, Mo } },
3308   },
3309
3310   /* PREFIX_0F38DB */
3311   {
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { "aesimc", { XM, EXx } },
3315   },
3316
3317   /* PREFIX_0F38DC */
3318   {
3319     { Bad_Opcode },
3320     { Bad_Opcode },
3321     { "aesenc", { XM, EXx } },
3322   },
3323
3324   /* PREFIX_0F38DD */
3325   {
3326     { Bad_Opcode },
3327     { Bad_Opcode },
3328     { "aesenclast", { XM, EXx } },
3329   },
3330
3331   /* PREFIX_0F38DE */
3332   {
3333     { Bad_Opcode },
3334     { Bad_Opcode },
3335     { "aesdec", { XM, EXx } },
3336   },
3337
3338   /* PREFIX_0F38DF */
3339   {
3340     { Bad_Opcode },
3341     { Bad_Opcode },
3342     { "aesdeclast", { XM, EXx } },
3343   },
3344
3345   /* PREFIX_0F38F0 */
3346   {
3347     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3348     { Bad_Opcode },
3349     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3350     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3351   },
3352
3353   /* PREFIX_0F38F1 */
3354   {
3355     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3356     { Bad_Opcode },
3357     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3358     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3359   },
3360
3361   /* PREFIX_0F3A08 */
3362   {
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { "roundps", { XM, EXx, Ib } },
3366   },
3367
3368   /* PREFIX_0F3A09 */
3369   {
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { "roundpd", { XM, EXx, Ib } },
3373   },
3374
3375   /* PREFIX_0F3A0A */
3376   {
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { "roundss", { XM, EXd, Ib } },
3380   },
3381
3382   /* PREFIX_0F3A0B */
3383   {
3384     { Bad_Opcode },
3385     { Bad_Opcode },
3386     { "roundsd", { XM, EXq, Ib } },
3387   },
3388
3389   /* PREFIX_0F3A0C */
3390   {
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393     { "blendps", { XM, EXx, Ib } },
3394   },
3395
3396   /* PREFIX_0F3A0D */
3397   {
3398     { Bad_Opcode },
3399     { Bad_Opcode },
3400     { "blendpd", { XM, EXx, Ib } },
3401   },
3402
3403   /* PREFIX_0F3A0E */
3404   {
3405     { Bad_Opcode },
3406     { Bad_Opcode },
3407     { "pblendw", { XM, EXx, Ib } },
3408   },
3409
3410   /* PREFIX_0F3A14 */
3411   {
3412     { Bad_Opcode },
3413     { Bad_Opcode },
3414     { "pextrb", { Edqb, XM, Ib } },
3415   },
3416
3417   /* PREFIX_0F3A15 */
3418   {
3419     { Bad_Opcode },
3420     { Bad_Opcode },
3421     { "pextrw", { Edqw, XM, Ib } },
3422   },
3423
3424   /* PREFIX_0F3A16 */
3425   {
3426     { Bad_Opcode },
3427     { Bad_Opcode },
3428     { "pextrK", { Edq, XM, Ib } },
3429   },
3430
3431   /* PREFIX_0F3A17 */
3432   {
3433     { Bad_Opcode },
3434     { Bad_Opcode },
3435     { "extractps", { Edqd, XM, Ib } },
3436   },
3437
3438   /* PREFIX_0F3A20 */
3439   {
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { "pinsrb", { XM, Edqb, Ib } },
3443   },
3444
3445   /* PREFIX_0F3A21 */
3446   {
3447     { Bad_Opcode },
3448     { Bad_Opcode },
3449     { "insertps", { XM, EXd, Ib } },
3450   },
3451
3452   /* PREFIX_0F3A22 */
3453   {
3454     { Bad_Opcode },
3455     { Bad_Opcode },
3456     { "pinsrK", { XM, Edq, Ib } },
3457   },
3458
3459   /* PREFIX_0F3A40 */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { "dpps",   { XM, EXx, Ib } },
3464   },
3465
3466   /* PREFIX_0F3A41 */
3467   {
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { "dppd",   { XM, EXx, Ib } },
3471   },
3472
3473   /* PREFIX_0F3A42 */
3474   {
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { "mpsadbw", { XM, EXx, Ib } },
3478   },
3479
3480   /* PREFIX_0F3A44 */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { "pclmulqdq", { XM, EXx, PCLMUL } },
3485   },
3486
3487   /* PREFIX_0F3A60 */
3488   {
3489     { Bad_Opcode },
3490     { Bad_Opcode },
3491     { "pcmpestrm", { XM, EXx, Ib } },
3492   },
3493
3494   /* PREFIX_0F3A61 */
3495   {
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { "pcmpestri", { XM, EXx, Ib } },
3499   },
3500
3501   /* PREFIX_0F3A62 */
3502   {
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { "pcmpistrm", { XM, EXx, Ib } },
3506   },
3507
3508   /* PREFIX_0F3A63 */
3509   {
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { "pcmpistri", { XM, EXx, Ib } },
3513   },
3514
3515   /* PREFIX_0F3ADF */
3516   {
3517     { Bad_Opcode },
3518     { Bad_Opcode },
3519     { "aeskeygenassist", { XM, EXx, Ib } },
3520   },
3521
3522   /* PREFIX_VEX_10 */
3523   {
3524     { VEX_W_TABLE (VEX_W_10_P_0) },
3525     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3526     { VEX_W_TABLE (VEX_W_10_P_2) },
3527     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3528   },
3529
3530   /* PREFIX_VEX_11 */
3531   {
3532     { VEX_W_TABLE (VEX_W_11_P_0) },
3533     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3534     { VEX_W_TABLE (VEX_W_11_P_2) },
3535     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3536   },
3537
3538   /* PREFIX_VEX_12 */
3539   {
3540     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3541     { VEX_W_TABLE (VEX_W_12_P_1) },
3542     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3543     { VEX_W_TABLE (VEX_W_12_P_3) },
3544   },
3545
3546   /* PREFIX_VEX_16 */
3547   {
3548     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3549     { VEX_W_TABLE (VEX_W_16_P_1) },
3550     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3551   },
3552
3553   /* PREFIX_VEX_2A */
3554   {
3555     { Bad_Opcode },
3556     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3557     { Bad_Opcode },
3558     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3559   },
3560
3561   /* PREFIX_VEX_2C */
3562   {
3563     { Bad_Opcode },
3564     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3565     { Bad_Opcode },
3566     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3567   },
3568
3569   /* PREFIX_VEX_2D */
3570   {
3571     { Bad_Opcode },
3572     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3573     { Bad_Opcode },
3574     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3575   },
3576
3577   /* PREFIX_VEX_2E */
3578   {
3579     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3580     { Bad_Opcode },
3581     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3582   },
3583
3584   /* PREFIX_VEX_2F */
3585   {
3586     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3587     { Bad_Opcode },
3588     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3589   },
3590
3591   /* PREFIX_VEX_51 */
3592   {
3593     { VEX_W_TABLE (VEX_W_51_P_0) },
3594     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3595     { VEX_W_TABLE (VEX_W_51_P_2) },
3596     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3597   },
3598
3599   /* PREFIX_VEX_52 */
3600   {
3601     { VEX_W_TABLE (VEX_W_52_P_0) },
3602     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3603   },
3604
3605   /* PREFIX_VEX_53 */
3606   {
3607     { VEX_W_TABLE (VEX_W_53_P_0) },
3608     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3609   },
3610
3611   /* PREFIX_VEX_58 */
3612   {
3613     { VEX_W_TABLE (VEX_W_58_P_0) },
3614     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3615     { VEX_W_TABLE (VEX_W_58_P_2) },
3616     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3617   },
3618
3619   /* PREFIX_VEX_59 */
3620   {
3621     { VEX_W_TABLE (VEX_W_59_P_0) },
3622     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3623     { VEX_W_TABLE (VEX_W_59_P_2) },
3624     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3625   },
3626
3627   /* PREFIX_VEX_5A */
3628   {
3629     { VEX_W_TABLE (VEX_W_5A_P_0) },
3630     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3631     { "vcvtpd2ps%XY", { XMM, EXx } },
3632     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3633   },
3634
3635   /* PREFIX_VEX_5B */
3636   {
3637     { VEX_W_TABLE (VEX_W_5B_P_0) },
3638     { VEX_W_TABLE (VEX_W_5B_P_1) },
3639     { VEX_W_TABLE (VEX_W_5B_P_2) },
3640   },
3641
3642   /* PREFIX_VEX_5C */
3643   {
3644     { VEX_W_TABLE (VEX_W_5C_P_0) },
3645     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3646     { VEX_W_TABLE (VEX_W_5C_P_2) },
3647     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3648   },
3649
3650   /* PREFIX_VEX_5D */
3651   {
3652     { VEX_W_TABLE (VEX_W_5D_P_0) },
3653     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3654     { VEX_W_TABLE (VEX_W_5D_P_2) },
3655     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3656   },
3657
3658   /* PREFIX_VEX_5E */
3659   {
3660     { VEX_W_TABLE (VEX_W_5E_P_0) },
3661     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3662     { VEX_W_TABLE (VEX_W_5E_P_2) },
3663     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3664   },
3665
3666   /* PREFIX_VEX_5F */
3667   {
3668     { VEX_W_TABLE (VEX_W_5F_P_0) },
3669     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3670     { VEX_W_TABLE (VEX_W_5F_P_2) },
3671     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3672   },
3673
3674   /* PREFIX_VEX_60 */
3675   {
3676     { Bad_Opcode },
3677     { Bad_Opcode },
3678     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3679   },
3680
3681   /* PREFIX_VEX_61 */
3682   {
3683     { Bad_Opcode },
3684     { Bad_Opcode },
3685     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3686   },
3687
3688   /* PREFIX_VEX_62 */
3689   {
3690     { Bad_Opcode },
3691     { Bad_Opcode },
3692     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3693   },
3694
3695   /* PREFIX_VEX_63 */
3696   {
3697     { Bad_Opcode },
3698     { Bad_Opcode },
3699     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3700   },
3701
3702   /* PREFIX_VEX_64 */
3703   {
3704     { Bad_Opcode },
3705     { Bad_Opcode },
3706     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3707   },
3708
3709   /* PREFIX_VEX_65 */
3710   {
3711     { Bad_Opcode },
3712     { Bad_Opcode },
3713     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3714   },
3715
3716   /* PREFIX_VEX_66 */
3717   {
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3721   },
3722
3723   /* PREFIX_VEX_67 */
3724   {
3725     { Bad_Opcode },
3726     { Bad_Opcode },
3727     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3728   },
3729
3730   /* PREFIX_VEX_68 */
3731   {
3732     { Bad_Opcode },
3733     { Bad_Opcode },
3734     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3735   },
3736
3737   /* PREFIX_VEX_69 */
3738   {
3739     { Bad_Opcode },
3740     { Bad_Opcode },
3741     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3742   },
3743
3744   /* PREFIX_VEX_6A */
3745   {
3746     { Bad_Opcode },
3747     { Bad_Opcode },
3748     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3749   },
3750
3751   /* PREFIX_VEX_6B */
3752   {
3753     { Bad_Opcode },
3754     { Bad_Opcode },
3755     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3756   },
3757
3758   /* PREFIX_VEX_6C */
3759   {
3760     { Bad_Opcode },
3761     { Bad_Opcode },
3762     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3763   },
3764
3765   /* PREFIX_VEX_6D */
3766   {
3767     { Bad_Opcode },
3768     { Bad_Opcode },
3769     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3770   },
3771
3772   /* PREFIX_VEX_6E */
3773   {
3774     { Bad_Opcode },
3775     { Bad_Opcode },
3776     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3777   },
3778
3779   /* PREFIX_VEX_6F */
3780   {
3781     { Bad_Opcode },
3782     { VEX_W_TABLE (VEX_W_6F_P_1) },
3783     { VEX_W_TABLE (VEX_W_6F_P_2) },
3784   },
3785
3786   /* PREFIX_VEX_70 */
3787   {
3788     { Bad_Opcode },
3789     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3790     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3791     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3792   },
3793
3794   /* PREFIX_VEX_71_REG_2 */
3795   {
3796     { Bad_Opcode },
3797     { Bad_Opcode },
3798     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3799   },
3800
3801   /* PREFIX_VEX_71_REG_4 */
3802   {
3803     { Bad_Opcode },
3804     { Bad_Opcode },
3805     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3806   },
3807
3808   /* PREFIX_VEX_71_REG_6 */
3809   {
3810     { Bad_Opcode },
3811     { Bad_Opcode },
3812     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3813   },
3814
3815   /* PREFIX_VEX_72_REG_2 */
3816   {
3817     { Bad_Opcode },
3818     { Bad_Opcode },
3819     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3820   },
3821
3822   /* PREFIX_VEX_72_REG_4 */
3823   {
3824     { Bad_Opcode },
3825     { Bad_Opcode },
3826     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3827   },
3828
3829   /* PREFIX_VEX_72_REG_6 */
3830   {
3831     { Bad_Opcode },
3832     { Bad_Opcode },
3833     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3834   },
3835
3836   /* PREFIX_VEX_73_REG_2 */
3837   {
3838     { Bad_Opcode },
3839     { Bad_Opcode },
3840     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3841   },
3842
3843   /* PREFIX_VEX_73_REG_3 */
3844   {
3845     { Bad_Opcode },
3846     { Bad_Opcode },
3847     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3848   },
3849
3850   /* PREFIX_VEX_73_REG_6 */
3851   {
3852     { Bad_Opcode },
3853     { Bad_Opcode },
3854     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3855   },
3856
3857   /* PREFIX_VEX_73_REG_7 */
3858   {
3859     { Bad_Opcode },
3860     { Bad_Opcode },
3861     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3862   },
3863
3864   /* PREFIX_VEX_74 */
3865   {
3866     { Bad_Opcode },
3867     { Bad_Opcode },
3868     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3869   },
3870
3871   /* PREFIX_VEX_75 */
3872   {
3873     { Bad_Opcode },
3874     { Bad_Opcode },
3875     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3876   },
3877
3878   /* PREFIX_VEX_76 */
3879   {
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3883   },
3884
3885   /* PREFIX_VEX_77 */
3886   {
3887     { VEX_W_TABLE (VEX_W_77_P_0) },
3888   },
3889
3890   /* PREFIX_VEX_7C */
3891   {
3892     { Bad_Opcode },
3893     { Bad_Opcode },
3894     { VEX_W_TABLE (VEX_W_7C_P_2) },
3895     { VEX_W_TABLE (VEX_W_7C_P_3) },
3896   },
3897
3898   /* PREFIX_VEX_7D */
3899   {
3900     { Bad_Opcode },
3901     { Bad_Opcode },
3902     { VEX_W_TABLE (VEX_W_7D_P_2) },
3903     { VEX_W_TABLE (VEX_W_7D_P_3) },
3904   },
3905
3906   /* PREFIX_VEX_7E */
3907   {
3908     { Bad_Opcode },
3909     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3910     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3911   },
3912
3913   /* PREFIX_VEX_7F */
3914   {
3915     { Bad_Opcode },
3916     { VEX_W_TABLE (VEX_W_7F_P_1) },
3917     { VEX_W_TABLE (VEX_W_7F_P_2) },
3918   },
3919
3920   /* PREFIX_VEX_C2 */
3921   {
3922     { VEX_W_TABLE (VEX_W_C2_P_0) },
3923     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3924     { VEX_W_TABLE (VEX_W_C2_P_2) },
3925     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3926   },
3927
3928   /* PREFIX_VEX_C4 */
3929   {
3930     { Bad_Opcode },
3931     { Bad_Opcode },
3932     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3933   },
3934
3935   /* PREFIX_VEX_C5 */
3936   {
3937     { Bad_Opcode },
3938     { Bad_Opcode },
3939     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3940   },
3941
3942   /* PREFIX_VEX_D0 */
3943   {
3944     { Bad_Opcode },
3945     { Bad_Opcode },
3946     { VEX_W_TABLE (VEX_W_D0_P_2) },
3947     { VEX_W_TABLE (VEX_W_D0_P_3) },
3948   },
3949
3950   /* PREFIX_VEX_D1 */
3951   {
3952     { Bad_Opcode },
3953     { Bad_Opcode },
3954     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3955   },
3956
3957   /* PREFIX_VEX_D2 */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3962   },
3963
3964   /* PREFIX_VEX_D3 */
3965   {
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3969   },
3970
3971   /* PREFIX_VEX_D4 */
3972   {
3973     { Bad_Opcode },
3974     { Bad_Opcode },
3975     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3976   },
3977
3978   /* PREFIX_VEX_D5 */
3979   {
3980     { Bad_Opcode },
3981     { Bad_Opcode },
3982     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3983   },
3984
3985   /* PREFIX_VEX_D6 */
3986   {
3987     { Bad_Opcode },
3988     { Bad_Opcode },
3989     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3990   },
3991
3992   /* PREFIX_VEX_D7 */
3993   {
3994     { Bad_Opcode },
3995     { Bad_Opcode },
3996     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3997   },
3998
3999   /* PREFIX_VEX_D8 */
4000   {
4001     { Bad_Opcode },
4002     { Bad_Opcode },
4003     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4004   },
4005
4006   /* PREFIX_VEX_D9 */
4007   {
4008     { Bad_Opcode },
4009     { Bad_Opcode },
4010     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4011   },
4012
4013   /* PREFIX_VEX_DA */
4014   {
4015     { Bad_Opcode },
4016     { Bad_Opcode },
4017     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4018   },
4019
4020   /* PREFIX_VEX_DB */
4021   {
4022     { Bad_Opcode },
4023     { Bad_Opcode },
4024     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4025   },
4026
4027   /* PREFIX_VEX_DC */
4028   {
4029     { Bad_Opcode },
4030     { Bad_Opcode },
4031     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4032   },
4033
4034   /* PREFIX_VEX_DD */
4035   {
4036     { Bad_Opcode },
4037     { Bad_Opcode },
4038     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4039   },
4040
4041   /* PREFIX_VEX_DE */
4042   {
4043     { Bad_Opcode },
4044     { Bad_Opcode },
4045     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4046   },
4047
4048   /* PREFIX_VEX_DF */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4053   },
4054
4055   /* PREFIX_VEX_E0 */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4060   },
4061
4062   /* PREFIX_VEX_E1 */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4067   },
4068
4069   /* PREFIX_VEX_E2 */
4070   {
4071     { Bad_Opcode },
4072     { Bad_Opcode },
4073     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4074   },
4075
4076   /* PREFIX_VEX_E3 */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4081   },
4082
4083   /* PREFIX_VEX_E4 */
4084   {
4085     { Bad_Opcode },
4086     { Bad_Opcode },
4087     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4088   },
4089
4090   /* PREFIX_VEX_E5 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4095   },
4096
4097   /* PREFIX_VEX_E6 */
4098   {
4099     { Bad_Opcode },
4100     { VEX_W_TABLE (VEX_W_E6_P_1) },
4101     { VEX_W_TABLE (VEX_W_E6_P_2) },
4102     { VEX_W_TABLE (VEX_W_E6_P_3) },
4103   },
4104
4105   /* PREFIX_VEX_E7 */
4106   {
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4110   },
4111
4112   /* PREFIX_VEX_E8 */
4113   {
4114     { Bad_Opcode },
4115     { Bad_Opcode },
4116     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4117   },
4118
4119   /* PREFIX_VEX_E9 */
4120   {
4121     { Bad_Opcode },
4122     { Bad_Opcode },
4123     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4124   },
4125
4126   /* PREFIX_VEX_EA */
4127   {
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4131   },
4132
4133   /* PREFIX_VEX_EB */
4134   {
4135     { Bad_Opcode },
4136     { Bad_Opcode },
4137     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4138   },
4139
4140   /* PREFIX_VEX_EC */
4141   {
4142     { Bad_Opcode },
4143     { Bad_Opcode },
4144     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4145   },
4146
4147   /* PREFIX_VEX_ED */
4148   {
4149     { Bad_Opcode },
4150     { Bad_Opcode },
4151     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4152   },
4153
4154   /* PREFIX_VEX_EE */
4155   {
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4159   },
4160
4161   /* PREFIX_VEX_EF */
4162   {
4163     { Bad_Opcode },
4164     { Bad_Opcode },
4165     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4166   },
4167
4168   /* PREFIX_VEX_F0 */
4169   {
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4174   },
4175
4176   /* PREFIX_VEX_F1 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4181   },
4182
4183   /* PREFIX_VEX_F2 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4188   },
4189
4190   /* PREFIX_VEX_F3 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4195   },
4196
4197   /* PREFIX_VEX_F4 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4202   },
4203
4204   /* PREFIX_VEX_F5 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4209   },
4210
4211   /* PREFIX_VEX_F6 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4216   },
4217
4218   /* PREFIX_VEX_F7 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4223   },
4224
4225   /* PREFIX_VEX_F8 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4230   },
4231
4232   /* PREFIX_VEX_F9 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4237   },
4238
4239   /* PREFIX_VEX_FA */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4244   },
4245
4246   /* PREFIX_VEX_FB */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4251   },
4252
4253   /* PREFIX_VEX_FC */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4258   },
4259
4260   /* PREFIX_VEX_FD */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4265   },
4266
4267   /* PREFIX_VEX_FE */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4272   },
4273
4274   /* PREFIX_VEX_3800 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4279   },
4280
4281   /* PREFIX_VEX_3801 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4286   },
4287
4288   /* PREFIX_VEX_3802 */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4293   },
4294
4295   /* PREFIX_VEX_3803 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4300   },
4301
4302   /* PREFIX_VEX_3804 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4307   },
4308
4309   /* PREFIX_VEX_3805 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4314   },
4315
4316   /* PREFIX_VEX_3806 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4321   },
4322
4323   /* PREFIX_VEX_3807 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4328   },
4329
4330   /* PREFIX_VEX_3808 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4335   },
4336
4337   /* PREFIX_VEX_3809 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4342   },
4343
4344   /* PREFIX_VEX_380A */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4349   },
4350
4351   /* PREFIX_VEX_380B */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4356   },
4357
4358   /* PREFIX_VEX_380C */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { VEX_W_TABLE (VEX_W_380C_P_2) },
4363   },
4364
4365   /* PREFIX_VEX_380D */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { VEX_W_TABLE (VEX_W_380D_P_2) },
4370   },
4371
4372   /* PREFIX_VEX_380E */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { VEX_W_TABLE (VEX_W_380E_P_2) },
4377   },
4378
4379   /* PREFIX_VEX_380F */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { VEX_W_TABLE (VEX_W_380F_P_2) },
4384   },
4385
4386   /* PREFIX_VEX_3817 */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { VEX_W_TABLE (VEX_W_3817_P_2) },
4391   },
4392
4393   /* PREFIX_VEX_3818 */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4398   },
4399
4400   /* PREFIX_VEX_3819 */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4405   },
4406
4407   /* PREFIX_VEX_381A */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4412   },
4413
4414   /* PREFIX_VEX_381C */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4419   },
4420
4421   /* PREFIX_VEX_381D */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4426   },
4427
4428   /* PREFIX_VEX_381E */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4433   },
4434
4435   /* PREFIX_VEX_3820 */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4440     { Bad_Opcode },
4441   },
4442
4443   /* PREFIX_VEX_3821 */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4448   },
4449
4450   /* PREFIX_VEX_3822 */
4451   {
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4455   },
4456
4457   /* PREFIX_VEX_3823 */
4458   {
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4462   },
4463
4464   /* PREFIX_VEX_3824 */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4469   },
4470
4471   /* PREFIX_VEX_3825 */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4476   },
4477
4478   /* PREFIX_VEX_3828 */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4483   },
4484
4485   /* PREFIX_VEX_3829 */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4490   },
4491
4492   /* PREFIX_VEX_382A */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4497   },
4498
4499   /* PREFIX_VEX_382B */
4500   {
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4504   },
4505
4506   /* PREFIX_VEX_382C */
4507   {
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4511   },
4512
4513   /* PREFIX_VEX_382D */
4514   {
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4518   },
4519
4520   /* PREFIX_VEX_382E */
4521   {
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4525   },
4526
4527   /* PREFIX_VEX_382F */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4532   },
4533
4534   /* PREFIX_VEX_3830 */
4535   {
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4539   },
4540
4541   /* PREFIX_VEX_3831 */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4546   },
4547
4548   /* PREFIX_VEX_3832 */
4549   {
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4553   },
4554
4555   /* PREFIX_VEX_3833 */
4556   {
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4560   },
4561
4562   /* PREFIX_VEX_3834 */
4563   {
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4567   },
4568
4569   /* PREFIX_VEX_3835 */
4570   {
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4574   },
4575
4576   /* PREFIX_VEX_3837 */
4577   {
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4581   },
4582
4583   /* PREFIX_VEX_3838 */
4584   {
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4588   },
4589
4590   /* PREFIX_VEX_3839 */
4591   {
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4595   },
4596
4597   /* PREFIX_VEX_383A */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4602   },
4603
4604   /* PREFIX_VEX_383B */
4605   {
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4609   },
4610
4611   /* PREFIX_VEX_383C */
4612   {
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4616   },
4617
4618   /* PREFIX_VEX_383D */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4623   },
4624
4625   /* PREFIX_VEX_383E */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4630   },
4631
4632   /* PREFIX_VEX_383F */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4637   },
4638
4639   /* PREFIX_VEX_3840 */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4644   },
4645
4646   /* PREFIX_VEX_3841 */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4651   },
4652
4653   /* PREFIX_VEX_3896 */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4658   },
4659
4660   /* PREFIX_VEX_3897 */
4661   {
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4665   },
4666
4667   /* PREFIX_VEX_3898 */
4668   {
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { "vfmadd132p%XW", { XM, Vex, EXx } },
4672   },
4673
4674   /* PREFIX_VEX_3899 */
4675   {
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4679   },
4680
4681   /* PREFIX_VEX_389A */
4682   {
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { "vfmsub132p%XW", { XM, Vex, EXx } },
4686   },
4687
4688   /* PREFIX_VEX_389B */
4689   {
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4693   },
4694
4695   /* PREFIX_VEX_389C */
4696   {
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4700   },
4701
4702   /* PREFIX_VEX_389D */
4703   {
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4707   },
4708
4709   /* PREFIX_VEX_389E */
4710   {
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4714   },
4715
4716   /* PREFIX_VEX_389F */
4717   {
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4721   },
4722
4723   /* PREFIX_VEX_38A6 */
4724   {
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4728     { Bad_Opcode },
4729   },
4730
4731   /* PREFIX_VEX_38A7 */
4732   {
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4736   },
4737
4738   /* PREFIX_VEX_38A8 */
4739   {
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { "vfmadd213p%XW", { XM, Vex, EXx } },
4743   },
4744
4745   /* PREFIX_VEX_38A9 */
4746   {
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4750   },
4751
4752   /* PREFIX_VEX_38AA */
4753   {
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { "vfmsub213p%XW", { XM, Vex, EXx } },
4757   },
4758
4759   /* PREFIX_VEX_38AB */
4760   {
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4764   },
4765
4766   /* PREFIX_VEX_38AC */
4767   {
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4771   },
4772
4773   /* PREFIX_VEX_38AD */
4774   {
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4778   },
4779
4780   /* PREFIX_VEX_38AE */
4781   {
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4785   },
4786
4787   /* PREFIX_VEX_38AF */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4792   },
4793
4794   /* PREFIX_VEX_38B6 */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4799   },
4800
4801   /* PREFIX_VEX_38B7 */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4806   },
4807
4808   /* PREFIX_VEX_38B8 */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "vfmadd231p%XW", { XM, Vex, EXx } },
4813   },
4814
4815   /* PREFIX_VEX_38B9 */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4820   },
4821
4822   /* PREFIX_VEX_38BA */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { "vfmsub231p%XW", { XM, Vex, EXx } },
4827   },
4828
4829   /* PREFIX_VEX_38BB */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4834   },
4835
4836   /* PREFIX_VEX_38BC */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4841   },
4842
4843   /* PREFIX_VEX_38BD */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4848   },
4849
4850   /* PREFIX_VEX_38BE */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4855   },
4856
4857   /* PREFIX_VEX_38BF */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4862   },
4863
4864   /* PREFIX_VEX_38DB */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4869   },
4870
4871   /* PREFIX_VEX_38DC */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4876   },
4877
4878   /* PREFIX_VEX_38DD */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4883   },
4884
4885   /* PREFIX_VEX_38DE */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4890   },
4891
4892   /* PREFIX_VEX_38DF */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4897   },
4898
4899   /* PREFIX_VEX_3A04 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { VEX_W_TABLE (VEX_W_3A04_P_2) },
4904   },
4905
4906   /* PREFIX_VEX_3A05 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { VEX_W_TABLE (VEX_W_3A05_P_2) },
4911   },
4912
4913   /* PREFIX_VEX_3A06 */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4918   },
4919
4920   /* PREFIX_VEX_3A08 */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { VEX_W_TABLE (VEX_W_3A08_P_2) },
4925   },
4926
4927   /* PREFIX_VEX_3A09 */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { VEX_W_TABLE (VEX_W_3A09_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_3A0A */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_3A0B */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_3A0C */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_W_TABLE (VEX_W_3A0C_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_3A0D */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_W_TABLE (VEX_W_3A0D_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_3A0E */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_3A0F */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_3A14 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_3A15 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_3A16 */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_3A17 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5002   },
5003
5004   /* PREFIX_VEX_3A18 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_3A19 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_3A20 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_3A21 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_3A22 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_3A40 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_W_TABLE (VEX_W_3A40_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_3A41 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_3A42 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_3A44 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_3A4A */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_W_TABLE (VEX_W_3A4A_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_3A4B */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { VEX_W_TABLE (VEX_W_3A4B_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_3A4C */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_3A5C */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5093   },
5094
5095   /* PREFIX_VEX_3A5D */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5100   },
5101
5102   /* PREFIX_VEX_3A5E */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5107   },
5108
5109   /* PREFIX_VEX_3A5F */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5114   },
5115
5116   /* PREFIX_VEX_3A60 */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5121     { Bad_Opcode },
5122   },
5123
5124   /* PREFIX_VEX_3A61 */
5125   {
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_3A62 */
5132   {
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_3A63 */
5139   {
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_3A68 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5150   },
5151
5152   /* PREFIX_VEX_3A69 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5157   },
5158
5159   /* PREFIX_VEX_3A6A */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_3A6B */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5171   },
5172
5173   /* PREFIX_VEX_3A6C */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5178   },
5179
5180   /* PREFIX_VEX_3A6D */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5185   },
5186
5187   /* PREFIX_VEX_3A6E */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5192   },
5193
5194   /* PREFIX_VEX_3A6F */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5199   },
5200
5201   /* PREFIX_VEX_3A78 */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5206   },
5207
5208   /* PREFIX_VEX_3A79 */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5213   },
5214
5215   /* PREFIX_VEX_3A7A */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5220   },
5221
5222   /* PREFIX_VEX_3A7B */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5227   },
5228
5229   /* PREFIX_VEX_3A7C */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5234     { Bad_Opcode },
5235   },
5236
5237   /* PREFIX_VEX_3A7D */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5242   },
5243
5244   /* PREFIX_VEX_3A7E */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5249   },
5250
5251   /* PREFIX_VEX_3A7F */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5256   },
5257
5258   /* PREFIX_VEX_3ADF */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5263   },
5264 };
5265
5266 static const struct dis386 x86_64_table[][2] = {
5267   /* X86_64_06 */
5268   {
5269     { "push{T|}", { es } },
5270   },
5271
5272   /* X86_64_07 */
5273   {
5274     { "pop{T|}", { es } },
5275   },
5276
5277   /* X86_64_0D */
5278   {
5279     { "push{T|}", { cs } },
5280   },
5281
5282   /* X86_64_16 */
5283   {
5284     { "push{T|}", { ss } },
5285   },
5286
5287   /* X86_64_17 */
5288   {
5289     { "pop{T|}", { ss } },
5290   },
5291
5292   /* X86_64_1E */
5293   {
5294     { "push{T|}", { ds } },
5295   },
5296
5297   /* X86_64_1F */
5298   {
5299     { "pop{T|}", { ds } },
5300   },
5301
5302   /* X86_64_27 */
5303   {
5304     { "daa", { XX } },
5305   },
5306
5307   /* X86_64_2F */
5308   {
5309     { "das", { XX } },
5310   },
5311
5312   /* X86_64_37 */
5313   {
5314     { "aaa", { XX } },
5315   },
5316
5317   /* X86_64_3F */
5318   {
5319     { "aas", { XX } },
5320   },
5321
5322   /* X86_64_60 */
5323   {
5324     { "pusha{P|}", { XX } },
5325   },
5326
5327   /* X86_64_61 */
5328   {
5329     { "popa{P|}", { XX } },
5330   },
5331
5332   /* X86_64_62 */
5333   {
5334     { MOD_TABLE (MOD_62_32BIT) },
5335   },
5336
5337   /* X86_64_63 */
5338   {
5339     { "arpl", { Ew, Gw } },
5340     { "movs{lq|xd}", { Gv, Ed } },
5341   },
5342
5343   /* X86_64_6D */
5344   {
5345     { "ins{R|}", { Yzr, indirDX } },
5346     { "ins{G|}", { Yzr, indirDX } },
5347   },
5348
5349   /* X86_64_6F */
5350   {
5351     { "outs{R|}", { indirDXr, Xz } },
5352     { "outs{G|}", { indirDXr, Xz } },
5353   },
5354
5355   /* X86_64_9A */
5356   {
5357     { "Jcall{T|}", { Ap } },
5358   },
5359
5360   /* X86_64_C4 */
5361   {
5362     { MOD_TABLE (MOD_C4_32BIT) },
5363     { VEX_C4_TABLE (VEX_0F) },
5364   },
5365
5366   /* X86_64_C5 */
5367   {
5368     { MOD_TABLE (MOD_C5_32BIT) },
5369     { VEX_C5_TABLE (VEX_0F) },
5370   },
5371
5372   /* X86_64_CE */
5373   {
5374     { "into", { XX } },
5375   },
5376
5377   /* X86_64_D4 */
5378   {
5379     { "aam", { sIb } },
5380   },
5381
5382   /* X86_64_D5 */
5383   {
5384     { "aad", { sIb } },
5385   },
5386
5387   /* X86_64_EA */
5388   {
5389     { "Jjmp{T|}", { Ap } },
5390   },
5391
5392   /* X86_64_0F01_REG_0 */
5393   {
5394     { "sgdt{Q|IQ}", { M } },
5395     { "sgdt", { M } },
5396   },
5397
5398   /* X86_64_0F01_REG_1 */
5399   {
5400     { "sidt{Q|IQ}", { M } },
5401     { "sidt", { M } },
5402   },
5403
5404   /* X86_64_0F01_REG_2 */
5405   {
5406     { "lgdt{Q|Q}", { M } },
5407     { "lgdt", { M } },
5408   },
5409
5410   /* X86_64_0F01_REG_3 */
5411   {
5412     { "lidt{Q|Q}", { M } },
5413     { "lidt", { M } },
5414   },
5415 };
5416
5417 static const struct dis386 three_byte_table[][256] = {
5418
5419   /* THREE_BYTE_0F38 */
5420   {
5421     /* 00 */
5422     { "pshufb",         { MX, EM } },
5423     { "phaddw",         { MX, EM } },
5424     { "phaddd",         { MX, EM } },
5425     { "phaddsw",        { MX, EM } },
5426     { "pmaddubsw",      { MX, EM } },
5427     { "phsubw",         { MX, EM } },
5428     { "phsubd",         { MX, EM } },
5429     { "phsubsw",        { MX, EM } },
5430     /* 08 */
5431     { "psignb",         { MX, EM } },
5432     { "psignw",         { MX, EM } },
5433     { "psignd",         { MX, EM } },
5434     { "pmulhrsw",       { MX, EM } },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     /* 10 */
5440     { PREFIX_TABLE (PREFIX_0F3810) },
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { PREFIX_TABLE (PREFIX_0F3814) },
5445     { PREFIX_TABLE (PREFIX_0F3815) },
5446     { Bad_Opcode },
5447     { PREFIX_TABLE (PREFIX_0F3817) },
5448     /* 18 */
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { "pabsb",          { MX, EM } },
5454     { "pabsw",          { MX, EM } },
5455     { "pabsd",          { MX, EM } },
5456     { Bad_Opcode },
5457     /* 20 */
5458     { PREFIX_TABLE (PREFIX_0F3820) },
5459     { PREFIX_TABLE (PREFIX_0F3821) },
5460     { PREFIX_TABLE (PREFIX_0F3822) },
5461     { PREFIX_TABLE (PREFIX_0F3823) },
5462     { PREFIX_TABLE (PREFIX_0F3824) },
5463     { PREFIX_TABLE (PREFIX_0F3825) },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     /* 28 */
5467     { PREFIX_TABLE (PREFIX_0F3828) },
5468     { PREFIX_TABLE (PREFIX_0F3829) },
5469     { PREFIX_TABLE (PREFIX_0F382A) },
5470     { PREFIX_TABLE (PREFIX_0F382B) },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     /* 30 */
5476     { PREFIX_TABLE (PREFIX_0F3830) },
5477     { PREFIX_TABLE (PREFIX_0F3831) },
5478     { PREFIX_TABLE (PREFIX_0F3832) },
5479     { PREFIX_TABLE (PREFIX_0F3833) },
5480     { PREFIX_TABLE (PREFIX_0F3834) },
5481     { PREFIX_TABLE (PREFIX_0F3835) },
5482     { Bad_Opcode },
5483     { PREFIX_TABLE (PREFIX_0F3837) },
5484     /* 38 */
5485     { PREFIX_TABLE (PREFIX_0F3838) },
5486     { PREFIX_TABLE (PREFIX_0F3839) },
5487     { PREFIX_TABLE (PREFIX_0F383A) },
5488     { PREFIX_TABLE (PREFIX_0F383B) },
5489     { PREFIX_TABLE (PREFIX_0F383C) },
5490     { PREFIX_TABLE (PREFIX_0F383D) },
5491     { PREFIX_TABLE (PREFIX_0F383E) },
5492     { PREFIX_TABLE (PREFIX_0F383F) },
5493     /* 40 */
5494     { PREFIX_TABLE (PREFIX_0F3840) },
5495     { PREFIX_TABLE (PREFIX_0F3841) },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     /* 48 */
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     /* 50 */
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     /* 58 */
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     /* 60 */
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     /* 68 */
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     /* 70 */
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     /* 78 */
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     /* 80 */
5566     { PREFIX_TABLE (PREFIX_0F3880) },
5567     { PREFIX_TABLE (PREFIX_0F3881) },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     /* 88 */
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     /* 90 */
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     /* 98 */
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     /* a0 */
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     /* a8 */
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     /* b0 */
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     /* b8 */
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     /* c0 */
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     /* c8 */
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     /* d0 */
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     /* d8 */
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { PREFIX_TABLE (PREFIX_0F38DB) },
5669     { PREFIX_TABLE (PREFIX_0F38DC) },
5670     { PREFIX_TABLE (PREFIX_0F38DD) },
5671     { PREFIX_TABLE (PREFIX_0F38DE) },
5672     { PREFIX_TABLE (PREFIX_0F38DF) },
5673     /* e0 */
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     /* e8 */
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     /* f0 */
5692     { PREFIX_TABLE (PREFIX_0F38F0) },
5693     { PREFIX_TABLE (PREFIX_0F38F1) },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     /* f8 */
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709   },
5710   /* THREE_BYTE_0F3A */
5711   {
5712     /* 00 */
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     /* 08 */
5722     { PREFIX_TABLE (PREFIX_0F3A08) },
5723     { PREFIX_TABLE (PREFIX_0F3A09) },
5724     { PREFIX_TABLE (PREFIX_0F3A0A) },
5725     { PREFIX_TABLE (PREFIX_0F3A0B) },
5726     { PREFIX_TABLE (PREFIX_0F3A0C) },
5727     { PREFIX_TABLE (PREFIX_0F3A0D) },
5728     { PREFIX_TABLE (PREFIX_0F3A0E) },
5729     { "palignr",        { MX, EM, Ib } },
5730     /* 10 */
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { PREFIX_TABLE (PREFIX_0F3A14) },
5736     { PREFIX_TABLE (PREFIX_0F3A15) },
5737     { PREFIX_TABLE (PREFIX_0F3A16) },
5738     { PREFIX_TABLE (PREFIX_0F3A17) },
5739     /* 18 */
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     /* 20 */
5749     { PREFIX_TABLE (PREFIX_0F3A20) },
5750     { PREFIX_TABLE (PREFIX_0F3A21) },
5751     { PREFIX_TABLE (PREFIX_0F3A22) },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     /* 28 */
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     /* 30 */
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     /* 38 */
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     /* 40 */
5785     { PREFIX_TABLE (PREFIX_0F3A40) },
5786     { PREFIX_TABLE (PREFIX_0F3A41) },
5787     { PREFIX_TABLE (PREFIX_0F3A42) },
5788     { Bad_Opcode },
5789     { PREFIX_TABLE (PREFIX_0F3A44) },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     /* 48 */
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     /* 50 */
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     /* 58 */
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     /* 60 */
5821     { PREFIX_TABLE (PREFIX_0F3A60) },
5822     { PREFIX_TABLE (PREFIX_0F3A61) },
5823     { PREFIX_TABLE (PREFIX_0F3A62) },
5824     { PREFIX_TABLE (PREFIX_0F3A63) },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     /* 68 */
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     /* 70 */
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     /* 78 */
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     /* 80 */
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     /* 88 */
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     /* 90 */
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     /* 98 */
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     /* a0 */
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     /* a8 */
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     /* b0 */
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     /* b8 */
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     /* c0 */
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     /* c8 */
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     /* d0 */
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     /* d8 */
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { PREFIX_TABLE (PREFIX_0F3ADF) },
5964     /* e0 */
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     /* e8 */
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     /* f0 */
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     /* f8 */
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000   },
6001
6002   /* THREE_BYTE_0F7A */
6003   {
6004     /* 00 */
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     /* 08 */
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     /* 10 */
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     /* 18 */
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     /* 20 */
6041     { "ptest",          { XX } },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     /* 28 */
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     /* 30 */
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     /* 38 */
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     /* 40 */
6077     { Bad_Opcode },
6078     { "phaddbw",        { XM, EXq } },
6079     { "phaddbd",        { XM, EXq } },
6080     { "phaddbq",        { XM, EXq } },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { "phaddwd",        { XM, EXq } },
6084     { "phaddwq",        { XM, EXq } },
6085     /* 48 */
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { "phadddq",        { XM, EXq } },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     /* 50 */
6095     { Bad_Opcode },
6096     { "phaddubw",       { XM, EXq } },
6097     { "phaddubd",       { XM, EXq } },
6098     { "phaddubq",       { XM, EXq } },
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "phadduwd",       { XM, EXq } },
6102     { "phadduwq",       { XM, EXq } },
6103     /* 58 */
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "phaddudq",       { XM, EXq } },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     /* 60 */
6113     { Bad_Opcode },
6114     { "phsubbw",        { XM, EXq } },
6115     { "phsubbd",        { XM, EXq } },
6116     { "phsubbq",        { XM, EXq } },
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     /* 68 */
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     /* 70 */
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     /* 78 */
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     /* 80 */
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     /* 88 */
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     /* 90 */
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     /* 98 */
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     /* a0 */
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     /* a8 */
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     /* b0 */
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     /* b8 */
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     /* c0 */
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     /* c8 */
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     /* d0 */
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     /* d8 */
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     /* e0 */
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     /* e8 */
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     /* f0 */
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     /* f8 */
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292   },
6293 };
6294
6295 static const struct dis386 xop_table[][256] = {
6296   /* XOP_08 */
6297   {
6298     /* 00 */
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     /* 08 */
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     /* 10 */
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     /* 18 */
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     /* 20 */
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     /* 28 */
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     /* 30 */
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     /* 38 */
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     /* 40 */
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     /* 48 */
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     /* 50 */
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     /* 58 */
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     /* 60 */
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     /* 68 */
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     /* 70 */
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     /* 78 */
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     /* 80 */
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6449     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6450     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6451     /* 88 */
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6459     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6460     /* 90 */
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6467     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6468     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6469     /* 98 */
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6477     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6478     /* a0 */
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6482     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6486     { Bad_Opcode },
6487     /* a8 */
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     /* b0 */
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6504     { Bad_Opcode },
6505     /* b8 */
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     /* c0 */
6515     { "vprotb",         { XM, Vex_2src_1, Ib } },
6516     { "vprotw",         { XM, Vex_2src_1, Ib } },
6517     { "vprotd",         { XM, Vex_2src_1, Ib } },
6518     { "vprotq",         { XM, Vex_2src_1, Ib } },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     /* c8 */
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6529     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6530     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6531     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6532     /* d0 */
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     /* d8 */
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     /* e0 */
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     /* e8 */
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6565     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6566     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6567     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6568     /* f0 */
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     /* f8 */
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586   },
6587   /* XOP_09 */
6588   {
6589     /* 00 */
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     /* 08 */
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     /* 10 */
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { REG_TABLE (REG_XOP_LWPCB) },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     /* 18 */
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     /* 20 */
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     /* 28 */
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     /* 30 */
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     /* 38 */
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     /* 40 */
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     /* 48 */
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     /* 50 */
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     /* 58 */
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     /* 60 */
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     /* 68 */
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     /* 70 */
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     /* 78 */
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     /* 80 */
6734     { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6735     { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6736     { "vfrczss",        { XM, EXd } },
6737     { "vfrczsd",        { XM, EXq } },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     /* 88 */
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     /* 90 */
6752     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6753     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6754     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6755     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6756     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6757     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6758     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6759     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6760     /* 98 */
6761     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6762     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6763     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6764     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     /* a0 */
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     /* a8 */
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     /* b0 */
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     /* b8 */
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     /* c0 */
6806     { Bad_Opcode },
6807     { "vphaddbw",       { XM, EXxmm } },
6808     { "vphaddbd",       { XM, EXxmm } },
6809     { "vphaddbq",       { XM, EXxmm } },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { "vphaddwd",       { XM, EXxmm } },
6813     { "vphaddwq",       { XM, EXxmm } },
6814     /* c8 */
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { "vphadddq",       { XM, EXxmm } },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     /* d0 */
6824     { Bad_Opcode },
6825     { "vphaddubw",      { XM, EXxmm } },
6826     { "vphaddubd",      { XM, EXxmm } },
6827     { "vphaddubq",      { XM, EXxmm } },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { "vphadduwd",      { XM, EXxmm } },
6831     { "vphadduwq",      { XM, EXxmm } },
6832     /* d8 */
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { "vphaddudq",      { XM, EXxmm } },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     /* e0 */
6842     { Bad_Opcode },
6843     { "vphsubbw",       { XM, EXxmm } },
6844     { "vphsubwd",       { XM, EXxmm } },
6845     { "vphsubdq",       { XM, EXxmm } },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     /* e8 */
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     /* f0 */
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     /* f8 */
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877   },
6878   /* XOP_0A */
6879   {
6880     /* 00 */
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     /* 08 */
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     /* 10 */
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { REG_TABLE (REG_XOP_LWP) },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     /* 18 */
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     /* 20 */
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     /* 28 */
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     /* 30 */
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     /* 38 */
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* 40 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 48 */
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* 50 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* 58 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 60 */
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* 68 */
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 70 */
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 78 */
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* 80 */
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* 88 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* 90 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* 98 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* a0 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* a8 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* b0 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* b8 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* c0 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* c8 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* d0 */
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* d8 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     /* e0 */
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     /* e8 */
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     /* f0 */
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     /* f8 */
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168   },
7169 };
7170
7171 static const struct dis386 vex_table[][256] = {
7172   /* VEX_0F */
7173   {
7174     /* 00 */
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     /* 08 */
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     /* 10 */
7193     { PREFIX_TABLE (PREFIX_VEX_10) },
7194     { PREFIX_TABLE (PREFIX_VEX_11) },
7195     { PREFIX_TABLE (PREFIX_VEX_12) },
7196     { MOD_TABLE (MOD_VEX_13) },
7197     { VEX_W_TABLE (VEX_W_14) },
7198     { VEX_W_TABLE (VEX_W_15) },
7199     { PREFIX_TABLE (PREFIX_VEX_16) },
7200     { MOD_TABLE (MOD_VEX_17) },
7201     /* 18 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     /* 20 */
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     /* 28 */
7220     { VEX_W_TABLE (VEX_W_28) },
7221     { VEX_W_TABLE (VEX_W_29) },
7222     { PREFIX_TABLE (PREFIX_VEX_2A) },
7223     { MOD_TABLE (MOD_VEX_2B) },
7224     { PREFIX_TABLE (PREFIX_VEX_2C) },
7225     { PREFIX_TABLE (PREFIX_VEX_2D) },
7226     { PREFIX_TABLE (PREFIX_VEX_2E) },
7227     { PREFIX_TABLE (PREFIX_VEX_2F) },
7228     /* 30 */
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     /* 38 */
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     /* 40 */
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     /* 48 */
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     /* 50 */
7265     { MOD_TABLE (MOD_VEX_50) },
7266     { PREFIX_TABLE (PREFIX_VEX_51) },
7267     { PREFIX_TABLE (PREFIX_VEX_52) },
7268     { PREFIX_TABLE (PREFIX_VEX_53) },
7269     { "vandpX",         { XM, Vex, EXx } },
7270     { "vandnpX",        { XM, Vex, EXx } },
7271     { "vorpX",          { XM, Vex, EXx } },
7272     { "vxorpX",         { XM, Vex, EXx } },
7273     /* 58 */
7274     { PREFIX_TABLE (PREFIX_VEX_58) },
7275     { PREFIX_TABLE (PREFIX_VEX_59) },
7276     { PREFIX_TABLE (PREFIX_VEX_5A) },
7277     { PREFIX_TABLE (PREFIX_VEX_5B) },
7278     { PREFIX_TABLE (PREFIX_VEX_5C) },
7279     { PREFIX_TABLE (PREFIX_VEX_5D) },
7280     { PREFIX_TABLE (PREFIX_VEX_5E) },
7281     { PREFIX_TABLE (PREFIX_VEX_5F) },
7282     /* 60 */
7283     { PREFIX_TABLE (PREFIX_VEX_60) },
7284     { PREFIX_TABLE (PREFIX_VEX_61) },
7285     { PREFIX_TABLE (PREFIX_VEX_62) },
7286     { PREFIX_TABLE (PREFIX_VEX_63) },
7287     { PREFIX_TABLE (PREFIX_VEX_64) },
7288     { PREFIX_TABLE (PREFIX_VEX_65) },
7289     { PREFIX_TABLE (PREFIX_VEX_66) },
7290     { PREFIX_TABLE (PREFIX_VEX_67) },
7291     /* 68 */
7292     { PREFIX_TABLE (PREFIX_VEX_68) },
7293     { PREFIX_TABLE (PREFIX_VEX_69) },
7294     { PREFIX_TABLE (PREFIX_VEX_6A) },
7295     { PREFIX_TABLE (PREFIX_VEX_6B) },
7296     { PREFIX_TABLE (PREFIX_VEX_6C) },
7297     { PREFIX_TABLE (PREFIX_VEX_6D) },
7298     { PREFIX_TABLE (PREFIX_VEX_6E) },
7299     { PREFIX_TABLE (PREFIX_VEX_6F) },
7300     /* 70 */
7301     { PREFIX_TABLE (PREFIX_VEX_70) },
7302     { REG_TABLE (REG_VEX_71) },
7303     { REG_TABLE (REG_VEX_72) },
7304     { REG_TABLE (REG_VEX_73) },
7305     { PREFIX_TABLE (PREFIX_VEX_74) },
7306     { PREFIX_TABLE (PREFIX_VEX_75) },
7307     { PREFIX_TABLE (PREFIX_VEX_76) },
7308     { PREFIX_TABLE (PREFIX_VEX_77) },
7309     /* 78 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { PREFIX_TABLE (PREFIX_VEX_7C) },
7315     { PREFIX_TABLE (PREFIX_VEX_7D) },
7316     { PREFIX_TABLE (PREFIX_VEX_7E) },
7317     { PREFIX_TABLE (PREFIX_VEX_7F) },
7318     /* 80 */
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 88 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 90 */
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 98 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* a0 */
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* a8 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { REG_TABLE (REG_VEX_AE) },
7371     { Bad_Opcode },
7372     /* b0 */
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* b8 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* c0 */
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { PREFIX_TABLE (PREFIX_VEX_C2) },
7394     { Bad_Opcode },
7395     { PREFIX_TABLE (PREFIX_VEX_C4) },
7396     { PREFIX_TABLE (PREFIX_VEX_C5) },
7397     { "vshufpX",        { XM, Vex, EXx, Ib } },
7398     { Bad_Opcode },
7399     /* c8 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* d0 */
7409     { PREFIX_TABLE (PREFIX_VEX_D0) },
7410     { PREFIX_TABLE (PREFIX_VEX_D1) },
7411     { PREFIX_TABLE (PREFIX_VEX_D2) },
7412     { PREFIX_TABLE (PREFIX_VEX_D3) },
7413     { PREFIX_TABLE (PREFIX_VEX_D4) },
7414     { PREFIX_TABLE (PREFIX_VEX_D5) },
7415     { PREFIX_TABLE (PREFIX_VEX_D6) },
7416     { PREFIX_TABLE (PREFIX_VEX_D7) },
7417     /* d8 */
7418     { PREFIX_TABLE (PREFIX_VEX_D8) },
7419     { PREFIX_TABLE (PREFIX_VEX_D9) },
7420     { PREFIX_TABLE (PREFIX_VEX_DA) },
7421     { PREFIX_TABLE (PREFIX_VEX_DB) },
7422     { PREFIX_TABLE (PREFIX_VEX_DC) },
7423     { PREFIX_TABLE (PREFIX_VEX_DD) },
7424     { PREFIX_TABLE (PREFIX_VEX_DE) },
7425     { PREFIX_TABLE (PREFIX_VEX_DF) },
7426     /* e0 */
7427     { PREFIX_TABLE (PREFIX_VEX_E0) },
7428     { PREFIX_TABLE (PREFIX_VEX_E1) },
7429     { PREFIX_TABLE (PREFIX_VEX_E2) },
7430     { PREFIX_TABLE (PREFIX_VEX_E3) },
7431     { PREFIX_TABLE (PREFIX_VEX_E4) },
7432     { PREFIX_TABLE (PREFIX_VEX_E5) },
7433     { PREFIX_TABLE (PREFIX_VEX_E6) },
7434     { PREFIX_TABLE (PREFIX_VEX_E7) },
7435     /* e8 */
7436     { PREFIX_TABLE (PREFIX_VEX_E8) },
7437     { PREFIX_TABLE (PREFIX_VEX_E9) },
7438     { PREFIX_TABLE (PREFIX_VEX_EA) },
7439     { PREFIX_TABLE (PREFIX_VEX_EB) },
7440     { PREFIX_TABLE (PREFIX_VEX_EC) },
7441     { PREFIX_TABLE (PREFIX_VEX_ED) },
7442     { PREFIX_TABLE (PREFIX_VEX_EE) },
7443     { PREFIX_TABLE (PREFIX_VEX_EF) },
7444     /* f0 */
7445     { PREFIX_TABLE (PREFIX_VEX_F0) },
7446     { PREFIX_TABLE (PREFIX_VEX_F1) },
7447     { PREFIX_TABLE (PREFIX_VEX_F2) },
7448     { PREFIX_TABLE (PREFIX_VEX_F3) },
7449     { PREFIX_TABLE (PREFIX_VEX_F4) },
7450     { PREFIX_TABLE (PREFIX_VEX_F5) },
7451     { PREFIX_TABLE (PREFIX_VEX_F6) },
7452     { PREFIX_TABLE (PREFIX_VEX_F7) },
7453     /* f8 */
7454     { PREFIX_TABLE (PREFIX_VEX_F8) },
7455     { PREFIX_TABLE (PREFIX_VEX_F9) },
7456     { PREFIX_TABLE (PREFIX_VEX_FA) },
7457     { PREFIX_TABLE (PREFIX_VEX_FB) },
7458     { PREFIX_TABLE (PREFIX_VEX_FC) },
7459     { PREFIX_TABLE (PREFIX_VEX_FD) },
7460     { PREFIX_TABLE (PREFIX_VEX_FE) },
7461     { Bad_Opcode },
7462   },
7463   /* VEX_0F38 */
7464   {
7465     /* 00 */
7466     { PREFIX_TABLE (PREFIX_VEX_3800) },
7467     { PREFIX_TABLE (PREFIX_VEX_3801) },
7468     { PREFIX_TABLE (PREFIX_VEX_3802) },
7469     { PREFIX_TABLE (PREFIX_VEX_3803) },
7470     { PREFIX_TABLE (PREFIX_VEX_3804) },
7471     { PREFIX_TABLE (PREFIX_VEX_3805) },
7472     { PREFIX_TABLE (PREFIX_VEX_3806) },
7473     { PREFIX_TABLE (PREFIX_VEX_3807) },
7474     /* 08 */
7475     { PREFIX_TABLE (PREFIX_VEX_3808) },
7476     { PREFIX_TABLE (PREFIX_VEX_3809) },
7477     { PREFIX_TABLE (PREFIX_VEX_380A) },
7478     { PREFIX_TABLE (PREFIX_VEX_380B) },
7479     { PREFIX_TABLE (PREFIX_VEX_380C) },
7480     { PREFIX_TABLE (PREFIX_VEX_380D) },
7481     { PREFIX_TABLE (PREFIX_VEX_380E) },
7482     { PREFIX_TABLE (PREFIX_VEX_380F) },
7483     /* 10 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { PREFIX_TABLE (PREFIX_VEX_3817) },
7492     /* 18 */
7493     { PREFIX_TABLE (PREFIX_VEX_3818) },
7494     { PREFIX_TABLE (PREFIX_VEX_3819) },
7495     { PREFIX_TABLE (PREFIX_VEX_381A) },
7496     { Bad_Opcode },
7497     { PREFIX_TABLE (PREFIX_VEX_381C) },
7498     { PREFIX_TABLE (PREFIX_VEX_381D) },
7499     { PREFIX_TABLE (PREFIX_VEX_381E) },
7500     { Bad_Opcode },
7501     /* 20 */
7502     { PREFIX_TABLE (PREFIX_VEX_3820) },
7503     { PREFIX_TABLE (PREFIX_VEX_3821) },
7504     { PREFIX_TABLE (PREFIX_VEX_3822) },
7505     { PREFIX_TABLE (PREFIX_VEX_3823) },
7506     { PREFIX_TABLE (PREFIX_VEX_3824) },
7507     { PREFIX_TABLE (PREFIX_VEX_3825) },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* 28 */
7511     { PREFIX_TABLE (PREFIX_VEX_3828) },
7512     { PREFIX_TABLE (PREFIX_VEX_3829) },
7513     { PREFIX_TABLE (PREFIX_VEX_382A) },
7514     { PREFIX_TABLE (PREFIX_VEX_382B) },
7515     { PREFIX_TABLE (PREFIX_VEX_382C) },
7516     { PREFIX_TABLE (PREFIX_VEX_382D) },
7517     { PREFIX_TABLE (PREFIX_VEX_382E) },
7518     { PREFIX_TABLE (PREFIX_VEX_382F) },
7519     /* 30 */
7520     { PREFIX_TABLE (PREFIX_VEX_3830) },
7521     { PREFIX_TABLE (PREFIX_VEX_3831) },
7522     { PREFIX_TABLE (PREFIX_VEX_3832) },
7523     { PREFIX_TABLE (PREFIX_VEX_3833) },
7524     { PREFIX_TABLE (PREFIX_VEX_3834) },
7525     { PREFIX_TABLE (PREFIX_VEX_3835) },
7526     { Bad_Opcode },
7527     { PREFIX_TABLE (PREFIX_VEX_3837) },
7528     /* 38 */
7529     { PREFIX_TABLE (PREFIX_VEX_3838) },
7530     { PREFIX_TABLE (PREFIX_VEX_3839) },
7531     { PREFIX_TABLE (PREFIX_VEX_383A) },
7532     { PREFIX_TABLE (PREFIX_VEX_383B) },
7533     { PREFIX_TABLE (PREFIX_VEX_383C) },
7534     { PREFIX_TABLE (PREFIX_VEX_383D) },
7535     { PREFIX_TABLE (PREFIX_VEX_383E) },
7536     { PREFIX_TABLE (PREFIX_VEX_383F) },
7537     /* 40 */
7538     { PREFIX_TABLE (PREFIX_VEX_3840) },
7539     { PREFIX_TABLE (PREFIX_VEX_3841) },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     /* 48 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* 50 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 58 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 60 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     /* 68 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     /* 70 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     /* 78 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     /* 80 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     /* 88 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     /* 90 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { PREFIX_TABLE (PREFIX_VEX_3896) },
7635     { PREFIX_TABLE (PREFIX_VEX_3897) },
7636     /* 98 */
7637     { PREFIX_TABLE (PREFIX_VEX_3898) },
7638     { PREFIX_TABLE (PREFIX_VEX_3899) },
7639     { PREFIX_TABLE (PREFIX_VEX_389A) },
7640     { PREFIX_TABLE (PREFIX_VEX_389B) },
7641     { PREFIX_TABLE (PREFIX_VEX_389C) },
7642     { PREFIX_TABLE (PREFIX_VEX_389D) },
7643     { PREFIX_TABLE (PREFIX_VEX_389E) },
7644     { PREFIX_TABLE (PREFIX_VEX_389F) },
7645     /* a0 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7653     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7654     /* a8 */
7655     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7656     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7657     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7658     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7659     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7660     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7661     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7662     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7663     /* b0 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7671     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7672     /* b8 */
7673     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7674     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7675     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7676     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7677     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7678     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7679     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7680     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7681     /* c0 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* c8 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     /* d0 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     /* d8 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7713     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7714     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7715     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7716     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7717     /* e0 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     /* e8 */
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     /* f0 */
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     /* f8 */
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753   },
7754   /* VEX_0F3A */
7755   {
7756     /* 00 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7762     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7763     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7764     { Bad_Opcode },
7765     /* 08 */
7766     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7767     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7768     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7769     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7770     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7771     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7772     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7773     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7774     /* 10 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7780     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7781     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7782     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7783     /* 18 */
7784     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7785     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* 20 */
7793     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7794     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7795     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* 28 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* 30 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* 38 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* 40 */
7829     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7830     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7831     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7832     { Bad_Opcode },
7833     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* 48 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7841     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7842     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     /* 50 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 58 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7861     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7862     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7863     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7864     /* 60 */
7865     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7866     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7867     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7868     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 68 */
7874     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7875     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7876     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7877     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7878     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7879     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7880     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7881     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7882     /* 70 */
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     /* 78 */
7892     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7893     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7894     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7895     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7896     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7897     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7898     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7899     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7900     /* 80 */
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     /* 88 */
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* 90 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* 98 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* a0 */
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* a8 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* b0 */
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     /* b8 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* c0 */
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* c8 */
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* d0 */
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* d8 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8008     /* e0 */
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     /* e8 */
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     /* f0 */
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     /* f8 */
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044   },
8045 };
8046
8047 static const struct dis386 vex_len_table[][2] = {
8048   /* VEX_LEN_10_P_1 */
8049   {
8050     { VEX_W_TABLE (VEX_W_10_P_1) },
8051   },
8052
8053   /* VEX_LEN_10_P_3 */
8054   {
8055     { VEX_W_TABLE (VEX_W_10_P_3) },
8056   },
8057
8058   /* VEX_LEN_11_P_1 */
8059   {
8060     { VEX_W_TABLE (VEX_W_11_P_1) },
8061   },
8062
8063   /* VEX_LEN_11_P_3 */
8064   {
8065     { VEX_W_TABLE (VEX_W_11_P_3) },
8066   },
8067
8068   /* VEX_LEN_12_P_0_M_0 */
8069   {
8070     { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
8071   },
8072
8073   /* VEX_LEN_12_P_0_M_1 */
8074   {
8075     { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
8076   },
8077
8078   /* VEX_LEN_12_P_2 */
8079   {
8080     { VEX_W_TABLE (VEX_W_12_P_2) },
8081   },
8082
8083   /* VEX_LEN_13_M_0 */
8084   {
8085     { VEX_W_TABLE (VEX_W_13_M_0) },
8086   },
8087
8088   /* VEX_LEN_16_P_0_M_0 */
8089   {
8090     { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
8091   },
8092
8093   /* VEX_LEN_16_P_0_M_1 */
8094   {
8095     { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
8096   },
8097
8098   /* VEX_LEN_16_P_2 */
8099   {
8100     { VEX_W_TABLE (VEX_W_16_P_2) },
8101   },
8102
8103   /* VEX_LEN_17_M_0 */
8104   {
8105     { VEX_W_TABLE (VEX_W_17_M_0) },
8106   },
8107
8108   /* VEX_LEN_2A_P_1 */
8109   {
8110     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
8111   },
8112
8113   /* VEX_LEN_2A_P_3 */
8114   {
8115     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
8116   },
8117
8118   /* VEX_LEN_2C_P_1 */
8119   {
8120     { "vcvttss2siY",    { Gv, EXd } },
8121   },
8122
8123   /* VEX_LEN_2C_P_3 */
8124   {
8125     { "vcvttsd2siY",    { Gv, EXq } },
8126   },
8127
8128   /* VEX_LEN_2D_P_1 */
8129   {
8130     { "vcvtss2siY",     { Gv, EXd } },
8131   },
8132
8133   /* VEX_LEN_2D_P_3 */
8134   {
8135     { "vcvtsd2siY",     { Gv, EXq } },
8136   },
8137
8138   /* VEX_LEN_2E_P_0 */
8139   {
8140     { VEX_W_TABLE (VEX_W_2E_P_0) },
8141   },
8142
8143   /* VEX_LEN_2E_P_2 */
8144   {
8145     { VEX_W_TABLE (VEX_W_2E_P_2) },
8146   },
8147
8148   /* VEX_LEN_2F_P_0 */
8149   {
8150     { VEX_W_TABLE (VEX_W_2F_P_0) },
8151   },
8152
8153   /* VEX_LEN_2F_P_2 */
8154   {
8155     { VEX_W_TABLE (VEX_W_2F_P_2) },
8156   },
8157
8158   /* VEX_LEN_51_P_1 */
8159   {
8160     { VEX_W_TABLE (VEX_W_51_P_1) },
8161   },
8162
8163   /* VEX_LEN_51_P_3 */
8164   {
8165     { VEX_W_TABLE (VEX_W_51_P_3) },
8166   },
8167
8168   /* VEX_LEN_52_P_1 */
8169   {
8170     { VEX_W_TABLE (VEX_W_52_P_1) },
8171   },
8172
8173   /* VEX_LEN_53_P_1 */
8174   {
8175     { VEX_W_TABLE (VEX_W_53_P_1) },
8176   },
8177
8178   /* VEX_LEN_58_P_1 */
8179   {
8180     { VEX_W_TABLE (VEX_W_58_P_1) },
8181   },
8182
8183   /* VEX_LEN_58_P_3 */
8184   {
8185     { VEX_W_TABLE (VEX_W_58_P_3) },
8186   },
8187
8188   /* VEX_LEN_59_P_1 */
8189   {
8190     { VEX_W_TABLE (VEX_W_59_P_1) },
8191   },
8192
8193   /* VEX_LEN_59_P_3 */
8194   {
8195     { VEX_W_TABLE (VEX_W_59_P_3) },
8196   },
8197
8198   /* VEX_LEN_5A_P_1 */
8199   {
8200     { VEX_W_TABLE (VEX_W_5A_P_1) },
8201   },
8202
8203   /* VEX_LEN_5A_P_3 */
8204   {
8205     { VEX_W_TABLE (VEX_W_5A_P_3) },
8206   },
8207
8208   /* VEX_LEN_5C_P_1 */
8209   {
8210     { VEX_W_TABLE (VEX_W_5C_P_1) },
8211   },
8212
8213   /* VEX_LEN_5C_P_3 */
8214   {
8215     { VEX_W_TABLE (VEX_W_5C_P_3) },
8216   },
8217
8218   /* VEX_LEN_5D_P_1 */
8219   {
8220     { VEX_W_TABLE (VEX_W_5D_P_1) },
8221   },
8222
8223   /* VEX_LEN_5D_P_3 */
8224   {
8225     { VEX_W_TABLE (VEX_W_5D_P_3) },
8226   },
8227
8228   /* VEX_LEN_5E_P_1 */
8229   {
8230     { VEX_W_TABLE (VEX_W_5E_P_1) },
8231   },
8232
8233   /* VEX_LEN_5E_P_3 */
8234   {
8235     { VEX_W_TABLE (VEX_W_5E_P_3) },
8236   },
8237
8238   /* VEX_LEN_5F_P_1 */
8239   {
8240     { VEX_W_TABLE (VEX_W_5F_P_1) },
8241   },
8242
8243   /* VEX_LEN_5F_P_3 */
8244   {
8245     { VEX_W_TABLE (VEX_W_5F_P_3) },
8246   },
8247
8248   /* VEX_LEN_60_P_2 */
8249   {
8250     { VEX_W_TABLE (VEX_W_60_P_2) },
8251   },
8252
8253   /* VEX_LEN_61_P_2 */
8254   {
8255     { VEX_W_TABLE (VEX_W_61_P_2) },
8256   },
8257
8258   /* VEX_LEN_62_P_2 */
8259   {
8260     { VEX_W_TABLE (VEX_W_62_P_2) },
8261   },
8262
8263   /* VEX_LEN_63_P_2 */
8264   {
8265     { VEX_W_TABLE (VEX_W_63_P_2) },
8266   },
8267
8268   /* VEX_LEN_64_P_2 */
8269   {
8270     { VEX_W_TABLE (VEX_W_64_P_2) },
8271   },
8272
8273   /* VEX_LEN_65_P_2 */
8274   {
8275     { VEX_W_TABLE (VEX_W_65_P_2) },
8276   },
8277
8278   /* VEX_LEN_66_P_2 */
8279   {
8280     { VEX_W_TABLE (VEX_W_66_P_2) },
8281   },
8282
8283   /* VEX_LEN_67_P_2 */
8284   {
8285     { VEX_W_TABLE (VEX_W_67_P_2) },
8286   },
8287
8288   /* VEX_LEN_68_P_2 */
8289   {
8290     { VEX_W_TABLE (VEX_W_68_P_2) },
8291   },
8292
8293   /* VEX_LEN_69_P_2 */
8294   {
8295     { VEX_W_TABLE (VEX_W_69_P_2) },
8296   },
8297
8298   /* VEX_LEN_6A_P_2 */
8299   {
8300     { VEX_W_TABLE (VEX_W_6A_P_2) },
8301   },
8302
8303   /* VEX_LEN_6B_P_2 */
8304   {
8305     { VEX_W_TABLE (VEX_W_6B_P_2) },
8306   },
8307
8308   /* VEX_LEN_6C_P_2 */
8309   {
8310     { VEX_W_TABLE (VEX_W_6C_P_2) },
8311   },
8312
8313   /* VEX_LEN_6D_P_2 */
8314   {
8315     { VEX_W_TABLE (VEX_W_6D_P_2) },
8316   },
8317
8318   /* VEX_LEN_6E_P_2 */
8319   {
8320     { "vmovK",          { XM, Edq } },
8321   },
8322
8323   /* VEX_LEN_70_P_1 */
8324   {
8325     { VEX_W_TABLE (VEX_W_70_P_1) },
8326   },
8327
8328   /* VEX_LEN_70_P_2 */
8329   {
8330     { VEX_W_TABLE (VEX_W_70_P_2) },
8331   },
8332
8333   /* VEX_LEN_70_P_3 */
8334   {
8335     { VEX_W_TABLE (VEX_W_70_P_3) },
8336   },
8337
8338   /* VEX_LEN_71_R_2_P_2 */
8339   {
8340     { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
8341   },
8342
8343   /* VEX_LEN_71_R_4_P_2 */
8344   {
8345     { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
8346   },
8347
8348   /* VEX_LEN_71_R_6_P_2 */
8349   {
8350     { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
8351   },
8352
8353   /* VEX_LEN_72_R_2_P_2 */
8354   {
8355     { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
8356   },
8357
8358   /* VEX_LEN_72_R_4_P_2 */
8359   {
8360     { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
8361   },
8362
8363   /* VEX_LEN_72_R_6_P_2 */
8364   {
8365     { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
8366   },
8367
8368   /* VEX_LEN_73_R_2_P_2 */
8369   {
8370     { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
8371   },
8372
8373   /* VEX_LEN_73_R_3_P_2 */
8374   {
8375     { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
8376   },
8377
8378   /* VEX_LEN_73_R_6_P_2 */
8379   {
8380     { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
8381   },
8382
8383   /* VEX_LEN_73_R_7_P_2 */
8384   {
8385     { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
8386   },
8387
8388   /* VEX_LEN_74_P_2 */
8389   {
8390     { VEX_W_TABLE (VEX_W_74_P_2) },
8391   },
8392
8393   /* VEX_LEN_75_P_2 */
8394   {
8395     { VEX_W_TABLE (VEX_W_75_P_2) },
8396   },
8397
8398   /* VEX_LEN_76_P_2 */
8399   {
8400     { VEX_W_TABLE (VEX_W_76_P_2) },
8401   },
8402
8403   /* VEX_LEN_7E_P_1 */
8404   {
8405     { VEX_W_TABLE (VEX_W_7E_P_1) },
8406   },
8407
8408   /* VEX_LEN_7E_P_2 */
8409   {
8410     { "vmovK",          { Edq, XM } },
8411   },
8412
8413   /* VEX_LEN_AE_R_2_M_0 */
8414   {
8415     { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
8416   },
8417
8418   /* VEX_LEN_AE_R_3_M_0 */
8419   {
8420     { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
8421   },
8422
8423   /* VEX_LEN_C2_P_1 */
8424   {
8425     { VEX_W_TABLE (VEX_W_C2_P_1) },
8426   },
8427
8428   /* VEX_LEN_C2_P_3 */
8429   {
8430     { VEX_W_TABLE (VEX_W_C2_P_3) },
8431   },
8432
8433   /* VEX_LEN_C4_P_2 */
8434   {
8435     { VEX_W_TABLE (VEX_W_C4_P_2) },
8436   },
8437
8438   /* VEX_LEN_C5_P_2 */
8439   {
8440     { VEX_W_TABLE (VEX_W_C5_P_2) },
8441   },
8442
8443   /* VEX_LEN_D1_P_2 */
8444   {
8445     { VEX_W_TABLE (VEX_W_D1_P_2) },
8446   },
8447
8448   /* VEX_LEN_D2_P_2 */
8449   {
8450     { VEX_W_TABLE (VEX_W_D2_P_2) },
8451   },
8452
8453   /* VEX_LEN_D3_P_2 */
8454   {
8455     { VEX_W_TABLE (VEX_W_D3_P_2) },
8456   },
8457
8458   /* VEX_LEN_D4_P_2 */
8459   {
8460     { VEX_W_TABLE (VEX_W_D4_P_2) },
8461   },
8462
8463   /* VEX_LEN_D5_P_2 */
8464   {
8465     { VEX_W_TABLE (VEX_W_D5_P_2) },
8466   },
8467
8468   /* VEX_LEN_D6_P_2 */
8469   {
8470     { VEX_W_TABLE (VEX_W_D6_P_2) },
8471   },
8472
8473   /* VEX_LEN_D7_P_2_M_1 */
8474   {
8475     { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
8476   },
8477
8478   /* VEX_LEN_D8_P_2 */
8479   {
8480     { VEX_W_TABLE (VEX_W_D8_P_2) },
8481   },
8482
8483   /* VEX_LEN_D9_P_2 */
8484   {
8485     { VEX_W_TABLE (VEX_W_D9_P_2) },
8486   },
8487
8488   /* VEX_LEN_DA_P_2 */
8489   {
8490     { VEX_W_TABLE (VEX_W_DA_P_2) },
8491   },
8492
8493   /* VEX_LEN_DB_P_2 */
8494   {
8495     { VEX_W_TABLE (VEX_W_DB_P_2) },
8496   },
8497
8498   /* VEX_LEN_DC_P_2 */
8499   {
8500     { VEX_W_TABLE (VEX_W_DC_P_2) },
8501   },
8502
8503   /* VEX_LEN_DD_P_2 */
8504   {
8505     { VEX_W_TABLE (VEX_W_DD_P_2) },
8506   },
8507
8508   /* VEX_LEN_DE_P_2 */
8509   {
8510     { VEX_W_TABLE (VEX_W_DE_P_2) },
8511   },
8512
8513   /* VEX_LEN_DF_P_2 */
8514   {
8515     { VEX_W_TABLE (VEX_W_DF_P_2) },
8516   },
8517
8518   /* VEX_LEN_E0_P_2 */
8519   {
8520     { VEX_W_TABLE (VEX_W_E0_P_2) },
8521   },
8522
8523   /* VEX_LEN_E1_P_2 */
8524   {
8525     { VEX_W_TABLE (VEX_W_E1_P_2) },
8526   },
8527
8528   /* VEX_LEN_E2_P_2 */
8529   {
8530     { VEX_W_TABLE (VEX_W_E2_P_2) },
8531   },
8532
8533   /* VEX_LEN_E3_P_2 */
8534   {
8535     { VEX_W_TABLE (VEX_W_E3_P_2) },
8536   },
8537
8538   /* VEX_LEN_E4_P_2 */
8539   {
8540     { VEX_W_TABLE (VEX_W_E4_P_2) },
8541   },
8542
8543   /* VEX_LEN_E5_P_2 */
8544   {
8545     { VEX_W_TABLE (VEX_W_E5_P_2) },
8546   },
8547
8548   /* VEX_LEN_E8_P_2 */
8549   {
8550     { VEX_W_TABLE (VEX_W_E8_P_2) },
8551   },
8552
8553   /* VEX_LEN_E9_P_2 */
8554   {
8555     { VEX_W_TABLE (VEX_W_E9_P_2) },
8556   },
8557
8558   /* VEX_LEN_EA_P_2 */
8559   {
8560     { VEX_W_TABLE (VEX_W_EA_P_2) },
8561   },
8562
8563   /* VEX_LEN_EB_P_2 */
8564   {
8565     { VEX_W_TABLE (VEX_W_EB_P_2) },
8566   },
8567
8568   /* VEX_LEN_EC_P_2 */
8569   {
8570     { VEX_W_TABLE (VEX_W_EC_P_2) },
8571   },
8572
8573   /* VEX_LEN_ED_P_2 */
8574   {
8575     { VEX_W_TABLE (VEX_W_ED_P_2) },
8576   },
8577
8578   /* VEX_LEN_EE_P_2 */
8579   {
8580     { VEX_W_TABLE (VEX_W_EE_P_2) },
8581   },
8582
8583   /* VEX_LEN_EF_P_2 */
8584   {
8585     { VEX_W_TABLE (VEX_W_EF_P_2) },
8586   },
8587
8588   /* VEX_LEN_F1_P_2 */
8589   {
8590     { VEX_W_TABLE (VEX_W_F1_P_2) },
8591   },
8592
8593   /* VEX_LEN_F2_P_2 */
8594   {
8595     { VEX_W_TABLE (VEX_W_F2_P_2) },
8596   },
8597
8598   /* VEX_LEN_F3_P_2 */
8599   {
8600     { VEX_W_TABLE (VEX_W_F3_P_2) },
8601   },
8602
8603   /* VEX_LEN_F4_P_2 */
8604   {
8605     { VEX_W_TABLE (VEX_W_F4_P_2) },
8606   },
8607
8608   /* VEX_LEN_F5_P_2 */
8609   {
8610     { VEX_W_TABLE (VEX_W_F5_P_2) },
8611   },
8612
8613   /* VEX_LEN_F6_P_2 */
8614   {
8615     { VEX_W_TABLE (VEX_W_F6_P_2) },
8616   },
8617
8618   /* VEX_LEN_F7_P_2 */
8619   {
8620     { VEX_W_TABLE (VEX_W_F7_P_2) },
8621   },
8622
8623   /* VEX_LEN_F8_P_2 */
8624   {
8625     { VEX_W_TABLE (VEX_W_F8_P_2) },
8626   },
8627
8628   /* VEX_LEN_F9_P_2 */
8629   {
8630     { VEX_W_TABLE (VEX_W_F9_P_2) },
8631   },
8632
8633   /* VEX_LEN_FA_P_2 */
8634   {
8635     { VEX_W_TABLE (VEX_W_FA_P_2) },
8636   },
8637
8638   /* VEX_LEN_FB_P_2 */
8639   {
8640     { VEX_W_TABLE (VEX_W_FB_P_2) },
8641   },
8642
8643   /* VEX_LEN_FC_P_2 */
8644   {
8645     { VEX_W_TABLE (VEX_W_FC_P_2) },
8646   },
8647
8648   /* VEX_LEN_FD_P_2 */
8649   {
8650     { VEX_W_TABLE (VEX_W_FD_P_2) },
8651   },
8652
8653   /* VEX_LEN_FE_P_2 */
8654   {
8655     { VEX_W_TABLE (VEX_W_FE_P_2) },
8656   },
8657
8658   /* VEX_LEN_3800_P_2 */
8659   {
8660     { VEX_W_TABLE (VEX_W_3800_P_2) },
8661   },
8662
8663   /* VEX_LEN_3801_P_2 */
8664   {
8665     { VEX_W_TABLE (VEX_W_3801_P_2) },
8666   },
8667
8668   /* VEX_LEN_3802_P_2 */
8669   {
8670     { VEX_W_TABLE (VEX_W_3802_P_2) },
8671   },
8672
8673   /* VEX_LEN_3803_P_2 */
8674   {
8675     { VEX_W_TABLE (VEX_W_3803_P_2) },
8676   },
8677
8678   /* VEX_LEN_3804_P_2 */
8679   {
8680     { VEX_W_TABLE (VEX_W_3804_P_2) },
8681   },
8682
8683   /* VEX_LEN_3805_P_2 */
8684   {
8685     { VEX_W_TABLE (VEX_W_3805_P_2) },
8686   },
8687
8688   /* VEX_LEN_3806_P_2 */
8689   {
8690     { VEX_W_TABLE (VEX_W_3806_P_2) },
8691   },
8692
8693   /* VEX_LEN_3807_P_2 */
8694   {
8695     { VEX_W_TABLE (VEX_W_3807_P_2) },
8696   },
8697
8698   /* VEX_LEN_3808_P_2 */
8699   {
8700     { VEX_W_TABLE (VEX_W_3808_P_2) },
8701   },
8702
8703   /* VEX_LEN_3809_P_2 */
8704   {
8705     { VEX_W_TABLE (VEX_W_3809_P_2) },
8706   },
8707
8708   /* VEX_LEN_380A_P_2 */
8709   {
8710     { VEX_W_TABLE (VEX_W_380A_P_2) },
8711   },
8712
8713   /* VEX_LEN_380B_P_2 */
8714   {
8715     { VEX_W_TABLE (VEX_W_380B_P_2) },
8716   },
8717
8718   /* VEX_LEN_3819_P_2_M_0 */
8719   {
8720     { Bad_Opcode },
8721     { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
8722   },
8723
8724   /* VEX_LEN_381A_P_2_M_0 */
8725   {
8726     { Bad_Opcode },
8727     { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
8728   },
8729
8730   /* VEX_LEN_381C_P_2 */
8731   {
8732     { VEX_W_TABLE (VEX_W_381C_P_2) },
8733   },
8734
8735   /* VEX_LEN_381D_P_2 */
8736   {
8737     { VEX_W_TABLE (VEX_W_381D_P_2) },
8738   },
8739
8740   /* VEX_LEN_381E_P_2 */
8741   {
8742     { VEX_W_TABLE (VEX_W_381E_P_2) },
8743   },
8744
8745   /* VEX_LEN_3820_P_2 */
8746   {
8747     { VEX_W_TABLE (VEX_W_3820_P_2) },
8748   },
8749
8750   /* VEX_LEN_3821_P_2 */
8751   {
8752     { VEX_W_TABLE (VEX_W_3821_P_2) },
8753   },
8754
8755   /* VEX_LEN_3822_P_2 */
8756   {
8757     { VEX_W_TABLE (VEX_W_3822_P_2) },
8758   },
8759
8760   /* VEX_LEN_3823_P_2 */
8761   {
8762     { VEX_W_TABLE (VEX_W_3823_P_2) },
8763   },
8764
8765   /* VEX_LEN_3824_P_2 */
8766   {
8767     { VEX_W_TABLE (VEX_W_3824_P_2) },
8768   },
8769
8770   /* VEX_LEN_3825_P_2 */
8771   {
8772     { VEX_W_TABLE (VEX_W_3825_P_2) },
8773   },
8774
8775   /* VEX_LEN_3828_P_2 */
8776   {
8777     { VEX_W_TABLE (VEX_W_3828_P_2) },
8778   },
8779
8780   /* VEX_LEN_3829_P_2 */
8781   {
8782     { VEX_W_TABLE (VEX_W_3829_P_2) },
8783   },
8784
8785   /* VEX_LEN_382A_P_2_M_0 */
8786   {
8787     { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
8788   },
8789
8790   /* VEX_LEN_382B_P_2 */
8791   {
8792     { VEX_W_TABLE (VEX_W_382B_P_2) },
8793   },
8794
8795   /* VEX_LEN_3830_P_2 */
8796   {
8797     { VEX_W_TABLE (VEX_W_3830_P_2) },
8798   },
8799
8800   /* VEX_LEN_3831_P_2 */
8801   {
8802     { VEX_W_TABLE (VEX_W_3831_P_2) },
8803   },
8804
8805   /* VEX_LEN_3832_P_2 */
8806   {
8807     { VEX_W_TABLE (VEX_W_3832_P_2) },
8808   },
8809
8810   /* VEX_LEN_3833_P_2 */
8811   {
8812     { VEX_W_TABLE (VEX_W_3833_P_2) },
8813   },
8814
8815   /* VEX_LEN_3834_P_2 */
8816   {
8817     { VEX_W_TABLE (VEX_W_3834_P_2) },
8818   },
8819
8820   /* VEX_LEN_3835_P_2 */
8821   {
8822     { VEX_W_TABLE (VEX_W_3835_P_2) },
8823   },
8824
8825   /* VEX_LEN_3837_P_2 */
8826   {
8827     { VEX_W_TABLE (VEX_W_3837_P_2) },
8828   },
8829
8830   /* VEX_LEN_3838_P_2 */
8831   {
8832     { VEX_W_TABLE (VEX_W_3838_P_2) },
8833   },
8834
8835   /* VEX_LEN_3839_P_2 */
8836   {
8837     { VEX_W_TABLE (VEX_W_3839_P_2) },
8838   },
8839
8840   /* VEX_LEN_383A_P_2 */
8841   {
8842     { VEX_W_TABLE (VEX_W_383A_P_2) },
8843   },
8844
8845   /* VEX_LEN_383B_P_2 */
8846   {
8847     { VEX_W_TABLE (VEX_W_383B_P_2) },
8848   },
8849
8850   /* VEX_LEN_383C_P_2 */
8851   {
8852     { VEX_W_TABLE (VEX_W_383C_P_2) },
8853   },
8854
8855   /* VEX_LEN_383D_P_2 */
8856   {
8857     { VEX_W_TABLE (VEX_W_383D_P_2) },
8858   },
8859
8860   /* VEX_LEN_383E_P_2 */
8861   {
8862     { VEX_W_TABLE (VEX_W_383E_P_2) },
8863   },
8864
8865   /* VEX_LEN_383F_P_2 */
8866   {
8867     { VEX_W_TABLE (VEX_W_383F_P_2) },
8868   },
8869
8870   /* VEX_LEN_3840_P_2 */
8871   {
8872     { VEX_W_TABLE (VEX_W_3840_P_2) },
8873   },
8874
8875   /* VEX_LEN_3841_P_2 */
8876   {
8877     { VEX_W_TABLE (VEX_W_3841_P_2) },
8878   },
8879
8880   /* VEX_LEN_38DB_P_2 */
8881   {
8882     { VEX_W_TABLE (VEX_W_38DB_P_2) },
8883   },
8884
8885   /* VEX_LEN_38DC_P_2 */
8886   {
8887     { VEX_W_TABLE (VEX_W_38DC_P_2) },
8888   },
8889
8890   /* VEX_LEN_38DD_P_2 */
8891   {
8892     { VEX_W_TABLE (VEX_W_38DD_P_2) },
8893   },
8894
8895   /* VEX_LEN_38DE_P_2 */
8896   {
8897     { VEX_W_TABLE (VEX_W_38DE_P_2) },
8898   },
8899
8900   /* VEX_LEN_38DF_P_2 */
8901   {
8902     { VEX_W_TABLE (VEX_W_38DF_P_2) },
8903   },
8904
8905   /* VEX_LEN_3A06_P_2 */
8906   {
8907     { Bad_Opcode },
8908     { VEX_W_TABLE (VEX_W_3A06_P_2) },
8909   },
8910
8911   /* VEX_LEN_3A0A_P_2 */
8912   {
8913     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8914   },
8915
8916   /* VEX_LEN_3A0B_P_2 */
8917   {
8918     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
8919   },
8920
8921   /* VEX_LEN_3A0E_P_2 */
8922   {
8923     { VEX_W_TABLE (VEX_W_3A0E_P_2) },
8924   },
8925
8926   /* VEX_LEN_3A0F_P_2 */
8927   {
8928     { VEX_W_TABLE (VEX_W_3A0F_P_2) },
8929   },
8930
8931   /* VEX_LEN_3A14_P_2 */
8932   {
8933     { VEX_W_TABLE (VEX_W_3A14_P_2) },
8934   },
8935
8936   /* VEX_LEN_3A15_P_2 */
8937   {
8938     { VEX_W_TABLE (VEX_W_3A15_P_2) },
8939   },
8940
8941   /* VEX_LEN_3A16_P_2  */
8942   {
8943     { "vpextrK",        { Edq, XM, Ib } },
8944   },
8945
8946   /* VEX_LEN_3A17_P_2 */
8947   {
8948     { "vextractps",     { Edqd, XM, Ib } },
8949   },
8950
8951   /* VEX_LEN_3A18_P_2 */
8952   {
8953     { Bad_Opcode },
8954     { VEX_W_TABLE (VEX_W_3A18_P_2) },
8955   },
8956
8957   /* VEX_LEN_3A19_P_2 */
8958   {
8959     { Bad_Opcode },
8960     { VEX_W_TABLE (VEX_W_3A19_P_2) },
8961   },
8962
8963   /* VEX_LEN_3A20_P_2 */
8964   {
8965     { VEX_W_TABLE (VEX_W_3A20_P_2) },
8966   },
8967
8968   /* VEX_LEN_3A21_P_2 */
8969   {
8970     { VEX_W_TABLE (VEX_W_3A21_P_2) },
8971   },
8972
8973   /* VEX_LEN_3A22_P_2 */
8974   {
8975     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8976   },
8977
8978   /* VEX_LEN_3A41_P_2 */
8979   {
8980     { VEX_W_TABLE (VEX_W_3A41_P_2) },
8981   },
8982
8983   /* VEX_LEN_3A42_P_2 */
8984   {
8985     { VEX_W_TABLE (VEX_W_3A42_P_2) },
8986   },
8987
8988   /* VEX_LEN_3A44_P_2 */
8989   {
8990     { VEX_W_TABLE (VEX_W_3A44_P_2) },
8991   },
8992
8993   /* VEX_LEN_3A4C_P_2 */
8994   {
8995     { VEX_W_TABLE (VEX_W_3A4C_P_2) },
8996   },
8997
8998   /* VEX_LEN_3A60_P_2 */
8999   {
9000     { VEX_W_TABLE (VEX_W_3A60_P_2) },
9001   },
9002
9003   /* VEX_LEN_3A61_P_2 */
9004   {
9005     { VEX_W_TABLE (VEX_W_3A61_P_2) },
9006   },
9007
9008   /* VEX_LEN_3A62_P_2 */
9009   {
9010     { VEX_W_TABLE (VEX_W_3A62_P_2) },
9011   },
9012
9013   /* VEX_LEN_3A63_P_2 */
9014   {
9015     { VEX_W_TABLE (VEX_W_3A63_P_2) },
9016   },
9017
9018   /* VEX_LEN_3A6A_P_2 */
9019   {
9020     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9021   },
9022
9023   /* VEX_LEN_3A6B_P_2 */
9024   {
9025     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9026   },
9027
9028   /* VEX_LEN_3A6E_P_2 */
9029   {
9030     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9031   },
9032
9033   /* VEX_LEN_3A6F_P_2 */
9034   {
9035     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9036   },
9037
9038   /* VEX_LEN_3A7A_P_2 */
9039   {
9040     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9041   },
9042
9043   /* VEX_LEN_3A7B_P_2 */
9044   {
9045     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9046   },
9047
9048   /* VEX_LEN_3A7E_P_2 */
9049   {
9050     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9051   },
9052
9053   /* VEX_LEN_3A7F_P_2 */
9054   {
9055     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9056   },
9057
9058   /* VEX_LEN_3ADF_P_2 */
9059   {
9060     { VEX_W_TABLE (VEX_W_3ADF_P_2) },
9061   },
9062
9063   /* VEX_LEN_XOP_09_80 */
9064   {
9065     { "vfrczps",        { XM, EXxmm } },
9066     { "vfrczps",        { XM, EXymmq } },
9067   },
9068
9069   /* VEX_LEN_XOP_09_81 */
9070   {
9071     { "vfrczpd",        { XM, EXxmm } },
9072     { "vfrczpd",        { XM, EXymmq } },
9073   },
9074 };
9075
9076 static const struct dis386 vex_w_table[][2] = {
9077   {
9078     /* VEX_W_10_P_0 */
9079     { "vmovups",        { XM, EXx } },
9080   },
9081   {
9082     /* VEX_W_10_P_1 */
9083     { "vmovss",         { XMVex, Vex128, EXd } },
9084   },
9085   {
9086     /* VEX_W_10_P_2 */
9087     { "vmovupd",        { XM, EXx } },
9088   },
9089   {
9090     /* VEX_W_10_P_3 */
9091     { "vmovsd",         { XMVex, Vex128, EXq } },
9092   },
9093   {
9094     /* VEX_W_11_P_0 */
9095     { "vmovups",        { EXxS, XM } },
9096   },
9097   {
9098     /* VEX_W_11_P_1 */
9099     { "vmovss",         { EXdVexS, Vex128, XM } },
9100   },
9101   {
9102     /* VEX_W_11_P_2 */
9103     { "vmovupd",        { EXxS, XM } },
9104   },
9105   {
9106     /* VEX_W_11_P_3 */
9107     { "vmovsd",         { EXqVexS, Vex128, XM } },
9108   },
9109   {
9110     /* VEX_W_12_P_0_M_0 */
9111     { "vmovlps",        { XM, Vex128, EXq } },
9112   },
9113   {
9114     /* VEX_W_12_P_0_M_1 */
9115     { "vmovhlps",       { XM, Vex128, EXq } },
9116   },
9117   {
9118     /* VEX_W_12_P_1 */
9119     { "vmovsldup",      { XM, EXx } },
9120   },
9121   {
9122     /* VEX_W_12_P_2 */
9123     { "vmovlpd",        { XM, Vex128, EXq } },
9124   },
9125   {
9126     /* VEX_W_12_P_3 */
9127     { "vmovddup",       { XM, EXymmq } },
9128   },
9129   {
9130     /* VEX_W_13_M_0 */
9131     { "vmovlpX",        { EXq, XM } },
9132   },
9133   {
9134     /* VEX_W_14 */
9135     { "vunpcklpX",      { XM, Vex, EXx } },
9136   },
9137   {
9138     /* VEX_W_15 */
9139     { "vunpckhpX",      { XM, Vex, EXx } },
9140   },
9141   {
9142     /* VEX_W_16_P_0_M_0 */
9143     { "vmovhps",        { XM, Vex128, EXq } },
9144   },
9145   {
9146     /* VEX_W_16_P_0_M_1 */
9147     { "vmovlhps",       { XM, Vex128, EXq } },
9148   },
9149   {
9150     /* VEX_W_16_P_1 */
9151     { "vmovshdup",      { XM, EXx } },
9152   },
9153   {
9154     /* VEX_W_16_P_2 */
9155     { "vmovhpd",        { XM, Vex128, EXq } },
9156   },
9157   {
9158     /* VEX_W_17_M_0 */
9159     { "vmovhpX",        { EXq, XM } },
9160   },
9161   {
9162     /* VEX_W_28 */
9163     { "vmovapX",        { XM, EXx } },
9164   },
9165   {
9166     /* VEX_W_29 */
9167     { "vmovapX",        { EXxS, XM } },
9168   },
9169   {
9170     /* VEX_W_2B_M_0 */
9171     { "vmovntpX",       { Mx, XM } },
9172   },
9173   {
9174     /* VEX_W_2E_P_0 */
9175     { "vucomiss",       { XM, EXd } },
9176   },
9177   {
9178     /* VEX_W_2E_P_2 */
9179     { "vucomisd",       { XM, EXq } },
9180   },
9181   {
9182     /* VEX_W_2F_P_0 */
9183     { "vcomiss",        { XM, EXd } },
9184   },
9185   {
9186     /* VEX_W_2F_P_2 */
9187     { "vcomisd",        { XM, EXq } },
9188   },
9189   {
9190     /* VEX_W_50_M_0 */
9191     { "vmovmskpX",      { Gdq, XS } },
9192   },
9193   {
9194     /* VEX_W_51_P_0 */
9195     { "vsqrtps",        { XM, EXx } },
9196   },
9197   {
9198     /* VEX_W_51_P_1 */
9199     { "vsqrtss",        { XM, Vex128, EXd } },
9200   },
9201   {
9202     /* VEX_W_51_P_2  */
9203     { "vsqrtpd",        { XM, EXx } },
9204   },
9205   {
9206     /* VEX_W_51_P_3 */
9207     { "vsqrtsd",        { XM, Vex128, EXq } },
9208   },
9209   {
9210     /* VEX_W_52_P_0 */
9211     { "vrsqrtps",       { XM, EXx } },
9212   },
9213   {
9214     /* VEX_W_52_P_1 */
9215     { "vrsqrtss",       { XM, Vex128, EXd } },
9216   },
9217   {
9218     /* VEX_W_53_P_0  */
9219     { "vrcpps",         { XM, EXx } },
9220   },
9221   {
9222     /* VEX_W_53_P_1  */
9223     { "vrcpss",         { XM, Vex128, EXd } },
9224   },
9225   {
9226     /* VEX_W_58_P_0  */
9227     { "vaddps",         { XM, Vex, EXx } },
9228   },
9229   {
9230     /* VEX_W_58_P_1  */
9231     { "vaddss",         { XM, Vex128, EXd } },
9232   },
9233   {
9234     /* VEX_W_58_P_2  */
9235     { "vaddpd",         { XM, Vex, EXx } },
9236   },
9237   {
9238     /* VEX_W_58_P_3  */
9239     { "vaddsd",         { XM, Vex128, EXq } },
9240   },
9241   {
9242     /* VEX_W_59_P_0  */
9243     { "vmulps",         { XM, Vex, EXx } },
9244   },
9245   {
9246     /* VEX_W_59_P_1  */
9247     { "vmulss",         { XM, Vex128, EXd } },
9248   },
9249   {
9250     /* VEX_W_59_P_2  */
9251     { "vmulpd",         { XM, Vex, EXx } },
9252   },
9253   {
9254     /* VEX_W_59_P_3  */
9255     { "vmulsd",         { XM, Vex128, EXq } },
9256   },
9257   {
9258     /* VEX_W_5A_P_0  */
9259     { "vcvtps2pd",      { XM, EXxmmq } },
9260   },
9261   {
9262     /* VEX_W_5A_P_1  */
9263     { "vcvtss2sd",      { XM, Vex128, EXd } },
9264   },
9265   {
9266     /* VEX_W_5A_P_3  */
9267     { "vcvtsd2ss",      { XM, Vex128, EXq } },
9268   },
9269   {
9270     /* VEX_W_5B_P_0  */
9271     { "vcvtdq2ps",      { XM, EXx } },
9272   },
9273   {
9274     /* VEX_W_5B_P_1  */
9275     { "vcvttps2dq",     { XM, EXx } },
9276   },
9277   {
9278     /* VEX_W_5B_P_2  */
9279     { "vcvtps2dq",      { XM, EXx } },
9280   },
9281   {
9282     /* VEX_W_5C_P_0  */
9283     { "vsubps",         { XM, Vex, EXx } },
9284   },
9285   {
9286     /* VEX_W_5C_P_1  */
9287     { "vsubss",         { XM, Vex128, EXd } },
9288   },
9289   {
9290     /* VEX_W_5C_P_2  */
9291     { "vsubpd",         { XM, Vex, EXx } },
9292   },
9293   {
9294     /* VEX_W_5C_P_3  */
9295     { "vsubsd",         { XM, Vex128, EXq } },
9296   },
9297   {
9298     /* VEX_W_5D_P_0  */
9299     { "vminps",         { XM, Vex, EXx } },
9300   },
9301   {
9302     /* VEX_W_5D_P_1  */
9303     { "vminss",         { XM, Vex128, EXd } },
9304   },
9305   {
9306     /* VEX_W_5D_P_2  */
9307     { "vminpd",         { XM, Vex, EXx } },
9308   },
9309   {
9310     /* VEX_W_5D_P_3  */
9311     { "vminsd",         { XM, Vex128, EXq } },
9312   },
9313   {
9314     /* VEX_W_5E_P_0  */
9315     { "vdivps",         { XM, Vex, EXx } },
9316   },
9317   {
9318     /* VEX_W_5E_P_1  */
9319     { "vdivss",         { XM, Vex128, EXd } },
9320   },
9321   {
9322     /* VEX_W_5E_P_2  */
9323     { "vdivpd",         { XM, Vex, EXx } },
9324   },
9325   {
9326     /* VEX_W_5E_P_3  */
9327     { "vdivsd",         { XM, Vex128, EXq } },
9328   },
9329   {
9330     /* VEX_W_5F_P_0  */
9331     { "vmaxps",         { XM, Vex, EXx } },
9332   },
9333   {
9334     /* VEX_W_5F_P_1  */
9335     { "vmaxss",         { XM, Vex128, EXd } },
9336   },
9337   {
9338     /* VEX_W_5F_P_2  */
9339     { "vmaxpd",         { XM, Vex, EXx } },
9340   },
9341   {
9342     /* VEX_W_5F_P_3  */
9343     { "vmaxsd",         { XM, Vex128, EXq } },
9344   },
9345   {
9346     /* VEX_W_60_P_2  */
9347     { "vpunpcklbw",     { XM, Vex128, EXx } },
9348   },
9349   {
9350     /* VEX_W_61_P_2  */
9351     { "vpunpcklwd",     { XM, Vex128, EXx } },
9352   },
9353   {
9354     /* VEX_W_62_P_2  */
9355     { "vpunpckldq",     { XM, Vex128, EXx } },
9356   },
9357   {
9358     /* VEX_W_63_P_2  */
9359     { "vpacksswb",      { XM, Vex128, EXx } },
9360   },
9361   {
9362     /* VEX_W_64_P_2  */
9363     { "vpcmpgtb",       { XM, Vex128, EXx } },
9364   },
9365   {
9366     /* VEX_W_65_P_2  */
9367     { "vpcmpgtw",       { XM, Vex128, EXx } },
9368   },
9369   {
9370     /* VEX_W_66_P_2  */
9371     { "vpcmpgtd",       { XM, Vex128, EXx } },
9372   },
9373   {
9374     /* VEX_W_67_P_2  */
9375     { "vpackuswb",      { XM, Vex128, EXx } },
9376   },
9377   {
9378     /* VEX_W_68_P_2  */
9379     { "vpunpckhbw",     { XM, Vex128, EXx } },
9380   },
9381   {
9382     /* VEX_W_69_P_2  */
9383     { "vpunpckhwd",     { XM, Vex128, EXx } },
9384   },
9385   {
9386     /* VEX_W_6A_P_2  */
9387     { "vpunpckhdq",     { XM, Vex128, EXx } },
9388   },
9389   {
9390     /* VEX_W_6B_P_2  */
9391     { "vpackssdw",      { XM, Vex128, EXx } },
9392   },
9393   {
9394     /* VEX_W_6C_P_2  */
9395     { "vpunpcklqdq",    { XM, Vex128, EXx } },
9396   },
9397   {
9398     /* VEX_W_6D_P_2  */
9399     { "vpunpckhqdq",    { XM, Vex128, EXx } },
9400   },
9401   {
9402     /* VEX_W_6F_P_1  */
9403     { "vmovdqu",        { XM, EXx } },
9404   },
9405   {
9406     /* VEX_W_6F_P_2  */
9407     { "vmovdqa",        { XM, EXx } },
9408   },
9409   {
9410     /* VEX_W_70_P_1 */
9411     { "vpshufhw",       { XM, EXx, Ib } },
9412   },
9413   {
9414     /* VEX_W_70_P_2 */
9415     { "vpshufd",        { XM, EXx, Ib } },
9416   },
9417   {
9418     /* VEX_W_70_P_3 */
9419     { "vpshuflw",       { XM, EXx, Ib } },
9420   },
9421   {
9422     /* VEX_W_71_R_2_P_2  */
9423     { "vpsrlw",         { Vex128, XS, Ib } },
9424   },
9425   {
9426     /* VEX_W_71_R_4_P_2  */
9427     { "vpsraw",         { Vex128, XS, Ib } },
9428   },
9429   {
9430     /* VEX_W_71_R_6_P_2  */
9431     { "vpsllw",         { Vex128, XS, Ib } },
9432   },
9433   {
9434     /* VEX_W_72_R_2_P_2  */
9435     { "vpsrld",         { Vex128, XS, Ib } },
9436   },
9437   {
9438     /* VEX_W_72_R_4_P_2  */
9439     { "vpsrad",         { Vex128, XS, Ib } },
9440   },
9441   {
9442     /* VEX_W_72_R_6_P_2  */
9443     { "vpslld",         { Vex128, XS, Ib } },
9444   },
9445   {
9446     /* VEX_W_73_R_2_P_2  */
9447     { "vpsrlq",         { Vex128, XS, Ib } },
9448   },
9449   {
9450     /* VEX_W_73_R_3_P_2  */
9451     { "vpsrldq",        { Vex128, XS, Ib } },
9452   },
9453   {
9454     /* VEX_W_73_R_6_P_2  */
9455     { "vpsllq",         { Vex128, XS, Ib } },
9456   },
9457   {
9458     /* VEX_W_73_R_7_P_2  */
9459     { "vpslldq",        { Vex128, XS, Ib } },
9460   },
9461   {
9462     /* VEX_W_74_P_2 */
9463     { "vpcmpeqb",       { XM, Vex128, EXx } },
9464   },
9465   {
9466     /* VEX_W_75_P_2 */
9467     { "vpcmpeqw",       { XM, Vex128, EXx } },
9468   },
9469   {
9470     /* VEX_W_76_P_2 */
9471     { "vpcmpeqd",       { XM, Vex128, EXx } },
9472   },
9473   {
9474     /* VEX_W_77_P_0 */
9475     { "",               { VZERO } },
9476   },
9477   {
9478     /* VEX_W_7C_P_2 */
9479     { "vhaddpd",        { XM, Vex, EXx } },
9480   },
9481   {
9482     /* VEX_W_7C_P_3 */
9483     { "vhaddps",        { XM, Vex, EXx } },
9484   },
9485   {
9486     /* VEX_W_7D_P_2 */
9487     { "vhsubpd",        { XM, Vex, EXx } },
9488   },
9489   {
9490     /* VEX_W_7D_P_3 */
9491     { "vhsubps",        { XM, Vex, EXx } },
9492   },
9493   {
9494     /* VEX_W_7E_P_1 */
9495     { "vmovq",          { XM, EXq } },
9496   },
9497   {
9498     /* VEX_W_7F_P_1 */
9499     { "vmovdqu",        { EXxS, XM } },
9500   },
9501   {
9502     /* VEX_W_7F_P_2 */
9503     { "vmovdqa",        { EXxS, XM } },
9504   },
9505   {
9506     /* VEX_W_AE_R_2_M_0 */
9507     { "vldmxcsr",       { Md } },
9508   },
9509   {
9510     /* VEX_W_AE_R_3_M_0 */
9511     { "vstmxcsr",       { Md } },
9512   },
9513   {
9514     /* VEX_W_C2_P_0 */
9515     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9516   },
9517   {
9518     /* VEX_W_C2_P_1 */
9519     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
9520   },
9521   {
9522     /* VEX_W_C2_P_2 */
9523     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9524   },
9525   {
9526     /* VEX_W_C2_P_3 */
9527     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
9528   },
9529   {
9530     /* VEX_W_C4_P_2 */
9531     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9532   },
9533   {
9534     /* VEX_W_C5_P_2 */
9535     { "vpextrw",        { Gdq, XS, Ib } },
9536   },
9537   {
9538     /* VEX_W_D0_P_2 */
9539     { "vaddsubpd",      { XM, Vex, EXx } },
9540   },
9541   {
9542     /* VEX_W_D0_P_3 */
9543     { "vaddsubps",      { XM, Vex, EXx } },
9544   },
9545   {
9546     /* VEX_W_D1_P_2 */
9547     { "vpsrlw",         { XM, Vex128, EXx } },
9548   },
9549   {
9550     /* VEX_W_D2_P_2 */
9551     { "vpsrld",         { XM, Vex128, EXx } },
9552   },
9553   {
9554     /* VEX_W_D3_P_2 */
9555     { "vpsrlq",         { XM, Vex128, EXx } },
9556   },
9557   {
9558     /* VEX_W_D4_P_2 */
9559     { "vpaddq",         { XM, Vex128, EXx } },
9560   },
9561   {
9562     /* VEX_W_D5_P_2 */
9563     { "vpmullw",        { XM, Vex128, EXx } },
9564   },
9565   {
9566     /* VEX_W_D6_P_2 */
9567     { "vmovq",          { EXqS, XM } },
9568   },
9569   {
9570     /* VEX_W_D7_P_2_M_1 */
9571     { "vpmovmskb",      { Gdq, XS } },
9572   },
9573   {
9574     /* VEX_W_D8_P_2 */
9575     { "vpsubusb",       { XM, Vex128, EXx } },
9576   },
9577   {
9578     /* VEX_W_D9_P_2 */
9579     { "vpsubusw",       { XM, Vex128, EXx } },
9580   },
9581   {
9582     /* VEX_W_DA_P_2 */
9583     { "vpminub",        { XM, Vex128, EXx } },
9584   },
9585   {
9586     /* VEX_W_DB_P_2 */
9587     { "vpand",          { XM, Vex128, EXx } },
9588   },
9589   {
9590     /* VEX_W_DC_P_2 */
9591     { "vpaddusb",       { XM, Vex128, EXx } },
9592   },
9593   {
9594     /* VEX_W_DD_P_2 */
9595     { "vpaddusw",       { XM, Vex128, EXx } },
9596   },
9597   {
9598     /* VEX_W_DE_P_2 */
9599     { "vpmaxub",        { XM, Vex128, EXx } },
9600   },
9601   {
9602     /* VEX_W_DF_P_2 */
9603     { "vpandn",         { XM, Vex128, EXx } },
9604   },
9605   {
9606     /* VEX_W_E0_P_2  */
9607     { "vpavgb",         { XM, Vex128, EXx } },
9608   },
9609   {
9610     /* VEX_W_E1_P_2  */
9611     { "vpsraw",         { XM, Vex128, EXx } },
9612   },
9613   {
9614     /* VEX_W_E2_P_2  */
9615     { "vpsrad",         { XM, Vex128, EXx } },
9616   },
9617   {
9618     /* VEX_W_E3_P_2  */
9619     { "vpavgw",         { XM, Vex128, EXx } },
9620   },
9621   {
9622     /* VEX_W_E4_P_2  */
9623     { "vpmulhuw",       { XM, Vex128, EXx } },
9624   },
9625   {
9626     /* VEX_W_E5_P_2  */
9627     { "vpmulhw",        { XM, Vex128, EXx } },
9628   },
9629   {
9630     /* VEX_W_E6_P_1  */
9631     { "vcvtdq2pd",      { XM, EXxmmq } },
9632   },
9633   {
9634     /* VEX_W_E6_P_2  */
9635     { "vcvttpd2dq%XY",  { XMM, EXx } },
9636   },
9637   {
9638     /* VEX_W_E6_P_3  */
9639     { "vcvtpd2dq%XY",   { XMM, EXx } },
9640   },
9641   {
9642     /* VEX_W_E7_P_2_M_0 */
9643     { "vmovntdq",       { Mx, XM } },
9644   },
9645   {
9646     /* VEX_W_E8_P_2  */
9647     { "vpsubsb",        { XM, Vex128, EXx } },
9648   },
9649   {
9650     /* VEX_W_E9_P_2  */
9651     { "vpsubsw",        { XM, Vex128, EXx } },
9652   },
9653   {
9654     /* VEX_W_EA_P_2  */
9655     { "vpminsw",        { XM, Vex128, EXx } },
9656   },
9657   {
9658     /* VEX_W_EB_P_2  */
9659     { "vpor",           { XM, Vex128, EXx } },
9660   },
9661   {
9662     /* VEX_W_EC_P_2  */
9663     { "vpaddsb",        { XM, Vex128, EXx } },
9664   },
9665   {
9666     /* VEX_W_ED_P_2  */
9667     { "vpaddsw",        { XM, Vex128, EXx } },
9668   },
9669   {
9670     /* VEX_W_EE_P_2  */
9671     { "vpmaxsw",        { XM, Vex128, EXx } },
9672   },
9673   {
9674     /* VEX_W_EF_P_2  */
9675     { "vpxor",          { XM, Vex128, EXx } },
9676   },
9677   {
9678     /* VEX_W_F0_P_3_M_0 */
9679     { "vlddqu",         { XM, M } },
9680   },
9681   {
9682     /* VEX_W_F1_P_2 */
9683     { "vpsllw",         { XM, Vex128, EXx } },
9684   },
9685   {
9686     /* VEX_W_F2_P_2 */
9687     { "vpslld",         { XM, Vex128, EXx } },
9688   },
9689   {
9690     /* VEX_W_F3_P_2 */
9691     { "vpsllq",         { XM, Vex128, EXx } },
9692   },
9693   {
9694     /* VEX_W_F4_P_2 */
9695     { "vpmuludq",       { XM, Vex128, EXx } },
9696   },
9697   {
9698     /* VEX_W_F5_P_2 */
9699     { "vpmaddwd",       { XM, Vex128, EXx } },
9700   },
9701   {
9702     /* VEX_W_F6_P_2 */
9703     { "vpsadbw",        { XM, Vex128, EXx } },
9704   },
9705   {
9706     /* VEX_W_F7_P_2 */
9707     { "vmaskmovdqu",    { XM, XS } },
9708   },
9709   {
9710     /* VEX_W_F8_P_2 */
9711     { "vpsubb",         { XM, Vex128, EXx } },
9712   },
9713   {
9714     /* VEX_W_F9_P_2 */
9715     { "vpsubw",         { XM, Vex128, EXx } },
9716   },
9717   {
9718     /* VEX_W_FA_P_2 */
9719     { "vpsubd",         { XM, Vex128, EXx } },
9720   },
9721   {
9722     /* VEX_W_FB_P_2 */
9723     { "vpsubq",         { XM, Vex128, EXx } },
9724   },
9725   {
9726     /* VEX_W_FC_P_2 */
9727     { "vpaddb",         { XM, Vex128, EXx } },
9728   },
9729   {
9730     /* VEX_W_FD_P_2 */
9731     { "vpaddw",         { XM, Vex128, EXx } },
9732   },
9733   {
9734     /* VEX_W_FE_P_2 */
9735     { "vpaddd",         { XM, Vex128, EXx } },
9736   },
9737   {
9738     /* VEX_W_3800_P_2  */
9739     { "vpshufb",        { XM, Vex128, EXx } },
9740   },
9741   {
9742     /* VEX_W_3801_P_2  */
9743     { "vphaddw",        { XM, Vex128, EXx } },
9744   },
9745   {
9746     /* VEX_W_3802_P_2  */
9747     { "vphaddd",        { XM, Vex128, EXx } },
9748   },
9749   {
9750     /* VEX_W_3803_P_2  */
9751     { "vphaddsw",       { XM, Vex128, EXx } },
9752   },
9753   {
9754     /* VEX_W_3804_P_2  */
9755     { "vpmaddubsw",     { XM, Vex128, EXx } },
9756   },
9757   {
9758     /* VEX_W_3805_P_2  */
9759     { "vphsubw",        { XM, Vex128, EXx } },
9760   },
9761   {
9762     /* VEX_W_3806_P_2  */
9763     { "vphsubd",        { XM, Vex128, EXx } },
9764   },
9765   {
9766     /* VEX_W_3807_P_2  */
9767     { "vphsubsw",       { XM, Vex128, EXx } },
9768   },
9769   {
9770     /* VEX_W_3808_P_2  */
9771     { "vpsignb",        { XM, Vex128, EXx } },
9772   },
9773   {
9774     /* VEX_W_3809_P_2  */
9775     { "vpsignw",        { XM, Vex128, EXx } },
9776   },
9777   {
9778     /* VEX_W_380A_P_2  */
9779     { "vpsignd",        { XM, Vex128, EXx } },
9780   },
9781   {
9782     /* VEX_W_380B_P_2  */
9783     { "vpmulhrsw",      { XM, Vex128, EXx } },
9784   },
9785   {
9786     /* VEX_W_380C_P_2  */
9787     { "vpermilps",      { XM, Vex, EXx } },
9788   },
9789   {
9790     /* VEX_W_380D_P_2  */
9791     { "vpermilpd",      { XM, Vex, EXx } },
9792   },
9793   {
9794     /* VEX_W_380E_P_2  */
9795     { "vtestps",        { XM, EXx } },
9796   },
9797   {
9798     /* VEX_W_380F_P_2  */
9799     { "vtestpd",        { XM, EXx } },
9800   },
9801   {
9802     /* VEX_W_3817_P_2 */
9803     { "vptest",         { XM, EXx } },
9804   },
9805   {
9806     /* VEX_W_3818_P_2_M_0 */
9807     { "vbroadcastss",   { XM, Md } },
9808   },
9809   {
9810     /* VEX_W_3819_P_2_M_0 */
9811     { "vbroadcastsd",   { XM, Mq } },
9812   },
9813   {
9814     /* VEX_W_381A_P_2_M_0 */
9815     { "vbroadcastf128", { XM, Mxmm } },
9816   },
9817   {
9818     /* VEX_W_381C_P_2 */
9819     { "vpabsb",         { XM, EXx } },
9820   },
9821   {
9822     /* VEX_W_381D_P_2 */
9823     { "vpabsw",         { XM, EXx } },
9824   },
9825   {
9826     /* VEX_W_381E_P_2 */
9827     { "vpabsd",         { XM, EXx } },
9828   },
9829   {
9830     /* VEX_W_3820_P_2 */
9831     { "vpmovsxbw",      { XM, EXq } },
9832   },
9833   {
9834     /* VEX_W_3821_P_2 */
9835     { "vpmovsxbd",      { XM, EXd } },
9836   },
9837   {
9838     /* VEX_W_3822_P_2 */
9839     { "vpmovsxbq",      { XM, EXw } },
9840   },
9841   {
9842     /* VEX_W_3823_P_2 */
9843     { "vpmovsxwd",      { XM, EXq } },
9844   },
9845   {
9846     /* VEX_W_3824_P_2 */
9847     { "vpmovsxwq",      { XM, EXd } },
9848   },
9849   {
9850     /* VEX_W_3825_P_2 */
9851     { "vpmovsxdq",      { XM, EXq } },
9852   },
9853   {
9854     /* VEX_W_3828_P_2 */
9855     { "vpmuldq",        { XM, Vex128, EXx } },
9856   },
9857   {
9858     /* VEX_W_3829_P_2 */
9859     { "vpcmpeqq",       { XM, Vex128, EXx } },
9860   },
9861   {
9862     /* VEX_W_382A_P_2_M_0 */
9863     { "vmovntdqa",      { XM, Mx } },
9864   },
9865   {
9866     /* VEX_W_382B_P_2 */
9867     { "vpackusdw",      { XM, Vex128, EXx } },
9868   },
9869   {
9870     /* VEX_W_382C_P_2_M_0 */
9871     { "vmaskmovps",     { XM, Vex, Mx } },
9872   },
9873   {
9874     /* VEX_W_382D_P_2_M_0 */
9875     { "vmaskmovpd",     { XM, Vex, Mx } },
9876   },
9877   {
9878     /* VEX_W_382E_P_2_M_0 */
9879     { "vmaskmovps",     { Mx, Vex, XM } },
9880   },
9881   {
9882     /* VEX_W_382F_P_2_M_0 */
9883     { "vmaskmovpd",     { Mx, Vex, XM } },
9884   },
9885   {
9886     /* VEX_W_3830_P_2 */
9887     { "vpmovzxbw",      { XM, EXq } },
9888   },
9889   {
9890     /* VEX_W_3831_P_2 */
9891     { "vpmovzxbd",      { XM, EXd } },
9892   },
9893   {
9894     /* VEX_W_3832_P_2 */
9895     { "vpmovzxbq",      { XM, EXw } },
9896   },
9897   {
9898     /* VEX_W_3833_P_2 */
9899     { "vpmovzxwd",      { XM, EXq } },
9900   },
9901   {
9902     /* VEX_W_3834_P_2 */
9903     { "vpmovzxwq",      { XM, EXd } },
9904   },
9905   {
9906     /* VEX_W_3835_P_2 */
9907     { "vpmovzxdq",      { XM, EXq } },
9908   },
9909   {
9910     /* VEX_W_3837_P_2 */
9911     { "vpcmpgtq",       { XM, Vex128, EXx } },
9912   },
9913   {
9914     /* VEX_W_3838_P_2 */
9915     { "vpminsb",        { XM, Vex128, EXx } },
9916   },
9917   {
9918     /* VEX_W_3839_P_2 */
9919     { "vpminsd",        { XM, Vex128, EXx } },
9920   },
9921   {
9922     /* VEX_W_383A_P_2 */
9923     { "vpminuw",        { XM, Vex128, EXx } },
9924   },
9925   {
9926     /* VEX_W_383B_P_2 */
9927     { "vpminud",        { XM, Vex128, EXx } },
9928   },
9929   {
9930     /* VEX_W_383C_P_2 */
9931     { "vpmaxsb",        { XM, Vex128, EXx } },
9932   },
9933   {
9934     /* VEX_W_383D_P_2 */
9935     { "vpmaxsd",        { XM, Vex128, EXx } },
9936   },
9937   {
9938     /* VEX_W_383E_P_2 */
9939     { "vpmaxuw",        { XM, Vex128, EXx } },
9940   },
9941   {
9942     /* VEX_W_383F_P_2 */
9943     { "vpmaxud",        { XM, Vex128, EXx } },
9944   },
9945   {
9946     /* VEX_W_3840_P_2 */
9947     { "vpmulld",        { XM, Vex128, EXx } },
9948   },
9949   {
9950     /* VEX_W_3841_P_2 */
9951     { "vphminposuw",    { XM, EXx } },
9952   },
9953   {
9954     /* VEX_W_38DB_P_2 */
9955     { "vaesimc",        { XM, EXx } },
9956   },
9957   {
9958     /* VEX_W_38DC_P_2 */
9959     { "vaesenc",        { XM, Vex128, EXx } },
9960   },
9961   {
9962     /* VEX_W_38DD_P_2 */
9963     { "vaesenclast",    { XM, Vex128, EXx } },
9964   },
9965   {
9966     /* VEX_W_38DE_P_2 */
9967     { "vaesdec",        { XM, Vex128, EXx } },
9968   },
9969   {
9970     /* VEX_W_38DF_P_2 */
9971     { "vaesdeclast",    { XM, Vex128, EXx } },
9972   },
9973   {
9974     /* VEX_W_3A04_P_2 */
9975     { "vpermilps",      { XM, EXx, Ib } },
9976   },
9977   {
9978     /* VEX_W_3A05_P_2 */
9979     { "vpermilpd",      { XM, EXx, Ib } },
9980   },
9981   {
9982     /* VEX_W_3A06_P_2 */
9983     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
9984   },
9985   {
9986     /* VEX_W_3A08_P_2 */
9987     { "vroundps",       { XM, EXx, Ib } },
9988   },
9989   {
9990     /* VEX_W_3A09_P_2 */
9991     { "vroundpd",       { XM, EXx, Ib } },
9992   },
9993   {
9994     /* VEX_W_3A0A_P_2 */
9995     { "vroundss",       { XM, Vex128, EXd, Ib } },
9996   },
9997   {
9998     /* VEX_W_3A0B_P_2 */
9999     { "vroundsd",       { XM, Vex128, EXq, Ib } },
10000   },
10001   {
10002     /* VEX_W_3A0C_P_2 */
10003     { "vblendps",       { XM, Vex, EXx, Ib } },
10004   },
10005   {
10006     /* VEX_W_3A0D_P_2 */
10007     { "vblendpd",       { XM, Vex, EXx, Ib } },
10008   },
10009   {
10010     /* VEX_W_3A0E_P_2 */
10011     { "vpblendw",       { XM, Vex128, EXx, Ib } },
10012   },
10013   {
10014     /* VEX_W_3A0F_P_2 */
10015     { "vpalignr",       { XM, Vex128, EXx, Ib } },
10016   },
10017   {
10018     /* VEX_W_3A14_P_2 */
10019     { "vpextrb",        { Edqb, XM, Ib } },
10020   },
10021   {
10022     /* VEX_W_3A15_P_2 */
10023     { "vpextrw",        { Edqw, XM, Ib } },
10024   },
10025   {
10026     /* VEX_W_3A18_P_2 */
10027     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10028   },
10029   {
10030     /* VEX_W_3A19_P_2 */
10031     { "vextractf128",   { EXxmm, XM, Ib } },
10032   },
10033   {
10034     /* VEX_W_3A20_P_2 */
10035     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10036   },
10037   {
10038     /* VEX_W_3A21_P_2 */
10039     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10040   },
10041   {
10042     /* VEX_W_3A40_P_2 */
10043     { "vdpps",          { XM, Vex, EXx, Ib } },
10044   },
10045   {
10046     /* VEX_W_3A41_P_2 */
10047     { "vdppd",          { XM, Vex128, EXx, Ib } },
10048   },
10049   {
10050     /* VEX_W_3A42_P_2 */
10051     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
10052   },
10053   {
10054     /* VEX_W_3A44_P_2 */
10055     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10056   },
10057   {
10058     /* VEX_W_3A4A_P_2 */
10059     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10060   },
10061   {
10062     /* VEX_W_3A4B_P_2 */
10063     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10064   },
10065   {
10066     /* VEX_W_3A4C_P_2 */
10067     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
10068   },
10069   {
10070     /* VEX_W_3A60_P_2 */
10071     { "vpcmpestrm",     { XM, EXx, Ib } },
10072   },
10073   {
10074     /* VEX_W_3A61_P_2 */
10075     { "vpcmpestri",     { XM, EXx, Ib } },
10076   },
10077   {
10078     /* VEX_W_3A62_P_2 */
10079     { "vpcmpistrm",     { XM, EXx, Ib } },
10080   },
10081   {
10082     /* VEX_W_3A63_P_2 */
10083     { "vpcmpistri",     { XM, EXx, Ib } },
10084   },
10085   {
10086     /* VEX_W_3ADF_P_2 */
10087     { "vaeskeygenassist", { XM, EXx, Ib } },
10088   },
10089 };
10090
10091 static const struct dis386 mod_table[][2] = {
10092   {
10093     /* MOD_8D */
10094     { "leaS",           { Gv, M } },
10095   },
10096   {
10097     /* MOD_0F01_REG_0 */
10098     { X86_64_TABLE (X86_64_0F01_REG_0) },
10099     { RM_TABLE (RM_0F01_REG_0) },
10100   },
10101   {
10102     /* MOD_0F01_REG_1 */
10103     { X86_64_TABLE (X86_64_0F01_REG_1) },
10104     { RM_TABLE (RM_0F01_REG_1) },
10105   },
10106   {
10107     /* MOD_0F01_REG_2 */
10108     { X86_64_TABLE (X86_64_0F01_REG_2) },
10109     { RM_TABLE (RM_0F01_REG_2) },
10110   },
10111   {
10112     /* MOD_0F01_REG_3 */
10113     { X86_64_TABLE (X86_64_0F01_REG_3) },
10114     { RM_TABLE (RM_0F01_REG_3) },
10115   },
10116   {
10117     /* MOD_0F01_REG_7 */
10118     { "invlpg",         { Mb } },
10119     { RM_TABLE (RM_0F01_REG_7) },
10120   },
10121   {
10122     /* MOD_0F12_PREFIX_0 */
10123     { "movlps",         { XM, EXq } },
10124     { "movhlps",        { XM, EXq } },
10125   },
10126   {
10127     /* MOD_0F13 */
10128     { "movlpX",         { EXq, XM } },
10129   },
10130   {
10131     /* MOD_0F16_PREFIX_0 */
10132     { "movhps",         { XM, EXq } },
10133     { "movlhps",        { XM, EXq } },
10134   },
10135   {
10136     /* MOD_0F17 */
10137     { "movhpX",         { EXq, XM } },
10138   },
10139   {
10140     /* MOD_0F18_REG_0 */
10141     { "prefetchnta",    { Mb } },
10142   },
10143   {
10144     /* MOD_0F18_REG_1 */
10145     { "prefetcht0",     { Mb } },
10146   },
10147   {
10148     /* MOD_0F18_REG_2 */
10149     { "prefetcht1",     { Mb } },
10150   },
10151   {
10152     /* MOD_0F18_REG_3 */
10153     { "prefetcht2",     { Mb } },
10154   },
10155   {
10156     /* MOD_0F20 */
10157     { Bad_Opcode },
10158     { "movZ",           { Rm, Cm } },
10159   },
10160   {
10161     /* MOD_0F21 */
10162     { Bad_Opcode },
10163     { "movZ",           { Rm, Dm } },
10164   },
10165   {
10166     /* MOD_0F22 */
10167     { Bad_Opcode },
10168     { "movZ",           { Cm, Rm } },
10169   },
10170   {
10171     /* MOD_0F23 */
10172     { Bad_Opcode },
10173     { "movZ",           { Dm, Rm } },
10174   },
10175   {
10176     /* MOD_0F24 */
10177     { Bad_Opcode },
10178     { "movL",           { Rd, Td } },
10179   },
10180   {
10181     /* MOD_0F26 */
10182     { Bad_Opcode },
10183     { "movL",           { Td, Rd } },
10184   },
10185   {
10186     /* MOD_0F2B_PREFIX_0 */
10187     {"movntps",         { Mx, XM } },
10188   },
10189   {
10190     /* MOD_0F2B_PREFIX_1 */
10191     {"movntss",         { Md, XM } },
10192   },
10193   {
10194     /* MOD_0F2B_PREFIX_2 */
10195     {"movntpd",         { Mx, XM } },
10196   },
10197   {
10198     /* MOD_0F2B_PREFIX_3 */
10199     {"movntsd",         { Mq, XM } },
10200   },
10201   {
10202     /* MOD_0F51 */
10203     { Bad_Opcode },
10204     { "movmskpX",       { Gdq, XS } },
10205   },
10206   {
10207     /* MOD_0F71_REG_2 */
10208     { Bad_Opcode },
10209     { "psrlw",          { MS, Ib } },
10210   },
10211   {
10212     /* MOD_0F71_REG_4 */
10213     { Bad_Opcode },
10214     { "psraw",          { MS, Ib } },
10215   },
10216   {
10217     /* MOD_0F71_REG_6 */
10218     { Bad_Opcode },
10219     { "psllw",          { MS, Ib } },
10220   },
10221   {
10222     /* MOD_0F72_REG_2 */
10223     { Bad_Opcode },
10224     { "psrld",          { MS, Ib } },
10225   },
10226   {
10227     /* MOD_0F72_REG_4 */
10228     { Bad_Opcode },
10229     { "psrad",          { MS, Ib } },
10230   },
10231   {
10232     /* MOD_0F72_REG_6 */
10233     { Bad_Opcode },
10234     { "pslld",          { MS, Ib } },
10235   },
10236   {
10237     /* MOD_0F73_REG_2 */
10238     { Bad_Opcode },
10239     { "psrlq",          { MS, Ib } },
10240   },
10241   {
10242     /* MOD_0F73_REG_3 */
10243     { Bad_Opcode },
10244     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10245   },
10246   {
10247     /* MOD_0F73_REG_6 */
10248     { Bad_Opcode },
10249     { "psllq",          { MS, Ib } },
10250   },
10251   {
10252     /* MOD_0F73_REG_7 */
10253     { Bad_Opcode },
10254     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10255   },
10256   {
10257     /* MOD_0FAE_REG_0 */
10258     { "fxsave",         { FXSAVE } },
10259   },
10260   {
10261     /* MOD_0FAE_REG_1 */
10262     { "fxrstor",        { FXSAVE } },
10263   },
10264   {
10265     /* MOD_0FAE_REG_2 */
10266     { "ldmxcsr",        { Md } },
10267   },
10268   {
10269     /* MOD_0FAE_REG_3 */
10270     { "stmxcsr",        { Md } },
10271   },
10272   {
10273     /* MOD_0FAE_REG_4 */
10274     { "xsave",          { FXSAVE } },
10275   },
10276   {
10277     /* MOD_0FAE_REG_5 */
10278     { "xrstor",         { FXSAVE } },
10279     { RM_TABLE (RM_0FAE_REG_5) },
10280   },
10281   {
10282     /* MOD_0FAE_REG_6 */
10283     { Bad_Opcode },
10284     { RM_TABLE (RM_0FAE_REG_6) },
10285   },
10286   {
10287     /* MOD_0FAE_REG_7 */
10288     { "clflush",        { Mb } },
10289     { RM_TABLE (RM_0FAE_REG_7) },
10290   },
10291   {
10292     /* MOD_0FB2 */
10293     { "lssS",           { Gv, Mp } },
10294   },
10295   {
10296     /* MOD_0FB4 */
10297     { "lfsS",           { Gv, Mp } },
10298   },
10299   {
10300     /* MOD_0FB5 */
10301     { "lgsS",           { Gv, Mp } },
10302   },
10303   {
10304     /* MOD_0FC7_REG_6 */
10305     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10306   },
10307   {
10308     /* MOD_0FC7_REG_7 */
10309     { "vmptrst",        { Mq } },
10310   },
10311   {
10312     /* MOD_0FD7 */
10313     { Bad_Opcode },
10314     { "pmovmskb",       { Gdq, MS } },
10315   },
10316   {
10317     /* MOD_0FE7_PREFIX_2 */
10318     { "movntdq",        { Mx, XM } },
10319   },
10320   {
10321     /* MOD_0FF0_PREFIX_3 */
10322     { "lddqu",          { XM, M } },
10323   },
10324   {
10325     /* MOD_0F382A_PREFIX_2 */
10326     { "movntdqa",       { XM, Mx } },
10327   },
10328   {
10329     /* MOD_62_32BIT */
10330     { "bound{S|}",      { Gv, Ma } },
10331   },
10332   {
10333     /* MOD_C4_32BIT */
10334     { "lesS",           { Gv, Mp } },
10335     { VEX_C4_TABLE (VEX_0F) },
10336   },
10337   {
10338     /* MOD_C5_32BIT */
10339     { "ldsS",           { Gv, Mp } },
10340     { VEX_C5_TABLE (VEX_0F) },
10341   },
10342   {
10343     /* MOD_VEX_12_PREFIX_0 */
10344     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
10345     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
10346   },
10347   {
10348     /* MOD_VEX_13 */
10349     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
10350   },
10351   {
10352     /* MOD_VEX_16_PREFIX_0 */
10353     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
10354     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
10355   },
10356   {
10357     /* MOD_VEX_17 */
10358     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
10359   },
10360   {
10361     /* MOD_VEX_2B */
10362     { VEX_W_TABLE (VEX_W_2B_M_0) },
10363   },
10364   {
10365     /* MOD_VEX_50 */
10366     { Bad_Opcode },
10367     { VEX_W_TABLE (VEX_W_50_M_0) },
10368   },
10369   {
10370     /* MOD_VEX_71_REG_2 */
10371     { Bad_Opcode },
10372     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
10373   },
10374   {
10375     /* MOD_VEX_71_REG_4 */
10376     { Bad_Opcode },
10377     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
10378   },
10379   {
10380     /* MOD_VEX_71_REG_6 */
10381     { Bad_Opcode },
10382     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
10383   },
10384   {
10385     /* MOD_VEX_72_REG_2 */
10386     { Bad_Opcode },
10387     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
10388   },
10389   {
10390     /* MOD_VEX_72_REG_4 */
10391     { Bad_Opcode },
10392     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
10393   },
10394   {
10395     /* MOD_VEX_72_REG_6 */
10396     { Bad_Opcode },
10397     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
10398   },
10399   {
10400     /* MOD_VEX_73_REG_2 */
10401     { Bad_Opcode },
10402     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
10403   },
10404   {
10405     /* MOD_VEX_73_REG_3 */
10406     { Bad_Opcode },
10407     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
10408   },
10409   {
10410     /* MOD_VEX_73_REG_6 */
10411     { Bad_Opcode },
10412     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
10413   },
10414   {
10415     /* MOD_VEX_73_REG_7 */
10416     { Bad_Opcode },
10417     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
10418   },
10419   {
10420     /* MOD_VEX_AE_REG_2 */
10421     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
10422   },
10423   {
10424     /* MOD_VEX_AE_REG_3 */
10425     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
10426   },
10427   {
10428     /* MOD_VEX_D7_PREFIX_2 */
10429     { Bad_Opcode },
10430     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
10431   },
10432   {
10433     /* MOD_VEX_E7_PREFIX_2 */
10434     { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
10435   },
10436   {
10437     /* MOD_VEX_F0_PREFIX_3 */
10438     { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
10439   },
10440   {
10441     /* MOD_VEX_3818_PREFIX_2 */
10442     { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
10443   },
10444   {
10445     /* MOD_VEX_3819_PREFIX_2 */
10446     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
10447   },
10448   {
10449     /* MOD_VEX_381A_PREFIX_2 */
10450     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
10451   },
10452   {
10453     /* MOD_VEX_382A_PREFIX_2 */
10454     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
10455   },
10456   {
10457     /* MOD_VEX_382C_PREFIX_2 */
10458     { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
10459   },
10460   {
10461     /* MOD_VEX_382D_PREFIX_2 */
10462     { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
10463   },
10464   {
10465     /* MOD_VEX_382E_PREFIX_2 */
10466     { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
10467   },
10468   {
10469     /* MOD_VEX_382F_PREFIX_2 */
10470     { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
10471   },
10472 };
10473
10474 static const struct dis386 rm_table[][8] = {
10475   {
10476     /* RM_0F01_REG_0 */
10477     { Bad_Opcode },
10478     { "vmcall",         { Skip_MODRM } },
10479     { "vmlaunch",       { Skip_MODRM } },
10480     { "vmresume",       { Skip_MODRM } },
10481     { "vmxoff",         { Skip_MODRM } },
10482   },
10483   {
10484     /* RM_0F01_REG_1 */
10485     { "monitor",        { { OP_Monitor, 0 } } },
10486     { "mwait",          { { OP_Mwait, 0 } } },
10487   },
10488   {
10489     /* RM_0F01_REG_2 */
10490     { "xgetbv",         { Skip_MODRM } },
10491     { "xsetbv",         { Skip_MODRM } },
10492   },
10493   {
10494     /* RM_0F01_REG_3 */
10495     { "vmrun",          { Skip_MODRM } },
10496     { "vmmcall",        { Skip_MODRM } },
10497     { "vmload",         { Skip_MODRM } },
10498     { "vmsave",         { Skip_MODRM } },
10499     { "stgi",           { Skip_MODRM } },
10500     { "clgi",           { Skip_MODRM } },
10501     { "skinit",         { Skip_MODRM } },
10502     { "invlpga",        { Skip_MODRM } },
10503   },
10504   {
10505     /* RM_0F01_REG_7 */
10506     { "swapgs",         { Skip_MODRM } },
10507     { "rdtscp",         { Skip_MODRM } },
10508   },
10509   {
10510     /* RM_0FAE_REG_5 */
10511     { "lfence",         { Skip_MODRM } },
10512   },
10513   {
10514     /* RM_0FAE_REG_6 */
10515     { "mfence",         { Skip_MODRM } },
10516   },
10517   {
10518     /* RM_0FAE_REG_7 */
10519     { "sfence",         { Skip_MODRM } },
10520   },
10521 };
10522
10523 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10524
10525 /* We use the high bit to indicate different name for the same
10526    prefix.  */
10527 #define ADDR16_PREFIX   (0x67 | 0x100)
10528 #define ADDR32_PREFIX   (0x67 | 0x200)
10529 #define DATA16_PREFIX   (0x66 | 0x100)
10530 #define DATA32_PREFIX   (0x66 | 0x200)
10531 #define REP_PREFIX      (0xf3 | 0x100)
10532
10533 static int
10534 ckprefix (void)
10535 {
10536   int newrex, i, length;
10537   rex = 0;
10538   rex_ignored = 0;
10539   prefixes = 0;
10540   used_prefixes = 0;
10541   rex_used = 0;
10542   last_lock_prefix = -1;
10543   last_repz_prefix = -1;
10544   last_repnz_prefix = -1;
10545   last_data_prefix = -1;
10546   last_addr_prefix = -1;
10547   last_rex_prefix = -1;
10548   last_seg_prefix = -1;
10549   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10550     all_prefixes[i] = 0;
10551   i = 0;
10552   length = 0;
10553   /* The maximum instruction length is 15bytes.  */
10554   while (length < MAX_CODE_LENGTH - 1)
10555     {
10556       FETCH_DATA (the_info, codep + 1);
10557       newrex = 0;
10558       switch (*codep)
10559         {
10560         /* REX prefixes family.  */
10561         case 0x40:
10562         case 0x41:
10563         case 0x42:
10564         case 0x43:
10565         case 0x44:
10566         case 0x45:
10567         case 0x46:
10568         case 0x47:
10569         case 0x48:
10570         case 0x49:
10571         case 0x4a:
10572         case 0x4b:
10573         case 0x4c:
10574         case 0x4d:
10575         case 0x4e:
10576         case 0x4f:
10577           if (address_mode == mode_64bit)
10578             newrex = *codep;
10579           else
10580             return 1;
10581           last_rex_prefix = i;
10582           break;
10583         case 0xf3:
10584           prefixes |= PREFIX_REPZ;
10585           last_repz_prefix = i;
10586           break;
10587         case 0xf2:
10588           prefixes |= PREFIX_REPNZ;
10589           last_repnz_prefix = i;
10590           break;
10591         case 0xf0:
10592           prefixes |= PREFIX_LOCK;
10593           last_lock_prefix = i;
10594           break;
10595         case 0x2e:
10596           prefixes |= PREFIX_CS;
10597           last_seg_prefix = i;
10598           break;
10599         case 0x36:
10600           prefixes |= PREFIX_SS;
10601           last_seg_prefix = i;
10602           break;
10603         case 0x3e:
10604           prefixes |= PREFIX_DS;
10605           last_seg_prefix = i;
10606           break;
10607         case 0x26:
10608           prefixes |= PREFIX_ES;
10609           last_seg_prefix = i;
10610           break;
10611         case 0x64:
10612           prefixes |= PREFIX_FS;
10613           last_seg_prefix = i;
10614           break;
10615         case 0x65:
10616           prefixes |= PREFIX_GS;
10617           last_seg_prefix = i;
10618           break;
10619         case 0x66:
10620           prefixes |= PREFIX_DATA;
10621           last_data_prefix = i;
10622           break;
10623         case 0x67:
10624           prefixes |= PREFIX_ADDR;
10625           last_addr_prefix = i;
10626           break;
10627         case FWAIT_OPCODE:
10628           /* fwait is really an instruction.  If there are prefixes
10629              before the fwait, they belong to the fwait, *not* to the
10630              following instruction.  */
10631           if (prefixes || rex)
10632             {
10633               prefixes |= PREFIX_FWAIT;
10634               codep++;
10635               return 1;
10636             }
10637           prefixes = PREFIX_FWAIT;
10638           break;
10639         default:
10640           return 1;
10641         }
10642       /* Rex is ignored when followed by another prefix.  */
10643       if (rex)
10644         {
10645           rex_used = rex;
10646           return 1;
10647         }
10648       if (*codep != FWAIT_OPCODE)
10649         all_prefixes[i++] = *codep;
10650       rex = newrex;
10651       codep++;
10652       length++;
10653     }
10654   return 0;
10655 }
10656
10657 static int
10658 seg_prefix (int pref)
10659 {
10660   switch (pref)
10661     {
10662     case 0x2e:
10663       return PREFIX_CS;
10664     case 0x36:
10665       return PREFIX_SS;
10666     case 0x3e:
10667       return PREFIX_DS;
10668     case 0x26:
10669       return PREFIX_ES;
10670     case 0x64:
10671       return PREFIX_FS;
10672     case 0x65:
10673       return PREFIX_GS;
10674     default:
10675       return 0;
10676     }
10677 }
10678
10679 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10680    prefix byte.  */
10681
10682 static const char *
10683 prefix_name (int pref, int sizeflag)
10684 {
10685   static const char *rexes [16] =
10686     {
10687       "rex",            /* 0x40 */
10688       "rex.B",          /* 0x41 */
10689       "rex.X",          /* 0x42 */
10690       "rex.XB",         /* 0x43 */
10691       "rex.R",          /* 0x44 */
10692       "rex.RB",         /* 0x45 */
10693       "rex.RX",         /* 0x46 */
10694       "rex.RXB",        /* 0x47 */
10695       "rex.W",          /* 0x48 */
10696       "rex.WB",         /* 0x49 */
10697       "rex.WX",         /* 0x4a */
10698       "rex.WXB",        /* 0x4b */
10699       "rex.WR",         /* 0x4c */
10700       "rex.WRB",        /* 0x4d */
10701       "rex.WRX",        /* 0x4e */
10702       "rex.WRXB",       /* 0x4f */
10703     };
10704
10705   switch (pref)
10706     {
10707     /* REX prefixes family.  */
10708     case 0x40:
10709     case 0x41:
10710     case 0x42:
10711     case 0x43:
10712     case 0x44:
10713     case 0x45:
10714     case 0x46:
10715     case 0x47:
10716     case 0x48:
10717     case 0x49:
10718     case 0x4a:
10719     case 0x4b:
10720     case 0x4c:
10721     case 0x4d:
10722     case 0x4e:
10723     case 0x4f:
10724       return rexes [pref - 0x40];
10725     case 0xf3:
10726       return "repz";
10727     case 0xf2:
10728       return "repnz";
10729     case 0xf0:
10730       return "lock";
10731     case 0x2e:
10732       return "cs";
10733     case 0x36:
10734       return "ss";
10735     case 0x3e:
10736       return "ds";
10737     case 0x26:
10738       return "es";
10739     case 0x64:
10740       return "fs";
10741     case 0x65:
10742       return "gs";
10743     case 0x66:
10744       return (sizeflag & DFLAG) ? "data16" : "data32";
10745     case 0x67:
10746       if (address_mode == mode_64bit)
10747         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10748       else
10749         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10750     case FWAIT_OPCODE:
10751       return "fwait";
10752     case ADDR16_PREFIX:
10753       return "addr16";
10754     case ADDR32_PREFIX:
10755       return "addr32";
10756     case DATA16_PREFIX:
10757       return "data16";
10758     case DATA32_PREFIX:
10759       return "data32";
10760     case REP_PREFIX:
10761       return "rep";
10762     default:
10763       return NULL;
10764     }
10765 }
10766
10767 static char op_out[MAX_OPERANDS][100];
10768 static int op_ad, op_index[MAX_OPERANDS];
10769 static int two_source_ops;
10770 static bfd_vma op_address[MAX_OPERANDS];
10771 static bfd_vma op_riprel[MAX_OPERANDS];
10772 static bfd_vma start_pc;
10773
10774 /*
10775  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10776  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10777  *   section of the "Virtual 8086 Mode" chapter.)
10778  * 'pc' should be the address of this instruction, it will
10779  *   be used to print the target address if this is a relative jump or call
10780  * The function returns the length of this instruction in bytes.
10781  */
10782
10783 static char intel_syntax;
10784 static char intel_mnemonic = !SYSV386_COMPAT;
10785 static char open_char;
10786 static char close_char;
10787 static char separator_char;
10788 static char scale_char;
10789
10790 /* Here for backwards compatibility.  When gdb stops using
10791    print_insn_i386_att and print_insn_i386_intel these functions can
10792    disappear, and print_insn_i386 be merged into print_insn.  */
10793 int
10794 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10795 {
10796   intel_syntax = 0;
10797
10798   return print_insn (pc, info);
10799 }
10800
10801 int
10802 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10803 {
10804   intel_syntax = 1;
10805
10806   return print_insn (pc, info);
10807 }
10808
10809 int
10810 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10811 {
10812   intel_syntax = -1;
10813
10814   return print_insn (pc, info);
10815 }
10816
10817 void
10818 print_i386_disassembler_options (FILE *stream)
10819 {
10820   fprintf (stream, _("\n\
10821 The following i386/x86-64 specific disassembler options are supported for use\n\
10822 with the -M switch (multiple options should be separated by commas):\n"));
10823
10824   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10825   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10826   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10827   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10828   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10829   fprintf (stream, _("  att-mnemonic\n"
10830                      "              Display instruction in AT&T mnemonic\n"));
10831   fprintf (stream, _("  intel-mnemonic\n"
10832                      "              Display instruction in Intel mnemonic\n"));
10833   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10834   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10835   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10836   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10837   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10838   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10839 }
10840
10841 /* Bad opcode.  */
10842 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10843
10844 /* Get a pointer to struct dis386 with a valid name.  */
10845
10846 static const struct dis386 *
10847 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10848 {
10849   int vindex, vex_table_index;
10850
10851   if (dp->name != NULL)
10852     return dp;
10853
10854   switch (dp->op[0].bytemode)
10855     {
10856     case USE_REG_TABLE:
10857       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10858       break;
10859
10860     case USE_MOD_TABLE:
10861       vindex = modrm.mod == 0x3 ? 1 : 0;
10862       dp = &mod_table[dp->op[1].bytemode][vindex];
10863       break;
10864
10865     case USE_RM_TABLE:
10866       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10867       break;
10868
10869     case USE_PREFIX_TABLE:
10870       if (need_vex)
10871         {
10872           /* The prefix in VEX is implicit.  */
10873           switch (vex.prefix)
10874             {
10875             case 0:
10876               vindex = 0;
10877               break;
10878             case REPE_PREFIX_OPCODE:
10879               vindex = 1;
10880               break;
10881             case DATA_PREFIX_OPCODE:
10882               vindex = 2;
10883               break;
10884             case REPNE_PREFIX_OPCODE:
10885               vindex = 3;
10886               break;
10887             default:
10888               abort ();
10889               break;
10890             }
10891         }
10892       else
10893         {
10894           vindex = 0;
10895           used_prefixes |= (prefixes & PREFIX_REPZ);
10896           if (prefixes & PREFIX_REPZ)
10897             {
10898               vindex = 1;
10899               all_prefixes[last_repz_prefix] = 0;
10900             }
10901           else
10902             {
10903               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10904                  PREFIX_DATA.  */
10905               used_prefixes |= (prefixes & PREFIX_REPNZ);
10906               if (prefixes & PREFIX_REPNZ)
10907                 {
10908                   vindex = 3;
10909                   all_prefixes[last_repnz_prefix] = 0;
10910                 }
10911               else
10912                 {
10913                   used_prefixes |= (prefixes & PREFIX_DATA);
10914                   if (prefixes & PREFIX_DATA)
10915                     {
10916                       vindex = 2;
10917                       all_prefixes[last_data_prefix] = 0;
10918                     }
10919                 }
10920             }
10921         }
10922       dp = &prefix_table[dp->op[1].bytemode][vindex];
10923       break;
10924
10925     case USE_X86_64_TABLE:
10926       vindex = address_mode == mode_64bit ? 1 : 0;
10927       dp = &x86_64_table[dp->op[1].bytemode][vindex];
10928       break;
10929
10930     case USE_3BYTE_TABLE:
10931       FETCH_DATA (info, codep + 2);
10932       vindex = *codep++;
10933       dp = &three_byte_table[dp->op[1].bytemode][vindex];
10934       modrm.mod = (*codep >> 6) & 3;
10935       modrm.reg = (*codep >> 3) & 7;
10936       modrm.rm = *codep & 7;
10937       break;
10938
10939     case USE_VEX_LEN_TABLE:
10940       if (!need_vex)
10941         abort ();
10942
10943       switch (vex.length)
10944         {
10945         case 128:
10946           vindex = 0;
10947           break;
10948         case 256:
10949           vindex = 1;
10950           break;
10951         default:
10952           abort ();
10953           break;
10954         }
10955
10956       dp = &vex_len_table[dp->op[1].bytemode][vindex];
10957       break;
10958
10959     case USE_XOP_8F_TABLE:
10960       FETCH_DATA (info, codep + 3);
10961       /* All bits in the REX prefix are ignored.  */
10962       rex_ignored = rex;
10963       rex = ~(*codep >> 5) & 0x7;
10964
10965       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
10966       switch ((*codep & 0x1f))
10967         {
10968         default:
10969           BadOp ();
10970         case 0x8:
10971           vex_table_index = XOP_08;
10972           break;
10973         case 0x9:
10974           vex_table_index = XOP_09;
10975           break;
10976         case 0xa:
10977           vex_table_index = XOP_0A;
10978           break;
10979         }
10980       codep++;
10981       vex.w = *codep & 0x80;
10982       if (vex.w && address_mode == mode_64bit)
10983         rex |= REX_W;
10984
10985       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10986       if (address_mode != mode_64bit
10987           && vex.register_specifier > 0x7)
10988         BadOp ();
10989
10990       vex.length = (*codep & 0x4) ? 256 : 128;
10991       switch ((*codep & 0x3))
10992         {
10993         case 0:
10994           vex.prefix = 0;
10995           break;
10996         case 1:
10997           vex.prefix = DATA_PREFIX_OPCODE;
10998           break;
10999         case 2:
11000           vex.prefix = REPE_PREFIX_OPCODE;
11001           break;
11002         case 3:
11003           vex.prefix = REPNE_PREFIX_OPCODE;
11004           break;
11005         }
11006       need_vex = 1;
11007       need_vex_reg = 1;
11008       codep++;
11009       vindex = *codep++;
11010       dp = &xop_table[vex_table_index][vindex];
11011
11012       FETCH_DATA (info, codep + 1);
11013       modrm.mod = (*codep >> 6) & 3;
11014       modrm.reg = (*codep >> 3) & 7;
11015       modrm.rm = *codep & 7;
11016       break;
11017
11018     case USE_VEX_C4_TABLE:
11019       FETCH_DATA (info, codep + 3);
11020       /* All bits in the REX prefix are ignored.  */
11021       rex_ignored = rex;
11022       rex = ~(*codep >> 5) & 0x7;
11023       switch ((*codep & 0x1f))
11024         {
11025         default:
11026           BadOp ();
11027         case 0x1:
11028           vex_table_index = VEX_0F;
11029           break;
11030         case 0x2:
11031           vex_table_index = VEX_0F38;
11032           break;
11033         case 0x3:
11034           vex_table_index = VEX_0F3A;
11035           break;
11036         }
11037       codep++;
11038       vex.w = *codep & 0x80;
11039       if (vex.w && address_mode == mode_64bit)
11040         rex |= REX_W;
11041
11042       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11043       if (address_mode != mode_64bit
11044           && vex.register_specifier > 0x7)
11045         BadOp ();
11046
11047       vex.length = (*codep & 0x4) ? 256 : 128;
11048       switch ((*codep & 0x3))
11049         {
11050         case 0:
11051           vex.prefix = 0;
11052           break;
11053         case 1:
11054           vex.prefix = DATA_PREFIX_OPCODE;
11055           break;
11056         case 2:
11057           vex.prefix = REPE_PREFIX_OPCODE;
11058           break;
11059         case 3:
11060           vex.prefix = REPNE_PREFIX_OPCODE;
11061           break;
11062         }
11063       need_vex = 1;
11064       need_vex_reg = 1;
11065       codep++;
11066       vindex = *codep++;
11067       dp = &vex_table[vex_table_index][vindex];
11068       /* There is no MODRM byte for VEX [82|77].  */
11069       if (vindex != 0x77 && vindex != 0x82)
11070         {
11071           FETCH_DATA (info, codep + 1);
11072           modrm.mod = (*codep >> 6) & 3;
11073           modrm.reg = (*codep >> 3) & 7;
11074           modrm.rm = *codep & 7;
11075         }
11076       break;
11077
11078     case USE_VEX_C5_TABLE:
11079       FETCH_DATA (info, codep + 2);
11080       /* All bits in the REX prefix are ignored.  */
11081       rex_ignored = rex;
11082       rex = (*codep & 0x80) ? 0 : REX_R;
11083
11084       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11085       if (address_mode != mode_64bit
11086           && vex.register_specifier > 0x7)
11087         BadOp ();
11088
11089       vex.w = 0;
11090
11091       vex.length = (*codep & 0x4) ? 256 : 128;
11092       switch ((*codep & 0x3))
11093         {
11094         case 0:
11095           vex.prefix = 0;
11096           break;
11097         case 1:
11098           vex.prefix = DATA_PREFIX_OPCODE;
11099           break;
11100         case 2:
11101           vex.prefix = REPE_PREFIX_OPCODE;
11102           break;
11103         case 3:
11104           vex.prefix = REPNE_PREFIX_OPCODE;
11105           break;
11106         }
11107       need_vex = 1;
11108       need_vex_reg = 1;
11109       codep++;
11110       vindex = *codep++;
11111       dp = &vex_table[dp->op[1].bytemode][vindex];
11112       /* There is no MODRM byte for VEX [82|77].  */
11113       if (vindex != 0x77 && vindex != 0x82)
11114         {
11115           FETCH_DATA (info, codep + 1);
11116           modrm.mod = (*codep >> 6) & 3;
11117           modrm.reg = (*codep >> 3) & 7;
11118           modrm.rm = *codep & 7;
11119         }
11120       break;
11121
11122     case USE_VEX_W_TABLE:
11123       if (!need_vex)
11124         abort ();
11125
11126       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11127       break;
11128
11129     case 0:
11130       dp = &bad_opcode;
11131       break;
11132
11133     default:
11134       abort ();
11135     }
11136
11137   if (dp->name != NULL)
11138     return dp;
11139   else
11140     return get_valid_dis386 (dp, info);
11141 }
11142
11143 static int
11144 print_insn (bfd_vma pc, disassemble_info *info)
11145 {
11146   const struct dis386 *dp;
11147   int i;
11148   char *op_txt[MAX_OPERANDS];
11149   int needcomma;
11150   int sizeflag;
11151   const char *p;
11152   struct dis_private priv;
11153   unsigned char op;
11154   int prefix_length;
11155   int default_prefixes;
11156
11157   if (info->mach == bfd_mach_x86_64_intel_syntax
11158       || info->mach == bfd_mach_x86_64
11159       || info->mach == bfd_mach_l1om
11160       || info->mach == bfd_mach_l1om_intel_syntax)
11161     address_mode = mode_64bit;
11162   else
11163     address_mode = mode_32bit;
11164
11165   if (intel_syntax == (char) -1)
11166     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11167                     || info->mach == bfd_mach_x86_64_intel_syntax
11168                     || info->mach == bfd_mach_l1om_intel_syntax);
11169
11170   if (info->mach == bfd_mach_i386_i386
11171       || info->mach == bfd_mach_x86_64
11172       || info->mach == bfd_mach_l1om
11173       || info->mach == bfd_mach_i386_i386_intel_syntax
11174       || info->mach == bfd_mach_x86_64_intel_syntax
11175       || info->mach == bfd_mach_l1om_intel_syntax)
11176     priv.orig_sizeflag = AFLAG | DFLAG;
11177   else if (info->mach == bfd_mach_i386_i8086)
11178     priv.orig_sizeflag = 0;
11179   else
11180     abort ();
11181
11182   for (p = info->disassembler_options; p != NULL; )
11183     {
11184       if (CONST_STRNEQ (p, "x86-64"))
11185         {
11186           address_mode = mode_64bit;
11187           priv.orig_sizeflag = AFLAG | DFLAG;
11188         }
11189       else if (CONST_STRNEQ (p, "i386"))
11190         {
11191           address_mode = mode_32bit;
11192           priv.orig_sizeflag = AFLAG | DFLAG;
11193         }
11194       else if (CONST_STRNEQ (p, "i8086"))
11195         {
11196           address_mode = mode_16bit;
11197           priv.orig_sizeflag = 0;
11198         }
11199       else if (CONST_STRNEQ (p, "intel"))
11200         {
11201           intel_syntax = 1;
11202           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11203             intel_mnemonic = 1;
11204         }
11205       else if (CONST_STRNEQ (p, "att"))
11206         {
11207           intel_syntax = 0;
11208           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11209             intel_mnemonic = 0;
11210         }
11211       else if (CONST_STRNEQ (p, "addr"))
11212         {
11213           if (address_mode == mode_64bit)
11214             {
11215               if (p[4] == '3' && p[5] == '2')
11216                 priv.orig_sizeflag &= ~AFLAG;
11217               else if (p[4] == '6' && p[5] == '4')
11218                 priv.orig_sizeflag |= AFLAG;
11219             }
11220           else
11221             {
11222               if (p[4] == '1' && p[5] == '6')
11223                 priv.orig_sizeflag &= ~AFLAG;
11224               else if (p[4] == '3' && p[5] == '2')
11225                 priv.orig_sizeflag |= AFLAG;
11226             }
11227         }
11228       else if (CONST_STRNEQ (p, "data"))
11229         {
11230           if (p[4] == '1' && p[5] == '6')
11231             priv.orig_sizeflag &= ~DFLAG;
11232           else if (p[4] == '3' && p[5] == '2')
11233             priv.orig_sizeflag |= DFLAG;
11234         }
11235       else if (CONST_STRNEQ (p, "suffix"))
11236         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11237
11238       p = strchr (p, ',');
11239       if (p != NULL)
11240         p++;
11241     }
11242
11243   if (intel_syntax)
11244     {
11245       names64 = intel_names64;
11246       names32 = intel_names32;
11247       names16 = intel_names16;
11248       names8 = intel_names8;
11249       names8rex = intel_names8rex;
11250       names_seg = intel_names_seg;
11251       names_mm = intel_names_mm;
11252       names_xmm = intel_names_xmm;
11253       names_ymm = intel_names_ymm;
11254       index64 = intel_index64;
11255       index32 = intel_index32;
11256       index16 = intel_index16;
11257       open_char = '[';
11258       close_char = ']';
11259       separator_char = '+';
11260       scale_char = '*';
11261     }
11262   else
11263     {
11264       names64 = att_names64;
11265       names32 = att_names32;
11266       names16 = att_names16;
11267       names8 = att_names8;
11268       names8rex = att_names8rex;
11269       names_seg = att_names_seg;
11270       names_mm = att_names_mm;
11271       names_xmm = att_names_xmm;
11272       names_ymm = att_names_ymm;
11273       index64 = att_index64;
11274       index32 = att_index32;
11275       index16 = att_index16;
11276       open_char = '(';
11277       close_char =  ')';
11278       separator_char = ',';
11279       scale_char = ',';
11280     }
11281
11282   /* The output looks better if we put 7 bytes on a line, since that
11283      puts most long word instructions on a single line.  Use 8 bytes
11284      for Intel L1OM.  */
11285   if (info->mach == bfd_mach_l1om
11286       || info->mach == bfd_mach_l1om_intel_syntax)
11287     info->bytes_per_line = 8;
11288   else
11289     info->bytes_per_line = 7;
11290
11291   info->private_data = &priv;
11292   priv.max_fetched = priv.the_buffer;
11293   priv.insn_start = pc;
11294
11295   obuf[0] = 0;
11296   for (i = 0; i < MAX_OPERANDS; ++i)
11297     {
11298       op_out[i][0] = 0;
11299       op_index[i] = -1;
11300     }
11301
11302   the_info = info;
11303   start_pc = pc;
11304   start_codep = priv.the_buffer;
11305   codep = priv.the_buffer;
11306
11307   if (setjmp (priv.bailout) != 0)
11308     {
11309       const char *name;
11310
11311       /* Getting here means we tried for data but didn't get it.  That
11312          means we have an incomplete instruction of some sort.  Just
11313          print the first byte as a prefix or a .byte pseudo-op.  */
11314       if (codep > priv.the_buffer)
11315         {
11316           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11317           if (name != NULL)
11318             (*info->fprintf_func) (info->stream, "%s", name);
11319           else
11320             {
11321               /* Just print the first byte as a .byte instruction.  */
11322               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11323                                      (unsigned int) priv.the_buffer[0]);
11324             }
11325
11326           return 1;
11327         }
11328
11329       return -1;
11330     }
11331
11332   obufp = obuf;
11333   sizeflag = priv.orig_sizeflag;
11334
11335   if (!ckprefix () || rex_used)
11336     {
11337       /* Too many prefixes or unused REX prefixes.  */
11338       for (i = 0;
11339            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11340            i++)
11341         (*info->fprintf_func) (info->stream, "%s",
11342                                prefix_name (all_prefixes[i], sizeflag));
11343       return 1;
11344     }
11345
11346   insn_codep = codep;
11347
11348   FETCH_DATA (info, codep + 1);
11349   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11350
11351   if (((prefixes & PREFIX_FWAIT)
11352        && ((*codep < 0xd8) || (*codep > 0xdf))))
11353     {
11354       (*info->fprintf_func) (info->stream, "fwait");
11355       return 1;
11356     }
11357
11358   op = 0;
11359
11360   if (*codep == 0x0f)
11361     {
11362       unsigned char threebyte;
11363       FETCH_DATA (info, codep + 2);
11364       threebyte = *++codep;
11365       dp = &dis386_twobyte[threebyte];
11366       need_modrm = twobyte_has_modrm[*codep];
11367       codep++;
11368     }
11369   else
11370     {
11371       dp = &dis386[*codep];
11372       need_modrm = onebyte_has_modrm[*codep];
11373       codep++;
11374     }
11375
11376   if ((prefixes & PREFIX_REPZ))
11377     used_prefixes |= PREFIX_REPZ;
11378   if ((prefixes & PREFIX_REPNZ))
11379     used_prefixes |= PREFIX_REPNZ;
11380   if ((prefixes & PREFIX_LOCK))
11381     used_prefixes |= PREFIX_LOCK;
11382
11383   default_prefixes = 0;
11384   if (prefixes & PREFIX_ADDR)
11385     {
11386       sizeflag ^= AFLAG;
11387       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11388         {
11389           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11390             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11391           else
11392             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11393           default_prefixes |= PREFIX_ADDR;
11394         }
11395     }
11396
11397   if ((prefixes & PREFIX_DATA))
11398     {
11399       sizeflag ^= DFLAG;
11400       if (dp->op[2].bytemode == cond_jump_mode
11401           && dp->op[0].bytemode == v_mode
11402           && !intel_syntax)
11403         {
11404           if (sizeflag & DFLAG)
11405             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11406           else
11407             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11408           default_prefixes |= PREFIX_DATA;
11409         }
11410       else if (rex & REX_W)
11411         {
11412           /* REX_W will override PREFIX_DATA.  */
11413           default_prefixes |= PREFIX_DATA;
11414         }
11415     }
11416
11417   if (need_modrm)
11418     {
11419       FETCH_DATA (info, codep + 1);
11420       modrm.mod = (*codep >> 6) & 3;
11421       modrm.reg = (*codep >> 3) & 7;
11422       modrm.rm = *codep & 7;
11423     }
11424
11425    need_vex = 0;
11426    need_vex_reg = 0;
11427    vex_w_done = 0;
11428
11429   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11430     {
11431       dofloat (sizeflag);
11432     }
11433   else
11434     {
11435       dp = get_valid_dis386 (dp, info);
11436       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11437         {
11438           for (i = 0; i < MAX_OPERANDS; ++i)
11439             {
11440               obufp = op_out[i];
11441               op_ad = MAX_OPERANDS - 1 - i;
11442               if (dp->op[i].rtn)
11443                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11444             }
11445         }
11446     }
11447
11448   /* See if any prefixes were not used.  If so, print the first one
11449      separately.  If we don't do this, we'll wind up printing an
11450      instruction stream which does not precisely correspond to the
11451      bytes we are disassembling.  */
11452   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11453     {
11454       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11455         if (all_prefixes[i])
11456           {
11457             const char *name;
11458             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11459             if (name == NULL)
11460               name = INTERNAL_DISASSEMBLER_ERROR;
11461             (*info->fprintf_func) (info->stream, "%s", name);
11462             return 1;
11463           }
11464     }
11465
11466   /* Check if the REX prefix is used.  */
11467   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11468     all_prefixes[last_rex_prefix] = 0;
11469
11470   /* Check if the SEG prefix is used.  */
11471   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11472                    | PREFIX_FS | PREFIX_GS)) != 0
11473       && (used_prefixes
11474           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11475     all_prefixes[last_seg_prefix] = 0;
11476
11477   /* Check if the ADDR prefix is used.  */
11478   if ((prefixes & PREFIX_ADDR) != 0
11479       && (used_prefixes & PREFIX_ADDR) != 0)
11480     all_prefixes[last_addr_prefix] = 0;
11481
11482   /* Check if the DATA prefix is used.  */
11483   if ((prefixes & PREFIX_DATA) != 0
11484       && (used_prefixes & PREFIX_DATA) != 0)
11485     all_prefixes[last_data_prefix] = 0;
11486
11487   prefix_length = 0;
11488   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11489     if (all_prefixes[i])
11490       {
11491         const char *name;
11492         name = prefix_name (all_prefixes[i], sizeflag);
11493         if (name == NULL)
11494           abort ();
11495         prefix_length += strlen (name) + 1;
11496         (*info->fprintf_func) (info->stream, "%s ", name);
11497       }
11498
11499   /* Check maximum code length.  */
11500   if ((codep - start_codep) > MAX_CODE_LENGTH)
11501     {
11502       (*info->fprintf_func) (info->stream, "(bad)");
11503       return MAX_CODE_LENGTH;
11504     }
11505
11506   obufp = mnemonicendp;
11507   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11508     oappend (" ");
11509   oappend (" ");
11510   (*info->fprintf_func) (info->stream, "%s", obuf);
11511
11512   /* The enter and bound instructions are printed with operands in the same
11513      order as the intel book; everything else is printed in reverse order.  */
11514   if (intel_syntax || two_source_ops)
11515     {
11516       bfd_vma riprel;
11517
11518       for (i = 0; i < MAX_OPERANDS; ++i)
11519         op_txt[i] = op_out[i];
11520
11521       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11522         {
11523           op_ad = op_index[i];
11524           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11525           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11526           riprel = op_riprel[i];
11527           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11528           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11529         }
11530     }
11531   else
11532     {
11533       for (i = 0; i < MAX_OPERANDS; ++i)
11534         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11535     }
11536
11537   needcomma = 0;
11538   for (i = 0; i < MAX_OPERANDS; ++i)
11539     if (*op_txt[i])
11540       {
11541         if (needcomma)
11542           (*info->fprintf_func) (info->stream, ",");
11543         if (op_index[i] != -1 && !op_riprel[i])
11544           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11545         else
11546           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11547         needcomma = 1;
11548       }
11549
11550   for (i = 0; i < MAX_OPERANDS; i++)
11551     if (op_index[i] != -1 && op_riprel[i])
11552       {
11553         (*info->fprintf_func) (info->stream, "        # ");
11554         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11555                                                 + op_address[op_index[i]]), info);
11556         break;
11557       }
11558   return codep - priv.the_buffer;
11559 }
11560
11561 static const char *float_mem[] = {
11562   /* d8 */
11563   "fadd{s|}",
11564   "fmul{s|}",
11565   "fcom{s|}",
11566   "fcomp{s|}",
11567   "fsub{s|}",
11568   "fsubr{s|}",
11569   "fdiv{s|}",
11570   "fdivr{s|}",
11571   /* d9 */
11572   "fld{s|}",
11573   "(bad)",
11574   "fst{s|}",
11575   "fstp{s|}",
11576   "fldenvIC",
11577   "fldcw",
11578   "fNstenvIC",
11579   "fNstcw",
11580   /* da */
11581   "fiadd{l|}",
11582   "fimul{l|}",
11583   "ficom{l|}",
11584   "ficomp{l|}",
11585   "fisub{l|}",
11586   "fisubr{l|}",
11587   "fidiv{l|}",
11588   "fidivr{l|}",
11589   /* db */
11590   "fild{l|}",
11591   "fisttp{l|}",
11592   "fist{l|}",
11593   "fistp{l|}",
11594   "(bad)",
11595   "fld{t||t|}",
11596   "(bad)",
11597   "fstp{t||t|}",
11598   /* dc */
11599   "fadd{l|}",
11600   "fmul{l|}",
11601   "fcom{l|}",
11602   "fcomp{l|}",
11603   "fsub{l|}",
11604   "fsubr{l|}",
11605   "fdiv{l|}",
11606   "fdivr{l|}",
11607   /* dd */
11608   "fld{l|}",
11609   "fisttp{ll|}",
11610   "fst{l||}",
11611   "fstp{l|}",
11612   "frstorIC",
11613   "(bad)",
11614   "fNsaveIC",
11615   "fNstsw",
11616   /* de */
11617   "fiadd",
11618   "fimul",
11619   "ficom",
11620   "ficomp",
11621   "fisub",
11622   "fisubr",
11623   "fidiv",
11624   "fidivr",
11625   /* df */
11626   "fild",
11627   "fisttp",
11628   "fist",
11629   "fistp",
11630   "fbld",
11631   "fild{ll|}",
11632   "fbstp",
11633   "fistp{ll|}",
11634 };
11635
11636 static const unsigned char float_mem_mode[] = {
11637   /* d8 */
11638   d_mode,
11639   d_mode,
11640   d_mode,
11641   d_mode,
11642   d_mode,
11643   d_mode,
11644   d_mode,
11645   d_mode,
11646   /* d9 */
11647   d_mode,
11648   0,
11649   d_mode,
11650   d_mode,
11651   0,
11652   w_mode,
11653   0,
11654   w_mode,
11655   /* da */
11656   d_mode,
11657   d_mode,
11658   d_mode,
11659   d_mode,
11660   d_mode,
11661   d_mode,
11662   d_mode,
11663   d_mode,
11664   /* db */
11665   d_mode,
11666   d_mode,
11667   d_mode,
11668   d_mode,
11669   0,
11670   t_mode,
11671   0,
11672   t_mode,
11673   /* dc */
11674   q_mode,
11675   q_mode,
11676   q_mode,
11677   q_mode,
11678   q_mode,
11679   q_mode,
11680   q_mode,
11681   q_mode,
11682   /* dd */
11683   q_mode,
11684   q_mode,
11685   q_mode,
11686   q_mode,
11687   0,
11688   0,
11689   0,
11690   w_mode,
11691   /* de */
11692   w_mode,
11693   w_mode,
11694   w_mode,
11695   w_mode,
11696   w_mode,
11697   w_mode,
11698   w_mode,
11699   w_mode,
11700   /* df */
11701   w_mode,
11702   w_mode,
11703   w_mode,
11704   w_mode,
11705   t_mode,
11706   q_mode,
11707   t_mode,
11708   q_mode
11709 };
11710
11711 #define ST { OP_ST, 0 }
11712 #define STi { OP_STi, 0 }
11713
11714 #define FGRPd9_2 NULL, { { NULL, 0 } }
11715 #define FGRPd9_4 NULL, { { NULL, 1 } }
11716 #define FGRPd9_5 NULL, { { NULL, 2 } }
11717 #define FGRPd9_6 NULL, { { NULL, 3 } }
11718 #define FGRPd9_7 NULL, { { NULL, 4 } }
11719 #define FGRPda_5 NULL, { { NULL, 5 } }
11720 #define FGRPdb_4 NULL, { { NULL, 6 } }
11721 #define FGRPde_3 NULL, { { NULL, 7 } }
11722 #define FGRPdf_4 NULL, { { NULL, 8 } }
11723
11724 static const struct dis386 float_reg[][8] = {
11725   /* d8 */
11726   {
11727     { "fadd",   { ST, STi } },
11728     { "fmul",   { ST, STi } },
11729     { "fcom",   { STi } },
11730     { "fcomp",  { STi } },
11731     { "fsub",   { ST, STi } },
11732     { "fsubr",  { ST, STi } },
11733     { "fdiv",   { ST, STi } },
11734     { "fdivr",  { ST, STi } },
11735   },
11736   /* d9 */
11737   {
11738     { "fld",    { STi } },
11739     { "fxch",   { STi } },
11740     { FGRPd9_2 },
11741     { Bad_Opcode },
11742     { FGRPd9_4 },
11743     { FGRPd9_5 },
11744     { FGRPd9_6 },
11745     { FGRPd9_7 },
11746   },
11747   /* da */
11748   {
11749     { "fcmovb", { ST, STi } },
11750     { "fcmove", { ST, STi } },
11751     { "fcmovbe",{ ST, STi } },
11752     { "fcmovu", { ST, STi } },
11753     { Bad_Opcode },
11754     { FGRPda_5 },
11755     { Bad_Opcode },
11756     { Bad_Opcode },
11757   },
11758   /* db */
11759   {
11760     { "fcmovnb",{ ST, STi } },
11761     { "fcmovne",{ ST, STi } },
11762     { "fcmovnbe",{ ST, STi } },
11763     { "fcmovnu",{ ST, STi } },
11764     { FGRPdb_4 },
11765     { "fucomi", { ST, STi } },
11766     { "fcomi",  { ST, STi } },
11767     { Bad_Opcode },
11768   },
11769   /* dc */
11770   {
11771     { "fadd",   { STi, ST } },
11772     { "fmul",   { STi, ST } },
11773     { Bad_Opcode },
11774     { Bad_Opcode },
11775     { "fsub!M", { STi, ST } },
11776     { "fsubM",  { STi, ST } },
11777     { "fdiv!M", { STi, ST } },
11778     { "fdivM",  { STi, ST } },
11779   },
11780   /* dd */
11781   {
11782     { "ffree",  { STi } },
11783     { Bad_Opcode },
11784     { "fst",    { STi } },
11785     { "fstp",   { STi } },
11786     { "fucom",  { STi } },
11787     { "fucomp", { STi } },
11788     { Bad_Opcode },
11789     { Bad_Opcode },
11790   },
11791   /* de */
11792   {
11793     { "faddp",  { STi, ST } },
11794     { "fmulp",  { STi, ST } },
11795     { Bad_Opcode },
11796     { FGRPde_3 },
11797     { "fsub!Mp", { STi, ST } },
11798     { "fsubMp", { STi, ST } },
11799     { "fdiv!Mp", { STi, ST } },
11800     { "fdivMp", { STi, ST } },
11801   },
11802   /* df */
11803   {
11804     { "ffreep", { STi } },
11805     { Bad_Opcode },
11806     { Bad_Opcode },
11807     { Bad_Opcode },
11808     { FGRPdf_4 },
11809     { "fucomip", { ST, STi } },
11810     { "fcomip", { ST, STi } },
11811     { Bad_Opcode },
11812   },
11813 };
11814
11815 static char *fgrps[][8] = {
11816   /* d9_2  0 */
11817   {
11818     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11819   },
11820
11821   /* d9_4  1 */
11822   {
11823     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11824   },
11825
11826   /* d9_5  2 */
11827   {
11828     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11829   },
11830
11831   /* d9_6  3 */
11832   {
11833     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11834   },
11835
11836   /* d9_7  4 */
11837   {
11838     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11839   },
11840
11841   /* da_5  5 */
11842   {
11843     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11844   },
11845
11846   /* db_4  6 */
11847   {
11848     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11849     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11850   },
11851
11852   /* de_3  7 */
11853   {
11854     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11855   },
11856
11857   /* df_4  8 */
11858   {
11859     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11860   },
11861 };
11862
11863 static void
11864 swap_operand (void)
11865 {
11866   mnemonicendp[0] = '.';
11867   mnemonicendp[1] = 's';
11868   mnemonicendp += 2;
11869 }
11870
11871 static void
11872 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11873                int sizeflag ATTRIBUTE_UNUSED)
11874 {
11875   /* Skip mod/rm byte.  */
11876   MODRM_CHECK;
11877   codep++;
11878 }
11879
11880 static void
11881 dofloat (int sizeflag)
11882 {
11883   const struct dis386 *dp;
11884   unsigned char floatop;
11885
11886   floatop = codep[-1];
11887
11888   if (modrm.mod != 3)
11889     {
11890       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11891
11892       putop (float_mem[fp_indx], sizeflag);
11893       obufp = op_out[0];
11894       op_ad = 2;
11895       OP_E (float_mem_mode[fp_indx], sizeflag);
11896       return;
11897     }
11898   /* Skip mod/rm byte.  */
11899   MODRM_CHECK;
11900   codep++;
11901
11902   dp = &float_reg[floatop - 0xd8][modrm.reg];
11903   if (dp->name == NULL)
11904     {
11905       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11906
11907       /* Instruction fnstsw is only one with strange arg.  */
11908       if (floatop == 0xdf && codep[-1] == 0xe0)
11909         strcpy (op_out[0], names16[0]);
11910     }
11911   else
11912     {
11913       putop (dp->name, sizeflag);
11914
11915       obufp = op_out[0];
11916       op_ad = 2;
11917       if (dp->op[0].rtn)
11918         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
11919
11920       obufp = op_out[1];
11921       op_ad = 1;
11922       if (dp->op[1].rtn)
11923         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
11924     }
11925 }
11926
11927 static void
11928 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11929 {
11930   oappend ("%st" + intel_syntax);
11931 }
11932
11933 static void
11934 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11935 {
11936   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
11937   oappend (scratchbuf + intel_syntax);
11938 }
11939
11940 /* Capital letters in template are macros.  */
11941 static int
11942 putop (const char *in_template, int sizeflag)
11943 {
11944   const char *p;
11945   int alt = 0;
11946   int cond = 1;
11947   unsigned int l = 0, len = 1;
11948   char last[4];
11949
11950 #define SAVE_LAST(c)                    \
11951   if (l < len && l < sizeof (last))     \
11952     last[l++] = c;                      \
11953   else                                  \
11954     abort ();
11955
11956   for (p = in_template; *p; p++)
11957     {
11958       switch (*p)
11959         {
11960         default:
11961           *obufp++ = *p;
11962           break;
11963         case '%':
11964           len++;
11965           break;
11966         case '!':
11967           cond = 0;
11968           break;
11969         case '{':
11970           alt = 0;
11971           if (intel_syntax)
11972             {
11973               while (*++p != '|')
11974                 if (*p == '}' || *p == '\0')
11975                   abort ();
11976             }
11977           /* Fall through.  */
11978         case 'I':
11979           alt = 1;
11980           continue;
11981         case '|':
11982           while (*++p != '}')
11983             {
11984               if (*p == '\0')
11985                 abort ();
11986             }
11987           break;
11988         case '}':
11989           break;
11990         case 'A':
11991           if (intel_syntax)
11992             break;
11993           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11994             *obufp++ = 'b';
11995           break;
11996         case 'B':
11997           if (l == 0 && len == 1)
11998             {
11999 case_B:
12000               if (intel_syntax)
12001                 break;
12002               if (sizeflag & SUFFIX_ALWAYS)
12003                 *obufp++ = 'b';
12004             }
12005           else
12006             {
12007               if (l != 1
12008                   || len != 2
12009                   || last[0] != 'L')
12010                 {
12011                   SAVE_LAST (*p);
12012                   break;
12013                 }
12014
12015               if (address_mode == mode_64bit
12016                   && !(prefixes & PREFIX_ADDR))
12017                 {
12018                   *obufp++ = 'a';
12019                   *obufp++ = 'b';
12020                   *obufp++ = 's';
12021                 }
12022
12023               goto case_B;
12024             }
12025           break;
12026         case 'C':
12027           if (intel_syntax && !alt)
12028             break;
12029           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12030             {
12031               if (sizeflag & DFLAG)
12032                 *obufp++ = intel_syntax ? 'd' : 'l';
12033               else
12034                 *obufp++ = intel_syntax ? 'w' : 's';
12035               used_prefixes |= (prefixes & PREFIX_DATA);
12036             }
12037           break;
12038         case 'D':
12039           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12040             break;
12041           USED_REX (REX_W);
12042           if (modrm.mod == 3)
12043             {
12044               if (rex & REX_W)
12045                 *obufp++ = 'q';
12046               else
12047                 {
12048                   if (sizeflag & DFLAG)
12049                     *obufp++ = intel_syntax ? 'd' : 'l';
12050                   else
12051                     *obufp++ = 'w';
12052                   used_prefixes |= (prefixes & PREFIX_DATA);
12053                 }
12054             }
12055           else
12056             *obufp++ = 'w';
12057           break;
12058         case 'E':               /* For jcxz/jecxz */
12059           if (address_mode == mode_64bit)
12060             {
12061               if (sizeflag & AFLAG)
12062                 *obufp++ = 'r';
12063               else
12064                 *obufp++ = 'e';
12065             }
12066           else
12067             if (sizeflag & AFLAG)
12068               *obufp++ = 'e';
12069           used_prefixes |= (prefixes & PREFIX_ADDR);
12070           break;
12071         case 'F':
12072           if (intel_syntax)
12073             break;
12074           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12075             {
12076               if (sizeflag & AFLAG)
12077                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12078               else
12079                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12080               used_prefixes |= (prefixes & PREFIX_ADDR);
12081             }
12082           break;
12083         case 'G':
12084           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12085             break;
12086           if ((rex & REX_W) || (sizeflag & DFLAG))
12087             *obufp++ = 'l';
12088           else
12089             *obufp++ = 'w';
12090           if (!(rex & REX_W))
12091             used_prefixes |= (prefixes & PREFIX_DATA);
12092           break;
12093         case 'H':
12094           if (intel_syntax)
12095             break;
12096           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12097               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12098             {
12099               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12100               *obufp++ = ',';
12101               *obufp++ = 'p';
12102               if (prefixes & PREFIX_DS)
12103                 *obufp++ = 't';
12104               else
12105                 *obufp++ = 'n';
12106             }
12107           break;
12108         case 'J':
12109           if (intel_syntax)
12110             break;
12111           *obufp++ = 'l';
12112           break;
12113         case 'K':
12114           USED_REX (REX_W);
12115           if (rex & REX_W)
12116             *obufp++ = 'q';
12117           else
12118             *obufp++ = 'd';
12119           break;
12120         case 'Z':
12121           if (intel_syntax)
12122             break;
12123           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12124             {
12125               *obufp++ = 'q';
12126               break;
12127             }
12128           /* Fall through.  */
12129           goto case_L;
12130         case 'L':
12131           if (l != 0 || len != 1)
12132             {
12133               SAVE_LAST (*p);
12134               break;
12135             }
12136 case_L:
12137           if (intel_syntax)
12138             break;
12139           if (sizeflag & SUFFIX_ALWAYS)
12140             *obufp++ = 'l';
12141           break;
12142         case 'M':
12143           if (intel_mnemonic != cond)
12144             *obufp++ = 'r';
12145           break;
12146         case 'N':
12147           if ((prefixes & PREFIX_FWAIT) == 0)
12148             *obufp++ = 'n';
12149           else
12150             used_prefixes |= PREFIX_FWAIT;
12151           break;
12152         case 'O':
12153           USED_REX (REX_W);
12154           if (rex & REX_W)
12155             *obufp++ = 'o';
12156           else if (intel_syntax && (sizeflag & DFLAG))
12157             *obufp++ = 'q';
12158           else
12159             *obufp++ = 'd';
12160           if (!(rex & REX_W))
12161             used_prefixes |= (prefixes & PREFIX_DATA);
12162           break;
12163         case 'T':
12164           if (intel_syntax)
12165             break;
12166           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12167             {
12168               *obufp++ = 'q';
12169               break;
12170             }
12171           /* Fall through.  */
12172         case 'P':
12173           if (intel_syntax)
12174             break;
12175           if ((prefixes & PREFIX_DATA)
12176               || (rex & REX_W)
12177               || (sizeflag & SUFFIX_ALWAYS))
12178             {
12179               USED_REX (REX_W);
12180               if (rex & REX_W)
12181                 *obufp++ = 'q';
12182               else
12183                 {
12184                    if (sizeflag & DFLAG)
12185                       *obufp++ = 'l';
12186                    else
12187                      *obufp++ = 'w';
12188                    used_prefixes |= (prefixes & PREFIX_DATA);
12189                 }
12190             }
12191           break;
12192         case 'U':
12193           if (intel_syntax)
12194             break;
12195           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12196             {
12197               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12198                 *obufp++ = 'q';
12199               break;
12200             }
12201           /* Fall through.  */
12202           goto case_Q;
12203         case 'Q':
12204           if (l == 0 && len == 1)
12205             {
12206 case_Q:
12207               if (intel_syntax && !alt)
12208                 break;
12209               USED_REX (REX_W);
12210               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12211                 {
12212                   if (rex & REX_W)
12213                     *obufp++ = 'q';
12214                   else
12215                     {
12216                       if (sizeflag & DFLAG)
12217                         *obufp++ = intel_syntax ? 'd' : 'l';
12218                       else
12219                         *obufp++ = 'w';
12220                       used_prefixes |= (prefixes & PREFIX_DATA);
12221                     }
12222                 }
12223             }
12224           else
12225             {
12226               if (l != 1 || len != 2 || last[0] != 'L')
12227                 {
12228                   SAVE_LAST (*p);
12229                   break;
12230                 }
12231               if (intel_syntax
12232                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12233                 break;
12234               if ((rex & REX_W))
12235                 {
12236                   USED_REX (REX_W);
12237                   *obufp++ = 'q';
12238                 }
12239               else
12240                 *obufp++ = 'l';
12241             }
12242           break;
12243         case 'R':
12244           USED_REX (REX_W);
12245           if (rex & REX_W)
12246             *obufp++ = 'q';
12247           else if (sizeflag & DFLAG)
12248             {
12249               if (intel_syntax)
12250                   *obufp++ = 'd';
12251               else
12252                   *obufp++ = 'l';
12253             }
12254           else
12255             *obufp++ = 'w';
12256           if (intel_syntax && !p[1]
12257               && ((rex & REX_W) || (sizeflag & DFLAG)))
12258             *obufp++ = 'e';
12259           if (!(rex & REX_W))
12260             used_prefixes |= (prefixes & PREFIX_DATA);
12261           break;
12262         case 'V':
12263           if (l == 0 && len == 1)
12264             {
12265               if (intel_syntax)
12266                 break;
12267               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12268                 {
12269                   if (sizeflag & SUFFIX_ALWAYS)
12270                     *obufp++ = 'q';
12271                   break;
12272                 }
12273             }
12274           else
12275             {
12276               if (l != 1
12277                   || len != 2
12278                   || last[0] != 'L')
12279                 {
12280                   SAVE_LAST (*p);
12281                   break;
12282                 }
12283
12284               if (rex & REX_W)
12285                 {
12286                   *obufp++ = 'a';
12287                   *obufp++ = 'b';
12288                   *obufp++ = 's';
12289                 }
12290             }
12291           /* Fall through.  */
12292           goto case_S;
12293         case 'S':
12294           if (l == 0 && len == 1)
12295             {
12296 case_S:
12297               if (intel_syntax)
12298                 break;
12299               if (sizeflag & SUFFIX_ALWAYS)
12300                 {
12301                   if (rex & REX_W)
12302                     *obufp++ = 'q';
12303                   else
12304                     {
12305                       if (sizeflag & DFLAG)
12306                         *obufp++ = 'l';
12307                       else
12308                         *obufp++ = 'w';
12309                       used_prefixes |= (prefixes & PREFIX_DATA);
12310                     }
12311                 }
12312             }
12313           else
12314             {
12315               if (l != 1
12316                   || len != 2
12317                   || last[0] != 'L')
12318                 {
12319                   SAVE_LAST (*p);
12320                   break;
12321                 }
12322
12323               if (address_mode == mode_64bit
12324                   && !(prefixes & PREFIX_ADDR))
12325                 {
12326                   *obufp++ = 'a';
12327                   *obufp++ = 'b';
12328                   *obufp++ = 's';
12329                 }
12330
12331               goto case_S;
12332             }
12333           break;
12334         case 'X':
12335           if (l != 0 || len != 1)
12336             {
12337               SAVE_LAST (*p);
12338               break;
12339             }
12340           if (need_vex && vex.prefix)
12341             {
12342               if (vex.prefix == DATA_PREFIX_OPCODE)
12343                 *obufp++ = 'd';
12344               else
12345                 *obufp++ = 's';
12346             }
12347           else
12348             {
12349               if (prefixes & PREFIX_DATA)
12350                 *obufp++ = 'd';
12351               else
12352                 *obufp++ = 's';
12353               used_prefixes |= (prefixes & PREFIX_DATA);
12354             }
12355           break;
12356         case 'Y':
12357           if (l == 0 && len == 1)
12358             {
12359               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12360                 break;
12361               if (rex & REX_W)
12362                 {
12363                   USED_REX (REX_W);
12364                   *obufp++ = 'q';
12365                 }
12366               break;
12367             }
12368           else
12369             {
12370               if (l != 1 || len != 2 || last[0] != 'X')
12371                 {
12372                   SAVE_LAST (*p);
12373                   break;
12374                 }
12375               if (!need_vex)
12376                 abort ();
12377               if (intel_syntax
12378                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12379                 break;
12380               switch (vex.length)
12381                 {
12382                 case 128:
12383                   *obufp++ = 'x';
12384                   break;
12385                 case 256:
12386                   *obufp++ = 'y';
12387                   break;
12388                 default:
12389                   abort ();
12390                 }
12391             }
12392           break;
12393         case 'W':
12394           if (l == 0 && len == 1)
12395             {
12396               /* operand size flag for cwtl, cbtw */
12397               USED_REX (REX_W);
12398               if (rex & REX_W)
12399                 {
12400                   if (intel_syntax)
12401                     *obufp++ = 'd';
12402                   else
12403                     *obufp++ = 'l';
12404                 }
12405               else if (sizeflag & DFLAG)
12406                 *obufp++ = 'w';
12407               else
12408                 *obufp++ = 'b';
12409               if (!(rex & REX_W))
12410                 used_prefixes |= (prefixes & PREFIX_DATA);
12411             }
12412           else
12413             {
12414               if (l != 1 || len != 2 || last[0] != 'X')
12415                 {
12416                   SAVE_LAST (*p);
12417                   break;
12418                 }
12419               if (!need_vex)
12420                 abort ();
12421               *obufp++ = vex.w ? 'd': 's';
12422             }
12423           break;
12424         }
12425       alt = 0;
12426     }
12427   *obufp = 0;
12428   mnemonicendp = obufp;
12429   return 0;
12430 }
12431
12432 static void
12433 oappend (const char *s)
12434 {
12435   obufp = stpcpy (obufp, s);
12436 }
12437
12438 static void
12439 append_seg (void)
12440 {
12441   if (prefixes & PREFIX_CS)
12442     {
12443       used_prefixes |= PREFIX_CS;
12444       oappend ("%cs:" + intel_syntax);
12445     }
12446   if (prefixes & PREFIX_DS)
12447     {
12448       used_prefixes |= PREFIX_DS;
12449       oappend ("%ds:" + intel_syntax);
12450     }
12451   if (prefixes & PREFIX_SS)
12452     {
12453       used_prefixes |= PREFIX_SS;
12454       oappend ("%ss:" + intel_syntax);
12455     }
12456   if (prefixes & PREFIX_ES)
12457     {
12458       used_prefixes |= PREFIX_ES;
12459       oappend ("%es:" + intel_syntax);
12460     }
12461   if (prefixes & PREFIX_FS)
12462     {
12463       used_prefixes |= PREFIX_FS;
12464       oappend ("%fs:" + intel_syntax);
12465     }
12466   if (prefixes & PREFIX_GS)
12467     {
12468       used_prefixes |= PREFIX_GS;
12469       oappend ("%gs:" + intel_syntax);
12470     }
12471 }
12472
12473 static void
12474 OP_indirE (int bytemode, int sizeflag)
12475 {
12476   if (!intel_syntax)
12477     oappend ("*");
12478   OP_E (bytemode, sizeflag);
12479 }
12480
12481 static void
12482 print_operand_value (char *buf, int hex, bfd_vma disp)
12483 {
12484   if (address_mode == mode_64bit)
12485     {
12486       if (hex)
12487         {
12488           char tmp[30];
12489           int i;
12490           buf[0] = '0';
12491           buf[1] = 'x';
12492           sprintf_vma (tmp, disp);
12493           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12494           strcpy (buf + 2, tmp + i);
12495         }
12496       else
12497         {
12498           bfd_signed_vma v = disp;
12499           char tmp[30];
12500           int i;
12501           if (v < 0)
12502             {
12503               *(buf++) = '-';
12504               v = -disp;
12505               /* Check for possible overflow on 0x8000000000000000.  */
12506               if (v < 0)
12507                 {
12508                   strcpy (buf, "9223372036854775808");
12509                   return;
12510                 }
12511             }
12512           if (!v)
12513             {
12514               strcpy (buf, "0");
12515               return;
12516             }
12517
12518           i = 0;
12519           tmp[29] = 0;
12520           while (v)
12521             {
12522               tmp[28 - i] = (v % 10) + '0';
12523               v /= 10;
12524               i++;
12525             }
12526           strcpy (buf, tmp + 29 - i);
12527         }
12528     }
12529   else
12530     {
12531       if (hex)
12532         sprintf (buf, "0x%x", (unsigned int) disp);
12533       else
12534         sprintf (buf, "%d", (int) disp);
12535     }
12536 }
12537
12538 /* Put DISP in BUF as signed hex number.  */
12539
12540 static void
12541 print_displacement (char *buf, bfd_vma disp)
12542 {
12543   bfd_signed_vma val = disp;
12544   char tmp[30];
12545   int i, j = 0;
12546
12547   if (val < 0)
12548     {
12549       buf[j++] = '-';
12550       val = -disp;
12551
12552       /* Check for possible overflow.  */
12553       if (val < 0)
12554         {
12555           switch (address_mode)
12556             {
12557             case mode_64bit:
12558               strcpy (buf + j, "0x8000000000000000");
12559               break;
12560             case mode_32bit:
12561               strcpy (buf + j, "0x80000000");
12562               break;
12563             case mode_16bit:
12564               strcpy (buf + j, "0x8000");
12565               break;
12566             }
12567           return;
12568         }
12569     }
12570
12571   buf[j++] = '0';
12572   buf[j++] = 'x';
12573
12574   sprintf_vma (tmp, (bfd_vma) val);
12575   for (i = 0; tmp[i] == '0'; i++)
12576     continue;
12577   if (tmp[i] == '\0')
12578     i--;
12579   strcpy (buf + j, tmp + i);
12580 }
12581
12582 static void
12583 intel_operand_size (int bytemode, int sizeflag)
12584 {
12585   switch (bytemode)
12586     {
12587     case b_mode:
12588     case b_swap_mode:
12589     case dqb_mode:
12590       oappend ("BYTE PTR ");
12591       break;
12592     case w_mode:
12593     case dqw_mode:
12594       oappend ("WORD PTR ");
12595       break;
12596     case stack_v_mode:
12597       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12598         {
12599           oappend ("QWORD PTR ");
12600           break;
12601         }
12602       /* FALLTHRU */
12603     case v_mode:
12604     case v_swap_mode:
12605     case dq_mode:
12606       USED_REX (REX_W);
12607       if (rex & REX_W)
12608         oappend ("QWORD PTR ");
12609       else
12610         {
12611           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12612             oappend ("DWORD PTR ");
12613           else
12614             oappend ("WORD PTR ");
12615           used_prefixes |= (prefixes & PREFIX_DATA);
12616         }
12617       break;
12618     case z_mode:
12619       if ((rex & REX_W) || (sizeflag & DFLAG))
12620         *obufp++ = 'D';
12621       oappend ("WORD PTR ");
12622       if (!(rex & REX_W))
12623         used_prefixes |= (prefixes & PREFIX_DATA);
12624       break;
12625     case a_mode:
12626       if (sizeflag & DFLAG)
12627         oappend ("QWORD PTR ");
12628       else
12629         oappend ("DWORD PTR ");
12630       used_prefixes |= (prefixes & PREFIX_DATA);
12631       break;
12632     case d_mode:
12633     case d_swap_mode:
12634     case dqd_mode:
12635       oappend ("DWORD PTR ");
12636       break;
12637     case q_mode:
12638     case q_swap_mode:
12639       oappend ("QWORD PTR ");
12640       break;
12641     case m_mode:
12642       if (address_mode == mode_64bit)
12643         oappend ("QWORD PTR ");
12644       else
12645         oappend ("DWORD PTR ");
12646       break;
12647     case f_mode:
12648       if (sizeflag & DFLAG)
12649         oappend ("FWORD PTR ");
12650       else
12651         oappend ("DWORD PTR ");
12652       used_prefixes |= (prefixes & PREFIX_DATA);
12653       break;
12654     case t_mode:
12655       oappend ("TBYTE PTR ");
12656       break;
12657     case x_mode:
12658     case x_swap_mode:
12659       if (need_vex)
12660         {
12661           switch (vex.length)
12662             {
12663             case 128:
12664               oappend ("XMMWORD PTR ");
12665               break;
12666             case 256:
12667               oappend ("YMMWORD PTR ");
12668               break;
12669             default:
12670               abort ();
12671             }
12672         }
12673       else
12674         oappend ("XMMWORD PTR ");
12675       break;
12676     case xmm_mode:
12677       oappend ("XMMWORD PTR ");
12678       break;
12679     case xmmq_mode:
12680       if (!need_vex)
12681         abort ();
12682
12683       switch (vex.length)
12684         {
12685         case 128:
12686           oappend ("QWORD PTR ");
12687           break;
12688         case 256:
12689           oappend ("XMMWORD PTR ");
12690           break;
12691         default:
12692           abort ();
12693         }
12694       break;
12695     case ymmq_mode:
12696       if (!need_vex)
12697         abort ();
12698
12699       switch (vex.length)
12700         {
12701         case 128:
12702           oappend ("QWORD PTR ");
12703           break;
12704         case 256:
12705           oappend ("YMMWORD PTR ");
12706           break;
12707         default:
12708           abort ();
12709         }
12710       break;
12711     case o_mode:
12712       oappend ("OWORD PTR ");
12713       break;
12714     case vex_w_dq_mode:
12715       if (!need_vex)
12716         abort ();
12717
12718       if (vex.w)
12719         oappend ("QWORD PTR ");
12720       else
12721         oappend ("DWORD PTR ");
12722       break;
12723     default:
12724       break;
12725     }
12726 }
12727
12728 static void
12729 OP_E_register (int bytemode, int sizeflag)
12730 {
12731   int reg = modrm.rm;
12732   const char **names;
12733
12734   USED_REX (REX_B);
12735   if ((rex & REX_B))
12736     reg += 8;
12737
12738   if ((sizeflag & SUFFIX_ALWAYS)
12739       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12740     swap_operand ();
12741
12742   switch (bytemode)
12743     {
12744     case b_mode:
12745     case b_swap_mode:
12746       USED_REX (0);
12747       if (rex)
12748         names = names8rex;
12749       else
12750         names = names8;
12751       break;
12752     case w_mode:
12753       names = names16;
12754       break;
12755     case d_mode:
12756       names = names32;
12757       break;
12758     case q_mode:
12759       names = names64;
12760       break;
12761     case m_mode:
12762       names = address_mode == mode_64bit ? names64 : names32;
12763       break;
12764     case stack_v_mode:
12765       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12766         {
12767           names = names64;
12768           break;
12769         }
12770       bytemode = v_mode;
12771       /* FALLTHRU */
12772     case v_mode:
12773     case v_swap_mode:
12774     case dq_mode:
12775     case dqb_mode:
12776     case dqd_mode:
12777     case dqw_mode:
12778       USED_REX (REX_W);
12779       if (rex & REX_W)
12780         names = names64;
12781       else
12782         {
12783           if ((sizeflag & DFLAG)
12784               || (bytemode != v_mode
12785                   && bytemode != v_swap_mode))
12786             names = names32;
12787           else
12788             names = names16;
12789           used_prefixes |= (prefixes & PREFIX_DATA);
12790         }
12791       break;
12792     case 0:
12793       return;
12794     default:
12795       oappend (INTERNAL_DISASSEMBLER_ERROR);
12796       return;
12797     }
12798   oappend (names[reg]);
12799 }
12800
12801 static void
12802 OP_E_memory (int bytemode, int sizeflag)
12803 {
12804   bfd_vma disp = 0;
12805   int add = (rex & REX_B) ? 8 : 0;
12806   int riprel = 0;
12807
12808   USED_REX (REX_B);
12809   if (intel_syntax)
12810     intel_operand_size (bytemode, sizeflag);
12811   append_seg ();
12812
12813   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12814     {
12815       /* 32/64 bit address mode */
12816       int havedisp;
12817       int havesib;
12818       int havebase;
12819       int haveindex;
12820       int needindex;
12821       int base, rbase;
12822       int vindex = 0;
12823       int scale = 0;
12824
12825       havesib = 0;
12826       havebase = 1;
12827       haveindex = 0;
12828       base = modrm.rm;
12829
12830       if (base == 4)
12831         {
12832           havesib = 1;
12833           FETCH_DATA (the_info, codep + 1);
12834           vindex = (*codep >> 3) & 7;
12835           scale = (*codep >> 6) & 3;
12836           base = *codep & 7;
12837           USED_REX (REX_X);
12838           if (rex & REX_X)
12839             vindex += 8;
12840           haveindex = vindex != 4;
12841           codep++;
12842         }
12843       rbase = base + add;
12844
12845       switch (modrm.mod)
12846         {
12847         case 0:
12848           if (base == 5)
12849             {
12850               havebase = 0;
12851               if (address_mode == mode_64bit && !havesib)
12852                 riprel = 1;
12853               disp = get32s ();
12854             }
12855           break;
12856         case 1:
12857           FETCH_DATA (the_info, codep + 1);
12858           disp = *codep++;
12859           if ((disp & 0x80) != 0)
12860             disp -= 0x100;
12861           break;
12862         case 2:
12863           disp = get32s ();
12864           break;
12865         }
12866
12867       /* In 32bit mode, we need index register to tell [offset] from
12868          [eiz*1 + offset].  */
12869       needindex = (havesib
12870                    && !havebase
12871                    && !haveindex
12872                    && address_mode == mode_32bit);
12873       havedisp = (havebase
12874                   || needindex
12875                   || (havesib && (haveindex || scale != 0)));
12876
12877       if (!intel_syntax)
12878         if (modrm.mod != 0 || base == 5)
12879           {
12880             if (havedisp || riprel)
12881               print_displacement (scratchbuf, disp);
12882             else
12883               print_operand_value (scratchbuf, 1, disp);
12884             oappend (scratchbuf);
12885             if (riprel)
12886               {
12887                 set_op (disp, 1);
12888                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
12889               }
12890           }
12891
12892       if (havebase || haveindex || riprel)
12893         used_prefixes |= PREFIX_ADDR;
12894
12895       if (havedisp || (intel_syntax && riprel))
12896         {
12897           *obufp++ = open_char;
12898           if (intel_syntax && riprel)
12899             {
12900               set_op (disp, 1);
12901               oappend (sizeflag & AFLAG ? "rip" : "eip");
12902             }
12903           *obufp = '\0';
12904           if (havebase)
12905             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
12906                      ? names64[rbase] : names32[rbase]);
12907           if (havesib)
12908             {
12909               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12910                  print index to tell base + index from base.  */
12911               if (scale != 0
12912                   || needindex
12913                   || haveindex
12914                   || (havebase && base != ESP_REG_NUM))
12915                 {
12916                   if (!intel_syntax || havebase)
12917                     {
12918                       *obufp++ = separator_char;
12919                       *obufp = '\0';
12920                     }
12921                   if (haveindex)
12922                     oappend (address_mode == mode_64bit
12923                              && (sizeflag & AFLAG)
12924                              ? names64[vindex] : names32[vindex]);
12925                   else
12926                     oappend (address_mode == mode_64bit
12927                              && (sizeflag & AFLAG)
12928                              ? index64 : index32);
12929
12930                   *obufp++ = scale_char;
12931                   *obufp = '\0';
12932                   sprintf (scratchbuf, "%d", 1 << scale);
12933                   oappend (scratchbuf);
12934                 }
12935             }
12936           if (intel_syntax
12937               && (disp || modrm.mod != 0 || base == 5))
12938             {
12939               if (!havedisp || (bfd_signed_vma) disp >= 0)
12940                 {
12941                   *obufp++ = '+';
12942                   *obufp = '\0';
12943                 }
12944               else if (modrm.mod != 1 && disp != -disp)
12945                 {
12946                   *obufp++ = '-';
12947                   *obufp = '\0';
12948                   disp = - (bfd_signed_vma) disp;
12949                 }
12950
12951               if (havedisp)
12952                 print_displacement (scratchbuf, disp);
12953               else
12954                 print_operand_value (scratchbuf, 1, disp);
12955               oappend (scratchbuf);
12956             }
12957
12958           *obufp++ = close_char;
12959           *obufp = '\0';
12960         }
12961       else if (intel_syntax)
12962         {
12963           if (modrm.mod != 0 || base == 5)
12964             {
12965               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12966                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
12967                 ;
12968               else
12969                 {
12970                   oappend (names_seg[ds_reg - es_reg]);
12971                   oappend (":");
12972                 }
12973               print_operand_value (scratchbuf, 1, disp);
12974               oappend (scratchbuf);
12975             }
12976         }
12977     }
12978   else
12979     {
12980       /* 16 bit address mode */
12981       used_prefixes |= prefixes & PREFIX_ADDR;
12982       switch (modrm.mod)
12983         {
12984         case 0:
12985           if (modrm.rm == 6)
12986             {
12987               disp = get16 ();
12988               if ((disp & 0x8000) != 0)
12989                 disp -= 0x10000;
12990             }
12991           break;
12992         case 1:
12993           FETCH_DATA (the_info, codep + 1);
12994           disp = *codep++;
12995           if ((disp & 0x80) != 0)
12996             disp -= 0x100;
12997           break;
12998         case 2:
12999           disp = get16 ();
13000           if ((disp & 0x8000) != 0)
13001             disp -= 0x10000;
13002           break;
13003         }
13004
13005       if (!intel_syntax)
13006         if (modrm.mod != 0 || modrm.rm == 6)
13007           {
13008             print_displacement (scratchbuf, disp);
13009             oappend (scratchbuf);
13010           }
13011
13012       if (modrm.mod != 0 || modrm.rm != 6)
13013         {
13014           *obufp++ = open_char;
13015           *obufp = '\0';
13016           oappend (index16[modrm.rm]);
13017           if (intel_syntax
13018               && (disp || modrm.mod != 0 || modrm.rm == 6))
13019             {
13020               if ((bfd_signed_vma) disp >= 0)
13021                 {
13022                   *obufp++ = '+';
13023                   *obufp = '\0';
13024                 }
13025               else if (modrm.mod != 1)
13026                 {
13027                   *obufp++ = '-';
13028                   *obufp = '\0';
13029                   disp = - (bfd_signed_vma) disp;
13030                 }
13031
13032               print_displacement (scratchbuf, disp);
13033               oappend (scratchbuf);
13034             }
13035
13036           *obufp++ = close_char;
13037           *obufp = '\0';
13038         }
13039       else if (intel_syntax)
13040         {
13041           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13042                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13043             ;
13044           else
13045             {
13046               oappend (names_seg[ds_reg - es_reg]);
13047               oappend (":");
13048             }
13049           print_operand_value (scratchbuf, 1, disp & 0xffff);
13050           oappend (scratchbuf);
13051         }
13052     }
13053 }
13054
13055 static void
13056 OP_E (int bytemode, int sizeflag)
13057 {
13058   /* Skip mod/rm byte.  */
13059   MODRM_CHECK;
13060   codep++;
13061
13062   if (modrm.mod == 3)
13063     OP_E_register (bytemode, sizeflag);
13064   else
13065     OP_E_memory (bytemode, sizeflag);
13066 }
13067
13068 static void
13069 OP_G (int bytemode, int sizeflag)
13070 {
13071   int add = 0;
13072   USED_REX (REX_R);
13073   if (rex & REX_R)
13074     add += 8;
13075   switch (bytemode)
13076     {
13077     case b_mode:
13078       USED_REX (0);
13079       if (rex)
13080         oappend (names8rex[modrm.reg + add]);
13081       else
13082         oappend (names8[modrm.reg + add]);
13083       break;
13084     case w_mode:
13085       oappend (names16[modrm.reg + add]);
13086       break;
13087     case d_mode:
13088       oappend (names32[modrm.reg + add]);
13089       break;
13090     case q_mode:
13091       oappend (names64[modrm.reg + add]);
13092       break;
13093     case v_mode:
13094     case dq_mode:
13095     case dqb_mode:
13096     case dqd_mode:
13097     case dqw_mode:
13098       USED_REX (REX_W);
13099       if (rex & REX_W)
13100         oappend (names64[modrm.reg + add]);
13101       else
13102         {
13103           if ((sizeflag & DFLAG) || bytemode != v_mode)
13104             oappend (names32[modrm.reg + add]);
13105           else
13106             oappend (names16[modrm.reg + add]);
13107           used_prefixes |= (prefixes & PREFIX_DATA);
13108         }
13109       break;
13110     case m_mode:
13111       if (address_mode == mode_64bit)
13112         oappend (names64[modrm.reg + add]);
13113       else
13114         oappend (names32[modrm.reg + add]);
13115       break;
13116     default:
13117       oappend (INTERNAL_DISASSEMBLER_ERROR);
13118       break;
13119     }
13120 }
13121
13122 static bfd_vma
13123 get64 (void)
13124 {
13125   bfd_vma x;
13126 #ifdef BFD64
13127   unsigned int a;
13128   unsigned int b;
13129
13130   FETCH_DATA (the_info, codep + 8);
13131   a = *codep++ & 0xff;
13132   a |= (*codep++ & 0xff) << 8;
13133   a |= (*codep++ & 0xff) << 16;
13134   a |= (*codep++ & 0xff) << 24;
13135   b = *codep++ & 0xff;
13136   b |= (*codep++ & 0xff) << 8;
13137   b |= (*codep++ & 0xff) << 16;
13138   b |= (*codep++ & 0xff) << 24;
13139   x = a + ((bfd_vma) b << 32);
13140 #else
13141   abort ();
13142   x = 0;
13143 #endif
13144   return x;
13145 }
13146
13147 static bfd_signed_vma
13148 get32 (void)
13149 {
13150   bfd_signed_vma x = 0;
13151
13152   FETCH_DATA (the_info, codep + 4);
13153   x = *codep++ & (bfd_signed_vma) 0xff;
13154   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13155   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13156   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13157   return x;
13158 }
13159
13160 static bfd_signed_vma
13161 get32s (void)
13162 {
13163   bfd_signed_vma x = 0;
13164
13165   FETCH_DATA (the_info, codep + 4);
13166   x = *codep++ & (bfd_signed_vma) 0xff;
13167   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13168   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13169   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13170
13171   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13172
13173   return x;
13174 }
13175
13176 static int
13177 get16 (void)
13178 {
13179   int x = 0;
13180
13181   FETCH_DATA (the_info, codep + 2);
13182   x = *codep++ & 0xff;
13183   x |= (*codep++ & 0xff) << 8;
13184   return x;
13185 }
13186
13187 static void
13188 set_op (bfd_vma op, int riprel)
13189 {
13190   op_index[op_ad] = op_ad;
13191   if (address_mode == mode_64bit)
13192     {
13193       op_address[op_ad] = op;
13194       op_riprel[op_ad] = riprel;
13195     }
13196   else
13197     {
13198       /* Mask to get a 32-bit address.  */
13199       op_address[op_ad] = op & 0xffffffff;
13200       op_riprel[op_ad] = riprel & 0xffffffff;
13201     }
13202 }
13203
13204 static void
13205 OP_REG (int code, int sizeflag)
13206 {
13207   const char *s;
13208   int add;
13209   USED_REX (REX_B);
13210   if (rex & REX_B)
13211     add = 8;
13212   else
13213     add = 0;
13214
13215   switch (code)
13216     {
13217     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13218     case sp_reg: case bp_reg: case si_reg: case di_reg:
13219       s = names16[code - ax_reg + add];
13220       break;
13221     case es_reg: case ss_reg: case cs_reg:
13222     case ds_reg: case fs_reg: case gs_reg:
13223       s = names_seg[code - es_reg + add];
13224       break;
13225     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13226     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13227       USED_REX (0);
13228       if (rex)
13229         s = names8rex[code - al_reg + add];
13230       else
13231         s = names8[code - al_reg];
13232       break;
13233     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13234     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13235       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13236         {
13237           s = names64[code - rAX_reg + add];
13238           break;
13239         }
13240       code += eAX_reg - rAX_reg;
13241       /* Fall through.  */
13242     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13243     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13244       USED_REX (REX_W);
13245       if (rex & REX_W)
13246         s = names64[code - eAX_reg + add];
13247       else
13248         {
13249           if (sizeflag & DFLAG)
13250             s = names32[code - eAX_reg + add];
13251           else
13252             s = names16[code - eAX_reg + add];
13253           used_prefixes |= (prefixes & PREFIX_DATA);
13254         }
13255       break;
13256     default:
13257       s = INTERNAL_DISASSEMBLER_ERROR;
13258       break;
13259     }
13260   oappend (s);
13261 }
13262
13263 static void
13264 OP_IMREG (int code, int sizeflag)
13265 {
13266   const char *s;
13267
13268   switch (code)
13269     {
13270     case indir_dx_reg:
13271       if (intel_syntax)
13272         s = "dx";
13273       else
13274         s = "(%dx)";
13275       break;
13276     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13277     case sp_reg: case bp_reg: case si_reg: case di_reg:
13278       s = names16[code - ax_reg];
13279       break;
13280     case es_reg: case ss_reg: case cs_reg:
13281     case ds_reg: case fs_reg: case gs_reg:
13282       s = names_seg[code - es_reg];
13283       break;
13284     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13285     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13286       USED_REX (0);
13287       if (rex)
13288         s = names8rex[code - al_reg];
13289       else
13290         s = names8[code - al_reg];
13291       break;
13292     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13293     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13294       USED_REX (REX_W);
13295       if (rex & REX_W)
13296         s = names64[code - eAX_reg];
13297       else
13298         {
13299           if (sizeflag & DFLAG)
13300             s = names32[code - eAX_reg];
13301           else
13302             s = names16[code - eAX_reg];
13303           used_prefixes |= (prefixes & PREFIX_DATA);
13304         }
13305       break;
13306     case z_mode_ax_reg:
13307       if ((rex & REX_W) || (sizeflag & DFLAG))
13308         s = *names32;
13309       else
13310         s = *names16;
13311       if (!(rex & REX_W))
13312         used_prefixes |= (prefixes & PREFIX_DATA);
13313       break;
13314     default:
13315       s = INTERNAL_DISASSEMBLER_ERROR;
13316       break;
13317     }
13318   oappend (s);
13319 }
13320
13321 static void
13322 OP_I (int bytemode, int sizeflag)
13323 {
13324   bfd_signed_vma op;
13325   bfd_signed_vma mask = -1;
13326
13327   switch (bytemode)
13328     {
13329     case b_mode:
13330       FETCH_DATA (the_info, codep + 1);
13331       op = *codep++;
13332       mask = 0xff;
13333       break;
13334     case q_mode:
13335       if (address_mode == mode_64bit)
13336         {
13337           op = get32s ();
13338           break;
13339         }
13340       /* Fall through.  */
13341     case v_mode:
13342       USED_REX (REX_W);
13343       if (rex & REX_W)
13344         op = get32s ();
13345       else
13346         {
13347           if (sizeflag & DFLAG)
13348             {
13349               op = get32 ();
13350               mask = 0xffffffff;
13351             }
13352           else
13353             {
13354               op = get16 ();
13355               mask = 0xfffff;
13356             }
13357           used_prefixes |= (prefixes & PREFIX_DATA);
13358         }
13359       break;
13360     case w_mode:
13361       mask = 0xfffff;
13362       op = get16 ();
13363       break;
13364     case const_1_mode:
13365       if (intel_syntax)
13366         oappend ("1");
13367       return;
13368     default:
13369       oappend (INTERNAL_DISASSEMBLER_ERROR);
13370       return;
13371     }
13372
13373   op &= mask;
13374   scratchbuf[0] = '$';
13375   print_operand_value (scratchbuf + 1, 1, op);
13376   oappend (scratchbuf + intel_syntax);
13377   scratchbuf[0] = '\0';
13378 }
13379
13380 static void
13381 OP_I64 (int bytemode, int sizeflag)
13382 {
13383   bfd_signed_vma op;
13384   bfd_signed_vma mask = -1;
13385
13386   if (address_mode != mode_64bit)
13387     {
13388       OP_I (bytemode, sizeflag);
13389       return;
13390     }
13391
13392   switch (bytemode)
13393     {
13394     case b_mode:
13395       FETCH_DATA (the_info, codep + 1);
13396       op = *codep++;
13397       mask = 0xff;
13398       break;
13399     case v_mode:
13400       USED_REX (REX_W);
13401       if (rex & REX_W)
13402         op = get64 ();
13403       else
13404         {
13405           if (sizeflag & DFLAG)
13406             {
13407               op = get32 ();
13408               mask = 0xffffffff;
13409             }
13410           else
13411             {
13412               op = get16 ();
13413               mask = 0xfffff;
13414             }
13415           used_prefixes |= (prefixes & PREFIX_DATA);
13416         }
13417       break;
13418     case w_mode:
13419       mask = 0xfffff;
13420       op = get16 ();
13421       break;
13422     default:
13423       oappend (INTERNAL_DISASSEMBLER_ERROR);
13424       return;
13425     }
13426
13427   op &= mask;
13428   scratchbuf[0] = '$';
13429   print_operand_value (scratchbuf + 1, 1, op);
13430   oappend (scratchbuf + intel_syntax);
13431   scratchbuf[0] = '\0';
13432 }
13433
13434 static void
13435 OP_sI (int bytemode, int sizeflag)
13436 {
13437   bfd_signed_vma op;
13438   bfd_signed_vma mask = -1;
13439
13440   switch (bytemode)
13441     {
13442     case b_mode:
13443       FETCH_DATA (the_info, codep + 1);
13444       op = *codep++;
13445       if ((op & 0x80) != 0)
13446         op -= 0x100;
13447       mask = 0xffffffff;
13448       break;
13449     case v_mode:
13450       USED_REX (REX_W);
13451       if (rex & REX_W)
13452         op = get32s ();
13453       else
13454         {
13455           if (sizeflag & DFLAG)
13456             {
13457               op = get32s ();
13458               mask = 0xffffffff;
13459             }
13460           else
13461             {
13462               mask = 0xffffffff;
13463               op = get16 ();
13464               if ((op & 0x8000) != 0)
13465                 op -= 0x10000;
13466             }
13467           used_prefixes |= (prefixes & PREFIX_DATA);
13468         }
13469       break;
13470     case w_mode:
13471       op = get16 ();
13472       mask = 0xffffffff;
13473       if ((op & 0x8000) != 0)
13474         op -= 0x10000;
13475       break;
13476     default:
13477       oappend (INTERNAL_DISASSEMBLER_ERROR);
13478       return;
13479     }
13480
13481   scratchbuf[0] = '$';
13482   print_operand_value (scratchbuf + 1, 1, op);
13483   oappend (scratchbuf + intel_syntax);
13484 }
13485
13486 static void
13487 OP_J (int bytemode, int sizeflag)
13488 {
13489   bfd_vma disp;
13490   bfd_vma mask = -1;
13491   bfd_vma segment = 0;
13492
13493   switch (bytemode)
13494     {
13495     case b_mode:
13496       FETCH_DATA (the_info, codep + 1);
13497       disp = *codep++;
13498       if ((disp & 0x80) != 0)
13499         disp -= 0x100;
13500       break;
13501     case v_mode:
13502       USED_REX (REX_W);
13503       if ((sizeflag & DFLAG) || (rex & REX_W))
13504         disp = get32s ();
13505       else
13506         {
13507           disp = get16 ();
13508           if ((disp & 0x8000) != 0)
13509             disp -= 0x10000;
13510           /* In 16bit mode, address is wrapped around at 64k within
13511              the same segment.  Otherwise, a data16 prefix on a jump
13512              instruction means that the pc is masked to 16 bits after
13513              the displacement is added!  */
13514           mask = 0xffff;
13515           if ((prefixes & PREFIX_DATA) == 0)
13516             segment = ((start_pc + codep - start_codep)
13517                        & ~((bfd_vma) 0xffff));
13518         }
13519       if (!(rex & REX_W))
13520         used_prefixes |= (prefixes & PREFIX_DATA);
13521       break;
13522     default:
13523       oappend (INTERNAL_DISASSEMBLER_ERROR);
13524       return;
13525     }
13526   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13527   set_op (disp, 0);
13528   print_operand_value (scratchbuf, 1, disp);
13529   oappend (scratchbuf);
13530 }
13531
13532 static void
13533 OP_SEG (int bytemode, int sizeflag)
13534 {
13535   if (bytemode == w_mode)
13536     oappend (names_seg[modrm.reg]);
13537   else
13538     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13539 }
13540
13541 static void
13542 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13543 {
13544   int seg, offset;
13545
13546   if (sizeflag & DFLAG)
13547     {
13548       offset = get32 ();
13549       seg = get16 ();
13550     }
13551   else
13552     {
13553       offset = get16 ();
13554       seg = get16 ();
13555     }
13556   used_prefixes |= (prefixes & PREFIX_DATA);
13557   if (intel_syntax)
13558     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13559   else
13560     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13561   oappend (scratchbuf);
13562 }
13563
13564 static void
13565 OP_OFF (int bytemode, int sizeflag)
13566 {
13567   bfd_vma off;
13568
13569   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13570     intel_operand_size (bytemode, sizeflag);
13571   append_seg ();
13572
13573   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13574     off = get32 ();
13575   else
13576     off = get16 ();
13577
13578   if (intel_syntax)
13579     {
13580       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13581                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13582         {
13583           oappend (names_seg[ds_reg - es_reg]);
13584           oappend (":");
13585         }
13586     }
13587   print_operand_value (scratchbuf, 1, off);
13588   oappend (scratchbuf);
13589 }
13590
13591 static void
13592 OP_OFF64 (int bytemode, int sizeflag)
13593 {
13594   bfd_vma off;
13595
13596   if (address_mode != mode_64bit
13597       || (prefixes & PREFIX_ADDR))
13598     {
13599       OP_OFF (bytemode, sizeflag);
13600       return;
13601     }
13602
13603   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13604     intel_operand_size (bytemode, sizeflag);
13605   append_seg ();
13606
13607   off = get64 ();
13608
13609   if (intel_syntax)
13610     {
13611       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13612                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13613         {
13614           oappend (names_seg[ds_reg - es_reg]);
13615           oappend (":");
13616         }
13617     }
13618   print_operand_value (scratchbuf, 1, off);
13619   oappend (scratchbuf);
13620 }
13621
13622 static void
13623 ptr_reg (int code, int sizeflag)
13624 {
13625   const char *s;
13626
13627   *obufp++ = open_char;
13628   used_prefixes |= (prefixes & PREFIX_ADDR);
13629   if (address_mode == mode_64bit)
13630     {
13631       if (!(sizeflag & AFLAG))
13632         s = names32[code - eAX_reg];
13633       else
13634         s = names64[code - eAX_reg];
13635     }
13636   else if (sizeflag & AFLAG)
13637     s = names32[code - eAX_reg];
13638   else
13639     s = names16[code - eAX_reg];
13640   oappend (s);
13641   *obufp++ = close_char;
13642   *obufp = 0;
13643 }
13644
13645 static void
13646 OP_ESreg (int code, int sizeflag)
13647 {
13648   if (intel_syntax)
13649     {
13650       switch (codep[-1])
13651         {
13652         case 0x6d:      /* insw/insl */
13653           intel_operand_size (z_mode, sizeflag);
13654           break;
13655         case 0xa5:      /* movsw/movsl/movsq */
13656         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13657         case 0xab:      /* stosw/stosl */
13658         case 0xaf:      /* scasw/scasl */
13659           intel_operand_size (v_mode, sizeflag);
13660           break;
13661         default:
13662           intel_operand_size (b_mode, sizeflag);
13663         }
13664     }
13665   oappend ("%es:" + intel_syntax);
13666   ptr_reg (code, sizeflag);
13667 }
13668
13669 static void
13670 OP_DSreg (int code, int sizeflag)
13671 {
13672   if (intel_syntax)
13673     {
13674       switch (codep[-1])
13675         {
13676         case 0x6f:      /* outsw/outsl */
13677           intel_operand_size (z_mode, sizeflag);
13678           break;
13679         case 0xa5:      /* movsw/movsl/movsq */
13680         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13681         case 0xad:      /* lodsw/lodsl/lodsq */
13682           intel_operand_size (v_mode, sizeflag);
13683           break;
13684         default:
13685           intel_operand_size (b_mode, sizeflag);
13686         }
13687     }
13688   if ((prefixes
13689        & (PREFIX_CS
13690           | PREFIX_DS
13691           | PREFIX_SS
13692           | PREFIX_ES
13693           | PREFIX_FS
13694           | PREFIX_GS)) == 0)
13695     prefixes |= PREFIX_DS;
13696   append_seg ();
13697   ptr_reg (code, sizeflag);
13698 }
13699
13700 static void
13701 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13702 {
13703   int add;
13704   if (rex & REX_R)
13705     {
13706       USED_REX (REX_R);
13707       add = 8;
13708     }
13709   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13710     {
13711       all_prefixes[last_lock_prefix] = 0;
13712       used_prefixes |= PREFIX_LOCK;
13713       add = 8;
13714     }
13715   else
13716     add = 0;
13717   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13718   oappend (scratchbuf + intel_syntax);
13719 }
13720
13721 static void
13722 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13723 {
13724   int add;
13725   USED_REX (REX_R);
13726   if (rex & REX_R)
13727     add = 8;
13728   else
13729     add = 0;
13730   if (intel_syntax)
13731     sprintf (scratchbuf, "db%d", modrm.reg + add);
13732   else
13733     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13734   oappend (scratchbuf);
13735 }
13736
13737 static void
13738 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13739 {
13740   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13741   oappend (scratchbuf + intel_syntax);
13742 }
13743
13744 static void
13745 OP_R (int bytemode, int sizeflag)
13746 {
13747   if (modrm.mod == 3)
13748     OP_E (bytemode, sizeflag);
13749   else
13750     BadOp ();
13751 }
13752
13753 static void
13754 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13755 {
13756   int reg = modrm.reg;
13757   const char **names;
13758
13759   used_prefixes |= (prefixes & PREFIX_DATA);
13760   if (prefixes & PREFIX_DATA)
13761     {
13762       names = names_xmm;
13763       USED_REX (REX_R);
13764       if (rex & REX_R)
13765         reg += 8;
13766     }
13767   else
13768     names = names_mm;
13769   oappend (names[reg]);
13770 }
13771
13772 static void
13773 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13774 {
13775   int reg = modrm.reg;
13776   const char **names;
13777
13778   USED_REX (REX_R);
13779   if (rex & REX_R)
13780     reg += 8;
13781   if (need_vex && bytemode != xmm_mode)
13782     {
13783       switch (vex.length)
13784         {
13785         case 128:
13786           names = names_xmm;
13787           break;
13788         case 256:
13789           names = names_ymm;
13790           break;
13791         default:
13792           abort ();
13793         }
13794     }
13795   else
13796     names = names_xmm;
13797   oappend (names[reg]);
13798 }
13799
13800 static void
13801 OP_EM (int bytemode, int sizeflag)
13802 {
13803   int reg;
13804   const char **names;
13805
13806   if (modrm.mod != 3)
13807     {
13808       if (intel_syntax
13809           && (bytemode == v_mode || bytemode == v_swap_mode))
13810         {
13811           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13812           used_prefixes |= (prefixes & PREFIX_DATA);
13813         }
13814       OP_E (bytemode, sizeflag);
13815       return;
13816     }
13817
13818   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13819     swap_operand ();
13820
13821   /* Skip mod/rm byte.  */
13822   MODRM_CHECK;
13823   codep++;
13824   used_prefixes |= (prefixes & PREFIX_DATA);
13825   reg = modrm.rm;
13826   if (prefixes & PREFIX_DATA)
13827     {
13828       names = names_xmm;
13829       USED_REX (REX_B);
13830       if (rex & REX_B)
13831         reg += 8;
13832     }
13833   else
13834     names = names_mm;
13835   oappend (names[reg]);
13836 }
13837
13838 /* cvt* are the only instructions in sse2 which have
13839    both SSE and MMX operands and also have 0x66 prefix
13840    in their opcode. 0x66 was originally used to differentiate
13841    between SSE and MMX instruction(operands). So we have to handle the
13842    cvt* separately using OP_EMC and OP_MXC */
13843 static void
13844 OP_EMC (int bytemode, int sizeflag)
13845 {
13846   if (modrm.mod != 3)
13847     {
13848       if (intel_syntax && bytemode == v_mode)
13849         {
13850           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13851           used_prefixes |= (prefixes & PREFIX_DATA);
13852         }
13853       OP_E (bytemode, sizeflag);
13854       return;
13855     }
13856
13857   /* Skip mod/rm byte.  */
13858   MODRM_CHECK;
13859   codep++;
13860   used_prefixes |= (prefixes & PREFIX_DATA);
13861   oappend (names_mm[modrm.rm]);
13862 }
13863
13864 static void
13865 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13866 {
13867   used_prefixes |= (prefixes & PREFIX_DATA);
13868   oappend (names_mm[modrm.reg]);
13869 }
13870
13871 static void
13872 OP_EX (int bytemode, int sizeflag)
13873 {
13874   int reg;
13875   const char **names;
13876
13877   /* Skip mod/rm byte.  */
13878   MODRM_CHECK;
13879   codep++;
13880
13881   if (modrm.mod != 3)
13882     {
13883       OP_E_memory (bytemode, sizeflag);
13884       return;
13885     }
13886
13887   reg = modrm.rm;
13888   USED_REX (REX_B);
13889   if (rex & REX_B)
13890     reg += 8;
13891
13892   if ((sizeflag & SUFFIX_ALWAYS)
13893       && (bytemode == x_swap_mode
13894           || bytemode == d_swap_mode
13895           || bytemode == q_swap_mode))
13896     swap_operand ();
13897
13898   if (need_vex
13899       && bytemode != xmm_mode
13900       && bytemode != xmmq_mode)
13901     {
13902       switch (vex.length)
13903         {
13904         case 128:
13905           names = names_xmm;
13906           break;
13907         case 256:
13908           names = names_ymm;
13909           break;
13910         default:
13911           abort ();
13912         }
13913     }
13914   else
13915     names = names_xmm;
13916   oappend (names[reg]);
13917 }
13918
13919 static void
13920 OP_MS (int bytemode, int sizeflag)
13921 {
13922   if (modrm.mod == 3)
13923     OP_EM (bytemode, sizeflag);
13924   else
13925     BadOp ();
13926 }
13927
13928 static void
13929 OP_XS (int bytemode, int sizeflag)
13930 {
13931   if (modrm.mod == 3)
13932     OP_EX (bytemode, sizeflag);
13933   else
13934     BadOp ();
13935 }
13936
13937 static void
13938 OP_M (int bytemode, int sizeflag)
13939 {
13940   if (modrm.mod == 3)
13941     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13942     BadOp ();
13943   else
13944     OP_E (bytemode, sizeflag);
13945 }
13946
13947 static void
13948 OP_0f07 (int bytemode, int sizeflag)
13949 {
13950   if (modrm.mod != 3 || modrm.rm != 0)
13951     BadOp ();
13952   else
13953     OP_E (bytemode, sizeflag);
13954 }
13955
13956 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13957    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13958
13959 static void
13960 NOP_Fixup1 (int bytemode, int sizeflag)
13961 {
13962   if ((prefixes & PREFIX_DATA) != 0
13963       || (rex != 0
13964           && rex != 0x48
13965           && address_mode == mode_64bit))
13966     OP_REG (bytemode, sizeflag);
13967   else
13968     strcpy (obuf, "nop");
13969 }
13970
13971 static void
13972 NOP_Fixup2 (int bytemode, int sizeflag)
13973 {
13974   if ((prefixes & PREFIX_DATA) != 0
13975       || (rex != 0
13976           && rex != 0x48
13977           && address_mode == mode_64bit))
13978     OP_IMREG (bytemode, sizeflag);
13979 }
13980
13981 static const char *const Suffix3DNow[] = {
13982 /* 00 */        NULL,           NULL,           NULL,           NULL,
13983 /* 04 */        NULL,           NULL,           NULL,           NULL,
13984 /* 08 */        NULL,           NULL,           NULL,           NULL,
13985 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13986 /* 10 */        NULL,           NULL,           NULL,           NULL,
13987 /* 14 */        NULL,           NULL,           NULL,           NULL,
13988 /* 18 */        NULL,           NULL,           NULL,           NULL,
13989 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13990 /* 20 */        NULL,           NULL,           NULL,           NULL,
13991 /* 24 */        NULL,           NULL,           NULL,           NULL,
13992 /* 28 */        NULL,           NULL,           NULL,           NULL,
13993 /* 2C */        NULL,           NULL,           NULL,           NULL,
13994 /* 30 */        NULL,           NULL,           NULL,           NULL,
13995 /* 34 */        NULL,           NULL,           NULL,           NULL,
13996 /* 38 */        NULL,           NULL,           NULL,           NULL,
13997 /* 3C */        NULL,           NULL,           NULL,           NULL,
13998 /* 40 */        NULL,           NULL,           NULL,           NULL,
13999 /* 44 */        NULL,           NULL,           NULL,           NULL,
14000 /* 48 */        NULL,           NULL,           NULL,           NULL,
14001 /* 4C */        NULL,           NULL,           NULL,           NULL,
14002 /* 50 */        NULL,           NULL,           NULL,           NULL,
14003 /* 54 */        NULL,           NULL,           NULL,           NULL,
14004 /* 58 */        NULL,           NULL,           NULL,           NULL,
14005 /* 5C */        NULL,           NULL,           NULL,           NULL,
14006 /* 60 */        NULL,           NULL,           NULL,           NULL,
14007 /* 64 */        NULL,           NULL,           NULL,           NULL,
14008 /* 68 */        NULL,           NULL,           NULL,           NULL,
14009 /* 6C */        NULL,           NULL,           NULL,           NULL,
14010 /* 70 */        NULL,           NULL,           NULL,           NULL,
14011 /* 74 */        NULL,           NULL,           NULL,           NULL,
14012 /* 78 */        NULL,           NULL,           NULL,           NULL,
14013 /* 7C */        NULL,           NULL,           NULL,           NULL,
14014 /* 80 */        NULL,           NULL,           NULL,           NULL,
14015 /* 84 */        NULL,           NULL,           NULL,           NULL,
14016 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14017 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14018 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14019 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14020 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14021 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14022 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14023 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14024 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14025 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14026 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14027 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14028 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14029 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14030 /* C0 */        NULL,           NULL,           NULL,           NULL,
14031 /* C4 */        NULL,           NULL,           NULL,           NULL,
14032 /* C8 */        NULL,           NULL,           NULL,           NULL,
14033 /* CC */        NULL,           NULL,           NULL,           NULL,
14034 /* D0 */        NULL,           NULL,           NULL,           NULL,
14035 /* D4 */        NULL,           NULL,           NULL,           NULL,
14036 /* D8 */        NULL,           NULL,           NULL,           NULL,
14037 /* DC */        NULL,           NULL,           NULL,           NULL,
14038 /* E0 */        NULL,           NULL,           NULL,           NULL,
14039 /* E4 */        NULL,           NULL,           NULL,           NULL,
14040 /* E8 */        NULL,           NULL,           NULL,           NULL,
14041 /* EC */        NULL,           NULL,           NULL,           NULL,
14042 /* F0 */        NULL,           NULL,           NULL,           NULL,
14043 /* F4 */        NULL,           NULL,           NULL,           NULL,
14044 /* F8 */        NULL,           NULL,           NULL,           NULL,
14045 /* FC */        NULL,           NULL,           NULL,           NULL,
14046 };
14047
14048 static void
14049 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14050 {
14051   const char *mnemonic;
14052
14053   FETCH_DATA (the_info, codep + 1);
14054   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14055      place where an 8-bit immediate would normally go.  ie. the last
14056      byte of the instruction.  */
14057   obufp = mnemonicendp;
14058   mnemonic = Suffix3DNow[*codep++ & 0xff];
14059   if (mnemonic)
14060     oappend (mnemonic);
14061   else
14062     {
14063       /* Since a variable sized modrm/sib chunk is between the start
14064          of the opcode (0x0f0f) and the opcode suffix, we need to do
14065          all the modrm processing first, and don't know until now that
14066          we have a bad opcode.  This necessitates some cleaning up.  */
14067       op_out[0][0] = '\0';
14068       op_out[1][0] = '\0';
14069       BadOp ();
14070     }
14071   mnemonicendp = obufp;
14072 }
14073
14074 static struct op simd_cmp_op[] =
14075 {
14076   { STRING_COMMA_LEN ("eq") },
14077   { STRING_COMMA_LEN ("lt") },
14078   { STRING_COMMA_LEN ("le") },
14079   { STRING_COMMA_LEN ("unord") },
14080   { STRING_COMMA_LEN ("neq") },
14081   { STRING_COMMA_LEN ("nlt") },
14082   { STRING_COMMA_LEN ("nle") },
14083   { STRING_COMMA_LEN ("ord") }
14084 };
14085
14086 static void
14087 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14088 {
14089   unsigned int cmp_type;
14090
14091   FETCH_DATA (the_info, codep + 1);
14092   cmp_type = *codep++ & 0xff;
14093   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14094     {
14095       char suffix [3];
14096       char *p = mnemonicendp - 2;
14097       suffix[0] = p[0];
14098       suffix[1] = p[1];
14099       suffix[2] = '\0';
14100       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14101       mnemonicendp += simd_cmp_op[cmp_type].len;
14102     }
14103   else
14104     {
14105       /* We have a reserved extension byte.  Output it directly.  */
14106       scratchbuf[0] = '$';
14107       print_operand_value (scratchbuf + 1, 1, cmp_type);
14108       oappend (scratchbuf + intel_syntax);
14109       scratchbuf[0] = '\0';
14110     }
14111 }
14112
14113 static void
14114 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14115           int sizeflag ATTRIBUTE_UNUSED)
14116 {
14117   /* mwait %eax,%ecx  */
14118   if (!intel_syntax)
14119     {
14120       const char **names = (address_mode == mode_64bit
14121                             ? names64 : names32);
14122       strcpy (op_out[0], names[0]);
14123       strcpy (op_out[1], names[1]);
14124       two_source_ops = 1;
14125     }
14126   /* Skip mod/rm byte.  */
14127   MODRM_CHECK;
14128   codep++;
14129 }
14130
14131 static void
14132 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14133             int sizeflag ATTRIBUTE_UNUSED)
14134 {
14135   /* monitor %eax,%ecx,%edx"  */
14136   if (!intel_syntax)
14137     {
14138       const char **op1_names;
14139       const char **names = (address_mode == mode_64bit
14140                             ? names64 : names32);
14141
14142       if (!(prefixes & PREFIX_ADDR))
14143         op1_names = (address_mode == mode_16bit
14144                      ? names16 : names);
14145       else
14146         {
14147           /* Remove "addr16/addr32".  */
14148           all_prefixes[last_addr_prefix] = 0;
14149           op1_names = (address_mode != mode_32bit
14150                        ? names32 : names16);
14151           used_prefixes |= PREFIX_ADDR;
14152         }
14153       strcpy (op_out[0], op1_names[0]);
14154       strcpy (op_out[1], names[1]);
14155       strcpy (op_out[2], names[2]);
14156       two_source_ops = 1;
14157     }
14158   /* Skip mod/rm byte.  */
14159   MODRM_CHECK;
14160   codep++;
14161 }
14162
14163 static void
14164 BadOp (void)
14165 {
14166   /* Throw away prefixes and 1st. opcode byte.  */
14167   codep = insn_codep + 1;
14168   oappend ("(bad)");
14169 }
14170
14171 static void
14172 REP_Fixup (int bytemode, int sizeflag)
14173 {
14174   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14175      lods and stos.  */
14176   if (prefixes & PREFIX_REPZ)
14177     all_prefixes[last_repz_prefix] = REP_PREFIX;
14178
14179   switch (bytemode)
14180     {
14181     case al_reg:
14182     case eAX_reg:
14183     case indir_dx_reg:
14184       OP_IMREG (bytemode, sizeflag);
14185       break;
14186     case eDI_reg:
14187       OP_ESreg (bytemode, sizeflag);
14188       break;
14189     case eSI_reg:
14190       OP_DSreg (bytemode, sizeflag);
14191       break;
14192     default:
14193       abort ();
14194       break;
14195     }
14196 }
14197
14198 static void
14199 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14200 {
14201   USED_REX (REX_W);
14202   if (rex & REX_W)
14203     {
14204       /* Change cmpxchg8b to cmpxchg16b.  */
14205       char *p = mnemonicendp - 2;
14206       mnemonicendp = stpcpy (p, "16b");
14207       bytemode = o_mode;
14208     }
14209   OP_M (bytemode, sizeflag);
14210 }
14211
14212 static void
14213 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14214 {
14215   const char **names;
14216
14217   if (need_vex)
14218     {
14219       switch (vex.length)
14220         {
14221         case 128:
14222           names = names_xmm;
14223           break;
14224         case 256:
14225           names = names_ymm;
14226           break;
14227         default:
14228           abort ();
14229         }
14230     }
14231   else
14232     names = names_xmm;
14233   oappend (names[reg]);
14234 }
14235
14236 static void
14237 CRC32_Fixup (int bytemode, int sizeflag)
14238 {
14239   /* Add proper suffix to "crc32".  */
14240   char *p = mnemonicendp;
14241
14242   switch (bytemode)
14243     {
14244     case b_mode:
14245       if (intel_syntax)
14246         goto skip;
14247
14248       *p++ = 'b';
14249       break;
14250     case v_mode:
14251       if (intel_syntax)
14252         goto skip;
14253
14254       USED_REX (REX_W);
14255       if (rex & REX_W)
14256         *p++ = 'q';
14257       else
14258         {
14259           if (sizeflag & DFLAG)
14260             *p++ = 'l';
14261           else
14262             *p++ = 'w';
14263           used_prefixes |= (prefixes & PREFIX_DATA);
14264         }
14265       break;
14266     default:
14267       oappend (INTERNAL_DISASSEMBLER_ERROR);
14268       break;
14269     }
14270   mnemonicendp = p;
14271   *p = '\0';
14272
14273 skip:
14274   if (modrm.mod == 3)
14275     {
14276       int add;
14277
14278       /* Skip mod/rm byte.  */
14279       MODRM_CHECK;
14280       codep++;
14281
14282       USED_REX (REX_B);
14283       add = (rex & REX_B) ? 8 : 0;
14284       if (bytemode == b_mode)
14285         {
14286           USED_REX (0);
14287           if (rex)
14288             oappend (names8rex[modrm.rm + add]);
14289           else
14290             oappend (names8[modrm.rm + add]);
14291         }
14292       else
14293         {
14294           USED_REX (REX_W);
14295           if (rex & REX_W)
14296             oappend (names64[modrm.rm + add]);
14297           else if ((prefixes & PREFIX_DATA))
14298             oappend (names16[modrm.rm + add]);
14299           else
14300             oappend (names32[modrm.rm + add]);
14301         }
14302     }
14303   else
14304     OP_E (bytemode, sizeflag);
14305 }
14306
14307 static void
14308 FXSAVE_Fixup (int bytemode, int sizeflag)
14309 {
14310   /* Add proper suffix to "fxsave" and "fxrstor".  */
14311   USED_REX (REX_W);
14312   if (rex & REX_W)
14313     {
14314       char *p = mnemonicendp;
14315       *p++ = '6';
14316       *p++ = '4';
14317       *p = '\0';
14318       mnemonicendp = p;
14319     }
14320   OP_M (bytemode, sizeflag);
14321 }
14322
14323 /* Display the destination register operand for instructions with
14324    VEX. */
14325
14326 static void
14327 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14328 {
14329   const char **names;
14330
14331   if (!need_vex)
14332     abort ();
14333
14334   if (!need_vex_reg)
14335     return;
14336
14337   switch (vex.length)
14338     {
14339     case 128:
14340       switch (bytemode)
14341         {
14342         case vex_mode:
14343         case vex128_mode:
14344           break;
14345         default:
14346           abort ();
14347           return;
14348         }
14349
14350       names = names_xmm;
14351       break;
14352     case 256:
14353       switch (bytemode)
14354         {
14355         case vex_mode:
14356         case vex256_mode:
14357           break;
14358         default:
14359           abort ();
14360           return;
14361         }
14362
14363       names = names_ymm;
14364       break;
14365     default:
14366       abort ();
14367       break;
14368     }
14369   oappend (names[vex.register_specifier]);
14370 }
14371
14372 /* Get the VEX immediate byte without moving codep.  */
14373
14374 static unsigned char
14375 get_vex_imm8 (int sizeflag, int opnum)
14376 {
14377   int bytes_before_imm = 0;
14378
14379   if (modrm.mod != 3)
14380     {
14381       /* There are SIB/displacement bytes.  */
14382       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14383         {
14384           /* 32/64 bit address mode */
14385           int base = modrm.rm;
14386
14387           /* Check SIB byte.  */
14388           if (base == 4)
14389             {
14390               FETCH_DATA (the_info, codep + 1);
14391               base = *codep & 7;
14392               /* When decoding the third source, don't increase
14393                  bytes_before_imm as this has already been incremented
14394                  by one in OP_E_memory while decoding the second
14395                  source operand.  */
14396               if (opnum == 0)
14397                 bytes_before_imm++;
14398             }
14399
14400           /* Don't increase bytes_before_imm when decoding the third source,
14401              it has already been incremented by OP_E_memory while decoding
14402              the second source operand.  */
14403           if (opnum == 0)
14404             {
14405               switch (modrm.mod)
14406                 {
14407                   case 0:
14408                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14409                        SIB == 5, there is a 4 byte displacement.  */
14410                     if (base != 5)
14411                       /* No displacement. */
14412                       break;
14413                   case 2:
14414                     /* 4 byte displacement.  */
14415                     bytes_before_imm += 4;
14416                     break;
14417                   case 1:
14418                     /* 1 byte displacement.  */
14419                     bytes_before_imm++;
14420                     break;
14421                 }
14422             }
14423         }
14424       else
14425         {
14426           /* 16 bit address mode */
14427           /* Don't increase bytes_before_imm when decoding the third source,
14428              it has already been incremented by OP_E_memory while decoding
14429              the second source operand.  */
14430           if (opnum == 0)
14431             {
14432               switch (modrm.mod)
14433                 {
14434                 case 0:
14435                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14436                   if (modrm.rm != 6)
14437                     /* No displacement. */
14438                     break;
14439                 case 2:
14440                   /* 2 byte displacement.  */
14441                   bytes_before_imm += 2;
14442                   break;
14443                 case 1:
14444                   /* 1 byte displacement: when decoding the third source,
14445                      don't increase bytes_before_imm as this has already
14446                      been incremented by one in OP_E_memory while decoding
14447                      the second source operand.  */
14448                   if (opnum == 0)
14449                     bytes_before_imm++;
14450
14451                   break;
14452                 }
14453             }
14454         }
14455     }
14456
14457   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14458   return codep [bytes_before_imm];
14459 }
14460
14461 static void
14462 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14463 {
14464   const char **names;
14465
14466   if (reg == -1 && modrm.mod != 3)
14467     {
14468       OP_E_memory (bytemode, sizeflag);
14469       return;
14470     }
14471   else
14472     {
14473       if (reg == -1)
14474         {
14475           reg = modrm.rm;
14476           USED_REX (REX_B);
14477           if (rex & REX_B)
14478             reg += 8;
14479         }
14480       else if (reg > 7 && address_mode != mode_64bit)
14481         BadOp ();
14482     }
14483
14484   switch (vex.length)
14485     {
14486     case 128:
14487       names = names_xmm;
14488       break;
14489     case 256:
14490       names = names_ymm;
14491       break;
14492     default:
14493       abort ();
14494     }
14495   oappend (names[reg]);
14496 }
14497
14498 static void
14499 OP_Vex_2src (int bytemode, int sizeflag)
14500 {
14501   if (modrm.mod == 3)
14502     {
14503       int reg = modrm.rm;
14504       USED_REX (REX_B);
14505       if (rex & REX_B)
14506         reg += 8;
14507       oappend (names_xmm[reg]);
14508     }
14509   else
14510     {
14511       if (intel_syntax
14512           && (bytemode == v_mode || bytemode == v_swap_mode))
14513         {
14514           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14515           used_prefixes |= (prefixes & PREFIX_DATA);
14516         }
14517       OP_E (bytemode, sizeflag);
14518     }
14519 }
14520
14521 static void
14522 OP_Vex_2src_1 (int bytemode, int sizeflag)
14523 {
14524   if (modrm.mod == 3)
14525     {
14526       /* Skip mod/rm byte.   */
14527       MODRM_CHECK;
14528       codep++;
14529     }
14530
14531   if (vex.w)
14532     oappend (names_xmm[vex.register_specifier]);
14533   else
14534     OP_Vex_2src (bytemode, sizeflag);
14535 }
14536
14537 static void
14538 OP_Vex_2src_2 (int bytemode, int sizeflag)
14539 {
14540   if (vex.w)
14541     OP_Vex_2src (bytemode, sizeflag);
14542   else
14543     oappend (names_xmm[vex.register_specifier]);
14544 }
14545
14546 static void
14547 OP_EX_VexW (int bytemode, int sizeflag)
14548 {
14549   int reg = -1;
14550
14551   if (!vex_w_done)
14552     {
14553       vex_w_done = 1;
14554
14555       /* Skip mod/rm byte.  */
14556       MODRM_CHECK;
14557       codep++;
14558
14559       if (vex.w)
14560         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14561     }
14562   else
14563     {
14564       if (!vex.w)
14565         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14566     }
14567
14568   OP_EX_VexReg (bytemode, sizeflag, reg);
14569 }
14570
14571 static void
14572 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14573              int sizeflag ATTRIBUTE_UNUSED)
14574 {
14575   /* Skip the immediate byte and check for invalid bits.  */
14576   FETCH_DATA (the_info, codep + 1);
14577   if (*codep++ & 0xf)
14578     BadOp ();
14579 }
14580
14581 static void
14582 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14583 {
14584   int reg;
14585   const char **names;
14586
14587   FETCH_DATA (the_info, codep + 1);
14588   reg = *codep++;
14589
14590   if (bytemode != x_mode)
14591     abort ();
14592
14593   if (reg & 0xf)
14594       BadOp ();
14595
14596   reg >>= 4;
14597   if (reg > 7 && address_mode != mode_64bit)
14598     BadOp ();
14599
14600   switch (vex.length)
14601     {
14602     case 128:
14603       names = names_xmm;
14604       break;
14605     case 256:
14606       names = names_ymm;
14607       break;
14608     default:
14609       abort ();
14610     }
14611   oappend (names[reg]);
14612 }
14613
14614 static void
14615 OP_XMM_VexW (int bytemode, int sizeflag)
14616 {
14617   /* Turn off the REX.W bit since it is used for swapping operands
14618      now.  */
14619   rex &= ~REX_W;
14620   OP_XMM (bytemode, sizeflag);
14621 }
14622
14623 static void
14624 OP_EX_Vex (int bytemode, int sizeflag)
14625 {
14626   if (modrm.mod != 3)
14627     {
14628       if (vex.register_specifier != 0)
14629         BadOp ();
14630       need_vex_reg = 0;
14631     }
14632   OP_EX (bytemode, sizeflag);
14633 }
14634
14635 static void
14636 OP_XMM_Vex (int bytemode, int sizeflag)
14637 {
14638   if (modrm.mod != 3)
14639     {
14640       if (vex.register_specifier != 0)
14641         BadOp ();
14642       need_vex_reg = 0;
14643     }
14644   OP_XMM (bytemode, sizeflag);
14645 }
14646
14647 static void
14648 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14649 {
14650   switch (vex.length)
14651     {
14652     case 128:
14653       mnemonicendp = stpcpy (obuf, "vzeroupper");
14654       break;
14655     case 256:
14656       mnemonicendp = stpcpy (obuf, "vzeroall");
14657       break;
14658     default:
14659       abort ();
14660     }
14661 }
14662
14663 static struct op vex_cmp_op[] =
14664 {
14665   { STRING_COMMA_LEN ("eq") },
14666   { STRING_COMMA_LEN ("lt") },
14667   { STRING_COMMA_LEN ("le") },
14668   { STRING_COMMA_LEN ("unord") },
14669   { STRING_COMMA_LEN ("neq") },
14670   { STRING_COMMA_LEN ("nlt") },
14671   { STRING_COMMA_LEN ("nle") },
14672   { STRING_COMMA_LEN ("ord") },
14673   { STRING_COMMA_LEN ("eq_uq") },
14674   { STRING_COMMA_LEN ("nge") },
14675   { STRING_COMMA_LEN ("ngt") },
14676   { STRING_COMMA_LEN ("false") },
14677   { STRING_COMMA_LEN ("neq_oq") },
14678   { STRING_COMMA_LEN ("ge") },
14679   { STRING_COMMA_LEN ("gt") },
14680   { STRING_COMMA_LEN ("true") },
14681   { STRING_COMMA_LEN ("eq_os") },
14682   { STRING_COMMA_LEN ("lt_oq") },
14683   { STRING_COMMA_LEN ("le_oq") },
14684   { STRING_COMMA_LEN ("unord_s") },
14685   { STRING_COMMA_LEN ("neq_us") },
14686   { STRING_COMMA_LEN ("nlt_uq") },
14687   { STRING_COMMA_LEN ("nle_uq") },
14688   { STRING_COMMA_LEN ("ord_s") },
14689   { STRING_COMMA_LEN ("eq_us") },
14690   { STRING_COMMA_LEN ("nge_uq") },
14691   { STRING_COMMA_LEN ("ngt_uq") },
14692   { STRING_COMMA_LEN ("false_os") },
14693   { STRING_COMMA_LEN ("neq_os") },
14694   { STRING_COMMA_LEN ("ge_oq") },
14695   { STRING_COMMA_LEN ("gt_oq") },
14696   { STRING_COMMA_LEN ("true_us") },
14697 };
14698
14699 static void
14700 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14701 {
14702   unsigned int cmp_type;
14703
14704   FETCH_DATA (the_info, codep + 1);
14705   cmp_type = *codep++ & 0xff;
14706   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14707     {
14708       char suffix [3];
14709       char *p = mnemonicendp - 2;
14710       suffix[0] = p[0];
14711       suffix[1] = p[1];
14712       suffix[2] = '\0';
14713       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14714       mnemonicendp += vex_cmp_op[cmp_type].len;
14715     }
14716   else
14717     {
14718       /* We have a reserved extension byte.  Output it directly.  */
14719       scratchbuf[0] = '$';
14720       print_operand_value (scratchbuf + 1, 1, cmp_type);
14721       oappend (scratchbuf + intel_syntax);
14722       scratchbuf[0] = '\0';
14723     }
14724 }
14725
14726 static const struct op pclmul_op[] =
14727 {
14728   { STRING_COMMA_LEN ("lql") },
14729   { STRING_COMMA_LEN ("hql") },
14730   { STRING_COMMA_LEN ("lqh") },
14731   { STRING_COMMA_LEN ("hqh") }
14732 };
14733
14734 static void
14735 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14736               int sizeflag ATTRIBUTE_UNUSED)
14737 {
14738   unsigned int pclmul_type;
14739
14740   FETCH_DATA (the_info, codep + 1);
14741   pclmul_type = *codep++ & 0xff;
14742   switch (pclmul_type)
14743     {
14744     case 0x10:
14745       pclmul_type = 2;
14746       break;
14747     case 0x11:
14748       pclmul_type = 3;
14749       break;
14750     default:
14751       break;
14752     }
14753   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14754     {
14755       char suffix [4];
14756       char *p = mnemonicendp - 3;
14757       suffix[0] = p[0];
14758       suffix[1] = p[1];
14759       suffix[2] = p[2];
14760       suffix[3] = '\0';
14761       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14762       mnemonicendp += pclmul_op[pclmul_type].len;
14763     }
14764   else
14765     {
14766       /* We have a reserved extension byte.  Output it directly.  */
14767       scratchbuf[0] = '$';
14768       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14769       oappend (scratchbuf + intel_syntax);
14770       scratchbuf[0] = '\0';
14771     }
14772 }
14773
14774 static void
14775 MOVBE_Fixup (int bytemode, int sizeflag)
14776 {
14777   /* Add proper suffix to "movbe".  */
14778   char *p = mnemonicendp;
14779
14780   switch (bytemode)
14781     {
14782     case v_mode:
14783       if (intel_syntax)
14784         goto skip;
14785
14786       USED_REX (REX_W);
14787       if (sizeflag & SUFFIX_ALWAYS)
14788         {
14789           if (rex & REX_W)
14790             *p++ = 'q';
14791           else
14792             {
14793               if (sizeflag & DFLAG)
14794                 *p++ = 'l';
14795               else
14796                 *p++ = 'w';
14797               used_prefixes |= (prefixes & PREFIX_DATA);
14798             }
14799         }
14800       break;
14801     default:
14802       oappend (INTERNAL_DISASSEMBLER_ERROR);
14803       break;
14804     }
14805   mnemonicendp = p;
14806   *p = '\0';
14807
14808 skip:
14809   OP_M (bytemode, sizeflag);
14810 }
14811
14812 static void
14813 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14814 {
14815   int reg;
14816   const char **names;
14817
14818   /* Skip mod/rm byte.  */
14819   MODRM_CHECK;
14820   codep++;
14821
14822   if (vex.w)
14823     names = names64;
14824   else if (vex.length == 256)
14825     names = names32;
14826   else
14827     names = names16;
14828
14829   reg = modrm.rm;
14830   USED_REX (REX_B);
14831   if (rex & REX_B)
14832     reg += 8;
14833
14834   oappend (names[reg]);
14835 }
14836
14837 static void
14838 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14839 {
14840   const char **names;
14841
14842   if (vex.w)
14843     names = names64;
14844   else if (vex.length == 256)
14845     names = names32;
14846   else
14847     names = names16;
14848
14849   oappend (names[vex.register_specifier]);
14850 }
14851
14852 static void
14853 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
14854 {
14855   if (vex.w || vex.length == 256)
14856     OP_I (q_mode, sizeflag);
14857   else
14858     OP_I (w_mode, sizeflag);
14859 }
14860