opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void CMPXCHG8B_Fixup (int, int);
 111 static void XMM_Fixup (int, int);
 112 static void CRC32_Fixup (int, int);
 113 static void FXSAVE_Fixup (int, int);
 114 static void OP_LWPCB_E (int, int);
 115 static void OP_LWP_E (int, int);
 116 static void OP_LWP_I (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* REX bits in original REX prefix ignored.  */
 148 static int rex_ignored;
 149 /* Mark parts used in the REX prefix.  When we are testing for
 150    empty prefix (for 8bit register REX extension), just mask it
 151    out.  Otherwise test for REX bit is excuse for existence of REX
 152    only in case value is nonzero.  */
 153 #define USED_REX(value)                                 \
 154   {                                                     \
 155     if (value)                                          \
 156       {                                                 \
 157         if ((rex & value))                              \
 158           rex_used |= (value) | REX_OPCODE;             \
 159       }                                                 \
 160     else                                                \
 161       rex_used |= REX_OPCODE;                           \
 162   }
 163
 164 /* Flags for prefixes which we somehow handled when printing the
 165    current instruction.  */
 166 static int used_prefixes;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       longjmp (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 #define XX { NULL, 0 }
 219 #define Bad_Opcode NULL, { { NULL, 0 } }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define Iv { OP_I, v_mode }
 256 #define Iq { OP_I, q_mode }
 257 #define Iv64 { OP_I64, v_mode }
 258 #define Iw { OP_I, w_mode }
 259 #define I1 { OP_I, const_1_mode }
 260 #define Jb { OP_J, b_mode }
 261 #define Jv { OP_J, v_mode }
 262 #define Cm { OP_C, m_mode }
 263 #define Dm { OP_D, m_mode }
 264 #define Td { OP_T, d_mode }
 265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 266
 267 #define RMeAX { OP_REG, eAX_reg }
 268 #define RMeBX { OP_REG, eBX_reg }
 269 #define RMeCX { OP_REG, eCX_reg }
 270 #define RMeDX { OP_REG, eDX_reg }
 271 #define RMeSP { OP_REG, eSP_reg }
 272 #define RMeBP { OP_REG, eBP_reg }
 273 #define RMeSI { OP_REG, eSI_reg }
 274 #define RMeDI { OP_REG, eDI_reg }
 275 #define RMrAX { OP_REG, rAX_reg }
 276 #define RMrBX { OP_REG, rBX_reg }
 277 #define RMrCX { OP_REG, rCX_reg }
 278 #define RMrDX { OP_REG, rDX_reg }
 279 #define RMrSP { OP_REG, rSP_reg }
 280 #define RMrBP { OP_REG, rBP_reg }
 281 #define RMrSI { OP_REG, rSI_reg }
 282 #define RMrDI { OP_REG, rDI_reg }
 283 #define RMAL { OP_REG, al_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMCL { OP_REG, cl_reg }
 286 #define RMDL { OP_REG, dl_reg }
 287 #define RMBL { OP_REG, bl_reg }
 288 #define RMAH { OP_REG, ah_reg }
 289 #define RMCH { OP_REG, ch_reg }
 290 #define RMDH { OP_REG, dh_reg }
 291 #define RMBH { OP_REG, bh_reg }
 292 #define RMAX { OP_REG, ax_reg }
 293 #define RMDX { OP_REG, dx_reg }
 294
 295 #define eAX { OP_IMREG, eAX_reg }
 296 #define eBX { OP_IMREG, eBX_reg }
 297 #define eCX { OP_IMREG, eCX_reg }
 298 #define eDX { OP_IMREG, eDX_reg }
 299 #define eSP { OP_IMREG, eSP_reg }
 300 #define eBP { OP_IMREG, eBP_reg }
 301 #define eSI { OP_IMREG, eSI_reg }
 302 #define eDI { OP_IMREG, eDI_reg }
 303 #define AL { OP_IMREG, al_reg }
 304 #define CL { OP_IMREG, cl_reg }
 305 #define DL { OP_IMREG, dl_reg }
 306 #define BL { OP_IMREG, bl_reg }
 307 #define AH { OP_IMREG, ah_reg }
 308 #define CH { OP_IMREG, ch_reg }
 309 #define DH { OP_IMREG, dh_reg }
 310 #define BH { OP_IMREG, bh_reg }
 311 #define AX { OP_IMREG, ax_reg }
 312 #define DX { OP_IMREG, dx_reg }
 313 #define zAX { OP_IMREG, z_mode_ax_reg }
 314 #define indirDX { OP_IMREG, indir_dx_reg }
 315
 316 #define Sw { OP_SEG, w_mode }
 317 #define Sv { OP_SEG, v_mode }
 318 #define Ap { OP_DIR, 0 }
 319 #define Ob { OP_OFF64, b_mode }
 320 #define Ov { OP_OFF64, v_mode }
 321 #define Xb { OP_DSreg, eSI_reg }
 322 #define Xv { OP_DSreg, eSI_reg }
 323 #define Xz { OP_DSreg, eSI_reg }
 324 #define Yb { OP_ESreg, eDI_reg }
 325 #define Yv { OP_ESreg, eDI_reg }
 326 #define DSBX { OP_DSreg, eBX_reg }
 327
 328 #define es { OP_REG, es_reg }
 329 #define ss { OP_REG, ss_reg }
 330 #define cs { OP_REG, cs_reg }
 331 #define ds { OP_REG, ds_reg }
 332 #define fs { OP_REG, fs_reg }
 333 #define gs { OP_REG, gs_reg }
 334
 335 #define MX { OP_MMX, 0 }
 336 #define XM { OP_XMM, 0 }
 337 #define XMM { OP_XMM, xmm_mode }
 338 #define EM { OP_EM, v_mode }
 339 #define EMS { OP_EM, v_swap_mode }
 340 #define EMd { OP_EM, d_mode }
 341 #define EMx { OP_EM, x_mode }
 342 #define EXw { OP_EX, w_mode }
 343 #define EXd { OP_EX, d_mode }
 344 #define EXdS { OP_EX, d_swap_mode }
 345 #define EXq { OP_EX, q_mode }
 346 #define EXqS { OP_EX, q_swap_mode }
 347 #define EXx { OP_EX, x_mode }
 348 #define EXxS { OP_EX, x_swap_mode }
 349 #define EXxmm { OP_EX, xmm_mode }
 350 #define EXxmmq { OP_EX, xmmq_mode }
 351 #define EXymmq { OP_EX, ymmq_mode }
 352 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 353 #define MS { OP_MS, v_mode }
 354 #define XS { OP_XS, v_mode }
 355 #define EMCq { OP_EMC, q_mode }
 356 #define MXC { OP_MXC, 0 }
 357 #define OPSUF { OP_3DNowSuffix, 0 }
 358 #define CMP { CMP_Fixup, 0 }
 359 #define XMM0 { XMM_Fixup, 0 }
 360 #define FXSAVE { FXSAVE_Fixup, 0 }
 361 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 362 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 363
 364 #define Vex { OP_VEX, vex_mode }
 365 #define Vex128 { OP_VEX, vex128_mode }
 366 #define Vex256 { OP_VEX, vex256_mode }
 367 #define VexI4 { VEXI4_Fixup, 0}
 368 #define EXdVex { OP_EX_Vex, d_mode }
 369 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 370 #define EXqVex { OP_EX_Vex, q_mode }
 371 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 372 #define EXVexW { OP_EX_VexW, x_mode }
 373 #define EXdVexW { OP_EX_VexW, d_mode }
 374 #define EXqVexW { OP_EX_VexW, q_mode }
 375 #define XMVex { OP_XMM_Vex, 0 }
 376 #define XMVexW { OP_XMM_VexW, 0 }
 377 #define XMVexI4 { OP_REG_VexI4, x_mode }
 378 #define PCLMUL { PCLMUL_Fixup, 0 }
 379 #define VZERO { VZERO_Fixup, 0 }
 380 #define VCMP { VCMP_Fixup, 0 }
 381
 382 /* Used handle "rep" prefix for string instructions.  */
 383 #define Xbr { REP_Fixup, eSI_reg }
 384 #define Xvr { REP_Fixup, eSI_reg }
 385 #define Ybr { REP_Fixup, eDI_reg }
 386 #define Yvr { REP_Fixup, eDI_reg }
 387 #define Yzr { REP_Fixup, eDI_reg }
 388 #define indirDXr { REP_Fixup, indir_dx_reg }
 389 #define ALr { REP_Fixup, al_reg }
 390 #define eAXr { REP_Fixup, eAX_reg }
 391
 392 #define cond_jump_flag { NULL, cond_jump_mode }
 393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 394
 395 /* bits in sizeflag */
 396 #define SUFFIX_ALWAYS 4
 397 #define AFLAG 2
 398 #define DFLAG 1
 399
 400 enum
 401 {
 402   /* byte operand */
 403   b_mode = 1,
 404   /* byte operand with operand swapped */
 405   b_swap_mode,
 406   /* operand size depends on prefixes */
 407   v_mode,
 408   /* operand size depends on prefixes with operand swapped */
 409   v_swap_mode,
 410   /* word operand */
 411   w_mode,
 412   /* double word operand  */
 413   d_mode,
 414   /* double word operand with operand swapped */
 415   d_swap_mode,
 416   /* quad word operand */
 417   q_mode,
 418   /* quad word operand with operand swapped */
 419   q_swap_mode,
 420   /* ten-byte operand */
 421   t_mode,
 422   /* 16-byte XMM or 32-byte YMM operand */
 423   x_mode,
 424   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 425   x_swap_mode,
 426   /* 16-byte XMM operand */
 427   xmm_mode,
 428   /* 16-byte XMM or quad word operand */
 429   xmmq_mode,
 430   /* 32-byte YMM or quad word operand */
 431   ymmq_mode,
 432   /* d_mode in 32bit, q_mode in 64bit mode.  */
 433   m_mode,
 434   /* pair of v_mode operands */
 435   a_mode,
 436   cond_jump_mode,
 437   loop_jcxz_mode,
 438   /* operand size depends on REX prefixes.  */
 439   dq_mode,
 440   /* registers like dq_mode, memory like w_mode.  */
 441   dqw_mode,
 442   /* 4- or 6-byte pointer operand */
 443   f_mode,
 444   const_1_mode,
 445   /* v_mode for stack-related opcodes.  */
 446   stack_v_mode,
 447   /* non-quad operand size depends on prefixes */
 448   z_mode,
 449   /* 16-byte operand */
 450   o_mode,
 451   /* registers like dq_mode, memory like b_mode.  */
 452   dqb_mode,
 453   /* registers like dq_mode, memory like d_mode.  */
 454   dqd_mode,
 455   /* normal vex mode */
 456   vex_mode,
 457   /* 128bit vex mode */
 458   vex128_mode,
 459   /* 256bit vex mode */
 460   vex256_mode,
 461   /* operand size depends on the VEX.W bit.  */
 462   vex_w_dq_mode,
 463
 464   es_reg,
 465   cs_reg,
 466   ss_reg,
 467   ds_reg,
 468   fs_reg,
 469   gs_reg,
 470
 471   eAX_reg,
 472   eCX_reg,
 473   eDX_reg,
 474   eBX_reg,
 475   eSP_reg,
 476   eBP_reg,
 477   eSI_reg,
 478   eDI_reg,
 479
 480   al_reg,
 481   cl_reg,
 482   dl_reg,
 483   bl_reg,
 484   ah_reg,
 485   ch_reg,
 486   dh_reg,
 487   bh_reg,
 488
 489   ax_reg,
 490   cx_reg,
 491   dx_reg,
 492   bx_reg,
 493   sp_reg,
 494   bp_reg,
 495   si_reg,
 496   di_reg,
 497
 498   rAX_reg,
 499   rCX_reg,
 500   rDX_reg,
 501   rBX_reg,
 502   rSP_reg,
 503   rBP_reg,
 504   rSI_reg,
 505   rDI_reg,
 506
 507   z_mode_ax_reg,
 508   indir_dx_reg
 509 };
 510
 511 enum
 512 {
 513   FLOATCODE = 1,
 514   USE_REG_TABLE,
 515   USE_MOD_TABLE,
 516   USE_RM_TABLE,
 517   USE_PREFIX_TABLE,
 518   USE_X86_64_TABLE,
 519   USE_3BYTE_TABLE,
 520   USE_XOP_8F_TABLE,
 521   USE_VEX_C4_TABLE,
 522   USE_VEX_C5_TABLE,
 523   USE_VEX_LEN_TABLE,
 524   USE_VEX_W_TABLE
 525 };
 526
 527 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 528
 529 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 530 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 531 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 532 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 533 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 534 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 535 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 536 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 537 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 538 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 539 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 540 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 541
 542 enum
 543 {
 544   REG_80 = 0,
 545   REG_81,
 546   REG_82,
 547   REG_8F,
 548   REG_C0,
 549   REG_C1,
 550   REG_C6,
 551   REG_C7,
 552   REG_D0,
 553   REG_D1,
 554   REG_D2,
 555   REG_D3,
 556   REG_F6,
 557   REG_F7,
 558   REG_FE,
 559   REG_FF,
 560   REG_0F00,
 561   REG_0F01,
 562   REG_0F0D,
 563   REG_0F18,
 564   REG_0F71,
 565   REG_0F72,
 566   REG_0F73,
 567   REG_0FA6,
 568   REG_0FA7,
 569   REG_0FAE,
 570   REG_0FBA,
 571   REG_0FC7,
 572   REG_VEX_71,
 573   REG_VEX_72,
 574   REG_VEX_73,
 575   REG_VEX_AE,
 576   REG_XOP_LWPCB,
 577   REG_XOP_LWP
 578 };
 579
 580 enum
 581 {
 582   MOD_8D = 0,
 583   MOD_0F01_REG_0,
 584   MOD_0F01_REG_1,
 585   MOD_0F01_REG_2,
 586   MOD_0F01_REG_3,
 587   MOD_0F01_REG_7,
 588   MOD_0F12_PREFIX_0,
 589   MOD_0F13,
 590   MOD_0F16_PREFIX_0,
 591   MOD_0F17,
 592   MOD_0F18_REG_0,
 593   MOD_0F18_REG_1,
 594   MOD_0F18_REG_2,
 595   MOD_0F18_REG_3,
 596   MOD_0F20,
 597   MOD_0F21,
 598   MOD_0F22,
 599   MOD_0F23,
 600   MOD_0F24,
 601   MOD_0F26,
 602   MOD_0F2B_PREFIX_0,
 603   MOD_0F2B_PREFIX_1,
 604   MOD_0F2B_PREFIX_2,
 605   MOD_0F2B_PREFIX_3,
 606   MOD_0F51,
 607   MOD_0F71_REG_2,
 608   MOD_0F71_REG_4,
 609   MOD_0F71_REG_6,
 610   MOD_0F72_REG_2,
 611   MOD_0F72_REG_4,
 612   MOD_0F72_REG_6,
 613   MOD_0F73_REG_2,
 614   MOD_0F73_REG_3,
 615   MOD_0F73_REG_6,
 616   MOD_0F73_REG_7,
 617   MOD_0FAE_REG_0,
 618   MOD_0FAE_REG_1,
 619   MOD_0FAE_REG_2,
 620   MOD_0FAE_REG_3,
 621   MOD_0FAE_REG_4,
 622   MOD_0FAE_REG_5,
 623   MOD_0FAE_REG_6,
 624   MOD_0FAE_REG_7,
 625   MOD_0FB2,
 626   MOD_0FB4,
 627   MOD_0FB5,
 628   MOD_0FC7_REG_6,
 629   MOD_0FC7_REG_7,
 630   MOD_0FD7,
 631   MOD_0FE7_PREFIX_2,
 632   MOD_0FF0_PREFIX_3,
 633   MOD_0F382A_PREFIX_2,
 634   MOD_62_32BIT,
 635   MOD_C4_32BIT,
 636   MOD_C5_32BIT,
 637   MOD_VEX_12_PREFIX_0,
 638   MOD_VEX_13,
 639   MOD_VEX_16_PREFIX_0,
 640   MOD_VEX_17,
 641   MOD_VEX_2B,
 642   MOD_VEX_50,
 643   MOD_VEX_71_REG_2,
 644   MOD_VEX_71_REG_4,
 645   MOD_VEX_71_REG_6,
 646   MOD_VEX_72_REG_2,
 647   MOD_VEX_72_REG_4,
 648   MOD_VEX_72_REG_6,
 649   MOD_VEX_73_REG_2,
 650   MOD_VEX_73_REG_3,
 651   MOD_VEX_73_REG_6,
 652   MOD_VEX_73_REG_7,
 653   MOD_VEX_AE_REG_2,
 654   MOD_VEX_AE_REG_3,
 655   MOD_VEX_D7_PREFIX_2,
 656   MOD_VEX_E7_PREFIX_2,
 657   MOD_VEX_F0_PREFIX_3,
 658   MOD_VEX_3818_PREFIX_2,
 659   MOD_VEX_3819_PREFIX_2,
 660   MOD_VEX_381A_PREFIX_2,
 661   MOD_VEX_382A_PREFIX_2,
 662   MOD_VEX_382C_PREFIX_2,
 663   MOD_VEX_382D_PREFIX_2,
 664   MOD_VEX_382E_PREFIX_2,
 665   MOD_VEX_382F_PREFIX_2
 666 };
 667
 668 enum
 669 {
 670   RM_0F01_REG_0 = 0,
 671   RM_0F01_REG_1,
 672   RM_0F01_REG_2,
 673   RM_0F01_REG_3,
 674   RM_0F01_REG_7,
 675   RM_0FAE_REG_5,
 676   RM_0FAE_REG_6,
 677   RM_0FAE_REG_7
 678 };
 679
 680 enum
 681 {
 682   PREFIX_90 = 0,
 683   PREFIX_0F10,
 684   PREFIX_0F11,
 685   PREFIX_0F12,
 686   PREFIX_0F16,
 687   PREFIX_0F2A,
 688   PREFIX_0F2B,
 689   PREFIX_0F2C,
 690   PREFIX_0F2D,
 691   PREFIX_0F2E,
 692   PREFIX_0F2F,
 693   PREFIX_0F51,
 694   PREFIX_0F52,
 695   PREFIX_0F53,
 696   PREFIX_0F58,
 697   PREFIX_0F59,
 698   PREFIX_0F5A,
 699   PREFIX_0F5B,
 700   PREFIX_0F5C,
 701   PREFIX_0F5D,
 702   PREFIX_0F5E,
 703   PREFIX_0F5F,
 704   PREFIX_0F60,
 705   PREFIX_0F61,
 706   PREFIX_0F62,
 707   PREFIX_0F6C,
 708   PREFIX_0F6D,
 709   PREFIX_0F6F,
 710   PREFIX_0F70,
 711   PREFIX_0F73_REG_3,
 712   PREFIX_0F73_REG_7,
 713   PREFIX_0F78,
 714   PREFIX_0F79,
 715   PREFIX_0F7C,
 716   PREFIX_0F7D,
 717   PREFIX_0F7E,
 718   PREFIX_0F7F,
 719   PREFIX_0FB8,
 720   PREFIX_0FBD,
 721   PREFIX_0FC2,
 722   PREFIX_0FC3,
 723   PREFIX_0FC7_REG_6,
 724   PREFIX_0FD0,
 725   PREFIX_0FD6,
 726   PREFIX_0FE6,
 727   PREFIX_0FE7,
 728   PREFIX_0FF0,
 729   PREFIX_0FF7,
 730   PREFIX_0F3810,
 731   PREFIX_0F3814,
 732   PREFIX_0F3815,
 733   PREFIX_0F3817,
 734   PREFIX_0F3820,
 735   PREFIX_0F3821,
 736   PREFIX_0F3822,
 737   PREFIX_0F3823,
 738   PREFIX_0F3824,
 739   PREFIX_0F3825,
 740   PREFIX_0F3828,
 741   PREFIX_0F3829,
 742   PREFIX_0F382A,
 743   PREFIX_0F382B,
 744   PREFIX_0F3830,
 745   PREFIX_0F3831,
 746   PREFIX_0F3832,
 747   PREFIX_0F3833,
 748   PREFIX_0F3834,
 749   PREFIX_0F3835,
 750   PREFIX_0F3837,
 751   PREFIX_0F3838,
 752   PREFIX_0F3839,
 753   PREFIX_0F383A,
 754   PREFIX_0F383B,
 755   PREFIX_0F383C,
 756   PREFIX_0F383D,
 757   PREFIX_0F383E,
 758   PREFIX_0F383F,
 759   PREFIX_0F3840,
 760   PREFIX_0F3841,
 761   PREFIX_0F3880,
 762   PREFIX_0F3881,
 763   PREFIX_0F38DB,
 764   PREFIX_0F38DC,
 765   PREFIX_0F38DD,
 766   PREFIX_0F38DE,
 767   PREFIX_0F38DF,
 768   PREFIX_0F38F0,
 769   PREFIX_0F38F1,
 770   PREFIX_0F3A08,
 771   PREFIX_0F3A09,
 772   PREFIX_0F3A0A,
 773   PREFIX_0F3A0B,
 774   PREFIX_0F3A0C,
 775   PREFIX_0F3A0D,
 776   PREFIX_0F3A0E,
 777   PREFIX_0F3A14,
 778   PREFIX_0F3A15,
 779   PREFIX_0F3A16,
 780   PREFIX_0F3A17,
 781   PREFIX_0F3A20,
 782   PREFIX_0F3A21,
 783   PREFIX_0F3A22,
 784   PREFIX_0F3A40,
 785   PREFIX_0F3A41,
 786   PREFIX_0F3A42,
 787   PREFIX_0F3A44,
 788   PREFIX_0F3A60,
 789   PREFIX_0F3A61,
 790   PREFIX_0F3A62,
 791   PREFIX_0F3A63,
 792   PREFIX_0F3ADF,
 793   PREFIX_VEX_10,
 794   PREFIX_VEX_11,
 795   PREFIX_VEX_12,
 796   PREFIX_VEX_16,
 797   PREFIX_VEX_2A,
 798   PREFIX_VEX_2C,
 799   PREFIX_VEX_2D,
 800   PREFIX_VEX_2E,
 801   PREFIX_VEX_2F,
 802   PREFIX_VEX_51,
 803   PREFIX_VEX_52,
 804   PREFIX_VEX_53,
 805   PREFIX_VEX_58,
 806   PREFIX_VEX_59,
 807   PREFIX_VEX_5A,
 808   PREFIX_VEX_5B,
 809   PREFIX_VEX_5C,
 810   PREFIX_VEX_5D,
 811   PREFIX_VEX_5E,
 812   PREFIX_VEX_5F,
 813   PREFIX_VEX_60,
 814   PREFIX_VEX_61,
 815   PREFIX_VEX_62,
 816   PREFIX_VEX_63,
 817   PREFIX_VEX_64,
 818   PREFIX_VEX_65,
 819   PREFIX_VEX_66,
 820   PREFIX_VEX_67,
 821   PREFIX_VEX_68,
 822   PREFIX_VEX_69,
 823   PREFIX_VEX_6A,
 824   PREFIX_VEX_6B,
 825   PREFIX_VEX_6C,
 826   PREFIX_VEX_6D,
 827   PREFIX_VEX_6E,
 828   PREFIX_VEX_6F,
 829   PREFIX_VEX_70,
 830   PREFIX_VEX_71_REG_2,
 831   PREFIX_VEX_71_REG_4,
 832   PREFIX_VEX_71_REG_6,
 833   PREFIX_VEX_72_REG_2,
 834   PREFIX_VEX_72_REG_4,
 835   PREFIX_VEX_72_REG_6,
 836   PREFIX_VEX_73_REG_2,
 837   PREFIX_VEX_73_REG_3,
 838   PREFIX_VEX_73_REG_6,
 839   PREFIX_VEX_73_REG_7,
 840   PREFIX_VEX_74,
 841   PREFIX_VEX_75,
 842   PREFIX_VEX_76,
 843   PREFIX_VEX_77,
 844   PREFIX_VEX_7C,
 845   PREFIX_VEX_7D,
 846   PREFIX_VEX_7E,
 847   PREFIX_VEX_7F,
 848   PREFIX_VEX_C2,
 849   PREFIX_VEX_C4,
 850   PREFIX_VEX_C5,
 851   PREFIX_VEX_D0,
 852   PREFIX_VEX_D1,
 853   PREFIX_VEX_D2,
 854   PREFIX_VEX_D3,
 855   PREFIX_VEX_D4,
 856   PREFIX_VEX_D5,
 857   PREFIX_VEX_D6,
 858   PREFIX_VEX_D7,
 859   PREFIX_VEX_D8,
 860   PREFIX_VEX_D9,
 861   PREFIX_VEX_DA,
 862   PREFIX_VEX_DB,
 863   PREFIX_VEX_DC,
 864   PREFIX_VEX_DD,
 865   PREFIX_VEX_DE,
 866   PREFIX_VEX_DF,
 867   PREFIX_VEX_E0,
 868   PREFIX_VEX_E1,
 869   PREFIX_VEX_E2,
 870   PREFIX_VEX_E3,
 871   PREFIX_VEX_E4,
 872   PREFIX_VEX_E5,
 873   PREFIX_VEX_E6,
 874   PREFIX_VEX_E7,
 875   PREFIX_VEX_E8,
 876   PREFIX_VEX_E9,
 877   PREFIX_VEX_EA,
 878   PREFIX_VEX_EB,
 879   PREFIX_VEX_EC,
 880   PREFIX_VEX_ED,
 881   PREFIX_VEX_EE,
 882   PREFIX_VEX_EF,
 883   PREFIX_VEX_F0,
 884   PREFIX_VEX_F1,
 885   PREFIX_VEX_F2,
 886   PREFIX_VEX_F3,
 887   PREFIX_VEX_F4,
 888   PREFIX_VEX_F5,
 889   PREFIX_VEX_F6,
 890   PREFIX_VEX_F7,
 891   PREFIX_VEX_F8,
 892   PREFIX_VEX_F9,
 893   PREFIX_VEX_FA,
 894   PREFIX_VEX_FB,
 895   PREFIX_VEX_FC,
 896   PREFIX_VEX_FD,
 897   PREFIX_VEX_FE,
 898   PREFIX_VEX_3800,
 899   PREFIX_VEX_3801,
 900   PREFIX_VEX_3802,
 901   PREFIX_VEX_3803,
 902   PREFIX_VEX_3804,
 903   PREFIX_VEX_3805,
 904   PREFIX_VEX_3806,
 905   PREFIX_VEX_3807,
 906   PREFIX_VEX_3808,
 907   PREFIX_VEX_3809,
 908   PREFIX_VEX_380A,
 909   PREFIX_VEX_380B,
 910   PREFIX_VEX_380C,
 911   PREFIX_VEX_380D,
 912   PREFIX_VEX_380E,
 913   PREFIX_VEX_380F,
 914   PREFIX_VEX_3817,
 915   PREFIX_VEX_3818,
 916   PREFIX_VEX_3819,
 917   PREFIX_VEX_381A,
 918   PREFIX_VEX_381C,
 919   PREFIX_VEX_381D,
 920   PREFIX_VEX_381E,
 921   PREFIX_VEX_3820,
 922   PREFIX_VEX_3821,
 923   PREFIX_VEX_3822,
 924   PREFIX_VEX_3823,
 925   PREFIX_VEX_3824,
 926   PREFIX_VEX_3825,
 927   PREFIX_VEX_3828,
 928   PREFIX_VEX_3829,
 929   PREFIX_VEX_382A,
 930   PREFIX_VEX_382B,
 931   PREFIX_VEX_382C,
 932   PREFIX_VEX_382D,
 933   PREFIX_VEX_382E,
 934   PREFIX_VEX_382F,
 935   PREFIX_VEX_3830,
 936   PREFIX_VEX_3831,
 937   PREFIX_VEX_3832,
 938   PREFIX_VEX_3833,
 939   PREFIX_VEX_3834,
 940   PREFIX_VEX_3835,
 941   PREFIX_VEX_3837,
 942   PREFIX_VEX_3838,
 943   PREFIX_VEX_3839,
 944   PREFIX_VEX_383A,
 945   PREFIX_VEX_383B,
 946   PREFIX_VEX_383C,
 947   PREFIX_VEX_383D,
 948   PREFIX_VEX_383E,
 949   PREFIX_VEX_383F,
 950   PREFIX_VEX_3840,
 951   PREFIX_VEX_3841,
 952   PREFIX_VEX_3896,
 953   PREFIX_VEX_3897,
 954   PREFIX_VEX_3898,
 955   PREFIX_VEX_3899,
 956   PREFIX_VEX_389A,
 957   PREFIX_VEX_389B,
 958   PREFIX_VEX_389C,
 959   PREFIX_VEX_389D,
 960   PREFIX_VEX_389E,
 961   PREFIX_VEX_389F,
 962   PREFIX_VEX_38A6,
 963   PREFIX_VEX_38A7,
 964   PREFIX_VEX_38A8,
 965   PREFIX_VEX_38A9,
 966   PREFIX_VEX_38AA,
 967   PREFIX_VEX_38AB,
 968   PREFIX_VEX_38AC,
 969   PREFIX_VEX_38AD,
 970   PREFIX_VEX_38AE,
 971   PREFIX_VEX_38AF,
 972   PREFIX_VEX_38B6,
 973   PREFIX_VEX_38B7,
 974   PREFIX_VEX_38B8,
 975   PREFIX_VEX_38B9,
 976   PREFIX_VEX_38BA,
 977   PREFIX_VEX_38BB,
 978   PREFIX_VEX_38BC,
 979   PREFIX_VEX_38BD,
 980   PREFIX_VEX_38BE,
 981   PREFIX_VEX_38BF,
 982   PREFIX_VEX_38DB,
 983   PREFIX_VEX_38DC,
 984   PREFIX_VEX_38DD,
 985   PREFIX_VEX_38DE,
 986   PREFIX_VEX_38DF,
 987   PREFIX_VEX_3A04,
 988   PREFIX_VEX_3A05,
 989   PREFIX_VEX_3A06,
 990   PREFIX_VEX_3A08,
 991   PREFIX_VEX_3A09,
 992   PREFIX_VEX_3A0A,
 993   PREFIX_VEX_3A0B,
 994   PREFIX_VEX_3A0C,
 995   PREFIX_VEX_3A0D,
 996   PREFIX_VEX_3A0E,
 997   PREFIX_VEX_3A0F,
 998   PREFIX_VEX_3A14,
 999   PREFIX_VEX_3A15,
1000   PREFIX_VEX_3A16,
1001   PREFIX_VEX_3A17,
1002   PREFIX_VEX_3A18,
1003   PREFIX_VEX_3A19,
1004   PREFIX_VEX_3A20,
1005   PREFIX_VEX_3A21,
1006   PREFIX_VEX_3A22,
1007   PREFIX_VEX_3A40,
1008   PREFIX_VEX_3A41,
1009   PREFIX_VEX_3A42,
1010   PREFIX_VEX_3A44,
1011   PREFIX_VEX_3A4A,
1012   PREFIX_VEX_3A4B,
1013   PREFIX_VEX_3A4C,
1014   PREFIX_VEX_3A5C,
1015   PREFIX_VEX_3A5D,
1016   PREFIX_VEX_3A5E,
1017   PREFIX_VEX_3A5F,
1018   PREFIX_VEX_3A60,
1019   PREFIX_VEX_3A61,
1020   PREFIX_VEX_3A62,
1021   PREFIX_VEX_3A63,
1022   PREFIX_VEX_3A68,
1023   PREFIX_VEX_3A69,
1024   PREFIX_VEX_3A6A,
1025   PREFIX_VEX_3A6B,
1026   PREFIX_VEX_3A6C,
1027   PREFIX_VEX_3A6D,
1028   PREFIX_VEX_3A6E,
1029   PREFIX_VEX_3A6F,
1030   PREFIX_VEX_3A78,
1031   PREFIX_VEX_3A79,
1032   PREFIX_VEX_3A7A,
1033   PREFIX_VEX_3A7B,
1034   PREFIX_VEX_3A7C,
1035   PREFIX_VEX_3A7D,
1036   PREFIX_VEX_3A7E,
1037   PREFIX_VEX_3A7F,
1038   PREFIX_VEX_3ADF
1039 };
1040
1041 enum
1042 {
1043   X86_64_06 = 0,
1044   X86_64_07,
1045   X86_64_0D,
1046   X86_64_16,
1047   X86_64_17,
1048   X86_64_1E,
1049   X86_64_1F,
1050   X86_64_27,
1051   X86_64_2F,
1052   X86_64_37,
1053   X86_64_3F,
1054   X86_64_60,
1055   X86_64_61,
1056   X86_64_62,
1057   X86_64_63,
1058   X86_64_6D,
1059   X86_64_6F,
1060   X86_64_9A,
1061   X86_64_C4,
1062   X86_64_C5,
1063   X86_64_CE,
1064   X86_64_D4,
1065   X86_64_D5,
1066   X86_64_EA,
1067   X86_64_0F01_REG_0,
1068   X86_64_0F01_REG_1,
1069   X86_64_0F01_REG_2,
1070   X86_64_0F01_REG_3
1071 };
1072
1073 enum
1074 {
1075   THREE_BYTE_0F38 = 0,
1076   THREE_BYTE_0F3A,
1077   THREE_BYTE_0F7A
1078 };
1079
1080 enum
1081 {
1082   XOP_08 = 0,
1083   XOP_09,
1084   XOP_0A
1085 };
1086
1087 enum
1088 {
1089   VEX_0F = 0,
1090   VEX_0F38,
1091   VEX_0F3A
1092 };
1093
1094 enum
1095 {
1096   VEX_LEN_10_P_1 = 0,
1097   VEX_LEN_10_P_3,
1098   VEX_LEN_11_P_1,
1099   VEX_LEN_11_P_3,
1100   VEX_LEN_12_P_0_M_0,
1101   VEX_LEN_12_P_0_M_1,
1102   VEX_LEN_12_P_2,
1103   VEX_LEN_13_M_0,
1104   VEX_LEN_16_P_0_M_0,
1105   VEX_LEN_16_P_0_M_1,
1106   VEX_LEN_16_P_2,
1107   VEX_LEN_17_M_0,
1108   VEX_LEN_2A_P_1,
1109   VEX_LEN_2A_P_3,
1110   VEX_LEN_2C_P_1,
1111   VEX_LEN_2C_P_3,
1112   VEX_LEN_2D_P_1,
1113   VEX_LEN_2D_P_3,
1114   VEX_LEN_2E_P_0,
1115   VEX_LEN_2E_P_2,
1116   VEX_LEN_2F_P_0,
1117   VEX_LEN_2F_P_2,
1118   VEX_LEN_51_P_1,
1119   VEX_LEN_51_P_3,
1120   VEX_LEN_52_P_1,
1121   VEX_LEN_53_P_1,
1122   VEX_LEN_58_P_1,
1123   VEX_LEN_58_P_3,
1124   VEX_LEN_59_P_1,
1125   VEX_LEN_59_P_3,
1126   VEX_LEN_5A_P_1,
1127   VEX_LEN_5A_P_3,
1128   VEX_LEN_5C_P_1,
1129   VEX_LEN_5C_P_3,
1130   VEX_LEN_5D_P_1,
1131   VEX_LEN_5D_P_3,
1132   VEX_LEN_5E_P_1,
1133   VEX_LEN_5E_P_3,
1134   VEX_LEN_5F_P_1,
1135   VEX_LEN_5F_P_3,
1136   VEX_LEN_60_P_2,
1137   VEX_LEN_61_P_2,
1138   VEX_LEN_62_P_2,
1139   VEX_LEN_63_P_2,
1140   VEX_LEN_64_P_2,
1141   VEX_LEN_65_P_2,
1142   VEX_LEN_66_P_2,
1143   VEX_LEN_67_P_2,
1144   VEX_LEN_68_P_2,
1145   VEX_LEN_69_P_2,
1146   VEX_LEN_6A_P_2,
1147   VEX_LEN_6B_P_2,
1148   VEX_LEN_6C_P_2,
1149   VEX_LEN_6D_P_2,
1150   VEX_LEN_6E_P_2,
1151   VEX_LEN_70_P_1,
1152   VEX_LEN_70_P_2,
1153   VEX_LEN_70_P_3,
1154   VEX_LEN_71_R_2_P_2,
1155   VEX_LEN_71_R_4_P_2,
1156   VEX_LEN_71_R_6_P_2,
1157   VEX_LEN_72_R_2_P_2,
1158   VEX_LEN_72_R_4_P_2,
1159   VEX_LEN_72_R_6_P_2,
1160   VEX_LEN_73_R_2_P_2,
1161   VEX_LEN_73_R_3_P_2,
1162   VEX_LEN_73_R_6_P_2,
1163   VEX_LEN_73_R_7_P_2,
1164   VEX_LEN_74_P_2,
1165   VEX_LEN_75_P_2,
1166   VEX_LEN_76_P_2,
1167   VEX_LEN_7E_P_1,
1168   VEX_LEN_7E_P_2,
1169   VEX_LEN_AE_R_2_M_0,
1170   VEX_LEN_AE_R_3_M_0,
1171   VEX_LEN_C2_P_1,
1172   VEX_LEN_C2_P_3,
1173   VEX_LEN_C4_P_2,
1174   VEX_LEN_C5_P_2,
1175   VEX_LEN_D1_P_2,
1176   VEX_LEN_D2_P_2,
1177   VEX_LEN_D3_P_2,
1178   VEX_LEN_D4_P_2,
1179   VEX_LEN_D5_P_2,
1180   VEX_LEN_D6_P_2,
1181   VEX_LEN_D7_P_2_M_1,
1182   VEX_LEN_D8_P_2,
1183   VEX_LEN_D9_P_2,
1184   VEX_LEN_DA_P_2,
1185   VEX_LEN_DB_P_2,
1186   VEX_LEN_DC_P_2,
1187   VEX_LEN_DD_P_2,
1188   VEX_LEN_DE_P_2,
1189   VEX_LEN_DF_P_2,
1190   VEX_LEN_E0_P_2,
1191   VEX_LEN_E1_P_2,
1192   VEX_LEN_E2_P_2,
1193   VEX_LEN_E3_P_2,
1194   VEX_LEN_E4_P_2,
1195   VEX_LEN_E5_P_2,
1196   VEX_LEN_E8_P_2,
1197   VEX_LEN_E9_P_2,
1198   VEX_LEN_EA_P_2,
1199   VEX_LEN_EB_P_2,
1200   VEX_LEN_EC_P_2,
1201   VEX_LEN_ED_P_2,
1202   VEX_LEN_EE_P_2,
1203   VEX_LEN_EF_P_2,
1204   VEX_LEN_F1_P_2,
1205   VEX_LEN_F2_P_2,
1206   VEX_LEN_F3_P_2,
1207   VEX_LEN_F4_P_2,
1208   VEX_LEN_F5_P_2,
1209   VEX_LEN_F6_P_2,
1210   VEX_LEN_F7_P_2,
1211   VEX_LEN_F8_P_2,
1212   VEX_LEN_F9_P_2,
1213   VEX_LEN_FA_P_2,
1214   VEX_LEN_FB_P_2,
1215   VEX_LEN_FC_P_2,
1216   VEX_LEN_FD_P_2,
1217   VEX_LEN_FE_P_2,
1218   VEX_LEN_3800_P_2,
1219   VEX_LEN_3801_P_2,
1220   VEX_LEN_3802_P_2,
1221   VEX_LEN_3803_P_2,
1222   VEX_LEN_3804_P_2,
1223   VEX_LEN_3805_P_2,
1224   VEX_LEN_3806_P_2,
1225   VEX_LEN_3807_P_2,
1226   VEX_LEN_3808_P_2,
1227   VEX_LEN_3809_P_2,
1228   VEX_LEN_380A_P_2,
1229   VEX_LEN_380B_P_2,
1230   VEX_LEN_3819_P_2_M_0,
1231   VEX_LEN_381A_P_2_M_0,
1232   VEX_LEN_381C_P_2,
1233   VEX_LEN_381D_P_2,
1234   VEX_LEN_381E_P_2,
1235   VEX_LEN_3820_P_2,
1236   VEX_LEN_3821_P_2,
1237   VEX_LEN_3822_P_2,
1238   VEX_LEN_3823_P_2,
1239   VEX_LEN_3824_P_2,
1240   VEX_LEN_3825_P_2,
1241   VEX_LEN_3828_P_2,
1242   VEX_LEN_3829_P_2,
1243   VEX_LEN_382A_P_2_M_0,
1244   VEX_LEN_382B_P_2,
1245   VEX_LEN_3830_P_2,
1246   VEX_LEN_3831_P_2,
1247   VEX_LEN_3832_P_2,
1248   VEX_LEN_3833_P_2,
1249   VEX_LEN_3834_P_2,
1250   VEX_LEN_3835_P_2,
1251   VEX_LEN_3837_P_2,
1252   VEX_LEN_3838_P_2,
1253   VEX_LEN_3839_P_2,
1254   VEX_LEN_383A_P_2,
1255   VEX_LEN_383B_P_2,
1256   VEX_LEN_383C_P_2,
1257   VEX_LEN_383D_P_2,
1258   VEX_LEN_383E_P_2,
1259   VEX_LEN_383F_P_2,
1260   VEX_LEN_3840_P_2,
1261   VEX_LEN_3841_P_2,
1262   VEX_LEN_38DB_P_2,
1263   VEX_LEN_38DC_P_2,
1264   VEX_LEN_38DD_P_2,
1265   VEX_LEN_38DE_P_2,
1266   VEX_LEN_38DF_P_2,
1267   VEX_LEN_3A06_P_2,
1268   VEX_LEN_3A0A_P_2,
1269   VEX_LEN_3A0B_P_2,
1270   VEX_LEN_3A0E_P_2,
1271   VEX_LEN_3A0F_P_2,
1272   VEX_LEN_3A14_P_2,
1273   VEX_LEN_3A15_P_2,
1274   VEX_LEN_3A16_P_2,
1275   VEX_LEN_3A17_P_2,
1276   VEX_LEN_3A18_P_2,
1277   VEX_LEN_3A19_P_2,
1278   VEX_LEN_3A20_P_2,
1279   VEX_LEN_3A21_P_2,
1280   VEX_LEN_3A22_P_2,
1281   VEX_LEN_3A41_P_2,
1282   VEX_LEN_3A42_P_2,
1283   VEX_LEN_3A44_P_2,
1284   VEX_LEN_3A4C_P_2,
1285   VEX_LEN_3A60_P_2,
1286   VEX_LEN_3A61_P_2,
1287   VEX_LEN_3A62_P_2,
1288   VEX_LEN_3A63_P_2,
1289   VEX_LEN_3A6A_P_2,
1290   VEX_LEN_3A6B_P_2,
1291   VEX_LEN_3A6E_P_2,
1292   VEX_LEN_3A6F_P_2,
1293   VEX_LEN_3A7A_P_2,
1294   VEX_LEN_3A7B_P_2,
1295   VEX_LEN_3A7E_P_2,
1296   VEX_LEN_3A7F_P_2,
1297   VEX_LEN_3ADF_P_2,
1298   VEX_LEN_XOP_09_80,
1299   VEX_LEN_XOP_09_81
1300 };
1301
1302 enum
1303 {
1304   VEX_W_10_P_0 = 0,
1305   VEX_W_10_P_1,
1306   VEX_W_10_P_2,
1307   VEX_W_10_P_3,
1308   VEX_W_11_P_0,
1309   VEX_W_11_P_1,
1310   VEX_W_11_P_2,
1311   VEX_W_11_P_3,
1312   VEX_W_12_P_0_M_0,
1313   VEX_W_12_P_0_M_1,
1314   VEX_W_12_P_1,
1315   VEX_W_12_P_2,
1316   VEX_W_12_P_3,
1317   VEX_W_13_M_0,
1318   VEX_W_14,
1319   VEX_W_15,
1320   VEX_W_16_P_0_M_0,
1321   VEX_W_16_P_0_M_1,
1322   VEX_W_16_P_1,
1323   VEX_W_16_P_2,
1324   VEX_W_17_M_0,
1325   VEX_W_28,
1326   VEX_W_29,
1327   VEX_W_2B_M_0,
1328   VEX_W_2E_P_0,
1329   VEX_W_2E_P_2,
1330   VEX_W_2F_P_0,
1331   VEX_W_2F_P_2,
1332   VEX_W_50_M_0,
1333   VEX_W_51_P_0,
1334   VEX_W_51_P_1,
1335   VEX_W_51_P_2,
1336   VEX_W_51_P_3,
1337   VEX_W_52_P_0,
1338   VEX_W_52_P_1,
1339   VEX_W_53_P_0,
1340   VEX_W_53_P_1,
1341   VEX_W_58_P_0,
1342   VEX_W_58_P_1,
1343   VEX_W_58_P_2,
1344   VEX_W_58_P_3,
1345   VEX_W_59_P_0,
1346   VEX_W_59_P_1,
1347   VEX_W_59_P_2,
1348   VEX_W_59_P_3,
1349   VEX_W_5A_P_0,
1350   VEX_W_5A_P_1,
1351   VEX_W_5A_P_3,
1352   VEX_W_5B_P_0,
1353   VEX_W_5B_P_1,
1354   VEX_W_5B_P_2,
1355   VEX_W_5C_P_0,
1356   VEX_W_5C_P_1,
1357   VEX_W_5C_P_2,
1358   VEX_W_5C_P_3,
1359   VEX_W_5D_P_0,
1360   VEX_W_5D_P_1,
1361   VEX_W_5D_P_2,
1362   VEX_W_5D_P_3,
1363   VEX_W_5E_P_0,
1364   VEX_W_5E_P_1,
1365   VEX_W_5E_P_2,
1366   VEX_W_5E_P_3,
1367   VEX_W_5F_P_0,
1368   VEX_W_5F_P_1,
1369   VEX_W_5F_P_2,
1370   VEX_W_5F_P_3,
1371   VEX_W_60_P_2,
1372   VEX_W_61_P_2,
1373   VEX_W_62_P_2,
1374   VEX_W_63_P_2,
1375   VEX_W_64_P_2,
1376   VEX_W_65_P_2,
1377   VEX_W_66_P_2,
1378   VEX_W_67_P_2,
1379   VEX_W_68_P_2,
1380   VEX_W_69_P_2,
1381   VEX_W_6A_P_2,
1382   VEX_W_6B_P_2,
1383   VEX_W_6C_P_2,
1384   VEX_W_6D_P_2,
1385   VEX_W_6F_P_1,
1386   VEX_W_6F_P_2,
1387   VEX_W_70_P_1,
1388   VEX_W_70_P_2,
1389   VEX_W_70_P_3,
1390   VEX_W_71_R_2_P_2,
1391   VEX_W_71_R_4_P_2,
1392   VEX_W_71_R_6_P_2,
1393   VEX_W_72_R_2_P_2,
1394   VEX_W_72_R_4_P_2,
1395   VEX_W_72_R_6_P_2,
1396   VEX_W_73_R_2_P_2,
1397   VEX_W_73_R_3_P_2,
1398   VEX_W_73_R_6_P_2,
1399   VEX_W_73_R_7_P_2,
1400   VEX_W_74_P_2,
1401   VEX_W_75_P_2,
1402   VEX_W_76_P_2,
1403   VEX_W_77_P_0,
1404   VEX_W_7C_P_2,
1405   VEX_W_7C_P_3,
1406   VEX_W_7D_P_2,
1407   VEX_W_7D_P_3,
1408   VEX_W_7E_P_1,
1409   VEX_W_7F_P_1,
1410   VEX_W_7F_P_2,
1411   VEX_W_AE_R_2_M_0,
1412   VEX_W_AE_R_3_M_0,
1413   VEX_W_C2_P_0,
1414   VEX_W_C2_P_1,
1415   VEX_W_C2_P_2,
1416   VEX_W_C2_P_3,
1417   VEX_W_C4_P_2,
1418   VEX_W_C5_P_2,
1419   VEX_W_D0_P_2,
1420   VEX_W_D0_P_3,
1421   VEX_W_D1_P_2,
1422   VEX_W_D2_P_2,
1423   VEX_W_D3_P_2,
1424   VEX_W_D4_P_2,
1425   VEX_W_D5_P_2,
1426   VEX_W_D6_P_2,
1427   VEX_W_D7_P_2_M_1,
1428   VEX_W_D8_P_2,
1429   VEX_W_D9_P_2,
1430   VEX_W_DA_P_2,
1431   VEX_W_DB_P_2,
1432   VEX_W_DC_P_2,
1433   VEX_W_DD_P_2,
1434   VEX_W_DE_P_2,
1435   VEX_W_DF_P_2,
1436   VEX_W_E0_P_2,
1437   VEX_W_E1_P_2,
1438   VEX_W_E2_P_2,
1439   VEX_W_E3_P_2,
1440   VEX_W_E4_P_2,
1441   VEX_W_E5_P_2,
1442   VEX_W_E6_P_1,
1443   VEX_W_E6_P_2,
1444   VEX_W_E6_P_3,
1445   VEX_W_E7_P_2_M_0,
1446   VEX_W_E8_P_2,
1447   VEX_W_E9_P_2,
1448   VEX_W_EA_P_2,
1449   VEX_W_EB_P_2,
1450   VEX_W_EC_P_2,
1451   VEX_W_ED_P_2,
1452   VEX_W_EE_P_2,
1453   VEX_W_EF_P_2,
1454   VEX_W_F0_P_3_M_0,
1455   VEX_W_F1_P_2,
1456   VEX_W_F2_P_2,
1457   VEX_W_F3_P_2,
1458   VEX_W_F4_P_2,
1459   VEX_W_F5_P_2,
1460   VEX_W_F6_P_2,
1461   VEX_W_F7_P_2,
1462   VEX_W_F8_P_2,
1463   VEX_W_F9_P_2,
1464   VEX_W_FA_P_2,
1465   VEX_W_FB_P_2,
1466   VEX_W_FC_P_2,
1467   VEX_W_FD_P_2,
1468   VEX_W_FE_P_2,
1469   VEX_W_3800_P_2,
1470   VEX_W_3801_P_2,
1471   VEX_W_3802_P_2,
1472   VEX_W_3803_P_2,
1473   VEX_W_3804_P_2,
1474   VEX_W_3805_P_2,
1475   VEX_W_3806_P_2,
1476   VEX_W_3807_P_2,
1477   VEX_W_3808_P_2,
1478   VEX_W_3809_P_2,
1479   VEX_W_380A_P_2,
1480   VEX_W_380B_P_2,
1481   VEX_W_380C_P_2,
1482   VEX_W_380D_P_2,
1483   VEX_W_380E_P_2,
1484   VEX_W_380F_P_2,
1485   VEX_W_3817_P_2,
1486   VEX_W_3818_P_2_M_0,
1487   VEX_W_3819_P_2_M_0,
1488   VEX_W_381A_P_2_M_0,
1489   VEX_W_381C_P_2,
1490   VEX_W_381D_P_2,
1491   VEX_W_381E_P_2,
1492   VEX_W_3820_P_2,
1493   VEX_W_3821_P_2,
1494   VEX_W_3822_P_2,
1495   VEX_W_3823_P_2,
1496   VEX_W_3824_P_2,
1497   VEX_W_3825_P_2,
1498   VEX_W_3828_P_2,
1499   VEX_W_3829_P_2,
1500   VEX_W_382A_P_2_M_0,
1501   VEX_W_382B_P_2,
1502   VEX_W_382C_P_2_M_0,
1503   VEX_W_382D_P_2_M_0,
1504   VEX_W_382E_P_2_M_0,
1505   VEX_W_382F_P_2_M_0,
1506   VEX_W_3830_P_2,
1507   VEX_W_3831_P_2,
1508   VEX_W_3832_P_2,
1509   VEX_W_3833_P_2,
1510   VEX_W_3834_P_2,
1511   VEX_W_3835_P_2,
1512   VEX_W_3837_P_2,
1513   VEX_W_3838_P_2,
1514   VEX_W_3839_P_2,
1515   VEX_W_383A_P_2,
1516   VEX_W_383B_P_2,
1517   VEX_W_383C_P_2,
1518   VEX_W_383D_P_2,
1519   VEX_W_383E_P_2,
1520   VEX_W_383F_P_2,
1521   VEX_W_3840_P_2,
1522   VEX_W_3841_P_2,
1523   VEX_W_38DB_P_2,
1524   VEX_W_38DC_P_2,
1525   VEX_W_38DD_P_2,
1526   VEX_W_38DE_P_2,
1527   VEX_W_38DF_P_2,
1528   VEX_W_3A04_P_2,
1529   VEX_W_3A05_P_2,
1530   VEX_W_3A06_P_2,
1531   VEX_W_3A08_P_2,
1532   VEX_W_3A09_P_2,
1533   VEX_W_3A0A_P_2,
1534   VEX_W_3A0B_P_2,
1535   VEX_W_3A0C_P_2,
1536   VEX_W_3A0D_P_2,
1537   VEX_W_3A0E_P_2,
1538   VEX_W_3A0F_P_2,
1539   VEX_W_3A14_P_2,
1540   VEX_W_3A15_P_2,
1541   VEX_W_3A18_P_2,
1542   VEX_W_3A19_P_2,
1543   VEX_W_3A20_P_2,
1544   VEX_W_3A21_P_2,
1545   VEX_W_3A40_P_2,
1546   VEX_W_3A41_P_2,
1547   VEX_W_3A42_P_2,
1548   VEX_W_3A44_P_2,
1549   VEX_W_3A4A_P_2,
1550   VEX_W_3A4B_P_2,
1551   VEX_W_3A4C_P_2,
1552   VEX_W_3A60_P_2,
1553   VEX_W_3A61_P_2,
1554   VEX_W_3A62_P_2,
1555   VEX_W_3A63_P_2,
1556   VEX_W_3ADF_P_2
1557 };
1558
1559 typedef void (*op_rtn) (int bytemode, int sizeflag);
1560
1561 struct dis386 {
1562   const char *name;
1563   struct
1564     {
1565       op_rtn rtn;
1566       int bytemode;
1567     } op[MAX_OPERANDS];
1568 };
1569
1570 /* Upper case letters in the instruction names here are macros.
1571    'A' => print 'b' if no register operands or suffix_always is true
1572    'B' => print 'b' if suffix_always is true
1573    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1574           size prefix
1575    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1576           suffix_always is true
1577    'E' => print 'e' if 32-bit form of jcxz
1578    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1579    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1580    'H' => print ",pt" or ",pn" branch hint
1581    'I' => honor following macro letter even in Intel mode (implemented only
1582           for some of the macro letters)
1583    'J' => print 'l'
1584    'K' => print 'd' or 'q' if rex prefix is present.
1585    'L' => print 'l' if suffix_always is true
1586    'M' => print 'r' if intel_mnemonic is false.
1587    'N' => print 'n' if instruction has no wait "prefix"
1588    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1589    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1590           or suffix_always is true.  print 'q' if rex prefix is present.
1591    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1592           is true
1593    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1594    'S' => print 'w', 'l' or 'q' if suffix_always is true
1595    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1596    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1597    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1598    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1599    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1600    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1601           suffix_always is true.
1602    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1603    '!' => change condition from true to false or from false to true.
1604    '%' => add 1 upper case letter to the macro.
1605
1606    2 upper case letter macros:
1607    "XY" => print 'x' or 'y' if no register operands or suffix_always
1608            is true.
1609    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1610    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1611            or suffix_always is true
1612    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1613    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1614    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1615
1616    Many of the above letters print nothing in Intel mode.  See "putop"
1617    for the details.
1618
1619    Braces '{' and '}', and vertical bars '|', indicate alternative
1620    mnemonic strings for AT&T and Intel.  */
1621
1622 static const struct dis386 dis386[] = {
1623   /* 00 */
1624   { "addB",             { Eb, Gb } },
1625   { "addS",             { Ev, Gv } },
1626   { "addB",             { Gb, EbS } },
1627   { "addS",             { Gv, EvS } },
1628   { "addB",             { AL, Ib } },
1629   { "addS",             { eAX, Iv } },
1630   { X86_64_TABLE (X86_64_06) },
1631   { X86_64_TABLE (X86_64_07) },
1632   /* 08 */
1633   { "orB",              { Eb, Gb } },
1634   { "orS",              { Ev, Gv } },
1635   { "orB",              { Gb, EbS } },
1636   { "orS",              { Gv, EvS } },
1637   { "orB",              { AL, Ib } },
1638   { "orS",              { eAX, Iv } },
1639   { X86_64_TABLE (X86_64_0D) },
1640   { Bad_Opcode },       /* 0x0f extended opcode escape */
1641   /* 10 */
1642   { "adcB",             { Eb, Gb } },
1643   { "adcS",             { Ev, Gv } },
1644   { "adcB",             { Gb, EbS } },
1645   { "adcS",             { Gv, EvS } },
1646   { "adcB",             { AL, Ib } },
1647   { "adcS",             { eAX, Iv } },
1648   { X86_64_TABLE (X86_64_16) },
1649   { X86_64_TABLE (X86_64_17) },
1650   /* 18 */
1651   { "sbbB",             { Eb, Gb } },
1652   { "sbbS",             { Ev, Gv } },
1653   { "sbbB",             { Gb, EbS } },
1654   { "sbbS",             { Gv, EvS } },
1655   { "sbbB",             { AL, Ib } },
1656   { "sbbS",             { eAX, Iv } },
1657   { X86_64_TABLE (X86_64_1E) },
1658   { X86_64_TABLE (X86_64_1F) },
1659   /* 20 */
1660   { "andB",             { Eb, Gb } },
1661   { "andS",             { Ev, Gv } },
1662   { "andB",             { Gb, EbS } },
1663   { "andS",             { Gv, EvS } },
1664   { "andB",             { AL, Ib } },
1665   { "andS",             { eAX, Iv } },
1666   { Bad_Opcode },       /* SEG ES prefix */
1667   { X86_64_TABLE (X86_64_27) },
1668   /* 28 */
1669   { "subB",             { Eb, Gb } },
1670   { "subS",             { Ev, Gv } },
1671   { "subB",             { Gb, EbS } },
1672   { "subS",             { Gv, EvS } },
1673   { "subB",             { AL, Ib } },
1674   { "subS",             { eAX, Iv } },
1675   { Bad_Opcode },       /* SEG CS prefix */
1676   { X86_64_TABLE (X86_64_2F) },
1677   /* 30 */
1678   { "xorB",             { Eb, Gb } },
1679   { "xorS",             { Ev, Gv } },
1680   { "xorB",             { Gb, EbS } },
1681   { "xorS",             { Gv, EvS } },
1682   { "xorB",             { AL, Ib } },
1683   { "xorS",             { eAX, Iv } },
1684   { Bad_Opcode },       /* SEG SS prefix */
1685   { X86_64_TABLE (X86_64_37) },
1686   /* 38 */
1687   { "cmpB",             { Eb, Gb } },
1688   { "cmpS",             { Ev, Gv } },
1689   { "cmpB",             { Gb, EbS } },
1690   { "cmpS",             { Gv, EvS } },
1691   { "cmpB",             { AL, Ib } },
1692   { "cmpS",             { eAX, Iv } },
1693   { Bad_Opcode },       /* SEG DS prefix */
1694   { X86_64_TABLE (X86_64_3F) },
1695   /* 40 */
1696   { "inc{S|}",          { RMeAX } },
1697   { "inc{S|}",          { RMeCX } },
1698   { "inc{S|}",          { RMeDX } },
1699   { "inc{S|}",          { RMeBX } },
1700   { "inc{S|}",          { RMeSP } },
1701   { "inc{S|}",          { RMeBP } },
1702   { "inc{S|}",          { RMeSI } },
1703   { "inc{S|}",          { RMeDI } },
1704   /* 48 */
1705   { "dec{S|}",          { RMeAX } },
1706   { "dec{S|}",          { RMeCX } },
1707   { "dec{S|}",          { RMeDX } },
1708   { "dec{S|}",          { RMeBX } },
1709   { "dec{S|}",          { RMeSP } },
1710   { "dec{S|}",          { RMeBP } },
1711   { "dec{S|}",          { RMeSI } },
1712   { "dec{S|}",          { RMeDI } },
1713   /* 50 */
1714   { "pushV",            { RMrAX } },
1715   { "pushV",            { RMrCX } },
1716   { "pushV",            { RMrDX } },
1717   { "pushV",            { RMrBX } },
1718   { "pushV",            { RMrSP } },
1719   { "pushV",            { RMrBP } },
1720   { "pushV",            { RMrSI } },
1721   { "pushV",            { RMrDI } },
1722   /* 58 */
1723   { "popV",             { RMrAX } },
1724   { "popV",             { RMrCX } },
1725   { "popV",             { RMrDX } },
1726   { "popV",             { RMrBX } },
1727   { "popV",             { RMrSP } },
1728   { "popV",             { RMrBP } },
1729   { "popV",             { RMrSI } },
1730   { "popV",             { RMrDI } },
1731   /* 60 */
1732   { X86_64_TABLE (X86_64_60) },
1733   { X86_64_TABLE (X86_64_61) },
1734   { X86_64_TABLE (X86_64_62) },
1735   { X86_64_TABLE (X86_64_63) },
1736   { Bad_Opcode },       /* seg fs */
1737   { Bad_Opcode },       /* seg gs */
1738   { Bad_Opcode },       /* op size prefix */
1739   { Bad_Opcode },       /* adr size prefix */
1740   /* 68 */
1741   { "pushT",            { Iq } },
1742   { "imulS",            { Gv, Ev, Iv } },
1743   { "pushT",            { sIb } },
1744   { "imulS",            { Gv, Ev, sIb } },
1745   { "ins{b|}",          { Ybr, indirDX } },
1746   { X86_64_TABLE (X86_64_6D) },
1747   { "outs{b|}",         { indirDXr, Xb } },
1748   { X86_64_TABLE (X86_64_6F) },
1749   /* 70 */
1750   { "joH",              { Jb, XX, cond_jump_flag } },
1751   { "jnoH",             { Jb, XX, cond_jump_flag } },
1752   { "jbH",              { Jb, XX, cond_jump_flag } },
1753   { "jaeH",             { Jb, XX, cond_jump_flag } },
1754   { "jeH",              { Jb, XX, cond_jump_flag } },
1755   { "jneH",             { Jb, XX, cond_jump_flag } },
1756   { "jbeH",             { Jb, XX, cond_jump_flag } },
1757   { "jaH",              { Jb, XX, cond_jump_flag } },
1758   /* 78 */
1759   { "jsH",              { Jb, XX, cond_jump_flag } },
1760   { "jnsH",             { Jb, XX, cond_jump_flag } },
1761   { "jpH",              { Jb, XX, cond_jump_flag } },
1762   { "jnpH",             { Jb, XX, cond_jump_flag } },
1763   { "jlH",              { Jb, XX, cond_jump_flag } },
1764   { "jgeH",             { Jb, XX, cond_jump_flag } },
1765   { "jleH",             { Jb, XX, cond_jump_flag } },
1766   { "jgH",              { Jb, XX, cond_jump_flag } },
1767   /* 80 */
1768   { REG_TABLE (REG_80) },
1769   { REG_TABLE (REG_81) },
1770   { Bad_Opcode },
1771   { REG_TABLE (REG_82) },
1772   { "testB",            { Eb, Gb } },
1773   { "testS",            { Ev, Gv } },
1774   { "xchgB",            { Eb, Gb } },
1775   { "xchgS",            { Ev, Gv } },
1776   /* 88 */
1777   { "movB",             { Eb, Gb } },
1778   { "movS",             { Ev, Gv } },
1779   { "movB",             { Gb, EbS } },
1780   { "movS",             { Gv, EvS } },
1781   { "movD",             { Sv, Sw } },
1782   { MOD_TABLE (MOD_8D) },
1783   { "movD",             { Sw, Sv } },
1784   { REG_TABLE (REG_8F) },
1785   /* 90 */
1786   { PREFIX_TABLE (PREFIX_90) },
1787   { "xchgS",            { RMeCX, eAX } },
1788   { "xchgS",            { RMeDX, eAX } },
1789   { "xchgS",            { RMeBX, eAX } },
1790   { "xchgS",            { RMeSP, eAX } },
1791   { "xchgS",            { RMeBP, eAX } },
1792   { "xchgS",            { RMeSI, eAX } },
1793   { "xchgS",            { RMeDI, eAX } },
1794   /* 98 */
1795   { "cW{t|}R",          { XX } },
1796   { "cR{t|}O",          { XX } },
1797   { X86_64_TABLE (X86_64_9A) },
1798   { Bad_Opcode },       /* fwait */
1799   { "pushfT",           { XX } },
1800   { "popfT",            { XX } },
1801   { "sahf",             { XX } },
1802   { "lahf",             { XX } },
1803   /* a0 */
1804   { "mov%LB",           { AL, Ob } },
1805   { "mov%LS",           { eAX, Ov } },
1806   { "mov%LB",           { Ob, AL } },
1807   { "mov%LS",           { Ov, eAX } },
1808   { "movs{b|}",         { Ybr, Xb } },
1809   { "movs{R|}",         { Yvr, Xv } },
1810   { "cmps{b|}",         { Xb, Yb } },
1811   { "cmps{R|}",         { Xv, Yv } },
1812   /* a8 */
1813   { "testB",            { AL, Ib } },
1814   { "testS",            { eAX, Iv } },
1815   { "stosB",            { Ybr, AL } },
1816   { "stosS",            { Yvr, eAX } },
1817   { "lodsB",            { ALr, Xb } },
1818   { "lodsS",            { eAXr, Xv } },
1819   { "scasB",            { AL, Yb } },
1820   { "scasS",            { eAX, Yv } },
1821   /* b0 */
1822   { "movB",             { RMAL, Ib } },
1823   { "movB",             { RMCL, Ib } },
1824   { "movB",             { RMDL, Ib } },
1825   { "movB",             { RMBL, Ib } },
1826   { "movB",             { RMAH, Ib } },
1827   { "movB",             { RMCH, Ib } },
1828   { "movB",             { RMDH, Ib } },
1829   { "movB",             { RMBH, Ib } },
1830   /* b8 */
1831   { "mov%LV",           { RMeAX, Iv64 } },
1832   { "mov%LV",           { RMeCX, Iv64 } },
1833   { "mov%LV",           { RMeDX, Iv64 } },
1834   { "mov%LV",           { RMeBX, Iv64 } },
1835   { "mov%LV",           { RMeSP, Iv64 } },
1836   { "mov%LV",           { RMeBP, Iv64 } },
1837   { "mov%LV",           { RMeSI, Iv64 } },
1838   { "mov%LV",           { RMeDI, Iv64 } },
1839   /* c0 */
1840   { REG_TABLE (REG_C0) },
1841   { REG_TABLE (REG_C1) },
1842   { "retT",             { Iw } },
1843   { "retT",             { XX } },
1844   { X86_64_TABLE (X86_64_C4) },
1845   { X86_64_TABLE (X86_64_C5) },
1846   { REG_TABLE (REG_C6) },
1847   { REG_TABLE (REG_C7) },
1848   /* c8 */
1849   { "enterT",           { Iw, Ib } },
1850   { "leaveT",           { XX } },
1851   { "Jret{|f}P",        { Iw } },
1852   { "Jret{|f}P",        { XX } },
1853   { "int3",             { XX } },
1854   { "int",              { Ib } },
1855   { X86_64_TABLE (X86_64_CE) },
1856   { "iretP",            { XX } },
1857   /* d0 */
1858   { REG_TABLE (REG_D0) },
1859   { REG_TABLE (REG_D1) },
1860   { REG_TABLE (REG_D2) },
1861   { REG_TABLE (REG_D3) },
1862   { X86_64_TABLE (X86_64_D4) },
1863   { X86_64_TABLE (X86_64_D5) },
1864   { Bad_Opcode },
1865   { "xlat",             { DSBX } },
1866   /* d8 */
1867   { FLOAT },
1868   { FLOAT },
1869   { FLOAT },
1870   { FLOAT },
1871   { FLOAT },
1872   { FLOAT },
1873   { FLOAT },
1874   { FLOAT },
1875   /* e0 */
1876   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1877   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1878   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1879   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1880   { "inB",              { AL, Ib } },
1881   { "inG",              { zAX, Ib } },
1882   { "outB",             { Ib, AL } },
1883   { "outG",             { Ib, zAX } },
1884   /* e8 */
1885   { "callT",            { Jv } },
1886   { "jmpT",             { Jv } },
1887   { X86_64_TABLE (X86_64_EA) },
1888   { "jmp",              { Jb } },
1889   { "inB",              { AL, indirDX } },
1890   { "inG",              { zAX, indirDX } },
1891   { "outB",             { indirDX, AL } },
1892   { "outG",             { indirDX, zAX } },
1893   /* f0 */
1894   { Bad_Opcode },       /* lock prefix */
1895   { "icebp",            { XX } },
1896   { Bad_Opcode },       /* repne */
1897   { Bad_Opcode },       /* repz */
1898   { "hlt",              { XX } },
1899   { "cmc",              { XX } },
1900   { REG_TABLE (REG_F6) },
1901   { REG_TABLE (REG_F7) },
1902   /* f8 */
1903   { "clc",              { XX } },
1904   { "stc",              { XX } },
1905   { "cli",              { XX } },
1906   { "sti",              { XX } },
1907   { "cld",              { XX } },
1908   { "std",              { XX } },
1909   { REG_TABLE (REG_FE) },
1910   { REG_TABLE (REG_FF) },
1911 };
1912
1913 static const struct dis386 dis386_twobyte[] = {
1914   /* 00 */
1915   { REG_TABLE (REG_0F00 ) },
1916   { REG_TABLE (REG_0F01 ) },
1917   { "larS",             { Gv, Ew } },
1918   { "lslS",             { Gv, Ew } },
1919   { Bad_Opcode },
1920   { "syscall",          { XX } },
1921   { "clts",             { XX } },
1922   { "sysretP",          { XX } },
1923   /* 08 */
1924   { "invd",             { XX } },
1925   { "wbinvd",           { XX } },
1926   { Bad_Opcode },
1927   { "ud2a",             { XX } },
1928   { Bad_Opcode },
1929   { REG_TABLE (REG_0F0D) },
1930   { "femms",            { XX } },
1931   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1932   /* 10 */
1933   { PREFIX_TABLE (PREFIX_0F10) },
1934   { PREFIX_TABLE (PREFIX_0F11) },
1935   { PREFIX_TABLE (PREFIX_0F12) },
1936   { MOD_TABLE (MOD_0F13) },
1937   { "unpcklpX",         { XM, EXx } },
1938   { "unpckhpX",         { XM, EXx } },
1939   { PREFIX_TABLE (PREFIX_0F16) },
1940   { MOD_TABLE (MOD_0F17) },
1941   /* 18 */
1942   { REG_TABLE (REG_0F18) },
1943   { "nopQ",             { Ev } },
1944   { "nopQ",             { Ev } },
1945   { "nopQ",             { Ev } },
1946   { "nopQ",             { Ev } },
1947   { "nopQ",             { Ev } },
1948   { "nopQ",             { Ev } },
1949   { "nopQ",             { Ev } },
1950   /* 20 */
1951   { MOD_TABLE (MOD_0F20) },
1952   { MOD_TABLE (MOD_0F21) },
1953   { MOD_TABLE (MOD_0F22) },
1954   { MOD_TABLE (MOD_0F23) },
1955   { MOD_TABLE (MOD_0F24) },
1956   { Bad_Opcode },
1957   { MOD_TABLE (MOD_0F26) },
1958   { Bad_Opcode },
1959   /* 28 */
1960   { "movapX",           { XM, EXx } },
1961   { "movapX",           { EXxS, XM } },
1962   { PREFIX_TABLE (PREFIX_0F2A) },
1963   { PREFIX_TABLE (PREFIX_0F2B) },
1964   { PREFIX_TABLE (PREFIX_0F2C) },
1965   { PREFIX_TABLE (PREFIX_0F2D) },
1966   { PREFIX_TABLE (PREFIX_0F2E) },
1967   { PREFIX_TABLE (PREFIX_0F2F) },
1968   /* 30 */
1969   { "wrmsr",            { XX } },
1970   { "rdtsc",            { XX } },
1971   { "rdmsr",            { XX } },
1972   { "rdpmc",            { XX } },
1973   { "sysenter",         { XX } },
1974   { "sysexit",          { XX } },
1975   { Bad_Opcode },
1976   { "getsec",           { XX } },
1977   /* 38 */
1978   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1979   { Bad_Opcode },
1980   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1981   { Bad_Opcode },
1982   { Bad_Opcode },
1983   { Bad_Opcode },
1984   { Bad_Opcode },
1985   { Bad_Opcode },
1986   /* 40 */
1987   { "cmovoS",           { Gv, Ev } },
1988   { "cmovnoS",          { Gv, Ev } },
1989   { "cmovbS",           { Gv, Ev } },
1990   { "cmovaeS",          { Gv, Ev } },
1991   { "cmoveS",           { Gv, Ev } },
1992   { "cmovneS",          { Gv, Ev } },
1993   { "cmovbeS",          { Gv, Ev } },
1994   { "cmovaS",           { Gv, Ev } },
1995   /* 48 */
1996   { "cmovsS",           { Gv, Ev } },
1997   { "cmovnsS",          { Gv, Ev } },
1998   { "cmovpS",           { Gv, Ev } },
1999   { "cmovnpS",          { Gv, Ev } },
2000   { "cmovlS",           { Gv, Ev } },
2001   { "cmovgeS",          { Gv, Ev } },
2002   { "cmovleS",          { Gv, Ev } },
2003   { "cmovgS",           { Gv, Ev } },
2004   /* 50 */
2005   { MOD_TABLE (MOD_0F51) },
2006   { PREFIX_TABLE (PREFIX_0F51) },
2007   { PREFIX_TABLE (PREFIX_0F52) },
2008   { PREFIX_TABLE (PREFIX_0F53) },
2009   { "andpX",            { XM, EXx } },
2010   { "andnpX",           { XM, EXx } },
2011   { "orpX",             { XM, EXx } },
2012   { "xorpX",            { XM, EXx } },
2013   /* 58 */
2014   { PREFIX_TABLE (PREFIX_0F58) },
2015   { PREFIX_TABLE (PREFIX_0F59) },
2016   { PREFIX_TABLE (PREFIX_0F5A) },
2017   { PREFIX_TABLE (PREFIX_0F5B) },
2018   { PREFIX_TABLE (PREFIX_0F5C) },
2019   { PREFIX_TABLE (PREFIX_0F5D) },
2020   { PREFIX_TABLE (PREFIX_0F5E) },
2021   { PREFIX_TABLE (PREFIX_0F5F) },
2022   /* 60 */
2023   { PREFIX_TABLE (PREFIX_0F60) },
2024   { PREFIX_TABLE (PREFIX_0F61) },
2025   { PREFIX_TABLE (PREFIX_0F62) },
2026   { "packsswb",         { MX, EM } },
2027   { "pcmpgtb",          { MX, EM } },
2028   { "pcmpgtw",          { MX, EM } },
2029   { "pcmpgtd",          { MX, EM } },
2030   { "packuswb",         { MX, EM } },
2031   /* 68 */
2032   { "punpckhbw",        { MX, EM } },
2033   { "punpckhwd",        { MX, EM } },
2034   { "punpckhdq",        { MX, EM } },
2035   { "packssdw",         { MX, EM } },
2036   { PREFIX_TABLE (PREFIX_0F6C) },
2037   { PREFIX_TABLE (PREFIX_0F6D) },
2038   { "movK",             { MX, Edq } },
2039   { PREFIX_TABLE (PREFIX_0F6F) },
2040   /* 70 */
2041   { PREFIX_TABLE (PREFIX_0F70) },
2042   { REG_TABLE (REG_0F71) },
2043   { REG_TABLE (REG_0F72) },
2044   { REG_TABLE (REG_0F73) },
2045   { "pcmpeqb",          { MX, EM } },
2046   { "pcmpeqw",          { MX, EM } },
2047   { "pcmpeqd",          { MX, EM } },
2048   { "emms",             { XX } },
2049   /* 78 */
2050   { PREFIX_TABLE (PREFIX_0F78) },
2051   { PREFIX_TABLE (PREFIX_0F79) },
2052   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2053   { Bad_Opcode },
2054   { PREFIX_TABLE (PREFIX_0F7C) },
2055   { PREFIX_TABLE (PREFIX_0F7D) },
2056   { PREFIX_TABLE (PREFIX_0F7E) },
2057   { PREFIX_TABLE (PREFIX_0F7F) },
2058   /* 80 */
2059   { "joH",              { Jv, XX, cond_jump_flag } },
2060   { "jnoH",             { Jv, XX, cond_jump_flag } },
2061   { "jbH",              { Jv, XX, cond_jump_flag } },
2062   { "jaeH",             { Jv, XX, cond_jump_flag } },
2063   { "jeH",              { Jv, XX, cond_jump_flag } },
2064   { "jneH",             { Jv, XX, cond_jump_flag } },
2065   { "jbeH",             { Jv, XX, cond_jump_flag } },
2066   { "jaH",              { Jv, XX, cond_jump_flag } },
2067   /* 88 */
2068   { "jsH",              { Jv, XX, cond_jump_flag } },
2069   { "jnsH",             { Jv, XX, cond_jump_flag } },
2070   { "jpH",              { Jv, XX, cond_jump_flag } },
2071   { "jnpH",             { Jv, XX, cond_jump_flag } },
2072   { "jlH",              { Jv, XX, cond_jump_flag } },
2073   { "jgeH",             { Jv, XX, cond_jump_flag } },
2074   { "jleH",             { Jv, XX, cond_jump_flag } },
2075   { "jgH",              { Jv, XX, cond_jump_flag } },
2076   /* 90 */
2077   { "seto",             { Eb } },
2078   { "setno",            { Eb } },
2079   { "setb",             { Eb } },
2080   { "setae",            { Eb } },
2081   { "sete",             { Eb } },
2082   { "setne",            { Eb } },
2083   { "setbe",            { Eb } },
2084   { "seta",             { Eb } },
2085   /* 98 */
2086   { "sets",             { Eb } },
2087   { "setns",            { Eb } },
2088   { "setp",             { Eb } },
2089   { "setnp",            { Eb } },
2090   { "setl",             { Eb } },
2091   { "setge",            { Eb } },
2092   { "setle",            { Eb } },
2093   { "setg",             { Eb } },
2094   /* a0 */
2095   { "pushT",            { fs } },
2096   { "popT",             { fs } },
2097   { "cpuid",            { XX } },
2098   { "btS",              { Ev, Gv } },
2099   { "shldS",            { Ev, Gv, Ib } },
2100   { "shldS",            { Ev, Gv, CL } },
2101   { REG_TABLE (REG_0FA6) },
2102   { REG_TABLE (REG_0FA7) },
2103   /* a8 */
2104   { "pushT",            { gs } },
2105   { "popT",             { gs } },
2106   { "rsm",              { XX } },
2107   { "btsS",             { Ev, Gv } },
2108   { "shrdS",            { Ev, Gv, Ib } },
2109   { "shrdS",            { Ev, Gv, CL } },
2110   { REG_TABLE (REG_0FAE) },
2111   { "imulS",            { Gv, Ev } },
2112   /* b0 */
2113   { "cmpxchgB",         { Eb, Gb } },
2114   { "cmpxchgS",         { Ev, Gv } },
2115   { MOD_TABLE (MOD_0FB2) },
2116   { "btrS",             { Ev, Gv } },
2117   { MOD_TABLE (MOD_0FB4) },
2118   { MOD_TABLE (MOD_0FB5) },
2119   { "movz{bR|x}",       { Gv, Eb } },
2120   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2121   /* b8 */
2122   { PREFIX_TABLE (PREFIX_0FB8) },
2123   { "ud2b",             { XX } },
2124   { REG_TABLE (REG_0FBA) },
2125   { "btcS",             { Ev, Gv } },
2126   { "bsfS",             { Gv, Ev } },
2127   { PREFIX_TABLE (PREFIX_0FBD) },
2128   { "movs{bR|x}",       { Gv, Eb } },
2129   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2130   /* c0 */
2131   { "xaddB",            { Eb, Gb } },
2132   { "xaddS",            { Ev, Gv } },
2133   { PREFIX_TABLE (PREFIX_0FC2) },
2134   { PREFIX_TABLE (PREFIX_0FC3) },
2135   { "pinsrw",           { MX, Edqw, Ib } },
2136   { "pextrw",           { Gdq, MS, Ib } },
2137   { "shufpX",           { XM, EXx, Ib } },
2138   { REG_TABLE (REG_0FC7) },
2139   /* c8 */
2140   { "bswap",            { RMeAX } },
2141   { "bswap",            { RMeCX } },
2142   { "bswap",            { RMeDX } },
2143   { "bswap",            { RMeBX } },
2144   { "bswap",            { RMeSP } },
2145   { "bswap",            { RMeBP } },
2146   { "bswap",            { RMeSI } },
2147   { "bswap",            { RMeDI } },
2148   /* d0 */
2149   { PREFIX_TABLE (PREFIX_0FD0) },
2150   { "psrlw",            { MX, EM } },
2151   { "psrld",            { MX, EM } },
2152   { "psrlq",            { MX, EM } },
2153   { "paddq",            { MX, EM } },
2154   { "pmullw",           { MX, EM } },
2155   { PREFIX_TABLE (PREFIX_0FD6) },
2156   { MOD_TABLE (MOD_0FD7) },
2157   /* d8 */
2158   { "psubusb",          { MX, EM } },
2159   { "psubusw",          { MX, EM } },
2160   { "pminub",           { MX, EM } },
2161   { "pand",             { MX, EM } },
2162   { "paddusb",          { MX, EM } },
2163   { "paddusw",          { MX, EM } },
2164   { "pmaxub",           { MX, EM } },
2165   { "pandn",            { MX, EM } },
2166   /* e0 */
2167   { "pavgb",            { MX, EM } },
2168   { "psraw",            { MX, EM } },
2169   { "psrad",            { MX, EM } },
2170   { "pavgw",            { MX, EM } },
2171   { "pmulhuw",          { MX, EM } },
2172   { "pmulhw",           { MX, EM } },
2173   { PREFIX_TABLE (PREFIX_0FE6) },
2174   { PREFIX_TABLE (PREFIX_0FE7) },
2175   /* e8 */
2176   { "psubsb",           { MX, EM } },
2177   { "psubsw",           { MX, EM } },
2178   { "pminsw",           { MX, EM } },
2179   { "por",              { MX, EM } },
2180   { "paddsb",           { MX, EM } },
2181   { "paddsw",           { MX, EM } },
2182   { "pmaxsw",           { MX, EM } },
2183   { "pxor",             { MX, EM } },
2184   /* f0 */
2185   { PREFIX_TABLE (PREFIX_0FF0) },
2186   { "psllw",            { MX, EM } },
2187   { "pslld",            { MX, EM } },
2188   { "psllq",            { MX, EM } },
2189   { "pmuludq",          { MX, EM } },
2190   { "pmaddwd",          { MX, EM } },
2191   { "psadbw",           { MX, EM } },
2192   { PREFIX_TABLE (PREFIX_0FF7) },
2193   /* f8 */
2194   { "psubb",            { MX, EM } },
2195   { "psubw",            { MX, EM } },
2196   { "psubd",            { MX, EM } },
2197   { "psubq",            { MX, EM } },
2198   { "paddb",            { MX, EM } },
2199   { "paddw",            { MX, EM } },
2200   { "paddd",            { MX, EM } },
2201   { Bad_Opcode },
2202 };
2203
2204 static const unsigned char onebyte_has_modrm[256] = {
2205   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2206   /*       -------------------------------        */
2207   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2208   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2209   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2210   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2211   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2212   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2213   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2214   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2215   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2216   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2217   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2218   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2219   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2220   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2221   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2222   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2223   /*       -------------------------------        */
2224   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2225 };
2226
2227 static const unsigned char twobyte_has_modrm[256] = {
2228   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2229   /*       -------------------------------        */
2230   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2231   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2232   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2233   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2234   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2235   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2236   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2237   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2238   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2239   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2240   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2241   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2242   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2243   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2244   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2245   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2246   /*       -------------------------------        */
2247   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2248 };
2249
2250 static char obuf[100];
2251 static char *obufp;
2252 static char *mnemonicendp;
2253 static char scratchbuf[100];
2254 static unsigned char *start_codep;
2255 static unsigned char *insn_codep;
2256 static unsigned char *codep;
2257 static int last_lock_prefix;
2258 static int last_repz_prefix;
2259 static int last_repnz_prefix;
2260 static int last_data_prefix;
2261 static int last_addr_prefix;
2262 static int last_rex_prefix;
2263 static int last_seg_prefix;
2264 #define MAX_CODE_LENGTH 15
2265 /* We can up to 14 prefixes since the maximum instruction length is
2266    15bytes.  */
2267 static int all_prefixes[MAX_CODE_LENGTH - 1];
2268 static disassemble_info *the_info;
2269 static struct
2270   {
2271     int mod;
2272     int reg;
2273     int rm;
2274   }
2275 modrm;
2276 static unsigned char need_modrm;
2277 static struct
2278   {
2279     int register_specifier;
2280     int length;
2281     int prefix;
2282     int w;
2283   }
2284 vex;
2285 static unsigned char need_vex;
2286 static unsigned char need_vex_reg;
2287 static unsigned char vex_w_done;
2288
2289 struct op
2290   {
2291     const char *name;
2292     unsigned int len;
2293   };
2294
2295 /* If we are accessing mod/rm/reg without need_modrm set, then the
2296    values are stale.  Hitting this abort likely indicates that you
2297    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2298 #define MODRM_CHECK  if (!need_modrm) abort ()
2299
2300 static const char **names64;
2301 static const char **names32;
2302 static const char **names16;
2303 static const char **names8;
2304 static const char **names8rex;
2305 static const char **names_seg;
2306 static const char *index64;
2307 static const char *index32;
2308 static const char **index16;
2309
2310 static const char *intel_names64[] = {
2311   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2312   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2313 };
2314 static const char *intel_names32[] = {
2315   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2316   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2317 };
2318 static const char *intel_names16[] = {
2319   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2320   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2321 };
2322 static const char *intel_names8[] = {
2323   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2324 };
2325 static const char *intel_names8rex[] = {
2326   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2327   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2328 };
2329 static const char *intel_names_seg[] = {
2330   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2331 };
2332 static const char *intel_index64 = "riz";
2333 static const char *intel_index32 = "eiz";
2334 static const char *intel_index16[] = {
2335   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2336 };
2337
2338 static const char *att_names64[] = {
2339   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2340   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2341 };
2342 static const char *att_names32[] = {
2343   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2344   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2345 };
2346 static const char *att_names16[] = {
2347   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2348   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2349 };
2350 static const char *att_names8[] = {
2351   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2352 };
2353 static const char *att_names8rex[] = {
2354   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2355   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2356 };
2357 static const char *att_names_seg[] = {
2358   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2359 };
2360 static const char *att_index64 = "%riz";
2361 static const char *att_index32 = "%eiz";
2362 static const char *att_index16[] = {
2363   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2364 };
2365
2366 static const char **names_mm;
2367 static const char *intel_names_mm[] = {
2368   "mm0", "mm1", "mm2", "mm3",
2369   "mm4", "mm5", "mm6", "mm7"
2370 };
2371 static const char *att_names_mm[] = {
2372   "%mm0", "%mm1", "%mm2", "%mm3",
2373   "%mm4", "%mm5", "%mm6", "%mm7"
2374 };
2375
2376 static const char **names_xmm;
2377 static const char *intel_names_xmm[] = {
2378   "xmm0", "xmm1", "xmm2", "xmm3",
2379   "xmm4", "xmm5", "xmm6", "xmm7",
2380   "xmm8", "xmm9", "xmm10", "xmm11",
2381   "xmm12", "xmm13", "xmm14", "xmm15"
2382 };
2383 static const char *att_names_xmm[] = {
2384   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2385   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2386   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2387   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2388 };
2389
2390 static const char **names_ymm;
2391 static const char *intel_names_ymm[] = {
2392   "ymm0", "ymm1", "ymm2", "ymm3",
2393   "ymm4", "ymm5", "ymm6", "ymm7",
2394   "ymm8", "ymm9", "ymm10", "ymm11",
2395   "ymm12", "ymm13", "ymm14", "ymm15"
2396 };
2397 static const char *att_names_ymm[] = {
2398   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2399   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2400   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2401   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2402 };
2403
2404 static const struct dis386 reg_table[][8] = {
2405   /* REG_80 */
2406   {
2407     { "addA",   { Eb, Ib } },
2408     { "orA",    { Eb, Ib } },
2409     { "adcA",   { Eb, Ib } },
2410     { "sbbA",   { Eb, Ib } },
2411     { "andA",   { Eb, Ib } },
2412     { "subA",   { Eb, Ib } },
2413     { "xorA",   { Eb, Ib } },
2414     { "cmpA",   { Eb, Ib } },
2415   },
2416   /* REG_81 */
2417   {
2418     { "addQ",   { Ev, Iv } },
2419     { "orQ",    { Ev, Iv } },
2420     { "adcQ",   { Ev, Iv } },
2421     { "sbbQ",   { Ev, Iv } },
2422     { "andQ",   { Ev, Iv } },
2423     { "subQ",   { Ev, Iv } },
2424     { "xorQ",   { Ev, Iv } },
2425     { "cmpQ",   { Ev, Iv } },
2426   },
2427   /* REG_82 */
2428   {
2429     { "addQ",   { Ev, sIb } },
2430     { "orQ",    { Ev, sIb } },
2431     { "adcQ",   { Ev, sIb } },
2432     { "sbbQ",   { Ev, sIb } },
2433     { "andQ",   { Ev, sIb } },
2434     { "subQ",   { Ev, sIb } },
2435     { "xorQ",   { Ev, sIb } },
2436     { "cmpQ",   { Ev, sIb } },
2437   },
2438   /* REG_8F */
2439   {
2440     { "popU",   { stackEv } },
2441     { XOP_8F_TABLE (XOP_09) },
2442     { Bad_Opcode },
2443     { Bad_Opcode },
2444     { Bad_Opcode },
2445     { XOP_8F_TABLE (XOP_09) },
2446   },
2447   /* REG_C0 */
2448   {
2449     { "rolA",   { Eb, Ib } },
2450     { "rorA",   { Eb, Ib } },
2451     { "rclA",   { Eb, Ib } },
2452     { "rcrA",   { Eb, Ib } },
2453     { "shlA",   { Eb, Ib } },
2454     { "shrA",   { Eb, Ib } },
2455     { Bad_Opcode },
2456     { "sarA",   { Eb, Ib } },
2457   },
2458   /* REG_C1 */
2459   {
2460     { "rolQ",   { Ev, Ib } },
2461     { "rorQ",   { Ev, Ib } },
2462     { "rclQ",   { Ev, Ib } },
2463     { "rcrQ",   { Ev, Ib } },
2464     { "shlQ",   { Ev, Ib } },
2465     { "shrQ",   { Ev, Ib } },
2466     { Bad_Opcode },
2467     { "sarQ",   { Ev, Ib } },
2468   },
2469   /* REG_C6 */
2470   {
2471     { "movA",   { Eb, Ib } },
2472   },
2473   /* REG_C7 */
2474   {
2475     { "movQ",   { Ev, Iv } },
2476   },
2477   /* REG_D0 */
2478   {
2479     { "rolA",   { Eb, I1 } },
2480     { "rorA",   { Eb, I1 } },
2481     { "rclA",   { Eb, I1 } },
2482     { "rcrA",   { Eb, I1 } },
2483     { "shlA",   { Eb, I1 } },
2484     { "shrA",   { Eb, I1 } },
2485     { Bad_Opcode },
2486     { "sarA",   { Eb, I1 } },
2487   },
2488   /* REG_D1 */
2489   {
2490     { "rolQ",   { Ev, I1 } },
2491     { "rorQ",   { Ev, I1 } },
2492     { "rclQ",   { Ev, I1 } },
2493     { "rcrQ",   { Ev, I1 } },
2494     { "shlQ",   { Ev, I1 } },
2495     { "shrQ",   { Ev, I1 } },
2496     { Bad_Opcode },
2497     { "sarQ",   { Ev, I1 } },
2498   },
2499   /* REG_D2 */
2500   {
2501     { "rolA",   { Eb, CL } },
2502     { "rorA",   { Eb, CL } },
2503     { "rclA",   { Eb, CL } },
2504     { "rcrA",   { Eb, CL } },
2505     { "shlA",   { Eb, CL } },
2506     { "shrA",   { Eb, CL } },
2507     { Bad_Opcode },
2508     { "sarA",   { Eb, CL } },
2509   },
2510   /* REG_D3 */
2511   {
2512     { "rolQ",   { Ev, CL } },
2513     { "rorQ",   { Ev, CL } },
2514     { "rclQ",   { Ev, CL } },
2515     { "rcrQ",   { Ev, CL } },
2516     { "shlQ",   { Ev, CL } },
2517     { "shrQ",   { Ev, CL } },
2518     { Bad_Opcode },
2519     { "sarQ",   { Ev, CL } },
2520   },
2521   /* REG_F6 */
2522   {
2523     { "testA",  { Eb, Ib } },
2524     { Bad_Opcode },
2525     { "notA",   { Eb } },
2526     { "negA",   { Eb } },
2527     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2528     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2529     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2530     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2531   },
2532   /* REG_F7 */
2533   {
2534     { "testQ",  { Ev, Iv } },
2535     { Bad_Opcode },
2536     { "notQ",   { Ev } },
2537     { "negQ",   { Ev } },
2538     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2539     { "imulQ",  { Ev } },
2540     { "divQ",   { Ev } },
2541     { "idivQ",  { Ev } },
2542   },
2543   /* REG_FE */
2544   {
2545     { "incA",   { Eb } },
2546     { "decA",   { Eb } },
2547   },
2548   /* REG_FF */
2549   {
2550     { "incQ",   { Ev } },
2551     { "decQ",   { Ev } },
2552     { "callT",  { indirEv } },
2553     { "JcallT", { indirEp } },
2554     { "jmpT",   { indirEv } },
2555     { "JjmpT",  { indirEp } },
2556     { "pushU",  { stackEv } },
2557     { Bad_Opcode },
2558   },
2559   /* REG_0F00 */
2560   {
2561     { "sldtD",  { Sv } },
2562     { "strD",   { Sv } },
2563     { "lldt",   { Ew } },
2564     { "ltr",    { Ew } },
2565     { "verr",   { Ew } },
2566     { "verw",   { Ew } },
2567     { Bad_Opcode },
2568     { Bad_Opcode },
2569   },
2570   /* REG_0F01 */
2571   {
2572     { MOD_TABLE (MOD_0F01_REG_0) },
2573     { MOD_TABLE (MOD_0F01_REG_1) },
2574     { MOD_TABLE (MOD_0F01_REG_2) },
2575     { MOD_TABLE (MOD_0F01_REG_3) },
2576     { "smswD",  { Sv } },
2577     { Bad_Opcode },
2578     { "lmsw",   { Ew } },
2579     { MOD_TABLE (MOD_0F01_REG_7) },
2580   },
2581   /* REG_0F0D */
2582   {
2583     { "prefetch",       { Eb } },
2584     { "prefetchw",      { Eb } },
2585   },
2586   /* REG_0F18 */
2587   {
2588     { MOD_TABLE (MOD_0F18_REG_0) },
2589     { MOD_TABLE (MOD_0F18_REG_1) },
2590     { MOD_TABLE (MOD_0F18_REG_2) },
2591     { MOD_TABLE (MOD_0F18_REG_3) },
2592   },
2593   /* REG_0F71 */
2594   {
2595     { Bad_Opcode },
2596     { Bad_Opcode },
2597     { MOD_TABLE (MOD_0F71_REG_2) },
2598     { Bad_Opcode },
2599     { MOD_TABLE (MOD_0F71_REG_4) },
2600     { Bad_Opcode },
2601     { MOD_TABLE (MOD_0F71_REG_6) },
2602   },
2603   /* REG_0F72 */
2604   {
2605     { Bad_Opcode },
2606     { Bad_Opcode },
2607     { MOD_TABLE (MOD_0F72_REG_2) },
2608     { Bad_Opcode },
2609     { MOD_TABLE (MOD_0F72_REG_4) },
2610     { Bad_Opcode },
2611     { MOD_TABLE (MOD_0F72_REG_6) },
2612   },
2613   /* REG_0F73 */
2614   {
2615     { Bad_Opcode },
2616     { Bad_Opcode },
2617     { MOD_TABLE (MOD_0F73_REG_2) },
2618     { MOD_TABLE (MOD_0F73_REG_3) },
2619     { Bad_Opcode },
2620     { Bad_Opcode },
2621     { MOD_TABLE (MOD_0F73_REG_6) },
2622     { MOD_TABLE (MOD_0F73_REG_7) },
2623   },
2624   /* REG_0FA6 */
2625   {
2626     { "montmul",        { { OP_0f07, 0 } } },
2627     { "xsha1",          { { OP_0f07, 0 } } },
2628     { "xsha256",        { { OP_0f07, 0 } } },
2629   },
2630   /* REG_0FA7 */
2631   {
2632     { "xstore-rng",     { { OP_0f07, 0 } } },
2633     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2634     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2635     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2636     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2637     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2638   },
2639   /* REG_0FAE */
2640   {
2641     { MOD_TABLE (MOD_0FAE_REG_0) },
2642     { MOD_TABLE (MOD_0FAE_REG_1) },
2643     { MOD_TABLE (MOD_0FAE_REG_2) },
2644     { MOD_TABLE (MOD_0FAE_REG_3) },
2645     { MOD_TABLE (MOD_0FAE_REG_4) },
2646     { MOD_TABLE (MOD_0FAE_REG_5) },
2647     { MOD_TABLE (MOD_0FAE_REG_6) },
2648     { MOD_TABLE (MOD_0FAE_REG_7) },
2649   },
2650   /* REG_0FBA */
2651   {
2652     { Bad_Opcode },
2653     { Bad_Opcode },
2654     { Bad_Opcode },
2655     { Bad_Opcode },
2656     { "btQ",    { Ev, Ib } },
2657     { "btsQ",   { Ev, Ib } },
2658     { "btrQ",   { Ev, Ib } },
2659     { "btcQ",   { Ev, Ib } },
2660   },
2661   /* REG_0FC7 */
2662   {
2663     { Bad_Opcode },
2664     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2665     { Bad_Opcode },
2666     { Bad_Opcode },
2667     { Bad_Opcode },
2668     { Bad_Opcode },
2669     { MOD_TABLE (MOD_0FC7_REG_6) },
2670     { MOD_TABLE (MOD_0FC7_REG_7) },
2671   },
2672   /* REG_VEX_71 */
2673   {
2674     { Bad_Opcode },
2675     { Bad_Opcode },
2676     { MOD_TABLE (MOD_VEX_71_REG_2) },
2677     { Bad_Opcode },
2678     { MOD_TABLE (MOD_VEX_71_REG_4) },
2679     { Bad_Opcode },
2680     { MOD_TABLE (MOD_VEX_71_REG_6) },
2681   },
2682   /* REG_VEX_72 */
2683   {
2684     { Bad_Opcode },
2685     { Bad_Opcode },
2686     { MOD_TABLE (MOD_VEX_72_REG_2) },
2687     { Bad_Opcode },
2688     { MOD_TABLE (MOD_VEX_72_REG_4) },
2689     { Bad_Opcode },
2690     { MOD_TABLE (MOD_VEX_72_REG_6) },
2691   },
2692   /* REG_VEX_73 */
2693   {
2694     { Bad_Opcode },
2695     { Bad_Opcode },
2696     { MOD_TABLE (MOD_VEX_73_REG_2) },
2697     { MOD_TABLE (MOD_VEX_73_REG_3) },
2698     { Bad_Opcode },
2699     { Bad_Opcode },
2700     { MOD_TABLE (MOD_VEX_73_REG_6) },
2701     { MOD_TABLE (MOD_VEX_73_REG_7) },
2702   },
2703   /* REG_VEX_AE */
2704   {
2705     { Bad_Opcode },
2706     { Bad_Opcode },
2707     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2708     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2709   },
2710   /* REG_XOP_LWPCB */
2711   {
2712     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2713     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2714   },
2715   /* REG_XOP_LWP */
2716   {
2717     { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2718     { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2719   },
2720 };
2721
2722 static const struct dis386 prefix_table[][4] = {
2723   /* PREFIX_90 */
2724   {
2725     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2726     { "pause", { XX } },
2727     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2728   },
2729
2730   /* PREFIX_0F10 */
2731   {
2732     { "movups", { XM, EXx } },
2733     { "movss",  { XM, EXd } },
2734     { "movupd", { XM, EXx } },
2735     { "movsd",  { XM, EXq } },
2736   },
2737
2738   /* PREFIX_0F11 */
2739   {
2740     { "movups", { EXxS, XM } },
2741     { "movss",  { EXdS, XM } },
2742     { "movupd", { EXxS, XM } },
2743     { "movsd",  { EXqS, XM } },
2744   },
2745
2746   /* PREFIX_0F12 */
2747   {
2748     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2749     { "movsldup", { XM, EXx } },
2750     { "movlpd", { XM, EXq } },
2751     { "movddup", { XM, EXq } },
2752   },
2753
2754   /* PREFIX_0F16 */
2755   {
2756     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2757     { "movshdup", { XM, EXx } },
2758     { "movhpd", { XM, EXq } },
2759   },
2760
2761   /* PREFIX_0F2A */
2762   {
2763     { "cvtpi2ps", { XM, EMCq } },
2764     { "cvtsi2ss%LQ", { XM, Ev } },
2765     { "cvtpi2pd", { XM, EMCq } },
2766     { "cvtsi2sd%LQ", { XM, Ev } },
2767   },
2768
2769   /* PREFIX_0F2B */
2770   {
2771     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2772     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2773     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2774     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2775   },
2776
2777   /* PREFIX_0F2C */
2778   {
2779     { "cvttps2pi", { MXC, EXq } },
2780     { "cvttss2siY", { Gv, EXd } },
2781     { "cvttpd2pi", { MXC, EXx } },
2782     { "cvttsd2siY", { Gv, EXq } },
2783   },
2784
2785   /* PREFIX_0F2D */
2786   {
2787     { "cvtps2pi", { MXC, EXq } },
2788     { "cvtss2siY", { Gv, EXd } },
2789     { "cvtpd2pi", { MXC, EXx } },
2790     { "cvtsd2siY", { Gv, EXq } },
2791   },
2792
2793   /* PREFIX_0F2E */
2794   {
2795     { "ucomiss",{ XM, EXd } },
2796     { Bad_Opcode },
2797     { "ucomisd",{ XM, EXq } },
2798   },
2799
2800   /* PREFIX_0F2F */
2801   {
2802     { "comiss", { XM, EXd } },
2803     { Bad_Opcode },
2804     { "comisd", { XM, EXq } },
2805   },
2806
2807   /* PREFIX_0F51 */
2808   {
2809     { "sqrtps", { XM, EXx } },
2810     { "sqrtss", { XM, EXd } },
2811     { "sqrtpd", { XM, EXx } },
2812     { "sqrtsd", { XM, EXq } },
2813   },
2814
2815   /* PREFIX_0F52 */
2816   {
2817     { "rsqrtps",{ XM, EXx } },
2818     { "rsqrtss",{ XM, EXd } },
2819   },
2820
2821   /* PREFIX_0F53 */
2822   {
2823     { "rcpps",  { XM, EXx } },
2824     { "rcpss",  { XM, EXd } },
2825   },
2826
2827   /* PREFIX_0F58 */
2828   {
2829     { "addps", { XM, EXx } },
2830     { "addss", { XM, EXd } },
2831     { "addpd", { XM, EXx } },
2832     { "addsd", { XM, EXq } },
2833   },
2834
2835   /* PREFIX_0F59 */
2836   {
2837     { "mulps",  { XM, EXx } },
2838     { "mulss",  { XM, EXd } },
2839     { "mulpd",  { XM, EXx } },
2840     { "mulsd",  { XM, EXq } },
2841   },
2842
2843   /* PREFIX_0F5A */
2844   {
2845     { "cvtps2pd", { XM, EXq } },
2846     { "cvtss2sd", { XM, EXd } },
2847     { "cvtpd2ps", { XM, EXx } },
2848     { "cvtsd2ss", { XM, EXq } },
2849   },
2850
2851   /* PREFIX_0F5B */
2852   {
2853     { "cvtdq2ps", { XM, EXx } },
2854     { "cvttps2dq", { XM, EXx } },
2855     { "cvtps2dq", { XM, EXx } },
2856   },
2857
2858   /* PREFIX_0F5C */
2859   {
2860     { "subps",  { XM, EXx } },
2861     { "subss",  { XM, EXd } },
2862     { "subpd",  { XM, EXx } },
2863     { "subsd",  { XM, EXq } },
2864   },
2865
2866   /* PREFIX_0F5D */
2867   {
2868     { "minps",  { XM, EXx } },
2869     { "minss",  { XM, EXd } },
2870     { "minpd",  { XM, EXx } },
2871     { "minsd",  { XM, EXq } },
2872   },
2873
2874   /* PREFIX_0F5E */
2875   {
2876     { "divps",  { XM, EXx } },
2877     { "divss",  { XM, EXd } },
2878     { "divpd",  { XM, EXx } },
2879     { "divsd",  { XM, EXq } },
2880   },
2881
2882   /* PREFIX_0F5F */
2883   {
2884     { "maxps",  { XM, EXx } },
2885     { "maxss",  { XM, EXd } },
2886     { "maxpd",  { XM, EXx } },
2887     { "maxsd",  { XM, EXq } },
2888   },
2889
2890   /* PREFIX_0F60 */
2891   {
2892     { "punpcklbw",{ MX, EMd } },
2893     { Bad_Opcode },
2894     { "punpcklbw",{ MX, EMx } },
2895   },
2896
2897   /* PREFIX_0F61 */
2898   {
2899     { "punpcklwd",{ MX, EMd } },
2900     { Bad_Opcode },
2901     { "punpcklwd",{ MX, EMx } },
2902   },
2903
2904   /* PREFIX_0F62 */
2905   {
2906     { "punpckldq",{ MX, EMd } },
2907     { Bad_Opcode },
2908     { "punpckldq",{ MX, EMx } },
2909   },
2910
2911   /* PREFIX_0F6C */
2912   {
2913     { Bad_Opcode },
2914     { Bad_Opcode },
2915     { "punpcklqdq", { XM, EXx } },
2916   },
2917
2918   /* PREFIX_0F6D */
2919   {
2920     { Bad_Opcode },
2921     { Bad_Opcode },
2922     { "punpckhqdq", { XM, EXx } },
2923   },
2924
2925   /* PREFIX_0F6F */
2926   {
2927     { "movq",   { MX, EM } },
2928     { "movdqu", { XM, EXx } },
2929     { "movdqa", { XM, EXx } },
2930   },
2931
2932   /* PREFIX_0F70 */
2933   {
2934     { "pshufw", { MX, EM, Ib } },
2935     { "pshufhw",{ XM, EXx, Ib } },
2936     { "pshufd", { XM, EXx, Ib } },
2937     { "pshuflw",{ XM, EXx, Ib } },
2938   },
2939
2940   /* PREFIX_0F73_REG_3 */
2941   {
2942     { Bad_Opcode },
2943     { Bad_Opcode },
2944     { "psrldq", { XS, Ib } },
2945   },
2946
2947   /* PREFIX_0F73_REG_7 */
2948   {
2949     { Bad_Opcode },
2950     { Bad_Opcode },
2951     { "pslldq", { XS, Ib } },
2952   },
2953
2954   /* PREFIX_0F78 */
2955   {
2956     {"vmread",  { Em, Gm } },
2957     { Bad_Opcode },
2958     {"extrq",   { XS, Ib, Ib } },
2959     {"insertq", { XM, XS, Ib, Ib } },
2960   },
2961
2962   /* PREFIX_0F79 */
2963   {
2964     {"vmwrite", { Gm, Em } },
2965     { Bad_Opcode },
2966     {"extrq",   { XM, XS } },
2967     {"insertq", { XM, XS } },
2968   },
2969
2970   /* PREFIX_0F7C */
2971   {
2972     { Bad_Opcode },
2973     { Bad_Opcode },
2974     { "haddpd", { XM, EXx } },
2975     { "haddps", { XM, EXx } },
2976   },
2977
2978   /* PREFIX_0F7D */
2979   {
2980     { Bad_Opcode },
2981     { Bad_Opcode },
2982     { "hsubpd", { XM, EXx } },
2983     { "hsubps", { XM, EXx } },
2984   },
2985
2986   /* PREFIX_0F7E */
2987   {
2988     { "movK",   { Edq, MX } },
2989     { "movq",   { XM, EXq } },
2990     { "movK",   { Edq, XM } },
2991   },
2992
2993   /* PREFIX_0F7F */
2994   {
2995     { "movq",   { EMS, MX } },
2996     { "movdqu", { EXxS, XM } },
2997     { "movdqa", { EXxS, XM } },
2998   },
2999
3000   /* PREFIX_0FB8 */
3001   {
3002     { Bad_Opcode },
3003     { "popcntS", { Gv, Ev } },
3004   },
3005
3006   /* PREFIX_0FBD */
3007   {
3008     { "bsrS",   { Gv, Ev } },
3009     { "lzcntS", { Gv, Ev } },
3010     { "bsrS",   { Gv, Ev } },
3011   },
3012
3013   /* PREFIX_0FC2 */
3014   {
3015     { "cmpps",  { XM, EXx, CMP } },
3016     { "cmpss",  { XM, EXd, CMP } },
3017     { "cmppd",  { XM, EXx, CMP } },
3018     { "cmpsd",  { XM, EXq, CMP } },
3019   },
3020
3021   /* PREFIX_0FC3 */
3022   {
3023     { "movntiS", { Ma, Gv } },
3024   },
3025
3026   /* PREFIX_0FC7_REG_6 */
3027   {
3028     { "vmptrld",{ Mq } },
3029     { "vmxon",  { Mq } },
3030     { "vmclear",{ Mq } },
3031   },
3032
3033   /* PREFIX_0FD0 */
3034   {
3035     { Bad_Opcode },
3036     { Bad_Opcode },
3037     { "addsubpd", { XM, EXx } },
3038     { "addsubps", { XM, EXx } },
3039   },
3040
3041   /* PREFIX_0FD6 */
3042   {
3043     { Bad_Opcode },
3044     { "movq2dq",{ XM, MS } },
3045     { "movq",   { EXqS, XM } },
3046     { "movdq2q",{ MX, XS } },
3047   },
3048
3049   /* PREFIX_0FE6 */
3050   {
3051     { Bad_Opcode },
3052     { "cvtdq2pd", { XM, EXq } },
3053     { "cvttpd2dq", { XM, EXx } },
3054     { "cvtpd2dq", { XM, EXx } },
3055   },
3056
3057   /* PREFIX_0FE7 */
3058   {
3059     { "movntq", { Mq, MX } },
3060     { Bad_Opcode },
3061     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3062   },
3063
3064   /* PREFIX_0FF0 */
3065   {
3066     { Bad_Opcode },
3067     { Bad_Opcode },
3068     { Bad_Opcode },
3069     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3070   },
3071
3072   /* PREFIX_0FF7 */
3073   {
3074     { "maskmovq", { MX, MS } },
3075     { Bad_Opcode },
3076     { "maskmovdqu", { XM, XS } },
3077   },
3078
3079   /* PREFIX_0F3810 */
3080   {
3081     { Bad_Opcode },
3082     { Bad_Opcode },
3083     { "pblendvb", { XM, EXx, XMM0 } },
3084   },
3085
3086   /* PREFIX_0F3814 */
3087   {
3088     { Bad_Opcode },
3089     { Bad_Opcode },
3090     { "blendvps", { XM, EXx, XMM0 } },
3091   },
3092
3093   /* PREFIX_0F3815 */
3094   {
3095     { Bad_Opcode },
3096     { Bad_Opcode },
3097     { "blendvpd", { XM, EXx, XMM0 } },
3098   },
3099
3100   /* PREFIX_0F3817 */
3101   {
3102     { Bad_Opcode },
3103     { Bad_Opcode },
3104     { "ptest",  { XM, EXx } },
3105   },
3106
3107   /* PREFIX_0F3820 */
3108   {
3109     { Bad_Opcode },
3110     { Bad_Opcode },
3111     { "pmovsxbw", { XM, EXq } },
3112   },
3113
3114   /* PREFIX_0F3821 */
3115   {
3116     { Bad_Opcode },
3117     { Bad_Opcode },
3118     { "pmovsxbd", { XM, EXd } },
3119   },
3120
3121   /* PREFIX_0F3822 */
3122   {
3123     { Bad_Opcode },
3124     { Bad_Opcode },
3125     { "pmovsxbq", { XM, EXw } },
3126   },
3127
3128   /* PREFIX_0F3823 */
3129   {
3130     { Bad_Opcode },
3131     { Bad_Opcode },
3132     { "pmovsxwd", { XM, EXq } },
3133   },
3134
3135   /* PREFIX_0F3824 */
3136   {
3137     { Bad_Opcode },
3138     { Bad_Opcode },
3139     { "pmovsxwq", { XM, EXd } },
3140   },
3141
3142   /* PREFIX_0F3825 */
3143   {
3144     { Bad_Opcode },
3145     { Bad_Opcode },
3146     { "pmovsxdq", { XM, EXq } },
3147   },
3148
3149   /* PREFIX_0F3828 */
3150   {
3151     { Bad_Opcode },
3152     { Bad_Opcode },
3153     { "pmuldq", { XM, EXx } },
3154   },
3155
3156   /* PREFIX_0F3829 */
3157   {
3158     { Bad_Opcode },
3159     { Bad_Opcode },
3160     { "pcmpeqq", { XM, EXx } },
3161   },
3162
3163   /* PREFIX_0F382A */
3164   {
3165     { Bad_Opcode },
3166     { Bad_Opcode },
3167     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3168   },
3169
3170   /* PREFIX_0F382B */
3171   {
3172     { Bad_Opcode },
3173     { Bad_Opcode },
3174     { "packusdw", { XM, EXx } },
3175   },
3176
3177   /* PREFIX_0F3830 */
3178   {
3179     { Bad_Opcode },
3180     { Bad_Opcode },
3181     { "pmovzxbw", { XM, EXq } },
3182   },
3183
3184   /* PREFIX_0F3831 */
3185   {
3186     { Bad_Opcode },
3187     { Bad_Opcode },
3188     { "pmovzxbd", { XM, EXd } },
3189   },
3190
3191   /* PREFIX_0F3832 */
3192   {
3193     { Bad_Opcode },
3194     { Bad_Opcode },
3195     { "pmovzxbq", { XM, EXw } },
3196   },
3197
3198   /* PREFIX_0F3833 */
3199   {
3200     { Bad_Opcode },
3201     { Bad_Opcode },
3202     { "pmovzxwd", { XM, EXq } },
3203   },
3204
3205   /* PREFIX_0F3834 */
3206   {
3207     { Bad_Opcode },
3208     { Bad_Opcode },
3209     { "pmovzxwq", { XM, EXd } },
3210   },
3211
3212   /* PREFIX_0F3835 */
3213   {
3214     { Bad_Opcode },
3215     { Bad_Opcode },
3216     { "pmovzxdq", { XM, EXq } },
3217   },
3218
3219   /* PREFIX_0F3837 */
3220   {
3221     { Bad_Opcode },
3222     { Bad_Opcode },
3223     { "pcmpgtq", { XM, EXx } },
3224   },
3225
3226   /* PREFIX_0F3838 */
3227   {
3228     { Bad_Opcode },
3229     { Bad_Opcode },
3230     { "pminsb", { XM, EXx } },
3231   },
3232
3233   /* PREFIX_0F3839 */
3234   {
3235     { Bad_Opcode },
3236     { Bad_Opcode },
3237     { "pminsd", { XM, EXx } },
3238   },
3239
3240   /* PREFIX_0F383A */
3241   {
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { "pminuw", { XM, EXx } },
3245   },
3246
3247   /* PREFIX_0F383B */
3248   {
3249     { Bad_Opcode },
3250     { Bad_Opcode },
3251     { "pminud", { XM, EXx } },
3252   },
3253
3254   /* PREFIX_0F383C */
3255   {
3256     { Bad_Opcode },
3257     { Bad_Opcode },
3258     { "pmaxsb", { XM, EXx } },
3259   },
3260
3261   /* PREFIX_0F383D */
3262   {
3263     { Bad_Opcode },
3264     { Bad_Opcode },
3265     { "pmaxsd", { XM, EXx } },
3266   },
3267
3268   /* PREFIX_0F383E */
3269   {
3270     { Bad_Opcode },
3271     { Bad_Opcode },
3272     { "pmaxuw", { XM, EXx } },
3273   },
3274
3275   /* PREFIX_0F383F */
3276   {
3277     { Bad_Opcode },
3278     { Bad_Opcode },
3279     { "pmaxud", { XM, EXx } },
3280   },
3281
3282   /* PREFIX_0F3840 */
3283   {
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { "pmulld", { XM, EXx } },
3287   },
3288
3289   /* PREFIX_0F3841 */
3290   {
3291     { Bad_Opcode },
3292     { Bad_Opcode },
3293     { "phminposuw", { XM, EXx } },
3294   },
3295
3296   /* PREFIX_0F3880 */
3297   {
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { "invept", { Gm, Mo } },
3301   },
3302
3303   /* PREFIX_0F3881 */
3304   {
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { "invvpid", { Gm, Mo } },
3308   },
3309
3310   /* PREFIX_0F38DB */
3311   {
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { "aesimc", { XM, EXx } },
3315   },
3316
3317   /* PREFIX_0F38DC */
3318   {
3319     { Bad_Opcode },
3320     { Bad_Opcode },
3321     { "aesenc", { XM, EXx } },
3322   },
3323
3324   /* PREFIX_0F38DD */
3325   {
3326     { Bad_Opcode },
3327     { Bad_Opcode },
3328     { "aesenclast", { XM, EXx } },
3329   },
3330
3331   /* PREFIX_0F38DE */
3332   {
3333     { Bad_Opcode },
3334     { Bad_Opcode },
3335     { "aesdec", { XM, EXx } },
3336   },
3337
3338   /* PREFIX_0F38DF */
3339   {
3340     { Bad_Opcode },
3341     { Bad_Opcode },
3342     { "aesdeclast", { XM, EXx } },
3343   },
3344
3345   /* PREFIX_0F38F0 */
3346   {
3347     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3348     { Bad_Opcode },
3349     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3350     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3351   },
3352
3353   /* PREFIX_0F38F1 */
3354   {
3355     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3356     { Bad_Opcode },
3357     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3358     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3359   },
3360
3361   /* PREFIX_0F3A08 */
3362   {
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { "roundps", { XM, EXx, Ib } },
3366   },
3367
3368   /* PREFIX_0F3A09 */
3369   {
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { "roundpd", { XM, EXx, Ib } },
3373   },
3374
3375   /* PREFIX_0F3A0A */
3376   {
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { "roundss", { XM, EXd, Ib } },
3380   },
3381
3382   /* PREFIX_0F3A0B */
3383   {
3384     { Bad_Opcode },
3385     { Bad_Opcode },
3386     { "roundsd", { XM, EXq, Ib } },
3387   },
3388
3389   /* PREFIX_0F3A0C */
3390   {
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393     { "blendps", { XM, EXx, Ib } },
3394   },
3395
3396   /* PREFIX_0F3A0D */
3397   {
3398     { Bad_Opcode },
3399     { Bad_Opcode },
3400     { "blendpd", { XM, EXx, Ib } },
3401   },
3402
3403   /* PREFIX_0F3A0E */
3404   {
3405     { Bad_Opcode },
3406     { Bad_Opcode },
3407     { "pblendw", { XM, EXx, Ib } },
3408   },
3409
3410   /* PREFIX_0F3A14 */
3411   {
3412     { Bad_Opcode },
3413     { Bad_Opcode },
3414     { "pextrb", { Edqb, XM, Ib } },
3415   },
3416
3417   /* PREFIX_0F3A15 */
3418   {
3419     { Bad_Opcode },
3420     { Bad_Opcode },
3421     { "pextrw", { Edqw, XM, Ib } },
3422   },
3423
3424   /* PREFIX_0F3A16 */
3425   {
3426     { Bad_Opcode },
3427     { Bad_Opcode },
3428     { "pextrK", { Edq, XM, Ib } },
3429   },
3430
3431   /* PREFIX_0F3A17 */
3432   {
3433     { Bad_Opcode },
3434     { Bad_Opcode },
3435     { "extractps", { Edqd, XM, Ib } },
3436   },
3437
3438   /* PREFIX_0F3A20 */
3439   {
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { "pinsrb", { XM, Edqb, Ib } },
3443   },
3444
3445   /* PREFIX_0F3A21 */
3446   {
3447     { Bad_Opcode },
3448     { Bad_Opcode },
3449     { "insertps", { XM, EXd, Ib } },
3450   },
3451
3452   /* PREFIX_0F3A22 */
3453   {
3454     { Bad_Opcode },
3455     { Bad_Opcode },
3456     { "pinsrK", { XM, Edq, Ib } },
3457   },
3458
3459   /* PREFIX_0F3A40 */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { "dpps",   { XM, EXx, Ib } },
3464   },
3465
3466   /* PREFIX_0F3A41 */
3467   {
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { "dppd",   { XM, EXx, Ib } },
3471   },
3472
3473   /* PREFIX_0F3A42 */
3474   {
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { "mpsadbw", { XM, EXx, Ib } },
3478   },
3479
3480   /* PREFIX_0F3A44 */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { "pclmulqdq", { XM, EXx, PCLMUL } },
3485   },
3486
3487   /* PREFIX_0F3A60 */
3488   {
3489     { Bad_Opcode },
3490     { Bad_Opcode },
3491     { "pcmpestrm", { XM, EXx, Ib } },
3492   },
3493
3494   /* PREFIX_0F3A61 */
3495   {
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { "pcmpestri", { XM, EXx, Ib } },
3499   },
3500
3501   /* PREFIX_0F3A62 */
3502   {
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { "pcmpistrm", { XM, EXx, Ib } },
3506   },
3507
3508   /* PREFIX_0F3A63 */
3509   {
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { "pcmpistri", { XM, EXx, Ib } },
3513   },
3514
3515   /* PREFIX_0F3ADF */
3516   {
3517     { Bad_Opcode },
3518     { Bad_Opcode },
3519     { "aeskeygenassist", { XM, EXx, Ib } },
3520   },
3521
3522   /* PREFIX_VEX_10 */
3523   {
3524     { VEX_W_TABLE (VEX_W_10_P_0) },
3525     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3526     { VEX_W_TABLE (VEX_W_10_P_2) },
3527     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3528   },
3529
3530   /* PREFIX_VEX_11 */
3531   {
3532     { VEX_W_TABLE (VEX_W_11_P_0) },
3533     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3534     { VEX_W_TABLE (VEX_W_11_P_2) },
3535     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3536   },
3537
3538   /* PREFIX_VEX_12 */
3539   {
3540     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3541     { VEX_W_TABLE (VEX_W_12_P_1) },
3542     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3543     { VEX_W_TABLE (VEX_W_12_P_3) },
3544   },
3545
3546   /* PREFIX_VEX_16 */
3547   {
3548     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3549     { VEX_W_TABLE (VEX_W_16_P_1) },
3550     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3551   },
3552
3553   /* PREFIX_VEX_2A */
3554   {
3555     { Bad_Opcode },
3556     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3557     { Bad_Opcode },
3558     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3559   },
3560
3561   /* PREFIX_VEX_2C */
3562   {
3563     { Bad_Opcode },
3564     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3565     { Bad_Opcode },
3566     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3567   },
3568
3569   /* PREFIX_VEX_2D */
3570   {
3571     { Bad_Opcode },
3572     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3573     { Bad_Opcode },
3574     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3575   },
3576
3577   /* PREFIX_VEX_2E */
3578   {
3579     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3580     { Bad_Opcode },
3581     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3582   },
3583
3584   /* PREFIX_VEX_2F */
3585   {
3586     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3587     { Bad_Opcode },
3588     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3589   },
3590
3591   /* PREFIX_VEX_51 */
3592   {
3593     { VEX_W_TABLE (VEX_W_51_P_0) },
3594     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3595     { VEX_W_TABLE (VEX_W_51_P_2) },
3596     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3597   },
3598
3599   /* PREFIX_VEX_52 */
3600   {
3601     { VEX_W_TABLE (VEX_W_52_P_0) },
3602     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3603   },
3604
3605   /* PREFIX_VEX_53 */
3606   {
3607     { VEX_W_TABLE (VEX_W_53_P_0) },
3608     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3609   },
3610
3611   /* PREFIX_VEX_58 */
3612   {
3613     { VEX_W_TABLE (VEX_W_58_P_0) },
3614     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3615     { VEX_W_TABLE (VEX_W_58_P_2) },
3616     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3617   },
3618
3619   /* PREFIX_VEX_59 */
3620   {
3621     { VEX_W_TABLE (VEX_W_59_P_0) },
3622     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3623     { VEX_W_TABLE (VEX_W_59_P_2) },
3624     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3625   },
3626
3627   /* PREFIX_VEX_5A */
3628   {
3629     { VEX_W_TABLE (VEX_W_5A_P_0) },
3630     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3631     { "vcvtpd2ps%XY", { XMM, EXx } },
3632     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3633   },
3634
3635   /* PREFIX_VEX_5B */
3636   {
3637     { VEX_W_TABLE (VEX_W_5B_P_0) },
3638     { VEX_W_TABLE (VEX_W_5B_P_1) },
3639     { VEX_W_TABLE (VEX_W_5B_P_2) },
3640   },
3641
3642   /* PREFIX_VEX_5C */
3643   {
3644     { VEX_W_TABLE (VEX_W_5C_P_0) },
3645     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3646     { VEX_W_TABLE (VEX_W_5C_P_2) },
3647     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3648   },
3649
3650   /* PREFIX_VEX_5D */
3651   {
3652     { VEX_W_TABLE (VEX_W_5D_P_0) },
3653     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3654     { VEX_W_TABLE (VEX_W_5D_P_2) },
3655     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3656   },
3657
3658   /* PREFIX_VEX_5E */
3659   {
3660     { VEX_W_TABLE (VEX_W_5E_P_0) },
3661     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3662     { VEX_W_TABLE (VEX_W_5E_P_2) },
3663     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3664   },
3665
3666   /* PREFIX_VEX_5F */
3667   {
3668     { VEX_W_TABLE (VEX_W_5F_P_0) },
3669     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3670     { VEX_W_TABLE (VEX_W_5F_P_2) },
3671     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3672   },
3673
3674   /* PREFIX_VEX_60 */
3675   {
3676     { Bad_Opcode },
3677     { Bad_Opcode },
3678     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3679   },
3680
3681   /* PREFIX_VEX_61 */
3682   {
3683     { Bad_Opcode },
3684     { Bad_Opcode },
3685     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3686   },
3687
3688   /* PREFIX_VEX_62 */
3689   {
3690     { Bad_Opcode },
3691     { Bad_Opcode },
3692     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3693   },
3694
3695   /* PREFIX_VEX_63 */
3696   {
3697     { Bad_Opcode },
3698     { Bad_Opcode },
3699     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3700   },
3701
3702   /* PREFIX_VEX_64 */
3703   {
3704     { Bad_Opcode },
3705     { Bad_Opcode },
3706     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3707   },
3708
3709   /* PREFIX_VEX_65 */
3710   {
3711     { Bad_Opcode },
3712     { Bad_Opcode },
3713     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3714   },
3715
3716   /* PREFIX_VEX_66 */
3717   {
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3721   },
3722
3723   /* PREFIX_VEX_67 */
3724   {
3725     { Bad_Opcode },
3726     { Bad_Opcode },
3727     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3728   },
3729
3730   /* PREFIX_VEX_68 */
3731   {
3732     { Bad_Opcode },
3733     { Bad_Opcode },
3734     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3735   },
3736
3737   /* PREFIX_VEX_69 */
3738   {
3739     { Bad_Opcode },
3740     { Bad_Opcode },
3741     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3742   },
3743
3744   /* PREFIX_VEX_6A */
3745   {
3746     { Bad_Opcode },
3747     { Bad_Opcode },
3748     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3749   },
3750
3751   /* PREFIX_VEX_6B */
3752   {
3753     { Bad_Opcode },
3754     { Bad_Opcode },
3755     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3756   },
3757
3758   /* PREFIX_VEX_6C */
3759   {
3760     { Bad_Opcode },
3761     { Bad_Opcode },
3762     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3763   },
3764
3765   /* PREFIX_VEX_6D */
3766   {
3767     { Bad_Opcode },
3768     { Bad_Opcode },
3769     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3770   },
3771
3772   /* PREFIX_VEX_6E */
3773   {
3774     { Bad_Opcode },
3775     { Bad_Opcode },
3776     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3777   },
3778
3779   /* PREFIX_VEX_6F */
3780   {
3781     { Bad_Opcode },
3782     { VEX_W_TABLE (VEX_W_6F_P_1) },
3783     { VEX_W_TABLE (VEX_W_6F_P_2) },
3784   },
3785
3786   /* PREFIX_VEX_70 */
3787   {
3788     { Bad_Opcode },
3789     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3790     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3791     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3792   },
3793
3794   /* PREFIX_VEX_71_REG_2 */
3795   {
3796     { Bad_Opcode },
3797     { Bad_Opcode },
3798     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3799   },
3800
3801   /* PREFIX_VEX_71_REG_4 */
3802   {
3803     { Bad_Opcode },
3804     { Bad_Opcode },
3805     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3806   },
3807
3808   /* PREFIX_VEX_71_REG_6 */
3809   {
3810     { Bad_Opcode },
3811     { Bad_Opcode },
3812     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3813   },
3814
3815   /* PREFIX_VEX_72_REG_2 */
3816   {
3817     { Bad_Opcode },
3818     { Bad_Opcode },
3819     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3820   },
3821
3822   /* PREFIX_VEX_72_REG_4 */
3823   {
3824     { Bad_Opcode },
3825     { Bad_Opcode },
3826     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3827   },
3828
3829   /* PREFIX_VEX_72_REG_6 */
3830   {
3831     { Bad_Opcode },
3832     { Bad_Opcode },
3833     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3834   },
3835
3836   /* PREFIX_VEX_73_REG_2 */
3837   {
3838     { Bad_Opcode },
3839     { Bad_Opcode },
3840     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3841   },
3842
3843   /* PREFIX_VEX_73_REG_3 */
3844   {
3845     { Bad_Opcode },
3846     { Bad_Opcode },
3847     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3848   },
3849
3850   /* PREFIX_VEX_73_REG_6 */
3851   {
3852     { Bad_Opcode },
3853     { Bad_Opcode },
3854     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3855   },
3856
3857   /* PREFIX_VEX_73_REG_7 */
3858   {
3859     { Bad_Opcode },
3860     { Bad_Opcode },
3861     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3862   },
3863
3864   /* PREFIX_VEX_74 */
3865   {
3866     { Bad_Opcode },
3867     { Bad_Opcode },
3868     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3869   },
3870
3871   /* PREFIX_VEX_75 */
3872   {
3873     { Bad_Opcode },
3874     { Bad_Opcode },
3875     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3876   },
3877
3878   /* PREFIX_VEX_76 */
3879   {
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3883   },
3884
3885   /* PREFIX_VEX_77 */
3886   {
3887     { VEX_W_TABLE (VEX_W_77_P_0) },
3888   },
3889
3890   /* PREFIX_VEX_7C */
3891   {
3892     { Bad_Opcode },
3893     { Bad_Opcode },
3894     { VEX_W_TABLE (VEX_W_7C_P_2) },
3895     { VEX_W_TABLE (VEX_W_7C_P_3) },
3896   },
3897
3898   /* PREFIX_VEX_7D */
3899   {
3900     { Bad_Opcode },
3901     { Bad_Opcode },
3902     { VEX_W_TABLE (VEX_W_7D_P_2) },
3903     { VEX_W_TABLE (VEX_W_7D_P_3) },
3904   },
3905
3906   /* PREFIX_VEX_7E */
3907   {
3908     { Bad_Opcode },
3909     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3910     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3911   },
3912
3913   /* PREFIX_VEX_7F */
3914   {
3915     { Bad_Opcode },
3916     { VEX_W_TABLE (VEX_W_7F_P_1) },
3917     { VEX_W_TABLE (VEX_W_7F_P_2) },
3918   },
3919
3920   /* PREFIX_VEX_C2 */
3921   {
3922     { VEX_W_TABLE (VEX_W_C2_P_0) },
3923     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3924     { VEX_W_TABLE (VEX_W_C2_P_2) },
3925     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3926   },
3927
3928   /* PREFIX_VEX_C4 */
3929   {
3930     { Bad_Opcode },
3931     { Bad_Opcode },
3932     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3933   },
3934
3935   /* PREFIX_VEX_C5 */
3936   {
3937     { Bad_Opcode },
3938     { Bad_Opcode },
3939     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3940   },
3941
3942   /* PREFIX_VEX_D0 */
3943   {
3944     { Bad_Opcode },
3945     { Bad_Opcode },
3946     { VEX_W_TABLE (VEX_W_D0_P_2) },
3947     { VEX_W_TABLE (VEX_W_D0_P_3) },
3948   },
3949
3950   /* PREFIX_VEX_D1 */
3951   {
3952     { Bad_Opcode },
3953     { Bad_Opcode },
3954     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3955   },
3956
3957   /* PREFIX_VEX_D2 */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3962   },
3963
3964   /* PREFIX_VEX_D3 */
3965   {
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3969   },
3970
3971   /* PREFIX_VEX_D4 */
3972   {
3973     { Bad_Opcode },
3974     { Bad_Opcode },
3975     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3976   },
3977
3978   /* PREFIX_VEX_D5 */
3979   {
3980     { Bad_Opcode },
3981     { Bad_Opcode },
3982     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3983   },
3984
3985   /* PREFIX_VEX_D6 */
3986   {
3987     { Bad_Opcode },
3988     { Bad_Opcode },
3989     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3990   },
3991
3992   /* PREFIX_VEX_D7 */
3993   {
3994     { Bad_Opcode },
3995     { Bad_Opcode },
3996     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3997   },
3998
3999   /* PREFIX_VEX_D8 */
4000   {
4001     { Bad_Opcode },
4002     { Bad_Opcode },
4003     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4004   },
4005
4006   /* PREFIX_VEX_D9 */
4007   {
4008     { Bad_Opcode },
4009     { Bad_Opcode },
4010     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4011   },
4012
4013   /* PREFIX_VEX_DA */
4014   {
4015     { Bad_Opcode },
4016     { Bad_Opcode },
4017     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4018   },
4019
4020   /* PREFIX_VEX_DB */
4021   {
4022     { Bad_Opcode },
4023     { Bad_Opcode },
4024     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4025   },
4026
4027   /* PREFIX_VEX_DC */
4028   {
4029     { Bad_Opcode },
4030     { Bad_Opcode },
4031     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4032   },
4033
4034   /* PREFIX_VEX_DD */
4035   {
4036     { Bad_Opcode },
4037     { Bad_Opcode },
4038     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4039   },
4040
4041   /* PREFIX_VEX_DE */
4042   {
4043     { Bad_Opcode },
4044     { Bad_Opcode },
4045     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4046   },
4047
4048   /* PREFIX_VEX_DF */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4053   },
4054
4055   /* PREFIX_VEX_E0 */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4060   },
4061
4062   /* PREFIX_VEX_E1 */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4067   },
4068
4069   /* PREFIX_VEX_E2 */
4070   {
4071     { Bad_Opcode },
4072     { Bad_Opcode },
4073     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4074   },
4075
4076   /* PREFIX_VEX_E3 */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4081   },
4082
4083   /* PREFIX_VEX_E4 */
4084   {
4085     { Bad_Opcode },
4086     { Bad_Opcode },
4087     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4088   },
4089
4090   /* PREFIX_VEX_E5 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4095   },
4096
4097   /* PREFIX_VEX_E6 */
4098   {
4099     { Bad_Opcode },
4100     { VEX_W_TABLE (VEX_W_E6_P_1) },
4101     { VEX_W_TABLE (VEX_W_E6_P_2) },
4102     { VEX_W_TABLE (VEX_W_E6_P_3) },
4103   },
4104
4105   /* PREFIX_VEX_E7 */
4106   {
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4110   },
4111
4112   /* PREFIX_VEX_E8 */
4113   {
4114     { Bad_Opcode },
4115     { Bad_Opcode },
4116     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4117   },
4118
4119   /* PREFIX_VEX_E9 */
4120   {
4121     { Bad_Opcode },
4122     { Bad_Opcode },
4123     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4124   },
4125
4126   /* PREFIX_VEX_EA */
4127   {
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4131   },
4132
4133   /* PREFIX_VEX_EB */
4134   {
4135     { Bad_Opcode },
4136     { Bad_Opcode },
4137     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4138   },
4139
4140   /* PREFIX_VEX_EC */
4141   {
4142     { Bad_Opcode },
4143     { Bad_Opcode },
4144     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4145   },
4146
4147   /* PREFIX_VEX_ED */
4148   {
4149     { Bad_Opcode },
4150     { Bad_Opcode },
4151     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4152   },
4153
4154   /* PREFIX_VEX_EE */
4155   {
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4159   },
4160
4161   /* PREFIX_VEX_EF */
4162   {
4163     { Bad_Opcode },
4164     { Bad_Opcode },
4165     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4166   },
4167
4168   /* PREFIX_VEX_F0 */
4169   {
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4174   },
4175
4176   /* PREFIX_VEX_F1 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4181   },
4182
4183   /* PREFIX_VEX_F2 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4188   },
4189
4190   /* PREFIX_VEX_F3 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4195   },
4196
4197   /* PREFIX_VEX_F4 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4202   },
4203
4204   /* PREFIX_VEX_F5 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4209   },
4210
4211   /* PREFIX_VEX_F6 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4216   },
4217
4218   /* PREFIX_VEX_F7 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4223   },
4224
4225   /* PREFIX_VEX_F8 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4230   },
4231
4232   /* PREFIX_VEX_F9 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4237   },
4238
4239   /* PREFIX_VEX_FA */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4244   },
4245
4246   /* PREFIX_VEX_FB */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4251   },
4252
4253   /* PREFIX_VEX_FC */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4258   },
4259
4260   /* PREFIX_VEX_FD */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4265   },
4266
4267   /* PREFIX_VEX_FE */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4272   },
4273
4274   /* PREFIX_VEX_3800 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4279   },
4280
4281   /* PREFIX_VEX_3801 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4286   },
4287
4288   /* PREFIX_VEX_3802 */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4293   },
4294
4295   /* PREFIX_VEX_3803 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4300   },
4301
4302   /* PREFIX_VEX_3804 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4307   },
4308
4309   /* PREFIX_VEX_3805 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4314   },
4315
4316   /* PREFIX_VEX_3806 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4321   },
4322
4323   /* PREFIX_VEX_3807 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4328   },
4329
4330   /* PREFIX_VEX_3808 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4335   },
4336
4337   /* PREFIX_VEX_3809 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4342   },
4343
4344   /* PREFIX_VEX_380A */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4349   },
4350
4351   /* PREFIX_VEX_380B */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4356   },
4357
4358   /* PREFIX_VEX_380C */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { VEX_W_TABLE (VEX_W_380C_P_2) },
4363   },
4364
4365   /* PREFIX_VEX_380D */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { VEX_W_TABLE (VEX_W_380D_P_2) },
4370   },
4371
4372   /* PREFIX_VEX_380E */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { VEX_W_TABLE (VEX_W_380E_P_2) },
4377   },
4378
4379   /* PREFIX_VEX_380F */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { VEX_W_TABLE (VEX_W_380F_P_2) },
4384   },
4385
4386   /* PREFIX_VEX_3817 */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { VEX_W_TABLE (VEX_W_3817_P_2) },
4391   },
4392
4393   /* PREFIX_VEX_3818 */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4398   },
4399
4400   /* PREFIX_VEX_3819 */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4405   },
4406
4407   /* PREFIX_VEX_381A */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4412   },
4413
4414   /* PREFIX_VEX_381C */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4419   },
4420
4421   /* PREFIX_VEX_381D */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4426   },
4427
4428   /* PREFIX_VEX_381E */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4433   },
4434
4435   /* PREFIX_VEX_3820 */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4440     { Bad_Opcode },
4441   },
4442
4443   /* PREFIX_VEX_3821 */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4448   },
4449
4450   /* PREFIX_VEX_3822 */
4451   {
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4455   },
4456
4457   /* PREFIX_VEX_3823 */
4458   {
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4462   },
4463
4464   /* PREFIX_VEX_3824 */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4469   },
4470
4471   /* PREFIX_VEX_3825 */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4476   },
4477
4478   /* PREFIX_VEX_3828 */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4483   },
4484
4485   /* PREFIX_VEX_3829 */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4490   },
4491
4492   /* PREFIX_VEX_382A */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4497   },
4498
4499   /* PREFIX_VEX_382B */
4500   {
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4504   },
4505
4506   /* PREFIX_VEX_382C */
4507   {
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4511   },
4512
4513   /* PREFIX_VEX_382D */
4514   {
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4518   },
4519
4520   /* PREFIX_VEX_382E */
4521   {
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4525   },
4526
4527   /* PREFIX_VEX_382F */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4532   },
4533
4534   /* PREFIX_VEX_3830 */
4535   {
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4539   },
4540
4541   /* PREFIX_VEX_3831 */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4546   },
4547
4548   /* PREFIX_VEX_3832 */
4549   {
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4553   },
4554
4555   /* PREFIX_VEX_3833 */
4556   {
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4560   },
4561
4562   /* PREFIX_VEX_3834 */
4563   {
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4567   },
4568
4569   /* PREFIX_VEX_3835 */
4570   {
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4574   },
4575
4576   /* PREFIX_VEX_3837 */
4577   {
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4581   },
4582
4583   /* PREFIX_VEX_3838 */
4584   {
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4588   },
4589
4590   /* PREFIX_VEX_3839 */
4591   {
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4595   },
4596
4597   /* PREFIX_VEX_383A */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4602   },
4603
4604   /* PREFIX_VEX_383B */
4605   {
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4609   },
4610
4611   /* PREFIX_VEX_383C */
4612   {
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4616   },
4617
4618   /* PREFIX_VEX_383D */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4623   },
4624
4625   /* PREFIX_VEX_383E */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4630   },
4631
4632   /* PREFIX_VEX_383F */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4637   },
4638
4639   /* PREFIX_VEX_3840 */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4644   },
4645
4646   /* PREFIX_VEX_3841 */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4651   },
4652
4653   /* PREFIX_VEX_3896 */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4658   },
4659
4660   /* PREFIX_VEX_3897 */
4661   {
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4665   },
4666
4667   /* PREFIX_VEX_3898 */
4668   {
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { "vfmadd132p%XW", { XM, Vex, EXx } },
4672   },
4673
4674   /* PREFIX_VEX_3899 */
4675   {
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4679   },
4680
4681   /* PREFIX_VEX_389A */
4682   {
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { "vfmsub132p%XW", { XM, Vex, EXx } },
4686   },
4687
4688   /* PREFIX_VEX_389B */
4689   {
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4693   },
4694
4695   /* PREFIX_VEX_389C */
4696   {
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4700   },
4701
4702   /* PREFIX_VEX_389D */
4703   {
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4707   },
4708
4709   /* PREFIX_VEX_389E */
4710   {
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4714   },
4715
4716   /* PREFIX_VEX_389F */
4717   {
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4721   },
4722
4723   /* PREFIX_VEX_38A6 */
4724   {
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4728     { Bad_Opcode },
4729   },
4730
4731   /* PREFIX_VEX_38A7 */
4732   {
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4736   },
4737
4738   /* PREFIX_VEX_38A8 */
4739   {
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { "vfmadd213p%XW", { XM, Vex, EXx } },
4743   },
4744
4745   /* PREFIX_VEX_38A9 */
4746   {
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4750   },
4751
4752   /* PREFIX_VEX_38AA */
4753   {
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { "vfmsub213p%XW", { XM, Vex, EXx } },
4757   },
4758
4759   /* PREFIX_VEX_38AB */
4760   {
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4764   },
4765
4766   /* PREFIX_VEX_38AC */
4767   {
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4771   },
4772
4773   /* PREFIX_VEX_38AD */
4774   {
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4778   },
4779
4780   /* PREFIX_VEX_38AE */
4781   {
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4785   },
4786
4787   /* PREFIX_VEX_38AF */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4792   },
4793
4794   /* PREFIX_VEX_38B6 */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4799   },
4800
4801   /* PREFIX_VEX_38B7 */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4806   },
4807
4808   /* PREFIX_VEX_38B8 */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "vfmadd231p%XW", { XM, Vex, EXx } },
4813   },
4814
4815   /* PREFIX_VEX_38B9 */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4820   },
4821
4822   /* PREFIX_VEX_38BA */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { "vfmsub231p%XW", { XM, Vex, EXx } },
4827   },
4828
4829   /* PREFIX_VEX_38BB */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4834   },
4835
4836   /* PREFIX_VEX_38BC */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4841   },
4842
4843   /* PREFIX_VEX_38BD */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4848   },
4849
4850   /* PREFIX_VEX_38BE */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4855   },
4856
4857   /* PREFIX_VEX_38BF */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4862   },
4863
4864   /* PREFIX_VEX_38DB */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4869   },
4870
4871   /* PREFIX_VEX_38DC */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4876   },
4877
4878   /* PREFIX_VEX_38DD */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4883   },
4884
4885   /* PREFIX_VEX_38DE */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4890   },
4891
4892   /* PREFIX_VEX_38DF */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4897   },
4898
4899   /* PREFIX_VEX_3A04 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { VEX_W_TABLE (VEX_W_3A04_P_2) },
4904   },
4905
4906   /* PREFIX_VEX_3A05 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { VEX_W_TABLE (VEX_W_3A05_P_2) },
4911   },
4912
4913   /* PREFIX_VEX_3A06 */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4918   },
4919
4920   /* PREFIX_VEX_3A08 */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { VEX_W_TABLE (VEX_W_3A08_P_2) },
4925   },
4926
4927   /* PREFIX_VEX_3A09 */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { VEX_W_TABLE (VEX_W_3A09_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_3A0A */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_3A0B */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_3A0C */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_W_TABLE (VEX_W_3A0C_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_3A0D */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_W_TABLE (VEX_W_3A0D_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_3A0E */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_3A0F */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_3A14 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_3A15 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_3A16 */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_3A17 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5002   },
5003
5004   /* PREFIX_VEX_3A18 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_3A19 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_3A20 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_3A21 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_3A22 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_3A40 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_W_TABLE (VEX_W_3A40_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_3A41 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_3A42 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_3A44 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_3A4A */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_W_TABLE (VEX_W_3A4A_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_3A4B */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { VEX_W_TABLE (VEX_W_3A4B_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_3A4C */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_3A5C */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5093   },
5094
5095   /* PREFIX_VEX_3A5D */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5100   },
5101
5102   /* PREFIX_VEX_3A5E */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5107   },
5108
5109   /* PREFIX_VEX_3A5F */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5114   },
5115
5116   /* PREFIX_VEX_3A60 */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5121     { Bad_Opcode },
5122   },
5123
5124   /* PREFIX_VEX_3A61 */
5125   {
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_3A62 */
5132   {
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_3A63 */
5139   {
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_3A68 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5150   },
5151
5152   /* PREFIX_VEX_3A69 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5157   },
5158
5159   /* PREFIX_VEX_3A6A */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_3A6B */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5171   },
5172
5173   /* PREFIX_VEX_3A6C */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5178   },
5179
5180   /* PREFIX_VEX_3A6D */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5185   },
5186
5187   /* PREFIX_VEX_3A6E */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5192   },
5193
5194   /* PREFIX_VEX_3A6F */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5199   },
5200
5201   /* PREFIX_VEX_3A78 */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5206   },
5207
5208   /* PREFIX_VEX_3A79 */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5213   },
5214
5215   /* PREFIX_VEX_3A7A */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5220   },
5221
5222   /* PREFIX_VEX_3A7B */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5227   },
5228
5229   /* PREFIX_VEX_3A7C */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5234     { Bad_Opcode },
5235   },
5236
5237   /* PREFIX_VEX_3A7D */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5242   },
5243
5244   /* PREFIX_VEX_3A7E */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5249   },
5250
5251   /* PREFIX_VEX_3A7F */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5256   },
5257
5258   /* PREFIX_VEX_3ADF */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5263     { Bad_Opcode },
5264   },
5265 };
5266
5267 static const struct dis386 x86_64_table[][2] = {
5268   /* X86_64_06 */
5269   {
5270     { "push{T|}", { es } },
5271   },
5272
5273   /* X86_64_07 */
5274   {
5275     { "pop{T|}", { es } },
5276   },
5277
5278   /* X86_64_0D */
5279   {
5280     { "push{T|}", { cs } },
5281   },
5282
5283   /* X86_64_16 */
5284   {
5285     { "push{T|}", { ss } },
5286   },
5287
5288   /* X86_64_17 */
5289   {
5290     { "pop{T|}", { ss } },
5291   },
5292
5293   /* X86_64_1E */
5294   {
5295     { "push{T|}", { ds } },
5296   },
5297
5298   /* X86_64_1F */
5299   {
5300     { "pop{T|}", { ds } },
5301   },
5302
5303   /* X86_64_27 */
5304   {
5305     { "daa", { XX } },
5306   },
5307
5308   /* X86_64_2F */
5309   {
5310     { "das", { XX } },
5311   },
5312
5313   /* X86_64_37 */
5314   {
5315     { "aaa", { XX } },
5316   },
5317
5318   /* X86_64_3F */
5319   {
5320     { "aas", { XX } },
5321   },
5322
5323   /* X86_64_60 */
5324   {
5325     { "pusha{P|}", { XX } },
5326   },
5327
5328   /* X86_64_61 */
5329   {
5330     { "popa{P|}", { XX } },
5331   },
5332
5333   /* X86_64_62 */
5334   {
5335     { MOD_TABLE (MOD_62_32BIT) },
5336   },
5337
5338   /* X86_64_63 */
5339   {
5340     { "arpl", { Ew, Gw } },
5341     { "movs{lq|xd}", { Gv, Ed } },
5342   },
5343
5344   /* X86_64_6D */
5345   {
5346     { "ins{R|}", { Yzr, indirDX } },
5347     { "ins{G|}", { Yzr, indirDX } },
5348   },
5349
5350   /* X86_64_6F */
5351   {
5352     { "outs{R|}", { indirDXr, Xz } },
5353     { "outs{G|}", { indirDXr, Xz } },
5354   },
5355
5356   /* X86_64_9A */
5357   {
5358     { "Jcall{T|}", { Ap } },
5359   },
5360
5361   /* X86_64_C4 */
5362   {
5363     { MOD_TABLE (MOD_C4_32BIT) },
5364     { VEX_C4_TABLE (VEX_0F) },
5365   },
5366
5367   /* X86_64_C5 */
5368   {
5369     { MOD_TABLE (MOD_C5_32BIT) },
5370     { VEX_C5_TABLE (VEX_0F) },
5371   },
5372
5373   /* X86_64_CE */
5374   {
5375     { "into", { XX } },
5376   },
5377
5378   /* X86_64_D4 */
5379   {
5380     { "aam", { sIb } },
5381   },
5382
5383   /* X86_64_D5 */
5384   {
5385     { "aad", { sIb } },
5386   },
5387
5388   /* X86_64_EA */
5389   {
5390     { "Jjmp{T|}", { Ap } },
5391   },
5392
5393   /* X86_64_0F01_REG_0 */
5394   {
5395     { "sgdt{Q|IQ}", { M } },
5396     { "sgdt", { M } },
5397   },
5398
5399   /* X86_64_0F01_REG_1 */
5400   {
5401     { "sidt{Q|IQ}", { M } },
5402     { "sidt", { M } },
5403   },
5404
5405   /* X86_64_0F01_REG_2 */
5406   {
5407     { "lgdt{Q|Q}", { M } },
5408     { "lgdt", { M } },
5409   },
5410
5411   /* X86_64_0F01_REG_3 */
5412   {
5413     { "lidt{Q|Q}", { M } },
5414     { "lidt", { M } },
5415   },
5416 };
5417
5418 static const struct dis386 three_byte_table[][256] = {
5419
5420   /* THREE_BYTE_0F38 */
5421   {
5422     /* 00 */
5423     { "pshufb",         { MX, EM } },
5424     { "phaddw",         { MX, EM } },
5425     { "phaddd",         { MX, EM } },
5426     { "phaddsw",        { MX, EM } },
5427     { "pmaddubsw",      { MX, EM } },
5428     { "phsubw",         { MX, EM } },
5429     { "phsubd",         { MX, EM } },
5430     { "phsubsw",        { MX, EM } },
5431     /* 08 */
5432     { "psignb",         { MX, EM } },
5433     { "psignw",         { MX, EM } },
5434     { "psignd",         { MX, EM } },
5435     { "pmulhrsw",       { MX, EM } },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     /* 10 */
5441     { PREFIX_TABLE (PREFIX_0F3810) },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { PREFIX_TABLE (PREFIX_0F3814) },
5446     { PREFIX_TABLE (PREFIX_0F3815) },
5447     { Bad_Opcode },
5448     { PREFIX_TABLE (PREFIX_0F3817) },
5449     /* 18 */
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { "pabsb",          { MX, EM } },
5455     { "pabsw",          { MX, EM } },
5456     { "pabsd",          { MX, EM } },
5457     { Bad_Opcode },
5458     /* 20 */
5459     { PREFIX_TABLE (PREFIX_0F3820) },
5460     { PREFIX_TABLE (PREFIX_0F3821) },
5461     { PREFIX_TABLE (PREFIX_0F3822) },
5462     { PREFIX_TABLE (PREFIX_0F3823) },
5463     { PREFIX_TABLE (PREFIX_0F3824) },
5464     { PREFIX_TABLE (PREFIX_0F3825) },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     /* 28 */
5468     { PREFIX_TABLE (PREFIX_0F3828) },
5469     { PREFIX_TABLE (PREFIX_0F3829) },
5470     { PREFIX_TABLE (PREFIX_0F382A) },
5471     { PREFIX_TABLE (PREFIX_0F382B) },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     /* 30 */
5477     { PREFIX_TABLE (PREFIX_0F3830) },
5478     { PREFIX_TABLE (PREFIX_0F3831) },
5479     { PREFIX_TABLE (PREFIX_0F3832) },
5480     { PREFIX_TABLE (PREFIX_0F3833) },
5481     { PREFIX_TABLE (PREFIX_0F3834) },
5482     { PREFIX_TABLE (PREFIX_0F3835) },
5483     { Bad_Opcode },
5484     { PREFIX_TABLE (PREFIX_0F3837) },
5485     /* 38 */
5486     { PREFIX_TABLE (PREFIX_0F3838) },
5487     { PREFIX_TABLE (PREFIX_0F3839) },
5488     { PREFIX_TABLE (PREFIX_0F383A) },
5489     { PREFIX_TABLE (PREFIX_0F383B) },
5490     { PREFIX_TABLE (PREFIX_0F383C) },
5491     { PREFIX_TABLE (PREFIX_0F383D) },
5492     { PREFIX_TABLE (PREFIX_0F383E) },
5493     { PREFIX_TABLE (PREFIX_0F383F) },
5494     /* 40 */
5495     { PREFIX_TABLE (PREFIX_0F3840) },
5496     { PREFIX_TABLE (PREFIX_0F3841) },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     /* 48 */
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     /* 50 */
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     /* 58 */
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     /* 60 */
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     /* 68 */
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     /* 70 */
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     /* 78 */
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     /* 80 */
5567     { PREFIX_TABLE (PREFIX_0F3880) },
5568     { PREFIX_TABLE (PREFIX_0F3881) },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     /* 88 */
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     /* 90 */
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     /* 98 */
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     /* a0 */
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     /* a8 */
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     /* b0 */
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     /* b8 */
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     /* c0 */
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     /* c8 */
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     /* d0 */
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     /* d8 */
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { PREFIX_TABLE (PREFIX_0F38DB) },
5670     { PREFIX_TABLE (PREFIX_0F38DC) },
5671     { PREFIX_TABLE (PREFIX_0F38DD) },
5672     { PREFIX_TABLE (PREFIX_0F38DE) },
5673     { PREFIX_TABLE (PREFIX_0F38DF) },
5674     /* e0 */
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     /* e8 */
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     /* f0 */
5693     { PREFIX_TABLE (PREFIX_0F38F0) },
5694     { PREFIX_TABLE (PREFIX_0F38F1) },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     /* f8 */
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710   },
5711   /* THREE_BYTE_0F3A */
5712   {
5713     /* 00 */
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     /* 08 */
5723     { PREFIX_TABLE (PREFIX_0F3A08) },
5724     { PREFIX_TABLE (PREFIX_0F3A09) },
5725     { PREFIX_TABLE (PREFIX_0F3A0A) },
5726     { PREFIX_TABLE (PREFIX_0F3A0B) },
5727     { PREFIX_TABLE (PREFIX_0F3A0C) },
5728     { PREFIX_TABLE (PREFIX_0F3A0D) },
5729     { PREFIX_TABLE (PREFIX_0F3A0E) },
5730     { "palignr",        { MX, EM, Ib } },
5731     /* 10 */
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { PREFIX_TABLE (PREFIX_0F3A14) },
5737     { PREFIX_TABLE (PREFIX_0F3A15) },
5738     { PREFIX_TABLE (PREFIX_0F3A16) },
5739     { PREFIX_TABLE (PREFIX_0F3A17) },
5740     /* 18 */
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     /* 20 */
5750     { PREFIX_TABLE (PREFIX_0F3A20) },
5751     { PREFIX_TABLE (PREFIX_0F3A21) },
5752     { PREFIX_TABLE (PREFIX_0F3A22) },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     /* 28 */
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     /* 30 */
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     /* 38 */
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     /* 40 */
5786     { PREFIX_TABLE (PREFIX_0F3A40) },
5787     { PREFIX_TABLE (PREFIX_0F3A41) },
5788     { PREFIX_TABLE (PREFIX_0F3A42) },
5789     { Bad_Opcode },
5790     { PREFIX_TABLE (PREFIX_0F3A44) },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     /* 48 */
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     /* 50 */
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     /* 58 */
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     /* 60 */
5822     { PREFIX_TABLE (PREFIX_0F3A60) },
5823     { PREFIX_TABLE (PREFIX_0F3A61) },
5824     { PREFIX_TABLE (PREFIX_0F3A62) },
5825     { PREFIX_TABLE (PREFIX_0F3A63) },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     /* 68 */
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     /* 70 */
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     /* 78 */
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     /* 80 */
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     /* 88 */
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     /* 90 */
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     /* 98 */
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     /* a0 */
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     /* a8 */
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     /* b0 */
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     /* b8 */
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     /* c0 */
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     /* c8 */
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     /* d0 */
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     /* d8 */
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { PREFIX_TABLE (PREFIX_0F3ADF) },
5965     /* e0 */
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     /* e8 */
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     /* f0 */
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     /* f8 */
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001   },
6002
6003   /* THREE_BYTE_0F7A */
6004   {
6005     /* 00 */
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     /* 08 */
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     /* 10 */
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     /* 18 */
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     /* 20 */
6042     { "ptest",          { XX } },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     /* 28 */
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     /* 30 */
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     /* 38 */
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     /* 40 */
6078     { Bad_Opcode },
6079     { "phaddbw",        { XM, EXq } },
6080     { "phaddbd",        { XM, EXq } },
6081     { "phaddbq",        { XM, EXq } },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "phaddwd",        { XM, EXq } },
6085     { "phaddwq",        { XM, EXq } },
6086     /* 48 */
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "phadddq",        { XM, EXq } },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     /* 50 */
6096     { Bad_Opcode },
6097     { "phaddubw",       { XM, EXq } },
6098     { "phaddubd",       { XM, EXq } },
6099     { "phaddubq",       { XM, EXq } },
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "phadduwd",       { XM, EXq } },
6103     { "phadduwq",       { XM, EXq } },
6104     /* 58 */
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "phaddudq",       { XM, EXq } },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     /* 60 */
6114     { Bad_Opcode },
6115     { "phsubbw",        { XM, EXq } },
6116     { "phsubbd",        { XM, EXq } },
6117     { "phsubbq",        { XM, EXq } },
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     /* 68 */
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     /* 70 */
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     /* 78 */
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     /* 80 */
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     /* 88 */
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     /* 90 */
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     /* 98 */
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     /* a0 */
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     /* a8 */
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     /* b0 */
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     /* b8 */
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     /* c0 */
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     /* c8 */
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     /* d0 */
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     /* d8 */
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     /* e0 */
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     /* e8 */
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     /* f0 */
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     /* f8 */
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293   },
6294 };
6295
6296 static const struct dis386 xop_table[][256] = {
6297   /* XOP_08 */
6298   {
6299     /* 00 */
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     /* 08 */
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     /* 10 */
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     /* 18 */
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     /* 20 */
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     /* 28 */
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     /* 30 */
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     /* 38 */
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     /* 40 */
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     /* 48 */
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     /* 50 */
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     /* 58 */
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     /* 60 */
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     /* 68 */
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     /* 70 */
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     /* 78 */
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     /* 80 */
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6450     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6451     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6452     /* 88 */
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6460     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6461     /* 90 */
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6468     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6469     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6470     /* 98 */
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6478     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6479     /* a0 */
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6483     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6487     { Bad_Opcode },
6488     /* a8 */
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     /* b0 */
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6505     { Bad_Opcode },
6506     /* b8 */
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     /* c0 */
6516     { "vprotb",         { XM, Vex_2src_1, Ib } },
6517     { "vprotw",         { XM, Vex_2src_1, Ib } },
6518     { "vprotd",         { XM, Vex_2src_1, Ib } },
6519     { "vprotq",         { XM, Vex_2src_1, Ib } },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     /* c8 */
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6530     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6531     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6532     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6533     /* d0 */
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     /* d8 */
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     /* e0 */
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     /* e8 */
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6566     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6567     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6568     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6569     /* f0 */
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     /* f8 */
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587   },
6588   /* XOP_09 */
6589   {
6590     /* 00 */
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     /* 08 */
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     /* 10 */
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { REG_TABLE (REG_XOP_LWPCB) },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     /* 18 */
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     /* 20 */
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     /* 28 */
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     /* 30 */
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     /* 38 */
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     /* 40 */
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     /* 48 */
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     /* 50 */
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     /* 58 */
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     /* 60 */
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     /* 68 */
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     /* 70 */
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     /* 78 */
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     /* 80 */
6735     { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6736     { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6737     { "vfrczss",        { XM, EXd } },
6738     { "vfrczsd",        { XM, EXq } },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     /* 88 */
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     /* 90 */
6753     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6754     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6755     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6756     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6757     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6758     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6759     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6760     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6761     /* 98 */
6762     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6763     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6764     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6765     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     /* a0 */
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     /* a8 */
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     /* b0 */
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     /* b8 */
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     /* c0 */
6807     { Bad_Opcode },
6808     { "vphaddbw",       { XM, EXxmm } },
6809     { "vphaddbd",       { XM, EXxmm } },
6810     { "vphaddbq",       { XM, EXxmm } },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { "vphaddwd",       { XM, EXxmm } },
6814     { "vphaddwq",       { XM, EXxmm } },
6815     /* c8 */
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { "vphadddq",       { XM, EXxmm } },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     /* d0 */
6825     { Bad_Opcode },
6826     { "vphaddubw",      { XM, EXxmm } },
6827     { "vphaddubd",      { XM, EXxmm } },
6828     { "vphaddubq",      { XM, EXxmm } },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { "vphadduwd",      { XM, EXxmm } },
6832     { "vphadduwq",      { XM, EXxmm } },
6833     /* d8 */
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { "vphaddudq",      { XM, EXxmm } },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     /* e0 */
6843     { Bad_Opcode },
6844     { "vphsubbw",       { XM, EXxmm } },
6845     { "vphsubwd",       { XM, EXxmm } },
6846     { "vphsubdq",       { XM, EXxmm } },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     /* e8 */
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     /* f0 */
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     /* f8 */
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878   },
6879   /* XOP_0A */
6880   {
6881     /* 00 */
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     /* 08 */
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     /* 10 */
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { REG_TABLE (REG_XOP_LWP) },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     /* 18 */
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     /* 20 */
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     /* 28 */
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     /* 30 */
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     /* 38 */
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     /* 40 */
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     /* 48 */
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     /* 50 */
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     /* 58 */
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     /* 60 */
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     /* 68 */
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     /* 70 */
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     /* 78 */
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     /* 80 */
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* 88 */
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* 90 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* 98 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* a0 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* a8 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* b0 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* b8 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* c0 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* c8 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* d0 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* d8 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* e0 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     /* e8 */
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     /* f0 */
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     /* f8 */
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169   },
7170 };
7171
7172 static const struct dis386 vex_table[][256] = {
7173   /* VEX_0F */
7174   {
7175     /* 00 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* 08 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* 10 */
7194     { PREFIX_TABLE (PREFIX_VEX_10) },
7195     { PREFIX_TABLE (PREFIX_VEX_11) },
7196     { PREFIX_TABLE (PREFIX_VEX_12) },
7197     { MOD_TABLE (MOD_VEX_13) },
7198     { VEX_W_TABLE (VEX_W_14) },
7199     { VEX_W_TABLE (VEX_W_15) },
7200     { PREFIX_TABLE (PREFIX_VEX_16) },
7201     { MOD_TABLE (MOD_VEX_17) },
7202     /* 18 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 20 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 28 */
7221     { VEX_W_TABLE (VEX_W_28) },
7222     { VEX_W_TABLE (VEX_W_29) },
7223     { PREFIX_TABLE (PREFIX_VEX_2A) },
7224     { MOD_TABLE (MOD_VEX_2B) },
7225     { PREFIX_TABLE (PREFIX_VEX_2C) },
7226     { PREFIX_TABLE (PREFIX_VEX_2D) },
7227     { PREFIX_TABLE (PREFIX_VEX_2E) },
7228     { PREFIX_TABLE (PREFIX_VEX_2F) },
7229     /* 30 */
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 38 */
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* 40 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* 48 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* 50 */
7266     { MOD_TABLE (MOD_VEX_50) },
7267     { PREFIX_TABLE (PREFIX_VEX_51) },
7268     { PREFIX_TABLE (PREFIX_VEX_52) },
7269     { PREFIX_TABLE (PREFIX_VEX_53) },
7270     { "vandpX",         { XM, Vex, EXx } },
7271     { "vandnpX",        { XM, Vex, EXx } },
7272     { "vorpX",          { XM, Vex, EXx } },
7273     { "vxorpX",         { XM, Vex, EXx } },
7274     /* 58 */
7275     { PREFIX_TABLE (PREFIX_VEX_58) },
7276     { PREFIX_TABLE (PREFIX_VEX_59) },
7277     { PREFIX_TABLE (PREFIX_VEX_5A) },
7278     { PREFIX_TABLE (PREFIX_VEX_5B) },
7279     { PREFIX_TABLE (PREFIX_VEX_5C) },
7280     { PREFIX_TABLE (PREFIX_VEX_5D) },
7281     { PREFIX_TABLE (PREFIX_VEX_5E) },
7282     { PREFIX_TABLE (PREFIX_VEX_5F) },
7283     /* 60 */
7284     { PREFIX_TABLE (PREFIX_VEX_60) },
7285     { PREFIX_TABLE (PREFIX_VEX_61) },
7286     { PREFIX_TABLE (PREFIX_VEX_62) },
7287     { PREFIX_TABLE (PREFIX_VEX_63) },
7288     { PREFIX_TABLE (PREFIX_VEX_64) },
7289     { PREFIX_TABLE (PREFIX_VEX_65) },
7290     { PREFIX_TABLE (PREFIX_VEX_66) },
7291     { PREFIX_TABLE (PREFIX_VEX_67) },
7292     /* 68 */
7293     { PREFIX_TABLE (PREFIX_VEX_68) },
7294     { PREFIX_TABLE (PREFIX_VEX_69) },
7295     { PREFIX_TABLE (PREFIX_VEX_6A) },
7296     { PREFIX_TABLE (PREFIX_VEX_6B) },
7297     { PREFIX_TABLE (PREFIX_VEX_6C) },
7298     { PREFIX_TABLE (PREFIX_VEX_6D) },
7299     { PREFIX_TABLE (PREFIX_VEX_6E) },
7300     { PREFIX_TABLE (PREFIX_VEX_6F) },
7301     /* 70 */
7302     { PREFIX_TABLE (PREFIX_VEX_70) },
7303     { REG_TABLE (REG_VEX_71) },
7304     { REG_TABLE (REG_VEX_72) },
7305     { REG_TABLE (REG_VEX_73) },
7306     { PREFIX_TABLE (PREFIX_VEX_74) },
7307     { PREFIX_TABLE (PREFIX_VEX_75) },
7308     { PREFIX_TABLE (PREFIX_VEX_76) },
7309     { PREFIX_TABLE (PREFIX_VEX_77) },
7310     /* 78 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { PREFIX_TABLE (PREFIX_VEX_7C) },
7316     { PREFIX_TABLE (PREFIX_VEX_7D) },
7317     { PREFIX_TABLE (PREFIX_VEX_7E) },
7318     { PREFIX_TABLE (PREFIX_VEX_7F) },
7319     /* 80 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* 88 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* 90 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* 98 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* a0 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* a8 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { REG_TABLE (REG_VEX_AE) },
7372     { Bad_Opcode },
7373     /* b0 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* b8 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* c0 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { PREFIX_TABLE (PREFIX_VEX_C2) },
7395     { Bad_Opcode },
7396     { PREFIX_TABLE (PREFIX_VEX_C4) },
7397     { PREFIX_TABLE (PREFIX_VEX_C5) },
7398     { "vshufpX",        { XM, Vex, EXx, Ib } },
7399     { Bad_Opcode },
7400     /* c8 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* d0 */
7410     { PREFIX_TABLE (PREFIX_VEX_D0) },
7411     { PREFIX_TABLE (PREFIX_VEX_D1) },
7412     { PREFIX_TABLE (PREFIX_VEX_D2) },
7413     { PREFIX_TABLE (PREFIX_VEX_D3) },
7414     { PREFIX_TABLE (PREFIX_VEX_D4) },
7415     { PREFIX_TABLE (PREFIX_VEX_D5) },
7416     { PREFIX_TABLE (PREFIX_VEX_D6) },
7417     { PREFIX_TABLE (PREFIX_VEX_D7) },
7418     /* d8 */
7419     { PREFIX_TABLE (PREFIX_VEX_D8) },
7420     { PREFIX_TABLE (PREFIX_VEX_D9) },
7421     { PREFIX_TABLE (PREFIX_VEX_DA) },
7422     { PREFIX_TABLE (PREFIX_VEX_DB) },
7423     { PREFIX_TABLE (PREFIX_VEX_DC) },
7424     { PREFIX_TABLE (PREFIX_VEX_DD) },
7425     { PREFIX_TABLE (PREFIX_VEX_DE) },
7426     { PREFIX_TABLE (PREFIX_VEX_DF) },
7427     /* e0 */
7428     { PREFIX_TABLE (PREFIX_VEX_E0) },
7429     { PREFIX_TABLE (PREFIX_VEX_E1) },
7430     { PREFIX_TABLE (PREFIX_VEX_E2) },
7431     { PREFIX_TABLE (PREFIX_VEX_E3) },
7432     { PREFIX_TABLE (PREFIX_VEX_E4) },
7433     { PREFIX_TABLE (PREFIX_VEX_E5) },
7434     { PREFIX_TABLE (PREFIX_VEX_E6) },
7435     { PREFIX_TABLE (PREFIX_VEX_E7) },
7436     /* e8 */
7437     { PREFIX_TABLE (PREFIX_VEX_E8) },
7438     { PREFIX_TABLE (PREFIX_VEX_E9) },
7439     { PREFIX_TABLE (PREFIX_VEX_EA) },
7440     { PREFIX_TABLE (PREFIX_VEX_EB) },
7441     { PREFIX_TABLE (PREFIX_VEX_EC) },
7442     { PREFIX_TABLE (PREFIX_VEX_ED) },
7443     { PREFIX_TABLE (PREFIX_VEX_EE) },
7444     { PREFIX_TABLE (PREFIX_VEX_EF) },
7445     /* f0 */
7446     { PREFIX_TABLE (PREFIX_VEX_F0) },
7447     { PREFIX_TABLE (PREFIX_VEX_F1) },
7448     { PREFIX_TABLE (PREFIX_VEX_F2) },
7449     { PREFIX_TABLE (PREFIX_VEX_F3) },
7450     { PREFIX_TABLE (PREFIX_VEX_F4) },
7451     { PREFIX_TABLE (PREFIX_VEX_F5) },
7452     { PREFIX_TABLE (PREFIX_VEX_F6) },
7453     { PREFIX_TABLE (PREFIX_VEX_F7) },
7454     /* f8 */
7455     { PREFIX_TABLE (PREFIX_VEX_F8) },
7456     { PREFIX_TABLE (PREFIX_VEX_F9) },
7457     { PREFIX_TABLE (PREFIX_VEX_FA) },
7458     { PREFIX_TABLE (PREFIX_VEX_FB) },
7459     { PREFIX_TABLE (PREFIX_VEX_FC) },
7460     { PREFIX_TABLE (PREFIX_VEX_FD) },
7461     { PREFIX_TABLE (PREFIX_VEX_FE) },
7462     { Bad_Opcode },
7463   },
7464   /* VEX_0F38 */
7465   {
7466     /* 00 */
7467     { PREFIX_TABLE (PREFIX_VEX_3800) },
7468     { PREFIX_TABLE (PREFIX_VEX_3801) },
7469     { PREFIX_TABLE (PREFIX_VEX_3802) },
7470     { PREFIX_TABLE (PREFIX_VEX_3803) },
7471     { PREFIX_TABLE (PREFIX_VEX_3804) },
7472     { PREFIX_TABLE (PREFIX_VEX_3805) },
7473     { PREFIX_TABLE (PREFIX_VEX_3806) },
7474     { PREFIX_TABLE (PREFIX_VEX_3807) },
7475     /* 08 */
7476     { PREFIX_TABLE (PREFIX_VEX_3808) },
7477     { PREFIX_TABLE (PREFIX_VEX_3809) },
7478     { PREFIX_TABLE (PREFIX_VEX_380A) },
7479     { PREFIX_TABLE (PREFIX_VEX_380B) },
7480     { PREFIX_TABLE (PREFIX_VEX_380C) },
7481     { PREFIX_TABLE (PREFIX_VEX_380D) },
7482     { PREFIX_TABLE (PREFIX_VEX_380E) },
7483     { PREFIX_TABLE (PREFIX_VEX_380F) },
7484     /* 10 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { PREFIX_TABLE (PREFIX_VEX_3817) },
7493     /* 18 */
7494     { PREFIX_TABLE (PREFIX_VEX_3818) },
7495     { PREFIX_TABLE (PREFIX_VEX_3819) },
7496     { PREFIX_TABLE (PREFIX_VEX_381A) },
7497     { Bad_Opcode },
7498     { PREFIX_TABLE (PREFIX_VEX_381C) },
7499     { PREFIX_TABLE (PREFIX_VEX_381D) },
7500     { PREFIX_TABLE (PREFIX_VEX_381E) },
7501     { Bad_Opcode },
7502     /* 20 */
7503     { PREFIX_TABLE (PREFIX_VEX_3820) },
7504     { PREFIX_TABLE (PREFIX_VEX_3821) },
7505     { PREFIX_TABLE (PREFIX_VEX_3822) },
7506     { PREFIX_TABLE (PREFIX_VEX_3823) },
7507     { PREFIX_TABLE (PREFIX_VEX_3824) },
7508     { PREFIX_TABLE (PREFIX_VEX_3825) },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     /* 28 */
7512     { PREFIX_TABLE (PREFIX_VEX_3828) },
7513     { PREFIX_TABLE (PREFIX_VEX_3829) },
7514     { PREFIX_TABLE (PREFIX_VEX_382A) },
7515     { PREFIX_TABLE (PREFIX_VEX_382B) },
7516     { PREFIX_TABLE (PREFIX_VEX_382C) },
7517     { PREFIX_TABLE (PREFIX_VEX_382D) },
7518     { PREFIX_TABLE (PREFIX_VEX_382E) },
7519     { PREFIX_TABLE (PREFIX_VEX_382F) },
7520     /* 30 */
7521     { PREFIX_TABLE (PREFIX_VEX_3830) },
7522     { PREFIX_TABLE (PREFIX_VEX_3831) },
7523     { PREFIX_TABLE (PREFIX_VEX_3832) },
7524     { PREFIX_TABLE (PREFIX_VEX_3833) },
7525     { PREFIX_TABLE (PREFIX_VEX_3834) },
7526     { PREFIX_TABLE (PREFIX_VEX_3835) },
7527     { Bad_Opcode },
7528     { PREFIX_TABLE (PREFIX_VEX_3837) },
7529     /* 38 */
7530     { PREFIX_TABLE (PREFIX_VEX_3838) },
7531     { PREFIX_TABLE (PREFIX_VEX_3839) },
7532     { PREFIX_TABLE (PREFIX_VEX_383A) },
7533     { PREFIX_TABLE (PREFIX_VEX_383B) },
7534     { PREFIX_TABLE (PREFIX_VEX_383C) },
7535     { PREFIX_TABLE (PREFIX_VEX_383D) },
7536     { PREFIX_TABLE (PREFIX_VEX_383E) },
7537     { PREFIX_TABLE (PREFIX_VEX_383F) },
7538     /* 40 */
7539     { PREFIX_TABLE (PREFIX_VEX_3840) },
7540     { PREFIX_TABLE (PREFIX_VEX_3841) },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     /* 48 */
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     /* 50 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* 58 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* 60 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 68 */
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* 70 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* 78 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* 80 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* 88 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* 90 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { PREFIX_TABLE (PREFIX_VEX_3896) },
7636     { PREFIX_TABLE (PREFIX_VEX_3897) },
7637     /* 98 */
7638     { PREFIX_TABLE (PREFIX_VEX_3898) },
7639     { PREFIX_TABLE (PREFIX_VEX_3899) },
7640     { PREFIX_TABLE (PREFIX_VEX_389A) },
7641     { PREFIX_TABLE (PREFIX_VEX_389B) },
7642     { PREFIX_TABLE (PREFIX_VEX_389C) },
7643     { PREFIX_TABLE (PREFIX_VEX_389D) },
7644     { PREFIX_TABLE (PREFIX_VEX_389E) },
7645     { PREFIX_TABLE (PREFIX_VEX_389F) },
7646     /* a0 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7654     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7655     /* a8 */
7656     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7657     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7658     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7659     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7660     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7661     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7662     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7663     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7664     /* b0 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7672     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7673     /* b8 */
7674     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7675     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7676     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7677     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7678     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7679     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7680     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7681     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7682     /* c0 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* c8 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* d0 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     /* d8 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7714     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7715     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7716     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7717     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7718     /* e0 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     /* e8 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     /* f0 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     /* f8 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754   },
7755   /* VEX_0F3A */
7756   {
7757     /* 00 */
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7763     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7764     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7765     { Bad_Opcode },
7766     /* 08 */
7767     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7768     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7769     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7770     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7771     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7772     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7773     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7774     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7775     /* 10 */
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7781     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7782     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7783     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7784     /* 18 */
7785     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7786     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     /* 20 */
7794     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7795     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7796     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     /* 28 */
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     /* 30 */
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     /* 38 */
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     /* 40 */
7830     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7831     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7832     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7833     { Bad_Opcode },
7834     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     /* 48 */
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7842     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7843     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     /* 50 */
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     /* 58 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7862     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7863     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7864     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7865     /* 60 */
7866     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7867     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7868     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7869     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     /* 68 */
7875     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7876     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7877     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7878     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7879     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7880     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7881     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7882     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7883     /* 70 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     /* 78 */
7893     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7894     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7895     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7896     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7897     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7898     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7899     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7900     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7901     /* 80 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     /* 88 */
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     /* 90 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     /* 98 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     /* a0 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* a8 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* b0 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* b8 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* c0 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* c8 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* d0 */
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* d8 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8009     /* e0 */
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     /* e8 */
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     /* f0 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     /* f8 */
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045   },
8046 };
8047
8048 static const struct dis386 vex_len_table[][2] = {
8049   /* VEX_LEN_10_P_1 */
8050   {
8051     { VEX_W_TABLE (VEX_W_10_P_1) },
8052   },
8053
8054   /* VEX_LEN_10_P_3 */
8055   {
8056     { VEX_W_TABLE (VEX_W_10_P_3) },
8057   },
8058
8059   /* VEX_LEN_11_P_1 */
8060   {
8061     { VEX_W_TABLE (VEX_W_11_P_1) },
8062   },
8063
8064   /* VEX_LEN_11_P_3 */
8065   {
8066     { VEX_W_TABLE (VEX_W_11_P_3) },
8067   },
8068
8069   /* VEX_LEN_12_P_0_M_0 */
8070   {
8071     { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
8072   },
8073
8074   /* VEX_LEN_12_P_0_M_1 */
8075   {
8076     { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
8077   },
8078
8079   /* VEX_LEN_12_P_2 */
8080   {
8081     { VEX_W_TABLE (VEX_W_12_P_2) },
8082   },
8083
8084   /* VEX_LEN_13_M_0 */
8085   {
8086     { VEX_W_TABLE (VEX_W_13_M_0) },
8087   },
8088
8089   /* VEX_LEN_16_P_0_M_0 */
8090   {
8091     { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
8092   },
8093
8094   /* VEX_LEN_16_P_0_M_1 */
8095   {
8096     { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
8097   },
8098
8099   /* VEX_LEN_16_P_2 */
8100   {
8101     { VEX_W_TABLE (VEX_W_16_P_2) },
8102   },
8103
8104   /* VEX_LEN_17_M_0 */
8105   {
8106     { VEX_W_TABLE (VEX_W_17_M_0) },
8107   },
8108
8109   /* VEX_LEN_2A_P_1 */
8110   {
8111     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
8112   },
8113
8114   /* VEX_LEN_2A_P_3 */
8115   {
8116     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
8117   },
8118
8119   /* VEX_LEN_2C_P_1 */
8120   {
8121     { "vcvttss2siY",    { Gv, EXd } },
8122   },
8123
8124   /* VEX_LEN_2C_P_3 */
8125   {
8126     { "vcvttsd2siY",    { Gv, EXq } },
8127   },
8128
8129   /* VEX_LEN_2D_P_1 */
8130   {
8131     { "vcvtss2siY",     { Gv, EXd } },
8132   },
8133
8134   /* VEX_LEN_2D_P_3 */
8135   {
8136     { "vcvtsd2siY",     { Gv, EXq } },
8137   },
8138
8139   /* VEX_LEN_2E_P_0 */
8140   {
8141     { VEX_W_TABLE (VEX_W_2E_P_0) },
8142   },
8143
8144   /* VEX_LEN_2E_P_2 */
8145   {
8146     { VEX_W_TABLE (VEX_W_2E_P_2) },
8147   },
8148
8149   /* VEX_LEN_2F_P_0 */
8150   {
8151     { VEX_W_TABLE (VEX_W_2F_P_0) },
8152   },
8153
8154   /* VEX_LEN_2F_P_2 */
8155   {
8156     { VEX_W_TABLE (VEX_W_2F_P_2) },
8157   },
8158
8159   /* VEX_LEN_51_P_1 */
8160   {
8161     { VEX_W_TABLE (VEX_W_51_P_1) },
8162   },
8163
8164   /* VEX_LEN_51_P_3 */
8165   {
8166     { VEX_W_TABLE (VEX_W_51_P_3) },
8167   },
8168
8169   /* VEX_LEN_52_P_1 */
8170   {
8171     { VEX_W_TABLE (VEX_W_52_P_1) },
8172   },
8173
8174   /* VEX_LEN_53_P_1 */
8175   {
8176     { VEX_W_TABLE (VEX_W_53_P_1) },
8177   },
8178
8179   /* VEX_LEN_58_P_1 */
8180   {
8181     { VEX_W_TABLE (VEX_W_58_P_1) },
8182   },
8183
8184   /* VEX_LEN_58_P_3 */
8185   {
8186     { VEX_W_TABLE (VEX_W_58_P_3) },
8187   },
8188
8189   /* VEX_LEN_59_P_1 */
8190   {
8191     { VEX_W_TABLE (VEX_W_59_P_1) },
8192   },
8193
8194   /* VEX_LEN_59_P_3 */
8195   {
8196     { VEX_W_TABLE (VEX_W_59_P_3) },
8197   },
8198
8199   /* VEX_LEN_5A_P_1 */
8200   {
8201     { VEX_W_TABLE (VEX_W_5A_P_1) },
8202   },
8203
8204   /* VEX_LEN_5A_P_3 */
8205   {
8206     { VEX_W_TABLE (VEX_W_5A_P_3) },
8207   },
8208
8209   /* VEX_LEN_5C_P_1 */
8210   {
8211     { VEX_W_TABLE (VEX_W_5C_P_1) },
8212   },
8213
8214   /* VEX_LEN_5C_P_3 */
8215   {
8216     { VEX_W_TABLE (VEX_W_5C_P_3) },
8217   },
8218
8219   /* VEX_LEN_5D_P_1 */
8220   {
8221     { VEX_W_TABLE (VEX_W_5D_P_1) },
8222   },
8223
8224   /* VEX_LEN_5D_P_3 */
8225   {
8226     { VEX_W_TABLE (VEX_W_5D_P_3) },
8227   },
8228
8229   /* VEX_LEN_5E_P_1 */
8230   {
8231     { VEX_W_TABLE (VEX_W_5E_P_1) },
8232   },
8233
8234   /* VEX_LEN_5E_P_3 */
8235   {
8236     { VEX_W_TABLE (VEX_W_5E_P_3) },
8237   },
8238
8239   /* VEX_LEN_5F_P_1 */
8240   {
8241     { VEX_W_TABLE (VEX_W_5F_P_1) },
8242   },
8243
8244   /* VEX_LEN_5F_P_3 */
8245   {
8246     { VEX_W_TABLE (VEX_W_5F_P_3) },
8247   },
8248
8249   /* VEX_LEN_60_P_2 */
8250   {
8251     { VEX_W_TABLE (VEX_W_60_P_2) },
8252   },
8253
8254   /* VEX_LEN_61_P_2 */
8255   {
8256     { VEX_W_TABLE (VEX_W_61_P_2) },
8257   },
8258
8259   /* VEX_LEN_62_P_2 */
8260   {
8261     { VEX_W_TABLE (VEX_W_62_P_2) },
8262   },
8263
8264   /* VEX_LEN_63_P_2 */
8265   {
8266     { VEX_W_TABLE (VEX_W_63_P_2) },
8267   },
8268
8269   /* VEX_LEN_64_P_2 */
8270   {
8271     { VEX_W_TABLE (VEX_W_64_P_2) },
8272   },
8273
8274   /* VEX_LEN_65_P_2 */
8275   {
8276     { VEX_W_TABLE (VEX_W_65_P_2) },
8277   },
8278
8279   /* VEX_LEN_66_P_2 */
8280   {
8281     { VEX_W_TABLE (VEX_W_66_P_2) },
8282   },
8283
8284   /* VEX_LEN_67_P_2 */
8285   {
8286     { VEX_W_TABLE (VEX_W_67_P_2) },
8287   },
8288
8289   /* VEX_LEN_68_P_2 */
8290   {
8291     { VEX_W_TABLE (VEX_W_68_P_2) },
8292   },
8293
8294   /* VEX_LEN_69_P_2 */
8295   {
8296     { VEX_W_TABLE (VEX_W_69_P_2) },
8297   },
8298
8299   /* VEX_LEN_6A_P_2 */
8300   {
8301     { VEX_W_TABLE (VEX_W_6A_P_2) },
8302   },
8303
8304   /* VEX_LEN_6B_P_2 */
8305   {
8306     { VEX_W_TABLE (VEX_W_6B_P_2) },
8307   },
8308
8309   /* VEX_LEN_6C_P_2 */
8310   {
8311     { VEX_W_TABLE (VEX_W_6C_P_2) },
8312   },
8313
8314   /* VEX_LEN_6D_P_2 */
8315   {
8316     { VEX_W_TABLE (VEX_W_6D_P_2) },
8317   },
8318
8319   /* VEX_LEN_6E_P_2 */
8320   {
8321     { "vmovK",          { XM, Edq } },
8322   },
8323
8324   /* VEX_LEN_70_P_1 */
8325   {
8326     { VEX_W_TABLE (VEX_W_70_P_1) },
8327   },
8328
8329   /* VEX_LEN_70_P_2 */
8330   {
8331     { VEX_W_TABLE (VEX_W_70_P_2) },
8332   },
8333
8334   /* VEX_LEN_70_P_3 */
8335   {
8336     { VEX_W_TABLE (VEX_W_70_P_3) },
8337   },
8338
8339   /* VEX_LEN_71_R_2_P_2 */
8340   {
8341     { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
8342   },
8343
8344   /* VEX_LEN_71_R_4_P_2 */
8345   {
8346     { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
8347   },
8348
8349   /* VEX_LEN_71_R_6_P_2 */
8350   {
8351     { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
8352   },
8353
8354   /* VEX_LEN_72_R_2_P_2 */
8355   {
8356     { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
8357   },
8358
8359   /* VEX_LEN_72_R_4_P_2 */
8360   {
8361     { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
8362   },
8363
8364   /* VEX_LEN_72_R_6_P_2 */
8365   {
8366     { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
8367   },
8368
8369   /* VEX_LEN_73_R_2_P_2 */
8370   {
8371     { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
8372   },
8373
8374   /* VEX_LEN_73_R_3_P_2 */
8375   {
8376     { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
8377   },
8378
8379   /* VEX_LEN_73_R_6_P_2 */
8380   {
8381     { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
8382   },
8383
8384   /* VEX_LEN_73_R_7_P_2 */
8385   {
8386     { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
8387   },
8388
8389   /* VEX_LEN_74_P_2 */
8390   {
8391     { VEX_W_TABLE (VEX_W_74_P_2) },
8392   },
8393
8394   /* VEX_LEN_75_P_2 */
8395   {
8396     { VEX_W_TABLE (VEX_W_75_P_2) },
8397   },
8398
8399   /* VEX_LEN_76_P_2 */
8400   {
8401     { VEX_W_TABLE (VEX_W_76_P_2) },
8402   },
8403
8404   /* VEX_LEN_7E_P_1 */
8405   {
8406     { VEX_W_TABLE (VEX_W_7E_P_1) },
8407   },
8408
8409   /* VEX_LEN_7E_P_2 */
8410   {
8411     { "vmovK",          { Edq, XM } },
8412   },
8413
8414   /* VEX_LEN_AE_R_2_M_0 */
8415   {
8416     { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
8417   },
8418
8419   /* VEX_LEN_AE_R_3_M_0 */
8420   {
8421     { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
8422   },
8423
8424   /* VEX_LEN_C2_P_1 */
8425   {
8426     { VEX_W_TABLE (VEX_W_C2_P_1) },
8427   },
8428
8429   /* VEX_LEN_C2_P_3 */
8430   {
8431     { VEX_W_TABLE (VEX_W_C2_P_3) },
8432   },
8433
8434   /* VEX_LEN_C4_P_2 */
8435   {
8436     { VEX_W_TABLE (VEX_W_C4_P_2) },
8437   },
8438
8439   /* VEX_LEN_C5_P_2 */
8440   {
8441     { VEX_W_TABLE (VEX_W_C5_P_2) },
8442   },
8443
8444   /* VEX_LEN_D1_P_2 */
8445   {
8446     { VEX_W_TABLE (VEX_W_D1_P_2) },
8447   },
8448
8449   /* VEX_LEN_D2_P_2 */
8450   {
8451     { VEX_W_TABLE (VEX_W_D2_P_2) },
8452   },
8453
8454   /* VEX_LEN_D3_P_2 */
8455   {
8456     { VEX_W_TABLE (VEX_W_D3_P_2) },
8457   },
8458
8459   /* VEX_LEN_D4_P_2 */
8460   {
8461     { VEX_W_TABLE (VEX_W_D4_P_2) },
8462   },
8463
8464   /* VEX_LEN_D5_P_2 */
8465   {
8466     { VEX_W_TABLE (VEX_W_D5_P_2) },
8467   },
8468
8469   /* VEX_LEN_D6_P_2 */
8470   {
8471     { VEX_W_TABLE (VEX_W_D6_P_2) },
8472   },
8473
8474   /* VEX_LEN_D7_P_2_M_1 */
8475   {
8476     { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
8477   },
8478
8479   /* VEX_LEN_D8_P_2 */
8480   {
8481     { VEX_W_TABLE (VEX_W_D8_P_2) },
8482   },
8483
8484   /* VEX_LEN_D9_P_2 */
8485   {
8486     { VEX_W_TABLE (VEX_W_D9_P_2) },
8487   },
8488
8489   /* VEX_LEN_DA_P_2 */
8490   {
8491     { VEX_W_TABLE (VEX_W_DA_P_2) },
8492   },
8493
8494   /* VEX_LEN_DB_P_2 */
8495   {
8496     { VEX_W_TABLE (VEX_W_DB_P_2) },
8497   },
8498
8499   /* VEX_LEN_DC_P_2 */
8500   {
8501     { VEX_W_TABLE (VEX_W_DC_P_2) },
8502   },
8503
8504   /* VEX_LEN_DD_P_2 */
8505   {
8506     { VEX_W_TABLE (VEX_W_DD_P_2) },
8507   },
8508
8509   /* VEX_LEN_DE_P_2 */
8510   {
8511     { VEX_W_TABLE (VEX_W_DE_P_2) },
8512   },
8513
8514   /* VEX_LEN_DF_P_2 */
8515   {
8516     { VEX_W_TABLE (VEX_W_DF_P_2) },
8517   },
8518
8519   /* VEX_LEN_E0_P_2 */
8520   {
8521     { VEX_W_TABLE (VEX_W_E0_P_2) },
8522   },
8523
8524   /* VEX_LEN_E1_P_2 */
8525   {
8526     { VEX_W_TABLE (VEX_W_E1_P_2) },
8527   },
8528
8529   /* VEX_LEN_E2_P_2 */
8530   {
8531     { VEX_W_TABLE (VEX_W_E2_P_2) },
8532   },
8533
8534   /* VEX_LEN_E3_P_2 */
8535   {
8536     { VEX_W_TABLE (VEX_W_E3_P_2) },
8537   },
8538
8539   /* VEX_LEN_E4_P_2 */
8540   {
8541     { VEX_W_TABLE (VEX_W_E4_P_2) },
8542   },
8543
8544   /* VEX_LEN_E5_P_2 */
8545   {
8546     { VEX_W_TABLE (VEX_W_E5_P_2) },
8547   },
8548
8549   /* VEX_LEN_E8_P_2 */
8550   {
8551     { VEX_W_TABLE (VEX_W_E8_P_2) },
8552   },
8553
8554   /* VEX_LEN_E9_P_2 */
8555   {
8556     { VEX_W_TABLE (VEX_W_E9_P_2) },
8557   },
8558
8559   /* VEX_LEN_EA_P_2 */
8560   {
8561     { VEX_W_TABLE (VEX_W_EA_P_2) },
8562   },
8563
8564   /* VEX_LEN_EB_P_2 */
8565   {
8566     { VEX_W_TABLE (VEX_W_EB_P_2) },
8567   },
8568
8569   /* VEX_LEN_EC_P_2 */
8570   {
8571     { VEX_W_TABLE (VEX_W_EC_P_2) },
8572   },
8573
8574   /* VEX_LEN_ED_P_2 */
8575   {
8576     { VEX_W_TABLE (VEX_W_ED_P_2) },
8577   },
8578
8579   /* VEX_LEN_EE_P_2 */
8580   {
8581     { VEX_W_TABLE (VEX_W_EE_P_2) },
8582   },
8583
8584   /* VEX_LEN_EF_P_2 */
8585   {
8586     { VEX_W_TABLE (VEX_W_EF_P_2) },
8587   },
8588
8589   /* VEX_LEN_F1_P_2 */
8590   {
8591     { VEX_W_TABLE (VEX_W_F1_P_2) },
8592   },
8593
8594   /* VEX_LEN_F2_P_2 */
8595   {
8596     { VEX_W_TABLE (VEX_W_F2_P_2) },
8597     { Bad_Opcode },
8598   },
8599
8600   /* VEX_LEN_F3_P_2 */
8601   {
8602     { VEX_W_TABLE (VEX_W_F3_P_2) },
8603   },
8604
8605   /* VEX_LEN_F4_P_2 */
8606   {
8607     { VEX_W_TABLE (VEX_W_F4_P_2) },
8608   },
8609
8610   /* VEX_LEN_F5_P_2 */
8611   {
8612     { VEX_W_TABLE (VEX_W_F5_P_2) },
8613   },
8614
8615   /* VEX_LEN_F6_P_2 */
8616   {
8617     { VEX_W_TABLE (VEX_W_F6_P_2) },
8618   },
8619
8620   /* VEX_LEN_F7_P_2 */
8621   {
8622     { VEX_W_TABLE (VEX_W_F7_P_2) },
8623   },
8624
8625   /* VEX_LEN_F8_P_2 */
8626   {
8627     { VEX_W_TABLE (VEX_W_F8_P_2) },
8628   },
8629
8630   /* VEX_LEN_F9_P_2 */
8631   {
8632     { VEX_W_TABLE (VEX_W_F9_P_2) },
8633   },
8634
8635   /* VEX_LEN_FA_P_2 */
8636   {
8637     { VEX_W_TABLE (VEX_W_FA_P_2) },
8638   },
8639
8640   /* VEX_LEN_FB_P_2 */
8641   {
8642     { VEX_W_TABLE (VEX_W_FB_P_2) },
8643   },
8644
8645   /* VEX_LEN_FC_P_2 */
8646   {
8647     { VEX_W_TABLE (VEX_W_FC_P_2) },
8648   },
8649
8650   /* VEX_LEN_FD_P_2 */
8651   {
8652     { VEX_W_TABLE (VEX_W_FD_P_2) },
8653   },
8654
8655   /* VEX_LEN_FE_P_2 */
8656   {
8657     { VEX_W_TABLE (VEX_W_FE_P_2) },
8658   },
8659
8660   /* VEX_LEN_3800_P_2 */
8661   {
8662     { VEX_W_TABLE (VEX_W_3800_P_2) },
8663   },
8664
8665   /* VEX_LEN_3801_P_2 */
8666   {
8667     { VEX_W_TABLE (VEX_W_3801_P_2) },
8668   },
8669
8670   /* VEX_LEN_3802_P_2 */
8671   {
8672     { VEX_W_TABLE (VEX_W_3802_P_2) },
8673   },
8674
8675   /* VEX_LEN_3803_P_2 */
8676   {
8677     { VEX_W_TABLE (VEX_W_3803_P_2) },
8678   },
8679
8680   /* VEX_LEN_3804_P_2 */
8681   {
8682     { VEX_W_TABLE (VEX_W_3804_P_2) },
8683   },
8684
8685   /* VEX_LEN_3805_P_2 */
8686   {
8687     { VEX_W_TABLE (VEX_W_3805_P_2) },
8688   },
8689
8690   /* VEX_LEN_3806_P_2 */
8691   {
8692     { VEX_W_TABLE (VEX_W_3806_P_2) },
8693   },
8694
8695   /* VEX_LEN_3807_P_2 */
8696   {
8697     { VEX_W_TABLE (VEX_W_3807_P_2) },
8698   },
8699
8700   /* VEX_LEN_3808_P_2 */
8701   {
8702     { VEX_W_TABLE (VEX_W_3808_P_2) },
8703   },
8704
8705   /* VEX_LEN_3809_P_2 */
8706   {
8707     { VEX_W_TABLE (VEX_W_3809_P_2) },
8708   },
8709
8710   /* VEX_LEN_380A_P_2 */
8711   {
8712     { VEX_W_TABLE (VEX_W_380A_P_2) },
8713   },
8714
8715   /* VEX_LEN_380B_P_2 */
8716   {
8717     { VEX_W_TABLE (VEX_W_380B_P_2) },
8718   },
8719
8720   /* VEX_LEN_3819_P_2_M_0 */
8721   {
8722     { Bad_Opcode },
8723     { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
8724   },
8725
8726   /* VEX_LEN_381A_P_2_M_0 */
8727   {
8728     { Bad_Opcode },
8729     { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
8730   },
8731
8732   /* VEX_LEN_381C_P_2 */
8733   {
8734     { VEX_W_TABLE (VEX_W_381C_P_2) },
8735   },
8736
8737   /* VEX_LEN_381D_P_2 */
8738   {
8739     { VEX_W_TABLE (VEX_W_381D_P_2) },
8740   },
8741
8742   /* VEX_LEN_381E_P_2 */
8743   {
8744     { VEX_W_TABLE (VEX_W_381E_P_2) },
8745   },
8746
8747   /* VEX_LEN_3820_P_2 */
8748   {
8749     { VEX_W_TABLE (VEX_W_3820_P_2) },
8750   },
8751
8752   /* VEX_LEN_3821_P_2 */
8753   {
8754     { VEX_W_TABLE (VEX_W_3821_P_2) },
8755   },
8756
8757   /* VEX_LEN_3822_P_2 */
8758   {
8759     { VEX_W_TABLE (VEX_W_3822_P_2) },
8760   },
8761
8762   /* VEX_LEN_3823_P_2 */
8763   {
8764     { VEX_W_TABLE (VEX_W_3823_P_2) },
8765   },
8766
8767   /* VEX_LEN_3824_P_2 */
8768   {
8769     { VEX_W_TABLE (VEX_W_3824_P_2) },
8770   },
8771
8772   /* VEX_LEN_3825_P_2 */
8773   {
8774     { VEX_W_TABLE (VEX_W_3825_P_2) },
8775   },
8776
8777   /* VEX_LEN_3828_P_2 */
8778   {
8779     { VEX_W_TABLE (VEX_W_3828_P_2) },
8780   },
8781
8782   /* VEX_LEN_3829_P_2 */
8783   {
8784     { VEX_W_TABLE (VEX_W_3829_P_2) },
8785   },
8786
8787   /* VEX_LEN_382A_P_2_M_0 */
8788   {
8789     { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
8790   },
8791
8792   /* VEX_LEN_382B_P_2 */
8793   {
8794     { VEX_W_TABLE (VEX_W_382B_P_2) },
8795   },
8796
8797   /* VEX_LEN_3830_P_2 */
8798   {
8799     { VEX_W_TABLE (VEX_W_3830_P_2) },
8800   },
8801
8802   /* VEX_LEN_3831_P_2 */
8803   {
8804     { VEX_W_TABLE (VEX_W_3831_P_2) },
8805   },
8806
8807   /* VEX_LEN_3832_P_2 */
8808   {
8809     { VEX_W_TABLE (VEX_W_3832_P_2) },
8810   },
8811
8812   /* VEX_LEN_3833_P_2 */
8813   {
8814     { VEX_W_TABLE (VEX_W_3833_P_2) },
8815   },
8816
8817   /* VEX_LEN_3834_P_2 */
8818   {
8819     { VEX_W_TABLE (VEX_W_3834_P_2) },
8820   },
8821
8822   /* VEX_LEN_3835_P_2 */
8823   {
8824     { VEX_W_TABLE (VEX_W_3835_P_2) },
8825   },
8826
8827   /* VEX_LEN_3837_P_2 */
8828   {
8829     { VEX_W_TABLE (VEX_W_3837_P_2) },
8830   },
8831
8832   /* VEX_LEN_3838_P_2 */
8833   {
8834     { VEX_W_TABLE (VEX_W_3838_P_2) },
8835   },
8836
8837   /* VEX_LEN_3839_P_2 */
8838   {
8839     { VEX_W_TABLE (VEX_W_3839_P_2) },
8840   },
8841
8842   /* VEX_LEN_383A_P_2 */
8843   {
8844     { VEX_W_TABLE (VEX_W_383A_P_2) },
8845   },
8846
8847   /* VEX_LEN_383B_P_2 */
8848   {
8849     { VEX_W_TABLE (VEX_W_383B_P_2) },
8850   },
8851
8852   /* VEX_LEN_383C_P_2 */
8853   {
8854     { VEX_W_TABLE (VEX_W_383C_P_2) },
8855   },
8856
8857   /* VEX_LEN_383D_P_2 */
8858   {
8859     { VEX_W_TABLE (VEX_W_383D_P_2) },
8860   },
8861
8862   /* VEX_LEN_383E_P_2 */
8863   {
8864     { VEX_W_TABLE (VEX_W_383E_P_2) },
8865   },
8866
8867   /* VEX_LEN_383F_P_2 */
8868   {
8869     { VEX_W_TABLE (VEX_W_383F_P_2) },
8870   },
8871
8872   /* VEX_LEN_3840_P_2 */
8873   {
8874     { VEX_W_TABLE (VEX_W_3840_P_2) },
8875   },
8876
8877   /* VEX_LEN_3841_P_2 */
8878   {
8879     { VEX_W_TABLE (VEX_W_3841_P_2) },
8880   },
8881
8882   /* VEX_LEN_38DB_P_2 */
8883   {
8884     { VEX_W_TABLE (VEX_W_38DB_P_2) },
8885   },
8886
8887   /* VEX_LEN_38DC_P_2 */
8888   {
8889     { VEX_W_TABLE (VEX_W_38DC_P_2) },
8890   },
8891
8892   /* VEX_LEN_38DD_P_2 */
8893   {
8894     { VEX_W_TABLE (VEX_W_38DD_P_2) },
8895   },
8896
8897   /* VEX_LEN_38DE_P_2 */
8898   {
8899     { VEX_W_TABLE (VEX_W_38DE_P_2) },
8900   },
8901
8902   /* VEX_LEN_38DF_P_2 */
8903   {
8904     { VEX_W_TABLE (VEX_W_38DF_P_2) },
8905   },
8906
8907   /* VEX_LEN_3A06_P_2 */
8908   {
8909     { Bad_Opcode },
8910     { VEX_W_TABLE (VEX_W_3A06_P_2) },
8911   },
8912
8913   /* VEX_LEN_3A0A_P_2 */
8914   {
8915     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8916   },
8917
8918   /* VEX_LEN_3A0B_P_2 */
8919   {
8920     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
8921   },
8922
8923   /* VEX_LEN_3A0E_P_2 */
8924   {
8925     { VEX_W_TABLE (VEX_W_3A0E_P_2) },
8926   },
8927
8928   /* VEX_LEN_3A0F_P_2 */
8929   {
8930     { VEX_W_TABLE (VEX_W_3A0F_P_2) },
8931   },
8932
8933   /* VEX_LEN_3A14_P_2 */
8934   {
8935     { VEX_W_TABLE (VEX_W_3A14_P_2) },
8936   },
8937
8938   /* VEX_LEN_3A15_P_2 */
8939   {
8940     { VEX_W_TABLE (VEX_W_3A15_P_2) },
8941   },
8942
8943   /* VEX_LEN_3A16_P_2  */
8944   {
8945     { "vpextrK",        { Edq, XM, Ib } },
8946   },
8947
8948   /* VEX_LEN_3A17_P_2 */
8949   {
8950     { "vextractps",     { Edqd, XM, Ib } },
8951   },
8952
8953   /* VEX_LEN_3A18_P_2 */
8954   {
8955     { Bad_Opcode },
8956     { VEX_W_TABLE (VEX_W_3A18_P_2) },
8957   },
8958
8959   /* VEX_LEN_3A19_P_2 */
8960   {
8961     { Bad_Opcode },
8962     { VEX_W_TABLE (VEX_W_3A19_P_2) },
8963   },
8964
8965   /* VEX_LEN_3A20_P_2 */
8966   {
8967     { VEX_W_TABLE (VEX_W_3A20_P_2) },
8968   },
8969
8970   /* VEX_LEN_3A21_P_2 */
8971   {
8972     { VEX_W_TABLE (VEX_W_3A21_P_2) },
8973   },
8974
8975   /* VEX_LEN_3A22_P_2 */
8976   {
8977     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8978   },
8979
8980   /* VEX_LEN_3A41_P_2 */
8981   {
8982     { VEX_W_TABLE (VEX_W_3A41_P_2) },
8983   },
8984
8985   /* VEX_LEN_3A42_P_2 */
8986   {
8987     { VEX_W_TABLE (VEX_W_3A42_P_2) },
8988   },
8989
8990   /* VEX_LEN_3A44_P_2 */
8991   {
8992     { VEX_W_TABLE (VEX_W_3A44_P_2) },
8993   },
8994
8995   /* VEX_LEN_3A4C_P_2 */
8996   {
8997     { VEX_W_TABLE (VEX_W_3A4C_P_2) },
8998   },
8999
9000   /* VEX_LEN_3A60_P_2 */
9001   {
9002     { VEX_W_TABLE (VEX_W_3A60_P_2) },
9003   },
9004
9005   /* VEX_LEN_3A61_P_2 */
9006   {
9007     { VEX_W_TABLE (VEX_W_3A61_P_2) },
9008   },
9009
9010   /* VEX_LEN_3A62_P_2 */
9011   {
9012     { VEX_W_TABLE (VEX_W_3A62_P_2) },
9013   },
9014
9015   /* VEX_LEN_3A63_P_2 */
9016   {
9017     { VEX_W_TABLE (VEX_W_3A63_P_2) },
9018   },
9019
9020   /* VEX_LEN_3A6A_P_2 */
9021   {
9022     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9023   },
9024
9025   /* VEX_LEN_3A6B_P_2 */
9026   {
9027     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9028   },
9029
9030   /* VEX_LEN_3A6E_P_2 */
9031   {
9032     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9033   },
9034
9035   /* VEX_LEN_3A6F_P_2 */
9036   {
9037     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9038   },
9039
9040   /* VEX_LEN_3A7A_P_2 */
9041   {
9042     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9043   },
9044
9045   /* VEX_LEN_3A7B_P_2 */
9046   {
9047     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9048   },
9049
9050   /* VEX_LEN_3A7E_P_2 */
9051   {
9052     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9053   },
9054
9055   /* VEX_LEN_3A7F_P_2 */
9056   {
9057     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9058   },
9059
9060   /* VEX_LEN_3ADF_P_2 */
9061   {
9062     { VEX_W_TABLE (VEX_W_3ADF_P_2) },
9063   },
9064
9065   /* VEX_LEN_XOP_09_80 */
9066   {
9067     { "vfrczps",        { XM, EXxmm } },
9068     { "vfrczps",        { XM, EXymmq } },
9069   },
9070
9071   /* VEX_LEN_XOP_09_81 */
9072   {
9073     { "vfrczpd",        { XM, EXxmm } },
9074     { "vfrczpd",        { XM, EXymmq } },
9075   },
9076 };
9077
9078 static const struct dis386 vex_w_table[][2] = {
9079   {
9080     /* VEX_W_10_P_0 */
9081     { "vmovups",        { XM, EXx } },
9082   },
9083   {
9084     /* VEX_W_10_P_1 */
9085     { "vmovss",         { XMVex, Vex128, EXd } },
9086   },
9087   {
9088     /* VEX_W_10_P_2 */
9089     { "vmovupd",        { XM, EXx } },
9090   },
9091   {
9092     /* VEX_W_10_P_3 */
9093     { "vmovsd",         { XMVex, Vex128, EXq } },
9094   },
9095   {
9096     /* VEX_W_11_P_0 */
9097     { "vmovups",        { EXxS, XM } },
9098   },
9099   {
9100     /* VEX_W_11_P_1 */
9101     { "vmovss",         { EXdVexS, Vex128, XM } },
9102   },
9103   {
9104     /* VEX_W_11_P_2 */
9105     { "vmovupd",        { EXxS, XM } },
9106   },
9107   {
9108     /* VEX_W_11_P_3 */
9109     { "vmovsd",         { EXqVexS, Vex128, XM } },
9110   },
9111   {
9112     /* VEX_W_12_P_0_M_0 */
9113     { "vmovlps",        { XM, Vex128, EXq } },
9114   },
9115   {
9116     /* VEX_W_12_P_0_M_1 */
9117     { "vmovhlps",       { XM, Vex128, EXq } },
9118   },
9119   {
9120     /* VEX_W_12_P_1 */
9121     { "vmovsldup",      { XM, EXx } },
9122   },
9123   {
9124     /* VEX_W_12_P_2 */
9125     { "vmovlpd",        { XM, Vex128, EXq } },
9126   },
9127   {
9128     /* VEX_W_12_P_3 */
9129     { "vmovddup",       { XM, EXymmq } },
9130   },
9131   {
9132     /* VEX_W_13_M_0 */
9133     { "vmovlpX",        { EXq, XM } },
9134   },
9135   {
9136     /* VEX_W_14 */
9137     { "vunpcklpX",      { XM, Vex, EXx } },
9138   },
9139   {
9140     /* VEX_W_15 */
9141     { "vunpckhpX",      { XM, Vex, EXx } },
9142   },
9143   {
9144     /* VEX_W_16_P_0_M_0 */
9145     { "vmovhps",        { XM, Vex128, EXq } },
9146   },
9147   {
9148     /* VEX_W_16_P_0_M_1 */
9149     { "vmovlhps",       { XM, Vex128, EXq } },
9150   },
9151   {
9152     /* VEX_W_16_P_1 */
9153     { "vmovshdup",      { XM, EXx } },
9154   },
9155   {
9156     /* VEX_W_16_P_2 */
9157     { "vmovhpd",        { XM, Vex128, EXq } },
9158   },
9159   {
9160     /* VEX_W_17_M_0 */
9161     { "vmovhpX",        { EXq, XM } },
9162   },
9163   {
9164     /* VEX_W_28 */
9165     { "vmovapX",        { XM, EXx } },
9166   },
9167   {
9168     /* VEX_W_29 */
9169     { "vmovapX",        { EXxS, XM } },
9170   },
9171   {
9172     /* VEX_W_2B_M_0 */
9173     { "vmovntpX",       { Mx, XM } },
9174   },
9175   {
9176     /* VEX_W_2E_P_0 */
9177     { "vucomiss",       { XM, EXd } },
9178   },
9179   {
9180     /* VEX_W_2E_P_2 */
9181     { "vucomisd",       { XM, EXq } },
9182   },
9183   {
9184     /* VEX_W_2F_P_0 */
9185     { "vcomiss",        { XM, EXd } },
9186   },
9187   {
9188     /* VEX_W_2F_P_2 */
9189     { "vcomisd",        { XM, EXq } },
9190   },
9191   {
9192     /* VEX_W_50_M_0 */
9193     { "vmovmskpX",      { Gdq, XS } },
9194   },
9195   {
9196     /* VEX_W_51_P_0 */
9197     { "vsqrtps",        { XM, EXx } },
9198   },
9199   {
9200     /* VEX_W_51_P_1 */
9201     { "vsqrtss",        { XM, Vex128, EXd } },
9202   },
9203   {
9204     /* VEX_W_51_P_2  */
9205     { "vsqrtpd",        { XM, EXx } },
9206   },
9207   {
9208     /* VEX_W_51_P_3 */
9209     { "vsqrtsd",        { XM, Vex128, EXq } },
9210   },
9211   {
9212     /* VEX_W_52_P_0 */
9213     { "vrsqrtps",       { XM, EXx } },
9214   },
9215   {
9216     /* VEX_W_52_P_1 */
9217     { "vrsqrtss",       { XM, Vex128, EXd } },
9218   },
9219   {
9220     /* VEX_W_53_P_0  */
9221     { "vrcpps",         { XM, EXx } },
9222   },
9223   {
9224     /* VEX_W_53_P_1  */
9225     { "vrcpss",         { XM, Vex128, EXd } },
9226   },
9227   {
9228     /* VEX_W_58_P_0  */
9229     { "vaddps",         { XM, Vex, EXx } },
9230   },
9231   {
9232     /* VEX_W_58_P_1  */
9233     { "vaddss",         { XM, Vex128, EXd } },
9234   },
9235   {
9236     /* VEX_W_58_P_2  */
9237     { "vaddpd",         { XM, Vex, EXx } },
9238   },
9239   {
9240     /* VEX_W_58_P_3  */
9241     { "vaddsd",         { XM, Vex128, EXq } },
9242   },
9243   {
9244     /* VEX_W_59_P_0  */
9245     { "vmulps",         { XM, Vex, EXx } },
9246   },
9247   {
9248     /* VEX_W_59_P_1  */
9249     { "vmulss",         { XM, Vex128, EXd } },
9250   },
9251   {
9252     /* VEX_W_59_P_2  */
9253     { "vmulpd",         { XM, Vex, EXx } },
9254   },
9255   {
9256     /* VEX_W_59_P_3  */
9257     { "vmulsd",         { XM, Vex128, EXq } },
9258   },
9259   {
9260     /* VEX_W_5A_P_0  */
9261     { "vcvtps2pd",      { XM, EXxmmq } },
9262   },
9263   {
9264     /* VEX_W_5A_P_1  */
9265     { "vcvtss2sd",      { XM, Vex128, EXd } },
9266   },
9267   {
9268     /* VEX_W_5A_P_3  */
9269     { "vcvtsd2ss",      { XM, Vex128, EXq } },
9270   },
9271   {
9272     /* VEX_W_5B_P_0  */
9273     { "vcvtdq2ps",      { XM, EXx } },
9274   },
9275   {
9276     /* VEX_W_5B_P_1  */
9277     { "vcvttps2dq",     { XM, EXx } },
9278   },
9279   {
9280     /* VEX_W_5B_P_2  */
9281     { "vcvtps2dq",      { XM, EXx } },
9282   },
9283   {
9284     /* VEX_W_5C_P_0  */
9285     { "vsubps",         { XM, Vex, EXx } },
9286   },
9287   {
9288     /* VEX_W_5C_P_1  */
9289     { "vsubss",         { XM, Vex128, EXd } },
9290   },
9291   {
9292     /* VEX_W_5C_P_2  */
9293     { "vsubpd",         { XM, Vex, EXx } },
9294   },
9295   {
9296     /* VEX_W_5C_P_3  */
9297     { "vsubsd",         { XM, Vex128, EXq } },
9298   },
9299   {
9300     /* VEX_W_5D_P_0  */
9301     { "vminps",         { XM, Vex, EXx } },
9302   },
9303   {
9304     /* VEX_W_5D_P_1  */
9305     { "vminss",         { XM, Vex128, EXd } },
9306   },
9307   {
9308     /* VEX_W_5D_P_2  */
9309     { "vminpd",         { XM, Vex, EXx } },
9310   },
9311   {
9312     /* VEX_W_5D_P_3  */
9313     { "vminsd",         { XM, Vex128, EXq } },
9314   },
9315   {
9316     /* VEX_W_5E_P_0  */
9317     { "vdivps",         { XM, Vex, EXx } },
9318   },
9319   {
9320     /* VEX_W_5E_P_1  */
9321     { "vdivss",         { XM, Vex128, EXd } },
9322   },
9323   {
9324     /* VEX_W_5E_P_2  */
9325     { "vdivpd",         { XM, Vex, EXx } },
9326   },
9327   {
9328     /* VEX_W_5E_P_3  */
9329     { "vdivsd",         { XM, Vex128, EXq } },
9330   },
9331   {
9332     /* VEX_W_5F_P_0  */
9333     { "vmaxps",         { XM, Vex, EXx } },
9334   },
9335   {
9336     /* VEX_W_5F_P_1  */
9337     { "vmaxss",         { XM, Vex128, EXd } },
9338   },
9339   {
9340     /* VEX_W_5F_P_2  */
9341     { "vmaxpd",         { XM, Vex, EXx } },
9342   },
9343   {
9344     /* VEX_W_5F_P_3  */
9345     { "vmaxsd",         { XM, Vex128, EXq } },
9346   },
9347   {
9348     /* VEX_W_60_P_2  */
9349     { "vpunpcklbw",     { XM, Vex128, EXx } },
9350   },
9351   {
9352     /* VEX_W_61_P_2  */
9353     { "vpunpcklwd",     { XM, Vex128, EXx } },
9354   },
9355   {
9356     /* VEX_W_62_P_2  */
9357     { "vpunpckldq",     { XM, Vex128, EXx } },
9358   },
9359   {
9360     /* VEX_W_63_P_2  */
9361     { "vpacksswb",      { XM, Vex128, EXx } },
9362   },
9363   {
9364     /* VEX_W_64_P_2  */
9365     { "vpcmpgtb",       { XM, Vex128, EXx } },
9366   },
9367   {
9368     /* VEX_W_65_P_2  */
9369     { "vpcmpgtw",       { XM, Vex128, EXx } },
9370   },
9371   {
9372     /* VEX_W_66_P_2  */
9373     { "vpcmpgtd",       { XM, Vex128, EXx } },
9374   },
9375   {
9376     /* VEX_W_67_P_2  */
9377     { "vpackuswb",      { XM, Vex128, EXx } },
9378   },
9379   {
9380     /* VEX_W_68_P_2  */
9381     { "vpunpckhbw",     { XM, Vex128, EXx } },
9382   },
9383   {
9384     /* VEX_W_69_P_2  */
9385     { "vpunpckhwd",     { XM, Vex128, EXx } },
9386   },
9387   {
9388     /* VEX_W_6A_P_2  */
9389     { "vpunpckhdq",     { XM, Vex128, EXx } },
9390   },
9391   {
9392     /* VEX_W_6B_P_2  */
9393     { "vpackssdw",      { XM, Vex128, EXx } },
9394   },
9395   {
9396     /* VEX_W_6C_P_2  */
9397     { "vpunpcklqdq",    { XM, Vex128, EXx } },
9398   },
9399   {
9400     /* VEX_W_6D_P_2  */
9401     { "vpunpckhqdq",    { XM, Vex128, EXx } },
9402   },
9403   {
9404     /* VEX_W_6F_P_1  */
9405     { "vmovdqu",        { XM, EXx } },
9406   },
9407   {
9408     /* VEX_W_6F_P_2  */
9409     { "vmovdqa",        { XM, EXx } },
9410   },
9411   {
9412     /* VEX_W_70_P_1 */
9413     { "vpshufhw",       { XM, EXx, Ib } },
9414   },
9415   {
9416     /* VEX_W_70_P_2 */
9417     { "vpshufd",        { XM, EXx, Ib } },
9418   },
9419   {
9420     /* VEX_W_70_P_3 */
9421     { "vpshuflw",       { XM, EXx, Ib } },
9422   },
9423   {
9424     /* VEX_W_71_R_2_P_2  */
9425     { "vpsrlw",         { Vex128, XS, Ib } },
9426   },
9427   {
9428     /* VEX_W_71_R_4_P_2  */
9429     { "vpsraw",         { Vex128, XS, Ib } },
9430   },
9431   {
9432     /* VEX_W_71_R_6_P_2  */
9433     { "vpsllw",         { Vex128, XS, Ib } },
9434   },
9435   {
9436     /* VEX_W_72_R_2_P_2  */
9437     { "vpsrld",         { Vex128, XS, Ib } },
9438   },
9439   {
9440     /* VEX_W_72_R_4_P_2  */
9441     { "vpsrad",         { Vex128, XS, Ib } },
9442   },
9443   {
9444     /* VEX_W_72_R_6_P_2  */
9445     { "vpslld",         { Vex128, XS, Ib } },
9446   },
9447   {
9448     /* VEX_W_73_R_2_P_2  */
9449     { "vpsrlq",         { Vex128, XS, Ib } },
9450   },
9451   {
9452     /* VEX_W_73_R_3_P_2  */
9453     { "vpsrldq",        { Vex128, XS, Ib } },
9454   },
9455   {
9456     /* VEX_W_73_R_6_P_2  */
9457     { "vpsllq",         { Vex128, XS, Ib } },
9458   },
9459   {
9460     /* VEX_W_73_R_7_P_2  */
9461     { "vpslldq",        { Vex128, XS, Ib } },
9462   },
9463   {
9464     /* VEX_W_74_P_2 */
9465     { "vpcmpeqb",       { XM, Vex128, EXx } },
9466   },
9467   {
9468     /* VEX_W_75_P_2 */
9469     { "vpcmpeqw",       { XM, Vex128, EXx } },
9470   },
9471   {
9472     /* VEX_W_76_P_2 */
9473     { "vpcmpeqd",       { XM, Vex128, EXx } },
9474   },
9475   {
9476     /* VEX_W_77_P_0 */
9477     { "",               { VZERO } },
9478   },
9479   {
9480     /* VEX_W_7C_P_2 */
9481     { "vhaddpd",        { XM, Vex, EXx } },
9482   },
9483   {
9484     /* VEX_W_7C_P_3 */
9485     { "vhaddps",        { XM, Vex, EXx } },
9486   },
9487   {
9488     /* VEX_W_7D_P_2 */
9489     { "vhsubpd",        { XM, Vex, EXx } },
9490   },
9491   {
9492     /* VEX_W_7D_P_3 */
9493     { "vhsubps",        { XM, Vex, EXx } },
9494   },
9495   {
9496     /* VEX_W_7E_P_1 */
9497     { "vmovq",          { XM, EXq } },
9498   },
9499   {
9500     /* VEX_W_7F_P_1 */
9501     { "vmovdqu",        { EXxS, XM } },
9502   },
9503   {
9504     /* VEX_W_7F_P_2 */
9505     { "vmovdqa",        { EXxS, XM } },
9506   },
9507   {
9508     /* VEX_W_AE_R_2_M_0 */
9509     { "vldmxcsr",       { Md } },
9510   },
9511   {
9512     /* VEX_W_AE_R_3_M_0 */
9513     { "vstmxcsr",       { Md } },
9514   },
9515   {
9516     /* VEX_W_C2_P_0 */
9517     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9518   },
9519   {
9520     /* VEX_W_C2_P_1 */
9521     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
9522   },
9523   {
9524     /* VEX_W_C2_P_2 */
9525     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9526   },
9527   {
9528     /* VEX_W_C2_P_3 */
9529     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
9530   },
9531   {
9532     /* VEX_W_C4_P_2 */
9533     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9534   },
9535   {
9536     /* VEX_W_C5_P_2 */
9537     { "vpextrw",        { Gdq, XS, Ib } },
9538   },
9539   {
9540     /* VEX_W_D0_P_2 */
9541     { "vaddsubpd",      { XM, Vex, EXx } },
9542   },
9543   {
9544     /* VEX_W_D0_P_3 */
9545     { "vaddsubps",      { XM, Vex, EXx } },
9546   },
9547   {
9548     /* VEX_W_D1_P_2 */
9549     { "vpsrlw",         { XM, Vex128, EXx } },
9550   },
9551   {
9552     /* VEX_W_D2_P_2 */
9553     { "vpsrld",         { XM, Vex128, EXx } },
9554   },
9555   {
9556     /* VEX_W_D3_P_2 */
9557     { "vpsrlq",         { XM, Vex128, EXx } },
9558   },
9559   {
9560     /* VEX_W_D4_P_2 */
9561     { "vpaddq",         { XM, Vex128, EXx } },
9562   },
9563   {
9564     /* VEX_W_D5_P_2 */
9565     { "vpmullw",        { XM, Vex128, EXx } },
9566   },
9567   {
9568     /* VEX_W_D6_P_2 */
9569     { "vmovq",          { EXqS, XM } },
9570   },
9571   {
9572     /* VEX_W_D7_P_2_M_1 */
9573     { "vpmovmskb",      { Gdq, XS } },
9574   },
9575   {
9576     /* VEX_W_D8_P_2 */
9577     { "vpsubusb",       { XM, Vex128, EXx } },
9578   },
9579   {
9580     /* VEX_W_D9_P_2 */
9581     { "vpsubusw",       { XM, Vex128, EXx } },
9582   },
9583   {
9584     /* VEX_W_DA_P_2 */
9585     { "vpminub",        { XM, Vex128, EXx } },
9586   },
9587   {
9588     /* VEX_W_DB_P_2 */
9589     { "vpand",          { XM, Vex128, EXx } },
9590   },
9591   {
9592     /* VEX_W_DC_P_2 */
9593     { "vpaddusb",       { XM, Vex128, EXx } },
9594   },
9595   {
9596     /* VEX_W_DD_P_2 */
9597     { "vpaddusw",       { XM, Vex128, EXx } },
9598   },
9599   {
9600     /* VEX_W_DE_P_2 */
9601     { "vpmaxub",        { XM, Vex128, EXx } },
9602   },
9603   {
9604     /* VEX_W_DF_P_2 */
9605     { "vpandn",         { XM, Vex128, EXx } },
9606   },
9607   {
9608     /* VEX_W_E0_P_2  */
9609     { "vpavgb",         { XM, Vex128, EXx } },
9610   },
9611   {
9612     /* VEX_W_E1_P_2  */
9613     { "vpsraw",         { XM, Vex128, EXx } },
9614   },
9615   {
9616     /* VEX_W_E2_P_2  */
9617     { "vpsrad",         { XM, Vex128, EXx } },
9618   },
9619   {
9620     /* VEX_W_E3_P_2  */
9621     { "vpavgw",         { XM, Vex128, EXx } },
9622   },
9623   {
9624     /* VEX_W_E4_P_2  */
9625     { "vpmulhuw",       { XM, Vex128, EXx } },
9626   },
9627   {
9628     /* VEX_W_E5_P_2  */
9629     { "vpmulhw",        { XM, Vex128, EXx } },
9630   },
9631   {
9632     /* VEX_W_E6_P_1  */
9633     { "vcvtdq2pd",      { XM, EXxmmq } },
9634   },
9635   {
9636     /* VEX_W_E6_P_2  */
9637     { "vcvttpd2dq%XY",  { XMM, EXx } },
9638   },
9639   {
9640     /* VEX_W_E6_P_3  */
9641     { "vcvtpd2dq%XY",   { XMM, EXx } },
9642   },
9643   {
9644     /* VEX_W_E7_P_2_M_0 */
9645     { "vmovntdq",       { Mx, XM } },
9646   },
9647   {
9648     /* VEX_W_E8_P_2  */
9649     { "vpsubsb",        { XM, Vex128, EXx } },
9650   },
9651   {
9652     /* VEX_W_E9_P_2  */
9653     { "vpsubsw",        { XM, Vex128, EXx } },
9654   },
9655   {
9656     /* VEX_W_EA_P_2  */
9657     { "vpminsw",        { XM, Vex128, EXx } },
9658   },
9659   {
9660     /* VEX_W_EB_P_2  */
9661     { "vpor",           { XM, Vex128, EXx } },
9662   },
9663   {
9664     /* VEX_W_EC_P_2  */
9665     { "vpaddsb",        { XM, Vex128, EXx } },
9666   },
9667   {
9668     /* VEX_W_ED_P_2  */
9669     { "vpaddsw",        { XM, Vex128, EXx } },
9670   },
9671   {
9672     /* VEX_W_EE_P_2  */
9673     { "vpmaxsw",        { XM, Vex128, EXx } },
9674   },
9675   {
9676     /* VEX_W_EF_P_2  */
9677     { "vpxor",          { XM, Vex128, EXx } },
9678   },
9679   {
9680     /* VEX_W_F0_P_3_M_0 */
9681     { "vlddqu",         { XM, M } },
9682   },
9683   {
9684     /* VEX_W_F1_P_2 */
9685     { "vpsllw",         { XM, Vex128, EXx } },
9686   },
9687   {
9688     /* VEX_W_F2_P_2 */
9689     { "vpslld",         { XM, Vex128, EXx } },
9690   },
9691   {
9692     /* VEX_W_F3_P_2 */
9693     { "vpsllq",         { XM, Vex128, EXx } },
9694   },
9695   {
9696     /* VEX_W_F4_P_2 */
9697     { "vpmuludq",       { XM, Vex128, EXx } },
9698   },
9699   {
9700     /* VEX_W_F5_P_2 */
9701     { "vpmaddwd",       { XM, Vex128, EXx } },
9702   },
9703   {
9704     /* VEX_W_F6_P_2 */
9705     { "vpsadbw",        { XM, Vex128, EXx } },
9706   },
9707   {
9708     /* VEX_W_F7_P_2 */
9709     { "vmaskmovdqu",    { XM, XS } },
9710   },
9711   {
9712     /* VEX_W_F8_P_2 */
9713     { "vpsubb",         { XM, Vex128, EXx } },
9714   },
9715   {
9716     /* VEX_W_F9_P_2 */
9717     { "vpsubw",         { XM, Vex128, EXx } },
9718   },
9719   {
9720     /* VEX_W_FA_P_2 */
9721     { "vpsubd",         { XM, Vex128, EXx } },
9722   },
9723   {
9724     /* VEX_W_FB_P_2 */
9725     { "vpsubq",         { XM, Vex128, EXx } },
9726   },
9727   {
9728     /* VEX_W_FC_P_2 */
9729     { "vpaddb",         { XM, Vex128, EXx } },
9730   },
9731   {
9732     /* VEX_W_FD_P_2 */
9733     { "vpaddw",         { XM, Vex128, EXx } },
9734   },
9735   {
9736     /* VEX_W_FE_P_2 */
9737     { "vpaddd",         { XM, Vex128, EXx } },
9738   },
9739   {
9740     /* VEX_W_3800_P_2  */
9741     { "vpshufb",        { XM, Vex128, EXx } },
9742   },
9743   {
9744     /* VEX_W_3801_P_2  */
9745     { "vphaddw",        { XM, Vex128, EXx } },
9746   },
9747   {
9748     /* VEX_W_3802_P_2  */
9749     { "vphaddd",        { XM, Vex128, EXx } },
9750   },
9751   {
9752     /* VEX_W_3803_P_2  */
9753     { "vphaddsw",       { XM, Vex128, EXx } },
9754   },
9755   {
9756     /* VEX_W_3804_P_2  */
9757     { "vpmaddubsw",     { XM, Vex128, EXx } },
9758   },
9759   {
9760     /* VEX_W_3805_P_2  */
9761     { "vphsubw",        { XM, Vex128, EXx } },
9762   },
9763   {
9764     /* VEX_W_3806_P_2  */
9765     { "vphsubd",        { XM, Vex128, EXx } },
9766   },
9767   {
9768     /* VEX_W_3807_P_2  */
9769     { "vphsubsw",       { XM, Vex128, EXx } },
9770   },
9771   {
9772     /* VEX_W_3808_P_2  */
9773     { "vpsignb",        { XM, Vex128, EXx } },
9774   },
9775   {
9776     /* VEX_W_3809_P_2  */
9777     { "vpsignw",        { XM, Vex128, EXx } },
9778   },
9779   {
9780     /* VEX_W_380A_P_2  */
9781     { "vpsignd",        { XM, Vex128, EXx } },
9782   },
9783   {
9784     /* VEX_W_380B_P_2  */
9785     { "vpmulhrsw",      { XM, Vex128, EXx } },
9786   },
9787   {
9788     /* VEX_W_380C_P_2  */
9789     { "vpermilps",      { XM, Vex, EXx } },
9790   },
9791   {
9792     /* VEX_W_380D_P_2  */
9793     { "vpermilpd",      { XM, Vex, EXx } },
9794   },
9795   {
9796     /* VEX_W_380E_P_2  */
9797     { "vtestps",        { XM, EXx } },
9798   },
9799   {
9800     /* VEX_W_380F_P_2  */
9801     { "vtestpd",        { XM, EXx } },
9802   },
9803   {
9804     /* VEX_W_3817_P_2 */
9805     { "vptest",         { XM, EXx } },
9806   },
9807   {
9808     /* VEX_W_3818_P_2_M_0 */
9809     { "vbroadcastss",   { XM, Md } },
9810   },
9811   {
9812     /* VEX_W_3819_P_2_M_0 */
9813     { "vbroadcastsd",   { XM, Mq } },
9814   },
9815   {
9816     /* VEX_W_381A_P_2_M_0 */
9817     { "vbroadcastf128", { XM, Mxmm } },
9818   },
9819   {
9820     /* VEX_W_381C_P_2 */
9821     { "vpabsb",         { XM, EXx } },
9822   },
9823   {
9824     /* VEX_W_381D_P_2 */
9825     { "vpabsw",         { XM, EXx } },
9826   },
9827   {
9828     /* VEX_W_381E_P_2 */
9829     { "vpabsd",         { XM, EXx } },
9830   },
9831   {
9832     /* VEX_W_3820_P_2 */
9833     { "vpmovsxbw",      { XM, EXq } },
9834   },
9835   {
9836     /* VEX_W_3821_P_2 */
9837     { "vpmovsxbd",      { XM, EXd } },
9838   },
9839   {
9840     /* VEX_W_3822_P_2 */
9841     { "vpmovsxbq",      { XM, EXw } },
9842   },
9843   {
9844     /* VEX_W_3823_P_2 */
9845     { "vpmovsxwd",      { XM, EXq } },
9846   },
9847   {
9848     /* VEX_W_3824_P_2 */
9849     { "vpmovsxwq",      { XM, EXd } },
9850   },
9851   {
9852     /* VEX_W_3825_P_2 */
9853     { "vpmovsxdq",      { XM, EXq } },
9854   },
9855   {
9856     /* VEX_W_3828_P_2 */
9857     { "vpmuldq",        { XM, Vex128, EXx } },
9858   },
9859   {
9860     /* VEX_W_3829_P_2 */
9861     { "vpcmpeqq",       { XM, Vex128, EXx } },
9862   },
9863   {
9864     /* VEX_W_382A_P_2_M_0 */
9865     { "vmovntdqa",      { XM, Mx } },
9866   },
9867   {
9868     /* VEX_W_382B_P_2 */
9869     { "vpackusdw",      { XM, Vex128, EXx } },
9870   },
9871   {
9872     /* VEX_W_382C_P_2_M_0 */
9873     { "vmaskmovps",     { XM, Vex, Mx } },
9874   },
9875   {
9876     /* VEX_W_382D_P_2_M_0 */
9877     { "vmaskmovpd",     { XM, Vex, Mx } },
9878   },
9879   {
9880     /* VEX_W_382E_P_2_M_0 */
9881     { "vmaskmovps",     { Mx, Vex, XM } },
9882   },
9883   {
9884     /* VEX_W_382F_P_2_M_0 */
9885     { "vmaskmovpd",     { Mx, Vex, XM } },
9886   },
9887   {
9888     /* VEX_W_3830_P_2 */
9889     { "vpmovzxbw",      { XM, EXq } },
9890   },
9891   {
9892     /* VEX_W_3831_P_2 */
9893     { "vpmovzxbd",      { XM, EXd } },
9894   },
9895   {
9896     /* VEX_W_3832_P_2 */
9897     { "vpmovzxbq",      { XM, EXw } },
9898   },
9899   {
9900     /* VEX_W_3833_P_2 */
9901     { "vpmovzxwd",      { XM, EXq } },
9902   },
9903   {
9904     /* VEX_W_3834_P_2 */
9905     { "vpmovzxwq",      { XM, EXd } },
9906   },
9907   {
9908     /* VEX_W_3835_P_2 */
9909     { "vpmovzxdq",      { XM, EXq } },
9910   },
9911   {
9912     /* VEX_W_3837_P_2 */
9913     { "vpcmpgtq",       { XM, Vex128, EXx } },
9914   },
9915   {
9916     /* VEX_W_3838_P_2 */
9917     { "vpminsb",        { XM, Vex128, EXx } },
9918   },
9919   {
9920     /* VEX_W_3839_P_2 */
9921     { "vpminsd",        { XM, Vex128, EXx } },
9922   },
9923   {
9924     /* VEX_W_383A_P_2 */
9925     { "vpminuw",        { XM, Vex128, EXx } },
9926   },
9927   {
9928     /* VEX_W_383B_P_2 */
9929     { "vpminud",        { XM, Vex128, EXx } },
9930   },
9931   {
9932     /* VEX_W_383C_P_2 */
9933     { "vpmaxsb",        { XM, Vex128, EXx } },
9934   },
9935   {
9936     /* VEX_W_383D_P_2 */
9937     { "vpmaxsd",        { XM, Vex128, EXx } },
9938   },
9939   {
9940     /* VEX_W_383E_P_2 */
9941     { "vpmaxuw",        { XM, Vex128, EXx } },
9942   },
9943   {
9944     /* VEX_W_383F_P_2 */
9945     { "vpmaxud",        { XM, Vex128, EXx } },
9946   },
9947   {
9948     /* VEX_W_3840_P_2 */
9949     { "vpmulld",        { XM, Vex128, EXx } },
9950   },
9951   {
9952     /* VEX_W_3841_P_2 */
9953     { "vphminposuw",    { XM, EXx } },
9954   },
9955   {
9956     /* VEX_W_38DB_P_2 */
9957     { "vaesimc",        { XM, EXx } },
9958   },
9959   {
9960     /* VEX_W_38DC_P_2 */
9961     { "vaesenc",        { XM, Vex128, EXx } },
9962   },
9963   {
9964     /* VEX_W_38DD_P_2 */
9965     { "vaesenclast",    { XM, Vex128, EXx } },
9966   },
9967   {
9968     /* VEX_W_38DE_P_2 */
9969     { "vaesdec",        { XM, Vex128, EXx } },
9970   },
9971   {
9972     /* VEX_W_38DF_P_2 */
9973     { "vaesdeclast",    { XM, Vex128, EXx } },
9974   },
9975   {
9976     /* VEX_W_3A04_P_2 */
9977     { "vpermilps",      { XM, EXx, Ib } },
9978   },
9979   {
9980     /* VEX_W_3A05_P_2 */
9981     { "vpermilpd",      { XM, EXx, Ib } },
9982   },
9983   {
9984     /* VEX_W_3A06_P_2 */
9985     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
9986   },
9987   {
9988     /* VEX_W_3A08_P_2 */
9989     { "vroundps",       { XM, EXx, Ib } },
9990   },
9991   {
9992     /* VEX_W_3A09_P_2 */
9993     { "vroundpd",       { XM, EXx, Ib } },
9994   },
9995   {
9996     /* VEX_W_3A0A_P_2 */
9997     { "vroundss",       { XM, Vex128, EXd, Ib } },
9998   },
9999   {
10000     /* VEX_W_3A0B_P_2 */
10001     { "vroundsd",       { XM, Vex128, EXq, Ib } },
10002   },
10003   {
10004     /* VEX_W_3A0C_P_2 */
10005     { "vblendps",       { XM, Vex, EXx, Ib } },
10006   },
10007   {
10008     /* VEX_W_3A0D_P_2 */
10009     { "vblendpd",       { XM, Vex, EXx, Ib } },
10010   },
10011   {
10012     /* VEX_W_3A0E_P_2 */
10013     { "vpblendw",       { XM, Vex128, EXx, Ib } },
10014   },
10015   {
10016     /* VEX_W_3A0F_P_2 */
10017     { "vpalignr",       { XM, Vex128, EXx, Ib } },
10018   },
10019   {
10020     /* VEX_W_3A14_P_2 */
10021     { "vpextrb",        { Edqb, XM, Ib } },
10022   },
10023   {
10024     /* VEX_W_3A15_P_2 */
10025     { "vpextrw",        { Edqw, XM, Ib } },
10026   },
10027   {
10028     /* VEX_W_3A18_P_2 */
10029     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10030   },
10031   {
10032     /* VEX_W_3A19_P_2 */
10033     { "vextractf128",   { EXxmm, XM, Ib } },
10034   },
10035   {
10036     /* VEX_W_3A20_P_2 */
10037     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10038   },
10039   {
10040     /* VEX_W_3A21_P_2 */
10041     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10042   },
10043   {
10044     /* VEX_W_3A40_P_2 */
10045     { "vdpps",          { XM, Vex, EXx, Ib } },
10046   },
10047   {
10048     /* VEX_W_3A41_P_2 */
10049     { "vdppd",          { XM, Vex128, EXx, Ib } },
10050   },
10051   {
10052     /* VEX_W_3A42_P_2 */
10053     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
10054   },
10055   {
10056     /* VEX_W_3A44_P_2 */
10057     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10058   },
10059   {
10060     /* VEX_W_3A4A_P_2 */
10061     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10062   },
10063   {
10064     /* VEX_W_3A4B_P_2 */
10065     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10066   },
10067   {
10068     /* VEX_W_3A4C_P_2 */
10069     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
10070   },
10071   {
10072     /* VEX_W_3A60_P_2 */
10073     { "vpcmpestrm",     { XM, EXx, Ib } },
10074   },
10075   {
10076     /* VEX_W_3A61_P_2 */
10077     { "vpcmpestri",     { XM, EXx, Ib } },
10078   },
10079   {
10080     /* VEX_W_3A62_P_2 */
10081     { "vpcmpistrm",     { XM, EXx, Ib } },
10082   },
10083   {
10084     /* VEX_W_3A63_P_2 */
10085     { "vpcmpistri",     { XM, EXx, Ib } },
10086   },
10087   {
10088     /* VEX_W_3ADF_P_2 */
10089     { "vaeskeygenassist", { XM, EXx, Ib } },
10090   },
10091 };
10092
10093 static const struct dis386 mod_table[][2] = {
10094   {
10095     /* MOD_8D */
10096     { "leaS",           { Gv, M } },
10097   },
10098   {
10099     /* MOD_0F01_REG_0 */
10100     { X86_64_TABLE (X86_64_0F01_REG_0) },
10101     { RM_TABLE (RM_0F01_REG_0) },
10102   },
10103   {
10104     /* MOD_0F01_REG_1 */
10105     { X86_64_TABLE (X86_64_0F01_REG_1) },
10106     { RM_TABLE (RM_0F01_REG_1) },
10107   },
10108   {
10109     /* MOD_0F01_REG_2 */
10110     { X86_64_TABLE (X86_64_0F01_REG_2) },
10111     { RM_TABLE (RM_0F01_REG_2) },
10112   },
10113   {
10114     /* MOD_0F01_REG_3 */
10115     { X86_64_TABLE (X86_64_0F01_REG_3) },
10116     { RM_TABLE (RM_0F01_REG_3) },
10117   },
10118   {
10119     /* MOD_0F01_REG_7 */
10120     { "invlpg",         { Mb } },
10121     { RM_TABLE (RM_0F01_REG_7) },
10122   },
10123   {
10124     /* MOD_0F12_PREFIX_0 */
10125     { "movlps",         { XM, EXq } },
10126     { "movhlps",        { XM, EXq } },
10127   },
10128   {
10129     /* MOD_0F13 */
10130     { "movlpX",         { EXq, XM } },
10131   },
10132   {
10133     /* MOD_0F16_PREFIX_0 */
10134     { "movhps",         { XM, EXq } },
10135     { "movlhps",        { XM, EXq } },
10136   },
10137   {
10138     /* MOD_0F17 */
10139     { "movhpX",         { EXq, XM } },
10140   },
10141   {
10142     /* MOD_0F18_REG_0 */
10143     { "prefetchnta",    { Mb } },
10144   },
10145   {
10146     /* MOD_0F18_REG_1 */
10147     { "prefetcht0",     { Mb } },
10148   },
10149   {
10150     /* MOD_0F18_REG_2 */
10151     { "prefetcht1",     { Mb } },
10152   },
10153   {
10154     /* MOD_0F18_REG_3 */
10155     { "prefetcht2",     { Mb } },
10156   },
10157   {
10158     /* MOD_0F20 */
10159     { Bad_Opcode },
10160     { "movZ",           { Rm, Cm } },
10161   },
10162   {
10163     /* MOD_0F21 */
10164     { Bad_Opcode },
10165     { "movZ",           { Rm, Dm } },
10166   },
10167   {
10168     /* MOD_0F22 */
10169     { Bad_Opcode },
10170     { "movZ",           { Cm, Rm } },
10171   },
10172   {
10173     /* MOD_0F23 */
10174     { Bad_Opcode },
10175     { "movZ",           { Dm, Rm } },
10176   },
10177   {
10178     /* MOD_0F24 */
10179     { Bad_Opcode },
10180     { "movL",           { Rd, Td } },
10181   },
10182   {
10183     /* MOD_0F26 */
10184     { Bad_Opcode },
10185     { "movL",           { Td, Rd } },
10186   },
10187   {
10188     /* MOD_0F2B_PREFIX_0 */
10189     {"movntps",         { Mx, XM } },
10190   },
10191   {
10192     /* MOD_0F2B_PREFIX_1 */
10193     {"movntss",         { Md, XM } },
10194   },
10195   {
10196     /* MOD_0F2B_PREFIX_2 */
10197     {"movntpd",         { Mx, XM } },
10198   },
10199   {
10200     /* MOD_0F2B_PREFIX_3 */
10201     {"movntsd",         { Mq, XM } },
10202   },
10203   {
10204     /* MOD_0F51 */
10205     { Bad_Opcode },
10206     { "movmskpX",       { Gdq, XS } },
10207   },
10208   {
10209     /* MOD_0F71_REG_2 */
10210     { Bad_Opcode },
10211     { "psrlw",          { MS, Ib } },
10212   },
10213   {
10214     /* MOD_0F71_REG_4 */
10215     { Bad_Opcode },
10216     { "psraw",          { MS, Ib } },
10217   },
10218   {
10219     /* MOD_0F71_REG_6 */
10220     { Bad_Opcode },
10221     { "psllw",          { MS, Ib } },
10222   },
10223   {
10224     /* MOD_0F72_REG_2 */
10225     { Bad_Opcode },
10226     { "psrld",          { MS, Ib } },
10227   },
10228   {
10229     /* MOD_0F72_REG_4 */
10230     { Bad_Opcode },
10231     { "psrad",          { MS, Ib } },
10232   },
10233   {
10234     /* MOD_0F72_REG_6 */
10235     { Bad_Opcode },
10236     { "pslld",          { MS, Ib } },
10237   },
10238   {
10239     /* MOD_0F73_REG_2 */
10240     { Bad_Opcode },
10241     { "psrlq",          { MS, Ib } },
10242   },
10243   {
10244     /* MOD_0F73_REG_3 */
10245     { Bad_Opcode },
10246     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10247   },
10248   {
10249     /* MOD_0F73_REG_6 */
10250     { Bad_Opcode },
10251     { "psllq",          { MS, Ib } },
10252   },
10253   {
10254     /* MOD_0F73_REG_7 */
10255     { Bad_Opcode },
10256     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10257   },
10258   {
10259     /* MOD_0FAE_REG_0 */
10260     { "fxsave",         { FXSAVE } },
10261   },
10262   {
10263     /* MOD_0FAE_REG_1 */
10264     { "fxrstor",        { FXSAVE } },
10265   },
10266   {
10267     /* MOD_0FAE_REG_2 */
10268     { "ldmxcsr",        { Md } },
10269   },
10270   {
10271     /* MOD_0FAE_REG_3 */
10272     { "stmxcsr",        { Md } },
10273   },
10274   {
10275     /* MOD_0FAE_REG_4 */
10276     { "xsave",          { FXSAVE } },
10277   },
10278   {
10279     /* MOD_0FAE_REG_5 */
10280     { "xrstor",         { FXSAVE } },
10281     { RM_TABLE (RM_0FAE_REG_5) },
10282   },
10283   {
10284     /* MOD_0FAE_REG_6 */
10285     { Bad_Opcode },
10286     { RM_TABLE (RM_0FAE_REG_6) },
10287   },
10288   {
10289     /* MOD_0FAE_REG_7 */
10290     { "clflush",        { Mb } },
10291     { RM_TABLE (RM_0FAE_REG_7) },
10292   },
10293   {
10294     /* MOD_0FB2 */
10295     { "lssS",           { Gv, Mp } },
10296   },
10297   {
10298     /* MOD_0FB4 */
10299     { "lfsS",           { Gv, Mp } },
10300   },
10301   {
10302     /* MOD_0FB5 */
10303     { "lgsS",           { Gv, Mp } },
10304   },
10305   {
10306     /* MOD_0FC7_REG_6 */
10307     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10308   },
10309   {
10310     /* MOD_0FC7_REG_7 */
10311     { "vmptrst",        { Mq } },
10312   },
10313   {
10314     /* MOD_0FD7 */
10315     { Bad_Opcode },
10316     { "pmovmskb",       { Gdq, MS } },
10317   },
10318   {
10319     /* MOD_0FE7_PREFIX_2 */
10320     { "movntdq",        { Mx, XM } },
10321   },
10322   {
10323     /* MOD_0FF0_PREFIX_3 */
10324     { "lddqu",          { XM, M } },
10325   },
10326   {
10327     /* MOD_0F382A_PREFIX_2 */
10328     { "movntdqa",       { XM, Mx } },
10329   },
10330   {
10331     /* MOD_62_32BIT */
10332     { "bound{S|}",      { Gv, Ma } },
10333   },
10334   {
10335     /* MOD_C4_32BIT */
10336     { "lesS",           { Gv, Mp } },
10337     { VEX_C4_TABLE (VEX_0F) },
10338   },
10339   {
10340     /* MOD_C5_32BIT */
10341     { "ldsS",           { Gv, Mp } },
10342     { VEX_C5_TABLE (VEX_0F) },
10343   },
10344   {
10345     /* MOD_VEX_12_PREFIX_0 */
10346     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
10347     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
10348   },
10349   {
10350     /* MOD_VEX_13 */
10351     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
10352   },
10353   {
10354     /* MOD_VEX_16_PREFIX_0 */
10355     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
10356     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
10357   },
10358   {
10359     /* MOD_VEX_17 */
10360     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
10361   },
10362   {
10363     /* MOD_VEX_2B */
10364     { VEX_W_TABLE (VEX_W_2B_M_0) },
10365   },
10366   {
10367     /* MOD_VEX_50 */
10368     { Bad_Opcode },
10369     { VEX_W_TABLE (VEX_W_50_M_0) },
10370   },
10371   {
10372     /* MOD_VEX_71_REG_2 */
10373     { Bad_Opcode },
10374     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
10375   },
10376   {
10377     /* MOD_VEX_71_REG_4 */
10378     { Bad_Opcode },
10379     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
10380   },
10381   {
10382     /* MOD_VEX_71_REG_6 */
10383     { Bad_Opcode },
10384     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
10385   },
10386   {
10387     /* MOD_VEX_72_REG_2 */
10388     { Bad_Opcode },
10389     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
10390   },
10391   {
10392     /* MOD_VEX_72_REG_4 */
10393     { Bad_Opcode },
10394     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
10395   },
10396   {
10397     /* MOD_VEX_72_REG_6 */
10398     { Bad_Opcode },
10399     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
10400   },
10401   {
10402     /* MOD_VEX_73_REG_2 */
10403     { Bad_Opcode },
10404     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
10405   },
10406   {
10407     /* MOD_VEX_73_REG_3 */
10408     { Bad_Opcode },
10409     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
10410   },
10411   {
10412     /* MOD_VEX_73_REG_6 */
10413     { Bad_Opcode },
10414     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
10415   },
10416   {
10417     /* MOD_VEX_73_REG_7 */
10418     { Bad_Opcode },
10419     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
10420   },
10421   {
10422     /* MOD_VEX_AE_REG_2 */
10423     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
10424   },
10425   {
10426     /* MOD_VEX_AE_REG_3 */
10427     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
10428   },
10429   {
10430     /* MOD_VEX_D7_PREFIX_2 */
10431     { Bad_Opcode },
10432     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
10433   },
10434   {
10435     /* MOD_VEX_E7_PREFIX_2 */
10436     { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
10437   },
10438   {
10439     /* MOD_VEX_F0_PREFIX_3 */
10440     { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
10441   },
10442   {
10443     /* MOD_VEX_3818_PREFIX_2 */
10444     { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
10445   },
10446   {
10447     /* MOD_VEX_3819_PREFIX_2 */
10448     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
10449   },
10450   {
10451     /* MOD_VEX_381A_PREFIX_2 */
10452     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
10453   },
10454   {
10455     /* MOD_VEX_382A_PREFIX_2 */
10456     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
10457   },
10458   {
10459     /* MOD_VEX_382C_PREFIX_2 */
10460     { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
10461   },
10462   {
10463     /* MOD_VEX_382D_PREFIX_2 */
10464     { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
10465   },
10466   {
10467     /* MOD_VEX_382E_PREFIX_2 */
10468     { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
10469   },
10470   {
10471     /* MOD_VEX_382F_PREFIX_2 */
10472     { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
10473   },
10474 };
10475
10476 static const struct dis386 rm_table[][8] = {
10477   {
10478     /* RM_0F01_REG_0 */
10479     { Bad_Opcode },
10480     { "vmcall",         { Skip_MODRM } },
10481     { "vmlaunch",       { Skip_MODRM } },
10482     { "vmresume",       { Skip_MODRM } },
10483     { "vmxoff",         { Skip_MODRM } },
10484   },
10485   {
10486     /* RM_0F01_REG_1 */
10487     { "monitor",        { { OP_Monitor, 0 } } },
10488     { "mwait",          { { OP_Mwait, 0 } } },
10489   },
10490   {
10491     /* RM_0F01_REG_2 */
10492     { "xgetbv",         { Skip_MODRM } },
10493     { "xsetbv",         { Skip_MODRM } },
10494   },
10495   {
10496     /* RM_0F01_REG_3 */
10497     { "vmrun",          { Skip_MODRM } },
10498     { "vmmcall",        { Skip_MODRM } },
10499     { "vmload",         { Skip_MODRM } },
10500     { "vmsave",         { Skip_MODRM } },
10501     { "stgi",           { Skip_MODRM } },
10502     { "clgi",           { Skip_MODRM } },
10503     { "skinit",         { Skip_MODRM } },
10504     { "invlpga",        { Skip_MODRM } },
10505   },
10506   {
10507     /* RM_0F01_REG_7 */
10508     { "swapgs",         { Skip_MODRM } },
10509     { "rdtscp",         { Skip_MODRM } },
10510   },
10511   {
10512     /* RM_0FAE_REG_5 */
10513     { "lfence",         { Skip_MODRM } },
10514   },
10515   {
10516     /* RM_0FAE_REG_6 */
10517     { "mfence",         { Skip_MODRM } },
10518   },
10519   {
10520     /* RM_0FAE_REG_7 */
10521     { "sfence",         { Skip_MODRM } },
10522   },
10523 };
10524
10525 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10526
10527 /* We use the high bit to indicate different name for the same
10528    prefix.  */
10529 #define ADDR16_PREFIX   (0x67 | 0x100)
10530 #define ADDR32_PREFIX   (0x67 | 0x200)
10531 #define DATA16_PREFIX   (0x66 | 0x100)
10532 #define DATA32_PREFIX   (0x66 | 0x200)
10533 #define REP_PREFIX      (0xf3 | 0x100)
10534
10535 static int
10536 ckprefix (void)
10537 {
10538   int newrex, i, length;
10539   rex = 0;
10540   rex_ignored = 0;
10541   prefixes = 0;
10542   used_prefixes = 0;
10543   rex_used = 0;
10544   last_lock_prefix = -1;
10545   last_repz_prefix = -1;
10546   last_repnz_prefix = -1;
10547   last_data_prefix = -1;
10548   last_addr_prefix = -1;
10549   last_rex_prefix = -1;
10550   last_seg_prefix = -1;
10551   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10552     all_prefixes[i] = 0;
10553   i = 0;
10554   length = 0;
10555   /* The maximum instruction length is 15bytes.  */
10556   while (length < MAX_CODE_LENGTH - 1)
10557     {
10558       FETCH_DATA (the_info, codep + 1);
10559       newrex = 0;
10560       switch (*codep)
10561         {
10562         /* REX prefixes family.  */
10563         case 0x40:
10564         case 0x41:
10565         case 0x42:
10566         case 0x43:
10567         case 0x44:
10568         case 0x45:
10569         case 0x46:
10570         case 0x47:
10571         case 0x48:
10572         case 0x49:
10573         case 0x4a:
10574         case 0x4b:
10575         case 0x4c:
10576         case 0x4d:
10577         case 0x4e:
10578         case 0x4f:
10579           if (address_mode == mode_64bit)
10580             newrex = *codep;
10581           else
10582             return 1;
10583           last_rex_prefix = i;
10584           break;
10585         case 0xf3:
10586           prefixes |= PREFIX_REPZ;
10587           last_repz_prefix = i;
10588           break;
10589         case 0xf2:
10590           prefixes |= PREFIX_REPNZ;
10591           last_repnz_prefix = i;
10592           break;
10593         case 0xf0:
10594           prefixes |= PREFIX_LOCK;
10595           last_lock_prefix = i;
10596           break;
10597         case 0x2e:
10598           prefixes |= PREFIX_CS;
10599           last_seg_prefix = i;
10600           break;
10601         case 0x36:
10602           prefixes |= PREFIX_SS;
10603           last_seg_prefix = i;
10604           break;
10605         case 0x3e:
10606           prefixes |= PREFIX_DS;
10607           last_seg_prefix = i;
10608           break;
10609         case 0x26:
10610           prefixes |= PREFIX_ES;
10611           last_seg_prefix = i;
10612           break;
10613         case 0x64:
10614           prefixes |= PREFIX_FS;
10615           last_seg_prefix = i;
10616           break;
10617         case 0x65:
10618           prefixes |= PREFIX_GS;
10619           last_seg_prefix = i;
10620           break;
10621         case 0x66:
10622           prefixes |= PREFIX_DATA;
10623           last_data_prefix = i;
10624           break;
10625         case 0x67:
10626           prefixes |= PREFIX_ADDR;
10627           last_addr_prefix = i;
10628           break;
10629         case FWAIT_OPCODE:
10630           /* fwait is really an instruction.  If there are prefixes
10631              before the fwait, they belong to the fwait, *not* to the
10632              following instruction.  */
10633           if (prefixes || rex)
10634             {
10635               prefixes |= PREFIX_FWAIT;
10636               codep++;
10637               return 1;
10638             }
10639           prefixes = PREFIX_FWAIT;
10640           break;
10641         default:
10642           return 1;
10643         }
10644       /* Rex is ignored when followed by another prefix.  */
10645       if (rex)
10646         {
10647           rex_used = rex;
10648           return 1;
10649         }
10650       if (*codep != FWAIT_OPCODE)
10651         all_prefixes[i++] = *codep;
10652       rex = newrex;
10653       codep++;
10654       length++;
10655     }
10656   return 0;
10657 }
10658
10659 static int
10660 seg_prefix (int pref)
10661 {
10662   switch (pref)
10663     {
10664     case 0x2e:
10665       return PREFIX_CS;
10666     case 0x36:
10667       return PREFIX_SS;
10668     case 0x3e:
10669       return PREFIX_DS;
10670     case 0x26:
10671       return PREFIX_ES;
10672     case 0x64:
10673       return PREFIX_FS;
10674     case 0x65:
10675       return PREFIX_GS;
10676     default:
10677       return 0;
10678     }
10679 }
10680
10681 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10682    prefix byte.  */
10683
10684 static const char *
10685 prefix_name (int pref, int sizeflag)
10686 {
10687   static const char *rexes [16] =
10688     {
10689       "rex",            /* 0x40 */
10690       "rex.B",          /* 0x41 */
10691       "rex.X",          /* 0x42 */
10692       "rex.XB",         /* 0x43 */
10693       "rex.R",          /* 0x44 */
10694       "rex.RB",         /* 0x45 */
10695       "rex.RX",         /* 0x46 */
10696       "rex.RXB",        /* 0x47 */
10697       "rex.W",          /* 0x48 */
10698       "rex.WB",         /* 0x49 */
10699       "rex.WX",         /* 0x4a */
10700       "rex.WXB",        /* 0x4b */
10701       "rex.WR",         /* 0x4c */
10702       "rex.WRB",        /* 0x4d */
10703       "rex.WRX",        /* 0x4e */
10704       "rex.WRXB",       /* 0x4f */
10705     };
10706
10707   switch (pref)
10708     {
10709     /* REX prefixes family.  */
10710     case 0x40:
10711     case 0x41:
10712     case 0x42:
10713     case 0x43:
10714     case 0x44:
10715     case 0x45:
10716     case 0x46:
10717     case 0x47:
10718     case 0x48:
10719     case 0x49:
10720     case 0x4a:
10721     case 0x4b:
10722     case 0x4c:
10723     case 0x4d:
10724     case 0x4e:
10725     case 0x4f:
10726       return rexes [pref - 0x40];
10727     case 0xf3:
10728       return "repz";
10729     case 0xf2:
10730       return "repnz";
10731     case 0xf0:
10732       return "lock";
10733     case 0x2e:
10734       return "cs";
10735     case 0x36:
10736       return "ss";
10737     case 0x3e:
10738       return "ds";
10739     case 0x26:
10740       return "es";
10741     case 0x64:
10742       return "fs";
10743     case 0x65:
10744       return "gs";
10745     case 0x66:
10746       return (sizeflag & DFLAG) ? "data16" : "data32";
10747     case 0x67:
10748       if (address_mode == mode_64bit)
10749         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10750       else
10751         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10752     case FWAIT_OPCODE:
10753       return "fwait";
10754     case ADDR16_PREFIX:
10755       return "addr16";
10756     case ADDR32_PREFIX:
10757       return "addr32";
10758     case DATA16_PREFIX:
10759       return "data16";
10760     case DATA32_PREFIX:
10761       return "data32";
10762     case REP_PREFIX:
10763       return "rep";
10764     default:
10765       return NULL;
10766     }
10767 }
10768
10769 static char op_out[MAX_OPERANDS][100];
10770 static int op_ad, op_index[MAX_OPERANDS];
10771 static int two_source_ops;
10772 static bfd_vma op_address[MAX_OPERANDS];
10773 static bfd_vma op_riprel[MAX_OPERANDS];
10774 static bfd_vma start_pc;
10775
10776 /*
10777  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10778  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10779  *   section of the "Virtual 8086 Mode" chapter.)
10780  * 'pc' should be the address of this instruction, it will
10781  *   be used to print the target address if this is a relative jump or call
10782  * The function returns the length of this instruction in bytes.
10783  */
10784
10785 static char intel_syntax;
10786 static char intel_mnemonic = !SYSV386_COMPAT;
10787 static char open_char;
10788 static char close_char;
10789 static char separator_char;
10790 static char scale_char;
10791
10792 /* Here for backwards compatibility.  When gdb stops using
10793    print_insn_i386_att and print_insn_i386_intel these functions can
10794    disappear, and print_insn_i386 be merged into print_insn.  */
10795 int
10796 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10797 {
10798   intel_syntax = 0;
10799
10800   return print_insn (pc, info);
10801 }
10802
10803 int
10804 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10805 {
10806   intel_syntax = 1;
10807
10808   return print_insn (pc, info);
10809 }
10810
10811 int
10812 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10813 {
10814   intel_syntax = -1;
10815
10816   return print_insn (pc, info);
10817 }
10818
10819 void
10820 print_i386_disassembler_options (FILE *stream)
10821 {
10822   fprintf (stream, _("\n\
10823 The following i386/x86-64 specific disassembler options are supported for use\n\
10824 with the -M switch (multiple options should be separated by commas):\n"));
10825
10826   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10827   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10828   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10829   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10830   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10831   fprintf (stream, _("  att-mnemonic\n"
10832                      "              Display instruction in AT&T mnemonic\n"));
10833   fprintf (stream, _("  intel-mnemonic\n"
10834                      "              Display instruction in Intel mnemonic\n"));
10835   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10836   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10837   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10838   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10839   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10840   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10841 }
10842
10843 /* Bad opcode.  */
10844 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10845
10846 /* Get a pointer to struct dis386 with a valid name.  */
10847
10848 static const struct dis386 *
10849 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10850 {
10851   int vindex, vex_table_index;
10852
10853   if (dp->name != NULL)
10854     return dp;
10855
10856   switch (dp->op[0].bytemode)
10857     {
10858     case USE_REG_TABLE:
10859       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10860       break;
10861
10862     case USE_MOD_TABLE:
10863       vindex = modrm.mod == 0x3 ? 1 : 0;
10864       dp = &mod_table[dp->op[1].bytemode][vindex];
10865       break;
10866
10867     case USE_RM_TABLE:
10868       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10869       break;
10870
10871     case USE_PREFIX_TABLE:
10872       if (need_vex)
10873         {
10874           /* The prefix in VEX is implicit.  */
10875           switch (vex.prefix)
10876             {
10877             case 0:
10878               vindex = 0;
10879               break;
10880             case REPE_PREFIX_OPCODE:
10881               vindex = 1;
10882               break;
10883             case DATA_PREFIX_OPCODE:
10884               vindex = 2;
10885               break;
10886             case REPNE_PREFIX_OPCODE:
10887               vindex = 3;
10888               break;
10889             default:
10890               abort ();
10891               break;
10892             }
10893         }
10894       else
10895         {
10896           vindex = 0;
10897           used_prefixes |= (prefixes & PREFIX_REPZ);
10898           if (prefixes & PREFIX_REPZ)
10899             {
10900               vindex = 1;
10901               all_prefixes[last_repz_prefix] = 0;
10902             }
10903           else
10904             {
10905               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10906                  PREFIX_DATA.  */
10907               used_prefixes |= (prefixes & PREFIX_REPNZ);
10908               if (prefixes & PREFIX_REPNZ)
10909                 {
10910                   vindex = 3;
10911                   all_prefixes[last_repnz_prefix] = 0;
10912                 }
10913               else
10914                 {
10915                   used_prefixes |= (prefixes & PREFIX_DATA);
10916                   if (prefixes & PREFIX_DATA)
10917                     {
10918                       vindex = 2;
10919                       all_prefixes[last_data_prefix] = 0;
10920                     }
10921                 }
10922             }
10923         }
10924       dp = &prefix_table[dp->op[1].bytemode][vindex];
10925       break;
10926
10927     case USE_X86_64_TABLE:
10928       vindex = address_mode == mode_64bit ? 1 : 0;
10929       dp = &x86_64_table[dp->op[1].bytemode][vindex];
10930       break;
10931
10932     case USE_3BYTE_TABLE:
10933       FETCH_DATA (info, codep + 2);
10934       vindex = *codep++;
10935       dp = &three_byte_table[dp->op[1].bytemode][vindex];
10936       modrm.mod = (*codep >> 6) & 3;
10937       modrm.reg = (*codep >> 3) & 7;
10938       modrm.rm = *codep & 7;
10939       break;
10940
10941     case USE_VEX_LEN_TABLE:
10942       if (!need_vex)
10943         abort ();
10944
10945       switch (vex.length)
10946         {
10947         case 128:
10948           vindex = 0;
10949           break;
10950         case 256:
10951           vindex = 1;
10952           break;
10953         default:
10954           abort ();
10955           break;
10956         }
10957
10958       dp = &vex_len_table[dp->op[1].bytemode][vindex];
10959       break;
10960
10961     case USE_XOP_8F_TABLE:
10962       FETCH_DATA (info, codep + 3);
10963       /* All bits in the REX prefix are ignored.  */
10964       rex_ignored = rex;
10965       rex = ~(*codep >> 5) & 0x7;
10966
10967       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
10968       switch ((*codep & 0x1f))
10969         {
10970         default:
10971           BadOp ();
10972         case 0x8:
10973           vex_table_index = XOP_08;
10974           break;
10975         case 0x9:
10976           vex_table_index = XOP_09;
10977           break;
10978         case 0xa:
10979           vex_table_index = XOP_0A;
10980           break;
10981         }
10982       codep++;
10983       vex.w = *codep & 0x80;
10984       if (vex.w && address_mode == mode_64bit)
10985         rex |= REX_W;
10986
10987       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10988       if (address_mode != mode_64bit
10989           && vex.register_specifier > 0x7)
10990         BadOp ();
10991
10992       vex.length = (*codep & 0x4) ? 256 : 128;
10993       switch ((*codep & 0x3))
10994         {
10995         case 0:
10996           vex.prefix = 0;
10997           break;
10998         case 1:
10999           vex.prefix = DATA_PREFIX_OPCODE;
11000           break;
11001         case 2:
11002           vex.prefix = REPE_PREFIX_OPCODE;
11003           break;
11004         case 3:
11005           vex.prefix = REPNE_PREFIX_OPCODE;
11006           break;
11007         }
11008       need_vex = 1;
11009       need_vex_reg = 1;
11010       codep++;
11011       vindex = *codep++;
11012       dp = &xop_table[vex_table_index][vindex];
11013
11014       FETCH_DATA (info, codep + 1);
11015       modrm.mod = (*codep >> 6) & 3;
11016       modrm.reg = (*codep >> 3) & 7;
11017       modrm.rm = *codep & 7;
11018       break;
11019
11020     case USE_VEX_C4_TABLE:
11021       FETCH_DATA (info, codep + 3);
11022       /* All bits in the REX prefix are ignored.  */
11023       rex_ignored = rex;
11024       rex = ~(*codep >> 5) & 0x7;
11025       switch ((*codep & 0x1f))
11026         {
11027         default:
11028           BadOp ();
11029         case 0x1:
11030           vex_table_index = VEX_0F;
11031           break;
11032         case 0x2:
11033           vex_table_index = VEX_0F38;
11034           break;
11035         case 0x3:
11036           vex_table_index = VEX_0F3A;
11037           break;
11038         }
11039       codep++;
11040       vex.w = *codep & 0x80;
11041       if (vex.w && address_mode == mode_64bit)
11042         rex |= REX_W;
11043
11044       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11045       if (address_mode != mode_64bit
11046           && vex.register_specifier > 0x7)
11047         BadOp ();
11048
11049       vex.length = (*codep & 0x4) ? 256 : 128;
11050       switch ((*codep & 0x3))
11051         {
11052         case 0:
11053           vex.prefix = 0;
11054           break;
11055         case 1:
11056           vex.prefix = DATA_PREFIX_OPCODE;
11057           break;
11058         case 2:
11059           vex.prefix = REPE_PREFIX_OPCODE;
11060           break;
11061         case 3:
11062           vex.prefix = REPNE_PREFIX_OPCODE;
11063           break;
11064         }
11065       need_vex = 1;
11066       need_vex_reg = 1;
11067       codep++;
11068       vindex = *codep++;
11069       dp = &vex_table[vex_table_index][vindex];
11070       /* There is no MODRM byte for VEX [82|77].  */
11071       if (vindex != 0x77 && vindex != 0x82)
11072         {
11073           FETCH_DATA (info, codep + 1);
11074           modrm.mod = (*codep >> 6) & 3;
11075           modrm.reg = (*codep >> 3) & 7;
11076           modrm.rm = *codep & 7;
11077         }
11078       break;
11079
11080     case USE_VEX_C5_TABLE:
11081       FETCH_DATA (info, codep + 2);
11082       /* All bits in the REX prefix are ignored.  */
11083       rex_ignored = rex;
11084       rex = (*codep & 0x80) ? 0 : REX_R;
11085
11086       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11087       if (address_mode != mode_64bit
11088           && vex.register_specifier > 0x7)
11089         BadOp ();
11090
11091       vex.w = 0;
11092
11093       vex.length = (*codep & 0x4) ? 256 : 128;
11094       switch ((*codep & 0x3))
11095         {
11096         case 0:
11097           vex.prefix = 0;
11098           break;
11099         case 1:
11100           vex.prefix = DATA_PREFIX_OPCODE;
11101           break;
11102         case 2:
11103           vex.prefix = REPE_PREFIX_OPCODE;
11104           break;
11105         case 3:
11106           vex.prefix = REPNE_PREFIX_OPCODE;
11107           break;
11108         }
11109       need_vex = 1;
11110       need_vex_reg = 1;
11111       codep++;
11112       vindex = *codep++;
11113       dp = &vex_table[dp->op[1].bytemode][vindex];
11114       /* There is no MODRM byte for VEX [82|77].  */
11115       if (vindex != 0x77 && vindex != 0x82)
11116         {
11117           FETCH_DATA (info, codep + 1);
11118           modrm.mod = (*codep >> 6) & 3;
11119           modrm.reg = (*codep >> 3) & 7;
11120           modrm.rm = *codep & 7;
11121         }
11122       break;
11123
11124     case USE_VEX_W_TABLE:
11125       if (!need_vex)
11126         abort ();
11127
11128       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11129       break;
11130
11131     case 0:
11132       dp = &bad_opcode;
11133       break;
11134
11135     default:
11136       abort ();
11137     }
11138
11139   if (dp->name != NULL)
11140     return dp;
11141   else
11142     return get_valid_dis386 (dp, info);
11143 }
11144
11145 static int
11146 print_insn (bfd_vma pc, disassemble_info *info)
11147 {
11148   const struct dis386 *dp;
11149   int i;
11150   char *op_txt[MAX_OPERANDS];
11151   int needcomma;
11152   int sizeflag;
11153   const char *p;
11154   struct dis_private priv;
11155   unsigned char op;
11156   int prefix_length;
11157   int default_prefixes;
11158
11159   if (info->mach == bfd_mach_x86_64_intel_syntax
11160       || info->mach == bfd_mach_x86_64
11161       || info->mach == bfd_mach_l1om
11162       || info->mach == bfd_mach_l1om_intel_syntax)
11163     address_mode = mode_64bit;
11164   else
11165     address_mode = mode_32bit;
11166
11167   if (intel_syntax == (char) -1)
11168     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11169                     || info->mach == bfd_mach_x86_64_intel_syntax
11170                     || info->mach == bfd_mach_l1om_intel_syntax);
11171
11172   if (info->mach == bfd_mach_i386_i386
11173       || info->mach == bfd_mach_x86_64
11174       || info->mach == bfd_mach_l1om
11175       || info->mach == bfd_mach_i386_i386_intel_syntax
11176       || info->mach == bfd_mach_x86_64_intel_syntax
11177       || info->mach == bfd_mach_l1om_intel_syntax)
11178     priv.orig_sizeflag = AFLAG | DFLAG;
11179   else if (info->mach == bfd_mach_i386_i8086)
11180     priv.orig_sizeflag = 0;
11181   else
11182     abort ();
11183
11184   for (p = info->disassembler_options; p != NULL; )
11185     {
11186       if (CONST_STRNEQ (p, "x86-64"))
11187         {
11188           address_mode = mode_64bit;
11189           priv.orig_sizeflag = AFLAG | DFLAG;
11190         }
11191       else if (CONST_STRNEQ (p, "i386"))
11192         {
11193           address_mode = mode_32bit;
11194           priv.orig_sizeflag = AFLAG | DFLAG;
11195         }
11196       else if (CONST_STRNEQ (p, "i8086"))
11197         {
11198           address_mode = mode_16bit;
11199           priv.orig_sizeflag = 0;
11200         }
11201       else if (CONST_STRNEQ (p, "intel"))
11202         {
11203           intel_syntax = 1;
11204           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11205             intel_mnemonic = 1;
11206         }
11207       else if (CONST_STRNEQ (p, "att"))
11208         {
11209           intel_syntax = 0;
11210           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11211             intel_mnemonic = 0;
11212         }
11213       else if (CONST_STRNEQ (p, "addr"))
11214         {
11215           if (address_mode == mode_64bit)
11216             {
11217               if (p[4] == '3' && p[5] == '2')
11218                 priv.orig_sizeflag &= ~AFLAG;
11219               else if (p[4] == '6' && p[5] == '4')
11220                 priv.orig_sizeflag |= AFLAG;
11221             }
11222           else
11223             {
11224               if (p[4] == '1' && p[5] == '6')
11225                 priv.orig_sizeflag &= ~AFLAG;
11226               else if (p[4] == '3' && p[5] == '2')
11227                 priv.orig_sizeflag |= AFLAG;
11228             }
11229         }
11230       else if (CONST_STRNEQ (p, "data"))
11231         {
11232           if (p[4] == '1' && p[5] == '6')
11233             priv.orig_sizeflag &= ~DFLAG;
11234           else if (p[4] == '3' && p[5] == '2')
11235             priv.orig_sizeflag |= DFLAG;
11236         }
11237       else if (CONST_STRNEQ (p, "suffix"))
11238         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11239
11240       p = strchr (p, ',');
11241       if (p != NULL)
11242         p++;
11243     }
11244
11245   if (intel_syntax)
11246     {
11247       names64 = intel_names64;
11248       names32 = intel_names32;
11249       names16 = intel_names16;
11250       names8 = intel_names8;
11251       names8rex = intel_names8rex;
11252       names_seg = intel_names_seg;
11253       names_mm = intel_names_mm;
11254       names_xmm = intel_names_xmm;
11255       names_ymm = intel_names_ymm;
11256       index64 = intel_index64;
11257       index32 = intel_index32;
11258       index16 = intel_index16;
11259       open_char = '[';
11260       close_char = ']';
11261       separator_char = '+';
11262       scale_char = '*';
11263     }
11264   else
11265     {
11266       names64 = att_names64;
11267       names32 = att_names32;
11268       names16 = att_names16;
11269       names8 = att_names8;
11270       names8rex = att_names8rex;
11271       names_seg = att_names_seg;
11272       names_mm = att_names_mm;
11273       names_xmm = att_names_xmm;
11274       names_ymm = att_names_ymm;
11275       index64 = att_index64;
11276       index32 = att_index32;
11277       index16 = att_index16;
11278       open_char = '(';
11279       close_char =  ')';
11280       separator_char = ',';
11281       scale_char = ',';
11282     }
11283
11284   /* The output looks better if we put 7 bytes on a line, since that
11285      puts most long word instructions on a single line.  Use 8 bytes
11286      for Intel L1OM.  */
11287   if (info->mach == bfd_mach_l1om
11288       || info->mach == bfd_mach_l1om_intel_syntax)
11289     info->bytes_per_line = 8;
11290   else
11291     info->bytes_per_line = 7;
11292
11293   info->private_data = &priv;
11294   priv.max_fetched = priv.the_buffer;
11295   priv.insn_start = pc;
11296
11297   obuf[0] = 0;
11298   for (i = 0; i < MAX_OPERANDS; ++i)
11299     {
11300       op_out[i][0] = 0;
11301       op_index[i] = -1;
11302     }
11303
11304   the_info = info;
11305   start_pc = pc;
11306   start_codep = priv.the_buffer;
11307   codep = priv.the_buffer;
11308
11309   if (setjmp (priv.bailout) != 0)
11310     {
11311       const char *name;
11312
11313       /* Getting here means we tried for data but didn't get it.  That
11314          means we have an incomplete instruction of some sort.  Just
11315          print the first byte as a prefix or a .byte pseudo-op.  */
11316       if (codep > priv.the_buffer)
11317         {
11318           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11319           if (name != NULL)
11320             (*info->fprintf_func) (info->stream, "%s", name);
11321           else
11322             {
11323               /* Just print the first byte as a .byte instruction.  */
11324               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11325                                      (unsigned int) priv.the_buffer[0]);
11326             }
11327
11328           return 1;
11329         }
11330
11331       return -1;
11332     }
11333
11334   obufp = obuf;
11335   sizeflag = priv.orig_sizeflag;
11336
11337   if (!ckprefix () || rex_used)
11338     {
11339       /* Too many prefixes or unused REX prefixes.  */
11340       for (i = 0;
11341            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11342            i++)
11343         (*info->fprintf_func) (info->stream, "%s",
11344                                prefix_name (all_prefixes[i], sizeflag));
11345       return 1;
11346     }
11347
11348   insn_codep = codep;
11349
11350   FETCH_DATA (info, codep + 1);
11351   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11352
11353   if (((prefixes & PREFIX_FWAIT)
11354        && ((*codep < 0xd8) || (*codep > 0xdf))))
11355     {
11356       (*info->fprintf_func) (info->stream, "fwait");
11357       return 1;
11358     }
11359
11360   op = 0;
11361
11362   if (*codep == 0x0f)
11363     {
11364       unsigned char threebyte;
11365       FETCH_DATA (info, codep + 2);
11366       threebyte = *++codep;
11367       dp = &dis386_twobyte[threebyte];
11368       need_modrm = twobyte_has_modrm[*codep];
11369       codep++;
11370     }
11371   else
11372     {
11373       dp = &dis386[*codep];
11374       need_modrm = onebyte_has_modrm[*codep];
11375       codep++;
11376     }
11377
11378   if ((prefixes & PREFIX_REPZ))
11379     used_prefixes |= PREFIX_REPZ;
11380   if ((prefixes & PREFIX_REPNZ))
11381     used_prefixes |= PREFIX_REPNZ;
11382   if ((prefixes & PREFIX_LOCK))
11383     used_prefixes |= PREFIX_LOCK;
11384
11385   default_prefixes = 0;
11386   if (prefixes & PREFIX_ADDR)
11387     {
11388       sizeflag ^= AFLAG;
11389       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11390         {
11391           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11392             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11393           else
11394             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11395           default_prefixes |= PREFIX_ADDR;
11396         }
11397     }
11398
11399   if ((prefixes & PREFIX_DATA))
11400     {
11401       sizeflag ^= DFLAG;
11402       if (dp->op[2].bytemode == cond_jump_mode
11403           && dp->op[0].bytemode == v_mode
11404           && !intel_syntax)
11405         {
11406           if (sizeflag & DFLAG)
11407             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11408           else
11409             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11410           default_prefixes |= PREFIX_DATA;
11411         }
11412       else if (rex & REX_W)
11413         {
11414           /* REX_W will override PREFIX_DATA.  */
11415           default_prefixes |= PREFIX_DATA;
11416         }
11417     }
11418
11419   if (need_modrm)
11420     {
11421       FETCH_DATA (info, codep + 1);
11422       modrm.mod = (*codep >> 6) & 3;
11423       modrm.reg = (*codep >> 3) & 7;
11424       modrm.rm = *codep & 7;
11425     }
11426
11427    need_vex = 0;
11428    need_vex_reg = 0;
11429    vex_w_done = 0;
11430
11431   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11432     {
11433       dofloat (sizeflag);
11434     }
11435   else
11436     {
11437       dp = get_valid_dis386 (dp, info);
11438       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11439         {
11440           for (i = 0; i < MAX_OPERANDS; ++i)
11441             {
11442               obufp = op_out[i];
11443               op_ad = MAX_OPERANDS - 1 - i;
11444               if (dp->op[i].rtn)
11445                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11446             }
11447         }
11448     }
11449
11450   /* See if any prefixes were not used.  If so, print the first one
11451      separately.  If we don't do this, we'll wind up printing an
11452      instruction stream which does not precisely correspond to the
11453      bytes we are disassembling.  */
11454   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11455     {
11456       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11457         if (all_prefixes[i])
11458           {
11459             const char *name;
11460             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11461             if (name == NULL)
11462               name = INTERNAL_DISASSEMBLER_ERROR;
11463             (*info->fprintf_func) (info->stream, "%s", name);
11464             return 1;
11465           }
11466     }
11467
11468   /* Check if the REX prefix is used.  */
11469   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11470     all_prefixes[last_rex_prefix] = 0;
11471
11472   /* Check if the SEG prefix is used.  */
11473   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11474                    | PREFIX_FS | PREFIX_GS)) != 0
11475       && (used_prefixes
11476           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11477     all_prefixes[last_seg_prefix] = 0;
11478
11479   /* Check if the ADDR prefix is used.  */
11480   if ((prefixes & PREFIX_ADDR) != 0
11481       && (used_prefixes & PREFIX_ADDR) != 0)
11482     all_prefixes[last_addr_prefix] = 0;
11483
11484   /* Check if the DATA prefix is used.  */
11485   if ((prefixes & PREFIX_DATA) != 0
11486       && (used_prefixes & PREFIX_DATA) != 0)
11487     all_prefixes[last_data_prefix] = 0;
11488
11489   prefix_length = 0;
11490   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11491     if (all_prefixes[i])
11492       {
11493         const char *name;
11494         name = prefix_name (all_prefixes[i], sizeflag);
11495         if (name == NULL)
11496           abort ();
11497         prefix_length += strlen (name) + 1;
11498         (*info->fprintf_func) (info->stream, "%s ", name);
11499       }
11500
11501   /* Check maximum code length.  */
11502   if ((codep - start_codep) > MAX_CODE_LENGTH)
11503     {
11504       (*info->fprintf_func) (info->stream, "(bad)");
11505       return MAX_CODE_LENGTH;
11506     }
11507
11508   obufp = mnemonicendp;
11509   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11510     oappend (" ");
11511   oappend (" ");
11512   (*info->fprintf_func) (info->stream, "%s", obuf);
11513
11514   /* The enter and bound instructions are printed with operands in the same
11515      order as the intel book; everything else is printed in reverse order.  */
11516   if (intel_syntax || two_source_ops)
11517     {
11518       bfd_vma riprel;
11519
11520       for (i = 0; i < MAX_OPERANDS; ++i)
11521         op_txt[i] = op_out[i];
11522
11523       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11524         {
11525           op_ad = op_index[i];
11526           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11527           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11528           riprel = op_riprel[i];
11529           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11530           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11531         }
11532     }
11533   else
11534     {
11535       for (i = 0; i < MAX_OPERANDS; ++i)
11536         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11537     }
11538
11539   needcomma = 0;
11540   for (i = 0; i < MAX_OPERANDS; ++i)
11541     if (*op_txt[i])
11542       {
11543         if (needcomma)
11544           (*info->fprintf_func) (info->stream, ",");
11545         if (op_index[i] != -1 && !op_riprel[i])
11546           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11547         else
11548           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11549         needcomma = 1;
11550       }
11551
11552   for (i = 0; i < MAX_OPERANDS; i++)
11553     if (op_index[i] != -1 && op_riprel[i])
11554       {
11555         (*info->fprintf_func) (info->stream, "        # ");
11556         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11557                                                 + op_address[op_index[i]]), info);
11558         break;
11559       }
11560   return codep - priv.the_buffer;
11561 }
11562
11563 static const char *float_mem[] = {
11564   /* d8 */
11565   "fadd{s|}",
11566   "fmul{s|}",
11567   "fcom{s|}",
11568   "fcomp{s|}",
11569   "fsub{s|}",
11570   "fsubr{s|}",
11571   "fdiv{s|}",
11572   "fdivr{s|}",
11573   /* d9 */
11574   "fld{s|}",
11575   "(bad)",
11576   "fst{s|}",
11577   "fstp{s|}",
11578   "fldenvIC",
11579   "fldcw",
11580   "fNstenvIC",
11581   "fNstcw",
11582   /* da */
11583   "fiadd{l|}",
11584   "fimul{l|}",
11585   "ficom{l|}",
11586   "ficomp{l|}",
11587   "fisub{l|}",
11588   "fisubr{l|}",
11589   "fidiv{l|}",
11590   "fidivr{l|}",
11591   /* db */
11592   "fild{l|}",
11593   "fisttp{l|}",
11594   "fist{l|}",
11595   "fistp{l|}",
11596   "(bad)",
11597   "fld{t||t|}",
11598   "(bad)",
11599   "fstp{t||t|}",
11600   /* dc */
11601   "fadd{l|}",
11602   "fmul{l|}",
11603   "fcom{l|}",
11604   "fcomp{l|}",
11605   "fsub{l|}",
11606   "fsubr{l|}",
11607   "fdiv{l|}",
11608   "fdivr{l|}",
11609   /* dd */
11610   "fld{l|}",
11611   "fisttp{ll|}",
11612   "fst{l||}",
11613   "fstp{l|}",
11614   "frstorIC",
11615   "(bad)",
11616   "fNsaveIC",
11617   "fNstsw",
11618   /* de */
11619   "fiadd",
11620   "fimul",
11621   "ficom",
11622   "ficomp",
11623   "fisub",
11624   "fisubr",
11625   "fidiv",
11626   "fidivr",
11627   /* df */
11628   "fild",
11629   "fisttp",
11630   "fist",
11631   "fistp",
11632   "fbld",
11633   "fild{ll|}",
11634   "fbstp",
11635   "fistp{ll|}",
11636 };
11637
11638 static const unsigned char float_mem_mode[] = {
11639   /* d8 */
11640   d_mode,
11641   d_mode,
11642   d_mode,
11643   d_mode,
11644   d_mode,
11645   d_mode,
11646   d_mode,
11647   d_mode,
11648   /* d9 */
11649   d_mode,
11650   0,
11651   d_mode,
11652   d_mode,
11653   0,
11654   w_mode,
11655   0,
11656   w_mode,
11657   /* da */
11658   d_mode,
11659   d_mode,
11660   d_mode,
11661   d_mode,
11662   d_mode,
11663   d_mode,
11664   d_mode,
11665   d_mode,
11666   /* db */
11667   d_mode,
11668   d_mode,
11669   d_mode,
11670   d_mode,
11671   0,
11672   t_mode,
11673   0,
11674   t_mode,
11675   /* dc */
11676   q_mode,
11677   q_mode,
11678   q_mode,
11679   q_mode,
11680   q_mode,
11681   q_mode,
11682   q_mode,
11683   q_mode,
11684   /* dd */
11685   q_mode,
11686   q_mode,
11687   q_mode,
11688   q_mode,
11689   0,
11690   0,
11691   0,
11692   w_mode,
11693   /* de */
11694   w_mode,
11695   w_mode,
11696   w_mode,
11697   w_mode,
11698   w_mode,
11699   w_mode,
11700   w_mode,
11701   w_mode,
11702   /* df */
11703   w_mode,
11704   w_mode,
11705   w_mode,
11706   w_mode,
11707   t_mode,
11708   q_mode,
11709   t_mode,
11710   q_mode
11711 };
11712
11713 #define ST { OP_ST, 0 }
11714 #define STi { OP_STi, 0 }
11715
11716 #define FGRPd9_2 NULL, { { NULL, 0 } }
11717 #define FGRPd9_4 NULL, { { NULL, 1 } }
11718 #define FGRPd9_5 NULL, { { NULL, 2 } }
11719 #define FGRPd9_6 NULL, { { NULL, 3 } }
11720 #define FGRPd9_7 NULL, { { NULL, 4 } }
11721 #define FGRPda_5 NULL, { { NULL, 5 } }
11722 #define FGRPdb_4 NULL, { { NULL, 6 } }
11723 #define FGRPde_3 NULL, { { NULL, 7 } }
11724 #define FGRPdf_4 NULL, { { NULL, 8 } }
11725
11726 static const struct dis386 float_reg[][8] = {
11727   /* d8 */
11728   {
11729     { "fadd",   { ST, STi } },
11730     { "fmul",   { ST, STi } },
11731     { "fcom",   { STi } },
11732     { "fcomp",  { STi } },
11733     { "fsub",   { ST, STi } },
11734     { "fsubr",  { ST, STi } },
11735     { "fdiv",   { ST, STi } },
11736     { "fdivr",  { ST, STi } },
11737   },
11738   /* d9 */
11739   {
11740     { "fld",    { STi } },
11741     { "fxch",   { STi } },
11742     { FGRPd9_2 },
11743     { Bad_Opcode },
11744     { FGRPd9_4 },
11745     { FGRPd9_5 },
11746     { FGRPd9_6 },
11747     { FGRPd9_7 },
11748   },
11749   /* da */
11750   {
11751     { "fcmovb", { ST, STi } },
11752     { "fcmove", { ST, STi } },
11753     { "fcmovbe",{ ST, STi } },
11754     { "fcmovu", { ST, STi } },
11755     { Bad_Opcode },
11756     { FGRPda_5 },
11757     { Bad_Opcode },
11758     { Bad_Opcode },
11759   },
11760   /* db */
11761   {
11762     { "fcmovnb",{ ST, STi } },
11763     { "fcmovne",{ ST, STi } },
11764     { "fcmovnbe",{ ST, STi } },
11765     { "fcmovnu",{ ST, STi } },
11766     { FGRPdb_4 },
11767     { "fucomi", { ST, STi } },
11768     { "fcomi",  { ST, STi } },
11769     { Bad_Opcode },
11770   },
11771   /* dc */
11772   {
11773     { "fadd",   { STi, ST } },
11774     { "fmul",   { STi, ST } },
11775     { Bad_Opcode },
11776     { Bad_Opcode },
11777     { "fsub!M", { STi, ST } },
11778     { "fsubM",  { STi, ST } },
11779     { "fdiv!M", { STi, ST } },
11780     { "fdivM",  { STi, ST } },
11781   },
11782   /* dd */
11783   {
11784     { "ffree",  { STi } },
11785     { Bad_Opcode },
11786     { "fst",    { STi } },
11787     { "fstp",   { STi } },
11788     { "fucom",  { STi } },
11789     { "fucomp", { STi } },
11790     { Bad_Opcode },
11791     { Bad_Opcode },
11792   },
11793   /* de */
11794   {
11795     { "faddp",  { STi, ST } },
11796     { "fmulp",  { STi, ST } },
11797     { Bad_Opcode },
11798     { FGRPde_3 },
11799     { "fsub!Mp", { STi, ST } },
11800     { "fsubMp", { STi, ST } },
11801     { "fdiv!Mp", { STi, ST } },
11802     { "fdivMp", { STi, ST } },
11803   },
11804   /* df */
11805   {
11806     { "ffreep", { STi } },
11807     { Bad_Opcode },
11808     { Bad_Opcode },
11809     { Bad_Opcode },
11810     { FGRPdf_4 },
11811     { "fucomip", { ST, STi } },
11812     { "fcomip", { ST, STi } },
11813     { Bad_Opcode },
11814   },
11815 };
11816
11817 static char *fgrps[][8] = {
11818   /* d9_2  0 */
11819   {
11820     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11821   },
11822
11823   /* d9_4  1 */
11824   {
11825     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11826   },
11827
11828   /* d9_5  2 */
11829   {
11830     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11831   },
11832
11833   /* d9_6  3 */
11834   {
11835     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11836   },
11837
11838   /* d9_7  4 */
11839   {
11840     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11841   },
11842
11843   /* da_5  5 */
11844   {
11845     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11846   },
11847
11848   /* db_4  6 */
11849   {
11850     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11851     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11852   },
11853
11854   /* de_3  7 */
11855   {
11856     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11857   },
11858
11859   /* df_4  8 */
11860   {
11861     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11862   },
11863 };
11864
11865 static void
11866 swap_operand (void)
11867 {
11868   mnemonicendp[0] = '.';
11869   mnemonicendp[1] = 's';
11870   mnemonicendp += 2;
11871 }
11872
11873 static void
11874 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11875                int sizeflag ATTRIBUTE_UNUSED)
11876 {
11877   /* Skip mod/rm byte.  */
11878   MODRM_CHECK;
11879   codep++;
11880 }
11881
11882 static void
11883 dofloat (int sizeflag)
11884 {
11885   const struct dis386 *dp;
11886   unsigned char floatop;
11887
11888   floatop = codep[-1];
11889
11890   if (modrm.mod != 3)
11891     {
11892       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11893
11894       putop (float_mem[fp_indx], sizeflag);
11895       obufp = op_out[0];
11896       op_ad = 2;
11897       OP_E (float_mem_mode[fp_indx], sizeflag);
11898       return;
11899     }
11900   /* Skip mod/rm byte.  */
11901   MODRM_CHECK;
11902   codep++;
11903
11904   dp = &float_reg[floatop - 0xd8][modrm.reg];
11905   if (dp->name == NULL)
11906     {
11907       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11908
11909       /* Instruction fnstsw is only one with strange arg.  */
11910       if (floatop == 0xdf && codep[-1] == 0xe0)
11911         strcpy (op_out[0], names16[0]);
11912     }
11913   else
11914     {
11915       putop (dp->name, sizeflag);
11916
11917       obufp = op_out[0];
11918       op_ad = 2;
11919       if (dp->op[0].rtn)
11920         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
11921
11922       obufp = op_out[1];
11923       op_ad = 1;
11924       if (dp->op[1].rtn)
11925         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
11926     }
11927 }
11928
11929 static void
11930 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11931 {
11932   oappend ("%st" + intel_syntax);
11933 }
11934
11935 static void
11936 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11937 {
11938   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
11939   oappend (scratchbuf + intel_syntax);
11940 }
11941
11942 /* Capital letters in template are macros.  */
11943 static int
11944 putop (const char *in_template, int sizeflag)
11945 {
11946   const char *p;
11947   int alt = 0;
11948   int cond = 1;
11949   unsigned int l = 0, len = 1;
11950   char last[4];
11951
11952 #define SAVE_LAST(c)                    \
11953   if (l < len && l < sizeof (last))     \
11954     last[l++] = c;                      \
11955   else                                  \
11956     abort ();
11957
11958   for (p = in_template; *p; p++)
11959     {
11960       switch (*p)
11961         {
11962         default:
11963           *obufp++ = *p;
11964           break;
11965         case '%':
11966           len++;
11967           break;
11968         case '!':
11969           cond = 0;
11970           break;
11971         case '{':
11972           alt = 0;
11973           if (intel_syntax)
11974             {
11975               while (*++p != '|')
11976                 if (*p == '}' || *p == '\0')
11977                   abort ();
11978             }
11979           /* Fall through.  */
11980         case 'I':
11981           alt = 1;
11982           continue;
11983         case '|':
11984           while (*++p != '}')
11985             {
11986               if (*p == '\0')
11987                 abort ();
11988             }
11989           break;
11990         case '}':
11991           break;
11992         case 'A':
11993           if (intel_syntax)
11994             break;
11995           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11996             *obufp++ = 'b';
11997           break;
11998         case 'B':
11999           if (l == 0 && len == 1)
12000             {
12001 case_B:
12002               if (intel_syntax)
12003                 break;
12004               if (sizeflag & SUFFIX_ALWAYS)
12005                 *obufp++ = 'b';
12006             }
12007           else
12008             {
12009               if (l != 1
12010                   || len != 2
12011                   || last[0] != 'L')
12012                 {
12013                   SAVE_LAST (*p);
12014                   break;
12015                 }
12016
12017               if (address_mode == mode_64bit
12018                   && !(prefixes & PREFIX_ADDR))
12019                 {
12020                   *obufp++ = 'a';
12021                   *obufp++ = 'b';
12022                   *obufp++ = 's';
12023                 }
12024
12025               goto case_B;
12026             }
12027           break;
12028         case 'C':
12029           if (intel_syntax && !alt)
12030             break;
12031           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12032             {
12033               if (sizeflag & DFLAG)
12034                 *obufp++ = intel_syntax ? 'd' : 'l';
12035               else
12036                 *obufp++ = intel_syntax ? 'w' : 's';
12037               used_prefixes |= (prefixes & PREFIX_DATA);
12038             }
12039           break;
12040         case 'D':
12041           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12042             break;
12043           USED_REX (REX_W);
12044           if (modrm.mod == 3)
12045             {
12046               if (rex & REX_W)
12047                 *obufp++ = 'q';
12048               else
12049                 {
12050                   if (sizeflag & DFLAG)
12051                     *obufp++ = intel_syntax ? 'd' : 'l';
12052                   else
12053                     *obufp++ = 'w';
12054                   used_prefixes |= (prefixes & PREFIX_DATA);
12055                 }
12056             }
12057           else
12058             *obufp++ = 'w';
12059           break;
12060         case 'E':               /* For jcxz/jecxz */
12061           if (address_mode == mode_64bit)
12062             {
12063               if (sizeflag & AFLAG)
12064                 *obufp++ = 'r';
12065               else
12066                 *obufp++ = 'e';
12067             }
12068           else
12069             if (sizeflag & AFLAG)
12070               *obufp++ = 'e';
12071           used_prefixes |= (prefixes & PREFIX_ADDR);
12072           break;
12073         case 'F':
12074           if (intel_syntax)
12075             break;
12076           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12077             {
12078               if (sizeflag & AFLAG)
12079                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12080               else
12081                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12082               used_prefixes |= (prefixes & PREFIX_ADDR);
12083             }
12084           break;
12085         case 'G':
12086           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12087             break;
12088           if ((rex & REX_W) || (sizeflag & DFLAG))
12089             *obufp++ = 'l';
12090           else
12091             *obufp++ = 'w';
12092           if (!(rex & REX_W))
12093             used_prefixes |= (prefixes & PREFIX_DATA);
12094           break;
12095         case 'H':
12096           if (intel_syntax)
12097             break;
12098           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12099               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12100             {
12101               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12102               *obufp++ = ',';
12103               *obufp++ = 'p';
12104               if (prefixes & PREFIX_DS)
12105                 *obufp++ = 't';
12106               else
12107                 *obufp++ = 'n';
12108             }
12109           break;
12110         case 'J':
12111           if (intel_syntax)
12112             break;
12113           *obufp++ = 'l';
12114           break;
12115         case 'K':
12116           USED_REX (REX_W);
12117           if (rex & REX_W)
12118             *obufp++ = 'q';
12119           else
12120             *obufp++ = 'd';
12121           break;
12122         case 'Z':
12123           if (intel_syntax)
12124             break;
12125           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12126             {
12127               *obufp++ = 'q';
12128               break;
12129             }
12130           /* Fall through.  */
12131           goto case_L;
12132         case 'L':
12133           if (l != 0 || len != 1)
12134             {
12135               SAVE_LAST (*p);
12136               break;
12137             }
12138 case_L:
12139           if (intel_syntax)
12140             break;
12141           if (sizeflag & SUFFIX_ALWAYS)
12142             *obufp++ = 'l';
12143           break;
12144         case 'M':
12145           if (intel_mnemonic != cond)
12146             *obufp++ = 'r';
12147           break;
12148         case 'N':
12149           if ((prefixes & PREFIX_FWAIT) == 0)
12150             *obufp++ = 'n';
12151           else
12152             used_prefixes |= PREFIX_FWAIT;
12153           break;
12154         case 'O':
12155           USED_REX (REX_W);
12156           if (rex & REX_W)
12157             *obufp++ = 'o';
12158           else if (intel_syntax && (sizeflag & DFLAG))
12159             *obufp++ = 'q';
12160           else
12161             *obufp++ = 'd';
12162           if (!(rex & REX_W))
12163             used_prefixes |= (prefixes & PREFIX_DATA);
12164           break;
12165         case 'T':
12166           if (intel_syntax)
12167             break;
12168           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12169             {
12170               *obufp++ = 'q';
12171               break;
12172             }
12173           /* Fall through.  */
12174         case 'P':
12175           if (intel_syntax)
12176             break;
12177           if ((prefixes & PREFIX_DATA)
12178               || (rex & REX_W)
12179               || (sizeflag & SUFFIX_ALWAYS))
12180             {
12181               USED_REX (REX_W);
12182               if (rex & REX_W)
12183                 *obufp++ = 'q';
12184               else
12185                 {
12186                    if (sizeflag & DFLAG)
12187                       *obufp++ = 'l';
12188                    else
12189                      *obufp++ = 'w';
12190                    used_prefixes |= (prefixes & PREFIX_DATA);
12191                 }
12192             }
12193           break;
12194         case 'U':
12195           if (intel_syntax)
12196             break;
12197           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12198             {
12199               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12200                 *obufp++ = 'q';
12201               break;
12202             }
12203           /* Fall through.  */
12204           goto case_Q;
12205         case 'Q':
12206           if (l == 0 && len == 1)
12207             {
12208 case_Q:
12209               if (intel_syntax && !alt)
12210                 break;
12211               USED_REX (REX_W);
12212               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12213                 {
12214                   if (rex & REX_W)
12215                     *obufp++ = 'q';
12216                   else
12217                     {
12218                       if (sizeflag & DFLAG)
12219                         *obufp++ = intel_syntax ? 'd' : 'l';
12220                       else
12221                         *obufp++ = 'w';
12222                       used_prefixes |= (prefixes & PREFIX_DATA);
12223                     }
12224                 }
12225             }
12226           else
12227             {
12228               if (l != 1 || len != 2 || last[0] != 'L')
12229                 {
12230                   SAVE_LAST (*p);
12231                   break;
12232                 }
12233               if (intel_syntax
12234                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12235                 break;
12236               if ((rex & REX_W))
12237                 {
12238                   USED_REX (REX_W);
12239                   *obufp++ = 'q';
12240                 }
12241               else
12242                 *obufp++ = 'l';
12243             }
12244           break;
12245         case 'R':
12246           USED_REX (REX_W);
12247           if (rex & REX_W)
12248             *obufp++ = 'q';
12249           else if (sizeflag & DFLAG)
12250             {
12251               if (intel_syntax)
12252                   *obufp++ = 'd';
12253               else
12254                   *obufp++ = 'l';
12255             }
12256           else
12257             *obufp++ = 'w';
12258           if (intel_syntax && !p[1]
12259               && ((rex & REX_W) || (sizeflag & DFLAG)))
12260             *obufp++ = 'e';
12261           if (!(rex & REX_W))
12262             used_prefixes |= (prefixes & PREFIX_DATA);
12263           break;
12264         case 'V':
12265           if (l == 0 && len == 1)
12266             {
12267               if (intel_syntax)
12268                 break;
12269               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12270                 {
12271                   if (sizeflag & SUFFIX_ALWAYS)
12272                     *obufp++ = 'q';
12273                   break;
12274                 }
12275             }
12276           else
12277             {
12278               if (l != 1
12279                   || len != 2
12280                   || last[0] != 'L')
12281                 {
12282                   SAVE_LAST (*p);
12283                   break;
12284                 }
12285
12286               if (rex & REX_W)
12287                 {
12288                   *obufp++ = 'a';
12289                   *obufp++ = 'b';
12290                   *obufp++ = 's';
12291                 }
12292             }
12293           /* Fall through.  */
12294           goto case_S;
12295         case 'S':
12296           if (l == 0 && len == 1)
12297             {
12298 case_S:
12299               if (intel_syntax)
12300                 break;
12301               if (sizeflag & SUFFIX_ALWAYS)
12302                 {
12303                   if (rex & REX_W)
12304                     *obufp++ = 'q';
12305                   else
12306                     {
12307                       if (sizeflag & DFLAG)
12308                         *obufp++ = 'l';
12309                       else
12310                         *obufp++ = 'w';
12311                       used_prefixes |= (prefixes & PREFIX_DATA);
12312                     }
12313                 }
12314             }
12315           else
12316             {
12317               if (l != 1
12318                   || len != 2
12319                   || last[0] != 'L')
12320                 {
12321                   SAVE_LAST (*p);
12322                   break;
12323                 }
12324
12325               if (address_mode == mode_64bit
12326                   && !(prefixes & PREFIX_ADDR))
12327                 {
12328                   *obufp++ = 'a';
12329                   *obufp++ = 'b';
12330                   *obufp++ = 's';
12331                 }
12332
12333               goto case_S;
12334             }
12335           break;
12336         case 'X':
12337           if (l != 0 || len != 1)
12338             {
12339               SAVE_LAST (*p);
12340               break;
12341             }
12342           if (need_vex && vex.prefix)
12343             {
12344               if (vex.prefix == DATA_PREFIX_OPCODE)
12345                 *obufp++ = 'd';
12346               else
12347                 *obufp++ = 's';
12348             }
12349           else
12350             {
12351               if (prefixes & PREFIX_DATA)
12352                 *obufp++ = 'd';
12353               else
12354                 *obufp++ = 's';
12355               used_prefixes |= (prefixes & PREFIX_DATA);
12356             }
12357           break;
12358         case 'Y':
12359           if (l == 0 && len == 1)
12360             {
12361               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12362                 break;
12363               if (rex & REX_W)
12364                 {
12365                   USED_REX (REX_W);
12366                   *obufp++ = 'q';
12367                 }
12368               break;
12369             }
12370           else
12371             {
12372               if (l != 1 || len != 2 || last[0] != 'X')
12373                 {
12374                   SAVE_LAST (*p);
12375                   break;
12376                 }
12377               if (!need_vex)
12378                 abort ();
12379               if (intel_syntax
12380                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12381                 break;
12382               switch (vex.length)
12383                 {
12384                 case 128:
12385                   *obufp++ = 'x';
12386                   break;
12387                 case 256:
12388                   *obufp++ = 'y';
12389                   break;
12390                 default:
12391                   abort ();
12392                 }
12393             }
12394           break;
12395         case 'W':
12396           if (l == 0 && len == 1)
12397             {
12398               /* operand size flag for cwtl, cbtw */
12399               USED_REX (REX_W);
12400               if (rex & REX_W)
12401                 {
12402                   if (intel_syntax)
12403                     *obufp++ = 'd';
12404                   else
12405                     *obufp++ = 'l';
12406                 }
12407               else if (sizeflag & DFLAG)
12408                 *obufp++ = 'w';
12409               else
12410                 *obufp++ = 'b';
12411               if (!(rex & REX_W))
12412                 used_prefixes |= (prefixes & PREFIX_DATA);
12413             }
12414           else
12415             {
12416               if (l != 1 || len != 2 || last[0] != 'X')
12417                 {
12418                   SAVE_LAST (*p);
12419                   break;
12420                 }
12421               if (!need_vex)
12422                 abort ();
12423               *obufp++ = vex.w ? 'd': 's';
12424             }
12425           break;
12426         }
12427       alt = 0;
12428     }
12429   *obufp = 0;
12430   mnemonicendp = obufp;
12431   return 0;
12432 }
12433
12434 static void
12435 oappend (const char *s)
12436 {
12437   obufp = stpcpy (obufp, s);
12438 }
12439
12440 static void
12441 append_seg (void)
12442 {
12443   if (prefixes & PREFIX_CS)
12444     {
12445       used_prefixes |= PREFIX_CS;
12446       oappend ("%cs:" + intel_syntax);
12447     }
12448   if (prefixes & PREFIX_DS)
12449     {
12450       used_prefixes |= PREFIX_DS;
12451       oappend ("%ds:" + intel_syntax);
12452     }
12453   if (prefixes & PREFIX_SS)
12454     {
12455       used_prefixes |= PREFIX_SS;
12456       oappend ("%ss:" + intel_syntax);
12457     }
12458   if (prefixes & PREFIX_ES)
12459     {
12460       used_prefixes |= PREFIX_ES;
12461       oappend ("%es:" + intel_syntax);
12462     }
12463   if (prefixes & PREFIX_FS)
12464     {
12465       used_prefixes |= PREFIX_FS;
12466       oappend ("%fs:" + intel_syntax);
12467     }
12468   if (prefixes & PREFIX_GS)
12469     {
12470       used_prefixes |= PREFIX_GS;
12471       oappend ("%gs:" + intel_syntax);
12472     }
12473 }
12474
12475 static void
12476 OP_indirE (int bytemode, int sizeflag)
12477 {
12478   if (!intel_syntax)
12479     oappend ("*");
12480   OP_E (bytemode, sizeflag);
12481 }
12482
12483 static void
12484 print_operand_value (char *buf, int hex, bfd_vma disp)
12485 {
12486   if (address_mode == mode_64bit)
12487     {
12488       if (hex)
12489         {
12490           char tmp[30];
12491           int i;
12492           buf[0] = '0';
12493           buf[1] = 'x';
12494           sprintf_vma (tmp, disp);
12495           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12496           strcpy (buf + 2, tmp + i);
12497         }
12498       else
12499         {
12500           bfd_signed_vma v = disp;
12501           char tmp[30];
12502           int i;
12503           if (v < 0)
12504             {
12505               *(buf++) = '-';
12506               v = -disp;
12507               /* Check for possible overflow on 0x8000000000000000.  */
12508               if (v < 0)
12509                 {
12510                   strcpy (buf, "9223372036854775808");
12511                   return;
12512                 }
12513             }
12514           if (!v)
12515             {
12516               strcpy (buf, "0");
12517               return;
12518             }
12519
12520           i = 0;
12521           tmp[29] = 0;
12522           while (v)
12523             {
12524               tmp[28 - i] = (v % 10) + '0';
12525               v /= 10;
12526               i++;
12527             }
12528           strcpy (buf, tmp + 29 - i);
12529         }
12530     }
12531   else
12532     {
12533       if (hex)
12534         sprintf (buf, "0x%x", (unsigned int) disp);
12535       else
12536         sprintf (buf, "%d", (int) disp);
12537     }
12538 }
12539
12540 /* Put DISP in BUF as signed hex number.  */
12541
12542 static void
12543 print_displacement (char *buf, bfd_vma disp)
12544 {
12545   bfd_signed_vma val = disp;
12546   char tmp[30];
12547   int i, j = 0;
12548
12549   if (val < 0)
12550     {
12551       buf[j++] = '-';
12552       val = -disp;
12553
12554       /* Check for possible overflow.  */
12555       if (val < 0)
12556         {
12557           switch (address_mode)
12558             {
12559             case mode_64bit:
12560               strcpy (buf + j, "0x8000000000000000");
12561               break;
12562             case mode_32bit:
12563               strcpy (buf + j, "0x80000000");
12564               break;
12565             case mode_16bit:
12566               strcpy (buf + j, "0x8000");
12567               break;
12568             }
12569           return;
12570         }
12571     }
12572
12573   buf[j++] = '0';
12574   buf[j++] = 'x';
12575
12576   sprintf_vma (tmp, (bfd_vma) val);
12577   for (i = 0; tmp[i] == '0'; i++)
12578     continue;
12579   if (tmp[i] == '\0')
12580     i--;
12581   strcpy (buf + j, tmp + i);
12582 }
12583
12584 static void
12585 intel_operand_size (int bytemode, int sizeflag)
12586 {
12587   switch (bytemode)
12588     {
12589     case b_mode:
12590     case b_swap_mode:
12591     case dqb_mode:
12592       oappend ("BYTE PTR ");
12593       break;
12594     case w_mode:
12595     case dqw_mode:
12596       oappend ("WORD PTR ");
12597       break;
12598     case stack_v_mode:
12599       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12600         {
12601           oappend ("QWORD PTR ");
12602           break;
12603         }
12604       /* FALLTHRU */
12605     case v_mode:
12606     case v_swap_mode:
12607     case dq_mode:
12608       USED_REX (REX_W);
12609       if (rex & REX_W)
12610         oappend ("QWORD PTR ");
12611       else
12612         {
12613           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12614             oappend ("DWORD PTR ");
12615           else
12616             oappend ("WORD PTR ");
12617           used_prefixes |= (prefixes & PREFIX_DATA);
12618         }
12619       break;
12620     case z_mode:
12621       if ((rex & REX_W) || (sizeflag & DFLAG))
12622         *obufp++ = 'D';
12623       oappend ("WORD PTR ");
12624       if (!(rex & REX_W))
12625         used_prefixes |= (prefixes & PREFIX_DATA);
12626       break;
12627     case a_mode:
12628       if (sizeflag & DFLAG)
12629         oappend ("QWORD PTR ");
12630       else
12631         oappend ("DWORD PTR ");
12632       used_prefixes |= (prefixes & PREFIX_DATA);
12633       break;
12634     case d_mode:
12635     case d_swap_mode:
12636     case dqd_mode:
12637       oappend ("DWORD PTR ");
12638       break;
12639     case q_mode:
12640     case q_swap_mode:
12641       oappend ("QWORD PTR ");
12642       break;
12643     case m_mode:
12644       if (address_mode == mode_64bit)
12645         oappend ("QWORD PTR ");
12646       else
12647         oappend ("DWORD PTR ");
12648       break;
12649     case f_mode:
12650       if (sizeflag & DFLAG)
12651         oappend ("FWORD PTR ");
12652       else
12653         oappend ("DWORD PTR ");
12654       used_prefixes |= (prefixes & PREFIX_DATA);
12655       break;
12656     case t_mode:
12657       oappend ("TBYTE PTR ");
12658       break;
12659     case x_mode:
12660     case x_swap_mode:
12661       if (need_vex)
12662         {
12663           switch (vex.length)
12664             {
12665             case 128:
12666               oappend ("XMMWORD PTR ");
12667               break;
12668             case 256:
12669               oappend ("YMMWORD PTR ");
12670               break;
12671             default:
12672               abort ();
12673             }
12674         }
12675       else
12676         oappend ("XMMWORD PTR ");
12677       break;
12678     case xmm_mode:
12679       oappend ("XMMWORD PTR ");
12680       break;
12681     case xmmq_mode:
12682       if (!need_vex)
12683         abort ();
12684
12685       switch (vex.length)
12686         {
12687         case 128:
12688           oappend ("QWORD PTR ");
12689           break;
12690         case 256:
12691           oappend ("XMMWORD PTR ");
12692           break;
12693         default:
12694           abort ();
12695         }
12696       break;
12697     case ymmq_mode:
12698       if (!need_vex)
12699         abort ();
12700
12701       switch (vex.length)
12702         {
12703         case 128:
12704           oappend ("QWORD PTR ");
12705           break;
12706         case 256:
12707           oappend ("YMMWORD PTR ");
12708           break;
12709         default:
12710           abort ();
12711         }
12712       break;
12713     case o_mode:
12714       oappend ("OWORD PTR ");
12715       break;
12716     case vex_w_dq_mode:
12717       if (!need_vex)
12718         abort ();
12719
12720       if (vex.w)
12721         oappend ("QWORD PTR ");
12722       else
12723         oappend ("DWORD PTR ");
12724       break;
12725     default:
12726       break;
12727     }
12728 }
12729
12730 static void
12731 OP_E_register (int bytemode, int sizeflag)
12732 {
12733   int reg = modrm.rm;
12734   const char **names;
12735
12736   USED_REX (REX_B);
12737   if ((rex & REX_B))
12738     reg += 8;
12739
12740   if ((sizeflag & SUFFIX_ALWAYS)
12741       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12742     swap_operand ();
12743
12744   switch (bytemode)
12745     {
12746     case b_mode:
12747     case b_swap_mode:
12748       USED_REX (0);
12749       if (rex)
12750         names = names8rex;
12751       else
12752         names = names8;
12753       break;
12754     case w_mode:
12755       names = names16;
12756       break;
12757     case d_mode:
12758       names = names32;
12759       break;
12760     case q_mode:
12761       names = names64;
12762       break;
12763     case m_mode:
12764       names = address_mode == mode_64bit ? names64 : names32;
12765       break;
12766     case stack_v_mode:
12767       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12768         {
12769           names = names64;
12770           break;
12771         }
12772       bytemode = v_mode;
12773       /* FALLTHRU */
12774     case v_mode:
12775     case v_swap_mode:
12776     case dq_mode:
12777     case dqb_mode:
12778     case dqd_mode:
12779     case dqw_mode:
12780       USED_REX (REX_W);
12781       if (rex & REX_W)
12782         names = names64;
12783       else
12784         {
12785           if ((sizeflag & DFLAG)
12786               || (bytemode != v_mode
12787                   && bytemode != v_swap_mode))
12788             names = names32;
12789           else
12790             names = names16;
12791           used_prefixes |= (prefixes & PREFIX_DATA);
12792         }
12793       break;
12794     case 0:
12795       return;
12796     default:
12797       oappend (INTERNAL_DISASSEMBLER_ERROR);
12798       return;
12799     }
12800   oappend (names[reg]);
12801 }
12802
12803 static void
12804 OP_E_memory (int bytemode, int sizeflag)
12805 {
12806   bfd_vma disp = 0;
12807   int add = (rex & REX_B) ? 8 : 0;
12808   int riprel = 0;
12809
12810   USED_REX (REX_B);
12811   if (intel_syntax)
12812     intel_operand_size (bytemode, sizeflag);
12813   append_seg ();
12814
12815   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12816     {
12817       /* 32/64 bit address mode */
12818       int havedisp;
12819       int havesib;
12820       int havebase;
12821       int haveindex;
12822       int needindex;
12823       int base, rbase;
12824       int vindex = 0;
12825       int scale = 0;
12826
12827       havesib = 0;
12828       havebase = 1;
12829       haveindex = 0;
12830       base = modrm.rm;
12831
12832       if (base == 4)
12833         {
12834           havesib = 1;
12835           FETCH_DATA (the_info, codep + 1);
12836           vindex = (*codep >> 3) & 7;
12837           scale = (*codep >> 6) & 3;
12838           base = *codep & 7;
12839           USED_REX (REX_X);
12840           if (rex & REX_X)
12841             vindex += 8;
12842           haveindex = vindex != 4;
12843           codep++;
12844         }
12845       rbase = base + add;
12846
12847       switch (modrm.mod)
12848         {
12849         case 0:
12850           if (base == 5)
12851             {
12852               havebase = 0;
12853               if (address_mode == mode_64bit && !havesib)
12854                 riprel = 1;
12855               disp = get32s ();
12856             }
12857           break;
12858         case 1:
12859           FETCH_DATA (the_info, codep + 1);
12860           disp = *codep++;
12861           if ((disp & 0x80) != 0)
12862             disp -= 0x100;
12863           break;
12864         case 2:
12865           disp = get32s ();
12866           break;
12867         }
12868
12869       /* In 32bit mode, we need index register to tell [offset] from
12870          [eiz*1 + offset].  */
12871       needindex = (havesib
12872                    && !havebase
12873                    && !haveindex
12874                    && address_mode == mode_32bit);
12875       havedisp = (havebase
12876                   || needindex
12877                   || (havesib && (haveindex || scale != 0)));
12878
12879       if (!intel_syntax)
12880         if (modrm.mod != 0 || base == 5)
12881           {
12882             if (havedisp || riprel)
12883               print_displacement (scratchbuf, disp);
12884             else
12885               print_operand_value (scratchbuf, 1, disp);
12886             oappend (scratchbuf);
12887             if (riprel)
12888               {
12889                 set_op (disp, 1);
12890                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
12891               }
12892           }
12893
12894       if (havebase || haveindex || riprel)
12895         used_prefixes |= PREFIX_ADDR;
12896
12897       if (havedisp || (intel_syntax && riprel))
12898         {
12899           *obufp++ = open_char;
12900           if (intel_syntax && riprel)
12901             {
12902               set_op (disp, 1);
12903               oappend (sizeflag & AFLAG ? "rip" : "eip");
12904             }
12905           *obufp = '\0';
12906           if (havebase)
12907             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
12908                      ? names64[rbase] : names32[rbase]);
12909           if (havesib)
12910             {
12911               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12912                  print index to tell base + index from base.  */
12913               if (scale != 0
12914                   || needindex
12915                   || haveindex
12916                   || (havebase && base != ESP_REG_NUM))
12917                 {
12918                   if (!intel_syntax || havebase)
12919                     {
12920                       *obufp++ = separator_char;
12921                       *obufp = '\0';
12922                     }
12923                   if (haveindex)
12924                     oappend (address_mode == mode_64bit
12925                              && (sizeflag & AFLAG)
12926                              ? names64[vindex] : names32[vindex]);
12927                   else
12928                     oappend (address_mode == mode_64bit
12929                              && (sizeflag & AFLAG)
12930                              ? index64 : index32);
12931
12932                   *obufp++ = scale_char;
12933                   *obufp = '\0';
12934                   sprintf (scratchbuf, "%d", 1 << scale);
12935                   oappend (scratchbuf);
12936                 }
12937             }
12938           if (intel_syntax
12939               && (disp || modrm.mod != 0 || base == 5))
12940             {
12941               if (!havedisp || (bfd_signed_vma) disp >= 0)
12942                 {
12943                   *obufp++ = '+';
12944                   *obufp = '\0';
12945                 }
12946               else if (modrm.mod != 1 && disp != -disp)
12947                 {
12948                   *obufp++ = '-';
12949                   *obufp = '\0';
12950                   disp = - (bfd_signed_vma) disp;
12951                 }
12952
12953               if (havedisp)
12954                 print_displacement (scratchbuf, disp);
12955               else
12956                 print_operand_value (scratchbuf, 1, disp);
12957               oappend (scratchbuf);
12958             }
12959
12960           *obufp++ = close_char;
12961           *obufp = '\0';
12962         }
12963       else if (intel_syntax)
12964         {
12965           if (modrm.mod != 0 || base == 5)
12966             {
12967               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12968                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
12969                 ;
12970               else
12971                 {
12972                   oappend (names_seg[ds_reg - es_reg]);
12973                   oappend (":");
12974                 }
12975               print_operand_value (scratchbuf, 1, disp);
12976               oappend (scratchbuf);
12977             }
12978         }
12979     }
12980   else
12981     {
12982       /* 16 bit address mode */
12983       used_prefixes |= prefixes & PREFIX_ADDR;
12984       switch (modrm.mod)
12985         {
12986         case 0:
12987           if (modrm.rm == 6)
12988             {
12989               disp = get16 ();
12990               if ((disp & 0x8000) != 0)
12991                 disp -= 0x10000;
12992             }
12993           break;
12994         case 1:
12995           FETCH_DATA (the_info, codep + 1);
12996           disp = *codep++;
12997           if ((disp & 0x80) != 0)
12998             disp -= 0x100;
12999           break;
13000         case 2:
13001           disp = get16 ();
13002           if ((disp & 0x8000) != 0)
13003             disp -= 0x10000;
13004           break;
13005         }
13006
13007       if (!intel_syntax)
13008         if (modrm.mod != 0 || modrm.rm == 6)
13009           {
13010             print_displacement (scratchbuf, disp);
13011             oappend (scratchbuf);
13012           }
13013
13014       if (modrm.mod != 0 || modrm.rm != 6)
13015         {
13016           *obufp++ = open_char;
13017           *obufp = '\0';
13018           oappend (index16[modrm.rm]);
13019           if (intel_syntax
13020               && (disp || modrm.mod != 0 || modrm.rm == 6))
13021             {
13022               if ((bfd_signed_vma) disp >= 0)
13023                 {
13024                   *obufp++ = '+';
13025                   *obufp = '\0';
13026                 }
13027               else if (modrm.mod != 1)
13028                 {
13029                   *obufp++ = '-';
13030                   *obufp = '\0';
13031                   disp = - (bfd_signed_vma) disp;
13032                 }
13033
13034               print_displacement (scratchbuf, disp);
13035               oappend (scratchbuf);
13036             }
13037
13038           *obufp++ = close_char;
13039           *obufp = '\0';
13040         }
13041       else if (intel_syntax)
13042         {
13043           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13044                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13045             ;
13046           else
13047             {
13048               oappend (names_seg[ds_reg - es_reg]);
13049               oappend (":");
13050             }
13051           print_operand_value (scratchbuf, 1, disp & 0xffff);
13052           oappend (scratchbuf);
13053         }
13054     }
13055 }
13056
13057 static void
13058 OP_E (int bytemode, int sizeflag)
13059 {
13060   /* Skip mod/rm byte.  */
13061   MODRM_CHECK;
13062   codep++;
13063
13064   if (modrm.mod == 3)
13065     OP_E_register (bytemode, sizeflag);
13066   else
13067     OP_E_memory (bytemode, sizeflag);
13068 }
13069
13070 static void
13071 OP_G (int bytemode, int sizeflag)
13072 {
13073   int add = 0;
13074   USED_REX (REX_R);
13075   if (rex & REX_R)
13076     add += 8;
13077   switch (bytemode)
13078     {
13079     case b_mode:
13080       USED_REX (0);
13081       if (rex)
13082         oappend (names8rex[modrm.reg + add]);
13083       else
13084         oappend (names8[modrm.reg + add]);
13085       break;
13086     case w_mode:
13087       oappend (names16[modrm.reg + add]);
13088       break;
13089     case d_mode:
13090       oappend (names32[modrm.reg + add]);
13091       break;
13092     case q_mode:
13093       oappend (names64[modrm.reg + add]);
13094       break;
13095     case v_mode:
13096     case dq_mode:
13097     case dqb_mode:
13098     case dqd_mode:
13099     case dqw_mode:
13100       USED_REX (REX_W);
13101       if (rex & REX_W)
13102         oappend (names64[modrm.reg + add]);
13103       else
13104         {
13105           if ((sizeflag & DFLAG) || bytemode != v_mode)
13106             oappend (names32[modrm.reg + add]);
13107           else
13108             oappend (names16[modrm.reg + add]);
13109           used_prefixes |= (prefixes & PREFIX_DATA);
13110         }
13111       break;
13112     case m_mode:
13113       if (address_mode == mode_64bit)
13114         oappend (names64[modrm.reg + add]);
13115       else
13116         oappend (names32[modrm.reg + add]);
13117       break;
13118     default:
13119       oappend (INTERNAL_DISASSEMBLER_ERROR);
13120       break;
13121     }
13122 }
13123
13124 static bfd_vma
13125 get64 (void)
13126 {
13127   bfd_vma x;
13128 #ifdef BFD64
13129   unsigned int a;
13130   unsigned int b;
13131
13132   FETCH_DATA (the_info, codep + 8);
13133   a = *codep++ & 0xff;
13134   a |= (*codep++ & 0xff) << 8;
13135   a |= (*codep++ & 0xff) << 16;
13136   a |= (*codep++ & 0xff) << 24;
13137   b = *codep++ & 0xff;
13138   b |= (*codep++ & 0xff) << 8;
13139   b |= (*codep++ & 0xff) << 16;
13140   b |= (*codep++ & 0xff) << 24;
13141   x = a + ((bfd_vma) b << 32);
13142 #else
13143   abort ();
13144   x = 0;
13145 #endif
13146   return x;
13147 }
13148
13149 static bfd_signed_vma
13150 get32 (void)
13151 {
13152   bfd_signed_vma x = 0;
13153
13154   FETCH_DATA (the_info, codep + 4);
13155   x = *codep++ & (bfd_signed_vma) 0xff;
13156   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13157   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13158   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13159   return x;
13160 }
13161
13162 static bfd_signed_vma
13163 get32s (void)
13164 {
13165   bfd_signed_vma x = 0;
13166
13167   FETCH_DATA (the_info, codep + 4);
13168   x = *codep++ & (bfd_signed_vma) 0xff;
13169   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13170   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13171   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13172
13173   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13174
13175   return x;
13176 }
13177
13178 static int
13179 get16 (void)
13180 {
13181   int x = 0;
13182
13183   FETCH_DATA (the_info, codep + 2);
13184   x = *codep++ & 0xff;
13185   x |= (*codep++ & 0xff) << 8;
13186   return x;
13187 }
13188
13189 static void
13190 set_op (bfd_vma op, int riprel)
13191 {
13192   op_index[op_ad] = op_ad;
13193   if (address_mode == mode_64bit)
13194     {
13195       op_address[op_ad] = op;
13196       op_riprel[op_ad] = riprel;
13197     }
13198   else
13199     {
13200       /* Mask to get a 32-bit address.  */
13201       op_address[op_ad] = op & 0xffffffff;
13202       op_riprel[op_ad] = riprel & 0xffffffff;
13203     }
13204 }
13205
13206 static void
13207 OP_REG (int code, int sizeflag)
13208 {
13209   const char *s;
13210   int add;
13211   USED_REX (REX_B);
13212   if (rex & REX_B)
13213     add = 8;
13214   else
13215     add = 0;
13216
13217   switch (code)
13218     {
13219     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13220     case sp_reg: case bp_reg: case si_reg: case di_reg:
13221       s = names16[code - ax_reg + add];
13222       break;
13223     case es_reg: case ss_reg: case cs_reg:
13224     case ds_reg: case fs_reg: case gs_reg:
13225       s = names_seg[code - es_reg + add];
13226       break;
13227     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13228     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13229       USED_REX (0);
13230       if (rex)
13231         s = names8rex[code - al_reg + add];
13232       else
13233         s = names8[code - al_reg];
13234       break;
13235     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13236     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13237       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13238         {
13239           s = names64[code - rAX_reg + add];
13240           break;
13241         }
13242       code += eAX_reg - rAX_reg;
13243       /* Fall through.  */
13244     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13245     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13246       USED_REX (REX_W);
13247       if (rex & REX_W)
13248         s = names64[code - eAX_reg + add];
13249       else
13250         {
13251           if (sizeflag & DFLAG)
13252             s = names32[code - eAX_reg + add];
13253           else
13254             s = names16[code - eAX_reg + add];
13255           used_prefixes |= (prefixes & PREFIX_DATA);
13256         }
13257       break;
13258     default:
13259       s = INTERNAL_DISASSEMBLER_ERROR;
13260       break;
13261     }
13262   oappend (s);
13263 }
13264
13265 static void
13266 OP_IMREG (int code, int sizeflag)
13267 {
13268   const char *s;
13269
13270   switch (code)
13271     {
13272     case indir_dx_reg:
13273       if (intel_syntax)
13274         s = "dx";
13275       else
13276         s = "(%dx)";
13277       break;
13278     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13279     case sp_reg: case bp_reg: case si_reg: case di_reg:
13280       s = names16[code - ax_reg];
13281       break;
13282     case es_reg: case ss_reg: case cs_reg:
13283     case ds_reg: case fs_reg: case gs_reg:
13284       s = names_seg[code - es_reg];
13285       break;
13286     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13287     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13288       USED_REX (0);
13289       if (rex)
13290         s = names8rex[code - al_reg];
13291       else
13292         s = names8[code - al_reg];
13293       break;
13294     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13295     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13296       USED_REX (REX_W);
13297       if (rex & REX_W)
13298         s = names64[code - eAX_reg];
13299       else
13300         {
13301           if (sizeflag & DFLAG)
13302             s = names32[code - eAX_reg];
13303           else
13304             s = names16[code - eAX_reg];
13305           used_prefixes |= (prefixes & PREFIX_DATA);
13306         }
13307       break;
13308     case z_mode_ax_reg:
13309       if ((rex & REX_W) || (sizeflag & DFLAG))
13310         s = *names32;
13311       else
13312         s = *names16;
13313       if (!(rex & REX_W))
13314         used_prefixes |= (prefixes & PREFIX_DATA);
13315       break;
13316     default:
13317       s = INTERNAL_DISASSEMBLER_ERROR;
13318       break;
13319     }
13320   oappend (s);
13321 }
13322
13323 static void
13324 OP_I (int bytemode, int sizeflag)
13325 {
13326   bfd_signed_vma op;
13327   bfd_signed_vma mask = -1;
13328
13329   switch (bytemode)
13330     {
13331     case b_mode:
13332       FETCH_DATA (the_info, codep + 1);
13333       op = *codep++;
13334       mask = 0xff;
13335       break;
13336     case q_mode:
13337       if (address_mode == mode_64bit)
13338         {
13339           op = get32s ();
13340           break;
13341         }
13342       /* Fall through.  */
13343     case v_mode:
13344       USED_REX (REX_W);
13345       if (rex & REX_W)
13346         op = get32s ();
13347       else
13348         {
13349           if (sizeflag & DFLAG)
13350             {
13351               op = get32 ();
13352               mask = 0xffffffff;
13353             }
13354           else
13355             {
13356               op = get16 ();
13357               mask = 0xfffff;
13358             }
13359           used_prefixes |= (prefixes & PREFIX_DATA);
13360         }
13361       break;
13362     case w_mode:
13363       mask = 0xfffff;
13364       op = get16 ();
13365       break;
13366     case const_1_mode:
13367       if (intel_syntax)
13368         oappend ("1");
13369       return;
13370     default:
13371       oappend (INTERNAL_DISASSEMBLER_ERROR);
13372       return;
13373     }
13374
13375   op &= mask;
13376   scratchbuf[0] = '$';
13377   print_operand_value (scratchbuf + 1, 1, op);
13378   oappend (scratchbuf + intel_syntax);
13379   scratchbuf[0] = '\0';
13380 }
13381
13382 static void
13383 OP_I64 (int bytemode, int sizeflag)
13384 {
13385   bfd_signed_vma op;
13386   bfd_signed_vma mask = -1;
13387
13388   if (address_mode != mode_64bit)
13389     {
13390       OP_I (bytemode, sizeflag);
13391       return;
13392     }
13393
13394   switch (bytemode)
13395     {
13396     case b_mode:
13397       FETCH_DATA (the_info, codep + 1);
13398       op = *codep++;
13399       mask = 0xff;
13400       break;
13401     case v_mode:
13402       USED_REX (REX_W);
13403       if (rex & REX_W)
13404         op = get64 ();
13405       else
13406         {
13407           if (sizeflag & DFLAG)
13408             {
13409               op = get32 ();
13410               mask = 0xffffffff;
13411             }
13412           else
13413             {
13414               op = get16 ();
13415               mask = 0xfffff;
13416             }
13417           used_prefixes |= (prefixes & PREFIX_DATA);
13418         }
13419       break;
13420     case w_mode:
13421       mask = 0xfffff;
13422       op = get16 ();
13423       break;
13424     default:
13425       oappend (INTERNAL_DISASSEMBLER_ERROR);
13426       return;
13427     }
13428
13429   op &= mask;
13430   scratchbuf[0] = '$';
13431   print_operand_value (scratchbuf + 1, 1, op);
13432   oappend (scratchbuf + intel_syntax);
13433   scratchbuf[0] = '\0';
13434 }
13435
13436 static void
13437 OP_sI (int bytemode, int sizeflag)
13438 {
13439   bfd_signed_vma op;
13440   bfd_signed_vma mask = -1;
13441
13442   switch (bytemode)
13443     {
13444     case b_mode:
13445       FETCH_DATA (the_info, codep + 1);
13446       op = *codep++;
13447       if ((op & 0x80) != 0)
13448         op -= 0x100;
13449       mask = 0xffffffff;
13450       break;
13451     case v_mode:
13452       USED_REX (REX_W);
13453       if (rex & REX_W)
13454         op = get32s ();
13455       else
13456         {
13457           if (sizeflag & DFLAG)
13458             {
13459               op = get32s ();
13460               mask = 0xffffffff;
13461             }
13462           else
13463             {
13464               mask = 0xffffffff;
13465               op = get16 ();
13466               if ((op & 0x8000) != 0)
13467                 op -= 0x10000;
13468             }
13469           used_prefixes |= (prefixes & PREFIX_DATA);
13470         }
13471       break;
13472     case w_mode:
13473       op = get16 ();
13474       mask = 0xffffffff;
13475       if ((op & 0x8000) != 0)
13476         op -= 0x10000;
13477       break;
13478     default:
13479       oappend (INTERNAL_DISASSEMBLER_ERROR);
13480       return;
13481     }
13482
13483   scratchbuf[0] = '$';
13484   print_operand_value (scratchbuf + 1, 1, op);
13485   oappend (scratchbuf + intel_syntax);
13486 }
13487
13488 static void
13489 OP_J (int bytemode, int sizeflag)
13490 {
13491   bfd_vma disp;
13492   bfd_vma mask = -1;
13493   bfd_vma segment = 0;
13494
13495   switch (bytemode)
13496     {
13497     case b_mode:
13498       FETCH_DATA (the_info, codep + 1);
13499       disp = *codep++;
13500       if ((disp & 0x80) != 0)
13501         disp -= 0x100;
13502       break;
13503     case v_mode:
13504       USED_REX (REX_W);
13505       if ((sizeflag & DFLAG) || (rex & REX_W))
13506         disp = get32s ();
13507       else
13508         {
13509           disp = get16 ();
13510           if ((disp & 0x8000) != 0)
13511             disp -= 0x10000;
13512           /* In 16bit mode, address is wrapped around at 64k within
13513              the same segment.  Otherwise, a data16 prefix on a jump
13514              instruction means that the pc is masked to 16 bits after
13515              the displacement is added!  */
13516           mask = 0xffff;
13517           if ((prefixes & PREFIX_DATA) == 0)
13518             segment = ((start_pc + codep - start_codep)
13519                        & ~((bfd_vma) 0xffff));
13520         }
13521       if (!(rex & REX_W))
13522         used_prefixes |= (prefixes & PREFIX_DATA);
13523       break;
13524     default:
13525       oappend (INTERNAL_DISASSEMBLER_ERROR);
13526       return;
13527     }
13528   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13529   set_op (disp, 0);
13530   print_operand_value (scratchbuf, 1, disp);
13531   oappend (scratchbuf);
13532 }
13533
13534 static void
13535 OP_SEG (int bytemode, int sizeflag)
13536 {
13537   if (bytemode == w_mode)
13538     oappend (names_seg[modrm.reg]);
13539   else
13540     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13541 }
13542
13543 static void
13544 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13545 {
13546   int seg, offset;
13547
13548   if (sizeflag & DFLAG)
13549     {
13550       offset = get32 ();
13551       seg = get16 ();
13552     }
13553   else
13554     {
13555       offset = get16 ();
13556       seg = get16 ();
13557     }
13558   used_prefixes |= (prefixes & PREFIX_DATA);
13559   if (intel_syntax)
13560     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13561   else
13562     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13563   oappend (scratchbuf);
13564 }
13565
13566 static void
13567 OP_OFF (int bytemode, int sizeflag)
13568 {
13569   bfd_vma off;
13570
13571   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13572     intel_operand_size (bytemode, sizeflag);
13573   append_seg ();
13574
13575   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13576     off = get32 ();
13577   else
13578     off = get16 ();
13579
13580   if (intel_syntax)
13581     {
13582       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13583                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13584         {
13585           oappend (names_seg[ds_reg - es_reg]);
13586           oappend (":");
13587         }
13588     }
13589   print_operand_value (scratchbuf, 1, off);
13590   oappend (scratchbuf);
13591 }
13592
13593 static void
13594 OP_OFF64 (int bytemode, int sizeflag)
13595 {
13596   bfd_vma off;
13597
13598   if (address_mode != mode_64bit
13599       || (prefixes & PREFIX_ADDR))
13600     {
13601       OP_OFF (bytemode, sizeflag);
13602       return;
13603     }
13604
13605   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13606     intel_operand_size (bytemode, sizeflag);
13607   append_seg ();
13608
13609   off = get64 ();
13610
13611   if (intel_syntax)
13612     {
13613       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13614                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13615         {
13616           oappend (names_seg[ds_reg - es_reg]);
13617           oappend (":");
13618         }
13619     }
13620   print_operand_value (scratchbuf, 1, off);
13621   oappend (scratchbuf);
13622 }
13623
13624 static void
13625 ptr_reg (int code, int sizeflag)
13626 {
13627   const char *s;
13628
13629   *obufp++ = open_char;
13630   used_prefixes |= (prefixes & PREFIX_ADDR);
13631   if (address_mode == mode_64bit)
13632     {
13633       if (!(sizeflag & AFLAG))
13634         s = names32[code - eAX_reg];
13635       else
13636         s = names64[code - eAX_reg];
13637     }
13638   else if (sizeflag & AFLAG)
13639     s = names32[code - eAX_reg];
13640   else
13641     s = names16[code - eAX_reg];
13642   oappend (s);
13643   *obufp++ = close_char;
13644   *obufp = 0;
13645 }
13646
13647 static void
13648 OP_ESreg (int code, int sizeflag)
13649 {
13650   if (intel_syntax)
13651     {
13652       switch (codep[-1])
13653         {
13654         case 0x6d:      /* insw/insl */
13655           intel_operand_size (z_mode, sizeflag);
13656           break;
13657         case 0xa5:      /* movsw/movsl/movsq */
13658         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13659         case 0xab:      /* stosw/stosl */
13660         case 0xaf:      /* scasw/scasl */
13661           intel_operand_size (v_mode, sizeflag);
13662           break;
13663         default:
13664           intel_operand_size (b_mode, sizeflag);
13665         }
13666     }
13667   oappend ("%es:" + intel_syntax);
13668   ptr_reg (code, sizeflag);
13669 }
13670
13671 static void
13672 OP_DSreg (int code, int sizeflag)
13673 {
13674   if (intel_syntax)
13675     {
13676       switch (codep[-1])
13677         {
13678         case 0x6f:      /* outsw/outsl */
13679           intel_operand_size (z_mode, sizeflag);
13680           break;
13681         case 0xa5:      /* movsw/movsl/movsq */
13682         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13683         case 0xad:      /* lodsw/lodsl/lodsq */
13684           intel_operand_size (v_mode, sizeflag);
13685           break;
13686         default:
13687           intel_operand_size (b_mode, sizeflag);
13688         }
13689     }
13690   if ((prefixes
13691        & (PREFIX_CS
13692           | PREFIX_DS
13693           | PREFIX_SS
13694           | PREFIX_ES
13695           | PREFIX_FS
13696           | PREFIX_GS)) == 0)
13697     prefixes |= PREFIX_DS;
13698   append_seg ();
13699   ptr_reg (code, sizeflag);
13700 }
13701
13702 static void
13703 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13704 {
13705   int add;
13706   if (rex & REX_R)
13707     {
13708       USED_REX (REX_R);
13709       add = 8;
13710     }
13711   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13712     {
13713       all_prefixes[last_lock_prefix] = 0;
13714       used_prefixes |= PREFIX_LOCK;
13715       add = 8;
13716     }
13717   else
13718     add = 0;
13719   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13720   oappend (scratchbuf + intel_syntax);
13721 }
13722
13723 static void
13724 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13725 {
13726   int add;
13727   USED_REX (REX_R);
13728   if (rex & REX_R)
13729     add = 8;
13730   else
13731     add = 0;
13732   if (intel_syntax)
13733     sprintf (scratchbuf, "db%d", modrm.reg + add);
13734   else
13735     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13736   oappend (scratchbuf);
13737 }
13738
13739 static void
13740 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13741 {
13742   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13743   oappend (scratchbuf + intel_syntax);
13744 }
13745
13746 static void
13747 OP_R (int bytemode, int sizeflag)
13748 {
13749   if (modrm.mod == 3)
13750     OP_E (bytemode, sizeflag);
13751   else
13752     BadOp ();
13753 }
13754
13755 static void
13756 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13757 {
13758   int reg = modrm.reg;
13759   const char **names;
13760
13761   used_prefixes |= (prefixes & PREFIX_DATA);
13762   if (prefixes & PREFIX_DATA)
13763     {
13764       names = names_xmm;
13765       USED_REX (REX_R);
13766       if (rex & REX_R)
13767         reg += 8;
13768     }
13769   else
13770     names = names_mm;
13771   oappend (names[reg]);
13772 }
13773
13774 static void
13775 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13776 {
13777   int reg = modrm.reg;
13778   const char **names;
13779
13780   USED_REX (REX_R);
13781   if (rex & REX_R)
13782     reg += 8;
13783   if (need_vex && bytemode != xmm_mode)
13784     {
13785       switch (vex.length)
13786         {
13787         case 128:
13788           names = names_xmm;
13789           break;
13790         case 256:
13791           names = names_ymm;
13792           break;
13793         default:
13794           abort ();
13795         }
13796     }
13797   else
13798     names = names_xmm;
13799   oappend (names[reg]);
13800 }
13801
13802 static void
13803 OP_EM (int bytemode, int sizeflag)
13804 {
13805   int reg;
13806   const char **names;
13807
13808   if (modrm.mod != 3)
13809     {
13810       if (intel_syntax
13811           && (bytemode == v_mode || bytemode == v_swap_mode))
13812         {
13813           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13814           used_prefixes |= (prefixes & PREFIX_DATA);
13815         }
13816       OP_E (bytemode, sizeflag);
13817       return;
13818     }
13819
13820   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13821     swap_operand ();
13822
13823   /* Skip mod/rm byte.  */
13824   MODRM_CHECK;
13825   codep++;
13826   used_prefixes |= (prefixes & PREFIX_DATA);
13827   reg = modrm.rm;
13828   if (prefixes & PREFIX_DATA)
13829     {
13830       names = names_xmm;
13831       USED_REX (REX_B);
13832       if (rex & REX_B)
13833         reg += 8;
13834     }
13835   else
13836     names = names_mm;
13837   oappend (names[reg]);
13838 }
13839
13840 /* cvt* are the only instructions in sse2 which have
13841    both SSE and MMX operands and also have 0x66 prefix
13842    in their opcode. 0x66 was originally used to differentiate
13843    between SSE and MMX instruction(operands). So we have to handle the
13844    cvt* separately using OP_EMC and OP_MXC */
13845 static void
13846 OP_EMC (int bytemode, int sizeflag)
13847 {
13848   if (modrm.mod != 3)
13849     {
13850       if (intel_syntax && bytemode == v_mode)
13851         {
13852           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13853           used_prefixes |= (prefixes & PREFIX_DATA);
13854         }
13855       OP_E (bytemode, sizeflag);
13856       return;
13857     }
13858
13859   /* Skip mod/rm byte.  */
13860   MODRM_CHECK;
13861   codep++;
13862   used_prefixes |= (prefixes & PREFIX_DATA);
13863   oappend (names_mm[modrm.rm]);
13864 }
13865
13866 static void
13867 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13868 {
13869   used_prefixes |= (prefixes & PREFIX_DATA);
13870   oappend (names_mm[modrm.reg]);
13871 }
13872
13873 static void
13874 OP_EX (int bytemode, int sizeflag)
13875 {
13876   int reg;
13877   const char **names;
13878
13879   /* Skip mod/rm byte.  */
13880   MODRM_CHECK;
13881   codep++;
13882
13883   if (modrm.mod != 3)
13884     {
13885       OP_E_memory (bytemode, sizeflag);
13886       return;
13887     }
13888
13889   reg = modrm.rm;
13890   USED_REX (REX_B);
13891   if (rex & REX_B)
13892     reg += 8;
13893
13894   if ((sizeflag & SUFFIX_ALWAYS)
13895       && (bytemode == x_swap_mode
13896           || bytemode == d_swap_mode
13897           || bytemode == q_swap_mode))
13898     swap_operand ();
13899
13900   if (need_vex
13901       && bytemode != xmm_mode
13902       && bytemode != xmmq_mode)
13903     {
13904       switch (vex.length)
13905         {
13906         case 128:
13907           names = names_xmm;
13908           break;
13909         case 256:
13910           names = names_ymm;
13911           break;
13912         default:
13913           abort ();
13914         }
13915     }
13916   else
13917     names = names_xmm;
13918   oappend (names[reg]);
13919 }
13920
13921 static void
13922 OP_MS (int bytemode, int sizeflag)
13923 {
13924   if (modrm.mod == 3)
13925     OP_EM (bytemode, sizeflag);
13926   else
13927     BadOp ();
13928 }
13929
13930 static void
13931 OP_XS (int bytemode, int sizeflag)
13932 {
13933   if (modrm.mod == 3)
13934     OP_EX (bytemode, sizeflag);
13935   else
13936     BadOp ();
13937 }
13938
13939 static void
13940 OP_M (int bytemode, int sizeflag)
13941 {
13942   if (modrm.mod == 3)
13943     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13944     BadOp ();
13945   else
13946     OP_E (bytemode, sizeflag);
13947 }
13948
13949 static void
13950 OP_0f07 (int bytemode, int sizeflag)
13951 {
13952   if (modrm.mod != 3 || modrm.rm != 0)
13953     BadOp ();
13954   else
13955     OP_E (bytemode, sizeflag);
13956 }
13957
13958 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13959    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13960
13961 static void
13962 NOP_Fixup1 (int bytemode, int sizeflag)
13963 {
13964   if ((prefixes & PREFIX_DATA) != 0
13965       || (rex != 0
13966           && rex != 0x48
13967           && address_mode == mode_64bit))
13968     OP_REG (bytemode, sizeflag);
13969   else
13970     strcpy (obuf, "nop");
13971 }
13972
13973 static void
13974 NOP_Fixup2 (int bytemode, int sizeflag)
13975 {
13976   if ((prefixes & PREFIX_DATA) != 0
13977       || (rex != 0
13978           && rex != 0x48
13979           && address_mode == mode_64bit))
13980     OP_IMREG (bytemode, sizeflag);
13981 }
13982
13983 static const char *const Suffix3DNow[] = {
13984 /* 00 */        NULL,           NULL,           NULL,           NULL,
13985 /* 04 */        NULL,           NULL,           NULL,           NULL,
13986 /* 08 */        NULL,           NULL,           NULL,           NULL,
13987 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13988 /* 10 */        NULL,           NULL,           NULL,           NULL,
13989 /* 14 */        NULL,           NULL,           NULL,           NULL,
13990 /* 18 */        NULL,           NULL,           NULL,           NULL,
13991 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13992 /* 20 */        NULL,           NULL,           NULL,           NULL,
13993 /* 24 */        NULL,           NULL,           NULL,           NULL,
13994 /* 28 */        NULL,           NULL,           NULL,           NULL,
13995 /* 2C */        NULL,           NULL,           NULL,           NULL,
13996 /* 30 */        NULL,           NULL,           NULL,           NULL,
13997 /* 34 */        NULL,           NULL,           NULL,           NULL,
13998 /* 38 */        NULL,           NULL,           NULL,           NULL,
13999 /* 3C */        NULL,           NULL,           NULL,           NULL,
14000 /* 40 */        NULL,           NULL,           NULL,           NULL,
14001 /* 44 */        NULL,           NULL,           NULL,           NULL,
14002 /* 48 */        NULL,           NULL,           NULL,           NULL,
14003 /* 4C */        NULL,           NULL,           NULL,           NULL,
14004 /* 50 */        NULL,           NULL,           NULL,           NULL,
14005 /* 54 */        NULL,           NULL,           NULL,           NULL,
14006 /* 58 */        NULL,           NULL,           NULL,           NULL,
14007 /* 5C */        NULL,           NULL,           NULL,           NULL,
14008 /* 60 */        NULL,           NULL,           NULL,           NULL,
14009 /* 64 */        NULL,           NULL,           NULL,           NULL,
14010 /* 68 */        NULL,           NULL,           NULL,           NULL,
14011 /* 6C */        NULL,           NULL,           NULL,           NULL,
14012 /* 70 */        NULL,           NULL,           NULL,           NULL,
14013 /* 74 */        NULL,           NULL,           NULL,           NULL,
14014 /* 78 */        NULL,           NULL,           NULL,           NULL,
14015 /* 7C */        NULL,           NULL,           NULL,           NULL,
14016 /* 80 */        NULL,           NULL,           NULL,           NULL,
14017 /* 84 */        NULL,           NULL,           NULL,           NULL,
14018 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14019 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14020 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14021 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14022 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14023 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14024 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14025 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14026 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14027 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14028 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14029 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14030 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14031 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14032 /* C0 */        NULL,           NULL,           NULL,           NULL,
14033 /* C4 */        NULL,           NULL,           NULL,           NULL,
14034 /* C8 */        NULL,           NULL,           NULL,           NULL,
14035 /* CC */        NULL,           NULL,           NULL,           NULL,
14036 /* D0 */        NULL,           NULL,           NULL,           NULL,
14037 /* D4 */        NULL,           NULL,           NULL,           NULL,
14038 /* D8 */        NULL,           NULL,           NULL,           NULL,
14039 /* DC */        NULL,           NULL,           NULL,           NULL,
14040 /* E0 */        NULL,           NULL,           NULL,           NULL,
14041 /* E4 */        NULL,           NULL,           NULL,           NULL,
14042 /* E8 */        NULL,           NULL,           NULL,           NULL,
14043 /* EC */        NULL,           NULL,           NULL,           NULL,
14044 /* F0 */        NULL,           NULL,           NULL,           NULL,
14045 /* F4 */        NULL,           NULL,           NULL,           NULL,
14046 /* F8 */        NULL,           NULL,           NULL,           NULL,
14047 /* FC */        NULL,           NULL,           NULL,           NULL,
14048 };
14049
14050 static void
14051 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14052 {
14053   const char *mnemonic;
14054
14055   FETCH_DATA (the_info, codep + 1);
14056   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14057      place where an 8-bit immediate would normally go.  ie. the last
14058      byte of the instruction.  */
14059   obufp = mnemonicendp;
14060   mnemonic = Suffix3DNow[*codep++ & 0xff];
14061   if (mnemonic)
14062     oappend (mnemonic);
14063   else
14064     {
14065       /* Since a variable sized modrm/sib chunk is between the start
14066          of the opcode (0x0f0f) and the opcode suffix, we need to do
14067          all the modrm processing first, and don't know until now that
14068          we have a bad opcode.  This necessitates some cleaning up.  */
14069       op_out[0][0] = '\0';
14070       op_out[1][0] = '\0';
14071       BadOp ();
14072     }
14073   mnemonicendp = obufp;
14074 }
14075
14076 static struct op simd_cmp_op[] =
14077 {
14078   { STRING_COMMA_LEN ("eq") },
14079   { STRING_COMMA_LEN ("lt") },
14080   { STRING_COMMA_LEN ("le") },
14081   { STRING_COMMA_LEN ("unord") },
14082   { STRING_COMMA_LEN ("neq") },
14083   { STRING_COMMA_LEN ("nlt") },
14084   { STRING_COMMA_LEN ("nle") },
14085   { STRING_COMMA_LEN ("ord") }
14086 };
14087
14088 static void
14089 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14090 {
14091   unsigned int cmp_type;
14092
14093   FETCH_DATA (the_info, codep + 1);
14094   cmp_type = *codep++ & 0xff;
14095   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14096     {
14097       char suffix [3];
14098       char *p = mnemonicendp - 2;
14099       suffix[0] = p[0];
14100       suffix[1] = p[1];
14101       suffix[2] = '\0';
14102       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14103       mnemonicendp += simd_cmp_op[cmp_type].len;
14104     }
14105   else
14106     {
14107       /* We have a reserved extension byte.  Output it directly.  */
14108       scratchbuf[0] = '$';
14109       print_operand_value (scratchbuf + 1, 1, cmp_type);
14110       oappend (scratchbuf + intel_syntax);
14111       scratchbuf[0] = '\0';
14112     }
14113 }
14114
14115 static void
14116 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14117           int sizeflag ATTRIBUTE_UNUSED)
14118 {
14119   /* mwait %eax,%ecx  */
14120   if (!intel_syntax)
14121     {
14122       const char **names = (address_mode == mode_64bit
14123                             ? names64 : names32);
14124       strcpy (op_out[0], names[0]);
14125       strcpy (op_out[1], names[1]);
14126       two_source_ops = 1;
14127     }
14128   /* Skip mod/rm byte.  */
14129   MODRM_CHECK;
14130   codep++;
14131 }
14132
14133 static void
14134 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14135             int sizeflag ATTRIBUTE_UNUSED)
14136 {
14137   /* monitor %eax,%ecx,%edx"  */
14138   if (!intel_syntax)
14139     {
14140       const char **op1_names;
14141       const char **names = (address_mode == mode_64bit
14142                             ? names64 : names32);
14143
14144       if (!(prefixes & PREFIX_ADDR))
14145         op1_names = (address_mode == mode_16bit
14146                      ? names16 : names);
14147       else
14148         {
14149           /* Remove "addr16/addr32".  */
14150           all_prefixes[last_addr_prefix] = 0;
14151           op1_names = (address_mode != mode_32bit
14152                        ? names32 : names16);
14153           used_prefixes |= PREFIX_ADDR;
14154         }
14155       strcpy (op_out[0], op1_names[0]);
14156       strcpy (op_out[1], names[1]);
14157       strcpy (op_out[2], names[2]);
14158       two_source_ops = 1;
14159     }
14160   /* Skip mod/rm byte.  */
14161   MODRM_CHECK;
14162   codep++;
14163 }
14164
14165 static void
14166 BadOp (void)
14167 {
14168   /* Throw away prefixes and 1st. opcode byte.  */
14169   codep = insn_codep + 1;
14170   oappend ("(bad)");
14171 }
14172
14173 static void
14174 REP_Fixup (int bytemode, int sizeflag)
14175 {
14176   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14177      lods and stos.  */
14178   if (prefixes & PREFIX_REPZ)
14179     all_prefixes[last_repz_prefix] = REP_PREFIX;
14180
14181   switch (bytemode)
14182     {
14183     case al_reg:
14184     case eAX_reg:
14185     case indir_dx_reg:
14186       OP_IMREG (bytemode, sizeflag);
14187       break;
14188     case eDI_reg:
14189       OP_ESreg (bytemode, sizeflag);
14190       break;
14191     case eSI_reg:
14192       OP_DSreg (bytemode, sizeflag);
14193       break;
14194     default:
14195       abort ();
14196       break;
14197     }
14198 }
14199
14200 static void
14201 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14202 {
14203   USED_REX (REX_W);
14204   if (rex & REX_W)
14205     {
14206       /* Change cmpxchg8b to cmpxchg16b.  */
14207       char *p = mnemonicendp - 2;
14208       mnemonicendp = stpcpy (p, "16b");
14209       bytemode = o_mode;
14210     }
14211   OP_M (bytemode, sizeflag);
14212 }
14213
14214 static void
14215 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14216 {
14217   const char **names;
14218
14219   if (need_vex)
14220     {
14221       switch (vex.length)
14222         {
14223         case 128:
14224           names = names_xmm;
14225           break;
14226         case 256:
14227           names = names_ymm;
14228           break;
14229         default:
14230           abort ();
14231         }
14232     }
14233   else
14234     names = names_xmm;
14235   oappend (names[reg]);
14236 }
14237
14238 static void
14239 CRC32_Fixup (int bytemode, int sizeflag)
14240 {
14241   /* Add proper suffix to "crc32".  */
14242   char *p = mnemonicendp;
14243
14244   switch (bytemode)
14245     {
14246     case b_mode:
14247       if (intel_syntax)
14248         goto skip;
14249
14250       *p++ = 'b';
14251       break;
14252     case v_mode:
14253       if (intel_syntax)
14254         goto skip;
14255
14256       USED_REX (REX_W);
14257       if (rex & REX_W)
14258         *p++ = 'q';
14259       else
14260         {
14261           if (sizeflag & DFLAG)
14262             *p++ = 'l';
14263           else
14264             *p++ = 'w';
14265           used_prefixes |= (prefixes & PREFIX_DATA);
14266         }
14267       break;
14268     default:
14269       oappend (INTERNAL_DISASSEMBLER_ERROR);
14270       break;
14271     }
14272   mnemonicendp = p;
14273   *p = '\0';
14274
14275 skip:
14276   if (modrm.mod == 3)
14277     {
14278       int add;
14279
14280       /* Skip mod/rm byte.  */
14281       MODRM_CHECK;
14282       codep++;
14283
14284       USED_REX (REX_B);
14285       add = (rex & REX_B) ? 8 : 0;
14286       if (bytemode == b_mode)
14287         {
14288           USED_REX (0);
14289           if (rex)
14290             oappend (names8rex[modrm.rm + add]);
14291           else
14292             oappend (names8[modrm.rm + add]);
14293         }
14294       else
14295         {
14296           USED_REX (REX_W);
14297           if (rex & REX_W)
14298             oappend (names64[modrm.rm + add]);
14299           else if ((prefixes & PREFIX_DATA))
14300             oappend (names16[modrm.rm + add]);
14301           else
14302             oappend (names32[modrm.rm + add]);
14303         }
14304     }
14305   else
14306     OP_E (bytemode, sizeflag);
14307 }
14308
14309 static void
14310 FXSAVE_Fixup (int bytemode, int sizeflag)
14311 {
14312   /* Add proper suffix to "fxsave" and "fxrstor".  */
14313   USED_REX (REX_W);
14314   if (rex & REX_W)
14315     {
14316       char *p = mnemonicendp;
14317       *p++ = '6';
14318       *p++ = '4';
14319       *p = '\0';
14320       mnemonicendp = p;
14321     }
14322   OP_M (bytemode, sizeflag);
14323 }
14324
14325 /* Display the destination register operand for instructions with
14326    VEX. */
14327
14328 static void
14329 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14330 {
14331   const char **names;
14332
14333   if (!need_vex)
14334     abort ();
14335
14336   if (!need_vex_reg)
14337     return;
14338
14339   switch (vex.length)
14340     {
14341     case 128:
14342       switch (bytemode)
14343         {
14344         case vex_mode:
14345         case vex128_mode:
14346           break;
14347         default:
14348           abort ();
14349           return;
14350         }
14351
14352       names = names_xmm;
14353       break;
14354     case 256:
14355       switch (bytemode)
14356         {
14357         case vex_mode:
14358         case vex256_mode:
14359           break;
14360         default:
14361           abort ();
14362           return;
14363         }
14364
14365       names = names_ymm;
14366       break;
14367     default:
14368       abort ();
14369       break;
14370     }
14371   oappend (names[vex.register_specifier]);
14372 }
14373
14374 /* Get the VEX immediate byte without moving codep.  */
14375
14376 static unsigned char
14377 get_vex_imm8 (int sizeflag, int opnum)
14378 {
14379   int bytes_before_imm = 0;
14380
14381   if (modrm.mod != 3)
14382     {
14383       /* There are SIB/displacement bytes.  */
14384       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14385         {
14386           /* 32/64 bit address mode */
14387           int base = modrm.rm;
14388
14389           /* Check SIB byte.  */
14390           if (base == 4)
14391             {
14392               FETCH_DATA (the_info, codep + 1);
14393               base = *codep & 7;
14394               /* When decoding the third source, don't increase
14395                  bytes_before_imm as this has already been incremented
14396                  by one in OP_E_memory while decoding the second
14397                  source operand.  */
14398               if (opnum == 0)
14399                 bytes_before_imm++;
14400             }
14401
14402           /* Don't increase bytes_before_imm when decoding the third source,
14403              it has already been incremented by OP_E_memory while decoding
14404              the second source operand.  */
14405           if (opnum == 0)
14406             {
14407               switch (modrm.mod)
14408                 {
14409                   case 0:
14410                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14411                        SIB == 5, there is a 4 byte displacement.  */
14412                     if (base != 5)
14413                       /* No displacement. */
14414                       break;
14415                   case 2:
14416                     /* 4 byte displacement.  */
14417                     bytes_before_imm += 4;
14418                     break;
14419                   case 1:
14420                     /* 1 byte displacement.  */
14421                     bytes_before_imm++;
14422                     break;
14423                 }
14424             }
14425         }
14426       else
14427         {
14428           /* 16 bit address mode */
14429           /* Don't increase bytes_before_imm when decoding the third source,
14430              it has already been incremented by OP_E_memory while decoding
14431              the second source operand.  */
14432           if (opnum == 0)
14433             {
14434               switch (modrm.mod)
14435                 {
14436                 case 0:
14437                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14438                   if (modrm.rm != 6)
14439                     /* No displacement. */
14440                     break;
14441                 case 2:
14442                   /* 2 byte displacement.  */
14443                   bytes_before_imm += 2;
14444                   break;
14445                 case 1:
14446                   /* 1 byte displacement: when decoding the third source,
14447                      don't increase bytes_before_imm as this has already
14448                      been incremented by one in OP_E_memory while decoding
14449                      the second source operand.  */
14450                   if (opnum == 0)
14451                     bytes_before_imm++;
14452
14453                   break;
14454                 }
14455             }
14456         }
14457     }
14458
14459   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14460   return codep [bytes_before_imm];
14461 }
14462
14463 static void
14464 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14465 {
14466   const char **names;
14467
14468   if (reg == -1 && modrm.mod != 3)
14469     {
14470       OP_E_memory (bytemode, sizeflag);
14471       return;
14472     }
14473   else
14474     {
14475       if (reg == -1)
14476         {
14477           reg = modrm.rm;
14478           USED_REX (REX_B);
14479           if (rex & REX_B)
14480             reg += 8;
14481         }
14482       else if (reg > 7 && address_mode != mode_64bit)
14483         BadOp ();
14484     }
14485
14486   switch (vex.length)
14487     {
14488     case 128:
14489       names = names_xmm;
14490       break;
14491     case 256:
14492       names = names_ymm;
14493       break;
14494     default:
14495       abort ();
14496     }
14497   oappend (names[reg]);
14498 }
14499
14500 static void
14501 OP_Vex_2src (int bytemode, int sizeflag)
14502 {
14503   if (modrm.mod == 3)
14504     {
14505       int reg = modrm.rm;
14506       USED_REX (REX_B);
14507       if (rex & REX_B)
14508         reg += 8;
14509       oappend (names_xmm[reg]);
14510     }
14511   else
14512     {
14513       if (intel_syntax
14514           && (bytemode == v_mode || bytemode == v_swap_mode))
14515         {
14516           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14517           used_prefixes |= (prefixes & PREFIX_DATA);
14518         }
14519       OP_E (bytemode, sizeflag);
14520     }
14521 }
14522
14523 static void
14524 OP_Vex_2src_1 (int bytemode, int sizeflag)
14525 {
14526   if (modrm.mod == 3)
14527     {
14528       /* Skip mod/rm byte.   */
14529       MODRM_CHECK;
14530       codep++;
14531     }
14532
14533   if (vex.w)
14534     oappend (names_xmm[vex.register_specifier]);
14535   else
14536     OP_Vex_2src (bytemode, sizeflag);
14537 }
14538
14539 static void
14540 OP_Vex_2src_2 (int bytemode, int sizeflag)
14541 {
14542   if (vex.w)
14543     OP_Vex_2src (bytemode, sizeflag);
14544   else
14545     oappend (names_xmm[vex.register_specifier]);
14546 }
14547
14548 static void
14549 OP_EX_VexW (int bytemode, int sizeflag)
14550 {
14551   int reg = -1;
14552
14553   if (!vex_w_done)
14554     {
14555       vex_w_done = 1;
14556
14557       /* Skip mod/rm byte.  */
14558       MODRM_CHECK;
14559       codep++;
14560
14561       if (vex.w)
14562         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14563     }
14564   else
14565     {
14566       if (!vex.w)
14567         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14568     }
14569
14570   OP_EX_VexReg (bytemode, sizeflag, reg);
14571 }
14572
14573 static void
14574 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14575              int sizeflag ATTRIBUTE_UNUSED)
14576 {
14577   /* Skip the immediate byte and check for invalid bits.  */
14578   FETCH_DATA (the_info, codep + 1);
14579   if (*codep++ & 0xf)
14580     BadOp ();
14581 }
14582
14583 static void
14584 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14585 {
14586   int reg;
14587   const char **names;
14588
14589   FETCH_DATA (the_info, codep + 1);
14590   reg = *codep++;
14591
14592   if (bytemode != x_mode)
14593     abort ();
14594
14595   if (reg & 0xf)
14596       BadOp ();
14597
14598   reg >>= 4;
14599   if (reg > 7 && address_mode != mode_64bit)
14600     BadOp ();
14601
14602   switch (vex.length)
14603     {
14604     case 128:
14605       names = names_xmm;
14606       break;
14607     case 256:
14608       names = names_ymm;
14609       break;
14610     default:
14611       abort ();
14612     }
14613   oappend (names[reg]);
14614 }
14615
14616 static void
14617 OP_XMM_VexW (int bytemode, int sizeflag)
14618 {
14619   /* Turn off the REX.W bit since it is used for swapping operands
14620      now.  */
14621   rex &= ~REX_W;
14622   OP_XMM (bytemode, sizeflag);
14623 }
14624
14625 static void
14626 OP_EX_Vex (int bytemode, int sizeflag)
14627 {
14628   if (modrm.mod != 3)
14629     {
14630       if (vex.register_specifier != 0)
14631         BadOp ();
14632       need_vex_reg = 0;
14633     }
14634   OP_EX (bytemode, sizeflag);
14635 }
14636
14637 static void
14638 OP_XMM_Vex (int bytemode, int sizeflag)
14639 {
14640   if (modrm.mod != 3)
14641     {
14642       if (vex.register_specifier != 0)
14643         BadOp ();
14644       need_vex_reg = 0;
14645     }
14646   OP_XMM (bytemode, sizeflag);
14647 }
14648
14649 static void
14650 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14651 {
14652   switch (vex.length)
14653     {
14654     case 128:
14655       mnemonicendp = stpcpy (obuf, "vzeroupper");
14656       break;
14657     case 256:
14658       mnemonicendp = stpcpy (obuf, "vzeroall");
14659       break;
14660     default:
14661       abort ();
14662     }
14663 }
14664
14665 static struct op vex_cmp_op[] =
14666 {
14667   { STRING_COMMA_LEN ("eq") },
14668   { STRING_COMMA_LEN ("lt") },
14669   { STRING_COMMA_LEN ("le") },
14670   { STRING_COMMA_LEN ("unord") },
14671   { STRING_COMMA_LEN ("neq") },
14672   { STRING_COMMA_LEN ("nlt") },
14673   { STRING_COMMA_LEN ("nle") },
14674   { STRING_COMMA_LEN ("ord") },
14675   { STRING_COMMA_LEN ("eq_uq") },
14676   { STRING_COMMA_LEN ("nge") },
14677   { STRING_COMMA_LEN ("ngt") },
14678   { STRING_COMMA_LEN ("false") },
14679   { STRING_COMMA_LEN ("neq_oq") },
14680   { STRING_COMMA_LEN ("ge") },
14681   { STRING_COMMA_LEN ("gt") },
14682   { STRING_COMMA_LEN ("true") },
14683   { STRING_COMMA_LEN ("eq_os") },
14684   { STRING_COMMA_LEN ("lt_oq") },
14685   { STRING_COMMA_LEN ("le_oq") },
14686   { STRING_COMMA_LEN ("unord_s") },
14687   { STRING_COMMA_LEN ("neq_us") },
14688   { STRING_COMMA_LEN ("nlt_uq") },
14689   { STRING_COMMA_LEN ("nle_uq") },
14690   { STRING_COMMA_LEN ("ord_s") },
14691   { STRING_COMMA_LEN ("eq_us") },
14692   { STRING_COMMA_LEN ("nge_uq") },
14693   { STRING_COMMA_LEN ("ngt_uq") },
14694   { STRING_COMMA_LEN ("false_os") },
14695   { STRING_COMMA_LEN ("neq_os") },
14696   { STRING_COMMA_LEN ("ge_oq") },
14697   { STRING_COMMA_LEN ("gt_oq") },
14698   { STRING_COMMA_LEN ("true_us") },
14699 };
14700
14701 static void
14702 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14703 {
14704   unsigned int cmp_type;
14705
14706   FETCH_DATA (the_info, codep + 1);
14707   cmp_type = *codep++ & 0xff;
14708   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14709     {
14710       char suffix [3];
14711       char *p = mnemonicendp - 2;
14712       suffix[0] = p[0];
14713       suffix[1] = p[1];
14714       suffix[2] = '\0';
14715       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14716       mnemonicendp += vex_cmp_op[cmp_type].len;
14717     }
14718   else
14719     {
14720       /* We have a reserved extension byte.  Output it directly.  */
14721       scratchbuf[0] = '$';
14722       print_operand_value (scratchbuf + 1, 1, cmp_type);
14723       oappend (scratchbuf + intel_syntax);
14724       scratchbuf[0] = '\0';
14725     }
14726 }
14727
14728 static const struct op pclmul_op[] =
14729 {
14730   { STRING_COMMA_LEN ("lql") },
14731   { STRING_COMMA_LEN ("hql") },
14732   { STRING_COMMA_LEN ("lqh") },
14733   { STRING_COMMA_LEN ("hqh") }
14734 };
14735
14736 static void
14737 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14738               int sizeflag ATTRIBUTE_UNUSED)
14739 {
14740   unsigned int pclmul_type;
14741
14742   FETCH_DATA (the_info, codep + 1);
14743   pclmul_type = *codep++ & 0xff;
14744   switch (pclmul_type)
14745     {
14746     case 0x10:
14747       pclmul_type = 2;
14748       break;
14749     case 0x11:
14750       pclmul_type = 3;
14751       break;
14752     default:
14753       break;
14754     }
14755   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14756     {
14757       char suffix [4];
14758       char *p = mnemonicendp - 3;
14759       suffix[0] = p[0];
14760       suffix[1] = p[1];
14761       suffix[2] = p[2];
14762       suffix[3] = '\0';
14763       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14764       mnemonicendp += pclmul_op[pclmul_type].len;
14765     }
14766   else
14767     {
14768       /* We have a reserved extension byte.  Output it directly.  */
14769       scratchbuf[0] = '$';
14770       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14771       oappend (scratchbuf + intel_syntax);
14772       scratchbuf[0] = '\0';
14773     }
14774 }
14775
14776 static void
14777 MOVBE_Fixup (int bytemode, int sizeflag)
14778 {
14779   /* Add proper suffix to "movbe".  */
14780   char *p = mnemonicendp;
14781
14782   switch (bytemode)
14783     {
14784     case v_mode:
14785       if (intel_syntax)
14786         goto skip;
14787
14788       USED_REX (REX_W);
14789       if (sizeflag & SUFFIX_ALWAYS)
14790         {
14791           if (rex & REX_W)
14792             *p++ = 'q';
14793           else
14794             {
14795               if (sizeflag & DFLAG)
14796                 *p++ = 'l';
14797               else
14798                 *p++ = 'w';
14799               used_prefixes |= (prefixes & PREFIX_DATA);
14800             }
14801         }
14802       break;
14803     default:
14804       oappend (INTERNAL_DISASSEMBLER_ERROR);
14805       break;
14806     }
14807   mnemonicendp = p;
14808   *p = '\0';
14809
14810 skip:
14811   OP_M (bytemode, sizeflag);
14812 }
14813
14814 static void
14815 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14816 {
14817   int reg;
14818   const char **names;
14819
14820   /* Skip mod/rm byte.  */
14821   MODRM_CHECK;
14822   codep++;
14823
14824   if (vex.w)
14825     names = names64;
14826   else if (vex.length == 256)
14827     names = names32;
14828   else
14829     names = names16;
14830
14831   reg = modrm.rm;
14832   USED_REX (REX_B);
14833   if (rex & REX_B)
14834     reg += 8;
14835
14836   oappend (names[reg]);
14837 }
14838
14839 static void
14840 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14841 {
14842   const char **names;
14843
14844   if (vex.w)
14845     names = names64;
14846   else if (vex.length == 256)
14847     names = names32;
14848   else
14849     names = names16;
14850
14851   oappend (names[vex.register_specifier]);
14852 }
14853
14854 static void
14855 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
14856 {
14857   if (vex.w || vex.length == 256)
14858     OP_I (q_mode, sizeflag);
14859   else
14860     OP_I (w_mode, sizeflag);
14861 }
14862