opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_EX_Vex (int, int);
  92 static void OP_EX_VexW (int, int);
  93 static void OP_EX_VexImmW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_Rounding (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void SEP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128 static void MOVSXD_Fixup (int, int);
 129
 130 static void OP_Mask (int, int);
 131
 132 struct dis_private {
 133   /* Points to first byte not fetched.  */
 134   bfd_byte *max_fetched;
 135   bfd_byte the_buffer[MAX_MNEM_SIZE];
 136   bfd_vma insn_start;
 137   int orig_sizeflag;
 138   OPCODES_SIGJMP_BUF bailout;
 139 };
 140
 141 enum address_mode
 142 {
 143   mode_16bit,
 144   mode_32bit,
 145   mode_64bit
 146 };
 147
 148 enum address_mode address_mode;
 149
 150 /* Flags for the prefixes for the current instruction.  See below.  */
 151 static int prefixes;
 152
 153 /* REX prefix the current instruction.  See below.  */
 154 static int rex;
 155 /* Bits of REX we've already used.  */
 156 static int rex_used;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Jdqw { OP_J, dqw_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmmdw { OP_EX, xmmdw_mode }
 401 #define EXxmmqd { OP_EX, xmmqd_mode }
 402 #define EXymmq { OP_EX, ymmq_mode }
 403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 406 #define MS { OP_MS, v_mode }
 407 #define XS { OP_XS, v_mode }
 408 #define EMCq { OP_EMC, q_mode }
 409 #define MXC { OP_MXC, 0 }
 410 #define OPSUF { OP_3DNowSuffix, 0 }
 411 #define SEP { SEP_Fixup, 0 }
 412 #define CMP { CMP_Fixup, 0 }
 413 #define XMM0 { XMM_Fixup, 0 }
 414 #define FXSAVE { FXSAVE_Fixup, 0 }
 415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 417
 418 #define Vex { OP_VEX, vex_mode }
 419 #define VexScalar { OP_VEX, vex_scalar_mode }
 420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 421 #define Vex128 { OP_VEX, vex128_mode }
 422 #define Vex256 { OP_VEX, vex256_mode }
 423 #define VexGdq { OP_VEX, dq_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 426 #define EXVexW { OP_EX_VexW, x_mode }
 427 #define EXdVexW { OP_EX_VexW, d_mode }
 428 #define EXqVexW { OP_EX_VexW, q_mode }
 429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 431 #define XMVexW { OP_XMM_VexW, 0 }
 432 #define XMVexI4 { OP_REG_VexI4, x_mode }
 433 #define PCLMUL { PCLMUL_Fixup, 0 }
 434 #define VCMP { VCMP_Fixup, 0 }
 435 #define VPCMP { VPCMP_Fixup, 0 }
 436 #define VPCOM { VPCOM_Fixup, 0 }
 437
 438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 441
 442 #define XMask { OP_Mask, mask_mode }
 443 #define MaskG { OP_G, mask_mode }
 444 #define MaskE { OP_E, mask_mode }
 445 #define MaskBDE { OP_E, mask_bd_mode }
 446 #define MaskR { OP_R, mask_mode }
 447 #define MaskVex { OP_VEX, mask_mode }
 448
 449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 453
 454 /* Used handle "rep" prefix for string instructions.  */
 455 #define Xbr { REP_Fixup, eSI_reg }
 456 #define Xvr { REP_Fixup, eSI_reg }
 457 #define Ybr { REP_Fixup, eDI_reg }
 458 #define Yvr { REP_Fixup, eDI_reg }
 459 #define Yzr { REP_Fixup, eDI_reg }
 460 #define indirDXr { REP_Fixup, indir_dx_reg }
 461 #define ALr { REP_Fixup, al_reg }
 462 #define eAXr { REP_Fixup, eAX_reg }
 463
 464 /* Used handle HLE prefix for lockable instructions.  */
 465 #define Ebh1 { HLE_Fixup1, b_mode }
 466 #define Evh1 { HLE_Fixup1, v_mode }
 467 #define Ebh2 { HLE_Fixup2, b_mode }
 468 #define Evh2 { HLE_Fixup2, v_mode }
 469 #define Ebh3 { HLE_Fixup3, b_mode }
 470 #define Evh3 { HLE_Fixup3, v_mode }
 471
 472 #define BND { BND_Fixup, 0 }
 473 #define NOTRACK { NOTRACK_Fixup, 0 }
 474
 475 #define cond_jump_flag { NULL, cond_jump_mode }
 476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 477
 478 /* bits in sizeflag */
 479 #define SUFFIX_ALWAYS 4
 480 #define AFLAG 2
 481 #define DFLAG 1
 482
 483 enum
 484 {
 485   /* byte operand */
 486   b_mode = 1,
 487   /* byte operand with operand swapped */
 488   b_swap_mode,
 489   /* byte operand, sign extend like 'T' suffix */
 490   b_T_mode,
 491   /* operand size depends on prefixes */
 492   v_mode,
 493   /* operand size depends on prefixes with operand swapped */
 494   v_swap_mode,
 495   /* operand size depends on address prefix */
 496   va_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* 16-byte XMM, word, double word or quad word operand.  */
 536   xmmdw_mode,
 537   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 538   xmmqd_mode,
 539   /* 32-byte YMM operand */
 540   ymm_mode,
 541   /* quad word, ymmword or zmmword memory operand.  */
 542   ymmq_mode,
 543   /* 32-byte YMM or 16-byte word operand */
 544   ymmxmm_mode,
 545   /* d_mode in 32bit, q_mode in 64bit mode.  */
 546   m_mode,
 547   /* pair of v_mode operands */
 548   a_mode,
 549   cond_jump_mode,
 550   loop_jcxz_mode,
 551   movsxd_mode,
 552   v_bnd_mode,
 553   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 554   v_bndmk_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode, displacements like
 558      v_mode without considering Intel64 ISA.  */
 559   dqw_mode,
 560   /* bounds operand */
 561   bnd_mode,
 562   /* bounds operand with operand swapped */
 563   bnd_swap_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589
 590   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 591   vex_vsib_d_w_dq_mode,
 592   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 593   vex_vsib_d_w_d_mode,
 594   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 595   vex_vsib_q_w_dq_mode,
 596   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 597   vex_vsib_q_w_d_mode,
 598
 599   /* scalar, ignore vector length.  */
 600   scalar_mode,
 601   /* like b_mode, ignore vector length.  */
 602   b_scalar_mode,
 603   /* like w_mode, ignore vector length.  */
 604   w_scalar_mode,
 605   /* like d_swap_mode, ignore vector length.  */
 606   d_scalar_swap_mode,
 607   /* like q_swap_mode, ignore vector length.  */
 608   q_scalar_swap_mode,
 609   /* like vex_mode, ignore vector length.  */
 610   vex_scalar_mode,
 611   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 612   vex_scalar_w_dq_mode,
 613
 614   /* Static rounding.  */
 615   evex_rounding_mode,
 616   /* Static rounding, 64-bit mode only.  */
 617   evex_rounding_64_mode,
 618   /* Supress all exceptions.  */
 619   evex_sae_mode,
 620
 621   /* Mask register operand.  */
 622   mask_mode,
 623   /* Mask register operand.  */
 624   mask_bd_mode,
 625
 626   es_reg,
 627   cs_reg,
 628   ss_reg,
 629   ds_reg,
 630   fs_reg,
 631   gs_reg,
 632
 633   eAX_reg,
 634   eCX_reg,
 635   eDX_reg,
 636   eBX_reg,
 637   eSP_reg,
 638   eBP_reg,
 639   eSI_reg,
 640   eDI_reg,
 641
 642   al_reg,
 643   cl_reg,
 644   dl_reg,
 645   bl_reg,
 646   ah_reg,
 647   ch_reg,
 648   dh_reg,
 649   bh_reg,
 650
 651   ax_reg,
 652   cx_reg,
 653   dx_reg,
 654   bx_reg,
 655   sp_reg,
 656   bp_reg,
 657   si_reg,
 658   di_reg,
 659
 660   rAX_reg,
 661   rCX_reg,
 662   rDX_reg,
 663   rBX_reg,
 664   rSP_reg,
 665   rBP_reg,
 666   rSI_reg,
 667   rDI_reg,
 668
 669   z_mode_ax_reg,
 670   indir_dx_reg
 671 };
 672
 673 enum
 674 {
 675   FLOATCODE = 1,
 676   USE_REG_TABLE,
 677   USE_MOD_TABLE,
 678   USE_RM_TABLE,
 679   USE_PREFIX_TABLE,
 680   USE_X86_64_TABLE,
 681   USE_3BYTE_TABLE,
 682   USE_XOP_8F_TABLE,
 683   USE_VEX_C4_TABLE,
 684   USE_VEX_C5_TABLE,
 685   USE_VEX_LEN_TABLE,
 686   USE_VEX_W_TABLE,
 687   USE_EVEX_TABLE,
 688   USE_EVEX_LEN_TABLE
 689 };
 690
 691 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 692
 693 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 694 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 695 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 696 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 697 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 698 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 699 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 700 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 701 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 702 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 703 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 704 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 705 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 706 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 707 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 708 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 709
 710 enum
 711 {
 712   REG_80 = 0,
 713   REG_81,
 714   REG_83,
 715   REG_8F,
 716   REG_C0,
 717   REG_C1,
 718   REG_C6,
 719   REG_C7,
 720   REG_D0,
 721   REG_D1,
 722   REG_D2,
 723   REG_D3,
 724   REG_F6,
 725   REG_F7,
 726   REG_FE,
 727   REG_FF,
 728   REG_0F00,
 729   REG_0F01,
 730   REG_0F0D,
 731   REG_0F18,
 732   REG_0F1C_P_0_MOD_0,
 733   REG_0F1E_P_1_MOD_3,
 734   REG_0F71,
 735   REG_0F72,
 736   REG_0F73,
 737   REG_0FA6,
 738   REG_0FA7,
 739   REG_0FAE,
 740   REG_0FBA,
 741   REG_0FC7,
 742   REG_VEX_0F71,
 743   REG_VEX_0F72,
 744   REG_VEX_0F73,
 745   REG_VEX_0FAE,
 746   REG_VEX_0F38F3,
 747   REG_XOP_LWPCB,
 748   REG_XOP_LWP,
 749   REG_XOP_TBM_01,
 750   REG_XOP_TBM_02,
 751
 752   REG_EVEX_0F71,
 753   REG_EVEX_0F72,
 754   REG_EVEX_0F73,
 755   REG_EVEX_0F38C6,
 756   REG_EVEX_0F38C7
 757 };
 758
 759 enum
 760 {
 761   MOD_8D = 0,
 762   MOD_C6_REG_7,
 763   MOD_C7_REG_7,
 764   MOD_FF_REG_3,
 765   MOD_FF_REG_5,
 766   MOD_0F01_REG_0,
 767   MOD_0F01_REG_1,
 768   MOD_0F01_REG_2,
 769   MOD_0F01_REG_3,
 770   MOD_0F01_REG_5,
 771   MOD_0F01_REG_7,
 772   MOD_0F12_PREFIX_0,
 773   MOD_0F12_PREFIX_2,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F16_PREFIX_2,
 777   MOD_0F17,
 778   MOD_0F18_REG_0,
 779   MOD_0F18_REG_1,
 780   MOD_0F18_REG_2,
 781   MOD_0F18_REG_3,
 782   MOD_0F18_REG_4,
 783   MOD_0F18_REG_5,
 784   MOD_0F18_REG_6,
 785   MOD_0F18_REG_7,
 786   MOD_0F1A_PREFIX_0,
 787   MOD_0F1B_PREFIX_0,
 788   MOD_0F1B_PREFIX_1,
 789   MOD_0F1C_PREFIX_0,
 790   MOD_0F1E_PREFIX_1,
 791   MOD_0F24,
 792   MOD_0F26,
 793   MOD_0F2B_PREFIX_0,
 794   MOD_0F2B_PREFIX_1,
 795   MOD_0F2B_PREFIX_2,
 796   MOD_0F2B_PREFIX_3,
 797   MOD_0F50,
 798   MOD_0F71_REG_2,
 799   MOD_0F71_REG_4,
 800   MOD_0F71_REG_6,
 801   MOD_0F72_REG_2,
 802   MOD_0F72_REG_4,
 803   MOD_0F72_REG_6,
 804   MOD_0F73_REG_2,
 805   MOD_0F73_REG_3,
 806   MOD_0F73_REG_6,
 807   MOD_0F73_REG_7,
 808   MOD_0FAE_REG_0,
 809   MOD_0FAE_REG_1,
 810   MOD_0FAE_REG_2,
 811   MOD_0FAE_REG_3,
 812   MOD_0FAE_REG_4,
 813   MOD_0FAE_REG_5,
 814   MOD_0FAE_REG_6,
 815   MOD_0FAE_REG_7,
 816   MOD_0FB2,
 817   MOD_0FB4,
 818   MOD_0FB5,
 819   MOD_0FC3,
 820   MOD_0FC7_REG_3,
 821   MOD_0FC7_REG_4,
 822   MOD_0FC7_REG_5,
 823   MOD_0FC7_REG_6,
 824   MOD_0FC7_REG_7,
 825   MOD_0FD7,
 826   MOD_0FE7_PREFIX_2,
 827   MOD_0FF0_PREFIX_3,
 828   MOD_0F382A_PREFIX_2,
 829   MOD_0F38F5_PREFIX_2,
 830   MOD_0F38F6_PREFIX_0,
 831   MOD_0F38F8_PREFIX_1,
 832   MOD_0F38F8_PREFIX_2,
 833   MOD_0F38F8_PREFIX_3,
 834   MOD_0F38F9_PREFIX_0,
 835   MOD_62_32BIT,
 836   MOD_C4_32BIT,
 837   MOD_C5_32BIT,
 838   MOD_VEX_0F12_PREFIX_0,
 839   MOD_VEX_0F12_PREFIX_2,
 840   MOD_VEX_0F13,
 841   MOD_VEX_0F16_PREFIX_0,
 842   MOD_VEX_0F16_PREFIX_2,
 843   MOD_VEX_0F17,
 844   MOD_VEX_0F2B,
 845   MOD_VEX_W_0_0F41_P_0_LEN_1,
 846   MOD_VEX_W_1_0F41_P_0_LEN_1,
 847   MOD_VEX_W_0_0F41_P_2_LEN_1,
 848   MOD_VEX_W_1_0F41_P_2_LEN_1,
 849   MOD_VEX_W_0_0F42_P_0_LEN_1,
 850   MOD_VEX_W_1_0F42_P_0_LEN_1,
 851   MOD_VEX_W_0_0F42_P_2_LEN_1,
 852   MOD_VEX_W_1_0F42_P_2_LEN_1,
 853   MOD_VEX_W_0_0F44_P_0_LEN_1,
 854   MOD_VEX_W_1_0F44_P_0_LEN_1,
 855   MOD_VEX_W_0_0F44_P_2_LEN_1,
 856   MOD_VEX_W_1_0F44_P_2_LEN_1,
 857   MOD_VEX_W_0_0F45_P_0_LEN_1,
 858   MOD_VEX_W_1_0F45_P_0_LEN_1,
 859   MOD_VEX_W_0_0F45_P_2_LEN_1,
 860   MOD_VEX_W_1_0F45_P_2_LEN_1,
 861   MOD_VEX_W_0_0F46_P_0_LEN_1,
 862   MOD_VEX_W_1_0F46_P_0_LEN_1,
 863   MOD_VEX_W_0_0F46_P_2_LEN_1,
 864   MOD_VEX_W_1_0F46_P_2_LEN_1,
 865   MOD_VEX_W_0_0F47_P_0_LEN_1,
 866   MOD_VEX_W_1_0F47_P_0_LEN_1,
 867   MOD_VEX_W_0_0F47_P_2_LEN_1,
 868   MOD_VEX_W_1_0F47_P_2_LEN_1,
 869   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 870   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 871   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 872   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 873   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 874   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 875   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 876   MOD_VEX_0F50,
 877   MOD_VEX_0F71_REG_2,
 878   MOD_VEX_0F71_REG_4,
 879   MOD_VEX_0F71_REG_6,
 880   MOD_VEX_0F72_REG_2,
 881   MOD_VEX_0F72_REG_4,
 882   MOD_VEX_0F72_REG_6,
 883   MOD_VEX_0F73_REG_2,
 884   MOD_VEX_0F73_REG_3,
 885   MOD_VEX_0F73_REG_6,
 886   MOD_VEX_0F73_REG_7,
 887   MOD_VEX_W_0_0F91_P_0_LEN_0,
 888   MOD_VEX_W_1_0F91_P_0_LEN_0,
 889   MOD_VEX_W_0_0F91_P_2_LEN_0,
 890   MOD_VEX_W_1_0F91_P_2_LEN_0,
 891   MOD_VEX_W_0_0F92_P_0_LEN_0,
 892   MOD_VEX_W_0_0F92_P_2_LEN_0,
 893   MOD_VEX_0F92_P_3_LEN_0,
 894   MOD_VEX_W_0_0F93_P_0_LEN_0,
 895   MOD_VEX_W_0_0F93_P_2_LEN_0,
 896   MOD_VEX_0F93_P_3_LEN_0,
 897   MOD_VEX_W_0_0F98_P_0_LEN_0,
 898   MOD_VEX_W_1_0F98_P_0_LEN_0,
 899   MOD_VEX_W_0_0F98_P_2_LEN_0,
 900   MOD_VEX_W_1_0F98_P_2_LEN_0,
 901   MOD_VEX_W_0_0F99_P_0_LEN_0,
 902   MOD_VEX_W_1_0F99_P_0_LEN_0,
 903   MOD_VEX_W_0_0F99_P_2_LEN_0,
 904   MOD_VEX_W_1_0F99_P_2_LEN_0,
 905   MOD_VEX_0FAE_REG_2,
 906   MOD_VEX_0FAE_REG_3,
 907   MOD_VEX_0FD7_PREFIX_2,
 908   MOD_VEX_0FE7_PREFIX_2,
 909   MOD_VEX_0FF0_PREFIX_3,
 910   MOD_VEX_0F381A_PREFIX_2,
 911   MOD_VEX_0F382A_PREFIX_2,
 912   MOD_VEX_0F382C_PREFIX_2,
 913   MOD_VEX_0F382D_PREFIX_2,
 914   MOD_VEX_0F382E_PREFIX_2,
 915   MOD_VEX_0F382F_PREFIX_2,
 916   MOD_VEX_0F385A_PREFIX_2,
 917   MOD_VEX_0F388C_PREFIX_2,
 918   MOD_VEX_0F388E_PREFIX_2,
 919   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 923   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 925   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 927
 928   MOD_EVEX_0F12_PREFIX_0,
 929   MOD_EVEX_0F12_PREFIX_2,
 930   MOD_EVEX_0F13,
 931   MOD_EVEX_0F16_PREFIX_0,
 932   MOD_EVEX_0F16_PREFIX_2,
 933   MOD_EVEX_0F17,
 934   MOD_EVEX_0F2B,
 935   MOD_EVEX_0F38C6_REG_1,
 936   MOD_EVEX_0F38C6_REG_2,
 937   MOD_EVEX_0F38C6_REG_5,
 938   MOD_EVEX_0F38C6_REG_6,
 939   MOD_EVEX_0F38C7_REG_1,
 940   MOD_EVEX_0F38C7_REG_2,
 941   MOD_EVEX_0F38C7_REG_5,
 942   MOD_EVEX_0F38C7_REG_6
 943 };
 944
 945 enum
 946 {
 947   RM_C6_REG_7 = 0,
 948   RM_C7_REG_7,
 949   RM_0F01_REG_0,
 950   RM_0F01_REG_1,
 951   RM_0F01_REG_2,
 952   RM_0F01_REG_3,
 953   RM_0F01_REG_5_MOD_3,
 954   RM_0F01_REG_7_MOD_3,
 955   RM_0F1E_P_1_MOD_3_REG_7,
 956   RM_0FAE_REG_6_MOD_3_P_0,
 957   RM_0FAE_REG_7_MOD_3,
 958 };
 959
 960 enum
 961 {
 962   PREFIX_90 = 0,
 963   PREFIX_0F01_REG_3_RM_1,
 964   PREFIX_0F01_REG_5_MOD_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_0,
 966   PREFIX_0F01_REG_5_MOD_3_RM_1,
 967   PREFIX_0F01_REG_5_MOD_3_RM_2,
 968   PREFIX_0F01_REG_7_MOD_3_RM_2,
 969   PREFIX_0F01_REG_7_MOD_3_RM_3,
 970   PREFIX_0F09,
 971   PREFIX_0F10,
 972   PREFIX_0F11,
 973   PREFIX_0F12,
 974   PREFIX_0F16,
 975   PREFIX_0F1A,
 976   PREFIX_0F1B,
 977   PREFIX_0F1C,
 978   PREFIX_0F1E,
 979   PREFIX_0F2A,
 980   PREFIX_0F2B,
 981   PREFIX_0F2C,
 982   PREFIX_0F2D,
 983   PREFIX_0F2E,
 984   PREFIX_0F2F,
 985   PREFIX_0F51,
 986   PREFIX_0F52,
 987   PREFIX_0F53,
 988   PREFIX_0F58,
 989   PREFIX_0F59,
 990   PREFIX_0F5A,
 991   PREFIX_0F5B,
 992   PREFIX_0F5C,
 993   PREFIX_0F5D,
 994   PREFIX_0F5E,
 995   PREFIX_0F5F,
 996   PREFIX_0F60,
 997   PREFIX_0F61,
 998   PREFIX_0F62,
 999   PREFIX_0F6C,
1000   PREFIX_0F6D,
1001   PREFIX_0F6F,
1002   PREFIX_0F70,
1003   PREFIX_0F73_REG_3,
1004   PREFIX_0F73_REG_7,
1005   PREFIX_0F78,
1006   PREFIX_0F79,
1007   PREFIX_0F7C,
1008   PREFIX_0F7D,
1009   PREFIX_0F7E,
1010   PREFIX_0F7F,
1011   PREFIX_0FAE_REG_0_MOD_3,
1012   PREFIX_0FAE_REG_1_MOD_3,
1013   PREFIX_0FAE_REG_2_MOD_3,
1014   PREFIX_0FAE_REG_3_MOD_3,
1015   PREFIX_0FAE_REG_4_MOD_0,
1016   PREFIX_0FAE_REG_4_MOD_3,
1017   PREFIX_0FAE_REG_5_MOD_0,
1018   PREFIX_0FAE_REG_5_MOD_3,
1019   PREFIX_0FAE_REG_6_MOD_0,
1020   PREFIX_0FAE_REG_6_MOD_3,
1021   PREFIX_0FAE_REG_7_MOD_0,
1022   PREFIX_0FB8,
1023   PREFIX_0FBC,
1024   PREFIX_0FBD,
1025   PREFIX_0FC2,
1026   PREFIX_0FC3_MOD_0,
1027   PREFIX_0FC7_REG_6_MOD_0,
1028   PREFIX_0FC7_REG_6_MOD_3,
1029   PREFIX_0FC7_REG_7_MOD_3,
1030   PREFIX_0FD0,
1031   PREFIX_0FD6,
1032   PREFIX_0FE6,
1033   PREFIX_0FE7,
1034   PREFIX_0FF0,
1035   PREFIX_0FF7,
1036   PREFIX_0F3810,
1037   PREFIX_0F3814,
1038   PREFIX_0F3815,
1039   PREFIX_0F3817,
1040   PREFIX_0F3820,
1041   PREFIX_0F3821,
1042   PREFIX_0F3822,
1043   PREFIX_0F3823,
1044   PREFIX_0F3824,
1045   PREFIX_0F3825,
1046   PREFIX_0F3828,
1047   PREFIX_0F3829,
1048   PREFIX_0F382A,
1049   PREFIX_0F382B,
1050   PREFIX_0F3830,
1051   PREFIX_0F3831,
1052   PREFIX_0F3832,
1053   PREFIX_0F3833,
1054   PREFIX_0F3834,
1055   PREFIX_0F3835,
1056   PREFIX_0F3837,
1057   PREFIX_0F3838,
1058   PREFIX_0F3839,
1059   PREFIX_0F383A,
1060   PREFIX_0F383B,
1061   PREFIX_0F383C,
1062   PREFIX_0F383D,
1063   PREFIX_0F383E,
1064   PREFIX_0F383F,
1065   PREFIX_0F3840,
1066   PREFIX_0F3841,
1067   PREFIX_0F3880,
1068   PREFIX_0F3881,
1069   PREFIX_0F3882,
1070   PREFIX_0F38C8,
1071   PREFIX_0F38C9,
1072   PREFIX_0F38CA,
1073   PREFIX_0F38CB,
1074   PREFIX_0F38CC,
1075   PREFIX_0F38CD,
1076   PREFIX_0F38CF,
1077   PREFIX_0F38DB,
1078   PREFIX_0F38DC,
1079   PREFIX_0F38DD,
1080   PREFIX_0F38DE,
1081   PREFIX_0F38DF,
1082   PREFIX_0F38F0,
1083   PREFIX_0F38F1,
1084   PREFIX_0F38F5,
1085   PREFIX_0F38F6,
1086   PREFIX_0F38F8,
1087   PREFIX_0F38F9,
1088   PREFIX_0F3A08,
1089   PREFIX_0F3A09,
1090   PREFIX_0F3A0A,
1091   PREFIX_0F3A0B,
1092   PREFIX_0F3A0C,
1093   PREFIX_0F3A0D,
1094   PREFIX_0F3A0E,
1095   PREFIX_0F3A14,
1096   PREFIX_0F3A15,
1097   PREFIX_0F3A16,
1098   PREFIX_0F3A17,
1099   PREFIX_0F3A20,
1100   PREFIX_0F3A21,
1101   PREFIX_0F3A22,
1102   PREFIX_0F3A40,
1103   PREFIX_0F3A41,
1104   PREFIX_0F3A42,
1105   PREFIX_0F3A44,
1106   PREFIX_0F3A60,
1107   PREFIX_0F3A61,
1108   PREFIX_0F3A62,
1109   PREFIX_0F3A63,
1110   PREFIX_0F3ACC,
1111   PREFIX_0F3ACE,
1112   PREFIX_0F3ACF,
1113   PREFIX_0F3ADF,
1114   PREFIX_VEX_0F10,
1115   PREFIX_VEX_0F11,
1116   PREFIX_VEX_0F12,
1117   PREFIX_VEX_0F16,
1118   PREFIX_VEX_0F2A,
1119   PREFIX_VEX_0F2C,
1120   PREFIX_VEX_0F2D,
1121   PREFIX_VEX_0F2E,
1122   PREFIX_VEX_0F2F,
1123   PREFIX_VEX_0F41,
1124   PREFIX_VEX_0F42,
1125   PREFIX_VEX_0F44,
1126   PREFIX_VEX_0F45,
1127   PREFIX_VEX_0F46,
1128   PREFIX_VEX_0F47,
1129   PREFIX_VEX_0F4A,
1130   PREFIX_VEX_0F4B,
1131   PREFIX_VEX_0F51,
1132   PREFIX_VEX_0F52,
1133   PREFIX_VEX_0F53,
1134   PREFIX_VEX_0F58,
1135   PREFIX_VEX_0F59,
1136   PREFIX_VEX_0F5A,
1137   PREFIX_VEX_0F5B,
1138   PREFIX_VEX_0F5C,
1139   PREFIX_VEX_0F5D,
1140   PREFIX_VEX_0F5E,
1141   PREFIX_VEX_0F5F,
1142   PREFIX_VEX_0F60,
1143   PREFIX_VEX_0F61,
1144   PREFIX_VEX_0F62,
1145   PREFIX_VEX_0F63,
1146   PREFIX_VEX_0F64,
1147   PREFIX_VEX_0F65,
1148   PREFIX_VEX_0F66,
1149   PREFIX_VEX_0F67,
1150   PREFIX_VEX_0F68,
1151   PREFIX_VEX_0F69,
1152   PREFIX_VEX_0F6A,
1153   PREFIX_VEX_0F6B,
1154   PREFIX_VEX_0F6C,
1155   PREFIX_VEX_0F6D,
1156   PREFIX_VEX_0F6E,
1157   PREFIX_VEX_0F6F,
1158   PREFIX_VEX_0F70,
1159   PREFIX_VEX_0F71_REG_2,
1160   PREFIX_VEX_0F71_REG_4,
1161   PREFIX_VEX_0F71_REG_6,
1162   PREFIX_VEX_0F72_REG_2,
1163   PREFIX_VEX_0F72_REG_4,
1164   PREFIX_VEX_0F72_REG_6,
1165   PREFIX_VEX_0F73_REG_2,
1166   PREFIX_VEX_0F73_REG_3,
1167   PREFIX_VEX_0F73_REG_6,
1168   PREFIX_VEX_0F73_REG_7,
1169   PREFIX_VEX_0F74,
1170   PREFIX_VEX_0F75,
1171   PREFIX_VEX_0F76,
1172   PREFIX_VEX_0F77,
1173   PREFIX_VEX_0F7C,
1174   PREFIX_VEX_0F7D,
1175   PREFIX_VEX_0F7E,
1176   PREFIX_VEX_0F7F,
1177   PREFIX_VEX_0F90,
1178   PREFIX_VEX_0F91,
1179   PREFIX_VEX_0F92,
1180   PREFIX_VEX_0F93,
1181   PREFIX_VEX_0F98,
1182   PREFIX_VEX_0F99,
1183   PREFIX_VEX_0FC2,
1184   PREFIX_VEX_0FC4,
1185   PREFIX_VEX_0FC5,
1186   PREFIX_VEX_0FD0,
1187   PREFIX_VEX_0FD1,
1188   PREFIX_VEX_0FD2,
1189   PREFIX_VEX_0FD3,
1190   PREFIX_VEX_0FD4,
1191   PREFIX_VEX_0FD5,
1192   PREFIX_VEX_0FD6,
1193   PREFIX_VEX_0FD7,
1194   PREFIX_VEX_0FD8,
1195   PREFIX_VEX_0FD9,
1196   PREFIX_VEX_0FDA,
1197   PREFIX_VEX_0FDB,
1198   PREFIX_VEX_0FDC,
1199   PREFIX_VEX_0FDD,
1200   PREFIX_VEX_0FDE,
1201   PREFIX_VEX_0FDF,
1202   PREFIX_VEX_0FE0,
1203   PREFIX_VEX_0FE1,
1204   PREFIX_VEX_0FE2,
1205   PREFIX_VEX_0FE3,
1206   PREFIX_VEX_0FE4,
1207   PREFIX_VEX_0FE5,
1208   PREFIX_VEX_0FE6,
1209   PREFIX_VEX_0FE7,
1210   PREFIX_VEX_0FE8,
1211   PREFIX_VEX_0FE9,
1212   PREFIX_VEX_0FEA,
1213   PREFIX_VEX_0FEB,
1214   PREFIX_VEX_0FEC,
1215   PREFIX_VEX_0FED,
1216   PREFIX_VEX_0FEE,
1217   PREFIX_VEX_0FEF,
1218   PREFIX_VEX_0FF0,
1219   PREFIX_VEX_0FF1,
1220   PREFIX_VEX_0FF2,
1221   PREFIX_VEX_0FF3,
1222   PREFIX_VEX_0FF4,
1223   PREFIX_VEX_0FF5,
1224   PREFIX_VEX_0FF6,
1225   PREFIX_VEX_0FF7,
1226   PREFIX_VEX_0FF8,
1227   PREFIX_VEX_0FF9,
1228   PREFIX_VEX_0FFA,
1229   PREFIX_VEX_0FFB,
1230   PREFIX_VEX_0FFC,
1231   PREFIX_VEX_0FFD,
1232   PREFIX_VEX_0FFE,
1233   PREFIX_VEX_0F3800,
1234   PREFIX_VEX_0F3801,
1235   PREFIX_VEX_0F3802,
1236   PREFIX_VEX_0F3803,
1237   PREFIX_VEX_0F3804,
1238   PREFIX_VEX_0F3805,
1239   PREFIX_VEX_0F3806,
1240   PREFIX_VEX_0F3807,
1241   PREFIX_VEX_0F3808,
1242   PREFIX_VEX_0F3809,
1243   PREFIX_VEX_0F380A,
1244   PREFIX_VEX_0F380B,
1245   PREFIX_VEX_0F380C,
1246   PREFIX_VEX_0F380D,
1247   PREFIX_VEX_0F380E,
1248   PREFIX_VEX_0F380F,
1249   PREFIX_VEX_0F3813,
1250   PREFIX_VEX_0F3816,
1251   PREFIX_VEX_0F3817,
1252   PREFIX_VEX_0F3818,
1253   PREFIX_VEX_0F3819,
1254   PREFIX_VEX_0F381A,
1255   PREFIX_VEX_0F381C,
1256   PREFIX_VEX_0F381D,
1257   PREFIX_VEX_0F381E,
1258   PREFIX_VEX_0F3820,
1259   PREFIX_VEX_0F3821,
1260   PREFIX_VEX_0F3822,
1261   PREFIX_VEX_0F3823,
1262   PREFIX_VEX_0F3824,
1263   PREFIX_VEX_0F3825,
1264   PREFIX_VEX_0F3828,
1265   PREFIX_VEX_0F3829,
1266   PREFIX_VEX_0F382A,
1267   PREFIX_VEX_0F382B,
1268   PREFIX_VEX_0F382C,
1269   PREFIX_VEX_0F382D,
1270   PREFIX_VEX_0F382E,
1271   PREFIX_VEX_0F382F,
1272   PREFIX_VEX_0F3830,
1273   PREFIX_VEX_0F3831,
1274   PREFIX_VEX_0F3832,
1275   PREFIX_VEX_0F3833,
1276   PREFIX_VEX_0F3834,
1277   PREFIX_VEX_0F3835,
1278   PREFIX_VEX_0F3836,
1279   PREFIX_VEX_0F3837,
1280   PREFIX_VEX_0F3838,
1281   PREFIX_VEX_0F3839,
1282   PREFIX_VEX_0F383A,
1283   PREFIX_VEX_0F383B,
1284   PREFIX_VEX_0F383C,
1285   PREFIX_VEX_0F383D,
1286   PREFIX_VEX_0F383E,
1287   PREFIX_VEX_0F383F,
1288   PREFIX_VEX_0F3840,
1289   PREFIX_VEX_0F3841,
1290   PREFIX_VEX_0F3845,
1291   PREFIX_VEX_0F3846,
1292   PREFIX_VEX_0F3847,
1293   PREFIX_VEX_0F3858,
1294   PREFIX_VEX_0F3859,
1295   PREFIX_VEX_0F385A,
1296   PREFIX_VEX_0F3878,
1297   PREFIX_VEX_0F3879,
1298   PREFIX_VEX_0F388C,
1299   PREFIX_VEX_0F388E,
1300   PREFIX_VEX_0F3890,
1301   PREFIX_VEX_0F3891,
1302   PREFIX_VEX_0F3892,
1303   PREFIX_VEX_0F3893,
1304   PREFIX_VEX_0F3896,
1305   PREFIX_VEX_0F3897,
1306   PREFIX_VEX_0F3898,
1307   PREFIX_VEX_0F3899,
1308   PREFIX_VEX_0F389A,
1309   PREFIX_VEX_0F389B,
1310   PREFIX_VEX_0F389C,
1311   PREFIX_VEX_0F389D,
1312   PREFIX_VEX_0F389E,
1313   PREFIX_VEX_0F389F,
1314   PREFIX_VEX_0F38A6,
1315   PREFIX_VEX_0F38A7,
1316   PREFIX_VEX_0F38A8,
1317   PREFIX_VEX_0F38A9,
1318   PREFIX_VEX_0F38AA,
1319   PREFIX_VEX_0F38AB,
1320   PREFIX_VEX_0F38AC,
1321   PREFIX_VEX_0F38AD,
1322   PREFIX_VEX_0F38AE,
1323   PREFIX_VEX_0F38AF,
1324   PREFIX_VEX_0F38B6,
1325   PREFIX_VEX_0F38B7,
1326   PREFIX_VEX_0F38B8,
1327   PREFIX_VEX_0F38B9,
1328   PREFIX_VEX_0F38BA,
1329   PREFIX_VEX_0F38BB,
1330   PREFIX_VEX_0F38BC,
1331   PREFIX_VEX_0F38BD,
1332   PREFIX_VEX_0F38BE,
1333   PREFIX_VEX_0F38BF,
1334   PREFIX_VEX_0F38CF,
1335   PREFIX_VEX_0F38DB,
1336   PREFIX_VEX_0F38DC,
1337   PREFIX_VEX_0F38DD,
1338   PREFIX_VEX_0F38DE,
1339   PREFIX_VEX_0F38DF,
1340   PREFIX_VEX_0F38F2,
1341   PREFIX_VEX_0F38F3_REG_1,
1342   PREFIX_VEX_0F38F3_REG_2,
1343   PREFIX_VEX_0F38F3_REG_3,
1344   PREFIX_VEX_0F38F5,
1345   PREFIX_VEX_0F38F6,
1346   PREFIX_VEX_0F38F7,
1347   PREFIX_VEX_0F3A00,
1348   PREFIX_VEX_0F3A01,
1349   PREFIX_VEX_0F3A02,
1350   PREFIX_VEX_0F3A04,
1351   PREFIX_VEX_0F3A05,
1352   PREFIX_VEX_0F3A06,
1353   PREFIX_VEX_0F3A08,
1354   PREFIX_VEX_0F3A09,
1355   PREFIX_VEX_0F3A0A,
1356   PREFIX_VEX_0F3A0B,
1357   PREFIX_VEX_0F3A0C,
1358   PREFIX_VEX_0F3A0D,
1359   PREFIX_VEX_0F3A0E,
1360   PREFIX_VEX_0F3A0F,
1361   PREFIX_VEX_0F3A14,
1362   PREFIX_VEX_0F3A15,
1363   PREFIX_VEX_0F3A16,
1364   PREFIX_VEX_0F3A17,
1365   PREFIX_VEX_0F3A18,
1366   PREFIX_VEX_0F3A19,
1367   PREFIX_VEX_0F3A1D,
1368   PREFIX_VEX_0F3A20,
1369   PREFIX_VEX_0F3A21,
1370   PREFIX_VEX_0F3A22,
1371   PREFIX_VEX_0F3A30,
1372   PREFIX_VEX_0F3A31,
1373   PREFIX_VEX_0F3A32,
1374   PREFIX_VEX_0F3A33,
1375   PREFIX_VEX_0F3A38,
1376   PREFIX_VEX_0F3A39,
1377   PREFIX_VEX_0F3A40,
1378   PREFIX_VEX_0F3A41,
1379   PREFIX_VEX_0F3A42,
1380   PREFIX_VEX_0F3A44,
1381   PREFIX_VEX_0F3A46,
1382   PREFIX_VEX_0F3A48,
1383   PREFIX_VEX_0F3A49,
1384   PREFIX_VEX_0F3A4A,
1385   PREFIX_VEX_0F3A4B,
1386   PREFIX_VEX_0F3A4C,
1387   PREFIX_VEX_0F3A5C,
1388   PREFIX_VEX_0F3A5D,
1389   PREFIX_VEX_0F3A5E,
1390   PREFIX_VEX_0F3A5F,
1391   PREFIX_VEX_0F3A60,
1392   PREFIX_VEX_0F3A61,
1393   PREFIX_VEX_0F3A62,
1394   PREFIX_VEX_0F3A63,
1395   PREFIX_VEX_0F3A68,
1396   PREFIX_VEX_0F3A69,
1397   PREFIX_VEX_0F3A6A,
1398   PREFIX_VEX_0F3A6B,
1399   PREFIX_VEX_0F3A6C,
1400   PREFIX_VEX_0F3A6D,
1401   PREFIX_VEX_0F3A6E,
1402   PREFIX_VEX_0F3A6F,
1403   PREFIX_VEX_0F3A78,
1404   PREFIX_VEX_0F3A79,
1405   PREFIX_VEX_0F3A7A,
1406   PREFIX_VEX_0F3A7B,
1407   PREFIX_VEX_0F3A7C,
1408   PREFIX_VEX_0F3A7D,
1409   PREFIX_VEX_0F3A7E,
1410   PREFIX_VEX_0F3A7F,
1411   PREFIX_VEX_0F3ACE,
1412   PREFIX_VEX_0F3ACF,
1413   PREFIX_VEX_0F3ADF,
1414   PREFIX_VEX_0F3AF0,
1415
1416   PREFIX_EVEX_0F10,
1417   PREFIX_EVEX_0F11,
1418   PREFIX_EVEX_0F12,
1419   PREFIX_EVEX_0F16,
1420   PREFIX_EVEX_0F2A,
1421   PREFIX_EVEX_0F2C,
1422   PREFIX_EVEX_0F2D,
1423   PREFIX_EVEX_0F2E,
1424   PREFIX_EVEX_0F2F,
1425   PREFIX_EVEX_0F51,
1426   PREFIX_EVEX_0F58,
1427   PREFIX_EVEX_0F59,
1428   PREFIX_EVEX_0F5A,
1429   PREFIX_EVEX_0F5B,
1430   PREFIX_EVEX_0F5C,
1431   PREFIX_EVEX_0F5D,
1432   PREFIX_EVEX_0F5E,
1433   PREFIX_EVEX_0F5F,
1434   PREFIX_EVEX_0F62,
1435   PREFIX_EVEX_0F64,
1436   PREFIX_EVEX_0F65,
1437   PREFIX_EVEX_0F66,
1438   PREFIX_EVEX_0F6A,
1439   PREFIX_EVEX_0F6B,
1440   PREFIX_EVEX_0F6C,
1441   PREFIX_EVEX_0F6D,
1442   PREFIX_EVEX_0F6E,
1443   PREFIX_EVEX_0F6F,
1444   PREFIX_EVEX_0F70,
1445   PREFIX_EVEX_0F71_REG_2,
1446   PREFIX_EVEX_0F71_REG_4,
1447   PREFIX_EVEX_0F71_REG_6,
1448   PREFIX_EVEX_0F72_REG_0,
1449   PREFIX_EVEX_0F72_REG_1,
1450   PREFIX_EVEX_0F72_REG_2,
1451   PREFIX_EVEX_0F72_REG_4,
1452   PREFIX_EVEX_0F72_REG_6,
1453   PREFIX_EVEX_0F73_REG_2,
1454   PREFIX_EVEX_0F73_REG_3,
1455   PREFIX_EVEX_0F73_REG_6,
1456   PREFIX_EVEX_0F73_REG_7,
1457   PREFIX_EVEX_0F74,
1458   PREFIX_EVEX_0F75,
1459   PREFIX_EVEX_0F76,
1460   PREFIX_EVEX_0F78,
1461   PREFIX_EVEX_0F79,
1462   PREFIX_EVEX_0F7A,
1463   PREFIX_EVEX_0F7B,
1464   PREFIX_EVEX_0F7E,
1465   PREFIX_EVEX_0F7F,
1466   PREFIX_EVEX_0FC2,
1467   PREFIX_EVEX_0FC4,
1468   PREFIX_EVEX_0FC5,
1469   PREFIX_EVEX_0FD2,
1470   PREFIX_EVEX_0FD3,
1471   PREFIX_EVEX_0FD4,
1472   PREFIX_EVEX_0FD6,
1473   PREFIX_EVEX_0FDB,
1474   PREFIX_EVEX_0FDF,
1475   PREFIX_EVEX_0FE2,
1476   PREFIX_EVEX_0FE6,
1477   PREFIX_EVEX_0FE7,
1478   PREFIX_EVEX_0FEB,
1479   PREFIX_EVEX_0FEF,
1480   PREFIX_EVEX_0FF2,
1481   PREFIX_EVEX_0FF3,
1482   PREFIX_EVEX_0FF4,
1483   PREFIX_EVEX_0FFA,
1484   PREFIX_EVEX_0FFB,
1485   PREFIX_EVEX_0FFE,
1486   PREFIX_EVEX_0F380D,
1487   PREFIX_EVEX_0F3810,
1488   PREFIX_EVEX_0F3811,
1489   PREFIX_EVEX_0F3812,
1490   PREFIX_EVEX_0F3813,
1491   PREFIX_EVEX_0F3814,
1492   PREFIX_EVEX_0F3815,
1493   PREFIX_EVEX_0F3816,
1494   PREFIX_EVEX_0F3819,
1495   PREFIX_EVEX_0F381A,
1496   PREFIX_EVEX_0F381B,
1497   PREFIX_EVEX_0F381E,
1498   PREFIX_EVEX_0F381F,
1499   PREFIX_EVEX_0F3820,
1500   PREFIX_EVEX_0F3821,
1501   PREFIX_EVEX_0F3822,
1502   PREFIX_EVEX_0F3823,
1503   PREFIX_EVEX_0F3824,
1504   PREFIX_EVEX_0F3825,
1505   PREFIX_EVEX_0F3826,
1506   PREFIX_EVEX_0F3827,
1507   PREFIX_EVEX_0F3828,
1508   PREFIX_EVEX_0F3829,
1509   PREFIX_EVEX_0F382A,
1510   PREFIX_EVEX_0F382B,
1511   PREFIX_EVEX_0F382C,
1512   PREFIX_EVEX_0F382D,
1513   PREFIX_EVEX_0F3830,
1514   PREFIX_EVEX_0F3831,
1515   PREFIX_EVEX_0F3832,
1516   PREFIX_EVEX_0F3833,
1517   PREFIX_EVEX_0F3834,
1518   PREFIX_EVEX_0F3835,
1519   PREFIX_EVEX_0F3836,
1520   PREFIX_EVEX_0F3837,
1521   PREFIX_EVEX_0F3838,
1522   PREFIX_EVEX_0F3839,
1523   PREFIX_EVEX_0F383A,
1524   PREFIX_EVEX_0F383B,
1525   PREFIX_EVEX_0F383D,
1526   PREFIX_EVEX_0F383F,
1527   PREFIX_EVEX_0F3840,
1528   PREFIX_EVEX_0F3842,
1529   PREFIX_EVEX_0F3843,
1530   PREFIX_EVEX_0F3844,
1531   PREFIX_EVEX_0F3845,
1532   PREFIX_EVEX_0F3846,
1533   PREFIX_EVEX_0F3847,
1534   PREFIX_EVEX_0F384C,
1535   PREFIX_EVEX_0F384D,
1536   PREFIX_EVEX_0F384E,
1537   PREFIX_EVEX_0F384F,
1538   PREFIX_EVEX_0F3850,
1539   PREFIX_EVEX_0F3851,
1540   PREFIX_EVEX_0F3852,
1541   PREFIX_EVEX_0F3853,
1542   PREFIX_EVEX_0F3854,
1543   PREFIX_EVEX_0F3855,
1544   PREFIX_EVEX_0F3859,
1545   PREFIX_EVEX_0F385A,
1546   PREFIX_EVEX_0F385B,
1547   PREFIX_EVEX_0F3862,
1548   PREFIX_EVEX_0F3863,
1549   PREFIX_EVEX_0F3864,
1550   PREFIX_EVEX_0F3865,
1551   PREFIX_EVEX_0F3866,
1552   PREFIX_EVEX_0F3868,
1553   PREFIX_EVEX_0F3870,
1554   PREFIX_EVEX_0F3871,
1555   PREFIX_EVEX_0F3872,
1556   PREFIX_EVEX_0F3873,
1557   PREFIX_EVEX_0F3875,
1558   PREFIX_EVEX_0F3876,
1559   PREFIX_EVEX_0F3877,
1560   PREFIX_EVEX_0F387A,
1561   PREFIX_EVEX_0F387B,
1562   PREFIX_EVEX_0F387C,
1563   PREFIX_EVEX_0F387D,
1564   PREFIX_EVEX_0F387E,
1565   PREFIX_EVEX_0F387F,
1566   PREFIX_EVEX_0F3883,
1567   PREFIX_EVEX_0F3888,
1568   PREFIX_EVEX_0F3889,
1569   PREFIX_EVEX_0F388A,
1570   PREFIX_EVEX_0F388B,
1571   PREFIX_EVEX_0F388D,
1572   PREFIX_EVEX_0F388F,
1573   PREFIX_EVEX_0F3890,
1574   PREFIX_EVEX_0F3891,
1575   PREFIX_EVEX_0F3892,
1576   PREFIX_EVEX_0F3893,
1577   PREFIX_EVEX_0F389A,
1578   PREFIX_EVEX_0F389B,
1579   PREFIX_EVEX_0F38A0,
1580   PREFIX_EVEX_0F38A1,
1581   PREFIX_EVEX_0F38A2,
1582   PREFIX_EVEX_0F38A3,
1583   PREFIX_EVEX_0F38AA,
1584   PREFIX_EVEX_0F38AB,
1585   PREFIX_EVEX_0F38B4,
1586   PREFIX_EVEX_0F38B5,
1587   PREFIX_EVEX_0F38C4,
1588   PREFIX_EVEX_0F38C6_REG_1,
1589   PREFIX_EVEX_0F38C6_REG_2,
1590   PREFIX_EVEX_0F38C6_REG_5,
1591   PREFIX_EVEX_0F38C6_REG_6,
1592   PREFIX_EVEX_0F38C7_REG_1,
1593   PREFIX_EVEX_0F38C7_REG_2,
1594   PREFIX_EVEX_0F38C7_REG_5,
1595   PREFIX_EVEX_0F38C7_REG_6,
1596   PREFIX_EVEX_0F38C8,
1597   PREFIX_EVEX_0F38CA,
1598   PREFIX_EVEX_0F38CB,
1599   PREFIX_EVEX_0F38CC,
1600   PREFIX_EVEX_0F38CD,
1601
1602   PREFIX_EVEX_0F3A00,
1603   PREFIX_EVEX_0F3A01,
1604   PREFIX_EVEX_0F3A03,
1605   PREFIX_EVEX_0F3A05,
1606   PREFIX_EVEX_0F3A08,
1607   PREFIX_EVEX_0F3A09,
1608   PREFIX_EVEX_0F3A0A,
1609   PREFIX_EVEX_0F3A0B,
1610   PREFIX_EVEX_0F3A14,
1611   PREFIX_EVEX_0F3A15,
1612   PREFIX_EVEX_0F3A16,
1613   PREFIX_EVEX_0F3A17,
1614   PREFIX_EVEX_0F3A18,
1615   PREFIX_EVEX_0F3A19,
1616   PREFIX_EVEX_0F3A1A,
1617   PREFIX_EVEX_0F3A1B,
1618   PREFIX_EVEX_0F3A1D,
1619   PREFIX_EVEX_0F3A1E,
1620   PREFIX_EVEX_0F3A1F,
1621   PREFIX_EVEX_0F3A20,
1622   PREFIX_EVEX_0F3A21,
1623   PREFIX_EVEX_0F3A22,
1624   PREFIX_EVEX_0F3A23,
1625   PREFIX_EVEX_0F3A25,
1626   PREFIX_EVEX_0F3A26,
1627   PREFIX_EVEX_0F3A27,
1628   PREFIX_EVEX_0F3A38,
1629   PREFIX_EVEX_0F3A39,
1630   PREFIX_EVEX_0F3A3A,
1631   PREFIX_EVEX_0F3A3B,
1632   PREFIX_EVEX_0F3A3E,
1633   PREFIX_EVEX_0F3A3F,
1634   PREFIX_EVEX_0F3A42,
1635   PREFIX_EVEX_0F3A43,
1636   PREFIX_EVEX_0F3A50,
1637   PREFIX_EVEX_0F3A51,
1638   PREFIX_EVEX_0F3A54,
1639   PREFIX_EVEX_0F3A55,
1640   PREFIX_EVEX_0F3A56,
1641   PREFIX_EVEX_0F3A57,
1642   PREFIX_EVEX_0F3A66,
1643   PREFIX_EVEX_0F3A67,
1644   PREFIX_EVEX_0F3A70,
1645   PREFIX_EVEX_0F3A71,
1646   PREFIX_EVEX_0F3A72,
1647   PREFIX_EVEX_0F3A73,
1648 };
1649
1650 enum
1651 {
1652   X86_64_06 = 0,
1653   X86_64_07,
1654   X86_64_0E,
1655   X86_64_16,
1656   X86_64_17,
1657   X86_64_1E,
1658   X86_64_1F,
1659   X86_64_27,
1660   X86_64_2F,
1661   X86_64_37,
1662   X86_64_3F,
1663   X86_64_60,
1664   X86_64_61,
1665   X86_64_62,
1666   X86_64_63,
1667   X86_64_6D,
1668   X86_64_6F,
1669   X86_64_82,
1670   X86_64_9A,
1671   X86_64_C2,
1672   X86_64_C3,
1673   X86_64_C4,
1674   X86_64_C5,
1675   X86_64_CE,
1676   X86_64_D4,
1677   X86_64_D5,
1678   X86_64_E8,
1679   X86_64_E9,
1680   X86_64_EA,
1681   X86_64_0F01_REG_0,
1682   X86_64_0F01_REG_1,
1683   X86_64_0F01_REG_2,
1684   X86_64_0F01_REG_3
1685 };
1686
1687 enum
1688 {
1689   THREE_BYTE_0F38 = 0,
1690   THREE_BYTE_0F3A
1691 };
1692
1693 enum
1694 {
1695   XOP_08 = 0,
1696   XOP_09,
1697   XOP_0A
1698 };
1699
1700 enum
1701 {
1702   VEX_0F = 0,
1703   VEX_0F38,
1704   VEX_0F3A
1705 };
1706
1707 enum
1708 {
1709   EVEX_0F = 0,
1710   EVEX_0F38,
1711   EVEX_0F3A
1712 };
1713
1714 enum
1715 {
1716   VEX_LEN_0F12_P_0_M_0 = 0,
1717   VEX_LEN_0F12_P_0_M_1,
1718 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1719   VEX_LEN_0F13_M_0,
1720   VEX_LEN_0F16_P_0_M_0,
1721   VEX_LEN_0F16_P_0_M_1,
1722 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1723   VEX_LEN_0F17_M_0,
1724   VEX_LEN_0F41_P_0,
1725   VEX_LEN_0F41_P_2,
1726   VEX_LEN_0F42_P_0,
1727   VEX_LEN_0F42_P_2,
1728   VEX_LEN_0F44_P_0,
1729   VEX_LEN_0F44_P_2,
1730   VEX_LEN_0F45_P_0,
1731   VEX_LEN_0F45_P_2,
1732   VEX_LEN_0F46_P_0,
1733   VEX_LEN_0F46_P_2,
1734   VEX_LEN_0F47_P_0,
1735   VEX_LEN_0F47_P_2,
1736   VEX_LEN_0F4A_P_0,
1737   VEX_LEN_0F4A_P_2,
1738   VEX_LEN_0F4B_P_0,
1739   VEX_LEN_0F4B_P_2,
1740   VEX_LEN_0F6E_P_2,
1741   VEX_LEN_0F77_P_0,
1742   VEX_LEN_0F7E_P_1,
1743   VEX_LEN_0F7E_P_2,
1744   VEX_LEN_0F90_P_0,
1745   VEX_LEN_0F90_P_2,
1746   VEX_LEN_0F91_P_0,
1747   VEX_LEN_0F91_P_2,
1748   VEX_LEN_0F92_P_0,
1749   VEX_LEN_0F92_P_2,
1750   VEX_LEN_0F92_P_3,
1751   VEX_LEN_0F93_P_0,
1752   VEX_LEN_0F93_P_2,
1753   VEX_LEN_0F93_P_3,
1754   VEX_LEN_0F98_P_0,
1755   VEX_LEN_0F98_P_2,
1756   VEX_LEN_0F99_P_0,
1757   VEX_LEN_0F99_P_2,
1758   VEX_LEN_0FAE_R_2_M_0,
1759   VEX_LEN_0FAE_R_3_M_0,
1760   VEX_LEN_0FC4_P_2,
1761   VEX_LEN_0FC5_P_2,
1762   VEX_LEN_0FD6_P_2,
1763   VEX_LEN_0FF7_P_2,
1764   VEX_LEN_0F3816_P_2,
1765   VEX_LEN_0F3819_P_2,
1766   VEX_LEN_0F381A_P_2_M_0,
1767   VEX_LEN_0F3836_P_2,
1768   VEX_LEN_0F3841_P_2,
1769   VEX_LEN_0F385A_P_2_M_0,
1770   VEX_LEN_0F38DB_P_2,
1771   VEX_LEN_0F38F2_P_0,
1772   VEX_LEN_0F38F3_R_1_P_0,
1773   VEX_LEN_0F38F3_R_2_P_0,
1774   VEX_LEN_0F38F3_R_3_P_0,
1775   VEX_LEN_0F38F5_P_0,
1776   VEX_LEN_0F38F5_P_1,
1777   VEX_LEN_0F38F5_P_3,
1778   VEX_LEN_0F38F6_P_3,
1779   VEX_LEN_0F38F7_P_0,
1780   VEX_LEN_0F38F7_P_1,
1781   VEX_LEN_0F38F7_P_2,
1782   VEX_LEN_0F38F7_P_3,
1783   VEX_LEN_0F3A00_P_2,
1784   VEX_LEN_0F3A01_P_2,
1785   VEX_LEN_0F3A06_P_2,
1786   VEX_LEN_0F3A14_P_2,
1787   VEX_LEN_0F3A15_P_2,
1788   VEX_LEN_0F3A16_P_2,
1789   VEX_LEN_0F3A17_P_2,
1790   VEX_LEN_0F3A18_P_2,
1791   VEX_LEN_0F3A19_P_2,
1792   VEX_LEN_0F3A20_P_2,
1793   VEX_LEN_0F3A21_P_2,
1794   VEX_LEN_0F3A22_P_2,
1795   VEX_LEN_0F3A30_P_2,
1796   VEX_LEN_0F3A31_P_2,
1797   VEX_LEN_0F3A32_P_2,
1798   VEX_LEN_0F3A33_P_2,
1799   VEX_LEN_0F3A38_P_2,
1800   VEX_LEN_0F3A39_P_2,
1801   VEX_LEN_0F3A41_P_2,
1802   VEX_LEN_0F3A46_P_2,
1803   VEX_LEN_0F3A60_P_2,
1804   VEX_LEN_0F3A61_P_2,
1805   VEX_LEN_0F3A62_P_2,
1806   VEX_LEN_0F3A63_P_2,
1807   VEX_LEN_0F3A6A_P_2,
1808   VEX_LEN_0F3A6B_P_2,
1809   VEX_LEN_0F3A6E_P_2,
1810   VEX_LEN_0F3A6F_P_2,
1811   VEX_LEN_0F3A7A_P_2,
1812   VEX_LEN_0F3A7B_P_2,
1813   VEX_LEN_0F3A7E_P_2,
1814   VEX_LEN_0F3A7F_P_2,
1815   VEX_LEN_0F3ADF_P_2,
1816   VEX_LEN_0F3AF0_P_3,
1817   VEX_LEN_0FXOP_08_CC,
1818   VEX_LEN_0FXOP_08_CD,
1819   VEX_LEN_0FXOP_08_CE,
1820   VEX_LEN_0FXOP_08_CF,
1821   VEX_LEN_0FXOP_08_EC,
1822   VEX_LEN_0FXOP_08_ED,
1823   VEX_LEN_0FXOP_08_EE,
1824   VEX_LEN_0FXOP_08_EF,
1825   VEX_LEN_0FXOP_09_80,
1826   VEX_LEN_0FXOP_09_81
1827 };
1828
1829 enum
1830 {
1831   EVEX_LEN_0F6E_P_2 = 0,
1832   EVEX_LEN_0F7E_P_1,
1833   EVEX_LEN_0F7E_P_2,
1834   EVEX_LEN_0FD6_P_2,
1835   EVEX_LEN_0F3819_P_2_W_0,
1836   EVEX_LEN_0F3819_P_2_W_1,
1837   EVEX_LEN_0F381A_P_2_W_0,
1838   EVEX_LEN_0F381A_P_2_W_1,
1839   EVEX_LEN_0F381B_P_2_W_0,
1840   EVEX_LEN_0F381B_P_2_W_1,
1841   EVEX_LEN_0F385A_P_2_W_0,
1842   EVEX_LEN_0F385A_P_2_W_1,
1843   EVEX_LEN_0F385B_P_2_W_0,
1844   EVEX_LEN_0F385B_P_2_W_1,
1845   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1846   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1847   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1848   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1849   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1850   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1851   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1852   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1853   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1854   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1855   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1856   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1857   EVEX_LEN_0F3A18_P_2_W_0,
1858   EVEX_LEN_0F3A18_P_2_W_1,
1859   EVEX_LEN_0F3A19_P_2_W_0,
1860   EVEX_LEN_0F3A19_P_2_W_1,
1861   EVEX_LEN_0F3A1A_P_2_W_0,
1862   EVEX_LEN_0F3A1A_P_2_W_1,
1863   EVEX_LEN_0F3A1B_P_2_W_0,
1864   EVEX_LEN_0F3A1B_P_2_W_1,
1865   EVEX_LEN_0F3A23_P_2_W_0,
1866   EVEX_LEN_0F3A23_P_2_W_1,
1867   EVEX_LEN_0F3A38_P_2_W_0,
1868   EVEX_LEN_0F3A38_P_2_W_1,
1869   EVEX_LEN_0F3A39_P_2_W_0,
1870   EVEX_LEN_0F3A39_P_2_W_1,
1871   EVEX_LEN_0F3A3A_P_2_W_0,
1872   EVEX_LEN_0F3A3A_P_2_W_1,
1873   EVEX_LEN_0F3A3B_P_2_W_0,
1874   EVEX_LEN_0F3A3B_P_2_W_1,
1875   EVEX_LEN_0F3A43_P_2_W_0,
1876   EVEX_LEN_0F3A43_P_2_W_1
1877 };
1878
1879 enum
1880 {
1881   VEX_W_0F41_P_0_LEN_1 = 0,
1882   VEX_W_0F41_P_2_LEN_1,
1883   VEX_W_0F42_P_0_LEN_1,
1884   VEX_W_0F42_P_2_LEN_1,
1885   VEX_W_0F44_P_0_LEN_0,
1886   VEX_W_0F44_P_2_LEN_0,
1887   VEX_W_0F45_P_0_LEN_1,
1888   VEX_W_0F45_P_2_LEN_1,
1889   VEX_W_0F46_P_0_LEN_1,
1890   VEX_W_0F46_P_2_LEN_1,
1891   VEX_W_0F47_P_0_LEN_1,
1892   VEX_W_0F47_P_2_LEN_1,
1893   VEX_W_0F4A_P_0_LEN_1,
1894   VEX_W_0F4A_P_2_LEN_1,
1895   VEX_W_0F4B_P_0_LEN_1,
1896   VEX_W_0F4B_P_2_LEN_1,
1897   VEX_W_0F90_P_0_LEN_0,
1898   VEX_W_0F90_P_2_LEN_0,
1899   VEX_W_0F91_P_0_LEN_0,
1900   VEX_W_0F91_P_2_LEN_0,
1901   VEX_W_0F92_P_0_LEN_0,
1902   VEX_W_0F92_P_2_LEN_0,
1903   VEX_W_0F93_P_0_LEN_0,
1904   VEX_W_0F93_P_2_LEN_0,
1905   VEX_W_0F98_P_0_LEN_0,
1906   VEX_W_0F98_P_2_LEN_0,
1907   VEX_W_0F99_P_0_LEN_0,
1908   VEX_W_0F99_P_2_LEN_0,
1909   VEX_W_0F380C_P_2,
1910   VEX_W_0F380D_P_2,
1911   VEX_W_0F380E_P_2,
1912   VEX_W_0F380F_P_2,
1913   VEX_W_0F3816_P_2,
1914   VEX_W_0F3818_P_2,
1915   VEX_W_0F3819_P_2,
1916   VEX_W_0F381A_P_2_M_0,
1917   VEX_W_0F382C_P_2_M_0,
1918   VEX_W_0F382D_P_2_M_0,
1919   VEX_W_0F382E_P_2_M_0,
1920   VEX_W_0F382F_P_2_M_0,
1921   VEX_W_0F3836_P_2,
1922   VEX_W_0F3846_P_2,
1923   VEX_W_0F3858_P_2,
1924   VEX_W_0F3859_P_2,
1925   VEX_W_0F385A_P_2_M_0,
1926   VEX_W_0F3878_P_2,
1927   VEX_W_0F3879_P_2,
1928   VEX_W_0F38CF_P_2,
1929   VEX_W_0F3A00_P_2,
1930   VEX_W_0F3A01_P_2,
1931   VEX_W_0F3A02_P_2,
1932   VEX_W_0F3A04_P_2,
1933   VEX_W_0F3A05_P_2,
1934   VEX_W_0F3A06_P_2,
1935   VEX_W_0F3A18_P_2,
1936   VEX_W_0F3A19_P_2,
1937   VEX_W_0F3A30_P_2_LEN_0,
1938   VEX_W_0F3A31_P_2_LEN_0,
1939   VEX_W_0F3A32_P_2_LEN_0,
1940   VEX_W_0F3A33_P_2_LEN_0,
1941   VEX_W_0F3A38_P_2,
1942   VEX_W_0F3A39_P_2,
1943   VEX_W_0F3A46_P_2,
1944   VEX_W_0F3A48_P_2,
1945   VEX_W_0F3A49_P_2,
1946   VEX_W_0F3A4A_P_2,
1947   VEX_W_0F3A4B_P_2,
1948   VEX_W_0F3A4C_P_2,
1949   VEX_W_0F3ACE_P_2,
1950   VEX_W_0F3ACF_P_2,
1951
1952   EVEX_W_0F10_P_1,
1953   EVEX_W_0F10_P_3,
1954   EVEX_W_0F11_P_1,
1955   EVEX_W_0F11_P_3,
1956   EVEX_W_0F12_P_0_M_1,
1957   EVEX_W_0F12_P_1,
1958   EVEX_W_0F12_P_3,
1959   EVEX_W_0F16_P_0_M_1,
1960   EVEX_W_0F16_P_1,
1961   EVEX_W_0F2A_P_3,
1962   EVEX_W_0F51_P_1,
1963   EVEX_W_0F51_P_3,
1964   EVEX_W_0F58_P_1,
1965   EVEX_W_0F58_P_3,
1966   EVEX_W_0F59_P_1,
1967   EVEX_W_0F59_P_3,
1968   EVEX_W_0F5A_P_0,
1969   EVEX_W_0F5A_P_1,
1970   EVEX_W_0F5A_P_2,
1971   EVEX_W_0F5A_P_3,
1972   EVEX_W_0F5B_P_0,
1973   EVEX_W_0F5B_P_1,
1974   EVEX_W_0F5B_P_2,
1975   EVEX_W_0F5C_P_1,
1976   EVEX_W_0F5C_P_3,
1977   EVEX_W_0F5D_P_1,
1978   EVEX_W_0F5D_P_3,
1979   EVEX_W_0F5E_P_1,
1980   EVEX_W_0F5E_P_3,
1981   EVEX_W_0F5F_P_1,
1982   EVEX_W_0F5F_P_3,
1983   EVEX_W_0F62_P_2,
1984   EVEX_W_0F66_P_2,
1985   EVEX_W_0F6A_P_2,
1986   EVEX_W_0F6B_P_2,
1987   EVEX_W_0F6C_P_2,
1988   EVEX_W_0F6D_P_2,
1989   EVEX_W_0F6F_P_1,
1990   EVEX_W_0F6F_P_2,
1991   EVEX_W_0F6F_P_3,
1992   EVEX_W_0F70_P_2,
1993   EVEX_W_0F72_R_2_P_2,
1994   EVEX_W_0F72_R_6_P_2,
1995   EVEX_W_0F73_R_2_P_2,
1996   EVEX_W_0F73_R_6_P_2,
1997   EVEX_W_0F76_P_2,
1998   EVEX_W_0F78_P_0,
1999   EVEX_W_0F78_P_2,
2000   EVEX_W_0F79_P_0,
2001   EVEX_W_0F79_P_2,
2002   EVEX_W_0F7A_P_1,
2003   EVEX_W_0F7A_P_2,
2004   EVEX_W_0F7A_P_3,
2005   EVEX_W_0F7B_P_2,
2006   EVEX_W_0F7B_P_3,
2007   EVEX_W_0F7E_P_1,
2008   EVEX_W_0F7F_P_1,
2009   EVEX_W_0F7F_P_2,
2010   EVEX_W_0F7F_P_3,
2011   EVEX_W_0FC2_P_1,
2012   EVEX_W_0FC2_P_3,
2013   EVEX_W_0FD2_P_2,
2014   EVEX_W_0FD3_P_2,
2015   EVEX_W_0FD4_P_2,
2016   EVEX_W_0FD6_P_2,
2017   EVEX_W_0FE6_P_1,
2018   EVEX_W_0FE6_P_2,
2019   EVEX_W_0FE6_P_3,
2020   EVEX_W_0FE7_P_2,
2021   EVEX_W_0FF2_P_2,
2022   EVEX_W_0FF3_P_2,
2023   EVEX_W_0FF4_P_2,
2024   EVEX_W_0FFA_P_2,
2025   EVEX_W_0FFB_P_2,
2026   EVEX_W_0FFE_P_2,
2027   EVEX_W_0F380D_P_2,
2028   EVEX_W_0F3810_P_1,
2029   EVEX_W_0F3810_P_2,
2030   EVEX_W_0F3811_P_1,
2031   EVEX_W_0F3811_P_2,
2032   EVEX_W_0F3812_P_1,
2033   EVEX_W_0F3812_P_2,
2034   EVEX_W_0F3813_P_1,
2035   EVEX_W_0F3813_P_2,
2036   EVEX_W_0F3814_P_1,
2037   EVEX_W_0F3815_P_1,
2038   EVEX_W_0F3819_P_2,
2039   EVEX_W_0F381A_P_2,
2040   EVEX_W_0F381B_P_2,
2041   EVEX_W_0F381E_P_2,
2042   EVEX_W_0F381F_P_2,
2043   EVEX_W_0F3820_P_1,
2044   EVEX_W_0F3821_P_1,
2045   EVEX_W_0F3822_P_1,
2046   EVEX_W_0F3823_P_1,
2047   EVEX_W_0F3824_P_1,
2048   EVEX_W_0F3825_P_1,
2049   EVEX_W_0F3825_P_2,
2050   EVEX_W_0F3826_P_1,
2051   EVEX_W_0F3826_P_2,
2052   EVEX_W_0F3828_P_1,
2053   EVEX_W_0F3828_P_2,
2054   EVEX_W_0F3829_P_1,
2055   EVEX_W_0F3829_P_2,
2056   EVEX_W_0F382A_P_1,
2057   EVEX_W_0F382A_P_2,
2058   EVEX_W_0F382B_P_2,
2059   EVEX_W_0F3830_P_1,
2060   EVEX_W_0F3831_P_1,
2061   EVEX_W_0F3832_P_1,
2062   EVEX_W_0F3833_P_1,
2063   EVEX_W_0F3834_P_1,
2064   EVEX_W_0F3835_P_1,
2065   EVEX_W_0F3835_P_2,
2066   EVEX_W_0F3837_P_2,
2067   EVEX_W_0F3838_P_1,
2068   EVEX_W_0F3839_P_1,
2069   EVEX_W_0F383A_P_1,
2070   EVEX_W_0F3840_P_2,
2071   EVEX_W_0F3852_P_1,
2072   EVEX_W_0F3854_P_2,
2073   EVEX_W_0F3855_P_2,
2074   EVEX_W_0F3859_P_2,
2075   EVEX_W_0F385A_P_2,
2076   EVEX_W_0F385B_P_2,
2077   EVEX_W_0F3862_P_2,
2078   EVEX_W_0F3863_P_2,
2079   EVEX_W_0F3866_P_2,
2080   EVEX_W_0F3868_P_3,
2081   EVEX_W_0F3870_P_2,
2082   EVEX_W_0F3871_P_2,
2083   EVEX_W_0F3872_P_1,
2084   EVEX_W_0F3872_P_2,
2085   EVEX_W_0F3872_P_3,
2086   EVEX_W_0F3873_P_2,
2087   EVEX_W_0F3875_P_2,
2088   EVEX_W_0F387A_P_2,
2089   EVEX_W_0F387B_P_2,
2090   EVEX_W_0F387D_P_2,
2091   EVEX_W_0F3883_P_2,
2092   EVEX_W_0F388D_P_2,
2093   EVEX_W_0F3891_P_2,
2094   EVEX_W_0F3893_P_2,
2095   EVEX_W_0F38A1_P_2,
2096   EVEX_W_0F38A3_P_2,
2097   EVEX_W_0F38C7_R_1_P_2,
2098   EVEX_W_0F38C7_R_2_P_2,
2099   EVEX_W_0F38C7_R_5_P_2,
2100   EVEX_W_0F38C7_R_6_P_2,
2101
2102   EVEX_W_0F3A00_P_2,
2103   EVEX_W_0F3A01_P_2,
2104   EVEX_W_0F3A05_P_2,
2105   EVEX_W_0F3A08_P_2,
2106   EVEX_W_0F3A09_P_2,
2107   EVEX_W_0F3A0A_P_2,
2108   EVEX_W_0F3A0B_P_2,
2109   EVEX_W_0F3A18_P_2,
2110   EVEX_W_0F3A19_P_2,
2111   EVEX_W_0F3A1A_P_2,
2112   EVEX_W_0F3A1B_P_2,
2113   EVEX_W_0F3A1D_P_2,
2114   EVEX_W_0F3A21_P_2,
2115   EVEX_W_0F3A23_P_2,
2116   EVEX_W_0F3A38_P_2,
2117   EVEX_W_0F3A39_P_2,
2118   EVEX_W_0F3A3A_P_2,
2119   EVEX_W_0F3A3B_P_2,
2120   EVEX_W_0F3A3E_P_2,
2121   EVEX_W_0F3A3F_P_2,
2122   EVEX_W_0F3A42_P_2,
2123   EVEX_W_0F3A43_P_2,
2124   EVEX_W_0F3A50_P_2,
2125   EVEX_W_0F3A51_P_2,
2126   EVEX_W_0F3A56_P_2,
2127   EVEX_W_0F3A57_P_2,
2128   EVEX_W_0F3A66_P_2,
2129   EVEX_W_0F3A67_P_2,
2130   EVEX_W_0F3A70_P_2,
2131   EVEX_W_0F3A71_P_2,
2132   EVEX_W_0F3A72_P_2,
2133   EVEX_W_0F3A73_P_2,
2134 };
2135
2136 typedef void (*op_rtn) (int bytemode, int sizeflag);
2137
2138 struct dis386 {
2139   const char *name;
2140   struct
2141     {
2142       op_rtn rtn;
2143       int bytemode;
2144     } op[MAX_OPERANDS];
2145   unsigned int prefix_requirement;
2146 };
2147
2148 /* Upper case letters in the instruction names here are macros.
2149    'A' => print 'b' if no register operands or suffix_always is true
2150    'B' => print 'b' if suffix_always is true
2151    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2152           size prefix
2153    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2154           suffix_always is true
2155    'E' => print 'e' if 32-bit form of jcxz
2156    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2157    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2158    'H' => print ",pt" or ",pn" branch hint
2159    'I' unused.
2160    'J' unused.
2161    'K' => print 'd' or 'q' if rex prefix is present.
2162    'L' => print 'l' if suffix_always is true
2163    'M' => print 'r' if intel_mnemonic is false.
2164    'N' => print 'n' if instruction has no wait "prefix"
2165    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2166    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2167           or suffix_always is true.  print 'q' if rex prefix is present.
2168    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2169           is true
2170    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2171    'S' => print 'w', 'l' or 'q' if suffix_always is true
2172    'T' => print 'q' in 64bit mode if instruction has no operand size
2173           prefix and behave as 'P' otherwise
2174    'U' => print 'q' in 64bit mode if instruction has no operand size
2175           prefix and behave as 'Q' otherwise
2176    'V' => print 'q' in 64bit mode if instruction has no operand size
2177           prefix and behave as 'S' otherwise
2178    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2179    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2180    'Y' unused.
2181    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2182    '!' => change condition from true to false or from false to true.
2183    '%' => add 1 upper case letter to the macro.
2184    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2185           prefix or suffix_always is true (lcall/ljmp).
2186    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2187           on operand size prefix.
2188    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2189           has no operand size prefix for AMD64 ISA, behave as 'P'
2190           otherwise
2191
2192    2 upper case letter macros:
2193    "XY" => print 'x' or 'y' if suffix_always is true or no register
2194            operands and no broadcast.
2195    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2196            register operands and no broadcast.
2197    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2198    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2199            operand or no operand at all in 64bit mode, or if suffix_always
2200            is true.
2201    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2202    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2203    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2204    "LW" => print 'd', 'q' depending on the VEX.W bit
2205    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2206            an operand size prefix, or suffix_always is true.  print
2207            'q' if rex prefix is present.
2208
2209    Many of the above letters print nothing in Intel mode.  See "putop"
2210    for the details.
2211
2212    Braces '{' and '}', and vertical bars '|', indicate alternative
2213    mnemonic strings for AT&T and Intel.  */
2214
2215 static const struct dis386 dis386[] = {
2216   /* 00 */
2217   { "addB",             { Ebh1, Gb }, 0 },
2218   { "addS",             { Evh1, Gv }, 0 },
2219   { "addB",             { Gb, EbS }, 0 },
2220   { "addS",             { Gv, EvS }, 0 },
2221   { "addB",             { AL, Ib }, 0 },
2222   { "addS",             { eAX, Iv }, 0 },
2223   { X86_64_TABLE (X86_64_06) },
2224   { X86_64_TABLE (X86_64_07) },
2225   /* 08 */
2226   { "orB",              { Ebh1, Gb }, 0 },
2227   { "orS",              { Evh1, Gv }, 0 },
2228   { "orB",              { Gb, EbS }, 0 },
2229   { "orS",              { Gv, EvS }, 0 },
2230   { "orB",              { AL, Ib }, 0 },
2231   { "orS",              { eAX, Iv }, 0 },
2232   { X86_64_TABLE (X86_64_0E) },
2233   { Bad_Opcode },       /* 0x0f extended opcode escape */
2234   /* 10 */
2235   { "adcB",             { Ebh1, Gb }, 0 },
2236   { "adcS",             { Evh1, Gv }, 0 },
2237   { "adcB",             { Gb, EbS }, 0 },
2238   { "adcS",             { Gv, EvS }, 0 },
2239   { "adcB",             { AL, Ib }, 0 },
2240   { "adcS",             { eAX, Iv }, 0 },
2241   { X86_64_TABLE (X86_64_16) },
2242   { X86_64_TABLE (X86_64_17) },
2243   /* 18 */
2244   { "sbbB",             { Ebh1, Gb }, 0 },
2245   { "sbbS",             { Evh1, Gv }, 0 },
2246   { "sbbB",             { Gb, EbS }, 0 },
2247   { "sbbS",             { Gv, EvS }, 0 },
2248   { "sbbB",             { AL, Ib }, 0 },
2249   { "sbbS",             { eAX, Iv }, 0 },
2250   { X86_64_TABLE (X86_64_1E) },
2251   { X86_64_TABLE (X86_64_1F) },
2252   /* 20 */
2253   { "andB",             { Ebh1, Gb }, 0 },
2254   { "andS",             { Evh1, Gv }, 0 },
2255   { "andB",             { Gb, EbS }, 0 },
2256   { "andS",             { Gv, EvS }, 0 },
2257   { "andB",             { AL, Ib }, 0 },
2258   { "andS",             { eAX, Iv }, 0 },
2259   { Bad_Opcode },       /* SEG ES prefix */
2260   { X86_64_TABLE (X86_64_27) },
2261   /* 28 */
2262   { "subB",             { Ebh1, Gb }, 0 },
2263   { "subS",             { Evh1, Gv }, 0 },
2264   { "subB",             { Gb, EbS }, 0 },
2265   { "subS",             { Gv, EvS }, 0 },
2266   { "subB",             { AL, Ib }, 0 },
2267   { "subS",             { eAX, Iv }, 0 },
2268   { Bad_Opcode },       /* SEG CS prefix */
2269   { X86_64_TABLE (X86_64_2F) },
2270   /* 30 */
2271   { "xorB",             { Ebh1, Gb }, 0 },
2272   { "xorS",             { Evh1, Gv }, 0 },
2273   { "xorB",             { Gb, EbS }, 0 },
2274   { "xorS",             { Gv, EvS }, 0 },
2275   { "xorB",             { AL, Ib }, 0 },
2276   { "xorS",             { eAX, Iv }, 0 },
2277   { Bad_Opcode },       /* SEG SS prefix */
2278   { X86_64_TABLE (X86_64_37) },
2279   /* 38 */
2280   { "cmpB",             { Eb, Gb }, 0 },
2281   { "cmpS",             { Ev, Gv }, 0 },
2282   { "cmpB",             { Gb, EbS }, 0 },
2283   { "cmpS",             { Gv, EvS }, 0 },
2284   { "cmpB",             { AL, Ib }, 0 },
2285   { "cmpS",             { eAX, Iv }, 0 },
2286   { Bad_Opcode },       /* SEG DS prefix */
2287   { X86_64_TABLE (X86_64_3F) },
2288   /* 40 */
2289   { "inc{S|}",          { RMeAX }, 0 },
2290   { "inc{S|}",          { RMeCX }, 0 },
2291   { "inc{S|}",          { RMeDX }, 0 },
2292   { "inc{S|}",          { RMeBX }, 0 },
2293   { "inc{S|}",          { RMeSP }, 0 },
2294   { "inc{S|}",          { RMeBP }, 0 },
2295   { "inc{S|}",          { RMeSI }, 0 },
2296   { "inc{S|}",          { RMeDI }, 0 },
2297   /* 48 */
2298   { "dec{S|}",          { RMeAX }, 0 },
2299   { "dec{S|}",          { RMeCX }, 0 },
2300   { "dec{S|}",          { RMeDX }, 0 },
2301   { "dec{S|}",          { RMeBX }, 0 },
2302   { "dec{S|}",          { RMeSP }, 0 },
2303   { "dec{S|}",          { RMeBP }, 0 },
2304   { "dec{S|}",          { RMeSI }, 0 },
2305   { "dec{S|}",          { RMeDI }, 0 },
2306   /* 50 */
2307   { "pushV",            { RMrAX }, 0 },
2308   { "pushV",            { RMrCX }, 0 },
2309   { "pushV",            { RMrDX }, 0 },
2310   { "pushV",            { RMrBX }, 0 },
2311   { "pushV",            { RMrSP }, 0 },
2312   { "pushV",            { RMrBP }, 0 },
2313   { "pushV",            { RMrSI }, 0 },
2314   { "pushV",            { RMrDI }, 0 },
2315   /* 58 */
2316   { "popV",             { RMrAX }, 0 },
2317   { "popV",             { RMrCX }, 0 },
2318   { "popV",             { RMrDX }, 0 },
2319   { "popV",             { RMrBX }, 0 },
2320   { "popV",             { RMrSP }, 0 },
2321   { "popV",             { RMrBP }, 0 },
2322   { "popV",             { RMrSI }, 0 },
2323   { "popV",             { RMrDI }, 0 },
2324   /* 60 */
2325   { X86_64_TABLE (X86_64_60) },
2326   { X86_64_TABLE (X86_64_61) },
2327   { X86_64_TABLE (X86_64_62) },
2328   { X86_64_TABLE (X86_64_63) },
2329   { Bad_Opcode },       /* seg fs */
2330   { Bad_Opcode },       /* seg gs */
2331   { Bad_Opcode },       /* op size prefix */
2332   { Bad_Opcode },       /* adr size prefix */
2333   /* 68 */
2334   { "pushT",            { sIv }, 0 },
2335   { "imulS",            { Gv, Ev, Iv }, 0 },
2336   { "pushT",            { sIbT }, 0 },
2337   { "imulS",            { Gv, Ev, sIb }, 0 },
2338   { "ins{b|}",          { Ybr, indirDX }, 0 },
2339   { X86_64_TABLE (X86_64_6D) },
2340   { "outs{b|}",         { indirDXr, Xb }, 0 },
2341   { X86_64_TABLE (X86_64_6F) },
2342   /* 70 */
2343   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2344   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2345   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2346   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2347   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2348   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2349   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2350   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2351   /* 78 */
2352   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2353   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2354   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2355   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2356   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2357   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2358   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2359   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2360   /* 80 */
2361   { REG_TABLE (REG_80) },
2362   { REG_TABLE (REG_81) },
2363   { X86_64_TABLE (X86_64_82) },
2364   { REG_TABLE (REG_83) },
2365   { "testB",            { Eb, Gb }, 0 },
2366   { "testS",            { Ev, Gv }, 0 },
2367   { "xchgB",            { Ebh2, Gb }, 0 },
2368   { "xchgS",            { Evh2, Gv }, 0 },
2369   /* 88 */
2370   { "movB",             { Ebh3, Gb }, 0 },
2371   { "movS",             { Evh3, Gv }, 0 },
2372   { "movB",             { Gb, EbS }, 0 },
2373   { "movS",             { Gv, EvS }, 0 },
2374   { "movD",             { Sv, Sw }, 0 },
2375   { MOD_TABLE (MOD_8D) },
2376   { "movD",             { Sw, Sv }, 0 },
2377   { REG_TABLE (REG_8F) },
2378   /* 90 */
2379   { PREFIX_TABLE (PREFIX_90) },
2380   { "xchgS",            { RMeCX, eAX }, 0 },
2381   { "xchgS",            { RMeDX, eAX }, 0 },
2382   { "xchgS",            { RMeBX, eAX }, 0 },
2383   { "xchgS",            { RMeSP, eAX }, 0 },
2384   { "xchgS",            { RMeBP, eAX }, 0 },
2385   { "xchgS",            { RMeSI, eAX }, 0 },
2386   { "xchgS",            { RMeDI, eAX }, 0 },
2387   /* 98 */
2388   { "cW{t|}R",          { XX }, 0 },
2389   { "cR{t|}O",          { XX }, 0 },
2390   { X86_64_TABLE (X86_64_9A) },
2391   { Bad_Opcode },       /* fwait */
2392   { "pushfT",           { XX }, 0 },
2393   { "popfT",            { XX }, 0 },
2394   { "sahf",             { XX }, 0 },
2395   { "lahf",             { XX }, 0 },
2396   /* a0 */
2397   { "mov%LB",           { AL, Ob }, 0 },
2398   { "mov%LS",           { eAX, Ov }, 0 },
2399   { "mov%LB",           { Ob, AL }, 0 },
2400   { "mov%LS",           { Ov, eAX }, 0 },
2401   { "movs{b|}",         { Ybr, Xb }, 0 },
2402   { "movs{R|}",         { Yvr, Xv }, 0 },
2403   { "cmps{b|}",         { Xb, Yb }, 0 },
2404   { "cmps{R|}",         { Xv, Yv }, 0 },
2405   /* a8 */
2406   { "testB",            { AL, Ib }, 0 },
2407   { "testS",            { eAX, Iv }, 0 },
2408   { "stosB",            { Ybr, AL }, 0 },
2409   { "stosS",            { Yvr, eAX }, 0 },
2410   { "lodsB",            { ALr, Xb }, 0 },
2411   { "lodsS",            { eAXr, Xv }, 0 },
2412   { "scasB",            { AL, Yb }, 0 },
2413   { "scasS",            { eAX, Yv }, 0 },
2414   /* b0 */
2415   { "movB",             { RMAL, Ib }, 0 },
2416   { "movB",             { RMCL, Ib }, 0 },
2417   { "movB",             { RMDL, Ib }, 0 },
2418   { "movB",             { RMBL, Ib }, 0 },
2419   { "movB",             { RMAH, Ib }, 0 },
2420   { "movB",             { RMCH, Ib }, 0 },
2421   { "movB",             { RMDH, Ib }, 0 },
2422   { "movB",             { RMBH, Ib }, 0 },
2423   /* b8 */
2424   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2425   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2426   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2427   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2428   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2429   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2430   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2431   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2432   /* c0 */
2433   { REG_TABLE (REG_C0) },
2434   { REG_TABLE (REG_C1) },
2435   { X86_64_TABLE (X86_64_C2) },
2436   { X86_64_TABLE (X86_64_C3) },
2437   { X86_64_TABLE (X86_64_C4) },
2438   { X86_64_TABLE (X86_64_C5) },
2439   { REG_TABLE (REG_C6) },
2440   { REG_TABLE (REG_C7) },
2441   /* c8 */
2442   { "enterT",           { Iw, Ib }, 0 },
2443   { "leaveT",           { XX }, 0 },
2444   { "{l|}ret{|f}P",     { Iw }, 0 },
2445   { "{l|}ret{|f}P",     { XX }, 0 },
2446   { "int3",             { XX }, 0 },
2447   { "int",              { Ib }, 0 },
2448   { X86_64_TABLE (X86_64_CE) },
2449   { "iret%LP",          { XX }, 0 },
2450   /* d0 */
2451   { REG_TABLE (REG_D0) },
2452   { REG_TABLE (REG_D1) },
2453   { REG_TABLE (REG_D2) },
2454   { REG_TABLE (REG_D3) },
2455   { X86_64_TABLE (X86_64_D4) },
2456   { X86_64_TABLE (X86_64_D5) },
2457   { Bad_Opcode },
2458   { "xlat",             { DSBX }, 0 },
2459   /* d8 */
2460   { FLOAT },
2461   { FLOAT },
2462   { FLOAT },
2463   { FLOAT },
2464   { FLOAT },
2465   { FLOAT },
2466   { FLOAT },
2467   { FLOAT },
2468   /* e0 */
2469   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2470   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2471   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2472   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2473   { "inB",              { AL, Ib }, 0 },
2474   { "inG",              { zAX, Ib }, 0 },
2475   { "outB",             { Ib, AL }, 0 },
2476   { "outG",             { Ib, zAX }, 0 },
2477   /* e8 */
2478   { X86_64_TABLE (X86_64_E8) },
2479   { X86_64_TABLE (X86_64_E9) },
2480   { X86_64_TABLE (X86_64_EA) },
2481   { "jmp",              { Jb, BND }, 0 },
2482   { "inB",              { AL, indirDX }, 0 },
2483   { "inG",              { zAX, indirDX }, 0 },
2484   { "outB",             { indirDX, AL }, 0 },
2485   { "outG",             { indirDX, zAX }, 0 },
2486   /* f0 */
2487   { Bad_Opcode },       /* lock prefix */
2488   { "icebp",            { XX }, 0 },
2489   { Bad_Opcode },       /* repne */
2490   { Bad_Opcode },       /* repz */
2491   { "hlt",              { XX }, 0 },
2492   { "cmc",              { XX }, 0 },
2493   { REG_TABLE (REG_F6) },
2494   { REG_TABLE (REG_F7) },
2495   /* f8 */
2496   { "clc",              { XX }, 0 },
2497   { "stc",              { XX }, 0 },
2498   { "cli",              { XX }, 0 },
2499   { "sti",              { XX }, 0 },
2500   { "cld",              { XX }, 0 },
2501   { "std",              { XX }, 0 },
2502   { REG_TABLE (REG_FE) },
2503   { REG_TABLE (REG_FF) },
2504 };
2505
2506 static const struct dis386 dis386_twobyte[] = {
2507   /* 00 */
2508   { REG_TABLE (REG_0F00 ) },
2509   { REG_TABLE (REG_0F01 ) },
2510   { "larS",             { Gv, Ew }, 0 },
2511   { "lslS",             { Gv, Ew }, 0 },
2512   { Bad_Opcode },
2513   { "syscall",          { XX }, 0 },
2514   { "clts",             { XX }, 0 },
2515   { "sysret%LQ",                { XX }, 0 },
2516   /* 08 */
2517   { "invd",             { XX }, 0 },
2518   { PREFIX_TABLE (PREFIX_0F09) },
2519   { Bad_Opcode },
2520   { "ud2",              { XX }, 0 },
2521   { Bad_Opcode },
2522   { REG_TABLE (REG_0F0D) },
2523   { "femms",            { XX }, 0 },
2524   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2525   /* 10 */
2526   { PREFIX_TABLE (PREFIX_0F10) },
2527   { PREFIX_TABLE (PREFIX_0F11) },
2528   { PREFIX_TABLE (PREFIX_0F12) },
2529   { MOD_TABLE (MOD_0F13) },
2530   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2531   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2532   { PREFIX_TABLE (PREFIX_0F16) },
2533   { MOD_TABLE (MOD_0F17) },
2534   /* 18 */
2535   { REG_TABLE (REG_0F18) },
2536   { "nopQ",             { Ev }, 0 },
2537   { PREFIX_TABLE (PREFIX_0F1A) },
2538   { PREFIX_TABLE (PREFIX_0F1B) },
2539   { PREFIX_TABLE (PREFIX_0F1C) },
2540   { "nopQ",             { Ev }, 0 },
2541   { PREFIX_TABLE (PREFIX_0F1E) },
2542   { "nopQ",             { Ev }, 0 },
2543   /* 20 */
2544   { "movZ",             { Rm, Cm }, 0 },
2545   { "movZ",             { Rm, Dm }, 0 },
2546   { "movZ",             { Cm, Rm }, 0 },
2547   { "movZ",             { Dm, Rm }, 0 },
2548   { MOD_TABLE (MOD_0F24) },
2549   { Bad_Opcode },
2550   { MOD_TABLE (MOD_0F26) },
2551   { Bad_Opcode },
2552   /* 28 */
2553   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2554   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2555   { PREFIX_TABLE (PREFIX_0F2A) },
2556   { PREFIX_TABLE (PREFIX_0F2B) },
2557   { PREFIX_TABLE (PREFIX_0F2C) },
2558   { PREFIX_TABLE (PREFIX_0F2D) },
2559   { PREFIX_TABLE (PREFIX_0F2E) },
2560   { PREFIX_TABLE (PREFIX_0F2F) },
2561   /* 30 */
2562   { "wrmsr",            { XX }, 0 },
2563   { "rdtsc",            { XX }, 0 },
2564   { "rdmsr",            { XX }, 0 },
2565   { "rdpmc",            { XX }, 0 },
2566   { "sysenter",         { SEP }, 0 },
2567   { "sysexit",          { SEP }, 0 },
2568   { Bad_Opcode },
2569   { "getsec",           { XX }, 0 },
2570   /* 38 */
2571   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2572   { Bad_Opcode },
2573   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2574   { Bad_Opcode },
2575   { Bad_Opcode },
2576   { Bad_Opcode },
2577   { Bad_Opcode },
2578   { Bad_Opcode },
2579   /* 40 */
2580   { "cmovoS",           { Gv, Ev }, 0 },
2581   { "cmovnoS",          { Gv, Ev }, 0 },
2582   { "cmovbS",           { Gv, Ev }, 0 },
2583   { "cmovaeS",          { Gv, Ev }, 0 },
2584   { "cmoveS",           { Gv, Ev }, 0 },
2585   { "cmovneS",          { Gv, Ev }, 0 },
2586   { "cmovbeS",          { Gv, Ev }, 0 },
2587   { "cmovaS",           { Gv, Ev }, 0 },
2588   /* 48 */
2589   { "cmovsS",           { Gv, Ev }, 0 },
2590   { "cmovnsS",          { Gv, Ev }, 0 },
2591   { "cmovpS",           { Gv, Ev }, 0 },
2592   { "cmovnpS",          { Gv, Ev }, 0 },
2593   { "cmovlS",           { Gv, Ev }, 0 },
2594   { "cmovgeS",          { Gv, Ev }, 0 },
2595   { "cmovleS",          { Gv, Ev }, 0 },
2596   { "cmovgS",           { Gv, Ev }, 0 },
2597   /* 50 */
2598   { MOD_TABLE (MOD_0F50) },
2599   { PREFIX_TABLE (PREFIX_0F51) },
2600   { PREFIX_TABLE (PREFIX_0F52) },
2601   { PREFIX_TABLE (PREFIX_0F53) },
2602   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2603   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2604   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2605   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2606   /* 58 */
2607   { PREFIX_TABLE (PREFIX_0F58) },
2608   { PREFIX_TABLE (PREFIX_0F59) },
2609   { PREFIX_TABLE (PREFIX_0F5A) },
2610   { PREFIX_TABLE (PREFIX_0F5B) },
2611   { PREFIX_TABLE (PREFIX_0F5C) },
2612   { PREFIX_TABLE (PREFIX_0F5D) },
2613   { PREFIX_TABLE (PREFIX_0F5E) },
2614   { PREFIX_TABLE (PREFIX_0F5F) },
2615   /* 60 */
2616   { PREFIX_TABLE (PREFIX_0F60) },
2617   { PREFIX_TABLE (PREFIX_0F61) },
2618   { PREFIX_TABLE (PREFIX_0F62) },
2619   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2620   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2621   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2622   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2623   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2624   /* 68 */
2625   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2626   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2627   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2628   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2629   { PREFIX_TABLE (PREFIX_0F6C) },
2630   { PREFIX_TABLE (PREFIX_0F6D) },
2631   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2632   { PREFIX_TABLE (PREFIX_0F6F) },
2633   /* 70 */
2634   { PREFIX_TABLE (PREFIX_0F70) },
2635   { REG_TABLE (REG_0F71) },
2636   { REG_TABLE (REG_0F72) },
2637   { REG_TABLE (REG_0F73) },
2638   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2639   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2640   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2641   { "emms",             { XX }, PREFIX_OPCODE },
2642   /* 78 */
2643   { PREFIX_TABLE (PREFIX_0F78) },
2644   { PREFIX_TABLE (PREFIX_0F79) },
2645   { Bad_Opcode },
2646   { Bad_Opcode },
2647   { PREFIX_TABLE (PREFIX_0F7C) },
2648   { PREFIX_TABLE (PREFIX_0F7D) },
2649   { PREFIX_TABLE (PREFIX_0F7E) },
2650   { PREFIX_TABLE (PREFIX_0F7F) },
2651   /* 80 */
2652   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2653   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2654   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2655   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2656   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2657   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2658   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2659   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2660   /* 88 */
2661   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2662   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2663   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2664   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2665   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2666   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2667   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2668   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2669   /* 90 */
2670   { "seto",             { Eb }, 0 },
2671   { "setno",            { Eb }, 0 },
2672   { "setb",             { Eb }, 0 },
2673   { "setae",            { Eb }, 0 },
2674   { "sete",             { Eb }, 0 },
2675   { "setne",            { Eb }, 0 },
2676   { "setbe",            { Eb }, 0 },
2677   { "seta",             { Eb }, 0 },
2678   /* 98 */
2679   { "sets",             { Eb }, 0 },
2680   { "setns",            { Eb }, 0 },
2681   { "setp",             { Eb }, 0 },
2682   { "setnp",            { Eb }, 0 },
2683   { "setl",             { Eb }, 0 },
2684   { "setge",            { Eb }, 0 },
2685   { "setle",            { Eb }, 0 },
2686   { "setg",             { Eb }, 0 },
2687   /* a0 */
2688   { "pushT",            { fs }, 0 },
2689   { "popT",             { fs }, 0 },
2690   { "cpuid",            { XX }, 0 },
2691   { "btS",              { Ev, Gv }, 0 },
2692   { "shldS",            { Ev, Gv, Ib }, 0 },
2693   { "shldS",            { Ev, Gv, CL }, 0 },
2694   { REG_TABLE (REG_0FA6) },
2695   { REG_TABLE (REG_0FA7) },
2696   /* a8 */
2697   { "pushT",            { gs }, 0 },
2698   { "popT",             { gs }, 0 },
2699   { "rsm",              { XX }, 0 },
2700   { "btsS",             { Evh1, Gv }, 0 },
2701   { "shrdS",            { Ev, Gv, Ib }, 0 },
2702   { "shrdS",            { Ev, Gv, CL }, 0 },
2703   { REG_TABLE (REG_0FAE) },
2704   { "imulS",            { Gv, Ev }, 0 },
2705   /* b0 */
2706   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2707   { "cmpxchgS",         { Evh1, Gv }, 0 },
2708   { MOD_TABLE (MOD_0FB2) },
2709   { "btrS",             { Evh1, Gv }, 0 },
2710   { MOD_TABLE (MOD_0FB4) },
2711   { MOD_TABLE (MOD_0FB5) },
2712   { "movz{bR|x}",       { Gv, Eb }, 0 },
2713   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2714   /* b8 */
2715   { PREFIX_TABLE (PREFIX_0FB8) },
2716   { "ud1S",             { Gv, Ev }, 0 },
2717   { REG_TABLE (REG_0FBA) },
2718   { "btcS",             { Evh1, Gv }, 0 },
2719   { PREFIX_TABLE (PREFIX_0FBC) },
2720   { PREFIX_TABLE (PREFIX_0FBD) },
2721   { "movs{bR|x}",       { Gv, Eb }, 0 },
2722   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2723   /* c0 */
2724   { "xaddB",            { Ebh1, Gb }, 0 },
2725   { "xaddS",            { Evh1, Gv }, 0 },
2726   { PREFIX_TABLE (PREFIX_0FC2) },
2727   { MOD_TABLE (MOD_0FC3) },
2728   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2729   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2730   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2731   { REG_TABLE (REG_0FC7) },
2732   /* c8 */
2733   { "bswap",            { RMeAX }, 0 },
2734   { "bswap",            { RMeCX }, 0 },
2735   { "bswap",            { RMeDX }, 0 },
2736   { "bswap",            { RMeBX }, 0 },
2737   { "bswap",            { RMeSP }, 0 },
2738   { "bswap",            { RMeBP }, 0 },
2739   { "bswap",            { RMeSI }, 0 },
2740   { "bswap",            { RMeDI }, 0 },
2741   /* d0 */
2742   { PREFIX_TABLE (PREFIX_0FD0) },
2743   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2744   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2745   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2746   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2747   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2748   { PREFIX_TABLE (PREFIX_0FD6) },
2749   { MOD_TABLE (MOD_0FD7) },
2750   /* d8 */
2751   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2752   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2753   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2754   { "pand",             { MX, EM }, PREFIX_OPCODE },
2755   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2756   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2757   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2758   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2759   /* e0 */
2760   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2761   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2762   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2763   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2764   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2765   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2766   { PREFIX_TABLE (PREFIX_0FE6) },
2767   { PREFIX_TABLE (PREFIX_0FE7) },
2768   /* e8 */
2769   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2770   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2771   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2772   { "por",              { MX, EM }, PREFIX_OPCODE },
2773   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2774   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2775   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2776   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2777   /* f0 */
2778   { PREFIX_TABLE (PREFIX_0FF0) },
2779   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2780   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2781   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2782   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2783   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2784   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2785   { PREFIX_TABLE (PREFIX_0FF7) },
2786   /* f8 */
2787   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2788   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2789   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2790   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2791   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2792   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2793   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2794   { "ud0S",             { Gv, Ev }, 0 },
2795 };
2796
2797 static const unsigned char onebyte_has_modrm[256] = {
2798   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2799   /*       -------------------------------        */
2800   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2801   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2802   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2803   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2804   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2805   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2806   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2807   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2808   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2809   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2810   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2811   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2812   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2813   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2814   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2815   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2816   /*       -------------------------------        */
2817   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2818 };
2819
2820 static const unsigned char twobyte_has_modrm[256] = {
2821   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2822   /*       -------------------------------        */
2823   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2824   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2825   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2826   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2827   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2828   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2829   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2830   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2831   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2832   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2833   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2834   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2835   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2836   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2837   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2838   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2839   /*       -------------------------------        */
2840   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2841 };
2842
2843 static char obuf[100];
2844 static char *obufp;
2845 static char *mnemonicendp;
2846 static char scratchbuf[100];
2847 static unsigned char *start_codep;
2848 static unsigned char *insn_codep;
2849 static unsigned char *codep;
2850 static unsigned char *end_codep;
2851 static int last_lock_prefix;
2852 static int last_repz_prefix;
2853 static int last_repnz_prefix;
2854 static int last_data_prefix;
2855 static int last_addr_prefix;
2856 static int last_rex_prefix;
2857 static int last_seg_prefix;
2858 static int fwait_prefix;
2859 /* The active segment register prefix.  */
2860 static int active_seg_prefix;
2861 #define MAX_CODE_LENGTH 15
2862 /* We can up to 14 prefixes since the maximum instruction length is
2863    15bytes.  */
2864 static int all_prefixes[MAX_CODE_LENGTH - 1];
2865 static disassemble_info *the_info;
2866 static struct
2867   {
2868     int mod;
2869     int reg;
2870     int rm;
2871   }
2872 modrm;
2873 static unsigned char need_modrm;
2874 static struct
2875   {
2876     int scale;
2877     int index;
2878     int base;
2879   }
2880 sib;
2881 static struct
2882   {
2883     int register_specifier;
2884     int length;
2885     int prefix;
2886     int w;
2887     int evex;
2888     int r;
2889     int v;
2890     int mask_register_specifier;
2891     int zeroing;
2892     int ll;
2893     int b;
2894   }
2895 vex;
2896 static unsigned char need_vex;
2897 static unsigned char need_vex_reg;
2898 static unsigned char vex_w_done;
2899
2900 struct op
2901   {
2902     const char *name;
2903     unsigned int len;
2904   };
2905
2906 /* If we are accessing mod/rm/reg without need_modrm set, then the
2907    values are stale.  Hitting this abort likely indicates that you
2908    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2909 #define MODRM_CHECK  if (!need_modrm) abort ()
2910
2911 static const char **names64;
2912 static const char **names32;
2913 static const char **names16;
2914 static const char **names8;
2915 static const char **names8rex;
2916 static const char **names_seg;
2917 static const char *index64;
2918 static const char *index32;
2919 static const char **index16;
2920 static const char **names_bnd;
2921
2922 static const char *intel_names64[] = {
2923   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2924   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2925 };
2926 static const char *intel_names32[] = {
2927   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2928   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2929 };
2930 static const char *intel_names16[] = {
2931   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2932   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2933 };
2934 static const char *intel_names8[] = {
2935   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2936 };
2937 static const char *intel_names8rex[] = {
2938   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2939   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2940 };
2941 static const char *intel_names_seg[] = {
2942   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2943 };
2944 static const char *intel_index64 = "riz";
2945 static const char *intel_index32 = "eiz";
2946 static const char *intel_index16[] = {
2947   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2948 };
2949
2950 static const char *att_names64[] = {
2951   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2952   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2953 };
2954 static const char *att_names32[] = {
2955   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2956   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2957 };
2958 static const char *att_names16[] = {
2959   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2960   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2961 };
2962 static const char *att_names8[] = {
2963   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2964 };
2965 static const char *att_names8rex[] = {
2966   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2967   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2968 };
2969 static const char *att_names_seg[] = {
2970   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2971 };
2972 static const char *att_index64 = "%riz";
2973 static const char *att_index32 = "%eiz";
2974 static const char *att_index16[] = {
2975   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2976 };
2977
2978 static const char **names_mm;
2979 static const char *intel_names_mm[] = {
2980   "mm0", "mm1", "mm2", "mm3",
2981   "mm4", "mm5", "mm6", "mm7"
2982 };
2983 static const char *att_names_mm[] = {
2984   "%mm0", "%mm1", "%mm2", "%mm3",
2985   "%mm4", "%mm5", "%mm6", "%mm7"
2986 };
2987
2988 static const char *intel_names_bnd[] = {
2989   "bnd0", "bnd1", "bnd2", "bnd3"
2990 };
2991
2992 static const char *att_names_bnd[] = {
2993   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2994 };
2995
2996 static const char **names_xmm;
2997 static const char *intel_names_xmm[] = {
2998   "xmm0", "xmm1", "xmm2", "xmm3",
2999   "xmm4", "xmm5", "xmm6", "xmm7",
3000   "xmm8", "xmm9", "xmm10", "xmm11",
3001   "xmm12", "xmm13", "xmm14", "xmm15",
3002   "xmm16", "xmm17", "xmm18", "xmm19",
3003   "xmm20", "xmm21", "xmm22", "xmm23",
3004   "xmm24", "xmm25", "xmm26", "xmm27",
3005   "xmm28", "xmm29", "xmm30", "xmm31"
3006 };
3007 static const char *att_names_xmm[] = {
3008   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3009   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3010   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3011   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3012   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3013   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3014   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3015   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3016 };
3017
3018 static const char **names_ymm;
3019 static const char *intel_names_ymm[] = {
3020   "ymm0", "ymm1", "ymm2", "ymm3",
3021   "ymm4", "ymm5", "ymm6", "ymm7",
3022   "ymm8", "ymm9", "ymm10", "ymm11",
3023   "ymm12", "ymm13", "ymm14", "ymm15",
3024   "ymm16", "ymm17", "ymm18", "ymm19",
3025   "ymm20", "ymm21", "ymm22", "ymm23",
3026   "ymm24", "ymm25", "ymm26", "ymm27",
3027   "ymm28", "ymm29", "ymm30", "ymm31"
3028 };
3029 static const char *att_names_ymm[] = {
3030   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3031   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3032   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3033   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3034   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3035   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3036   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3037   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3038 };
3039
3040 static const char **names_zmm;
3041 static const char *intel_names_zmm[] = {
3042   "zmm0", "zmm1", "zmm2", "zmm3",
3043   "zmm4", "zmm5", "zmm6", "zmm7",
3044   "zmm8", "zmm9", "zmm10", "zmm11",
3045   "zmm12", "zmm13", "zmm14", "zmm15",
3046   "zmm16", "zmm17", "zmm18", "zmm19",
3047   "zmm20", "zmm21", "zmm22", "zmm23",
3048   "zmm24", "zmm25", "zmm26", "zmm27",
3049   "zmm28", "zmm29", "zmm30", "zmm31"
3050 };
3051 static const char *att_names_zmm[] = {
3052   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3053   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3054   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3055   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3056   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3057   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3058   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3059   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3060 };
3061
3062 static const char **names_mask;
3063 static const char *intel_names_mask[] = {
3064   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3065 };
3066 static const char *att_names_mask[] = {
3067   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3068 };
3069
3070 static const char *names_rounding[] =
3071 {
3072   "{rn-sae}",
3073   "{rd-sae}",
3074   "{ru-sae}",
3075   "{rz-sae}"
3076 };
3077
3078 static const struct dis386 reg_table[][8] = {
3079   /* REG_80 */
3080   {
3081     { "addA",   { Ebh1, Ib }, 0 },
3082     { "orA",    { Ebh1, Ib }, 0 },
3083     { "adcA",   { Ebh1, Ib }, 0 },
3084     { "sbbA",   { Ebh1, Ib }, 0 },
3085     { "andA",   { Ebh1, Ib }, 0 },
3086     { "subA",   { Ebh1, Ib }, 0 },
3087     { "xorA",   { Ebh1, Ib }, 0 },
3088     { "cmpA",   { Eb, Ib }, 0 },
3089   },
3090   /* REG_81 */
3091   {
3092     { "addQ",   { Evh1, Iv }, 0 },
3093     { "orQ",    { Evh1, Iv }, 0 },
3094     { "adcQ",   { Evh1, Iv }, 0 },
3095     { "sbbQ",   { Evh1, Iv }, 0 },
3096     { "andQ",   { Evh1, Iv }, 0 },
3097     { "subQ",   { Evh1, Iv }, 0 },
3098     { "xorQ",   { Evh1, Iv }, 0 },
3099     { "cmpQ",   { Ev, Iv }, 0 },
3100   },
3101   /* REG_83 */
3102   {
3103     { "addQ",   { Evh1, sIb }, 0 },
3104     { "orQ",    { Evh1, sIb }, 0 },
3105     { "adcQ",   { Evh1, sIb }, 0 },
3106     { "sbbQ",   { Evh1, sIb }, 0 },
3107     { "andQ",   { Evh1, sIb }, 0 },
3108     { "subQ",   { Evh1, sIb }, 0 },
3109     { "xorQ",   { Evh1, sIb }, 0 },
3110     { "cmpQ",   { Ev, sIb }, 0 },
3111   },
3112   /* REG_8F */
3113   {
3114     { "popU",   { stackEv }, 0 },
3115     { XOP_8F_TABLE (XOP_09) },
3116     { Bad_Opcode },
3117     { Bad_Opcode },
3118     { Bad_Opcode },
3119     { XOP_8F_TABLE (XOP_09) },
3120   },
3121   /* REG_C0 */
3122   {
3123     { "rolA",   { Eb, Ib }, 0 },
3124     { "rorA",   { Eb, Ib }, 0 },
3125     { "rclA",   { Eb, Ib }, 0 },
3126     { "rcrA",   { Eb, Ib }, 0 },
3127     { "shlA",   { Eb, Ib }, 0 },
3128     { "shrA",   { Eb, Ib }, 0 },
3129     { "shlA",   { Eb, Ib }, 0 },
3130     { "sarA",   { Eb, Ib }, 0 },
3131   },
3132   /* REG_C1 */
3133   {
3134     { "rolQ",   { Ev, Ib }, 0 },
3135     { "rorQ",   { Ev, Ib }, 0 },
3136     { "rclQ",   { Ev, Ib }, 0 },
3137     { "rcrQ",   { Ev, Ib }, 0 },
3138     { "shlQ",   { Ev, Ib }, 0 },
3139     { "shrQ",   { Ev, Ib }, 0 },
3140     { "shlQ",   { Ev, Ib }, 0 },
3141     { "sarQ",   { Ev, Ib }, 0 },
3142   },
3143   /* REG_C6 */
3144   {
3145     { "movA",   { Ebh3, Ib }, 0 },
3146     { Bad_Opcode },
3147     { Bad_Opcode },
3148     { Bad_Opcode },
3149     { Bad_Opcode },
3150     { Bad_Opcode },
3151     { Bad_Opcode },
3152     { MOD_TABLE (MOD_C6_REG_7) },
3153   },
3154   /* REG_C7 */
3155   {
3156     { "movQ",   { Evh3, Iv }, 0 },
3157     { Bad_Opcode },
3158     { Bad_Opcode },
3159     { Bad_Opcode },
3160     { Bad_Opcode },
3161     { Bad_Opcode },
3162     { Bad_Opcode },
3163     { MOD_TABLE (MOD_C7_REG_7) },
3164   },
3165   /* REG_D0 */
3166   {
3167     { "rolA",   { Eb, I1 }, 0 },
3168     { "rorA",   { Eb, I1 }, 0 },
3169     { "rclA",   { Eb, I1 }, 0 },
3170     { "rcrA",   { Eb, I1 }, 0 },
3171     { "shlA",   { Eb, I1 }, 0 },
3172     { "shrA",   { Eb, I1 }, 0 },
3173     { "shlA",   { Eb, I1 }, 0 },
3174     { "sarA",   { Eb, I1 }, 0 },
3175   },
3176   /* REG_D1 */
3177   {
3178     { "rolQ",   { Ev, I1 }, 0 },
3179     { "rorQ",   { Ev, I1 }, 0 },
3180     { "rclQ",   { Ev, I1 }, 0 },
3181     { "rcrQ",   { Ev, I1 }, 0 },
3182     { "shlQ",   { Ev, I1 }, 0 },
3183     { "shrQ",   { Ev, I1 }, 0 },
3184     { "shlQ",   { Ev, I1 }, 0 },
3185     { "sarQ",   { Ev, I1 }, 0 },
3186   },
3187   /* REG_D2 */
3188   {
3189     { "rolA",   { Eb, CL }, 0 },
3190     { "rorA",   { Eb, CL }, 0 },
3191     { "rclA",   { Eb, CL }, 0 },
3192     { "rcrA",   { Eb, CL }, 0 },
3193     { "shlA",   { Eb, CL }, 0 },
3194     { "shrA",   { Eb, CL }, 0 },
3195     { "shlA",   { Eb, CL }, 0 },
3196     { "sarA",   { Eb, CL }, 0 },
3197   },
3198   /* REG_D3 */
3199   {
3200     { "rolQ",   { Ev, CL }, 0 },
3201     { "rorQ",   { Ev, CL }, 0 },
3202     { "rclQ",   { Ev, CL }, 0 },
3203     { "rcrQ",   { Ev, CL }, 0 },
3204     { "shlQ",   { Ev, CL }, 0 },
3205     { "shrQ",   { Ev, CL }, 0 },
3206     { "shlQ",   { Ev, CL }, 0 },
3207     { "sarQ",   { Ev, CL }, 0 },
3208   },
3209   /* REG_F6 */
3210   {
3211     { "testA",  { Eb, Ib }, 0 },
3212     { "testA",  { Eb, Ib }, 0 },
3213     { "notA",   { Ebh1 }, 0 },
3214     { "negA",   { Ebh1 }, 0 },
3215     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3216     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3217     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3218     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3219   },
3220   /* REG_F7 */
3221   {
3222     { "testQ",  { Ev, Iv }, 0 },
3223     { "testQ",  { Ev, Iv }, 0 },
3224     { "notQ",   { Evh1 }, 0 },
3225     { "negQ",   { Evh1 }, 0 },
3226     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3227     { "imulQ",  { Ev }, 0 },
3228     { "divQ",   { Ev }, 0 },
3229     { "idivQ",  { Ev }, 0 },
3230   },
3231   /* REG_FE */
3232   {
3233     { "incA",   { Ebh1 }, 0 },
3234     { "decA",   { Ebh1 }, 0 },
3235   },
3236   /* REG_FF */
3237   {
3238     { "incQ",   { Evh1 }, 0 },
3239     { "decQ",   { Evh1 }, 0 },
3240     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3241     { MOD_TABLE (MOD_FF_REG_3) },
3242     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3243     { MOD_TABLE (MOD_FF_REG_5) },
3244     { "pushU",  { stackEv }, 0 },
3245     { Bad_Opcode },
3246   },
3247   /* REG_0F00 */
3248   {
3249     { "sldtD",  { Sv }, 0 },
3250     { "strD",   { Sv }, 0 },
3251     { "lldt",   { Ew }, 0 },
3252     { "ltr",    { Ew }, 0 },
3253     { "verr",   { Ew }, 0 },
3254     { "verw",   { Ew }, 0 },
3255     { Bad_Opcode },
3256     { Bad_Opcode },
3257   },
3258   /* REG_0F01 */
3259   {
3260     { MOD_TABLE (MOD_0F01_REG_0) },
3261     { MOD_TABLE (MOD_0F01_REG_1) },
3262     { MOD_TABLE (MOD_0F01_REG_2) },
3263     { MOD_TABLE (MOD_0F01_REG_3) },
3264     { "smswD",  { Sv }, 0 },
3265     { MOD_TABLE (MOD_0F01_REG_5) },
3266     { "lmsw",   { Ew }, 0 },
3267     { MOD_TABLE (MOD_0F01_REG_7) },
3268   },
3269   /* REG_0F0D */
3270   {
3271     { "prefetch",       { Mb }, 0 },
3272     { "prefetchw",      { Mb }, 0 },
3273     { "prefetchwt1",    { Mb }, 0 },
3274     { "prefetch",       { Mb }, 0 },
3275     { "prefetch",       { Mb }, 0 },
3276     { "prefetch",       { Mb }, 0 },
3277     { "prefetch",       { Mb }, 0 },
3278     { "prefetch",       { Mb }, 0 },
3279   },
3280   /* REG_0F18 */
3281   {
3282     { MOD_TABLE (MOD_0F18_REG_0) },
3283     { MOD_TABLE (MOD_0F18_REG_1) },
3284     { MOD_TABLE (MOD_0F18_REG_2) },
3285     { MOD_TABLE (MOD_0F18_REG_3) },
3286     { MOD_TABLE (MOD_0F18_REG_4) },
3287     { MOD_TABLE (MOD_0F18_REG_5) },
3288     { MOD_TABLE (MOD_0F18_REG_6) },
3289     { MOD_TABLE (MOD_0F18_REG_7) },
3290   },
3291   /* REG_0F1C_P_0_MOD_0 */
3292   {
3293     { "cldemote",       { Mb }, 0 },
3294     { "nopQ",           { Ev }, 0 },
3295     { "nopQ",           { Ev }, 0 },
3296     { "nopQ",           { Ev }, 0 },
3297     { "nopQ",           { Ev }, 0 },
3298     { "nopQ",           { Ev }, 0 },
3299     { "nopQ",           { Ev }, 0 },
3300     { "nopQ",           { Ev }, 0 },
3301   },
3302   /* REG_0F1E_P_1_MOD_3 */
3303   {
3304     { "nopQ",           { Ev }, 0 },
3305     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3306     { "nopQ",           { Ev }, 0 },
3307     { "nopQ",           { Ev }, 0 },
3308     { "nopQ",           { Ev }, 0 },
3309     { "nopQ",           { Ev }, 0 },
3310     { "nopQ",           { Ev }, 0 },
3311     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3312   },
3313   /* REG_0F71 */
3314   {
3315     { Bad_Opcode },
3316     { Bad_Opcode },
3317     { MOD_TABLE (MOD_0F71_REG_2) },
3318     { Bad_Opcode },
3319     { MOD_TABLE (MOD_0F71_REG_4) },
3320     { Bad_Opcode },
3321     { MOD_TABLE (MOD_0F71_REG_6) },
3322   },
3323   /* REG_0F72 */
3324   {
3325     { Bad_Opcode },
3326     { Bad_Opcode },
3327     { MOD_TABLE (MOD_0F72_REG_2) },
3328     { Bad_Opcode },
3329     { MOD_TABLE (MOD_0F72_REG_4) },
3330     { Bad_Opcode },
3331     { MOD_TABLE (MOD_0F72_REG_6) },
3332   },
3333   /* REG_0F73 */
3334   {
3335     { Bad_Opcode },
3336     { Bad_Opcode },
3337     { MOD_TABLE (MOD_0F73_REG_2) },
3338     { MOD_TABLE (MOD_0F73_REG_3) },
3339     { Bad_Opcode },
3340     { Bad_Opcode },
3341     { MOD_TABLE (MOD_0F73_REG_6) },
3342     { MOD_TABLE (MOD_0F73_REG_7) },
3343   },
3344   /* REG_0FA6 */
3345   {
3346     { "montmul",        { { OP_0f07, 0 } }, 0 },
3347     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3348     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3349   },
3350   /* REG_0FA7 */
3351   {
3352     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3353     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3354     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3355     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3356     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3357     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3358   },
3359   /* REG_0FAE */
3360   {
3361     { MOD_TABLE (MOD_0FAE_REG_0) },
3362     { MOD_TABLE (MOD_0FAE_REG_1) },
3363     { MOD_TABLE (MOD_0FAE_REG_2) },
3364     { MOD_TABLE (MOD_0FAE_REG_3) },
3365     { MOD_TABLE (MOD_0FAE_REG_4) },
3366     { MOD_TABLE (MOD_0FAE_REG_5) },
3367     { MOD_TABLE (MOD_0FAE_REG_6) },
3368     { MOD_TABLE (MOD_0FAE_REG_7) },
3369   },
3370   /* REG_0FBA */
3371   {
3372     { Bad_Opcode },
3373     { Bad_Opcode },
3374     { Bad_Opcode },
3375     { Bad_Opcode },
3376     { "btQ",    { Ev, Ib }, 0 },
3377     { "btsQ",   { Evh1, Ib }, 0 },
3378     { "btrQ",   { Evh1, Ib }, 0 },
3379     { "btcQ",   { Evh1, Ib }, 0 },
3380   },
3381   /* REG_0FC7 */
3382   {
3383     { Bad_Opcode },
3384     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3385     { Bad_Opcode },
3386     { MOD_TABLE (MOD_0FC7_REG_3) },
3387     { MOD_TABLE (MOD_0FC7_REG_4) },
3388     { MOD_TABLE (MOD_0FC7_REG_5) },
3389     { MOD_TABLE (MOD_0FC7_REG_6) },
3390     { MOD_TABLE (MOD_0FC7_REG_7) },
3391   },
3392   /* REG_VEX_0F71 */
3393   {
3394     { Bad_Opcode },
3395     { Bad_Opcode },
3396     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3397     { Bad_Opcode },
3398     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3399     { Bad_Opcode },
3400     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3401   },
3402   /* REG_VEX_0F72 */
3403   {
3404     { Bad_Opcode },
3405     { Bad_Opcode },
3406     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3407     { Bad_Opcode },
3408     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3409     { Bad_Opcode },
3410     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3411   },
3412   /* REG_VEX_0F73 */
3413   {
3414     { Bad_Opcode },
3415     { Bad_Opcode },
3416     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3417     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3418     { Bad_Opcode },
3419     { Bad_Opcode },
3420     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3421     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3422   },
3423   /* REG_VEX_0FAE */
3424   {
3425     { Bad_Opcode },
3426     { Bad_Opcode },
3427     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3428     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3429   },
3430   /* REG_VEX_0F38F3 */
3431   {
3432     { Bad_Opcode },
3433     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3434     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3435     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3436   },
3437   /* REG_XOP_LWPCB */
3438   {
3439     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3440     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3441   },
3442   /* REG_XOP_LWP */
3443   {
3444     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3445     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3446   },
3447   /* REG_XOP_TBM_01 */
3448   {
3449     { Bad_Opcode },
3450     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3451     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3452     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3453     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3454     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3455     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3456     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3457   },
3458   /* REG_XOP_TBM_02 */
3459   {
3460     { Bad_Opcode },
3461     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3467   },
3468
3469 #include "i386-dis-evex-reg.h"
3470 };
3471
3472 static const struct dis386 prefix_table[][4] = {
3473   /* PREFIX_90 */
3474   {
3475     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3476     { "pause", { XX }, 0 },
3477     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3478     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3479   },
3480
3481   /* PREFIX_0F01_REG_3_RM_1 */
3482   {
3483     { "vmmcall",        { Skip_MODRM }, 0 },
3484     { "vmgexit",        { Skip_MODRM }, 0 },
3485     { Bad_Opcode },
3486     { "vmgexit",        { Skip_MODRM }, 0 },
3487   },
3488
3489   /* PREFIX_0F01_REG_5_MOD_0 */
3490   {
3491     { Bad_Opcode },
3492     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3493   },
3494
3495   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3496   {
3497     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3498     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3499     { Bad_Opcode },
3500     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3501   },
3502
3503   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3504   {
3505     { Bad_Opcode },
3506     { Bad_Opcode },
3507     { Bad_Opcode },
3508     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3509   },
3510
3511   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3512   {
3513     { Bad_Opcode },
3514     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3515   },
3516
3517   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3518   {
3519     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3520     { "mcommit",        { Skip_MODRM }, 0 },
3521   },
3522
3523   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3524   {
3525     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3526   },
3527
3528   /* PREFIX_0F09 */
3529   {
3530     { "wbinvd",   { XX }, 0 },
3531     { "wbnoinvd", { XX }, 0 },
3532   },
3533
3534   /* PREFIX_0F10 */
3535   {
3536     { "movups", { XM, EXx }, PREFIX_OPCODE },
3537     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3538     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3539     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3540   },
3541
3542   /* PREFIX_0F11 */
3543   {
3544     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3545     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3546     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3547     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3548   },
3549
3550   /* PREFIX_0F12 */
3551   {
3552     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3553     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3554     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3555     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3556   },
3557
3558   /* PREFIX_0F16 */
3559   {
3560     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3561     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3562     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3563   },
3564
3565   /* PREFIX_0F1A */
3566   {
3567     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3568     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3569     { "bndmov", { Gbnd, Ebnd }, 0 },
3570     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3571   },
3572
3573   /* PREFIX_0F1B */
3574   {
3575     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3576     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3577     { "bndmov", { EbndS, Gbnd }, 0 },
3578     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3579   },
3580
3581   /* PREFIX_0F1C */
3582   {
3583     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3584     { "nopQ",   { Ev }, PREFIX_OPCODE },
3585     { "nopQ",   { Ev }, PREFIX_OPCODE },
3586     { "nopQ",   { Ev }, PREFIX_OPCODE },
3587   },
3588
3589   /* PREFIX_0F1E */
3590   {
3591     { "nopQ",   { Ev }, PREFIX_OPCODE },
3592     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3593     { "nopQ",   { Ev }, PREFIX_OPCODE },
3594     { "nopQ",   { Ev }, PREFIX_OPCODE },
3595   },
3596
3597   /* PREFIX_0F2A */
3598   {
3599     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3600     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3601     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3602     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3603   },
3604
3605   /* PREFIX_0F2B */
3606   {
3607     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3608     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3609     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3610     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3611   },
3612
3613   /* PREFIX_0F2C */
3614   {
3615     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3616     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3617     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3618     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3619   },
3620
3621   /* PREFIX_0F2D */
3622   {
3623     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3624     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3625     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3626     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3627   },
3628
3629   /* PREFIX_0F2E */
3630   {
3631     { "ucomiss",{ XM, EXd }, 0 },
3632     { Bad_Opcode },
3633     { "ucomisd",{ XM, EXq }, 0 },
3634   },
3635
3636   /* PREFIX_0F2F */
3637   {
3638     { "comiss", { XM, EXd }, 0 },
3639     { Bad_Opcode },
3640     { "comisd", { XM, EXq }, 0 },
3641   },
3642
3643   /* PREFIX_0F51 */
3644   {
3645     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3646     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3647     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3648     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3649   },
3650
3651   /* PREFIX_0F52 */
3652   {
3653     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3654     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3655   },
3656
3657   /* PREFIX_0F53 */
3658   {
3659     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3660     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3661   },
3662
3663   /* PREFIX_0F58 */
3664   {
3665     { "addps", { XM, EXx }, PREFIX_OPCODE },
3666     { "addss", { XM, EXd }, PREFIX_OPCODE },
3667     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3668     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3669   },
3670
3671   /* PREFIX_0F59 */
3672   {
3673     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3674     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3675     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3676     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3677   },
3678
3679   /* PREFIX_0F5A */
3680   {
3681     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3682     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3683     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3684     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3685   },
3686
3687   /* PREFIX_0F5B */
3688   {
3689     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3690     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3691     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3692   },
3693
3694   /* PREFIX_0F5C */
3695   {
3696     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3697     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3698     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3699     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3700   },
3701
3702   /* PREFIX_0F5D */
3703   {
3704     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3705     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3706     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3707     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3708   },
3709
3710   /* PREFIX_0F5E */
3711   {
3712     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3713     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3714     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3715     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3716   },
3717
3718   /* PREFIX_0F5F */
3719   {
3720     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3721     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3722     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3723     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3724   },
3725
3726   /* PREFIX_0F60 */
3727   {
3728     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3729     { Bad_Opcode },
3730     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3731   },
3732
3733   /* PREFIX_0F61 */
3734   {
3735     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3736     { Bad_Opcode },
3737     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3738   },
3739
3740   /* PREFIX_0F62 */
3741   {
3742     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3743     { Bad_Opcode },
3744     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3745   },
3746
3747   /* PREFIX_0F6C */
3748   {
3749     { Bad_Opcode },
3750     { Bad_Opcode },
3751     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3752   },
3753
3754   /* PREFIX_0F6D */
3755   {
3756     { Bad_Opcode },
3757     { Bad_Opcode },
3758     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3759   },
3760
3761   /* PREFIX_0F6F */
3762   {
3763     { "movq",   { MX, EM }, PREFIX_OPCODE },
3764     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3765     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3766   },
3767
3768   /* PREFIX_0F70 */
3769   {
3770     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3771     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3772     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3773     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3774   },
3775
3776   /* PREFIX_0F73_REG_3 */
3777   {
3778     { Bad_Opcode },
3779     { Bad_Opcode },
3780     { "psrldq", { XS, Ib }, 0 },
3781   },
3782
3783   /* PREFIX_0F73_REG_7 */
3784   {
3785     { Bad_Opcode },
3786     { Bad_Opcode },
3787     { "pslldq", { XS, Ib }, 0 },
3788   },
3789
3790   /* PREFIX_0F78 */
3791   {
3792     {"vmread",  { Em, Gm }, 0 },
3793     { Bad_Opcode },
3794     {"extrq",   { XS, Ib, Ib }, 0 },
3795     {"insertq", { XM, XS, Ib, Ib }, 0 },
3796   },
3797
3798   /* PREFIX_0F79 */
3799   {
3800     {"vmwrite", { Gm, Em }, 0 },
3801     { Bad_Opcode },
3802     {"extrq",   { XM, XS }, 0 },
3803     {"insertq", { XM, XS }, 0 },
3804   },
3805
3806   /* PREFIX_0F7C */
3807   {
3808     { Bad_Opcode },
3809     { Bad_Opcode },
3810     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3811     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3812   },
3813
3814   /* PREFIX_0F7D */
3815   {
3816     { Bad_Opcode },
3817     { Bad_Opcode },
3818     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3819     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3820   },
3821
3822   /* PREFIX_0F7E */
3823   {
3824     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3825     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3826     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3827   },
3828
3829   /* PREFIX_0F7F */
3830   {
3831     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3832     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3833     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3834   },
3835
3836   /* PREFIX_0FAE_REG_0_MOD_3 */
3837   {
3838     { Bad_Opcode },
3839     { "rdfsbase", { Ev }, 0 },
3840   },
3841
3842   /* PREFIX_0FAE_REG_1_MOD_3 */
3843   {
3844     { Bad_Opcode },
3845     { "rdgsbase", { Ev }, 0 },
3846   },
3847
3848   /* PREFIX_0FAE_REG_2_MOD_3 */
3849   {
3850     { Bad_Opcode },
3851     { "wrfsbase", { Ev }, 0 },
3852   },
3853
3854   /* PREFIX_0FAE_REG_3_MOD_3 */
3855   {
3856     { Bad_Opcode },
3857     { "wrgsbase", { Ev }, 0 },
3858   },
3859
3860   /* PREFIX_0FAE_REG_4_MOD_0 */
3861   {
3862     { "xsave",  { FXSAVE }, 0 },
3863     { "ptwrite%LQ", { Edq }, 0 },
3864   },
3865
3866   /* PREFIX_0FAE_REG_4_MOD_3 */
3867   {
3868     { Bad_Opcode },
3869     { "ptwrite%LQ", { Edq }, 0 },
3870   },
3871
3872   /* PREFIX_0FAE_REG_5_MOD_0 */
3873   {
3874     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3875   },
3876
3877   /* PREFIX_0FAE_REG_5_MOD_3 */
3878   {
3879     { "lfence",         { Skip_MODRM }, 0 },
3880     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3881   },
3882
3883   /* PREFIX_0FAE_REG_6_MOD_0 */
3884   {
3885     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3886     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3887     { "clwb",   { Mb }, PREFIX_OPCODE },
3888   },
3889
3890   /* PREFIX_0FAE_REG_6_MOD_3 */
3891   {
3892     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3893     { "umonitor",       { Eva }, PREFIX_OPCODE },
3894     { "tpause", { Edq }, PREFIX_OPCODE },
3895     { "umwait", { Edq }, PREFIX_OPCODE },
3896   },
3897
3898   /* PREFIX_0FAE_REG_7_MOD_0 */
3899   {
3900     { "clflush",        { Mb }, 0 },
3901     { Bad_Opcode },
3902     { "clflushopt",     { Mb }, 0 },
3903   },
3904
3905   /* PREFIX_0FB8 */
3906   {
3907     { Bad_Opcode },
3908     { "popcntS", { Gv, Ev }, 0 },
3909   },
3910
3911   /* PREFIX_0FBC */
3912   {
3913     { "bsfS",   { Gv, Ev }, 0 },
3914     { "tzcntS", { Gv, Ev }, 0 },
3915     { "bsfS",   { Gv, Ev }, 0 },
3916   },
3917
3918   /* PREFIX_0FBD */
3919   {
3920     { "bsrS",   { Gv, Ev }, 0 },
3921     { "lzcntS", { Gv, Ev }, 0 },
3922     { "bsrS",   { Gv, Ev }, 0 },
3923   },
3924
3925   /* PREFIX_0FC2 */
3926   {
3927     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3928     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3929     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3930     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3931   },
3932
3933   /* PREFIX_0FC3_MOD_0 */
3934   {
3935     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3936   },
3937
3938   /* PREFIX_0FC7_REG_6_MOD_0 */
3939   {
3940     { "vmptrld",{ Mq }, 0 },
3941     { "vmxon",  { Mq }, 0 },
3942     { "vmclear",{ Mq }, 0 },
3943   },
3944
3945   /* PREFIX_0FC7_REG_6_MOD_3 */
3946   {
3947     { "rdrand", { Ev }, 0 },
3948     { Bad_Opcode },
3949     { "rdrand", { Ev }, 0 }
3950   },
3951
3952   /* PREFIX_0FC7_REG_7_MOD_3 */
3953   {
3954     { "rdseed", { Ev }, 0 },
3955     { "rdpid",  { Em }, 0 },
3956     { "rdseed", { Ev }, 0 },
3957   },
3958
3959   /* PREFIX_0FD0 */
3960   {
3961     { Bad_Opcode },
3962     { Bad_Opcode },
3963     { "addsubpd", { XM, EXx }, 0 },
3964     { "addsubps", { XM, EXx }, 0 },
3965   },
3966
3967   /* PREFIX_0FD6 */
3968   {
3969     { Bad_Opcode },
3970     { "movq2dq",{ XM, MS }, 0 },
3971     { "movq",   { EXqS, XM }, 0 },
3972     { "movdq2q",{ MX, XS }, 0 },
3973   },
3974
3975   /* PREFIX_0FE6 */
3976   {
3977     { Bad_Opcode },
3978     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3979     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3980     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3981   },
3982
3983   /* PREFIX_0FE7 */
3984   {
3985     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3986     { Bad_Opcode },
3987     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3988   },
3989
3990   /* PREFIX_0FF0 */
3991   {
3992     { Bad_Opcode },
3993     { Bad_Opcode },
3994     { Bad_Opcode },
3995     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3996   },
3997
3998   /* PREFIX_0FF7 */
3999   {
4000     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4001     { Bad_Opcode },
4002     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4003   },
4004
4005   /* PREFIX_0F3810 */
4006   {
4007     { Bad_Opcode },
4008     { Bad_Opcode },
4009     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4010   },
4011
4012   /* PREFIX_0F3814 */
4013   {
4014     { Bad_Opcode },
4015     { Bad_Opcode },
4016     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4017   },
4018
4019   /* PREFIX_0F3815 */
4020   {
4021     { Bad_Opcode },
4022     { Bad_Opcode },
4023     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4024   },
4025
4026   /* PREFIX_0F3817 */
4027   {
4028     { Bad_Opcode },
4029     { Bad_Opcode },
4030     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4031   },
4032
4033   /* PREFIX_0F3820 */
4034   {
4035     { Bad_Opcode },
4036     { Bad_Opcode },
4037     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4038   },
4039
4040   /* PREFIX_0F3821 */
4041   {
4042     { Bad_Opcode },
4043     { Bad_Opcode },
4044     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4045   },
4046
4047   /* PREFIX_0F3822 */
4048   {
4049     { Bad_Opcode },
4050     { Bad_Opcode },
4051     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4052   },
4053
4054   /* PREFIX_0F3823 */
4055   {
4056     { Bad_Opcode },
4057     { Bad_Opcode },
4058     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4059   },
4060
4061   /* PREFIX_0F3824 */
4062   {
4063     { Bad_Opcode },
4064     { Bad_Opcode },
4065     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4066   },
4067
4068   /* PREFIX_0F3825 */
4069   {
4070     { Bad_Opcode },
4071     { Bad_Opcode },
4072     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4073   },
4074
4075   /* PREFIX_0F3828 */
4076   {
4077     { Bad_Opcode },
4078     { Bad_Opcode },
4079     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4080   },
4081
4082   /* PREFIX_0F3829 */
4083   {
4084     { Bad_Opcode },
4085     { Bad_Opcode },
4086     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4087   },
4088
4089   /* PREFIX_0F382A */
4090   {
4091     { Bad_Opcode },
4092     { Bad_Opcode },
4093     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4094   },
4095
4096   /* PREFIX_0F382B */
4097   {
4098     { Bad_Opcode },
4099     { Bad_Opcode },
4100     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4101   },
4102
4103   /* PREFIX_0F3830 */
4104   {
4105     { Bad_Opcode },
4106     { Bad_Opcode },
4107     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4108   },
4109
4110   /* PREFIX_0F3831 */
4111   {
4112     { Bad_Opcode },
4113     { Bad_Opcode },
4114     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4115   },
4116
4117   /* PREFIX_0F3832 */
4118   {
4119     { Bad_Opcode },
4120     { Bad_Opcode },
4121     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4122   },
4123
4124   /* PREFIX_0F3833 */
4125   {
4126     { Bad_Opcode },
4127     { Bad_Opcode },
4128     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4129   },
4130
4131   /* PREFIX_0F3834 */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4136   },
4137
4138   /* PREFIX_0F3835 */
4139   {
4140     { Bad_Opcode },
4141     { Bad_Opcode },
4142     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4143   },
4144
4145   /* PREFIX_0F3837 */
4146   {
4147     { Bad_Opcode },
4148     { Bad_Opcode },
4149     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4150   },
4151
4152   /* PREFIX_0F3838 */
4153   {
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4157   },
4158
4159   /* PREFIX_0F3839 */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4164   },
4165
4166   /* PREFIX_0F383A */
4167   {
4168     { Bad_Opcode },
4169     { Bad_Opcode },
4170     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4171   },
4172
4173   /* PREFIX_0F383B */
4174   {
4175     { Bad_Opcode },
4176     { Bad_Opcode },
4177     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4178   },
4179
4180   /* PREFIX_0F383C */
4181   {
4182     { Bad_Opcode },
4183     { Bad_Opcode },
4184     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_0F383D */
4188   {
4189     { Bad_Opcode },
4190     { Bad_Opcode },
4191     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4192   },
4193
4194   /* PREFIX_0F383E */
4195   {
4196     { Bad_Opcode },
4197     { Bad_Opcode },
4198     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4199   },
4200
4201   /* PREFIX_0F383F */
4202   {
4203     { Bad_Opcode },
4204     { Bad_Opcode },
4205     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4206   },
4207
4208   /* PREFIX_0F3840 */
4209   {
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4213   },
4214
4215   /* PREFIX_0F3841 */
4216   {
4217     { Bad_Opcode },
4218     { Bad_Opcode },
4219     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4220   },
4221
4222   /* PREFIX_0F3880 */
4223   {
4224     { Bad_Opcode },
4225     { Bad_Opcode },
4226     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4227   },
4228
4229   /* PREFIX_0F3881 */
4230   {
4231     { Bad_Opcode },
4232     { Bad_Opcode },
4233     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4234   },
4235
4236   /* PREFIX_0F3882 */
4237   {
4238     { Bad_Opcode },
4239     { Bad_Opcode },
4240     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4241   },
4242
4243   /* PREFIX_0F38C8 */
4244   {
4245     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F38C9 */
4249   {
4250     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F38CA */
4254   {
4255     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4256   },
4257
4258   /* PREFIX_0F38CB */
4259   {
4260     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4261   },
4262
4263   /* PREFIX_0F38CC */
4264   {
4265     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F38CD */
4269   {
4270     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4271   },
4272
4273   /* PREFIX_0F38CF */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4278   },
4279
4280   /* PREFIX_0F38DB */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4285   },
4286
4287   /* PREFIX_0F38DC */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4292   },
4293
4294   /* PREFIX_0F38DD */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4299   },
4300
4301   /* PREFIX_0F38DE */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F38DF */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F38F0 */
4316   {
4317     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4318     { Bad_Opcode },
4319     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4320     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F38F1 */
4324   {
4325     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4326     { Bad_Opcode },
4327     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4328     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F38F5 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4336   },
4337
4338   /* PREFIX_0F38F6 */
4339   {
4340     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4341     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4342     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4343     { Bad_Opcode },
4344   },
4345
4346   /* PREFIX_0F38F8 */
4347   {
4348     { Bad_Opcode },
4349     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4350     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4351     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4352   },
4353
4354   /* PREFIX_0F38F9 */
4355   {
4356     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4357   },
4358
4359   /* PREFIX_0F3A08 */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F3A09 */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F3A0A */
4374   {
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F3A0B */
4381   {
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F3A0C */
4388   {
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F3A0D */
4395   {
4396     { Bad_Opcode },
4397     { Bad_Opcode },
4398     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4399   },
4400
4401   /* PREFIX_0F3A0E */
4402   {
4403     { Bad_Opcode },
4404     { Bad_Opcode },
4405     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4406   },
4407
4408   /* PREFIX_0F3A14 */
4409   {
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4413   },
4414
4415   /* PREFIX_0F3A15 */
4416   {
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4420   },
4421
4422   /* PREFIX_0F3A16 */
4423   {
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4427   },
4428
4429   /* PREFIX_0F3A17 */
4430   {
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4434   },
4435
4436   /* PREFIX_0F3A20 */
4437   {
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4441   },
4442
4443   /* PREFIX_0F3A21 */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4448   },
4449
4450   /* PREFIX_0F3A22 */
4451   {
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4455   },
4456
4457   /* PREFIX_0F3A40 */
4458   {
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4462   },
4463
4464   /* PREFIX_0F3A41 */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4469   },
4470
4471   /* PREFIX_0F3A42 */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4476   },
4477
4478   /* PREFIX_0F3A44 */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4483   },
4484
4485   /* PREFIX_0F3A60 */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4490   },
4491
4492   /* PREFIX_0F3A61 */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4497   },
4498
4499   /* PREFIX_0F3A62 */
4500   {
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4504   },
4505
4506   /* PREFIX_0F3A63 */
4507   {
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4511   },
4512
4513   /* PREFIX_0F3ACC */
4514   {
4515     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3ACE */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3ACF */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3ADF */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_VEX_0F10 */
4540   {
4541     { "vmovups",        { XM, EXx }, 0 },
4542     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4543     { "vmovupd",        { XM, EXx }, 0 },
4544     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4545   },
4546
4547   /* PREFIX_VEX_0F11 */
4548   {
4549     { "vmovups",        { EXxS, XM }, 0 },
4550     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4551     { "vmovupd",        { EXxS, XM }, 0 },
4552     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4553   },
4554
4555   /* PREFIX_VEX_0F12 */
4556   {
4557     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4558     { "vmovsldup",      { XM, EXx }, 0 },
4559     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4560     { "vmovddup",       { XM, EXymmq }, 0 },
4561   },
4562
4563   /* PREFIX_VEX_0F16 */
4564   {
4565     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4566     { "vmovshdup",      { XM, EXx }, 0 },
4567     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4568   },
4569
4570   /* PREFIX_VEX_0F2A */
4571   {
4572     { Bad_Opcode },
4573     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4574     { Bad_Opcode },
4575     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4576   },
4577
4578   /* PREFIX_VEX_0F2C */
4579   {
4580     { Bad_Opcode },
4581     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4582     { Bad_Opcode },
4583     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4584   },
4585
4586   /* PREFIX_VEX_0F2D */
4587   {
4588     { Bad_Opcode },
4589     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4590     { Bad_Opcode },
4591     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4592   },
4593
4594   /* PREFIX_VEX_0F2E */
4595   {
4596     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4597     { Bad_Opcode },
4598     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4599   },
4600
4601   /* PREFIX_VEX_0F2F */
4602   {
4603     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4604     { Bad_Opcode },
4605     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4606   },
4607
4608   /* PREFIX_VEX_0F41 */
4609   {
4610     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4611     { Bad_Opcode },
4612     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4613   },
4614
4615   /* PREFIX_VEX_0F42 */
4616   {
4617     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4618     { Bad_Opcode },
4619     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4620   },
4621
4622   /* PREFIX_VEX_0F44 */
4623   {
4624     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4625     { Bad_Opcode },
4626     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4627   },
4628
4629   /* PREFIX_VEX_0F45 */
4630   {
4631     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4632     { Bad_Opcode },
4633     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4634   },
4635
4636   /* PREFIX_VEX_0F46 */
4637   {
4638     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4639     { Bad_Opcode },
4640     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4641   },
4642
4643   /* PREFIX_VEX_0F47 */
4644   {
4645     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4646     { Bad_Opcode },
4647     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4648   },
4649
4650   /* PREFIX_VEX_0F4A */
4651   {
4652     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4653     { Bad_Opcode },
4654     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4655   },
4656
4657   /* PREFIX_VEX_0F4B */
4658   {
4659     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4660     { Bad_Opcode },
4661     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4662   },
4663
4664   /* PREFIX_VEX_0F51 */
4665   {
4666     { "vsqrtps",        { XM, EXx }, 0 },
4667     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4668     { "vsqrtpd",        { XM, EXx }, 0 },
4669     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4670   },
4671
4672   /* PREFIX_VEX_0F52 */
4673   {
4674     { "vrsqrtps",       { XM, EXx }, 0 },
4675     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4676   },
4677
4678   /* PREFIX_VEX_0F53 */
4679   {
4680     { "vrcpps",         { XM, EXx }, 0 },
4681     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4682   },
4683
4684   /* PREFIX_VEX_0F58 */
4685   {
4686     { "vaddps",         { XM, Vex, EXx }, 0 },
4687     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4688     { "vaddpd",         { XM, Vex, EXx }, 0 },
4689     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4690   },
4691
4692   /* PREFIX_VEX_0F59 */
4693   {
4694     { "vmulps",         { XM, Vex, EXx }, 0 },
4695     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4696     { "vmulpd",         { XM, Vex, EXx }, 0 },
4697     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4698   },
4699
4700   /* PREFIX_VEX_0F5A */
4701   {
4702     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4703     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4704     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4705     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4706   },
4707
4708   /* PREFIX_VEX_0F5B */
4709   {
4710     { "vcvtdq2ps",      { XM, EXx }, 0 },
4711     { "vcvttps2dq",     { XM, EXx }, 0 },
4712     { "vcvtps2dq",      { XM, EXx }, 0 },
4713   },
4714
4715   /* PREFIX_VEX_0F5C */
4716   {
4717     { "vsubps",         { XM, Vex, EXx }, 0 },
4718     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4719     { "vsubpd",         { XM, Vex, EXx }, 0 },
4720     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4721   },
4722
4723   /* PREFIX_VEX_0F5D */
4724   {
4725     { "vminps",         { XM, Vex, EXx }, 0 },
4726     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4727     { "vminpd",         { XM, Vex, EXx }, 0 },
4728     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4729   },
4730
4731   /* PREFIX_VEX_0F5E */
4732   {
4733     { "vdivps",         { XM, Vex, EXx }, 0 },
4734     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4735     { "vdivpd",         { XM, Vex, EXx }, 0 },
4736     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4737   },
4738
4739   /* PREFIX_VEX_0F5F */
4740   {
4741     { "vmaxps",         { XM, Vex, EXx }, 0 },
4742     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4743     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4744     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4745   },
4746
4747   /* PREFIX_VEX_0F60 */
4748   {
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4752   },
4753
4754   /* PREFIX_VEX_0F61 */
4755   {
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4759   },
4760
4761   /* PREFIX_VEX_0F62 */
4762   {
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4766   },
4767
4768   /* PREFIX_VEX_0F63 */
4769   {
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4773   },
4774
4775   /* PREFIX_VEX_0F64 */
4776   {
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4780   },
4781
4782   /* PREFIX_VEX_0F65 */
4783   {
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4787   },
4788
4789   /* PREFIX_VEX_0F66 */
4790   {
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4794   },
4795
4796   /* PREFIX_VEX_0F67 */
4797   {
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4801   },
4802
4803   /* PREFIX_VEX_0F68 */
4804   {
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F69 */
4811   {
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4815   },
4816
4817   /* PREFIX_VEX_0F6A */
4818   {
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4822   },
4823
4824   /* PREFIX_VEX_0F6B */
4825   {
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4829   },
4830
4831   /* PREFIX_VEX_0F6C */
4832   {
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4836   },
4837
4838   /* PREFIX_VEX_0F6D */
4839   {
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4843   },
4844
4845   /* PREFIX_VEX_0F6E */
4846   {
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4850   },
4851
4852   /* PREFIX_VEX_0F6F */
4853   {
4854     { Bad_Opcode },
4855     { "vmovdqu",        { XM, EXx }, 0 },
4856     { "vmovdqa",        { XM, EXx }, 0 },
4857   },
4858
4859   /* PREFIX_VEX_0F70 */
4860   {
4861     { Bad_Opcode },
4862     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4863     { "vpshufd",        { XM, EXx, Ib }, 0 },
4864     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4865   },
4866
4867   /* PREFIX_VEX_0F71_REG_2 */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4872   },
4873
4874   /* PREFIX_VEX_0F71_REG_4 */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { "vpsraw",         { Vex, XS, Ib }, 0 },
4879   },
4880
4881   /* PREFIX_VEX_0F71_REG_6 */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { "vpsllw",         { Vex, XS, Ib }, 0 },
4886   },
4887
4888   /* PREFIX_VEX_0F72_REG_2 */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { "vpsrld",         { Vex, XS, Ib }, 0 },
4893   },
4894
4895   /* PREFIX_VEX_0F72_REG_4 */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { "vpsrad",         { Vex, XS, Ib }, 0 },
4900   },
4901
4902   /* PREFIX_VEX_0F72_REG_6 */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { "vpslld",         { Vex, XS, Ib }, 0 },
4907   },
4908
4909   /* PREFIX_VEX_0F73_REG_2 */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4914   },
4915
4916   /* PREFIX_VEX_0F73_REG_3 */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { "vpsrldq",        { Vex, XS, Ib }, 0 },
4921   },
4922
4923   /* PREFIX_VEX_0F73_REG_6 */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { "vpsllq",         { Vex, XS, Ib }, 0 },
4928   },
4929
4930   /* PREFIX_VEX_0F73_REG_7 */
4931   {
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { "vpslldq",        { Vex, XS, Ib }, 0 },
4935   },
4936
4937   /* PREFIX_VEX_0F74 */
4938   {
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
4942   },
4943
4944   /* PREFIX_VEX_0F75 */
4945   {
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
4949   },
4950
4951   /* PREFIX_VEX_0F76 */
4952   {
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
4956   },
4957
4958   /* PREFIX_VEX_0F77 */
4959   {
4960     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
4961   },
4962
4963   /* PREFIX_VEX_0F7C */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { "vhaddpd",        { XM, Vex, EXx }, 0 },
4968     { "vhaddps",        { XM, Vex, EXx }, 0 },
4969   },
4970
4971   /* PREFIX_VEX_0F7D */
4972   {
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { "vhsubpd",        { XM, Vex, EXx }, 0 },
4976     { "vhsubps",        { XM, Vex, EXx }, 0 },
4977   },
4978
4979   /* PREFIX_VEX_0F7E */
4980   {
4981     { Bad_Opcode },
4982     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4983     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4984   },
4985
4986   /* PREFIX_VEX_0F7F */
4987   {
4988     { Bad_Opcode },
4989     { "vmovdqu",        { EXxS, XM }, 0 },
4990     { "vmovdqa",        { EXxS, XM }, 0 },
4991   },
4992
4993   /* PREFIX_VEX_0F90 */
4994   {
4995     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4996     { Bad_Opcode },
4997     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
4998   },
4999
5000   /* PREFIX_VEX_0F91 */
5001   {
5002     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5003     { Bad_Opcode },
5004     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5005   },
5006
5007   /* PREFIX_VEX_0F92 */
5008   {
5009     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5010     { Bad_Opcode },
5011     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5012     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5013   },
5014
5015   /* PREFIX_VEX_0F93 */
5016   {
5017     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5018     { Bad_Opcode },
5019     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5020     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5021   },
5022
5023   /* PREFIX_VEX_0F98 */
5024   {
5025     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5026     { Bad_Opcode },
5027     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5028   },
5029
5030   /* PREFIX_VEX_0F99 */
5031   {
5032     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5033     { Bad_Opcode },
5034     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5035   },
5036
5037   /* PREFIX_VEX_0FC2 */
5038   {
5039     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5040     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5041     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5042     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5043   },
5044
5045   /* PREFIX_VEX_0FC4 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5050   },
5051
5052   /* PREFIX_VEX_0FC5 */
5053   {
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5057   },
5058
5059   /* PREFIX_VEX_0FD0 */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5064     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5065   },
5066
5067   /* PREFIX_VEX_0FD1 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5072   },
5073
5074   /* PREFIX_VEX_0FD2 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5079   },
5080
5081   /* PREFIX_VEX_0FD3 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5086   },
5087
5088   /* PREFIX_VEX_0FD4 */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { "vpaddq",         { XM, Vex, EXx }, 0 },
5093   },
5094
5095   /* PREFIX_VEX_0FD5 */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { "vpmullw",        { XM, Vex, EXx }, 0 },
5100   },
5101
5102   /* PREFIX_VEX_0FD6 */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_0FD7 */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5114   },
5115
5116   /* PREFIX_VEX_0FD8 */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5121   },
5122
5123   /* PREFIX_VEX_0FD9 */
5124   {
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5128   },
5129
5130   /* PREFIX_VEX_0FDA */
5131   {
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { "vpminub",        { XM, Vex, EXx }, 0 },
5135   },
5136
5137   /* PREFIX_VEX_0FDB */
5138   {
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { "vpand",          { XM, Vex, EXx }, 0 },
5142   },
5143
5144   /* PREFIX_VEX_0FDC */
5145   {
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5149   },
5150
5151   /* PREFIX_VEX_0FDD */
5152   {
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5156   },
5157
5158   /* PREFIX_VEX_0FDE */
5159   {
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5163   },
5164
5165   /* PREFIX_VEX_0FDF */
5166   {
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { "vpandn",         { XM, Vex, EXx }, 0 },
5170   },
5171
5172   /* PREFIX_VEX_0FE0 */
5173   {
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { "vpavgb",         { XM, Vex, EXx }, 0 },
5177   },
5178
5179   /* PREFIX_VEX_0FE1 */
5180   {
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5184   },
5185
5186   /* PREFIX_VEX_0FE2 */
5187   {
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5191   },
5192
5193   /* PREFIX_VEX_0FE3 */
5194   {
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { "vpavgw",         { XM, Vex, EXx }, 0 },
5198   },
5199
5200   /* PREFIX_VEX_0FE4 */
5201   {
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5205   },
5206
5207   /* PREFIX_VEX_0FE5 */
5208   {
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5212   },
5213
5214   /* PREFIX_VEX_0FE6 */
5215   {
5216     { Bad_Opcode },
5217     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5218     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5219     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5220   },
5221
5222   /* PREFIX_VEX_0FE7 */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5227   },
5228
5229   /* PREFIX_VEX_0FE8 */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5234   },
5235
5236   /* PREFIX_VEX_0FE9 */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5241   },
5242
5243   /* PREFIX_VEX_0FEA */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { "vpminsw",        { XM, Vex, EXx }, 0 },
5248   },
5249
5250   /* PREFIX_VEX_0FEB */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { "vpor",           { XM, Vex, EXx }, 0 },
5255   },
5256
5257   /* PREFIX_VEX_0FEC */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5262   },
5263
5264   /* PREFIX_VEX_0FED */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5269   },
5270
5271   /* PREFIX_VEX_0FEE */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5276   },
5277
5278   /* PREFIX_VEX_0FEF */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { "vpxor",          { XM, Vex, EXx }, 0 },
5283   },
5284
5285   /* PREFIX_VEX_0FF0 */
5286   {
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5291   },
5292
5293   /* PREFIX_VEX_0FF1 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5298   },
5299
5300   /* PREFIX_VEX_0FF2 */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5305   },
5306
5307   /* PREFIX_VEX_0FF3 */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5312   },
5313
5314   /* PREFIX_VEX_0FF4 */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5319   },
5320
5321   /* PREFIX_VEX_0FF5 */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5326   },
5327
5328   /* PREFIX_VEX_0FF6 */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5333   },
5334
5335   /* PREFIX_VEX_0FF7 */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5340   },
5341
5342   /* PREFIX_VEX_0FF8 */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { "vpsubb",         { XM, Vex, EXx }, 0 },
5347   },
5348
5349   /* PREFIX_VEX_0FF9 */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { "vpsubw",         { XM, Vex, EXx }, 0 },
5354   },
5355
5356   /* PREFIX_VEX_0FFA */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { "vpsubd",         { XM, Vex, EXx }, 0 },
5361   },
5362
5363   /* PREFIX_VEX_0FFB */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { "vpsubq",         { XM, Vex, EXx }, 0 },
5368   },
5369
5370   /* PREFIX_VEX_0FFC */
5371   {
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { "vpaddb",         { XM, Vex, EXx }, 0 },
5375   },
5376
5377   /* PREFIX_VEX_0FFD */
5378   {
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { "vpaddw",         { XM, Vex, EXx }, 0 },
5382   },
5383
5384   /* PREFIX_VEX_0FFE */
5385   {
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { "vpaddd",         { XM, Vex, EXx }, 0 },
5389   },
5390
5391   /* PREFIX_VEX_0F3800 */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { "vpshufb",        { XM, Vex, EXx }, 0 },
5396   },
5397
5398   /* PREFIX_VEX_0F3801 */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { "vphaddw",        { XM, Vex, EXx }, 0 },
5403   },
5404
5405   /* PREFIX_VEX_0F3802 */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { "vphaddd",        { XM, Vex, EXx }, 0 },
5410   },
5411
5412   /* PREFIX_VEX_0F3803 */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5417   },
5418
5419   /* PREFIX_VEX_0F3804 */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5424   },
5425
5426   /* PREFIX_VEX_0F3805 */
5427   {
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { "vphsubw",        { XM, Vex, EXx }, 0 },
5431   },
5432
5433   /* PREFIX_VEX_0F3806 */
5434   {
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { "vphsubd",        { XM, Vex, EXx }, 0 },
5438   },
5439
5440   /* PREFIX_VEX_0F3807 */
5441   {
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5445   },
5446
5447   /* PREFIX_VEX_0F3808 */
5448   {
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { "vpsignb",        { XM, Vex, EXx }, 0 },
5452   },
5453
5454   /* PREFIX_VEX_0F3809 */
5455   {
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { "vpsignw",        { XM, Vex, EXx }, 0 },
5459   },
5460
5461   /* PREFIX_VEX_0F380A */
5462   {
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { "vpsignd",        { XM, Vex, EXx }, 0 },
5466   },
5467
5468   /* PREFIX_VEX_0F380B */
5469   {
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5473   },
5474
5475   /* PREFIX_VEX_0F380C */
5476   {
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5480   },
5481
5482   /* PREFIX_VEX_0F380D */
5483   {
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5487   },
5488
5489   /* PREFIX_VEX_0F380E */
5490   {
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5494   },
5495
5496   /* PREFIX_VEX_0F380F */
5497   {
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5501   },
5502
5503   /* PREFIX_VEX_0F3813 */
5504   {
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5508   },
5509
5510   /* PREFIX_VEX_0F3816 */
5511   {
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5515   },
5516
5517   /* PREFIX_VEX_0F3817 */
5518   {
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { "vptest",         { XM, EXx }, 0 },
5522   },
5523
5524   /* PREFIX_VEX_0F3818 */
5525   {
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5529   },
5530
5531   /* PREFIX_VEX_0F3819 */
5532   {
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5536   },
5537
5538   /* PREFIX_VEX_0F381A */
5539   {
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5543   },
5544
5545   /* PREFIX_VEX_0F381C */
5546   {
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { "vpabsb",         { XM, EXx }, 0 },
5550   },
5551
5552   /* PREFIX_VEX_0F381D */
5553   {
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { "vpabsw",         { XM, EXx }, 0 },
5557   },
5558
5559   /* PREFIX_VEX_0F381E */
5560   {
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { "vpabsd",         { XM, EXx }, 0 },
5564   },
5565
5566   /* PREFIX_VEX_0F3820 */
5567   {
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5571   },
5572
5573   /* PREFIX_VEX_0F3821 */
5574   {
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5578   },
5579
5580   /* PREFIX_VEX_0F3822 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5585   },
5586
5587   /* PREFIX_VEX_0F3823 */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5592   },
5593
5594   /* PREFIX_VEX_0F3824 */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5599   },
5600
5601   /* PREFIX_VEX_0F3825 */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5606   },
5607
5608   /* PREFIX_VEX_0F3828 */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5613   },
5614
5615   /* PREFIX_VEX_0F3829 */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5620   },
5621
5622   /* PREFIX_VEX_0F382A */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5627   },
5628
5629   /* PREFIX_VEX_0F382B */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5634   },
5635
5636   /* PREFIX_VEX_0F382C */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5641   },
5642
5643   /* PREFIX_VEX_0F382D */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5648   },
5649
5650   /* PREFIX_VEX_0F382E */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5655   },
5656
5657   /* PREFIX_VEX_0F382F */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5662   },
5663
5664   /* PREFIX_VEX_0F3830 */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5669   },
5670
5671   /* PREFIX_VEX_0F3831 */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5676   },
5677
5678   /* PREFIX_VEX_0F3832 */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5683   },
5684
5685   /* PREFIX_VEX_0F3833 */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5690   },
5691
5692   /* PREFIX_VEX_0F3834 */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5697   },
5698
5699   /* PREFIX_VEX_0F3835 */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5704   },
5705
5706   /* PREFIX_VEX_0F3836 */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5711   },
5712
5713   /* PREFIX_VEX_0F3837 */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5718   },
5719
5720   /* PREFIX_VEX_0F3838 */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { "vpminsb",        { XM, Vex, EXx }, 0 },
5725   },
5726
5727   /* PREFIX_VEX_0F3839 */
5728   {
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { "vpminsd",        { XM, Vex, EXx }, 0 },
5732   },
5733
5734   /* PREFIX_VEX_0F383A */
5735   {
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { "vpminuw",        { XM, Vex, EXx }, 0 },
5739   },
5740
5741   /* PREFIX_VEX_0F383B */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { "vpminud",        { XM, Vex, EXx }, 0 },
5746   },
5747
5748   /* PREFIX_VEX_0F383C */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5753   },
5754
5755   /* PREFIX_VEX_0F383D */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5760   },
5761
5762   /* PREFIX_VEX_0F383E */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5767   },
5768
5769   /* PREFIX_VEX_0F383F */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5774   },
5775
5776   /* PREFIX_VEX_0F3840 */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { "vpmulld",        { XM, Vex, EXx }, 0 },
5781   },
5782
5783   /* PREFIX_VEX_0F3841 */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5788   },
5789
5790   /* PREFIX_VEX_0F3845 */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5795   },
5796
5797   /* PREFIX_VEX_0F3846 */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5802   },
5803
5804   /* PREFIX_VEX_0F3847 */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5809   },
5810
5811   /* PREFIX_VEX_0F3858 */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5816   },
5817
5818   /* PREFIX_VEX_0F3859 */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5823   },
5824
5825   /* PREFIX_VEX_0F385A */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5830   },
5831
5832   /* PREFIX_VEX_0F3878 */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5837   },
5838
5839   /* PREFIX_VEX_0F3879 */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5844   },
5845
5846   /* PREFIX_VEX_0F388C */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5851   },
5852
5853   /* PREFIX_VEX_0F388E */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5858   },
5859
5860   /* PREFIX_VEX_0F3890 */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5865   },
5866
5867   /* PREFIX_VEX_0F3891 */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5872   },
5873
5874   /* PREFIX_VEX_0F3892 */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5879   },
5880
5881   /* PREFIX_VEX_0F3893 */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5886   },
5887
5888   /* PREFIX_VEX_0F3896 */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5893   },
5894
5895   /* PREFIX_VEX_0F3897 */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5900   },
5901
5902   /* PREFIX_VEX_0F3898 */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5907   },
5908
5909   /* PREFIX_VEX_0F3899 */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5914   },
5915
5916   /* PREFIX_VEX_0F389A */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5921   },
5922
5923   /* PREFIX_VEX_0F389B */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5928   },
5929
5930   /* PREFIX_VEX_0F389C */
5931   {
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5935   },
5936
5937   /* PREFIX_VEX_0F389D */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5942   },
5943
5944   /* PREFIX_VEX_0F389E */
5945   {
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5949   },
5950
5951   /* PREFIX_VEX_0F389F */
5952   {
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5956   },
5957
5958   /* PREFIX_VEX_0F38A6 */
5959   {
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5963     { Bad_Opcode },
5964   },
5965
5966   /* PREFIX_VEX_0F38A7 */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5971   },
5972
5973   /* PREFIX_VEX_0F38A8 */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5978   },
5979
5980   /* PREFIX_VEX_0F38A9 */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5985   },
5986
5987   /* PREFIX_VEX_0F38AA */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
5992   },
5993
5994   /* PREFIX_VEX_0F38AB */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5999   },
6000
6001   /* PREFIX_VEX_0F38AC */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6006   },
6007
6008   /* PREFIX_VEX_0F38AD */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6013   },
6014
6015   /* PREFIX_VEX_0F38AE */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6020   },
6021
6022   /* PREFIX_VEX_0F38AF */
6023   {
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6027   },
6028
6029   /* PREFIX_VEX_0F38B6 */
6030   {
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6034   },
6035
6036   /* PREFIX_VEX_0F38B7 */
6037   {
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6041   },
6042
6043   /* PREFIX_VEX_0F38B8 */
6044   {
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6048   },
6049
6050   /* PREFIX_VEX_0F38B9 */
6051   {
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6055   },
6056
6057   /* PREFIX_VEX_0F38BA */
6058   {
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6062   },
6063
6064   /* PREFIX_VEX_0F38BB */
6065   {
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6069   },
6070
6071   /* PREFIX_VEX_0F38BC */
6072   {
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6076   },
6077
6078   /* PREFIX_VEX_0F38BD */
6079   {
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6083   },
6084
6085   /* PREFIX_VEX_0F38BE */
6086   {
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6090   },
6091
6092   /* PREFIX_VEX_0F38BF */
6093   {
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6097   },
6098
6099   /* PREFIX_VEX_0F38CF */
6100   {
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6104   },
6105
6106   /* PREFIX_VEX_0F38DB */
6107   {
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6111   },
6112
6113   /* PREFIX_VEX_0F38DC */
6114   {
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { "vaesenc",        { XM, Vex, EXx }, 0 },
6118   },
6119
6120   /* PREFIX_VEX_0F38DD */
6121   {
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6125   },
6126
6127   /* PREFIX_VEX_0F38DE */
6128   {
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { "vaesdec",        { XM, Vex, EXx }, 0 },
6132   },
6133
6134   /* PREFIX_VEX_0F38DF */
6135   {
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6139   },
6140
6141   /* PREFIX_VEX_0F38F2 */
6142   {
6143     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6144   },
6145
6146   /* PREFIX_VEX_0F38F3_REG_1 */
6147   {
6148     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6149   },
6150
6151   /* PREFIX_VEX_0F38F3_REG_2 */
6152   {
6153     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6154   },
6155
6156   /* PREFIX_VEX_0F38F3_REG_3 */
6157   {
6158     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6159   },
6160
6161   /* PREFIX_VEX_0F38F5 */
6162   {
6163     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6164     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6165     { Bad_Opcode },
6166     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6167   },
6168
6169   /* PREFIX_VEX_0F38F6 */
6170   {
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6175   },
6176
6177   /* PREFIX_VEX_0F38F7 */
6178   {
6179     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6180     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6181     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6182     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6183   },
6184
6185   /* PREFIX_VEX_0F3A00 */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6190   },
6191
6192   /* PREFIX_VEX_0F3A01 */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6197   },
6198
6199   /* PREFIX_VEX_0F3A02 */
6200   {
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6204   },
6205
6206   /* PREFIX_VEX_0F3A04 */
6207   {
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6211   },
6212
6213   /* PREFIX_VEX_0F3A05 */
6214   {
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6218   },
6219
6220   /* PREFIX_VEX_0F3A06 */
6221   {
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6225   },
6226
6227   /* PREFIX_VEX_0F3A08 */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { "vroundps",       { XM, EXx, Ib }, 0 },
6232   },
6233
6234   /* PREFIX_VEX_0F3A09 */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { "vroundpd",       { XM, EXx, Ib }, 0 },
6239   },
6240
6241   /* PREFIX_VEX_0F3A0A */
6242   {
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6246   },
6247
6248   /* PREFIX_VEX_0F3A0B */
6249   {
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6253   },
6254
6255   /* PREFIX_VEX_0F3A0C */
6256   {
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6260   },
6261
6262   /* PREFIX_VEX_0F3A0D */
6263   {
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6267   },
6268
6269   /* PREFIX_VEX_0F3A0E */
6270   {
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6274   },
6275
6276   /* PREFIX_VEX_0F3A0F */
6277   {
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6281   },
6282
6283   /* PREFIX_VEX_0F3A14 */
6284   {
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6288   },
6289
6290   /* PREFIX_VEX_0F3A15 */
6291   {
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6295   },
6296
6297   /* PREFIX_VEX_0F3A16 */
6298   {
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6302   },
6303
6304   /* PREFIX_VEX_0F3A17 */
6305   {
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6309   },
6310
6311   /* PREFIX_VEX_0F3A18 */
6312   {
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6316   },
6317
6318   /* PREFIX_VEX_0F3A19 */
6319   {
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6323   },
6324
6325   /* PREFIX_VEX_0F3A1D */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6330   },
6331
6332   /* PREFIX_VEX_0F3A20 */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6337   },
6338
6339   /* PREFIX_VEX_0F3A21 */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6344   },
6345
6346   /* PREFIX_VEX_0F3A22 */
6347   {
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6351   },
6352
6353   /* PREFIX_VEX_0F3A30 */
6354   {
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6358   },
6359
6360   /* PREFIX_VEX_0F3A31 */
6361   {
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6365   },
6366
6367   /* PREFIX_VEX_0F3A32 */
6368   {
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6372   },
6373
6374   /* PREFIX_VEX_0F3A33 */
6375   {
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6379   },
6380
6381   /* PREFIX_VEX_0F3A38 */
6382   {
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6386   },
6387
6388   /* PREFIX_VEX_0F3A39 */
6389   {
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6393   },
6394
6395   /* PREFIX_VEX_0F3A40 */
6396   {
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6400   },
6401
6402   /* PREFIX_VEX_0F3A41 */
6403   {
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6407   },
6408
6409   /* PREFIX_VEX_0F3A42 */
6410   {
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6414   },
6415
6416   /* PREFIX_VEX_0F3A44 */
6417   {
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6421   },
6422
6423   /* PREFIX_VEX_0F3A46 */
6424   {
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6428   },
6429
6430   /* PREFIX_VEX_0F3A48 */
6431   {
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6435   },
6436
6437   /* PREFIX_VEX_0F3A49 */
6438   {
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6442   },
6443
6444   /* PREFIX_VEX_0F3A4A */
6445   {
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6449   },
6450
6451   /* PREFIX_VEX_0F3A4B */
6452   {
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6456   },
6457
6458   /* PREFIX_VEX_0F3A4C */
6459   {
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6463   },
6464
6465   /* PREFIX_VEX_0F3A5C */
6466   {
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6470   },
6471
6472   /* PREFIX_VEX_0F3A5D */
6473   {
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6477   },
6478
6479   /* PREFIX_VEX_0F3A5E */
6480   {
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6484   },
6485
6486   /* PREFIX_VEX_0F3A5F */
6487   {
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6491   },
6492
6493   /* PREFIX_VEX_0F3A60 */
6494   {
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6498     { Bad_Opcode },
6499   },
6500
6501   /* PREFIX_VEX_0F3A61 */
6502   {
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6506   },
6507
6508   /* PREFIX_VEX_0F3A62 */
6509   {
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6513   },
6514
6515   /* PREFIX_VEX_0F3A63 */
6516   {
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6520   },
6521
6522   /* PREFIX_VEX_0F3A68 */
6523   {
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6527   },
6528
6529   /* PREFIX_VEX_0F3A69 */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6534   },
6535
6536   /* PREFIX_VEX_0F3A6A */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6541   },
6542
6543   /* PREFIX_VEX_0F3A6B */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6548   },
6549
6550   /* PREFIX_VEX_0F3A6C */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6555   },
6556
6557   /* PREFIX_VEX_0F3A6D */
6558   {
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6562   },
6563
6564   /* PREFIX_VEX_0F3A6E */
6565   {
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6569   },
6570
6571   /* PREFIX_VEX_0F3A6F */
6572   {
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6576   },
6577
6578   /* PREFIX_VEX_0F3A78 */
6579   {
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6583   },
6584
6585   /* PREFIX_VEX_0F3A79 */
6586   {
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6590   },
6591
6592   /* PREFIX_VEX_0F3A7A */
6593   {
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6597   },
6598
6599   /* PREFIX_VEX_0F3A7B */
6600   {
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6604   },
6605
6606   /* PREFIX_VEX_0F3A7C */
6607   {
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6611     { Bad_Opcode },
6612   },
6613
6614   /* PREFIX_VEX_0F3A7D */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6619   },
6620
6621   /* PREFIX_VEX_0F3A7E */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6626   },
6627
6628   /* PREFIX_VEX_0F3A7F */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6633   },
6634
6635   /* PREFIX_VEX_0F3ACE */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3ACF */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6647   },
6648
6649   /* PREFIX_VEX_0F3ADF */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6654   },
6655
6656   /* PREFIX_VEX_0F3AF0 */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6662   },
6663
6664 #include "i386-dis-evex-prefix.h"
6665 };
6666
6667 static const struct dis386 x86_64_table[][2] = {
6668   /* X86_64_06 */
6669   {
6670     { "pushP", { es }, 0 },
6671   },
6672
6673   /* X86_64_07 */
6674   {
6675     { "popP", { es }, 0 },
6676   },
6677
6678   /* X86_64_0E */
6679   {
6680     { "pushP", { cs }, 0 },
6681   },
6682
6683   /* X86_64_16 */
6684   {
6685     { "pushP", { ss }, 0 },
6686   },
6687
6688   /* X86_64_17 */
6689   {
6690     { "popP", { ss }, 0 },
6691   },
6692
6693   /* X86_64_1E */
6694   {
6695     { "pushP", { ds }, 0 },
6696   },
6697
6698   /* X86_64_1F */
6699   {
6700     { "popP", { ds }, 0 },
6701   },
6702
6703   /* X86_64_27 */
6704   {
6705     { "daa", { XX }, 0 },
6706   },
6707
6708   /* X86_64_2F */
6709   {
6710     { "das", { XX }, 0 },
6711   },
6712
6713   /* X86_64_37 */
6714   {
6715     { "aaa", { XX }, 0 },
6716   },
6717
6718   /* X86_64_3F */
6719   {
6720     { "aas", { XX }, 0 },
6721   },
6722
6723   /* X86_64_60 */
6724   {
6725     { "pushaP", { XX }, 0 },
6726   },
6727
6728   /* X86_64_61 */
6729   {
6730     { "popaP", { XX }, 0 },
6731   },
6732
6733   /* X86_64_62 */
6734   {
6735     { MOD_TABLE (MOD_62_32BIT) },
6736     { EVEX_TABLE (EVEX_0F) },
6737   },
6738
6739   /* X86_64_63 */
6740   {
6741     { "arpl", { Ew, Gw }, 0 },
6742     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6743   },
6744
6745   /* X86_64_6D */
6746   {
6747     { "ins{R|}", { Yzr, indirDX }, 0 },
6748     { "ins{G|}", { Yzr, indirDX }, 0 },
6749   },
6750
6751   /* X86_64_6F */
6752   {
6753     { "outs{R|}", { indirDXr, Xz }, 0 },
6754     { "outs{G|}", { indirDXr, Xz }, 0 },
6755   },
6756
6757   /* X86_64_82 */
6758   {
6759     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6760     { REG_TABLE (REG_80) },
6761   },
6762
6763   /* X86_64_9A */
6764   {
6765     { "{l|}call{T|}", { Ap }, 0 },
6766   },
6767
6768   /* X86_64_C2 */
6769   {
6770     { "retP",           { Iw, BND }, 0 },
6771     { "ret@",           { Iw, BND }, 0 },
6772   },
6773
6774   /* X86_64_C3 */
6775   {
6776     { "retP",           { BND }, 0 },
6777     { "ret@",           { BND }, 0 },
6778   },
6779
6780   /* X86_64_C4 */
6781   {
6782     { MOD_TABLE (MOD_C4_32BIT) },
6783     { VEX_C4_TABLE (VEX_0F) },
6784   },
6785
6786   /* X86_64_C5 */
6787   {
6788     { MOD_TABLE (MOD_C5_32BIT) },
6789     { VEX_C5_TABLE (VEX_0F) },
6790   },
6791
6792   /* X86_64_CE */
6793   {
6794     { "into", { XX }, 0 },
6795   },
6796
6797   /* X86_64_D4 */
6798   {
6799     { "aam", { Ib }, 0 },
6800   },
6801
6802   /* X86_64_D5 */
6803   {
6804     { "aad", { Ib }, 0 },
6805   },
6806
6807   /* X86_64_E8 */
6808   {
6809     { "callP",          { Jv, BND }, 0 },
6810     { "call@",          { Jv, BND }, 0 }
6811   },
6812
6813   /* X86_64_E9 */
6814   {
6815     { "jmpP",           { Jv, BND }, 0 },
6816     { "jmp@",           { Jv, BND }, 0 }
6817   },
6818
6819   /* X86_64_EA */
6820   {
6821     { "{l|}jmp{T|}", { Ap }, 0 },
6822   },
6823
6824   /* X86_64_0F01_REG_0 */
6825   {
6826     { "sgdt{Q|Q}", { M }, 0 },
6827     { "sgdt", { M }, 0 },
6828   },
6829
6830   /* X86_64_0F01_REG_1 */
6831   {
6832     { "sidt{Q|Q}", { M }, 0 },
6833     { "sidt", { M }, 0 },
6834   },
6835
6836   /* X86_64_0F01_REG_2 */
6837   {
6838     { "lgdt{Q|Q}", { M }, 0 },
6839     { "lgdt", { M }, 0 },
6840   },
6841
6842   /* X86_64_0F01_REG_3 */
6843   {
6844     { "lidt{Q|Q}", { M }, 0 },
6845     { "lidt", { M }, 0 },
6846   },
6847 };
6848
6849 static const struct dis386 three_byte_table[][256] = {
6850
6851   /* THREE_BYTE_0F38 */
6852   {
6853     /* 00 */
6854     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6855     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6856     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6857     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6858     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6859     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6860     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6861     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6862     /* 08 */
6863     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6864     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6865     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6866     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     /* 10 */
6872     { PREFIX_TABLE (PREFIX_0F3810) },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { PREFIX_TABLE (PREFIX_0F3814) },
6877     { PREFIX_TABLE (PREFIX_0F3815) },
6878     { Bad_Opcode },
6879     { PREFIX_TABLE (PREFIX_0F3817) },
6880     /* 18 */
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6886     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6887     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6888     { Bad_Opcode },
6889     /* 20 */
6890     { PREFIX_TABLE (PREFIX_0F3820) },
6891     { PREFIX_TABLE (PREFIX_0F3821) },
6892     { PREFIX_TABLE (PREFIX_0F3822) },
6893     { PREFIX_TABLE (PREFIX_0F3823) },
6894     { PREFIX_TABLE (PREFIX_0F3824) },
6895     { PREFIX_TABLE (PREFIX_0F3825) },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     /* 28 */
6899     { PREFIX_TABLE (PREFIX_0F3828) },
6900     { PREFIX_TABLE (PREFIX_0F3829) },
6901     { PREFIX_TABLE (PREFIX_0F382A) },
6902     { PREFIX_TABLE (PREFIX_0F382B) },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     /* 30 */
6908     { PREFIX_TABLE (PREFIX_0F3830) },
6909     { PREFIX_TABLE (PREFIX_0F3831) },
6910     { PREFIX_TABLE (PREFIX_0F3832) },
6911     { PREFIX_TABLE (PREFIX_0F3833) },
6912     { PREFIX_TABLE (PREFIX_0F3834) },
6913     { PREFIX_TABLE (PREFIX_0F3835) },
6914     { Bad_Opcode },
6915     { PREFIX_TABLE (PREFIX_0F3837) },
6916     /* 38 */
6917     { PREFIX_TABLE (PREFIX_0F3838) },
6918     { PREFIX_TABLE (PREFIX_0F3839) },
6919     { PREFIX_TABLE (PREFIX_0F383A) },
6920     { PREFIX_TABLE (PREFIX_0F383B) },
6921     { PREFIX_TABLE (PREFIX_0F383C) },
6922     { PREFIX_TABLE (PREFIX_0F383D) },
6923     { PREFIX_TABLE (PREFIX_0F383E) },
6924     { PREFIX_TABLE (PREFIX_0F383F) },
6925     /* 40 */
6926     { PREFIX_TABLE (PREFIX_0F3840) },
6927     { PREFIX_TABLE (PREFIX_0F3841) },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     /* 48 */
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     /* 50 */
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* 58 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 60 */
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* 68 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* 70 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 78 */
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* 80 */
6998     { PREFIX_TABLE (PREFIX_0F3880) },
6999     { PREFIX_TABLE (PREFIX_0F3881) },
7000     { PREFIX_TABLE (PREFIX_0F3882) },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 88 */
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 90 */
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* 98 */
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* a0 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* a8 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* b0 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* b8 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* c0 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* c8 */
7079     { PREFIX_TABLE (PREFIX_0F38C8) },
7080     { PREFIX_TABLE (PREFIX_0F38C9) },
7081     { PREFIX_TABLE (PREFIX_0F38CA) },
7082     { PREFIX_TABLE (PREFIX_0F38CB) },
7083     { PREFIX_TABLE (PREFIX_0F38CC) },
7084     { PREFIX_TABLE (PREFIX_0F38CD) },
7085     { Bad_Opcode },
7086     { PREFIX_TABLE (PREFIX_0F38CF) },
7087     /* d0 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* d8 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { PREFIX_TABLE (PREFIX_0F38DB) },
7101     { PREFIX_TABLE (PREFIX_0F38DC) },
7102     { PREFIX_TABLE (PREFIX_0F38DD) },
7103     { PREFIX_TABLE (PREFIX_0F38DE) },
7104     { PREFIX_TABLE (PREFIX_0F38DF) },
7105     /* e0 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* e8 */
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* f0 */
7124     { PREFIX_TABLE (PREFIX_0F38F0) },
7125     { PREFIX_TABLE (PREFIX_0F38F1) },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { PREFIX_TABLE (PREFIX_0F38F5) },
7130     { PREFIX_TABLE (PREFIX_0F38F6) },
7131     { Bad_Opcode },
7132     /* f8 */
7133     { PREFIX_TABLE (PREFIX_0F38F8) },
7134     { PREFIX_TABLE (PREFIX_0F38F9) },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141   },
7142   /* THREE_BYTE_0F3A */
7143   {
7144     /* 00 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* 08 */
7154     { PREFIX_TABLE (PREFIX_0F3A08) },
7155     { PREFIX_TABLE (PREFIX_0F3A09) },
7156     { PREFIX_TABLE (PREFIX_0F3A0A) },
7157     { PREFIX_TABLE (PREFIX_0F3A0B) },
7158     { PREFIX_TABLE (PREFIX_0F3A0C) },
7159     { PREFIX_TABLE (PREFIX_0F3A0D) },
7160     { PREFIX_TABLE (PREFIX_0F3A0E) },
7161     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7162     /* 10 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { PREFIX_TABLE (PREFIX_0F3A14) },
7168     { PREFIX_TABLE (PREFIX_0F3A15) },
7169     { PREFIX_TABLE (PREFIX_0F3A16) },
7170     { PREFIX_TABLE (PREFIX_0F3A17) },
7171     /* 18 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* 20 */
7181     { PREFIX_TABLE (PREFIX_0F3A20) },
7182     { PREFIX_TABLE (PREFIX_0F3A21) },
7183     { PREFIX_TABLE (PREFIX_0F3A22) },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* 28 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* 30 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* 38 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* 40 */
7217     { PREFIX_TABLE (PREFIX_0F3A40) },
7218     { PREFIX_TABLE (PREFIX_0F3A41) },
7219     { PREFIX_TABLE (PREFIX_0F3A42) },
7220     { Bad_Opcode },
7221     { PREFIX_TABLE (PREFIX_0F3A44) },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* 48 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* 50 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* 58 */
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* 60 */
7253     { PREFIX_TABLE (PREFIX_0F3A60) },
7254     { PREFIX_TABLE (PREFIX_0F3A61) },
7255     { PREFIX_TABLE (PREFIX_0F3A62) },
7256     { PREFIX_TABLE (PREFIX_0F3A63) },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* 68 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* 70 */
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* 78 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 80 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 88 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 90 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* 98 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* a0 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* a8 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* b0 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* b8 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* c0 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* c8 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { PREFIX_TABLE (PREFIX_0F3ACC) },
7375     { Bad_Opcode },
7376     { PREFIX_TABLE (PREFIX_0F3ACE) },
7377     { PREFIX_TABLE (PREFIX_0F3ACF) },
7378     /* d0 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* d8 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { PREFIX_TABLE (PREFIX_0F3ADF) },
7396     /* e0 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* e8 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* f0 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* f8 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432   },
7433 };
7434
7435 static const struct dis386 xop_table[][256] = {
7436   /* XOP_08 */
7437   {
7438     /* 00 */
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     /* 08 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     /* 10 */
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     /* 18 */
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     /* 20 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     /* 28 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     /* 30 */
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     /* 38 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* 40 */
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     /* 48 */
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     /* 50 */
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     /* 58 */
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     /* 60 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* 68 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 70 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 78 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     /* 80 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7589     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7590     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7591     /* 88 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7599     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7600     /* 90 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7607     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7608     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7609     /* 98 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7617     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7618     /* a0 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7622     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7626     { Bad_Opcode },
7627     /* a8 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     /* b0 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7644     { Bad_Opcode },
7645     /* b8 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     /* c0 */
7655     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7656     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7657     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7658     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     /* c8 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7669     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7670     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7671     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7672     /* d0 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     /* d8 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* e0 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     /* e8 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7705     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7706     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7707     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7708     /* f0 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     /* f8 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726   },
7727   /* XOP_09 */
7728   {
7729     /* 00 */
7730     { Bad_Opcode },
7731     { REG_TABLE (REG_XOP_TBM_01) },
7732     { REG_TABLE (REG_XOP_TBM_02) },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     /* 08 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     /* 10 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { REG_TABLE (REG_XOP_LWPCB) },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* 18 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     /* 20 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* 28 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* 30 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* 38 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* 40 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* 48 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* 50 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* 58 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* 60 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     /* 68 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 70 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     /* 78 */
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 80 */
7874     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7875     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7876     { "vfrczss",        { XM, EXd }, 0 },
7877     { "vfrczsd",        { XM, EXq }, 0 },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     /* 88 */
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     /* 90 */
7892     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7893     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7894     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7895     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7896     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7897     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7898     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7899     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7900     /* 98 */
7901     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7902     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7903     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7904     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     /* a0 */
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* a8 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* b0 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* b8 */
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* c0 */
7946     { Bad_Opcode },
7947     { "vphaddbw",       { XM, EXxmm }, 0 },
7948     { "vphaddbd",       { XM, EXxmm }, 0 },
7949     { "vphaddbq",       { XM, EXxmm }, 0 },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { "vphaddwd",       { XM, EXxmm }, 0 },
7953     { "vphaddwq",       { XM, EXxmm }, 0 },
7954     /* c8 */
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { "vphadddq",       { XM, EXxmm }, 0 },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     /* d0 */
7964     { Bad_Opcode },
7965     { "vphaddubw",      { XM, EXxmm }, 0 },
7966     { "vphaddubd",      { XM, EXxmm }, 0 },
7967     { "vphaddubq",      { XM, EXxmm }, 0 },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { "vphadduwd",      { XM, EXxmm }, 0 },
7971     { "vphadduwq",      { XM, EXxmm }, 0 },
7972     /* d8 */
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { "vphaddudq",      { XM, EXxmm }, 0 },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* e0 */
7982     { Bad_Opcode },
7983     { "vphsubbw",       { XM, EXxmm }, 0 },
7984     { "vphsubwd",       { XM, EXxmm }, 0 },
7985     { "vphsubdq",       { XM, EXxmm }, 0 },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* e8 */
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* f0 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     /* f8 */
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017   },
8018   /* XOP_0A */
8019   {
8020     /* 00 */
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     /* 08 */
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     /* 10 */
8039     { "bextrS", { Gdq, Edq, Id }, 0 },
8040     { Bad_Opcode },
8041     { REG_TABLE (REG_XOP_LWP) },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* 18 */
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     /* 20 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* 28 */
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     /* 30 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* 38 */
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     /* 40 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     /* 48 */
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     /* 50 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* 58 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* 60 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     /* 68 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     /* 70 */
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     /* 78 */
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* 80 */
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     /* 88 */
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     /* 90 */
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     /* 98 */
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     /* a0 */
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     /* a8 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* b0 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* b8 */
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* c0 */
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     /* c8 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* d0 */
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     /* d8 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* e0 */
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* e8 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* f0 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     /* f8 */
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308   },
8309 };
8310
8311 static const struct dis386 vex_table[][256] = {
8312   /* VEX_0F */
8313   {
8314     /* 00 */
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* 08 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* 10 */
8333     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8334     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8335     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8336     { MOD_TABLE (MOD_VEX_0F13) },
8337     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8338     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8339     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8340     { MOD_TABLE (MOD_VEX_0F17) },
8341     /* 18 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* 20 */
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     /* 28 */
8360     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8361     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8362     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8363     { MOD_TABLE (MOD_VEX_0F2B) },
8364     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8365     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8366     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8367     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8368     /* 30 */
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     /* 38 */
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     /* 40 */
8387     { Bad_Opcode },
8388     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8389     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8390     { Bad_Opcode },
8391     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8392     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8393     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8394     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8395     /* 48 */
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8399     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     /* 50 */
8405     { MOD_TABLE (MOD_VEX_0F50) },
8406     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8407     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8408     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8409     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8410     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8411     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8412     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8413     /* 58 */
8414     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8415     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8416     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8417     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8418     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8419     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8422     /* 60 */
8423     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8427     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8431     /* 68 */
8432     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8433     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8434     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8435     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8436     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8437     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8438     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8439     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8440     /* 70 */
8441     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8442     { REG_TABLE (REG_VEX_0F71) },
8443     { REG_TABLE (REG_VEX_0F72) },
8444     { REG_TABLE (REG_VEX_0F73) },
8445     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8446     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8447     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8449     /* 78 */
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8457     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8458     /* 80 */
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     /* 88 */
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     /* 90 */
8477     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8478     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8479     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8480     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     /* 98 */
8486     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     /* a0 */
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     /* a8 */
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { REG_TABLE (REG_VEX_0FAE) },
8511     { Bad_Opcode },
8512     /* b0 */
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     /* b8 */
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     /* c0 */
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8534     { Bad_Opcode },
8535     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8536     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8537     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8538     { Bad_Opcode },
8539     /* c8 */
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     /* d0 */
8549     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8550     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8551     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8552     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8553     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8557     /* d8 */
8558     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8559     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8560     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8561     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8562     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8566     /* e0 */
8567     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8569     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8570     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8571     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8575     /* e8 */
8576     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8577     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8578     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8579     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8580     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8584     /* f0 */
8585     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8586     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8587     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8589     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8592     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8593     /* f8 */
8594     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8595     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8596     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8597     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8598     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8599     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8600     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8601     { Bad_Opcode },
8602   },
8603   /* VEX_0F38 */
8604   {
8605     /* 00 */
8606     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8614     /* 08 */
8615     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8623     /* 10 */
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8632     /* 18 */
8633     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8636     { Bad_Opcode },
8637     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8640     { Bad_Opcode },
8641     /* 20 */
8642     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     /* 28 */
8651     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8659     /* 30 */
8660     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8668     /* 38 */
8669     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8677     /* 40 */
8678     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8686     /* 48 */
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     /* 50 */
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     /* 58 */
8705     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     /* 60 */
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     /* 68 */
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     /* 70 */
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     /* 78 */
8741     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     /* 80 */
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     /* 88 */
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8764     { Bad_Opcode },
8765     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8766     { Bad_Opcode },
8767     /* 90 */
8768     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8776     /* 98 */
8777     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8785     /* a0 */
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8794     /* a8 */
8795     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8803     /* b0 */
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8812     /* b8 */
8813     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8821     /* c0 */
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     /* c8 */
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8839     /* d0 */
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     /* d8 */
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8854     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8857     /* e0 */
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     /* e8 */
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     /* f0 */
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8879     { REG_TABLE (REG_VEX_0F38F3) },
8880     { Bad_Opcode },
8881     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8884     /* f8 */
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893   },
8894   /* VEX_0F3A */
8895   {
8896     /* 00 */
8897     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8900     { Bad_Opcode },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8904     { Bad_Opcode },
8905     /* 08 */
8906     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8914     /* 10 */
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8923     /* 18 */
8924     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     /* 20 */
8933     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     /* 28 */
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     /* 30 */
8951     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     /* 38 */
8960     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     /* 40 */
8969     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8972     { Bad_Opcode },
8973     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8974     { Bad_Opcode },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8976     { Bad_Opcode },
8977     /* 48 */
8978     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     /* 50 */
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     /* 58 */
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9004     /* 60 */
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     /* 68 */
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9022     /* 70 */
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     /* 78 */
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9040     /* 80 */
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     /* 88 */
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     /* 90 */
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     /* 98 */
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     /* a0 */
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     /* a8 */
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     /* b0 */
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     /* b8 */
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     /* c0 */
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     /* c8 */
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9129     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9130     /* d0 */
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     /* d8 */
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9148     /* e0 */
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     /* e8 */
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     /* f0 */
9167     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     /* f8 */
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184   },
9185 };
9186
9187 #include "i386-dis-evex.h"
9188
9189 static const struct dis386 vex_len_table[][2] = {
9190   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9191   {
9192     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9193   },
9194
9195   /* VEX_LEN_0F12_P_0_M_1 */
9196   {
9197     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9198   },
9199
9200   /* VEX_LEN_0F13_M_0 */
9201   {
9202     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9203   },
9204
9205   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9206   {
9207     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9208   },
9209
9210   /* VEX_LEN_0F16_P_0_M_1 */
9211   {
9212     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9213   },
9214
9215   /* VEX_LEN_0F17_M_0 */
9216   {
9217     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9218   },
9219
9220   /* VEX_LEN_0F41_P_0 */
9221   {
9222     { Bad_Opcode },
9223     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9224   },
9225   /* VEX_LEN_0F41_P_2 */
9226   {
9227     { Bad_Opcode },
9228     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9229   },
9230   /* VEX_LEN_0F42_P_0 */
9231   {
9232     { Bad_Opcode },
9233     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9234   },
9235   /* VEX_LEN_0F42_P_2 */
9236   {
9237     { Bad_Opcode },
9238     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9239   },
9240   /* VEX_LEN_0F44_P_0 */
9241   {
9242     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9243   },
9244   /* VEX_LEN_0F44_P_2 */
9245   {
9246     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9247   },
9248   /* VEX_LEN_0F45_P_0 */
9249   {
9250     { Bad_Opcode },
9251     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9252   },
9253   /* VEX_LEN_0F45_P_2 */
9254   {
9255     { Bad_Opcode },
9256     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9257   },
9258   /* VEX_LEN_0F46_P_0 */
9259   {
9260     { Bad_Opcode },
9261     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9262   },
9263   /* VEX_LEN_0F46_P_2 */
9264   {
9265     { Bad_Opcode },
9266     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9267   },
9268   /* VEX_LEN_0F47_P_0 */
9269   {
9270     { Bad_Opcode },
9271     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9272   },
9273   /* VEX_LEN_0F47_P_2 */
9274   {
9275     { Bad_Opcode },
9276     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9277   },
9278   /* VEX_LEN_0F4A_P_0 */
9279   {
9280     { Bad_Opcode },
9281     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9282   },
9283   /* VEX_LEN_0F4A_P_2 */
9284   {
9285     { Bad_Opcode },
9286     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9287   },
9288   /* VEX_LEN_0F4B_P_0 */
9289   {
9290     { Bad_Opcode },
9291     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9292   },
9293   /* VEX_LEN_0F4B_P_2 */
9294   {
9295     { Bad_Opcode },
9296     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9297   },
9298
9299   /* VEX_LEN_0F6E_P_2 */
9300   {
9301     { "vmovK",          { XMScalar, Edq }, 0 },
9302   },
9303
9304   /* VEX_LEN_0F77_P_1 */
9305   {
9306     { "vzeroupper",     { XX }, 0 },
9307     { "vzeroall",       { XX }, 0 },
9308   },
9309
9310   /* VEX_LEN_0F7E_P_1 */
9311   {
9312     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9313   },
9314
9315   /* VEX_LEN_0F7E_P_2 */
9316   {
9317     { "vmovK",          { Edq, XMScalar }, 0 },
9318   },
9319
9320   /* VEX_LEN_0F90_P_0 */
9321   {
9322     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9323   },
9324
9325   /* VEX_LEN_0F90_P_2 */
9326   {
9327     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9328   },
9329
9330   /* VEX_LEN_0F91_P_0 */
9331   {
9332     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9333   },
9334
9335   /* VEX_LEN_0F91_P_2 */
9336   {
9337     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9338   },
9339
9340   /* VEX_LEN_0F92_P_0 */
9341   {
9342     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9343   },
9344
9345   /* VEX_LEN_0F92_P_2 */
9346   {
9347     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9348   },
9349
9350   /* VEX_LEN_0F92_P_3 */
9351   {
9352     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9353   },
9354
9355   /* VEX_LEN_0F93_P_0 */
9356   {
9357     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9358   },
9359
9360   /* VEX_LEN_0F93_P_2 */
9361   {
9362     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9363   },
9364
9365   /* VEX_LEN_0F93_P_3 */
9366   {
9367     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9368   },
9369
9370   /* VEX_LEN_0F98_P_0 */
9371   {
9372     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9373   },
9374
9375   /* VEX_LEN_0F98_P_2 */
9376   {
9377     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9378   },
9379
9380   /* VEX_LEN_0F99_P_0 */
9381   {
9382     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9383   },
9384
9385   /* VEX_LEN_0F99_P_2 */
9386   {
9387     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9388   },
9389
9390   /* VEX_LEN_0FAE_R_2_M_0 */
9391   {
9392     { "vldmxcsr",       { Md }, 0 },
9393   },
9394
9395   /* VEX_LEN_0FAE_R_3_M_0 */
9396   {
9397     { "vstmxcsr",       { Md }, 0 },
9398   },
9399
9400   /* VEX_LEN_0FC4_P_2 */
9401   {
9402     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9403   },
9404
9405   /* VEX_LEN_0FC5_P_2 */
9406   {
9407     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9408   },
9409
9410   /* VEX_LEN_0FD6_P_2 */
9411   {
9412     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9413   },
9414
9415   /* VEX_LEN_0FF7_P_2 */
9416   {
9417     { "vmaskmovdqu",    { XM, XS }, 0 },
9418   },
9419
9420   /* VEX_LEN_0F3816_P_2 */
9421   {
9422     { Bad_Opcode },
9423     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9424   },
9425
9426   /* VEX_LEN_0F3819_P_2 */
9427   {
9428     { Bad_Opcode },
9429     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9430   },
9431
9432   /* VEX_LEN_0F381A_P_2_M_0 */
9433   {
9434     { Bad_Opcode },
9435     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9436   },
9437
9438   /* VEX_LEN_0F3836_P_2 */
9439   {
9440     { Bad_Opcode },
9441     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9442   },
9443
9444   /* VEX_LEN_0F3841_P_2 */
9445   {
9446     { "vphminposuw",    { XM, EXx }, 0 },
9447   },
9448
9449   /* VEX_LEN_0F385A_P_2_M_0 */
9450   {
9451     { Bad_Opcode },
9452     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9453   },
9454
9455   /* VEX_LEN_0F38DB_P_2 */
9456   {
9457     { "vaesimc",        { XM, EXx }, 0 },
9458   },
9459
9460   /* VEX_LEN_0F38F2_P_0 */
9461   {
9462     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9463   },
9464
9465   /* VEX_LEN_0F38F3_R_1_P_0 */
9466   {
9467     { "blsrS",          { VexGdq, Edq }, 0 },
9468   },
9469
9470   /* VEX_LEN_0F38F3_R_2_P_0 */
9471   {
9472     { "blsmskS",        { VexGdq, Edq }, 0 },
9473   },
9474
9475   /* VEX_LEN_0F38F3_R_3_P_0 */
9476   {
9477     { "blsiS",          { VexGdq, Edq }, 0 },
9478   },
9479
9480   /* VEX_LEN_0F38F5_P_0 */
9481   {
9482     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9483   },
9484
9485   /* VEX_LEN_0F38F5_P_1 */
9486   {
9487     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9488   },
9489
9490   /* VEX_LEN_0F38F5_P_3 */
9491   {
9492     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9493   },
9494
9495   /* VEX_LEN_0F38F6_P_3 */
9496   {
9497     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9498   },
9499
9500   /* VEX_LEN_0F38F7_P_0 */
9501   {
9502     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9503   },
9504
9505   /* VEX_LEN_0F38F7_P_1 */
9506   {
9507     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9508   },
9509
9510   /* VEX_LEN_0F38F7_P_2 */
9511   {
9512     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9513   },
9514
9515   /* VEX_LEN_0F38F7_P_3 */
9516   {
9517     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9518   },
9519
9520   /* VEX_LEN_0F3A00_P_2 */
9521   {
9522     { Bad_Opcode },
9523     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9524   },
9525
9526   /* VEX_LEN_0F3A01_P_2 */
9527   {
9528     { Bad_Opcode },
9529     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9530   },
9531
9532   /* VEX_LEN_0F3A06_P_2 */
9533   {
9534     { Bad_Opcode },
9535     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9536   },
9537
9538   /* VEX_LEN_0F3A14_P_2 */
9539   {
9540     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9541   },
9542
9543   /* VEX_LEN_0F3A15_P_2 */
9544   {
9545     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9546   },
9547
9548   /* VEX_LEN_0F3A16_P_2  */
9549   {
9550     { "vpextrK",        { Edq, XM, Ib }, 0 },
9551   },
9552
9553   /* VEX_LEN_0F3A17_P_2 */
9554   {
9555     { "vextractps",     { Edqd, XM, Ib }, 0 },
9556   },
9557
9558   /* VEX_LEN_0F3A18_P_2 */
9559   {
9560     { Bad_Opcode },
9561     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9562   },
9563
9564   /* VEX_LEN_0F3A19_P_2 */
9565   {
9566     { Bad_Opcode },
9567     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9568   },
9569
9570   /* VEX_LEN_0F3A20_P_2 */
9571   {
9572     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9573   },
9574
9575   /* VEX_LEN_0F3A21_P_2 */
9576   {
9577     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9578   },
9579
9580   /* VEX_LEN_0F3A22_P_2 */
9581   {
9582     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9583   },
9584
9585   /* VEX_LEN_0F3A30_P_2 */
9586   {
9587     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9588   },
9589
9590   /* VEX_LEN_0F3A31_P_2 */
9591   {
9592     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9593   },
9594
9595   /* VEX_LEN_0F3A32_P_2 */
9596   {
9597     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9598   },
9599
9600   /* VEX_LEN_0F3A33_P_2 */
9601   {
9602     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9603   },
9604
9605   /* VEX_LEN_0F3A38_P_2 */
9606   {
9607     { Bad_Opcode },
9608     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9609   },
9610
9611   /* VEX_LEN_0F3A39_P_2 */
9612   {
9613     { Bad_Opcode },
9614     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9615   },
9616
9617   /* VEX_LEN_0F3A41_P_2 */
9618   {
9619     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9620   },
9621
9622   /* VEX_LEN_0F3A46_P_2 */
9623   {
9624     { Bad_Opcode },
9625     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9626   },
9627
9628   /* VEX_LEN_0F3A60_P_2 */
9629   {
9630     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9631   },
9632
9633   /* VEX_LEN_0F3A61_P_2 */
9634   {
9635     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9636   },
9637
9638   /* VEX_LEN_0F3A62_P_2 */
9639   {
9640     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9641   },
9642
9643   /* VEX_LEN_0F3A63_P_2 */
9644   {
9645     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9646   },
9647
9648   /* VEX_LEN_0F3A6A_P_2 */
9649   {
9650     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9651   },
9652
9653   /* VEX_LEN_0F3A6B_P_2 */
9654   {
9655     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9656   },
9657
9658   /* VEX_LEN_0F3A6E_P_2 */
9659   {
9660     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9661   },
9662
9663   /* VEX_LEN_0F3A6F_P_2 */
9664   {
9665     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9666   },
9667
9668   /* VEX_LEN_0F3A7A_P_2 */
9669   {
9670     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9671   },
9672
9673   /* VEX_LEN_0F3A7B_P_2 */
9674   {
9675     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9676   },
9677
9678   /* VEX_LEN_0F3A7E_P_2 */
9679   {
9680     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9681   },
9682
9683   /* VEX_LEN_0F3A7F_P_2 */
9684   {
9685     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9686   },
9687
9688   /* VEX_LEN_0F3ADF_P_2 */
9689   {
9690     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9691   },
9692
9693   /* VEX_LEN_0F3AF0_P_3 */
9694   {
9695     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9696   },
9697
9698   /* VEX_LEN_0FXOP_08_CC */
9699   {
9700      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9701   },
9702
9703   /* VEX_LEN_0FXOP_08_CD */
9704   {
9705      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9706   },
9707
9708   /* VEX_LEN_0FXOP_08_CE */
9709   {
9710      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9711   },
9712
9713   /* VEX_LEN_0FXOP_08_CF */
9714   {
9715      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9716   },
9717
9718   /* VEX_LEN_0FXOP_08_EC */
9719   {
9720      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9721   },
9722
9723   /* VEX_LEN_0FXOP_08_ED */
9724   {
9725      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9726   },
9727
9728   /* VEX_LEN_0FXOP_08_EE */
9729   {
9730      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9731   },
9732
9733   /* VEX_LEN_0FXOP_08_EF */
9734   {
9735      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9736   },
9737
9738   /* VEX_LEN_0FXOP_09_80 */
9739   {
9740     { "vfrczps",        { XM, EXxmm }, 0 },
9741     { "vfrczps",        { XM, EXymmq }, 0 },
9742   },
9743
9744   /* VEX_LEN_0FXOP_09_81 */
9745   {
9746     { "vfrczpd",        { XM, EXxmm }, 0 },
9747     { "vfrczpd",        { XM, EXymmq }, 0 },
9748   },
9749 };
9750
9751 #include "i386-dis-evex-len.h"
9752
9753 static const struct dis386 vex_w_table[][2] = {
9754   {
9755     /* VEX_W_0F41_P_0_LEN_1 */
9756     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9757     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9758   },
9759   {
9760     /* VEX_W_0F41_P_2_LEN_1 */
9761     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9762     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9763   },
9764   {
9765     /* VEX_W_0F42_P_0_LEN_1 */
9766     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9767     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9768   },
9769   {
9770     /* VEX_W_0F42_P_2_LEN_1 */
9771     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9772     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9773   },
9774   {
9775     /* VEX_W_0F44_P_0_LEN_0 */
9776     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9777     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9778   },
9779   {
9780     /* VEX_W_0F44_P_2_LEN_0 */
9781     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9782     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9783   },
9784   {
9785     /* VEX_W_0F45_P_0_LEN_1 */
9786     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9787     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9788   },
9789   {
9790     /* VEX_W_0F45_P_2_LEN_1 */
9791     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9792     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9793   },
9794   {
9795     /* VEX_W_0F46_P_0_LEN_1 */
9796     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9797     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9798   },
9799   {
9800     /* VEX_W_0F46_P_2_LEN_1 */
9801     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9802     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9803   },
9804   {
9805     /* VEX_W_0F47_P_0_LEN_1 */
9806     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9807     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9808   },
9809   {
9810     /* VEX_W_0F47_P_2_LEN_1 */
9811     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9812     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9813   },
9814   {
9815     /* VEX_W_0F4A_P_0_LEN_1 */
9816     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9817     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9818   },
9819   {
9820     /* VEX_W_0F4A_P_2_LEN_1 */
9821     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9822     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9823   },
9824   {
9825     /* VEX_W_0F4B_P_0_LEN_1 */
9826     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9827     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9828   },
9829   {
9830     /* VEX_W_0F4B_P_2_LEN_1 */
9831     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9832   },
9833   {
9834     /* VEX_W_0F90_P_0_LEN_0 */
9835     { "kmovw",          { MaskG, MaskE }, 0 },
9836     { "kmovq",          { MaskG, MaskE }, 0 },
9837   },
9838   {
9839     /* VEX_W_0F90_P_2_LEN_0 */
9840     { "kmovb",          { MaskG, MaskBDE }, 0 },
9841     { "kmovd",          { MaskG, MaskBDE }, 0 },
9842   },
9843   {
9844     /* VEX_W_0F91_P_0_LEN_0 */
9845     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9846     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9847   },
9848   {
9849     /* VEX_W_0F91_P_2_LEN_0 */
9850     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9851     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9852   },
9853   {
9854     /* VEX_W_0F92_P_0_LEN_0 */
9855     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9856   },
9857   {
9858     /* VEX_W_0F92_P_2_LEN_0 */
9859     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9860   },
9861   {
9862     /* VEX_W_0F93_P_0_LEN_0 */
9863     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9864   },
9865   {
9866     /* VEX_W_0F93_P_2_LEN_0 */
9867     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9868   },
9869   {
9870     /* VEX_W_0F98_P_0_LEN_0 */
9871     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9872     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9873   },
9874   {
9875     /* VEX_W_0F98_P_2_LEN_0 */
9876     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9877     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9878   },
9879   {
9880     /* VEX_W_0F99_P_0_LEN_0 */
9881     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9882     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9883   },
9884   {
9885     /* VEX_W_0F99_P_2_LEN_0 */
9886     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9887     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9888   },
9889   {
9890     /* VEX_W_0F380C_P_2  */
9891     { "vpermilps",      { XM, Vex, EXx }, 0 },
9892   },
9893   {
9894     /* VEX_W_0F380D_P_2  */
9895     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9896   },
9897   {
9898     /* VEX_W_0F380E_P_2  */
9899     { "vtestps",        { XM, EXx }, 0 },
9900   },
9901   {
9902     /* VEX_W_0F380F_P_2  */
9903     { "vtestpd",        { XM, EXx }, 0 },
9904   },
9905   {
9906     /* VEX_W_0F3816_P_2  */
9907     { "vpermps",        { XM, Vex, EXx }, 0 },
9908   },
9909   {
9910     /* VEX_W_0F3818_P_2 */
9911     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
9912   },
9913   {
9914     /* VEX_W_0F3819_P_2 */
9915     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
9916   },
9917   {
9918     /* VEX_W_0F381A_P_2_M_0 */
9919     { "vbroadcastf128", { XM, Mxmm }, 0 },
9920   },
9921   {
9922     /* VEX_W_0F382C_P_2_M_0 */
9923     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
9924   },
9925   {
9926     /* VEX_W_0F382D_P_2_M_0 */
9927     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
9928   },
9929   {
9930     /* VEX_W_0F382E_P_2_M_0 */
9931     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
9932   },
9933   {
9934     /* VEX_W_0F382F_P_2_M_0 */
9935     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
9936   },
9937   {
9938     /* VEX_W_0F3836_P_2  */
9939     { "vpermd",         { XM, Vex, EXx }, 0 },
9940   },
9941   {
9942     /* VEX_W_0F3846_P_2 */
9943     { "vpsravd",        { XM, Vex, EXx }, 0 },
9944   },
9945   {
9946     /* VEX_W_0F3858_P_2 */
9947     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
9948   },
9949   {
9950     /* VEX_W_0F3859_P_2 */
9951     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
9952   },
9953   {
9954     /* VEX_W_0F385A_P_2_M_0 */
9955     { "vbroadcasti128", { XM, Mxmm }, 0 },
9956   },
9957   {
9958     /* VEX_W_0F3878_P_2 */
9959     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
9960   },
9961   {
9962     /* VEX_W_0F3879_P_2 */
9963     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
9964   },
9965   {
9966     /* VEX_W_0F38CF_P_2 */
9967     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
9968   },
9969   {
9970     /* VEX_W_0F3A00_P_2 */
9971     { Bad_Opcode },
9972     { "vpermq",         { XM, EXx, Ib }, 0 },
9973   },
9974   {
9975     /* VEX_W_0F3A01_P_2 */
9976     { Bad_Opcode },
9977     { "vpermpd",        { XM, EXx, Ib }, 0 },
9978   },
9979   {
9980     /* VEX_W_0F3A02_P_2 */
9981     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
9982   },
9983   {
9984     /* VEX_W_0F3A04_P_2 */
9985     { "vpermilps",      { XM, EXx, Ib }, 0 },
9986   },
9987   {
9988     /* VEX_W_0F3A05_P_2 */
9989     { "vpermilpd",      { XM, EXx, Ib }, 0 },
9990   },
9991   {
9992     /* VEX_W_0F3A06_P_2 */
9993     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
9994   },
9995   {
9996     /* VEX_W_0F3A18_P_2 */
9997     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
9998   },
9999   {
10000     /* VEX_W_0F3A19_P_2 */
10001     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10002   },
10003   {
10004     /* VEX_W_0F3A30_P_2_LEN_0 */
10005     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10006     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10007   },
10008   {
10009     /* VEX_W_0F3A31_P_2_LEN_0 */
10010     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10011     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10012   },
10013   {
10014     /* VEX_W_0F3A32_P_2_LEN_0 */
10015     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10016     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10017   },
10018   {
10019     /* VEX_W_0F3A33_P_2_LEN_0 */
10020     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10021     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10022   },
10023   {
10024     /* VEX_W_0F3A38_P_2 */
10025     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10026   },
10027   {
10028     /* VEX_W_0F3A39_P_2 */
10029     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10030   },
10031   {
10032     /* VEX_W_0F3A46_P_2 */
10033     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10034   },
10035   {
10036     /* VEX_W_0F3A48_P_2 */
10037     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10038     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10039   },
10040   {
10041     /* VEX_W_0F3A49_P_2 */
10042     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10043     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10044   },
10045   {
10046     /* VEX_W_0F3A4A_P_2 */
10047     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10048   },
10049   {
10050     /* VEX_W_0F3A4B_P_2 */
10051     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10052   },
10053   {
10054     /* VEX_W_0F3A4C_P_2 */
10055     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10056   },
10057   {
10058     /* VEX_W_0F3ACE_P_2 */
10059     { Bad_Opcode },
10060     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10061   },
10062   {
10063     /* VEX_W_0F3ACF_P_2 */
10064     { Bad_Opcode },
10065     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10066   },
10067
10068 #include "i386-dis-evex-w.h"
10069 };
10070
10071 static const struct dis386 mod_table[][2] = {
10072   {
10073     /* MOD_8D */
10074     { "leaS",           { Gv, M }, 0 },
10075   },
10076   {
10077     /* MOD_C6_REG_7 */
10078     { Bad_Opcode },
10079     { RM_TABLE (RM_C6_REG_7) },
10080   },
10081   {
10082     /* MOD_C7_REG_7 */
10083     { Bad_Opcode },
10084     { RM_TABLE (RM_C7_REG_7) },
10085   },
10086   {
10087     /* MOD_FF_REG_3 */
10088     { "{l|}call^", { indirEp }, 0 },
10089   },
10090   {
10091     /* MOD_FF_REG_5 */
10092     { "{l|}jmp^", { indirEp }, 0 },
10093   },
10094   {
10095     /* MOD_0F01_REG_0 */
10096     { X86_64_TABLE (X86_64_0F01_REG_0) },
10097     { RM_TABLE (RM_0F01_REG_0) },
10098   },
10099   {
10100     /* MOD_0F01_REG_1 */
10101     { X86_64_TABLE (X86_64_0F01_REG_1) },
10102     { RM_TABLE (RM_0F01_REG_1) },
10103   },
10104   {
10105     /* MOD_0F01_REG_2 */
10106     { X86_64_TABLE (X86_64_0F01_REG_2) },
10107     { RM_TABLE (RM_0F01_REG_2) },
10108   },
10109   {
10110     /* MOD_0F01_REG_3 */
10111     { X86_64_TABLE (X86_64_0F01_REG_3) },
10112     { RM_TABLE (RM_0F01_REG_3) },
10113   },
10114   {
10115     /* MOD_0F01_REG_5 */
10116     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10117     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10118   },
10119   {
10120     /* MOD_0F01_REG_7 */
10121     { "invlpg",         { Mb }, 0 },
10122     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10123   },
10124   {
10125     /* MOD_0F12_PREFIX_0 */
10126     { "movlpX",         { XM, EXq }, 0 },
10127     { "movhlps",        { XM, EXq }, 0 },
10128   },
10129   {
10130     /* MOD_0F12_PREFIX_2 */
10131     { "movlpX", { XM, EXq }, 0 },
10132   },
10133   {
10134     /* MOD_0F13 */
10135     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10136   },
10137   {
10138     /* MOD_0F16_PREFIX_0 */
10139     { "movhpX",         { XM, EXq }, 0 },
10140     { "movlhps",        { XM, EXq }, 0 },
10141   },
10142   {
10143     /* MOD_0F16_PREFIX_2 */
10144     { "movhpX", { XM, EXq }, 0 },
10145   },
10146   {
10147     /* MOD_0F17 */
10148     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10149   },
10150   {
10151     /* MOD_0F18_REG_0 */
10152     { "prefetchnta",    { Mb }, 0 },
10153   },
10154   {
10155     /* MOD_0F18_REG_1 */
10156     { "prefetcht0",     { Mb }, 0 },
10157   },
10158   {
10159     /* MOD_0F18_REG_2 */
10160     { "prefetcht1",     { Mb }, 0 },
10161   },
10162   {
10163     /* MOD_0F18_REG_3 */
10164     { "prefetcht2",     { Mb }, 0 },
10165   },
10166   {
10167     /* MOD_0F18_REG_4 */
10168     { "nop/reserved",   { Mb }, 0 },
10169   },
10170   {
10171     /* MOD_0F18_REG_5 */
10172     { "nop/reserved",   { Mb }, 0 },
10173   },
10174   {
10175     /* MOD_0F18_REG_6 */
10176     { "nop/reserved",   { Mb }, 0 },
10177   },
10178   {
10179     /* MOD_0F18_REG_7 */
10180     { "nop/reserved",   { Mb }, 0 },
10181   },
10182   {
10183     /* MOD_0F1A_PREFIX_0 */
10184     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10185     { "nopQ",           { Ev }, 0 },
10186   },
10187   {
10188     /* MOD_0F1B_PREFIX_0 */
10189     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10190     { "nopQ",           { Ev }, 0 },
10191   },
10192   {
10193     /* MOD_0F1B_PREFIX_1 */
10194     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10195     { "nopQ",           { Ev }, 0 },
10196   },
10197   {
10198     /* MOD_0F1C_PREFIX_0 */
10199     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10200     { "nopQ",           { Ev }, 0 },
10201   },
10202   {
10203     /* MOD_0F1E_PREFIX_1 */
10204     { "nopQ",           { Ev }, 0 },
10205     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10206   },
10207   {
10208     /* MOD_0F24 */
10209     { Bad_Opcode },
10210     { "movL",           { Rd, Td }, 0 },
10211   },
10212   {
10213     /* MOD_0F26 */
10214     { Bad_Opcode },
10215     { "movL",           { Td, Rd }, 0 },
10216   },
10217   {
10218     /* MOD_0F2B_PREFIX_0 */
10219     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10220   },
10221   {
10222     /* MOD_0F2B_PREFIX_1 */
10223     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10224   },
10225   {
10226     /* MOD_0F2B_PREFIX_2 */
10227     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10228   },
10229   {
10230     /* MOD_0F2B_PREFIX_3 */
10231     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10232   },
10233   {
10234     /* MOD_0F50 */
10235     { Bad_Opcode },
10236     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10237   },
10238   {
10239     /* MOD_0F71_REG_2 */
10240     { Bad_Opcode },
10241     { "psrlw",          { MS, Ib }, 0 },
10242   },
10243   {
10244     /* MOD_0F71_REG_4 */
10245     { Bad_Opcode },
10246     { "psraw",          { MS, Ib }, 0 },
10247   },
10248   {
10249     /* MOD_0F71_REG_6 */
10250     { Bad_Opcode },
10251     { "psllw",          { MS, Ib }, 0 },
10252   },
10253   {
10254     /* MOD_0F72_REG_2 */
10255     { Bad_Opcode },
10256     { "psrld",          { MS, Ib }, 0 },
10257   },
10258   {
10259     /* MOD_0F72_REG_4 */
10260     { Bad_Opcode },
10261     { "psrad",          { MS, Ib }, 0 },
10262   },
10263   {
10264     /* MOD_0F72_REG_6 */
10265     { Bad_Opcode },
10266     { "pslld",          { MS, Ib }, 0 },
10267   },
10268   {
10269     /* MOD_0F73_REG_2 */
10270     { Bad_Opcode },
10271     { "psrlq",          { MS, Ib }, 0 },
10272   },
10273   {
10274     /* MOD_0F73_REG_3 */
10275     { Bad_Opcode },
10276     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10277   },
10278   {
10279     /* MOD_0F73_REG_6 */
10280     { Bad_Opcode },
10281     { "psllq",          { MS, Ib }, 0 },
10282   },
10283   {
10284     /* MOD_0F73_REG_7 */
10285     { Bad_Opcode },
10286     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10287   },
10288   {
10289     /* MOD_0FAE_REG_0 */
10290     { "fxsave",         { FXSAVE }, 0 },
10291     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10292   },
10293   {
10294     /* MOD_0FAE_REG_1 */
10295     { "fxrstor",        { FXSAVE }, 0 },
10296     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10297   },
10298   {
10299     /* MOD_0FAE_REG_2 */
10300     { "ldmxcsr",        { Md }, 0 },
10301     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10302   },
10303   {
10304     /* MOD_0FAE_REG_3 */
10305     { "stmxcsr",        { Md }, 0 },
10306     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10307   },
10308   {
10309     /* MOD_0FAE_REG_4 */
10310     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10311     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10312   },
10313   {
10314     /* MOD_0FAE_REG_5 */
10315     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10316     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10317   },
10318   {
10319     /* MOD_0FAE_REG_6 */
10320     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10321     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10322   },
10323   {
10324     /* MOD_0FAE_REG_7 */
10325     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10326     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10327   },
10328   {
10329     /* MOD_0FB2 */
10330     { "lssS",           { Gv, Mp }, 0 },
10331   },
10332   {
10333     /* MOD_0FB4 */
10334     { "lfsS",           { Gv, Mp }, 0 },
10335   },
10336   {
10337     /* MOD_0FB5 */
10338     { "lgsS",           { Gv, Mp }, 0 },
10339   },
10340   {
10341     /* MOD_0FC3 */
10342     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10343   },
10344   {
10345     /* MOD_0FC7_REG_3 */
10346     { "xrstors",        { FXSAVE }, 0 },
10347   },
10348   {
10349     /* MOD_0FC7_REG_4 */
10350     { "xsavec",         { FXSAVE }, 0 },
10351   },
10352   {
10353     /* MOD_0FC7_REG_5 */
10354     { "xsaves",         { FXSAVE }, 0 },
10355   },
10356   {
10357     /* MOD_0FC7_REG_6 */
10358     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10359     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10360   },
10361   {
10362     /* MOD_0FC7_REG_7 */
10363     { "vmptrst",        { Mq }, 0 },
10364     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10365   },
10366   {
10367     /* MOD_0FD7 */
10368     { Bad_Opcode },
10369     { "pmovmskb",       { Gdq, MS }, 0 },
10370   },
10371   {
10372     /* MOD_0FE7_PREFIX_2 */
10373     { "movntdq",        { Mx, XM }, 0 },
10374   },
10375   {
10376     /* MOD_0FF0_PREFIX_3 */
10377     { "lddqu",          { XM, M }, 0 },
10378   },
10379   {
10380     /* MOD_0F382A_PREFIX_2 */
10381     { "movntdqa",       { XM, Mx }, 0 },
10382   },
10383   {
10384     /* MOD_0F38F5_PREFIX_2 */
10385     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10386   },
10387   {
10388     /* MOD_0F38F6_PREFIX_0 */
10389     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10390   },
10391   {
10392     /* MOD_0F38F8_PREFIX_1 */
10393     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10394   },
10395   {
10396     /* MOD_0F38F8_PREFIX_2 */
10397     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10398   },
10399   {
10400     /* MOD_0F38F8_PREFIX_3 */
10401     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10402   },
10403   {
10404     /* MOD_0F38F9_PREFIX_0 */
10405     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10406   },
10407   {
10408     /* MOD_62_32BIT */
10409     { "bound{S|}",      { Gv, Ma }, 0 },
10410     { EVEX_TABLE (EVEX_0F) },
10411   },
10412   {
10413     /* MOD_C4_32BIT */
10414     { "lesS",           { Gv, Mp }, 0 },
10415     { VEX_C4_TABLE (VEX_0F) },
10416   },
10417   {
10418     /* MOD_C5_32BIT */
10419     { "ldsS",           { Gv, Mp }, 0 },
10420     { VEX_C5_TABLE (VEX_0F) },
10421   },
10422   {
10423     /* MOD_VEX_0F12_PREFIX_0 */
10424     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10425     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10426   },
10427   {
10428     /* MOD_VEX_0F12_PREFIX_2 */
10429     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10430   },
10431   {
10432     /* MOD_VEX_0F13 */
10433     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10434   },
10435   {
10436     /* MOD_VEX_0F16_PREFIX_0 */
10437     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10438     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10439   },
10440   {
10441     /* MOD_VEX_0F16_PREFIX_2 */
10442     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10443   },
10444   {
10445     /* MOD_VEX_0F17 */
10446     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10447   },
10448   {
10449     /* MOD_VEX_0F2B */
10450     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10451   },
10452   {
10453     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10454     { Bad_Opcode },
10455     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10456   },
10457   {
10458     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10459     { Bad_Opcode },
10460     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10461   },
10462   {
10463     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10464     { Bad_Opcode },
10465     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10466   },
10467   {
10468     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10469     { Bad_Opcode },
10470     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10471   },
10472   {
10473     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10474     { Bad_Opcode },
10475     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10476   },
10477   {
10478     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10479     { Bad_Opcode },
10480     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10481   },
10482   {
10483     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10484     { Bad_Opcode },
10485     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10486   },
10487   {
10488     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10489     { Bad_Opcode },
10490     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10491   },
10492   {
10493     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10494     { Bad_Opcode },
10495     { "knotw",          { MaskG, MaskR }, 0 },
10496   },
10497   {
10498     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10499     { Bad_Opcode },
10500     { "knotq",          { MaskG, MaskR }, 0 },
10501   },
10502   {
10503     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10504     { Bad_Opcode },
10505     { "knotb",          { MaskG, MaskR }, 0 },
10506   },
10507   {
10508     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10509     { Bad_Opcode },
10510     { "knotd",          { MaskG, MaskR }, 0 },
10511   },
10512   {
10513     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10514     { Bad_Opcode },
10515     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10516   },
10517   {
10518     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10519     { Bad_Opcode },
10520     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10521   },
10522   {
10523     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10524     { Bad_Opcode },
10525     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10526   },
10527   {
10528     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10529     { Bad_Opcode },
10530     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10531   },
10532  {
10533     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10534     { Bad_Opcode },
10535     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10536   },
10537   {
10538     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10539     { Bad_Opcode },
10540     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10541   },
10542   {
10543     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10544     { Bad_Opcode },
10545     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10546   },
10547   {
10548     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10549     { Bad_Opcode },
10550     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10551   },
10552   {
10553     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10554     { Bad_Opcode },
10555     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10556   },
10557   {
10558     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10559     { Bad_Opcode },
10560     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10561   },
10562   {
10563     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10564     { Bad_Opcode },
10565     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10566   },
10567   {
10568     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10569     { Bad_Opcode },
10570     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10571   },
10572   {
10573     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10574     { Bad_Opcode },
10575     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10576   },
10577   {
10578     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10579     { Bad_Opcode },
10580     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10581   },
10582   {
10583     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10584     { Bad_Opcode },
10585     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10586   },
10587   {
10588     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10589     { Bad_Opcode },
10590     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10591   },
10592   {
10593     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10594     { Bad_Opcode },
10595     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10596   },
10597   {
10598     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10599     { Bad_Opcode },
10600     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10601   },
10602   {
10603     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10604     { Bad_Opcode },
10605     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10606   },
10607   {
10608     /* MOD_VEX_0F50 */
10609     { Bad_Opcode },
10610     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10611   },
10612   {
10613     /* MOD_VEX_0F71_REG_2 */
10614     { Bad_Opcode },
10615     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10616   },
10617   {
10618     /* MOD_VEX_0F71_REG_4 */
10619     { Bad_Opcode },
10620     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10621   },
10622   {
10623     /* MOD_VEX_0F71_REG_6 */
10624     { Bad_Opcode },
10625     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10626   },
10627   {
10628     /* MOD_VEX_0F72_REG_2 */
10629     { Bad_Opcode },
10630     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10631   },
10632   {
10633     /* MOD_VEX_0F72_REG_4 */
10634     { Bad_Opcode },
10635     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10636   },
10637   {
10638     /* MOD_VEX_0F72_REG_6 */
10639     { Bad_Opcode },
10640     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10641   },
10642   {
10643     /* MOD_VEX_0F73_REG_2 */
10644     { Bad_Opcode },
10645     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10646   },
10647   {
10648     /* MOD_VEX_0F73_REG_3 */
10649     { Bad_Opcode },
10650     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10651   },
10652   {
10653     /* MOD_VEX_0F73_REG_6 */
10654     { Bad_Opcode },
10655     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10656   },
10657   {
10658     /* MOD_VEX_0F73_REG_7 */
10659     { Bad_Opcode },
10660     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10661   },
10662   {
10663     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10664     { "kmovw",          { Ew, MaskG }, 0 },
10665     { Bad_Opcode },
10666   },
10667   {
10668     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10669     { "kmovq",          { Eq, MaskG }, 0 },
10670     { Bad_Opcode },
10671   },
10672   {
10673     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10674     { "kmovb",          { Eb, MaskG }, 0 },
10675     { Bad_Opcode },
10676   },
10677   {
10678     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10679     { "kmovd",          { Ed, MaskG }, 0 },
10680     { Bad_Opcode },
10681   },
10682   {
10683     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10684     { Bad_Opcode },
10685     { "kmovw",          { MaskG, Rdq }, 0 },
10686   },
10687   {
10688     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10689     { Bad_Opcode },
10690     { "kmovb",          { MaskG, Rdq }, 0 },
10691   },
10692   {
10693     /* MOD_VEX_0F92_P_3_LEN_0 */
10694     { Bad_Opcode },
10695     { "kmovK",          { MaskG, Rdq }, 0 },
10696   },
10697   {
10698     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10699     { Bad_Opcode },
10700     { "kmovw",          { Gdq, MaskR }, 0 },
10701   },
10702   {
10703     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10704     { Bad_Opcode },
10705     { "kmovb",          { Gdq, MaskR }, 0 },
10706   },
10707   {
10708     /* MOD_VEX_0F93_P_3_LEN_0 */
10709     { Bad_Opcode },
10710     { "kmovK",          { Gdq, MaskR }, 0 },
10711   },
10712   {
10713     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10714     { Bad_Opcode },
10715     { "kortestw", { MaskG, MaskR }, 0 },
10716   },
10717   {
10718     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10719     { Bad_Opcode },
10720     { "kortestq", { MaskG, MaskR }, 0 },
10721   },
10722   {
10723     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10724     { Bad_Opcode },
10725     { "kortestb", { MaskG, MaskR }, 0 },
10726   },
10727   {
10728     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10729     { Bad_Opcode },
10730     { "kortestd", { MaskG, MaskR }, 0 },
10731   },
10732   {
10733     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10734     { Bad_Opcode },
10735     { "ktestw", { MaskG, MaskR }, 0 },
10736   },
10737   {
10738     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10739     { Bad_Opcode },
10740     { "ktestq", { MaskG, MaskR }, 0 },
10741   },
10742   {
10743     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10744     { Bad_Opcode },
10745     { "ktestb", { MaskG, MaskR }, 0 },
10746   },
10747   {
10748     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10749     { Bad_Opcode },
10750     { "ktestd", { MaskG, MaskR }, 0 },
10751   },
10752   {
10753     /* MOD_VEX_0FAE_REG_2 */
10754     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10755   },
10756   {
10757     /* MOD_VEX_0FAE_REG_3 */
10758     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10759   },
10760   {
10761     /* MOD_VEX_0FD7_PREFIX_2 */
10762     { Bad_Opcode },
10763     { "vpmovmskb",      { Gdq, XS }, 0 },
10764   },
10765   {
10766     /* MOD_VEX_0FE7_PREFIX_2 */
10767     { "vmovntdq",       { Mx, XM }, 0 },
10768   },
10769   {
10770     /* MOD_VEX_0FF0_PREFIX_3 */
10771     { "vlddqu",         { XM, M }, 0 },
10772   },
10773   {
10774     /* MOD_VEX_0F381A_PREFIX_2 */
10775     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10776   },
10777   {
10778     /* MOD_VEX_0F382A_PREFIX_2 */
10779     { "vmovntdqa",      { XM, Mx }, 0 },
10780   },
10781   {
10782     /* MOD_VEX_0F382C_PREFIX_2 */
10783     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10784   },
10785   {
10786     /* MOD_VEX_0F382D_PREFIX_2 */
10787     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10788   },
10789   {
10790     /* MOD_VEX_0F382E_PREFIX_2 */
10791     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10792   },
10793   {
10794     /* MOD_VEX_0F382F_PREFIX_2 */
10795     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10796   },
10797   {
10798     /* MOD_VEX_0F385A_PREFIX_2 */
10799     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10800   },
10801   {
10802     /* MOD_VEX_0F388C_PREFIX_2 */
10803     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10804   },
10805   {
10806     /* MOD_VEX_0F388E_PREFIX_2 */
10807     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10808   },
10809   {
10810     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10811     { Bad_Opcode },
10812     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10813   },
10814   {
10815     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10816     { Bad_Opcode },
10817     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10818   },
10819   {
10820     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10821     { Bad_Opcode },
10822     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10823   },
10824   {
10825     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10826     { Bad_Opcode },
10827     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10828   },
10829   {
10830     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10831     { Bad_Opcode },
10832     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10833   },
10834   {
10835     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10836     { Bad_Opcode },
10837     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10838   },
10839   {
10840     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10841     { Bad_Opcode },
10842     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10843   },
10844   {
10845     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10846     { Bad_Opcode },
10847     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10848   },
10849
10850 #include "i386-dis-evex-mod.h"
10851 };
10852
10853 static const struct dis386 rm_table[][8] = {
10854   {
10855     /* RM_C6_REG_7 */
10856     { "xabort",         { Skip_MODRM, Ib }, 0 },
10857   },
10858   {
10859     /* RM_C7_REG_7 */
10860     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10861   },
10862   {
10863     /* RM_0F01_REG_0 */
10864     { "enclv",          { Skip_MODRM }, 0 },
10865     { "vmcall",         { Skip_MODRM }, 0 },
10866     { "vmlaunch",       { Skip_MODRM }, 0 },
10867     { "vmresume",       { Skip_MODRM }, 0 },
10868     { "vmxoff",         { Skip_MODRM }, 0 },
10869     { "pconfig",        { Skip_MODRM }, 0 },
10870   },
10871   {
10872     /* RM_0F01_REG_1 */
10873     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10874     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10875     { "clac",           { Skip_MODRM }, 0 },
10876     { "stac",           { Skip_MODRM }, 0 },
10877     { Bad_Opcode },
10878     { Bad_Opcode },
10879     { Bad_Opcode },
10880     { "encls",          { Skip_MODRM }, 0 },
10881   },
10882   {
10883     /* RM_0F01_REG_2 */
10884     { "xgetbv",         { Skip_MODRM }, 0 },
10885     { "xsetbv",         { Skip_MODRM }, 0 },
10886     { Bad_Opcode },
10887     { Bad_Opcode },
10888     { "vmfunc",         { Skip_MODRM }, 0 },
10889     { "xend",           { Skip_MODRM }, 0 },
10890     { "xtest",          { Skip_MODRM }, 0 },
10891     { "enclu",          { Skip_MODRM }, 0 },
10892   },
10893   {
10894     /* RM_0F01_REG_3 */
10895     { "vmrun",          { Skip_MODRM }, 0 },
10896     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10897     { "vmload",         { Skip_MODRM }, 0 },
10898     { "vmsave",         { Skip_MODRM }, 0 },
10899     { "stgi",           { Skip_MODRM }, 0 },
10900     { "clgi",           { Skip_MODRM }, 0 },
10901     { "skinit",         { Skip_MODRM }, 0 },
10902     { "invlpga",        { Skip_MODRM }, 0 },
10903   },
10904   {
10905     /* RM_0F01_REG_5_MOD_3 */
10906     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10907     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10908     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10909     { Bad_Opcode },
10910     { Bad_Opcode },
10911     { Bad_Opcode },
10912     { "rdpkru",         { Skip_MODRM }, 0 },
10913     { "wrpkru",         { Skip_MODRM }, 0 },
10914   },
10915   {
10916     /* RM_0F01_REG_7_MOD_3 */
10917     { "swapgs",         { Skip_MODRM }, 0  },
10918     { "rdtscp",         { Skip_MODRM }, 0  },
10919     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
10920     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
10921     { "clzero",         { Skip_MODRM }, 0  },
10922     { "rdpru",          { Skip_MODRM }, 0  },
10923   },
10924   {
10925     /* RM_0F1E_P_1_MOD_3_REG_7 */
10926     { "nopQ",           { Ev }, 0 },
10927     { "nopQ",           { Ev }, 0 },
10928     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
10929     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
10930     { "nopQ",           { Ev }, 0 },
10931     { "nopQ",           { Ev }, 0 },
10932     { "nopQ",           { Ev }, 0 },
10933     { "nopQ",           { Ev }, 0 },
10934   },
10935   {
10936     /* RM_0FAE_REG_6_MOD_3 */
10937     { "mfence",         { Skip_MODRM }, 0 },
10938   },
10939   {
10940     /* RM_0FAE_REG_7_MOD_3 */
10941     { "sfence",         { Skip_MODRM }, 0 },
10942
10943   },
10944 };
10945
10946 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10947
10948 /* We use the high bit to indicate different name for the same
10949    prefix.  */
10950 #define REP_PREFIX      (0xf3 | 0x100)
10951 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10952 #define XRELEASE_PREFIX (0xf3 | 0x400)
10953 #define BND_PREFIX      (0xf2 | 0x400)
10954 #define NOTRACK_PREFIX  (0x3e | 0x100)
10955
10956 /* Remember if the current op is a jump instruction.  */
10957 static bfd_boolean op_is_jump = FALSE;
10958
10959 static int
10960 ckprefix (void)
10961 {
10962   int newrex, i, length;
10963   rex = 0;
10964   prefixes = 0;
10965   used_prefixes = 0;
10966   rex_used = 0;
10967   last_lock_prefix = -1;
10968   last_repz_prefix = -1;
10969   last_repnz_prefix = -1;
10970   last_data_prefix = -1;
10971   last_addr_prefix = -1;
10972   last_rex_prefix = -1;
10973   last_seg_prefix = -1;
10974   fwait_prefix = -1;
10975   active_seg_prefix = 0;
10976   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10977     all_prefixes[i] = 0;
10978   i = 0;
10979   length = 0;
10980   /* The maximum instruction length is 15bytes.  */
10981   while (length < MAX_CODE_LENGTH - 1)
10982     {
10983       FETCH_DATA (the_info, codep + 1);
10984       newrex = 0;
10985       switch (*codep)
10986         {
10987         /* REX prefixes family.  */
10988         case 0x40:
10989         case 0x41:
10990         case 0x42:
10991         case 0x43:
10992         case 0x44:
10993         case 0x45:
10994         case 0x46:
10995         case 0x47:
10996         case 0x48:
10997         case 0x49:
10998         case 0x4a:
10999         case 0x4b:
11000         case 0x4c:
11001         case 0x4d:
11002         case 0x4e:
11003         case 0x4f:
11004           if (address_mode == mode_64bit)
11005             newrex = *codep;
11006           else
11007             return 1;
11008           last_rex_prefix = i;
11009           break;
11010         case 0xf3:
11011           prefixes |= PREFIX_REPZ;
11012           last_repz_prefix = i;
11013           break;
11014         case 0xf2:
11015           prefixes |= PREFIX_REPNZ;
11016           last_repnz_prefix = i;
11017           break;
11018         case 0xf0:
11019           prefixes |= PREFIX_LOCK;
11020           last_lock_prefix = i;
11021           break;
11022         case 0x2e:
11023           prefixes |= PREFIX_CS;
11024           last_seg_prefix = i;
11025           active_seg_prefix = PREFIX_CS;
11026           break;
11027         case 0x36:
11028           prefixes |= PREFIX_SS;
11029           last_seg_prefix = i;
11030           active_seg_prefix = PREFIX_SS;
11031           break;
11032         case 0x3e:
11033           prefixes |= PREFIX_DS;
11034           last_seg_prefix = i;
11035           active_seg_prefix = PREFIX_DS;
11036           break;
11037         case 0x26:
11038           prefixes |= PREFIX_ES;
11039           last_seg_prefix = i;
11040           active_seg_prefix = PREFIX_ES;
11041           break;
11042         case 0x64:
11043           prefixes |= PREFIX_FS;
11044           last_seg_prefix = i;
11045           active_seg_prefix = PREFIX_FS;
11046           break;
11047         case 0x65:
11048           prefixes |= PREFIX_GS;
11049           last_seg_prefix = i;
11050           active_seg_prefix = PREFIX_GS;
11051           break;
11052         case 0x66:
11053           prefixes |= PREFIX_DATA;
11054           last_data_prefix = i;
11055           break;
11056         case 0x67:
11057           prefixes |= PREFIX_ADDR;
11058           last_addr_prefix = i;
11059           break;
11060         case FWAIT_OPCODE:
11061           /* fwait is really an instruction.  If there are prefixes
11062              before the fwait, they belong to the fwait, *not* to the
11063              following instruction.  */
11064           fwait_prefix = i;
11065           if (prefixes || rex)
11066             {
11067               prefixes |= PREFIX_FWAIT;
11068               codep++;
11069               /* This ensures that the previous REX prefixes are noticed
11070                  as unused prefixes, as in the return case below.  */
11071               rex_used = rex;
11072               return 1;
11073             }
11074           prefixes = PREFIX_FWAIT;
11075           break;
11076         default:
11077           return 1;
11078         }
11079       /* Rex is ignored when followed by another prefix.  */
11080       if (rex)
11081         {
11082           rex_used = rex;
11083           return 1;
11084         }
11085       if (*codep != FWAIT_OPCODE)
11086         all_prefixes[i++] = *codep;
11087       rex = newrex;
11088       codep++;
11089       length++;
11090     }
11091   return 0;
11092 }
11093
11094 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11095    prefix byte.  */
11096
11097 static const char *
11098 prefix_name (int pref, int sizeflag)
11099 {
11100   static const char *rexes [16] =
11101     {
11102       "rex",            /* 0x40 */
11103       "rex.B",          /* 0x41 */
11104       "rex.X",          /* 0x42 */
11105       "rex.XB",         /* 0x43 */
11106       "rex.R",          /* 0x44 */
11107       "rex.RB",         /* 0x45 */
11108       "rex.RX",         /* 0x46 */
11109       "rex.RXB",        /* 0x47 */
11110       "rex.W",          /* 0x48 */
11111       "rex.WB",         /* 0x49 */
11112       "rex.WX",         /* 0x4a */
11113       "rex.WXB",        /* 0x4b */
11114       "rex.WR",         /* 0x4c */
11115       "rex.WRB",        /* 0x4d */
11116       "rex.WRX",        /* 0x4e */
11117       "rex.WRXB",       /* 0x4f */
11118     };
11119
11120   switch (pref)
11121     {
11122     /* REX prefixes family.  */
11123     case 0x40:
11124     case 0x41:
11125     case 0x42:
11126     case 0x43:
11127     case 0x44:
11128     case 0x45:
11129     case 0x46:
11130     case 0x47:
11131     case 0x48:
11132     case 0x49:
11133     case 0x4a:
11134     case 0x4b:
11135     case 0x4c:
11136     case 0x4d:
11137     case 0x4e:
11138     case 0x4f:
11139       return rexes [pref - 0x40];
11140     case 0xf3:
11141       return "repz";
11142     case 0xf2:
11143       return "repnz";
11144     case 0xf0:
11145       return "lock";
11146     case 0x2e:
11147       return "cs";
11148     case 0x36:
11149       return "ss";
11150     case 0x3e:
11151       return "ds";
11152     case 0x26:
11153       return "es";
11154     case 0x64:
11155       return "fs";
11156     case 0x65:
11157       return "gs";
11158     case 0x66:
11159       return (sizeflag & DFLAG) ? "data16" : "data32";
11160     case 0x67:
11161       if (address_mode == mode_64bit)
11162         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11163       else
11164         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11165     case FWAIT_OPCODE:
11166       return "fwait";
11167     case REP_PREFIX:
11168       return "rep";
11169     case XACQUIRE_PREFIX:
11170       return "xacquire";
11171     case XRELEASE_PREFIX:
11172       return "xrelease";
11173     case BND_PREFIX:
11174       return "bnd";
11175     case NOTRACK_PREFIX:
11176       return "notrack";
11177     default:
11178       return NULL;
11179     }
11180 }
11181
11182 static char op_out[MAX_OPERANDS][100];
11183 static int op_ad, op_index[MAX_OPERANDS];
11184 static int two_source_ops;
11185 static bfd_vma op_address[MAX_OPERANDS];
11186 static bfd_vma op_riprel[MAX_OPERANDS];
11187 static bfd_vma start_pc;
11188
11189 /*
11190  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11191  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11192  *   section of the "Virtual 8086 Mode" chapter.)
11193  * 'pc' should be the address of this instruction, it will
11194  *   be used to print the target address if this is a relative jump or call
11195  * The function returns the length of this instruction in bytes.
11196  */
11197
11198 static char intel_syntax;
11199 static char intel_mnemonic = !SYSV386_COMPAT;
11200 static char open_char;
11201 static char close_char;
11202 static char separator_char;
11203 static char scale_char;
11204
11205 enum x86_64_isa
11206 {
11207   amd64 = 1,
11208   intel64
11209 };
11210
11211 static enum x86_64_isa isa64;
11212
11213 /* Here for backwards compatibility.  When gdb stops using
11214    print_insn_i386_att and print_insn_i386_intel these functions can
11215    disappear, and print_insn_i386 be merged into print_insn.  */
11216 int
11217 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11218 {
11219   intel_syntax = 0;
11220
11221   return print_insn (pc, info);
11222 }
11223
11224 int
11225 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11226 {
11227   intel_syntax = 1;
11228
11229   return print_insn (pc, info);
11230 }
11231
11232 int
11233 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11234 {
11235   intel_syntax = -1;
11236
11237   return print_insn (pc, info);
11238 }
11239
11240 void
11241 print_i386_disassembler_options (FILE *stream)
11242 {
11243   fprintf (stream, _("\n\
11244 The following i386/x86-64 specific disassembler options are supported for use\n\
11245 with the -M switch (multiple options should be separated by commas):\n"));
11246
11247   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11248   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11249   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11250   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11251   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11252   fprintf (stream, _("  att-mnemonic\n"
11253                      "              Display instruction in AT&T mnemonic\n"));
11254   fprintf (stream, _("  intel-mnemonic\n"
11255                      "              Display instruction in Intel mnemonic\n"));
11256   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11257   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11258   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11259   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11260   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11261   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11262   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11263   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11264 }
11265
11266 /* Bad opcode.  */
11267 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11268
11269 /* Get a pointer to struct dis386 with a valid name.  */
11270
11271 static const struct dis386 *
11272 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11273 {
11274   int vindex, vex_table_index;
11275
11276   if (dp->name != NULL)
11277     return dp;
11278
11279   switch (dp->op[0].bytemode)
11280     {
11281     case USE_REG_TABLE:
11282       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11283       break;
11284
11285     case USE_MOD_TABLE:
11286       vindex = modrm.mod == 0x3 ? 1 : 0;
11287       dp = &mod_table[dp->op[1].bytemode][vindex];
11288       break;
11289
11290     case USE_RM_TABLE:
11291       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11292       break;
11293
11294     case USE_PREFIX_TABLE:
11295       if (need_vex)
11296         {
11297           /* The prefix in VEX is implicit.  */
11298           switch (vex.prefix)
11299             {
11300             case 0:
11301               vindex = 0;
11302               break;
11303             case REPE_PREFIX_OPCODE:
11304               vindex = 1;
11305               break;
11306             case DATA_PREFIX_OPCODE:
11307               vindex = 2;
11308               break;
11309             case REPNE_PREFIX_OPCODE:
11310               vindex = 3;
11311               break;
11312             default:
11313               abort ();
11314               break;
11315             }
11316         }
11317       else
11318         {
11319           int last_prefix = -1;
11320           int prefix = 0;
11321           vindex = 0;
11322           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11323              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11324              last one wins.  */
11325           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11326             {
11327               if (last_repz_prefix > last_repnz_prefix)
11328                 {
11329                   vindex = 1;
11330                   prefix = PREFIX_REPZ;
11331                   last_prefix = last_repz_prefix;
11332                 }
11333               else
11334                 {
11335                   vindex = 3;
11336                   prefix = PREFIX_REPNZ;
11337                   last_prefix = last_repnz_prefix;
11338                 }
11339
11340               /* Check if prefix should be ignored.  */
11341               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11342                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11343                    & prefix) != 0)
11344                 vindex = 0;
11345             }
11346
11347           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11348             {
11349               vindex = 2;
11350               prefix = PREFIX_DATA;
11351               last_prefix = last_data_prefix;
11352             }
11353
11354           if (vindex != 0)
11355             {
11356               used_prefixes |= prefix;
11357               all_prefixes[last_prefix] = 0;
11358             }
11359         }
11360       dp = &prefix_table[dp->op[1].bytemode][vindex];
11361       break;
11362
11363     case USE_X86_64_TABLE:
11364       vindex = address_mode == mode_64bit ? 1 : 0;
11365       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11366       break;
11367
11368     case USE_3BYTE_TABLE:
11369       FETCH_DATA (info, codep + 2);
11370       vindex = *codep++;
11371       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11372       end_codep = codep;
11373       modrm.mod = (*codep >> 6) & 3;
11374       modrm.reg = (*codep >> 3) & 7;
11375       modrm.rm = *codep & 7;
11376       break;
11377
11378     case USE_VEX_LEN_TABLE:
11379       if (!need_vex)
11380         abort ();
11381
11382       switch (vex.length)
11383         {
11384         case 128:
11385           vindex = 0;
11386           break;
11387         case 256:
11388           vindex = 1;
11389           break;
11390         default:
11391           abort ();
11392           break;
11393         }
11394
11395       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11396       break;
11397
11398     case USE_EVEX_LEN_TABLE:
11399       if (!vex.evex)
11400         abort ();
11401
11402       switch (vex.length)
11403         {
11404         case 128:
11405           vindex = 0;
11406           break;
11407         case 256:
11408           vindex = 1;
11409           break;
11410         case 512:
11411           vindex = 2;
11412           break;
11413         default:
11414           abort ();
11415           break;
11416         }
11417
11418       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11419       break;
11420
11421     case USE_XOP_8F_TABLE:
11422       FETCH_DATA (info, codep + 3);
11423       rex = ~(*codep >> 5) & 0x7;
11424
11425       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11426       switch ((*codep & 0x1f))
11427         {
11428         default:
11429           dp = &bad_opcode;
11430           return dp;
11431         case 0x8:
11432           vex_table_index = XOP_08;
11433           break;
11434         case 0x9:
11435           vex_table_index = XOP_09;
11436           break;
11437         case 0xa:
11438           vex_table_index = XOP_0A;
11439           break;
11440         }
11441       codep++;
11442       vex.w = *codep & 0x80;
11443       if (vex.w && address_mode == mode_64bit)
11444         rex |= REX_W;
11445
11446       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11447       if (address_mode != mode_64bit)
11448         {
11449           /* In 16/32-bit mode REX_B is silently ignored.  */
11450           rex &= ~REX_B;
11451         }
11452
11453       vex.length = (*codep & 0x4) ? 256 : 128;
11454       switch ((*codep & 0x3))
11455         {
11456         case 0:
11457           break;
11458         case 1:
11459           vex.prefix = DATA_PREFIX_OPCODE;
11460           break;
11461         case 2:
11462           vex.prefix = REPE_PREFIX_OPCODE;
11463           break;
11464         case 3:
11465           vex.prefix = REPNE_PREFIX_OPCODE;
11466           break;
11467         }
11468       need_vex = 1;
11469       need_vex_reg = 1;
11470       codep++;
11471       vindex = *codep++;
11472       dp = &xop_table[vex_table_index][vindex];
11473
11474       end_codep = codep;
11475       FETCH_DATA (info, codep + 1);
11476       modrm.mod = (*codep >> 6) & 3;
11477       modrm.reg = (*codep >> 3) & 7;
11478       modrm.rm = *codep & 7;
11479       break;
11480
11481     case USE_VEX_C4_TABLE:
11482       /* VEX prefix.  */
11483       FETCH_DATA (info, codep + 3);
11484       rex = ~(*codep >> 5) & 0x7;
11485       switch ((*codep & 0x1f))
11486         {
11487         default:
11488           dp = &bad_opcode;
11489           return dp;
11490         case 0x1:
11491           vex_table_index = VEX_0F;
11492           break;
11493         case 0x2:
11494           vex_table_index = VEX_0F38;
11495           break;
11496         case 0x3:
11497           vex_table_index = VEX_0F3A;
11498           break;
11499         }
11500       codep++;
11501       vex.w = *codep & 0x80;
11502       if (address_mode == mode_64bit)
11503         {
11504           if (vex.w)
11505             rex |= REX_W;
11506         }
11507       else
11508         {
11509           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11510              is ignored, other REX bits are 0 and the highest bit in
11511              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11512           rex = 0;
11513         }
11514       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11515       vex.length = (*codep & 0x4) ? 256 : 128;
11516       switch ((*codep & 0x3))
11517         {
11518         case 0:
11519           break;
11520         case 1:
11521           vex.prefix = DATA_PREFIX_OPCODE;
11522           break;
11523         case 2:
11524           vex.prefix = REPE_PREFIX_OPCODE;
11525           break;
11526         case 3:
11527           vex.prefix = REPNE_PREFIX_OPCODE;
11528           break;
11529         }
11530       need_vex = 1;
11531       need_vex_reg = 1;
11532       codep++;
11533       vindex = *codep++;
11534       dp = &vex_table[vex_table_index][vindex];
11535       end_codep = codep;
11536       /* There is no MODRM byte for VEX0F 77.  */
11537       if (vex_table_index != VEX_0F || vindex != 0x77)
11538         {
11539           FETCH_DATA (info, codep + 1);
11540           modrm.mod = (*codep >> 6) & 3;
11541           modrm.reg = (*codep >> 3) & 7;
11542           modrm.rm = *codep & 7;
11543         }
11544       break;
11545
11546     case USE_VEX_C5_TABLE:
11547       /* VEX prefix.  */
11548       FETCH_DATA (info, codep + 2);
11549       rex = (*codep & 0x80) ? 0 : REX_R;
11550
11551       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11552          VEX.vvvv is 1.  */
11553       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11554       vex.length = (*codep & 0x4) ? 256 : 128;
11555       switch ((*codep & 0x3))
11556         {
11557         case 0:
11558           break;
11559         case 1:
11560           vex.prefix = DATA_PREFIX_OPCODE;
11561           break;
11562         case 2:
11563           vex.prefix = REPE_PREFIX_OPCODE;
11564           break;
11565         case 3:
11566           vex.prefix = REPNE_PREFIX_OPCODE;
11567           break;
11568         }
11569       need_vex = 1;
11570       need_vex_reg = 1;
11571       codep++;
11572       vindex = *codep++;
11573       dp = &vex_table[dp->op[1].bytemode][vindex];
11574       end_codep = codep;
11575       /* There is no MODRM byte for VEX 77.  */
11576       if (vindex != 0x77)
11577         {
11578           FETCH_DATA (info, codep + 1);
11579           modrm.mod = (*codep >> 6) & 3;
11580           modrm.reg = (*codep >> 3) & 7;
11581           modrm.rm = *codep & 7;
11582         }
11583       break;
11584
11585     case USE_VEX_W_TABLE:
11586       if (!need_vex)
11587         abort ();
11588
11589       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11590       break;
11591
11592     case USE_EVEX_TABLE:
11593       two_source_ops = 0;
11594       /* EVEX prefix.  */
11595       vex.evex = 1;
11596       FETCH_DATA (info, codep + 4);
11597       /* The first byte after 0x62.  */
11598       rex = ~(*codep >> 5) & 0x7;
11599       vex.r = *codep & 0x10;
11600       switch ((*codep & 0xf))
11601         {
11602         default:
11603           return &bad_opcode;
11604         case 0x1:
11605           vex_table_index = EVEX_0F;
11606           break;
11607         case 0x2:
11608           vex_table_index = EVEX_0F38;
11609           break;
11610         case 0x3:
11611           vex_table_index = EVEX_0F3A;
11612           break;
11613         }
11614
11615       /* The second byte after 0x62.  */
11616       codep++;
11617       vex.w = *codep & 0x80;
11618       if (vex.w && address_mode == mode_64bit)
11619         rex |= REX_W;
11620
11621       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11622
11623       /* The U bit.  */
11624       if (!(*codep & 0x4))
11625         return &bad_opcode;
11626
11627       switch ((*codep & 0x3))
11628         {
11629         case 0:
11630           break;
11631         case 1:
11632           vex.prefix = DATA_PREFIX_OPCODE;
11633           break;
11634         case 2:
11635           vex.prefix = REPE_PREFIX_OPCODE;
11636           break;
11637         case 3:
11638           vex.prefix = REPNE_PREFIX_OPCODE;
11639           break;
11640         }
11641
11642       /* The third byte after 0x62.  */
11643       codep++;
11644
11645       /* Remember the static rounding bits.  */
11646       vex.ll = (*codep >> 5) & 3;
11647       vex.b = (*codep & 0x10) != 0;
11648
11649       vex.v = *codep & 0x8;
11650       vex.mask_register_specifier = *codep & 0x7;
11651       vex.zeroing = *codep & 0x80;
11652
11653       if (address_mode != mode_64bit)
11654         {
11655           /* In 16/32-bit mode silently ignore following bits.  */
11656           rex &= ~REX_B;
11657           vex.r = 1;
11658           vex.v = 1;
11659         }
11660
11661       need_vex = 1;
11662       need_vex_reg = 1;
11663       codep++;
11664       vindex = *codep++;
11665       dp = &evex_table[vex_table_index][vindex];
11666       end_codep = codep;
11667       FETCH_DATA (info, codep + 1);
11668       modrm.mod = (*codep >> 6) & 3;
11669       modrm.reg = (*codep >> 3) & 7;
11670       modrm.rm = *codep & 7;
11671
11672       /* Set vector length.  */
11673       if (modrm.mod == 3 && vex.b)
11674         vex.length = 512;
11675       else
11676         {
11677           switch (vex.ll)
11678             {
11679             case 0x0:
11680               vex.length = 128;
11681               break;
11682             case 0x1:
11683               vex.length = 256;
11684               break;
11685             case 0x2:
11686               vex.length = 512;
11687               break;
11688             default:
11689               return &bad_opcode;
11690             }
11691         }
11692       break;
11693
11694     case 0:
11695       dp = &bad_opcode;
11696       break;
11697
11698     default:
11699       abort ();
11700     }
11701
11702   if (dp->name != NULL)
11703     return dp;
11704   else
11705     return get_valid_dis386 (dp, info);
11706 }
11707
11708 static void
11709 get_sib (disassemble_info *info, int sizeflag)
11710 {
11711   /* If modrm.mod == 3, operand must be register.  */
11712   if (need_modrm
11713       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11714       && modrm.mod != 3
11715       && modrm.rm == 4)
11716     {
11717       FETCH_DATA (info, codep + 2);
11718       sib.index = (codep [1] >> 3) & 7;
11719       sib.scale = (codep [1] >> 6) & 3;
11720       sib.base = codep [1] & 7;
11721     }
11722 }
11723
11724 static int
11725 print_insn (bfd_vma pc, disassemble_info *info)
11726 {
11727   const struct dis386 *dp;
11728   int i;
11729   char *op_txt[MAX_OPERANDS];
11730   int needcomma;
11731   int sizeflag, orig_sizeflag;
11732   const char *p;
11733   struct dis_private priv;
11734   int prefix_length;
11735
11736   priv.orig_sizeflag = AFLAG | DFLAG;
11737   if ((info->mach & bfd_mach_i386_i386) != 0)
11738     address_mode = mode_32bit;
11739   else if (info->mach == bfd_mach_i386_i8086)
11740     {
11741       address_mode = mode_16bit;
11742       priv.orig_sizeflag = 0;
11743     }
11744   else
11745     address_mode = mode_64bit;
11746
11747   if (intel_syntax == (char) -1)
11748     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11749
11750   for (p = info->disassembler_options; p != NULL; )
11751     {
11752       if (CONST_STRNEQ (p, "amd64"))
11753         isa64 = amd64;
11754       else if (CONST_STRNEQ (p, "intel64"))
11755         isa64 = intel64;
11756       else if (CONST_STRNEQ (p, "x86-64"))
11757         {
11758           address_mode = mode_64bit;
11759           priv.orig_sizeflag |= AFLAG | DFLAG;
11760         }
11761       else if (CONST_STRNEQ (p, "i386"))
11762         {
11763           address_mode = mode_32bit;
11764           priv.orig_sizeflag |= AFLAG | DFLAG;
11765         }
11766       else if (CONST_STRNEQ (p, "i8086"))
11767         {
11768           address_mode = mode_16bit;
11769           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11770         }
11771       else if (CONST_STRNEQ (p, "intel"))
11772         {
11773           intel_syntax = 1;
11774           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11775             intel_mnemonic = 1;
11776         }
11777       else if (CONST_STRNEQ (p, "att"))
11778         {
11779           intel_syntax = 0;
11780           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11781             intel_mnemonic = 0;
11782         }
11783       else if (CONST_STRNEQ (p, "addr"))
11784         {
11785           if (address_mode == mode_64bit)
11786             {
11787               if (p[4] == '3' && p[5] == '2')
11788                 priv.orig_sizeflag &= ~AFLAG;
11789               else if (p[4] == '6' && p[5] == '4')
11790                 priv.orig_sizeflag |= AFLAG;
11791             }
11792           else
11793             {
11794               if (p[4] == '1' && p[5] == '6')
11795                 priv.orig_sizeflag &= ~AFLAG;
11796               else if (p[4] == '3' && p[5] == '2')
11797                 priv.orig_sizeflag |= AFLAG;
11798             }
11799         }
11800       else if (CONST_STRNEQ (p, "data"))
11801         {
11802           if (p[4] == '1' && p[5] == '6')
11803             priv.orig_sizeflag &= ~DFLAG;
11804           else if (p[4] == '3' && p[5] == '2')
11805             priv.orig_sizeflag |= DFLAG;
11806         }
11807       else if (CONST_STRNEQ (p, "suffix"))
11808         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11809
11810       p = strchr (p, ',');
11811       if (p != NULL)
11812         p++;
11813     }
11814
11815   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11816     {
11817       (*info->fprintf_func) (info->stream,
11818                              _("64-bit address is disabled"));
11819       return -1;
11820     }
11821
11822   if (intel_syntax)
11823     {
11824       names64 = intel_names64;
11825       names32 = intel_names32;
11826       names16 = intel_names16;
11827       names8 = intel_names8;
11828       names8rex = intel_names8rex;
11829       names_seg = intel_names_seg;
11830       names_mm = intel_names_mm;
11831       names_bnd = intel_names_bnd;
11832       names_xmm = intel_names_xmm;
11833       names_ymm = intel_names_ymm;
11834       names_zmm = intel_names_zmm;
11835       index64 = intel_index64;
11836       index32 = intel_index32;
11837       names_mask = intel_names_mask;
11838       index16 = intel_index16;
11839       open_char = '[';
11840       close_char = ']';
11841       separator_char = '+';
11842       scale_char = '*';
11843     }
11844   else
11845     {
11846       names64 = att_names64;
11847       names32 = att_names32;
11848       names16 = att_names16;
11849       names8 = att_names8;
11850       names8rex = att_names8rex;
11851       names_seg = att_names_seg;
11852       names_mm = att_names_mm;
11853       names_bnd = att_names_bnd;
11854       names_xmm = att_names_xmm;
11855       names_ymm = att_names_ymm;
11856       names_zmm = att_names_zmm;
11857       index64 = att_index64;
11858       index32 = att_index32;
11859       names_mask = att_names_mask;
11860       index16 = att_index16;
11861       open_char = '(';
11862       close_char =  ')';
11863       separator_char = ',';
11864       scale_char = ',';
11865     }
11866
11867   /* The output looks better if we put 7 bytes on a line, since that
11868      puts most long word instructions on a single line.  Use 8 bytes
11869      for Intel L1OM.  */
11870   if ((info->mach & bfd_mach_l1om) != 0)
11871     info->bytes_per_line = 8;
11872   else
11873     info->bytes_per_line = 7;
11874
11875   info->private_data = &priv;
11876   priv.max_fetched = priv.the_buffer;
11877   priv.insn_start = pc;
11878
11879   obuf[0] = 0;
11880   for (i = 0; i < MAX_OPERANDS; ++i)
11881     {
11882       op_out[i][0] = 0;
11883       op_index[i] = -1;
11884     }
11885
11886   the_info = info;
11887   start_pc = pc;
11888   start_codep = priv.the_buffer;
11889   codep = priv.the_buffer;
11890
11891   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11892     {
11893       const char *name;
11894
11895       /* Getting here means we tried for data but didn't get it.  That
11896          means we have an incomplete instruction of some sort.  Just
11897          print the first byte as a prefix or a .byte pseudo-op.  */
11898       if (codep > priv.the_buffer)
11899         {
11900           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11901           if (name != NULL)
11902             (*info->fprintf_func) (info->stream, "%s", name);
11903           else
11904             {
11905               /* Just print the first byte as a .byte instruction.  */
11906               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11907                                      (unsigned int) priv.the_buffer[0]);
11908             }
11909
11910           return 1;
11911         }
11912
11913       return -1;
11914     }
11915
11916   obufp = obuf;
11917   sizeflag = priv.orig_sizeflag;
11918
11919   if (!ckprefix () || rex_used)
11920     {
11921       /* Too many prefixes or unused REX prefixes.  */
11922       for (i = 0;
11923            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11924            i++)
11925         (*info->fprintf_func) (info->stream, "%s%s",
11926                                i == 0 ? "" : " ",
11927                                prefix_name (all_prefixes[i], sizeflag));
11928       return i;
11929     }
11930
11931   insn_codep = codep;
11932
11933   FETCH_DATA (info, codep + 1);
11934   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11935
11936   if (((prefixes & PREFIX_FWAIT)
11937        && ((*codep < 0xd8) || (*codep > 0xdf))))
11938     {
11939       /* Handle prefixes before fwait.  */
11940       for (i = 0; i < fwait_prefix && all_prefixes[i];
11941            i++)
11942         (*info->fprintf_func) (info->stream, "%s ",
11943                                prefix_name (all_prefixes[i], sizeflag));
11944       (*info->fprintf_func) (info->stream, "fwait");
11945       return i + 1;
11946     }
11947
11948   if (*codep == 0x0f)
11949     {
11950       unsigned char threebyte;
11951
11952       codep++;
11953       FETCH_DATA (info, codep + 1);
11954       threebyte = *codep;
11955       dp = &dis386_twobyte[threebyte];
11956       need_modrm = twobyte_has_modrm[*codep];
11957       codep++;
11958     }
11959   else
11960     {
11961       dp = &dis386[*codep];
11962       need_modrm = onebyte_has_modrm[*codep];
11963       codep++;
11964     }
11965
11966   /* Save sizeflag for printing the extra prefixes later before updating
11967      it for mnemonic and operand processing.  The prefix names depend
11968      only on the address mode.  */
11969   orig_sizeflag = sizeflag;
11970   if (prefixes & PREFIX_ADDR)
11971     sizeflag ^= AFLAG;
11972   if ((prefixes & PREFIX_DATA))
11973     sizeflag ^= DFLAG;
11974
11975   end_codep = codep;
11976   if (need_modrm)
11977     {
11978       FETCH_DATA (info, codep + 1);
11979       modrm.mod = (*codep >> 6) & 3;
11980       modrm.reg = (*codep >> 3) & 7;
11981       modrm.rm = *codep & 7;
11982     }
11983
11984   need_vex = 0;
11985   need_vex_reg = 0;
11986   vex_w_done = 0;
11987   memset (&vex, 0, sizeof (vex));
11988
11989   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11990     {
11991       get_sib (info, sizeflag);
11992       dofloat (sizeflag);
11993     }
11994   else
11995     {
11996       dp = get_valid_dis386 (dp, info);
11997       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11998         {
11999           get_sib (info, sizeflag);
12000           for (i = 0; i < MAX_OPERANDS; ++i)
12001             {
12002               obufp = op_out[i];
12003               op_ad = MAX_OPERANDS - 1 - i;
12004               if (dp->op[i].rtn)
12005                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12006               /* For EVEX instruction after the last operand masking
12007                  should be printed.  */
12008               if (i == 0 && vex.evex)
12009                 {
12010                   /* Don't print {%k0}.  */
12011                   if (vex.mask_register_specifier)
12012                     {
12013                       oappend ("{");
12014                       oappend (names_mask[vex.mask_register_specifier]);
12015                       oappend ("}");
12016                     }
12017                   if (vex.zeroing)
12018                     oappend ("{z}");
12019                 }
12020             }
12021         }
12022     }
12023
12024   /* Clear instruction information.  */
12025   if (the_info)
12026     {
12027       the_info->insn_info_valid = 0;
12028       the_info->branch_delay_insns = 0;
12029       the_info->data_size = 0;
12030       the_info->insn_type = dis_noninsn;
12031       the_info->target = 0;
12032       the_info->target2 = 0;
12033     }
12034
12035   /* Reset jump operation indicator.  */
12036   op_is_jump = FALSE;
12037
12038   {
12039     int jump_detection = 0;
12040
12041     /* Extract flags.  */
12042     for (i = 0; i < MAX_OPERANDS; ++i)
12043       {
12044         if ((dp->op[i].rtn == OP_J)
12045             || (dp->op[i].rtn == OP_indirE))
12046           jump_detection |= 1;
12047         else if ((dp->op[i].rtn == BND_Fixup)
12048                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12049           jump_detection |= 2;
12050         else if ((dp->op[i].bytemode == cond_jump_mode)
12051                  || (dp->op[i].bytemode == loop_jcxz_mode))
12052           jump_detection |= 4;
12053       }
12054
12055     /* Determine if this is a jump or branch.  */
12056     if ((jump_detection & 0x3) == 0x3)
12057       {
12058         op_is_jump = TRUE;
12059         if (jump_detection & 0x4)
12060           the_info->insn_type = dis_condbranch;
12061         else
12062           the_info->insn_type =
12063             (dp->name && !strncmp(dp->name, "call", 4))
12064             ? dis_jsr : dis_branch;
12065       }
12066   }
12067
12068   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12069      are all 0s in inverted form.  */
12070   if (need_vex && vex.register_specifier != 0)
12071     {
12072       (*info->fprintf_func) (info->stream, "(bad)");
12073       return end_codep - priv.the_buffer;
12074     }
12075
12076   /* Check if the REX prefix is used.  */
12077   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12078     all_prefixes[last_rex_prefix] = 0;
12079
12080   /* Check if the SEG prefix is used.  */
12081   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12082                    | PREFIX_FS | PREFIX_GS)) != 0
12083       && (used_prefixes & active_seg_prefix) != 0)
12084     all_prefixes[last_seg_prefix] = 0;
12085
12086   /* Check if the ADDR prefix is used.  */
12087   if ((prefixes & PREFIX_ADDR) != 0
12088       && (used_prefixes & PREFIX_ADDR) != 0)
12089     all_prefixes[last_addr_prefix] = 0;
12090
12091   /* Check if the DATA prefix is used.  */
12092   if ((prefixes & PREFIX_DATA) != 0
12093       && (used_prefixes & PREFIX_DATA) != 0
12094       && !need_vex)
12095     all_prefixes[last_data_prefix] = 0;
12096
12097   /* Print the extra prefixes.  */
12098   prefix_length = 0;
12099   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12100     if (all_prefixes[i])
12101       {
12102         const char *name;
12103         name = prefix_name (all_prefixes[i], orig_sizeflag);
12104         if (name == NULL)
12105           abort ();
12106         prefix_length += strlen (name) + 1;
12107         (*info->fprintf_func) (info->stream, "%s ", name);
12108       }
12109
12110   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12111      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12112      used by putop and MMX/SSE operand and may be overriden by the
12113      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12114      separately.  */
12115   if (dp->prefix_requirement == PREFIX_OPCODE
12116       && (((need_vex
12117             ? vex.prefix == REPE_PREFIX_OPCODE
12118               || vex.prefix == REPNE_PREFIX_OPCODE
12119             : (prefixes
12120                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12121            && (used_prefixes
12122                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12123           || (((need_vex
12124                 ? vex.prefix == DATA_PREFIX_OPCODE
12125                 : ((prefixes
12126                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12127                    == PREFIX_DATA))
12128                && (used_prefixes & PREFIX_DATA) == 0))
12129           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12130     {
12131       (*info->fprintf_func) (info->stream, "(bad)");
12132       return end_codep - priv.the_buffer;
12133     }
12134
12135   /* Check maximum code length.  */
12136   if ((codep - start_codep) > MAX_CODE_LENGTH)
12137     {
12138       (*info->fprintf_func) (info->stream, "(bad)");
12139       return MAX_CODE_LENGTH;
12140     }
12141
12142   obufp = mnemonicendp;
12143   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12144     oappend (" ");
12145   oappend (" ");
12146   (*info->fprintf_func) (info->stream, "%s", obuf);
12147
12148   /* The enter and bound instructions are printed with operands in the same
12149      order as the intel book; everything else is printed in reverse order.  */
12150   if (intel_syntax || two_source_ops)
12151     {
12152       bfd_vma riprel;
12153
12154       for (i = 0; i < MAX_OPERANDS; ++i)
12155         op_txt[i] = op_out[i];
12156
12157       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12158           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12159         {
12160           op_txt[2] = op_out[3];
12161           op_txt[3] = op_out[2];
12162         }
12163
12164       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12165         {
12166           op_ad = op_index[i];
12167           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12168           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12169           riprel = op_riprel[i];
12170           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12171           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12172         }
12173     }
12174   else
12175     {
12176       for (i = 0; i < MAX_OPERANDS; ++i)
12177         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12178     }
12179
12180   needcomma = 0;
12181   for (i = 0; i < MAX_OPERANDS; ++i)
12182     if (*op_txt[i])
12183       {
12184         if (needcomma)
12185           (*info->fprintf_func) (info->stream, ",");
12186         if (op_index[i] != -1 && !op_riprel[i])
12187           {
12188             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12189
12190             if (the_info && op_is_jump)
12191               {
12192                 the_info->insn_info_valid = 1;
12193                 the_info->branch_delay_insns = 0;
12194                 the_info->data_size = 0;
12195                 the_info->target = target;
12196                 the_info->target2 = 0;
12197               }
12198             (*info->print_address_func) (target, info);
12199           }
12200         else
12201           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12202         needcomma = 1;
12203       }
12204
12205   for (i = 0; i < MAX_OPERANDS; i++)
12206     if (op_index[i] != -1 && op_riprel[i])
12207       {
12208         (*info->fprintf_func) (info->stream, "        # ");
12209         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12210                                                 + op_address[op_index[i]]), info);
12211         break;
12212       }
12213   return codep - priv.the_buffer;
12214 }
12215
12216 static const char *float_mem[] = {
12217   /* d8 */
12218   "fadd{s|}",
12219   "fmul{s|}",
12220   "fcom{s|}",
12221   "fcomp{s|}",
12222   "fsub{s|}",
12223   "fsubr{s|}",
12224   "fdiv{s|}",
12225   "fdivr{s|}",
12226   /* d9 */
12227   "fld{s|}",
12228   "(bad)",
12229   "fst{s|}",
12230   "fstp{s|}",
12231   "fldenv{C|C}",
12232   "fldcw",
12233   "fNstenv{C|C}",
12234   "fNstcw",
12235   /* da */
12236   "fiadd{l|}",
12237   "fimul{l|}",
12238   "ficom{l|}",
12239   "ficomp{l|}",
12240   "fisub{l|}",
12241   "fisubr{l|}",
12242   "fidiv{l|}",
12243   "fidivr{l|}",
12244   /* db */
12245   "fild{l|}",
12246   "fisttp{l|}",
12247   "fist{l|}",
12248   "fistp{l|}",
12249   "(bad)",
12250   "fld{t|}",
12251   "(bad)",
12252   "fstp{t|}",
12253   /* dc */
12254   "fadd{l|}",
12255   "fmul{l|}",
12256   "fcom{l|}",
12257   "fcomp{l|}",
12258   "fsub{l|}",
12259   "fsubr{l|}",
12260   "fdiv{l|}",
12261   "fdivr{l|}",
12262   /* dd */
12263   "fld{l|}",
12264   "fisttp{ll|}",
12265   "fst{l||}",
12266   "fstp{l|}",
12267   "frstor{C|C}",
12268   "(bad)",
12269   "fNsave{C|C}",
12270   "fNstsw",
12271   /* de */
12272   "fiadd{s|}",
12273   "fimul{s|}",
12274   "ficom{s|}",
12275   "ficomp{s|}",
12276   "fisub{s|}",
12277   "fisubr{s|}",
12278   "fidiv{s|}",
12279   "fidivr{s|}",
12280   /* df */
12281   "fild{s|}",
12282   "fisttp{s|}",
12283   "fist{s|}",
12284   "fistp{s|}",
12285   "fbld",
12286   "fild{ll|}",
12287   "fbstp",
12288   "fistp{ll|}",
12289 };
12290
12291 static const unsigned char float_mem_mode[] = {
12292   /* d8 */
12293   d_mode,
12294   d_mode,
12295   d_mode,
12296   d_mode,
12297   d_mode,
12298   d_mode,
12299   d_mode,
12300   d_mode,
12301   /* d9 */
12302   d_mode,
12303   0,
12304   d_mode,
12305   d_mode,
12306   0,
12307   w_mode,
12308   0,
12309   w_mode,
12310   /* da */
12311   d_mode,
12312   d_mode,
12313   d_mode,
12314   d_mode,
12315   d_mode,
12316   d_mode,
12317   d_mode,
12318   d_mode,
12319   /* db */
12320   d_mode,
12321   d_mode,
12322   d_mode,
12323   d_mode,
12324   0,
12325   t_mode,
12326   0,
12327   t_mode,
12328   /* dc */
12329   q_mode,
12330   q_mode,
12331   q_mode,
12332   q_mode,
12333   q_mode,
12334   q_mode,
12335   q_mode,
12336   q_mode,
12337   /* dd */
12338   q_mode,
12339   q_mode,
12340   q_mode,
12341   q_mode,
12342   0,
12343   0,
12344   0,
12345   w_mode,
12346   /* de */
12347   w_mode,
12348   w_mode,
12349   w_mode,
12350   w_mode,
12351   w_mode,
12352   w_mode,
12353   w_mode,
12354   w_mode,
12355   /* df */
12356   w_mode,
12357   w_mode,
12358   w_mode,
12359   w_mode,
12360   t_mode,
12361   q_mode,
12362   t_mode,
12363   q_mode
12364 };
12365
12366 #define ST { OP_ST, 0 }
12367 #define STi { OP_STi, 0 }
12368
12369 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12370 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12371 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12372 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12373 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12374 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12375 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12376 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12377 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12378
12379 static const struct dis386 float_reg[][8] = {
12380   /* d8 */
12381   {
12382     { "fadd",   { ST, STi }, 0 },
12383     { "fmul",   { ST, STi }, 0 },
12384     { "fcom",   { STi }, 0 },
12385     { "fcomp",  { STi }, 0 },
12386     { "fsub",   { ST, STi }, 0 },
12387     { "fsubr",  { ST, STi }, 0 },
12388     { "fdiv",   { ST, STi }, 0 },
12389     { "fdivr",  { ST, STi }, 0 },
12390   },
12391   /* d9 */
12392   {
12393     { "fld",    { STi }, 0 },
12394     { "fxch",   { STi }, 0 },
12395     { FGRPd9_2 },
12396     { Bad_Opcode },
12397     { FGRPd9_4 },
12398     { FGRPd9_5 },
12399     { FGRPd9_6 },
12400     { FGRPd9_7 },
12401   },
12402   /* da */
12403   {
12404     { "fcmovb", { ST, STi }, 0 },
12405     { "fcmove", { ST, STi }, 0 },
12406     { "fcmovbe",{ ST, STi }, 0 },
12407     { "fcmovu", { ST, STi }, 0 },
12408     { Bad_Opcode },
12409     { FGRPda_5 },
12410     { Bad_Opcode },
12411     { Bad_Opcode },
12412   },
12413   /* db */
12414   {
12415     { "fcmovnb",{ ST, STi }, 0 },
12416     { "fcmovne",{ ST, STi }, 0 },
12417     { "fcmovnbe",{ ST, STi }, 0 },
12418     { "fcmovnu",{ ST, STi }, 0 },
12419     { FGRPdb_4 },
12420     { "fucomi", { ST, STi }, 0 },
12421     { "fcomi",  { ST, STi }, 0 },
12422     { Bad_Opcode },
12423   },
12424   /* dc */
12425   {
12426     { "fadd",   { STi, ST }, 0 },
12427     { "fmul",   { STi, ST }, 0 },
12428     { Bad_Opcode },
12429     { Bad_Opcode },
12430     { "fsub{!M|r}",     { STi, ST }, 0 },
12431     { "fsub{M|}",       { STi, ST }, 0 },
12432     { "fdiv{!M|r}",     { STi, ST }, 0 },
12433     { "fdiv{M|}",       { STi, ST }, 0 },
12434   },
12435   /* dd */
12436   {
12437     { "ffree",  { STi }, 0 },
12438     { Bad_Opcode },
12439     { "fst",    { STi }, 0 },
12440     { "fstp",   { STi }, 0 },
12441     { "fucom",  { STi }, 0 },
12442     { "fucomp", { STi }, 0 },
12443     { Bad_Opcode },
12444     { Bad_Opcode },
12445   },
12446   /* de */
12447   {
12448     { "faddp",  { STi, ST }, 0 },
12449     { "fmulp",  { STi, ST }, 0 },
12450     { Bad_Opcode },
12451     { FGRPde_3 },
12452     { "fsub{!M|r}p",    { STi, ST }, 0 },
12453     { "fsub{M|}p",      { STi, ST }, 0 },
12454     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12455     { "fdiv{M|}p",      { STi, ST }, 0 },
12456   },
12457   /* df */
12458   {
12459     { "ffreep", { STi }, 0 },
12460     { Bad_Opcode },
12461     { Bad_Opcode },
12462     { Bad_Opcode },
12463     { FGRPdf_4 },
12464     { "fucomip", { ST, STi }, 0 },
12465     { "fcomip", { ST, STi }, 0 },
12466     { Bad_Opcode },
12467   },
12468 };
12469
12470 static char *fgrps[][8] = {
12471   /* Bad opcode 0 */
12472   {
12473     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12474   },
12475
12476   /* d9_2  1 */
12477   {
12478     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12479   },
12480
12481   /* d9_4  2 */
12482   {
12483     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12484   },
12485
12486   /* d9_5  3 */
12487   {
12488     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12489   },
12490
12491   /* d9_6  4 */
12492   {
12493     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12494   },
12495
12496   /* d9_7  5 */
12497   {
12498     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12499   },
12500
12501   /* da_5  6 */
12502   {
12503     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12504   },
12505
12506   /* db_4  7 */
12507   {
12508     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12509     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12510   },
12511
12512   /* de_3  8 */
12513   {
12514     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12515   },
12516
12517   /* df_4  9 */
12518   {
12519     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12520   },
12521 };
12522
12523 static void
12524 swap_operand (void)
12525 {
12526   mnemonicendp[0] = '.';
12527   mnemonicendp[1] = 's';
12528   mnemonicendp += 2;
12529 }
12530
12531 static void
12532 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12533                int sizeflag ATTRIBUTE_UNUSED)
12534 {
12535   /* Skip mod/rm byte.  */
12536   MODRM_CHECK;
12537   codep++;
12538 }
12539
12540 static void
12541 dofloat (int sizeflag)
12542 {
12543   const struct dis386 *dp;
12544   unsigned char floatop;
12545
12546   floatop = codep[-1];
12547
12548   if (modrm.mod != 3)
12549     {
12550       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12551
12552       putop (float_mem[fp_indx], sizeflag);
12553       obufp = op_out[0];
12554       op_ad = 2;
12555       OP_E (float_mem_mode[fp_indx], sizeflag);
12556       return;
12557     }
12558   /* Skip mod/rm byte.  */
12559   MODRM_CHECK;
12560   codep++;
12561
12562   dp = &float_reg[floatop - 0xd8][modrm.reg];
12563   if (dp->name == NULL)
12564     {
12565       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12566
12567       /* Instruction fnstsw is only one with strange arg.  */
12568       if (floatop == 0xdf && codep[-1] == 0xe0)
12569         strcpy (op_out[0], names16[0]);
12570     }
12571   else
12572     {
12573       putop (dp->name, sizeflag);
12574
12575       obufp = op_out[0];
12576       op_ad = 2;
12577       if (dp->op[0].rtn)
12578         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12579
12580       obufp = op_out[1];
12581       op_ad = 1;
12582       if (dp->op[1].rtn)
12583         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12584     }
12585 }
12586
12587 /* Like oappend (below), but S is a string starting with '%'.
12588    In Intel syntax, the '%' is elided.  */
12589 static void
12590 oappend_maybe_intel (const char *s)
12591 {
12592   oappend (s + intel_syntax);
12593 }
12594
12595 static void
12596 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12597 {
12598   oappend_maybe_intel ("%st");
12599 }
12600
12601 static void
12602 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12603 {
12604   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12605   oappend_maybe_intel (scratchbuf);
12606 }
12607
12608 /* Capital letters in template are macros.  */
12609 static int
12610 putop (const char *in_template, int sizeflag)
12611 {
12612   const char *p;
12613   int alt = 0;
12614   int cond = 1;
12615   unsigned int l = 0, len = 1;
12616   char last[4];
12617
12618 #define SAVE_LAST(c)                    \
12619   if (l < len && l < sizeof (last))     \
12620     last[l++] = c;                      \
12621   else                                  \
12622     abort ();
12623
12624   for (p = in_template; *p; p++)
12625     {
12626       switch (*p)
12627         {
12628         default:
12629           *obufp++ = *p;
12630           break;
12631         case '%':
12632           len++;
12633           break;
12634         case '!':
12635           cond = 0;
12636           break;
12637         case '{':
12638           if (intel_syntax)
12639             {
12640               while (*++p != '|')
12641                 if (*p == '}' || *p == '\0')
12642                   abort ();
12643               alt = 1;
12644             }
12645           break;
12646         case '|':
12647           while (*++p != '}')
12648             {
12649               if (*p == '\0')
12650                 abort ();
12651             }
12652           break;
12653         case '}':
12654           alt = 0;
12655           break;
12656         case 'A':
12657           if (intel_syntax)
12658             break;
12659           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12660             *obufp++ = 'b';
12661           break;
12662         case 'B':
12663           if (l == 0 && len == 1)
12664             {
12665             case_B:
12666               if (intel_syntax)
12667                 break;
12668               if (sizeflag & SUFFIX_ALWAYS)
12669                 *obufp++ = 'b';
12670             }
12671           else
12672             {
12673               if (l != 1
12674                   || len != 2
12675                   || last[0] != 'L')
12676                 {
12677                   SAVE_LAST (*p);
12678                   break;
12679                 }
12680
12681               if (address_mode == mode_64bit
12682                   && !(prefixes & PREFIX_ADDR))
12683                 {
12684                   *obufp++ = 'a';
12685                   *obufp++ = 'b';
12686                   *obufp++ = 's';
12687                 }
12688
12689               goto case_B;
12690             }
12691           break;
12692         case 'C':
12693           if (intel_syntax && !alt)
12694             break;
12695           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12696             {
12697               if (sizeflag & DFLAG)
12698                 *obufp++ = intel_syntax ? 'd' : 'l';
12699               else
12700                 *obufp++ = intel_syntax ? 'w' : 's';
12701               used_prefixes |= (prefixes & PREFIX_DATA);
12702             }
12703           break;
12704         case 'D':
12705           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12706             break;
12707           USED_REX (REX_W);
12708           if (modrm.mod == 3)
12709             {
12710               if (rex & REX_W)
12711                 *obufp++ = 'q';
12712               else
12713                 {
12714                   if (sizeflag & DFLAG)
12715                     *obufp++ = intel_syntax ? 'd' : 'l';
12716                   else
12717                     *obufp++ = 'w';
12718                   used_prefixes |= (prefixes & PREFIX_DATA);
12719                 }
12720             }
12721           else
12722             *obufp++ = 'w';
12723           break;
12724         case 'E':               /* For jcxz/jecxz */
12725           if (address_mode == mode_64bit)
12726             {
12727               if (sizeflag & AFLAG)
12728                 *obufp++ = 'r';
12729               else
12730                 *obufp++ = 'e';
12731             }
12732           else
12733             if (sizeflag & AFLAG)
12734               *obufp++ = 'e';
12735           used_prefixes |= (prefixes & PREFIX_ADDR);
12736           break;
12737         case 'F':
12738           if (intel_syntax)
12739             break;
12740           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12741             {
12742               if (sizeflag & AFLAG)
12743                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12744               else
12745                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12746               used_prefixes |= (prefixes & PREFIX_ADDR);
12747             }
12748           break;
12749         case 'G':
12750           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12751             break;
12752           if ((rex & REX_W) || (sizeflag & DFLAG))
12753             *obufp++ = 'l';
12754           else
12755             *obufp++ = 'w';
12756           if (!(rex & REX_W))
12757             used_prefixes |= (prefixes & PREFIX_DATA);
12758           break;
12759         case 'H':
12760           if (intel_syntax)
12761             break;
12762           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12763               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12764             {
12765               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12766               *obufp++ = ',';
12767               *obufp++ = 'p';
12768               if (prefixes & PREFIX_DS)
12769                 *obufp++ = 't';
12770               else
12771                 *obufp++ = 'n';
12772             }
12773           break;
12774         case 'K':
12775           USED_REX (REX_W);
12776           if (rex & REX_W)
12777             *obufp++ = 'q';
12778           else
12779             *obufp++ = 'd';
12780           break;
12781         case 'Z':
12782           if (l != 0 || len != 1)
12783             {
12784               if (l != 1 || len != 2 || last[0] != 'X')
12785                 {
12786                   SAVE_LAST (*p);
12787                   break;
12788                 }
12789               if (!need_vex || !vex.evex)
12790                 abort ();
12791               if (intel_syntax
12792                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12793                 break;
12794               switch (vex.length)
12795                 {
12796                 case 128:
12797                   *obufp++ = 'x';
12798                   break;
12799                 case 256:
12800                   *obufp++ = 'y';
12801                   break;
12802                 case 512:
12803                   *obufp++ = 'z';
12804                   break;
12805                 default:
12806                   abort ();
12807                 }
12808               break;
12809             }
12810           if (intel_syntax)
12811             break;
12812           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12813             {
12814               *obufp++ = 'q';
12815               break;
12816             }
12817           /* Fall through.  */
12818           goto case_L;
12819         case 'L':
12820           if (l != 0 || len != 1)
12821             {
12822               SAVE_LAST (*p);
12823               break;
12824             }
12825         case_L:
12826           if (intel_syntax)
12827             break;
12828           if (sizeflag & SUFFIX_ALWAYS)
12829             *obufp++ = 'l';
12830           break;
12831         case 'M':
12832           if (intel_mnemonic != cond)
12833             *obufp++ = 'r';
12834           break;
12835         case 'N':
12836           if ((prefixes & PREFIX_FWAIT) == 0)
12837             *obufp++ = 'n';
12838           else
12839             used_prefixes |= PREFIX_FWAIT;
12840           break;
12841         case 'O':
12842           USED_REX (REX_W);
12843           if (rex & REX_W)
12844             *obufp++ = 'o';
12845           else if (intel_syntax && (sizeflag & DFLAG))
12846             *obufp++ = 'q';
12847           else
12848             *obufp++ = 'd';
12849           if (!(rex & REX_W))
12850             used_prefixes |= (prefixes & PREFIX_DATA);
12851           break;
12852         case '&':
12853           if (!intel_syntax
12854               && address_mode == mode_64bit
12855               && isa64 == intel64)
12856             {
12857               *obufp++ = 'q';
12858               break;
12859             }
12860           /* Fall through.  */
12861         case 'T':
12862           if (!intel_syntax
12863               && address_mode == mode_64bit
12864               && ((sizeflag & DFLAG) || (rex & REX_W)))
12865             {
12866               *obufp++ = 'q';
12867               break;
12868             }
12869           /* Fall through.  */
12870           goto case_P;
12871         case 'P':
12872           if (l == 0 && len == 1)
12873             {
12874             case_P:
12875               if (intel_syntax)
12876                 {
12877                   if ((rex & REX_W) == 0
12878                       && (prefixes & PREFIX_DATA))
12879                     {
12880                       if ((sizeflag & DFLAG) == 0)
12881                         *obufp++ = 'w';
12882                       used_prefixes |= (prefixes & PREFIX_DATA);
12883                     }
12884                   break;
12885                 }
12886               if ((prefixes & PREFIX_DATA)
12887                   || (rex & REX_W)
12888                   || (sizeflag & SUFFIX_ALWAYS))
12889                 {
12890                   USED_REX (REX_W);
12891                   if (rex & REX_W)
12892                     *obufp++ = 'q';
12893                   else
12894                     {
12895                       if (sizeflag & DFLAG)
12896                         *obufp++ = 'l';
12897                       else
12898                         *obufp++ = 'w';
12899                       used_prefixes |= (prefixes & PREFIX_DATA);
12900                     }
12901                 }
12902             }
12903           else
12904             {
12905               if (l != 1 || len != 2 || last[0] != 'L')
12906                 {
12907                   SAVE_LAST (*p);
12908                   break;
12909                 }
12910
12911               if ((prefixes & PREFIX_DATA)
12912                   || (rex & REX_W)
12913                   || (sizeflag & SUFFIX_ALWAYS))
12914                 {
12915                   USED_REX (REX_W);
12916                   if (rex & REX_W)
12917                     *obufp++ = 'q';
12918                   else
12919                     {
12920                       if (sizeflag & DFLAG)
12921                         *obufp++ = intel_syntax ? 'd' : 'l';
12922                       else
12923                         *obufp++ = 'w';
12924                       used_prefixes |= (prefixes & PREFIX_DATA);
12925                     }
12926                 }
12927             }
12928           break;
12929         case 'U':
12930           if (intel_syntax)
12931             break;
12932           if (address_mode == mode_64bit
12933               && ((sizeflag & DFLAG) || (rex & REX_W)))
12934             {
12935               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12936                 *obufp++ = 'q';
12937               break;
12938             }
12939           /* Fall through.  */
12940           goto case_Q;
12941         case 'Q':
12942           if (l == 0 && len == 1)
12943             {
12944             case_Q:
12945               if (intel_syntax && !alt)
12946                 break;
12947               USED_REX (REX_W);
12948               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12949                 {
12950                   if (rex & REX_W)
12951                     *obufp++ = 'q';
12952                   else
12953                     {
12954                       if (sizeflag & DFLAG)
12955                         *obufp++ = intel_syntax ? 'd' : 'l';
12956                       else
12957                         *obufp++ = 'w';
12958                       used_prefixes |= (prefixes & PREFIX_DATA);
12959                     }
12960                 }
12961             }
12962           else
12963             {
12964               if (l != 1 || len != 2 || last[0] != 'L')
12965                 {
12966                   SAVE_LAST (*p);
12967                   break;
12968                 }
12969               if ((intel_syntax && need_modrm)
12970                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12971                 break;
12972               if ((rex & REX_W))
12973                 {
12974                   USED_REX (REX_W);
12975                   *obufp++ = 'q';
12976                 }
12977               else if((address_mode == mode_64bit && need_modrm)
12978                       || (sizeflag & SUFFIX_ALWAYS))
12979                 *obufp++ = intel_syntax? 'd' : 'l';
12980             }
12981           break;
12982         case 'R':
12983           USED_REX (REX_W);
12984           if (rex & REX_W)
12985             *obufp++ = 'q';
12986           else if (sizeflag & DFLAG)
12987             {
12988               if (intel_syntax)
12989                   *obufp++ = 'd';
12990               else
12991                   *obufp++ = 'l';
12992             }
12993           else
12994             *obufp++ = 'w';
12995           if (intel_syntax && !p[1]
12996               && ((rex & REX_W) || (sizeflag & DFLAG)))
12997             *obufp++ = 'e';
12998           if (!(rex & REX_W))
12999             used_prefixes |= (prefixes & PREFIX_DATA);
13000           break;
13001         case 'V':
13002           if (l == 0 && len == 1)
13003             {
13004               if (intel_syntax)
13005                 break;
13006               if (address_mode == mode_64bit
13007                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13008                 {
13009                   if (sizeflag & SUFFIX_ALWAYS)
13010                     *obufp++ = 'q';
13011                   break;
13012                 }
13013             }
13014           else
13015             {
13016               if (l != 1
13017                   || len != 2
13018                   || last[0] != 'L')
13019                 {
13020                   SAVE_LAST (*p);
13021                   break;
13022                 }
13023
13024               if (rex & REX_W)
13025                 {
13026                   *obufp++ = 'a';
13027                   *obufp++ = 'b';
13028                   *obufp++ = 's';
13029                 }
13030             }
13031           /* Fall through.  */
13032           goto case_S;
13033         case 'S':
13034           if (l == 0 && len == 1)
13035             {
13036             case_S:
13037               if (intel_syntax)
13038                 break;
13039               if (sizeflag & SUFFIX_ALWAYS)
13040                 {
13041                   if (rex & REX_W)
13042                     *obufp++ = 'q';
13043                   else
13044                     {
13045                       if (sizeflag & DFLAG)
13046                         *obufp++ = 'l';
13047                       else
13048                         *obufp++ = 'w';
13049                       used_prefixes |= (prefixes & PREFIX_DATA);
13050                     }
13051                 }
13052             }
13053           else
13054             {
13055               if (l != 1
13056                   || len != 2
13057                   || last[0] != 'L')
13058                 {
13059                   SAVE_LAST (*p);
13060                   break;
13061                 }
13062
13063               if (address_mode == mode_64bit
13064                   && !(prefixes & PREFIX_ADDR))
13065                 {
13066                   *obufp++ = 'a';
13067                   *obufp++ = 'b';
13068                   *obufp++ = 's';
13069                 }
13070
13071               goto case_S;
13072             }
13073           break;
13074         case 'X':
13075           if (l != 0 || len != 1)
13076             {
13077               SAVE_LAST (*p);
13078               break;
13079             }
13080           if (need_vex
13081               ? vex.prefix == DATA_PREFIX_OPCODE
13082               : prefixes & PREFIX_DATA)
13083             {
13084               *obufp++ = 'd';
13085               used_prefixes |= PREFIX_DATA;
13086             }
13087           else
13088             *obufp++ = 's';
13089           break;
13090         case 'Y':
13091           if (l == 0 && len == 1)
13092             abort ();
13093           else
13094             {
13095               if (l != 1 || len != 2 || last[0] != 'X')
13096                 {
13097                   SAVE_LAST (*p);
13098                   break;
13099                 }
13100               if (!need_vex)
13101                 abort ();
13102               if (intel_syntax
13103                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13104                 break;
13105               switch (vex.length)
13106                 {
13107                 case 128:
13108                   *obufp++ = 'x';
13109                   break;
13110                 case 256:
13111                   *obufp++ = 'y';
13112                   break;
13113                 case 512:
13114                   if (!vex.evex)
13115                 default:
13116                     abort ();
13117                 }
13118             }
13119           break;
13120         case 'W':
13121           if (l == 0 && len == 1)
13122             {
13123               /* operand size flag for cwtl, cbtw */
13124               USED_REX (REX_W);
13125               if (rex & REX_W)
13126                 {
13127                   if (intel_syntax)
13128                     *obufp++ = 'd';
13129                   else
13130                     *obufp++ = 'l';
13131                 }
13132               else if (sizeflag & DFLAG)
13133                 *obufp++ = 'w';
13134               else
13135                 *obufp++ = 'b';
13136               if (!(rex & REX_W))
13137                 used_prefixes |= (prefixes & PREFIX_DATA);
13138             }
13139           else
13140             {
13141               if (l != 1
13142                   || len != 2
13143                   || (last[0] != 'X'
13144                       && last[0] != 'L'))
13145                 {
13146                   SAVE_LAST (*p);
13147                   break;
13148                 }
13149               if (!need_vex)
13150                 abort ();
13151               if (last[0] == 'X')
13152                 *obufp++ = vex.w ? 'd': 's';
13153               else
13154                 *obufp++ = vex.w ? 'q': 'd';
13155             }
13156           break;
13157         case '^':
13158           if (intel_syntax)
13159             break;
13160           if (isa64 == intel64 && (rex & REX_W))
13161             {
13162               USED_REX (REX_W);
13163               *obufp++ = 'q';
13164               break;
13165             }
13166           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13167             {
13168               if (sizeflag & DFLAG)
13169                 *obufp++ = 'l';
13170               else
13171                 *obufp++ = 'w';
13172               used_prefixes |= (prefixes & PREFIX_DATA);
13173             }
13174           break;
13175         case '@':
13176           if (intel_syntax)
13177             break;
13178           if (address_mode == mode_64bit
13179               && (isa64 == intel64
13180                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13181               *obufp++ = 'q';
13182           else if ((prefixes & PREFIX_DATA))
13183             {
13184               if (!(sizeflag & DFLAG))
13185                 *obufp++ = 'w';
13186               used_prefixes |= (prefixes & PREFIX_DATA);
13187             }
13188           break;
13189         }
13190     }
13191   *obufp = 0;
13192   mnemonicendp = obufp;
13193   return 0;
13194 }
13195
13196 static void
13197 oappend (const char *s)
13198 {
13199   obufp = stpcpy (obufp, s);
13200 }
13201
13202 static void
13203 append_seg (void)
13204 {
13205   /* Only print the active segment register.  */
13206   if (!active_seg_prefix)
13207     return;
13208
13209   used_prefixes |= active_seg_prefix;
13210   switch (active_seg_prefix)
13211     {
13212     case PREFIX_CS:
13213       oappend_maybe_intel ("%cs:");
13214       break;
13215     case PREFIX_DS:
13216       oappend_maybe_intel ("%ds:");
13217       break;
13218     case PREFIX_SS:
13219       oappend_maybe_intel ("%ss:");
13220       break;
13221     case PREFIX_ES:
13222       oappend_maybe_intel ("%es:");
13223       break;
13224     case PREFIX_FS:
13225       oappend_maybe_intel ("%fs:");
13226       break;
13227     case PREFIX_GS:
13228       oappend_maybe_intel ("%gs:");
13229       break;
13230     default:
13231       break;
13232     }
13233 }
13234
13235 static void
13236 OP_indirE (int bytemode, int sizeflag)
13237 {
13238   if (!intel_syntax)
13239     oappend ("*");
13240   OP_E (bytemode, sizeflag);
13241 }
13242
13243 static void
13244 print_operand_value (char *buf, int hex, bfd_vma disp)
13245 {
13246   if (address_mode == mode_64bit)
13247     {
13248       if (hex)
13249         {
13250           char tmp[30];
13251           int i;
13252           buf[0] = '0';
13253           buf[1] = 'x';
13254           sprintf_vma (tmp, disp);
13255           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13256           strcpy (buf + 2, tmp + i);
13257         }
13258       else
13259         {
13260           bfd_signed_vma v = disp;
13261           char tmp[30];
13262           int i;
13263           if (v < 0)
13264             {
13265               *(buf++) = '-';
13266               v = -disp;
13267               /* Check for possible overflow on 0x8000000000000000.  */
13268               if (v < 0)
13269                 {
13270                   strcpy (buf, "9223372036854775808");
13271                   return;
13272                 }
13273             }
13274           if (!v)
13275             {
13276               strcpy (buf, "0");
13277               return;
13278             }
13279
13280           i = 0;
13281           tmp[29] = 0;
13282           while (v)
13283             {
13284               tmp[28 - i] = (v % 10) + '0';
13285               v /= 10;
13286               i++;
13287             }
13288           strcpy (buf, tmp + 29 - i);
13289         }
13290     }
13291   else
13292     {
13293       if (hex)
13294         sprintf (buf, "0x%x", (unsigned int) disp);
13295       else
13296         sprintf (buf, "%d", (int) disp);
13297     }
13298 }
13299
13300 /* Put DISP in BUF as signed hex number.  */
13301
13302 static void
13303 print_displacement (char *buf, bfd_vma disp)
13304 {
13305   bfd_signed_vma val = disp;
13306   char tmp[30];
13307   int i, j = 0;
13308
13309   if (val < 0)
13310     {
13311       buf[j++] = '-';
13312       val = -disp;
13313
13314       /* Check for possible overflow.  */
13315       if (val < 0)
13316         {
13317           switch (address_mode)
13318             {
13319             case mode_64bit:
13320               strcpy (buf + j, "0x8000000000000000");
13321               break;
13322             case mode_32bit:
13323               strcpy (buf + j, "0x80000000");
13324               break;
13325             case mode_16bit:
13326               strcpy (buf + j, "0x8000");
13327               break;
13328             }
13329           return;
13330         }
13331     }
13332
13333   buf[j++] = '0';
13334   buf[j++] = 'x';
13335
13336   sprintf_vma (tmp, (bfd_vma) val);
13337   for (i = 0; tmp[i] == '0'; i++)
13338     continue;
13339   if (tmp[i] == '\0')
13340     i--;
13341   strcpy (buf + j, tmp + i);
13342 }
13343
13344 static void
13345 intel_operand_size (int bytemode, int sizeflag)
13346 {
13347   if (vex.evex
13348       && vex.b
13349       && (bytemode == x_mode
13350           || bytemode == evex_half_bcst_xmmq_mode))
13351     {
13352       if (vex.w)
13353         oappend ("QWORD PTR ");
13354       else
13355         oappend ("DWORD PTR ");
13356       return;
13357     }
13358   switch (bytemode)
13359     {
13360     case b_mode:
13361     case b_swap_mode:
13362     case dqb_mode:
13363     case db_mode:
13364       oappend ("BYTE PTR ");
13365       break;
13366     case w_mode:
13367     case dw_mode:
13368     case dqw_mode:
13369       oappend ("WORD PTR ");
13370       break;
13371     case indir_v_mode:
13372       if (address_mode == mode_64bit && isa64 == intel64)
13373         {
13374           oappend ("QWORD PTR ");
13375           break;
13376         }
13377       /* Fall through.  */
13378     case stack_v_mode:
13379       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13380         {
13381           oappend ("QWORD PTR ");
13382           break;
13383         }
13384       /* Fall through.  */
13385     case v_mode:
13386     case v_swap_mode:
13387     case dq_mode:
13388       USED_REX (REX_W);
13389       if (rex & REX_W)
13390         oappend ("QWORD PTR ");
13391       else
13392         {
13393           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13394             oappend ("DWORD PTR ");
13395           else
13396             oappend ("WORD PTR ");
13397           used_prefixes |= (prefixes & PREFIX_DATA);
13398         }
13399       break;
13400     case z_mode:
13401       if ((rex & REX_W) || (sizeflag & DFLAG))
13402         *obufp++ = 'D';
13403       oappend ("WORD PTR ");
13404       if (!(rex & REX_W))
13405         used_prefixes |= (prefixes & PREFIX_DATA);
13406       break;
13407     case a_mode:
13408       if (sizeflag & DFLAG)
13409         oappend ("QWORD PTR ");
13410       else
13411         oappend ("DWORD PTR ");
13412       used_prefixes |= (prefixes & PREFIX_DATA);
13413       break;
13414     case movsxd_mode:
13415       if (!(sizeflag & DFLAG) && isa64 == intel64)
13416         oappend ("WORD PTR ");
13417       else
13418         oappend ("DWORD PTR ");
13419       used_prefixes |= (prefixes & PREFIX_DATA);
13420       break;
13421     case d_mode:
13422     case d_scalar_swap_mode:
13423     case d_swap_mode:
13424     case dqd_mode:
13425       oappend ("DWORD PTR ");
13426       break;
13427     case q_mode:
13428     case q_scalar_swap_mode:
13429     case q_swap_mode:
13430       oappend ("QWORD PTR ");
13431       break;
13432     case m_mode:
13433       if (address_mode == mode_64bit)
13434         oappend ("QWORD PTR ");
13435       else
13436         oappend ("DWORD PTR ");
13437       break;
13438     case f_mode:
13439       if (sizeflag & DFLAG)
13440         oappend ("FWORD PTR ");
13441       else
13442         oappend ("DWORD PTR ");
13443       used_prefixes |= (prefixes & PREFIX_DATA);
13444       break;
13445     case t_mode:
13446       oappend ("TBYTE PTR ");
13447       break;
13448     case x_mode:
13449     case x_swap_mode:
13450     case evex_x_gscat_mode:
13451     case evex_x_nobcst_mode:
13452     case b_scalar_mode:
13453     case w_scalar_mode:
13454       if (need_vex)
13455         {
13456           switch (vex.length)
13457             {
13458             case 128:
13459               oappend ("XMMWORD PTR ");
13460               break;
13461             case 256:
13462               oappend ("YMMWORD PTR ");
13463               break;
13464             case 512:
13465               oappend ("ZMMWORD PTR ");
13466               break;
13467             default:
13468               abort ();
13469             }
13470         }
13471       else
13472         oappend ("XMMWORD PTR ");
13473       break;
13474     case xmm_mode:
13475       oappend ("XMMWORD PTR ");
13476       break;
13477     case ymm_mode:
13478       oappend ("YMMWORD PTR ");
13479       break;
13480     case xmmq_mode:
13481     case evex_half_bcst_xmmq_mode:
13482       if (!need_vex)
13483         abort ();
13484
13485       switch (vex.length)
13486         {
13487         case 128:
13488           oappend ("QWORD PTR ");
13489           break;
13490         case 256:
13491           oappend ("XMMWORD PTR ");
13492           break;
13493         case 512:
13494           oappend ("YMMWORD PTR ");
13495           break;
13496         default:
13497           abort ();
13498         }
13499       break;
13500     case xmm_mb_mode:
13501       if (!need_vex)
13502         abort ();
13503
13504       switch (vex.length)
13505         {
13506         case 128:
13507         case 256:
13508         case 512:
13509           oappend ("BYTE PTR ");
13510           break;
13511         default:
13512           abort ();
13513         }
13514       break;
13515     case xmm_mw_mode:
13516       if (!need_vex)
13517         abort ();
13518
13519       switch (vex.length)
13520         {
13521         case 128:
13522         case 256:
13523         case 512:
13524           oappend ("WORD PTR ");
13525           break;
13526         default:
13527           abort ();
13528         }
13529       break;
13530     case xmm_md_mode:
13531       if (!need_vex)
13532         abort ();
13533
13534       switch (vex.length)
13535         {
13536         case 128:
13537         case 256:
13538         case 512:
13539           oappend ("DWORD PTR ");
13540           break;
13541         default:
13542           abort ();
13543         }
13544       break;
13545     case xmm_mq_mode:
13546       if (!need_vex)
13547         abort ();
13548
13549       switch (vex.length)
13550         {
13551         case 128:
13552         case 256:
13553         case 512:
13554           oappend ("QWORD PTR ");
13555           break;
13556         default:
13557           abort ();
13558         }
13559       break;
13560     case xmmdw_mode:
13561       if (!need_vex)
13562         abort ();
13563
13564       switch (vex.length)
13565         {
13566         case 128:
13567           oappend ("WORD PTR ");
13568           break;
13569         case 256:
13570           oappend ("DWORD PTR ");
13571           break;
13572         case 512:
13573           oappend ("QWORD PTR ");
13574           break;
13575         default:
13576           abort ();
13577         }
13578       break;
13579     case xmmqd_mode:
13580       if (!need_vex)
13581         abort ();
13582
13583       switch (vex.length)
13584         {
13585         case 128:
13586           oappend ("DWORD PTR ");
13587           break;
13588         case 256:
13589           oappend ("QWORD PTR ");
13590           break;
13591         case 512:
13592           oappend ("XMMWORD PTR ");
13593           break;
13594         default:
13595           abort ();
13596         }
13597       break;
13598     case ymmq_mode:
13599       if (!need_vex)
13600         abort ();
13601
13602       switch (vex.length)
13603         {
13604         case 128:
13605           oappend ("QWORD PTR ");
13606           break;
13607         case 256:
13608           oappend ("YMMWORD PTR ");
13609           break;
13610         case 512:
13611           oappend ("ZMMWORD PTR ");
13612           break;
13613         default:
13614           abort ();
13615         }
13616       break;
13617     case ymmxmm_mode:
13618       if (!need_vex)
13619         abort ();
13620
13621       switch (vex.length)
13622         {
13623         case 128:
13624         case 256:
13625           oappend ("XMMWORD PTR ");
13626           break;
13627         default:
13628           abort ();
13629         }
13630       break;
13631     case o_mode:
13632       oappend ("OWORD PTR ");
13633       break;
13634     case vex_scalar_w_dq_mode:
13635       if (!need_vex)
13636         abort ();
13637
13638       if (vex.w)
13639         oappend ("QWORD PTR ");
13640       else
13641         oappend ("DWORD PTR ");
13642       break;
13643     case vex_vsib_d_w_dq_mode:
13644     case vex_vsib_q_w_dq_mode:
13645       if (!need_vex)
13646         abort ();
13647
13648       if (!vex.evex)
13649         {
13650           if (vex.w)
13651             oappend ("QWORD PTR ");
13652           else
13653             oappend ("DWORD PTR ");
13654         }
13655       else
13656         {
13657           switch (vex.length)
13658             {
13659             case 128:
13660               oappend ("XMMWORD PTR ");
13661               break;
13662             case 256:
13663               oappend ("YMMWORD PTR ");
13664               break;
13665             case 512:
13666               oappend ("ZMMWORD PTR ");
13667               break;
13668             default:
13669               abort ();
13670             }
13671         }
13672       break;
13673     case vex_vsib_q_w_d_mode:
13674     case vex_vsib_d_w_d_mode:
13675       if (!need_vex || !vex.evex)
13676         abort ();
13677
13678       switch (vex.length)
13679         {
13680         case 128:
13681           oappend ("QWORD PTR ");
13682           break;
13683         case 256:
13684           oappend ("XMMWORD PTR ");
13685           break;
13686         case 512:
13687           oappend ("YMMWORD PTR ");
13688           break;
13689         default:
13690           abort ();
13691         }
13692
13693       break;
13694     case mask_bd_mode:
13695       if (!need_vex || vex.length != 128)
13696         abort ();
13697       if (vex.w)
13698         oappend ("DWORD PTR ");
13699       else
13700         oappend ("BYTE PTR ");
13701       break;
13702     case mask_mode:
13703       if (!need_vex)
13704         abort ();
13705       if (vex.w)
13706         oappend ("QWORD PTR ");
13707       else
13708         oappend ("WORD PTR ");
13709       break;
13710     case v_bnd_mode:
13711     case v_bndmk_mode:
13712     default:
13713       break;
13714     }
13715 }
13716
13717 static void
13718 OP_E_register (int bytemode, int sizeflag)
13719 {
13720   int reg = modrm.rm;
13721   const char **names;
13722
13723   USED_REX (REX_B);
13724   if ((rex & REX_B))
13725     reg += 8;
13726
13727   if ((sizeflag & SUFFIX_ALWAYS)
13728       && (bytemode == b_swap_mode
13729           || bytemode == bnd_swap_mode
13730           || bytemode == v_swap_mode))
13731     swap_operand ();
13732
13733   switch (bytemode)
13734     {
13735     case b_mode:
13736     case b_swap_mode:
13737       USED_REX (0);
13738       if (rex)
13739         names = names8rex;
13740       else
13741         names = names8;
13742       break;
13743     case w_mode:
13744       names = names16;
13745       break;
13746     case d_mode:
13747     case dw_mode:
13748     case db_mode:
13749       names = names32;
13750       break;
13751     case q_mode:
13752       names = names64;
13753       break;
13754     case m_mode:
13755     case v_bnd_mode:
13756       names = address_mode == mode_64bit ? names64 : names32;
13757       break;
13758     case bnd_mode:
13759     case bnd_swap_mode:
13760       if (reg > 0x3)
13761         {
13762           oappend ("(bad)");
13763           return;
13764         }
13765       names = names_bnd;
13766       break;
13767     case indir_v_mode:
13768       if (address_mode == mode_64bit && isa64 == intel64)
13769         {
13770           names = names64;
13771           break;
13772         }
13773       /* Fall through.  */
13774     case stack_v_mode:
13775       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13776         {
13777           names = names64;
13778           break;
13779         }
13780       bytemode = v_mode;
13781       /* Fall through.  */
13782     case v_mode:
13783     case v_swap_mode:
13784     case dq_mode:
13785     case dqb_mode:
13786     case dqd_mode:
13787     case dqw_mode:
13788       USED_REX (REX_W);
13789       if (rex & REX_W)
13790         names = names64;
13791       else
13792         {
13793           if ((sizeflag & DFLAG)
13794               || (bytemode != v_mode
13795                   && bytemode != v_swap_mode))
13796             names = names32;
13797           else
13798             names = names16;
13799           used_prefixes |= (prefixes & PREFIX_DATA);
13800         }
13801       break;
13802     case movsxd_mode:
13803       if (!(sizeflag & DFLAG) && isa64 == intel64)
13804         names = names16;
13805       else
13806         names = names32;
13807       used_prefixes |= (prefixes & PREFIX_DATA);
13808       break;
13809     case va_mode:
13810       names = (address_mode == mode_64bit
13811                ? names64 : names32);
13812       if (!(prefixes & PREFIX_ADDR))
13813         names = (address_mode == mode_16bit
13814                      ? names16 : names);
13815       else
13816         {
13817           /* Remove "addr16/addr32".  */
13818           all_prefixes[last_addr_prefix] = 0;
13819           names = (address_mode != mode_32bit
13820                        ? names32 : names16);
13821           used_prefixes |= PREFIX_ADDR;
13822         }
13823       break;
13824     case mask_bd_mode:
13825     case mask_mode:
13826       if (reg > 0x7)
13827         {
13828           oappend ("(bad)");
13829           return;
13830         }
13831       names = names_mask;
13832       break;
13833     case 0:
13834       return;
13835     default:
13836       oappend (INTERNAL_DISASSEMBLER_ERROR);
13837       return;
13838     }
13839   oappend (names[reg]);
13840 }
13841
13842 static void
13843 OP_E_memory (int bytemode, int sizeflag)
13844 {
13845   bfd_vma disp = 0;
13846   int add = (rex & REX_B) ? 8 : 0;
13847   int riprel = 0;
13848   int shift;
13849
13850   if (vex.evex)
13851     {
13852       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13853       if (vex.b
13854           && bytemode != x_mode
13855           && bytemode != xmmq_mode
13856           && bytemode != evex_half_bcst_xmmq_mode)
13857         {
13858           BadOp ();
13859           return;
13860         }
13861       switch (bytemode)
13862         {
13863         case dqw_mode:
13864         case dw_mode:
13865           shift = 1;
13866           break;
13867         case dqb_mode:
13868         case db_mode:
13869           shift = 0;
13870           break;
13871         case dq_mode:
13872           if (address_mode != mode_64bit)
13873             {
13874               shift = 2;
13875               break;
13876             }
13877             /* fall through */
13878         case vex_scalar_w_dq_mode:
13879         case vex_vsib_d_w_dq_mode:
13880         case vex_vsib_d_w_d_mode:
13881         case vex_vsib_q_w_dq_mode:
13882         case vex_vsib_q_w_d_mode:
13883         case evex_x_gscat_mode:
13884           shift = vex.w ? 3 : 2;
13885           break;
13886         case x_mode:
13887         case evex_half_bcst_xmmq_mode:
13888         case xmmq_mode:
13889           if (vex.b)
13890             {
13891               shift = vex.w ? 3 : 2;
13892               break;
13893             }
13894           /* Fall through.  */
13895         case xmmqd_mode:
13896         case xmmdw_mode:
13897         case ymmq_mode:
13898         case evex_x_nobcst_mode:
13899         case x_swap_mode:
13900           switch (vex.length)
13901             {
13902             case 128:
13903               shift = 4;
13904               break;
13905             case 256:
13906               shift = 5;
13907               break;
13908             case 512:
13909               shift = 6;
13910               break;
13911             default:
13912               abort ();
13913             }
13914           break;
13915         case ymm_mode:
13916           shift = 5;
13917           break;
13918         case xmm_mode:
13919           shift = 4;
13920           break;
13921         case xmm_mq_mode:
13922         case q_mode:
13923         case q_swap_mode:
13924         case q_scalar_swap_mode:
13925           shift = 3;
13926           break;
13927         case dqd_mode:
13928         case xmm_md_mode:
13929         case d_mode:
13930         case d_swap_mode:
13931         case d_scalar_swap_mode:
13932           shift = 2;
13933           break;
13934         case w_scalar_mode:
13935         case xmm_mw_mode:
13936           shift = 1;
13937           break;
13938         case b_scalar_mode:
13939         case xmm_mb_mode:
13940           shift = 0;
13941           break;
13942         default:
13943           abort ();
13944         }
13945       /* Make necessary corrections to shift for modes that need it.
13946          For these modes we currently have shift 4, 5 or 6 depending on
13947          vex.length (it corresponds to xmmword, ymmword or zmmword
13948          operand).  We might want to make it 3, 4 or 5 (e.g. for
13949          xmmq_mode).  In case of broadcast enabled the corrections
13950          aren't needed, as element size is always 32 or 64 bits.  */
13951       if (!vex.b
13952           && (bytemode == xmmq_mode
13953               || bytemode == evex_half_bcst_xmmq_mode))
13954         shift -= 1;
13955       else if (bytemode == xmmqd_mode)
13956         shift -= 2;
13957       else if (bytemode == xmmdw_mode)
13958         shift -= 3;
13959       else if (bytemode == ymmq_mode && vex.length == 128)
13960         shift -= 1;
13961     }
13962   else
13963     shift = 0;
13964
13965   USED_REX (REX_B);
13966   if (intel_syntax)
13967     intel_operand_size (bytemode, sizeflag);
13968   append_seg ();
13969
13970   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13971     {
13972       /* 32/64 bit address mode */
13973       int havedisp;
13974       int havesib;
13975       int havebase;
13976       int haveindex;
13977       int needindex;
13978       int needaddr32;
13979       int base, rbase;
13980       int vindex = 0;
13981       int scale = 0;
13982       int addr32flag = !((sizeflag & AFLAG)
13983                          || bytemode == v_bnd_mode
13984                          || bytemode == v_bndmk_mode
13985                          || bytemode == bnd_mode
13986                          || bytemode == bnd_swap_mode);
13987       const char **indexes64 = names64;
13988       const char **indexes32 = names32;
13989
13990       havesib = 0;
13991       havebase = 1;
13992       haveindex = 0;
13993       base = modrm.rm;
13994
13995       if (base == 4)
13996         {
13997           havesib = 1;
13998           vindex = sib.index;
13999           USED_REX (REX_X);
14000           if (rex & REX_X)
14001             vindex += 8;
14002           switch (bytemode)
14003             {
14004             case vex_vsib_d_w_dq_mode:
14005             case vex_vsib_d_w_d_mode:
14006             case vex_vsib_q_w_dq_mode:
14007             case vex_vsib_q_w_d_mode:
14008               if (!need_vex)
14009                 abort ();
14010               if (vex.evex)
14011                 {
14012                   if (!vex.v)
14013                     vindex += 16;
14014                 }
14015
14016               haveindex = 1;
14017               switch (vex.length)
14018                 {
14019                 case 128:
14020                   indexes64 = indexes32 = names_xmm;
14021                   break;
14022                 case 256:
14023                   if (!vex.w
14024                       || bytemode == vex_vsib_q_w_dq_mode
14025                       || bytemode == vex_vsib_q_w_d_mode)
14026                     indexes64 = indexes32 = names_ymm;
14027                   else
14028                     indexes64 = indexes32 = names_xmm;
14029                   break;
14030                 case 512:
14031                   if (!vex.w
14032                       || bytemode == vex_vsib_q_w_dq_mode
14033                       || bytemode == vex_vsib_q_w_d_mode)
14034                     indexes64 = indexes32 = names_zmm;
14035                   else
14036                     indexes64 = indexes32 = names_ymm;
14037                   break;
14038                 default:
14039                   abort ();
14040                 }
14041               break;
14042             default:
14043               haveindex = vindex != 4;
14044               break;
14045             }
14046           scale = sib.scale;
14047           base = sib.base;
14048           codep++;
14049         }
14050       rbase = base + add;
14051
14052       switch (modrm.mod)
14053         {
14054         case 0:
14055           if (base == 5)
14056             {
14057               havebase = 0;
14058               if (address_mode == mode_64bit && !havesib)
14059                 riprel = 1;
14060               disp = get32s ();
14061               if (riprel && bytemode == v_bndmk_mode)
14062                 {
14063                   oappend ("(bad)");
14064                   return;
14065                 }
14066             }
14067           break;
14068         case 1:
14069           FETCH_DATA (the_info, codep + 1);
14070           disp = *codep++;
14071           if ((disp & 0x80) != 0)
14072             disp -= 0x100;
14073           if (vex.evex && shift > 0)
14074             disp <<= shift;
14075           break;
14076         case 2:
14077           disp = get32s ();
14078           break;
14079         }
14080
14081       needindex = 0;
14082       needaddr32 = 0;
14083       if (havesib
14084           && !havebase
14085           && !haveindex
14086           && address_mode != mode_16bit)
14087         {
14088           if (address_mode == mode_64bit)
14089             {
14090               /* Display eiz instead of addr32.  */
14091               needindex = addr32flag;
14092               needaddr32 = 1;
14093             }
14094           else
14095             {
14096               /* In 32-bit mode, we need index register to tell [offset]
14097                  from [eiz*1 + offset].  */
14098               needindex = 1;
14099             }
14100         }
14101
14102       havedisp = (havebase
14103                   || needindex
14104                   || (havesib && (haveindex || scale != 0)));
14105
14106       if (!intel_syntax)
14107         if (modrm.mod != 0 || base == 5)
14108           {
14109             if (havedisp || riprel)
14110               print_displacement (scratchbuf, disp);
14111             else
14112               print_operand_value (scratchbuf, 1, disp);
14113             oappend (scratchbuf);
14114             if (riprel)
14115               {
14116                 set_op (disp, 1);
14117                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14118               }
14119           }
14120
14121       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14122           && (address_mode != mode_64bit
14123               || ((bytemode != v_bnd_mode)
14124                   && (bytemode != v_bndmk_mode)
14125                   && (bytemode != bnd_mode)
14126                   && (bytemode != bnd_swap_mode))))
14127         used_prefixes |= PREFIX_ADDR;
14128
14129       if (havedisp || (intel_syntax && riprel))
14130         {
14131           *obufp++ = open_char;
14132           if (intel_syntax && riprel)
14133             {
14134               set_op (disp, 1);
14135               oappend (!addr32flag ? "rip" : "eip");
14136             }
14137           *obufp = '\0';
14138           if (havebase)
14139             oappend (address_mode == mode_64bit && !addr32flag
14140                      ? names64[rbase] : names32[rbase]);
14141           if (havesib)
14142             {
14143               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14144                  print index to tell base + index from base.  */
14145               if (scale != 0
14146                   || needindex
14147                   || haveindex
14148                   || (havebase && base != ESP_REG_NUM))
14149                 {
14150                   if (!intel_syntax || havebase)
14151                     {
14152                       *obufp++ = separator_char;
14153                       *obufp = '\0';
14154                     }
14155                   if (haveindex)
14156                     oappend (address_mode == mode_64bit && !addr32flag
14157                              ? indexes64[vindex] : indexes32[vindex]);
14158                   else
14159                     oappend (address_mode == mode_64bit && !addr32flag
14160                              ? index64 : index32);
14161
14162                   *obufp++ = scale_char;
14163                   *obufp = '\0';
14164                   sprintf (scratchbuf, "%d", 1 << scale);
14165                   oappend (scratchbuf);
14166                 }
14167             }
14168           if (intel_syntax
14169               && (disp || modrm.mod != 0 || base == 5))
14170             {
14171               if (!havedisp || (bfd_signed_vma) disp >= 0)
14172                 {
14173                   *obufp++ = '+';
14174                   *obufp = '\0';
14175                 }
14176               else if (modrm.mod != 1 && disp != -disp)
14177                 {
14178                   *obufp++ = '-';
14179                   *obufp = '\0';
14180                   disp = - (bfd_signed_vma) disp;
14181                 }
14182
14183               if (havedisp)
14184                 print_displacement (scratchbuf, disp);
14185               else
14186                 print_operand_value (scratchbuf, 1, disp);
14187               oappend (scratchbuf);
14188             }
14189
14190           *obufp++ = close_char;
14191           *obufp = '\0';
14192         }
14193       else if (intel_syntax)
14194         {
14195           if (modrm.mod != 0 || base == 5)
14196             {
14197               if (!active_seg_prefix)
14198                 {
14199                   oappend (names_seg[ds_reg - es_reg]);
14200                   oappend (":");
14201                 }
14202               print_operand_value (scratchbuf, 1, disp);
14203               oappend (scratchbuf);
14204             }
14205         }
14206     }
14207   else if (bytemode == v_bnd_mode
14208            || bytemode == v_bndmk_mode
14209            || bytemode == bnd_mode
14210            || bytemode == bnd_swap_mode)
14211     {
14212       oappend ("(bad)");
14213       return;
14214     }
14215   else
14216     {
14217       /* 16 bit address mode */
14218       used_prefixes |= prefixes & PREFIX_ADDR;
14219       switch (modrm.mod)
14220         {
14221         case 0:
14222           if (modrm.rm == 6)
14223             {
14224               disp = get16 ();
14225               if ((disp & 0x8000) != 0)
14226                 disp -= 0x10000;
14227             }
14228           break;
14229         case 1:
14230           FETCH_DATA (the_info, codep + 1);
14231           disp = *codep++;
14232           if ((disp & 0x80) != 0)
14233             disp -= 0x100;
14234           if (vex.evex && shift > 0)
14235             disp <<= shift;
14236           break;
14237         case 2:
14238           disp = get16 ();
14239           if ((disp & 0x8000) != 0)
14240             disp -= 0x10000;
14241           break;
14242         }
14243
14244       if (!intel_syntax)
14245         if (modrm.mod != 0 || modrm.rm == 6)
14246           {
14247             print_displacement (scratchbuf, disp);
14248             oappend (scratchbuf);
14249           }
14250
14251       if (modrm.mod != 0 || modrm.rm != 6)
14252         {
14253           *obufp++ = open_char;
14254           *obufp = '\0';
14255           oappend (index16[modrm.rm]);
14256           if (intel_syntax
14257               && (disp || modrm.mod != 0 || modrm.rm == 6))
14258             {
14259               if ((bfd_signed_vma) disp >= 0)
14260                 {
14261                   *obufp++ = '+';
14262                   *obufp = '\0';
14263                 }
14264               else if (modrm.mod != 1)
14265                 {
14266                   *obufp++ = '-';
14267                   *obufp = '\0';
14268                   disp = - (bfd_signed_vma) disp;
14269                 }
14270
14271               print_displacement (scratchbuf, disp);
14272               oappend (scratchbuf);
14273             }
14274
14275           *obufp++ = close_char;
14276           *obufp = '\0';
14277         }
14278       else if (intel_syntax)
14279         {
14280           if (!active_seg_prefix)
14281             {
14282               oappend (names_seg[ds_reg - es_reg]);
14283               oappend (":");
14284             }
14285           print_operand_value (scratchbuf, 1, disp & 0xffff);
14286           oappend (scratchbuf);
14287         }
14288     }
14289   if (vex.evex && vex.b
14290       && (bytemode == x_mode
14291           || bytemode == xmmq_mode
14292           || bytemode == evex_half_bcst_xmmq_mode))
14293     {
14294       if (vex.w
14295           || bytemode == xmmq_mode
14296           || bytemode == evex_half_bcst_xmmq_mode)
14297         {
14298           switch (vex.length)
14299             {
14300             case 128:
14301               oappend ("{1to2}");
14302               break;
14303             case 256:
14304               oappend ("{1to4}");
14305               break;
14306             case 512:
14307               oappend ("{1to8}");
14308               break;
14309             default:
14310               abort ();
14311             }
14312         }
14313       else
14314         {
14315           switch (vex.length)
14316             {
14317             case 128:
14318               oappend ("{1to4}");
14319               break;
14320             case 256:
14321               oappend ("{1to8}");
14322               break;
14323             case 512:
14324               oappend ("{1to16}");
14325               break;
14326             default:
14327               abort ();
14328             }
14329         }
14330     }
14331 }
14332
14333 static void
14334 OP_E (int bytemode, int sizeflag)
14335 {
14336   /* Skip mod/rm byte.  */
14337   MODRM_CHECK;
14338   codep++;
14339
14340   if (modrm.mod == 3)
14341     OP_E_register (bytemode, sizeflag);
14342   else
14343     OP_E_memory (bytemode, sizeflag);
14344 }
14345
14346 static void
14347 OP_G (int bytemode, int sizeflag)
14348 {
14349   int add = 0;
14350   const char **names;
14351   USED_REX (REX_R);
14352   if (rex & REX_R)
14353     add += 8;
14354   switch (bytemode)
14355     {
14356     case b_mode:
14357       USED_REX (0);
14358       if (rex)
14359         oappend (names8rex[modrm.reg + add]);
14360       else
14361         oappend (names8[modrm.reg + add]);
14362       break;
14363     case w_mode:
14364       oappend (names16[modrm.reg + add]);
14365       break;
14366     case d_mode:
14367     case db_mode:
14368     case dw_mode:
14369       oappend (names32[modrm.reg + add]);
14370       break;
14371     case q_mode:
14372       oappend (names64[modrm.reg + add]);
14373       break;
14374     case bnd_mode:
14375       if (modrm.reg > 0x3)
14376         {
14377           oappend ("(bad)");
14378           return;
14379         }
14380       oappend (names_bnd[modrm.reg]);
14381       break;
14382     case v_mode:
14383     case dq_mode:
14384     case dqb_mode:
14385     case dqd_mode:
14386     case dqw_mode:
14387     case movsxd_mode:
14388       USED_REX (REX_W);
14389       if (rex & REX_W)
14390         oappend (names64[modrm.reg + add]);
14391       else
14392         {
14393           if ((sizeflag & DFLAG)
14394               || (bytemode != v_mode && bytemode != movsxd_mode))
14395             oappend (names32[modrm.reg + add]);
14396           else
14397             oappend (names16[modrm.reg + add]);
14398           used_prefixes |= (prefixes & PREFIX_DATA);
14399         }
14400       break;
14401     case va_mode:
14402       names = (address_mode == mode_64bit
14403                ? names64 : names32);
14404       if (!(prefixes & PREFIX_ADDR))
14405         {
14406           if (address_mode == mode_16bit)
14407             names = names16;
14408         }
14409       else
14410         {
14411           /* Remove "addr16/addr32".  */
14412           all_prefixes[last_addr_prefix] = 0;
14413           names = (address_mode != mode_32bit
14414                        ? names32 : names16);
14415           used_prefixes |= PREFIX_ADDR;
14416         }
14417       oappend (names[modrm.reg + add]);
14418       break;
14419     case m_mode:
14420       if (address_mode == mode_64bit)
14421         oappend (names64[modrm.reg + add]);
14422       else
14423         oappend (names32[modrm.reg + add]);
14424       break;
14425     case mask_bd_mode:
14426     case mask_mode:
14427       if ((modrm.reg + add) > 0x7)
14428         {
14429           oappend ("(bad)");
14430           return;
14431         }
14432       oappend (names_mask[modrm.reg + add]);
14433       break;
14434     default:
14435       oappend (INTERNAL_DISASSEMBLER_ERROR);
14436       break;
14437     }
14438 }
14439
14440 static bfd_vma
14441 get64 (void)
14442 {
14443   bfd_vma x;
14444 #ifdef BFD64
14445   unsigned int a;
14446   unsigned int b;
14447
14448   FETCH_DATA (the_info, codep + 8);
14449   a = *codep++ & 0xff;
14450   a |= (*codep++ & 0xff) << 8;
14451   a |= (*codep++ & 0xff) << 16;
14452   a |= (*codep++ & 0xffu) << 24;
14453   b = *codep++ & 0xff;
14454   b |= (*codep++ & 0xff) << 8;
14455   b |= (*codep++ & 0xff) << 16;
14456   b |= (*codep++ & 0xffu) << 24;
14457   x = a + ((bfd_vma) b << 32);
14458 #else
14459   abort ();
14460   x = 0;
14461 #endif
14462   return x;
14463 }
14464
14465 static bfd_signed_vma
14466 get32 (void)
14467 {
14468   bfd_signed_vma x = 0;
14469
14470   FETCH_DATA (the_info, codep + 4);
14471   x = *codep++ & (bfd_signed_vma) 0xff;
14472   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14473   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14474   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14475   return x;
14476 }
14477
14478 static bfd_signed_vma
14479 get32s (void)
14480 {
14481   bfd_signed_vma x = 0;
14482
14483   FETCH_DATA (the_info, codep + 4);
14484   x = *codep++ & (bfd_signed_vma) 0xff;
14485   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14486   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14487   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14488
14489   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14490
14491   return x;
14492 }
14493
14494 static int
14495 get16 (void)
14496 {
14497   int x = 0;
14498
14499   FETCH_DATA (the_info, codep + 2);
14500   x = *codep++ & 0xff;
14501   x |= (*codep++ & 0xff) << 8;
14502   return x;
14503 }
14504
14505 static void
14506 set_op (bfd_vma op, int riprel)
14507 {
14508   op_index[op_ad] = op_ad;
14509   if (address_mode == mode_64bit)
14510     {
14511       op_address[op_ad] = op;
14512       op_riprel[op_ad] = riprel;
14513     }
14514   else
14515     {
14516       /* Mask to get a 32-bit address.  */
14517       op_address[op_ad] = op & 0xffffffff;
14518       op_riprel[op_ad] = riprel & 0xffffffff;
14519     }
14520 }
14521
14522 static void
14523 OP_REG (int code, int sizeflag)
14524 {
14525   const char *s;
14526   int add;
14527
14528   switch (code)
14529     {
14530     case es_reg: case ss_reg: case cs_reg:
14531     case ds_reg: case fs_reg: case gs_reg:
14532       oappend (names_seg[code - es_reg]);
14533       return;
14534     }
14535
14536   USED_REX (REX_B);
14537   if (rex & REX_B)
14538     add = 8;
14539   else
14540     add = 0;
14541
14542   switch (code)
14543     {
14544     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14545     case sp_reg: case bp_reg: case si_reg: case di_reg:
14546       s = names16[code - ax_reg + add];
14547       break;
14548     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14549     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14550       USED_REX (0);
14551       if (rex)
14552         s = names8rex[code - al_reg + add];
14553       else
14554         s = names8[code - al_reg];
14555       break;
14556     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14557     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14558       if (address_mode == mode_64bit
14559           && ((sizeflag & DFLAG) || (rex & REX_W)))
14560         {
14561           s = names64[code - rAX_reg + add];
14562           break;
14563         }
14564       code += eAX_reg - rAX_reg;
14565       /* Fall through.  */
14566     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14567     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14568       USED_REX (REX_W);
14569       if (rex & REX_W)
14570         s = names64[code - eAX_reg + add];
14571       else
14572         {
14573           if (sizeflag & DFLAG)
14574             s = names32[code - eAX_reg + add];
14575           else
14576             s = names16[code - eAX_reg + add];
14577           used_prefixes |= (prefixes & PREFIX_DATA);
14578         }
14579       break;
14580     default:
14581       s = INTERNAL_DISASSEMBLER_ERROR;
14582       break;
14583     }
14584   oappend (s);
14585 }
14586
14587 static void
14588 OP_IMREG (int code, int sizeflag)
14589 {
14590   const char *s;
14591
14592   switch (code)
14593     {
14594     case indir_dx_reg:
14595       if (intel_syntax)
14596         s = "dx";
14597       else
14598         s = "(%dx)";
14599       break;
14600     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14601     case sp_reg: case bp_reg: case si_reg: case di_reg:
14602       s = names16[code - ax_reg];
14603       break;
14604     case es_reg: case ss_reg: case cs_reg:
14605     case ds_reg: case fs_reg: case gs_reg:
14606       s = names_seg[code - es_reg];
14607       break;
14608     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14609     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14610       USED_REX (0);
14611       if (rex)
14612         s = names8rex[code - al_reg];
14613       else
14614         s = names8[code - al_reg];
14615       break;
14616     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14617     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14618       USED_REX (REX_W);
14619       if (rex & REX_W)
14620         s = names64[code - eAX_reg];
14621       else
14622         {
14623           if (sizeflag & DFLAG)
14624             s = names32[code - eAX_reg];
14625           else
14626             s = names16[code - eAX_reg];
14627           used_prefixes |= (prefixes & PREFIX_DATA);
14628         }
14629       break;
14630     case z_mode_ax_reg:
14631       if ((rex & REX_W) || (sizeflag & DFLAG))
14632         s = *names32;
14633       else
14634         s = *names16;
14635       if (!(rex & REX_W))
14636         used_prefixes |= (prefixes & PREFIX_DATA);
14637       break;
14638     default:
14639       s = INTERNAL_DISASSEMBLER_ERROR;
14640       break;
14641     }
14642   oappend (s);
14643 }
14644
14645 static void
14646 OP_I (int bytemode, int sizeflag)
14647 {
14648   bfd_signed_vma op;
14649   bfd_signed_vma mask = -1;
14650
14651   switch (bytemode)
14652     {
14653     case b_mode:
14654       FETCH_DATA (the_info, codep + 1);
14655       op = *codep++;
14656       mask = 0xff;
14657       break;
14658     case v_mode:
14659       USED_REX (REX_W);
14660       if (rex & REX_W)
14661         op = get32s ();
14662       else
14663         {
14664           if (sizeflag & DFLAG)
14665             {
14666               op = get32 ();
14667               mask = 0xffffffff;
14668             }
14669           else
14670             {
14671               op = get16 ();
14672               mask = 0xfffff;
14673             }
14674           used_prefixes |= (prefixes & PREFIX_DATA);
14675         }
14676       break;
14677     case d_mode:
14678       mask = 0xffffffff;
14679       op = get32 ();
14680       break;
14681     case w_mode:
14682       mask = 0xfffff;
14683       op = get16 ();
14684       break;
14685     case const_1_mode:
14686       if (intel_syntax)
14687         oappend ("1");
14688       return;
14689     default:
14690       oappend (INTERNAL_DISASSEMBLER_ERROR);
14691       return;
14692     }
14693
14694   op &= mask;
14695   scratchbuf[0] = '$';
14696   print_operand_value (scratchbuf + 1, 1, op);
14697   oappend_maybe_intel (scratchbuf);
14698   scratchbuf[0] = '\0';
14699 }
14700
14701 static void
14702 OP_I64 (int bytemode, int sizeflag)
14703 {
14704   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14705     {
14706       OP_I (bytemode, sizeflag);
14707       return;
14708     }
14709
14710   USED_REX (REX_W);
14711
14712   scratchbuf[0] = '$';
14713   print_operand_value (scratchbuf + 1, 1, get64 ());
14714   oappend_maybe_intel (scratchbuf);
14715   scratchbuf[0] = '\0';
14716 }
14717
14718 static void
14719 OP_sI (int bytemode, int sizeflag)
14720 {
14721   bfd_signed_vma op;
14722
14723   switch (bytemode)
14724     {
14725     case b_mode:
14726     case b_T_mode:
14727       FETCH_DATA (the_info, codep + 1);
14728       op = *codep++;
14729       if ((op & 0x80) != 0)
14730         op -= 0x100;
14731       if (bytemode == b_T_mode)
14732         {
14733           if (address_mode != mode_64bit
14734               || !((sizeflag & DFLAG) || (rex & REX_W)))
14735             {
14736               /* The operand-size prefix is overridden by a REX prefix.  */
14737               if ((sizeflag & DFLAG) || (rex & REX_W))
14738                 op &= 0xffffffff;
14739               else
14740                 op &= 0xffff;
14741           }
14742         }
14743       else
14744         {
14745           if (!(rex & REX_W))
14746             {
14747               if (sizeflag & DFLAG)
14748                 op &= 0xffffffff;
14749               else
14750                 op &= 0xffff;
14751             }
14752         }
14753       break;
14754     case v_mode:
14755       /* The operand-size prefix is overridden by a REX prefix.  */
14756       if ((sizeflag & DFLAG) || (rex & REX_W))
14757         op = get32s ();
14758       else
14759         op = get16 ();
14760       break;
14761     default:
14762       oappend (INTERNAL_DISASSEMBLER_ERROR);
14763       return;
14764     }
14765
14766   scratchbuf[0] = '$';
14767   print_operand_value (scratchbuf + 1, 1, op);
14768   oappend_maybe_intel (scratchbuf);
14769 }
14770
14771 static void
14772 OP_J (int bytemode, int sizeflag)
14773 {
14774   bfd_vma disp;
14775   bfd_vma mask = -1;
14776   bfd_vma segment = 0;
14777
14778   switch (bytemode)
14779     {
14780     case b_mode:
14781       FETCH_DATA (the_info, codep + 1);
14782       disp = *codep++;
14783       if ((disp & 0x80) != 0)
14784         disp -= 0x100;
14785       break;
14786     case v_mode:
14787       if (isa64 != intel64)
14788     case dqw_mode:
14789         USED_REX (REX_W);
14790       if ((sizeflag & DFLAG)
14791           || (address_mode == mode_64bit
14792               && ((isa64 == intel64 && bytemode != dqw_mode)
14793                   || (rex & REX_W))))
14794         disp = get32s ();
14795       else
14796         {
14797           disp = get16 ();
14798           if ((disp & 0x8000) != 0)
14799             disp -= 0x10000;
14800           /* In 16bit mode, address is wrapped around at 64k within
14801              the same segment.  Otherwise, a data16 prefix on a jump
14802              instruction means that the pc is masked to 16 bits after
14803              the displacement is added!  */
14804           mask = 0xffff;
14805           if ((prefixes & PREFIX_DATA) == 0)
14806             segment = ((start_pc + (codep - start_codep))
14807                        & ~((bfd_vma) 0xffff));
14808         }
14809       if (address_mode != mode_64bit
14810           || (isa64 != intel64 && !(rex & REX_W)))
14811         used_prefixes |= (prefixes & PREFIX_DATA);
14812       break;
14813     default:
14814       oappend (INTERNAL_DISASSEMBLER_ERROR);
14815       return;
14816     }
14817   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14818   set_op (disp, 0);
14819   print_operand_value (scratchbuf, 1, disp);
14820   oappend (scratchbuf);
14821 }
14822
14823 static void
14824 OP_SEG (int bytemode, int sizeflag)
14825 {
14826   if (bytemode == w_mode)
14827     oappend (names_seg[modrm.reg]);
14828   else
14829     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14830 }
14831
14832 static void
14833 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14834 {
14835   int seg, offset;
14836
14837   if (sizeflag & DFLAG)
14838     {
14839       offset = get32 ();
14840       seg = get16 ();
14841     }
14842   else
14843     {
14844       offset = get16 ();
14845       seg = get16 ();
14846     }
14847   used_prefixes |= (prefixes & PREFIX_DATA);
14848   if (intel_syntax)
14849     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14850   else
14851     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14852   oappend (scratchbuf);
14853 }
14854
14855 static void
14856 OP_OFF (int bytemode, int sizeflag)
14857 {
14858   bfd_vma off;
14859
14860   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14861     intel_operand_size (bytemode, sizeflag);
14862   append_seg ();
14863
14864   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14865     off = get32 ();
14866   else
14867     off = get16 ();
14868
14869   if (intel_syntax)
14870     {
14871       if (!active_seg_prefix)
14872         {
14873           oappend (names_seg[ds_reg - es_reg]);
14874           oappend (":");
14875         }
14876     }
14877   print_operand_value (scratchbuf, 1, off);
14878   oappend (scratchbuf);
14879 }
14880
14881 static void
14882 OP_OFF64 (int bytemode, int sizeflag)
14883 {
14884   bfd_vma off;
14885
14886   if (address_mode != mode_64bit
14887       || (prefixes & PREFIX_ADDR))
14888     {
14889       OP_OFF (bytemode, sizeflag);
14890       return;
14891     }
14892
14893   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14894     intel_operand_size (bytemode, sizeflag);
14895   append_seg ();
14896
14897   off = get64 ();
14898
14899   if (intel_syntax)
14900     {
14901       if (!active_seg_prefix)
14902         {
14903           oappend (names_seg[ds_reg - es_reg]);
14904           oappend (":");
14905         }
14906     }
14907   print_operand_value (scratchbuf, 1, off);
14908   oappend (scratchbuf);
14909 }
14910
14911 static void
14912 ptr_reg (int code, int sizeflag)
14913 {
14914   const char *s;
14915
14916   *obufp++ = open_char;
14917   used_prefixes |= (prefixes & PREFIX_ADDR);
14918   if (address_mode == mode_64bit)
14919     {
14920       if (!(sizeflag & AFLAG))
14921         s = names32[code - eAX_reg];
14922       else
14923         s = names64[code - eAX_reg];
14924     }
14925   else if (sizeflag & AFLAG)
14926     s = names32[code - eAX_reg];
14927   else
14928     s = names16[code - eAX_reg];
14929   oappend (s);
14930   *obufp++ = close_char;
14931   *obufp = 0;
14932 }
14933
14934 static void
14935 OP_ESreg (int code, int sizeflag)
14936 {
14937   if (intel_syntax)
14938     {
14939       switch (codep[-1])
14940         {
14941         case 0x6d:      /* insw/insl */
14942           intel_operand_size (z_mode, sizeflag);
14943           break;
14944         case 0xa5:      /* movsw/movsl/movsq */
14945         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14946         case 0xab:      /* stosw/stosl */
14947         case 0xaf:      /* scasw/scasl */
14948           intel_operand_size (v_mode, sizeflag);
14949           break;
14950         default:
14951           intel_operand_size (b_mode, sizeflag);
14952         }
14953     }
14954   oappend_maybe_intel ("%es:");
14955   ptr_reg (code, sizeflag);
14956 }
14957
14958 static void
14959 OP_DSreg (int code, int sizeflag)
14960 {
14961   if (intel_syntax)
14962     {
14963       switch (codep[-1])
14964         {
14965         case 0x6f:      /* outsw/outsl */
14966           intel_operand_size (z_mode, sizeflag);
14967           break;
14968         case 0xa5:      /* movsw/movsl/movsq */
14969         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14970         case 0xad:      /* lodsw/lodsl/lodsq */
14971           intel_operand_size (v_mode, sizeflag);
14972           break;
14973         default:
14974           intel_operand_size (b_mode, sizeflag);
14975         }
14976     }
14977   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14978      default segment register DS is printed.  */
14979   if (!active_seg_prefix)
14980     active_seg_prefix = PREFIX_DS;
14981   append_seg ();
14982   ptr_reg (code, sizeflag);
14983 }
14984
14985 static void
14986 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14987 {
14988   int add;
14989   if (rex & REX_R)
14990     {
14991       USED_REX (REX_R);
14992       add = 8;
14993     }
14994   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
14995     {
14996       all_prefixes[last_lock_prefix] = 0;
14997       used_prefixes |= PREFIX_LOCK;
14998       add = 8;
14999     }
15000   else
15001     add = 0;
15002   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15003   oappend_maybe_intel (scratchbuf);
15004 }
15005
15006 static void
15007 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15008 {
15009   int add;
15010   USED_REX (REX_R);
15011   if (rex & REX_R)
15012     add = 8;
15013   else
15014     add = 0;
15015   if (intel_syntax)
15016     sprintf (scratchbuf, "db%d", modrm.reg + add);
15017   else
15018     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15019   oappend (scratchbuf);
15020 }
15021
15022 static void
15023 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15024 {
15025   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15026   oappend_maybe_intel (scratchbuf);
15027 }
15028
15029 static void
15030 OP_R (int bytemode, int sizeflag)
15031 {
15032   /* Skip mod/rm byte.  */
15033   MODRM_CHECK;
15034   codep++;
15035   OP_E_register (bytemode, sizeflag);
15036 }
15037
15038 static void
15039 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15040 {
15041   int reg = modrm.reg;
15042   const char **names;
15043
15044   used_prefixes |= (prefixes & PREFIX_DATA);
15045   if (prefixes & PREFIX_DATA)
15046     {
15047       names = names_xmm;
15048       USED_REX (REX_R);
15049       if (rex & REX_R)
15050         reg += 8;
15051     }
15052   else
15053     names = names_mm;
15054   oappend (names[reg]);
15055 }
15056
15057 static void
15058 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15059 {
15060   int reg = modrm.reg;
15061   const char **names;
15062
15063   USED_REX (REX_R);
15064   if (rex & REX_R)
15065     reg += 8;
15066   if (vex.evex)
15067     {
15068       if (!vex.r)
15069         reg += 16;
15070     }
15071
15072   if (need_vex
15073       && bytemode != xmm_mode
15074       && bytemode != xmmq_mode
15075       && bytemode != evex_half_bcst_xmmq_mode
15076       && bytemode != ymm_mode
15077       && bytemode != scalar_mode)
15078     {
15079       switch (vex.length)
15080         {
15081         case 128:
15082           names = names_xmm;
15083           break;
15084         case 256:
15085           if (vex.w
15086               || (bytemode != vex_vsib_q_w_dq_mode
15087                   && bytemode != vex_vsib_q_w_d_mode))
15088             names = names_ymm;
15089           else
15090             names = names_xmm;
15091           break;
15092         case 512:
15093           names = names_zmm;
15094           break;
15095         default:
15096           abort ();
15097         }
15098     }
15099   else if (bytemode == xmmq_mode
15100            || bytemode == evex_half_bcst_xmmq_mode)
15101     {
15102       switch (vex.length)
15103         {
15104         case 128:
15105         case 256:
15106           names = names_xmm;
15107           break;
15108         case 512:
15109           names = names_ymm;
15110           break;
15111         default:
15112           abort ();
15113         }
15114     }
15115   else if (bytemode == ymm_mode)
15116     names = names_ymm;
15117   else
15118     names = names_xmm;
15119   oappend (names[reg]);
15120 }
15121
15122 static void
15123 OP_EM (int bytemode, int sizeflag)
15124 {
15125   int reg;
15126   const char **names;
15127
15128   if (modrm.mod != 3)
15129     {
15130       if (intel_syntax
15131           && (bytemode == v_mode || bytemode == v_swap_mode))
15132         {
15133           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15134           used_prefixes |= (prefixes & PREFIX_DATA);
15135         }
15136       OP_E (bytemode, sizeflag);
15137       return;
15138     }
15139
15140   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15141     swap_operand ();
15142
15143   /* Skip mod/rm byte.  */
15144   MODRM_CHECK;
15145   codep++;
15146   used_prefixes |= (prefixes & PREFIX_DATA);
15147   reg = modrm.rm;
15148   if (prefixes & PREFIX_DATA)
15149     {
15150       names = names_xmm;
15151       USED_REX (REX_B);
15152       if (rex & REX_B)
15153         reg += 8;
15154     }
15155   else
15156     names = names_mm;
15157   oappend (names[reg]);
15158 }
15159
15160 /* cvt* are the only instructions in sse2 which have
15161    both SSE and MMX operands and also have 0x66 prefix
15162    in their opcode. 0x66 was originally used to differentiate
15163    between SSE and MMX instruction(operands). So we have to handle the
15164    cvt* separately using OP_EMC and OP_MXC */
15165 static void
15166 OP_EMC (int bytemode, int sizeflag)
15167 {
15168   if (modrm.mod != 3)
15169     {
15170       if (intel_syntax && bytemode == v_mode)
15171         {
15172           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15173           used_prefixes |= (prefixes & PREFIX_DATA);
15174         }
15175       OP_E (bytemode, sizeflag);
15176       return;
15177     }
15178
15179   /* Skip mod/rm byte.  */
15180   MODRM_CHECK;
15181   codep++;
15182   used_prefixes |= (prefixes & PREFIX_DATA);
15183   oappend (names_mm[modrm.rm]);
15184 }
15185
15186 static void
15187 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15188 {
15189   used_prefixes |= (prefixes & PREFIX_DATA);
15190   oappend (names_mm[modrm.reg]);
15191 }
15192
15193 static void
15194 OP_EX (int bytemode, int sizeflag)
15195 {
15196   int reg;
15197   const char **names;
15198
15199   /* Skip mod/rm byte.  */
15200   MODRM_CHECK;
15201   codep++;
15202
15203   if (modrm.mod != 3)
15204     {
15205       OP_E_memory (bytemode, sizeflag);
15206       return;
15207     }
15208
15209   reg = modrm.rm;
15210   USED_REX (REX_B);
15211   if (rex & REX_B)
15212     reg += 8;
15213   if (vex.evex)
15214     {
15215       USED_REX (REX_X);
15216       if ((rex & REX_X))
15217         reg += 16;
15218     }
15219
15220   if ((sizeflag & SUFFIX_ALWAYS)
15221       && (bytemode == x_swap_mode
15222           || bytemode == d_swap_mode
15223           || bytemode == d_scalar_swap_mode
15224           || bytemode == q_swap_mode
15225           || bytemode == q_scalar_swap_mode))
15226     swap_operand ();
15227
15228   if (need_vex
15229       && bytemode != xmm_mode
15230       && bytemode != xmmdw_mode
15231       && bytemode != xmmqd_mode
15232       && bytemode != xmm_mb_mode
15233       && bytemode != xmm_mw_mode
15234       && bytemode != xmm_md_mode
15235       && bytemode != xmm_mq_mode
15236       && bytemode != xmmq_mode
15237       && bytemode != evex_half_bcst_xmmq_mode
15238       && bytemode != ymm_mode
15239       && bytemode != d_scalar_swap_mode
15240       && bytemode != q_scalar_swap_mode
15241       && bytemode != vex_scalar_w_dq_mode)
15242     {
15243       switch (vex.length)
15244         {
15245         case 128:
15246           names = names_xmm;
15247           break;
15248         case 256:
15249           names = names_ymm;
15250           break;
15251         case 512:
15252           names = names_zmm;
15253           break;
15254         default:
15255           abort ();
15256         }
15257     }
15258   else if (bytemode == xmmq_mode
15259            || bytemode == evex_half_bcst_xmmq_mode)
15260     {
15261       switch (vex.length)
15262         {
15263         case 128:
15264         case 256:
15265           names = names_xmm;
15266           break;
15267         case 512:
15268           names = names_ymm;
15269           break;
15270         default:
15271           abort ();
15272         }
15273     }
15274   else if (bytemode == ymm_mode)
15275     names = names_ymm;
15276   else
15277     names = names_xmm;
15278   oappend (names[reg]);
15279 }
15280
15281 static void
15282 OP_MS (int bytemode, int sizeflag)
15283 {
15284   if (modrm.mod == 3)
15285     OP_EM (bytemode, sizeflag);
15286   else
15287     BadOp ();
15288 }
15289
15290 static void
15291 OP_XS (int bytemode, int sizeflag)
15292 {
15293   if (modrm.mod == 3)
15294     OP_EX (bytemode, sizeflag);
15295   else
15296     BadOp ();
15297 }
15298
15299 static void
15300 OP_M (int bytemode, int sizeflag)
15301 {
15302   if (modrm.mod == 3)
15303     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15304     BadOp ();
15305   else
15306     OP_E (bytemode, sizeflag);
15307 }
15308
15309 static void
15310 OP_0f07 (int bytemode, int sizeflag)
15311 {
15312   if (modrm.mod != 3 || modrm.rm != 0)
15313     BadOp ();
15314   else
15315     OP_E (bytemode, sizeflag);
15316 }
15317
15318 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15319    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15320
15321 static void
15322 NOP_Fixup1 (int bytemode, int sizeflag)
15323 {
15324   if ((prefixes & PREFIX_DATA) != 0
15325       || (rex != 0
15326           && rex != 0x48
15327           && address_mode == mode_64bit))
15328     OP_REG (bytemode, sizeflag);
15329   else
15330     strcpy (obuf, "nop");
15331 }
15332
15333 static void
15334 NOP_Fixup2 (int bytemode, int sizeflag)
15335 {
15336   if ((prefixes & PREFIX_DATA) != 0
15337       || (rex != 0
15338           && rex != 0x48
15339           && address_mode == mode_64bit))
15340     OP_IMREG (bytemode, sizeflag);
15341 }
15342
15343 static const char *const Suffix3DNow[] = {
15344 /* 00 */        NULL,           NULL,           NULL,           NULL,
15345 /* 04 */        NULL,           NULL,           NULL,           NULL,
15346 /* 08 */        NULL,           NULL,           NULL,           NULL,
15347 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15348 /* 10 */        NULL,           NULL,           NULL,           NULL,
15349 /* 14 */        NULL,           NULL,           NULL,           NULL,
15350 /* 18 */        NULL,           NULL,           NULL,           NULL,
15351 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15352 /* 20 */        NULL,           NULL,           NULL,           NULL,
15353 /* 24 */        NULL,           NULL,           NULL,           NULL,
15354 /* 28 */        NULL,           NULL,           NULL,           NULL,
15355 /* 2C */        NULL,           NULL,           NULL,           NULL,
15356 /* 30 */        NULL,           NULL,           NULL,           NULL,
15357 /* 34 */        NULL,           NULL,           NULL,           NULL,
15358 /* 38 */        NULL,           NULL,           NULL,           NULL,
15359 /* 3C */        NULL,           NULL,           NULL,           NULL,
15360 /* 40 */        NULL,           NULL,           NULL,           NULL,
15361 /* 44 */        NULL,           NULL,           NULL,           NULL,
15362 /* 48 */        NULL,           NULL,           NULL,           NULL,
15363 /* 4C */        NULL,           NULL,           NULL,           NULL,
15364 /* 50 */        NULL,           NULL,           NULL,           NULL,
15365 /* 54 */        NULL,           NULL,           NULL,           NULL,
15366 /* 58 */        NULL,           NULL,           NULL,           NULL,
15367 /* 5C */        NULL,           NULL,           NULL,           NULL,
15368 /* 60 */        NULL,           NULL,           NULL,           NULL,
15369 /* 64 */        NULL,           NULL,           NULL,           NULL,
15370 /* 68 */        NULL,           NULL,           NULL,           NULL,
15371 /* 6C */        NULL,           NULL,           NULL,           NULL,
15372 /* 70 */        NULL,           NULL,           NULL,           NULL,
15373 /* 74 */        NULL,           NULL,           NULL,           NULL,
15374 /* 78 */        NULL,           NULL,           NULL,           NULL,
15375 /* 7C */        NULL,           NULL,           NULL,           NULL,
15376 /* 80 */        NULL,           NULL,           NULL,           NULL,
15377 /* 84 */        NULL,           NULL,           NULL,           NULL,
15378 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15379 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15380 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15381 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15382 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15383 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15384 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15385 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15386 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15387 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15388 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15389 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15390 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15391 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15392 /* C0 */        NULL,           NULL,           NULL,           NULL,
15393 /* C4 */        NULL,           NULL,           NULL,           NULL,
15394 /* C8 */        NULL,           NULL,           NULL,           NULL,
15395 /* CC */        NULL,           NULL,           NULL,           NULL,
15396 /* D0 */        NULL,           NULL,           NULL,           NULL,
15397 /* D4 */        NULL,           NULL,           NULL,           NULL,
15398 /* D8 */        NULL,           NULL,           NULL,           NULL,
15399 /* DC */        NULL,           NULL,           NULL,           NULL,
15400 /* E0 */        NULL,           NULL,           NULL,           NULL,
15401 /* E4 */        NULL,           NULL,           NULL,           NULL,
15402 /* E8 */        NULL,           NULL,           NULL,           NULL,
15403 /* EC */        NULL,           NULL,           NULL,           NULL,
15404 /* F0 */        NULL,           NULL,           NULL,           NULL,
15405 /* F4 */        NULL,           NULL,           NULL,           NULL,
15406 /* F8 */        NULL,           NULL,           NULL,           NULL,
15407 /* FC */        NULL,           NULL,           NULL,           NULL,
15408 };
15409
15410 static void
15411 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15412 {
15413   const char *mnemonic;
15414
15415   FETCH_DATA (the_info, codep + 1);
15416   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15417      place where an 8-bit immediate would normally go.  ie. the last
15418      byte of the instruction.  */
15419   obufp = mnemonicendp;
15420   mnemonic = Suffix3DNow[*codep++ & 0xff];
15421   if (mnemonic)
15422     oappend (mnemonic);
15423   else
15424     {
15425       /* Since a variable sized modrm/sib chunk is between the start
15426          of the opcode (0x0f0f) and the opcode suffix, we need to do
15427          all the modrm processing first, and don't know until now that
15428          we have a bad opcode.  This necessitates some cleaning up.  */
15429       op_out[0][0] = '\0';
15430       op_out[1][0] = '\0';
15431       BadOp ();
15432     }
15433   mnemonicendp = obufp;
15434 }
15435
15436 static struct op simd_cmp_op[] =
15437 {
15438   { STRING_COMMA_LEN ("eq") },
15439   { STRING_COMMA_LEN ("lt") },
15440   { STRING_COMMA_LEN ("le") },
15441   { STRING_COMMA_LEN ("unord") },
15442   { STRING_COMMA_LEN ("neq") },
15443   { STRING_COMMA_LEN ("nlt") },
15444   { STRING_COMMA_LEN ("nle") },
15445   { STRING_COMMA_LEN ("ord") }
15446 };
15447
15448 static void
15449 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15450 {
15451   unsigned int cmp_type;
15452
15453   FETCH_DATA (the_info, codep + 1);
15454   cmp_type = *codep++ & 0xff;
15455   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15456     {
15457       char suffix [3];
15458       char *p = mnemonicendp - 2;
15459       suffix[0] = p[0];
15460       suffix[1] = p[1];
15461       suffix[2] = '\0';
15462       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15463       mnemonicendp += simd_cmp_op[cmp_type].len;
15464     }
15465   else
15466     {
15467       /* We have a reserved extension byte.  Output it directly.  */
15468       scratchbuf[0] = '$';
15469       print_operand_value (scratchbuf + 1, 1, cmp_type);
15470       oappend_maybe_intel (scratchbuf);
15471       scratchbuf[0] = '\0';
15472     }
15473 }
15474
15475 static void
15476 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15477 {
15478   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15479   if (!intel_syntax)
15480     {
15481       strcpy (op_out[0], names32[0]);
15482       strcpy (op_out[1], names32[1]);
15483       if (bytemode == eBX_reg)
15484         strcpy (op_out[2], names32[3]);
15485       two_source_ops = 1;
15486     }
15487   /* Skip mod/rm byte.  */
15488   MODRM_CHECK;
15489   codep++;
15490 }
15491
15492 static void
15493 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15494             int sizeflag ATTRIBUTE_UNUSED)
15495 {
15496   /* monitor %{e,r,}ax,%ecx,%edx"  */
15497   if (!intel_syntax)
15498     {
15499       const char **names = (address_mode == mode_64bit
15500                             ? names64 : names32);
15501
15502       if (prefixes & PREFIX_ADDR)
15503         {
15504           /* Remove "addr16/addr32".  */
15505           all_prefixes[last_addr_prefix] = 0;
15506           names = (address_mode != mode_32bit
15507                    ? names32 : names16);
15508           used_prefixes |= PREFIX_ADDR;
15509         }
15510       else if (address_mode == mode_16bit)
15511         names = names16;
15512       strcpy (op_out[0], names[0]);
15513       strcpy (op_out[1], names32[1]);
15514       strcpy (op_out[2], names32[2]);
15515       two_source_ops = 1;
15516     }
15517   /* Skip mod/rm byte.  */
15518   MODRM_CHECK;
15519   codep++;
15520 }
15521
15522 static void
15523 BadOp (void)
15524 {
15525   /* Throw away prefixes and 1st. opcode byte.  */
15526   codep = insn_codep + 1;
15527   oappend ("(bad)");
15528 }
15529
15530 static void
15531 REP_Fixup (int bytemode, int sizeflag)
15532 {
15533   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15534      lods and stos.  */
15535   if (prefixes & PREFIX_REPZ)
15536     all_prefixes[last_repz_prefix] = REP_PREFIX;
15537
15538   switch (bytemode)
15539     {
15540     case al_reg:
15541     case eAX_reg:
15542     case indir_dx_reg:
15543       OP_IMREG (bytemode, sizeflag);
15544       break;
15545     case eDI_reg:
15546       OP_ESreg (bytemode, sizeflag);
15547       break;
15548     case eSI_reg:
15549       OP_DSreg (bytemode, sizeflag);
15550       break;
15551     default:
15552       abort ();
15553       break;
15554     }
15555 }
15556
15557 static void
15558 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15559 {
15560   if ( isa64 != amd64 )
15561     return;
15562
15563   obufp = obuf;
15564   BadOp ();
15565   mnemonicendp = obufp;
15566   ++codep;
15567 }
15568
15569 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15570    "bnd".  */
15571
15572 static void
15573 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15574 {
15575   if (prefixes & PREFIX_REPNZ)
15576     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15577 }
15578
15579 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15580    "notrack".  */
15581
15582 static void
15583 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15584                int sizeflag ATTRIBUTE_UNUSED)
15585 {
15586   if (active_seg_prefix == PREFIX_DS
15587       && (address_mode != mode_64bit || last_data_prefix < 0))
15588     {
15589       /* NOTRACK prefix is only valid on indirect branch instructions.
15590          NB: DATA prefix is unsupported for Intel64.  */
15591       active_seg_prefix = 0;
15592       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15593     }
15594 }
15595
15596 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15597    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15598  */
15599
15600 static void
15601 HLE_Fixup1 (int bytemode, int sizeflag)
15602 {
15603   if (modrm.mod != 3
15604       && (prefixes & PREFIX_LOCK) != 0)
15605     {
15606       if (prefixes & PREFIX_REPZ)
15607         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15608       if (prefixes & PREFIX_REPNZ)
15609         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15610     }
15611
15612   OP_E (bytemode, sizeflag);
15613 }
15614
15615 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15616    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15617  */
15618
15619 static void
15620 HLE_Fixup2 (int bytemode, int sizeflag)
15621 {
15622   if (modrm.mod != 3)
15623     {
15624       if (prefixes & PREFIX_REPZ)
15625         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15626       if (prefixes & PREFIX_REPNZ)
15627         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15628     }
15629
15630   OP_E (bytemode, sizeflag);
15631 }
15632
15633 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15634    "xrelease" for memory operand.  No check for LOCK prefix.   */
15635
15636 static void
15637 HLE_Fixup3 (int bytemode, int sizeflag)
15638 {
15639   if (modrm.mod != 3
15640       && last_repz_prefix > last_repnz_prefix
15641       && (prefixes & PREFIX_REPZ) != 0)
15642     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15643
15644   OP_E (bytemode, sizeflag);
15645 }
15646
15647 static void
15648 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15649 {
15650   USED_REX (REX_W);
15651   if (rex & REX_W)
15652     {
15653       /* Change cmpxchg8b to cmpxchg16b.  */
15654       char *p = mnemonicendp - 2;
15655       mnemonicendp = stpcpy (p, "16b");
15656       bytemode = o_mode;
15657     }
15658   else if ((prefixes & PREFIX_LOCK) != 0)
15659     {
15660       if (prefixes & PREFIX_REPZ)
15661         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15662       if (prefixes & PREFIX_REPNZ)
15663         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15664     }
15665
15666   OP_M (bytemode, sizeflag);
15667 }
15668
15669 static void
15670 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15671 {
15672   const char **names;
15673
15674   if (need_vex)
15675     {
15676       switch (vex.length)
15677         {
15678         case 128:
15679           names = names_xmm;
15680           break;
15681         case 256:
15682           names = names_ymm;
15683           break;
15684         default:
15685           abort ();
15686         }
15687     }
15688   else
15689     names = names_xmm;
15690   oappend (names[reg]);
15691 }
15692
15693 static void
15694 CRC32_Fixup (int bytemode, int sizeflag)
15695 {
15696   /* Add proper suffix to "crc32".  */
15697   char *p = mnemonicendp;
15698
15699   switch (bytemode)
15700     {
15701     case b_mode:
15702       if (intel_syntax)
15703         goto skip;
15704
15705       *p++ = 'b';
15706       break;
15707     case v_mode:
15708       if (intel_syntax)
15709         goto skip;
15710
15711       USED_REX (REX_W);
15712       if (rex & REX_W)
15713         *p++ = 'q';
15714       else
15715         {
15716           if (sizeflag & DFLAG)
15717             *p++ = 'l';
15718           else
15719             *p++ = 'w';
15720           used_prefixes |= (prefixes & PREFIX_DATA);
15721         }
15722       break;
15723     default:
15724       oappend (INTERNAL_DISASSEMBLER_ERROR);
15725       break;
15726     }
15727   mnemonicendp = p;
15728   *p = '\0';
15729
15730  skip:
15731   if (modrm.mod == 3)
15732     {
15733       int add;
15734
15735       /* Skip mod/rm byte.  */
15736       MODRM_CHECK;
15737       codep++;
15738
15739       USED_REX (REX_B);
15740       add = (rex & REX_B) ? 8 : 0;
15741       if (bytemode == b_mode)
15742         {
15743           USED_REX (0);
15744           if (rex)
15745             oappend (names8rex[modrm.rm + add]);
15746           else
15747             oappend (names8[modrm.rm + add]);
15748         }
15749       else
15750         {
15751           USED_REX (REX_W);
15752           if (rex & REX_W)
15753             oappend (names64[modrm.rm + add]);
15754           else if ((prefixes & PREFIX_DATA))
15755             oappend (names16[modrm.rm + add]);
15756           else
15757             oappend (names32[modrm.rm + add]);
15758         }
15759     }
15760   else
15761     OP_E (bytemode, sizeflag);
15762 }
15763
15764 static void
15765 FXSAVE_Fixup (int bytemode, int sizeflag)
15766 {
15767   /* Add proper suffix to "fxsave" and "fxrstor".  */
15768   USED_REX (REX_W);
15769   if (rex & REX_W)
15770     {
15771       char *p = mnemonicendp;
15772       *p++ = '6';
15773       *p++ = '4';
15774       *p = '\0';
15775       mnemonicendp = p;
15776     }
15777   OP_M (bytemode, sizeflag);
15778 }
15779
15780 static void
15781 PCMPESTR_Fixup (int bytemode, int sizeflag)
15782 {
15783   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15784   if (!intel_syntax)
15785     {
15786       char *p = mnemonicendp;
15787
15788       USED_REX (REX_W);
15789       if (rex & REX_W)
15790         *p++ = 'q';
15791       else if (sizeflag & SUFFIX_ALWAYS)
15792         *p++ = 'l';
15793
15794       *p = '\0';
15795       mnemonicendp = p;
15796     }
15797
15798   OP_EX (bytemode, sizeflag);
15799 }
15800
15801 /* Display the destination register operand for instructions with
15802    VEX. */
15803
15804 static void
15805 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15806 {
15807   int reg;
15808   const char **names;
15809
15810   if (!need_vex)
15811     abort ();
15812
15813   if (!need_vex_reg)
15814     return;
15815
15816   reg = vex.register_specifier;
15817   vex.register_specifier = 0;
15818   if (address_mode != mode_64bit)
15819     reg &= 7;
15820   else if (vex.evex && !vex.v)
15821     reg += 16;
15822
15823   if (bytemode == vex_scalar_mode)
15824     {
15825       oappend (names_xmm[reg]);
15826       return;
15827     }
15828
15829   switch (vex.length)
15830     {
15831     case 128:
15832       switch (bytemode)
15833         {
15834         case vex_mode:
15835         case vex128_mode:
15836         case vex_vsib_q_w_dq_mode:
15837         case vex_vsib_q_w_d_mode:
15838           names = names_xmm;
15839           break;
15840         case dq_mode:
15841           if (rex & REX_W)
15842             names = names64;
15843           else
15844             names = names32;
15845           break;
15846         case mask_bd_mode:
15847         case mask_mode:
15848           if (reg > 0x7)
15849             {
15850               oappend ("(bad)");
15851               return;
15852             }
15853           names = names_mask;
15854           break;
15855         default:
15856           abort ();
15857           return;
15858         }
15859       break;
15860     case 256:
15861       switch (bytemode)
15862         {
15863         case vex_mode:
15864         case vex256_mode:
15865           names = names_ymm;
15866           break;
15867         case vex_vsib_q_w_dq_mode:
15868         case vex_vsib_q_w_d_mode:
15869           names = vex.w ? names_ymm : names_xmm;
15870           break;
15871         case mask_bd_mode:
15872         case mask_mode:
15873           if (reg > 0x7)
15874             {
15875               oappend ("(bad)");
15876               return;
15877             }
15878           names = names_mask;
15879           break;
15880         default:
15881           /* See PR binutils/20893 for a reproducer.  */
15882           oappend ("(bad)");
15883           return;
15884         }
15885       break;
15886     case 512:
15887       names = names_zmm;
15888       break;
15889     default:
15890       abort ();
15891       break;
15892     }
15893   oappend (names[reg]);
15894 }
15895
15896 /* Get the VEX immediate byte without moving codep.  */
15897
15898 static unsigned char
15899 get_vex_imm8 (int sizeflag, int opnum)
15900 {
15901   int bytes_before_imm = 0;
15902
15903   if (modrm.mod != 3)
15904     {
15905       /* There are SIB/displacement bytes.  */
15906       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15907         {
15908           /* 32/64 bit address mode */
15909           int base = modrm.rm;
15910
15911           /* Check SIB byte.  */
15912           if (base == 4)
15913             {
15914               FETCH_DATA (the_info, codep + 1);
15915               base = *codep & 7;
15916               /* When decoding the third source, don't increase
15917                  bytes_before_imm as this has already been incremented
15918                  by one in OP_E_memory while decoding the second
15919                  source operand.  */
15920               if (opnum == 0)
15921                 bytes_before_imm++;
15922             }
15923
15924           /* Don't increase bytes_before_imm when decoding the third source,
15925              it has already been incremented by OP_E_memory while decoding
15926              the second source operand.  */
15927           if (opnum == 0)
15928             {
15929               switch (modrm.mod)
15930                 {
15931                   case 0:
15932                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15933                        SIB == 5, there is a 4 byte displacement.  */
15934                     if (base != 5)
15935                       /* No displacement. */
15936                       break;
15937                     /* Fall through.  */
15938                   case 2:
15939                     /* 4 byte displacement.  */
15940                     bytes_before_imm += 4;
15941                     break;
15942                   case 1:
15943                     /* 1 byte displacement.  */
15944                     bytes_before_imm++;
15945                     break;
15946                 }
15947             }
15948         }
15949       else
15950         {
15951           /* 16 bit address mode */
15952           /* Don't increase bytes_before_imm when decoding the third source,
15953              it has already been incremented by OP_E_memory while decoding
15954              the second source operand.  */
15955           if (opnum == 0)
15956             {
15957               switch (modrm.mod)
15958                 {
15959                 case 0:
15960                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
15961                   if (modrm.rm != 6)
15962                     /* No displacement. */
15963                     break;
15964                   /* Fall through.  */
15965                 case 2:
15966                   /* 2 byte displacement.  */
15967                   bytes_before_imm += 2;
15968                   break;
15969                 case 1:
15970                   /* 1 byte displacement: when decoding the third source,
15971                      don't increase bytes_before_imm as this has already
15972                      been incremented by one in OP_E_memory while decoding
15973                      the second source operand.  */
15974                   if (opnum == 0)
15975                     bytes_before_imm++;
15976
15977                   break;
15978                 }
15979             }
15980         }
15981     }
15982
15983   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
15984   return codep [bytes_before_imm];
15985 }
15986
15987 static void
15988 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
15989 {
15990   const char **names;
15991
15992   if (reg == -1 && modrm.mod != 3)
15993     {
15994       OP_E_memory (bytemode, sizeflag);
15995       return;
15996     }
15997   else
15998     {
15999       if (reg == -1)
16000         {
16001           reg = modrm.rm;
16002           USED_REX (REX_B);
16003           if (rex & REX_B)
16004             reg += 8;
16005         }
16006       if (address_mode != mode_64bit)
16007         reg &= 7;
16008     }
16009
16010   switch (vex.length)
16011     {
16012     case 128:
16013       names = names_xmm;
16014       break;
16015     case 256:
16016       names = names_ymm;
16017       break;
16018     default:
16019       abort ();
16020     }
16021   oappend (names[reg]);
16022 }
16023
16024 static void
16025 OP_EX_VexImmW (int bytemode, int sizeflag)
16026 {
16027   int reg = -1;
16028   static unsigned char vex_imm8;
16029
16030   if (vex_w_done == 0)
16031     {
16032       vex_w_done = 1;
16033
16034       /* Skip mod/rm byte.  */
16035       MODRM_CHECK;
16036       codep++;
16037
16038       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16039
16040       if (vex.w)
16041           reg = vex_imm8 >> 4;
16042
16043       OP_EX_VexReg (bytemode, sizeflag, reg);
16044     }
16045   else if (vex_w_done == 1)
16046     {
16047       vex_w_done = 2;
16048
16049       if (!vex.w)
16050           reg = vex_imm8 >> 4;
16051
16052       OP_EX_VexReg (bytemode, sizeflag, reg);
16053     }
16054   else
16055     {
16056       /* Output the imm8 directly.  */
16057       scratchbuf[0] = '$';
16058       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16059       oappend_maybe_intel (scratchbuf);
16060       scratchbuf[0] = '\0';
16061       codep++;
16062     }
16063 }
16064
16065 static void
16066 OP_Vex_2src (int bytemode, int sizeflag)
16067 {
16068   if (modrm.mod == 3)
16069     {
16070       int reg = modrm.rm;
16071       USED_REX (REX_B);
16072       if (rex & REX_B)
16073         reg += 8;
16074       oappend (names_xmm[reg]);
16075     }
16076   else
16077     {
16078       if (intel_syntax
16079           && (bytemode == v_mode || bytemode == v_swap_mode))
16080         {
16081           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16082           used_prefixes |= (prefixes & PREFIX_DATA);
16083         }
16084       OP_E (bytemode, sizeflag);
16085     }
16086 }
16087
16088 static void
16089 OP_Vex_2src_1 (int bytemode, int sizeflag)
16090 {
16091   if (modrm.mod == 3)
16092     {
16093       /* Skip mod/rm byte.   */
16094       MODRM_CHECK;
16095       codep++;
16096     }
16097
16098   if (vex.w)
16099     {
16100       unsigned int reg = vex.register_specifier;
16101       vex.register_specifier = 0;
16102
16103       if (address_mode != mode_64bit)
16104         reg &= 7;
16105       oappend (names_xmm[reg]);
16106     }
16107   else
16108     OP_Vex_2src (bytemode, sizeflag);
16109 }
16110
16111 static void
16112 OP_Vex_2src_2 (int bytemode, int sizeflag)
16113 {
16114   if (vex.w)
16115     OP_Vex_2src (bytemode, sizeflag);
16116   else
16117     {
16118       unsigned int reg = vex.register_specifier;
16119       vex.register_specifier = 0;
16120
16121       if (address_mode != mode_64bit)
16122         reg &= 7;
16123       oappend (names_xmm[reg]);
16124     }
16125 }
16126
16127 static void
16128 OP_EX_VexW (int bytemode, int sizeflag)
16129 {
16130   int reg = -1;
16131
16132   if (!vex_w_done)
16133     {
16134       /* Skip mod/rm byte.  */
16135       MODRM_CHECK;
16136       codep++;
16137
16138       if (vex.w)
16139         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16140     }
16141   else
16142     {
16143       if (!vex.w)
16144         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16145     }
16146
16147   OP_EX_VexReg (bytemode, sizeflag, reg);
16148
16149   if (vex_w_done)
16150     codep++;
16151   vex_w_done = 1;
16152 }
16153
16154 static void
16155 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16156 {
16157   int reg;
16158   const char **names;
16159
16160   FETCH_DATA (the_info, codep + 1);
16161   reg = *codep++;
16162
16163   if (bytemode != x_mode)
16164     abort ();
16165
16166   reg >>= 4;
16167   if (address_mode != mode_64bit)
16168     reg &= 7;
16169
16170   switch (vex.length)
16171     {
16172     case 128:
16173       names = names_xmm;
16174       break;
16175     case 256:
16176       names = names_ymm;
16177       break;
16178     default:
16179       abort ();
16180     }
16181   oappend (names[reg]);
16182 }
16183
16184 static void
16185 OP_XMM_VexW (int bytemode, int sizeflag)
16186 {
16187   /* Turn off the REX.W bit since it is used for swapping operands
16188      now.  */
16189   rex &= ~REX_W;
16190   OP_XMM (bytemode, sizeflag);
16191 }
16192
16193 static void
16194 OP_EX_Vex (int bytemode, int sizeflag)
16195 {
16196   if (modrm.mod != 3)
16197     need_vex_reg = 0;
16198   OP_EX (bytemode, sizeflag);
16199 }
16200
16201 static void
16202 OP_XMM_Vex (int bytemode, int sizeflag)
16203 {
16204   if (modrm.mod != 3)
16205     need_vex_reg = 0;
16206   OP_XMM (bytemode, sizeflag);
16207 }
16208
16209 static struct op vex_cmp_op[] =
16210 {
16211   { STRING_COMMA_LEN ("eq") },
16212   { STRING_COMMA_LEN ("lt") },
16213   { STRING_COMMA_LEN ("le") },
16214   { STRING_COMMA_LEN ("unord") },
16215   { STRING_COMMA_LEN ("neq") },
16216   { STRING_COMMA_LEN ("nlt") },
16217   { STRING_COMMA_LEN ("nle") },
16218   { STRING_COMMA_LEN ("ord") },
16219   { STRING_COMMA_LEN ("eq_uq") },
16220   { STRING_COMMA_LEN ("nge") },
16221   { STRING_COMMA_LEN ("ngt") },
16222   { STRING_COMMA_LEN ("false") },
16223   { STRING_COMMA_LEN ("neq_oq") },
16224   { STRING_COMMA_LEN ("ge") },
16225   { STRING_COMMA_LEN ("gt") },
16226   { STRING_COMMA_LEN ("true") },
16227   { STRING_COMMA_LEN ("eq_os") },
16228   { STRING_COMMA_LEN ("lt_oq") },
16229   { STRING_COMMA_LEN ("le_oq") },
16230   { STRING_COMMA_LEN ("unord_s") },
16231   { STRING_COMMA_LEN ("neq_us") },
16232   { STRING_COMMA_LEN ("nlt_uq") },
16233   { STRING_COMMA_LEN ("nle_uq") },
16234   { STRING_COMMA_LEN ("ord_s") },
16235   { STRING_COMMA_LEN ("eq_us") },
16236   { STRING_COMMA_LEN ("nge_uq") },
16237   { STRING_COMMA_LEN ("ngt_uq") },
16238   { STRING_COMMA_LEN ("false_os") },
16239   { STRING_COMMA_LEN ("neq_os") },
16240   { STRING_COMMA_LEN ("ge_oq") },
16241   { STRING_COMMA_LEN ("gt_oq") },
16242   { STRING_COMMA_LEN ("true_us") },
16243 };
16244
16245 static void
16246 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16247 {
16248   unsigned int cmp_type;
16249
16250   FETCH_DATA (the_info, codep + 1);
16251   cmp_type = *codep++ & 0xff;
16252   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16253     {
16254       char suffix [3];
16255       char *p = mnemonicendp - 2;
16256       suffix[0] = p[0];
16257       suffix[1] = p[1];
16258       suffix[2] = '\0';
16259       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16260       mnemonicendp += vex_cmp_op[cmp_type].len;
16261     }
16262   else
16263     {
16264       /* We have a reserved extension byte.  Output it directly.  */
16265       scratchbuf[0] = '$';
16266       print_operand_value (scratchbuf + 1, 1, cmp_type);
16267       oappend_maybe_intel (scratchbuf);
16268       scratchbuf[0] = '\0';
16269     }
16270 }
16271
16272 static void
16273 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16274              int sizeflag ATTRIBUTE_UNUSED)
16275 {
16276   unsigned int cmp_type;
16277
16278   if (!vex.evex)
16279     abort ();
16280
16281   FETCH_DATA (the_info, codep + 1);
16282   cmp_type = *codep++ & 0xff;
16283   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16284      If it's the case, print suffix, otherwise - print the immediate.  */
16285   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16286       && cmp_type != 3
16287       && cmp_type != 7)
16288     {
16289       char suffix [3];
16290       char *p = mnemonicendp - 2;
16291
16292       /* vpcmp* can have both one- and two-lettered suffix.  */
16293       if (p[0] == 'p')
16294         {
16295           p++;
16296           suffix[0] = p[0];
16297           suffix[1] = '\0';
16298         }
16299       else
16300         {
16301           suffix[0] = p[0];
16302           suffix[1] = p[1];
16303           suffix[2] = '\0';
16304         }
16305
16306       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16307       mnemonicendp += simd_cmp_op[cmp_type].len;
16308     }
16309   else
16310     {
16311       /* We have a reserved extension byte.  Output it directly.  */
16312       scratchbuf[0] = '$';
16313       print_operand_value (scratchbuf + 1, 1, cmp_type);
16314       oappend_maybe_intel (scratchbuf);
16315       scratchbuf[0] = '\0';
16316     }
16317 }
16318
16319 static const struct op xop_cmp_op[] =
16320 {
16321   { STRING_COMMA_LEN ("lt") },
16322   { STRING_COMMA_LEN ("le") },
16323   { STRING_COMMA_LEN ("gt") },
16324   { STRING_COMMA_LEN ("ge") },
16325   { STRING_COMMA_LEN ("eq") },
16326   { STRING_COMMA_LEN ("neq") },
16327   { STRING_COMMA_LEN ("false") },
16328   { STRING_COMMA_LEN ("true") }
16329 };
16330
16331 static void
16332 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16333              int sizeflag ATTRIBUTE_UNUSED)
16334 {
16335   unsigned int cmp_type;
16336
16337   FETCH_DATA (the_info, codep + 1);
16338   cmp_type = *codep++ & 0xff;
16339   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16340     {
16341       char suffix[3];
16342       char *p = mnemonicendp - 2;
16343
16344       /* vpcom* can have both one- and two-lettered suffix.  */
16345       if (p[0] == 'm')
16346         {
16347           p++;
16348           suffix[0] = p[0];
16349           suffix[1] = '\0';
16350         }
16351       else
16352         {
16353           suffix[0] = p[0];
16354           suffix[1] = p[1];
16355           suffix[2] = '\0';
16356         }
16357
16358       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16359       mnemonicendp += xop_cmp_op[cmp_type].len;
16360     }
16361   else
16362     {
16363       /* We have a reserved extension byte.  Output it directly.  */
16364       scratchbuf[0] = '$';
16365       print_operand_value (scratchbuf + 1, 1, cmp_type);
16366       oappend_maybe_intel (scratchbuf);
16367       scratchbuf[0] = '\0';
16368     }
16369 }
16370
16371 static const struct op pclmul_op[] =
16372 {
16373   { STRING_COMMA_LEN ("lql") },
16374   { STRING_COMMA_LEN ("hql") },
16375   { STRING_COMMA_LEN ("lqh") },
16376   { STRING_COMMA_LEN ("hqh") }
16377 };
16378
16379 static void
16380 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16381               int sizeflag ATTRIBUTE_UNUSED)
16382 {
16383   unsigned int pclmul_type;
16384
16385   FETCH_DATA (the_info, codep + 1);
16386   pclmul_type = *codep++ & 0xff;
16387   switch (pclmul_type)
16388     {
16389     case 0x10:
16390       pclmul_type = 2;
16391       break;
16392     case 0x11:
16393       pclmul_type = 3;
16394       break;
16395     default:
16396       break;
16397     }
16398   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16399     {
16400       char suffix [4];
16401       char *p = mnemonicendp - 3;
16402       suffix[0] = p[0];
16403       suffix[1] = p[1];
16404       suffix[2] = p[2];
16405       suffix[3] = '\0';
16406       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16407       mnemonicendp += pclmul_op[pclmul_type].len;
16408     }
16409   else
16410     {
16411       /* We have a reserved extension byte.  Output it directly.  */
16412       scratchbuf[0] = '$';
16413       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16414       oappend_maybe_intel (scratchbuf);
16415       scratchbuf[0] = '\0';
16416     }
16417 }
16418
16419 static void
16420 MOVBE_Fixup (int bytemode, int sizeflag)
16421 {
16422   /* Add proper suffix to "movbe".  */
16423   char *p = mnemonicendp;
16424
16425   switch (bytemode)
16426     {
16427     case v_mode:
16428       if (intel_syntax)
16429         goto skip;
16430
16431       USED_REX (REX_W);
16432       if (sizeflag & SUFFIX_ALWAYS)
16433         {
16434           if (rex & REX_W)
16435             *p++ = 'q';
16436           else
16437             {
16438               if (sizeflag & DFLAG)
16439                 *p++ = 'l';
16440               else
16441                 *p++ = 'w';
16442               used_prefixes |= (prefixes & PREFIX_DATA);
16443             }
16444         }
16445       break;
16446     default:
16447       oappend (INTERNAL_DISASSEMBLER_ERROR);
16448       break;
16449     }
16450   mnemonicendp = p;
16451   *p = '\0';
16452
16453  skip:
16454   OP_M (bytemode, sizeflag);
16455 }
16456
16457 static void
16458 MOVSXD_Fixup (int bytemode, int sizeflag)
16459 {
16460   /* Add proper suffix to "movsxd".  */
16461   char *p = mnemonicendp;
16462
16463   switch (bytemode)
16464     {
16465     case movsxd_mode:
16466       if (intel_syntax)
16467         {
16468           *p++ = 'x';
16469           *p++ = 'd';
16470           goto skip;
16471         }
16472
16473       USED_REX (REX_W);
16474       if (rex & REX_W)
16475         {
16476           *p++ = 'l';
16477           *p++ = 'q';
16478         }
16479       else
16480         {
16481           *p++ = 'x';
16482           *p++ = 'd';
16483         }
16484       break;
16485     default:
16486       oappend (INTERNAL_DISASSEMBLER_ERROR);
16487       break;
16488     }
16489
16490  skip:
16491   mnemonicendp = p;
16492   *p = '\0';
16493   OP_E (bytemode, sizeflag);
16494 }
16495
16496 static void
16497 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16498 {
16499   int reg;
16500   const char **names;
16501
16502   /* Skip mod/rm byte.  */
16503   MODRM_CHECK;
16504   codep++;
16505
16506   if (rex & REX_W)
16507     names = names64;
16508   else
16509     names = names32;
16510
16511   reg = modrm.rm;
16512   USED_REX (REX_B);
16513   if (rex & REX_B)
16514     reg += 8;
16515
16516   oappend (names[reg]);
16517 }
16518
16519 static void
16520 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16521 {
16522   const char **names;
16523   unsigned int reg = vex.register_specifier;
16524   vex.register_specifier = 0;
16525
16526   if (rex & REX_W)
16527     names = names64;
16528   else
16529     names = names32;
16530
16531   if (address_mode != mode_64bit)
16532     reg &= 7;
16533   oappend (names[reg]);
16534 }
16535
16536 static void
16537 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16538 {
16539   if (!vex.evex
16540       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16541     abort ();
16542
16543   USED_REX (REX_R);
16544   if ((rex & REX_R) != 0 || !vex.r)
16545     {
16546       BadOp ();
16547       return;
16548     }
16549
16550   oappend (names_mask [modrm.reg]);
16551 }
16552
16553 static void
16554 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16555 {
16556   if (modrm.mod == 3 && vex.b)
16557     switch (bytemode)
16558       {
16559       case evex_rounding_64_mode:
16560         if (address_mode != mode_64bit)
16561           {
16562             oappend ("(bad)");
16563             break;
16564           }
16565         /* Fall through.  */
16566       case evex_rounding_mode:
16567         oappend (names_rounding[vex.ll]);
16568         break;
16569       case evex_sae_mode:
16570         oappend ("{sae}");
16571         break;
16572       default:
16573         abort ();
16574         break;
16575       }
16576 }