opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 struct dis_private {
 127   /* Points to first byte not fetched.  */
 128   bfd_byte *max_fetched;
 129   bfd_byte the_buffer[MAX_MNEM_SIZE];
 130   bfd_vma insn_start;
 131   int orig_sizeflag;
 132   jmp_buf bailout;
 133 };
 134
 135 enum address_mode
 136 {
 137   mode_16bit,
 138   mode_32bit,
 139   mode_64bit
 140 };
 141
 142 enum address_mode address_mode;
 143
 144 /* Flags for the prefixes for the current instruction.  See below.  */
 145 static int prefixes;
 146
 147 /* REX prefix the current instruction.  See below.  */
 148 static int rex;
 149 /* Bits of REX we've already used.  */
 150 static int rex_used;
 151 /* REX bits in original REX prefix ignored.  */
 152 static int rex_ignored;
 153 /* Mark parts used in the REX prefix.  When we are testing for
 154    empty prefix (for 8bit register REX extension), just mask it
 155    out.  Otherwise test for REX bit is excuse for existence of REX
 156    only in case value is nonzero.  */
 157 #define USED_REX(value)                                 \
 158   {                                                     \
 159     if (value)                                          \
 160       {                                                 \
 161         if ((rex & value))                              \
 162           rex_used |= (value) | REX_OPCODE;             \
 163       }                                                 \
 164     else                                                \
 165       rex_used |= REX_OPCODE;                           \
 166   }
 167
 168 /* Flags for prefixes which we somehow handled when printing the
 169    current instruction.  */
 170 static int used_prefixes;
 171
 172 /* Flags stored in PREFIXES.  */
 173 #define PREFIX_REPZ 1
 174 #define PREFIX_REPNZ 2
 175 #define PREFIX_LOCK 4
 176 #define PREFIX_CS 8
 177 #define PREFIX_SS 0x10
 178 #define PREFIX_DS 0x20
 179 #define PREFIX_ES 0x40
 180 #define PREFIX_FS 0x80
 181 #define PREFIX_GS 0x100
 182 #define PREFIX_DATA 0x200
 183 #define PREFIX_ADDR 0x400
 184 #define PREFIX_FWAIT 0x800
 185
 186 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 187    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 188    on error.  */
 189 #define FETCH_DATA(info, addr) \
 190   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 191    ? 1 : fetch_data ((info), (addr)))
 192
 193 static int
 194 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 195 {
 196   int status;
 197   struct dis_private *priv = (struct dis_private *) info->private_data;
 198   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 199
 200   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 201     status = (*info->read_memory_func) (start,
 202                                         priv->max_fetched,
 203                                         addr - priv->max_fetched,
 204                                         info);
 205   else
 206     status = -1;
 207   if (status != 0)
 208     {
 209       /* If we did manage to read at least one byte, then
 210          print_insn_i386 will do something sensible.  Otherwise, print
 211          an error.  We do that here because this is where we know
 212          STATUS.  */
 213       if (priv->max_fetched == priv->the_buffer)
 214         (*info->memory_error_func) (status, start, info);
 215       longjmp (priv->bailout, 1);
 216     }
 217   else
 218     priv->max_fetched = addr;
 219   return 1;
 220 }
 221
 222 #define XX { NULL, 0 }
 223 #define Bad_Opcode NULL, { { NULL, 0 } }
 224
 225 #define Eb { OP_E, b_mode }
 226 #define Ebnd { OP_E, bnd_mode }
 227 #define EbS { OP_E, b_swap_mode }
 228 #define Ev { OP_E, v_mode }
 229 #define Ev_bnd { OP_E, v_bnd_mode }
 230 #define EvS { OP_E, v_swap_mode }
 231 #define Ed { OP_E, d_mode }
 232 #define Edq { OP_E, dq_mode }
 233 #define Edqw { OP_E, dqw_mode }
 234 #define Edqb { OP_E, dqb_mode }
 235 #define Edqd { OP_E, dqd_mode }
 236 #define Eq { OP_E, q_mode }
 237 #define indirEv { OP_indirE, stack_v_mode }
 238 #define indirEp { OP_indirE, f_mode }
 239 #define stackEv { OP_E, stack_v_mode }
 240 #define Em { OP_E, m_mode }
 241 #define Ew { OP_E, w_mode }
 242 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 243 #define Ma { OP_M, a_mode }
 244 #define Mb { OP_M, b_mode }
 245 #define Md { OP_M, d_mode }
 246 #define Mo { OP_M, o_mode }
 247 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 248 #define Mq { OP_M, q_mode }
 249 #define Mx { OP_M, x_mode }
 250 #define Mxmm { OP_M, xmm_mode }
 251 #define Gb { OP_G, b_mode }
 252 #define Gbnd { OP_G, bnd_mode }
 253 #define Gv { OP_G, v_mode }
 254 #define Gd { OP_G, d_mode }
 255 #define Gdq { OP_G, dq_mode }
 256 #define Gm { OP_G, m_mode }
 257 #define Gw { OP_G, w_mode }
 258 #define Rd { OP_R, d_mode }
 259 #define Rm { OP_R, m_mode }
 260 #define Ib { OP_I, b_mode }
 261 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 262 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 263 #define Iv { OP_I, v_mode }
 264 #define sIv { OP_sI, v_mode }
 265 #define Iq { OP_I, q_mode }
 266 #define Iv64 { OP_I64, v_mode }
 267 #define Iw { OP_I, w_mode }
 268 #define I1 { OP_I, const_1_mode }
 269 #define Jb { OP_J, b_mode }
 270 #define Jv { OP_J, v_mode }
 271 #define Cm { OP_C, m_mode }
 272 #define Dm { OP_D, m_mode }
 273 #define Td { OP_T, d_mode }
 274 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 275
 276 #define RMeAX { OP_REG, eAX_reg }
 277 #define RMeBX { OP_REG, eBX_reg }
 278 #define RMeCX { OP_REG, eCX_reg }
 279 #define RMeDX { OP_REG, eDX_reg }
 280 #define RMeSP { OP_REG, eSP_reg }
 281 #define RMeBP { OP_REG, eBP_reg }
 282 #define RMeSI { OP_REG, eSI_reg }
 283 #define RMeDI { OP_REG, eDI_reg }
 284 #define RMrAX { OP_REG, rAX_reg }
 285 #define RMrBX { OP_REG, rBX_reg }
 286 #define RMrCX { OP_REG, rCX_reg }
 287 #define RMrDX { OP_REG, rDX_reg }
 288 #define RMrSP { OP_REG, rSP_reg }
 289 #define RMrBP { OP_REG, rBP_reg }
 290 #define RMrSI { OP_REG, rSI_reg }
 291 #define RMrDI { OP_REG, rDI_reg }
 292 #define RMAL { OP_REG, al_reg }
 293 #define RMCL { OP_REG, cl_reg }
 294 #define RMDL { OP_REG, dl_reg }
 295 #define RMBL { OP_REG, bl_reg }
 296 #define RMAH { OP_REG, ah_reg }
 297 #define RMCH { OP_REG, ch_reg }
 298 #define RMDH { OP_REG, dh_reg }
 299 #define RMBH { OP_REG, bh_reg }
 300 #define RMAX { OP_REG, ax_reg }
 301 #define RMDX { OP_REG, dx_reg }
 302
 303 #define eAX { OP_IMREG, eAX_reg }
 304 #define eBX { OP_IMREG, eBX_reg }
 305 #define eCX { OP_IMREG, eCX_reg }
 306 #define eDX { OP_IMREG, eDX_reg }
 307 #define eSP { OP_IMREG, eSP_reg }
 308 #define eBP { OP_IMREG, eBP_reg }
 309 #define eSI { OP_IMREG, eSI_reg }
 310 #define eDI { OP_IMREG, eDI_reg }
 311 #define AL { OP_IMREG, al_reg }
 312 #define CL { OP_IMREG, cl_reg }
 313 #define DL { OP_IMREG, dl_reg }
 314 #define BL { OP_IMREG, bl_reg }
 315 #define AH { OP_IMREG, ah_reg }
 316 #define CH { OP_IMREG, ch_reg }
 317 #define DH { OP_IMREG, dh_reg }
 318 #define BH { OP_IMREG, bh_reg }
 319 #define AX { OP_IMREG, ax_reg }
 320 #define DX { OP_IMREG, dx_reg }
 321 #define zAX { OP_IMREG, z_mode_ax_reg }
 322 #define indirDX { OP_IMREG, indir_dx_reg }
 323
 324 #define Sw { OP_SEG, w_mode }
 325 #define Sv { OP_SEG, v_mode }
 326 #define Ap { OP_DIR, 0 }
 327 #define Ob { OP_OFF64, b_mode }
 328 #define Ov { OP_OFF64, v_mode }
 329 #define Xb { OP_DSreg, eSI_reg }
 330 #define Xv { OP_DSreg, eSI_reg }
 331 #define Xz { OP_DSreg, eSI_reg }
 332 #define Yb { OP_ESreg, eDI_reg }
 333 #define Yv { OP_ESreg, eDI_reg }
 334 #define DSBX { OP_DSreg, eBX_reg }
 335
 336 #define es { OP_REG, es_reg }
 337 #define ss { OP_REG, ss_reg }
 338 #define cs { OP_REG, cs_reg }
 339 #define ds { OP_REG, ds_reg }
 340 #define fs { OP_REG, fs_reg }
 341 #define gs { OP_REG, gs_reg }
 342
 343 #define MX { OP_MMX, 0 }
 344 #define XM { OP_XMM, 0 }
 345 #define XMScalar { OP_XMM, scalar_mode }
 346 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 347 #define XMM { OP_XMM, xmm_mode }
 348 #define EM { OP_EM, v_mode }
 349 #define EMS { OP_EM, v_swap_mode }
 350 #define EMd { OP_EM, d_mode }
 351 #define EMx { OP_EM, x_mode }
 352 #define EXw { OP_EX, w_mode }
 353 #define EXd { OP_EX, d_mode }
 354 #define EXdScalar { OP_EX, d_scalar_mode }
 355 #define EXdS { OP_EX, d_swap_mode }
 356 #define EXq { OP_EX, q_mode }
 357 #define EXqScalar { OP_EX, q_scalar_mode }
 358 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 359 #define EXqS { OP_EX, q_swap_mode }
 360 #define EXx { OP_EX, x_mode }
 361 #define EXxS { OP_EX, x_swap_mode }
 362 #define EXxmm { OP_EX, xmm_mode }
 363 #define EXxmmq { OP_EX, xmmq_mode }
 364 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 365 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 366 #define EXxmm_md { OP_EX, xmm_md_mode }
 367 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 368 #define EXxmmdw { OP_EX, xmmdw_mode }
 369 #define EXxmmqd { OP_EX, xmmqd_mode }
 370 #define EXymmq { OP_EX, ymmq_mode }
 371 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 372 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 373 #define MS { OP_MS, v_mode }
 374 #define XS { OP_XS, v_mode }
 375 #define EMCq { OP_EMC, q_mode }
 376 #define MXC { OP_MXC, 0 }
 377 #define OPSUF { OP_3DNowSuffix, 0 }
 378 #define CMP { CMP_Fixup, 0 }
 379 #define XMM0 { XMM_Fixup, 0 }
 380 #define FXSAVE { FXSAVE_Fixup, 0 }
 381 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 382 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 383
 384 #define Vex { OP_VEX, vex_mode }
 385 #define VexScalar { OP_VEX, vex_scalar_mode }
 386 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 387 #define Vex128 { OP_VEX, vex128_mode }
 388 #define Vex256 { OP_VEX, vex256_mode }
 389 #define VexGdq { OP_VEX, dq_mode }
 390 #define VexI4 { VEXI4_Fixup, 0}
 391 #define EXdVex { OP_EX_Vex, d_mode }
 392 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 393 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 394 #define EXqVex { OP_EX_Vex, q_mode }
 395 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 396 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 397 #define EXVexW { OP_EX_VexW, x_mode }
 398 #define EXdVexW { OP_EX_VexW, d_mode }
 399 #define EXqVexW { OP_EX_VexW, q_mode }
 400 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 401 #define XMVex { OP_XMM_Vex, 0 }
 402 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 403 #define XMVexW { OP_XMM_VexW, 0 }
 404 #define XMVexI4 { OP_REG_VexI4, x_mode }
 405 #define PCLMUL { PCLMUL_Fixup, 0 }
 406 #define VZERO { VZERO_Fixup, 0 }
 407 #define VCMP { VCMP_Fixup, 0 }
 408
 409 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 410 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 411
 412 /* Used handle "rep" prefix for string instructions.  */
 413 #define Xbr { REP_Fixup, eSI_reg }
 414 #define Xvr { REP_Fixup, eSI_reg }
 415 #define Ybr { REP_Fixup, eDI_reg }
 416 #define Yvr { REP_Fixup, eDI_reg }
 417 #define Yzr { REP_Fixup, eDI_reg }
 418 #define indirDXr { REP_Fixup, indir_dx_reg }
 419 #define ALr { REP_Fixup, al_reg }
 420 #define eAXr { REP_Fixup, eAX_reg }
 421
 422 /* Used handle HLE prefix for lockable instructions.  */
 423 #define Ebh1 { HLE_Fixup1, b_mode }
 424 #define Evh1 { HLE_Fixup1, v_mode }
 425 #define Ebh2 { HLE_Fixup2, b_mode }
 426 #define Evh2 { HLE_Fixup2, v_mode }
 427 #define Ebh3 { HLE_Fixup3, b_mode }
 428 #define Evh3 { HLE_Fixup3, v_mode }
 429
 430 #define BND { BND_Fixup, 0 }
 431
 432 #define cond_jump_flag { NULL, cond_jump_mode }
 433 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 434
 435 /* bits in sizeflag */
 436 #define SUFFIX_ALWAYS 4
 437 #define AFLAG 2
 438 #define DFLAG 1
 439
 440 enum
 441 {
 442   /* byte operand */
 443   b_mode = 1,
 444   /* byte operand with operand swapped */
 445   b_swap_mode,
 446   /* byte operand, sign extend like 'T' suffix */
 447   b_T_mode,
 448   /* operand size depends on prefixes */
 449   v_mode,
 450   /* operand size depends on prefixes with operand swapped */
 451   v_swap_mode,
 452   /* word operand */
 453   w_mode,
 454   /* double word operand  */
 455   d_mode,
 456   /* double word operand with operand swapped */
 457   d_swap_mode,
 458   /* quad word operand */
 459   q_mode,
 460   /* quad word operand with operand swapped */
 461   q_swap_mode,
 462   /* ten-byte operand */
 463   t_mode,
 464   /* 16-byte XMM or 32-byte YMM operand */
 465   x_mode,
 466   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 467   x_swap_mode,
 468   /* 16-byte XMM operand */
 469   xmm_mode,
 470   /* 16-byte XMM or quad word operand */
 471   xmmq_mode,
 472   /* XMM register or byte memory operand */
 473   xmm_mb_mode,
 474   /* XMM register or word memory operand */
 475   xmm_mw_mode,
 476   /* XMM register or double word memory operand */
 477   xmm_md_mode,
 478   /* XMM register or quad word memory operand */
 479   xmm_mq_mode,
 480   /* 16-byte XMM, word or double word operand  */
 481   xmmdw_mode,
 482   /* 16-byte XMM, double word or quad word operand */
 483   xmmqd_mode,
 484   /* 32-byte YMM or quad word operand */
 485   ymmq_mode,
 486   /* 32-byte YMM or 16-byte word operand */
 487   ymmxmm_mode,
 488   /* d_mode in 32bit, q_mode in 64bit mode.  */
 489   m_mode,
 490   /* pair of v_mode operands */
 491   a_mode,
 492   cond_jump_mode,
 493   loop_jcxz_mode,
 494   v_bnd_mode,
 495   /* operand size depends on REX prefixes.  */
 496   dq_mode,
 497   /* registers like dq_mode, memory like w_mode.  */
 498   dqw_mode,
 499   bnd_mode,
 500   /* 4- or 6-byte pointer operand */
 501   f_mode,
 502   const_1_mode,
 503   /* v_mode for stack-related opcodes.  */
 504   stack_v_mode,
 505   /* non-quad operand size depends on prefixes */
 506   z_mode,
 507   /* 16-byte operand */
 508   o_mode,
 509   /* registers like dq_mode, memory like b_mode.  */
 510   dqb_mode,
 511   /* registers like dq_mode, memory like d_mode.  */
 512   dqd_mode,
 513   /* normal vex mode */
 514   vex_mode,
 515   /* 128bit vex mode */
 516   vex128_mode,
 517   /* 256bit vex mode */
 518   vex256_mode,
 519   /* operand size depends on the VEX.W bit.  */
 520   vex_w_dq_mode,
 521
 522   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 523   vex_vsib_d_w_dq_mode,
 524   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 525   vex_vsib_q_w_dq_mode,
 526
 527   /* scalar, ignore vector length.  */
 528   scalar_mode,
 529   /* like d_mode, ignore vector length.  */
 530   d_scalar_mode,
 531   /* like d_swap_mode, ignore vector length.  */
 532   d_scalar_swap_mode,
 533   /* like q_mode, ignore vector length.  */
 534   q_scalar_mode,
 535   /* like q_swap_mode, ignore vector length.  */
 536   q_scalar_swap_mode,
 537   /* like vex_mode, ignore vector length.  */
 538   vex_scalar_mode,
 539   /* like vex_w_dq_mode, ignore vector length.  */
 540   vex_scalar_w_dq_mode,
 541
 542   es_reg,
 543   cs_reg,
 544   ss_reg,
 545   ds_reg,
 546   fs_reg,
 547   gs_reg,
 548
 549   eAX_reg,
 550   eCX_reg,
 551   eDX_reg,
 552   eBX_reg,
 553   eSP_reg,
 554   eBP_reg,
 555   eSI_reg,
 556   eDI_reg,
 557
 558   al_reg,
 559   cl_reg,
 560   dl_reg,
 561   bl_reg,
 562   ah_reg,
 563   ch_reg,
 564   dh_reg,
 565   bh_reg,
 566
 567   ax_reg,
 568   cx_reg,
 569   dx_reg,
 570   bx_reg,
 571   sp_reg,
 572   bp_reg,
 573   si_reg,
 574   di_reg,
 575
 576   rAX_reg,
 577   rCX_reg,
 578   rDX_reg,
 579   rBX_reg,
 580   rSP_reg,
 581   rBP_reg,
 582   rSI_reg,
 583   rDI_reg,
 584
 585   z_mode_ax_reg,
 586   indir_dx_reg
 587 };
 588
 589 enum
 590 {
 591   FLOATCODE = 1,
 592   USE_REG_TABLE,
 593   USE_MOD_TABLE,
 594   USE_RM_TABLE,
 595   USE_PREFIX_TABLE,
 596   USE_X86_64_TABLE,
 597   USE_3BYTE_TABLE,
 598   USE_XOP_8F_TABLE,
 599   USE_VEX_C4_TABLE,
 600   USE_VEX_C5_TABLE,
 601   USE_VEX_LEN_TABLE,
 602   USE_VEX_W_TABLE
 603 };
 604
 605 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 606
 607 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 608 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 609 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 610 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 611 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 612 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 613 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 614 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 615 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 616 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 617 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 618 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 619
 620 enum
 621 {
 622   REG_80 = 0,
 623   REG_81,
 624   REG_82,
 625   REG_8F,
 626   REG_C0,
 627   REG_C1,
 628   REG_C6,
 629   REG_C7,
 630   REG_D0,
 631   REG_D1,
 632   REG_D2,
 633   REG_D3,
 634   REG_F6,
 635   REG_F7,
 636   REG_FE,
 637   REG_FF,
 638   REG_0F00,
 639   REG_0F01,
 640   REG_0F0D,
 641   REG_0F18,
 642   REG_0F71,
 643   REG_0F72,
 644   REG_0F73,
 645   REG_0FA6,
 646   REG_0FA7,
 647   REG_0FAE,
 648   REG_0FBA,
 649   REG_0FC7,
 650   REG_VEX_0F71,
 651   REG_VEX_0F72,
 652   REG_VEX_0F73,
 653   REG_VEX_0FAE,
 654   REG_VEX_0F38F3,
 655   REG_XOP_LWPCB,
 656   REG_XOP_LWP,
 657   REG_XOP_TBM_01,
 658   REG_XOP_TBM_02
 659 };
 660
 661 enum
 662 {
 663   MOD_8D = 0,
 664   MOD_C6_REG_7,
 665   MOD_C7_REG_7,
 666   MOD_0F01_REG_0,
 667   MOD_0F01_REG_1,
 668   MOD_0F01_REG_2,
 669   MOD_0F01_REG_3,
 670   MOD_0F01_REG_7,
 671   MOD_0F12_PREFIX_0,
 672   MOD_0F13,
 673   MOD_0F16_PREFIX_0,
 674   MOD_0F17,
 675   MOD_0F18_REG_0,
 676   MOD_0F18_REG_1,
 677   MOD_0F18_REG_2,
 678   MOD_0F18_REG_3,
 679   MOD_0F18_REG_4,
 680   MOD_0F18_REG_5,
 681   MOD_0F18_REG_6,
 682   MOD_0F18_REG_7,
 683   MOD_0F1A_PREFIX_0,
 684   MOD_0F1B_PREFIX_0,
 685   MOD_0F1B_PREFIX_1,
 686   MOD_0F20,
 687   MOD_0F21,
 688   MOD_0F22,
 689   MOD_0F23,
 690   MOD_0F24,
 691   MOD_0F26,
 692   MOD_0F2B_PREFIX_0,
 693   MOD_0F2B_PREFIX_1,
 694   MOD_0F2B_PREFIX_2,
 695   MOD_0F2B_PREFIX_3,
 696   MOD_0F51,
 697   MOD_0F71_REG_2,
 698   MOD_0F71_REG_4,
 699   MOD_0F71_REG_6,
 700   MOD_0F72_REG_2,
 701   MOD_0F72_REG_4,
 702   MOD_0F72_REG_6,
 703   MOD_0F73_REG_2,
 704   MOD_0F73_REG_3,
 705   MOD_0F73_REG_6,
 706   MOD_0F73_REG_7,
 707   MOD_0FAE_REG_0,
 708   MOD_0FAE_REG_1,
 709   MOD_0FAE_REG_2,
 710   MOD_0FAE_REG_3,
 711   MOD_0FAE_REG_4,
 712   MOD_0FAE_REG_5,
 713   MOD_0FAE_REG_6,
 714   MOD_0FAE_REG_7,
 715   MOD_0FB2,
 716   MOD_0FB4,
 717   MOD_0FB5,
 718   MOD_0FC7_REG_6,
 719   MOD_0FC7_REG_7,
 720   MOD_0FD7,
 721   MOD_0FE7_PREFIX_2,
 722   MOD_0FF0_PREFIX_3,
 723   MOD_0F382A_PREFIX_2,
 724   MOD_62_32BIT,
 725   MOD_C4_32BIT,
 726   MOD_C5_32BIT,
 727   MOD_VEX_0F12_PREFIX_0,
 728   MOD_VEX_0F13,
 729   MOD_VEX_0F16_PREFIX_0,
 730   MOD_VEX_0F17,
 731   MOD_VEX_0F2B,
 732   MOD_VEX_0F50,
 733   MOD_VEX_0F71_REG_2,
 734   MOD_VEX_0F71_REG_4,
 735   MOD_VEX_0F71_REG_6,
 736   MOD_VEX_0F72_REG_2,
 737   MOD_VEX_0F72_REG_4,
 738   MOD_VEX_0F72_REG_6,
 739   MOD_VEX_0F73_REG_2,
 740   MOD_VEX_0F73_REG_3,
 741   MOD_VEX_0F73_REG_6,
 742   MOD_VEX_0F73_REG_7,
 743   MOD_VEX_0FAE_REG_2,
 744   MOD_VEX_0FAE_REG_3,
 745   MOD_VEX_0FD7_PREFIX_2,
 746   MOD_VEX_0FE7_PREFIX_2,
 747   MOD_VEX_0FF0_PREFIX_3,
 748   MOD_VEX_0F381A_PREFIX_2,
 749   MOD_VEX_0F382A_PREFIX_2,
 750   MOD_VEX_0F382C_PREFIX_2,
 751   MOD_VEX_0F382D_PREFIX_2,
 752   MOD_VEX_0F382E_PREFIX_2,
 753   MOD_VEX_0F382F_PREFIX_2,
 754   MOD_VEX_0F385A_PREFIX_2,
 755   MOD_VEX_0F388C_PREFIX_2,
 756   MOD_VEX_0F388E_PREFIX_2,
 757 };
 758
 759 enum
 760 {
 761   RM_C6_REG_7 = 0,
 762   RM_C7_REG_7,
 763   RM_0F01_REG_0,
 764   RM_0F01_REG_1,
 765   RM_0F01_REG_2,
 766   RM_0F01_REG_3,
 767   RM_0F01_REG_7,
 768   RM_0FAE_REG_5,
 769   RM_0FAE_REG_6,
 770   RM_0FAE_REG_7
 771 };
 772
 773 enum
 774 {
 775   PREFIX_90 = 0,
 776   PREFIX_0F10,
 777   PREFIX_0F11,
 778   PREFIX_0F12,
 779   PREFIX_0F16,
 780   PREFIX_0F1A,
 781   PREFIX_0F1B,
 782   PREFIX_0F2A,
 783   PREFIX_0F2B,
 784   PREFIX_0F2C,
 785   PREFIX_0F2D,
 786   PREFIX_0F2E,
 787   PREFIX_0F2F,
 788   PREFIX_0F51,
 789   PREFIX_0F52,
 790   PREFIX_0F53,
 791   PREFIX_0F58,
 792   PREFIX_0F59,
 793   PREFIX_0F5A,
 794   PREFIX_0F5B,
 795   PREFIX_0F5C,
 796   PREFIX_0F5D,
 797   PREFIX_0F5E,
 798   PREFIX_0F5F,
 799   PREFIX_0F60,
 800   PREFIX_0F61,
 801   PREFIX_0F62,
 802   PREFIX_0F6C,
 803   PREFIX_0F6D,
 804   PREFIX_0F6F,
 805   PREFIX_0F70,
 806   PREFIX_0F73_REG_3,
 807   PREFIX_0F73_REG_7,
 808   PREFIX_0F78,
 809   PREFIX_0F79,
 810   PREFIX_0F7C,
 811   PREFIX_0F7D,
 812   PREFIX_0F7E,
 813   PREFIX_0F7F,
 814   PREFIX_0FAE_REG_0,
 815   PREFIX_0FAE_REG_1,
 816   PREFIX_0FAE_REG_2,
 817   PREFIX_0FAE_REG_3,
 818   PREFIX_0FB8,
 819   PREFIX_0FBC,
 820   PREFIX_0FBD,
 821   PREFIX_0FC2,
 822   PREFIX_0FC3,
 823   PREFIX_0FC7_REG_6,
 824   PREFIX_0FD0,
 825   PREFIX_0FD6,
 826   PREFIX_0FE6,
 827   PREFIX_0FE7,
 828   PREFIX_0FF0,
 829   PREFIX_0FF7,
 830   PREFIX_0F3810,
 831   PREFIX_0F3814,
 832   PREFIX_0F3815,
 833   PREFIX_0F3817,
 834   PREFIX_0F3820,
 835   PREFIX_0F3821,
 836   PREFIX_0F3822,
 837   PREFIX_0F3823,
 838   PREFIX_0F3824,
 839   PREFIX_0F3825,
 840   PREFIX_0F3828,
 841   PREFIX_0F3829,
 842   PREFIX_0F382A,
 843   PREFIX_0F382B,
 844   PREFIX_0F3830,
 845   PREFIX_0F3831,
 846   PREFIX_0F3832,
 847   PREFIX_0F3833,
 848   PREFIX_0F3834,
 849   PREFIX_0F3835,
 850   PREFIX_0F3837,
 851   PREFIX_0F3838,
 852   PREFIX_0F3839,
 853   PREFIX_0F383A,
 854   PREFIX_0F383B,
 855   PREFIX_0F383C,
 856   PREFIX_0F383D,
 857   PREFIX_0F383E,
 858   PREFIX_0F383F,
 859   PREFIX_0F3840,
 860   PREFIX_0F3841,
 861   PREFIX_0F3880,
 862   PREFIX_0F3881,
 863   PREFIX_0F3882,
 864   PREFIX_0F38DB,
 865   PREFIX_0F38DC,
 866   PREFIX_0F38DD,
 867   PREFIX_0F38DE,
 868   PREFIX_0F38DF,
 869   PREFIX_0F38F0,
 870   PREFIX_0F38F1,
 871   PREFIX_0F38F6,
 872   PREFIX_0F3A08,
 873   PREFIX_0F3A09,
 874   PREFIX_0F3A0A,
 875   PREFIX_0F3A0B,
 876   PREFIX_0F3A0C,
 877   PREFIX_0F3A0D,
 878   PREFIX_0F3A0E,
 879   PREFIX_0F3A14,
 880   PREFIX_0F3A15,
 881   PREFIX_0F3A16,
 882   PREFIX_0F3A17,
 883   PREFIX_0F3A20,
 884   PREFIX_0F3A21,
 885   PREFIX_0F3A22,
 886   PREFIX_0F3A40,
 887   PREFIX_0F3A41,
 888   PREFIX_0F3A42,
 889   PREFIX_0F3A44,
 890   PREFIX_0F3A60,
 891   PREFIX_0F3A61,
 892   PREFIX_0F3A62,
 893   PREFIX_0F3A63,
 894   PREFIX_0F3ADF,
 895   PREFIX_VEX_0F10,
 896   PREFIX_VEX_0F11,
 897   PREFIX_VEX_0F12,
 898   PREFIX_VEX_0F16,
 899   PREFIX_VEX_0F2A,
 900   PREFIX_VEX_0F2C,
 901   PREFIX_VEX_0F2D,
 902   PREFIX_VEX_0F2E,
 903   PREFIX_VEX_0F2F,
 904   PREFIX_VEX_0F51,
 905   PREFIX_VEX_0F52,
 906   PREFIX_VEX_0F53,
 907   PREFIX_VEX_0F58,
 908   PREFIX_VEX_0F59,
 909   PREFIX_VEX_0F5A,
 910   PREFIX_VEX_0F5B,
 911   PREFIX_VEX_0F5C,
 912   PREFIX_VEX_0F5D,
 913   PREFIX_VEX_0F5E,
 914   PREFIX_VEX_0F5F,
 915   PREFIX_VEX_0F60,
 916   PREFIX_VEX_0F61,
 917   PREFIX_VEX_0F62,
 918   PREFIX_VEX_0F63,
 919   PREFIX_VEX_0F64,
 920   PREFIX_VEX_0F65,
 921   PREFIX_VEX_0F66,
 922   PREFIX_VEX_0F67,
 923   PREFIX_VEX_0F68,
 924   PREFIX_VEX_0F69,
 925   PREFIX_VEX_0F6A,
 926   PREFIX_VEX_0F6B,
 927   PREFIX_VEX_0F6C,
 928   PREFIX_VEX_0F6D,
 929   PREFIX_VEX_0F6E,
 930   PREFIX_VEX_0F6F,
 931   PREFIX_VEX_0F70,
 932   PREFIX_VEX_0F71_REG_2,
 933   PREFIX_VEX_0F71_REG_4,
 934   PREFIX_VEX_0F71_REG_6,
 935   PREFIX_VEX_0F72_REG_2,
 936   PREFIX_VEX_0F72_REG_4,
 937   PREFIX_VEX_0F72_REG_6,
 938   PREFIX_VEX_0F73_REG_2,
 939   PREFIX_VEX_0F73_REG_3,
 940   PREFIX_VEX_0F73_REG_6,
 941   PREFIX_VEX_0F73_REG_7,
 942   PREFIX_VEX_0F74,
 943   PREFIX_VEX_0F75,
 944   PREFIX_VEX_0F76,
 945   PREFIX_VEX_0F77,
 946   PREFIX_VEX_0F7C,
 947   PREFIX_VEX_0F7D,
 948   PREFIX_VEX_0F7E,
 949   PREFIX_VEX_0F7F,
 950   PREFIX_VEX_0FC2,
 951   PREFIX_VEX_0FC4,
 952   PREFIX_VEX_0FC5,
 953   PREFIX_VEX_0FD0,
 954   PREFIX_VEX_0FD1,
 955   PREFIX_VEX_0FD2,
 956   PREFIX_VEX_0FD3,
 957   PREFIX_VEX_0FD4,
 958   PREFIX_VEX_0FD5,
 959   PREFIX_VEX_0FD6,
 960   PREFIX_VEX_0FD7,
 961   PREFIX_VEX_0FD8,
 962   PREFIX_VEX_0FD9,
 963   PREFIX_VEX_0FDA,
 964   PREFIX_VEX_0FDB,
 965   PREFIX_VEX_0FDC,
 966   PREFIX_VEX_0FDD,
 967   PREFIX_VEX_0FDE,
 968   PREFIX_VEX_0FDF,
 969   PREFIX_VEX_0FE0,
 970   PREFIX_VEX_0FE1,
 971   PREFIX_VEX_0FE2,
 972   PREFIX_VEX_0FE3,
 973   PREFIX_VEX_0FE4,
 974   PREFIX_VEX_0FE5,
 975   PREFIX_VEX_0FE6,
 976   PREFIX_VEX_0FE7,
 977   PREFIX_VEX_0FE8,
 978   PREFIX_VEX_0FE9,
 979   PREFIX_VEX_0FEA,
 980   PREFIX_VEX_0FEB,
 981   PREFIX_VEX_0FEC,
 982   PREFIX_VEX_0FED,
 983   PREFIX_VEX_0FEE,
 984   PREFIX_VEX_0FEF,
 985   PREFIX_VEX_0FF0,
 986   PREFIX_VEX_0FF1,
 987   PREFIX_VEX_0FF2,
 988   PREFIX_VEX_0FF3,
 989   PREFIX_VEX_0FF4,
 990   PREFIX_VEX_0FF5,
 991   PREFIX_VEX_0FF6,
 992   PREFIX_VEX_0FF7,
 993   PREFIX_VEX_0FF8,
 994   PREFIX_VEX_0FF9,
 995   PREFIX_VEX_0FFA,
 996   PREFIX_VEX_0FFB,
 997   PREFIX_VEX_0FFC,
 998   PREFIX_VEX_0FFD,
 999   PREFIX_VEX_0FFE,
1000   PREFIX_VEX_0F3800,
1001   PREFIX_VEX_0F3801,
1002   PREFIX_VEX_0F3802,
1003   PREFIX_VEX_0F3803,
1004   PREFIX_VEX_0F3804,
1005   PREFIX_VEX_0F3805,
1006   PREFIX_VEX_0F3806,
1007   PREFIX_VEX_0F3807,
1008   PREFIX_VEX_0F3808,
1009   PREFIX_VEX_0F3809,
1010   PREFIX_VEX_0F380A,
1011   PREFIX_VEX_0F380B,
1012   PREFIX_VEX_0F380C,
1013   PREFIX_VEX_0F380D,
1014   PREFIX_VEX_0F380E,
1015   PREFIX_VEX_0F380F,
1016   PREFIX_VEX_0F3813,
1017   PREFIX_VEX_0F3816,
1018   PREFIX_VEX_0F3817,
1019   PREFIX_VEX_0F3818,
1020   PREFIX_VEX_0F3819,
1021   PREFIX_VEX_0F381A,
1022   PREFIX_VEX_0F381C,
1023   PREFIX_VEX_0F381D,
1024   PREFIX_VEX_0F381E,
1025   PREFIX_VEX_0F3820,
1026   PREFIX_VEX_0F3821,
1027   PREFIX_VEX_0F3822,
1028   PREFIX_VEX_0F3823,
1029   PREFIX_VEX_0F3824,
1030   PREFIX_VEX_0F3825,
1031   PREFIX_VEX_0F3828,
1032   PREFIX_VEX_0F3829,
1033   PREFIX_VEX_0F382A,
1034   PREFIX_VEX_0F382B,
1035   PREFIX_VEX_0F382C,
1036   PREFIX_VEX_0F382D,
1037   PREFIX_VEX_0F382E,
1038   PREFIX_VEX_0F382F,
1039   PREFIX_VEX_0F3830,
1040   PREFIX_VEX_0F3831,
1041   PREFIX_VEX_0F3832,
1042   PREFIX_VEX_0F3833,
1043   PREFIX_VEX_0F3834,
1044   PREFIX_VEX_0F3835,
1045   PREFIX_VEX_0F3836,
1046   PREFIX_VEX_0F3837,
1047   PREFIX_VEX_0F3838,
1048   PREFIX_VEX_0F3839,
1049   PREFIX_VEX_0F383A,
1050   PREFIX_VEX_0F383B,
1051   PREFIX_VEX_0F383C,
1052   PREFIX_VEX_0F383D,
1053   PREFIX_VEX_0F383E,
1054   PREFIX_VEX_0F383F,
1055   PREFIX_VEX_0F3840,
1056   PREFIX_VEX_0F3841,
1057   PREFIX_VEX_0F3845,
1058   PREFIX_VEX_0F3846,
1059   PREFIX_VEX_0F3847,
1060   PREFIX_VEX_0F3858,
1061   PREFIX_VEX_0F3859,
1062   PREFIX_VEX_0F385A,
1063   PREFIX_VEX_0F3878,
1064   PREFIX_VEX_0F3879,
1065   PREFIX_VEX_0F388C,
1066   PREFIX_VEX_0F388E,
1067   PREFIX_VEX_0F3890,
1068   PREFIX_VEX_0F3891,
1069   PREFIX_VEX_0F3892,
1070   PREFIX_VEX_0F3893,
1071   PREFIX_VEX_0F3896,
1072   PREFIX_VEX_0F3897,
1073   PREFIX_VEX_0F3898,
1074   PREFIX_VEX_0F3899,
1075   PREFIX_VEX_0F389A,
1076   PREFIX_VEX_0F389B,
1077   PREFIX_VEX_0F389C,
1078   PREFIX_VEX_0F389D,
1079   PREFIX_VEX_0F389E,
1080   PREFIX_VEX_0F389F,
1081   PREFIX_VEX_0F38A6,
1082   PREFIX_VEX_0F38A7,
1083   PREFIX_VEX_0F38A8,
1084   PREFIX_VEX_0F38A9,
1085   PREFIX_VEX_0F38AA,
1086   PREFIX_VEX_0F38AB,
1087   PREFIX_VEX_0F38AC,
1088   PREFIX_VEX_0F38AD,
1089   PREFIX_VEX_0F38AE,
1090   PREFIX_VEX_0F38AF,
1091   PREFIX_VEX_0F38B6,
1092   PREFIX_VEX_0F38B7,
1093   PREFIX_VEX_0F38B8,
1094   PREFIX_VEX_0F38B9,
1095   PREFIX_VEX_0F38BA,
1096   PREFIX_VEX_0F38BB,
1097   PREFIX_VEX_0F38BC,
1098   PREFIX_VEX_0F38BD,
1099   PREFIX_VEX_0F38BE,
1100   PREFIX_VEX_0F38BF,
1101   PREFIX_VEX_0F38DB,
1102   PREFIX_VEX_0F38DC,
1103   PREFIX_VEX_0F38DD,
1104   PREFIX_VEX_0F38DE,
1105   PREFIX_VEX_0F38DF,
1106   PREFIX_VEX_0F38F2,
1107   PREFIX_VEX_0F38F3_REG_1,
1108   PREFIX_VEX_0F38F3_REG_2,
1109   PREFIX_VEX_0F38F3_REG_3,
1110   PREFIX_VEX_0F38F5,
1111   PREFIX_VEX_0F38F6,
1112   PREFIX_VEX_0F38F7,
1113   PREFIX_VEX_0F3A00,
1114   PREFIX_VEX_0F3A01,
1115   PREFIX_VEX_0F3A02,
1116   PREFIX_VEX_0F3A04,
1117   PREFIX_VEX_0F3A05,
1118   PREFIX_VEX_0F3A06,
1119   PREFIX_VEX_0F3A08,
1120   PREFIX_VEX_0F3A09,
1121   PREFIX_VEX_0F3A0A,
1122   PREFIX_VEX_0F3A0B,
1123   PREFIX_VEX_0F3A0C,
1124   PREFIX_VEX_0F3A0D,
1125   PREFIX_VEX_0F3A0E,
1126   PREFIX_VEX_0F3A0F,
1127   PREFIX_VEX_0F3A14,
1128   PREFIX_VEX_0F3A15,
1129   PREFIX_VEX_0F3A16,
1130   PREFIX_VEX_0F3A17,
1131   PREFIX_VEX_0F3A18,
1132   PREFIX_VEX_0F3A19,
1133   PREFIX_VEX_0F3A1D,
1134   PREFIX_VEX_0F3A20,
1135   PREFIX_VEX_0F3A21,
1136   PREFIX_VEX_0F3A22,
1137   PREFIX_VEX_0F3A38,
1138   PREFIX_VEX_0F3A39,
1139   PREFIX_VEX_0F3A40,
1140   PREFIX_VEX_0F3A41,
1141   PREFIX_VEX_0F3A42,
1142   PREFIX_VEX_0F3A44,
1143   PREFIX_VEX_0F3A46,
1144   PREFIX_VEX_0F3A48,
1145   PREFIX_VEX_0F3A49,
1146   PREFIX_VEX_0F3A4A,
1147   PREFIX_VEX_0F3A4B,
1148   PREFIX_VEX_0F3A4C,
1149   PREFIX_VEX_0F3A5C,
1150   PREFIX_VEX_0F3A5D,
1151   PREFIX_VEX_0F3A5E,
1152   PREFIX_VEX_0F3A5F,
1153   PREFIX_VEX_0F3A60,
1154   PREFIX_VEX_0F3A61,
1155   PREFIX_VEX_0F3A62,
1156   PREFIX_VEX_0F3A63,
1157   PREFIX_VEX_0F3A68,
1158   PREFIX_VEX_0F3A69,
1159   PREFIX_VEX_0F3A6A,
1160   PREFIX_VEX_0F3A6B,
1161   PREFIX_VEX_0F3A6C,
1162   PREFIX_VEX_0F3A6D,
1163   PREFIX_VEX_0F3A6E,
1164   PREFIX_VEX_0F3A6F,
1165   PREFIX_VEX_0F3A78,
1166   PREFIX_VEX_0F3A79,
1167   PREFIX_VEX_0F3A7A,
1168   PREFIX_VEX_0F3A7B,
1169   PREFIX_VEX_0F3A7C,
1170   PREFIX_VEX_0F3A7D,
1171   PREFIX_VEX_0F3A7E,
1172   PREFIX_VEX_0F3A7F,
1173   PREFIX_VEX_0F3ADF,
1174   PREFIX_VEX_0F3AF0
1175 };
1176
1177 enum
1178 {
1179   X86_64_06 = 0,
1180   X86_64_07,
1181   X86_64_0D,
1182   X86_64_16,
1183   X86_64_17,
1184   X86_64_1E,
1185   X86_64_1F,
1186   X86_64_27,
1187   X86_64_2F,
1188   X86_64_37,
1189   X86_64_3F,
1190   X86_64_60,
1191   X86_64_61,
1192   X86_64_62,
1193   X86_64_63,
1194   X86_64_6D,
1195   X86_64_6F,
1196   X86_64_9A,
1197   X86_64_C4,
1198   X86_64_C5,
1199   X86_64_CE,
1200   X86_64_D4,
1201   X86_64_D5,
1202   X86_64_EA,
1203   X86_64_0F01_REG_0,
1204   X86_64_0F01_REG_1,
1205   X86_64_0F01_REG_2,
1206   X86_64_0F01_REG_3
1207 };
1208
1209 enum
1210 {
1211   THREE_BYTE_0F38 = 0,
1212   THREE_BYTE_0F3A,
1213   THREE_BYTE_0F7A
1214 };
1215
1216 enum
1217 {
1218   XOP_08 = 0,
1219   XOP_09,
1220   XOP_0A
1221 };
1222
1223 enum
1224 {
1225   VEX_0F = 0,
1226   VEX_0F38,
1227   VEX_0F3A
1228 };
1229
1230 enum
1231 {
1232   VEX_LEN_0F10_P_1 = 0,
1233   VEX_LEN_0F10_P_3,
1234   VEX_LEN_0F11_P_1,
1235   VEX_LEN_0F11_P_3,
1236   VEX_LEN_0F12_P_0_M_0,
1237   VEX_LEN_0F12_P_0_M_1,
1238   VEX_LEN_0F12_P_2,
1239   VEX_LEN_0F13_M_0,
1240   VEX_LEN_0F16_P_0_M_0,
1241   VEX_LEN_0F16_P_0_M_1,
1242   VEX_LEN_0F16_P_2,
1243   VEX_LEN_0F17_M_0,
1244   VEX_LEN_0F2A_P_1,
1245   VEX_LEN_0F2A_P_3,
1246   VEX_LEN_0F2C_P_1,
1247   VEX_LEN_0F2C_P_3,
1248   VEX_LEN_0F2D_P_1,
1249   VEX_LEN_0F2D_P_3,
1250   VEX_LEN_0F2E_P_0,
1251   VEX_LEN_0F2E_P_2,
1252   VEX_LEN_0F2F_P_0,
1253   VEX_LEN_0F2F_P_2,
1254   VEX_LEN_0F51_P_1,
1255   VEX_LEN_0F51_P_3,
1256   VEX_LEN_0F52_P_1,
1257   VEX_LEN_0F53_P_1,
1258   VEX_LEN_0F58_P_1,
1259   VEX_LEN_0F58_P_3,
1260   VEX_LEN_0F59_P_1,
1261   VEX_LEN_0F59_P_3,
1262   VEX_LEN_0F5A_P_1,
1263   VEX_LEN_0F5A_P_3,
1264   VEX_LEN_0F5C_P_1,
1265   VEX_LEN_0F5C_P_3,
1266   VEX_LEN_0F5D_P_1,
1267   VEX_LEN_0F5D_P_3,
1268   VEX_LEN_0F5E_P_1,
1269   VEX_LEN_0F5E_P_3,
1270   VEX_LEN_0F5F_P_1,
1271   VEX_LEN_0F5F_P_3,
1272   VEX_LEN_0F6E_P_2,
1273   VEX_LEN_0F7E_P_1,
1274   VEX_LEN_0F7E_P_2,
1275   VEX_LEN_0FAE_R_2_M_0,
1276   VEX_LEN_0FAE_R_3_M_0,
1277   VEX_LEN_0FC2_P_1,
1278   VEX_LEN_0FC2_P_3,
1279   VEX_LEN_0FC4_P_2,
1280   VEX_LEN_0FC5_P_2,
1281   VEX_LEN_0FD6_P_2,
1282   VEX_LEN_0FF7_P_2,
1283   VEX_LEN_0F3816_P_2,
1284   VEX_LEN_0F3819_P_2,
1285   VEX_LEN_0F381A_P_2_M_0,
1286   VEX_LEN_0F3836_P_2,
1287   VEX_LEN_0F3841_P_2,
1288   VEX_LEN_0F385A_P_2_M_0,
1289   VEX_LEN_0F38DB_P_2,
1290   VEX_LEN_0F38DC_P_2,
1291   VEX_LEN_0F38DD_P_2,
1292   VEX_LEN_0F38DE_P_2,
1293   VEX_LEN_0F38DF_P_2,
1294   VEX_LEN_0F38F2_P_0,
1295   VEX_LEN_0F38F3_R_1_P_0,
1296   VEX_LEN_0F38F3_R_2_P_0,
1297   VEX_LEN_0F38F3_R_3_P_0,
1298   VEX_LEN_0F38F5_P_0,
1299   VEX_LEN_0F38F5_P_1,
1300   VEX_LEN_0F38F5_P_3,
1301   VEX_LEN_0F38F6_P_3,
1302   VEX_LEN_0F38F7_P_0,
1303   VEX_LEN_0F38F7_P_1,
1304   VEX_LEN_0F38F7_P_2,
1305   VEX_LEN_0F38F7_P_3,
1306   VEX_LEN_0F3A00_P_2,
1307   VEX_LEN_0F3A01_P_2,
1308   VEX_LEN_0F3A06_P_2,
1309   VEX_LEN_0F3A0A_P_2,
1310   VEX_LEN_0F3A0B_P_2,
1311   VEX_LEN_0F3A14_P_2,
1312   VEX_LEN_0F3A15_P_2,
1313   VEX_LEN_0F3A16_P_2,
1314   VEX_LEN_0F3A17_P_2,
1315   VEX_LEN_0F3A18_P_2,
1316   VEX_LEN_0F3A19_P_2,
1317   VEX_LEN_0F3A20_P_2,
1318   VEX_LEN_0F3A21_P_2,
1319   VEX_LEN_0F3A22_P_2,
1320   VEX_LEN_0F3A38_P_2,
1321   VEX_LEN_0F3A39_P_2,
1322   VEX_LEN_0F3A41_P_2,
1323   VEX_LEN_0F3A44_P_2,
1324   VEX_LEN_0F3A46_P_2,
1325   VEX_LEN_0F3A60_P_2,
1326   VEX_LEN_0F3A61_P_2,
1327   VEX_LEN_0F3A62_P_2,
1328   VEX_LEN_0F3A63_P_2,
1329   VEX_LEN_0F3A6A_P_2,
1330   VEX_LEN_0F3A6B_P_2,
1331   VEX_LEN_0F3A6E_P_2,
1332   VEX_LEN_0F3A6F_P_2,
1333   VEX_LEN_0F3A7A_P_2,
1334   VEX_LEN_0F3A7B_P_2,
1335   VEX_LEN_0F3A7E_P_2,
1336   VEX_LEN_0F3A7F_P_2,
1337   VEX_LEN_0F3ADF_P_2,
1338   VEX_LEN_0F3AF0_P_3,
1339   VEX_LEN_0FXOP_08_CC,
1340   VEX_LEN_0FXOP_08_CD,
1341   VEX_LEN_0FXOP_08_CE,
1342   VEX_LEN_0FXOP_08_CF,
1343   VEX_LEN_0FXOP_08_EC,
1344   VEX_LEN_0FXOP_08_ED,
1345   VEX_LEN_0FXOP_08_EE,
1346   VEX_LEN_0FXOP_08_EF,
1347   VEX_LEN_0FXOP_09_80,
1348   VEX_LEN_0FXOP_09_81
1349 };
1350
1351 enum
1352 {
1353   VEX_W_0F10_P_0 = 0,
1354   VEX_W_0F10_P_1,
1355   VEX_W_0F10_P_2,
1356   VEX_W_0F10_P_3,
1357   VEX_W_0F11_P_0,
1358   VEX_W_0F11_P_1,
1359   VEX_W_0F11_P_2,
1360   VEX_W_0F11_P_3,
1361   VEX_W_0F12_P_0_M_0,
1362   VEX_W_0F12_P_0_M_1,
1363   VEX_W_0F12_P_1,
1364   VEX_W_0F12_P_2,
1365   VEX_W_0F12_P_3,
1366   VEX_W_0F13_M_0,
1367   VEX_W_0F14,
1368   VEX_W_0F15,
1369   VEX_W_0F16_P_0_M_0,
1370   VEX_W_0F16_P_0_M_1,
1371   VEX_W_0F16_P_1,
1372   VEX_W_0F16_P_2,
1373   VEX_W_0F17_M_0,
1374   VEX_W_0F28,
1375   VEX_W_0F29,
1376   VEX_W_0F2B_M_0,
1377   VEX_W_0F2E_P_0,
1378   VEX_W_0F2E_P_2,
1379   VEX_W_0F2F_P_0,
1380   VEX_W_0F2F_P_2,
1381   VEX_W_0F50_M_0,
1382   VEX_W_0F51_P_0,
1383   VEX_W_0F51_P_1,
1384   VEX_W_0F51_P_2,
1385   VEX_W_0F51_P_3,
1386   VEX_W_0F52_P_0,
1387   VEX_W_0F52_P_1,
1388   VEX_W_0F53_P_0,
1389   VEX_W_0F53_P_1,
1390   VEX_W_0F58_P_0,
1391   VEX_W_0F58_P_1,
1392   VEX_W_0F58_P_2,
1393   VEX_W_0F58_P_3,
1394   VEX_W_0F59_P_0,
1395   VEX_W_0F59_P_1,
1396   VEX_W_0F59_P_2,
1397   VEX_W_0F59_P_3,
1398   VEX_W_0F5A_P_0,
1399   VEX_W_0F5A_P_1,
1400   VEX_W_0F5A_P_3,
1401   VEX_W_0F5B_P_0,
1402   VEX_W_0F5B_P_1,
1403   VEX_W_0F5B_P_2,
1404   VEX_W_0F5C_P_0,
1405   VEX_W_0F5C_P_1,
1406   VEX_W_0F5C_P_2,
1407   VEX_W_0F5C_P_3,
1408   VEX_W_0F5D_P_0,
1409   VEX_W_0F5D_P_1,
1410   VEX_W_0F5D_P_2,
1411   VEX_W_0F5D_P_3,
1412   VEX_W_0F5E_P_0,
1413   VEX_W_0F5E_P_1,
1414   VEX_W_0F5E_P_2,
1415   VEX_W_0F5E_P_3,
1416   VEX_W_0F5F_P_0,
1417   VEX_W_0F5F_P_1,
1418   VEX_W_0F5F_P_2,
1419   VEX_W_0F5F_P_3,
1420   VEX_W_0F60_P_2,
1421   VEX_W_0F61_P_2,
1422   VEX_W_0F62_P_2,
1423   VEX_W_0F63_P_2,
1424   VEX_W_0F64_P_2,
1425   VEX_W_0F65_P_2,
1426   VEX_W_0F66_P_2,
1427   VEX_W_0F67_P_2,
1428   VEX_W_0F68_P_2,
1429   VEX_W_0F69_P_2,
1430   VEX_W_0F6A_P_2,
1431   VEX_W_0F6B_P_2,
1432   VEX_W_0F6C_P_2,
1433   VEX_W_0F6D_P_2,
1434   VEX_W_0F6F_P_1,
1435   VEX_W_0F6F_P_2,
1436   VEX_W_0F70_P_1,
1437   VEX_W_0F70_P_2,
1438   VEX_W_0F70_P_3,
1439   VEX_W_0F71_R_2_P_2,
1440   VEX_W_0F71_R_4_P_2,
1441   VEX_W_0F71_R_6_P_2,
1442   VEX_W_0F72_R_2_P_2,
1443   VEX_W_0F72_R_4_P_2,
1444   VEX_W_0F72_R_6_P_2,
1445   VEX_W_0F73_R_2_P_2,
1446   VEX_W_0F73_R_3_P_2,
1447   VEX_W_0F73_R_6_P_2,
1448   VEX_W_0F73_R_7_P_2,
1449   VEX_W_0F74_P_2,
1450   VEX_W_0F75_P_2,
1451   VEX_W_0F76_P_2,
1452   VEX_W_0F77_P_0,
1453   VEX_W_0F7C_P_2,
1454   VEX_W_0F7C_P_3,
1455   VEX_W_0F7D_P_2,
1456   VEX_W_0F7D_P_3,
1457   VEX_W_0F7E_P_1,
1458   VEX_W_0F7F_P_1,
1459   VEX_W_0F7F_P_2,
1460   VEX_W_0FAE_R_2_M_0,
1461   VEX_W_0FAE_R_3_M_0,
1462   VEX_W_0FC2_P_0,
1463   VEX_W_0FC2_P_1,
1464   VEX_W_0FC2_P_2,
1465   VEX_W_0FC2_P_3,
1466   VEX_W_0FC4_P_2,
1467   VEX_W_0FC5_P_2,
1468   VEX_W_0FD0_P_2,
1469   VEX_W_0FD0_P_3,
1470   VEX_W_0FD1_P_2,
1471   VEX_W_0FD2_P_2,
1472   VEX_W_0FD3_P_2,
1473   VEX_W_0FD4_P_2,
1474   VEX_W_0FD5_P_2,
1475   VEX_W_0FD6_P_2,
1476   VEX_W_0FD7_P_2_M_1,
1477   VEX_W_0FD8_P_2,
1478   VEX_W_0FD9_P_2,
1479   VEX_W_0FDA_P_2,
1480   VEX_W_0FDB_P_2,
1481   VEX_W_0FDC_P_2,
1482   VEX_W_0FDD_P_2,
1483   VEX_W_0FDE_P_2,
1484   VEX_W_0FDF_P_2,
1485   VEX_W_0FE0_P_2,
1486   VEX_W_0FE1_P_2,
1487   VEX_W_0FE2_P_2,
1488   VEX_W_0FE3_P_2,
1489   VEX_W_0FE4_P_2,
1490   VEX_W_0FE5_P_2,
1491   VEX_W_0FE6_P_1,
1492   VEX_W_0FE6_P_2,
1493   VEX_W_0FE6_P_3,
1494   VEX_W_0FE7_P_2_M_0,
1495   VEX_W_0FE8_P_2,
1496   VEX_W_0FE9_P_2,
1497   VEX_W_0FEA_P_2,
1498   VEX_W_0FEB_P_2,
1499   VEX_W_0FEC_P_2,
1500   VEX_W_0FED_P_2,
1501   VEX_W_0FEE_P_2,
1502   VEX_W_0FEF_P_2,
1503   VEX_W_0FF0_P_3_M_0,
1504   VEX_W_0FF1_P_2,
1505   VEX_W_0FF2_P_2,
1506   VEX_W_0FF3_P_2,
1507   VEX_W_0FF4_P_2,
1508   VEX_W_0FF5_P_2,
1509   VEX_W_0FF6_P_2,
1510   VEX_W_0FF7_P_2,
1511   VEX_W_0FF8_P_2,
1512   VEX_W_0FF9_P_2,
1513   VEX_W_0FFA_P_2,
1514   VEX_W_0FFB_P_2,
1515   VEX_W_0FFC_P_2,
1516   VEX_W_0FFD_P_2,
1517   VEX_W_0FFE_P_2,
1518   VEX_W_0F3800_P_2,
1519   VEX_W_0F3801_P_2,
1520   VEX_W_0F3802_P_2,
1521   VEX_W_0F3803_P_2,
1522   VEX_W_0F3804_P_2,
1523   VEX_W_0F3805_P_2,
1524   VEX_W_0F3806_P_2,
1525   VEX_W_0F3807_P_2,
1526   VEX_W_0F3808_P_2,
1527   VEX_W_0F3809_P_2,
1528   VEX_W_0F380A_P_2,
1529   VEX_W_0F380B_P_2,
1530   VEX_W_0F380C_P_2,
1531   VEX_W_0F380D_P_2,
1532   VEX_W_0F380E_P_2,
1533   VEX_W_0F380F_P_2,
1534   VEX_W_0F3816_P_2,
1535   VEX_W_0F3817_P_2,
1536   VEX_W_0F3818_P_2,
1537   VEX_W_0F3819_P_2,
1538   VEX_W_0F381A_P_2_M_0,
1539   VEX_W_0F381C_P_2,
1540   VEX_W_0F381D_P_2,
1541   VEX_W_0F381E_P_2,
1542   VEX_W_0F3820_P_2,
1543   VEX_W_0F3821_P_2,
1544   VEX_W_0F3822_P_2,
1545   VEX_W_0F3823_P_2,
1546   VEX_W_0F3824_P_2,
1547   VEX_W_0F3825_P_2,
1548   VEX_W_0F3828_P_2,
1549   VEX_W_0F3829_P_2,
1550   VEX_W_0F382A_P_2_M_0,
1551   VEX_W_0F382B_P_2,
1552   VEX_W_0F382C_P_2_M_0,
1553   VEX_W_0F382D_P_2_M_0,
1554   VEX_W_0F382E_P_2_M_0,
1555   VEX_W_0F382F_P_2_M_0,
1556   VEX_W_0F3830_P_2,
1557   VEX_W_0F3831_P_2,
1558   VEX_W_0F3832_P_2,
1559   VEX_W_0F3833_P_2,
1560   VEX_W_0F3834_P_2,
1561   VEX_W_0F3835_P_2,
1562   VEX_W_0F3836_P_2,
1563   VEX_W_0F3837_P_2,
1564   VEX_W_0F3838_P_2,
1565   VEX_W_0F3839_P_2,
1566   VEX_W_0F383A_P_2,
1567   VEX_W_0F383B_P_2,
1568   VEX_W_0F383C_P_2,
1569   VEX_W_0F383D_P_2,
1570   VEX_W_0F383E_P_2,
1571   VEX_W_0F383F_P_2,
1572   VEX_W_0F3840_P_2,
1573   VEX_W_0F3841_P_2,
1574   VEX_W_0F3846_P_2,
1575   VEX_W_0F3858_P_2,
1576   VEX_W_0F3859_P_2,
1577   VEX_W_0F385A_P_2_M_0,
1578   VEX_W_0F3878_P_2,
1579   VEX_W_0F3879_P_2,
1580   VEX_W_0F38DB_P_2,
1581   VEX_W_0F38DC_P_2,
1582   VEX_W_0F38DD_P_2,
1583   VEX_W_0F38DE_P_2,
1584   VEX_W_0F38DF_P_2,
1585   VEX_W_0F3A00_P_2,
1586   VEX_W_0F3A01_P_2,
1587   VEX_W_0F3A02_P_2,
1588   VEX_W_0F3A04_P_2,
1589   VEX_W_0F3A05_P_2,
1590   VEX_W_0F3A06_P_2,
1591   VEX_W_0F3A08_P_2,
1592   VEX_W_0F3A09_P_2,
1593   VEX_W_0F3A0A_P_2,
1594   VEX_W_0F3A0B_P_2,
1595   VEX_W_0F3A0C_P_2,
1596   VEX_W_0F3A0D_P_2,
1597   VEX_W_0F3A0E_P_2,
1598   VEX_W_0F3A0F_P_2,
1599   VEX_W_0F3A14_P_2,
1600   VEX_W_0F3A15_P_2,
1601   VEX_W_0F3A18_P_2,
1602   VEX_W_0F3A19_P_2,
1603   VEX_W_0F3A20_P_2,
1604   VEX_W_0F3A21_P_2,
1605   VEX_W_0F3A38_P_2,
1606   VEX_W_0F3A39_P_2,
1607   VEX_W_0F3A40_P_2,
1608   VEX_W_0F3A41_P_2,
1609   VEX_W_0F3A42_P_2,
1610   VEX_W_0F3A44_P_2,
1611   VEX_W_0F3A46_P_2,
1612   VEX_W_0F3A48_P_2,
1613   VEX_W_0F3A49_P_2,
1614   VEX_W_0F3A4A_P_2,
1615   VEX_W_0F3A4B_P_2,
1616   VEX_W_0F3A4C_P_2,
1617   VEX_W_0F3A60_P_2,
1618   VEX_W_0F3A61_P_2,
1619   VEX_W_0F3A62_P_2,
1620   VEX_W_0F3A63_P_2,
1621   VEX_W_0F3ADF_P_2
1622 };
1623
1624 typedef void (*op_rtn) (int bytemode, int sizeflag);
1625
1626 struct dis386 {
1627   const char *name;
1628   struct
1629     {
1630       op_rtn rtn;
1631       int bytemode;
1632     } op[MAX_OPERANDS];
1633 };
1634
1635 /* Upper case letters in the instruction names here are macros.
1636    'A' => print 'b' if no register operands or suffix_always is true
1637    'B' => print 'b' if suffix_always is true
1638    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1639           size prefix
1640    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1641           suffix_always is true
1642    'E' => print 'e' if 32-bit form of jcxz
1643    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1644    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1645    'H' => print ",pt" or ",pn" branch hint
1646    'I' => honor following macro letter even in Intel mode (implemented only
1647           for some of the macro letters)
1648    'J' => print 'l'
1649    'K' => print 'd' or 'q' if rex prefix is present.
1650    'L' => print 'l' if suffix_always is true
1651    'M' => print 'r' if intel_mnemonic is false.
1652    'N' => print 'n' if instruction has no wait "prefix"
1653    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1654    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1655           or suffix_always is true.  print 'q' if rex prefix is present.
1656    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1657           is true
1658    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1659    'S' => print 'w', 'l' or 'q' if suffix_always is true
1660    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1661    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1662    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1663    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1664    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1665    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1666           suffix_always is true.
1667    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1668    '!' => change condition from true to false or from false to true.
1669    '%' => add 1 upper case letter to the macro.
1670
1671    2 upper case letter macros:
1672    "XY" => print 'x' or 'y' if no register operands or suffix_always
1673            is true.
1674    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1675    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1676            or suffix_always is true
1677    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1678    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1679    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1680    "LW" => print 'd', 'q' depending on the VEX.W bit
1681
1682    Many of the above letters print nothing in Intel mode.  See "putop"
1683    for the details.
1684
1685    Braces '{' and '}', and vertical bars '|', indicate alternative
1686    mnemonic strings for AT&T and Intel.  */
1687
1688 static const struct dis386 dis386[] = {
1689   /* 00 */
1690   { "addB",             { Ebh1, Gb } },
1691   { "addS",             { Evh1, Gv } },
1692   { "addB",             { Gb, EbS } },
1693   { "addS",             { Gv, EvS } },
1694   { "addB",             { AL, Ib } },
1695   { "addS",             { eAX, Iv } },
1696   { X86_64_TABLE (X86_64_06) },
1697   { X86_64_TABLE (X86_64_07) },
1698   /* 08 */
1699   { "orB",              { Ebh1, Gb } },
1700   { "orS",              { Evh1, Gv } },
1701   { "orB",              { Gb, EbS } },
1702   { "orS",              { Gv, EvS } },
1703   { "orB",              { AL, Ib } },
1704   { "orS",              { eAX, Iv } },
1705   { X86_64_TABLE (X86_64_0D) },
1706   { Bad_Opcode },       /* 0x0f extended opcode escape */
1707   /* 10 */
1708   { "adcB",             { Ebh1, Gb } },
1709   { "adcS",             { Evh1, Gv } },
1710   { "adcB",             { Gb, EbS } },
1711   { "adcS",             { Gv, EvS } },
1712   { "adcB",             { AL, Ib } },
1713   { "adcS",             { eAX, Iv } },
1714   { X86_64_TABLE (X86_64_16) },
1715   { X86_64_TABLE (X86_64_17) },
1716   /* 18 */
1717   { "sbbB",             { Ebh1, Gb } },
1718   { "sbbS",             { Evh1, Gv } },
1719   { "sbbB",             { Gb, EbS } },
1720   { "sbbS",             { Gv, EvS } },
1721   { "sbbB",             { AL, Ib } },
1722   { "sbbS",             { eAX, Iv } },
1723   { X86_64_TABLE (X86_64_1E) },
1724   { X86_64_TABLE (X86_64_1F) },
1725   /* 20 */
1726   { "andB",             { Ebh1, Gb } },
1727   { "andS",             { Evh1, Gv } },
1728   { "andB",             { Gb, EbS } },
1729   { "andS",             { Gv, EvS } },
1730   { "andB",             { AL, Ib } },
1731   { "andS",             { eAX, Iv } },
1732   { Bad_Opcode },       /* SEG ES prefix */
1733   { X86_64_TABLE (X86_64_27) },
1734   /* 28 */
1735   { "subB",             { Ebh1, Gb } },
1736   { "subS",             { Evh1, Gv } },
1737   { "subB",             { Gb, EbS } },
1738   { "subS",             { Gv, EvS } },
1739   { "subB",             { AL, Ib } },
1740   { "subS",             { eAX, Iv } },
1741   { Bad_Opcode },       /* SEG CS prefix */
1742   { X86_64_TABLE (X86_64_2F) },
1743   /* 30 */
1744   { "xorB",             { Ebh1, Gb } },
1745   { "xorS",             { Evh1, Gv } },
1746   { "xorB",             { Gb, EbS } },
1747   { "xorS",             { Gv, EvS } },
1748   { "xorB",             { AL, Ib } },
1749   { "xorS",             { eAX, Iv } },
1750   { Bad_Opcode },       /* SEG SS prefix */
1751   { X86_64_TABLE (X86_64_37) },
1752   /* 38 */
1753   { "cmpB",             { Eb, Gb } },
1754   { "cmpS",             { Ev, Gv } },
1755   { "cmpB",             { Gb, EbS } },
1756   { "cmpS",             { Gv, EvS } },
1757   { "cmpB",             { AL, Ib } },
1758   { "cmpS",             { eAX, Iv } },
1759   { Bad_Opcode },       /* SEG DS prefix */
1760   { X86_64_TABLE (X86_64_3F) },
1761   /* 40 */
1762   { "inc{S|}",          { RMeAX } },
1763   { "inc{S|}",          { RMeCX } },
1764   { "inc{S|}",          { RMeDX } },
1765   { "inc{S|}",          { RMeBX } },
1766   { "inc{S|}",          { RMeSP } },
1767   { "inc{S|}",          { RMeBP } },
1768   { "inc{S|}",          { RMeSI } },
1769   { "inc{S|}",          { RMeDI } },
1770   /* 48 */
1771   { "dec{S|}",          { RMeAX } },
1772   { "dec{S|}",          { RMeCX } },
1773   { "dec{S|}",          { RMeDX } },
1774   { "dec{S|}",          { RMeBX } },
1775   { "dec{S|}",          { RMeSP } },
1776   { "dec{S|}",          { RMeBP } },
1777   { "dec{S|}",          { RMeSI } },
1778   { "dec{S|}",          { RMeDI } },
1779   /* 50 */
1780   { "pushV",            { RMrAX } },
1781   { "pushV",            { RMrCX } },
1782   { "pushV",            { RMrDX } },
1783   { "pushV",            { RMrBX } },
1784   { "pushV",            { RMrSP } },
1785   { "pushV",            { RMrBP } },
1786   { "pushV",            { RMrSI } },
1787   { "pushV",            { RMrDI } },
1788   /* 58 */
1789   { "popV",             { RMrAX } },
1790   { "popV",             { RMrCX } },
1791   { "popV",             { RMrDX } },
1792   { "popV",             { RMrBX } },
1793   { "popV",             { RMrSP } },
1794   { "popV",             { RMrBP } },
1795   { "popV",             { RMrSI } },
1796   { "popV",             { RMrDI } },
1797   /* 60 */
1798   { X86_64_TABLE (X86_64_60) },
1799   { X86_64_TABLE (X86_64_61) },
1800   { X86_64_TABLE (X86_64_62) },
1801   { X86_64_TABLE (X86_64_63) },
1802   { Bad_Opcode },       /* seg fs */
1803   { Bad_Opcode },       /* seg gs */
1804   { Bad_Opcode },       /* op size prefix */
1805   { Bad_Opcode },       /* adr size prefix */
1806   /* 68 */
1807   { "pushT",            { sIv } },
1808   { "imulS",            { Gv, Ev, Iv } },
1809   { "pushT",            { sIbT } },
1810   { "imulS",            { Gv, Ev, sIb } },
1811   { "ins{b|}",          { Ybr, indirDX } },
1812   { X86_64_TABLE (X86_64_6D) },
1813   { "outs{b|}",         { indirDXr, Xb } },
1814   { X86_64_TABLE (X86_64_6F) },
1815   /* 70 */
1816   { "joH",              { Jb, BND, cond_jump_flag } },
1817   { "jnoH",             { Jb, BND, cond_jump_flag } },
1818   { "jbH",              { Jb, BND, cond_jump_flag } },
1819   { "jaeH",             { Jb, BND, cond_jump_flag } },
1820   { "jeH",              { Jb, BND, cond_jump_flag } },
1821   { "jneH",             { Jb, BND, cond_jump_flag } },
1822   { "jbeH",             { Jb, BND, cond_jump_flag } },
1823   { "jaH",              { Jb, BND, cond_jump_flag } },
1824   /* 78 */
1825   { "jsH",              { Jb, BND, cond_jump_flag } },
1826   { "jnsH",             { Jb, BND, cond_jump_flag } },
1827   { "jpH",              { Jb, BND, cond_jump_flag } },
1828   { "jnpH",             { Jb, BND, cond_jump_flag } },
1829   { "jlH",              { Jb, BND, cond_jump_flag } },
1830   { "jgeH",             { Jb, BND, cond_jump_flag } },
1831   { "jleH",             { Jb, BND, cond_jump_flag } },
1832   { "jgH",              { Jb, BND, cond_jump_flag } },
1833   /* 80 */
1834   { REG_TABLE (REG_80) },
1835   { REG_TABLE (REG_81) },
1836   { Bad_Opcode },
1837   { REG_TABLE (REG_82) },
1838   { "testB",            { Eb, Gb } },
1839   { "testS",            { Ev, Gv } },
1840   { "xchgB",            { Ebh2, Gb } },
1841   { "xchgS",            { Evh2, Gv } },
1842   /* 88 */
1843   { "movB",             { Ebh3, Gb } },
1844   { "movS",             { Evh3, Gv } },
1845   { "movB",             { Gb, EbS } },
1846   { "movS",             { Gv, EvS } },
1847   { "movD",             { Sv, Sw } },
1848   { MOD_TABLE (MOD_8D) },
1849   { "movD",             { Sw, Sv } },
1850   { REG_TABLE (REG_8F) },
1851   /* 90 */
1852   { PREFIX_TABLE (PREFIX_90) },
1853   { "xchgS",            { RMeCX, eAX } },
1854   { "xchgS",            { RMeDX, eAX } },
1855   { "xchgS",            { RMeBX, eAX } },
1856   { "xchgS",            { RMeSP, eAX } },
1857   { "xchgS",            { RMeBP, eAX } },
1858   { "xchgS",            { RMeSI, eAX } },
1859   { "xchgS",            { RMeDI, eAX } },
1860   /* 98 */
1861   { "cW{t|}R",          { XX } },
1862   { "cR{t|}O",          { XX } },
1863   { X86_64_TABLE (X86_64_9A) },
1864   { Bad_Opcode },       /* fwait */
1865   { "pushfT",           { XX } },
1866   { "popfT",            { XX } },
1867   { "sahf",             { XX } },
1868   { "lahf",             { XX } },
1869   /* a0 */
1870   { "mov%LB",           { AL, Ob } },
1871   { "mov%LS",           { eAX, Ov } },
1872   { "mov%LB",           { Ob, AL } },
1873   { "mov%LS",           { Ov, eAX } },
1874   { "movs{b|}",         { Ybr, Xb } },
1875   { "movs{R|}",         { Yvr, Xv } },
1876   { "cmps{b|}",         { Xb, Yb } },
1877   { "cmps{R|}",         { Xv, Yv } },
1878   /* a8 */
1879   { "testB",            { AL, Ib } },
1880   { "testS",            { eAX, Iv } },
1881   { "stosB",            { Ybr, AL } },
1882   { "stosS",            { Yvr, eAX } },
1883   { "lodsB",            { ALr, Xb } },
1884   { "lodsS",            { eAXr, Xv } },
1885   { "scasB",            { AL, Yb } },
1886   { "scasS",            { eAX, Yv } },
1887   /* b0 */
1888   { "movB",             { RMAL, Ib } },
1889   { "movB",             { RMCL, Ib } },
1890   { "movB",             { RMDL, Ib } },
1891   { "movB",             { RMBL, Ib } },
1892   { "movB",             { RMAH, Ib } },
1893   { "movB",             { RMCH, Ib } },
1894   { "movB",             { RMDH, Ib } },
1895   { "movB",             { RMBH, Ib } },
1896   /* b8 */
1897   { "mov%LV",           { RMeAX, Iv64 } },
1898   { "mov%LV",           { RMeCX, Iv64 } },
1899   { "mov%LV",           { RMeDX, Iv64 } },
1900   { "mov%LV",           { RMeBX, Iv64 } },
1901   { "mov%LV",           { RMeSP, Iv64 } },
1902   { "mov%LV",           { RMeBP, Iv64 } },
1903   { "mov%LV",           { RMeSI, Iv64 } },
1904   { "mov%LV",           { RMeDI, Iv64 } },
1905   /* c0 */
1906   { REG_TABLE (REG_C0) },
1907   { REG_TABLE (REG_C1) },
1908   { "retT",             { Iw, BND } },
1909   { "retT",             { BND } },
1910   { X86_64_TABLE (X86_64_C4) },
1911   { X86_64_TABLE (X86_64_C5) },
1912   { REG_TABLE (REG_C6) },
1913   { REG_TABLE (REG_C7) },
1914   /* c8 */
1915   { "enterT",           { Iw, Ib } },
1916   { "leaveT",           { XX } },
1917   { "Jret{|f}P",        { Iw } },
1918   { "Jret{|f}P",        { XX } },
1919   { "int3",             { XX } },
1920   { "int",              { Ib } },
1921   { X86_64_TABLE (X86_64_CE) },
1922   { "iretP",            { XX } },
1923   /* d0 */
1924   { REG_TABLE (REG_D0) },
1925   { REG_TABLE (REG_D1) },
1926   { REG_TABLE (REG_D2) },
1927   { REG_TABLE (REG_D3) },
1928   { X86_64_TABLE (X86_64_D4) },
1929   { X86_64_TABLE (X86_64_D5) },
1930   { Bad_Opcode },
1931   { "xlat",             { DSBX } },
1932   /* d8 */
1933   { FLOAT },
1934   { FLOAT },
1935   { FLOAT },
1936   { FLOAT },
1937   { FLOAT },
1938   { FLOAT },
1939   { FLOAT },
1940   { FLOAT },
1941   /* e0 */
1942   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1943   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1944   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1945   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1946   { "inB",              { AL, Ib } },
1947   { "inG",              { zAX, Ib } },
1948   { "outB",             { Ib, AL } },
1949   { "outG",             { Ib, zAX } },
1950   /* e8 */
1951   { "callT",            { Jv, BND } },
1952   { "jmpT",             { Jv, BND } },
1953   { X86_64_TABLE (X86_64_EA) },
1954   { "jmp",              { Jb, BND } },
1955   { "inB",              { AL, indirDX } },
1956   { "inG",              { zAX, indirDX } },
1957   { "outB",             { indirDX, AL } },
1958   { "outG",             { indirDX, zAX } },
1959   /* f0 */
1960   { Bad_Opcode },       /* lock prefix */
1961   { "icebp",            { XX } },
1962   { Bad_Opcode },       /* repne */
1963   { Bad_Opcode },       /* repz */
1964   { "hlt",              { XX } },
1965   { "cmc",              { XX } },
1966   { REG_TABLE (REG_F6) },
1967   { REG_TABLE (REG_F7) },
1968   /* f8 */
1969   { "clc",              { XX } },
1970   { "stc",              { XX } },
1971   { "cli",              { XX } },
1972   { "sti",              { XX } },
1973   { "cld",              { XX } },
1974   { "std",              { XX } },
1975   { REG_TABLE (REG_FE) },
1976   { REG_TABLE (REG_FF) },
1977 };
1978
1979 static const struct dis386 dis386_twobyte[] = {
1980   /* 00 */
1981   { REG_TABLE (REG_0F00 ) },
1982   { REG_TABLE (REG_0F01 ) },
1983   { "larS",             { Gv, Ew } },
1984   { "lslS",             { Gv, Ew } },
1985   { Bad_Opcode },
1986   { "syscall",          { XX } },
1987   { "clts",             { XX } },
1988   { "sysretP",          { XX } },
1989   /* 08 */
1990   { "invd",             { XX } },
1991   { "wbinvd",           { XX } },
1992   { Bad_Opcode },
1993   { "ud2",              { XX } },
1994   { Bad_Opcode },
1995   { REG_TABLE (REG_0F0D) },
1996   { "femms",            { XX } },
1997   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1998   /* 10 */
1999   { PREFIX_TABLE (PREFIX_0F10) },
2000   { PREFIX_TABLE (PREFIX_0F11) },
2001   { PREFIX_TABLE (PREFIX_0F12) },
2002   { MOD_TABLE (MOD_0F13) },
2003   { "unpcklpX",         { XM, EXx } },
2004   { "unpckhpX",         { XM, EXx } },
2005   { PREFIX_TABLE (PREFIX_0F16) },
2006   { MOD_TABLE (MOD_0F17) },
2007   /* 18 */
2008   { REG_TABLE (REG_0F18) },
2009   { "nopQ",             { Ev } },
2010   { PREFIX_TABLE (PREFIX_0F1A) },
2011   { PREFIX_TABLE (PREFIX_0F1B) },
2012   { "nopQ",             { Ev } },
2013   { "nopQ",             { Ev } },
2014   { "nopQ",             { Ev } },
2015   { "nopQ",             { Ev } },
2016   /* 20 */
2017   { MOD_TABLE (MOD_0F20) },
2018   { MOD_TABLE (MOD_0F21) },
2019   { MOD_TABLE (MOD_0F22) },
2020   { MOD_TABLE (MOD_0F23) },
2021   { MOD_TABLE (MOD_0F24) },
2022   { Bad_Opcode },
2023   { MOD_TABLE (MOD_0F26) },
2024   { Bad_Opcode },
2025   /* 28 */
2026   { "movapX",           { XM, EXx } },
2027   { "movapX",           { EXxS, XM } },
2028   { PREFIX_TABLE (PREFIX_0F2A) },
2029   { PREFIX_TABLE (PREFIX_0F2B) },
2030   { PREFIX_TABLE (PREFIX_0F2C) },
2031   { PREFIX_TABLE (PREFIX_0F2D) },
2032   { PREFIX_TABLE (PREFIX_0F2E) },
2033   { PREFIX_TABLE (PREFIX_0F2F) },
2034   /* 30 */
2035   { "wrmsr",            { XX } },
2036   { "rdtsc",            { XX } },
2037   { "rdmsr",            { XX } },
2038   { "rdpmc",            { XX } },
2039   { "sysenter",         { XX } },
2040   { "sysexit",          { XX } },
2041   { Bad_Opcode },
2042   { "getsec",           { XX } },
2043   /* 38 */
2044   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2045   { Bad_Opcode },
2046   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2047   { Bad_Opcode },
2048   { Bad_Opcode },
2049   { Bad_Opcode },
2050   { Bad_Opcode },
2051   { Bad_Opcode },
2052   /* 40 */
2053   { "cmovoS",           { Gv, Ev } },
2054   { "cmovnoS",          { Gv, Ev } },
2055   { "cmovbS",           { Gv, Ev } },
2056   { "cmovaeS",          { Gv, Ev } },
2057   { "cmoveS",           { Gv, Ev } },
2058   { "cmovneS",          { Gv, Ev } },
2059   { "cmovbeS",          { Gv, Ev } },
2060   { "cmovaS",           { Gv, Ev } },
2061   /* 48 */
2062   { "cmovsS",           { Gv, Ev } },
2063   { "cmovnsS",          { Gv, Ev } },
2064   { "cmovpS",           { Gv, Ev } },
2065   { "cmovnpS",          { Gv, Ev } },
2066   { "cmovlS",           { Gv, Ev } },
2067   { "cmovgeS",          { Gv, Ev } },
2068   { "cmovleS",          { Gv, Ev } },
2069   { "cmovgS",           { Gv, Ev } },
2070   /* 50 */
2071   { MOD_TABLE (MOD_0F51) },
2072   { PREFIX_TABLE (PREFIX_0F51) },
2073   { PREFIX_TABLE (PREFIX_0F52) },
2074   { PREFIX_TABLE (PREFIX_0F53) },
2075   { "andpX",            { XM, EXx } },
2076   { "andnpX",           { XM, EXx } },
2077   { "orpX",             { XM, EXx } },
2078   { "xorpX",            { XM, EXx } },
2079   /* 58 */
2080   { PREFIX_TABLE (PREFIX_0F58) },
2081   { PREFIX_TABLE (PREFIX_0F59) },
2082   { PREFIX_TABLE (PREFIX_0F5A) },
2083   { PREFIX_TABLE (PREFIX_0F5B) },
2084   { PREFIX_TABLE (PREFIX_0F5C) },
2085   { PREFIX_TABLE (PREFIX_0F5D) },
2086   { PREFIX_TABLE (PREFIX_0F5E) },
2087   { PREFIX_TABLE (PREFIX_0F5F) },
2088   /* 60 */
2089   { PREFIX_TABLE (PREFIX_0F60) },
2090   { PREFIX_TABLE (PREFIX_0F61) },
2091   { PREFIX_TABLE (PREFIX_0F62) },
2092   { "packsswb",         { MX, EM } },
2093   { "pcmpgtb",          { MX, EM } },
2094   { "pcmpgtw",          { MX, EM } },
2095   { "pcmpgtd",          { MX, EM } },
2096   { "packuswb",         { MX, EM } },
2097   /* 68 */
2098   { "punpckhbw",        { MX, EM } },
2099   { "punpckhwd",        { MX, EM } },
2100   { "punpckhdq",        { MX, EM } },
2101   { "packssdw",         { MX, EM } },
2102   { PREFIX_TABLE (PREFIX_0F6C) },
2103   { PREFIX_TABLE (PREFIX_0F6D) },
2104   { "movK",             { MX, Edq } },
2105   { PREFIX_TABLE (PREFIX_0F6F) },
2106   /* 70 */
2107   { PREFIX_TABLE (PREFIX_0F70) },
2108   { REG_TABLE (REG_0F71) },
2109   { REG_TABLE (REG_0F72) },
2110   { REG_TABLE (REG_0F73) },
2111   { "pcmpeqb",          { MX, EM } },
2112   { "pcmpeqw",          { MX, EM } },
2113   { "pcmpeqd",          { MX, EM } },
2114   { "emms",             { XX } },
2115   /* 78 */
2116   { PREFIX_TABLE (PREFIX_0F78) },
2117   { PREFIX_TABLE (PREFIX_0F79) },
2118   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2119   { Bad_Opcode },
2120   { PREFIX_TABLE (PREFIX_0F7C) },
2121   { PREFIX_TABLE (PREFIX_0F7D) },
2122   { PREFIX_TABLE (PREFIX_0F7E) },
2123   { PREFIX_TABLE (PREFIX_0F7F) },
2124   /* 80 */
2125   { "joH",              { Jv, BND, cond_jump_flag } },
2126   { "jnoH",             { Jv, BND, cond_jump_flag } },
2127   { "jbH",              { Jv, BND, cond_jump_flag } },
2128   { "jaeH",             { Jv, BND, cond_jump_flag } },
2129   { "jeH",              { Jv, BND, cond_jump_flag } },
2130   { "jneH",             { Jv, BND, cond_jump_flag } },
2131   { "jbeH",             { Jv, BND, cond_jump_flag } },
2132   { "jaH",              { Jv, BND, cond_jump_flag } },
2133   /* 88 */
2134   { "jsH",              { Jv, BND, cond_jump_flag } },
2135   { "jnsH",             { Jv, BND, cond_jump_flag } },
2136   { "jpH",              { Jv, BND, cond_jump_flag } },
2137   { "jnpH",             { Jv, BND, cond_jump_flag } },
2138   { "jlH",              { Jv, BND, cond_jump_flag } },
2139   { "jgeH",             { Jv, BND, cond_jump_flag } },
2140   { "jleH",             { Jv, BND, cond_jump_flag } },
2141   { "jgH",              { Jv, BND, cond_jump_flag } },
2142   /* 90 */
2143   { "seto",             { Eb } },
2144   { "setno",            { Eb } },
2145   { "setb",             { Eb } },
2146   { "setae",            { Eb } },
2147   { "sete",             { Eb } },
2148   { "setne",            { Eb } },
2149   { "setbe",            { Eb } },
2150   { "seta",             { Eb } },
2151   /* 98 */
2152   { "sets",             { Eb } },
2153   { "setns",            { Eb } },
2154   { "setp",             { Eb } },
2155   { "setnp",            { Eb } },
2156   { "setl",             { Eb } },
2157   { "setge",            { Eb } },
2158   { "setle",            { Eb } },
2159   { "setg",             { Eb } },
2160   /* a0 */
2161   { "pushT",            { fs } },
2162   { "popT",             { fs } },
2163   { "cpuid",            { XX } },
2164   { "btS",              { Ev, Gv } },
2165   { "shldS",            { Ev, Gv, Ib } },
2166   { "shldS",            { Ev, Gv, CL } },
2167   { REG_TABLE (REG_0FA6) },
2168   { REG_TABLE (REG_0FA7) },
2169   /* a8 */
2170   { "pushT",            { gs } },
2171   { "popT",             { gs } },
2172   { "rsm",              { XX } },
2173   { "btsS",             { Evh1, Gv } },
2174   { "shrdS",            { Ev, Gv, Ib } },
2175   { "shrdS",            { Ev, Gv, CL } },
2176   { REG_TABLE (REG_0FAE) },
2177   { "imulS",            { Gv, Ev } },
2178   /* b0 */
2179   { "cmpxchgB",         { Ebh1, Gb } },
2180   { "cmpxchgS",         { Evh1, Gv } },
2181   { MOD_TABLE (MOD_0FB2) },
2182   { "btrS",             { Evh1, Gv } },
2183   { MOD_TABLE (MOD_0FB4) },
2184   { MOD_TABLE (MOD_0FB5) },
2185   { "movz{bR|x}",       { Gv, Eb } },
2186   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2187   /* b8 */
2188   { PREFIX_TABLE (PREFIX_0FB8) },
2189   { "ud1",              { XX } },
2190   { REG_TABLE (REG_0FBA) },
2191   { "btcS",             { Evh1, Gv } },
2192   { PREFIX_TABLE (PREFIX_0FBC) },
2193   { PREFIX_TABLE (PREFIX_0FBD) },
2194   { "movs{bR|x}",       { Gv, Eb } },
2195   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2196   /* c0 */
2197   { "xaddB",            { Ebh1, Gb } },
2198   { "xaddS",            { Evh1, Gv } },
2199   { PREFIX_TABLE (PREFIX_0FC2) },
2200   { PREFIX_TABLE (PREFIX_0FC3) },
2201   { "pinsrw",           { MX, Edqw, Ib } },
2202   { "pextrw",           { Gdq, MS, Ib } },
2203   { "shufpX",           { XM, EXx, Ib } },
2204   { REG_TABLE (REG_0FC7) },
2205   /* c8 */
2206   { "bswap",            { RMeAX } },
2207   { "bswap",            { RMeCX } },
2208   { "bswap",            { RMeDX } },
2209   { "bswap",            { RMeBX } },
2210   { "bswap",            { RMeSP } },
2211   { "bswap",            { RMeBP } },
2212   { "bswap",            { RMeSI } },
2213   { "bswap",            { RMeDI } },
2214   /* d0 */
2215   { PREFIX_TABLE (PREFIX_0FD0) },
2216   { "psrlw",            { MX, EM } },
2217   { "psrld",            { MX, EM } },
2218   { "psrlq",            { MX, EM } },
2219   { "paddq",            { MX, EM } },
2220   { "pmullw",           { MX, EM } },
2221   { PREFIX_TABLE (PREFIX_0FD6) },
2222   { MOD_TABLE (MOD_0FD7) },
2223   /* d8 */
2224   { "psubusb",          { MX, EM } },
2225   { "psubusw",          { MX, EM } },
2226   { "pminub",           { MX, EM } },
2227   { "pand",             { MX, EM } },
2228   { "paddusb",          { MX, EM } },
2229   { "paddusw",          { MX, EM } },
2230   { "pmaxub",           { MX, EM } },
2231   { "pandn",            { MX, EM } },
2232   /* e0 */
2233   { "pavgb",            { MX, EM } },
2234   { "psraw",            { MX, EM } },
2235   { "psrad",            { MX, EM } },
2236   { "pavgw",            { MX, EM } },
2237   { "pmulhuw",          { MX, EM } },
2238   { "pmulhw",           { MX, EM } },
2239   { PREFIX_TABLE (PREFIX_0FE6) },
2240   { PREFIX_TABLE (PREFIX_0FE7) },
2241   /* e8 */
2242   { "psubsb",           { MX, EM } },
2243   { "psubsw",           { MX, EM } },
2244   { "pminsw",           { MX, EM } },
2245   { "por",              { MX, EM } },
2246   { "paddsb",           { MX, EM } },
2247   { "paddsw",           { MX, EM } },
2248   { "pmaxsw",           { MX, EM } },
2249   { "pxor",             { MX, EM } },
2250   /* f0 */
2251   { PREFIX_TABLE (PREFIX_0FF0) },
2252   { "psllw",            { MX, EM } },
2253   { "pslld",            { MX, EM } },
2254   { "psllq",            { MX, EM } },
2255   { "pmuludq",          { MX, EM } },
2256   { "pmaddwd",          { MX, EM } },
2257   { "psadbw",           { MX, EM } },
2258   { PREFIX_TABLE (PREFIX_0FF7) },
2259   /* f8 */
2260   { "psubb",            { MX, EM } },
2261   { "psubw",            { MX, EM } },
2262   { "psubd",            { MX, EM } },
2263   { "psubq",            { MX, EM } },
2264   { "paddb",            { MX, EM } },
2265   { "paddw",            { MX, EM } },
2266   { "paddd",            { MX, EM } },
2267   { Bad_Opcode },
2268 };
2269
2270 static const unsigned char onebyte_has_modrm[256] = {
2271   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2272   /*       -------------------------------        */
2273   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2274   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2275   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2276   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2277   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2278   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2279   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2280   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2281   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2282   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2283   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2284   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2285   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2286   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2287   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2288   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2289   /*       -------------------------------        */
2290   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2291 };
2292
2293 static const unsigned char twobyte_has_modrm[256] = {
2294   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2295   /*       -------------------------------        */
2296   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2297   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2298   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2299   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2300   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2301   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2302   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2303   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2304   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2305   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2306   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2307   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2308   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2309   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2310   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2311   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2312   /*       -------------------------------        */
2313   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2314 };
2315
2316 static char obuf[100];
2317 static char *obufp;
2318 static char *mnemonicendp;
2319 static char scratchbuf[100];
2320 static unsigned char *start_codep;
2321 static unsigned char *insn_codep;
2322 static unsigned char *codep;
2323 static int last_lock_prefix;
2324 static int last_repz_prefix;
2325 static int last_repnz_prefix;
2326 static int last_data_prefix;
2327 static int last_addr_prefix;
2328 static int last_rex_prefix;
2329 static int last_seg_prefix;
2330 #define MAX_CODE_LENGTH 15
2331 /* We can up to 14 prefixes since the maximum instruction length is
2332    15bytes.  */
2333 static int all_prefixes[MAX_CODE_LENGTH - 1];
2334 static disassemble_info *the_info;
2335 static struct
2336   {
2337     int mod;
2338     int reg;
2339     int rm;
2340   }
2341 modrm;
2342 static unsigned char need_modrm;
2343 static struct
2344   {
2345     int scale;
2346     int index;
2347     int base;
2348   }
2349 sib;
2350 static struct
2351   {
2352     int register_specifier;
2353     int length;
2354     int prefix;
2355     int w;
2356   }
2357 vex;
2358 static unsigned char need_vex;
2359 static unsigned char need_vex_reg;
2360 static unsigned char vex_w_done;
2361
2362 struct op
2363   {
2364     const char *name;
2365     unsigned int len;
2366   };
2367
2368 /* If we are accessing mod/rm/reg without need_modrm set, then the
2369    values are stale.  Hitting this abort likely indicates that you
2370    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2371 #define MODRM_CHECK  if (!need_modrm) abort ()
2372
2373 static const char **names64;
2374 static const char **names32;
2375 static const char **names16;
2376 static const char **names8;
2377 static const char **names8rex;
2378 static const char **names_seg;
2379 static const char *index64;
2380 static const char *index32;
2381 static const char **index16;
2382 static const char **names_bnd;
2383
2384 static const char *intel_names64[] = {
2385   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2386   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2387 };
2388 static const char *intel_names32[] = {
2389   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2390   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2391 };
2392 static const char *intel_names16[] = {
2393   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2394   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2395 };
2396 static const char *intel_names8[] = {
2397   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2398 };
2399 static const char *intel_names8rex[] = {
2400   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2401   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2402 };
2403 static const char *intel_names_seg[] = {
2404   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2405 };
2406 static const char *intel_index64 = "riz";
2407 static const char *intel_index32 = "eiz";
2408 static const char *intel_index16[] = {
2409   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2410 };
2411
2412 static const char *att_names64[] = {
2413   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2414   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2415 };
2416 static const char *att_names32[] = {
2417   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2418   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2419 };
2420 static const char *att_names16[] = {
2421   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2422   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2423 };
2424 static const char *att_names8[] = {
2425   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2426 };
2427 static const char *att_names8rex[] = {
2428   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2429   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2430 };
2431 static const char *att_names_seg[] = {
2432   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2433 };
2434 static const char *att_index64 = "%riz";
2435 static const char *att_index32 = "%eiz";
2436 static const char *att_index16[] = {
2437   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2438 };
2439
2440 static const char **names_mm;
2441 static const char *intel_names_mm[] = {
2442   "mm0", "mm1", "mm2", "mm3",
2443   "mm4", "mm5", "mm6", "mm7"
2444 };
2445 static const char *att_names_mm[] = {
2446   "%mm0", "%mm1", "%mm2", "%mm3",
2447   "%mm4", "%mm5", "%mm6", "%mm7"
2448 };
2449
2450 static const char *intel_names_bnd[] = {
2451   "bnd0", "bnd1", "bnd2", "bnd3"
2452 };
2453
2454 static const char *att_names_bnd[] = {
2455   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2456 };
2457
2458 static const char **names_xmm;
2459 static const char *intel_names_xmm[] = {
2460   "xmm0", "xmm1", "xmm2", "xmm3",
2461   "xmm4", "xmm5", "xmm6", "xmm7",
2462   "xmm8", "xmm9", "xmm10", "xmm11",
2463   "xmm12", "xmm13", "xmm14", "xmm15"
2464 };
2465 static const char *att_names_xmm[] = {
2466   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2467   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2468   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2469   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2470 };
2471
2472 static const char **names_ymm;
2473 static const char *intel_names_ymm[] = {
2474   "ymm0", "ymm1", "ymm2", "ymm3",
2475   "ymm4", "ymm5", "ymm6", "ymm7",
2476   "ymm8", "ymm9", "ymm10", "ymm11",
2477   "ymm12", "ymm13", "ymm14", "ymm15"
2478 };
2479 static const char *att_names_ymm[] = {
2480   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2481   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2482   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2483   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2484 };
2485
2486 static const struct dis386 reg_table[][8] = {
2487   /* REG_80 */
2488   {
2489     { "addA",   { Ebh1, Ib } },
2490     { "orA",    { Ebh1, Ib } },
2491     { "adcA",   { Ebh1, Ib } },
2492     { "sbbA",   { Ebh1, Ib } },
2493     { "andA",   { Ebh1, Ib } },
2494     { "subA",   { Ebh1, Ib } },
2495     { "xorA",   { Ebh1, Ib } },
2496     { "cmpA",   { Eb, Ib } },
2497   },
2498   /* REG_81 */
2499   {
2500     { "addQ",   { Evh1, Iv } },
2501     { "orQ",    { Evh1, Iv } },
2502     { "adcQ",   { Evh1, Iv } },
2503     { "sbbQ",   { Evh1, Iv } },
2504     { "andQ",   { Evh1, Iv } },
2505     { "subQ",   { Evh1, Iv } },
2506     { "xorQ",   { Evh1, Iv } },
2507     { "cmpQ",   { Ev, Iv } },
2508   },
2509   /* REG_82 */
2510   {
2511     { "addQ",   { Evh1, sIb } },
2512     { "orQ",    { Evh1, sIb } },
2513     { "adcQ",   { Evh1, sIb } },
2514     { "sbbQ",   { Evh1, sIb } },
2515     { "andQ",   { Evh1, sIb } },
2516     { "subQ",   { Evh1, sIb } },
2517     { "xorQ",   { Evh1, sIb } },
2518     { "cmpQ",   { Ev, sIb } },
2519   },
2520   /* REG_8F */
2521   {
2522     { "popU",   { stackEv } },
2523     { XOP_8F_TABLE (XOP_09) },
2524     { Bad_Opcode },
2525     { Bad_Opcode },
2526     { Bad_Opcode },
2527     { XOP_8F_TABLE (XOP_09) },
2528   },
2529   /* REG_C0 */
2530   {
2531     { "rolA",   { Eb, Ib } },
2532     { "rorA",   { Eb, Ib } },
2533     { "rclA",   { Eb, Ib } },
2534     { "rcrA",   { Eb, Ib } },
2535     { "shlA",   { Eb, Ib } },
2536     { "shrA",   { Eb, Ib } },
2537     { Bad_Opcode },
2538     { "sarA",   { Eb, Ib } },
2539   },
2540   /* REG_C1 */
2541   {
2542     { "rolQ",   { Ev, Ib } },
2543     { "rorQ",   { Ev, Ib } },
2544     { "rclQ",   { Ev, Ib } },
2545     { "rcrQ",   { Ev, Ib } },
2546     { "shlQ",   { Ev, Ib } },
2547     { "shrQ",   { Ev, Ib } },
2548     { Bad_Opcode },
2549     { "sarQ",   { Ev, Ib } },
2550   },
2551   /* REG_C6 */
2552   {
2553     { "movA",   { Ebh3, Ib } },
2554     { Bad_Opcode },
2555     { Bad_Opcode },
2556     { Bad_Opcode },
2557     { Bad_Opcode },
2558     { Bad_Opcode },
2559     { Bad_Opcode },
2560     { MOD_TABLE (MOD_C6_REG_7) },
2561   },
2562   /* REG_C7 */
2563   {
2564     { "movQ",   { Evh3, Iv } },
2565     { Bad_Opcode },
2566     { Bad_Opcode },
2567     { Bad_Opcode },
2568     { Bad_Opcode },
2569     { Bad_Opcode },
2570     { Bad_Opcode },
2571     { MOD_TABLE (MOD_C7_REG_7) },
2572   },
2573   /* REG_D0 */
2574   {
2575     { "rolA",   { Eb, I1 } },
2576     { "rorA",   { Eb, I1 } },
2577     { "rclA",   { Eb, I1 } },
2578     { "rcrA",   { Eb, I1 } },
2579     { "shlA",   { Eb, I1 } },
2580     { "shrA",   { Eb, I1 } },
2581     { Bad_Opcode },
2582     { "sarA",   { Eb, I1 } },
2583   },
2584   /* REG_D1 */
2585   {
2586     { "rolQ",   { Ev, I1 } },
2587     { "rorQ",   { Ev, I1 } },
2588     { "rclQ",   { Ev, I1 } },
2589     { "rcrQ",   { Ev, I1 } },
2590     { "shlQ",   { Ev, I1 } },
2591     { "shrQ",   { Ev, I1 } },
2592     { Bad_Opcode },
2593     { "sarQ",   { Ev, I1 } },
2594   },
2595   /* REG_D2 */
2596   {
2597     { "rolA",   { Eb, CL } },
2598     { "rorA",   { Eb, CL } },
2599     { "rclA",   { Eb, CL } },
2600     { "rcrA",   { Eb, CL } },
2601     { "shlA",   { Eb, CL } },
2602     { "shrA",   { Eb, CL } },
2603     { Bad_Opcode },
2604     { "sarA",   { Eb, CL } },
2605   },
2606   /* REG_D3 */
2607   {
2608     { "rolQ",   { Ev, CL } },
2609     { "rorQ",   { Ev, CL } },
2610     { "rclQ",   { Ev, CL } },
2611     { "rcrQ",   { Ev, CL } },
2612     { "shlQ",   { Ev, CL } },
2613     { "shrQ",   { Ev, CL } },
2614     { Bad_Opcode },
2615     { "sarQ",   { Ev, CL } },
2616   },
2617   /* REG_F6 */
2618   {
2619     { "testA",  { Eb, Ib } },
2620     { Bad_Opcode },
2621     { "notA",   { Ebh1 } },
2622     { "negA",   { Ebh1 } },
2623     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2624     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2625     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2626     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2627   },
2628   /* REG_F7 */
2629   {
2630     { "testQ",  { Ev, Iv } },
2631     { Bad_Opcode },
2632     { "notQ",   { Evh1 } },
2633     { "negQ",   { Evh1 } },
2634     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2635     { "imulQ",  { Ev } },
2636     { "divQ",   { Ev } },
2637     { "idivQ",  { Ev } },
2638   },
2639   /* REG_FE */
2640   {
2641     { "incA",   { Ebh1 } },
2642     { "decA",   { Ebh1 } },
2643   },
2644   /* REG_FF */
2645   {
2646     { "incQ",   { Evh1 } },
2647     { "decQ",   { Evh1 } },
2648     { "call{T|}", { indirEv, BND } },
2649     { "Jcall{T|}", { indirEp } },
2650     { "jmp{T|}", { indirEv, BND } },
2651     { "Jjmp{T|}", { indirEp } },
2652     { "pushU",  { stackEv } },
2653     { Bad_Opcode },
2654   },
2655   /* REG_0F00 */
2656   {
2657     { "sldtD",  { Sv } },
2658     { "strD",   { Sv } },
2659     { "lldt",   { Ew } },
2660     { "ltr",    { Ew } },
2661     { "verr",   { Ew } },
2662     { "verw",   { Ew } },
2663     { Bad_Opcode },
2664     { Bad_Opcode },
2665   },
2666   /* REG_0F01 */
2667   {
2668     { MOD_TABLE (MOD_0F01_REG_0) },
2669     { MOD_TABLE (MOD_0F01_REG_1) },
2670     { MOD_TABLE (MOD_0F01_REG_2) },
2671     { MOD_TABLE (MOD_0F01_REG_3) },
2672     { "smswD",  { Sv } },
2673     { Bad_Opcode },
2674     { "lmsw",   { Ew } },
2675     { MOD_TABLE (MOD_0F01_REG_7) },
2676   },
2677   /* REG_0F0D */
2678   {
2679     { "prefetch",       { Mb } },
2680     { "prefetchw",      { Mb } },
2681     { "prefetch",       { Mb } },
2682     { "prefetch",       { Mb } },
2683     { "prefetch",       { Mb } },
2684     { "prefetch",       { Mb } },
2685     { "prefetch",       { Mb } },
2686     { "prefetch",       { Mb } },
2687   },
2688   /* REG_0F18 */
2689   {
2690     { MOD_TABLE (MOD_0F18_REG_0) },
2691     { MOD_TABLE (MOD_0F18_REG_1) },
2692     { MOD_TABLE (MOD_0F18_REG_2) },
2693     { MOD_TABLE (MOD_0F18_REG_3) },
2694     { MOD_TABLE (MOD_0F18_REG_4) },
2695     { MOD_TABLE (MOD_0F18_REG_5) },
2696     { MOD_TABLE (MOD_0F18_REG_6) },
2697     { MOD_TABLE (MOD_0F18_REG_7) },
2698   },
2699   /* REG_0F71 */
2700   {
2701     { Bad_Opcode },
2702     { Bad_Opcode },
2703     { MOD_TABLE (MOD_0F71_REG_2) },
2704     { Bad_Opcode },
2705     { MOD_TABLE (MOD_0F71_REG_4) },
2706     { Bad_Opcode },
2707     { MOD_TABLE (MOD_0F71_REG_6) },
2708   },
2709   /* REG_0F72 */
2710   {
2711     { Bad_Opcode },
2712     { Bad_Opcode },
2713     { MOD_TABLE (MOD_0F72_REG_2) },
2714     { Bad_Opcode },
2715     { MOD_TABLE (MOD_0F72_REG_4) },
2716     { Bad_Opcode },
2717     { MOD_TABLE (MOD_0F72_REG_6) },
2718   },
2719   /* REG_0F73 */
2720   {
2721     { Bad_Opcode },
2722     { Bad_Opcode },
2723     { MOD_TABLE (MOD_0F73_REG_2) },
2724     { MOD_TABLE (MOD_0F73_REG_3) },
2725     { Bad_Opcode },
2726     { Bad_Opcode },
2727     { MOD_TABLE (MOD_0F73_REG_6) },
2728     { MOD_TABLE (MOD_0F73_REG_7) },
2729   },
2730   /* REG_0FA6 */
2731   {
2732     { "montmul",        { { OP_0f07, 0 } } },
2733     { "xsha1",          { { OP_0f07, 0 } } },
2734     { "xsha256",        { { OP_0f07, 0 } } },
2735   },
2736   /* REG_0FA7 */
2737   {
2738     { "xstore-rng",     { { OP_0f07, 0 } } },
2739     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2740     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2741     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2742     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2743     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2744   },
2745   /* REG_0FAE */
2746   {
2747     { MOD_TABLE (MOD_0FAE_REG_0) },
2748     { MOD_TABLE (MOD_0FAE_REG_1) },
2749     { MOD_TABLE (MOD_0FAE_REG_2) },
2750     { MOD_TABLE (MOD_0FAE_REG_3) },
2751     { MOD_TABLE (MOD_0FAE_REG_4) },
2752     { MOD_TABLE (MOD_0FAE_REG_5) },
2753     { MOD_TABLE (MOD_0FAE_REG_6) },
2754     { MOD_TABLE (MOD_0FAE_REG_7) },
2755   },
2756   /* REG_0FBA */
2757   {
2758     { Bad_Opcode },
2759     { Bad_Opcode },
2760     { Bad_Opcode },
2761     { Bad_Opcode },
2762     { "btQ",    { Ev, Ib } },
2763     { "btsQ",   { Evh1, Ib } },
2764     { "btrQ",   { Evh1, Ib } },
2765     { "btcQ",   { Evh1, Ib } },
2766   },
2767   /* REG_0FC7 */
2768   {
2769     { Bad_Opcode },
2770     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2771     { Bad_Opcode },
2772     { Bad_Opcode },
2773     { Bad_Opcode },
2774     { Bad_Opcode },
2775     { MOD_TABLE (MOD_0FC7_REG_6) },
2776     { MOD_TABLE (MOD_0FC7_REG_7) },
2777   },
2778   /* REG_VEX_0F71 */
2779   {
2780     { Bad_Opcode },
2781     { Bad_Opcode },
2782     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2783     { Bad_Opcode },
2784     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2785     { Bad_Opcode },
2786     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2787   },
2788   /* REG_VEX_0F72 */
2789   {
2790     { Bad_Opcode },
2791     { Bad_Opcode },
2792     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2793     { Bad_Opcode },
2794     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2795     { Bad_Opcode },
2796     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2797   },
2798   /* REG_VEX_0F73 */
2799   {
2800     { Bad_Opcode },
2801     { Bad_Opcode },
2802     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2803     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2804     { Bad_Opcode },
2805     { Bad_Opcode },
2806     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2807     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2808   },
2809   /* REG_VEX_0FAE */
2810   {
2811     { Bad_Opcode },
2812     { Bad_Opcode },
2813     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2814     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2815   },
2816   /* REG_VEX_0F38F3 */
2817   {
2818     { Bad_Opcode },
2819     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2820     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2821     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2822   },
2823   /* REG_XOP_LWPCB */
2824   {
2825     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2826     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2827   },
2828   /* REG_XOP_LWP */
2829   {
2830     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2831     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2832   },
2833   /* REG_XOP_TBM_01 */
2834   {
2835     { Bad_Opcode },
2836     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
2837     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
2838     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
2839     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
2840     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
2841     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
2842     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2843   },
2844   /* REG_XOP_TBM_02 */
2845   {
2846     { Bad_Opcode },
2847     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2848     { Bad_Opcode },
2849     { Bad_Opcode },
2850     { Bad_Opcode },
2851     { Bad_Opcode },
2852     { "blci",   { { OP_LWP_E, 0 }, Ev } },
2853   },
2854 };
2855
2856 static const struct dis386 prefix_table[][4] = {
2857   /* PREFIX_90 */
2858   {
2859     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2860     { "pause", { XX } },
2861     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2862   },
2863
2864   /* PREFIX_0F10 */
2865   {
2866     { "movups", { XM, EXx } },
2867     { "movss",  { XM, EXd } },
2868     { "movupd", { XM, EXx } },
2869     { "movsd",  { XM, EXq } },
2870   },
2871
2872   /* PREFIX_0F11 */
2873   {
2874     { "movups", { EXxS, XM } },
2875     { "movss",  { EXdS, XM } },
2876     { "movupd", { EXxS, XM } },
2877     { "movsd",  { EXqS, XM } },
2878   },
2879
2880   /* PREFIX_0F12 */
2881   {
2882     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2883     { "movsldup", { XM, EXx } },
2884     { "movlpd", { XM, EXq } },
2885     { "movddup", { XM, EXq } },
2886   },
2887
2888   /* PREFIX_0F16 */
2889   {
2890     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2891     { "movshdup", { XM, EXx } },
2892     { "movhpd", { XM, EXq } },
2893   },
2894
2895   /* PREFIX_0F1A */
2896   {
2897     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
2898     { "bndcl",  { Gbnd, Ev_bnd } },
2899     { "bndmov", { Gbnd, Ebnd } },
2900     { "bndcu",  { Gbnd, Ev_bnd } },
2901   },
2902
2903   /* PREFIX_0F1B */
2904   {
2905     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
2906     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
2907     { "bndmov", { Ebnd, Gbnd } },
2908     { "bndcn",  { Gbnd, Ev_bnd } },
2909   },
2910
2911   /* PREFIX_0F2A */
2912   {
2913     { "cvtpi2ps", { XM, EMCq } },
2914     { "cvtsi2ss%LQ", { XM, Ev } },
2915     { "cvtpi2pd", { XM, EMCq } },
2916     { "cvtsi2sd%LQ", { XM, Ev } },
2917   },
2918
2919   /* PREFIX_0F2B */
2920   {
2921     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2922     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2923     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2924     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2925   },
2926
2927   /* PREFIX_0F2C */
2928   {
2929     { "cvttps2pi", { MXC, EXq } },
2930     { "cvttss2siY", { Gv, EXd } },
2931     { "cvttpd2pi", { MXC, EXx } },
2932     { "cvttsd2siY", { Gv, EXq } },
2933   },
2934
2935   /* PREFIX_0F2D */
2936   {
2937     { "cvtps2pi", { MXC, EXq } },
2938     { "cvtss2siY", { Gv, EXd } },
2939     { "cvtpd2pi", { MXC, EXx } },
2940     { "cvtsd2siY", { Gv, EXq } },
2941   },
2942
2943   /* PREFIX_0F2E */
2944   {
2945     { "ucomiss",{ XM, EXd } },
2946     { Bad_Opcode },
2947     { "ucomisd",{ XM, EXq } },
2948   },
2949
2950   /* PREFIX_0F2F */
2951   {
2952     { "comiss", { XM, EXd } },
2953     { Bad_Opcode },
2954     { "comisd", { XM, EXq } },
2955   },
2956
2957   /* PREFIX_0F51 */
2958   {
2959     { "sqrtps", { XM, EXx } },
2960     { "sqrtss", { XM, EXd } },
2961     { "sqrtpd", { XM, EXx } },
2962     { "sqrtsd", { XM, EXq } },
2963   },
2964
2965   /* PREFIX_0F52 */
2966   {
2967     { "rsqrtps",{ XM, EXx } },
2968     { "rsqrtss",{ XM, EXd } },
2969   },
2970
2971   /* PREFIX_0F53 */
2972   {
2973     { "rcpps",  { XM, EXx } },
2974     { "rcpss",  { XM, EXd } },
2975   },
2976
2977   /* PREFIX_0F58 */
2978   {
2979     { "addps", { XM, EXx } },
2980     { "addss", { XM, EXd } },
2981     { "addpd", { XM, EXx } },
2982     { "addsd", { XM, EXq } },
2983   },
2984
2985   /* PREFIX_0F59 */
2986   {
2987     { "mulps",  { XM, EXx } },
2988     { "mulss",  { XM, EXd } },
2989     { "mulpd",  { XM, EXx } },
2990     { "mulsd",  { XM, EXq } },
2991   },
2992
2993   /* PREFIX_0F5A */
2994   {
2995     { "cvtps2pd", { XM, EXq } },
2996     { "cvtss2sd", { XM, EXd } },
2997     { "cvtpd2ps", { XM, EXx } },
2998     { "cvtsd2ss", { XM, EXq } },
2999   },
3000
3001   /* PREFIX_0F5B */
3002   {
3003     { "cvtdq2ps", { XM, EXx } },
3004     { "cvttps2dq", { XM, EXx } },
3005     { "cvtps2dq", { XM, EXx } },
3006   },
3007
3008   /* PREFIX_0F5C */
3009   {
3010     { "subps",  { XM, EXx } },
3011     { "subss",  { XM, EXd } },
3012     { "subpd",  { XM, EXx } },
3013     { "subsd",  { XM, EXq } },
3014   },
3015
3016   /* PREFIX_0F5D */
3017   {
3018     { "minps",  { XM, EXx } },
3019     { "minss",  { XM, EXd } },
3020     { "minpd",  { XM, EXx } },
3021     { "minsd",  { XM, EXq } },
3022   },
3023
3024   /* PREFIX_0F5E */
3025   {
3026     { "divps",  { XM, EXx } },
3027     { "divss",  { XM, EXd } },
3028     { "divpd",  { XM, EXx } },
3029     { "divsd",  { XM, EXq } },
3030   },
3031
3032   /* PREFIX_0F5F */
3033   {
3034     { "maxps",  { XM, EXx } },
3035     { "maxss",  { XM, EXd } },
3036     { "maxpd",  { XM, EXx } },
3037     { "maxsd",  { XM, EXq } },
3038   },
3039
3040   /* PREFIX_0F60 */
3041   {
3042     { "punpcklbw",{ MX, EMd } },
3043     { Bad_Opcode },
3044     { "punpcklbw",{ MX, EMx } },
3045   },
3046
3047   /* PREFIX_0F61 */
3048   {
3049     { "punpcklwd",{ MX, EMd } },
3050     { Bad_Opcode },
3051     { "punpcklwd",{ MX, EMx } },
3052   },
3053
3054   /* PREFIX_0F62 */
3055   {
3056     { "punpckldq",{ MX, EMd } },
3057     { Bad_Opcode },
3058     { "punpckldq",{ MX, EMx } },
3059   },
3060
3061   /* PREFIX_0F6C */
3062   {
3063     { Bad_Opcode },
3064     { Bad_Opcode },
3065     { "punpcklqdq", { XM, EXx } },
3066   },
3067
3068   /* PREFIX_0F6D */
3069   {
3070     { Bad_Opcode },
3071     { Bad_Opcode },
3072     { "punpckhqdq", { XM, EXx } },
3073   },
3074
3075   /* PREFIX_0F6F */
3076   {
3077     { "movq",   { MX, EM } },
3078     { "movdqu", { XM, EXx } },
3079     { "movdqa", { XM, EXx } },
3080   },
3081
3082   /* PREFIX_0F70 */
3083   {
3084     { "pshufw", { MX, EM, Ib } },
3085     { "pshufhw",{ XM, EXx, Ib } },
3086     { "pshufd", { XM, EXx, Ib } },
3087     { "pshuflw",{ XM, EXx, Ib } },
3088   },
3089
3090   /* PREFIX_0F73_REG_3 */
3091   {
3092     { Bad_Opcode },
3093     { Bad_Opcode },
3094     { "psrldq", { XS, Ib } },
3095   },
3096
3097   /* PREFIX_0F73_REG_7 */
3098   {
3099     { Bad_Opcode },
3100     { Bad_Opcode },
3101     { "pslldq", { XS, Ib } },
3102   },
3103
3104   /* PREFIX_0F78 */
3105   {
3106     {"vmread",  { Em, Gm } },
3107     { Bad_Opcode },
3108     {"extrq",   { XS, Ib, Ib } },
3109     {"insertq", { XM, XS, Ib, Ib } },
3110   },
3111
3112   /* PREFIX_0F79 */
3113   {
3114     {"vmwrite", { Gm, Em } },
3115     { Bad_Opcode },
3116     {"extrq",   { XM, XS } },
3117     {"insertq", { XM, XS } },
3118   },
3119
3120   /* PREFIX_0F7C */
3121   {
3122     { Bad_Opcode },
3123     { Bad_Opcode },
3124     { "haddpd", { XM, EXx } },
3125     { "haddps", { XM, EXx } },
3126   },
3127
3128   /* PREFIX_0F7D */
3129   {
3130     { Bad_Opcode },
3131     { Bad_Opcode },
3132     { "hsubpd", { XM, EXx } },
3133     { "hsubps", { XM, EXx } },
3134   },
3135
3136   /* PREFIX_0F7E */
3137   {
3138     { "movK",   { Edq, MX } },
3139     { "movq",   { XM, EXq } },
3140     { "movK",   { Edq, XM } },
3141   },
3142
3143   /* PREFIX_0F7F */
3144   {
3145     { "movq",   { EMS, MX } },
3146     { "movdqu", { EXxS, XM } },
3147     { "movdqa", { EXxS, XM } },
3148   },
3149
3150   /* PREFIX_0FAE_REG_0 */
3151   {
3152     { Bad_Opcode },
3153     { "rdfsbase", { Ev } },
3154   },
3155
3156   /* PREFIX_0FAE_REG_1 */
3157   {
3158     { Bad_Opcode },
3159     { "rdgsbase", { Ev } },
3160   },
3161
3162   /* PREFIX_0FAE_REG_2 */
3163   {
3164     { Bad_Opcode },
3165     { "wrfsbase", { Ev } },
3166   },
3167
3168   /* PREFIX_0FAE_REG_3 */
3169   {
3170     { Bad_Opcode },
3171     { "wrgsbase", { Ev } },
3172   },
3173
3174   /* PREFIX_0FB8 */
3175   {
3176     { Bad_Opcode },
3177     { "popcntS", { Gv, Ev } },
3178   },
3179
3180   /* PREFIX_0FBC */
3181   {
3182     { "bsfS",   { Gv, Ev } },
3183     { "tzcntS", { Gv, Ev } },
3184     { "bsfS",   { Gv, Ev } },
3185   },
3186
3187   /* PREFIX_0FBD */
3188   {
3189     { "bsrS",   { Gv, Ev } },
3190     { "lzcntS", { Gv, Ev } },
3191     { "bsrS",   { Gv, Ev } },
3192   },
3193
3194   /* PREFIX_0FC2 */
3195   {
3196     { "cmpps",  { XM, EXx, CMP } },
3197     { "cmpss",  { XM, EXd, CMP } },
3198     { "cmppd",  { XM, EXx, CMP } },
3199     { "cmpsd",  { XM, EXq, CMP } },
3200   },
3201
3202   /* PREFIX_0FC3 */
3203   {
3204     { "movntiS", { Ma, Gv } },
3205   },
3206
3207   /* PREFIX_0FC7_REG_6 */
3208   {
3209     { "vmptrld",{ Mq } },
3210     { "vmxon",  { Mq } },
3211     { "vmclear",{ Mq } },
3212   },
3213
3214   /* PREFIX_0FD0 */
3215   {
3216     { Bad_Opcode },
3217     { Bad_Opcode },
3218     { "addsubpd", { XM, EXx } },
3219     { "addsubps", { XM, EXx } },
3220   },
3221
3222   /* PREFIX_0FD6 */
3223   {
3224     { Bad_Opcode },
3225     { "movq2dq",{ XM, MS } },
3226     { "movq",   { EXqS, XM } },
3227     { "movdq2q",{ MX, XS } },
3228   },
3229
3230   /* PREFIX_0FE6 */
3231   {
3232     { Bad_Opcode },
3233     { "cvtdq2pd", { XM, EXq } },
3234     { "cvttpd2dq", { XM, EXx } },
3235     { "cvtpd2dq", { XM, EXx } },
3236   },
3237
3238   /* PREFIX_0FE7 */
3239   {
3240     { "movntq", { Mq, MX } },
3241     { Bad_Opcode },
3242     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3243   },
3244
3245   /* PREFIX_0FF0 */
3246   {
3247     { Bad_Opcode },
3248     { Bad_Opcode },
3249     { Bad_Opcode },
3250     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3251   },
3252
3253   /* PREFIX_0FF7 */
3254   {
3255     { "maskmovq", { MX, MS } },
3256     { Bad_Opcode },
3257     { "maskmovdqu", { XM, XS } },
3258   },
3259
3260   /* PREFIX_0F3810 */
3261   {
3262     { Bad_Opcode },
3263     { Bad_Opcode },
3264     { "pblendvb", { XM, EXx, XMM0 } },
3265   },
3266
3267   /* PREFIX_0F3814 */
3268   {
3269     { Bad_Opcode },
3270     { Bad_Opcode },
3271     { "blendvps", { XM, EXx, XMM0 } },
3272   },
3273
3274   /* PREFIX_0F3815 */
3275   {
3276     { Bad_Opcode },
3277     { Bad_Opcode },
3278     { "blendvpd", { XM, EXx, XMM0 } },
3279   },
3280
3281   /* PREFIX_0F3817 */
3282   {
3283     { Bad_Opcode },
3284     { Bad_Opcode },
3285     { "ptest",  { XM, EXx } },
3286   },
3287
3288   /* PREFIX_0F3820 */
3289   {
3290     { Bad_Opcode },
3291     { Bad_Opcode },
3292     { "pmovsxbw", { XM, EXq } },
3293   },
3294
3295   /* PREFIX_0F3821 */
3296   {
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { "pmovsxbd", { XM, EXd } },
3300   },
3301
3302   /* PREFIX_0F3822 */
3303   {
3304     { Bad_Opcode },
3305     { Bad_Opcode },
3306     { "pmovsxbq", { XM, EXw } },
3307   },
3308
3309   /* PREFIX_0F3823 */
3310   {
3311     { Bad_Opcode },
3312     { Bad_Opcode },
3313     { "pmovsxwd", { XM, EXq } },
3314   },
3315
3316   /* PREFIX_0F3824 */
3317   {
3318     { Bad_Opcode },
3319     { Bad_Opcode },
3320     { "pmovsxwq", { XM, EXd } },
3321   },
3322
3323   /* PREFIX_0F3825 */
3324   {
3325     { Bad_Opcode },
3326     { Bad_Opcode },
3327     { "pmovsxdq", { XM, EXq } },
3328   },
3329
3330   /* PREFIX_0F3828 */
3331   {
3332     { Bad_Opcode },
3333     { Bad_Opcode },
3334     { "pmuldq", { XM, EXx } },
3335   },
3336
3337   /* PREFIX_0F3829 */
3338   {
3339     { Bad_Opcode },
3340     { Bad_Opcode },
3341     { "pcmpeqq", { XM, EXx } },
3342   },
3343
3344   /* PREFIX_0F382A */
3345   {
3346     { Bad_Opcode },
3347     { Bad_Opcode },
3348     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3349   },
3350
3351   /* PREFIX_0F382B */
3352   {
3353     { Bad_Opcode },
3354     { Bad_Opcode },
3355     { "packusdw", { XM, EXx } },
3356   },
3357
3358   /* PREFIX_0F3830 */
3359   {
3360     { Bad_Opcode },
3361     { Bad_Opcode },
3362     { "pmovzxbw", { XM, EXq } },
3363   },
3364
3365   /* PREFIX_0F3831 */
3366   {
3367     { Bad_Opcode },
3368     { Bad_Opcode },
3369     { "pmovzxbd", { XM, EXd } },
3370   },
3371
3372   /* PREFIX_0F3832 */
3373   {
3374     { Bad_Opcode },
3375     { Bad_Opcode },
3376     { "pmovzxbq", { XM, EXw } },
3377   },
3378
3379   /* PREFIX_0F3833 */
3380   {
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383     { "pmovzxwd", { XM, EXq } },
3384   },
3385
3386   /* PREFIX_0F3834 */
3387   {
3388     { Bad_Opcode },
3389     { Bad_Opcode },
3390     { "pmovzxwq", { XM, EXd } },
3391   },
3392
3393   /* PREFIX_0F3835 */
3394   {
3395     { Bad_Opcode },
3396     { Bad_Opcode },
3397     { "pmovzxdq", { XM, EXq } },
3398   },
3399
3400   /* PREFIX_0F3837 */
3401   {
3402     { Bad_Opcode },
3403     { Bad_Opcode },
3404     { "pcmpgtq", { XM, EXx } },
3405   },
3406
3407   /* PREFIX_0F3838 */
3408   {
3409     { Bad_Opcode },
3410     { Bad_Opcode },
3411     { "pminsb", { XM, EXx } },
3412   },
3413
3414   /* PREFIX_0F3839 */
3415   {
3416     { Bad_Opcode },
3417     { Bad_Opcode },
3418     { "pminsd", { XM, EXx } },
3419   },
3420
3421   /* PREFIX_0F383A */
3422   {
3423     { Bad_Opcode },
3424     { Bad_Opcode },
3425     { "pminuw", { XM, EXx } },
3426   },
3427
3428   /* PREFIX_0F383B */
3429   {
3430     { Bad_Opcode },
3431     { Bad_Opcode },
3432     { "pminud", { XM, EXx } },
3433   },
3434
3435   /* PREFIX_0F383C */
3436   {
3437     { Bad_Opcode },
3438     { Bad_Opcode },
3439     { "pmaxsb", { XM, EXx } },
3440   },
3441
3442   /* PREFIX_0F383D */
3443   {
3444     { Bad_Opcode },
3445     { Bad_Opcode },
3446     { "pmaxsd", { XM, EXx } },
3447   },
3448
3449   /* PREFIX_0F383E */
3450   {
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { "pmaxuw", { XM, EXx } },
3454   },
3455
3456   /* PREFIX_0F383F */
3457   {
3458     { Bad_Opcode },
3459     { Bad_Opcode },
3460     { "pmaxud", { XM, EXx } },
3461   },
3462
3463   /* PREFIX_0F3840 */
3464   {
3465     { Bad_Opcode },
3466     { Bad_Opcode },
3467     { "pmulld", { XM, EXx } },
3468   },
3469
3470   /* PREFIX_0F3841 */
3471   {
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { "phminposuw", { XM, EXx } },
3475   },
3476
3477   /* PREFIX_0F3880 */
3478   {
3479     { Bad_Opcode },
3480     { Bad_Opcode },
3481     { "invept", { Gm, Mo } },
3482   },
3483
3484   /* PREFIX_0F3881 */
3485   {
3486     { Bad_Opcode },
3487     { Bad_Opcode },
3488     { "invvpid", { Gm, Mo } },
3489   },
3490
3491   /* PREFIX_0F3882 */
3492   {
3493     { Bad_Opcode },
3494     { Bad_Opcode },
3495     { "invpcid", { Gm, M } },
3496   },
3497
3498   /* PREFIX_0F38DB */
3499   {
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { "aesimc", { XM, EXx } },
3503   },
3504
3505   /* PREFIX_0F38DC */
3506   {
3507     { Bad_Opcode },
3508     { Bad_Opcode },
3509     { "aesenc", { XM, EXx } },
3510   },
3511
3512   /* PREFIX_0F38DD */
3513   {
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { "aesenclast", { XM, EXx } },
3517   },
3518
3519   /* PREFIX_0F38DE */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { "aesdec", { XM, EXx } },
3524   },
3525
3526   /* PREFIX_0F38DF */
3527   {
3528     { Bad_Opcode },
3529     { Bad_Opcode },
3530     { "aesdeclast", { XM, EXx } },
3531   },
3532
3533   /* PREFIX_0F38F0 */
3534   {
3535     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3536     { Bad_Opcode },
3537     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3538     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3539   },
3540
3541   /* PREFIX_0F38F1 */
3542   {
3543     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3544     { Bad_Opcode },
3545     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3546     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3547   },
3548
3549   /* PREFIX_0F38F6 */
3550   {
3551     { Bad_Opcode },
3552     { "adoxS",  { Gdq, Edq} },
3553     { "adcxS",  { Gdq, Edq} },
3554     { Bad_Opcode },
3555   },
3556
3557   /* PREFIX_0F3A08 */
3558   {
3559     { Bad_Opcode },
3560     { Bad_Opcode },
3561     { "roundps", { XM, EXx, Ib } },
3562   },
3563
3564   /* PREFIX_0F3A09 */
3565   {
3566     { Bad_Opcode },
3567     { Bad_Opcode },
3568     { "roundpd", { XM, EXx, Ib } },
3569   },
3570
3571   /* PREFIX_0F3A0A */
3572   {
3573     { Bad_Opcode },
3574     { Bad_Opcode },
3575     { "roundss", { XM, EXd, Ib } },
3576   },
3577
3578   /* PREFIX_0F3A0B */
3579   {
3580     { Bad_Opcode },
3581     { Bad_Opcode },
3582     { "roundsd", { XM, EXq, Ib } },
3583   },
3584
3585   /* PREFIX_0F3A0C */
3586   {
3587     { Bad_Opcode },
3588     { Bad_Opcode },
3589     { "blendps", { XM, EXx, Ib } },
3590   },
3591
3592   /* PREFIX_0F3A0D */
3593   {
3594     { Bad_Opcode },
3595     { Bad_Opcode },
3596     { "blendpd", { XM, EXx, Ib } },
3597   },
3598
3599   /* PREFIX_0F3A0E */
3600   {
3601     { Bad_Opcode },
3602     { Bad_Opcode },
3603     { "pblendw", { XM, EXx, Ib } },
3604   },
3605
3606   /* PREFIX_0F3A14 */
3607   {
3608     { Bad_Opcode },
3609     { Bad_Opcode },
3610     { "pextrb", { Edqb, XM, Ib } },
3611   },
3612
3613   /* PREFIX_0F3A15 */
3614   {
3615     { Bad_Opcode },
3616     { Bad_Opcode },
3617     { "pextrw", { Edqw, XM, Ib } },
3618   },
3619
3620   /* PREFIX_0F3A16 */
3621   {
3622     { Bad_Opcode },
3623     { Bad_Opcode },
3624     { "pextrK", { Edq, XM, Ib } },
3625   },
3626
3627   /* PREFIX_0F3A17 */
3628   {
3629     { Bad_Opcode },
3630     { Bad_Opcode },
3631     { "extractps", { Edqd, XM, Ib } },
3632   },
3633
3634   /* PREFIX_0F3A20 */
3635   {
3636     { Bad_Opcode },
3637     { Bad_Opcode },
3638     { "pinsrb", { XM, Edqb, Ib } },
3639   },
3640
3641   /* PREFIX_0F3A21 */
3642   {
3643     { Bad_Opcode },
3644     { Bad_Opcode },
3645     { "insertps", { XM, EXd, Ib } },
3646   },
3647
3648   /* PREFIX_0F3A22 */
3649   {
3650     { Bad_Opcode },
3651     { Bad_Opcode },
3652     { "pinsrK", { XM, Edq, Ib } },
3653   },
3654
3655   /* PREFIX_0F3A40 */
3656   {
3657     { Bad_Opcode },
3658     { Bad_Opcode },
3659     { "dpps",   { XM, EXx, Ib } },
3660   },
3661
3662   /* PREFIX_0F3A41 */
3663   {
3664     { Bad_Opcode },
3665     { Bad_Opcode },
3666     { "dppd",   { XM, EXx, Ib } },
3667   },
3668
3669   /* PREFIX_0F3A42 */
3670   {
3671     { Bad_Opcode },
3672     { Bad_Opcode },
3673     { "mpsadbw", { XM, EXx, Ib } },
3674   },
3675
3676   /* PREFIX_0F3A44 */
3677   {
3678     { Bad_Opcode },
3679     { Bad_Opcode },
3680     { "pclmulqdq", { XM, EXx, PCLMUL } },
3681   },
3682
3683   /* PREFIX_0F3A60 */
3684   {
3685     { Bad_Opcode },
3686     { Bad_Opcode },
3687     { "pcmpestrm", { XM, EXx, Ib } },
3688   },
3689
3690   /* PREFIX_0F3A61 */
3691   {
3692     { Bad_Opcode },
3693     { Bad_Opcode },
3694     { "pcmpestri", { XM, EXx, Ib } },
3695   },
3696
3697   /* PREFIX_0F3A62 */
3698   {
3699     { Bad_Opcode },
3700     { Bad_Opcode },
3701     { "pcmpistrm", { XM, EXx, Ib } },
3702   },
3703
3704   /* PREFIX_0F3A63 */
3705   {
3706     { Bad_Opcode },
3707     { Bad_Opcode },
3708     { "pcmpistri", { XM, EXx, Ib } },
3709   },
3710
3711   /* PREFIX_0F3ADF */
3712   {
3713     { Bad_Opcode },
3714     { Bad_Opcode },
3715     { "aeskeygenassist", { XM, EXx, Ib } },
3716   },
3717
3718   /* PREFIX_VEX_0F10 */
3719   {
3720     { VEX_W_TABLE (VEX_W_0F10_P_0) },
3721     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3722     { VEX_W_TABLE (VEX_W_0F10_P_2) },
3723     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3724   },
3725
3726   /* PREFIX_VEX_0F11 */
3727   {
3728     { VEX_W_TABLE (VEX_W_0F11_P_0) },
3729     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3730     { VEX_W_TABLE (VEX_W_0F11_P_2) },
3731     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3732   },
3733
3734   /* PREFIX_VEX_0F12 */
3735   {
3736     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3737     { VEX_W_TABLE (VEX_W_0F12_P_1) },
3738     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3739     { VEX_W_TABLE (VEX_W_0F12_P_3) },
3740   },
3741
3742   /* PREFIX_VEX_0F16 */
3743   {
3744     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3745     { VEX_W_TABLE (VEX_W_0F16_P_1) },
3746     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3747   },
3748
3749   /* PREFIX_VEX_0F2A */
3750   {
3751     { Bad_Opcode },
3752     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3753     { Bad_Opcode },
3754     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3755   },
3756
3757   /* PREFIX_VEX_0F2C */
3758   {
3759     { Bad_Opcode },
3760     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3761     { Bad_Opcode },
3762     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3763   },
3764
3765   /* PREFIX_VEX_0F2D */
3766   {
3767     { Bad_Opcode },
3768     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3769     { Bad_Opcode },
3770     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3771   },
3772
3773   /* PREFIX_VEX_0F2E */
3774   {
3775     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3776     { Bad_Opcode },
3777     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3778   },
3779
3780   /* PREFIX_VEX_0F2F */
3781   {
3782     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3783     { Bad_Opcode },
3784     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3785   },
3786
3787   /* PREFIX_VEX_0F51 */
3788   {
3789     { VEX_W_TABLE (VEX_W_0F51_P_0) },
3790     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3791     { VEX_W_TABLE (VEX_W_0F51_P_2) },
3792     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3793   },
3794
3795   /* PREFIX_VEX_0F52 */
3796   {
3797     { VEX_W_TABLE (VEX_W_0F52_P_0) },
3798     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3799   },
3800
3801   /* PREFIX_VEX_0F53 */
3802   {
3803     { VEX_W_TABLE (VEX_W_0F53_P_0) },
3804     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3805   },
3806
3807   /* PREFIX_VEX_0F58 */
3808   {
3809     { VEX_W_TABLE (VEX_W_0F58_P_0) },
3810     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3811     { VEX_W_TABLE (VEX_W_0F58_P_2) },
3812     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3813   },
3814
3815   /* PREFIX_VEX_0F59 */
3816   {
3817     { VEX_W_TABLE (VEX_W_0F59_P_0) },
3818     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3819     { VEX_W_TABLE (VEX_W_0F59_P_2) },
3820     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3821   },
3822
3823   /* PREFIX_VEX_0F5A */
3824   {
3825     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3826     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3827     { "vcvtpd2ps%XY", { XMM, EXx } },
3828     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3829   },
3830
3831   /* PREFIX_VEX_0F5B */
3832   {
3833     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3834     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3835     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3836   },
3837
3838   /* PREFIX_VEX_0F5C */
3839   {
3840     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3841     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3842     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3843     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3844   },
3845
3846   /* PREFIX_VEX_0F5D */
3847   {
3848     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3849     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3850     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3851     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3852   },
3853
3854   /* PREFIX_VEX_0F5E */
3855   {
3856     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3857     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3858     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3859     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3860   },
3861
3862   /* PREFIX_VEX_0F5F */
3863   {
3864     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3865     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3866     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3867     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3868   },
3869
3870   /* PREFIX_VEX_0F60 */
3871   {
3872     { Bad_Opcode },
3873     { Bad_Opcode },
3874     { VEX_W_TABLE (VEX_W_0F60_P_2) },
3875   },
3876
3877   /* PREFIX_VEX_0F61 */
3878   {
3879     { Bad_Opcode },
3880     { Bad_Opcode },
3881     { VEX_W_TABLE (VEX_W_0F61_P_2) },
3882   },
3883
3884   /* PREFIX_VEX_0F62 */
3885   {
3886     { Bad_Opcode },
3887     { Bad_Opcode },
3888     { VEX_W_TABLE (VEX_W_0F62_P_2) },
3889   },
3890
3891   /* PREFIX_VEX_0F63 */
3892   {
3893     { Bad_Opcode },
3894     { Bad_Opcode },
3895     { VEX_W_TABLE (VEX_W_0F63_P_2) },
3896   },
3897
3898   /* PREFIX_VEX_0F64 */
3899   {
3900     { Bad_Opcode },
3901     { Bad_Opcode },
3902     { VEX_W_TABLE (VEX_W_0F64_P_2) },
3903   },
3904
3905   /* PREFIX_VEX_0F65 */
3906   {
3907     { Bad_Opcode },
3908     { Bad_Opcode },
3909     { VEX_W_TABLE (VEX_W_0F65_P_2) },
3910   },
3911
3912   /* PREFIX_VEX_0F66 */
3913   {
3914     { Bad_Opcode },
3915     { Bad_Opcode },
3916     { VEX_W_TABLE (VEX_W_0F66_P_2) },
3917   },
3918
3919   /* PREFIX_VEX_0F67 */
3920   {
3921     { Bad_Opcode },
3922     { Bad_Opcode },
3923     { VEX_W_TABLE (VEX_W_0F67_P_2) },
3924   },
3925
3926   /* PREFIX_VEX_0F68 */
3927   {
3928     { Bad_Opcode },
3929     { Bad_Opcode },
3930     { VEX_W_TABLE (VEX_W_0F68_P_2) },
3931   },
3932
3933   /* PREFIX_VEX_0F69 */
3934   {
3935     { Bad_Opcode },
3936     { Bad_Opcode },
3937     { VEX_W_TABLE (VEX_W_0F69_P_2) },
3938   },
3939
3940   /* PREFIX_VEX_0F6A */
3941   {
3942     { Bad_Opcode },
3943     { Bad_Opcode },
3944     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
3945   },
3946
3947   /* PREFIX_VEX_0F6B */
3948   {
3949     { Bad_Opcode },
3950     { Bad_Opcode },
3951     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
3952   },
3953
3954   /* PREFIX_VEX_0F6C */
3955   {
3956     { Bad_Opcode },
3957     { Bad_Opcode },
3958     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
3959   },
3960
3961   /* PREFIX_VEX_0F6D */
3962   {
3963     { Bad_Opcode },
3964     { Bad_Opcode },
3965     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
3966   },
3967
3968   /* PREFIX_VEX_0F6E */
3969   {
3970     { Bad_Opcode },
3971     { Bad_Opcode },
3972     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3973   },
3974
3975   /* PREFIX_VEX_0F6F */
3976   {
3977     { Bad_Opcode },
3978     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3979     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3980   },
3981
3982   /* PREFIX_VEX_0F70 */
3983   {
3984     { Bad_Opcode },
3985     { VEX_W_TABLE (VEX_W_0F70_P_1) },
3986     { VEX_W_TABLE (VEX_W_0F70_P_2) },
3987     { VEX_W_TABLE (VEX_W_0F70_P_3) },
3988   },
3989
3990   /* PREFIX_VEX_0F71_REG_2 */
3991   {
3992     { Bad_Opcode },
3993     { Bad_Opcode },
3994     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
3995   },
3996
3997   /* PREFIX_VEX_0F71_REG_4 */
3998   {
3999     { Bad_Opcode },
4000     { Bad_Opcode },
4001     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4002   },
4003
4004   /* PREFIX_VEX_0F71_REG_6 */
4005   {
4006     { Bad_Opcode },
4007     { Bad_Opcode },
4008     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4009   },
4010
4011   /* PREFIX_VEX_0F72_REG_2 */
4012   {
4013     { Bad_Opcode },
4014     { Bad_Opcode },
4015     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4016   },
4017
4018   /* PREFIX_VEX_0F72_REG_4 */
4019   {
4020     { Bad_Opcode },
4021     { Bad_Opcode },
4022     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4023   },
4024
4025   /* PREFIX_VEX_0F72_REG_6 */
4026   {
4027     { Bad_Opcode },
4028     { Bad_Opcode },
4029     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4030   },
4031
4032   /* PREFIX_VEX_0F73_REG_2 */
4033   {
4034     { Bad_Opcode },
4035     { Bad_Opcode },
4036     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4037   },
4038
4039   /* PREFIX_VEX_0F73_REG_3 */
4040   {
4041     { Bad_Opcode },
4042     { Bad_Opcode },
4043     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4044   },
4045
4046   /* PREFIX_VEX_0F73_REG_6 */
4047   {
4048     { Bad_Opcode },
4049     { Bad_Opcode },
4050     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4051   },
4052
4053   /* PREFIX_VEX_0F73_REG_7 */
4054   {
4055     { Bad_Opcode },
4056     { Bad_Opcode },
4057     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4058   },
4059
4060   /* PREFIX_VEX_0F74 */
4061   {
4062     { Bad_Opcode },
4063     { Bad_Opcode },
4064     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4065   },
4066
4067   /* PREFIX_VEX_0F75 */
4068   {
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4072   },
4073
4074   /* PREFIX_VEX_0F76 */
4075   {
4076     { Bad_Opcode },
4077     { Bad_Opcode },
4078     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4079   },
4080
4081   /* PREFIX_VEX_0F77 */
4082   {
4083     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4084   },
4085
4086   /* PREFIX_VEX_0F7C */
4087   {
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4091     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4092   },
4093
4094   /* PREFIX_VEX_0F7D */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4099     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4100   },
4101
4102   /* PREFIX_VEX_0F7E */
4103   {
4104     { Bad_Opcode },
4105     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4106     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4107   },
4108
4109   /* PREFIX_VEX_0F7F */
4110   {
4111     { Bad_Opcode },
4112     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4113     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4114   },
4115
4116   /* PREFIX_VEX_0FC2 */
4117   {
4118     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4119     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4120     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4121     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4122   },
4123
4124   /* PREFIX_VEX_0FC4 */
4125   {
4126     { Bad_Opcode },
4127     { Bad_Opcode },
4128     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4129   },
4130
4131   /* PREFIX_VEX_0FC5 */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4136   },
4137
4138   /* PREFIX_VEX_0FD0 */
4139   {
4140     { Bad_Opcode },
4141     { Bad_Opcode },
4142     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4143     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4144   },
4145
4146   /* PREFIX_VEX_0FD1 */
4147   {
4148     { Bad_Opcode },
4149     { Bad_Opcode },
4150     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4151   },
4152
4153   /* PREFIX_VEX_0FD2 */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4158   },
4159
4160   /* PREFIX_VEX_0FD3 */
4161   {
4162     { Bad_Opcode },
4163     { Bad_Opcode },
4164     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4165   },
4166
4167   /* PREFIX_VEX_0FD4 */
4168   {
4169     { Bad_Opcode },
4170     { Bad_Opcode },
4171     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4172   },
4173
4174   /* PREFIX_VEX_0FD5 */
4175   {
4176     { Bad_Opcode },
4177     { Bad_Opcode },
4178     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4179   },
4180
4181   /* PREFIX_VEX_0FD6 */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4186   },
4187
4188   /* PREFIX_VEX_0FD7 */
4189   {
4190     { Bad_Opcode },
4191     { Bad_Opcode },
4192     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4193   },
4194
4195   /* PREFIX_VEX_0FD8 */
4196   {
4197     { Bad_Opcode },
4198     { Bad_Opcode },
4199     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4200   },
4201
4202   /* PREFIX_VEX_0FD9 */
4203   {
4204     { Bad_Opcode },
4205     { Bad_Opcode },
4206     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4207   },
4208
4209   /* PREFIX_VEX_0FDA */
4210   {
4211     { Bad_Opcode },
4212     { Bad_Opcode },
4213     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4214   },
4215
4216   /* PREFIX_VEX_0FDB */
4217   {
4218     { Bad_Opcode },
4219     { Bad_Opcode },
4220     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4221   },
4222
4223   /* PREFIX_VEX_0FDC */
4224   {
4225     { Bad_Opcode },
4226     { Bad_Opcode },
4227     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4228   },
4229
4230   /* PREFIX_VEX_0FDD */
4231   {
4232     { Bad_Opcode },
4233     { Bad_Opcode },
4234     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4235   },
4236
4237   /* PREFIX_VEX_0FDE */
4238   {
4239     { Bad_Opcode },
4240     { Bad_Opcode },
4241     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4242   },
4243
4244   /* PREFIX_VEX_0FDF */
4245   {
4246     { Bad_Opcode },
4247     { Bad_Opcode },
4248     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4249   },
4250
4251   /* PREFIX_VEX_0FE0 */
4252   {
4253     { Bad_Opcode },
4254     { Bad_Opcode },
4255     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4256   },
4257
4258   /* PREFIX_VEX_0FE1 */
4259   {
4260     { Bad_Opcode },
4261     { Bad_Opcode },
4262     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4263   },
4264
4265   /* PREFIX_VEX_0FE2 */
4266   {
4267     { Bad_Opcode },
4268     { Bad_Opcode },
4269     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4270   },
4271
4272   /* PREFIX_VEX_0FE3 */
4273   {
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4277   },
4278
4279   /* PREFIX_VEX_0FE4 */
4280   {
4281     { Bad_Opcode },
4282     { Bad_Opcode },
4283     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4284   },
4285
4286   /* PREFIX_VEX_0FE5 */
4287   {
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4291   },
4292
4293   /* PREFIX_VEX_0FE6 */
4294   {
4295     { Bad_Opcode },
4296     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4297     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4298     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4299   },
4300
4301   /* PREFIX_VEX_0FE7 */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4306   },
4307
4308   /* PREFIX_VEX_0FE8 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4313   },
4314
4315   /* PREFIX_VEX_0FE9 */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
4320   },
4321
4322   /* PREFIX_VEX_0FEA */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
4327   },
4328
4329   /* PREFIX_VEX_0FEB */
4330   {
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
4334   },
4335
4336   /* PREFIX_VEX_0FEC */
4337   {
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
4341   },
4342
4343   /* PREFIX_VEX_0FED */
4344   {
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { VEX_W_TABLE (VEX_W_0FED_P_2) },
4348   },
4349
4350   /* PREFIX_VEX_0FEE */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
4355   },
4356
4357   /* PREFIX_VEX_0FEF */
4358   {
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
4362   },
4363
4364   /* PREFIX_VEX_0FF0 */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4370   },
4371
4372   /* PREFIX_VEX_0FF1 */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
4377   },
4378
4379   /* PREFIX_VEX_0FF2 */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
4384   },
4385
4386   /* PREFIX_VEX_0FF3 */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
4391   },
4392
4393   /* PREFIX_VEX_0FF4 */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
4398   },
4399
4400   /* PREFIX_VEX_0FF5 */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
4405   },
4406
4407   /* PREFIX_VEX_0FF6 */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
4412   },
4413
4414   /* PREFIX_VEX_0FF7 */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4419   },
4420
4421   /* PREFIX_VEX_0FF8 */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
4426   },
4427
4428   /* PREFIX_VEX_0FF9 */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
4433   },
4434
4435   /* PREFIX_VEX_0FFA */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
4440   },
4441
4442   /* PREFIX_VEX_0FFB */
4443   {
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
4447   },
4448
4449   /* PREFIX_VEX_0FFC */
4450   {
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
4454   },
4455
4456   /* PREFIX_VEX_0FFD */
4457   {
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
4461   },
4462
4463   /* PREFIX_VEX_0FFE */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
4468   },
4469
4470   /* PREFIX_VEX_0F3800 */
4471   {
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
4475   },
4476
4477   /* PREFIX_VEX_0F3801 */
4478   {
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
4482   },
4483
4484   /* PREFIX_VEX_0F3802 */
4485   {
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
4489   },
4490
4491   /* PREFIX_VEX_0F3803 */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
4496   },
4497
4498   /* PREFIX_VEX_0F3804 */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
4503   },
4504
4505   /* PREFIX_VEX_0F3805 */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
4510   },
4511
4512   /* PREFIX_VEX_0F3806 */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
4517   },
4518
4519   /* PREFIX_VEX_0F3807 */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
4524   },
4525
4526   /* PREFIX_VEX_0F3808 */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
4531   },
4532
4533   /* PREFIX_VEX_0F3809 */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
4538   },
4539
4540   /* PREFIX_VEX_0F380A */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
4545   },
4546
4547   /* PREFIX_VEX_0F380B */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
4552   },
4553
4554   /* PREFIX_VEX_0F380C */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4559   },
4560
4561   /* PREFIX_VEX_0F380D */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4566   },
4567
4568   /* PREFIX_VEX_0F380E */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4573   },
4574
4575   /* PREFIX_VEX_0F380F */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4580   },
4581
4582   /* PREFIX_VEX_0F3813 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "vcvtph2ps", { XM, EXxmmq } },
4587   },
4588
4589   /* PREFIX_VEX_0F3816 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
4594   },
4595
4596   /* PREFIX_VEX_0F3817 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4601   },
4602
4603   /* PREFIX_VEX_0F3818 */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
4608   },
4609
4610   /* PREFIX_VEX_0F3819 */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
4615   },
4616
4617   /* PREFIX_VEX_0F381A */
4618   {
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4622   },
4623
4624   /* PREFIX_VEX_0F381C */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
4629   },
4630
4631   /* PREFIX_VEX_0F381D */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
4636   },
4637
4638   /* PREFIX_VEX_0F381E */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
4643   },
4644
4645   /* PREFIX_VEX_0F3820 */
4646   {
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
4650   },
4651
4652   /* PREFIX_VEX_0F3821 */
4653   {
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
4657   },
4658
4659   /* PREFIX_VEX_0F3822 */
4660   {
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
4664   },
4665
4666   /* PREFIX_VEX_0F3823 */
4667   {
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
4671   },
4672
4673   /* PREFIX_VEX_0F3824 */
4674   {
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
4678   },
4679
4680   /* PREFIX_VEX_0F3825 */
4681   {
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
4685   },
4686
4687   /* PREFIX_VEX_0F3828 */
4688   {
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
4692   },
4693
4694   /* PREFIX_VEX_0F3829 */
4695   {
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
4699   },
4700
4701   /* PREFIX_VEX_0F382A */
4702   {
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4706   },
4707
4708   /* PREFIX_VEX_0F382B */
4709   {
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
4713   },
4714
4715   /* PREFIX_VEX_0F382C */
4716   {
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4720   },
4721
4722   /* PREFIX_VEX_0F382D */
4723   {
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4727   },
4728
4729   /* PREFIX_VEX_0F382E */
4730   {
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4734   },
4735
4736   /* PREFIX_VEX_0F382F */
4737   {
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4741   },
4742
4743   /* PREFIX_VEX_0F3830 */
4744   {
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
4748   },
4749
4750   /* PREFIX_VEX_0F3831 */
4751   {
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
4755   },
4756
4757   /* PREFIX_VEX_0F3832 */
4758   {
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
4762   },
4763
4764   /* PREFIX_VEX_0F3833 */
4765   {
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
4769   },
4770
4771   /* PREFIX_VEX_0F3834 */
4772   {
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
4776   },
4777
4778   /* PREFIX_VEX_0F3835 */
4779   {
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
4783   },
4784
4785   /* PREFIX_VEX_0F3836 */
4786   {
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
4790   },
4791
4792   /* PREFIX_VEX_0F3837 */
4793   {
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
4797   },
4798
4799   /* PREFIX_VEX_0F3838 */
4800   {
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
4804   },
4805
4806   /* PREFIX_VEX_0F3839 */
4807   {
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
4811   },
4812
4813   /* PREFIX_VEX_0F383A */
4814   {
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
4818   },
4819
4820   /* PREFIX_VEX_0F383B */
4821   {
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
4825   },
4826
4827   /* PREFIX_VEX_0F383C */
4828   {
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
4832   },
4833
4834   /* PREFIX_VEX_0F383D */
4835   {
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
4839   },
4840
4841   /* PREFIX_VEX_0F383E */
4842   {
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
4846   },
4847
4848   /* PREFIX_VEX_0F383F */
4849   {
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
4853   },
4854
4855   /* PREFIX_VEX_0F3840 */
4856   {
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
4860   },
4861
4862   /* PREFIX_VEX_0F3841 */
4863   {
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4867   },
4868
4869   /* PREFIX_VEX_0F3845 */
4870   {
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { "vpsrlv%LW", { XM, Vex, EXx } },
4874   },
4875
4876   /* PREFIX_VEX_0F3846 */
4877   {
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
4881   },
4882
4883   /* PREFIX_VEX_0F3847 */
4884   {
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { "vpsllv%LW", { XM, Vex, EXx } },
4888   },
4889
4890   /* PREFIX_VEX_0F3858 */
4891   {
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
4895   },
4896
4897   /* PREFIX_VEX_0F3859 */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
4902   },
4903
4904   /* PREFIX_VEX_0F385A */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
4909   },
4910
4911   /* PREFIX_VEX_0F3878 */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
4916   },
4917
4918   /* PREFIX_VEX_0F3879 */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
4923   },
4924
4925   /* PREFIX_VEX_0F388C */
4926   {
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
4930   },
4931
4932   /* PREFIX_VEX_0F388E */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
4937   },
4938
4939   /* PREFIX_VEX_0F3890 */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
4944   },
4945
4946   /* PREFIX_VEX_0F3891 */
4947   {
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4951   },
4952
4953   /* PREFIX_VEX_0F3892 */
4954   {
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
4958   },
4959
4960   /* PREFIX_VEX_0F3893 */
4961   {
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4965   },
4966
4967   /* PREFIX_VEX_0F3896 */
4968   {
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4972   },
4973
4974   /* PREFIX_VEX_0F3897 */
4975   {
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4979   },
4980
4981   /* PREFIX_VEX_0F3898 */
4982   {
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { "vfmadd132p%XW", { XM, Vex, EXx } },
4986   },
4987
4988   /* PREFIX_VEX_0F3899 */
4989   {
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4993   },
4994
4995   /* PREFIX_VEX_0F389A */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { "vfmsub132p%XW", { XM, Vex, EXx } },
5000   },
5001
5002   /* PREFIX_VEX_0F389B */
5003   {
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5007   },
5008
5009   /* PREFIX_VEX_0F389C */
5010   {
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5014   },
5015
5016   /* PREFIX_VEX_0F389D */
5017   {
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5021   },
5022
5023   /* PREFIX_VEX_0F389E */
5024   {
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5028   },
5029
5030   /* PREFIX_VEX_0F389F */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5035   },
5036
5037   /* PREFIX_VEX_0F38A6 */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5042     { Bad_Opcode },
5043   },
5044
5045   /* PREFIX_VEX_0F38A7 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5050   },
5051
5052   /* PREFIX_VEX_0F38A8 */
5053   {
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { "vfmadd213p%XW", { XM, Vex, EXx } },
5057   },
5058
5059   /* PREFIX_VEX_0F38A9 */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5064   },
5065
5066   /* PREFIX_VEX_0F38AA */
5067   {
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { "vfmsub213p%XW", { XM, Vex, EXx } },
5071   },
5072
5073   /* PREFIX_VEX_0F38AB */
5074   {
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5078   },
5079
5080   /* PREFIX_VEX_0F38AC */
5081   {
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5085   },
5086
5087   /* PREFIX_VEX_0F38AD */
5088   {
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5092   },
5093
5094   /* PREFIX_VEX_0F38AE */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5099   },
5100
5101   /* PREFIX_VEX_0F38AF */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5106   },
5107
5108   /* PREFIX_VEX_0F38B6 */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5113   },
5114
5115   /* PREFIX_VEX_0F38B7 */
5116   {
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5120   },
5121
5122   /* PREFIX_VEX_0F38B8 */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { "vfmadd231p%XW", { XM, Vex, EXx } },
5127   },
5128
5129   /* PREFIX_VEX_0F38B9 */
5130   {
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5134   },
5135
5136   /* PREFIX_VEX_0F38BA */
5137   {
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { "vfmsub231p%XW", { XM, Vex, EXx } },
5141   },
5142
5143   /* PREFIX_VEX_0F38BB */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5148   },
5149
5150   /* PREFIX_VEX_0F38BC */
5151   {
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5155   },
5156
5157   /* PREFIX_VEX_0F38BD */
5158   {
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5162   },
5163
5164   /* PREFIX_VEX_0F38BE */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5169   },
5170
5171   /* PREFIX_VEX_0F38BF */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5176   },
5177
5178   /* PREFIX_VEX_0F38DB */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5183   },
5184
5185   /* PREFIX_VEX_0F38DC */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5190   },
5191
5192   /* PREFIX_VEX_0F38DD */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5197   },
5198
5199   /* PREFIX_VEX_0F38DE */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5204   },
5205
5206   /* PREFIX_VEX_0F38DF */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5211   },
5212
5213   /* PREFIX_VEX_0F38F2 */
5214   {
5215     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5216   },
5217
5218   /* PREFIX_VEX_0F38F3_REG_1 */
5219   {
5220     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5221   },
5222
5223   /* PREFIX_VEX_0F38F3_REG_2 */
5224   {
5225     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5226   },
5227
5228   /* PREFIX_VEX_0F38F3_REG_3 */
5229   {
5230     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5231   },
5232
5233   /* PREFIX_VEX_0F38F5 */
5234   {
5235     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5236     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5237     { Bad_Opcode },
5238     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5239   },
5240
5241   /* PREFIX_VEX_0F38F6 */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5247   },
5248
5249   /* PREFIX_VEX_0F38F7 */
5250   {
5251     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5252     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5253     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5254     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5255   },
5256
5257   /* PREFIX_VEX_0F3A00 */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5262   },
5263
5264   /* PREFIX_VEX_0F3A01 */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5269   },
5270
5271   /* PREFIX_VEX_0F3A02 */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5276   },
5277
5278   /* PREFIX_VEX_0F3A04 */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5283   },
5284
5285   /* PREFIX_VEX_0F3A05 */
5286   {
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5290   },
5291
5292   /* PREFIX_VEX_0F3A06 */
5293   {
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5297   },
5298
5299   /* PREFIX_VEX_0F3A08 */
5300   {
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5304   },
5305
5306   /* PREFIX_VEX_0F3A09 */
5307   {
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5311   },
5312
5313   /* PREFIX_VEX_0F3A0A */
5314   {
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5318   },
5319
5320   /* PREFIX_VEX_0F3A0B */
5321   {
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5325   },
5326
5327   /* PREFIX_VEX_0F3A0C */
5328   {
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5332   },
5333
5334   /* PREFIX_VEX_0F3A0D */
5335   {
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5339   },
5340
5341   /* PREFIX_VEX_0F3A0E */
5342   {
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
5346   },
5347
5348   /* PREFIX_VEX_0F3A0F */
5349   {
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
5353   },
5354
5355   /* PREFIX_VEX_0F3A14 */
5356   {
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5360   },
5361
5362   /* PREFIX_VEX_0F3A15 */
5363   {
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5367   },
5368
5369   /* PREFIX_VEX_0F3A16 */
5370   {
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5374   },
5375
5376   /* PREFIX_VEX_0F3A17 */
5377   {
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5381   },
5382
5383   /* PREFIX_VEX_0F3A18 */
5384   {
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5388   },
5389
5390   /* PREFIX_VEX_0F3A19 */
5391   {
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5395   },
5396
5397   /* PREFIX_VEX_0F3A1D */
5398   {
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { "vcvtps2ph", { EXxmmq, XM, Ib } },
5402   },
5403
5404   /* PREFIX_VEX_0F3A20 */
5405   {
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5409   },
5410
5411   /* PREFIX_VEX_0F3A21 */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5416   },
5417
5418   /* PREFIX_VEX_0F3A22 */
5419   {
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5423   },
5424
5425   /* PREFIX_VEX_0F3A38 */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
5430   },
5431
5432   /* PREFIX_VEX_0F3A39 */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
5437   },
5438
5439   /* PREFIX_VEX_0F3A40 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5444   },
5445
5446   /* PREFIX_VEX_0F3A41 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5451   },
5452
5453   /* PREFIX_VEX_0F3A42 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
5458   },
5459
5460   /* PREFIX_VEX_0F3A44 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5465   },
5466
5467   /* PREFIX_VEX_0F3A46 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
5472   },
5473
5474   /* PREFIX_VEX_0F3A48 */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5479   },
5480
5481   /* PREFIX_VEX_0F3A49 */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5486   },
5487
5488   /* PREFIX_VEX_0F3A4A */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5493   },
5494
5495   /* PREFIX_VEX_0F3A4B */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5500   },
5501
5502   /* PREFIX_VEX_0F3A4C */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
5507   },
5508
5509   /* PREFIX_VEX_0F3A5C */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5514   },
5515
5516   /* PREFIX_VEX_0F3A5D */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5521   },
5522
5523   /* PREFIX_VEX_0F3A5E */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5528   },
5529
5530   /* PREFIX_VEX_0F3A5F */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5535   },
5536
5537   /* PREFIX_VEX_0F3A60 */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5542     { Bad_Opcode },
5543   },
5544
5545   /* PREFIX_VEX_0F3A61 */
5546   {
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5550   },
5551
5552   /* PREFIX_VEX_0F3A62 */
5553   {
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5557   },
5558
5559   /* PREFIX_VEX_0F3A63 */
5560   {
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5564   },
5565
5566   /* PREFIX_VEX_0F3A68 */
5567   {
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5571   },
5572
5573   /* PREFIX_VEX_0F3A69 */
5574   {
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5578   },
5579
5580   /* PREFIX_VEX_0F3A6A */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5585   },
5586
5587   /* PREFIX_VEX_0F3A6B */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5592   },
5593
5594   /* PREFIX_VEX_0F3A6C */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5599   },
5600
5601   /* PREFIX_VEX_0F3A6D */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5606   },
5607
5608   /* PREFIX_VEX_0F3A6E */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5613   },
5614
5615   /* PREFIX_VEX_0F3A6F */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5620   },
5621
5622   /* PREFIX_VEX_0F3A78 */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5627   },
5628
5629   /* PREFIX_VEX_0F3A79 */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5634   },
5635
5636   /* PREFIX_VEX_0F3A7A */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5641   },
5642
5643   /* PREFIX_VEX_0F3A7B */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5648   },
5649
5650   /* PREFIX_VEX_0F3A7C */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5655     { Bad_Opcode },
5656   },
5657
5658   /* PREFIX_VEX_0F3A7D */
5659   {
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5663   },
5664
5665   /* PREFIX_VEX_0F3A7E */
5666   {
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5670   },
5671
5672   /* PREFIX_VEX_0F3A7F */
5673   {
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5677   },
5678
5679   /* PREFIX_VEX_0F3ADF */
5680   {
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5684   },
5685
5686   /* PREFIX_VEX_0F3AF0 */
5687   {
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
5692   },
5693 };
5694
5695 static const struct dis386 x86_64_table[][2] = {
5696   /* X86_64_06 */
5697   {
5698     { "pushP", { es } },
5699   },
5700
5701   /* X86_64_07 */
5702   {
5703     { "popP", { es } },
5704   },
5705
5706   /* X86_64_0D */
5707   {
5708     { "pushP", { cs } },
5709   },
5710
5711   /* X86_64_16 */
5712   {
5713     { "pushP", { ss } },
5714   },
5715
5716   /* X86_64_17 */
5717   {
5718     { "popP", { ss } },
5719   },
5720
5721   /* X86_64_1E */
5722   {
5723     { "pushP", { ds } },
5724   },
5725
5726   /* X86_64_1F */
5727   {
5728     { "popP", { ds } },
5729   },
5730
5731   /* X86_64_27 */
5732   {
5733     { "daa", { XX } },
5734   },
5735
5736   /* X86_64_2F */
5737   {
5738     { "das", { XX } },
5739   },
5740
5741   /* X86_64_37 */
5742   {
5743     { "aaa", { XX } },
5744   },
5745
5746   /* X86_64_3F */
5747   {
5748     { "aas", { XX } },
5749   },
5750
5751   /* X86_64_60 */
5752   {
5753     { "pushaP", { XX } },
5754   },
5755
5756   /* X86_64_61 */
5757   {
5758     { "popaP", { XX } },
5759   },
5760
5761   /* X86_64_62 */
5762   {
5763     { MOD_TABLE (MOD_62_32BIT) },
5764   },
5765
5766   /* X86_64_63 */
5767   {
5768     { "arpl", { Ew, Gw } },
5769     { "movs{lq|xd}", { Gv, Ed } },
5770   },
5771
5772   /* X86_64_6D */
5773   {
5774     { "ins{R|}", { Yzr, indirDX } },
5775     { "ins{G|}", { Yzr, indirDX } },
5776   },
5777
5778   /* X86_64_6F */
5779   {
5780     { "outs{R|}", { indirDXr, Xz } },
5781     { "outs{G|}", { indirDXr, Xz } },
5782   },
5783
5784   /* X86_64_9A */
5785   {
5786     { "Jcall{T|}", { Ap } },
5787   },
5788
5789   /* X86_64_C4 */
5790   {
5791     { MOD_TABLE (MOD_C4_32BIT) },
5792     { VEX_C4_TABLE (VEX_0F) },
5793   },
5794
5795   /* X86_64_C5 */
5796   {
5797     { MOD_TABLE (MOD_C5_32BIT) },
5798     { VEX_C5_TABLE (VEX_0F) },
5799   },
5800
5801   /* X86_64_CE */
5802   {
5803     { "into", { XX } },
5804   },
5805
5806   /* X86_64_D4 */
5807   {
5808     { "aam", { Ib } },
5809   },
5810
5811   /* X86_64_D5 */
5812   {
5813     { "aad", { Ib } },
5814   },
5815
5816   /* X86_64_EA */
5817   {
5818     { "Jjmp{T|}", { Ap } },
5819   },
5820
5821   /* X86_64_0F01_REG_0 */
5822   {
5823     { "sgdt{Q|IQ}", { M } },
5824     { "sgdt", { M } },
5825   },
5826
5827   /* X86_64_0F01_REG_1 */
5828   {
5829     { "sidt{Q|IQ}", { M } },
5830     { "sidt", { M } },
5831   },
5832
5833   /* X86_64_0F01_REG_2 */
5834   {
5835     { "lgdt{Q|Q}", { M } },
5836     { "lgdt", { M } },
5837   },
5838
5839   /* X86_64_0F01_REG_3 */
5840   {
5841     { "lidt{Q|Q}", { M } },
5842     { "lidt", { M } },
5843   },
5844 };
5845
5846 static const struct dis386 three_byte_table[][256] = {
5847
5848   /* THREE_BYTE_0F38 */
5849   {
5850     /* 00 */
5851     { "pshufb",         { MX, EM } },
5852     { "phaddw",         { MX, EM } },
5853     { "phaddd",         { MX, EM } },
5854     { "phaddsw",        { MX, EM } },
5855     { "pmaddubsw",      { MX, EM } },
5856     { "phsubw",         { MX, EM } },
5857     { "phsubd",         { MX, EM } },
5858     { "phsubsw",        { MX, EM } },
5859     /* 08 */
5860     { "psignb",         { MX, EM } },
5861     { "psignw",         { MX, EM } },
5862     { "psignd",         { MX, EM } },
5863     { "pmulhrsw",       { MX, EM } },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     /* 10 */
5869     { PREFIX_TABLE (PREFIX_0F3810) },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { PREFIX_TABLE (PREFIX_0F3814) },
5874     { PREFIX_TABLE (PREFIX_0F3815) },
5875     { Bad_Opcode },
5876     { PREFIX_TABLE (PREFIX_0F3817) },
5877     /* 18 */
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { "pabsb",          { MX, EM } },
5883     { "pabsw",          { MX, EM } },
5884     { "pabsd",          { MX, EM } },
5885     { Bad_Opcode },
5886     /* 20 */
5887     { PREFIX_TABLE (PREFIX_0F3820) },
5888     { PREFIX_TABLE (PREFIX_0F3821) },
5889     { PREFIX_TABLE (PREFIX_0F3822) },
5890     { PREFIX_TABLE (PREFIX_0F3823) },
5891     { PREFIX_TABLE (PREFIX_0F3824) },
5892     { PREFIX_TABLE (PREFIX_0F3825) },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     /* 28 */
5896     { PREFIX_TABLE (PREFIX_0F3828) },
5897     { PREFIX_TABLE (PREFIX_0F3829) },
5898     { PREFIX_TABLE (PREFIX_0F382A) },
5899     { PREFIX_TABLE (PREFIX_0F382B) },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     /* 30 */
5905     { PREFIX_TABLE (PREFIX_0F3830) },
5906     { PREFIX_TABLE (PREFIX_0F3831) },
5907     { PREFIX_TABLE (PREFIX_0F3832) },
5908     { PREFIX_TABLE (PREFIX_0F3833) },
5909     { PREFIX_TABLE (PREFIX_0F3834) },
5910     { PREFIX_TABLE (PREFIX_0F3835) },
5911     { Bad_Opcode },
5912     { PREFIX_TABLE (PREFIX_0F3837) },
5913     /* 38 */
5914     { PREFIX_TABLE (PREFIX_0F3838) },
5915     { PREFIX_TABLE (PREFIX_0F3839) },
5916     { PREFIX_TABLE (PREFIX_0F383A) },
5917     { PREFIX_TABLE (PREFIX_0F383B) },
5918     { PREFIX_TABLE (PREFIX_0F383C) },
5919     { PREFIX_TABLE (PREFIX_0F383D) },
5920     { PREFIX_TABLE (PREFIX_0F383E) },
5921     { PREFIX_TABLE (PREFIX_0F383F) },
5922     /* 40 */
5923     { PREFIX_TABLE (PREFIX_0F3840) },
5924     { PREFIX_TABLE (PREFIX_0F3841) },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     /* 48 */
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     /* 50 */
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     /* 58 */
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     /* 60 */
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     /* 68 */
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     /* 70 */
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     /* 78 */
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     /* 80 */
5995     { PREFIX_TABLE (PREFIX_0F3880) },
5996     { PREFIX_TABLE (PREFIX_0F3881) },
5997     { PREFIX_TABLE (PREFIX_0F3882) },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     /* 88 */
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     /* 90 */
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     /* 98 */
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     /* a0 */
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     /* a8 */
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     /* b0 */
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     /* b8 */
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     /* c0 */
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     /* c8 */
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     /* d0 */
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     /* d8 */
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { PREFIX_TABLE (PREFIX_0F38DB) },
6098     { PREFIX_TABLE (PREFIX_0F38DC) },
6099     { PREFIX_TABLE (PREFIX_0F38DD) },
6100     { PREFIX_TABLE (PREFIX_0F38DE) },
6101     { PREFIX_TABLE (PREFIX_0F38DF) },
6102     /* e0 */
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     /* e8 */
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     /* f0 */
6121     { PREFIX_TABLE (PREFIX_0F38F0) },
6122     { PREFIX_TABLE (PREFIX_0F38F1) },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { PREFIX_TABLE (PREFIX_0F38F6) },
6128     { Bad_Opcode },
6129     /* f8 */
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138   },
6139   /* THREE_BYTE_0F3A */
6140   {
6141     /* 00 */
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     /* 08 */
6151     { PREFIX_TABLE (PREFIX_0F3A08) },
6152     { PREFIX_TABLE (PREFIX_0F3A09) },
6153     { PREFIX_TABLE (PREFIX_0F3A0A) },
6154     { PREFIX_TABLE (PREFIX_0F3A0B) },
6155     { PREFIX_TABLE (PREFIX_0F3A0C) },
6156     { PREFIX_TABLE (PREFIX_0F3A0D) },
6157     { PREFIX_TABLE (PREFIX_0F3A0E) },
6158     { "palignr",        { MX, EM, Ib } },
6159     /* 10 */
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { PREFIX_TABLE (PREFIX_0F3A14) },
6165     { PREFIX_TABLE (PREFIX_0F3A15) },
6166     { PREFIX_TABLE (PREFIX_0F3A16) },
6167     { PREFIX_TABLE (PREFIX_0F3A17) },
6168     /* 18 */
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     /* 20 */
6178     { PREFIX_TABLE (PREFIX_0F3A20) },
6179     { PREFIX_TABLE (PREFIX_0F3A21) },
6180     { PREFIX_TABLE (PREFIX_0F3A22) },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     /* 28 */
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     /* 30 */
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     /* 38 */
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     /* 40 */
6214     { PREFIX_TABLE (PREFIX_0F3A40) },
6215     { PREFIX_TABLE (PREFIX_0F3A41) },
6216     { PREFIX_TABLE (PREFIX_0F3A42) },
6217     { Bad_Opcode },
6218     { PREFIX_TABLE (PREFIX_0F3A44) },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     /* 48 */
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     /* 50 */
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     /* 58 */
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     /* 60 */
6250     { PREFIX_TABLE (PREFIX_0F3A60) },
6251     { PREFIX_TABLE (PREFIX_0F3A61) },
6252     { PREFIX_TABLE (PREFIX_0F3A62) },
6253     { PREFIX_TABLE (PREFIX_0F3A63) },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     /* 68 */
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     /* 70 */
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     /* 78 */
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     /* 80 */
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     /* 88 */
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     /* 90 */
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     /* 98 */
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     /* a0 */
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     /* a8 */
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     /* b0 */
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     /* b8 */
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     /* c0 */
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     /* c8 */
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     /* d0 */
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     /* d8 */
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { PREFIX_TABLE (PREFIX_0F3ADF) },
6393     /* e0 */
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     /* e8 */
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     /* f0 */
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     /* f8 */
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429   },
6430
6431   /* THREE_BYTE_0F7A */
6432   {
6433     /* 00 */
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     /* 08 */
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     /* 10 */
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     /* 18 */
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     /* 20 */
6470     { "ptest",          { XX } },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     /* 28 */
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     /* 30 */
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     /* 38 */
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     /* 40 */
6506     { Bad_Opcode },
6507     { "phaddbw",        { XM, EXq } },
6508     { "phaddbd",        { XM, EXq } },
6509     { "phaddbq",        { XM, EXq } },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { "phaddwd",        { XM, EXq } },
6513     { "phaddwq",        { XM, EXq } },
6514     /* 48 */
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { "phadddq",        { XM, EXq } },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     /* 50 */
6524     { Bad_Opcode },
6525     { "phaddubw",       { XM, EXq } },
6526     { "phaddubd",       { XM, EXq } },
6527     { "phaddubq",       { XM, EXq } },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { "phadduwd",       { XM, EXq } },
6531     { "phadduwq",       { XM, EXq } },
6532     /* 58 */
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { "phaddudq",       { XM, EXq } },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     /* 60 */
6542     { Bad_Opcode },
6543     { "phsubbw",        { XM, EXq } },
6544     { "phsubbd",        { XM, EXq } },
6545     { "phsubbq",        { XM, EXq } },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     /* 68 */
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     /* 70 */
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     /* 78 */
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     /* 80 */
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     /* 88 */
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     /* 90 */
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     /* 98 */
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     /* a0 */
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     /* a8 */
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     /* b0 */
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     /* b8 */
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     /* c0 */
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     /* c8 */
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     /* d0 */
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     /* d8 */
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     /* e0 */
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     /* e8 */
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     /* f0 */
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     /* f8 */
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721   },
6722 };
6723
6724 static const struct dis386 xop_table[][256] = {
6725   /* XOP_08 */
6726   {
6727     /* 00 */
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     /* 08 */
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     /* 10 */
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     /* 18 */
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     /* 20 */
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     /* 28 */
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     /* 30 */
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     /* 38 */
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     /* 40 */
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     /* 48 */
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     /* 50 */
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     /* 58 */
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     /* 60 */
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     /* 68 */
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     /* 70 */
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     /* 78 */
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     /* 80 */
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6878     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6879     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6880     /* 88 */
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6888     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6889     /* 90 */
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6896     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6897     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6898     /* 98 */
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6906     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6907     /* a0 */
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6911     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6915     { Bad_Opcode },
6916     /* a8 */
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     /* b0 */
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6933     { Bad_Opcode },
6934     /* b8 */
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     /* c0 */
6944     { "vprotb",         { XM, Vex_2src_1, Ib } },
6945     { "vprotw",         { XM, Vex_2src_1, Ib } },
6946     { "vprotd",         { XM, Vex_2src_1, Ib } },
6947     { "vprotq",         { XM, Vex_2src_1, Ib } },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* c8 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
6958     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
6959     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
6960     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
6961     /* d0 */
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* d8 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* e0 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* e8 */
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
6994     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
6995     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
6996     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
6997     /* f0 */
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* f8 */
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015   },
7016   /* XOP_09 */
7017   {
7018     /* 00 */
7019     { Bad_Opcode },
7020     { REG_TABLE (REG_XOP_TBM_01) },
7021     { REG_TABLE (REG_XOP_TBM_02) },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     /* 08 */
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     /* 10 */
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { REG_TABLE (REG_XOP_LWPCB) },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     /* 18 */
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     /* 20 */
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     /* 28 */
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     /* 30 */
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     /* 38 */
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     /* 40 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* 48 */
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     /* 50 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     /* 58 */
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* 60 */
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* 68 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* 70 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* 78 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* 80 */
7163     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7164     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7165     { "vfrczss",        { XM, EXd } },
7166     { "vfrczsd",        { XM, EXq } },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* 88 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* 90 */
7181     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7182     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7183     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7184     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7185     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7186     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7187     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7188     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7189     /* 98 */
7190     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7191     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7192     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7193     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* a0 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* a8 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* b0 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* b8 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* c0 */
7235     { Bad_Opcode },
7236     { "vphaddbw",       { XM, EXxmm } },
7237     { "vphaddbd",       { XM, EXxmm } },
7238     { "vphaddbq",       { XM, EXxmm } },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { "vphaddwd",       { XM, EXxmm } },
7242     { "vphaddwq",       { XM, EXxmm } },
7243     /* c8 */
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { "vphadddq",       { XM, EXxmm } },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* d0 */
7253     { Bad_Opcode },
7254     { "vphaddubw",      { XM, EXxmm } },
7255     { "vphaddubd",      { XM, EXxmm } },
7256     { "vphaddubq",      { XM, EXxmm } },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { "vphadduwd",      { XM, EXxmm } },
7260     { "vphadduwq",      { XM, EXxmm } },
7261     /* d8 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { "vphaddudq",      { XM, EXxmm } },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* e0 */
7271     { Bad_Opcode },
7272     { "vphsubbw",       { XM, EXxmm } },
7273     { "vphsubwd",       { XM, EXxmm } },
7274     { "vphsubdq",       { XM, EXxmm } },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* e8 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* f0 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* f8 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306   },
7307   /* XOP_0A */
7308   {
7309     /* 00 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     /* 08 */
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 10 */
7328     { "bextr",  { Gv, Ev, Iq } },
7329     { Bad_Opcode },
7330     { REG_TABLE (REG_XOP_LWP) },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 18 */
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 20 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* 28 */
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* 30 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     /* 38 */
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* 40 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* 48 */
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     /* 50 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* 58 */
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     /* 60 */
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     /* 68 */
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     /* 70 */
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     /* 78 */
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     /* 80 */
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     /* 88 */
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     /* 90 */
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     /* 98 */
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     /* a0 */
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     /* a8 */
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     /* b0 */
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     /* b8 */
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     /* c0 */
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     /* c8 */
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     /* d0 */
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     /* d8 */
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     /* e0 */
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     /* e8 */
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     /* f0 */
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     /* f8 */
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597   },
7598 };
7599
7600 static const struct dis386 vex_table[][256] = {
7601   /* VEX_0F */
7602   {
7603     /* 00 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* 08 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* 10 */
7622     { PREFIX_TABLE (PREFIX_VEX_0F10) },
7623     { PREFIX_TABLE (PREFIX_VEX_0F11) },
7624     { PREFIX_TABLE (PREFIX_VEX_0F12) },
7625     { MOD_TABLE (MOD_VEX_0F13) },
7626     { VEX_W_TABLE (VEX_W_0F14) },
7627     { VEX_W_TABLE (VEX_W_0F15) },
7628     { PREFIX_TABLE (PREFIX_VEX_0F16) },
7629     { MOD_TABLE (MOD_VEX_0F17) },
7630     /* 18 */
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     /* 20 */
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     /* 28 */
7649     { VEX_W_TABLE (VEX_W_0F28) },
7650     { VEX_W_TABLE (VEX_W_0F29) },
7651     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7652     { MOD_TABLE (MOD_VEX_0F2B) },
7653     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7654     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7655     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7656     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7657     /* 30 */
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     /* 38 */
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     /* 40 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     /* 48 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     /* 50 */
7694     { MOD_TABLE (MOD_VEX_0F50) },
7695     { PREFIX_TABLE (PREFIX_VEX_0F51) },
7696     { PREFIX_TABLE (PREFIX_VEX_0F52) },
7697     { PREFIX_TABLE (PREFIX_VEX_0F53) },
7698     { "vandpX",         { XM, Vex, EXx } },
7699     { "vandnpX",        { XM, Vex, EXx } },
7700     { "vorpX",          { XM, Vex, EXx } },
7701     { "vxorpX",         { XM, Vex, EXx } },
7702     /* 58 */
7703     { PREFIX_TABLE (PREFIX_VEX_0F58) },
7704     { PREFIX_TABLE (PREFIX_VEX_0F59) },
7705     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7706     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7707     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7708     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7709     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7710     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7711     /* 60 */
7712     { PREFIX_TABLE (PREFIX_VEX_0F60) },
7713     { PREFIX_TABLE (PREFIX_VEX_0F61) },
7714     { PREFIX_TABLE (PREFIX_VEX_0F62) },
7715     { PREFIX_TABLE (PREFIX_VEX_0F63) },
7716     { PREFIX_TABLE (PREFIX_VEX_0F64) },
7717     { PREFIX_TABLE (PREFIX_VEX_0F65) },
7718     { PREFIX_TABLE (PREFIX_VEX_0F66) },
7719     { PREFIX_TABLE (PREFIX_VEX_0F67) },
7720     /* 68 */
7721     { PREFIX_TABLE (PREFIX_VEX_0F68) },
7722     { PREFIX_TABLE (PREFIX_VEX_0F69) },
7723     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7724     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7725     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7726     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7727     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7728     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7729     /* 70 */
7730     { PREFIX_TABLE (PREFIX_VEX_0F70) },
7731     { REG_TABLE (REG_VEX_0F71) },
7732     { REG_TABLE (REG_VEX_0F72) },
7733     { REG_TABLE (REG_VEX_0F73) },
7734     { PREFIX_TABLE (PREFIX_VEX_0F74) },
7735     { PREFIX_TABLE (PREFIX_VEX_0F75) },
7736     { PREFIX_TABLE (PREFIX_VEX_0F76) },
7737     { PREFIX_TABLE (PREFIX_VEX_0F77) },
7738     /* 78 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7744     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7745     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7746     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7747     /* 80 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* 88 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     /* 90 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* 98 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* a0 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* a8 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { REG_TABLE (REG_VEX_0FAE) },
7800     { Bad_Opcode },
7801     /* b0 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* b8 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* c0 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7823     { Bad_Opcode },
7824     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7825     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7826     { "vshufpX",        { XM, Vex, EXx, Ib } },
7827     { Bad_Opcode },
7828     /* c8 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* d0 */
7838     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7839     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7840     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7841     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7842     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7843     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7844     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7845     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7846     /* d8 */
7847     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7848     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7849     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7850     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7851     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7852     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7853     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7854     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7855     /* e0 */
7856     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7857     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7858     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7859     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7860     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7861     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7862     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7863     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7864     /* e8 */
7865     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7866     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7867     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7868     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7869     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7870     { PREFIX_TABLE (PREFIX_VEX_0FED) },
7871     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7872     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7873     /* f0 */
7874     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7875     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7876     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7877     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7878     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7879     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7880     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7881     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7882     /* f8 */
7883     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7884     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7885     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7886     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7887     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7888     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7889     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7890     { Bad_Opcode },
7891   },
7892   /* VEX_0F38 */
7893   {
7894     /* 00 */
7895     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7896     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7897     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7898     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7899     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7900     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7901     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7902     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7903     /* 08 */
7904     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7905     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7906     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7907     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7908     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7909     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7910     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7911     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7912     /* 10 */
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
7920     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7921     /* 18 */
7922     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7923     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7924     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7925     { Bad_Opcode },
7926     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7927     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7928     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7929     { Bad_Opcode },
7930     /* 20 */
7931     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7932     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7933     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7934     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7935     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7936     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     /* 28 */
7940     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7941     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7942     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7943     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7944     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7945     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7946     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7947     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7948     /* 30 */
7949     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7950     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7951     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7952     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7953     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7954     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7955     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
7956     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7957     /* 38 */
7958     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7959     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7960     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7961     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7962     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7963     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7964     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7965     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7966     /* 40 */
7967     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7968     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
7973     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
7974     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
7975     /* 48 */
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     /* 50 */
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     /* 58 */
7994     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
7995     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
7996     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     /* 60 */
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     /* 68 */
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     /* 70 */
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     /* 78 */
8030     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8031     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     /* 80 */
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* 88 */
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8053     { Bad_Opcode },
8054     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8055     { Bad_Opcode },
8056     /* 90 */
8057     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8058     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8059     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8060     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8064     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8065     /* 98 */
8066     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8067     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8068     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8069     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8070     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8071     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8072     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8073     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8074     /* a0 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8082     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8083     /* a8 */
8084     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8085     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8086     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8087     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8088     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8089     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8090     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8091     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8092     /* b0 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8100     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8101     /* b8 */
8102     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8103     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8104     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8105     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8106     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8107     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8108     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8109     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8110     /* c0 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* c8 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* d0 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     /* d8 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8142     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8143     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8144     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8145     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8146     /* e0 */
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     /* e8 */
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* f0 */
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8168     { REG_TABLE (REG_VEX_0F38F3) },
8169     { Bad_Opcode },
8170     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8171     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8172     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8173     /* f8 */
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182   },
8183   /* VEX_0F3A */
8184   {
8185     /* 00 */
8186     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8187     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8188     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8189     { Bad_Opcode },
8190     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8191     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8192     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8193     { Bad_Opcode },
8194     /* 08 */
8195     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8196     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8197     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8198     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8199     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8200     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8201     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8202     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8203     /* 10 */
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8209     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8210     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8211     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8212     /* 18 */
8213     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8214     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     /* 20 */
8222     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8223     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8224     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     /* 28 */
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     /* 30 */
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     /* 38 */
8249     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8250     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     /* 40 */
8258     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8259     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8260     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8261     { Bad_Opcode },
8262     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8263     { Bad_Opcode },
8264     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8265     { Bad_Opcode },
8266     /* 48 */
8267     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8268     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8269     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8270     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8271     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     /* 50 */
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     /* 58 */
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8290     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8291     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8292     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8293     /* 60 */
8294     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8295     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8296     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8297     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     /* 68 */
8303     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8304     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8305     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8306     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8307     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8308     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8309     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8310     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8311     /* 70 */
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     /* 78 */
8321     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8322     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8323     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8324     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8325     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8326     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8327     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8328     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8329     /* 80 */
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     /* 88 */
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     /* 90 */
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     /* 98 */
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     /* a0 */
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     /* a8 */
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     /* b0 */
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     /* b8 */
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     /* c0 */
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     /* c8 */
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     /* d0 */
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     /* d8 */
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8437     /* e0 */
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     /* e8 */
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     /* f0 */
8456     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     /* f8 */
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473   },
8474 };
8475
8476 static const struct dis386 vex_len_table[][2] = {
8477   /* VEX_LEN_0F10_P_1 */
8478   {
8479     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8480     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8481   },
8482
8483   /* VEX_LEN_0F10_P_3 */
8484   {
8485     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8486     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8487   },
8488
8489   /* VEX_LEN_0F11_P_1 */
8490   {
8491     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8492     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8493   },
8494
8495   /* VEX_LEN_0F11_P_3 */
8496   {
8497     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8498     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8499   },
8500
8501   /* VEX_LEN_0F12_P_0_M_0 */
8502   {
8503     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8504   },
8505
8506   /* VEX_LEN_0F12_P_0_M_1 */
8507   {
8508     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8509   },
8510
8511   /* VEX_LEN_0F12_P_2 */
8512   {
8513     { VEX_W_TABLE (VEX_W_0F12_P_2) },
8514   },
8515
8516   /* VEX_LEN_0F13_M_0 */
8517   {
8518     { VEX_W_TABLE (VEX_W_0F13_M_0) },
8519   },
8520
8521   /* VEX_LEN_0F16_P_0_M_0 */
8522   {
8523     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8524   },
8525
8526   /* VEX_LEN_0F16_P_0_M_1 */
8527   {
8528     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8529   },
8530
8531   /* VEX_LEN_0F16_P_2 */
8532   {
8533     { VEX_W_TABLE (VEX_W_0F16_P_2) },
8534   },
8535
8536   /* VEX_LEN_0F17_M_0 */
8537   {
8538     { VEX_W_TABLE (VEX_W_0F17_M_0) },
8539   },
8540
8541   /* VEX_LEN_0F2A_P_1 */
8542   {
8543     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8544     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8545   },
8546
8547   /* VEX_LEN_0F2A_P_3 */
8548   {
8549     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8550     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8551   },
8552
8553   /* VEX_LEN_0F2C_P_1 */
8554   {
8555     { "vcvttss2siY",    { Gv, EXdScalar } },
8556     { "vcvttss2siY",    { Gv, EXdScalar } },
8557   },
8558
8559   /* VEX_LEN_0F2C_P_3 */
8560   {
8561     { "vcvttsd2siY",    { Gv, EXqScalar } },
8562     { "vcvttsd2siY",    { Gv, EXqScalar } },
8563   },
8564
8565   /* VEX_LEN_0F2D_P_1 */
8566   {
8567     { "vcvtss2siY",     { Gv, EXdScalar } },
8568     { "vcvtss2siY",     { Gv, EXdScalar } },
8569   },
8570
8571   /* VEX_LEN_0F2D_P_3 */
8572   {
8573     { "vcvtsd2siY",     { Gv, EXqScalar } },
8574     { "vcvtsd2siY",     { Gv, EXqScalar } },
8575   },
8576
8577   /* VEX_LEN_0F2E_P_0 */
8578   {
8579     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8580     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8581   },
8582
8583   /* VEX_LEN_0F2E_P_2 */
8584   {
8585     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8586     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8587   },
8588
8589   /* VEX_LEN_0F2F_P_0 */
8590   {
8591     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8592     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8593   },
8594
8595   /* VEX_LEN_0F2F_P_2 */
8596   {
8597     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8598     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8599   },
8600
8601   /* VEX_LEN_0F51_P_1 */
8602   {
8603     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8604     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8605   },
8606
8607   /* VEX_LEN_0F51_P_3 */
8608   {
8609     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8610     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8611   },
8612
8613   /* VEX_LEN_0F52_P_1 */
8614   {
8615     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8616     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8617   },
8618
8619   /* VEX_LEN_0F53_P_1 */
8620   {
8621     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8622     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8623   },
8624
8625   /* VEX_LEN_0F58_P_1 */
8626   {
8627     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8628     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8629   },
8630
8631   /* VEX_LEN_0F58_P_3 */
8632   {
8633     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8634     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8635   },
8636
8637   /* VEX_LEN_0F59_P_1 */
8638   {
8639     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8640     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8641   },
8642
8643   /* VEX_LEN_0F59_P_3 */
8644   {
8645     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8646     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8647   },
8648
8649   /* VEX_LEN_0F5A_P_1 */
8650   {
8651     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8652     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8653   },
8654
8655   /* VEX_LEN_0F5A_P_3 */
8656   {
8657     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8658     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8659   },
8660
8661   /* VEX_LEN_0F5C_P_1 */
8662   {
8663     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8664     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8665   },
8666
8667   /* VEX_LEN_0F5C_P_3 */
8668   {
8669     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8670     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8671   },
8672
8673   /* VEX_LEN_0F5D_P_1 */
8674   {
8675     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8676     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8677   },
8678
8679   /* VEX_LEN_0F5D_P_3 */
8680   {
8681     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8682     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8683   },
8684
8685   /* VEX_LEN_0F5E_P_1 */
8686   {
8687     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8688     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8689   },
8690
8691   /* VEX_LEN_0F5E_P_3 */
8692   {
8693     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8694     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8695   },
8696
8697   /* VEX_LEN_0F5F_P_1 */
8698   {
8699     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8700     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8701   },
8702
8703   /* VEX_LEN_0F5F_P_3 */
8704   {
8705     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8706     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8707   },
8708
8709   /* VEX_LEN_0F6E_P_2 */
8710   {
8711     { "vmovK",          { XMScalar, Edq } },
8712     { "vmovK",          { XMScalar, Edq } },
8713   },
8714
8715   /* VEX_LEN_0F7E_P_1 */
8716   {
8717     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8718     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8719   },
8720
8721   /* VEX_LEN_0F7E_P_2 */
8722   {
8723     { "vmovK",          { Edq, XMScalar } },
8724     { "vmovK",          { Edq, XMScalar } },
8725   },
8726
8727   /* VEX_LEN_0FAE_R_2_M_0 */
8728   {
8729     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8730   },
8731
8732   /* VEX_LEN_0FAE_R_3_M_0 */
8733   {
8734     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8735   },
8736
8737   /* VEX_LEN_0FC2_P_1 */
8738   {
8739     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8740     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8741   },
8742
8743   /* VEX_LEN_0FC2_P_3 */
8744   {
8745     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8746     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8747   },
8748
8749   /* VEX_LEN_0FC4_P_2 */
8750   {
8751     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8752   },
8753
8754   /* VEX_LEN_0FC5_P_2 */
8755   {
8756     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8757   },
8758
8759   /* VEX_LEN_0FD6_P_2 */
8760   {
8761     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8762     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8763   },
8764
8765   /* VEX_LEN_0FF7_P_2 */
8766   {
8767     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8768   },
8769
8770   /* VEX_LEN_0F3816_P_2 */
8771   {
8772     { Bad_Opcode },
8773     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
8774   },
8775
8776   /* VEX_LEN_0F3819_P_2 */
8777   {
8778     { Bad_Opcode },
8779     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
8780   },
8781
8782   /* VEX_LEN_0F381A_P_2_M_0 */
8783   {
8784     { Bad_Opcode },
8785     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8786   },
8787
8788   /* VEX_LEN_0F3836_P_2 */
8789   {
8790     { Bad_Opcode },
8791     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
8792   },
8793
8794   /* VEX_LEN_0F3841_P_2 */
8795   {
8796     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
8797   },
8798
8799   /* VEX_LEN_0F385A_P_2_M_0 */
8800   {
8801     { Bad_Opcode },
8802     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
8803   },
8804
8805   /* VEX_LEN_0F38DB_P_2 */
8806   {
8807     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
8808   },
8809
8810   /* VEX_LEN_0F38DC_P_2 */
8811   {
8812     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
8813   },
8814
8815   /* VEX_LEN_0F38DD_P_2 */
8816   {
8817     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
8818   },
8819
8820   /* VEX_LEN_0F38DE_P_2 */
8821   {
8822     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
8823   },
8824
8825   /* VEX_LEN_0F38DF_P_2 */
8826   {
8827     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
8828   },
8829
8830   /* VEX_LEN_0F38F2_P_0 */
8831   {
8832     { "andnS",          { Gdq, VexGdq, Edq } },
8833   },
8834
8835   /* VEX_LEN_0F38F3_R_1_P_0 */
8836   {
8837     { "blsrS",          { VexGdq, Edq } },
8838   },
8839
8840   /* VEX_LEN_0F38F3_R_2_P_0 */
8841   {
8842     { "blsmskS",        { VexGdq, Edq } },
8843   },
8844
8845   /* VEX_LEN_0F38F3_R_3_P_0 */
8846   {
8847     { "blsiS",          { VexGdq, Edq } },
8848   },
8849
8850   /* VEX_LEN_0F38F5_P_0 */
8851   {
8852     { "bzhiS",          { Gdq, Edq, VexGdq } },
8853   },
8854
8855   /* VEX_LEN_0F38F5_P_1 */
8856   {
8857     { "pextS",          { Gdq, VexGdq, Edq } },
8858   },
8859
8860   /* VEX_LEN_0F38F5_P_3 */
8861   {
8862     { "pdepS",          { Gdq, VexGdq, Edq } },
8863   },
8864
8865   /* VEX_LEN_0F38F6_P_3 */
8866   {
8867     { "mulxS",          { Gdq, VexGdq, Edq } },
8868   },
8869
8870   /* VEX_LEN_0F38F7_P_0 */
8871   {
8872     { "bextrS",         { Gdq, Edq, VexGdq } },
8873   },
8874
8875   /* VEX_LEN_0F38F7_P_1 */
8876   {
8877     { "sarxS",          { Gdq, Edq, VexGdq } },
8878   },
8879
8880   /* VEX_LEN_0F38F7_P_2 */
8881   {
8882     { "shlxS",          { Gdq, Edq, VexGdq } },
8883   },
8884
8885   /* VEX_LEN_0F38F7_P_3 */
8886   {
8887     { "shrxS",          { Gdq, Edq, VexGdq } },
8888   },
8889
8890   /* VEX_LEN_0F3A00_P_2 */
8891   {
8892     { Bad_Opcode },
8893     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
8894   },
8895
8896   /* VEX_LEN_0F3A01_P_2 */
8897   {
8898     { Bad_Opcode },
8899     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
8900   },
8901
8902   /* VEX_LEN_0F3A06_P_2 */
8903   {
8904     { Bad_Opcode },
8905     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
8906   },
8907
8908   /* VEX_LEN_0F3A0A_P_2 */
8909   {
8910     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8911     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8912   },
8913
8914   /* VEX_LEN_0F3A0B_P_2 */
8915   {
8916     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8917     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8918   },
8919
8920   /* VEX_LEN_0F3A14_P_2 */
8921   {
8922     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
8923   },
8924
8925   /* VEX_LEN_0F3A15_P_2 */
8926   {
8927     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
8928   },
8929
8930   /* VEX_LEN_0F3A16_P_2  */
8931   {
8932     { "vpextrK",        { Edq, XM, Ib } },
8933   },
8934
8935   /* VEX_LEN_0F3A17_P_2 */
8936   {
8937     { "vextractps",     { Edqd, XM, Ib } },
8938   },
8939
8940   /* VEX_LEN_0F3A18_P_2 */
8941   {
8942     { Bad_Opcode },
8943     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
8944   },
8945
8946   /* VEX_LEN_0F3A19_P_2 */
8947   {
8948     { Bad_Opcode },
8949     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
8950   },
8951
8952   /* VEX_LEN_0F3A20_P_2 */
8953   {
8954     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
8955   },
8956
8957   /* VEX_LEN_0F3A21_P_2 */
8958   {
8959     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
8960   },
8961
8962   /* VEX_LEN_0F3A22_P_2 */
8963   {
8964     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8965   },
8966
8967   /* VEX_LEN_0F3A38_P_2 */
8968   {
8969     { Bad_Opcode },
8970     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
8971   },
8972
8973   /* VEX_LEN_0F3A39_P_2 */
8974   {
8975     { Bad_Opcode },
8976     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
8977   },
8978
8979   /* VEX_LEN_0F3A41_P_2 */
8980   {
8981     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
8982   },
8983
8984   /* VEX_LEN_0F3A44_P_2 */
8985   {
8986     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
8987   },
8988
8989   /* VEX_LEN_0F3A46_P_2 */
8990   {
8991     { Bad_Opcode },
8992     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
8993   },
8994
8995   /* VEX_LEN_0F3A60_P_2 */
8996   {
8997     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
8998   },
8999
9000   /* VEX_LEN_0F3A61_P_2 */
9001   {
9002     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9003   },
9004
9005   /* VEX_LEN_0F3A62_P_2 */
9006   {
9007     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9008   },
9009
9010   /* VEX_LEN_0F3A63_P_2 */
9011   {
9012     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9013   },
9014
9015   /* VEX_LEN_0F3A6A_P_2 */
9016   {
9017     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9018   },
9019
9020   /* VEX_LEN_0F3A6B_P_2 */
9021   {
9022     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9023   },
9024
9025   /* VEX_LEN_0F3A6E_P_2 */
9026   {
9027     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9028   },
9029
9030   /* VEX_LEN_0F3A6F_P_2 */
9031   {
9032     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9033   },
9034
9035   /* VEX_LEN_0F3A7A_P_2 */
9036   {
9037     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9038   },
9039
9040   /* VEX_LEN_0F3A7B_P_2 */
9041   {
9042     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9043   },
9044
9045   /* VEX_LEN_0F3A7E_P_2 */
9046   {
9047     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9048   },
9049
9050   /* VEX_LEN_0F3A7F_P_2 */
9051   {
9052     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9053   },
9054
9055   /* VEX_LEN_0F3ADF_P_2 */
9056   {
9057     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9058   },
9059
9060   /* VEX_LEN_0F3AF0_P_3 */
9061   {
9062     { "rorxS",          { Gdq, Edq, Ib } },
9063   },
9064
9065   /* VEX_LEN_0FXOP_08_CC */
9066   {
9067      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9068   },
9069
9070   /* VEX_LEN_0FXOP_08_CD */
9071   {
9072      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9073   },
9074
9075   /* VEX_LEN_0FXOP_08_CE */
9076   {
9077      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9078   },
9079
9080   /* VEX_LEN_0FXOP_08_CF */
9081   {
9082      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9083   },
9084
9085   /* VEX_LEN_0FXOP_08_EC */
9086   {
9087      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9088   },
9089
9090   /* VEX_LEN_0FXOP_08_ED */
9091   {
9092      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9093   },
9094
9095   /* VEX_LEN_0FXOP_08_EE */
9096   {
9097      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9098   },
9099
9100   /* VEX_LEN_0FXOP_08_EF */
9101   {
9102      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9103   },
9104
9105   /* VEX_LEN_0FXOP_09_80 */
9106   {
9107     { "vfrczps",        { XM, EXxmm } },
9108     { "vfrczps",        { XM, EXymmq } },
9109   },
9110
9111   /* VEX_LEN_0FXOP_09_81 */
9112   {
9113     { "vfrczpd",        { XM, EXxmm } },
9114     { "vfrczpd",        { XM, EXymmq } },
9115   },
9116 };
9117
9118 static const struct dis386 vex_w_table[][2] = {
9119   {
9120     /* VEX_W_0F10_P_0 */
9121     { "vmovups",        { XM, EXx } },
9122   },
9123   {
9124     /* VEX_W_0F10_P_1 */
9125     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9126   },
9127   {
9128     /* VEX_W_0F10_P_2 */
9129     { "vmovupd",        { XM, EXx } },
9130   },
9131   {
9132     /* VEX_W_0F10_P_3 */
9133     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9134   },
9135   {
9136     /* VEX_W_0F11_P_0 */
9137     { "vmovups",        { EXxS, XM } },
9138   },
9139   {
9140     /* VEX_W_0F11_P_1 */
9141     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9142   },
9143   {
9144     /* VEX_W_0F11_P_2 */
9145     { "vmovupd",        { EXxS, XM } },
9146   },
9147   {
9148     /* VEX_W_0F11_P_3 */
9149     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9150   },
9151   {
9152     /* VEX_W_0F12_P_0_M_0 */
9153     { "vmovlps",        { XM, Vex128, EXq } },
9154   },
9155   {
9156     /* VEX_W_0F12_P_0_M_1 */
9157     { "vmovhlps",       { XM, Vex128, EXq } },
9158   },
9159   {
9160     /* VEX_W_0F12_P_1 */
9161     { "vmovsldup",      { XM, EXx } },
9162   },
9163   {
9164     /* VEX_W_0F12_P_2 */
9165     { "vmovlpd",        { XM, Vex128, EXq } },
9166   },
9167   {
9168     /* VEX_W_0F12_P_3 */
9169     { "vmovddup",       { XM, EXymmq } },
9170   },
9171   {
9172     /* VEX_W_0F13_M_0 */
9173     { "vmovlpX",        { EXq, XM } },
9174   },
9175   {
9176     /* VEX_W_0F14 */
9177     { "vunpcklpX",      { XM, Vex, EXx } },
9178   },
9179   {
9180     /* VEX_W_0F15 */
9181     { "vunpckhpX",      { XM, Vex, EXx } },
9182   },
9183   {
9184     /* VEX_W_0F16_P_0_M_0 */
9185     { "vmovhps",        { XM, Vex128, EXq } },
9186   },
9187   {
9188     /* VEX_W_0F16_P_0_M_1 */
9189     { "vmovlhps",       { XM, Vex128, EXq } },
9190   },
9191   {
9192     /* VEX_W_0F16_P_1 */
9193     { "vmovshdup",      { XM, EXx } },
9194   },
9195   {
9196     /* VEX_W_0F16_P_2 */
9197     { "vmovhpd",        { XM, Vex128, EXq } },
9198   },
9199   {
9200     /* VEX_W_0F17_M_0 */
9201     { "vmovhpX",        { EXq, XM } },
9202   },
9203   {
9204     /* VEX_W_0F28 */
9205     { "vmovapX",        { XM, EXx } },
9206   },
9207   {
9208     /* VEX_W_0F29 */
9209     { "vmovapX",        { EXxS, XM } },
9210   },
9211   {
9212     /* VEX_W_0F2B_M_0 */
9213     { "vmovntpX",       { Mx, XM } },
9214   },
9215   {
9216     /* VEX_W_0F2E_P_0 */
9217     { "vucomiss",       { XMScalar, EXdScalar } },
9218   },
9219   {
9220     /* VEX_W_0F2E_P_2 */
9221     { "vucomisd",       { XMScalar, EXqScalar } },
9222   },
9223   {
9224     /* VEX_W_0F2F_P_0 */
9225     { "vcomiss",        { XMScalar, EXdScalar } },
9226   },
9227   {
9228     /* VEX_W_0F2F_P_2 */
9229     { "vcomisd",        { XMScalar, EXqScalar } },
9230   },
9231   {
9232     /* VEX_W_0F50_M_0 */
9233     { "vmovmskpX",      { Gdq, XS } },
9234   },
9235   {
9236     /* VEX_W_0F51_P_0 */
9237     { "vsqrtps",        { XM, EXx } },
9238   },
9239   {
9240     /* VEX_W_0F51_P_1 */
9241     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9242   },
9243   {
9244     /* VEX_W_0F51_P_2  */
9245     { "vsqrtpd",        { XM, EXx } },
9246   },
9247   {
9248     /* VEX_W_0F51_P_3 */
9249     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9250   },
9251   {
9252     /* VEX_W_0F52_P_0 */
9253     { "vrsqrtps",       { XM, EXx } },
9254   },
9255   {
9256     /* VEX_W_0F52_P_1 */
9257     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9258   },
9259   {
9260     /* VEX_W_0F53_P_0  */
9261     { "vrcpps",         { XM, EXx } },
9262   },
9263   {
9264     /* VEX_W_0F53_P_1  */
9265     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9266   },
9267   {
9268     /* VEX_W_0F58_P_0  */
9269     { "vaddps",         { XM, Vex, EXx } },
9270   },
9271   {
9272     /* VEX_W_0F58_P_1  */
9273     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9274   },
9275   {
9276     /* VEX_W_0F58_P_2  */
9277     { "vaddpd",         { XM, Vex, EXx } },
9278   },
9279   {
9280     /* VEX_W_0F58_P_3  */
9281     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9282   },
9283   {
9284     /* VEX_W_0F59_P_0  */
9285     { "vmulps",         { XM, Vex, EXx } },
9286   },
9287   {
9288     /* VEX_W_0F59_P_1  */
9289     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9290   },
9291   {
9292     /* VEX_W_0F59_P_2  */
9293     { "vmulpd",         { XM, Vex, EXx } },
9294   },
9295   {
9296     /* VEX_W_0F59_P_3  */
9297     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9298   },
9299   {
9300     /* VEX_W_0F5A_P_0  */
9301     { "vcvtps2pd",      { XM, EXxmmq } },
9302   },
9303   {
9304     /* VEX_W_0F5A_P_1  */
9305     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9306   },
9307   {
9308     /* VEX_W_0F5A_P_3  */
9309     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9310   },
9311   {
9312     /* VEX_W_0F5B_P_0  */
9313     { "vcvtdq2ps",      { XM, EXx } },
9314   },
9315   {
9316     /* VEX_W_0F5B_P_1  */
9317     { "vcvttps2dq",     { XM, EXx } },
9318   },
9319   {
9320     /* VEX_W_0F5B_P_2  */
9321     { "vcvtps2dq",      { XM, EXx } },
9322   },
9323   {
9324     /* VEX_W_0F5C_P_0  */
9325     { "vsubps",         { XM, Vex, EXx } },
9326   },
9327   {
9328     /* VEX_W_0F5C_P_1  */
9329     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9330   },
9331   {
9332     /* VEX_W_0F5C_P_2  */
9333     { "vsubpd",         { XM, Vex, EXx } },
9334   },
9335   {
9336     /* VEX_W_0F5C_P_3  */
9337     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9338   },
9339   {
9340     /* VEX_W_0F5D_P_0  */
9341     { "vminps",         { XM, Vex, EXx } },
9342   },
9343   {
9344     /* VEX_W_0F5D_P_1  */
9345     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9346   },
9347   {
9348     /* VEX_W_0F5D_P_2  */
9349     { "vminpd",         { XM, Vex, EXx } },
9350   },
9351   {
9352     /* VEX_W_0F5D_P_3  */
9353     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9354   },
9355   {
9356     /* VEX_W_0F5E_P_0  */
9357     { "vdivps",         { XM, Vex, EXx } },
9358   },
9359   {
9360     /* VEX_W_0F5E_P_1  */
9361     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9362   },
9363   {
9364     /* VEX_W_0F5E_P_2  */
9365     { "vdivpd",         { XM, Vex, EXx } },
9366   },
9367   {
9368     /* VEX_W_0F5E_P_3  */
9369     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9370   },
9371   {
9372     /* VEX_W_0F5F_P_0  */
9373     { "vmaxps",         { XM, Vex, EXx } },
9374   },
9375   {
9376     /* VEX_W_0F5F_P_1  */
9377     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9378   },
9379   {
9380     /* VEX_W_0F5F_P_2  */
9381     { "vmaxpd",         { XM, Vex, EXx } },
9382   },
9383   {
9384     /* VEX_W_0F5F_P_3  */
9385     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9386   },
9387   {
9388     /* VEX_W_0F60_P_2  */
9389     { "vpunpcklbw",     { XM, Vex, EXx } },
9390   },
9391   {
9392     /* VEX_W_0F61_P_2  */
9393     { "vpunpcklwd",     { XM, Vex, EXx } },
9394   },
9395   {
9396     /* VEX_W_0F62_P_2  */
9397     { "vpunpckldq",     { XM, Vex, EXx } },
9398   },
9399   {
9400     /* VEX_W_0F63_P_2  */
9401     { "vpacksswb",      { XM, Vex, EXx } },
9402   },
9403   {
9404     /* VEX_W_0F64_P_2  */
9405     { "vpcmpgtb",       { XM, Vex, EXx } },
9406   },
9407   {
9408     /* VEX_W_0F65_P_2  */
9409     { "vpcmpgtw",       { XM, Vex, EXx } },
9410   },
9411   {
9412     /* VEX_W_0F66_P_2  */
9413     { "vpcmpgtd",       { XM, Vex, EXx } },
9414   },
9415   {
9416     /* VEX_W_0F67_P_2  */
9417     { "vpackuswb",      { XM, Vex, EXx } },
9418   },
9419   {
9420     /* VEX_W_0F68_P_2  */
9421     { "vpunpckhbw",     { XM, Vex, EXx } },
9422   },
9423   {
9424     /* VEX_W_0F69_P_2  */
9425     { "vpunpckhwd",     { XM, Vex, EXx } },
9426   },
9427   {
9428     /* VEX_W_0F6A_P_2  */
9429     { "vpunpckhdq",     { XM, Vex, EXx } },
9430   },
9431   {
9432     /* VEX_W_0F6B_P_2  */
9433     { "vpackssdw",      { XM, Vex, EXx } },
9434   },
9435   {
9436     /* VEX_W_0F6C_P_2  */
9437     { "vpunpcklqdq",    { XM, Vex, EXx } },
9438   },
9439   {
9440     /* VEX_W_0F6D_P_2  */
9441     { "vpunpckhqdq",    { XM, Vex, EXx } },
9442   },
9443   {
9444     /* VEX_W_0F6F_P_1  */
9445     { "vmovdqu",        { XM, EXx } },
9446   },
9447   {
9448     /* VEX_W_0F6F_P_2  */
9449     { "vmovdqa",        { XM, EXx } },
9450   },
9451   {
9452     /* VEX_W_0F70_P_1 */
9453     { "vpshufhw",       { XM, EXx, Ib } },
9454   },
9455   {
9456     /* VEX_W_0F70_P_2 */
9457     { "vpshufd",        { XM, EXx, Ib } },
9458   },
9459   {
9460     /* VEX_W_0F70_P_3 */
9461     { "vpshuflw",       { XM, EXx, Ib } },
9462   },
9463   {
9464     /* VEX_W_0F71_R_2_P_2  */
9465     { "vpsrlw",         { Vex, XS, Ib } },
9466   },
9467   {
9468     /* VEX_W_0F71_R_4_P_2  */
9469     { "vpsraw",         { Vex, XS, Ib } },
9470   },
9471   {
9472     /* VEX_W_0F71_R_6_P_2  */
9473     { "vpsllw",         { Vex, XS, Ib } },
9474   },
9475   {
9476     /* VEX_W_0F72_R_2_P_2  */
9477     { "vpsrld",         { Vex, XS, Ib } },
9478   },
9479   {
9480     /* VEX_W_0F72_R_4_P_2  */
9481     { "vpsrad",         { Vex, XS, Ib } },
9482   },
9483   {
9484     /* VEX_W_0F72_R_6_P_2  */
9485     { "vpslld",         { Vex, XS, Ib } },
9486   },
9487   {
9488     /* VEX_W_0F73_R_2_P_2  */
9489     { "vpsrlq",         { Vex, XS, Ib } },
9490   },
9491   {
9492     /* VEX_W_0F73_R_3_P_2  */
9493     { "vpsrldq",        { Vex, XS, Ib } },
9494   },
9495   {
9496     /* VEX_W_0F73_R_6_P_2  */
9497     { "vpsllq",         { Vex, XS, Ib } },
9498   },
9499   {
9500     /* VEX_W_0F73_R_7_P_2  */
9501     { "vpslldq",        { Vex, XS, Ib } },
9502   },
9503   {
9504     /* VEX_W_0F74_P_2 */
9505     { "vpcmpeqb",       { XM, Vex, EXx } },
9506   },
9507   {
9508     /* VEX_W_0F75_P_2 */
9509     { "vpcmpeqw",       { XM, Vex, EXx } },
9510   },
9511   {
9512     /* VEX_W_0F76_P_2 */
9513     { "vpcmpeqd",       { XM, Vex, EXx } },
9514   },
9515   {
9516     /* VEX_W_0F77_P_0 */
9517     { "",               { VZERO } },
9518   },
9519   {
9520     /* VEX_W_0F7C_P_2 */
9521     { "vhaddpd",        { XM, Vex, EXx } },
9522   },
9523   {
9524     /* VEX_W_0F7C_P_3 */
9525     { "vhaddps",        { XM, Vex, EXx } },
9526   },
9527   {
9528     /* VEX_W_0F7D_P_2 */
9529     { "vhsubpd",        { XM, Vex, EXx } },
9530   },
9531   {
9532     /* VEX_W_0F7D_P_3 */
9533     { "vhsubps",        { XM, Vex, EXx } },
9534   },
9535   {
9536     /* VEX_W_0F7E_P_1 */
9537     { "vmovq",          { XMScalar, EXqScalar } },
9538   },
9539   {
9540     /* VEX_W_0F7F_P_1 */
9541     { "vmovdqu",        { EXxS, XM } },
9542   },
9543   {
9544     /* VEX_W_0F7F_P_2 */
9545     { "vmovdqa",        { EXxS, XM } },
9546   },
9547   {
9548     /* VEX_W_0FAE_R_2_M_0 */
9549     { "vldmxcsr",       { Md } },
9550   },
9551   {
9552     /* VEX_W_0FAE_R_3_M_0 */
9553     { "vstmxcsr",       { Md } },
9554   },
9555   {
9556     /* VEX_W_0FC2_P_0 */
9557     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9558   },
9559   {
9560     /* VEX_W_0FC2_P_1 */
9561     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9562   },
9563   {
9564     /* VEX_W_0FC2_P_2 */
9565     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9566   },
9567   {
9568     /* VEX_W_0FC2_P_3 */
9569     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9570   },
9571   {
9572     /* VEX_W_0FC4_P_2 */
9573     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9574   },
9575   {
9576     /* VEX_W_0FC5_P_2 */
9577     { "vpextrw",        { Gdq, XS, Ib } },
9578   },
9579   {
9580     /* VEX_W_0FD0_P_2 */
9581     { "vaddsubpd",      { XM, Vex, EXx } },
9582   },
9583   {
9584     /* VEX_W_0FD0_P_3 */
9585     { "vaddsubps",      { XM, Vex, EXx } },
9586   },
9587   {
9588     /* VEX_W_0FD1_P_2 */
9589     { "vpsrlw",         { XM, Vex, EXxmm } },
9590   },
9591   {
9592     /* VEX_W_0FD2_P_2 */
9593     { "vpsrld",         { XM, Vex, EXxmm } },
9594   },
9595   {
9596     /* VEX_W_0FD3_P_2 */
9597     { "vpsrlq",         { XM, Vex, EXxmm } },
9598   },
9599   {
9600     /* VEX_W_0FD4_P_2 */
9601     { "vpaddq",         { XM, Vex, EXx } },
9602   },
9603   {
9604     /* VEX_W_0FD5_P_2 */
9605     { "vpmullw",        { XM, Vex, EXx } },
9606   },
9607   {
9608     /* VEX_W_0FD6_P_2 */
9609     { "vmovq",          { EXqScalarS, XMScalar } },
9610   },
9611   {
9612     /* VEX_W_0FD7_P_2_M_1 */
9613     { "vpmovmskb",      { Gdq, XS } },
9614   },
9615   {
9616     /* VEX_W_0FD8_P_2 */
9617     { "vpsubusb",       { XM, Vex, EXx } },
9618   },
9619   {
9620     /* VEX_W_0FD9_P_2 */
9621     { "vpsubusw",       { XM, Vex, EXx } },
9622   },
9623   {
9624     /* VEX_W_0FDA_P_2 */
9625     { "vpminub",        { XM, Vex, EXx } },
9626   },
9627   {
9628     /* VEX_W_0FDB_P_2 */
9629     { "vpand",          { XM, Vex, EXx } },
9630   },
9631   {
9632     /* VEX_W_0FDC_P_2 */
9633     { "vpaddusb",       { XM, Vex, EXx } },
9634   },
9635   {
9636     /* VEX_W_0FDD_P_2 */
9637     { "vpaddusw",       { XM, Vex, EXx } },
9638   },
9639   {
9640     /* VEX_W_0FDE_P_2 */
9641     { "vpmaxub",        { XM, Vex, EXx } },
9642   },
9643   {
9644     /* VEX_W_0FDF_P_2 */
9645     { "vpandn",         { XM, Vex, EXx } },
9646   },
9647   {
9648     /* VEX_W_0FE0_P_2  */
9649     { "vpavgb",         { XM, Vex, EXx } },
9650   },
9651   {
9652     /* VEX_W_0FE1_P_2  */
9653     { "vpsraw",         { XM, Vex, EXxmm } },
9654   },
9655   {
9656     /* VEX_W_0FE2_P_2  */
9657     { "vpsrad",         { XM, Vex, EXxmm } },
9658   },
9659   {
9660     /* VEX_W_0FE3_P_2  */
9661     { "vpavgw",         { XM, Vex, EXx } },
9662   },
9663   {
9664     /* VEX_W_0FE4_P_2  */
9665     { "vpmulhuw",       { XM, Vex, EXx } },
9666   },
9667   {
9668     /* VEX_W_0FE5_P_2  */
9669     { "vpmulhw",        { XM, Vex, EXx } },
9670   },
9671   {
9672     /* VEX_W_0FE6_P_1  */
9673     { "vcvtdq2pd",      { XM, EXxmmq } },
9674   },
9675   {
9676     /* VEX_W_0FE6_P_2  */
9677     { "vcvttpd2dq%XY",  { XMM, EXx } },
9678   },
9679   {
9680     /* VEX_W_0FE6_P_3  */
9681     { "vcvtpd2dq%XY",   { XMM, EXx } },
9682   },
9683   {
9684     /* VEX_W_0FE7_P_2_M_0 */
9685     { "vmovntdq",       { Mx, XM } },
9686   },
9687   {
9688     /* VEX_W_0FE8_P_2  */
9689     { "vpsubsb",        { XM, Vex, EXx } },
9690   },
9691   {
9692     /* VEX_W_0FE9_P_2  */
9693     { "vpsubsw",        { XM, Vex, EXx } },
9694   },
9695   {
9696     /* VEX_W_0FEA_P_2  */
9697     { "vpminsw",        { XM, Vex, EXx } },
9698   },
9699   {
9700     /* VEX_W_0FEB_P_2  */
9701     { "vpor",           { XM, Vex, EXx } },
9702   },
9703   {
9704     /* VEX_W_0FEC_P_2  */
9705     { "vpaddsb",        { XM, Vex, EXx } },
9706   },
9707   {
9708     /* VEX_W_0FED_P_2  */
9709     { "vpaddsw",        { XM, Vex, EXx } },
9710   },
9711   {
9712     /* VEX_W_0FEE_P_2  */
9713     { "vpmaxsw",        { XM, Vex, EXx } },
9714   },
9715   {
9716     /* VEX_W_0FEF_P_2  */
9717     { "vpxor",          { XM, Vex, EXx } },
9718   },
9719   {
9720     /* VEX_W_0FF0_P_3_M_0 */
9721     { "vlddqu",         { XM, M } },
9722   },
9723   {
9724     /* VEX_W_0FF1_P_2 */
9725     { "vpsllw",         { XM, Vex, EXxmm } },
9726   },
9727   {
9728     /* VEX_W_0FF2_P_2 */
9729     { "vpslld",         { XM, Vex, EXxmm } },
9730   },
9731   {
9732     /* VEX_W_0FF3_P_2 */
9733     { "vpsllq",         { XM, Vex, EXxmm } },
9734   },
9735   {
9736     /* VEX_W_0FF4_P_2 */
9737     { "vpmuludq",       { XM, Vex, EXx } },
9738   },
9739   {
9740     /* VEX_W_0FF5_P_2 */
9741     { "vpmaddwd",       { XM, Vex, EXx } },
9742   },
9743   {
9744     /* VEX_W_0FF6_P_2 */
9745     { "vpsadbw",        { XM, Vex, EXx } },
9746   },
9747   {
9748     /* VEX_W_0FF7_P_2 */
9749     { "vmaskmovdqu",    { XM, XS } },
9750   },
9751   {
9752     /* VEX_W_0FF8_P_2 */
9753     { "vpsubb",         { XM, Vex, EXx } },
9754   },
9755   {
9756     /* VEX_W_0FF9_P_2 */
9757     { "vpsubw",         { XM, Vex, EXx } },
9758   },
9759   {
9760     /* VEX_W_0FFA_P_2 */
9761     { "vpsubd",         { XM, Vex, EXx } },
9762   },
9763   {
9764     /* VEX_W_0FFB_P_2 */
9765     { "vpsubq",         { XM, Vex, EXx } },
9766   },
9767   {
9768     /* VEX_W_0FFC_P_2 */
9769     { "vpaddb",         { XM, Vex, EXx } },
9770   },
9771   {
9772     /* VEX_W_0FFD_P_2 */
9773     { "vpaddw",         { XM, Vex, EXx } },
9774   },
9775   {
9776     /* VEX_W_0FFE_P_2 */
9777     { "vpaddd",         { XM, Vex, EXx } },
9778   },
9779   {
9780     /* VEX_W_0F3800_P_2  */
9781     { "vpshufb",        { XM, Vex, EXx } },
9782   },
9783   {
9784     /* VEX_W_0F3801_P_2  */
9785     { "vphaddw",        { XM, Vex, EXx } },
9786   },
9787   {
9788     /* VEX_W_0F3802_P_2  */
9789     { "vphaddd",        { XM, Vex, EXx } },
9790   },
9791   {
9792     /* VEX_W_0F3803_P_2  */
9793     { "vphaddsw",       { XM, Vex, EXx } },
9794   },
9795   {
9796     /* VEX_W_0F3804_P_2  */
9797     { "vpmaddubsw",     { XM, Vex, EXx } },
9798   },
9799   {
9800     /* VEX_W_0F3805_P_2  */
9801     { "vphsubw",        { XM, Vex, EXx } },
9802   },
9803   {
9804     /* VEX_W_0F3806_P_2  */
9805     { "vphsubd",        { XM, Vex, EXx } },
9806   },
9807   {
9808     /* VEX_W_0F3807_P_2  */
9809     { "vphsubsw",       { XM, Vex, EXx } },
9810   },
9811   {
9812     /* VEX_W_0F3808_P_2  */
9813     { "vpsignb",        { XM, Vex, EXx } },
9814   },
9815   {
9816     /* VEX_W_0F3809_P_2  */
9817     { "vpsignw",        { XM, Vex, EXx } },
9818   },
9819   {
9820     /* VEX_W_0F380A_P_2  */
9821     { "vpsignd",        { XM, Vex, EXx } },
9822   },
9823   {
9824     /* VEX_W_0F380B_P_2  */
9825     { "vpmulhrsw",      { XM, Vex, EXx } },
9826   },
9827   {
9828     /* VEX_W_0F380C_P_2  */
9829     { "vpermilps",      { XM, Vex, EXx } },
9830   },
9831   {
9832     /* VEX_W_0F380D_P_2  */
9833     { "vpermilpd",      { XM, Vex, EXx } },
9834   },
9835   {
9836     /* VEX_W_0F380E_P_2  */
9837     { "vtestps",        { XM, EXx } },
9838   },
9839   {
9840     /* VEX_W_0F380F_P_2  */
9841     { "vtestpd",        { XM, EXx } },
9842   },
9843   {
9844     /* VEX_W_0F3816_P_2  */
9845     { "vpermps",        { XM, Vex, EXx } },
9846   },
9847   {
9848     /* VEX_W_0F3817_P_2 */
9849     { "vptest",         { XM, EXx } },
9850   },
9851   {
9852     /* VEX_W_0F3818_P_2 */
9853     { "vbroadcastss",   { XM, EXxmm_md } },
9854   },
9855   {
9856     /* VEX_W_0F3819_P_2 */
9857     { "vbroadcastsd",   { XM, EXxmm_mq } },
9858   },
9859   {
9860     /* VEX_W_0F381A_P_2_M_0 */
9861     { "vbroadcastf128", { XM, Mxmm } },
9862   },
9863   {
9864     /* VEX_W_0F381C_P_2 */
9865     { "vpabsb",         { XM, EXx } },
9866   },
9867   {
9868     /* VEX_W_0F381D_P_2 */
9869     { "vpabsw",         { XM, EXx } },
9870   },
9871   {
9872     /* VEX_W_0F381E_P_2 */
9873     { "vpabsd",         { XM, EXx } },
9874   },
9875   {
9876     /* VEX_W_0F3820_P_2 */
9877     { "vpmovsxbw",      { XM, EXxmmq } },
9878   },
9879   {
9880     /* VEX_W_0F3821_P_2 */
9881     { "vpmovsxbd",      { XM, EXxmmqd } },
9882   },
9883   {
9884     /* VEX_W_0F3822_P_2 */
9885     { "vpmovsxbq",      { XM, EXxmmdw } },
9886   },
9887   {
9888     /* VEX_W_0F3823_P_2 */
9889     { "vpmovsxwd",      { XM, EXxmmq } },
9890   },
9891   {
9892     /* VEX_W_0F3824_P_2 */
9893     { "vpmovsxwq",      { XM, EXxmmqd } },
9894   },
9895   {
9896     /* VEX_W_0F3825_P_2 */
9897     { "vpmovsxdq",      { XM, EXxmmq } },
9898   },
9899   {
9900     /* VEX_W_0F3828_P_2 */
9901     { "vpmuldq",        { XM, Vex, EXx } },
9902   },
9903   {
9904     /* VEX_W_0F3829_P_2 */
9905     { "vpcmpeqq",       { XM, Vex, EXx } },
9906   },
9907   {
9908     /* VEX_W_0F382A_P_2_M_0 */
9909     { "vmovntdqa",      { XM, Mx } },
9910   },
9911   {
9912     /* VEX_W_0F382B_P_2 */
9913     { "vpackusdw",      { XM, Vex, EXx } },
9914   },
9915   {
9916     /* VEX_W_0F382C_P_2_M_0 */
9917     { "vmaskmovps",     { XM, Vex, Mx } },
9918   },
9919   {
9920     /* VEX_W_0F382D_P_2_M_0 */
9921     { "vmaskmovpd",     { XM, Vex, Mx } },
9922   },
9923   {
9924     /* VEX_W_0F382E_P_2_M_0 */
9925     { "vmaskmovps",     { Mx, Vex, XM } },
9926   },
9927   {
9928     /* VEX_W_0F382F_P_2_M_0 */
9929     { "vmaskmovpd",     { Mx, Vex, XM } },
9930   },
9931   {
9932     /* VEX_W_0F3830_P_2 */
9933     { "vpmovzxbw",      { XM, EXxmmq } },
9934   },
9935   {
9936     /* VEX_W_0F3831_P_2 */
9937     { "vpmovzxbd",      { XM, EXxmmqd } },
9938   },
9939   {
9940     /* VEX_W_0F3832_P_2 */
9941     { "vpmovzxbq",      { XM, EXxmmdw } },
9942   },
9943   {
9944     /* VEX_W_0F3833_P_2 */
9945     { "vpmovzxwd",      { XM, EXxmmq } },
9946   },
9947   {
9948     /* VEX_W_0F3834_P_2 */
9949     { "vpmovzxwq",      { XM, EXxmmqd } },
9950   },
9951   {
9952     /* VEX_W_0F3835_P_2 */
9953     { "vpmovzxdq",      { XM, EXxmmq } },
9954   },
9955   {
9956     /* VEX_W_0F3836_P_2  */
9957     { "vpermd",         { XM, Vex, EXx } },
9958   },
9959   {
9960     /* VEX_W_0F3837_P_2 */
9961     { "vpcmpgtq",       { XM, Vex, EXx } },
9962   },
9963   {
9964     /* VEX_W_0F3838_P_2 */
9965     { "vpminsb",        { XM, Vex, EXx } },
9966   },
9967   {
9968     /* VEX_W_0F3839_P_2 */
9969     { "vpminsd",        { XM, Vex, EXx } },
9970   },
9971   {
9972     /* VEX_W_0F383A_P_2 */
9973     { "vpminuw",        { XM, Vex, EXx } },
9974   },
9975   {
9976     /* VEX_W_0F383B_P_2 */
9977     { "vpminud",        { XM, Vex, EXx } },
9978   },
9979   {
9980     /* VEX_W_0F383C_P_2 */
9981     { "vpmaxsb",        { XM, Vex, EXx } },
9982   },
9983   {
9984     /* VEX_W_0F383D_P_2 */
9985     { "vpmaxsd",        { XM, Vex, EXx } },
9986   },
9987   {
9988     /* VEX_W_0F383E_P_2 */
9989     { "vpmaxuw",        { XM, Vex, EXx } },
9990   },
9991   {
9992     /* VEX_W_0F383F_P_2 */
9993     { "vpmaxud",        { XM, Vex, EXx } },
9994   },
9995   {
9996     /* VEX_W_0F3840_P_2 */
9997     { "vpmulld",        { XM, Vex, EXx } },
9998   },
9999   {
10000     /* VEX_W_0F3841_P_2 */
10001     { "vphminposuw",    { XM, EXx } },
10002   },
10003   {
10004     /* VEX_W_0F3846_P_2 */
10005     { "vpsravd",        { XM, Vex, EXx } },
10006   },
10007   {
10008     /* VEX_W_0F3858_P_2 */
10009     { "vpbroadcastd", { XM, EXxmm_md } },
10010   },
10011   {
10012     /* VEX_W_0F3859_P_2 */
10013     { "vpbroadcastq",   { XM, EXxmm_mq } },
10014   },
10015   {
10016     /* VEX_W_0F385A_P_2_M_0 */
10017     { "vbroadcasti128", { XM, Mxmm } },
10018   },
10019   {
10020     /* VEX_W_0F3878_P_2 */
10021     { "vpbroadcastb",   { XM, EXxmm_mb } },
10022   },
10023   {
10024     /* VEX_W_0F3879_P_2 */
10025     { "vpbroadcastw",   { XM, EXxmm_mw } },
10026   },
10027   {
10028     /* VEX_W_0F38DB_P_2 */
10029     { "vaesimc",        { XM, EXx } },
10030   },
10031   {
10032     /* VEX_W_0F38DC_P_2 */
10033     { "vaesenc",        { XM, Vex128, EXx } },
10034   },
10035   {
10036     /* VEX_W_0F38DD_P_2 */
10037     { "vaesenclast",    { XM, Vex128, EXx } },
10038   },
10039   {
10040     /* VEX_W_0F38DE_P_2 */
10041     { "vaesdec",        { XM, Vex128, EXx } },
10042   },
10043   {
10044     /* VEX_W_0F38DF_P_2 */
10045     { "vaesdeclast",    { XM, Vex128, EXx } },
10046   },
10047   {
10048     /* VEX_W_0F3A00_P_2 */
10049     { Bad_Opcode },
10050     { "vpermq",         { XM, EXx, Ib } },
10051   },
10052   {
10053     /* VEX_W_0F3A01_P_2 */
10054     { Bad_Opcode },
10055     { "vpermpd",        { XM, EXx, Ib } },
10056   },
10057   {
10058     /* VEX_W_0F3A02_P_2 */
10059     { "vpblendd",       { XM, Vex, EXx, Ib } },
10060   },
10061   {
10062     /* VEX_W_0F3A04_P_2 */
10063     { "vpermilps",      { XM, EXx, Ib } },
10064   },
10065   {
10066     /* VEX_W_0F3A05_P_2 */
10067     { "vpermilpd",      { XM, EXx, Ib } },
10068   },
10069   {
10070     /* VEX_W_0F3A06_P_2 */
10071     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10072   },
10073   {
10074     /* VEX_W_0F3A08_P_2 */
10075     { "vroundps",       { XM, EXx, Ib } },
10076   },
10077   {
10078     /* VEX_W_0F3A09_P_2 */
10079     { "vroundpd",       { XM, EXx, Ib } },
10080   },
10081   {
10082     /* VEX_W_0F3A0A_P_2 */
10083     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10084   },
10085   {
10086     /* VEX_W_0F3A0B_P_2 */
10087     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10088   },
10089   {
10090     /* VEX_W_0F3A0C_P_2 */
10091     { "vblendps",       { XM, Vex, EXx, Ib } },
10092   },
10093   {
10094     /* VEX_W_0F3A0D_P_2 */
10095     { "vblendpd",       { XM, Vex, EXx, Ib } },
10096   },
10097   {
10098     /* VEX_W_0F3A0E_P_2 */
10099     { "vpblendw",       { XM, Vex, EXx, Ib } },
10100   },
10101   {
10102     /* VEX_W_0F3A0F_P_2 */
10103     { "vpalignr",       { XM, Vex, EXx, Ib } },
10104   },
10105   {
10106     /* VEX_W_0F3A14_P_2 */
10107     { "vpextrb",        { Edqb, XM, Ib } },
10108   },
10109   {
10110     /* VEX_W_0F3A15_P_2 */
10111     { "vpextrw",        { Edqw, XM, Ib } },
10112   },
10113   {
10114     /* VEX_W_0F3A18_P_2 */
10115     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10116   },
10117   {
10118     /* VEX_W_0F3A19_P_2 */
10119     { "vextractf128",   { EXxmm, XM, Ib } },
10120   },
10121   {
10122     /* VEX_W_0F3A20_P_2 */
10123     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10124   },
10125   {
10126     /* VEX_W_0F3A21_P_2 */
10127     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10128   },
10129   {
10130     /* VEX_W_0F3A38_P_2 */
10131     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
10132   },
10133   {
10134     /* VEX_W_0F3A39_P_2 */
10135     { "vextracti128",   { EXxmm, XM, Ib } },
10136   },
10137   {
10138     /* VEX_W_0F3A40_P_2 */
10139     { "vdpps",          { XM, Vex, EXx, Ib } },
10140   },
10141   {
10142     /* VEX_W_0F3A41_P_2 */
10143     { "vdppd",          { XM, Vex128, EXx, Ib } },
10144   },
10145   {
10146     /* VEX_W_0F3A42_P_2 */
10147     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10148   },
10149   {
10150     /* VEX_W_0F3A44_P_2 */
10151     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10152   },
10153   {
10154     /* VEX_W_0F3A46_P_2 */
10155     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
10156   },
10157   {
10158     /* VEX_W_0F3A48_P_2 */
10159     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10160     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10161   },
10162   {
10163     /* VEX_W_0F3A49_P_2 */
10164     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10165     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10166   },
10167   {
10168     /* VEX_W_0F3A4A_P_2 */
10169     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10170   },
10171   {
10172     /* VEX_W_0F3A4B_P_2 */
10173     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10174   },
10175   {
10176     /* VEX_W_0F3A4C_P_2 */
10177     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
10178   },
10179   {
10180     /* VEX_W_0F3A60_P_2 */
10181     { "vpcmpestrm",     { XM, EXx, Ib } },
10182   },
10183   {
10184     /* VEX_W_0F3A61_P_2 */
10185     { "vpcmpestri",     { XM, EXx, Ib } },
10186   },
10187   {
10188     /* VEX_W_0F3A62_P_2 */
10189     { "vpcmpistrm",     { XM, EXx, Ib } },
10190   },
10191   {
10192     /* VEX_W_0F3A63_P_2 */
10193     { "vpcmpistri",     { XM, EXx, Ib } },
10194   },
10195   {
10196     /* VEX_W_0F3ADF_P_2 */
10197     { "vaeskeygenassist", { XM, EXx, Ib } },
10198   },
10199 };
10200
10201 static const struct dis386 mod_table[][2] = {
10202   {
10203     /* MOD_8D */
10204     { "leaS",           { Gv, M } },
10205   },
10206   {
10207     /* MOD_C6_REG_7 */
10208     { Bad_Opcode },
10209     { RM_TABLE (RM_C6_REG_7) },
10210   },
10211   {
10212     /* MOD_C7_REG_7 */
10213     { Bad_Opcode },
10214     { RM_TABLE (RM_C7_REG_7) },
10215   },
10216   {
10217     /* MOD_0F01_REG_0 */
10218     { X86_64_TABLE (X86_64_0F01_REG_0) },
10219     { RM_TABLE (RM_0F01_REG_0) },
10220   },
10221   {
10222     /* MOD_0F01_REG_1 */
10223     { X86_64_TABLE (X86_64_0F01_REG_1) },
10224     { RM_TABLE (RM_0F01_REG_1) },
10225   },
10226   {
10227     /* MOD_0F01_REG_2 */
10228     { X86_64_TABLE (X86_64_0F01_REG_2) },
10229     { RM_TABLE (RM_0F01_REG_2) },
10230   },
10231   {
10232     /* MOD_0F01_REG_3 */
10233     { X86_64_TABLE (X86_64_0F01_REG_3) },
10234     { RM_TABLE (RM_0F01_REG_3) },
10235   },
10236   {
10237     /* MOD_0F01_REG_7 */
10238     { "invlpg",         { Mb } },
10239     { RM_TABLE (RM_0F01_REG_7) },
10240   },
10241   {
10242     /* MOD_0F12_PREFIX_0 */
10243     { "movlps",         { XM, EXq } },
10244     { "movhlps",        { XM, EXq } },
10245   },
10246   {
10247     /* MOD_0F13 */
10248     { "movlpX",         { EXq, XM } },
10249   },
10250   {
10251     /* MOD_0F16_PREFIX_0 */
10252     { "movhps",         { XM, EXq } },
10253     { "movlhps",        { XM, EXq } },
10254   },
10255   {
10256     /* MOD_0F17 */
10257     { "movhpX",         { EXq, XM } },
10258   },
10259   {
10260     /* MOD_0F18_REG_0 */
10261     { "prefetchnta",    { Mb } },
10262   },
10263   {
10264     /* MOD_0F18_REG_1 */
10265     { "prefetcht0",     { Mb } },
10266   },
10267   {
10268     /* MOD_0F18_REG_2 */
10269     { "prefetcht1",     { Mb } },
10270   },
10271   {
10272     /* MOD_0F18_REG_3 */
10273     { "prefetcht2",     { Mb } },
10274   },
10275   {
10276     /* MOD_0F18_REG_4 */
10277     { "nop/reserved",   { Mb } },
10278   },
10279   {
10280     /* MOD_0F18_REG_5 */
10281     { "nop/reserved",   { Mb } },
10282   },
10283   {
10284     /* MOD_0F18_REG_6 */
10285     { "nop/reserved",   { Mb } },
10286   },
10287   {
10288     /* MOD_0F18_REG_7 */
10289     { "nop/reserved",   { Mb } },
10290   },
10291   {
10292     /* MOD_0F1A_PREFIX_0 */
10293     { "bndldx",         { Gbnd, Ev_bnd } },
10294     { "nopQ",           { Ev } },
10295   },
10296   {
10297     /* MOD_0F1B_PREFIX_0 */
10298     { "bndstx",         { Ev_bnd, Gbnd } },
10299     { "nopQ",           { Ev } },
10300   },
10301   {
10302     /* MOD_0F1B_PREFIX_1 */
10303     { "bndmk",          { Gbnd, Ev_bnd } },
10304     { "nopQ",           { Ev } },
10305   },
10306   {
10307     /* MOD_0F20 */
10308     { Bad_Opcode },
10309     { "movZ",           { Rm, Cm } },
10310   },
10311   {
10312     /* MOD_0F21 */
10313     { Bad_Opcode },
10314     { "movZ",           { Rm, Dm } },
10315   },
10316   {
10317     /* MOD_0F22 */
10318     { Bad_Opcode },
10319     { "movZ",           { Cm, Rm } },
10320   },
10321   {
10322     /* MOD_0F23 */
10323     { Bad_Opcode },
10324     { "movZ",           { Dm, Rm } },
10325   },
10326   {
10327     /* MOD_0F24 */
10328     { Bad_Opcode },
10329     { "movL",           { Rd, Td } },
10330   },
10331   {
10332     /* MOD_0F26 */
10333     { Bad_Opcode },
10334     { "movL",           { Td, Rd } },
10335   },
10336   {
10337     /* MOD_0F2B_PREFIX_0 */
10338     {"movntps",         { Mx, XM } },
10339   },
10340   {
10341     /* MOD_0F2B_PREFIX_1 */
10342     {"movntss",         { Md, XM } },
10343   },
10344   {
10345     /* MOD_0F2B_PREFIX_2 */
10346     {"movntpd",         { Mx, XM } },
10347   },
10348   {
10349     /* MOD_0F2B_PREFIX_3 */
10350     {"movntsd",         { Mq, XM } },
10351   },
10352   {
10353     /* MOD_0F51 */
10354     { Bad_Opcode },
10355     { "movmskpX",       { Gdq, XS } },
10356   },
10357   {
10358     /* MOD_0F71_REG_2 */
10359     { Bad_Opcode },
10360     { "psrlw",          { MS, Ib } },
10361   },
10362   {
10363     /* MOD_0F71_REG_4 */
10364     { Bad_Opcode },
10365     { "psraw",          { MS, Ib } },
10366   },
10367   {
10368     /* MOD_0F71_REG_6 */
10369     { Bad_Opcode },
10370     { "psllw",          { MS, Ib } },
10371   },
10372   {
10373     /* MOD_0F72_REG_2 */
10374     { Bad_Opcode },
10375     { "psrld",          { MS, Ib } },
10376   },
10377   {
10378     /* MOD_0F72_REG_4 */
10379     { Bad_Opcode },
10380     { "psrad",          { MS, Ib } },
10381   },
10382   {
10383     /* MOD_0F72_REG_6 */
10384     { Bad_Opcode },
10385     { "pslld",          { MS, Ib } },
10386   },
10387   {
10388     /* MOD_0F73_REG_2 */
10389     { Bad_Opcode },
10390     { "psrlq",          { MS, Ib } },
10391   },
10392   {
10393     /* MOD_0F73_REG_3 */
10394     { Bad_Opcode },
10395     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10396   },
10397   {
10398     /* MOD_0F73_REG_6 */
10399     { Bad_Opcode },
10400     { "psllq",          { MS, Ib } },
10401   },
10402   {
10403     /* MOD_0F73_REG_7 */
10404     { Bad_Opcode },
10405     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10406   },
10407   {
10408     /* MOD_0FAE_REG_0 */
10409     { "fxsave",         { FXSAVE } },
10410     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10411   },
10412   {
10413     /* MOD_0FAE_REG_1 */
10414     { "fxrstor",        { FXSAVE } },
10415     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10416   },
10417   {
10418     /* MOD_0FAE_REG_2 */
10419     { "ldmxcsr",        { Md } },
10420     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10421   },
10422   {
10423     /* MOD_0FAE_REG_3 */
10424     { "stmxcsr",        { Md } },
10425     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10426   },
10427   {
10428     /* MOD_0FAE_REG_4 */
10429     { "xsave",          { FXSAVE } },
10430   },
10431   {
10432     /* MOD_0FAE_REG_5 */
10433     { "xrstor",         { FXSAVE } },
10434     { RM_TABLE (RM_0FAE_REG_5) },
10435   },
10436   {
10437     /* MOD_0FAE_REG_6 */
10438     { "xsaveopt",       { FXSAVE } },
10439     { RM_TABLE (RM_0FAE_REG_6) },
10440   },
10441   {
10442     /* MOD_0FAE_REG_7 */
10443     { "clflush",        { Mb } },
10444     { RM_TABLE (RM_0FAE_REG_7) },
10445   },
10446   {
10447     /* MOD_0FB2 */
10448     { "lssS",           { Gv, Mp } },
10449   },
10450   {
10451     /* MOD_0FB4 */
10452     { "lfsS",           { Gv, Mp } },
10453   },
10454   {
10455     /* MOD_0FB5 */
10456     { "lgsS",           { Gv, Mp } },
10457   },
10458   {
10459     /* MOD_0FC7_REG_6 */
10460     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10461     { "rdrand",         { Ev } },
10462   },
10463   {
10464     /* MOD_0FC7_REG_7 */
10465     { "vmptrst",        { Mq } },
10466     { "rdseed",         { Ev } },
10467   },
10468   {
10469     /* MOD_0FD7 */
10470     { Bad_Opcode },
10471     { "pmovmskb",       { Gdq, MS } },
10472   },
10473   {
10474     /* MOD_0FE7_PREFIX_2 */
10475     { "movntdq",        { Mx, XM } },
10476   },
10477   {
10478     /* MOD_0FF0_PREFIX_3 */
10479     { "lddqu",          { XM, M } },
10480   },
10481   {
10482     /* MOD_0F382A_PREFIX_2 */
10483     { "movntdqa",       { XM, Mx } },
10484   },
10485   {
10486     /* MOD_62_32BIT */
10487     { "bound{S|}",      { Gv, Ma } },
10488   },
10489   {
10490     /* MOD_C4_32BIT */
10491     { "lesS",           { Gv, Mp } },
10492     { VEX_C4_TABLE (VEX_0F) },
10493   },
10494   {
10495     /* MOD_C5_32BIT */
10496     { "ldsS",           { Gv, Mp } },
10497     { VEX_C5_TABLE (VEX_0F) },
10498   },
10499   {
10500     /* MOD_VEX_0F12_PREFIX_0 */
10501     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10502     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10503   },
10504   {
10505     /* MOD_VEX_0F13 */
10506     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10507   },
10508   {
10509     /* MOD_VEX_0F16_PREFIX_0 */
10510     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10511     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10512   },
10513   {
10514     /* MOD_VEX_0F17 */
10515     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10516   },
10517   {
10518     /* MOD_VEX_0F2B */
10519     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10520   },
10521   {
10522     /* MOD_VEX_0F50 */
10523     { Bad_Opcode },
10524     { VEX_W_TABLE (VEX_W_0F50_M_0) },
10525   },
10526   {
10527     /* MOD_VEX_0F71_REG_2 */
10528     { Bad_Opcode },
10529     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10530   },
10531   {
10532     /* MOD_VEX_0F71_REG_4 */
10533     { Bad_Opcode },
10534     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10535   },
10536   {
10537     /* MOD_VEX_0F71_REG_6 */
10538     { Bad_Opcode },
10539     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10540   },
10541   {
10542     /* MOD_VEX_0F72_REG_2 */
10543     { Bad_Opcode },
10544     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10545   },
10546   {
10547     /* MOD_VEX_0F72_REG_4 */
10548     { Bad_Opcode },
10549     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10550   },
10551   {
10552     /* MOD_VEX_0F72_REG_6 */
10553     { Bad_Opcode },
10554     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10555   },
10556   {
10557     /* MOD_VEX_0F73_REG_2 */
10558     { Bad_Opcode },
10559     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10560   },
10561   {
10562     /* MOD_VEX_0F73_REG_3 */
10563     { Bad_Opcode },
10564     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10565   },
10566   {
10567     /* MOD_VEX_0F73_REG_6 */
10568     { Bad_Opcode },
10569     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10570   },
10571   {
10572     /* MOD_VEX_0F73_REG_7 */
10573     { Bad_Opcode },
10574     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10575   },
10576   {
10577     /* MOD_VEX_0FAE_REG_2 */
10578     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10579   },
10580   {
10581     /* MOD_VEX_0FAE_REG_3 */
10582     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10583   },
10584   {
10585     /* MOD_VEX_0FD7_PREFIX_2 */
10586     { Bad_Opcode },
10587     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
10588   },
10589   {
10590     /* MOD_VEX_0FE7_PREFIX_2 */
10591     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10592   },
10593   {
10594     /* MOD_VEX_0FF0_PREFIX_3 */
10595     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10596   },
10597   {
10598     /* MOD_VEX_0F381A_PREFIX_2 */
10599     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10600   },
10601   {
10602     /* MOD_VEX_0F382A_PREFIX_2 */
10603     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
10604   },
10605   {
10606     /* MOD_VEX_0F382C_PREFIX_2 */
10607     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10608   },
10609   {
10610     /* MOD_VEX_0F382D_PREFIX_2 */
10611     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10612   },
10613   {
10614     /* MOD_VEX_0F382E_PREFIX_2 */
10615     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10616   },
10617   {
10618     /* MOD_VEX_0F382F_PREFIX_2 */
10619     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10620   },
10621   {
10622     /* MOD_VEX_0F385A_PREFIX_2 */
10623     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10624   },
10625   {
10626     /* MOD_VEX_0F388C_PREFIX_2 */
10627     { "vpmaskmov%LW",   { XM, Vex, Mx } },
10628   },
10629   {
10630     /* MOD_VEX_0F388E_PREFIX_2 */
10631     { "vpmaskmov%LW",   { Mx, Vex, XM } },
10632   },
10633 };
10634
10635 static const struct dis386 rm_table[][8] = {
10636   {
10637     /* RM_C6_REG_7 */
10638     { "xabort",         { Skip_MODRM, Ib } },
10639   },
10640   {
10641     /* RM_C7_REG_7 */
10642     { "xbeginT",        { Skip_MODRM, Jv } },
10643   },
10644   {
10645     /* RM_0F01_REG_0 */
10646     { Bad_Opcode },
10647     { "vmcall",         { Skip_MODRM } },
10648     { "vmlaunch",       { Skip_MODRM } },
10649     { "vmresume",       { Skip_MODRM } },
10650     { "vmxoff",         { Skip_MODRM } },
10651   },
10652   {
10653     /* RM_0F01_REG_1 */
10654     { "monitor",        { { OP_Monitor, 0 } } },
10655     { "mwait",          { { OP_Mwait, 0 } } },
10656     { "clac",           { Skip_MODRM } },
10657     { "stac",           { Skip_MODRM } },
10658   },
10659   {
10660     /* RM_0F01_REG_2 */
10661     { "xgetbv",         { Skip_MODRM } },
10662     { "xsetbv",         { Skip_MODRM } },
10663     { Bad_Opcode },
10664     { Bad_Opcode },
10665     { "vmfunc",         { Skip_MODRM } },
10666     { "xend",           { Skip_MODRM } },
10667     { "xtest",          { Skip_MODRM } },
10668     { Bad_Opcode },
10669   },
10670   {
10671     /* RM_0F01_REG_3 */
10672     { "vmrun",          { Skip_MODRM } },
10673     { "vmmcall",        { Skip_MODRM } },
10674     { "vmload",         { Skip_MODRM } },
10675     { "vmsave",         { Skip_MODRM } },
10676     { "stgi",           { Skip_MODRM } },
10677     { "clgi",           { Skip_MODRM } },
10678     { "skinit",         { Skip_MODRM } },
10679     { "invlpga",        { Skip_MODRM } },
10680   },
10681   {
10682     /* RM_0F01_REG_7 */
10683     { "swapgs",         { Skip_MODRM } },
10684     { "rdtscp",         { Skip_MODRM } },
10685   },
10686   {
10687     /* RM_0FAE_REG_5 */
10688     { "lfence",         { Skip_MODRM } },
10689   },
10690   {
10691     /* RM_0FAE_REG_6 */
10692     { "mfence",         { Skip_MODRM } },
10693   },
10694   {
10695     /* RM_0FAE_REG_7 */
10696     { "sfence",         { Skip_MODRM } },
10697   },
10698 };
10699
10700 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10701
10702 /* We use the high bit to indicate different name for the same
10703    prefix.  */
10704 #define ADDR16_PREFIX   (0x67 | 0x100)
10705 #define ADDR32_PREFIX   (0x67 | 0x200)
10706 #define DATA16_PREFIX   (0x66 | 0x100)
10707 #define DATA32_PREFIX   (0x66 | 0x200)
10708 #define REP_PREFIX      (0xf3 | 0x100)
10709 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10710 #define XRELEASE_PREFIX (0xf3 | 0x400)
10711 #define BND_PREFIX      (0xf2 | 0x400)
10712
10713 static int
10714 ckprefix (void)
10715 {
10716   int newrex, i, length;
10717   rex = 0;
10718   rex_ignored = 0;
10719   prefixes = 0;
10720   used_prefixes = 0;
10721   rex_used = 0;
10722   last_lock_prefix = -1;
10723   last_repz_prefix = -1;
10724   last_repnz_prefix = -1;
10725   last_data_prefix = -1;
10726   last_addr_prefix = -1;
10727   last_rex_prefix = -1;
10728   last_seg_prefix = -1;
10729   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10730     all_prefixes[i] = 0;
10731   i = 0;
10732   length = 0;
10733   /* The maximum instruction length is 15bytes.  */
10734   while (length < MAX_CODE_LENGTH - 1)
10735     {
10736       FETCH_DATA (the_info, codep + 1);
10737       newrex = 0;
10738       switch (*codep)
10739         {
10740         /* REX prefixes family.  */
10741         case 0x40:
10742         case 0x41:
10743         case 0x42:
10744         case 0x43:
10745         case 0x44:
10746         case 0x45:
10747         case 0x46:
10748         case 0x47:
10749         case 0x48:
10750         case 0x49:
10751         case 0x4a:
10752         case 0x4b:
10753         case 0x4c:
10754         case 0x4d:
10755         case 0x4e:
10756         case 0x4f:
10757           if (address_mode == mode_64bit)
10758             newrex = *codep;
10759           else
10760             return 1;
10761           last_rex_prefix = i;
10762           break;
10763         case 0xf3:
10764           prefixes |= PREFIX_REPZ;
10765           last_repz_prefix = i;
10766           break;
10767         case 0xf2:
10768           prefixes |= PREFIX_REPNZ;
10769           last_repnz_prefix = i;
10770           break;
10771         case 0xf0:
10772           prefixes |= PREFIX_LOCK;
10773           last_lock_prefix = i;
10774           break;
10775         case 0x2e:
10776           prefixes |= PREFIX_CS;
10777           last_seg_prefix = i;
10778           break;
10779         case 0x36:
10780           prefixes |= PREFIX_SS;
10781           last_seg_prefix = i;
10782           break;
10783         case 0x3e:
10784           prefixes |= PREFIX_DS;
10785           last_seg_prefix = i;
10786           break;
10787         case 0x26:
10788           prefixes |= PREFIX_ES;
10789           last_seg_prefix = i;
10790           break;
10791         case 0x64:
10792           prefixes |= PREFIX_FS;
10793           last_seg_prefix = i;
10794           break;
10795         case 0x65:
10796           prefixes |= PREFIX_GS;
10797           last_seg_prefix = i;
10798           break;
10799         case 0x66:
10800           prefixes |= PREFIX_DATA;
10801           last_data_prefix = i;
10802           break;
10803         case 0x67:
10804           prefixes |= PREFIX_ADDR;
10805           last_addr_prefix = i;
10806           break;
10807         case FWAIT_OPCODE:
10808           /* fwait is really an instruction.  If there are prefixes
10809              before the fwait, they belong to the fwait, *not* to the
10810              following instruction.  */
10811           if (prefixes || rex)
10812             {
10813               prefixes |= PREFIX_FWAIT;
10814               codep++;
10815               /* This ensures that the previous REX prefixes are noticed
10816                  as unused prefixes, as in the return case below.  */
10817               rex_used = rex;
10818               return 1;
10819             }
10820           prefixes = PREFIX_FWAIT;
10821           break;
10822         default:
10823           return 1;
10824         }
10825       /* Rex is ignored when followed by another prefix.  */
10826       if (rex)
10827         {
10828           rex_used = rex;
10829           return 1;
10830         }
10831       if (*codep != FWAIT_OPCODE)
10832         all_prefixes[i++] = *codep;
10833       rex = newrex;
10834       codep++;
10835       length++;
10836     }
10837   return 0;
10838 }
10839
10840 static int
10841 seg_prefix (int pref)
10842 {
10843   switch (pref)
10844     {
10845     case 0x2e:
10846       return PREFIX_CS;
10847     case 0x36:
10848       return PREFIX_SS;
10849     case 0x3e:
10850       return PREFIX_DS;
10851     case 0x26:
10852       return PREFIX_ES;
10853     case 0x64:
10854       return PREFIX_FS;
10855     case 0x65:
10856       return PREFIX_GS;
10857     default:
10858       return 0;
10859     }
10860 }
10861
10862 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10863    prefix byte.  */
10864
10865 static const char *
10866 prefix_name (int pref, int sizeflag)
10867 {
10868   static const char *rexes [16] =
10869     {
10870       "rex",            /* 0x40 */
10871       "rex.B",          /* 0x41 */
10872       "rex.X",          /* 0x42 */
10873       "rex.XB",         /* 0x43 */
10874       "rex.R",          /* 0x44 */
10875       "rex.RB",         /* 0x45 */
10876       "rex.RX",         /* 0x46 */
10877       "rex.RXB",        /* 0x47 */
10878       "rex.W",          /* 0x48 */
10879       "rex.WB",         /* 0x49 */
10880       "rex.WX",         /* 0x4a */
10881       "rex.WXB",        /* 0x4b */
10882       "rex.WR",         /* 0x4c */
10883       "rex.WRB",        /* 0x4d */
10884       "rex.WRX",        /* 0x4e */
10885       "rex.WRXB",       /* 0x4f */
10886     };
10887
10888   switch (pref)
10889     {
10890     /* REX prefixes family.  */
10891     case 0x40:
10892     case 0x41:
10893     case 0x42:
10894     case 0x43:
10895     case 0x44:
10896     case 0x45:
10897     case 0x46:
10898     case 0x47:
10899     case 0x48:
10900     case 0x49:
10901     case 0x4a:
10902     case 0x4b:
10903     case 0x4c:
10904     case 0x4d:
10905     case 0x4e:
10906     case 0x4f:
10907       return rexes [pref - 0x40];
10908     case 0xf3:
10909       return "repz";
10910     case 0xf2:
10911       return "repnz";
10912     case 0xf0:
10913       return "lock";
10914     case 0x2e:
10915       return "cs";
10916     case 0x36:
10917       return "ss";
10918     case 0x3e:
10919       return "ds";
10920     case 0x26:
10921       return "es";
10922     case 0x64:
10923       return "fs";
10924     case 0x65:
10925       return "gs";
10926     case 0x66:
10927       return (sizeflag & DFLAG) ? "data16" : "data32";
10928     case 0x67:
10929       if (address_mode == mode_64bit)
10930         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10931       else
10932         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10933     case FWAIT_OPCODE:
10934       return "fwait";
10935     case ADDR16_PREFIX:
10936       return "addr16";
10937     case ADDR32_PREFIX:
10938       return "addr32";
10939     case DATA16_PREFIX:
10940       return "data16";
10941     case DATA32_PREFIX:
10942       return "data32";
10943     case REP_PREFIX:
10944       return "rep";
10945     case XACQUIRE_PREFIX:
10946       return "xacquire";
10947     case XRELEASE_PREFIX:
10948       return "xrelease";
10949     case BND_PREFIX:
10950       return "bnd";
10951     default:
10952       return NULL;
10953     }
10954 }
10955
10956 static char op_out[MAX_OPERANDS][100];
10957 static int op_ad, op_index[MAX_OPERANDS];
10958 static int two_source_ops;
10959 static bfd_vma op_address[MAX_OPERANDS];
10960 static bfd_vma op_riprel[MAX_OPERANDS];
10961 static bfd_vma start_pc;
10962
10963 /*
10964  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10965  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10966  *   section of the "Virtual 8086 Mode" chapter.)
10967  * 'pc' should be the address of this instruction, it will
10968  *   be used to print the target address if this is a relative jump or call
10969  * The function returns the length of this instruction in bytes.
10970  */
10971
10972 static char intel_syntax;
10973 static char intel_mnemonic = !SYSV386_COMPAT;
10974 static char open_char;
10975 static char close_char;
10976 static char separator_char;
10977 static char scale_char;
10978
10979 /* Here for backwards compatibility.  When gdb stops using
10980    print_insn_i386_att and print_insn_i386_intel these functions can
10981    disappear, and print_insn_i386 be merged into print_insn.  */
10982 int
10983 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10984 {
10985   intel_syntax = 0;
10986
10987   return print_insn (pc, info);
10988 }
10989
10990 int
10991 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10992 {
10993   intel_syntax = 1;
10994
10995   return print_insn (pc, info);
10996 }
10997
10998 int
10999 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11000 {
11001   intel_syntax = -1;
11002
11003   return print_insn (pc, info);
11004 }
11005
11006 void
11007 print_i386_disassembler_options (FILE *stream)
11008 {
11009   fprintf (stream, _("\n\
11010 The following i386/x86-64 specific disassembler options are supported for use\n\
11011 with the -M switch (multiple options should be separated by commas):\n"));
11012
11013   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11014   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11015   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11016   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11017   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11018   fprintf (stream, _("  att-mnemonic\n"
11019                      "              Display instruction in AT&T mnemonic\n"));
11020   fprintf (stream, _("  intel-mnemonic\n"
11021                      "              Display instruction in Intel mnemonic\n"));
11022   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11023   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11024   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11025   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11026   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11027   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11028 }
11029
11030 /* Bad opcode.  */
11031 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11032
11033 /* Get a pointer to struct dis386 with a valid name.  */
11034
11035 static const struct dis386 *
11036 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11037 {
11038   int vindex, vex_table_index;
11039
11040   if (dp->name != NULL)
11041     return dp;
11042
11043   switch (dp->op[0].bytemode)
11044     {
11045     case USE_REG_TABLE:
11046       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11047       break;
11048
11049     case USE_MOD_TABLE:
11050       vindex = modrm.mod == 0x3 ? 1 : 0;
11051       dp = &mod_table[dp->op[1].bytemode][vindex];
11052       break;
11053
11054     case USE_RM_TABLE:
11055       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11056       break;
11057
11058     case USE_PREFIX_TABLE:
11059       if (need_vex)
11060         {
11061           /* The prefix in VEX is implicit.  */
11062           switch (vex.prefix)
11063             {
11064             case 0:
11065               vindex = 0;
11066               break;
11067             case REPE_PREFIX_OPCODE:
11068               vindex = 1;
11069               break;
11070             case DATA_PREFIX_OPCODE:
11071               vindex = 2;
11072               break;
11073             case REPNE_PREFIX_OPCODE:
11074               vindex = 3;
11075               break;
11076             default:
11077               abort ();
11078               break;
11079             }
11080         }
11081       else
11082         {
11083           vindex = 0;
11084           used_prefixes |= (prefixes & PREFIX_REPZ);
11085           if (prefixes & PREFIX_REPZ)
11086             {
11087               vindex = 1;
11088               all_prefixes[last_repz_prefix] = 0;
11089             }
11090           else
11091             {
11092               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11093                  PREFIX_DATA.  */
11094               used_prefixes |= (prefixes & PREFIX_REPNZ);
11095               if (prefixes & PREFIX_REPNZ)
11096                 {
11097                   vindex = 3;
11098                   all_prefixes[last_repnz_prefix] = 0;
11099                 }
11100               else
11101                 {
11102                   used_prefixes |= (prefixes & PREFIX_DATA);
11103                   if (prefixes & PREFIX_DATA)
11104                     {
11105                       vindex = 2;
11106                       all_prefixes[last_data_prefix] = 0;
11107                     }
11108                 }
11109             }
11110         }
11111       dp = &prefix_table[dp->op[1].bytemode][vindex];
11112       break;
11113
11114     case USE_X86_64_TABLE:
11115       vindex = address_mode == mode_64bit ? 1 : 0;
11116       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11117       break;
11118
11119     case USE_3BYTE_TABLE:
11120       FETCH_DATA (info, codep + 2);
11121       vindex = *codep++;
11122       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11123       modrm.mod = (*codep >> 6) & 3;
11124       modrm.reg = (*codep >> 3) & 7;
11125       modrm.rm = *codep & 7;
11126       break;
11127
11128     case USE_VEX_LEN_TABLE:
11129       if (!need_vex)
11130         abort ();
11131
11132       switch (vex.length)
11133         {
11134         case 128:
11135           vindex = 0;
11136           break;
11137         case 256:
11138           vindex = 1;
11139           break;
11140         default:
11141           abort ();
11142           break;
11143         }
11144
11145       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11146       break;
11147
11148     case USE_XOP_8F_TABLE:
11149       FETCH_DATA (info, codep + 3);
11150       /* All bits in the REX prefix are ignored.  */
11151       rex_ignored = rex;
11152       rex = ~(*codep >> 5) & 0x7;
11153
11154       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11155       switch ((*codep & 0x1f))
11156         {
11157         default:
11158           dp = &bad_opcode;
11159           return dp;
11160         case 0x8:
11161           vex_table_index = XOP_08;
11162           break;
11163         case 0x9:
11164           vex_table_index = XOP_09;
11165           break;
11166         case 0xa:
11167           vex_table_index = XOP_0A;
11168           break;
11169         }
11170       codep++;
11171       vex.w = *codep & 0x80;
11172       if (vex.w && address_mode == mode_64bit)
11173         rex |= REX_W;
11174
11175       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11176       if (address_mode != mode_64bit
11177           && vex.register_specifier > 0x7)
11178         {
11179           dp = &bad_opcode;
11180           return dp;
11181         }
11182
11183       vex.length = (*codep & 0x4) ? 256 : 128;
11184       switch ((*codep & 0x3))
11185         {
11186         case 0:
11187           vex.prefix = 0;
11188           break;
11189         case 1:
11190           vex.prefix = DATA_PREFIX_OPCODE;
11191           break;
11192         case 2:
11193           vex.prefix = REPE_PREFIX_OPCODE;
11194           break;
11195         case 3:
11196           vex.prefix = REPNE_PREFIX_OPCODE;
11197           break;
11198         }
11199       need_vex = 1;
11200       need_vex_reg = 1;
11201       codep++;
11202       vindex = *codep++;
11203       dp = &xop_table[vex_table_index][vindex];
11204
11205       FETCH_DATA (info, codep + 1);
11206       modrm.mod = (*codep >> 6) & 3;
11207       modrm.reg = (*codep >> 3) & 7;
11208       modrm.rm = *codep & 7;
11209       break;
11210
11211     case USE_VEX_C4_TABLE:
11212       FETCH_DATA (info, codep + 3);
11213       /* All bits in the REX prefix are ignored.  */
11214       rex_ignored = rex;
11215       rex = ~(*codep >> 5) & 0x7;
11216       switch ((*codep & 0x1f))
11217         {
11218         default:
11219           dp = &bad_opcode;
11220           return dp;
11221         case 0x1:
11222           vex_table_index = VEX_0F;
11223           break;
11224         case 0x2:
11225           vex_table_index = VEX_0F38;
11226           break;
11227         case 0x3:
11228           vex_table_index = VEX_0F3A;
11229           break;
11230         }
11231       codep++;
11232       vex.w = *codep & 0x80;
11233       if (vex.w && address_mode == mode_64bit)
11234         rex |= REX_W;
11235
11236       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11237       if (address_mode != mode_64bit
11238           && vex.register_specifier > 0x7)
11239         {
11240           dp = &bad_opcode;
11241           return dp;
11242         }
11243
11244       vex.length = (*codep & 0x4) ? 256 : 128;
11245       switch ((*codep & 0x3))
11246         {
11247         case 0:
11248           vex.prefix = 0;
11249           break;
11250         case 1:
11251           vex.prefix = DATA_PREFIX_OPCODE;
11252           break;
11253         case 2:
11254           vex.prefix = REPE_PREFIX_OPCODE;
11255           break;
11256         case 3:
11257           vex.prefix = REPNE_PREFIX_OPCODE;
11258           break;
11259         }
11260       need_vex = 1;
11261       need_vex_reg = 1;
11262       codep++;
11263       vindex = *codep++;
11264       dp = &vex_table[vex_table_index][vindex];
11265       /* There is no MODRM byte for VEX [82|77].  */
11266       if (vindex != 0x77 && vindex != 0x82)
11267         {
11268           FETCH_DATA (info, codep + 1);
11269           modrm.mod = (*codep >> 6) & 3;
11270           modrm.reg = (*codep >> 3) & 7;
11271           modrm.rm = *codep & 7;
11272         }
11273       break;
11274
11275     case USE_VEX_C5_TABLE:
11276       FETCH_DATA (info, codep + 2);
11277       /* All bits in the REX prefix are ignored.  */
11278       rex_ignored = rex;
11279       rex = (*codep & 0x80) ? 0 : REX_R;
11280
11281       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11282       if (address_mode != mode_64bit
11283           && vex.register_specifier > 0x7)
11284         {
11285           dp = &bad_opcode;
11286           return dp;
11287         }
11288
11289       vex.w = 0;
11290
11291       vex.length = (*codep & 0x4) ? 256 : 128;
11292       switch ((*codep & 0x3))
11293         {
11294         case 0:
11295           vex.prefix = 0;
11296           break;
11297         case 1:
11298           vex.prefix = DATA_PREFIX_OPCODE;
11299           break;
11300         case 2:
11301           vex.prefix = REPE_PREFIX_OPCODE;
11302           break;
11303         case 3:
11304           vex.prefix = REPNE_PREFIX_OPCODE;
11305           break;
11306         }
11307       need_vex = 1;
11308       need_vex_reg = 1;
11309       codep++;
11310       vindex = *codep++;
11311       dp = &vex_table[dp->op[1].bytemode][vindex];
11312       /* There is no MODRM byte for VEX [82|77].  */
11313       if (vindex != 0x77 && vindex != 0x82)
11314         {
11315           FETCH_DATA (info, codep + 1);
11316           modrm.mod = (*codep >> 6) & 3;
11317           modrm.reg = (*codep >> 3) & 7;
11318           modrm.rm = *codep & 7;
11319         }
11320       break;
11321
11322     case USE_VEX_W_TABLE:
11323       if (!need_vex)
11324         abort ();
11325
11326       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11327       break;
11328
11329     case 0:
11330       dp = &bad_opcode;
11331       break;
11332
11333     default:
11334       abort ();
11335     }
11336
11337   if (dp->name != NULL)
11338     return dp;
11339   else
11340     return get_valid_dis386 (dp, info);
11341 }
11342
11343 static void
11344 get_sib (disassemble_info *info, int sizeflag)
11345 {
11346   /* If modrm.mod == 3, operand must be register.  */
11347   if (need_modrm
11348       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11349       && modrm.mod != 3
11350       && modrm.rm == 4)
11351     {
11352       FETCH_DATA (info, codep + 2);
11353       sib.index = (codep [1] >> 3) & 7;
11354       sib.scale = (codep [1] >> 6) & 3;
11355       sib.base = codep [1] & 7;
11356     }
11357 }
11358
11359 static int
11360 print_insn (bfd_vma pc, disassemble_info *info)
11361 {
11362   const struct dis386 *dp;
11363   int i;
11364   char *op_txt[MAX_OPERANDS];
11365   int needcomma;
11366   int sizeflag;
11367   const char *p;
11368   struct dis_private priv;
11369   int prefix_length;
11370   int default_prefixes;
11371
11372   priv.orig_sizeflag = AFLAG | DFLAG;
11373   if ((info->mach & bfd_mach_i386_i386) != 0)
11374     address_mode = mode_32bit;
11375   else if (info->mach == bfd_mach_i386_i8086)
11376     {
11377       address_mode = mode_16bit;
11378       priv.orig_sizeflag = 0;
11379     }
11380   else
11381     address_mode = mode_64bit;
11382
11383   if (intel_syntax == (char) -1)
11384     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11385
11386   for (p = info->disassembler_options; p != NULL; )
11387     {
11388       if (CONST_STRNEQ (p, "x86-64"))
11389         {
11390           address_mode = mode_64bit;
11391           priv.orig_sizeflag = AFLAG | DFLAG;
11392         }
11393       else if (CONST_STRNEQ (p, "i386"))
11394         {
11395           address_mode = mode_32bit;
11396           priv.orig_sizeflag = AFLAG | DFLAG;
11397         }
11398       else if (CONST_STRNEQ (p, "i8086"))
11399         {
11400           address_mode = mode_16bit;
11401           priv.orig_sizeflag = 0;
11402         }
11403       else if (CONST_STRNEQ (p, "intel"))
11404         {
11405           intel_syntax = 1;
11406           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11407             intel_mnemonic = 1;
11408         }
11409       else if (CONST_STRNEQ (p, "att"))
11410         {
11411           intel_syntax = 0;
11412           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11413             intel_mnemonic = 0;
11414         }
11415       else if (CONST_STRNEQ (p, "addr"))
11416         {
11417           if (address_mode == mode_64bit)
11418             {
11419               if (p[4] == '3' && p[5] == '2')
11420                 priv.orig_sizeflag &= ~AFLAG;
11421               else if (p[4] == '6' && p[5] == '4')
11422                 priv.orig_sizeflag |= AFLAG;
11423             }
11424           else
11425             {
11426               if (p[4] == '1' && p[5] == '6')
11427                 priv.orig_sizeflag &= ~AFLAG;
11428               else if (p[4] == '3' && p[5] == '2')
11429                 priv.orig_sizeflag |= AFLAG;
11430             }
11431         }
11432       else if (CONST_STRNEQ (p, "data"))
11433         {
11434           if (p[4] == '1' && p[5] == '6')
11435             priv.orig_sizeflag &= ~DFLAG;
11436           else if (p[4] == '3' && p[5] == '2')
11437             priv.orig_sizeflag |= DFLAG;
11438         }
11439       else if (CONST_STRNEQ (p, "suffix"))
11440         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11441
11442       p = strchr (p, ',');
11443       if (p != NULL)
11444         p++;
11445     }
11446
11447   if (intel_syntax)
11448     {
11449       names64 = intel_names64;
11450       names32 = intel_names32;
11451       names16 = intel_names16;
11452       names8 = intel_names8;
11453       names8rex = intel_names8rex;
11454       names_seg = intel_names_seg;
11455       names_mm = intel_names_mm;
11456       names_bnd = intel_names_bnd;
11457       names_xmm = intel_names_xmm;
11458       names_ymm = intel_names_ymm;
11459       index64 = intel_index64;
11460       index32 = intel_index32;
11461       index16 = intel_index16;
11462       open_char = '[';
11463       close_char = ']';
11464       separator_char = '+';
11465       scale_char = '*';
11466     }
11467   else
11468     {
11469       names64 = att_names64;
11470       names32 = att_names32;
11471       names16 = att_names16;
11472       names8 = att_names8;
11473       names8rex = att_names8rex;
11474       names_seg = att_names_seg;
11475       names_mm = att_names_mm;
11476       names_bnd = att_names_bnd;
11477       names_xmm = att_names_xmm;
11478       names_ymm = att_names_ymm;
11479       index64 = att_index64;
11480       index32 = att_index32;
11481       index16 = att_index16;
11482       open_char = '(';
11483       close_char =  ')';
11484       separator_char = ',';
11485       scale_char = ',';
11486     }
11487
11488   /* The output looks better if we put 7 bytes on a line, since that
11489      puts most long word instructions on a single line.  Use 8 bytes
11490      for Intel L1OM.  */
11491   if ((info->mach & bfd_mach_l1om) != 0)
11492     info->bytes_per_line = 8;
11493   else
11494     info->bytes_per_line = 7;
11495
11496   info->private_data = &priv;
11497   priv.max_fetched = priv.the_buffer;
11498   priv.insn_start = pc;
11499
11500   obuf[0] = 0;
11501   for (i = 0; i < MAX_OPERANDS; ++i)
11502     {
11503       op_out[i][0] = 0;
11504       op_index[i] = -1;
11505     }
11506
11507   the_info = info;
11508   start_pc = pc;
11509   start_codep = priv.the_buffer;
11510   codep = priv.the_buffer;
11511
11512   if (setjmp (priv.bailout) != 0)
11513     {
11514       const char *name;
11515
11516       /* Getting here means we tried for data but didn't get it.  That
11517          means we have an incomplete instruction of some sort.  Just
11518          print the first byte as a prefix or a .byte pseudo-op.  */
11519       if (codep > priv.the_buffer)
11520         {
11521           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11522           if (name != NULL)
11523             (*info->fprintf_func) (info->stream, "%s", name);
11524           else
11525             {
11526               /* Just print the first byte as a .byte instruction.  */
11527               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11528                                      (unsigned int) priv.the_buffer[0]);
11529             }
11530
11531           return 1;
11532         }
11533
11534       return -1;
11535     }
11536
11537   obufp = obuf;
11538   sizeflag = priv.orig_sizeflag;
11539
11540   if (!ckprefix () || rex_used)
11541     {
11542       /* Too many prefixes or unused REX prefixes.  */
11543       for (i = 0;
11544            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11545            i++)
11546         (*info->fprintf_func) (info->stream, "%s%s",
11547                                i == 0 ? "" : " ",
11548                                prefix_name (all_prefixes[i], sizeflag));
11549       return i;
11550     }
11551
11552   insn_codep = codep;
11553
11554   FETCH_DATA (info, codep + 1);
11555   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11556
11557   if (((prefixes & PREFIX_FWAIT)
11558        && ((*codep < 0xd8) || (*codep > 0xdf))))
11559     {
11560       (*info->fprintf_func) (info->stream, "fwait");
11561       return 1;
11562     }
11563
11564   if (*codep == 0x0f)
11565     {
11566       unsigned char threebyte;
11567       FETCH_DATA (info, codep + 2);
11568       threebyte = *++codep;
11569       dp = &dis386_twobyte[threebyte];
11570       need_modrm = twobyte_has_modrm[*codep];
11571       codep++;
11572     }
11573   else
11574     {
11575       dp = &dis386[*codep];
11576       need_modrm = onebyte_has_modrm[*codep];
11577       codep++;
11578     }
11579
11580   if ((prefixes & PREFIX_REPZ))
11581     used_prefixes |= PREFIX_REPZ;
11582   if ((prefixes & PREFIX_REPNZ))
11583     used_prefixes |= PREFIX_REPNZ;
11584   if ((prefixes & PREFIX_LOCK))
11585     used_prefixes |= PREFIX_LOCK;
11586
11587   default_prefixes = 0;
11588   if (prefixes & PREFIX_ADDR)
11589     {
11590       sizeflag ^= AFLAG;
11591       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11592         {
11593           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11594             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11595           else
11596             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11597           default_prefixes |= PREFIX_ADDR;
11598         }
11599     }
11600
11601   if ((prefixes & PREFIX_DATA))
11602     {
11603       sizeflag ^= DFLAG;
11604       if (dp->op[2].bytemode == cond_jump_mode
11605           && dp->op[0].bytemode == v_mode
11606           && !intel_syntax)
11607         {
11608           if (sizeflag & DFLAG)
11609             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11610           else
11611             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11612           default_prefixes |= PREFIX_DATA;
11613         }
11614       else if (rex & REX_W)
11615         {
11616           /* REX_W will override PREFIX_DATA.  */
11617           default_prefixes |= PREFIX_DATA;
11618         }
11619     }
11620
11621   if (need_modrm)
11622     {
11623       FETCH_DATA (info, codep + 1);
11624       modrm.mod = (*codep >> 6) & 3;
11625       modrm.reg = (*codep >> 3) & 7;
11626       modrm.rm = *codep & 7;
11627     }
11628
11629   need_vex = 0;
11630   need_vex_reg = 0;
11631   vex_w_done = 0;
11632
11633   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11634     {
11635       get_sib (info, sizeflag);
11636       dofloat (sizeflag);
11637     }
11638   else
11639     {
11640       dp = get_valid_dis386 (dp, info);
11641       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11642         {
11643           get_sib (info, sizeflag);
11644           for (i = 0; i < MAX_OPERANDS; ++i)
11645             {
11646               obufp = op_out[i];
11647               op_ad = MAX_OPERANDS - 1 - i;
11648               if (dp->op[i].rtn)
11649                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11650             }
11651         }
11652     }
11653
11654   /* See if any prefixes were not used.  If so, print the first one
11655      separately.  If we don't do this, we'll wind up printing an
11656      instruction stream which does not precisely correspond to the
11657      bytes we are disassembling.  */
11658   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11659     {
11660       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11661         if (all_prefixes[i])
11662           {
11663             const char *name;
11664             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11665             if (name == NULL)
11666               name = INTERNAL_DISASSEMBLER_ERROR;
11667             (*info->fprintf_func) (info->stream, "%s", name);
11668             return 1;
11669           }
11670     }
11671
11672   /* Check if the REX prefix is used.  */
11673   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11674     all_prefixes[last_rex_prefix] = 0;
11675
11676   /* Check if the SEG prefix is used.  */
11677   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11678                    | PREFIX_FS | PREFIX_GS)) != 0
11679       && (used_prefixes
11680           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11681     all_prefixes[last_seg_prefix] = 0;
11682
11683   /* Check if the ADDR prefix is used.  */
11684   if ((prefixes & PREFIX_ADDR) != 0
11685       && (used_prefixes & PREFIX_ADDR) != 0)
11686     all_prefixes[last_addr_prefix] = 0;
11687
11688   /* Check if the DATA prefix is used.  */
11689   if ((prefixes & PREFIX_DATA) != 0
11690       && (used_prefixes & PREFIX_DATA) != 0)
11691     all_prefixes[last_data_prefix] = 0;
11692
11693   prefix_length = 0;
11694   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11695     if (all_prefixes[i])
11696       {
11697         const char *name;
11698         name = prefix_name (all_prefixes[i], sizeflag);
11699         if (name == NULL)
11700           abort ();
11701         prefix_length += strlen (name) + 1;
11702         (*info->fprintf_func) (info->stream, "%s ", name);
11703       }
11704
11705   /* Check maximum code length.  */
11706   if ((codep - start_codep) > MAX_CODE_LENGTH)
11707     {
11708       (*info->fprintf_func) (info->stream, "(bad)");
11709       return MAX_CODE_LENGTH;
11710     }
11711
11712   obufp = mnemonicendp;
11713   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11714     oappend (" ");
11715   oappend (" ");
11716   (*info->fprintf_func) (info->stream, "%s", obuf);
11717
11718   /* The enter and bound instructions are printed with operands in the same
11719      order as the intel book; everything else is printed in reverse order.  */
11720   if (intel_syntax || two_source_ops)
11721     {
11722       bfd_vma riprel;
11723
11724       for (i = 0; i < MAX_OPERANDS; ++i)
11725         op_txt[i] = op_out[i];
11726
11727       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11728         {
11729           op_ad = op_index[i];
11730           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11731           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11732           riprel = op_riprel[i];
11733           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11734           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11735         }
11736     }
11737   else
11738     {
11739       for (i = 0; i < MAX_OPERANDS; ++i)
11740         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11741     }
11742
11743   needcomma = 0;
11744   for (i = 0; i < MAX_OPERANDS; ++i)
11745     if (*op_txt[i])
11746       {
11747         if (needcomma)
11748           (*info->fprintf_func) (info->stream, ",");
11749         if (op_index[i] != -1 && !op_riprel[i])
11750           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11751         else
11752           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11753         needcomma = 1;
11754       }
11755
11756   for (i = 0; i < MAX_OPERANDS; i++)
11757     if (op_index[i] != -1 && op_riprel[i])
11758       {
11759         (*info->fprintf_func) (info->stream, "        # ");
11760         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11761                                                 + op_address[op_index[i]]), info);
11762         break;
11763       }
11764   return codep - priv.the_buffer;
11765 }
11766
11767 static const char *float_mem[] = {
11768   /* d8 */
11769   "fadd{s|}",
11770   "fmul{s|}",
11771   "fcom{s|}",
11772   "fcomp{s|}",
11773   "fsub{s|}",
11774   "fsubr{s|}",
11775   "fdiv{s|}",
11776   "fdivr{s|}",
11777   /* d9 */
11778   "fld{s|}",
11779   "(bad)",
11780   "fst{s|}",
11781   "fstp{s|}",
11782   "fldenvIC",
11783   "fldcw",
11784   "fNstenvIC",
11785   "fNstcw",
11786   /* da */
11787   "fiadd{l|}",
11788   "fimul{l|}",
11789   "ficom{l|}",
11790   "ficomp{l|}",
11791   "fisub{l|}",
11792   "fisubr{l|}",
11793   "fidiv{l|}",
11794   "fidivr{l|}",
11795   /* db */
11796   "fild{l|}",
11797   "fisttp{l|}",
11798   "fist{l|}",
11799   "fistp{l|}",
11800   "(bad)",
11801   "fld{t||t|}",
11802   "(bad)",
11803   "fstp{t||t|}",
11804   /* dc */
11805   "fadd{l|}",
11806   "fmul{l|}",
11807   "fcom{l|}",
11808   "fcomp{l|}",
11809   "fsub{l|}",
11810   "fsubr{l|}",
11811   "fdiv{l|}",
11812   "fdivr{l|}",
11813   /* dd */
11814   "fld{l|}",
11815   "fisttp{ll|}",
11816   "fst{l||}",
11817   "fstp{l|}",
11818   "frstorIC",
11819   "(bad)",
11820   "fNsaveIC",
11821   "fNstsw",
11822   /* de */
11823   "fiadd",
11824   "fimul",
11825   "ficom",
11826   "ficomp",
11827   "fisub",
11828   "fisubr",
11829   "fidiv",
11830   "fidivr",
11831   /* df */
11832   "fild",
11833   "fisttp",
11834   "fist",
11835   "fistp",
11836   "fbld",
11837   "fild{ll|}",
11838   "fbstp",
11839   "fistp{ll|}",
11840 };
11841
11842 static const unsigned char float_mem_mode[] = {
11843   /* d8 */
11844   d_mode,
11845   d_mode,
11846   d_mode,
11847   d_mode,
11848   d_mode,
11849   d_mode,
11850   d_mode,
11851   d_mode,
11852   /* d9 */
11853   d_mode,
11854   0,
11855   d_mode,
11856   d_mode,
11857   0,
11858   w_mode,
11859   0,
11860   w_mode,
11861   /* da */
11862   d_mode,
11863   d_mode,
11864   d_mode,
11865   d_mode,
11866   d_mode,
11867   d_mode,
11868   d_mode,
11869   d_mode,
11870   /* db */
11871   d_mode,
11872   d_mode,
11873   d_mode,
11874   d_mode,
11875   0,
11876   t_mode,
11877   0,
11878   t_mode,
11879   /* dc */
11880   q_mode,
11881   q_mode,
11882   q_mode,
11883   q_mode,
11884   q_mode,
11885   q_mode,
11886   q_mode,
11887   q_mode,
11888   /* dd */
11889   q_mode,
11890   q_mode,
11891   q_mode,
11892   q_mode,
11893   0,
11894   0,
11895   0,
11896   w_mode,
11897   /* de */
11898   w_mode,
11899   w_mode,
11900   w_mode,
11901   w_mode,
11902   w_mode,
11903   w_mode,
11904   w_mode,
11905   w_mode,
11906   /* df */
11907   w_mode,
11908   w_mode,
11909   w_mode,
11910   w_mode,
11911   t_mode,
11912   q_mode,
11913   t_mode,
11914   q_mode
11915 };
11916
11917 #define ST { OP_ST, 0 }
11918 #define STi { OP_STi, 0 }
11919
11920 #define FGRPd9_2 NULL, { { NULL, 0 } }
11921 #define FGRPd9_4 NULL, { { NULL, 1 } }
11922 #define FGRPd9_5 NULL, { { NULL, 2 } }
11923 #define FGRPd9_6 NULL, { { NULL, 3 } }
11924 #define FGRPd9_7 NULL, { { NULL, 4 } }
11925 #define FGRPda_5 NULL, { { NULL, 5 } }
11926 #define FGRPdb_4 NULL, { { NULL, 6 } }
11927 #define FGRPde_3 NULL, { { NULL, 7 } }
11928 #define FGRPdf_4 NULL, { { NULL, 8 } }
11929
11930 static const struct dis386 float_reg[][8] = {
11931   /* d8 */
11932   {
11933     { "fadd",   { ST, STi } },
11934     { "fmul",   { ST, STi } },
11935     { "fcom",   { STi } },
11936     { "fcomp",  { STi } },
11937     { "fsub",   { ST, STi } },
11938     { "fsubr",  { ST, STi } },
11939     { "fdiv",   { ST, STi } },
11940     { "fdivr",  { ST, STi } },
11941   },
11942   /* d9 */
11943   {
11944     { "fld",    { STi } },
11945     { "fxch",   { STi } },
11946     { FGRPd9_2 },
11947     { Bad_Opcode },
11948     { FGRPd9_4 },
11949     { FGRPd9_5 },
11950     { FGRPd9_6 },
11951     { FGRPd9_7 },
11952   },
11953   /* da */
11954   {
11955     { "fcmovb", { ST, STi } },
11956     { "fcmove", { ST, STi } },
11957     { "fcmovbe",{ ST, STi } },
11958     { "fcmovu", { ST, STi } },
11959     { Bad_Opcode },
11960     { FGRPda_5 },
11961     { Bad_Opcode },
11962     { Bad_Opcode },
11963   },
11964   /* db */
11965   {
11966     { "fcmovnb",{ ST, STi } },
11967     { "fcmovne",{ ST, STi } },
11968     { "fcmovnbe",{ ST, STi } },
11969     { "fcmovnu",{ ST, STi } },
11970     { FGRPdb_4 },
11971     { "fucomi", { ST, STi } },
11972     { "fcomi",  { ST, STi } },
11973     { Bad_Opcode },
11974   },
11975   /* dc */
11976   {
11977     { "fadd",   { STi, ST } },
11978     { "fmul",   { STi, ST } },
11979     { Bad_Opcode },
11980     { Bad_Opcode },
11981     { "fsub!M", { STi, ST } },
11982     { "fsubM",  { STi, ST } },
11983     { "fdiv!M", { STi, ST } },
11984     { "fdivM",  { STi, ST } },
11985   },
11986   /* dd */
11987   {
11988     { "ffree",  { STi } },
11989     { Bad_Opcode },
11990     { "fst",    { STi } },
11991     { "fstp",   { STi } },
11992     { "fucom",  { STi } },
11993     { "fucomp", { STi } },
11994     { Bad_Opcode },
11995     { Bad_Opcode },
11996   },
11997   /* de */
11998   {
11999     { "faddp",  { STi, ST } },
12000     { "fmulp",  { STi, ST } },
12001     { Bad_Opcode },
12002     { FGRPde_3 },
12003     { "fsub!Mp", { STi, ST } },
12004     { "fsubMp", { STi, ST } },
12005     { "fdiv!Mp", { STi, ST } },
12006     { "fdivMp", { STi, ST } },
12007   },
12008   /* df */
12009   {
12010     { "ffreep", { STi } },
12011     { Bad_Opcode },
12012     { Bad_Opcode },
12013     { Bad_Opcode },
12014     { FGRPdf_4 },
12015     { "fucomip", { ST, STi } },
12016     { "fcomip", { ST, STi } },
12017     { Bad_Opcode },
12018   },
12019 };
12020
12021 static char *fgrps[][8] = {
12022   /* d9_2  0 */
12023   {
12024     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12025   },
12026
12027   /* d9_4  1 */
12028   {
12029     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12030   },
12031
12032   /* d9_5  2 */
12033   {
12034     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12035   },
12036
12037   /* d9_6  3 */
12038   {
12039     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12040   },
12041
12042   /* d9_7  4 */
12043   {
12044     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12045   },
12046
12047   /* da_5  5 */
12048   {
12049     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12050   },
12051
12052   /* db_4  6 */
12053   {
12054     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12055     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12056   },
12057
12058   /* de_3  7 */
12059   {
12060     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12061   },
12062
12063   /* df_4  8 */
12064   {
12065     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12066   },
12067 };
12068
12069 static void
12070 swap_operand (void)
12071 {
12072   mnemonicendp[0] = '.';
12073   mnemonicendp[1] = 's';
12074   mnemonicendp += 2;
12075 }
12076
12077 static void
12078 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12079                int sizeflag ATTRIBUTE_UNUSED)
12080 {
12081   /* Skip mod/rm byte.  */
12082   MODRM_CHECK;
12083   codep++;
12084 }
12085
12086 static void
12087 dofloat (int sizeflag)
12088 {
12089   const struct dis386 *dp;
12090   unsigned char floatop;
12091
12092   floatop = codep[-1];
12093
12094   if (modrm.mod != 3)
12095     {
12096       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12097
12098       putop (float_mem[fp_indx], sizeflag);
12099       obufp = op_out[0];
12100       op_ad = 2;
12101       OP_E (float_mem_mode[fp_indx], sizeflag);
12102       return;
12103     }
12104   /* Skip mod/rm byte.  */
12105   MODRM_CHECK;
12106   codep++;
12107
12108   dp = &float_reg[floatop - 0xd8][modrm.reg];
12109   if (dp->name == NULL)
12110     {
12111       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12112
12113       /* Instruction fnstsw is only one with strange arg.  */
12114       if (floatop == 0xdf && codep[-1] == 0xe0)
12115         strcpy (op_out[0], names16[0]);
12116     }
12117   else
12118     {
12119       putop (dp->name, sizeflag);
12120
12121       obufp = op_out[0];
12122       op_ad = 2;
12123       if (dp->op[0].rtn)
12124         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12125
12126       obufp = op_out[1];
12127       op_ad = 1;
12128       if (dp->op[1].rtn)
12129         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12130     }
12131 }
12132
12133 static void
12134 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12135 {
12136   oappend ("%st" + intel_syntax);
12137 }
12138
12139 static void
12140 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12141 {
12142   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12143   oappend (scratchbuf + intel_syntax);
12144 }
12145
12146 /* Capital letters in template are macros.  */
12147 static int
12148 putop (const char *in_template, int sizeflag)
12149 {
12150   const char *p;
12151   int alt = 0;
12152   int cond = 1;
12153   unsigned int l = 0, len = 1;
12154   char last[4];
12155
12156 #define SAVE_LAST(c)                    \
12157   if (l < len && l < sizeof (last))     \
12158     last[l++] = c;                      \
12159   else                                  \
12160     abort ();
12161
12162   for (p = in_template; *p; p++)
12163     {
12164       switch (*p)
12165         {
12166         default:
12167           *obufp++ = *p;
12168           break;
12169         case '%':
12170           len++;
12171           break;
12172         case '!':
12173           cond = 0;
12174           break;
12175         case '{':
12176           alt = 0;
12177           if (intel_syntax)
12178             {
12179               while (*++p != '|')
12180                 if (*p == '}' || *p == '\0')
12181                   abort ();
12182             }
12183           /* Fall through.  */
12184         case 'I':
12185           alt = 1;
12186           continue;
12187         case '|':
12188           while (*++p != '}')
12189             {
12190               if (*p == '\0')
12191                 abort ();
12192             }
12193           break;
12194         case '}':
12195           break;
12196         case 'A':
12197           if (intel_syntax)
12198             break;
12199           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12200             *obufp++ = 'b';
12201           break;
12202         case 'B':
12203           if (l == 0 && len == 1)
12204             {
12205 case_B:
12206               if (intel_syntax)
12207                 break;
12208               if (sizeflag & SUFFIX_ALWAYS)
12209                 *obufp++ = 'b';
12210             }
12211           else
12212             {
12213               if (l != 1
12214                   || len != 2
12215                   || last[0] != 'L')
12216                 {
12217                   SAVE_LAST (*p);
12218                   break;
12219                 }
12220
12221               if (address_mode == mode_64bit
12222                   && !(prefixes & PREFIX_ADDR))
12223                 {
12224                   *obufp++ = 'a';
12225                   *obufp++ = 'b';
12226                   *obufp++ = 's';
12227                 }
12228
12229               goto case_B;
12230             }
12231           break;
12232         case 'C':
12233           if (intel_syntax && !alt)
12234             break;
12235           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12236             {
12237               if (sizeflag & DFLAG)
12238                 *obufp++ = intel_syntax ? 'd' : 'l';
12239               else
12240                 *obufp++ = intel_syntax ? 'w' : 's';
12241               used_prefixes |= (prefixes & PREFIX_DATA);
12242             }
12243           break;
12244         case 'D':
12245           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12246             break;
12247           USED_REX (REX_W);
12248           if (modrm.mod == 3)
12249             {
12250               if (rex & REX_W)
12251                 *obufp++ = 'q';
12252               else
12253                 {
12254                   if (sizeflag & DFLAG)
12255                     *obufp++ = intel_syntax ? 'd' : 'l';
12256                   else
12257                     *obufp++ = 'w';
12258                   used_prefixes |= (prefixes & PREFIX_DATA);
12259                 }
12260             }
12261           else
12262             *obufp++ = 'w';
12263           break;
12264         case 'E':               /* For jcxz/jecxz */
12265           if (address_mode == mode_64bit)
12266             {
12267               if (sizeflag & AFLAG)
12268                 *obufp++ = 'r';
12269               else
12270                 *obufp++ = 'e';
12271             }
12272           else
12273             if (sizeflag & AFLAG)
12274               *obufp++ = 'e';
12275           used_prefixes |= (prefixes & PREFIX_ADDR);
12276           break;
12277         case 'F':
12278           if (intel_syntax)
12279             break;
12280           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12281             {
12282               if (sizeflag & AFLAG)
12283                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12284               else
12285                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12286               used_prefixes |= (prefixes & PREFIX_ADDR);
12287             }
12288           break;
12289         case 'G':
12290           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12291             break;
12292           if ((rex & REX_W) || (sizeflag & DFLAG))
12293             *obufp++ = 'l';
12294           else
12295             *obufp++ = 'w';
12296           if (!(rex & REX_W))
12297             used_prefixes |= (prefixes & PREFIX_DATA);
12298           break;
12299         case 'H':
12300           if (intel_syntax)
12301             break;
12302           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12303               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12304             {
12305               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12306               *obufp++ = ',';
12307               *obufp++ = 'p';
12308               if (prefixes & PREFIX_DS)
12309                 *obufp++ = 't';
12310               else
12311                 *obufp++ = 'n';
12312             }
12313           break;
12314         case 'J':
12315           if (intel_syntax)
12316             break;
12317           *obufp++ = 'l';
12318           break;
12319         case 'K':
12320           USED_REX (REX_W);
12321           if (rex & REX_W)
12322             *obufp++ = 'q';
12323           else
12324             *obufp++ = 'd';
12325           break;
12326         case 'Z':
12327           if (intel_syntax)
12328             break;
12329           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12330             {
12331               *obufp++ = 'q';
12332               break;
12333             }
12334           /* Fall through.  */
12335           goto case_L;
12336         case 'L':
12337           if (l != 0 || len != 1)
12338             {
12339               SAVE_LAST (*p);
12340               break;
12341             }
12342 case_L:
12343           if (intel_syntax)
12344             break;
12345           if (sizeflag & SUFFIX_ALWAYS)
12346             *obufp++ = 'l';
12347           break;
12348         case 'M':
12349           if (intel_mnemonic != cond)
12350             *obufp++ = 'r';
12351           break;
12352         case 'N':
12353           if ((prefixes & PREFIX_FWAIT) == 0)
12354             *obufp++ = 'n';
12355           else
12356             used_prefixes |= PREFIX_FWAIT;
12357           break;
12358         case 'O':
12359           USED_REX (REX_W);
12360           if (rex & REX_W)
12361             *obufp++ = 'o';
12362           else if (intel_syntax && (sizeflag & DFLAG))
12363             *obufp++ = 'q';
12364           else
12365             *obufp++ = 'd';
12366           if (!(rex & REX_W))
12367             used_prefixes |= (prefixes & PREFIX_DATA);
12368           break;
12369         case 'T':
12370           if (!intel_syntax
12371               && address_mode == mode_64bit
12372               && ((sizeflag & DFLAG) || (rex & REX_W)))
12373             {
12374               *obufp++ = 'q';
12375               break;
12376             }
12377           /* Fall through.  */
12378         case 'P':
12379           if (intel_syntax)
12380             {
12381               if ((rex & REX_W) == 0
12382                   && (prefixes & PREFIX_DATA))
12383                 {
12384                   if ((sizeflag & DFLAG) == 0)
12385                     *obufp++ = 'w';
12386                    used_prefixes |= (prefixes & PREFIX_DATA);
12387                 }
12388               break;
12389             }
12390           if ((prefixes & PREFIX_DATA)
12391               || (rex & REX_W)
12392               || (sizeflag & SUFFIX_ALWAYS))
12393             {
12394               USED_REX (REX_W);
12395               if (rex & REX_W)
12396                 *obufp++ = 'q';
12397               else
12398                 {
12399                    if (sizeflag & DFLAG)
12400                       *obufp++ = 'l';
12401                    else
12402                      *obufp++ = 'w';
12403                    used_prefixes |= (prefixes & PREFIX_DATA);
12404                 }
12405             }
12406           break;
12407         case 'U':
12408           if (intel_syntax)
12409             break;
12410           if (address_mode == mode_64bit
12411               && ((sizeflag & DFLAG) || (rex & REX_W)))
12412             {
12413               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12414                 *obufp++ = 'q';
12415               break;
12416             }
12417           /* Fall through.  */
12418           goto case_Q;
12419         case 'Q':
12420           if (l == 0 && len == 1)
12421             {
12422 case_Q:
12423               if (intel_syntax && !alt)
12424                 break;
12425               USED_REX (REX_W);
12426               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12427                 {
12428                   if (rex & REX_W)
12429                     *obufp++ = 'q';
12430                   else
12431                     {
12432                       if (sizeflag & DFLAG)
12433                         *obufp++ = intel_syntax ? 'd' : 'l';
12434                       else
12435                         *obufp++ = 'w';
12436                       used_prefixes |= (prefixes & PREFIX_DATA);
12437                     }
12438                 }
12439             }
12440           else
12441             {
12442               if (l != 1 || len != 2 || last[0] != 'L')
12443                 {
12444                   SAVE_LAST (*p);
12445                   break;
12446                 }
12447               if (intel_syntax
12448                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12449                 break;
12450               if ((rex & REX_W))
12451                 {
12452                   USED_REX (REX_W);
12453                   *obufp++ = 'q';
12454                 }
12455               else
12456                 *obufp++ = 'l';
12457             }
12458           break;
12459         case 'R':
12460           USED_REX (REX_W);
12461           if (rex & REX_W)
12462             *obufp++ = 'q';
12463           else if (sizeflag & DFLAG)
12464             {
12465               if (intel_syntax)
12466                   *obufp++ = 'd';
12467               else
12468                   *obufp++ = 'l';
12469             }
12470           else
12471             *obufp++ = 'w';
12472           if (intel_syntax && !p[1]
12473               && ((rex & REX_W) || (sizeflag & DFLAG)))
12474             *obufp++ = 'e';
12475           if (!(rex & REX_W))
12476             used_prefixes |= (prefixes & PREFIX_DATA);
12477           break;
12478         case 'V':
12479           if (l == 0 && len == 1)
12480             {
12481               if (intel_syntax)
12482                 break;
12483               if (address_mode == mode_64bit
12484                   && ((sizeflag & DFLAG) || (rex & REX_W)))
12485                 {
12486                   if (sizeflag & SUFFIX_ALWAYS)
12487                     *obufp++ = 'q';
12488                   break;
12489                 }
12490             }
12491           else
12492             {
12493               if (l != 1
12494                   || len != 2
12495                   || last[0] != 'L')
12496                 {
12497                   SAVE_LAST (*p);
12498                   break;
12499                 }
12500
12501               if (rex & REX_W)
12502                 {
12503                   *obufp++ = 'a';
12504                   *obufp++ = 'b';
12505                   *obufp++ = 's';
12506                 }
12507             }
12508           /* Fall through.  */
12509           goto case_S;
12510         case 'S':
12511           if (l == 0 && len == 1)
12512             {
12513 case_S:
12514               if (intel_syntax)
12515                 break;
12516               if (sizeflag & SUFFIX_ALWAYS)
12517                 {
12518                   if (rex & REX_W)
12519                     *obufp++ = 'q';
12520                   else
12521                     {
12522                       if (sizeflag & DFLAG)
12523                         *obufp++ = 'l';
12524                       else
12525                         *obufp++ = 'w';
12526                       used_prefixes |= (prefixes & PREFIX_DATA);
12527                     }
12528                 }
12529             }
12530           else
12531             {
12532               if (l != 1
12533                   || len != 2
12534                   || last[0] != 'L')
12535                 {
12536                   SAVE_LAST (*p);
12537                   break;
12538                 }
12539
12540               if (address_mode == mode_64bit
12541                   && !(prefixes & PREFIX_ADDR))
12542                 {
12543                   *obufp++ = 'a';
12544                   *obufp++ = 'b';
12545                   *obufp++ = 's';
12546                 }
12547
12548               goto case_S;
12549             }
12550           break;
12551         case 'X':
12552           if (l != 0 || len != 1)
12553             {
12554               SAVE_LAST (*p);
12555               break;
12556             }
12557           if (need_vex && vex.prefix)
12558             {
12559               if (vex.prefix == DATA_PREFIX_OPCODE)
12560                 *obufp++ = 'd';
12561               else
12562                 *obufp++ = 's';
12563             }
12564           else
12565             {
12566               if (prefixes & PREFIX_DATA)
12567                 *obufp++ = 'd';
12568               else
12569                 *obufp++ = 's';
12570               used_prefixes |= (prefixes & PREFIX_DATA);
12571             }
12572           break;
12573         case 'Y':
12574           if (l == 0 && len == 1)
12575             {
12576               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12577                 break;
12578               if (rex & REX_W)
12579                 {
12580                   USED_REX (REX_W);
12581                   *obufp++ = 'q';
12582                 }
12583               break;
12584             }
12585           else
12586             {
12587               if (l != 1 || len != 2 || last[0] != 'X')
12588                 {
12589                   SAVE_LAST (*p);
12590                   break;
12591                 }
12592               if (!need_vex)
12593                 abort ();
12594               if (intel_syntax
12595                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12596                 break;
12597               switch (vex.length)
12598                 {
12599                 case 128:
12600                   *obufp++ = 'x';
12601                   break;
12602                 case 256:
12603                   *obufp++ = 'y';
12604                   break;
12605                 default:
12606                   abort ();
12607                 }
12608             }
12609           break;
12610         case 'W':
12611           if (l == 0 && len == 1)
12612             {
12613               /* operand size flag for cwtl, cbtw */
12614               USED_REX (REX_W);
12615               if (rex & REX_W)
12616                 {
12617                   if (intel_syntax)
12618                     *obufp++ = 'd';
12619                   else
12620                     *obufp++ = 'l';
12621                 }
12622               else if (sizeflag & DFLAG)
12623                 *obufp++ = 'w';
12624               else
12625                 *obufp++ = 'b';
12626               if (!(rex & REX_W))
12627                 used_prefixes |= (prefixes & PREFIX_DATA);
12628             }
12629           else
12630             {
12631               if (l != 1
12632                   || len != 2
12633                   || (last[0] != 'X'
12634                       && last[0] != 'L'))
12635                 {
12636                   SAVE_LAST (*p);
12637                   break;
12638                 }
12639               if (!need_vex)
12640                 abort ();
12641               if (last[0] == 'X')
12642                 *obufp++ = vex.w ? 'd': 's';
12643               else
12644                 *obufp++ = vex.w ? 'q': 'd';
12645             }
12646           break;
12647         }
12648       alt = 0;
12649     }
12650   *obufp = 0;
12651   mnemonicendp = obufp;
12652   return 0;
12653 }
12654
12655 static void
12656 oappend (const char *s)
12657 {
12658   obufp = stpcpy (obufp, s);
12659 }
12660
12661 static void
12662 append_seg (void)
12663 {
12664   if (prefixes & PREFIX_CS)
12665     {
12666       used_prefixes |= PREFIX_CS;
12667       oappend ("%cs:" + intel_syntax);
12668     }
12669   if (prefixes & PREFIX_DS)
12670     {
12671       used_prefixes |= PREFIX_DS;
12672       oappend ("%ds:" + intel_syntax);
12673     }
12674   if (prefixes & PREFIX_SS)
12675     {
12676       used_prefixes |= PREFIX_SS;
12677       oappend ("%ss:" + intel_syntax);
12678     }
12679   if (prefixes & PREFIX_ES)
12680     {
12681       used_prefixes |= PREFIX_ES;
12682       oappend ("%es:" + intel_syntax);
12683     }
12684   if (prefixes & PREFIX_FS)
12685     {
12686       used_prefixes |= PREFIX_FS;
12687       oappend ("%fs:" + intel_syntax);
12688     }
12689   if (prefixes & PREFIX_GS)
12690     {
12691       used_prefixes |= PREFIX_GS;
12692       oappend ("%gs:" + intel_syntax);
12693     }
12694 }
12695
12696 static void
12697 OP_indirE (int bytemode, int sizeflag)
12698 {
12699   if (!intel_syntax)
12700     oappend ("*");
12701   OP_E (bytemode, sizeflag);
12702 }
12703
12704 static void
12705 print_operand_value (char *buf, int hex, bfd_vma disp)
12706 {
12707   if (address_mode == mode_64bit)
12708     {
12709       if (hex)
12710         {
12711           char tmp[30];
12712           int i;
12713           buf[0] = '0';
12714           buf[1] = 'x';
12715           sprintf_vma (tmp, disp);
12716           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12717           strcpy (buf + 2, tmp + i);
12718         }
12719       else
12720         {
12721           bfd_signed_vma v = disp;
12722           char tmp[30];
12723           int i;
12724           if (v < 0)
12725             {
12726               *(buf++) = '-';
12727               v = -disp;
12728               /* Check for possible overflow on 0x8000000000000000.  */
12729               if (v < 0)
12730                 {
12731                   strcpy (buf, "9223372036854775808");
12732                   return;
12733                 }
12734             }
12735           if (!v)
12736             {
12737               strcpy (buf, "0");
12738               return;
12739             }
12740
12741           i = 0;
12742           tmp[29] = 0;
12743           while (v)
12744             {
12745               tmp[28 - i] = (v % 10) + '0';
12746               v /= 10;
12747               i++;
12748             }
12749           strcpy (buf, tmp + 29 - i);
12750         }
12751     }
12752   else
12753     {
12754       if (hex)
12755         sprintf (buf, "0x%x", (unsigned int) disp);
12756       else
12757         sprintf (buf, "%d", (int) disp);
12758     }
12759 }
12760
12761 /* Put DISP in BUF as signed hex number.  */
12762
12763 static void
12764 print_displacement (char *buf, bfd_vma disp)
12765 {
12766   bfd_signed_vma val = disp;
12767   char tmp[30];
12768   int i, j = 0;
12769
12770   if (val < 0)
12771     {
12772       buf[j++] = '-';
12773       val = -disp;
12774
12775       /* Check for possible overflow.  */
12776       if (val < 0)
12777         {
12778           switch (address_mode)
12779             {
12780             case mode_64bit:
12781               strcpy (buf + j, "0x8000000000000000");
12782               break;
12783             case mode_32bit:
12784               strcpy (buf + j, "0x80000000");
12785               break;
12786             case mode_16bit:
12787               strcpy (buf + j, "0x8000");
12788               break;
12789             }
12790           return;
12791         }
12792     }
12793
12794   buf[j++] = '0';
12795   buf[j++] = 'x';
12796
12797   sprintf_vma (tmp, (bfd_vma) val);
12798   for (i = 0; tmp[i] == '0'; i++)
12799     continue;
12800   if (tmp[i] == '\0')
12801     i--;
12802   strcpy (buf + j, tmp + i);
12803 }
12804
12805 static void
12806 intel_operand_size (int bytemode, int sizeflag)
12807 {
12808   switch (bytemode)
12809     {
12810     case b_mode:
12811     case b_swap_mode:
12812     case dqb_mode:
12813       oappend ("BYTE PTR ");
12814       break;
12815     case w_mode:
12816     case dqw_mode:
12817       oappend ("WORD PTR ");
12818       break;
12819     case stack_v_mode:
12820       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
12821         {
12822           oappend ("QWORD PTR ");
12823           break;
12824         }
12825       /* FALLTHRU */
12826     case v_mode:
12827     case v_bnd_mode:
12828     case v_swap_mode:
12829     case dq_mode:
12830       USED_REX (REX_W);
12831       if (rex & REX_W)
12832         oappend ("QWORD PTR ");
12833       else
12834         {
12835           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12836             oappend ("DWORD PTR ");
12837           else
12838             oappend ("WORD PTR ");
12839           used_prefixes |= (prefixes & PREFIX_DATA);
12840         }
12841       break;
12842     case z_mode:
12843       if ((rex & REX_W) || (sizeflag & DFLAG))
12844         *obufp++ = 'D';
12845       oappend ("WORD PTR ");
12846       if (!(rex & REX_W))
12847         used_prefixes |= (prefixes & PREFIX_DATA);
12848       break;
12849     case a_mode:
12850       if (sizeflag & DFLAG)
12851         oappend ("QWORD PTR ");
12852       else
12853         oappend ("DWORD PTR ");
12854       used_prefixes |= (prefixes & PREFIX_DATA);
12855       break;
12856     case d_mode:
12857     case d_scalar_mode:
12858     case d_scalar_swap_mode:
12859     case d_swap_mode:
12860     case dqd_mode:
12861       oappend ("DWORD PTR ");
12862       break;
12863     case q_mode:
12864     case q_scalar_mode:
12865     case q_scalar_swap_mode:
12866     case q_swap_mode:
12867       oappend ("QWORD PTR ");
12868       break;
12869     case m_mode:
12870       if (address_mode == mode_64bit)
12871         oappend ("QWORD PTR ");
12872       else
12873         oappend ("DWORD PTR ");
12874       break;
12875     case f_mode:
12876       if (sizeflag & DFLAG)
12877         oappend ("FWORD PTR ");
12878       else
12879         oappend ("DWORD PTR ");
12880       used_prefixes |= (prefixes & PREFIX_DATA);
12881       break;
12882     case t_mode:
12883       oappend ("TBYTE PTR ");
12884       break;
12885     case x_mode:
12886     case x_swap_mode:
12887       if (need_vex)
12888         {
12889           switch (vex.length)
12890             {
12891             case 128:
12892               oappend ("XMMWORD PTR ");
12893               break;
12894             case 256:
12895               oappend ("YMMWORD PTR ");
12896               break;
12897             default:
12898               abort ();
12899             }
12900         }
12901       else
12902         oappend ("XMMWORD PTR ");
12903       break;
12904     case xmm_mode:
12905       oappend ("XMMWORD PTR ");
12906       break;
12907     case xmmq_mode:
12908       if (!need_vex)
12909         abort ();
12910
12911       switch (vex.length)
12912         {
12913         case 128:
12914           oappend ("QWORD PTR ");
12915           break;
12916         case 256:
12917           oappend ("XMMWORD PTR ");
12918           break;
12919         default:
12920           abort ();
12921         }
12922       break;
12923     case xmm_mb_mode:
12924       if (!need_vex)
12925         abort ();
12926
12927       switch (vex.length)
12928         {
12929         case 128:
12930         case 256:
12931           oappend ("BYTE PTR ");
12932           break;
12933         default:
12934           abort ();
12935         }
12936       break;
12937     case xmm_mw_mode:
12938       if (!need_vex)
12939         abort ();
12940
12941       switch (vex.length)
12942         {
12943         case 128:
12944         case 256:
12945           oappend ("WORD PTR ");
12946           break;
12947         default:
12948           abort ();
12949         }
12950       break;
12951     case xmm_md_mode:
12952       if (!need_vex)
12953         abort ();
12954
12955       switch (vex.length)
12956         {
12957         case 128:
12958         case 256:
12959           oappend ("DWORD PTR ");
12960           break;
12961         default:
12962           abort ();
12963         }
12964       break;
12965     case xmm_mq_mode:
12966       if (!need_vex)
12967         abort ();
12968
12969       switch (vex.length)
12970         {
12971         case 128:
12972         case 256:
12973           oappend ("QWORD PTR ");
12974           break;
12975         default:
12976           abort ();
12977         }
12978       break;
12979     case xmmdw_mode:
12980       if (!need_vex)
12981         abort ();
12982
12983       switch (vex.length)
12984         {
12985         case 128:
12986           oappend ("WORD PTR ");
12987           break;
12988         case 256:
12989           oappend ("DWORD PTR ");
12990           break;
12991         default:
12992           abort ();
12993         }
12994       break;
12995     case xmmqd_mode:
12996       if (!need_vex)
12997         abort ();
12998
12999       switch (vex.length)
13000         {
13001         case 128:
13002           oappend ("DWORD PTR ");
13003           break;
13004         case 256:
13005           oappend ("QWORD PTR ");
13006           break;
13007         default:
13008           abort ();
13009         }
13010       break;
13011     case ymmq_mode:
13012       if (!need_vex)
13013         abort ();
13014
13015       switch (vex.length)
13016         {
13017         case 128:
13018           oappend ("QWORD PTR ");
13019           break;
13020         case 256:
13021           oappend ("YMMWORD PTR ");
13022           break;
13023         default:
13024           abort ();
13025         }
13026       break;
13027     case ymmxmm_mode:
13028       if (!need_vex)
13029         abort ();
13030
13031       switch (vex.length)
13032         {
13033         case 128:
13034         case 256:
13035           oappend ("XMMWORD PTR ");
13036           break;
13037         default:
13038           abort ();
13039         }
13040       break;
13041     case o_mode:
13042       oappend ("OWORD PTR ");
13043       break;
13044     case vex_w_dq_mode:
13045     case vex_scalar_w_dq_mode:
13046     case vex_vsib_d_w_dq_mode:
13047     case vex_vsib_q_w_dq_mode:
13048       if (!need_vex)
13049         abort ();
13050
13051       if (vex.w)
13052         oappend ("QWORD PTR ");
13053       else
13054         oappend ("DWORD PTR ");
13055       break;
13056     default:
13057       break;
13058     }
13059 }
13060
13061 static void
13062 OP_E_register (int bytemode, int sizeflag)
13063 {
13064   int reg = modrm.rm;
13065   const char **names;
13066
13067   USED_REX (REX_B);
13068   if ((rex & REX_B))
13069     reg += 8;
13070
13071   if ((sizeflag & SUFFIX_ALWAYS)
13072       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
13073     swap_operand ();
13074
13075   switch (bytemode)
13076     {
13077     case b_mode:
13078     case b_swap_mode:
13079       USED_REX (0);
13080       if (rex)
13081         names = names8rex;
13082       else
13083         names = names8;
13084       break;
13085     case w_mode:
13086       names = names16;
13087       break;
13088     case d_mode:
13089       names = names32;
13090       break;
13091     case q_mode:
13092       names = names64;
13093       break;
13094     case m_mode:
13095       names = address_mode == mode_64bit ? names64 : names32;
13096       break;
13097     case bnd_mode:
13098       names = names_bnd;
13099       break;
13100     case stack_v_mode:
13101       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13102         {
13103           names = names64;
13104           break;
13105         }
13106       bytemode = v_mode;
13107       /* FALLTHRU */
13108     case v_mode:
13109     case v_bnd_mode:
13110     case v_swap_mode:
13111     case dq_mode:
13112     case dqb_mode:
13113     case dqd_mode:
13114     case dqw_mode:
13115       USED_REX (REX_W);
13116       if (rex & REX_W)
13117         names = names64;
13118       else
13119         {
13120           if ((sizeflag & DFLAG)
13121               || (bytemode != v_mode
13122                   && bytemode != v_swap_mode))
13123             names = names32;
13124           else
13125             names = names16;
13126           used_prefixes |= (prefixes & PREFIX_DATA);
13127         }
13128       break;
13129     case 0:
13130       return;
13131     default:
13132       oappend (INTERNAL_DISASSEMBLER_ERROR);
13133       return;
13134     }
13135   oappend (names[reg]);
13136 }
13137
13138 static void
13139 OP_E_memory (int bytemode, int sizeflag)
13140 {
13141   bfd_vma disp = 0;
13142   int add = (rex & REX_B) ? 8 : 0;
13143   int riprel = 0;
13144
13145   USED_REX (REX_B);
13146   if (intel_syntax)
13147     intel_operand_size (bytemode, sizeflag);
13148   append_seg ();
13149
13150   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13151     {
13152       /* 32/64 bit address mode */
13153       int havedisp;
13154       int havesib;
13155       int havebase;
13156       int haveindex;
13157       int needindex;
13158       int base, rbase;
13159       int vindex = 0;
13160       int scale = 0;
13161       int addr32flag = !((sizeflag & AFLAG)
13162                          || bytemode == v_bnd_mode
13163                          || bytemode == bnd_mode);
13164       const char **indexes64 = names64;
13165       const char **indexes32 = names32;
13166
13167       havesib = 0;
13168       havebase = 1;
13169       haveindex = 0;
13170       base = modrm.rm;
13171
13172       if (base == 4)
13173         {
13174           havesib = 1;
13175           vindex = sib.index;
13176           USED_REX (REX_X);
13177           if (rex & REX_X)
13178             vindex += 8;
13179           switch (bytemode)
13180             {
13181             case vex_vsib_d_w_dq_mode:
13182             case vex_vsib_q_w_dq_mode:
13183               if (!need_vex)
13184                 abort ();
13185
13186               haveindex = 1;
13187               switch (vex.length)
13188                 {
13189                 case 128:
13190                   indexes64 = indexes32 = names_xmm;
13191                   break;
13192                 case 256:
13193                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
13194                     indexes64 = indexes32 = names_ymm;
13195                   else
13196                     indexes64 = indexes32 = names_xmm;
13197                   break;
13198                 default:
13199                   abort ();
13200                 }
13201               break;
13202             default:
13203               haveindex = vindex != 4;
13204               break;
13205             }
13206           scale = sib.scale;
13207           base = sib.base;
13208           codep++;
13209         }
13210       rbase = base + add;
13211
13212       switch (modrm.mod)
13213         {
13214         case 0:
13215           if (base == 5)
13216             {
13217               havebase = 0;
13218               if (address_mode == mode_64bit && !havesib)
13219                 riprel = 1;
13220               disp = get32s ();
13221             }
13222           break;
13223         case 1:
13224           FETCH_DATA (the_info, codep + 1);
13225           disp = *codep++;
13226           if ((disp & 0x80) != 0)
13227             disp -= 0x100;
13228           break;
13229         case 2:
13230           disp = get32s ();
13231           break;
13232         }
13233
13234       /* In 32bit mode, we need index register to tell [offset] from
13235          [eiz*1 + offset].  */
13236       needindex = (havesib
13237                    && !havebase
13238                    && !haveindex
13239                    && address_mode == mode_32bit);
13240       havedisp = (havebase
13241                   || needindex
13242                   || (havesib && (haveindex || scale != 0)));
13243
13244       if (!intel_syntax)
13245         if (modrm.mod != 0 || base == 5)
13246           {
13247             if (havedisp || riprel)
13248               print_displacement (scratchbuf, disp);
13249             else
13250               print_operand_value (scratchbuf, 1, disp);
13251             oappend (scratchbuf);
13252             if (riprel)
13253               {
13254                 set_op (disp, 1);
13255                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13256               }
13257           }
13258
13259       if ((havebase || haveindex || riprel)
13260           && (bytemode != v_bnd_mode)
13261           && (bytemode != bnd_mode))
13262         used_prefixes |= PREFIX_ADDR;
13263
13264       if (havedisp || (intel_syntax && riprel))
13265         {
13266           *obufp++ = open_char;
13267           if (intel_syntax && riprel)
13268             {
13269               set_op (disp, 1);
13270               oappend (sizeflag & AFLAG ? "rip" : "eip");
13271             }
13272           *obufp = '\0';
13273           if (havebase)
13274             oappend (address_mode == mode_64bit && !addr32flag
13275                      ? names64[rbase] : names32[rbase]);
13276           if (havesib)
13277             {
13278               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13279                  print index to tell base + index from base.  */
13280               if (scale != 0
13281                   || needindex
13282                   || haveindex
13283                   || (havebase && base != ESP_REG_NUM))
13284                 {
13285                   if (!intel_syntax || havebase)
13286                     {
13287                       *obufp++ = separator_char;
13288                       *obufp = '\0';
13289                     }
13290                   if (haveindex)
13291                     oappend (address_mode == mode_64bit && !addr32flag
13292                              ? indexes64[vindex] : indexes32[vindex]);
13293                   else
13294                     oappend (address_mode == mode_64bit && !addr32flag
13295                              ? index64 : index32);
13296
13297                   *obufp++ = scale_char;
13298                   *obufp = '\0';
13299                   sprintf (scratchbuf, "%d", 1 << scale);
13300                   oappend (scratchbuf);
13301                 }
13302             }
13303           if (intel_syntax
13304               && (disp || modrm.mod != 0 || base == 5))
13305             {
13306               if (!havedisp || (bfd_signed_vma) disp >= 0)
13307                 {
13308                   *obufp++ = '+';
13309                   *obufp = '\0';
13310                 }
13311               else if (modrm.mod != 1 && disp != -disp)
13312                 {
13313                   *obufp++ = '-';
13314                   *obufp = '\0';
13315                   disp = - (bfd_signed_vma) disp;
13316                 }
13317
13318               if (havedisp)
13319                 print_displacement (scratchbuf, disp);
13320               else
13321                 print_operand_value (scratchbuf, 1, disp);
13322               oappend (scratchbuf);
13323             }
13324
13325           *obufp++ = close_char;
13326           *obufp = '\0';
13327         }
13328       else if (intel_syntax)
13329         {
13330           if (modrm.mod != 0 || base == 5)
13331             {
13332               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13333                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13334                 ;
13335               else
13336                 {
13337                   oappend (names_seg[ds_reg - es_reg]);
13338                   oappend (":");
13339                 }
13340               print_operand_value (scratchbuf, 1, disp);
13341               oappend (scratchbuf);
13342             }
13343         }
13344     }
13345   else
13346     {
13347       /* 16 bit address mode */
13348       used_prefixes |= prefixes & PREFIX_ADDR;
13349       switch (modrm.mod)
13350         {
13351         case 0:
13352           if (modrm.rm == 6)
13353             {
13354               disp = get16 ();
13355               if ((disp & 0x8000) != 0)
13356                 disp -= 0x10000;
13357             }
13358           break;
13359         case 1:
13360           FETCH_DATA (the_info, codep + 1);
13361           disp = *codep++;
13362           if ((disp & 0x80) != 0)
13363             disp -= 0x100;
13364           break;
13365         case 2:
13366           disp = get16 ();
13367           if ((disp & 0x8000) != 0)
13368             disp -= 0x10000;
13369           break;
13370         }
13371
13372       if (!intel_syntax)
13373         if (modrm.mod != 0 || modrm.rm == 6)
13374           {
13375             print_displacement (scratchbuf, disp);
13376             oappend (scratchbuf);
13377           }
13378
13379       if (modrm.mod != 0 || modrm.rm != 6)
13380         {
13381           *obufp++ = open_char;
13382           *obufp = '\0';
13383           oappend (index16[modrm.rm]);
13384           if (intel_syntax
13385               && (disp || modrm.mod != 0 || modrm.rm == 6))
13386             {
13387               if ((bfd_signed_vma) disp >= 0)
13388                 {
13389                   *obufp++ = '+';
13390                   *obufp = '\0';
13391                 }
13392               else if (modrm.mod != 1)
13393                 {
13394                   *obufp++ = '-';
13395                   *obufp = '\0';
13396                   disp = - (bfd_signed_vma) disp;
13397                 }
13398
13399               print_displacement (scratchbuf, disp);
13400               oappend (scratchbuf);
13401             }
13402
13403           *obufp++ = close_char;
13404           *obufp = '\0';
13405         }
13406       else if (intel_syntax)
13407         {
13408           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13409                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13410             ;
13411           else
13412             {
13413               oappend (names_seg[ds_reg - es_reg]);
13414               oappend (":");
13415             }
13416           print_operand_value (scratchbuf, 1, disp & 0xffff);
13417           oappend (scratchbuf);
13418         }
13419     }
13420 }
13421
13422 static void
13423 OP_E (int bytemode, int sizeflag)
13424 {
13425   /* Skip mod/rm byte.  */
13426   MODRM_CHECK;
13427   codep++;
13428
13429   if (modrm.mod == 3)
13430     OP_E_register (bytemode, sizeflag);
13431   else
13432     OP_E_memory (bytemode, sizeflag);
13433 }
13434
13435 static void
13436 OP_G (int bytemode, int sizeflag)
13437 {
13438   int add = 0;
13439   USED_REX (REX_R);
13440   if (rex & REX_R)
13441     add += 8;
13442   switch (bytemode)
13443     {
13444     case b_mode:
13445       USED_REX (0);
13446       if (rex)
13447         oappend (names8rex[modrm.reg + add]);
13448       else
13449         oappend (names8[modrm.reg + add]);
13450       break;
13451     case w_mode:
13452       oappend (names16[modrm.reg + add]);
13453       break;
13454     case d_mode:
13455       oappend (names32[modrm.reg + add]);
13456       break;
13457     case q_mode:
13458       oappend (names64[modrm.reg + add]);
13459       break;
13460     case bnd_mode:
13461       oappend (names_bnd[modrm.reg]);
13462       break;
13463     case v_mode:
13464     case dq_mode:
13465     case dqb_mode:
13466     case dqd_mode:
13467     case dqw_mode:
13468       USED_REX (REX_W);
13469       if (rex & REX_W)
13470         oappend (names64[modrm.reg + add]);
13471       else
13472         {
13473           if ((sizeflag & DFLAG) || bytemode != v_mode)
13474             oappend (names32[modrm.reg + add]);
13475           else
13476             oappend (names16[modrm.reg + add]);
13477           used_prefixes |= (prefixes & PREFIX_DATA);
13478         }
13479       break;
13480     case m_mode:
13481       if (address_mode == mode_64bit)
13482         oappend (names64[modrm.reg + add]);
13483       else
13484         oappend (names32[modrm.reg + add]);
13485       break;
13486     default:
13487       oappend (INTERNAL_DISASSEMBLER_ERROR);
13488       break;
13489     }
13490 }
13491
13492 static bfd_vma
13493 get64 (void)
13494 {
13495   bfd_vma x;
13496 #ifdef BFD64
13497   unsigned int a;
13498   unsigned int b;
13499
13500   FETCH_DATA (the_info, codep + 8);
13501   a = *codep++ & 0xff;
13502   a |= (*codep++ & 0xff) << 8;
13503   a |= (*codep++ & 0xff) << 16;
13504   a |= (*codep++ & 0xff) << 24;
13505   b = *codep++ & 0xff;
13506   b |= (*codep++ & 0xff) << 8;
13507   b |= (*codep++ & 0xff) << 16;
13508   b |= (*codep++ & 0xff) << 24;
13509   x = a + ((bfd_vma) b << 32);
13510 #else
13511   abort ();
13512   x = 0;
13513 #endif
13514   return x;
13515 }
13516
13517 static bfd_signed_vma
13518 get32 (void)
13519 {
13520   bfd_signed_vma x = 0;
13521
13522   FETCH_DATA (the_info, codep + 4);
13523   x = *codep++ & (bfd_signed_vma) 0xff;
13524   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13525   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13526   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13527   return x;
13528 }
13529
13530 static bfd_signed_vma
13531 get32s (void)
13532 {
13533   bfd_signed_vma x = 0;
13534
13535   FETCH_DATA (the_info, codep + 4);
13536   x = *codep++ & (bfd_signed_vma) 0xff;
13537   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13538   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13539   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13540
13541   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13542
13543   return x;
13544 }
13545
13546 static int
13547 get16 (void)
13548 {
13549   int x = 0;
13550
13551   FETCH_DATA (the_info, codep + 2);
13552   x = *codep++ & 0xff;
13553   x |= (*codep++ & 0xff) << 8;
13554   return x;
13555 }
13556
13557 static void
13558 set_op (bfd_vma op, int riprel)
13559 {
13560   op_index[op_ad] = op_ad;
13561   if (address_mode == mode_64bit)
13562     {
13563       op_address[op_ad] = op;
13564       op_riprel[op_ad] = riprel;
13565     }
13566   else
13567     {
13568       /* Mask to get a 32-bit address.  */
13569       op_address[op_ad] = op & 0xffffffff;
13570       op_riprel[op_ad] = riprel & 0xffffffff;
13571     }
13572 }
13573
13574 static void
13575 OP_REG (int code, int sizeflag)
13576 {
13577   const char *s;
13578   int add;
13579
13580   switch (code)
13581     {
13582     case es_reg: case ss_reg: case cs_reg:
13583     case ds_reg: case fs_reg: case gs_reg:
13584       oappend (names_seg[code - es_reg]);
13585       return;
13586     }
13587
13588   USED_REX (REX_B);
13589   if (rex & REX_B)
13590     add = 8;
13591   else
13592     add = 0;
13593
13594   switch (code)
13595     {
13596     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13597     case sp_reg: case bp_reg: case si_reg: case di_reg:
13598       s = names16[code - ax_reg + add];
13599       break;
13600     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13601     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13602       USED_REX (0);
13603       if (rex)
13604         s = names8rex[code - al_reg + add];
13605       else
13606         s = names8[code - al_reg];
13607       break;
13608     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13609     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13610       if (address_mode == mode_64bit
13611           && ((sizeflag & DFLAG) || (rex & REX_W)))
13612         {
13613           s = names64[code - rAX_reg + add];
13614           break;
13615         }
13616       code += eAX_reg - rAX_reg;
13617       /* Fall through.  */
13618     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13619     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13620       USED_REX (REX_W);
13621       if (rex & REX_W)
13622         s = names64[code - eAX_reg + add];
13623       else
13624         {
13625           if (sizeflag & DFLAG)
13626             s = names32[code - eAX_reg + add];
13627           else
13628             s = names16[code - eAX_reg + add];
13629           used_prefixes |= (prefixes & PREFIX_DATA);
13630         }
13631       break;
13632     default:
13633       s = INTERNAL_DISASSEMBLER_ERROR;
13634       break;
13635     }
13636   oappend (s);
13637 }
13638
13639 static void
13640 OP_IMREG (int code, int sizeflag)
13641 {
13642   const char *s;
13643
13644   switch (code)
13645     {
13646     case indir_dx_reg:
13647       if (intel_syntax)
13648         s = "dx";
13649       else
13650         s = "(%dx)";
13651       break;
13652     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13653     case sp_reg: case bp_reg: case si_reg: case di_reg:
13654       s = names16[code - ax_reg];
13655       break;
13656     case es_reg: case ss_reg: case cs_reg:
13657     case ds_reg: case fs_reg: case gs_reg:
13658       s = names_seg[code - es_reg];
13659       break;
13660     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13661     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13662       USED_REX (0);
13663       if (rex)
13664         s = names8rex[code - al_reg];
13665       else
13666         s = names8[code - al_reg];
13667       break;
13668     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13669     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13670       USED_REX (REX_W);
13671       if (rex & REX_W)
13672         s = names64[code - eAX_reg];
13673       else
13674         {
13675           if (sizeflag & DFLAG)
13676             s = names32[code - eAX_reg];
13677           else
13678             s = names16[code - eAX_reg];
13679           used_prefixes |= (prefixes & PREFIX_DATA);
13680         }
13681       break;
13682     case z_mode_ax_reg:
13683       if ((rex & REX_W) || (sizeflag & DFLAG))
13684         s = *names32;
13685       else
13686         s = *names16;
13687       if (!(rex & REX_W))
13688         used_prefixes |= (prefixes & PREFIX_DATA);
13689       break;
13690     default:
13691       s = INTERNAL_DISASSEMBLER_ERROR;
13692       break;
13693     }
13694   oappend (s);
13695 }
13696
13697 static void
13698 OP_I (int bytemode, int sizeflag)
13699 {
13700   bfd_signed_vma op;
13701   bfd_signed_vma mask = -1;
13702
13703   switch (bytemode)
13704     {
13705     case b_mode:
13706       FETCH_DATA (the_info, codep + 1);
13707       op = *codep++;
13708       mask = 0xff;
13709       break;
13710     case q_mode:
13711       if (address_mode == mode_64bit)
13712         {
13713           op = get32s ();
13714           break;
13715         }
13716       /* Fall through.  */
13717     case v_mode:
13718       USED_REX (REX_W);
13719       if (rex & REX_W)
13720         op = get32s ();
13721       else
13722         {
13723           if (sizeflag & DFLAG)
13724             {
13725               op = get32 ();
13726               mask = 0xffffffff;
13727             }
13728           else
13729             {
13730               op = get16 ();
13731               mask = 0xfffff;
13732             }
13733           used_prefixes |= (prefixes & PREFIX_DATA);
13734         }
13735       break;
13736     case w_mode:
13737       mask = 0xfffff;
13738       op = get16 ();
13739       break;
13740     case const_1_mode:
13741       if (intel_syntax)
13742         oappend ("1");
13743       return;
13744     default:
13745       oappend (INTERNAL_DISASSEMBLER_ERROR);
13746       return;
13747     }
13748
13749   op &= mask;
13750   scratchbuf[0] = '$';
13751   print_operand_value (scratchbuf + 1, 1, op);
13752   oappend (scratchbuf + intel_syntax);
13753   scratchbuf[0] = '\0';
13754 }
13755
13756 static void
13757 OP_I64 (int bytemode, int sizeflag)
13758 {
13759   bfd_signed_vma op;
13760   bfd_signed_vma mask = -1;
13761
13762   if (address_mode != mode_64bit)
13763     {
13764       OP_I (bytemode, sizeflag);
13765       return;
13766     }
13767
13768   switch (bytemode)
13769     {
13770     case b_mode:
13771       FETCH_DATA (the_info, codep + 1);
13772       op = *codep++;
13773       mask = 0xff;
13774       break;
13775     case v_mode:
13776       USED_REX (REX_W);
13777       if (rex & REX_W)
13778         op = get64 ();
13779       else
13780         {
13781           if (sizeflag & DFLAG)
13782             {
13783               op = get32 ();
13784               mask = 0xffffffff;
13785             }
13786           else
13787             {
13788               op = get16 ();
13789               mask = 0xfffff;
13790             }
13791           used_prefixes |= (prefixes & PREFIX_DATA);
13792         }
13793       break;
13794     case w_mode:
13795       mask = 0xfffff;
13796       op = get16 ();
13797       break;
13798     default:
13799       oappend (INTERNAL_DISASSEMBLER_ERROR);
13800       return;
13801     }
13802
13803   op &= mask;
13804   scratchbuf[0] = '$';
13805   print_operand_value (scratchbuf + 1, 1, op);
13806   oappend (scratchbuf + intel_syntax);
13807   scratchbuf[0] = '\0';
13808 }
13809
13810 static void
13811 OP_sI (int bytemode, int sizeflag)
13812 {
13813   bfd_signed_vma op;
13814
13815   switch (bytemode)
13816     {
13817     case b_mode:
13818     case b_T_mode:
13819       FETCH_DATA (the_info, codep + 1);
13820       op = *codep++;
13821       if ((op & 0x80) != 0)
13822         op -= 0x100;
13823       if (bytemode == b_T_mode)
13824         {
13825           if (address_mode != mode_64bit
13826               || !((sizeflag & DFLAG) || (rex & REX_W)))
13827             {
13828               /* The operand-size prefix is overridden by a REX prefix.  */
13829               if ((sizeflag & DFLAG) || (rex & REX_W))
13830                 op &= 0xffffffff;
13831               else
13832                 op &= 0xffff;
13833           }
13834         }
13835       else
13836         {
13837           if (!(rex & REX_W))
13838             {
13839               if (sizeflag & DFLAG)
13840                 op &= 0xffffffff;
13841               else
13842                 op &= 0xffff;
13843             }
13844         }
13845       break;
13846     case v_mode:
13847       /* The operand-size prefix is overridden by a REX prefix.  */
13848       if ((sizeflag & DFLAG) || (rex & REX_W))
13849         op = get32s ();
13850       else
13851         op = get16 ();
13852       break;
13853     default:
13854       oappend (INTERNAL_DISASSEMBLER_ERROR);
13855       return;
13856     }
13857
13858   scratchbuf[0] = '$';
13859   print_operand_value (scratchbuf + 1, 1, op);
13860   oappend (scratchbuf + intel_syntax);
13861 }
13862
13863 static void
13864 OP_J (int bytemode, int sizeflag)
13865 {
13866   bfd_vma disp;
13867   bfd_vma mask = -1;
13868   bfd_vma segment = 0;
13869
13870   switch (bytemode)
13871     {
13872     case b_mode:
13873       FETCH_DATA (the_info, codep + 1);
13874       disp = *codep++;
13875       if ((disp & 0x80) != 0)
13876         disp -= 0x100;
13877       break;
13878     case v_mode:
13879       USED_REX (REX_W);
13880       if ((sizeflag & DFLAG) || (rex & REX_W))
13881         disp = get32s ();
13882       else
13883         {
13884           disp = get16 ();
13885           if ((disp & 0x8000) != 0)
13886             disp -= 0x10000;
13887           /* In 16bit mode, address is wrapped around at 64k within
13888              the same segment.  Otherwise, a data16 prefix on a jump
13889              instruction means that the pc is masked to 16 bits after
13890              the displacement is added!  */
13891           mask = 0xffff;
13892           if ((prefixes & PREFIX_DATA) == 0)
13893             segment = ((start_pc + codep - start_codep)
13894                        & ~((bfd_vma) 0xffff));
13895         }
13896       if (!(rex & REX_W))
13897         used_prefixes |= (prefixes & PREFIX_DATA);
13898       break;
13899     default:
13900       oappend (INTERNAL_DISASSEMBLER_ERROR);
13901       return;
13902     }
13903   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
13904   set_op (disp, 0);
13905   print_operand_value (scratchbuf, 1, disp);
13906   oappend (scratchbuf);
13907 }
13908
13909 static void
13910 OP_SEG (int bytemode, int sizeflag)
13911 {
13912   if (bytemode == w_mode)
13913     oappend (names_seg[modrm.reg]);
13914   else
13915     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13916 }
13917
13918 static void
13919 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13920 {
13921   int seg, offset;
13922
13923   if (sizeflag & DFLAG)
13924     {
13925       offset = get32 ();
13926       seg = get16 ();
13927     }
13928   else
13929     {
13930       offset = get16 ();
13931       seg = get16 ();
13932     }
13933   used_prefixes |= (prefixes & PREFIX_DATA);
13934   if (intel_syntax)
13935     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13936   else
13937     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13938   oappend (scratchbuf);
13939 }
13940
13941 static void
13942 OP_OFF (int bytemode, int sizeflag)
13943 {
13944   bfd_vma off;
13945
13946   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13947     intel_operand_size (bytemode, sizeflag);
13948   append_seg ();
13949
13950   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13951     off = get32 ();
13952   else
13953     off = get16 ();
13954
13955   if (intel_syntax)
13956     {
13957       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13958                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13959         {
13960           oappend (names_seg[ds_reg - es_reg]);
13961           oappend (":");
13962         }
13963     }
13964   print_operand_value (scratchbuf, 1, off);
13965   oappend (scratchbuf);
13966 }
13967
13968 static void
13969 OP_OFF64 (int bytemode, int sizeflag)
13970 {
13971   bfd_vma off;
13972
13973   if (address_mode != mode_64bit
13974       || (prefixes & PREFIX_ADDR))
13975     {
13976       OP_OFF (bytemode, sizeflag);
13977       return;
13978     }
13979
13980   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13981     intel_operand_size (bytemode, sizeflag);
13982   append_seg ();
13983
13984   off = get64 ();
13985
13986   if (intel_syntax)
13987     {
13988       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13989                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13990         {
13991           oappend (names_seg[ds_reg - es_reg]);
13992           oappend (":");
13993         }
13994     }
13995   print_operand_value (scratchbuf, 1, off);
13996   oappend (scratchbuf);
13997 }
13998
13999 static void
14000 ptr_reg (int code, int sizeflag)
14001 {
14002   const char *s;
14003
14004   *obufp++ = open_char;
14005   used_prefixes |= (prefixes & PREFIX_ADDR);
14006   if (address_mode == mode_64bit)
14007     {
14008       if (!(sizeflag & AFLAG))
14009         s = names32[code - eAX_reg];
14010       else
14011         s = names64[code - eAX_reg];
14012     }
14013   else if (sizeflag & AFLAG)
14014     s = names32[code - eAX_reg];
14015   else
14016     s = names16[code - eAX_reg];
14017   oappend (s);
14018   *obufp++ = close_char;
14019   *obufp = 0;
14020 }
14021
14022 static void
14023 OP_ESreg (int code, int sizeflag)
14024 {
14025   if (intel_syntax)
14026     {
14027       switch (codep[-1])
14028         {
14029         case 0x6d:      /* insw/insl */
14030           intel_operand_size (z_mode, sizeflag);
14031           break;
14032         case 0xa5:      /* movsw/movsl/movsq */
14033         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14034         case 0xab:      /* stosw/stosl */
14035         case 0xaf:      /* scasw/scasl */
14036           intel_operand_size (v_mode, sizeflag);
14037           break;
14038         default:
14039           intel_operand_size (b_mode, sizeflag);
14040         }
14041     }
14042   oappend ("%es:" + intel_syntax);
14043   ptr_reg (code, sizeflag);
14044 }
14045
14046 static void
14047 OP_DSreg (int code, int sizeflag)
14048 {
14049   if (intel_syntax)
14050     {
14051       switch (codep[-1])
14052         {
14053         case 0x6f:      /* outsw/outsl */
14054           intel_operand_size (z_mode, sizeflag);
14055           break;
14056         case 0xa5:      /* movsw/movsl/movsq */
14057         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14058         case 0xad:      /* lodsw/lodsl/lodsq */
14059           intel_operand_size (v_mode, sizeflag);
14060           break;
14061         default:
14062           intel_operand_size (b_mode, sizeflag);
14063         }
14064     }
14065   if ((prefixes
14066        & (PREFIX_CS
14067           | PREFIX_DS
14068           | PREFIX_SS
14069           | PREFIX_ES
14070           | PREFIX_FS
14071           | PREFIX_GS)) == 0)
14072     prefixes |= PREFIX_DS;
14073   append_seg ();
14074   ptr_reg (code, sizeflag);
14075 }
14076
14077 static void
14078 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14079 {
14080   int add;
14081   if (rex & REX_R)
14082     {
14083       USED_REX (REX_R);
14084       add = 8;
14085     }
14086   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
14087     {
14088       all_prefixes[last_lock_prefix] = 0;
14089       used_prefixes |= PREFIX_LOCK;
14090       add = 8;
14091     }
14092   else
14093     add = 0;
14094   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
14095   oappend (scratchbuf + intel_syntax);
14096 }
14097
14098 static void
14099 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14100 {
14101   int add;
14102   USED_REX (REX_R);
14103   if (rex & REX_R)
14104     add = 8;
14105   else
14106     add = 0;
14107   if (intel_syntax)
14108     sprintf (scratchbuf, "db%d", modrm.reg + add);
14109   else
14110     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
14111   oappend (scratchbuf);
14112 }
14113
14114 static void
14115 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14116 {
14117   sprintf (scratchbuf, "%%tr%d", modrm.reg);
14118   oappend (scratchbuf + intel_syntax);
14119 }
14120
14121 static void
14122 OP_R (int bytemode, int sizeflag)
14123 {
14124   if (modrm.mod == 3)
14125     OP_E (bytemode, sizeflag);
14126   else
14127     BadOp ();
14128 }
14129
14130 static void
14131 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14132 {
14133   int reg = modrm.reg;
14134   const char **names;
14135
14136   used_prefixes |= (prefixes & PREFIX_DATA);
14137   if (prefixes & PREFIX_DATA)
14138     {
14139       names = names_xmm;
14140       USED_REX (REX_R);
14141       if (rex & REX_R)
14142         reg += 8;
14143     }
14144   else
14145     names = names_mm;
14146   oappend (names[reg]);
14147 }
14148
14149 static void
14150 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14151 {
14152   int reg = modrm.reg;
14153   const char **names;
14154
14155   USED_REX (REX_R);
14156   if (rex & REX_R)
14157     reg += 8;
14158   if (need_vex
14159       && bytemode != xmm_mode
14160       && bytemode != scalar_mode)
14161     {
14162       switch (vex.length)
14163         {
14164         case 128:
14165           names = names_xmm;
14166           break;
14167         case 256:
14168           if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
14169             names = names_ymm;
14170           else
14171             names = names_xmm;
14172           break;
14173         default:
14174           abort ();
14175         }
14176     }
14177   else
14178     names = names_xmm;
14179   oappend (names[reg]);
14180 }
14181
14182 static void
14183 OP_EM (int bytemode, int sizeflag)
14184 {
14185   int reg;
14186   const char **names;
14187
14188   if (modrm.mod != 3)
14189     {
14190       if (intel_syntax
14191           && (bytemode == v_mode || bytemode == v_swap_mode))
14192         {
14193           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14194           used_prefixes |= (prefixes & PREFIX_DATA);
14195         }
14196       OP_E (bytemode, sizeflag);
14197       return;
14198     }
14199
14200   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14201     swap_operand ();
14202
14203   /* Skip mod/rm byte.  */
14204   MODRM_CHECK;
14205   codep++;
14206   used_prefixes |= (prefixes & PREFIX_DATA);
14207   reg = modrm.rm;
14208   if (prefixes & PREFIX_DATA)
14209     {
14210       names = names_xmm;
14211       USED_REX (REX_B);
14212       if (rex & REX_B)
14213         reg += 8;
14214     }
14215   else
14216     names = names_mm;
14217   oappend (names[reg]);
14218 }
14219
14220 /* cvt* are the only instructions in sse2 which have
14221    both SSE and MMX operands and also have 0x66 prefix
14222    in their opcode. 0x66 was originally used to differentiate
14223    between SSE and MMX instruction(operands). So we have to handle the
14224    cvt* separately using OP_EMC and OP_MXC */
14225 static void
14226 OP_EMC (int bytemode, int sizeflag)
14227 {
14228   if (modrm.mod != 3)
14229     {
14230       if (intel_syntax && bytemode == v_mode)
14231         {
14232           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14233           used_prefixes |= (prefixes & PREFIX_DATA);
14234         }
14235       OP_E (bytemode, sizeflag);
14236       return;
14237     }
14238
14239   /* Skip mod/rm byte.  */
14240   MODRM_CHECK;
14241   codep++;
14242   used_prefixes |= (prefixes & PREFIX_DATA);
14243   oappend (names_mm[modrm.rm]);
14244 }
14245
14246 static void
14247 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14248 {
14249   used_prefixes |= (prefixes & PREFIX_DATA);
14250   oappend (names_mm[modrm.reg]);
14251 }
14252
14253 static void
14254 OP_EX (int bytemode, int sizeflag)
14255 {
14256   int reg;
14257   const char **names;
14258
14259   /* Skip mod/rm byte.  */
14260   MODRM_CHECK;
14261   codep++;
14262
14263   if (modrm.mod != 3)
14264     {
14265       OP_E_memory (bytemode, sizeflag);
14266       return;
14267     }
14268
14269   reg = modrm.rm;
14270   USED_REX (REX_B);
14271   if (rex & REX_B)
14272     reg += 8;
14273
14274   if ((sizeflag & SUFFIX_ALWAYS)
14275       && (bytemode == x_swap_mode
14276           || bytemode == d_swap_mode
14277           || bytemode == d_scalar_swap_mode
14278           || bytemode == q_swap_mode
14279           || bytemode == q_scalar_swap_mode))
14280     swap_operand ();
14281
14282   if (need_vex
14283       && bytemode != xmm_mode
14284       && bytemode != xmmdw_mode
14285       && bytemode != xmmqd_mode
14286       && bytemode != xmm_mb_mode
14287       && bytemode != xmm_mw_mode
14288       && bytemode != xmm_md_mode
14289       && bytemode != xmm_mq_mode
14290       && bytemode != xmmq_mode
14291       && bytemode != d_scalar_mode
14292       && bytemode != d_scalar_swap_mode
14293       && bytemode != q_scalar_mode
14294       && bytemode != q_scalar_swap_mode
14295       && bytemode != vex_scalar_w_dq_mode)
14296     {
14297       switch (vex.length)
14298         {
14299         case 128:
14300           names = names_xmm;
14301           break;
14302         case 256:
14303           names = names_ymm;
14304           break;
14305         default:
14306           abort ();
14307         }
14308     }
14309   else
14310     names = names_xmm;
14311   oappend (names[reg]);
14312 }
14313
14314 static void
14315 OP_MS (int bytemode, int sizeflag)
14316 {
14317   if (modrm.mod == 3)
14318     OP_EM (bytemode, sizeflag);
14319   else
14320     BadOp ();
14321 }
14322
14323 static void
14324 OP_XS (int bytemode, int sizeflag)
14325 {
14326   if (modrm.mod == 3)
14327     OP_EX (bytemode, sizeflag);
14328   else
14329     BadOp ();
14330 }
14331
14332 static void
14333 OP_M (int bytemode, int sizeflag)
14334 {
14335   if (modrm.mod == 3)
14336     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14337     BadOp ();
14338   else
14339     OP_E (bytemode, sizeflag);
14340 }
14341
14342 static void
14343 OP_0f07 (int bytemode, int sizeflag)
14344 {
14345   if (modrm.mod != 3 || modrm.rm != 0)
14346     BadOp ();
14347   else
14348     OP_E (bytemode, sizeflag);
14349 }
14350
14351 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14352    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14353
14354 static void
14355 NOP_Fixup1 (int bytemode, int sizeflag)
14356 {
14357   if ((prefixes & PREFIX_DATA) != 0
14358       || (rex != 0
14359           && rex != 0x48
14360           && address_mode == mode_64bit))
14361     OP_REG (bytemode, sizeflag);
14362   else
14363     strcpy (obuf, "nop");
14364 }
14365
14366 static void
14367 NOP_Fixup2 (int bytemode, int sizeflag)
14368 {
14369   if ((prefixes & PREFIX_DATA) != 0
14370       || (rex != 0
14371           && rex != 0x48
14372           && address_mode == mode_64bit))
14373     OP_IMREG (bytemode, sizeflag);
14374 }
14375
14376 static const char *const Suffix3DNow[] = {
14377 /* 00 */        NULL,           NULL,           NULL,           NULL,
14378 /* 04 */        NULL,           NULL,           NULL,           NULL,
14379 /* 08 */        NULL,           NULL,           NULL,           NULL,
14380 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14381 /* 10 */        NULL,           NULL,           NULL,           NULL,
14382 /* 14 */        NULL,           NULL,           NULL,           NULL,
14383 /* 18 */        NULL,           NULL,           NULL,           NULL,
14384 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14385 /* 20 */        NULL,           NULL,           NULL,           NULL,
14386 /* 24 */        NULL,           NULL,           NULL,           NULL,
14387 /* 28 */        NULL,           NULL,           NULL,           NULL,
14388 /* 2C */        NULL,           NULL,           NULL,           NULL,
14389 /* 30 */        NULL,           NULL,           NULL,           NULL,
14390 /* 34 */        NULL,           NULL,           NULL,           NULL,
14391 /* 38 */        NULL,           NULL,           NULL,           NULL,
14392 /* 3C */        NULL,           NULL,           NULL,           NULL,
14393 /* 40 */        NULL,           NULL,           NULL,           NULL,
14394 /* 44 */        NULL,           NULL,           NULL,           NULL,
14395 /* 48 */        NULL,           NULL,           NULL,           NULL,
14396 /* 4C */        NULL,           NULL,           NULL,           NULL,
14397 /* 50 */        NULL,           NULL,           NULL,           NULL,
14398 /* 54 */        NULL,           NULL,           NULL,           NULL,
14399 /* 58 */        NULL,           NULL,           NULL,           NULL,
14400 /* 5C */        NULL,           NULL,           NULL,           NULL,
14401 /* 60 */        NULL,           NULL,           NULL,           NULL,
14402 /* 64 */        NULL,           NULL,           NULL,           NULL,
14403 /* 68 */        NULL,           NULL,           NULL,           NULL,
14404 /* 6C */        NULL,           NULL,           NULL,           NULL,
14405 /* 70 */        NULL,           NULL,           NULL,           NULL,
14406 /* 74 */        NULL,           NULL,           NULL,           NULL,
14407 /* 78 */        NULL,           NULL,           NULL,           NULL,
14408 /* 7C */        NULL,           NULL,           NULL,           NULL,
14409 /* 80 */        NULL,           NULL,           NULL,           NULL,
14410 /* 84 */        NULL,           NULL,           NULL,           NULL,
14411 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14412 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14413 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14414 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14415 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14416 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14417 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14418 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14419 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14420 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14421 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14422 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14423 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14424 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14425 /* C0 */        NULL,           NULL,           NULL,           NULL,
14426 /* C4 */        NULL,           NULL,           NULL,           NULL,
14427 /* C8 */        NULL,           NULL,           NULL,           NULL,
14428 /* CC */        NULL,           NULL,           NULL,           NULL,
14429 /* D0 */        NULL,           NULL,           NULL,           NULL,
14430 /* D4 */        NULL,           NULL,           NULL,           NULL,
14431 /* D8 */        NULL,           NULL,           NULL,           NULL,
14432 /* DC */        NULL,           NULL,           NULL,           NULL,
14433 /* E0 */        NULL,           NULL,           NULL,           NULL,
14434 /* E4 */        NULL,           NULL,           NULL,           NULL,
14435 /* E8 */        NULL,           NULL,           NULL,           NULL,
14436 /* EC */        NULL,           NULL,           NULL,           NULL,
14437 /* F0 */        NULL,           NULL,           NULL,           NULL,
14438 /* F4 */        NULL,           NULL,           NULL,           NULL,
14439 /* F8 */        NULL,           NULL,           NULL,           NULL,
14440 /* FC */        NULL,           NULL,           NULL,           NULL,
14441 };
14442
14443 static void
14444 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14445 {
14446   const char *mnemonic;
14447
14448   FETCH_DATA (the_info, codep + 1);
14449   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14450      place where an 8-bit immediate would normally go.  ie. the last
14451      byte of the instruction.  */
14452   obufp = mnemonicendp;
14453   mnemonic = Suffix3DNow[*codep++ & 0xff];
14454   if (mnemonic)
14455     oappend (mnemonic);
14456   else
14457     {
14458       /* Since a variable sized modrm/sib chunk is between the start
14459          of the opcode (0x0f0f) and the opcode suffix, we need to do
14460          all the modrm processing first, and don't know until now that
14461          we have a bad opcode.  This necessitates some cleaning up.  */
14462       op_out[0][0] = '\0';
14463       op_out[1][0] = '\0';
14464       BadOp ();
14465     }
14466   mnemonicendp = obufp;
14467 }
14468
14469 static struct op simd_cmp_op[] =
14470 {
14471   { STRING_COMMA_LEN ("eq") },
14472   { STRING_COMMA_LEN ("lt") },
14473   { STRING_COMMA_LEN ("le") },
14474   { STRING_COMMA_LEN ("unord") },
14475   { STRING_COMMA_LEN ("neq") },
14476   { STRING_COMMA_LEN ("nlt") },
14477   { STRING_COMMA_LEN ("nle") },
14478   { STRING_COMMA_LEN ("ord") }
14479 };
14480
14481 static void
14482 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14483 {
14484   unsigned int cmp_type;
14485
14486   FETCH_DATA (the_info, codep + 1);
14487   cmp_type = *codep++ & 0xff;
14488   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14489     {
14490       char suffix [3];
14491       char *p = mnemonicendp - 2;
14492       suffix[0] = p[0];
14493       suffix[1] = p[1];
14494       suffix[2] = '\0';
14495       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14496       mnemonicendp += simd_cmp_op[cmp_type].len;
14497     }
14498   else
14499     {
14500       /* We have a reserved extension byte.  Output it directly.  */
14501       scratchbuf[0] = '$';
14502       print_operand_value (scratchbuf + 1, 1, cmp_type);
14503       oappend (scratchbuf + intel_syntax);
14504       scratchbuf[0] = '\0';
14505     }
14506 }
14507
14508 static void
14509 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14510           int sizeflag ATTRIBUTE_UNUSED)
14511 {
14512   /* mwait %eax,%ecx  */
14513   if (!intel_syntax)
14514     {
14515       const char **names = (address_mode == mode_64bit
14516                             ? names64 : names32);
14517       strcpy (op_out[0], names[0]);
14518       strcpy (op_out[1], names[1]);
14519       two_source_ops = 1;
14520     }
14521   /* Skip mod/rm byte.  */
14522   MODRM_CHECK;
14523   codep++;
14524 }
14525
14526 static void
14527 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14528             int sizeflag ATTRIBUTE_UNUSED)
14529 {
14530   /* monitor %eax,%ecx,%edx"  */
14531   if (!intel_syntax)
14532     {
14533       const char **op1_names;
14534       const char **names = (address_mode == mode_64bit
14535                             ? names64 : names32);
14536
14537       if (!(prefixes & PREFIX_ADDR))
14538         op1_names = (address_mode == mode_16bit
14539                      ? names16 : names);
14540       else
14541         {
14542           /* Remove "addr16/addr32".  */
14543           all_prefixes[last_addr_prefix] = 0;
14544           op1_names = (address_mode != mode_32bit
14545                        ? names32 : names16);
14546           used_prefixes |= PREFIX_ADDR;
14547         }
14548       strcpy (op_out[0], op1_names[0]);
14549       strcpy (op_out[1], names[1]);
14550       strcpy (op_out[2], names[2]);
14551       two_source_ops = 1;
14552     }
14553   /* Skip mod/rm byte.  */
14554   MODRM_CHECK;
14555   codep++;
14556 }
14557
14558 static void
14559 BadOp (void)
14560 {
14561   /* Throw away prefixes and 1st. opcode byte.  */
14562   codep = insn_codep + 1;
14563   oappend ("(bad)");
14564 }
14565
14566 static void
14567 REP_Fixup (int bytemode, int sizeflag)
14568 {
14569   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14570      lods and stos.  */
14571   if (prefixes & PREFIX_REPZ)
14572     all_prefixes[last_repz_prefix] = REP_PREFIX;
14573
14574   switch (bytemode)
14575     {
14576     case al_reg:
14577     case eAX_reg:
14578     case indir_dx_reg:
14579       OP_IMREG (bytemode, sizeflag);
14580       break;
14581     case eDI_reg:
14582       OP_ESreg (bytemode, sizeflag);
14583       break;
14584     case eSI_reg:
14585       OP_DSreg (bytemode, sizeflag);
14586       break;
14587     default:
14588       abort ();
14589       break;
14590     }
14591 }
14592
14593 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
14594    "bnd".  */
14595
14596 static void
14597 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14598 {
14599   if (prefixes & PREFIX_REPNZ)
14600     all_prefixes[last_repnz_prefix] = BND_PREFIX;
14601 }
14602
14603 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
14604    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
14605  */
14606
14607 static void
14608 HLE_Fixup1 (int bytemode, int sizeflag)
14609 {
14610   if (modrm.mod != 3
14611       && (prefixes & PREFIX_LOCK) != 0)
14612     {
14613       if (prefixes & PREFIX_REPZ)
14614         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14615       if (prefixes & PREFIX_REPNZ)
14616         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14617     }
14618
14619   OP_E (bytemode, sizeflag);
14620 }
14621
14622 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
14623    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
14624  */
14625
14626 static void
14627 HLE_Fixup2 (int bytemode, int sizeflag)
14628 {
14629   if (modrm.mod != 3)
14630     {
14631       if (prefixes & PREFIX_REPZ)
14632         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14633       if (prefixes & PREFIX_REPNZ)
14634         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14635     }
14636
14637   OP_E (bytemode, sizeflag);
14638 }
14639
14640 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
14641    "xrelease" for memory operand.  No check for LOCK prefix.   */
14642
14643 static void
14644 HLE_Fixup3 (int bytemode, int sizeflag)
14645 {
14646   if (modrm.mod != 3
14647       && last_repz_prefix > last_repnz_prefix
14648       && (prefixes & PREFIX_REPZ) != 0)
14649     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14650
14651   OP_E (bytemode, sizeflag);
14652 }
14653
14654 static void
14655 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14656 {
14657   USED_REX (REX_W);
14658   if (rex & REX_W)
14659     {
14660       /* Change cmpxchg8b to cmpxchg16b.  */
14661       char *p = mnemonicendp - 2;
14662       mnemonicendp = stpcpy (p, "16b");
14663       bytemode = o_mode;
14664     }
14665   else if ((prefixes & PREFIX_LOCK) != 0)
14666     {
14667       if (prefixes & PREFIX_REPZ)
14668         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14669       if (prefixes & PREFIX_REPNZ)
14670         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14671     }
14672
14673   OP_M (bytemode, sizeflag);
14674 }
14675
14676 static void
14677 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14678 {
14679   const char **names;
14680
14681   if (need_vex)
14682     {
14683       switch (vex.length)
14684         {
14685         case 128:
14686           names = names_xmm;
14687           break;
14688         case 256:
14689           names = names_ymm;
14690           break;
14691         default:
14692           abort ();
14693         }
14694     }
14695   else
14696     names = names_xmm;
14697   oappend (names[reg]);
14698 }
14699
14700 static void
14701 CRC32_Fixup (int bytemode, int sizeflag)
14702 {
14703   /* Add proper suffix to "crc32".  */
14704   char *p = mnemonicendp;
14705
14706   switch (bytemode)
14707     {
14708     case b_mode:
14709       if (intel_syntax)
14710         goto skip;
14711
14712       *p++ = 'b';
14713       break;
14714     case v_mode:
14715       if (intel_syntax)
14716         goto skip;
14717
14718       USED_REX (REX_W);
14719       if (rex & REX_W)
14720         *p++ = 'q';
14721       else
14722         {
14723           if (sizeflag & DFLAG)
14724             *p++ = 'l';
14725           else
14726             *p++ = 'w';
14727           used_prefixes |= (prefixes & PREFIX_DATA);
14728         }
14729       break;
14730     default:
14731       oappend (INTERNAL_DISASSEMBLER_ERROR);
14732       break;
14733     }
14734   mnemonicendp = p;
14735   *p = '\0';
14736
14737 skip:
14738   if (modrm.mod == 3)
14739     {
14740       int add;
14741
14742       /* Skip mod/rm byte.  */
14743       MODRM_CHECK;
14744       codep++;
14745
14746       USED_REX (REX_B);
14747       add = (rex & REX_B) ? 8 : 0;
14748       if (bytemode == b_mode)
14749         {
14750           USED_REX (0);
14751           if (rex)
14752             oappend (names8rex[modrm.rm + add]);
14753           else
14754             oappend (names8[modrm.rm + add]);
14755         }
14756       else
14757         {
14758           USED_REX (REX_W);
14759           if (rex & REX_W)
14760             oappend (names64[modrm.rm + add]);
14761           else if ((prefixes & PREFIX_DATA))
14762             oappend (names16[modrm.rm + add]);
14763           else
14764             oappend (names32[modrm.rm + add]);
14765         }
14766     }
14767   else
14768     OP_E (bytemode, sizeflag);
14769 }
14770
14771 static void
14772 FXSAVE_Fixup (int bytemode, int sizeflag)
14773 {
14774   /* Add proper suffix to "fxsave" and "fxrstor".  */
14775   USED_REX (REX_W);
14776   if (rex & REX_W)
14777     {
14778       char *p = mnemonicendp;
14779       *p++ = '6';
14780       *p++ = '4';
14781       *p = '\0';
14782       mnemonicendp = p;
14783     }
14784   OP_M (bytemode, sizeflag);
14785 }
14786
14787 /* Display the destination register operand for instructions with
14788    VEX. */
14789
14790 static void
14791 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14792 {
14793   int reg;
14794   const char **names;
14795
14796   if (!need_vex)
14797     abort ();
14798
14799   if (!need_vex_reg)
14800     return;
14801
14802   reg = vex.register_specifier;
14803   if (bytemode == vex_scalar_mode)
14804     {
14805       oappend (names_xmm[reg]);
14806       return;
14807     }
14808
14809   switch (vex.length)
14810     {
14811     case 128:
14812       switch (bytemode)
14813         {
14814         case vex_mode:
14815         case vex128_mode:
14816         case vex_vsib_q_w_dq_mode:
14817           names = names_xmm;
14818           break;
14819         case dq_mode:
14820           if (vex.w)
14821             names = names64;
14822           else
14823             names = names32;
14824           break;
14825         default:
14826           abort ();
14827           return;
14828         }
14829       break;
14830     case 256:
14831       switch (bytemode)
14832         {
14833         case vex_mode:
14834         case vex256_mode:
14835           names = names_ymm;
14836           break;
14837         case vex_vsib_q_w_dq_mode:
14838           names = vex.w ? names_ymm : names_xmm;
14839           break;
14840         default:
14841           abort ();
14842           return;
14843         }
14844       break;
14845     default:
14846       abort ();
14847       break;
14848     }
14849   oappend (names[reg]);
14850 }
14851
14852 /* Get the VEX immediate byte without moving codep.  */
14853
14854 static unsigned char
14855 get_vex_imm8 (int sizeflag, int opnum)
14856 {
14857   int bytes_before_imm = 0;
14858
14859   if (modrm.mod != 3)
14860     {
14861       /* There are SIB/displacement bytes.  */
14862       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14863         {
14864           /* 32/64 bit address mode */
14865           int base = modrm.rm;
14866
14867           /* Check SIB byte.  */
14868           if (base == 4)
14869             {
14870               FETCH_DATA (the_info, codep + 1);
14871               base = *codep & 7;
14872               /* When decoding the third source, don't increase
14873                  bytes_before_imm as this has already been incremented
14874                  by one in OP_E_memory while decoding the second
14875                  source operand.  */
14876               if (opnum == 0)
14877                 bytes_before_imm++;
14878             }
14879
14880           /* Don't increase bytes_before_imm when decoding the third source,
14881              it has already been incremented by OP_E_memory while decoding
14882              the second source operand.  */
14883           if (opnum == 0)
14884             {
14885               switch (modrm.mod)
14886                 {
14887                   case 0:
14888                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14889                        SIB == 5, there is a 4 byte displacement.  */
14890                     if (base != 5)
14891                       /* No displacement. */
14892                       break;
14893                   case 2:
14894                     /* 4 byte displacement.  */
14895                     bytes_before_imm += 4;
14896                     break;
14897                   case 1:
14898                     /* 1 byte displacement.  */
14899                     bytes_before_imm++;
14900                     break;
14901                 }
14902             }
14903         }
14904       else
14905         {
14906           /* 16 bit address mode */
14907           /* Don't increase bytes_before_imm when decoding the third source,
14908              it has already been incremented by OP_E_memory while decoding
14909              the second source operand.  */
14910           if (opnum == 0)
14911             {
14912               switch (modrm.mod)
14913                 {
14914                 case 0:
14915                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14916                   if (modrm.rm != 6)
14917                     /* No displacement. */
14918                     break;
14919                 case 2:
14920                   /* 2 byte displacement.  */
14921                   bytes_before_imm += 2;
14922                   break;
14923                 case 1:
14924                   /* 1 byte displacement: when decoding the third source,
14925                      don't increase bytes_before_imm as this has already
14926                      been incremented by one in OP_E_memory while decoding
14927                      the second source operand.  */
14928                   if (opnum == 0)
14929                     bytes_before_imm++;
14930
14931                   break;
14932                 }
14933             }
14934         }
14935     }
14936
14937   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14938   return codep [bytes_before_imm];
14939 }
14940
14941 static void
14942 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14943 {
14944   const char **names;
14945
14946   if (reg == -1 && modrm.mod != 3)
14947     {
14948       OP_E_memory (bytemode, sizeflag);
14949       return;
14950     }
14951   else
14952     {
14953       if (reg == -1)
14954         {
14955           reg = modrm.rm;
14956           USED_REX (REX_B);
14957           if (rex & REX_B)
14958             reg += 8;
14959         }
14960       else if (reg > 7 && address_mode != mode_64bit)
14961         BadOp ();
14962     }
14963
14964   switch (vex.length)
14965     {
14966     case 128:
14967       names = names_xmm;
14968       break;
14969     case 256:
14970       names = names_ymm;
14971       break;
14972     default:
14973       abort ();
14974     }
14975   oappend (names[reg]);
14976 }
14977
14978 static void
14979 OP_EX_VexImmW (int bytemode, int sizeflag)
14980 {
14981   int reg = -1;
14982   static unsigned char vex_imm8;
14983
14984   if (vex_w_done == 0)
14985     {
14986       vex_w_done = 1;
14987
14988       /* Skip mod/rm byte.  */
14989       MODRM_CHECK;
14990       codep++;
14991
14992       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14993
14994       if (vex.w)
14995           reg = vex_imm8 >> 4;
14996
14997       OP_EX_VexReg (bytemode, sizeflag, reg);
14998     }
14999   else if (vex_w_done == 1)
15000     {
15001       vex_w_done = 2;
15002
15003       if (!vex.w)
15004           reg = vex_imm8 >> 4;
15005
15006       OP_EX_VexReg (bytemode, sizeflag, reg);
15007     }
15008   else
15009     {
15010       /* Output the imm8 directly.  */
15011       scratchbuf[0] = '$';
15012       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
15013       oappend (scratchbuf + intel_syntax);
15014       scratchbuf[0] = '\0';
15015       codep++;
15016     }
15017 }
15018
15019 static void
15020 OP_Vex_2src (int bytemode, int sizeflag)
15021 {
15022   if (modrm.mod == 3)
15023     {
15024       int reg = modrm.rm;
15025       USED_REX (REX_B);
15026       if (rex & REX_B)
15027         reg += 8;
15028       oappend (names_xmm[reg]);
15029     }
15030   else
15031     {
15032       if (intel_syntax
15033           && (bytemode == v_mode || bytemode == v_swap_mode))
15034         {
15035           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15036           used_prefixes |= (prefixes & PREFIX_DATA);
15037         }
15038       OP_E (bytemode, sizeflag);
15039     }
15040 }
15041
15042 static void
15043 OP_Vex_2src_1 (int bytemode, int sizeflag)
15044 {
15045   if (modrm.mod == 3)
15046     {
15047       /* Skip mod/rm byte.   */
15048       MODRM_CHECK;
15049       codep++;
15050     }
15051
15052   if (vex.w)
15053     oappend (names_xmm[vex.register_specifier]);
15054   else
15055     OP_Vex_2src (bytemode, sizeflag);
15056 }
15057
15058 static void
15059 OP_Vex_2src_2 (int bytemode, int sizeflag)
15060 {
15061   if (vex.w)
15062     OP_Vex_2src (bytemode, sizeflag);
15063   else
15064     oappend (names_xmm[vex.register_specifier]);
15065 }
15066
15067 static void
15068 OP_EX_VexW (int bytemode, int sizeflag)
15069 {
15070   int reg = -1;
15071
15072   if (!vex_w_done)
15073     {
15074       vex_w_done = 1;
15075
15076       /* Skip mod/rm byte.  */
15077       MODRM_CHECK;
15078       codep++;
15079
15080       if (vex.w)
15081         reg = get_vex_imm8 (sizeflag, 0) >> 4;
15082     }
15083   else
15084     {
15085       if (!vex.w)
15086         reg = get_vex_imm8 (sizeflag, 1) >> 4;
15087     }
15088
15089   OP_EX_VexReg (bytemode, sizeflag, reg);
15090 }
15091
15092 static void
15093 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
15094              int sizeflag ATTRIBUTE_UNUSED)
15095 {
15096   /* Skip the immediate byte and check for invalid bits.  */
15097   FETCH_DATA (the_info, codep + 1);
15098   if (*codep++ & 0xf)
15099     BadOp ();
15100 }
15101
15102 static void
15103 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15104 {
15105   int reg;
15106   const char **names;
15107
15108   FETCH_DATA (the_info, codep + 1);
15109   reg = *codep++;
15110
15111   if (bytemode != x_mode)
15112     abort ();
15113
15114   if (reg & 0xf)
15115       BadOp ();
15116
15117   reg >>= 4;
15118   if (reg > 7 && address_mode != mode_64bit)
15119     BadOp ();
15120
15121   switch (vex.length)
15122     {
15123     case 128:
15124       names = names_xmm;
15125       break;
15126     case 256:
15127       names = names_ymm;
15128       break;
15129     default:
15130       abort ();
15131     }
15132   oappend (names[reg]);
15133 }
15134
15135 static void
15136 OP_XMM_VexW (int bytemode, int sizeflag)
15137 {
15138   /* Turn off the REX.W bit since it is used for swapping operands
15139      now.  */
15140   rex &= ~REX_W;
15141   OP_XMM (bytemode, sizeflag);
15142 }
15143
15144 static void
15145 OP_EX_Vex (int bytemode, int sizeflag)
15146 {
15147   if (modrm.mod != 3)
15148     {
15149       if (vex.register_specifier != 0)
15150         BadOp ();
15151       need_vex_reg = 0;
15152     }
15153   OP_EX (bytemode, sizeflag);
15154 }
15155
15156 static void
15157 OP_XMM_Vex (int bytemode, int sizeflag)
15158 {
15159   if (modrm.mod != 3)
15160     {
15161       if (vex.register_specifier != 0)
15162         BadOp ();
15163       need_vex_reg = 0;
15164     }
15165   OP_XMM (bytemode, sizeflag);
15166 }
15167
15168 static void
15169 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15170 {
15171   switch (vex.length)
15172     {
15173     case 128:
15174       mnemonicendp = stpcpy (obuf, "vzeroupper");
15175       break;
15176     case 256:
15177       mnemonicendp = stpcpy (obuf, "vzeroall");
15178       break;
15179     default:
15180       abort ();
15181     }
15182 }
15183
15184 static struct op vex_cmp_op[] =
15185 {
15186   { STRING_COMMA_LEN ("eq") },
15187   { STRING_COMMA_LEN ("lt") },
15188   { STRING_COMMA_LEN ("le") },
15189   { STRING_COMMA_LEN ("unord") },
15190   { STRING_COMMA_LEN ("neq") },
15191   { STRING_COMMA_LEN ("nlt") },
15192   { STRING_COMMA_LEN ("nle") },
15193   { STRING_COMMA_LEN ("ord") },
15194   { STRING_COMMA_LEN ("eq_uq") },
15195   { STRING_COMMA_LEN ("nge") },
15196   { STRING_COMMA_LEN ("ngt") },
15197   { STRING_COMMA_LEN ("false") },
15198   { STRING_COMMA_LEN ("neq_oq") },
15199   { STRING_COMMA_LEN ("ge") },
15200   { STRING_COMMA_LEN ("gt") },
15201   { STRING_COMMA_LEN ("true") },
15202   { STRING_COMMA_LEN ("eq_os") },
15203   { STRING_COMMA_LEN ("lt_oq") },
15204   { STRING_COMMA_LEN ("le_oq") },
15205   { STRING_COMMA_LEN ("unord_s") },
15206   { STRING_COMMA_LEN ("neq_us") },
15207   { STRING_COMMA_LEN ("nlt_uq") },
15208   { STRING_COMMA_LEN ("nle_uq") },
15209   { STRING_COMMA_LEN ("ord_s") },
15210   { STRING_COMMA_LEN ("eq_us") },
15211   { STRING_COMMA_LEN ("nge_uq") },
15212   { STRING_COMMA_LEN ("ngt_uq") },
15213   { STRING_COMMA_LEN ("false_os") },
15214   { STRING_COMMA_LEN ("neq_os") },
15215   { STRING_COMMA_LEN ("ge_oq") },
15216   { STRING_COMMA_LEN ("gt_oq") },
15217   { STRING_COMMA_LEN ("true_us") },
15218 };
15219
15220 static void
15221 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15222 {
15223   unsigned int cmp_type;
15224
15225   FETCH_DATA (the_info, codep + 1);
15226   cmp_type = *codep++ & 0xff;
15227   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15228     {
15229       char suffix [3];
15230       char *p = mnemonicendp - 2;
15231       suffix[0] = p[0];
15232       suffix[1] = p[1];
15233       suffix[2] = '\0';
15234       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15235       mnemonicendp += vex_cmp_op[cmp_type].len;
15236     }
15237   else
15238     {
15239       /* We have a reserved extension byte.  Output it directly.  */
15240       scratchbuf[0] = '$';
15241       print_operand_value (scratchbuf + 1, 1, cmp_type);
15242       oappend (scratchbuf + intel_syntax);
15243       scratchbuf[0] = '\0';
15244     }
15245 }
15246
15247 static const struct op pclmul_op[] =
15248 {
15249   { STRING_COMMA_LEN ("lql") },
15250   { STRING_COMMA_LEN ("hql") },
15251   { STRING_COMMA_LEN ("lqh") },
15252   { STRING_COMMA_LEN ("hqh") }
15253 };
15254
15255 static void
15256 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15257               int sizeflag ATTRIBUTE_UNUSED)
15258 {
15259   unsigned int pclmul_type;
15260
15261   FETCH_DATA (the_info, codep + 1);
15262   pclmul_type = *codep++ & 0xff;
15263   switch (pclmul_type)
15264     {
15265     case 0x10:
15266       pclmul_type = 2;
15267       break;
15268     case 0x11:
15269       pclmul_type = 3;
15270       break;
15271     default:
15272       break;
15273     }
15274   if (pclmul_type < ARRAY_SIZE (pclmul_op))
15275     {
15276       char suffix [4];
15277       char *p = mnemonicendp - 3;
15278       suffix[0] = p[0];
15279       suffix[1] = p[1];
15280       suffix[2] = p[2];
15281       suffix[3] = '\0';
15282       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15283       mnemonicendp += pclmul_op[pclmul_type].len;
15284     }
15285   else
15286     {
15287       /* We have a reserved extension byte.  Output it directly.  */
15288       scratchbuf[0] = '$';
15289       print_operand_value (scratchbuf + 1, 1, pclmul_type);
15290       oappend (scratchbuf + intel_syntax);
15291       scratchbuf[0] = '\0';
15292     }
15293 }
15294
15295 static void
15296 MOVBE_Fixup (int bytemode, int sizeflag)
15297 {
15298   /* Add proper suffix to "movbe".  */
15299   char *p = mnemonicendp;
15300
15301   switch (bytemode)
15302     {
15303     case v_mode:
15304       if (intel_syntax)
15305         goto skip;
15306
15307       USED_REX (REX_W);
15308       if (sizeflag & SUFFIX_ALWAYS)
15309         {
15310           if (rex & REX_W)
15311             *p++ = 'q';
15312           else
15313             {
15314               if (sizeflag & DFLAG)
15315                 *p++ = 'l';
15316               else
15317                 *p++ = 'w';
15318               used_prefixes |= (prefixes & PREFIX_DATA);
15319             }
15320         }
15321       break;
15322     default:
15323       oappend (INTERNAL_DISASSEMBLER_ERROR);
15324       break;
15325     }
15326   mnemonicendp = p;
15327   *p = '\0';
15328
15329 skip:
15330   OP_M (bytemode, sizeflag);
15331 }
15332
15333 static void
15334 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15335 {
15336   int reg;
15337   const char **names;
15338
15339   /* Skip mod/rm byte.  */
15340   MODRM_CHECK;
15341   codep++;
15342
15343   if (vex.w)
15344     names = names64;
15345   else
15346     names = names32;
15347
15348   reg = modrm.rm;
15349   USED_REX (REX_B);
15350   if (rex & REX_B)
15351     reg += 8;
15352
15353   oappend (names[reg]);
15354 }
15355
15356 static void
15357 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15358 {
15359   const char **names;
15360
15361   if (vex.w)
15362     names = names64;
15363   else
15364     names = names32;
15365
15366   oappend (names[vex.register_specifier]);
15367 }