opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Edqa { OP_E, dqa_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVex { OP_EX_Vex, d_mode }
 430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 432 #define EXqVex { OP_EX_Vex, q_mode }
 433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 435 #define EXVexW { OP_EX_VexW, x_mode }
 436 #define EXdVexW { OP_EX_VexW, d_mode }
 437 #define EXqVexW { OP_EX_VexW, q_mode }
 438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 439 #define XMVex { OP_XMM_Vex, 0 }
 440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 441 #define XMVexW { OP_XMM_VexW, 0 }
 442 #define XMVexI4 { OP_REG_VexI4, x_mode }
 443 #define PCLMUL { PCLMUL_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446 #define VPCOM { VPCOM_Fixup, 0 }
 447
 448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 451
 452 #define XMask { OP_Mask, mask_mode }
 453 #define MaskG { OP_G, mask_mode }
 454 #define MaskE { OP_E, mask_mode }
 455 #define MaskBDE { OP_E, mask_bd_mode }
 456 #define MaskR { OP_R, mask_mode }
 457 #define MaskVex { OP_VEX, mask_mode }
 458
 459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 463
 464 /* Used handle "rep" prefix for string instructions.  */
 465 #define Xbr { REP_Fixup, eSI_reg }
 466 #define Xvr { REP_Fixup, eSI_reg }
 467 #define Ybr { REP_Fixup, eDI_reg }
 468 #define Yvr { REP_Fixup, eDI_reg }
 469 #define Yzr { REP_Fixup, eDI_reg }
 470 #define indirDXr { REP_Fixup, indir_dx_reg }
 471 #define ALr { REP_Fixup, al_reg }
 472 #define eAXr { REP_Fixup, eAX_reg }
 473
 474 /* Used handle HLE prefix for lockable instructions.  */
 475 #define Ebh1 { HLE_Fixup1, b_mode }
 476 #define Evh1 { HLE_Fixup1, v_mode }
 477 #define Ebh2 { HLE_Fixup2, b_mode }
 478 #define Evh2 { HLE_Fixup2, v_mode }
 479 #define Ebh3 { HLE_Fixup3, b_mode }
 480 #define Evh3 { HLE_Fixup3, v_mode }
 481
 482 #define BND { BND_Fixup, 0 }
 483 #define NOTRACK { NOTRACK_Fixup, 0 }
 484
 485 #define cond_jump_flag { NULL, cond_jump_mode }
 486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 487
 488 /* bits in sizeflag */
 489 #define SUFFIX_ALWAYS 4
 490 #define AFLAG 2
 491 #define DFLAG 1
 492
 493 enum
 494 {
 495   /* byte operand */
 496   b_mode = 1,
 497   /* byte operand with operand swapped */
 498   b_swap_mode,
 499   /* byte operand, sign extend like 'T' suffix */
 500   b_T_mode,
 501   /* operand size depends on prefixes */
 502   v_mode,
 503   /* operand size depends on prefixes with operand swapped */
 504   v_swap_mode,
 505   /* operand size depends on address prefix */
 506   va_mode,
 507   /* word operand */
 508   w_mode,
 509   /* double word operand  */
 510   d_mode,
 511   /* double word operand with operand swapped */
 512   d_swap_mode,
 513   /* quad word operand */
 514   q_mode,
 515   /* quad word operand with operand swapped */
 516   q_swap_mode,
 517   /* ten-byte operand */
 518   t_mode,
 519   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 520      broadcast enabled.  */
 521   x_mode,
 522   /* Similar to x_mode, but with different EVEX mem shifts.  */
 523   evex_x_gscat_mode,
 524   /* Similar to x_mode, but with disabled broadcast.  */
 525   evex_x_nobcst_mode,
 526   /* Similar to x_mode, but with operands swapped and disabled broadcast
 527      in EVEX.  */
 528   x_swap_mode,
 529   /* 16-byte XMM operand */
 530   xmm_mode,
 531   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 532      memory operand (depending on vector length).  Broadcast isn't
 533      allowed.  */
 534   xmmq_mode,
 535   /* Same as xmmq_mode, but broadcast is allowed.  */
 536   evex_half_bcst_xmmq_mode,
 537   /* XMM register or byte memory operand */
 538   xmm_mb_mode,
 539   /* XMM register or word memory operand */
 540   xmm_mw_mode,
 541   /* XMM register or double word memory operand */
 542   xmm_md_mode,
 543   /* XMM register or quad word memory operand */
 544   xmm_mq_mode,
 545   /* XMM register or double/quad word memory operand, depending on
 546      VEX.W.  */
 547   xmm_mdq_mode,
 548   /* 16-byte XMM, word, double word or quad word operand.  */
 549   xmmdw_mode,
 550   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 551   xmmqd_mode,
 552   /* 32-byte YMM operand */
 553   ymm_mode,
 554   /* quad word, ymmword or zmmword memory operand.  */
 555   ymmq_mode,
 556   /* 32-byte YMM or 16-byte word operand */
 557   ymmxmm_mode,
 558   /* d_mode in 32bit, q_mode in 64bit mode.  */
 559   m_mode,
 560   /* pair of v_mode operands */
 561   a_mode,
 562   cond_jump_mode,
 563   loop_jcxz_mode,
 564   v_bnd_mode,
 565   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 566   v_bndmk_mode,
 567   /* operand size depends on REX prefixes.  */
 568   dq_mode,
 569   /* registers like dq_mode, memory like w_mode.  */
 570   dqw_mode,
 571   /* bounds operand */
 572   bnd_mode,
 573   /* bounds operand with operand swapped */
 574   bnd_swap_mode,
 575   /* 4- or 6-byte pointer operand */
 576   f_mode,
 577   const_1_mode,
 578   /* v_mode for indirect branch opcodes.  */
 579   indir_v_mode,
 580   /* v_mode for stack-related opcodes.  */
 581   stack_v_mode,
 582   /* non-quad operand size depends on prefixes */
 583   z_mode,
 584   /* 16-byte operand */
 585   o_mode,
 586   /* registers like dq_mode, memory like b_mode.  */
 587   dqb_mode,
 588   /* registers like d_mode, memory like b_mode.  */
 589   db_mode,
 590   /* registers like d_mode, memory like w_mode.  */
 591   dw_mode,
 592   /* registers like dq_mode, memory like d_mode.  */
 593   dqd_mode,
 594   /* operand size depends on the W bit as well as address mode.  */
 595   dqa_mode,
 596   /* normal vex mode */
 597   vex_mode,
 598   /* 128bit vex mode */
 599   vex128_mode,
 600   /* 256bit vex mode */
 601   vex256_mode,
 602   /* operand size depends on the VEX.W bit.  */
 603   vex_w_dq_mode,
 604
 605   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 606   vex_vsib_d_w_dq_mode,
 607   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 608   vex_vsib_d_w_d_mode,
 609   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 610   vex_vsib_q_w_dq_mode,
 611   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 612   vex_vsib_q_w_d_mode,
 613
 614   /* scalar, ignore vector length.  */
 615   scalar_mode,
 616   /* like b_mode, ignore vector length.  */
 617   b_scalar_mode,
 618   /* like w_mode, ignore vector length.  */
 619   w_scalar_mode,
 620   /* like d_mode, ignore vector length.  */
 621   d_scalar_mode,
 622   /* like d_swap_mode, ignore vector length.  */
 623   d_scalar_swap_mode,
 624   /* like q_mode, ignore vector length.  */
 625   q_scalar_mode,
 626   /* like q_swap_mode, ignore vector length.  */
 627   q_scalar_swap_mode,
 628   /* like vex_mode, ignore vector length.  */
 629   vex_scalar_mode,
 630   /* like vex_w_dq_mode, ignore vector length.  */
 631   vex_scalar_w_dq_mode,
 632
 633   /* Static rounding.  */
 634   evex_rounding_mode,
 635   /* Static rounding, 64-bit mode only.  */
 636   evex_rounding_64_mode,
 637   /* Supress all exceptions.  */
 638   evex_sae_mode,
 639
 640   /* Mask register operand.  */
 641   mask_mode,
 642   /* Mask register operand.  */
 643   mask_bd_mode,
 644
 645   es_reg,
 646   cs_reg,
 647   ss_reg,
 648   ds_reg,
 649   fs_reg,
 650   gs_reg,
 651
 652   eAX_reg,
 653   eCX_reg,
 654   eDX_reg,
 655   eBX_reg,
 656   eSP_reg,
 657   eBP_reg,
 658   eSI_reg,
 659   eDI_reg,
 660
 661   al_reg,
 662   cl_reg,
 663   dl_reg,
 664   bl_reg,
 665   ah_reg,
 666   ch_reg,
 667   dh_reg,
 668   bh_reg,
 669
 670   ax_reg,
 671   cx_reg,
 672   dx_reg,
 673   bx_reg,
 674   sp_reg,
 675   bp_reg,
 676   si_reg,
 677   di_reg,
 678
 679   rAX_reg,
 680   rCX_reg,
 681   rDX_reg,
 682   rBX_reg,
 683   rSP_reg,
 684   rBP_reg,
 685   rSI_reg,
 686   rDI_reg,
 687
 688   z_mode_ax_reg,
 689   indir_dx_reg
 690 };
 691
 692 enum
 693 {
 694   FLOATCODE = 1,
 695   USE_REG_TABLE,
 696   USE_MOD_TABLE,
 697   USE_RM_TABLE,
 698   USE_PREFIX_TABLE,
 699   USE_X86_64_TABLE,
 700   USE_3BYTE_TABLE,
 701   USE_XOP_8F_TABLE,
 702   USE_VEX_C4_TABLE,
 703   USE_VEX_C5_TABLE,
 704   USE_VEX_LEN_TABLE,
 705   USE_VEX_W_TABLE,
 706   USE_EVEX_TABLE,
 707   USE_EVEX_LEN_TABLE
 708 };
 709
 710 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 711
 712 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 713 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 714 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 715 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 716 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 717 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 718 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 719 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 720 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 721 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 722 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 723 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 724 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 725 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 726 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 727 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 728
 729 enum
 730 {
 731   REG_80 = 0,
 732   REG_81,
 733   REG_83,
 734   REG_8F,
 735   REG_C0,
 736   REG_C1,
 737   REG_C6,
 738   REG_C7,
 739   REG_D0,
 740   REG_D1,
 741   REG_D2,
 742   REG_D3,
 743   REG_F6,
 744   REG_F7,
 745   REG_FE,
 746   REG_FF,
 747   REG_0F00,
 748   REG_0F01,
 749   REG_0F0D,
 750   REG_0F18,
 751   REG_0F1C_MOD_0,
 752   REG_0F1E_MOD_3,
 753   REG_0F71,
 754   REG_0F72,
 755   REG_0F73,
 756   REG_0FA6,
 757   REG_0FA7,
 758   REG_0FAE,
 759   REG_0FBA,
 760   REG_0FC7,
 761   REG_VEX_0F71,
 762   REG_VEX_0F72,
 763   REG_VEX_0F73,
 764   REG_VEX_0FAE,
 765   REG_VEX_0F38F3,
 766   REG_XOP_LWPCB,
 767   REG_XOP_LWP,
 768   REG_XOP_TBM_01,
 769   REG_XOP_TBM_02,
 770
 771   REG_EVEX_0F71,
 772   REG_EVEX_0F72,
 773   REG_EVEX_0F73,
 774   REG_EVEX_0F38C6,
 775   REG_EVEX_0F38C7
 776 };
 777
 778 enum
 779 {
 780   MOD_8D = 0,
 781   MOD_C6_REG_7,
 782   MOD_C7_REG_7,
 783   MOD_FF_REG_3,
 784   MOD_FF_REG_5,
 785   MOD_0F01_REG_0,
 786   MOD_0F01_REG_1,
 787   MOD_0F01_REG_2,
 788   MOD_0F01_REG_3,
 789   MOD_0F01_REG_5,
 790   MOD_0F01_REG_7,
 791   MOD_0F12_PREFIX_0,
 792   MOD_0F13,
 793   MOD_0F16_PREFIX_0,
 794   MOD_0F17,
 795   MOD_0F18_REG_0,
 796   MOD_0F18_REG_1,
 797   MOD_0F18_REG_2,
 798   MOD_0F18_REG_3,
 799   MOD_0F18_REG_4,
 800   MOD_0F18_REG_5,
 801   MOD_0F18_REG_6,
 802   MOD_0F18_REG_7,
 803   MOD_0F1A_PREFIX_0,
 804   MOD_0F1B_PREFIX_0,
 805   MOD_0F1B_PREFIX_1,
 806   MOD_0F1C_PREFIX_0,
 807   MOD_0F1E_PREFIX_1,
 808   MOD_0F24,
 809   MOD_0F26,
 810   MOD_0F2B_PREFIX_0,
 811   MOD_0F2B_PREFIX_1,
 812   MOD_0F2B_PREFIX_2,
 813   MOD_0F2B_PREFIX_3,
 814   MOD_0F51,
 815   MOD_0F71_REG_2,
 816   MOD_0F71_REG_4,
 817   MOD_0F71_REG_6,
 818   MOD_0F72_REG_2,
 819   MOD_0F72_REG_4,
 820   MOD_0F72_REG_6,
 821   MOD_0F73_REG_2,
 822   MOD_0F73_REG_3,
 823   MOD_0F73_REG_6,
 824   MOD_0F73_REG_7,
 825   MOD_0FAE_REG_0,
 826   MOD_0FAE_REG_1,
 827   MOD_0FAE_REG_2,
 828   MOD_0FAE_REG_3,
 829   MOD_0FAE_REG_4,
 830   MOD_0FAE_REG_5,
 831   MOD_0FAE_REG_6,
 832   MOD_0FAE_REG_7,
 833   MOD_0FB2,
 834   MOD_0FB4,
 835   MOD_0FB5,
 836   MOD_0FC3,
 837   MOD_0FC7_REG_3,
 838   MOD_0FC7_REG_4,
 839   MOD_0FC7_REG_5,
 840   MOD_0FC7_REG_6,
 841   MOD_0FC7_REG_7,
 842   MOD_0FD7,
 843   MOD_0FE7_PREFIX_2,
 844   MOD_0FF0_PREFIX_3,
 845   MOD_0F382A_PREFIX_2,
 846   MOD_0F38F5_PREFIX_2,
 847   MOD_0F38F6_PREFIX_0,
 848   MOD_0F38F8_PREFIX_2,
 849   MOD_0F38F9_PREFIX_0,
 850   MOD_62_32BIT,
 851   MOD_C4_32BIT,
 852   MOD_C5_32BIT,
 853   MOD_VEX_0F12_PREFIX_0,
 854   MOD_VEX_0F13,
 855   MOD_VEX_0F16_PREFIX_0,
 856   MOD_VEX_0F17,
 857   MOD_VEX_0F2B,
 858   MOD_VEX_W_0_0F41_P_0_LEN_1,
 859   MOD_VEX_W_1_0F41_P_0_LEN_1,
 860   MOD_VEX_W_0_0F41_P_2_LEN_1,
 861   MOD_VEX_W_1_0F41_P_2_LEN_1,
 862   MOD_VEX_W_0_0F42_P_0_LEN_1,
 863   MOD_VEX_W_1_0F42_P_0_LEN_1,
 864   MOD_VEX_W_0_0F42_P_2_LEN_1,
 865   MOD_VEX_W_1_0F42_P_2_LEN_1,
 866   MOD_VEX_W_0_0F44_P_0_LEN_1,
 867   MOD_VEX_W_1_0F44_P_0_LEN_1,
 868   MOD_VEX_W_0_0F44_P_2_LEN_1,
 869   MOD_VEX_W_1_0F44_P_2_LEN_1,
 870   MOD_VEX_W_0_0F45_P_0_LEN_1,
 871   MOD_VEX_W_1_0F45_P_0_LEN_1,
 872   MOD_VEX_W_0_0F45_P_2_LEN_1,
 873   MOD_VEX_W_1_0F45_P_2_LEN_1,
 874   MOD_VEX_W_0_0F46_P_0_LEN_1,
 875   MOD_VEX_W_1_0F46_P_0_LEN_1,
 876   MOD_VEX_W_0_0F46_P_2_LEN_1,
 877   MOD_VEX_W_1_0F46_P_2_LEN_1,
 878   MOD_VEX_W_0_0F47_P_0_LEN_1,
 879   MOD_VEX_W_1_0F47_P_0_LEN_1,
 880   MOD_VEX_W_0_0F47_P_2_LEN_1,
 881   MOD_VEX_W_1_0F47_P_2_LEN_1,
 882   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 883   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 884   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 885   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 886   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 887   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 888   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 889   MOD_VEX_0F50,
 890   MOD_VEX_0F71_REG_2,
 891   MOD_VEX_0F71_REG_4,
 892   MOD_VEX_0F71_REG_6,
 893   MOD_VEX_0F72_REG_2,
 894   MOD_VEX_0F72_REG_4,
 895   MOD_VEX_0F72_REG_6,
 896   MOD_VEX_0F73_REG_2,
 897   MOD_VEX_0F73_REG_3,
 898   MOD_VEX_0F73_REG_6,
 899   MOD_VEX_0F73_REG_7,
 900   MOD_VEX_W_0_0F91_P_0_LEN_0,
 901   MOD_VEX_W_1_0F91_P_0_LEN_0,
 902   MOD_VEX_W_0_0F91_P_2_LEN_0,
 903   MOD_VEX_W_1_0F91_P_2_LEN_0,
 904   MOD_VEX_W_0_0F92_P_0_LEN_0,
 905   MOD_VEX_W_0_0F92_P_2_LEN_0,
 906   MOD_VEX_0F92_P_3_LEN_0,
 907   MOD_VEX_W_0_0F93_P_0_LEN_0,
 908   MOD_VEX_W_0_0F93_P_2_LEN_0,
 909   MOD_VEX_0F93_P_3_LEN_0,
 910   MOD_VEX_W_0_0F98_P_0_LEN_0,
 911   MOD_VEX_W_1_0F98_P_0_LEN_0,
 912   MOD_VEX_W_0_0F98_P_2_LEN_0,
 913   MOD_VEX_W_1_0F98_P_2_LEN_0,
 914   MOD_VEX_W_0_0F99_P_0_LEN_0,
 915   MOD_VEX_W_1_0F99_P_0_LEN_0,
 916   MOD_VEX_W_0_0F99_P_2_LEN_0,
 917   MOD_VEX_W_1_0F99_P_2_LEN_0,
 918   MOD_VEX_0FAE_REG_2,
 919   MOD_VEX_0FAE_REG_3,
 920   MOD_VEX_0FD7_PREFIX_2,
 921   MOD_VEX_0FE7_PREFIX_2,
 922   MOD_VEX_0FF0_PREFIX_3,
 923   MOD_VEX_0F381A_PREFIX_2,
 924   MOD_VEX_0F382A_PREFIX_2,
 925   MOD_VEX_0F382C_PREFIX_2,
 926   MOD_VEX_0F382D_PREFIX_2,
 927   MOD_VEX_0F382E_PREFIX_2,
 928   MOD_VEX_0F382F_PREFIX_2,
 929   MOD_VEX_0F385A_PREFIX_2,
 930   MOD_VEX_0F388C_PREFIX_2,
 931   MOD_VEX_0F388E_PREFIX_2,
 932   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 933   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 934   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 938   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 939   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 940
 941   MOD_EVEX_0F10_PREFIX_1,
 942   MOD_EVEX_0F10_PREFIX_3,
 943   MOD_EVEX_0F11_PREFIX_1,
 944   MOD_EVEX_0F11_PREFIX_3,
 945   MOD_EVEX_0F12_PREFIX_0,
 946   MOD_EVEX_0F16_PREFIX_0,
 947   MOD_EVEX_0F38C6_REG_1,
 948   MOD_EVEX_0F38C6_REG_2,
 949   MOD_EVEX_0F38C6_REG_5,
 950   MOD_EVEX_0F38C6_REG_6,
 951   MOD_EVEX_0F38C7_REG_1,
 952   MOD_EVEX_0F38C7_REG_2,
 953   MOD_EVEX_0F38C7_REG_5,
 954   MOD_EVEX_0F38C7_REG_6
 955 };
 956
 957 enum
 958 {
 959   RM_C6_REG_7 = 0,
 960   RM_C7_REG_7,
 961   RM_0F01_REG_0,
 962   RM_0F01_REG_1,
 963   RM_0F01_REG_2,
 964   RM_0F01_REG_3,
 965   RM_0F01_REG_5,
 966   RM_0F01_REG_7,
 967   RM_0F1E_MOD_3_REG_7,
 968   RM_0FAE_REG_6,
 969   RM_0FAE_REG_7
 970 };
 971
 972 enum
 973 {
 974   PREFIX_90 = 0,
 975   PREFIX_MOD_0_0F01_REG_5,
 976   PREFIX_MOD_3_0F01_REG_5_RM_0,
 977   PREFIX_MOD_3_0F01_REG_5_RM_2,
 978   PREFIX_0F09,
 979   PREFIX_0F10,
 980   PREFIX_0F11,
 981   PREFIX_0F12,
 982   PREFIX_0F16,
 983   PREFIX_0F1A,
 984   PREFIX_0F1B,
 985   PREFIX_0F1C,
 986   PREFIX_0F1E,
 987   PREFIX_0F2A,
 988   PREFIX_0F2B,
 989   PREFIX_0F2C,
 990   PREFIX_0F2D,
 991   PREFIX_0F2E,
 992   PREFIX_0F2F,
 993   PREFIX_0F51,
 994   PREFIX_0F52,
 995   PREFIX_0F53,
 996   PREFIX_0F58,
 997   PREFIX_0F59,
 998   PREFIX_0F5A,
 999   PREFIX_0F5B,
1000   PREFIX_0F5C,
1001   PREFIX_0F5D,
1002   PREFIX_0F5E,
1003   PREFIX_0F5F,
1004   PREFIX_0F60,
1005   PREFIX_0F61,
1006   PREFIX_0F62,
1007   PREFIX_0F6C,
1008   PREFIX_0F6D,
1009   PREFIX_0F6F,
1010   PREFIX_0F70,
1011   PREFIX_0F73_REG_3,
1012   PREFIX_0F73_REG_7,
1013   PREFIX_0F78,
1014   PREFIX_0F79,
1015   PREFIX_0F7C,
1016   PREFIX_0F7D,
1017   PREFIX_0F7E,
1018   PREFIX_0F7F,
1019   PREFIX_0FAE_REG_0,
1020   PREFIX_0FAE_REG_1,
1021   PREFIX_0FAE_REG_2,
1022   PREFIX_0FAE_REG_3,
1023   PREFIX_MOD_0_0FAE_REG_4,
1024   PREFIX_MOD_3_0FAE_REG_4,
1025   PREFIX_MOD_0_0FAE_REG_5,
1026   PREFIX_MOD_3_0FAE_REG_5,
1027   PREFIX_MOD_0_0FAE_REG_6,
1028   PREFIX_MOD_1_0FAE_REG_6,
1029   PREFIX_0FAE_REG_7,
1030   PREFIX_0FB8,
1031   PREFIX_0FBC,
1032   PREFIX_0FBD,
1033   PREFIX_0FC2,
1034   PREFIX_MOD_0_0FC3,
1035   PREFIX_MOD_0_0FC7_REG_6,
1036   PREFIX_MOD_3_0FC7_REG_6,
1037   PREFIX_MOD_3_0FC7_REG_7,
1038   PREFIX_0FD0,
1039   PREFIX_0FD6,
1040   PREFIX_0FE6,
1041   PREFIX_0FE7,
1042   PREFIX_0FF0,
1043   PREFIX_0FF7,
1044   PREFIX_0F3810,
1045   PREFIX_0F3814,
1046   PREFIX_0F3815,
1047   PREFIX_0F3817,
1048   PREFIX_0F3820,
1049   PREFIX_0F3821,
1050   PREFIX_0F3822,
1051   PREFIX_0F3823,
1052   PREFIX_0F3824,
1053   PREFIX_0F3825,
1054   PREFIX_0F3828,
1055   PREFIX_0F3829,
1056   PREFIX_0F382A,
1057   PREFIX_0F382B,
1058   PREFIX_0F3830,
1059   PREFIX_0F3831,
1060   PREFIX_0F3832,
1061   PREFIX_0F3833,
1062   PREFIX_0F3834,
1063   PREFIX_0F3835,
1064   PREFIX_0F3837,
1065   PREFIX_0F3838,
1066   PREFIX_0F3839,
1067   PREFIX_0F383A,
1068   PREFIX_0F383B,
1069   PREFIX_0F383C,
1070   PREFIX_0F383D,
1071   PREFIX_0F383E,
1072   PREFIX_0F383F,
1073   PREFIX_0F3840,
1074   PREFIX_0F3841,
1075   PREFIX_0F3880,
1076   PREFIX_0F3881,
1077   PREFIX_0F3882,
1078   PREFIX_0F38C8,
1079   PREFIX_0F38C9,
1080   PREFIX_0F38CA,
1081   PREFIX_0F38CB,
1082   PREFIX_0F38CC,
1083   PREFIX_0F38CD,
1084   PREFIX_0F38CF,
1085   PREFIX_0F38DB,
1086   PREFIX_0F38DC,
1087   PREFIX_0F38DD,
1088   PREFIX_0F38DE,
1089   PREFIX_0F38DF,
1090   PREFIX_0F38F0,
1091   PREFIX_0F38F1,
1092   PREFIX_0F38F5,
1093   PREFIX_0F38F6,
1094   PREFIX_0F38F8,
1095   PREFIX_0F38F9,
1096   PREFIX_0F3A08,
1097   PREFIX_0F3A09,
1098   PREFIX_0F3A0A,
1099   PREFIX_0F3A0B,
1100   PREFIX_0F3A0C,
1101   PREFIX_0F3A0D,
1102   PREFIX_0F3A0E,
1103   PREFIX_0F3A14,
1104   PREFIX_0F3A15,
1105   PREFIX_0F3A16,
1106   PREFIX_0F3A17,
1107   PREFIX_0F3A20,
1108   PREFIX_0F3A21,
1109   PREFIX_0F3A22,
1110   PREFIX_0F3A40,
1111   PREFIX_0F3A41,
1112   PREFIX_0F3A42,
1113   PREFIX_0F3A44,
1114   PREFIX_0F3A60,
1115   PREFIX_0F3A61,
1116   PREFIX_0F3A62,
1117   PREFIX_0F3A63,
1118   PREFIX_0F3ACC,
1119   PREFIX_0F3ACE,
1120   PREFIX_0F3ACF,
1121   PREFIX_0F3ADF,
1122   PREFIX_VEX_0F10,
1123   PREFIX_VEX_0F11,
1124   PREFIX_VEX_0F12,
1125   PREFIX_VEX_0F16,
1126   PREFIX_VEX_0F2A,
1127   PREFIX_VEX_0F2C,
1128   PREFIX_VEX_0F2D,
1129   PREFIX_VEX_0F2E,
1130   PREFIX_VEX_0F2F,
1131   PREFIX_VEX_0F41,
1132   PREFIX_VEX_0F42,
1133   PREFIX_VEX_0F44,
1134   PREFIX_VEX_0F45,
1135   PREFIX_VEX_0F46,
1136   PREFIX_VEX_0F47,
1137   PREFIX_VEX_0F4A,
1138   PREFIX_VEX_0F4B,
1139   PREFIX_VEX_0F51,
1140   PREFIX_VEX_0F52,
1141   PREFIX_VEX_0F53,
1142   PREFIX_VEX_0F58,
1143   PREFIX_VEX_0F59,
1144   PREFIX_VEX_0F5A,
1145   PREFIX_VEX_0F5B,
1146   PREFIX_VEX_0F5C,
1147   PREFIX_VEX_0F5D,
1148   PREFIX_VEX_0F5E,
1149   PREFIX_VEX_0F5F,
1150   PREFIX_VEX_0F60,
1151   PREFIX_VEX_0F61,
1152   PREFIX_VEX_0F62,
1153   PREFIX_VEX_0F63,
1154   PREFIX_VEX_0F64,
1155   PREFIX_VEX_0F65,
1156   PREFIX_VEX_0F66,
1157   PREFIX_VEX_0F67,
1158   PREFIX_VEX_0F68,
1159   PREFIX_VEX_0F69,
1160   PREFIX_VEX_0F6A,
1161   PREFIX_VEX_0F6B,
1162   PREFIX_VEX_0F6C,
1163   PREFIX_VEX_0F6D,
1164   PREFIX_VEX_0F6E,
1165   PREFIX_VEX_0F6F,
1166   PREFIX_VEX_0F70,
1167   PREFIX_VEX_0F71_REG_2,
1168   PREFIX_VEX_0F71_REG_4,
1169   PREFIX_VEX_0F71_REG_6,
1170   PREFIX_VEX_0F72_REG_2,
1171   PREFIX_VEX_0F72_REG_4,
1172   PREFIX_VEX_0F72_REG_6,
1173   PREFIX_VEX_0F73_REG_2,
1174   PREFIX_VEX_0F73_REG_3,
1175   PREFIX_VEX_0F73_REG_6,
1176   PREFIX_VEX_0F73_REG_7,
1177   PREFIX_VEX_0F74,
1178   PREFIX_VEX_0F75,
1179   PREFIX_VEX_0F76,
1180   PREFIX_VEX_0F77,
1181   PREFIX_VEX_0F7C,
1182   PREFIX_VEX_0F7D,
1183   PREFIX_VEX_0F7E,
1184   PREFIX_VEX_0F7F,
1185   PREFIX_VEX_0F90,
1186   PREFIX_VEX_0F91,
1187   PREFIX_VEX_0F92,
1188   PREFIX_VEX_0F93,
1189   PREFIX_VEX_0F98,
1190   PREFIX_VEX_0F99,
1191   PREFIX_VEX_0FC2,
1192   PREFIX_VEX_0FC4,
1193   PREFIX_VEX_0FC5,
1194   PREFIX_VEX_0FD0,
1195   PREFIX_VEX_0FD1,
1196   PREFIX_VEX_0FD2,
1197   PREFIX_VEX_0FD3,
1198   PREFIX_VEX_0FD4,
1199   PREFIX_VEX_0FD5,
1200   PREFIX_VEX_0FD6,
1201   PREFIX_VEX_0FD7,
1202   PREFIX_VEX_0FD8,
1203   PREFIX_VEX_0FD9,
1204   PREFIX_VEX_0FDA,
1205   PREFIX_VEX_0FDB,
1206   PREFIX_VEX_0FDC,
1207   PREFIX_VEX_0FDD,
1208   PREFIX_VEX_0FDE,
1209   PREFIX_VEX_0FDF,
1210   PREFIX_VEX_0FE0,
1211   PREFIX_VEX_0FE1,
1212   PREFIX_VEX_0FE2,
1213   PREFIX_VEX_0FE3,
1214   PREFIX_VEX_0FE4,
1215   PREFIX_VEX_0FE5,
1216   PREFIX_VEX_0FE6,
1217   PREFIX_VEX_0FE7,
1218   PREFIX_VEX_0FE8,
1219   PREFIX_VEX_0FE9,
1220   PREFIX_VEX_0FEA,
1221   PREFIX_VEX_0FEB,
1222   PREFIX_VEX_0FEC,
1223   PREFIX_VEX_0FED,
1224   PREFIX_VEX_0FEE,
1225   PREFIX_VEX_0FEF,
1226   PREFIX_VEX_0FF0,
1227   PREFIX_VEX_0FF1,
1228   PREFIX_VEX_0FF2,
1229   PREFIX_VEX_0FF3,
1230   PREFIX_VEX_0FF4,
1231   PREFIX_VEX_0FF5,
1232   PREFIX_VEX_0FF6,
1233   PREFIX_VEX_0FF7,
1234   PREFIX_VEX_0FF8,
1235   PREFIX_VEX_0FF9,
1236   PREFIX_VEX_0FFA,
1237   PREFIX_VEX_0FFB,
1238   PREFIX_VEX_0FFC,
1239   PREFIX_VEX_0FFD,
1240   PREFIX_VEX_0FFE,
1241   PREFIX_VEX_0F3800,
1242   PREFIX_VEX_0F3801,
1243   PREFIX_VEX_0F3802,
1244   PREFIX_VEX_0F3803,
1245   PREFIX_VEX_0F3804,
1246   PREFIX_VEX_0F3805,
1247   PREFIX_VEX_0F3806,
1248   PREFIX_VEX_0F3807,
1249   PREFIX_VEX_0F3808,
1250   PREFIX_VEX_0F3809,
1251   PREFIX_VEX_0F380A,
1252   PREFIX_VEX_0F380B,
1253   PREFIX_VEX_0F380C,
1254   PREFIX_VEX_0F380D,
1255   PREFIX_VEX_0F380E,
1256   PREFIX_VEX_0F380F,
1257   PREFIX_VEX_0F3813,
1258   PREFIX_VEX_0F3816,
1259   PREFIX_VEX_0F3817,
1260   PREFIX_VEX_0F3818,
1261   PREFIX_VEX_0F3819,
1262   PREFIX_VEX_0F381A,
1263   PREFIX_VEX_0F381C,
1264   PREFIX_VEX_0F381D,
1265   PREFIX_VEX_0F381E,
1266   PREFIX_VEX_0F3820,
1267   PREFIX_VEX_0F3821,
1268   PREFIX_VEX_0F3822,
1269   PREFIX_VEX_0F3823,
1270   PREFIX_VEX_0F3824,
1271   PREFIX_VEX_0F3825,
1272   PREFIX_VEX_0F3828,
1273   PREFIX_VEX_0F3829,
1274   PREFIX_VEX_0F382A,
1275   PREFIX_VEX_0F382B,
1276   PREFIX_VEX_0F382C,
1277   PREFIX_VEX_0F382D,
1278   PREFIX_VEX_0F382E,
1279   PREFIX_VEX_0F382F,
1280   PREFIX_VEX_0F3830,
1281   PREFIX_VEX_0F3831,
1282   PREFIX_VEX_0F3832,
1283   PREFIX_VEX_0F3833,
1284   PREFIX_VEX_0F3834,
1285   PREFIX_VEX_0F3835,
1286   PREFIX_VEX_0F3836,
1287   PREFIX_VEX_0F3837,
1288   PREFIX_VEX_0F3838,
1289   PREFIX_VEX_0F3839,
1290   PREFIX_VEX_0F383A,
1291   PREFIX_VEX_0F383B,
1292   PREFIX_VEX_0F383C,
1293   PREFIX_VEX_0F383D,
1294   PREFIX_VEX_0F383E,
1295   PREFIX_VEX_0F383F,
1296   PREFIX_VEX_0F3840,
1297   PREFIX_VEX_0F3841,
1298   PREFIX_VEX_0F3845,
1299   PREFIX_VEX_0F3846,
1300   PREFIX_VEX_0F3847,
1301   PREFIX_VEX_0F3858,
1302   PREFIX_VEX_0F3859,
1303   PREFIX_VEX_0F385A,
1304   PREFIX_VEX_0F3878,
1305   PREFIX_VEX_0F3879,
1306   PREFIX_VEX_0F388C,
1307   PREFIX_VEX_0F388E,
1308   PREFIX_VEX_0F3890,
1309   PREFIX_VEX_0F3891,
1310   PREFIX_VEX_0F3892,
1311   PREFIX_VEX_0F3893,
1312   PREFIX_VEX_0F3896,
1313   PREFIX_VEX_0F3897,
1314   PREFIX_VEX_0F3898,
1315   PREFIX_VEX_0F3899,
1316   PREFIX_VEX_0F389A,
1317   PREFIX_VEX_0F389B,
1318   PREFIX_VEX_0F389C,
1319   PREFIX_VEX_0F389D,
1320   PREFIX_VEX_0F389E,
1321   PREFIX_VEX_0F389F,
1322   PREFIX_VEX_0F38A6,
1323   PREFIX_VEX_0F38A7,
1324   PREFIX_VEX_0F38A8,
1325   PREFIX_VEX_0F38A9,
1326   PREFIX_VEX_0F38AA,
1327   PREFIX_VEX_0F38AB,
1328   PREFIX_VEX_0F38AC,
1329   PREFIX_VEX_0F38AD,
1330   PREFIX_VEX_0F38AE,
1331   PREFIX_VEX_0F38AF,
1332   PREFIX_VEX_0F38B6,
1333   PREFIX_VEX_0F38B7,
1334   PREFIX_VEX_0F38B8,
1335   PREFIX_VEX_0F38B9,
1336   PREFIX_VEX_0F38BA,
1337   PREFIX_VEX_0F38BB,
1338   PREFIX_VEX_0F38BC,
1339   PREFIX_VEX_0F38BD,
1340   PREFIX_VEX_0F38BE,
1341   PREFIX_VEX_0F38BF,
1342   PREFIX_VEX_0F38CF,
1343   PREFIX_VEX_0F38DB,
1344   PREFIX_VEX_0F38DC,
1345   PREFIX_VEX_0F38DD,
1346   PREFIX_VEX_0F38DE,
1347   PREFIX_VEX_0F38DF,
1348   PREFIX_VEX_0F38F2,
1349   PREFIX_VEX_0F38F3_REG_1,
1350   PREFIX_VEX_0F38F3_REG_2,
1351   PREFIX_VEX_0F38F3_REG_3,
1352   PREFIX_VEX_0F38F5,
1353   PREFIX_VEX_0F38F6,
1354   PREFIX_VEX_0F38F7,
1355   PREFIX_VEX_0F3A00,
1356   PREFIX_VEX_0F3A01,
1357   PREFIX_VEX_0F3A02,
1358   PREFIX_VEX_0F3A04,
1359   PREFIX_VEX_0F3A05,
1360   PREFIX_VEX_0F3A06,
1361   PREFIX_VEX_0F3A08,
1362   PREFIX_VEX_0F3A09,
1363   PREFIX_VEX_0F3A0A,
1364   PREFIX_VEX_0F3A0B,
1365   PREFIX_VEX_0F3A0C,
1366   PREFIX_VEX_0F3A0D,
1367   PREFIX_VEX_0F3A0E,
1368   PREFIX_VEX_0F3A0F,
1369   PREFIX_VEX_0F3A14,
1370   PREFIX_VEX_0F3A15,
1371   PREFIX_VEX_0F3A16,
1372   PREFIX_VEX_0F3A17,
1373   PREFIX_VEX_0F3A18,
1374   PREFIX_VEX_0F3A19,
1375   PREFIX_VEX_0F3A1D,
1376   PREFIX_VEX_0F3A20,
1377   PREFIX_VEX_0F3A21,
1378   PREFIX_VEX_0F3A22,
1379   PREFIX_VEX_0F3A30,
1380   PREFIX_VEX_0F3A31,
1381   PREFIX_VEX_0F3A32,
1382   PREFIX_VEX_0F3A33,
1383   PREFIX_VEX_0F3A38,
1384   PREFIX_VEX_0F3A39,
1385   PREFIX_VEX_0F3A40,
1386   PREFIX_VEX_0F3A41,
1387   PREFIX_VEX_0F3A42,
1388   PREFIX_VEX_0F3A44,
1389   PREFIX_VEX_0F3A46,
1390   PREFIX_VEX_0F3A48,
1391   PREFIX_VEX_0F3A49,
1392   PREFIX_VEX_0F3A4A,
1393   PREFIX_VEX_0F3A4B,
1394   PREFIX_VEX_0F3A4C,
1395   PREFIX_VEX_0F3A5C,
1396   PREFIX_VEX_0F3A5D,
1397   PREFIX_VEX_0F3A5E,
1398   PREFIX_VEX_0F3A5F,
1399   PREFIX_VEX_0F3A60,
1400   PREFIX_VEX_0F3A61,
1401   PREFIX_VEX_0F3A62,
1402   PREFIX_VEX_0F3A63,
1403   PREFIX_VEX_0F3A68,
1404   PREFIX_VEX_0F3A69,
1405   PREFIX_VEX_0F3A6A,
1406   PREFIX_VEX_0F3A6B,
1407   PREFIX_VEX_0F3A6C,
1408   PREFIX_VEX_0F3A6D,
1409   PREFIX_VEX_0F3A6E,
1410   PREFIX_VEX_0F3A6F,
1411   PREFIX_VEX_0F3A78,
1412   PREFIX_VEX_0F3A79,
1413   PREFIX_VEX_0F3A7A,
1414   PREFIX_VEX_0F3A7B,
1415   PREFIX_VEX_0F3A7C,
1416   PREFIX_VEX_0F3A7D,
1417   PREFIX_VEX_0F3A7E,
1418   PREFIX_VEX_0F3A7F,
1419   PREFIX_VEX_0F3ACE,
1420   PREFIX_VEX_0F3ACF,
1421   PREFIX_VEX_0F3ADF,
1422   PREFIX_VEX_0F3AF0,
1423
1424   PREFIX_EVEX_0F10,
1425   PREFIX_EVEX_0F11,
1426   PREFIX_EVEX_0F12,
1427   PREFIX_EVEX_0F13,
1428   PREFIX_EVEX_0F14,
1429   PREFIX_EVEX_0F15,
1430   PREFIX_EVEX_0F16,
1431   PREFIX_EVEX_0F17,
1432   PREFIX_EVEX_0F28,
1433   PREFIX_EVEX_0F29,
1434   PREFIX_EVEX_0F2A,
1435   PREFIX_EVEX_0F2B,
1436   PREFIX_EVEX_0F2C,
1437   PREFIX_EVEX_0F2D,
1438   PREFIX_EVEX_0F2E,
1439   PREFIX_EVEX_0F2F,
1440   PREFIX_EVEX_0F51,
1441   PREFIX_EVEX_0F54,
1442   PREFIX_EVEX_0F55,
1443   PREFIX_EVEX_0F56,
1444   PREFIX_EVEX_0F57,
1445   PREFIX_EVEX_0F58,
1446   PREFIX_EVEX_0F59,
1447   PREFIX_EVEX_0F5A,
1448   PREFIX_EVEX_0F5B,
1449   PREFIX_EVEX_0F5C,
1450   PREFIX_EVEX_0F5D,
1451   PREFIX_EVEX_0F5E,
1452   PREFIX_EVEX_0F5F,
1453   PREFIX_EVEX_0F60,
1454   PREFIX_EVEX_0F61,
1455   PREFIX_EVEX_0F62,
1456   PREFIX_EVEX_0F63,
1457   PREFIX_EVEX_0F64,
1458   PREFIX_EVEX_0F65,
1459   PREFIX_EVEX_0F66,
1460   PREFIX_EVEX_0F67,
1461   PREFIX_EVEX_0F68,
1462   PREFIX_EVEX_0F69,
1463   PREFIX_EVEX_0F6A,
1464   PREFIX_EVEX_0F6B,
1465   PREFIX_EVEX_0F6C,
1466   PREFIX_EVEX_0F6D,
1467   PREFIX_EVEX_0F6E,
1468   PREFIX_EVEX_0F6F,
1469   PREFIX_EVEX_0F70,
1470   PREFIX_EVEX_0F71_REG_2,
1471   PREFIX_EVEX_0F71_REG_4,
1472   PREFIX_EVEX_0F71_REG_6,
1473   PREFIX_EVEX_0F72_REG_0,
1474   PREFIX_EVEX_0F72_REG_1,
1475   PREFIX_EVEX_0F72_REG_2,
1476   PREFIX_EVEX_0F72_REG_4,
1477   PREFIX_EVEX_0F72_REG_6,
1478   PREFIX_EVEX_0F73_REG_2,
1479   PREFIX_EVEX_0F73_REG_3,
1480   PREFIX_EVEX_0F73_REG_6,
1481   PREFIX_EVEX_0F73_REG_7,
1482   PREFIX_EVEX_0F74,
1483   PREFIX_EVEX_0F75,
1484   PREFIX_EVEX_0F76,
1485   PREFIX_EVEX_0F78,
1486   PREFIX_EVEX_0F79,
1487   PREFIX_EVEX_0F7A,
1488   PREFIX_EVEX_0F7B,
1489   PREFIX_EVEX_0F7E,
1490   PREFIX_EVEX_0F7F,
1491   PREFIX_EVEX_0FC2,
1492   PREFIX_EVEX_0FC4,
1493   PREFIX_EVEX_0FC5,
1494   PREFIX_EVEX_0FC6,
1495   PREFIX_EVEX_0FD1,
1496   PREFIX_EVEX_0FD2,
1497   PREFIX_EVEX_0FD3,
1498   PREFIX_EVEX_0FD4,
1499   PREFIX_EVEX_0FD5,
1500   PREFIX_EVEX_0FD6,
1501   PREFIX_EVEX_0FD8,
1502   PREFIX_EVEX_0FD9,
1503   PREFIX_EVEX_0FDA,
1504   PREFIX_EVEX_0FDB,
1505   PREFIX_EVEX_0FDC,
1506   PREFIX_EVEX_0FDD,
1507   PREFIX_EVEX_0FDE,
1508   PREFIX_EVEX_0FDF,
1509   PREFIX_EVEX_0FE0,
1510   PREFIX_EVEX_0FE1,
1511   PREFIX_EVEX_0FE2,
1512   PREFIX_EVEX_0FE3,
1513   PREFIX_EVEX_0FE4,
1514   PREFIX_EVEX_0FE5,
1515   PREFIX_EVEX_0FE6,
1516   PREFIX_EVEX_0FE7,
1517   PREFIX_EVEX_0FE8,
1518   PREFIX_EVEX_0FE9,
1519   PREFIX_EVEX_0FEA,
1520   PREFIX_EVEX_0FEB,
1521   PREFIX_EVEX_0FEC,
1522   PREFIX_EVEX_0FED,
1523   PREFIX_EVEX_0FEE,
1524   PREFIX_EVEX_0FEF,
1525   PREFIX_EVEX_0FF1,
1526   PREFIX_EVEX_0FF2,
1527   PREFIX_EVEX_0FF3,
1528   PREFIX_EVEX_0FF4,
1529   PREFIX_EVEX_0FF5,
1530   PREFIX_EVEX_0FF6,
1531   PREFIX_EVEX_0FF8,
1532   PREFIX_EVEX_0FF9,
1533   PREFIX_EVEX_0FFA,
1534   PREFIX_EVEX_0FFB,
1535   PREFIX_EVEX_0FFC,
1536   PREFIX_EVEX_0FFD,
1537   PREFIX_EVEX_0FFE,
1538   PREFIX_EVEX_0F3800,
1539   PREFIX_EVEX_0F3804,
1540   PREFIX_EVEX_0F380B,
1541   PREFIX_EVEX_0F380C,
1542   PREFIX_EVEX_0F380D,
1543   PREFIX_EVEX_0F3810,
1544   PREFIX_EVEX_0F3811,
1545   PREFIX_EVEX_0F3812,
1546   PREFIX_EVEX_0F3813,
1547   PREFIX_EVEX_0F3814,
1548   PREFIX_EVEX_0F3815,
1549   PREFIX_EVEX_0F3816,
1550   PREFIX_EVEX_0F3818,
1551   PREFIX_EVEX_0F3819,
1552   PREFIX_EVEX_0F381A,
1553   PREFIX_EVEX_0F381B,
1554   PREFIX_EVEX_0F381C,
1555   PREFIX_EVEX_0F381D,
1556   PREFIX_EVEX_0F381E,
1557   PREFIX_EVEX_0F381F,
1558   PREFIX_EVEX_0F3820,
1559   PREFIX_EVEX_0F3821,
1560   PREFIX_EVEX_0F3822,
1561   PREFIX_EVEX_0F3823,
1562   PREFIX_EVEX_0F3824,
1563   PREFIX_EVEX_0F3825,
1564   PREFIX_EVEX_0F3826,
1565   PREFIX_EVEX_0F3827,
1566   PREFIX_EVEX_0F3828,
1567   PREFIX_EVEX_0F3829,
1568   PREFIX_EVEX_0F382A,
1569   PREFIX_EVEX_0F382B,
1570   PREFIX_EVEX_0F382C,
1571   PREFIX_EVEX_0F382D,
1572   PREFIX_EVEX_0F3830,
1573   PREFIX_EVEX_0F3831,
1574   PREFIX_EVEX_0F3832,
1575   PREFIX_EVEX_0F3833,
1576   PREFIX_EVEX_0F3834,
1577   PREFIX_EVEX_0F3835,
1578   PREFIX_EVEX_0F3836,
1579   PREFIX_EVEX_0F3837,
1580   PREFIX_EVEX_0F3838,
1581   PREFIX_EVEX_0F3839,
1582   PREFIX_EVEX_0F383A,
1583   PREFIX_EVEX_0F383B,
1584   PREFIX_EVEX_0F383C,
1585   PREFIX_EVEX_0F383D,
1586   PREFIX_EVEX_0F383E,
1587   PREFIX_EVEX_0F383F,
1588   PREFIX_EVEX_0F3840,
1589   PREFIX_EVEX_0F3842,
1590   PREFIX_EVEX_0F3843,
1591   PREFIX_EVEX_0F3844,
1592   PREFIX_EVEX_0F3845,
1593   PREFIX_EVEX_0F3846,
1594   PREFIX_EVEX_0F3847,
1595   PREFIX_EVEX_0F384C,
1596   PREFIX_EVEX_0F384D,
1597   PREFIX_EVEX_0F384E,
1598   PREFIX_EVEX_0F384F,
1599   PREFIX_EVEX_0F3850,
1600   PREFIX_EVEX_0F3851,
1601   PREFIX_EVEX_0F3852,
1602   PREFIX_EVEX_0F3853,
1603   PREFIX_EVEX_0F3854,
1604   PREFIX_EVEX_0F3855,
1605   PREFIX_EVEX_0F3858,
1606   PREFIX_EVEX_0F3859,
1607   PREFIX_EVEX_0F385A,
1608   PREFIX_EVEX_0F385B,
1609   PREFIX_EVEX_0F3862,
1610   PREFIX_EVEX_0F3863,
1611   PREFIX_EVEX_0F3864,
1612   PREFIX_EVEX_0F3865,
1613   PREFIX_EVEX_0F3866,
1614   PREFIX_EVEX_0F3870,
1615   PREFIX_EVEX_0F3871,
1616   PREFIX_EVEX_0F3872,
1617   PREFIX_EVEX_0F3873,
1618   PREFIX_EVEX_0F3875,
1619   PREFIX_EVEX_0F3876,
1620   PREFIX_EVEX_0F3877,
1621   PREFIX_EVEX_0F3878,
1622   PREFIX_EVEX_0F3879,
1623   PREFIX_EVEX_0F387A,
1624   PREFIX_EVEX_0F387B,
1625   PREFIX_EVEX_0F387C,
1626   PREFIX_EVEX_0F387D,
1627   PREFIX_EVEX_0F387E,
1628   PREFIX_EVEX_0F387F,
1629   PREFIX_EVEX_0F3883,
1630   PREFIX_EVEX_0F3888,
1631   PREFIX_EVEX_0F3889,
1632   PREFIX_EVEX_0F388A,
1633   PREFIX_EVEX_0F388B,
1634   PREFIX_EVEX_0F388D,
1635   PREFIX_EVEX_0F388F,
1636   PREFIX_EVEX_0F3890,
1637   PREFIX_EVEX_0F3891,
1638   PREFIX_EVEX_0F3892,
1639   PREFIX_EVEX_0F3893,
1640   PREFIX_EVEX_0F3896,
1641   PREFIX_EVEX_0F3897,
1642   PREFIX_EVEX_0F3898,
1643   PREFIX_EVEX_0F3899,
1644   PREFIX_EVEX_0F389A,
1645   PREFIX_EVEX_0F389B,
1646   PREFIX_EVEX_0F389C,
1647   PREFIX_EVEX_0F389D,
1648   PREFIX_EVEX_0F389E,
1649   PREFIX_EVEX_0F389F,
1650   PREFIX_EVEX_0F38A0,
1651   PREFIX_EVEX_0F38A1,
1652   PREFIX_EVEX_0F38A2,
1653   PREFIX_EVEX_0F38A3,
1654   PREFIX_EVEX_0F38A6,
1655   PREFIX_EVEX_0F38A7,
1656   PREFIX_EVEX_0F38A8,
1657   PREFIX_EVEX_0F38A9,
1658   PREFIX_EVEX_0F38AA,
1659   PREFIX_EVEX_0F38AB,
1660   PREFIX_EVEX_0F38AC,
1661   PREFIX_EVEX_0F38AD,
1662   PREFIX_EVEX_0F38AE,
1663   PREFIX_EVEX_0F38AF,
1664   PREFIX_EVEX_0F38B4,
1665   PREFIX_EVEX_0F38B5,
1666   PREFIX_EVEX_0F38B6,
1667   PREFIX_EVEX_0F38B7,
1668   PREFIX_EVEX_0F38B8,
1669   PREFIX_EVEX_0F38B9,
1670   PREFIX_EVEX_0F38BA,
1671   PREFIX_EVEX_0F38BB,
1672   PREFIX_EVEX_0F38BC,
1673   PREFIX_EVEX_0F38BD,
1674   PREFIX_EVEX_0F38BE,
1675   PREFIX_EVEX_0F38BF,
1676   PREFIX_EVEX_0F38C4,
1677   PREFIX_EVEX_0F38C6_REG_1,
1678   PREFIX_EVEX_0F38C6_REG_2,
1679   PREFIX_EVEX_0F38C6_REG_5,
1680   PREFIX_EVEX_0F38C6_REG_6,
1681   PREFIX_EVEX_0F38C7_REG_1,
1682   PREFIX_EVEX_0F38C7_REG_2,
1683   PREFIX_EVEX_0F38C7_REG_5,
1684   PREFIX_EVEX_0F38C7_REG_6,
1685   PREFIX_EVEX_0F38C8,
1686   PREFIX_EVEX_0F38CA,
1687   PREFIX_EVEX_0F38CB,
1688   PREFIX_EVEX_0F38CC,
1689   PREFIX_EVEX_0F38CD,
1690   PREFIX_EVEX_0F38CF,
1691   PREFIX_EVEX_0F38DC,
1692   PREFIX_EVEX_0F38DD,
1693   PREFIX_EVEX_0F38DE,
1694   PREFIX_EVEX_0F38DF,
1695
1696   PREFIX_EVEX_0F3A00,
1697   PREFIX_EVEX_0F3A01,
1698   PREFIX_EVEX_0F3A03,
1699   PREFIX_EVEX_0F3A04,
1700   PREFIX_EVEX_0F3A05,
1701   PREFIX_EVEX_0F3A08,
1702   PREFIX_EVEX_0F3A09,
1703   PREFIX_EVEX_0F3A0A,
1704   PREFIX_EVEX_0F3A0B,
1705   PREFIX_EVEX_0F3A0F,
1706   PREFIX_EVEX_0F3A14,
1707   PREFIX_EVEX_0F3A15,
1708   PREFIX_EVEX_0F3A16,
1709   PREFIX_EVEX_0F3A17,
1710   PREFIX_EVEX_0F3A18,
1711   PREFIX_EVEX_0F3A19,
1712   PREFIX_EVEX_0F3A1A,
1713   PREFIX_EVEX_0F3A1B,
1714   PREFIX_EVEX_0F3A1D,
1715   PREFIX_EVEX_0F3A1E,
1716   PREFIX_EVEX_0F3A1F,
1717   PREFIX_EVEX_0F3A20,
1718   PREFIX_EVEX_0F3A21,
1719   PREFIX_EVEX_0F3A22,
1720   PREFIX_EVEX_0F3A23,
1721   PREFIX_EVEX_0F3A25,
1722   PREFIX_EVEX_0F3A26,
1723   PREFIX_EVEX_0F3A27,
1724   PREFIX_EVEX_0F3A38,
1725   PREFIX_EVEX_0F3A39,
1726   PREFIX_EVEX_0F3A3A,
1727   PREFIX_EVEX_0F3A3B,
1728   PREFIX_EVEX_0F3A3E,
1729   PREFIX_EVEX_0F3A3F,
1730   PREFIX_EVEX_0F3A42,
1731   PREFIX_EVEX_0F3A43,
1732   PREFIX_EVEX_0F3A44,
1733   PREFIX_EVEX_0F3A50,
1734   PREFIX_EVEX_0F3A51,
1735   PREFIX_EVEX_0F3A54,
1736   PREFIX_EVEX_0F3A55,
1737   PREFIX_EVEX_0F3A56,
1738   PREFIX_EVEX_0F3A57,
1739   PREFIX_EVEX_0F3A66,
1740   PREFIX_EVEX_0F3A67,
1741   PREFIX_EVEX_0F3A70,
1742   PREFIX_EVEX_0F3A71,
1743   PREFIX_EVEX_0F3A72,
1744   PREFIX_EVEX_0F3A73,
1745   PREFIX_EVEX_0F3ACE,
1746   PREFIX_EVEX_0F3ACF
1747 };
1748
1749 enum
1750 {
1751   X86_64_06 = 0,
1752   X86_64_07,
1753   X86_64_0D,
1754   X86_64_16,
1755   X86_64_17,
1756   X86_64_1E,
1757   X86_64_1F,
1758   X86_64_27,
1759   X86_64_2F,
1760   X86_64_37,
1761   X86_64_3F,
1762   X86_64_60,
1763   X86_64_61,
1764   X86_64_62,
1765   X86_64_63,
1766   X86_64_6D,
1767   X86_64_6F,
1768   X86_64_82,
1769   X86_64_9A,
1770   X86_64_C4,
1771   X86_64_C5,
1772   X86_64_CE,
1773   X86_64_D4,
1774   X86_64_D5,
1775   X86_64_E8,
1776   X86_64_E9,
1777   X86_64_EA,
1778   X86_64_0F01_REG_0,
1779   X86_64_0F01_REG_1,
1780   X86_64_0F01_REG_2,
1781   X86_64_0F01_REG_3
1782 };
1783
1784 enum
1785 {
1786   THREE_BYTE_0F38 = 0,
1787   THREE_BYTE_0F3A
1788 };
1789
1790 enum
1791 {
1792   XOP_08 = 0,
1793   XOP_09,
1794   XOP_0A
1795 };
1796
1797 enum
1798 {
1799   VEX_0F = 0,
1800   VEX_0F38,
1801   VEX_0F3A
1802 };
1803
1804 enum
1805 {
1806   EVEX_0F = 0,
1807   EVEX_0F38,
1808   EVEX_0F3A
1809 };
1810
1811 enum
1812 {
1813   VEX_LEN_0F12_P_0_M_0 = 0,
1814   VEX_LEN_0F12_P_0_M_1,
1815   VEX_LEN_0F12_P_2,
1816   VEX_LEN_0F13_M_0,
1817   VEX_LEN_0F16_P_0_M_0,
1818   VEX_LEN_0F16_P_0_M_1,
1819   VEX_LEN_0F16_P_2,
1820   VEX_LEN_0F17_M_0,
1821   VEX_LEN_0F2A_P_1,
1822   VEX_LEN_0F2A_P_3,
1823   VEX_LEN_0F2C_P_1,
1824   VEX_LEN_0F2C_P_3,
1825   VEX_LEN_0F2D_P_1,
1826   VEX_LEN_0F2D_P_3,
1827   VEX_LEN_0F41_P_0,
1828   VEX_LEN_0F41_P_2,
1829   VEX_LEN_0F42_P_0,
1830   VEX_LEN_0F42_P_2,
1831   VEX_LEN_0F44_P_0,
1832   VEX_LEN_0F44_P_2,
1833   VEX_LEN_0F45_P_0,
1834   VEX_LEN_0F45_P_2,
1835   VEX_LEN_0F46_P_0,
1836   VEX_LEN_0F46_P_2,
1837   VEX_LEN_0F47_P_0,
1838   VEX_LEN_0F47_P_2,
1839   VEX_LEN_0F4A_P_0,
1840   VEX_LEN_0F4A_P_2,
1841   VEX_LEN_0F4B_P_0,
1842   VEX_LEN_0F4B_P_2,
1843   VEX_LEN_0F6E_P_2,
1844   VEX_LEN_0F77_P_0,
1845   VEX_LEN_0F7E_P_1,
1846   VEX_LEN_0F7E_P_2,
1847   VEX_LEN_0F90_P_0,
1848   VEX_LEN_0F90_P_2,
1849   VEX_LEN_0F91_P_0,
1850   VEX_LEN_0F91_P_2,
1851   VEX_LEN_0F92_P_0,
1852   VEX_LEN_0F92_P_2,
1853   VEX_LEN_0F92_P_3,
1854   VEX_LEN_0F93_P_0,
1855   VEX_LEN_0F93_P_2,
1856   VEX_LEN_0F93_P_3,
1857   VEX_LEN_0F98_P_0,
1858   VEX_LEN_0F98_P_2,
1859   VEX_LEN_0F99_P_0,
1860   VEX_LEN_0F99_P_2,
1861   VEX_LEN_0FAE_R_2_M_0,
1862   VEX_LEN_0FAE_R_3_M_0,
1863   VEX_LEN_0FC4_P_2,
1864   VEX_LEN_0FC5_P_2,
1865   VEX_LEN_0FD6_P_2,
1866   VEX_LEN_0FF7_P_2,
1867   VEX_LEN_0F3816_P_2,
1868   VEX_LEN_0F3819_P_2,
1869   VEX_LEN_0F381A_P_2_M_0,
1870   VEX_LEN_0F3836_P_2,
1871   VEX_LEN_0F3841_P_2,
1872   VEX_LEN_0F385A_P_2_M_0,
1873   VEX_LEN_0F38DB_P_2,
1874   VEX_LEN_0F38F2_P_0,
1875   VEX_LEN_0F38F3_R_1_P_0,
1876   VEX_LEN_0F38F3_R_2_P_0,
1877   VEX_LEN_0F38F3_R_3_P_0,
1878   VEX_LEN_0F38F5_P_0,
1879   VEX_LEN_0F38F5_P_1,
1880   VEX_LEN_0F38F5_P_3,
1881   VEX_LEN_0F38F6_P_3,
1882   VEX_LEN_0F38F7_P_0,
1883   VEX_LEN_0F38F7_P_1,
1884   VEX_LEN_0F38F7_P_2,
1885   VEX_LEN_0F38F7_P_3,
1886   VEX_LEN_0F3A00_P_2,
1887   VEX_LEN_0F3A01_P_2,
1888   VEX_LEN_0F3A06_P_2,
1889   VEX_LEN_0F3A14_P_2,
1890   VEX_LEN_0F3A15_P_2,
1891   VEX_LEN_0F3A16_P_2,
1892   VEX_LEN_0F3A17_P_2,
1893   VEX_LEN_0F3A18_P_2,
1894   VEX_LEN_0F3A19_P_2,
1895   VEX_LEN_0F3A20_P_2,
1896   VEX_LEN_0F3A21_P_2,
1897   VEX_LEN_0F3A22_P_2,
1898   VEX_LEN_0F3A30_P_2,
1899   VEX_LEN_0F3A31_P_2,
1900   VEX_LEN_0F3A32_P_2,
1901   VEX_LEN_0F3A33_P_2,
1902   VEX_LEN_0F3A38_P_2,
1903   VEX_LEN_0F3A39_P_2,
1904   VEX_LEN_0F3A41_P_2,
1905   VEX_LEN_0F3A46_P_2,
1906   VEX_LEN_0F3A60_P_2,
1907   VEX_LEN_0F3A61_P_2,
1908   VEX_LEN_0F3A62_P_2,
1909   VEX_LEN_0F3A63_P_2,
1910   VEX_LEN_0F3A6A_P_2,
1911   VEX_LEN_0F3A6B_P_2,
1912   VEX_LEN_0F3A6E_P_2,
1913   VEX_LEN_0F3A6F_P_2,
1914   VEX_LEN_0F3A7A_P_2,
1915   VEX_LEN_0F3A7B_P_2,
1916   VEX_LEN_0F3A7E_P_2,
1917   VEX_LEN_0F3A7F_P_2,
1918   VEX_LEN_0F3ADF_P_2,
1919   VEX_LEN_0F3AF0_P_3,
1920   VEX_LEN_0FXOP_08_CC,
1921   VEX_LEN_0FXOP_08_CD,
1922   VEX_LEN_0FXOP_08_CE,
1923   VEX_LEN_0FXOP_08_CF,
1924   VEX_LEN_0FXOP_08_EC,
1925   VEX_LEN_0FXOP_08_ED,
1926   VEX_LEN_0FXOP_08_EE,
1927   VEX_LEN_0FXOP_08_EF,
1928   VEX_LEN_0FXOP_09_80,
1929   VEX_LEN_0FXOP_09_81
1930 };
1931
1932 enum
1933 {
1934   EVEX_LEN_0F6E_P_2 = 0,
1935   EVEX_LEN_0F7E_P_1,
1936   EVEX_LEN_0F7E_P_2,
1937   EVEX_LEN_0FD6_P_2
1938 };
1939
1940 enum
1941 {
1942   VEX_W_0F41_P_0_LEN_1 = 0,
1943   VEX_W_0F41_P_2_LEN_1,
1944   VEX_W_0F42_P_0_LEN_1,
1945   VEX_W_0F42_P_2_LEN_1,
1946   VEX_W_0F44_P_0_LEN_0,
1947   VEX_W_0F44_P_2_LEN_0,
1948   VEX_W_0F45_P_0_LEN_1,
1949   VEX_W_0F45_P_2_LEN_1,
1950   VEX_W_0F46_P_0_LEN_1,
1951   VEX_W_0F46_P_2_LEN_1,
1952   VEX_W_0F47_P_0_LEN_1,
1953   VEX_W_0F47_P_2_LEN_1,
1954   VEX_W_0F4A_P_0_LEN_1,
1955   VEX_W_0F4A_P_2_LEN_1,
1956   VEX_W_0F4B_P_0_LEN_1,
1957   VEX_W_0F4B_P_2_LEN_1,
1958   VEX_W_0F90_P_0_LEN_0,
1959   VEX_W_0F90_P_2_LEN_0,
1960   VEX_W_0F91_P_0_LEN_0,
1961   VEX_W_0F91_P_2_LEN_0,
1962   VEX_W_0F92_P_0_LEN_0,
1963   VEX_W_0F92_P_2_LEN_0,
1964   VEX_W_0F93_P_0_LEN_0,
1965   VEX_W_0F93_P_2_LEN_0,
1966   VEX_W_0F98_P_0_LEN_0,
1967   VEX_W_0F98_P_2_LEN_0,
1968   VEX_W_0F99_P_0_LEN_0,
1969   VEX_W_0F99_P_2_LEN_0,
1970   VEX_W_0F380C_P_2,
1971   VEX_W_0F380D_P_2,
1972   VEX_W_0F380E_P_2,
1973   VEX_W_0F380F_P_2,
1974   VEX_W_0F3816_P_2,
1975   VEX_W_0F3818_P_2,
1976   VEX_W_0F3819_P_2,
1977   VEX_W_0F381A_P_2_M_0,
1978   VEX_W_0F382C_P_2_M_0,
1979   VEX_W_0F382D_P_2_M_0,
1980   VEX_W_0F382E_P_2_M_0,
1981   VEX_W_0F382F_P_2_M_0,
1982   VEX_W_0F3836_P_2,
1983   VEX_W_0F3846_P_2,
1984   VEX_W_0F3858_P_2,
1985   VEX_W_0F3859_P_2,
1986   VEX_W_0F385A_P_2_M_0,
1987   VEX_W_0F3878_P_2,
1988   VEX_W_0F3879_P_2,
1989   VEX_W_0F38CF_P_2,
1990   VEX_W_0F3A00_P_2,
1991   VEX_W_0F3A01_P_2,
1992   VEX_W_0F3A02_P_2,
1993   VEX_W_0F3A04_P_2,
1994   VEX_W_0F3A05_P_2,
1995   VEX_W_0F3A06_P_2,
1996   VEX_W_0F3A18_P_2,
1997   VEX_W_0F3A19_P_2,
1998   VEX_W_0F3A30_P_2_LEN_0,
1999   VEX_W_0F3A31_P_2_LEN_0,
2000   VEX_W_0F3A32_P_2_LEN_0,
2001   VEX_W_0F3A33_P_2_LEN_0,
2002   VEX_W_0F3A38_P_2,
2003   VEX_W_0F3A39_P_2,
2004   VEX_W_0F3A46_P_2,
2005   VEX_W_0F3A48_P_2,
2006   VEX_W_0F3A49_P_2,
2007   VEX_W_0F3A4A_P_2,
2008   VEX_W_0F3A4B_P_2,
2009   VEX_W_0F3A4C_P_2,
2010   VEX_W_0F3ACE_P_2,
2011   VEX_W_0F3ACF_P_2,
2012
2013   EVEX_W_0F10_P_0,
2014   EVEX_W_0F10_P_1_M_0,
2015   EVEX_W_0F10_P_1_M_1,
2016   EVEX_W_0F10_P_2,
2017   EVEX_W_0F10_P_3_M_0,
2018   EVEX_W_0F10_P_3_M_1,
2019   EVEX_W_0F11_P_0,
2020   EVEX_W_0F11_P_1_M_0,
2021   EVEX_W_0F11_P_1_M_1,
2022   EVEX_W_0F11_P_2,
2023   EVEX_W_0F11_P_3_M_0,
2024   EVEX_W_0F11_P_3_M_1,
2025   EVEX_W_0F12_P_0_M_0,
2026   EVEX_W_0F12_P_0_M_1,
2027   EVEX_W_0F12_P_1,
2028   EVEX_W_0F12_P_2,
2029   EVEX_W_0F12_P_3,
2030   EVEX_W_0F13_P_0,
2031   EVEX_W_0F13_P_2,
2032   EVEX_W_0F14_P_0,
2033   EVEX_W_0F14_P_2,
2034   EVEX_W_0F15_P_0,
2035   EVEX_W_0F15_P_2,
2036   EVEX_W_0F16_P_0_M_0,
2037   EVEX_W_0F16_P_0_M_1,
2038   EVEX_W_0F16_P_1,
2039   EVEX_W_0F16_P_2,
2040   EVEX_W_0F17_P_0,
2041   EVEX_W_0F17_P_2,
2042   EVEX_W_0F28_P_0,
2043   EVEX_W_0F28_P_2,
2044   EVEX_W_0F29_P_0,
2045   EVEX_W_0F29_P_2,
2046   EVEX_W_0F2A_P_1,
2047   EVEX_W_0F2A_P_3,
2048   EVEX_W_0F2B_P_0,
2049   EVEX_W_0F2B_P_2,
2050   EVEX_W_0F2E_P_0,
2051   EVEX_W_0F2E_P_2,
2052   EVEX_W_0F2F_P_0,
2053   EVEX_W_0F2F_P_2,
2054   EVEX_W_0F51_P_0,
2055   EVEX_W_0F51_P_1,
2056   EVEX_W_0F51_P_2,
2057   EVEX_W_0F51_P_3,
2058   EVEX_W_0F54_P_0,
2059   EVEX_W_0F54_P_2,
2060   EVEX_W_0F55_P_0,
2061   EVEX_W_0F55_P_2,
2062   EVEX_W_0F56_P_0,
2063   EVEX_W_0F56_P_2,
2064   EVEX_W_0F57_P_0,
2065   EVEX_W_0F57_P_2,
2066   EVEX_W_0F58_P_0,
2067   EVEX_W_0F58_P_1,
2068   EVEX_W_0F58_P_2,
2069   EVEX_W_0F58_P_3,
2070   EVEX_W_0F59_P_0,
2071   EVEX_W_0F59_P_1,
2072   EVEX_W_0F59_P_2,
2073   EVEX_W_0F59_P_3,
2074   EVEX_W_0F5A_P_0,
2075   EVEX_W_0F5A_P_1,
2076   EVEX_W_0F5A_P_2,
2077   EVEX_W_0F5A_P_3,
2078   EVEX_W_0F5B_P_0,
2079   EVEX_W_0F5B_P_1,
2080   EVEX_W_0F5B_P_2,
2081   EVEX_W_0F5C_P_0,
2082   EVEX_W_0F5C_P_1,
2083   EVEX_W_0F5C_P_2,
2084   EVEX_W_0F5C_P_3,
2085   EVEX_W_0F5D_P_0,
2086   EVEX_W_0F5D_P_1,
2087   EVEX_W_0F5D_P_2,
2088   EVEX_W_0F5D_P_3,
2089   EVEX_W_0F5E_P_0,
2090   EVEX_W_0F5E_P_1,
2091   EVEX_W_0F5E_P_2,
2092   EVEX_W_0F5E_P_3,
2093   EVEX_W_0F5F_P_0,
2094   EVEX_W_0F5F_P_1,
2095   EVEX_W_0F5F_P_2,
2096   EVEX_W_0F5F_P_3,
2097   EVEX_W_0F62_P_2,
2098   EVEX_W_0F66_P_2,
2099   EVEX_W_0F6A_P_2,
2100   EVEX_W_0F6B_P_2,
2101   EVEX_W_0F6C_P_2,
2102   EVEX_W_0F6D_P_2,
2103   EVEX_W_0F6F_P_1,
2104   EVEX_W_0F6F_P_2,
2105   EVEX_W_0F6F_P_3,
2106   EVEX_W_0F70_P_2,
2107   EVEX_W_0F72_R_2_P_2,
2108   EVEX_W_0F72_R_6_P_2,
2109   EVEX_W_0F73_R_2_P_2,
2110   EVEX_W_0F73_R_6_P_2,
2111   EVEX_W_0F76_P_2,
2112   EVEX_W_0F78_P_0,
2113   EVEX_W_0F78_P_2,
2114   EVEX_W_0F79_P_0,
2115   EVEX_W_0F79_P_2,
2116   EVEX_W_0F7A_P_1,
2117   EVEX_W_0F7A_P_2,
2118   EVEX_W_0F7A_P_3,
2119   EVEX_W_0F7B_P_1,
2120   EVEX_W_0F7B_P_2,
2121   EVEX_W_0F7B_P_3,
2122   EVEX_W_0F7E_P_1,
2123   EVEX_W_0F7F_P_1,
2124   EVEX_W_0F7F_P_2,
2125   EVEX_W_0F7F_P_3,
2126   EVEX_W_0FC2_P_0,
2127   EVEX_W_0FC2_P_1,
2128   EVEX_W_0FC2_P_2,
2129   EVEX_W_0FC2_P_3,
2130   EVEX_W_0FC6_P_0,
2131   EVEX_W_0FC6_P_2,
2132   EVEX_W_0FD2_P_2,
2133   EVEX_W_0FD3_P_2,
2134   EVEX_W_0FD4_P_2,
2135   EVEX_W_0FD6_P_2,
2136   EVEX_W_0FE6_P_1,
2137   EVEX_W_0FE6_P_2,
2138   EVEX_W_0FE6_P_3,
2139   EVEX_W_0FE7_P_2,
2140   EVEX_W_0FF2_P_2,
2141   EVEX_W_0FF3_P_2,
2142   EVEX_W_0FF4_P_2,
2143   EVEX_W_0FFA_P_2,
2144   EVEX_W_0FFB_P_2,
2145   EVEX_W_0FFE_P_2,
2146   EVEX_W_0F380C_P_2,
2147   EVEX_W_0F380D_P_2,
2148   EVEX_W_0F3810_P_1,
2149   EVEX_W_0F3810_P_2,
2150   EVEX_W_0F3811_P_1,
2151   EVEX_W_0F3811_P_2,
2152   EVEX_W_0F3812_P_1,
2153   EVEX_W_0F3812_P_2,
2154   EVEX_W_0F3813_P_1,
2155   EVEX_W_0F3813_P_2,
2156   EVEX_W_0F3814_P_1,
2157   EVEX_W_0F3815_P_1,
2158   EVEX_W_0F3818_P_2,
2159   EVEX_W_0F3819_P_2,
2160   EVEX_W_0F381A_P_2,
2161   EVEX_W_0F381B_P_2,
2162   EVEX_W_0F381E_P_2,
2163   EVEX_W_0F381F_P_2,
2164   EVEX_W_0F3820_P_1,
2165   EVEX_W_0F3821_P_1,
2166   EVEX_W_0F3822_P_1,
2167   EVEX_W_0F3823_P_1,
2168   EVEX_W_0F3824_P_1,
2169   EVEX_W_0F3825_P_1,
2170   EVEX_W_0F3825_P_2,
2171   EVEX_W_0F3826_P_1,
2172   EVEX_W_0F3826_P_2,
2173   EVEX_W_0F3828_P_1,
2174   EVEX_W_0F3828_P_2,
2175   EVEX_W_0F3829_P_1,
2176   EVEX_W_0F3829_P_2,
2177   EVEX_W_0F382A_P_1,
2178   EVEX_W_0F382A_P_2,
2179   EVEX_W_0F382B_P_2,
2180   EVEX_W_0F3830_P_1,
2181   EVEX_W_0F3831_P_1,
2182   EVEX_W_0F3832_P_1,
2183   EVEX_W_0F3833_P_1,
2184   EVEX_W_0F3834_P_1,
2185   EVEX_W_0F3835_P_1,
2186   EVEX_W_0F3835_P_2,
2187   EVEX_W_0F3837_P_2,
2188   EVEX_W_0F3838_P_1,
2189   EVEX_W_0F3839_P_1,
2190   EVEX_W_0F383A_P_1,
2191   EVEX_W_0F3840_P_2,
2192   EVEX_W_0F3854_P_2,
2193   EVEX_W_0F3855_P_2,
2194   EVEX_W_0F3858_P_2,
2195   EVEX_W_0F3859_P_2,
2196   EVEX_W_0F385A_P_2,
2197   EVEX_W_0F385B_P_2,
2198   EVEX_W_0F3862_P_2,
2199   EVEX_W_0F3863_P_2,
2200   EVEX_W_0F3866_P_2,
2201   EVEX_W_0F3870_P_2,
2202   EVEX_W_0F3871_P_2,
2203   EVEX_W_0F3872_P_2,
2204   EVEX_W_0F3873_P_2,
2205   EVEX_W_0F3875_P_2,
2206   EVEX_W_0F3878_P_2,
2207   EVEX_W_0F3879_P_2,
2208   EVEX_W_0F387A_P_2,
2209   EVEX_W_0F387B_P_2,
2210   EVEX_W_0F387D_P_2,
2211   EVEX_W_0F3883_P_2,
2212   EVEX_W_0F388D_P_2,
2213   EVEX_W_0F3891_P_2,
2214   EVEX_W_0F3893_P_2,
2215   EVEX_W_0F38A1_P_2,
2216   EVEX_W_0F38A3_P_2,
2217   EVEX_W_0F38C7_R_1_P_2,
2218   EVEX_W_0F38C7_R_2_P_2,
2219   EVEX_W_0F38C7_R_5_P_2,
2220   EVEX_W_0F38C7_R_6_P_2,
2221
2222   EVEX_W_0F3A00_P_2,
2223   EVEX_W_0F3A01_P_2,
2224   EVEX_W_0F3A04_P_2,
2225   EVEX_W_0F3A05_P_2,
2226   EVEX_W_0F3A08_P_2,
2227   EVEX_W_0F3A09_P_2,
2228   EVEX_W_0F3A0A_P_2,
2229   EVEX_W_0F3A0B_P_2,
2230   EVEX_W_0F3A18_P_2,
2231   EVEX_W_0F3A19_P_2,
2232   EVEX_W_0F3A1A_P_2,
2233   EVEX_W_0F3A1B_P_2,
2234   EVEX_W_0F3A1D_P_2,
2235   EVEX_W_0F3A21_P_2,
2236   EVEX_W_0F3A23_P_2,
2237   EVEX_W_0F3A38_P_2,
2238   EVEX_W_0F3A39_P_2,
2239   EVEX_W_0F3A3A_P_2,
2240   EVEX_W_0F3A3B_P_2,
2241   EVEX_W_0F3A3E_P_2,
2242   EVEX_W_0F3A3F_P_2,
2243   EVEX_W_0F3A42_P_2,
2244   EVEX_W_0F3A43_P_2,
2245   EVEX_W_0F3A50_P_2,
2246   EVEX_W_0F3A51_P_2,
2247   EVEX_W_0F3A56_P_2,
2248   EVEX_W_0F3A57_P_2,
2249   EVEX_W_0F3A66_P_2,
2250   EVEX_W_0F3A67_P_2,
2251   EVEX_W_0F3A70_P_2,
2252   EVEX_W_0F3A71_P_2,
2253   EVEX_W_0F3A72_P_2,
2254   EVEX_W_0F3A73_P_2,
2255   EVEX_W_0F3ACE_P_2,
2256   EVEX_W_0F3ACF_P_2
2257 };
2258
2259 typedef void (*op_rtn) (int bytemode, int sizeflag);
2260
2261 struct dis386 {
2262   const char *name;
2263   struct
2264     {
2265       op_rtn rtn;
2266       int bytemode;
2267     } op[MAX_OPERANDS];
2268   unsigned int prefix_requirement;
2269 };
2270
2271 /* Upper case letters in the instruction names here are macros.
2272    'A' => print 'b' if no register operands or suffix_always is true
2273    'B' => print 'b' if suffix_always is true
2274    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2275           size prefix
2276    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2277           suffix_always is true
2278    'E' => print 'e' if 32-bit form of jcxz
2279    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2280    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2281    'H' => print ",pt" or ",pn" branch hint
2282    'I' => honor following macro letter even in Intel mode (implemented only
2283           for some of the macro letters)
2284    'J' => print 'l'
2285    'K' => print 'd' or 'q' if rex prefix is present.
2286    'L' => print 'l' if suffix_always is true
2287    'M' => print 'r' if intel_mnemonic is false.
2288    'N' => print 'n' if instruction has no wait "prefix"
2289    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2290    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2291           or suffix_always is true.  print 'q' if rex prefix is present.
2292    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2293           is true
2294    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2295    'S' => print 'w', 'l' or 'q' if suffix_always is true
2296    'T' => print 'q' in 64bit mode if instruction has no operand size
2297           prefix and behave as 'P' otherwise
2298    'U' => print 'q' in 64bit mode if instruction has no operand size
2299           prefix and behave as 'Q' otherwise
2300    'V' => print 'q' in 64bit mode if instruction has no operand size
2301           prefix and behave as 'S' otherwise
2302    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2303    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2304    'Y' unused.
2305    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2306    '!' => change condition from true to false or from false to true.
2307    '%' => add 1 upper case letter to the macro.
2308    '^' => print 'w' or 'l' depending on operand size prefix or
2309           suffix_always is true (lcall/ljmp).
2310    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2311           on operand size prefix.
2312    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2313           has no operand size prefix for AMD64 ISA, behave as 'P'
2314           otherwise
2315
2316    2 upper case letter macros:
2317    "XY" => print 'x' or 'y' if suffix_always is true or no register
2318            operands and no broadcast.
2319    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2320            register operands and no broadcast.
2321    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2322    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2323            or suffix_always is true
2324    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2325    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2326    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2327    "LW" => print 'd', 'q' depending on the VEX.W bit
2328    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2329            an operand size prefix, or suffix_always is true.  print
2330            'q' if rex prefix is present.
2331
2332    Many of the above letters print nothing in Intel mode.  See "putop"
2333    for the details.
2334
2335    Braces '{' and '}', and vertical bars '|', indicate alternative
2336    mnemonic strings for AT&T and Intel.  */
2337
2338 static const struct dis386 dis386[] = {
2339   /* 00 */
2340   { "addB",             { Ebh1, Gb }, 0 },
2341   { "addS",             { Evh1, Gv }, 0 },
2342   { "addB",             { Gb, EbS }, 0 },
2343   { "addS",             { Gv, EvS }, 0 },
2344   { "addB",             { AL, Ib }, 0 },
2345   { "addS",             { eAX, Iv }, 0 },
2346   { X86_64_TABLE (X86_64_06) },
2347   { X86_64_TABLE (X86_64_07) },
2348   /* 08 */
2349   { "orB",              { Ebh1, Gb }, 0 },
2350   { "orS",              { Evh1, Gv }, 0 },
2351   { "orB",              { Gb, EbS }, 0 },
2352   { "orS",              { Gv, EvS }, 0 },
2353   { "orB",              { AL, Ib }, 0 },
2354   { "orS",              { eAX, Iv }, 0 },
2355   { X86_64_TABLE (X86_64_0D) },
2356   { Bad_Opcode },       /* 0x0f extended opcode escape */
2357   /* 10 */
2358   { "adcB",             { Ebh1, Gb }, 0 },
2359   { "adcS",             { Evh1, Gv }, 0 },
2360   { "adcB",             { Gb, EbS }, 0 },
2361   { "adcS",             { Gv, EvS }, 0 },
2362   { "adcB",             { AL, Ib }, 0 },
2363   { "adcS",             { eAX, Iv }, 0 },
2364   { X86_64_TABLE (X86_64_16) },
2365   { X86_64_TABLE (X86_64_17) },
2366   /* 18 */
2367   { "sbbB",             { Ebh1, Gb }, 0 },
2368   { "sbbS",             { Evh1, Gv }, 0 },
2369   { "sbbB",             { Gb, EbS }, 0 },
2370   { "sbbS",             { Gv, EvS }, 0 },
2371   { "sbbB",             { AL, Ib }, 0 },
2372   { "sbbS",             { eAX, Iv }, 0 },
2373   { X86_64_TABLE (X86_64_1E) },
2374   { X86_64_TABLE (X86_64_1F) },
2375   /* 20 */
2376   { "andB",             { Ebh1, Gb }, 0 },
2377   { "andS",             { Evh1, Gv }, 0 },
2378   { "andB",             { Gb, EbS }, 0 },
2379   { "andS",             { Gv, EvS }, 0 },
2380   { "andB",             { AL, Ib }, 0 },
2381   { "andS",             { eAX, Iv }, 0 },
2382   { Bad_Opcode },       /* SEG ES prefix */
2383   { X86_64_TABLE (X86_64_27) },
2384   /* 28 */
2385   { "subB",             { Ebh1, Gb }, 0 },
2386   { "subS",             { Evh1, Gv }, 0 },
2387   { "subB",             { Gb, EbS }, 0 },
2388   { "subS",             { Gv, EvS }, 0 },
2389   { "subB",             { AL, Ib }, 0 },
2390   { "subS",             { eAX, Iv }, 0 },
2391   { Bad_Opcode },       /* SEG CS prefix */
2392   { X86_64_TABLE (X86_64_2F) },
2393   /* 30 */
2394   { "xorB",             { Ebh1, Gb }, 0 },
2395   { "xorS",             { Evh1, Gv }, 0 },
2396   { "xorB",             { Gb, EbS }, 0 },
2397   { "xorS",             { Gv, EvS }, 0 },
2398   { "xorB",             { AL, Ib }, 0 },
2399   { "xorS",             { eAX, Iv }, 0 },
2400   { Bad_Opcode },       /* SEG SS prefix */
2401   { X86_64_TABLE (X86_64_37) },
2402   /* 38 */
2403   { "cmpB",             { Eb, Gb }, 0 },
2404   { "cmpS",             { Ev, Gv }, 0 },
2405   { "cmpB",             { Gb, EbS }, 0 },
2406   { "cmpS",             { Gv, EvS }, 0 },
2407   { "cmpB",             { AL, Ib }, 0 },
2408   { "cmpS",             { eAX, Iv }, 0 },
2409   { Bad_Opcode },       /* SEG DS prefix */
2410   { X86_64_TABLE (X86_64_3F) },
2411   /* 40 */
2412   { "inc{S|}",          { RMeAX }, 0 },
2413   { "inc{S|}",          { RMeCX }, 0 },
2414   { "inc{S|}",          { RMeDX }, 0 },
2415   { "inc{S|}",          { RMeBX }, 0 },
2416   { "inc{S|}",          { RMeSP }, 0 },
2417   { "inc{S|}",          { RMeBP }, 0 },
2418   { "inc{S|}",          { RMeSI }, 0 },
2419   { "inc{S|}",          { RMeDI }, 0 },
2420   /* 48 */
2421   { "dec{S|}",          { RMeAX }, 0 },
2422   { "dec{S|}",          { RMeCX }, 0 },
2423   { "dec{S|}",          { RMeDX }, 0 },
2424   { "dec{S|}",          { RMeBX }, 0 },
2425   { "dec{S|}",          { RMeSP }, 0 },
2426   { "dec{S|}",          { RMeBP }, 0 },
2427   { "dec{S|}",          { RMeSI }, 0 },
2428   { "dec{S|}",          { RMeDI }, 0 },
2429   /* 50 */
2430   { "pushV",            { RMrAX }, 0 },
2431   { "pushV",            { RMrCX }, 0 },
2432   { "pushV",            { RMrDX }, 0 },
2433   { "pushV",            { RMrBX }, 0 },
2434   { "pushV",            { RMrSP }, 0 },
2435   { "pushV",            { RMrBP }, 0 },
2436   { "pushV",            { RMrSI }, 0 },
2437   { "pushV",            { RMrDI }, 0 },
2438   /* 58 */
2439   { "popV",             { RMrAX }, 0 },
2440   { "popV",             { RMrCX }, 0 },
2441   { "popV",             { RMrDX }, 0 },
2442   { "popV",             { RMrBX }, 0 },
2443   { "popV",             { RMrSP }, 0 },
2444   { "popV",             { RMrBP }, 0 },
2445   { "popV",             { RMrSI }, 0 },
2446   { "popV",             { RMrDI }, 0 },
2447   /* 60 */
2448   { X86_64_TABLE (X86_64_60) },
2449   { X86_64_TABLE (X86_64_61) },
2450   { X86_64_TABLE (X86_64_62) },
2451   { X86_64_TABLE (X86_64_63) },
2452   { Bad_Opcode },       /* seg fs */
2453   { Bad_Opcode },       /* seg gs */
2454   { Bad_Opcode },       /* op size prefix */
2455   { Bad_Opcode },       /* adr size prefix */
2456   /* 68 */
2457   { "pushT",            { sIv }, 0 },
2458   { "imulS",            { Gv, Ev, Iv }, 0 },
2459   { "pushT",            { sIbT }, 0 },
2460   { "imulS",            { Gv, Ev, sIb }, 0 },
2461   { "ins{b|}",          { Ybr, indirDX }, 0 },
2462   { X86_64_TABLE (X86_64_6D) },
2463   { "outs{b|}",         { indirDXr, Xb }, 0 },
2464   { X86_64_TABLE (X86_64_6F) },
2465   /* 70 */
2466   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2467   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2468   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2469   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2470   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2471   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2472   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2473   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2474   /* 78 */
2475   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2476   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2477   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2478   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2479   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2480   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2481   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2482   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2483   /* 80 */
2484   { REG_TABLE (REG_80) },
2485   { REG_TABLE (REG_81) },
2486   { X86_64_TABLE (X86_64_82) },
2487   { REG_TABLE (REG_83) },
2488   { "testB",            { Eb, Gb }, 0 },
2489   { "testS",            { Ev, Gv }, 0 },
2490   { "xchgB",            { Ebh2, Gb }, 0 },
2491   { "xchgS",            { Evh2, Gv }, 0 },
2492   /* 88 */
2493   { "movB",             { Ebh3, Gb }, 0 },
2494   { "movS",             { Evh3, Gv }, 0 },
2495   { "movB",             { Gb, EbS }, 0 },
2496   { "movS",             { Gv, EvS }, 0 },
2497   { "movD",             { Sv, Sw }, 0 },
2498   { MOD_TABLE (MOD_8D) },
2499   { "movD",             { Sw, Sv }, 0 },
2500   { REG_TABLE (REG_8F) },
2501   /* 90 */
2502   { PREFIX_TABLE (PREFIX_90) },
2503   { "xchgS",            { RMeCX, eAX }, 0 },
2504   { "xchgS",            { RMeDX, eAX }, 0 },
2505   { "xchgS",            { RMeBX, eAX }, 0 },
2506   { "xchgS",            { RMeSP, eAX }, 0 },
2507   { "xchgS",            { RMeBP, eAX }, 0 },
2508   { "xchgS",            { RMeSI, eAX }, 0 },
2509   { "xchgS",            { RMeDI, eAX }, 0 },
2510   /* 98 */
2511   { "cW{t|}R",          { XX }, 0 },
2512   { "cR{t|}O",          { XX }, 0 },
2513   { X86_64_TABLE (X86_64_9A) },
2514   { Bad_Opcode },       /* fwait */
2515   { "pushfT",           { XX }, 0 },
2516   { "popfT",            { XX }, 0 },
2517   { "sahf",             { XX }, 0 },
2518   { "lahf",             { XX }, 0 },
2519   /* a0 */
2520   { "mov%LB",           { AL, Ob }, 0 },
2521   { "mov%LS",           { eAX, Ov }, 0 },
2522   { "mov%LB",           { Ob, AL }, 0 },
2523   { "mov%LS",           { Ov, eAX }, 0 },
2524   { "movs{b|}",         { Ybr, Xb }, 0 },
2525   { "movs{R|}",         { Yvr, Xv }, 0 },
2526   { "cmps{b|}",         { Xb, Yb }, 0 },
2527   { "cmps{R|}",         { Xv, Yv }, 0 },
2528   /* a8 */
2529   { "testB",            { AL, Ib }, 0 },
2530   { "testS",            { eAX, Iv }, 0 },
2531   { "stosB",            { Ybr, AL }, 0 },
2532   { "stosS",            { Yvr, eAX }, 0 },
2533   { "lodsB",            { ALr, Xb }, 0 },
2534   { "lodsS",            { eAXr, Xv }, 0 },
2535   { "scasB",            { AL, Yb }, 0 },
2536   { "scasS",            { eAX, Yv }, 0 },
2537   /* b0 */
2538   { "movB",             { RMAL, Ib }, 0 },
2539   { "movB",             { RMCL, Ib }, 0 },
2540   { "movB",             { RMDL, Ib }, 0 },
2541   { "movB",             { RMBL, Ib }, 0 },
2542   { "movB",             { RMAH, Ib }, 0 },
2543   { "movB",             { RMCH, Ib }, 0 },
2544   { "movB",             { RMDH, Ib }, 0 },
2545   { "movB",             { RMBH, Ib }, 0 },
2546   /* b8 */
2547   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2548   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2549   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2550   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2551   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2552   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2553   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2554   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2555   /* c0 */
2556   { REG_TABLE (REG_C0) },
2557   { REG_TABLE (REG_C1) },
2558   { "retT",             { Iw, BND }, 0 },
2559   { "retT",             { BND }, 0 },
2560   { X86_64_TABLE (X86_64_C4) },
2561   { X86_64_TABLE (X86_64_C5) },
2562   { REG_TABLE (REG_C6) },
2563   { REG_TABLE (REG_C7) },
2564   /* c8 */
2565   { "enterT",           { Iw, Ib }, 0 },
2566   { "leaveT",           { XX }, 0 },
2567   { "Jret{|f}P",        { Iw }, 0 },
2568   { "Jret{|f}P",        { XX }, 0 },
2569   { "int3",             { XX }, 0 },
2570   { "int",              { Ib }, 0 },
2571   { X86_64_TABLE (X86_64_CE) },
2572   { "iret%LP",          { XX }, 0 },
2573   /* d0 */
2574   { REG_TABLE (REG_D0) },
2575   { REG_TABLE (REG_D1) },
2576   { REG_TABLE (REG_D2) },
2577   { REG_TABLE (REG_D3) },
2578   { X86_64_TABLE (X86_64_D4) },
2579   { X86_64_TABLE (X86_64_D5) },
2580   { Bad_Opcode },
2581   { "xlat",             { DSBX }, 0 },
2582   /* d8 */
2583   { FLOAT },
2584   { FLOAT },
2585   { FLOAT },
2586   { FLOAT },
2587   { FLOAT },
2588   { FLOAT },
2589   { FLOAT },
2590   { FLOAT },
2591   /* e0 */
2592   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2593   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2594   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2595   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2596   { "inB",              { AL, Ib }, 0 },
2597   { "inG",              { zAX, Ib }, 0 },
2598   { "outB",             { Ib, AL }, 0 },
2599   { "outG",             { Ib, zAX }, 0 },
2600   /* e8 */
2601   { X86_64_TABLE (X86_64_E8) },
2602   { X86_64_TABLE (X86_64_E9) },
2603   { X86_64_TABLE (X86_64_EA) },
2604   { "jmp",              { Jb, BND }, 0 },
2605   { "inB",              { AL, indirDX }, 0 },
2606   { "inG",              { zAX, indirDX }, 0 },
2607   { "outB",             { indirDX, AL }, 0 },
2608   { "outG",             { indirDX, zAX }, 0 },
2609   /* f0 */
2610   { Bad_Opcode },       /* lock prefix */
2611   { "icebp",            { XX }, 0 },
2612   { Bad_Opcode },       /* repne */
2613   { Bad_Opcode },       /* repz */
2614   { "hlt",              { XX }, 0 },
2615   { "cmc",              { XX }, 0 },
2616   { REG_TABLE (REG_F6) },
2617   { REG_TABLE (REG_F7) },
2618   /* f8 */
2619   { "clc",              { XX }, 0 },
2620   { "stc",              { XX }, 0 },
2621   { "cli",              { XX }, 0 },
2622   { "sti",              { XX }, 0 },
2623   { "cld",              { XX }, 0 },
2624   { "std",              { XX }, 0 },
2625   { REG_TABLE (REG_FE) },
2626   { REG_TABLE (REG_FF) },
2627 };
2628
2629 static const struct dis386 dis386_twobyte[] = {
2630   /* 00 */
2631   { REG_TABLE (REG_0F00 ) },
2632   { REG_TABLE (REG_0F01 ) },
2633   { "larS",             { Gv, Ew }, 0 },
2634   { "lslS",             { Gv, Ew }, 0 },
2635   { Bad_Opcode },
2636   { "syscall",          { XX }, 0 },
2637   { "clts",             { XX }, 0 },
2638   { "sysret%LP",                { XX }, 0 },
2639   /* 08 */
2640   { "invd",             { XX }, 0 },
2641   { PREFIX_TABLE (PREFIX_0F09) },
2642   { Bad_Opcode },
2643   { "ud2",              { XX }, 0 },
2644   { Bad_Opcode },
2645   { REG_TABLE (REG_0F0D) },
2646   { "femms",            { XX }, 0 },
2647   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2648   /* 10 */
2649   { PREFIX_TABLE (PREFIX_0F10) },
2650   { PREFIX_TABLE (PREFIX_0F11) },
2651   { PREFIX_TABLE (PREFIX_0F12) },
2652   { MOD_TABLE (MOD_0F13) },
2653   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2654   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2655   { PREFIX_TABLE (PREFIX_0F16) },
2656   { MOD_TABLE (MOD_0F17) },
2657   /* 18 */
2658   { REG_TABLE (REG_0F18) },
2659   { "nopQ",             { Ev }, 0 },
2660   { PREFIX_TABLE (PREFIX_0F1A) },
2661   { PREFIX_TABLE (PREFIX_0F1B) },
2662   { PREFIX_TABLE (PREFIX_0F1C) },
2663   { "nopQ",             { Ev }, 0 },
2664   { PREFIX_TABLE (PREFIX_0F1E) },
2665   { "nopQ",             { Ev }, 0 },
2666   /* 20 */
2667   { "movZ",             { Rm, Cm }, 0 },
2668   { "movZ",             { Rm, Dm }, 0 },
2669   { "movZ",             { Cm, Rm }, 0 },
2670   { "movZ",             { Dm, Rm }, 0 },
2671   { MOD_TABLE (MOD_0F24) },
2672   { Bad_Opcode },
2673   { MOD_TABLE (MOD_0F26) },
2674   { Bad_Opcode },
2675   /* 28 */
2676   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2677   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2678   { PREFIX_TABLE (PREFIX_0F2A) },
2679   { PREFIX_TABLE (PREFIX_0F2B) },
2680   { PREFIX_TABLE (PREFIX_0F2C) },
2681   { PREFIX_TABLE (PREFIX_0F2D) },
2682   { PREFIX_TABLE (PREFIX_0F2E) },
2683   { PREFIX_TABLE (PREFIX_0F2F) },
2684   /* 30 */
2685   { "wrmsr",            { XX }, 0 },
2686   { "rdtsc",            { XX }, 0 },
2687   { "rdmsr",            { XX }, 0 },
2688   { "rdpmc",            { XX }, 0 },
2689   { "sysenter",         { XX }, 0 },
2690   { "sysexit",          { XX }, 0 },
2691   { Bad_Opcode },
2692   { "getsec",           { XX }, 0 },
2693   /* 38 */
2694   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2695   { Bad_Opcode },
2696   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2697   { Bad_Opcode },
2698   { Bad_Opcode },
2699   { Bad_Opcode },
2700   { Bad_Opcode },
2701   { Bad_Opcode },
2702   /* 40 */
2703   { "cmovoS",           { Gv, Ev }, 0 },
2704   { "cmovnoS",          { Gv, Ev }, 0 },
2705   { "cmovbS",           { Gv, Ev }, 0 },
2706   { "cmovaeS",          { Gv, Ev }, 0 },
2707   { "cmoveS",           { Gv, Ev }, 0 },
2708   { "cmovneS",          { Gv, Ev }, 0 },
2709   { "cmovbeS",          { Gv, Ev }, 0 },
2710   { "cmovaS",           { Gv, Ev }, 0 },
2711   /* 48 */
2712   { "cmovsS",           { Gv, Ev }, 0 },
2713   { "cmovnsS",          { Gv, Ev }, 0 },
2714   { "cmovpS",           { Gv, Ev }, 0 },
2715   { "cmovnpS",          { Gv, Ev }, 0 },
2716   { "cmovlS",           { Gv, Ev }, 0 },
2717   { "cmovgeS",          { Gv, Ev }, 0 },
2718   { "cmovleS",          { Gv, Ev }, 0 },
2719   { "cmovgS",           { Gv, Ev }, 0 },
2720   /* 50 */
2721   { MOD_TABLE (MOD_0F51) },
2722   { PREFIX_TABLE (PREFIX_0F51) },
2723   { PREFIX_TABLE (PREFIX_0F52) },
2724   { PREFIX_TABLE (PREFIX_0F53) },
2725   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2726   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2727   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2728   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2729   /* 58 */
2730   { PREFIX_TABLE (PREFIX_0F58) },
2731   { PREFIX_TABLE (PREFIX_0F59) },
2732   { PREFIX_TABLE (PREFIX_0F5A) },
2733   { PREFIX_TABLE (PREFIX_0F5B) },
2734   { PREFIX_TABLE (PREFIX_0F5C) },
2735   { PREFIX_TABLE (PREFIX_0F5D) },
2736   { PREFIX_TABLE (PREFIX_0F5E) },
2737   { PREFIX_TABLE (PREFIX_0F5F) },
2738   /* 60 */
2739   { PREFIX_TABLE (PREFIX_0F60) },
2740   { PREFIX_TABLE (PREFIX_0F61) },
2741   { PREFIX_TABLE (PREFIX_0F62) },
2742   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2743   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2744   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2745   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2746   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2747   /* 68 */
2748   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2749   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2750   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2751   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2752   { PREFIX_TABLE (PREFIX_0F6C) },
2753   { PREFIX_TABLE (PREFIX_0F6D) },
2754   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2755   { PREFIX_TABLE (PREFIX_0F6F) },
2756   /* 70 */
2757   { PREFIX_TABLE (PREFIX_0F70) },
2758   { REG_TABLE (REG_0F71) },
2759   { REG_TABLE (REG_0F72) },
2760   { REG_TABLE (REG_0F73) },
2761   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2762   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2763   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2764   { "emms",             { XX }, PREFIX_OPCODE },
2765   /* 78 */
2766   { PREFIX_TABLE (PREFIX_0F78) },
2767   { PREFIX_TABLE (PREFIX_0F79) },
2768   { Bad_Opcode },
2769   { Bad_Opcode },
2770   { PREFIX_TABLE (PREFIX_0F7C) },
2771   { PREFIX_TABLE (PREFIX_0F7D) },
2772   { PREFIX_TABLE (PREFIX_0F7E) },
2773   { PREFIX_TABLE (PREFIX_0F7F) },
2774   /* 80 */
2775   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2776   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2777   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2778   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2779   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2780   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2781   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2782   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2783   /* 88 */
2784   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2785   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2786   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2787   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2788   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2789   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2790   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2791   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2792   /* 90 */
2793   { "seto",             { Eb }, 0 },
2794   { "setno",            { Eb }, 0 },
2795   { "setb",             { Eb }, 0 },
2796   { "setae",            { Eb }, 0 },
2797   { "sete",             { Eb }, 0 },
2798   { "setne",            { Eb }, 0 },
2799   { "setbe",            { Eb }, 0 },
2800   { "seta",             { Eb }, 0 },
2801   /* 98 */
2802   { "sets",             { Eb }, 0 },
2803   { "setns",            { Eb }, 0 },
2804   { "setp",             { Eb }, 0 },
2805   { "setnp",            { Eb }, 0 },
2806   { "setl",             { Eb }, 0 },
2807   { "setge",            { Eb }, 0 },
2808   { "setle",            { Eb }, 0 },
2809   { "setg",             { Eb }, 0 },
2810   /* a0 */
2811   { "pushT",            { fs }, 0 },
2812   { "popT",             { fs }, 0 },
2813   { "cpuid",            { XX }, 0 },
2814   { "btS",              { Ev, Gv }, 0 },
2815   { "shldS",            { Ev, Gv, Ib }, 0 },
2816   { "shldS",            { Ev, Gv, CL }, 0 },
2817   { REG_TABLE (REG_0FA6) },
2818   { REG_TABLE (REG_0FA7) },
2819   /* a8 */
2820   { "pushT",            { gs }, 0 },
2821   { "popT",             { gs }, 0 },
2822   { "rsm",              { XX }, 0 },
2823   { "btsS",             { Evh1, Gv }, 0 },
2824   { "shrdS",            { Ev, Gv, Ib }, 0 },
2825   { "shrdS",            { Ev, Gv, CL }, 0 },
2826   { REG_TABLE (REG_0FAE) },
2827   { "imulS",            { Gv, Ev }, 0 },
2828   /* b0 */
2829   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2830   { "cmpxchgS",         { Evh1, Gv }, 0 },
2831   { MOD_TABLE (MOD_0FB2) },
2832   { "btrS",             { Evh1, Gv }, 0 },
2833   { MOD_TABLE (MOD_0FB4) },
2834   { MOD_TABLE (MOD_0FB5) },
2835   { "movz{bR|x}",       { Gv, Eb }, 0 },
2836   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2837   /* b8 */
2838   { PREFIX_TABLE (PREFIX_0FB8) },
2839   { "ud1S",             { Gv, Ev }, 0 },
2840   { REG_TABLE (REG_0FBA) },
2841   { "btcS",             { Evh1, Gv }, 0 },
2842   { PREFIX_TABLE (PREFIX_0FBC) },
2843   { PREFIX_TABLE (PREFIX_0FBD) },
2844   { "movs{bR|x}",       { Gv, Eb }, 0 },
2845   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2846   /* c0 */
2847   { "xaddB",            { Ebh1, Gb }, 0 },
2848   { "xaddS",            { Evh1, Gv }, 0 },
2849   { PREFIX_TABLE (PREFIX_0FC2) },
2850   { MOD_TABLE (MOD_0FC3) },
2851   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2852   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2853   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2854   { REG_TABLE (REG_0FC7) },
2855   /* c8 */
2856   { "bswap",            { RMeAX }, 0 },
2857   { "bswap",            { RMeCX }, 0 },
2858   { "bswap",            { RMeDX }, 0 },
2859   { "bswap",            { RMeBX }, 0 },
2860   { "bswap",            { RMeSP }, 0 },
2861   { "bswap",            { RMeBP }, 0 },
2862   { "bswap",            { RMeSI }, 0 },
2863   { "bswap",            { RMeDI }, 0 },
2864   /* d0 */
2865   { PREFIX_TABLE (PREFIX_0FD0) },
2866   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2867   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2868   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2869   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2870   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2871   { PREFIX_TABLE (PREFIX_0FD6) },
2872   { MOD_TABLE (MOD_0FD7) },
2873   /* d8 */
2874   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2875   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2876   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2877   { "pand",             { MX, EM }, PREFIX_OPCODE },
2878   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2879   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2880   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2881   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2882   /* e0 */
2883   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2884   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2885   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2886   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2887   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2888   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2889   { PREFIX_TABLE (PREFIX_0FE6) },
2890   { PREFIX_TABLE (PREFIX_0FE7) },
2891   /* e8 */
2892   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2893   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2894   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2895   { "por",              { MX, EM }, PREFIX_OPCODE },
2896   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2897   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2898   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2899   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2900   /* f0 */
2901   { PREFIX_TABLE (PREFIX_0FF0) },
2902   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2903   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2904   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2905   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2906   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2907   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2908   { PREFIX_TABLE (PREFIX_0FF7) },
2909   /* f8 */
2910   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2911   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2912   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2913   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2914   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2915   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2916   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2917   { "ud0S",             { Gv, Ev }, 0 },
2918 };
2919
2920 static const unsigned char onebyte_has_modrm[256] = {
2921   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2922   /*       -------------------------------        */
2923   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2924   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2925   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2926   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2927   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2928   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2929   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2930   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2931   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2932   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2933   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2934   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2935   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2936   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2937   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2938   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2939   /*       -------------------------------        */
2940   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2941 };
2942
2943 static const unsigned char twobyte_has_modrm[256] = {
2944   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2945   /*       -------------------------------        */
2946   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2947   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2948   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2949   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2950   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2951   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2952   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2953   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2954   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2955   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2956   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2957   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2958   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2959   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2960   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2961   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2962   /*       -------------------------------        */
2963   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2964 };
2965
2966 static char obuf[100];
2967 static char *obufp;
2968 static char *mnemonicendp;
2969 static char scratchbuf[100];
2970 static unsigned char *start_codep;
2971 static unsigned char *insn_codep;
2972 static unsigned char *codep;
2973 static unsigned char *end_codep;
2974 static int last_lock_prefix;
2975 static int last_repz_prefix;
2976 static int last_repnz_prefix;
2977 static int last_data_prefix;
2978 static int last_addr_prefix;
2979 static int last_rex_prefix;
2980 static int last_seg_prefix;
2981 static int fwait_prefix;
2982 /* The active segment register prefix.  */
2983 static int active_seg_prefix;
2984 #define MAX_CODE_LENGTH 15
2985 /* We can up to 14 prefixes since the maximum instruction length is
2986    15bytes.  */
2987 static int all_prefixes[MAX_CODE_LENGTH - 1];
2988 static disassemble_info *the_info;
2989 static struct
2990   {
2991     int mod;
2992     int reg;
2993     int rm;
2994   }
2995 modrm;
2996 static unsigned char need_modrm;
2997 static struct
2998   {
2999     int scale;
3000     int index;
3001     int base;
3002   }
3003 sib;
3004 static struct
3005   {
3006     int register_specifier;
3007     int length;
3008     int prefix;
3009     int w;
3010     int evex;
3011     int r;
3012     int v;
3013     int mask_register_specifier;
3014     int zeroing;
3015     int ll;
3016     int b;
3017   }
3018 vex;
3019 static unsigned char need_vex;
3020 static unsigned char need_vex_reg;
3021 static unsigned char vex_w_done;
3022
3023 struct op
3024   {
3025     const char *name;
3026     unsigned int len;
3027   };
3028
3029 /* If we are accessing mod/rm/reg without need_modrm set, then the
3030    values are stale.  Hitting this abort likely indicates that you
3031    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3032 #define MODRM_CHECK  if (!need_modrm) abort ()
3033
3034 static const char **names64;
3035 static const char **names32;
3036 static const char **names16;
3037 static const char **names8;
3038 static const char **names8rex;
3039 static const char **names_seg;
3040 static const char *index64;
3041 static const char *index32;
3042 static const char **index16;
3043 static const char **names_bnd;
3044
3045 static const char *intel_names64[] = {
3046   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3047   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3048 };
3049 static const char *intel_names32[] = {
3050   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3051   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3052 };
3053 static const char *intel_names16[] = {
3054   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3055   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3056 };
3057 static const char *intel_names8[] = {
3058   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3059 };
3060 static const char *intel_names8rex[] = {
3061   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3062   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3063 };
3064 static const char *intel_names_seg[] = {
3065   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3066 };
3067 static const char *intel_index64 = "riz";
3068 static const char *intel_index32 = "eiz";
3069 static const char *intel_index16[] = {
3070   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3071 };
3072
3073 static const char *att_names64[] = {
3074   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3075   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3076 };
3077 static const char *att_names32[] = {
3078   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3079   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3080 };
3081 static const char *att_names16[] = {
3082   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3083   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3084 };
3085 static const char *att_names8[] = {
3086   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3087 };
3088 static const char *att_names8rex[] = {
3089   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3090   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3091 };
3092 static const char *att_names_seg[] = {
3093   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3094 };
3095 static const char *att_index64 = "%riz";
3096 static const char *att_index32 = "%eiz";
3097 static const char *att_index16[] = {
3098   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3099 };
3100
3101 static const char **names_mm;
3102 static const char *intel_names_mm[] = {
3103   "mm0", "mm1", "mm2", "mm3",
3104   "mm4", "mm5", "mm6", "mm7"
3105 };
3106 static const char *att_names_mm[] = {
3107   "%mm0", "%mm1", "%mm2", "%mm3",
3108   "%mm4", "%mm5", "%mm6", "%mm7"
3109 };
3110
3111 static const char *intel_names_bnd[] = {
3112   "bnd0", "bnd1", "bnd2", "bnd3"
3113 };
3114
3115 static const char *att_names_bnd[] = {
3116   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3117 };
3118
3119 static const char **names_xmm;
3120 static const char *intel_names_xmm[] = {
3121   "xmm0", "xmm1", "xmm2", "xmm3",
3122   "xmm4", "xmm5", "xmm6", "xmm7",
3123   "xmm8", "xmm9", "xmm10", "xmm11",
3124   "xmm12", "xmm13", "xmm14", "xmm15",
3125   "xmm16", "xmm17", "xmm18", "xmm19",
3126   "xmm20", "xmm21", "xmm22", "xmm23",
3127   "xmm24", "xmm25", "xmm26", "xmm27",
3128   "xmm28", "xmm29", "xmm30", "xmm31"
3129 };
3130 static const char *att_names_xmm[] = {
3131   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3132   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3133   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3134   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3135   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3136   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3137   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3138   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3139 };
3140
3141 static const char **names_ymm;
3142 static const char *intel_names_ymm[] = {
3143   "ymm0", "ymm1", "ymm2", "ymm3",
3144   "ymm4", "ymm5", "ymm6", "ymm7",
3145   "ymm8", "ymm9", "ymm10", "ymm11",
3146   "ymm12", "ymm13", "ymm14", "ymm15",
3147   "ymm16", "ymm17", "ymm18", "ymm19",
3148   "ymm20", "ymm21", "ymm22", "ymm23",
3149   "ymm24", "ymm25", "ymm26", "ymm27",
3150   "ymm28", "ymm29", "ymm30", "ymm31"
3151 };
3152 static const char *att_names_ymm[] = {
3153   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3154   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3155   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3156   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3157   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3158   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3159   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3160   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3161 };
3162
3163 static const char **names_zmm;
3164 static const char *intel_names_zmm[] = {
3165   "zmm0", "zmm1", "zmm2", "zmm3",
3166   "zmm4", "zmm5", "zmm6", "zmm7",
3167   "zmm8", "zmm9", "zmm10", "zmm11",
3168   "zmm12", "zmm13", "zmm14", "zmm15",
3169   "zmm16", "zmm17", "zmm18", "zmm19",
3170   "zmm20", "zmm21", "zmm22", "zmm23",
3171   "zmm24", "zmm25", "zmm26", "zmm27",
3172   "zmm28", "zmm29", "zmm30", "zmm31"
3173 };
3174 static const char *att_names_zmm[] = {
3175   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3176   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3177   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3178   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3179   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3180   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3181   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3182   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3183 };
3184
3185 static const char **names_mask;
3186 static const char *intel_names_mask[] = {
3187   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3188 };
3189 static const char *att_names_mask[] = {
3190   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3191 };
3192
3193 static const char *names_rounding[] =
3194 {
3195   "{rn-sae}",
3196   "{rd-sae}",
3197   "{ru-sae}",
3198   "{rz-sae}"
3199 };
3200
3201 static const struct dis386 reg_table[][8] = {
3202   /* REG_80 */
3203   {
3204     { "addA",   { Ebh1, Ib }, 0 },
3205     { "orA",    { Ebh1, Ib }, 0 },
3206     { "adcA",   { Ebh1, Ib }, 0 },
3207     { "sbbA",   { Ebh1, Ib }, 0 },
3208     { "andA",   { Ebh1, Ib }, 0 },
3209     { "subA",   { Ebh1, Ib }, 0 },
3210     { "xorA",   { Ebh1, Ib }, 0 },
3211     { "cmpA",   { Eb, Ib }, 0 },
3212   },
3213   /* REG_81 */
3214   {
3215     { "addQ",   { Evh1, Iv }, 0 },
3216     { "orQ",    { Evh1, Iv }, 0 },
3217     { "adcQ",   { Evh1, Iv }, 0 },
3218     { "sbbQ",   { Evh1, Iv }, 0 },
3219     { "andQ",   { Evh1, Iv }, 0 },
3220     { "subQ",   { Evh1, Iv }, 0 },
3221     { "xorQ",   { Evh1, Iv }, 0 },
3222     { "cmpQ",   { Ev, Iv }, 0 },
3223   },
3224   /* REG_83 */
3225   {
3226     { "addQ",   { Evh1, sIb }, 0 },
3227     { "orQ",    { Evh1, sIb }, 0 },
3228     { "adcQ",   { Evh1, sIb }, 0 },
3229     { "sbbQ",   { Evh1, sIb }, 0 },
3230     { "andQ",   { Evh1, sIb }, 0 },
3231     { "subQ",   { Evh1, sIb }, 0 },
3232     { "xorQ",   { Evh1, sIb }, 0 },
3233     { "cmpQ",   { Ev, sIb }, 0 },
3234   },
3235   /* REG_8F */
3236   {
3237     { "popU",   { stackEv }, 0 },
3238     { XOP_8F_TABLE (XOP_09) },
3239     { Bad_Opcode },
3240     { Bad_Opcode },
3241     { Bad_Opcode },
3242     { XOP_8F_TABLE (XOP_09) },
3243   },
3244   /* REG_C0 */
3245   {
3246     { "rolA",   { Eb, Ib }, 0 },
3247     { "rorA",   { Eb, Ib }, 0 },
3248     { "rclA",   { Eb, Ib }, 0 },
3249     { "rcrA",   { Eb, Ib }, 0 },
3250     { "shlA",   { Eb, Ib }, 0 },
3251     { "shrA",   { Eb, Ib }, 0 },
3252     { "shlA",   { Eb, Ib }, 0 },
3253     { "sarA",   { Eb, Ib }, 0 },
3254   },
3255   /* REG_C1 */
3256   {
3257     { "rolQ",   { Ev, Ib }, 0 },
3258     { "rorQ",   { Ev, Ib }, 0 },
3259     { "rclQ",   { Ev, Ib }, 0 },
3260     { "rcrQ",   { Ev, Ib }, 0 },
3261     { "shlQ",   { Ev, Ib }, 0 },
3262     { "shrQ",   { Ev, Ib }, 0 },
3263     { "shlQ",   { Ev, Ib }, 0 },
3264     { "sarQ",   { Ev, Ib }, 0 },
3265   },
3266   /* REG_C6 */
3267   {
3268     { "movA",   { Ebh3, Ib }, 0 },
3269     { Bad_Opcode },
3270     { Bad_Opcode },
3271     { Bad_Opcode },
3272     { Bad_Opcode },
3273     { Bad_Opcode },
3274     { Bad_Opcode },
3275     { MOD_TABLE (MOD_C6_REG_7) },
3276   },
3277   /* REG_C7 */
3278   {
3279     { "movQ",   { Evh3, Iv }, 0 },
3280     { Bad_Opcode },
3281     { Bad_Opcode },
3282     { Bad_Opcode },
3283     { Bad_Opcode },
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { MOD_TABLE (MOD_C7_REG_7) },
3287   },
3288   /* REG_D0 */
3289   {
3290     { "rolA",   { Eb, I1 }, 0 },
3291     { "rorA",   { Eb, I1 }, 0 },
3292     { "rclA",   { Eb, I1 }, 0 },
3293     { "rcrA",   { Eb, I1 }, 0 },
3294     { "shlA",   { Eb, I1 }, 0 },
3295     { "shrA",   { Eb, I1 }, 0 },
3296     { "shlA",   { Eb, I1 }, 0 },
3297     { "sarA",   { Eb, I1 }, 0 },
3298   },
3299   /* REG_D1 */
3300   {
3301     { "rolQ",   { Ev, I1 }, 0 },
3302     { "rorQ",   { Ev, I1 }, 0 },
3303     { "rclQ",   { Ev, I1 }, 0 },
3304     { "rcrQ",   { Ev, I1 }, 0 },
3305     { "shlQ",   { Ev, I1 }, 0 },
3306     { "shrQ",   { Ev, I1 }, 0 },
3307     { "shlQ",   { Ev, I1 }, 0 },
3308     { "sarQ",   { Ev, I1 }, 0 },
3309   },
3310   /* REG_D2 */
3311   {
3312     { "rolA",   { Eb, CL }, 0 },
3313     { "rorA",   { Eb, CL }, 0 },
3314     { "rclA",   { Eb, CL }, 0 },
3315     { "rcrA",   { Eb, CL }, 0 },
3316     { "shlA",   { Eb, CL }, 0 },
3317     { "shrA",   { Eb, CL }, 0 },
3318     { "shlA",   { Eb, CL }, 0 },
3319     { "sarA",   { Eb, CL }, 0 },
3320   },
3321   /* REG_D3 */
3322   {
3323     { "rolQ",   { Ev, CL }, 0 },
3324     { "rorQ",   { Ev, CL }, 0 },
3325     { "rclQ",   { Ev, CL }, 0 },
3326     { "rcrQ",   { Ev, CL }, 0 },
3327     { "shlQ",   { Ev, CL }, 0 },
3328     { "shrQ",   { Ev, CL }, 0 },
3329     { "shlQ",   { Ev, CL }, 0 },
3330     { "sarQ",   { Ev, CL }, 0 },
3331   },
3332   /* REG_F6 */
3333   {
3334     { "testA",  { Eb, Ib }, 0 },
3335     { "testA",  { Eb, Ib }, 0 },
3336     { "notA",   { Ebh1 }, 0 },
3337     { "negA",   { Ebh1 }, 0 },
3338     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3339     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3340     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3341     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3342   },
3343   /* REG_F7 */
3344   {
3345     { "testQ",  { Ev, Iv }, 0 },
3346     { "testQ",  { Ev, Iv }, 0 },
3347     { "notQ",   { Evh1 }, 0 },
3348     { "negQ",   { Evh1 }, 0 },
3349     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3350     { "imulQ",  { Ev }, 0 },
3351     { "divQ",   { Ev }, 0 },
3352     { "idivQ",  { Ev }, 0 },
3353   },
3354   /* REG_FE */
3355   {
3356     { "incA",   { Ebh1 }, 0 },
3357     { "decA",   { Ebh1 }, 0 },
3358   },
3359   /* REG_FF */
3360   {
3361     { "incQ",   { Evh1 }, 0 },
3362     { "decQ",   { Evh1 }, 0 },
3363     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3364     { MOD_TABLE (MOD_FF_REG_3) },
3365     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3366     { MOD_TABLE (MOD_FF_REG_5) },
3367     { "pushU",  { stackEv }, 0 },
3368     { Bad_Opcode },
3369   },
3370   /* REG_0F00 */
3371   {
3372     { "sldtD",  { Sv }, 0 },
3373     { "strD",   { Sv }, 0 },
3374     { "lldt",   { Ew }, 0 },
3375     { "ltr",    { Ew }, 0 },
3376     { "verr",   { Ew }, 0 },
3377     { "verw",   { Ew }, 0 },
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380   },
3381   /* REG_0F01 */
3382   {
3383     { MOD_TABLE (MOD_0F01_REG_0) },
3384     { MOD_TABLE (MOD_0F01_REG_1) },
3385     { MOD_TABLE (MOD_0F01_REG_2) },
3386     { MOD_TABLE (MOD_0F01_REG_3) },
3387     { "smswD",  { Sv }, 0 },
3388     { MOD_TABLE (MOD_0F01_REG_5) },
3389     { "lmsw",   { Ew }, 0 },
3390     { MOD_TABLE (MOD_0F01_REG_7) },
3391   },
3392   /* REG_0F0D */
3393   {
3394     { "prefetch",       { Mb }, 0 },
3395     { "prefetchw",      { Mb }, 0 },
3396     { "prefetchwt1",    { Mb }, 0 },
3397     { "prefetch",       { Mb }, 0 },
3398     { "prefetch",       { Mb }, 0 },
3399     { "prefetch",       { Mb }, 0 },
3400     { "prefetch",       { Mb }, 0 },
3401     { "prefetch",       { Mb }, 0 },
3402   },
3403   /* REG_0F18 */
3404   {
3405     { MOD_TABLE (MOD_0F18_REG_0) },
3406     { MOD_TABLE (MOD_0F18_REG_1) },
3407     { MOD_TABLE (MOD_0F18_REG_2) },
3408     { MOD_TABLE (MOD_0F18_REG_3) },
3409     { MOD_TABLE (MOD_0F18_REG_4) },
3410     { MOD_TABLE (MOD_0F18_REG_5) },
3411     { MOD_TABLE (MOD_0F18_REG_6) },
3412     { MOD_TABLE (MOD_0F18_REG_7) },
3413   },
3414   /* REG_0F1C_MOD_0 */
3415   {
3416     { "cldemote",       { Mb }, 0 },
3417     { "nopQ",           { Ev }, 0 },
3418     { "nopQ",           { Ev }, 0 },
3419     { "nopQ",           { Ev }, 0 },
3420     { "nopQ",           { Ev }, 0 },
3421     { "nopQ",           { Ev }, 0 },
3422     { "nopQ",           { Ev }, 0 },
3423     { "nopQ",           { Ev }, 0 },
3424   },
3425   /* REG_0F1E_MOD_3 */
3426   {
3427     { "nopQ",           { Ev }, 0 },
3428     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3429     { "nopQ",           { Ev }, 0 },
3430     { "nopQ",           { Ev }, 0 },
3431     { "nopQ",           { Ev }, 0 },
3432     { "nopQ",           { Ev }, 0 },
3433     { "nopQ",           { Ev }, 0 },
3434     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3435   },
3436   /* REG_0F71 */
3437   {
3438     { Bad_Opcode },
3439     { Bad_Opcode },
3440     { MOD_TABLE (MOD_0F71_REG_2) },
3441     { Bad_Opcode },
3442     { MOD_TABLE (MOD_0F71_REG_4) },
3443     { Bad_Opcode },
3444     { MOD_TABLE (MOD_0F71_REG_6) },
3445   },
3446   /* REG_0F72 */
3447   {
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { MOD_TABLE (MOD_0F72_REG_2) },
3451     { Bad_Opcode },
3452     { MOD_TABLE (MOD_0F72_REG_4) },
3453     { Bad_Opcode },
3454     { MOD_TABLE (MOD_0F72_REG_6) },
3455   },
3456   /* REG_0F73 */
3457   {
3458     { Bad_Opcode },
3459     { Bad_Opcode },
3460     { MOD_TABLE (MOD_0F73_REG_2) },
3461     { MOD_TABLE (MOD_0F73_REG_3) },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { MOD_TABLE (MOD_0F73_REG_6) },
3465     { MOD_TABLE (MOD_0F73_REG_7) },
3466   },
3467   /* REG_0FA6 */
3468   {
3469     { "montmul",        { { OP_0f07, 0 } }, 0 },
3470     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3471     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3472   },
3473   /* REG_0FA7 */
3474   {
3475     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3476     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3477     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3478     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3479     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3480     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3481   },
3482   /* REG_0FAE */
3483   {
3484     { MOD_TABLE (MOD_0FAE_REG_0) },
3485     { MOD_TABLE (MOD_0FAE_REG_1) },
3486     { MOD_TABLE (MOD_0FAE_REG_2) },
3487     { MOD_TABLE (MOD_0FAE_REG_3) },
3488     { MOD_TABLE (MOD_0FAE_REG_4) },
3489     { MOD_TABLE (MOD_0FAE_REG_5) },
3490     { MOD_TABLE (MOD_0FAE_REG_6) },
3491     { MOD_TABLE (MOD_0FAE_REG_7) },
3492   },
3493   /* REG_0FBA */
3494   {
3495     { Bad_Opcode },
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { Bad_Opcode },
3499     { "btQ",    { Ev, Ib }, 0 },
3500     { "btsQ",   { Evh1, Ib }, 0 },
3501     { "btrQ",   { Evh1, Ib }, 0 },
3502     { "btcQ",   { Evh1, Ib }, 0 },
3503   },
3504   /* REG_0FC7 */
3505   {
3506     { Bad_Opcode },
3507     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3508     { Bad_Opcode },
3509     { MOD_TABLE (MOD_0FC7_REG_3) },
3510     { MOD_TABLE (MOD_0FC7_REG_4) },
3511     { MOD_TABLE (MOD_0FC7_REG_5) },
3512     { MOD_TABLE (MOD_0FC7_REG_6) },
3513     { MOD_TABLE (MOD_0FC7_REG_7) },
3514   },
3515   /* REG_VEX_0F71 */
3516   {
3517     { Bad_Opcode },
3518     { Bad_Opcode },
3519     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3520     { Bad_Opcode },
3521     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3522     { Bad_Opcode },
3523     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3524   },
3525   /* REG_VEX_0F72 */
3526   {
3527     { Bad_Opcode },
3528     { Bad_Opcode },
3529     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3530     { Bad_Opcode },
3531     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3532     { Bad_Opcode },
3533     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3534   },
3535   /* REG_VEX_0F73 */
3536   {
3537     { Bad_Opcode },
3538     { Bad_Opcode },
3539     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3540     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3541     { Bad_Opcode },
3542     { Bad_Opcode },
3543     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3544     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3545   },
3546   /* REG_VEX_0FAE */
3547   {
3548     { Bad_Opcode },
3549     { Bad_Opcode },
3550     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3551     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3552   },
3553   /* REG_VEX_0F38F3 */
3554   {
3555     { Bad_Opcode },
3556     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3557     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3558     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3559   },
3560   /* REG_XOP_LWPCB */
3561   {
3562     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3563     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3564   },
3565   /* REG_XOP_LWP */
3566   {
3567     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3568     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3569   },
3570   /* REG_XOP_TBM_01 */
3571   {
3572     { Bad_Opcode },
3573     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3574     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3575     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3576     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3577     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3578     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3579     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3580   },
3581   /* REG_XOP_TBM_02 */
3582   {
3583     { Bad_Opcode },
3584     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3585     { Bad_Opcode },
3586     { Bad_Opcode },
3587     { Bad_Opcode },
3588     { Bad_Opcode },
3589     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3590   },
3591 #define NEED_REG_TABLE
3592 #include "i386-dis-evex.h"
3593 #undef NEED_REG_TABLE
3594 };
3595
3596 static const struct dis386 prefix_table[][4] = {
3597   /* PREFIX_90 */
3598   {
3599     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3600     { "pause", { XX }, 0 },
3601     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3602     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3603   },
3604
3605   /* PREFIX_MOD_0_0F01_REG_5 */
3606   {
3607     { Bad_Opcode },
3608     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3609   },
3610
3611   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3612   {
3613     { Bad_Opcode },
3614     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3615   },
3616
3617   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3618   {
3619     { Bad_Opcode },
3620     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3621   },
3622
3623   /* PREFIX_0F09 */
3624   {
3625     { "wbinvd",   { XX }, 0 },
3626     { "wbnoinvd", { XX }, 0 },
3627   },
3628
3629   /* PREFIX_0F10 */
3630   {
3631     { "movups", { XM, EXx }, PREFIX_OPCODE },
3632     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3633     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3634     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3635   },
3636
3637   /* PREFIX_0F11 */
3638   {
3639     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3640     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3641     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3642     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3643   },
3644
3645   /* PREFIX_0F12 */
3646   {
3647     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3648     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3649     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3650     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3651   },
3652
3653   /* PREFIX_0F16 */
3654   {
3655     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3656     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3657     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3658   },
3659
3660   /* PREFIX_0F1A */
3661   {
3662     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3663     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3664     { "bndmov", { Gbnd, Ebnd }, 0 },
3665     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3666   },
3667
3668   /* PREFIX_0F1B */
3669   {
3670     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3671     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3672     { "bndmov", { EbndS, Gbnd }, 0 },
3673     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3674   },
3675
3676   /* PREFIX_0F1C */
3677   {
3678     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3679     { "nopQ",   { Ev }, PREFIX_OPCODE },
3680     { "nopQ",   { Ev }, PREFIX_OPCODE },
3681     { "nopQ",   { Ev }, PREFIX_OPCODE },
3682   },
3683
3684   /* PREFIX_0F1E */
3685   {
3686     { "nopQ",   { Ev }, PREFIX_OPCODE },
3687     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3688     { "nopQ",   { Ev }, PREFIX_OPCODE },
3689     { "nopQ",   { Ev }, PREFIX_OPCODE },
3690   },
3691
3692   /* PREFIX_0F2A */
3693   {
3694     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3695     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3696     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3697     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3698   },
3699
3700   /* PREFIX_0F2B */
3701   {
3702     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3703     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3704     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3705     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3706   },
3707
3708   /* PREFIX_0F2C */
3709   {
3710     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3711     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3712     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3713     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3714   },
3715
3716   /* PREFIX_0F2D */
3717   {
3718     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3719     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3720     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3721     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3722   },
3723
3724   /* PREFIX_0F2E */
3725   {
3726     { "ucomiss",{ XM, EXd }, 0 },
3727     { Bad_Opcode },
3728     { "ucomisd",{ XM, EXq }, 0 },
3729   },
3730
3731   /* PREFIX_0F2F */
3732   {
3733     { "comiss", { XM, EXd }, 0 },
3734     { Bad_Opcode },
3735     { "comisd", { XM, EXq }, 0 },
3736   },
3737
3738   /* PREFIX_0F51 */
3739   {
3740     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3741     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3742     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3743     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3744   },
3745
3746   /* PREFIX_0F52 */
3747   {
3748     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3749     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3750   },
3751
3752   /* PREFIX_0F53 */
3753   {
3754     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3755     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3756   },
3757
3758   /* PREFIX_0F58 */
3759   {
3760     { "addps", { XM, EXx }, PREFIX_OPCODE },
3761     { "addss", { XM, EXd }, PREFIX_OPCODE },
3762     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3763     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3764   },
3765
3766   /* PREFIX_0F59 */
3767   {
3768     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3769     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3770     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3771     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3772   },
3773
3774   /* PREFIX_0F5A */
3775   {
3776     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3777     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3778     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3779     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3780   },
3781
3782   /* PREFIX_0F5B */
3783   {
3784     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3785     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3786     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F5C */
3790   {
3791     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3792     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3793     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3794     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_0F5D */
3798   {
3799     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3800     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3801     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3802     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3803   },
3804
3805   /* PREFIX_0F5E */
3806   {
3807     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3808     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3809     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3810     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3811   },
3812
3813   /* PREFIX_0F5F */
3814   {
3815     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3816     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3817     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3818     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3819   },
3820
3821   /* PREFIX_0F60 */
3822   {
3823     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3824     { Bad_Opcode },
3825     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F61 */
3829   {
3830     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3831     { Bad_Opcode },
3832     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3833   },
3834
3835   /* PREFIX_0F62 */
3836   {
3837     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3838     { Bad_Opcode },
3839     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F6C */
3843   {
3844     { Bad_Opcode },
3845     { Bad_Opcode },
3846     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3847   },
3848
3849   /* PREFIX_0F6D */
3850   {
3851     { Bad_Opcode },
3852     { Bad_Opcode },
3853     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F6F */
3857   {
3858     { "movq",   { MX, EM }, PREFIX_OPCODE },
3859     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3860     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3861   },
3862
3863   /* PREFIX_0F70 */
3864   {
3865     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3866     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3867     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3868     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3869   },
3870
3871   /* PREFIX_0F73_REG_3 */
3872   {
3873     { Bad_Opcode },
3874     { Bad_Opcode },
3875     { "psrldq", { XS, Ib }, 0 },
3876   },
3877
3878   /* PREFIX_0F73_REG_7 */
3879   {
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { "pslldq", { XS, Ib }, 0 },
3883   },
3884
3885   /* PREFIX_0F78 */
3886   {
3887     {"vmread",  { Em, Gm }, 0 },
3888     { Bad_Opcode },
3889     {"extrq",   { XS, Ib, Ib }, 0 },
3890     {"insertq", { XM, XS, Ib, Ib }, 0 },
3891   },
3892
3893   /* PREFIX_0F79 */
3894   {
3895     {"vmwrite", { Gm, Em }, 0 },
3896     { Bad_Opcode },
3897     {"extrq",   { XM, XS }, 0 },
3898     {"insertq", { XM, XS }, 0 },
3899   },
3900
3901   /* PREFIX_0F7C */
3902   {
3903     { Bad_Opcode },
3904     { Bad_Opcode },
3905     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3906     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3907   },
3908
3909   /* PREFIX_0F7D */
3910   {
3911     { Bad_Opcode },
3912     { Bad_Opcode },
3913     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3914     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3915   },
3916
3917   /* PREFIX_0F7E */
3918   {
3919     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3920     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3921     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3922   },
3923
3924   /* PREFIX_0F7F */
3925   {
3926     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3927     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3928     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3929   },
3930
3931   /* PREFIX_0FAE_REG_0 */
3932   {
3933     { Bad_Opcode },
3934     { "rdfsbase", { Ev }, 0 },
3935   },
3936
3937   /* PREFIX_0FAE_REG_1 */
3938   {
3939     { Bad_Opcode },
3940     { "rdgsbase", { Ev }, 0 },
3941   },
3942
3943   /* PREFIX_0FAE_REG_2 */
3944   {
3945     { Bad_Opcode },
3946     { "wrfsbase", { Ev }, 0 },
3947   },
3948
3949   /* PREFIX_0FAE_REG_3 */
3950   {
3951     { Bad_Opcode },
3952     { "wrgsbase", { Ev }, 0 },
3953   },
3954
3955   /* PREFIX_MOD_0_0FAE_REG_4 */
3956   {
3957     { "xsave",  { FXSAVE }, 0 },
3958     { "ptwrite%LQ", { Edq }, 0 },
3959   },
3960
3961   /* PREFIX_MOD_3_0FAE_REG_4 */
3962   {
3963     { Bad_Opcode },
3964     { "ptwrite%LQ", { Edq }, 0 },
3965   },
3966
3967   /* PREFIX_MOD_0_0FAE_REG_5 */
3968   {
3969     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_MOD_3_0FAE_REG_5 */
3973   {
3974     { "lfence",         { Skip_MODRM }, 0 },
3975     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3976   },
3977
3978   /* PREFIX_MOD_0_0FAE_REG_6 */
3979   {
3980     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3981     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3982     { "clwb",   { Mb }, PREFIX_OPCODE },
3983   },
3984
3985   /* PREFIX_MOD_1_0FAE_REG_6 */
3986   {
3987     { RM_TABLE (RM_0FAE_REG_6) },
3988     { "umonitor",       { Eva }, PREFIX_OPCODE },
3989     { "tpause", { Edq }, PREFIX_OPCODE },
3990     { "umwait", { Edq }, PREFIX_OPCODE },
3991   },
3992
3993   /* PREFIX_0FAE_REG_7 */
3994   {
3995     { "clflush",        { Mb }, 0 },
3996     { Bad_Opcode },
3997     { "clflushopt",     { Mb }, 0 },
3998   },
3999
4000   /* PREFIX_0FB8 */
4001   {
4002     { Bad_Opcode },
4003     { "popcntS", { Gv, Ev }, 0 },
4004   },
4005
4006   /* PREFIX_0FBC */
4007   {
4008     { "bsfS",   { Gv, Ev }, 0 },
4009     { "tzcntS", { Gv, Ev }, 0 },
4010     { "bsfS",   { Gv, Ev }, 0 },
4011   },
4012
4013   /* PREFIX_0FBD */
4014   {
4015     { "bsrS",   { Gv, Ev }, 0 },
4016     { "lzcntS", { Gv, Ev }, 0 },
4017     { "bsrS",   { Gv, Ev }, 0 },
4018   },
4019
4020   /* PREFIX_0FC2 */
4021   {
4022     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4023     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4024     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4025     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4026   },
4027
4028   /* PREFIX_MOD_0_0FC3 */
4029   {
4030     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4031   },
4032
4033   /* PREFIX_MOD_0_0FC7_REG_6 */
4034   {
4035     { "vmptrld",{ Mq }, 0 },
4036     { "vmxon",  { Mq }, 0 },
4037     { "vmclear",{ Mq }, 0 },
4038   },
4039
4040   /* PREFIX_MOD_3_0FC7_REG_6 */
4041   {
4042     { "rdrand", { Ev }, 0 },
4043     { Bad_Opcode },
4044     { "rdrand", { Ev }, 0 }
4045   },
4046
4047   /* PREFIX_MOD_3_0FC7_REG_7 */
4048   {
4049     { "rdseed", { Ev }, 0 },
4050     { "rdpid",  { Em }, 0 },
4051     { "rdseed", { Ev }, 0 },
4052   },
4053
4054   /* PREFIX_0FD0 */
4055   {
4056     { Bad_Opcode },
4057     { Bad_Opcode },
4058     { "addsubpd", { XM, EXx }, 0 },
4059     { "addsubps", { XM, EXx }, 0 },
4060   },
4061
4062   /* PREFIX_0FD6 */
4063   {
4064     { Bad_Opcode },
4065     { "movq2dq",{ XM, MS }, 0 },
4066     { "movq",   { EXqS, XM }, 0 },
4067     { "movdq2q",{ MX, XS }, 0 },
4068   },
4069
4070   /* PREFIX_0FE6 */
4071   {
4072     { Bad_Opcode },
4073     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4074     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4075     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4076   },
4077
4078   /* PREFIX_0FE7 */
4079   {
4080     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4081     { Bad_Opcode },
4082     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4083   },
4084
4085   /* PREFIX_0FF0 */
4086   {
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4091   },
4092
4093   /* PREFIX_0FF7 */
4094   {
4095     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4096     { Bad_Opcode },
4097     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4098   },
4099
4100   /* PREFIX_0F3810 */
4101   {
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4105   },
4106
4107   /* PREFIX_0F3814 */
4108   {
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4112   },
4113
4114   /* PREFIX_0F3815 */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4119   },
4120
4121   /* PREFIX_0F3817 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4126   },
4127
4128   /* PREFIX_0F3820 */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4133   },
4134
4135   /* PREFIX_0F3821 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4140   },
4141
4142   /* PREFIX_0F3822 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4147   },
4148
4149   /* PREFIX_0F3823 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4154   },
4155
4156   /* PREFIX_0F3824 */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4161   },
4162
4163   /* PREFIX_0F3825 */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4168   },
4169
4170   /* PREFIX_0F3828 */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0F3829 */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4182   },
4183
4184   /* PREFIX_0F382A */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4189   },
4190
4191   /* PREFIX_0F382B */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4196   },
4197
4198   /* PREFIX_0F3830 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4203   },
4204
4205   /* PREFIX_0F3831 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4210   },
4211
4212   /* PREFIX_0F3832 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4217   },
4218
4219   /* PREFIX_0F3833 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4224   },
4225
4226   /* PREFIX_0F3834 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_0F3835 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4238   },
4239
4240   /* PREFIX_0F3837 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4245   },
4246
4247   /* PREFIX_0F3838 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F3839 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F383A */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F383B */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_0F383C */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F383D */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_0F383E */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F383F */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F3840 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F3841 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F3880 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F3881 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F3882 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4336   },
4337
4338   /* PREFIX_0F38C8 */
4339   {
4340     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F38C9 */
4344   {
4345     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4346   },
4347
4348   /* PREFIX_0F38CA */
4349   {
4350     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F38CB */
4354   {
4355     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F38CC */
4359   {
4360     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F38CD */
4364   {
4365     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F38CF */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F38DB */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F38DC */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F38DD */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4394   },
4395
4396   /* PREFIX_0F38DE */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F38DF */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F38F0 */
4411   {
4412     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4413     { Bad_Opcode },
4414     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4415     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4416   },
4417
4418   /* PREFIX_0F38F1 */
4419   {
4420     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4421     { Bad_Opcode },
4422     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4423     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F38F5 */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4431   },
4432
4433   /* PREFIX_0F38F6 */
4434   {
4435     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4436     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4437     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4438     { Bad_Opcode },
4439   },
4440
4441   /* PREFIX_0F38F8 */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4446   },
4447
4448   /* PREFIX_0F38F9 */
4449   {
4450     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4451   },
4452
4453   /* PREFIX_0F3A08 */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4458   },
4459
4460   /* PREFIX_0F3A09 */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4465   },
4466
4467   /* PREFIX_0F3A0A */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4472   },
4473
4474   /* PREFIX_0F3A0B */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4479   },
4480
4481   /* PREFIX_0F3A0C */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4486   },
4487
4488   /* PREFIX_0F3A0D */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4493   },
4494
4495   /* PREFIX_0F3A0E */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F3A14 */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4507   },
4508
4509   /* PREFIX_0F3A15 */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4514   },
4515
4516   /* PREFIX_0F3A16 */
4517   {
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4521   },
4522
4523   /* PREFIX_0F3A17 */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4528   },
4529
4530   /* PREFIX_0F3A20 */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4535   },
4536
4537   /* PREFIX_0F3A21 */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4542   },
4543
4544   /* PREFIX_0F3A22 */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4549   },
4550
4551   /* PREFIX_0F3A40 */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4556   },
4557
4558   /* PREFIX_0F3A41 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4563   },
4564
4565   /* PREFIX_0F3A42 */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4570   },
4571
4572   /* PREFIX_0F3A44 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4577   },
4578
4579   /* PREFIX_0F3A60 */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4584   },
4585
4586   /* PREFIX_0F3A61 */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4591   },
4592
4593   /* PREFIX_0F3A62 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4598   },
4599
4600   /* PREFIX_0F3A63 */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4605   },
4606
4607   /* PREFIX_0F3ACC */
4608   {
4609     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4610   },
4611
4612   /* PREFIX_0F3ACE */
4613   {
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4617   },
4618
4619   /* PREFIX_0F3ACF */
4620   {
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4624   },
4625
4626   /* PREFIX_0F3ADF */
4627   {
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4631   },
4632
4633   /* PREFIX_VEX_0F10 */
4634   {
4635     { "vmovups",        { XM, EXx }, 0 },
4636     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4637     { "vmovupd",        { XM, EXx }, 0 },
4638     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4639   },
4640
4641   /* PREFIX_VEX_0F11 */
4642   {
4643     { "vmovups",        { EXxS, XM }, 0 },
4644     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4645     { "vmovupd",        { EXxS, XM }, 0 },
4646     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4647   },
4648
4649   /* PREFIX_VEX_0F12 */
4650   {
4651     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4652     { "vmovsldup",      { XM, EXx }, 0 },
4653     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4654     { "vmovddup",       { XM, EXymmq }, 0 },
4655   },
4656
4657   /* PREFIX_VEX_0F16 */
4658   {
4659     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4660     { "vmovshdup",      { XM, EXx }, 0 },
4661     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4662   },
4663
4664   /* PREFIX_VEX_0F2A */
4665   {
4666     { Bad_Opcode },
4667     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4668     { Bad_Opcode },
4669     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4670   },
4671
4672   /* PREFIX_VEX_0F2C */
4673   {
4674     { Bad_Opcode },
4675     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4676     { Bad_Opcode },
4677     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4678   },
4679
4680   /* PREFIX_VEX_0F2D */
4681   {
4682     { Bad_Opcode },
4683     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4684     { Bad_Opcode },
4685     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4686   },
4687
4688   /* PREFIX_VEX_0F2E */
4689   {
4690     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4691     { Bad_Opcode },
4692     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4693   },
4694
4695   /* PREFIX_VEX_0F2F */
4696   {
4697     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4698     { Bad_Opcode },
4699     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4700   },
4701
4702   /* PREFIX_VEX_0F41 */
4703   {
4704     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4705     { Bad_Opcode },
4706     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4707   },
4708
4709   /* PREFIX_VEX_0F42 */
4710   {
4711     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4712     { Bad_Opcode },
4713     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4714   },
4715
4716   /* PREFIX_VEX_0F44 */
4717   {
4718     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4719     { Bad_Opcode },
4720     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4721   },
4722
4723   /* PREFIX_VEX_0F45 */
4724   {
4725     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4726     { Bad_Opcode },
4727     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4728   },
4729
4730   /* PREFIX_VEX_0F46 */
4731   {
4732     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4733     { Bad_Opcode },
4734     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4735   },
4736
4737   /* PREFIX_VEX_0F47 */
4738   {
4739     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4740     { Bad_Opcode },
4741     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4742   },
4743
4744   /* PREFIX_VEX_0F4A */
4745   {
4746     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4747     { Bad_Opcode },
4748     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4749   },
4750
4751   /* PREFIX_VEX_0F4B */
4752   {
4753     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4754     { Bad_Opcode },
4755     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4756   },
4757
4758   /* PREFIX_VEX_0F51 */
4759   {
4760     { "vsqrtps",        { XM, EXx }, 0 },
4761     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4762     { "vsqrtpd",        { XM, EXx }, 0 },
4763     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4764   },
4765
4766   /* PREFIX_VEX_0F52 */
4767   {
4768     { "vrsqrtps",       { XM, EXx }, 0 },
4769     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4770   },
4771
4772   /* PREFIX_VEX_0F53 */
4773   {
4774     { "vrcpps",         { XM, EXx }, 0 },
4775     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4776   },
4777
4778   /* PREFIX_VEX_0F58 */
4779   {
4780     { "vaddps",         { XM, Vex, EXx }, 0 },
4781     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4782     { "vaddpd",         { XM, Vex, EXx }, 0 },
4783     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4784   },
4785
4786   /* PREFIX_VEX_0F59 */
4787   {
4788     { "vmulps",         { XM, Vex, EXx }, 0 },
4789     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4790     { "vmulpd",         { XM, Vex, EXx }, 0 },
4791     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4792   },
4793
4794   /* PREFIX_VEX_0F5A */
4795   {
4796     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4797     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4798     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4799     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4800   },
4801
4802   /* PREFIX_VEX_0F5B */
4803   {
4804     { "vcvtdq2ps",      { XM, EXx }, 0 },
4805     { "vcvttps2dq",     { XM, EXx }, 0 },
4806     { "vcvtps2dq",      { XM, EXx }, 0 },
4807   },
4808
4809   /* PREFIX_VEX_0F5C */
4810   {
4811     { "vsubps",         { XM, Vex, EXx }, 0 },
4812     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4813     { "vsubpd",         { XM, Vex, EXx }, 0 },
4814     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4815   },
4816
4817   /* PREFIX_VEX_0F5D */
4818   {
4819     { "vminps",         { XM, Vex, EXx }, 0 },
4820     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4821     { "vminpd",         { XM, Vex, EXx }, 0 },
4822     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4823   },
4824
4825   /* PREFIX_VEX_0F5E */
4826   {
4827     { "vdivps",         { XM, Vex, EXx }, 0 },
4828     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4829     { "vdivpd",         { XM, Vex, EXx }, 0 },
4830     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4831   },
4832
4833   /* PREFIX_VEX_0F5F */
4834   {
4835     { "vmaxps",         { XM, Vex, EXx }, 0 },
4836     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4837     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4838     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4839   },
4840
4841   /* PREFIX_VEX_0F60 */
4842   {
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4846   },
4847
4848   /* PREFIX_VEX_0F61 */
4849   {
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4853   },
4854
4855   /* PREFIX_VEX_0F62 */
4856   {
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4860   },
4861
4862   /* PREFIX_VEX_0F63 */
4863   {
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4867   },
4868
4869   /* PREFIX_VEX_0F64 */
4870   {
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4874   },
4875
4876   /* PREFIX_VEX_0F65 */
4877   {
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4881   },
4882
4883   /* PREFIX_VEX_0F66 */
4884   {
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4888   },
4889
4890   /* PREFIX_VEX_0F67 */
4891   {
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4895   },
4896
4897   /* PREFIX_VEX_0F68 */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4902   },
4903
4904   /* PREFIX_VEX_0F69 */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4909   },
4910
4911   /* PREFIX_VEX_0F6A */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4916   },
4917
4918   /* PREFIX_VEX_0F6B */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4923   },
4924
4925   /* PREFIX_VEX_0F6C */
4926   {
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4930   },
4931
4932   /* PREFIX_VEX_0F6D */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4937   },
4938
4939   /* PREFIX_VEX_0F6E */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4944   },
4945
4946   /* PREFIX_VEX_0F6F */
4947   {
4948     { Bad_Opcode },
4949     { "vmovdqu",        { XM, EXx }, 0 },
4950     { "vmovdqa",        { XM, EXx }, 0 },
4951   },
4952
4953   /* PREFIX_VEX_0F70 */
4954   {
4955     { Bad_Opcode },
4956     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4957     { "vpshufd",        { XM, EXx, Ib }, 0 },
4958     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4959   },
4960
4961   /* PREFIX_VEX_0F71_REG_2 */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4966   },
4967
4968   /* PREFIX_VEX_0F71_REG_4 */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { "vpsraw",         { Vex, XS, Ib }, 0 },
4973   },
4974
4975   /* PREFIX_VEX_0F71_REG_6 */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { "vpsllw",         { Vex, XS, Ib }, 0 },
4980   },
4981
4982   /* PREFIX_VEX_0F72_REG_2 */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { "vpsrld",         { Vex, XS, Ib }, 0 },
4987   },
4988
4989   /* PREFIX_VEX_0F72_REG_4 */
4990   {
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { "vpsrad",         { Vex, XS, Ib }, 0 },
4994   },
4995
4996   /* PREFIX_VEX_0F72_REG_6 */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { "vpslld",         { Vex, XS, Ib }, 0 },
5001   },
5002
5003   /* PREFIX_VEX_0F73_REG_2 */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5008   },
5009
5010   /* PREFIX_VEX_0F73_REG_3 */
5011   {
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5015   },
5016
5017   /* PREFIX_VEX_0F73_REG_6 */
5018   {
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { "vpsllq",         { Vex, XS, Ib }, 0 },
5022   },
5023
5024   /* PREFIX_VEX_0F73_REG_7 */
5025   {
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { "vpslldq",        { Vex, XS, Ib }, 0 },
5029   },
5030
5031   /* PREFIX_VEX_0F74 */
5032   {
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5036   },
5037
5038   /* PREFIX_VEX_0F75 */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5043   },
5044
5045   /* PREFIX_VEX_0F76 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5050   },
5051
5052   /* PREFIX_VEX_0F77 */
5053   {
5054     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5055   },
5056
5057   /* PREFIX_VEX_0F7C */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5062     { "vhaddps",        { XM, Vex, EXx }, 0 },
5063   },
5064
5065   /* PREFIX_VEX_0F7D */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5070     { "vhsubps",        { XM, Vex, EXx }, 0 },
5071   },
5072
5073   /* PREFIX_VEX_0F7E */
5074   {
5075     { Bad_Opcode },
5076     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5077     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5078   },
5079
5080   /* PREFIX_VEX_0F7F */
5081   {
5082     { Bad_Opcode },
5083     { "vmovdqu",        { EXxS, XM }, 0 },
5084     { "vmovdqa",        { EXxS, XM }, 0 },
5085   },
5086
5087   /* PREFIX_VEX_0F90 */
5088   {
5089     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5090     { Bad_Opcode },
5091     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_0F91 */
5095   {
5096     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5097     { Bad_Opcode },
5098     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0F92 */
5102   {
5103     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5104     { Bad_Opcode },
5105     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5106     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5107   },
5108
5109   /* PREFIX_VEX_0F93 */
5110   {
5111     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5112     { Bad_Opcode },
5113     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5114     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5115   },
5116
5117   /* PREFIX_VEX_0F98 */
5118   {
5119     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5120     { Bad_Opcode },
5121     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5122   },
5123
5124   /* PREFIX_VEX_0F99 */
5125   {
5126     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5127     { Bad_Opcode },
5128     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_0FC2 */
5132   {
5133     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5134     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5135     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5136     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5137   },
5138
5139   /* PREFIX_VEX_0FC4 */
5140   {
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0FC5 */
5147   {
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5151   },
5152
5153   /* PREFIX_VEX_0FD0 */
5154   {
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5158     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5159   },
5160
5161   /* PREFIX_VEX_0FD1 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5166   },
5167
5168   /* PREFIX_VEX_0FD2 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5173   },
5174
5175   /* PREFIX_VEX_0FD3 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5180   },
5181
5182   /* PREFIX_VEX_0FD4 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { "vpaddq",         { XM, Vex, EXx }, 0 },
5187   },
5188
5189   /* PREFIX_VEX_0FD5 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { "vpmullw",        { XM, Vex, EXx }, 0 },
5194   },
5195
5196   /* PREFIX_VEX_0FD6 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5201   },
5202
5203   /* PREFIX_VEX_0FD7 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5208   },
5209
5210   /* PREFIX_VEX_0FD8 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5215   },
5216
5217   /* PREFIX_VEX_0FD9 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5222   },
5223
5224   /* PREFIX_VEX_0FDA */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { "vpminub",        { XM, Vex, EXx }, 0 },
5229   },
5230
5231   /* PREFIX_VEX_0FDB */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { "vpand",          { XM, Vex, EXx }, 0 },
5236   },
5237
5238   /* PREFIX_VEX_0FDC */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5243   },
5244
5245   /* PREFIX_VEX_0FDD */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5250   },
5251
5252   /* PREFIX_VEX_0FDE */
5253   {
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5257   },
5258
5259   /* PREFIX_VEX_0FDF */
5260   {
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { "vpandn",         { XM, Vex, EXx }, 0 },
5264   },
5265
5266   /* PREFIX_VEX_0FE0 */
5267   {
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { "vpavgb",         { XM, Vex, EXx }, 0 },
5271   },
5272
5273   /* PREFIX_VEX_0FE1 */
5274   {
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5278   },
5279
5280   /* PREFIX_VEX_0FE2 */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5285   },
5286
5287   /* PREFIX_VEX_0FE3 */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { "vpavgw",         { XM, Vex, EXx }, 0 },
5292   },
5293
5294   /* PREFIX_VEX_0FE4 */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5299   },
5300
5301   /* PREFIX_VEX_0FE5 */
5302   {
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5306   },
5307
5308   /* PREFIX_VEX_0FE6 */
5309   {
5310     { Bad_Opcode },
5311     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5312     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5313     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5314   },
5315
5316   /* PREFIX_VEX_0FE7 */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5321   },
5322
5323   /* PREFIX_VEX_0FE8 */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5328   },
5329
5330   /* PREFIX_VEX_0FE9 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5335   },
5336
5337   /* PREFIX_VEX_0FEA */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { "vpminsw",        { XM, Vex, EXx }, 0 },
5342   },
5343
5344   /* PREFIX_VEX_0FEB */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { "vpor",           { XM, Vex, EXx }, 0 },
5349   },
5350
5351   /* PREFIX_VEX_0FEC */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5356   },
5357
5358   /* PREFIX_VEX_0FED */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5363   },
5364
5365   /* PREFIX_VEX_0FEE */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5370   },
5371
5372   /* PREFIX_VEX_0FEF */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { "vpxor",          { XM, Vex, EXx }, 0 },
5377   },
5378
5379   /* PREFIX_VEX_0FF0 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5385   },
5386
5387   /* PREFIX_VEX_0FF1 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5392   },
5393
5394   /* PREFIX_VEX_0FF2 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5399   },
5400
5401   /* PREFIX_VEX_0FF3 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5406   },
5407
5408   /* PREFIX_VEX_0FF4 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5413   },
5414
5415   /* PREFIX_VEX_0FF5 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5420   },
5421
5422   /* PREFIX_VEX_0FF6 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5427   },
5428
5429   /* PREFIX_VEX_0FF7 */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5434   },
5435
5436   /* PREFIX_VEX_0FF8 */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { "vpsubb",         { XM, Vex, EXx }, 0 },
5441   },
5442
5443   /* PREFIX_VEX_0FF9 */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { "vpsubw",         { XM, Vex, EXx }, 0 },
5448   },
5449
5450   /* PREFIX_VEX_0FFA */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { "vpsubd",         { XM, Vex, EXx }, 0 },
5455   },
5456
5457   /* PREFIX_VEX_0FFB */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { "vpsubq",         { XM, Vex, EXx }, 0 },
5462   },
5463
5464   /* PREFIX_VEX_0FFC */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { "vpaddb",         { XM, Vex, EXx }, 0 },
5469   },
5470
5471   /* PREFIX_VEX_0FFD */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { "vpaddw",         { XM, Vex, EXx }, 0 },
5476   },
5477
5478   /* PREFIX_VEX_0FFE */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { "vpaddd",         { XM, Vex, EXx }, 0 },
5483   },
5484
5485   /* PREFIX_VEX_0F3800 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { "vpshufb",        { XM, Vex, EXx }, 0 },
5490   },
5491
5492   /* PREFIX_VEX_0F3801 */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { "vphaddw",        { XM, Vex, EXx }, 0 },
5497   },
5498
5499   /* PREFIX_VEX_0F3802 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { "vphaddd",        { XM, Vex, EXx }, 0 },
5504   },
5505
5506   /* PREFIX_VEX_0F3803 */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5511   },
5512
5513   /* PREFIX_VEX_0F3804 */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5518   },
5519
5520   /* PREFIX_VEX_0F3805 */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { "vphsubw",        { XM, Vex, EXx }, 0 },
5525   },
5526
5527   /* PREFIX_VEX_0F3806 */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { "vphsubd",        { XM, Vex, EXx }, 0 },
5532   },
5533
5534   /* PREFIX_VEX_0F3807 */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5539   },
5540
5541   /* PREFIX_VEX_0F3808 */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { "vpsignb",        { XM, Vex, EXx }, 0 },
5546   },
5547
5548   /* PREFIX_VEX_0F3809 */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { "vpsignw",        { XM, Vex, EXx }, 0 },
5553   },
5554
5555   /* PREFIX_VEX_0F380A */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { "vpsignd",        { XM, Vex, EXx }, 0 },
5560   },
5561
5562   /* PREFIX_VEX_0F380B */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5567   },
5568
5569   /* PREFIX_VEX_0F380C */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5574   },
5575
5576   /* PREFIX_VEX_0F380D */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5581   },
5582
5583   /* PREFIX_VEX_0F380E */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0F380F */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0F3813 */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5602   },
5603
5604   /* PREFIX_VEX_0F3816 */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F3817 */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { "vptest",         { XM, EXx }, 0 },
5616   },
5617
5618   /* PREFIX_VEX_0F3818 */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F3819 */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F381A */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F381C */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { "vpabsb",         { XM, EXx }, 0 },
5644   },
5645
5646   /* PREFIX_VEX_0F381D */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { "vpabsw",         { XM, EXx }, 0 },
5651   },
5652
5653   /* PREFIX_VEX_0F381E */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { "vpabsd",         { XM, EXx }, 0 },
5658   },
5659
5660   /* PREFIX_VEX_0F3820 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5665   },
5666
5667   /* PREFIX_VEX_0F3821 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5672   },
5673
5674   /* PREFIX_VEX_0F3822 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5679   },
5680
5681   /* PREFIX_VEX_0F3823 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5686   },
5687
5688   /* PREFIX_VEX_0F3824 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5693   },
5694
5695   /* PREFIX_VEX_0F3825 */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5700   },
5701
5702   /* PREFIX_VEX_0F3828 */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5707   },
5708
5709   /* PREFIX_VEX_0F3829 */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5714   },
5715
5716   /* PREFIX_VEX_0F382A */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5721   },
5722
5723   /* PREFIX_VEX_0F382B */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5728   },
5729
5730   /* PREFIX_VEX_0F382C */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5735   },
5736
5737   /* PREFIX_VEX_0F382D */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5742   },
5743
5744   /* PREFIX_VEX_0F382E */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5749   },
5750
5751   /* PREFIX_VEX_0F382F */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F3830 */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5763   },
5764
5765   /* PREFIX_VEX_0F3831 */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5770   },
5771
5772   /* PREFIX_VEX_0F3832 */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5777   },
5778
5779   /* PREFIX_VEX_0F3833 */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5784   },
5785
5786   /* PREFIX_VEX_0F3834 */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5791   },
5792
5793   /* PREFIX_VEX_0F3835 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5798   },
5799
5800   /* PREFIX_VEX_0F3836 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5805   },
5806
5807   /* PREFIX_VEX_0F3837 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5812   },
5813
5814   /* PREFIX_VEX_0F3838 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { "vpminsb",        { XM, Vex, EXx }, 0 },
5819   },
5820
5821   /* PREFIX_VEX_0F3839 */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { "vpminsd",        { XM, Vex, EXx }, 0 },
5826   },
5827
5828   /* PREFIX_VEX_0F383A */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { "vpminuw",        { XM, Vex, EXx }, 0 },
5833   },
5834
5835   /* PREFIX_VEX_0F383B */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { "vpminud",        { XM, Vex, EXx }, 0 },
5840   },
5841
5842   /* PREFIX_VEX_0F383C */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5847   },
5848
5849   /* PREFIX_VEX_0F383D */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5854   },
5855
5856   /* PREFIX_VEX_0F383E */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5861   },
5862
5863   /* PREFIX_VEX_0F383F */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5868   },
5869
5870   /* PREFIX_VEX_0F3840 */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { "vpmulld",        { XM, Vex, EXx }, 0 },
5875   },
5876
5877   /* PREFIX_VEX_0F3841 */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5882   },
5883
5884   /* PREFIX_VEX_0F3845 */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5889   },
5890
5891   /* PREFIX_VEX_0F3846 */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F3847 */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5903   },
5904
5905   /* PREFIX_VEX_0F3858 */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5910   },
5911
5912   /* PREFIX_VEX_0F3859 */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5917   },
5918
5919   /* PREFIX_VEX_0F385A */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5924   },
5925
5926   /* PREFIX_VEX_0F3878 */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5931   },
5932
5933   /* PREFIX_VEX_0F3879 */
5934   {
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5938   },
5939
5940   /* PREFIX_VEX_0F388C */
5941   {
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5945   },
5946
5947   /* PREFIX_VEX_0F388E */
5948   {
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5952   },
5953
5954   /* PREFIX_VEX_0F3890 */
5955   {
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5959   },
5960
5961   /* PREFIX_VEX_0F3891 */
5962   {
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5966   },
5967
5968   /* PREFIX_VEX_0F3892 */
5969   {
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5973   },
5974
5975   /* PREFIX_VEX_0F3893 */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5980   },
5981
5982   /* PREFIX_VEX_0F3896 */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5987   },
5988
5989   /* PREFIX_VEX_0F3897 */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5994   },
5995
5996   /* PREFIX_VEX_0F3898 */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6001   },
6002
6003   /* PREFIX_VEX_0F3899 */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6008   },
6009
6010   /* PREFIX_VEX_0F389A */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6015   },
6016
6017   /* PREFIX_VEX_0F389B */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6022   },
6023
6024   /* PREFIX_VEX_0F389C */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6029   },
6030
6031   /* PREFIX_VEX_0F389D */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6036   },
6037
6038   /* PREFIX_VEX_0F389E */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6043   },
6044
6045   /* PREFIX_VEX_0F389F */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6050   },
6051
6052   /* PREFIX_VEX_0F38A6 */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6057     { Bad_Opcode },
6058   },
6059
6060   /* PREFIX_VEX_0F38A7 */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F38A8 */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F38A9 */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6079   },
6080
6081   /* PREFIX_VEX_0F38AA */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F38AB */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6093   },
6094
6095   /* PREFIX_VEX_0F38AC */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6100   },
6101
6102   /* PREFIX_VEX_0F38AD */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6107   },
6108
6109   /* PREFIX_VEX_0F38AE */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6114   },
6115
6116   /* PREFIX_VEX_0F38AF */
6117   {
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6121   },
6122
6123   /* PREFIX_VEX_0F38B6 */
6124   {
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6128   },
6129
6130   /* PREFIX_VEX_0F38B7 */
6131   {
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6135   },
6136
6137   /* PREFIX_VEX_0F38B8 */
6138   {
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6142   },
6143
6144   /* PREFIX_VEX_0F38B9 */
6145   {
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6149   },
6150
6151   /* PREFIX_VEX_0F38BA */
6152   {
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6156   },
6157
6158   /* PREFIX_VEX_0F38BB */
6159   {
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6163   },
6164
6165   /* PREFIX_VEX_0F38BC */
6166   {
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6170   },
6171
6172   /* PREFIX_VEX_0F38BD */
6173   {
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6177   },
6178
6179   /* PREFIX_VEX_0F38BE */
6180   {
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6184   },
6185
6186   /* PREFIX_VEX_0F38BF */
6187   {
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6191   },
6192
6193   /* PREFIX_VEX_0F38CF */
6194   {
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6198   },
6199
6200   /* PREFIX_VEX_0F38DB */
6201   {
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6205   },
6206
6207   /* PREFIX_VEX_0F38DC */
6208   {
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { "vaesenc",        { XM, Vex, EXx }, 0 },
6212   },
6213
6214   /* PREFIX_VEX_0F38DD */
6215   {
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6219   },
6220
6221   /* PREFIX_VEX_0F38DE */
6222   {
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { "vaesdec",        { XM, Vex, EXx }, 0 },
6226   },
6227
6228   /* PREFIX_VEX_0F38DF */
6229   {
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6233   },
6234
6235   /* PREFIX_VEX_0F38F2 */
6236   {
6237     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6238   },
6239
6240   /* PREFIX_VEX_0F38F3_REG_1 */
6241   {
6242     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6243   },
6244
6245   /* PREFIX_VEX_0F38F3_REG_2 */
6246   {
6247     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6248   },
6249
6250   /* PREFIX_VEX_0F38F3_REG_3 */
6251   {
6252     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6253   },
6254
6255   /* PREFIX_VEX_0F38F5 */
6256   {
6257     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6258     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6259     { Bad_Opcode },
6260     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6261   },
6262
6263   /* PREFIX_VEX_0F38F6 */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6269   },
6270
6271   /* PREFIX_VEX_0F38F7 */
6272   {
6273     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6274     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6275     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6276     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6277   },
6278
6279   /* PREFIX_VEX_0F3A00 */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6284   },
6285
6286   /* PREFIX_VEX_0F3A01 */
6287   {
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6291   },
6292
6293   /* PREFIX_VEX_0F3A02 */
6294   {
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6298   },
6299
6300   /* PREFIX_VEX_0F3A04 */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6305   },
6306
6307   /* PREFIX_VEX_0F3A05 */
6308   {
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6312   },
6313
6314   /* PREFIX_VEX_0F3A06 */
6315   {
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6319   },
6320
6321   /* PREFIX_VEX_0F3A08 */
6322   {
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { "vroundps",       { XM, EXx, Ib }, 0 },
6326   },
6327
6328   /* PREFIX_VEX_0F3A09 */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { "vroundpd",       { XM, EXx, Ib }, 0 },
6333   },
6334
6335   /* PREFIX_VEX_0F3A0A */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6340   },
6341
6342   /* PREFIX_VEX_0F3A0B */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6347   },
6348
6349   /* PREFIX_VEX_0F3A0C */
6350   {
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6354   },
6355
6356   /* PREFIX_VEX_0F3A0D */
6357   {
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6361   },
6362
6363   /* PREFIX_VEX_0F3A0E */
6364   {
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6368   },
6369
6370   /* PREFIX_VEX_0F3A0F */
6371   {
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6375   },
6376
6377   /* PREFIX_VEX_0F3A14 */
6378   {
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6382   },
6383
6384   /* PREFIX_VEX_0F3A15 */
6385   {
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6389   },
6390
6391   /* PREFIX_VEX_0F3A16 */
6392   {
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6396   },
6397
6398   /* PREFIX_VEX_0F3A17 */
6399   {
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6403   },
6404
6405   /* PREFIX_VEX_0F3A18 */
6406   {
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6410   },
6411
6412   /* PREFIX_VEX_0F3A19 */
6413   {
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6417   },
6418
6419   /* PREFIX_VEX_0F3A1D */
6420   {
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6424   },
6425
6426   /* PREFIX_VEX_0F3A20 */
6427   {
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6431   },
6432
6433   /* PREFIX_VEX_0F3A21 */
6434   {
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6438   },
6439
6440   /* PREFIX_VEX_0F3A22 */
6441   {
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6445   },
6446
6447   /* PREFIX_VEX_0F3A30 */
6448   {
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6452   },
6453
6454   /* PREFIX_VEX_0F3A31 */
6455   {
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6459   },
6460
6461   /* PREFIX_VEX_0F3A32 */
6462   {
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6466   },
6467
6468   /* PREFIX_VEX_0F3A33 */
6469   {
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6473   },
6474
6475   /* PREFIX_VEX_0F3A38 */
6476   {
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6480   },
6481
6482   /* PREFIX_VEX_0F3A39 */
6483   {
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6487   },
6488
6489   /* PREFIX_VEX_0F3A40 */
6490   {
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6494   },
6495
6496   /* PREFIX_VEX_0F3A41 */
6497   {
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6501   },
6502
6503   /* PREFIX_VEX_0F3A42 */
6504   {
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6508   },
6509
6510   /* PREFIX_VEX_0F3A44 */
6511   {
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6515   },
6516
6517   /* PREFIX_VEX_0F3A46 */
6518   {
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6522   },
6523
6524   /* PREFIX_VEX_0F3A48 */
6525   {
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6529   },
6530
6531   /* PREFIX_VEX_0F3A49 */
6532   {
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6536   },
6537
6538   /* PREFIX_VEX_0F3A4A */
6539   {
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6543   },
6544
6545   /* PREFIX_VEX_0F3A4B */
6546   {
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6550   },
6551
6552   /* PREFIX_VEX_0F3A4C */
6553   {
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6557   },
6558
6559   /* PREFIX_VEX_0F3A5C */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6564   },
6565
6566   /* PREFIX_VEX_0F3A5D */
6567   {
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6571   },
6572
6573   /* PREFIX_VEX_0F3A5E */
6574   {
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6578   },
6579
6580   /* PREFIX_VEX_0F3A5F */
6581   {
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6585   },
6586
6587   /* PREFIX_VEX_0F3A60 */
6588   {
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6592     { Bad_Opcode },
6593   },
6594
6595   /* PREFIX_VEX_0F3A61 */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6600   },
6601
6602   /* PREFIX_VEX_0F3A62 */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6607   },
6608
6609   /* PREFIX_VEX_0F3A63 */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6614   },
6615
6616   /* PREFIX_VEX_0F3A68 */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6621   },
6622
6623   /* PREFIX_VEX_0F3A69 */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6628   },
6629
6630   /* PREFIX_VEX_0F3A6A */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6635   },
6636
6637   /* PREFIX_VEX_0F3A6B */
6638   {
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6642   },
6643
6644   /* PREFIX_VEX_0F3A6C */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6649   },
6650
6651   /* PREFIX_VEX_0F3A6D */
6652   {
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6656   },
6657
6658   /* PREFIX_VEX_0F3A6E */
6659   {
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6663   },
6664
6665   /* PREFIX_VEX_0F3A6F */
6666   {
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6670   },
6671
6672   /* PREFIX_VEX_0F3A78 */
6673   {
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6677   },
6678
6679   /* PREFIX_VEX_0F3A79 */
6680   {
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6684   },
6685
6686   /* PREFIX_VEX_0F3A7A */
6687   {
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6691   },
6692
6693   /* PREFIX_VEX_0F3A7B */
6694   {
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6698   },
6699
6700   /* PREFIX_VEX_0F3A7C */
6701   {
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6705     { Bad_Opcode },
6706   },
6707
6708   /* PREFIX_VEX_0F3A7D */
6709   {
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6713   },
6714
6715   /* PREFIX_VEX_0F3A7E */
6716   {
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6720   },
6721
6722   /* PREFIX_VEX_0F3A7F */
6723   {
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6727   },
6728
6729   /* PREFIX_VEX_0F3ACE */
6730   {
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6734   },
6735
6736   /* PREFIX_VEX_0F3ACF */
6737   {
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6741   },
6742
6743   /* PREFIX_VEX_0F3ADF */
6744   {
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6748   },
6749
6750   /* PREFIX_VEX_0F3AF0 */
6751   {
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6756   },
6757
6758 #define NEED_PREFIX_TABLE
6759 #include "i386-dis-evex.h"
6760 #undef NEED_PREFIX_TABLE
6761 };
6762
6763 static const struct dis386 x86_64_table[][2] = {
6764   /* X86_64_06 */
6765   {
6766     { "pushP", { es }, 0 },
6767   },
6768
6769   /* X86_64_07 */
6770   {
6771     { "popP", { es }, 0 },
6772   },
6773
6774   /* X86_64_0D */
6775   {
6776     { "pushP", { cs }, 0 },
6777   },
6778
6779   /* X86_64_16 */
6780   {
6781     { "pushP", { ss }, 0 },
6782   },
6783
6784   /* X86_64_17 */
6785   {
6786     { "popP", { ss }, 0 },
6787   },
6788
6789   /* X86_64_1E */
6790   {
6791     { "pushP", { ds }, 0 },
6792   },
6793
6794   /* X86_64_1F */
6795   {
6796     { "popP", { ds }, 0 },
6797   },
6798
6799   /* X86_64_27 */
6800   {
6801     { "daa", { XX }, 0 },
6802   },
6803
6804   /* X86_64_2F */
6805   {
6806     { "das", { XX }, 0 },
6807   },
6808
6809   /* X86_64_37 */
6810   {
6811     { "aaa", { XX }, 0 },
6812   },
6813
6814   /* X86_64_3F */
6815   {
6816     { "aas", { XX }, 0 },
6817   },
6818
6819   /* X86_64_60 */
6820   {
6821     { "pushaP", { XX }, 0 },
6822   },
6823
6824   /* X86_64_61 */
6825   {
6826     { "popaP", { XX }, 0 },
6827   },
6828
6829   /* X86_64_62 */
6830   {
6831     { MOD_TABLE (MOD_62_32BIT) },
6832     { EVEX_TABLE (EVEX_0F) },
6833   },
6834
6835   /* X86_64_63 */
6836   {
6837     { "arpl", { Ew, Gw }, 0 },
6838     { "movs{lq|xd}", { Gv, Ed }, 0 },
6839   },
6840
6841   /* X86_64_6D */
6842   {
6843     { "ins{R|}", { Yzr, indirDX }, 0 },
6844     { "ins{G|}", { Yzr, indirDX }, 0 },
6845   },
6846
6847   /* X86_64_6F */
6848   {
6849     { "outs{R|}", { indirDXr, Xz }, 0 },
6850     { "outs{G|}", { indirDXr, Xz }, 0 },
6851   },
6852
6853   /* X86_64_82 */
6854   {
6855     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6856     { REG_TABLE (REG_80) },
6857   },
6858
6859   /* X86_64_9A */
6860   {
6861     { "Jcall{T|}", { Ap }, 0 },
6862   },
6863
6864   /* X86_64_C4 */
6865   {
6866     { MOD_TABLE (MOD_C4_32BIT) },
6867     { VEX_C4_TABLE (VEX_0F) },
6868   },
6869
6870   /* X86_64_C5 */
6871   {
6872     { MOD_TABLE (MOD_C5_32BIT) },
6873     { VEX_C5_TABLE (VEX_0F) },
6874   },
6875
6876   /* X86_64_CE */
6877   {
6878     { "into", { XX }, 0 },
6879   },
6880
6881   /* X86_64_D4 */
6882   {
6883     { "aam", { Ib }, 0 },
6884   },
6885
6886   /* X86_64_D5 */
6887   {
6888     { "aad", { Ib }, 0 },
6889   },
6890
6891   /* X86_64_E8 */
6892   {
6893     { "callP",          { Jv, BND }, 0 },
6894     { "call@",          { Jv, BND }, 0 }
6895   },
6896
6897   /* X86_64_E9 */
6898   {
6899     { "jmpP",           { Jv, BND }, 0 },
6900     { "jmp@",           { Jv, BND }, 0 }
6901   },
6902
6903   /* X86_64_EA */
6904   {
6905     { "Jjmp{T|}", { Ap }, 0 },
6906   },
6907
6908   /* X86_64_0F01_REG_0 */
6909   {
6910     { "sgdt{Q|IQ}", { M }, 0 },
6911     { "sgdt", { M }, 0 },
6912   },
6913
6914   /* X86_64_0F01_REG_1 */
6915   {
6916     { "sidt{Q|IQ}", { M }, 0 },
6917     { "sidt", { M }, 0 },
6918   },
6919
6920   /* X86_64_0F01_REG_2 */
6921   {
6922     { "lgdt{Q|Q}", { M }, 0 },
6923     { "lgdt", { M }, 0 },
6924   },
6925
6926   /* X86_64_0F01_REG_3 */
6927   {
6928     { "lidt{Q|Q}", { M }, 0 },
6929     { "lidt", { M }, 0 },
6930   },
6931 };
6932
6933 static const struct dis386 three_byte_table[][256] = {
6934
6935   /* THREE_BYTE_0F38 */
6936   {
6937     /* 00 */
6938     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6939     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6940     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6941     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6942     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6943     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6944     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6945     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6946     /* 08 */
6947     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6948     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6949     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6950     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     /* 10 */
6956     { PREFIX_TABLE (PREFIX_0F3810) },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { PREFIX_TABLE (PREFIX_0F3814) },
6961     { PREFIX_TABLE (PREFIX_0F3815) },
6962     { Bad_Opcode },
6963     { PREFIX_TABLE (PREFIX_0F3817) },
6964     /* 18 */
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6970     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6971     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6972     { Bad_Opcode },
6973     /* 20 */
6974     { PREFIX_TABLE (PREFIX_0F3820) },
6975     { PREFIX_TABLE (PREFIX_0F3821) },
6976     { PREFIX_TABLE (PREFIX_0F3822) },
6977     { PREFIX_TABLE (PREFIX_0F3823) },
6978     { PREFIX_TABLE (PREFIX_0F3824) },
6979     { PREFIX_TABLE (PREFIX_0F3825) },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     /* 28 */
6983     { PREFIX_TABLE (PREFIX_0F3828) },
6984     { PREFIX_TABLE (PREFIX_0F3829) },
6985     { PREFIX_TABLE (PREFIX_0F382A) },
6986     { PREFIX_TABLE (PREFIX_0F382B) },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     /* 30 */
6992     { PREFIX_TABLE (PREFIX_0F3830) },
6993     { PREFIX_TABLE (PREFIX_0F3831) },
6994     { PREFIX_TABLE (PREFIX_0F3832) },
6995     { PREFIX_TABLE (PREFIX_0F3833) },
6996     { PREFIX_TABLE (PREFIX_0F3834) },
6997     { PREFIX_TABLE (PREFIX_0F3835) },
6998     { Bad_Opcode },
6999     { PREFIX_TABLE (PREFIX_0F3837) },
7000     /* 38 */
7001     { PREFIX_TABLE (PREFIX_0F3838) },
7002     { PREFIX_TABLE (PREFIX_0F3839) },
7003     { PREFIX_TABLE (PREFIX_0F383A) },
7004     { PREFIX_TABLE (PREFIX_0F383B) },
7005     { PREFIX_TABLE (PREFIX_0F383C) },
7006     { PREFIX_TABLE (PREFIX_0F383D) },
7007     { PREFIX_TABLE (PREFIX_0F383E) },
7008     { PREFIX_TABLE (PREFIX_0F383F) },
7009     /* 40 */
7010     { PREFIX_TABLE (PREFIX_0F3840) },
7011     { PREFIX_TABLE (PREFIX_0F3841) },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     /* 48 */
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     /* 50 */
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     /* 58 */
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     /* 60 */
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     /* 68 */
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     /* 70 */
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     /* 78 */
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     /* 80 */
7082     { PREFIX_TABLE (PREFIX_0F3880) },
7083     { PREFIX_TABLE (PREFIX_0F3881) },
7084     { PREFIX_TABLE (PREFIX_0F3882) },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     /* 88 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* 90 */
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     /* 98 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     /* a0 */
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* a8 */
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* b0 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* b8 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* c0 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* c8 */
7163     { PREFIX_TABLE (PREFIX_0F38C8) },
7164     { PREFIX_TABLE (PREFIX_0F38C9) },
7165     { PREFIX_TABLE (PREFIX_0F38CA) },
7166     { PREFIX_TABLE (PREFIX_0F38CB) },
7167     { PREFIX_TABLE (PREFIX_0F38CC) },
7168     { PREFIX_TABLE (PREFIX_0F38CD) },
7169     { Bad_Opcode },
7170     { PREFIX_TABLE (PREFIX_0F38CF) },
7171     /* d0 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* d8 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { PREFIX_TABLE (PREFIX_0F38DB) },
7185     { PREFIX_TABLE (PREFIX_0F38DC) },
7186     { PREFIX_TABLE (PREFIX_0F38DD) },
7187     { PREFIX_TABLE (PREFIX_0F38DE) },
7188     { PREFIX_TABLE (PREFIX_0F38DF) },
7189     /* e0 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* e8 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* f0 */
7208     { PREFIX_TABLE (PREFIX_0F38F0) },
7209     { PREFIX_TABLE (PREFIX_0F38F1) },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { PREFIX_TABLE (PREFIX_0F38F5) },
7214     { PREFIX_TABLE (PREFIX_0F38F6) },
7215     { Bad_Opcode },
7216     /* f8 */
7217     { PREFIX_TABLE (PREFIX_0F38F8) },
7218     { PREFIX_TABLE (PREFIX_0F38F9) },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225   },
7226   /* THREE_BYTE_0F3A */
7227   {
7228     /* 00 */
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     /* 08 */
7238     { PREFIX_TABLE (PREFIX_0F3A08) },
7239     { PREFIX_TABLE (PREFIX_0F3A09) },
7240     { PREFIX_TABLE (PREFIX_0F3A0A) },
7241     { PREFIX_TABLE (PREFIX_0F3A0B) },
7242     { PREFIX_TABLE (PREFIX_0F3A0C) },
7243     { PREFIX_TABLE (PREFIX_0F3A0D) },
7244     { PREFIX_TABLE (PREFIX_0F3A0E) },
7245     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7246     /* 10 */
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { PREFIX_TABLE (PREFIX_0F3A14) },
7252     { PREFIX_TABLE (PREFIX_0F3A15) },
7253     { PREFIX_TABLE (PREFIX_0F3A16) },
7254     { PREFIX_TABLE (PREFIX_0F3A17) },
7255     /* 18 */
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     /* 20 */
7265     { PREFIX_TABLE (PREFIX_0F3A20) },
7266     { PREFIX_TABLE (PREFIX_0F3A21) },
7267     { PREFIX_TABLE (PREFIX_0F3A22) },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     /* 28 */
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     /* 30 */
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     /* 38 */
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     /* 40 */
7301     { PREFIX_TABLE (PREFIX_0F3A40) },
7302     { PREFIX_TABLE (PREFIX_0F3A41) },
7303     { PREFIX_TABLE (PREFIX_0F3A42) },
7304     { Bad_Opcode },
7305     { PREFIX_TABLE (PREFIX_0F3A44) },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     /* 48 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     /* 50 */
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 58 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 60 */
7337     { PREFIX_TABLE (PREFIX_0F3A60) },
7338     { PREFIX_TABLE (PREFIX_0F3A61) },
7339     { PREFIX_TABLE (PREFIX_0F3A62) },
7340     { PREFIX_TABLE (PREFIX_0F3A63) },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 68 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* 70 */
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* 78 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     /* 80 */
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* 88 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* 90 */
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     /* 98 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* a0 */
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     /* a8 */
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     /* b0 */
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     /* b8 */
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     /* c0 */
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     /* c8 */
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { PREFIX_TABLE (PREFIX_0F3ACC) },
7459     { Bad_Opcode },
7460     { PREFIX_TABLE (PREFIX_0F3ACE) },
7461     { PREFIX_TABLE (PREFIX_0F3ACF) },
7462     /* d0 */
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     /* d8 */
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { PREFIX_TABLE (PREFIX_0F3ADF) },
7480     /* e0 */
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     /* e8 */
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     /* f0 */
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     /* f8 */
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516   },
7517 };
7518
7519 static const struct dis386 xop_table[][256] = {
7520   /* XOP_08 */
7521   {
7522     /* 00 */
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     /* 08 */
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     /* 10 */
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     /* 18 */
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     /* 20 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     /* 28 */
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     /* 30 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     /* 38 */
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* 40 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* 48 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* 50 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* 58 */
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     /* 60 */
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     /* 68 */
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     /* 70 */
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     /* 78 */
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     /* 80 */
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7673     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7674     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7675     /* 88 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7683     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7684     /* 90 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7691     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7692     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7693     /* 98 */
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7701     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7702     /* a0 */
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7706     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7710     { Bad_Opcode },
7711     /* a8 */
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     /* b0 */
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7728     { Bad_Opcode },
7729     /* b8 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     /* c0 */
7739     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7740     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7741     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7742     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     /* c8 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7753     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7754     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7755     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7756     /* d0 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     /* d8 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* e0 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* e8 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7790     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7791     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7792     /* f0 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* f8 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810   },
7811   /* XOP_09 */
7812   {
7813     /* 00 */
7814     { Bad_Opcode },
7815     { REG_TABLE (REG_XOP_TBM_01) },
7816     { REG_TABLE (REG_XOP_TBM_02) },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     /* 08 */
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     /* 10 */
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { REG_TABLE (REG_XOP_LWPCB) },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     /* 18 */
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     /* 20 */
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     /* 28 */
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     /* 30 */
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     /* 38 */
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     /* 40 */
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     /* 48 */
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     /* 50 */
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     /* 58 */
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     /* 60 */
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     /* 68 */
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     /* 70 */
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     /* 78 */
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     /* 80 */
7958     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7959     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7960     { "vfrczss",        { XM, EXd }, 0 },
7961     { "vfrczsd",        { XM, EXq }, 0 },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     /* 88 */
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     /* 90 */
7976     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7977     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7978     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7979     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7980     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7981     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7982     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7983     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7984     /* 98 */
7985     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7986     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7987     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7988     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     /* a0 */
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     /* a8 */
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     /* b0 */
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     /* b8 */
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     /* c0 */
8030     { Bad_Opcode },
8031     { "vphaddbw",       { XM, EXxmm }, 0 },
8032     { "vphaddbd",       { XM, EXxmm }, 0 },
8033     { "vphaddbq",       { XM, EXxmm }, 0 },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { "vphaddwd",       { XM, EXxmm }, 0 },
8037     { "vphaddwq",       { XM, EXxmm }, 0 },
8038     /* c8 */
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { "vphadddq",       { XM, EXxmm }, 0 },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* d0 */
8048     { Bad_Opcode },
8049     { "vphaddubw",      { XM, EXxmm }, 0 },
8050     { "vphaddubd",      { XM, EXxmm }, 0 },
8051     { "vphaddubq",      { XM, EXxmm }, 0 },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { "vphadduwd",      { XM, EXxmm }, 0 },
8055     { "vphadduwq",      { XM, EXxmm }, 0 },
8056     /* d8 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { "vphaddudq",      { XM, EXxmm }, 0 },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* e0 */
8066     { Bad_Opcode },
8067     { "vphsubbw",       { XM, EXxmm }, 0 },
8068     { "vphsubwd",       { XM, EXxmm }, 0 },
8069     { "vphsubdq",       { XM, EXxmm }, 0 },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     /* e8 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* f0 */
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     /* f8 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101   },
8102   /* XOP_0A */
8103   {
8104     /* 00 */
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     /* 08 */
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     /* 10 */
8123     { "bextr",  { Gv, Ev, Iq }, 0 },
8124     { Bad_Opcode },
8125     { REG_TABLE (REG_XOP_LWP) },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     /* 18 */
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     /* 20 */
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     /* 28 */
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     /* 30 */
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     /* 38 */
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     /* 40 */
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     /* 48 */
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     /* 50 */
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     /* 58 */
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     /* 60 */
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     /* 68 */
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     /* 70 */
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     /* 78 */
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     /* 80 */
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     /* 88 */
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     /* 90 */
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     /* 98 */
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     /* a0 */
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     /* a8 */
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     /* b0 */
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     /* b8 */
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     /* c0 */
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     /* c8 */
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     /* d0 */
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     /* d8 */
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     /* e0 */
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     /* e8 */
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     /* f0 */
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     /* f8 */
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392   },
8393 };
8394
8395 static const struct dis386 vex_table[][256] = {
8396   /* VEX_0F */
8397   {
8398     /* 00 */
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     /* 08 */
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     /* 10 */
8417     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8418     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8419     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8420     { MOD_TABLE (MOD_VEX_0F13) },
8421     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8422     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8423     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8424     { MOD_TABLE (MOD_VEX_0F17) },
8425     /* 18 */
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     /* 20 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     /* 28 */
8444     { "vmovapX",        { XM, EXx }, 0 },
8445     { "vmovapX",        { EXxS, XM }, 0 },
8446     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8447     { MOD_TABLE (MOD_VEX_0F2B) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8449     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8450     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8451     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8452     /* 30 */
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     /* 38 */
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     /* 40 */
8471     { Bad_Opcode },
8472     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8473     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8474     { Bad_Opcode },
8475     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8476     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8477     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8478     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8479     /* 48 */
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     /* 50 */
8489     { MOD_TABLE (MOD_VEX_0F50) },
8490     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8491     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8492     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8493     { "vandpX",         { XM, Vex, EXx }, 0 },
8494     { "vandnpX",        { XM, Vex, EXx }, 0 },
8495     { "vorpX",          { XM, Vex, EXx }, 0 },
8496     { "vxorpX",         { XM, Vex, EXx }, 0 },
8497     /* 58 */
8498     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8499     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8500     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8501     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8502     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8506     /* 60 */
8507     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8509     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8510     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8515     /* 68 */
8516     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8524     /* 70 */
8525     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8526     { REG_TABLE (REG_VEX_0F71) },
8527     { REG_TABLE (REG_VEX_0F72) },
8528     { REG_TABLE (REG_VEX_0F73) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8533     /* 78 */
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8542     /* 80 */
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     /* 88 */
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     /* 90 */
8561     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     /* 98 */
8570     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     /* a0 */
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     /* a8 */
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { REG_TABLE (REG_VEX_0FAE) },
8595     { Bad_Opcode },
8596     /* b0 */
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     /* b8 */
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     /* c0 */
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8618     { Bad_Opcode },
8619     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8620     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8621     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8622     { Bad_Opcode },
8623     /* c8 */
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     /* d0 */
8633     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8634     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8635     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8636     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8637     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8638     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8639     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8640     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8641     /* d8 */
8642     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8643     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8644     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8645     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8646     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8647     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8648     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8649     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8650     /* e0 */
8651     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8652     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8653     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8654     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8659     /* e8 */
8660     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8662     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8663     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8664     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8668     /* f0 */
8669     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8677     /* f8 */
8678     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8685     { Bad_Opcode },
8686   },
8687   /* VEX_0F38 */
8688   {
8689     /* 00 */
8690     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8698     /* 08 */
8699     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8707     /* 10 */
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8716     /* 18 */
8717     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8720     { Bad_Opcode },
8721     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8724     { Bad_Opcode },
8725     /* 20 */
8726     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     /* 28 */
8735     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8743     /* 30 */
8744     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8752     /* 38 */
8753     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8761     /* 40 */
8762     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8770     /* 48 */
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     /* 50 */
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     /* 58 */
8789     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     /* 60 */
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     /* 68 */
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     /* 70 */
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     /* 78 */
8825     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     /* 80 */
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     /* 88 */
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8848     { Bad_Opcode },
8849     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8850     { Bad_Opcode },
8851     /* 90 */
8852     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8854     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8860     /* 98 */
8861     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8863     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8864     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8865     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8869     /* a0 */
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8878     /* a8 */
8879     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8887     /* b0 */
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8896     /* b8 */
8897     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8905     /* c0 */
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     /* c8 */
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8923     /* d0 */
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     /* d8 */
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8941     /* e0 */
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     /* e8 */
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     /* f0 */
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8963     { REG_TABLE (REG_VEX_0F38F3) },
8964     { Bad_Opcode },
8965     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8968     /* f8 */
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977   },
8978   /* VEX_0F3A */
8979   {
8980     /* 00 */
8981     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8984     { Bad_Opcode },
8985     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8988     { Bad_Opcode },
8989     /* 08 */
8990     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8998     /* 10 */
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9007     /* 18 */
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     /* 20 */
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     /* 28 */
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     /* 30 */
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     /* 38 */
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     /* 40 */
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9056     { Bad_Opcode },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9058     { Bad_Opcode },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9060     { Bad_Opcode },
9061     /* 48 */
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     /* 50 */
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     /* 58 */
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9088     /* 60 */
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     /* 68 */
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9106     /* 70 */
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     /* 78 */
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9124     /* 80 */
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     /* 88 */
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     /* 90 */
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     /* 98 */
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     /* a0 */
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     /* a8 */
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     /* b0 */
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     /* b8 */
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     /* c0 */
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     /* c8 */
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9213     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9214     /* d0 */
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     /* d8 */
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9232     /* e0 */
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     /* e8 */
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     /* f0 */
9251     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     /* f8 */
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268   },
9269 };
9270
9271 #define NEED_OPCODE_TABLE
9272 #include "i386-dis-evex.h"
9273 #undef NEED_OPCODE_TABLE
9274 static const struct dis386 vex_len_table[][2] = {
9275   /* VEX_LEN_0F12_P_0_M_0 */
9276   {
9277     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9278   },
9279
9280   /* VEX_LEN_0F12_P_0_M_1 */
9281   {
9282     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9283   },
9284
9285   /* VEX_LEN_0F12_P_2 */
9286   {
9287     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9288   },
9289
9290   /* VEX_LEN_0F13_M_0 */
9291   {
9292     { "vmovlpX",        { EXq, XM }, 0 },
9293   },
9294
9295   /* VEX_LEN_0F16_P_0_M_0 */
9296   {
9297     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9298   },
9299
9300   /* VEX_LEN_0F16_P_0_M_1 */
9301   {
9302     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9303   },
9304
9305   /* VEX_LEN_0F16_P_2 */
9306   {
9307     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9308   },
9309
9310   /* VEX_LEN_0F17_M_0 */
9311   {
9312     { "vmovhpX",        { EXq, XM }, 0 },
9313   },
9314
9315   /* VEX_LEN_0F2A_P_1 */
9316   {
9317     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9318     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9319   },
9320
9321   /* VEX_LEN_0F2A_P_3 */
9322   {
9323     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9324     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9325   },
9326
9327   /* VEX_LEN_0F2C_P_1 */
9328   {
9329     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9330     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9331   },
9332
9333   /* VEX_LEN_0F2C_P_3 */
9334   {
9335     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9336     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9337   },
9338
9339   /* VEX_LEN_0F2D_P_1 */
9340   {
9341     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9342     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9343   },
9344
9345   /* VEX_LEN_0F2D_P_3 */
9346   {
9347     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9348     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9349   },
9350
9351   /* VEX_LEN_0F41_P_0 */
9352   {
9353     { Bad_Opcode },
9354     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9355   },
9356   /* VEX_LEN_0F41_P_2 */
9357   {
9358     { Bad_Opcode },
9359     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9360   },
9361   /* VEX_LEN_0F42_P_0 */
9362   {
9363     { Bad_Opcode },
9364     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9365   },
9366   /* VEX_LEN_0F42_P_2 */
9367   {
9368     { Bad_Opcode },
9369     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9370   },
9371   /* VEX_LEN_0F44_P_0 */
9372   {
9373     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9374   },
9375   /* VEX_LEN_0F44_P_2 */
9376   {
9377     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9378   },
9379   /* VEX_LEN_0F45_P_0 */
9380   {
9381     { Bad_Opcode },
9382     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9383   },
9384   /* VEX_LEN_0F45_P_2 */
9385   {
9386     { Bad_Opcode },
9387     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9388   },
9389   /* VEX_LEN_0F46_P_0 */
9390   {
9391     { Bad_Opcode },
9392     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9393   },
9394   /* VEX_LEN_0F46_P_2 */
9395   {
9396     { Bad_Opcode },
9397     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9398   },
9399   /* VEX_LEN_0F47_P_0 */
9400   {
9401     { Bad_Opcode },
9402     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9403   },
9404   /* VEX_LEN_0F47_P_2 */
9405   {
9406     { Bad_Opcode },
9407     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9408   },
9409   /* VEX_LEN_0F4A_P_0 */
9410   {
9411     { Bad_Opcode },
9412     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9413   },
9414   /* VEX_LEN_0F4A_P_2 */
9415   {
9416     { Bad_Opcode },
9417     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9418   },
9419   /* VEX_LEN_0F4B_P_0 */
9420   {
9421     { Bad_Opcode },
9422     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9423   },
9424   /* VEX_LEN_0F4B_P_2 */
9425   {
9426     { Bad_Opcode },
9427     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9428   },
9429
9430   /* VEX_LEN_0F6E_P_2 */
9431   {
9432     { "vmovK",          { XMScalar, Edq }, 0 },
9433   },
9434
9435   /* VEX_LEN_0F77_P_1 */
9436   {
9437     { "vzeroupper",     { XX }, 0 },
9438     { "vzeroall",       { XX }, 0 },
9439   },
9440
9441   /* VEX_LEN_0F7E_P_1 */
9442   {
9443     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9444   },
9445
9446   /* VEX_LEN_0F7E_P_2 */
9447   {
9448     { "vmovK",          { Edq, XMScalar }, 0 },
9449   },
9450
9451   /* VEX_LEN_0F90_P_0 */
9452   {
9453     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9454   },
9455
9456   /* VEX_LEN_0F90_P_2 */
9457   {
9458     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9459   },
9460
9461   /* VEX_LEN_0F91_P_0 */
9462   {
9463     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9464   },
9465
9466   /* VEX_LEN_0F91_P_2 */
9467   {
9468     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9469   },
9470
9471   /* VEX_LEN_0F92_P_0 */
9472   {
9473     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9474   },
9475
9476   /* VEX_LEN_0F92_P_2 */
9477   {
9478     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9479   },
9480
9481   /* VEX_LEN_0F92_P_3 */
9482   {
9483     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9484   },
9485
9486   /* VEX_LEN_0F93_P_0 */
9487   {
9488     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9489   },
9490
9491   /* VEX_LEN_0F93_P_2 */
9492   {
9493     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9494   },
9495
9496   /* VEX_LEN_0F93_P_3 */
9497   {
9498     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9499   },
9500
9501   /* VEX_LEN_0F98_P_0 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9504   },
9505
9506   /* VEX_LEN_0F98_P_2 */
9507   {
9508     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9509   },
9510
9511   /* VEX_LEN_0F99_P_0 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9514   },
9515
9516   /* VEX_LEN_0F99_P_2 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9519   },
9520
9521   /* VEX_LEN_0FAE_R_2_M_0 */
9522   {
9523     { "vldmxcsr",       { Md }, 0 },
9524   },
9525
9526   /* VEX_LEN_0FAE_R_3_M_0 */
9527   {
9528     { "vstmxcsr",       { Md }, 0 },
9529   },
9530
9531   /* VEX_LEN_0FC4_P_2 */
9532   {
9533     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9534   },
9535
9536   /* VEX_LEN_0FC5_P_2 */
9537   {
9538     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9539   },
9540
9541   /* VEX_LEN_0FD6_P_2 */
9542   {
9543     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9544   },
9545
9546   /* VEX_LEN_0FF7_P_2 */
9547   {
9548     { "vmaskmovdqu",    { XM, XS }, 0 },
9549   },
9550
9551   /* VEX_LEN_0F3816_P_2 */
9552   {
9553     { Bad_Opcode },
9554     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9555   },
9556
9557   /* VEX_LEN_0F3819_P_2 */
9558   {
9559     { Bad_Opcode },
9560     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9561   },
9562
9563   /* VEX_LEN_0F381A_P_2_M_0 */
9564   {
9565     { Bad_Opcode },
9566     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9567   },
9568
9569   /* VEX_LEN_0F3836_P_2 */
9570   {
9571     { Bad_Opcode },
9572     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9573   },
9574
9575   /* VEX_LEN_0F3841_P_2 */
9576   {
9577     { "vphminposuw",    { XM, EXx }, 0 },
9578   },
9579
9580   /* VEX_LEN_0F385A_P_2_M_0 */
9581   {
9582     { Bad_Opcode },
9583     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9584   },
9585
9586   /* VEX_LEN_0F38DB_P_2 */
9587   {
9588     { "vaesimc",        { XM, EXx }, 0 },
9589   },
9590
9591   /* VEX_LEN_0F38F2_P_0 */
9592   {
9593     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9594   },
9595
9596   /* VEX_LEN_0F38F3_R_1_P_0 */
9597   {
9598     { "blsrS",          { VexGdq, Edq }, 0 },
9599   },
9600
9601   /* VEX_LEN_0F38F3_R_2_P_0 */
9602   {
9603     { "blsmskS",        { VexGdq, Edq }, 0 },
9604   },
9605
9606   /* VEX_LEN_0F38F3_R_3_P_0 */
9607   {
9608     { "blsiS",          { VexGdq, Edq }, 0 },
9609   },
9610
9611   /* VEX_LEN_0F38F5_P_0 */
9612   {
9613     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9614   },
9615
9616   /* VEX_LEN_0F38F5_P_1 */
9617   {
9618     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9619   },
9620
9621   /* VEX_LEN_0F38F5_P_3 */
9622   {
9623     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9624   },
9625
9626   /* VEX_LEN_0F38F6_P_3 */
9627   {
9628     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9629   },
9630
9631   /* VEX_LEN_0F38F7_P_0 */
9632   {
9633     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9634   },
9635
9636   /* VEX_LEN_0F38F7_P_1 */
9637   {
9638     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9639   },
9640
9641   /* VEX_LEN_0F38F7_P_2 */
9642   {
9643     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9644   },
9645
9646   /* VEX_LEN_0F38F7_P_3 */
9647   {
9648     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9649   },
9650
9651   /* VEX_LEN_0F3A00_P_2 */
9652   {
9653     { Bad_Opcode },
9654     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9655   },
9656
9657   /* VEX_LEN_0F3A01_P_2 */
9658   {
9659     { Bad_Opcode },
9660     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9661   },
9662
9663   /* VEX_LEN_0F3A06_P_2 */
9664   {
9665     { Bad_Opcode },
9666     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9667   },
9668
9669   /* VEX_LEN_0F3A14_P_2 */
9670   {
9671     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9672   },
9673
9674   /* VEX_LEN_0F3A15_P_2 */
9675   {
9676     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9677   },
9678
9679   /* VEX_LEN_0F3A16_P_2  */
9680   {
9681     { "vpextrK",        { Edq, XM, Ib }, 0 },
9682   },
9683
9684   /* VEX_LEN_0F3A17_P_2 */
9685   {
9686     { "vextractps",     { Edqd, XM, Ib }, 0 },
9687   },
9688
9689   /* VEX_LEN_0F3A18_P_2 */
9690   {
9691     { Bad_Opcode },
9692     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9693   },
9694
9695   /* VEX_LEN_0F3A19_P_2 */
9696   {
9697     { Bad_Opcode },
9698     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9699   },
9700
9701   /* VEX_LEN_0F3A20_P_2 */
9702   {
9703     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9704   },
9705
9706   /* VEX_LEN_0F3A21_P_2 */
9707   {
9708     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9709   },
9710
9711   /* VEX_LEN_0F3A22_P_2 */
9712   {
9713     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9714   },
9715
9716   /* VEX_LEN_0F3A30_P_2 */
9717   {
9718     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9719   },
9720
9721   /* VEX_LEN_0F3A31_P_2 */
9722   {
9723     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9724   },
9725
9726   /* VEX_LEN_0F3A32_P_2 */
9727   {
9728     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9729   },
9730
9731   /* VEX_LEN_0F3A33_P_2 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9734   },
9735
9736   /* VEX_LEN_0F3A38_P_2 */
9737   {
9738     { Bad_Opcode },
9739     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9740   },
9741
9742   /* VEX_LEN_0F3A39_P_2 */
9743   {
9744     { Bad_Opcode },
9745     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9746   },
9747
9748   /* VEX_LEN_0F3A41_P_2 */
9749   {
9750     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9751   },
9752
9753   /* VEX_LEN_0F3A46_P_2 */
9754   {
9755     { Bad_Opcode },
9756     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9757   },
9758
9759   /* VEX_LEN_0F3A60_P_2 */
9760   {
9761     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9762   },
9763
9764   /* VEX_LEN_0F3A61_P_2 */
9765   {
9766     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9767   },
9768
9769   /* VEX_LEN_0F3A62_P_2 */
9770   {
9771     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9772   },
9773
9774   /* VEX_LEN_0F3A63_P_2 */
9775   {
9776     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9777   },
9778
9779   /* VEX_LEN_0F3A6A_P_2 */
9780   {
9781     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9782   },
9783
9784   /* VEX_LEN_0F3A6B_P_2 */
9785   {
9786     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9787   },
9788
9789   /* VEX_LEN_0F3A6E_P_2 */
9790   {
9791     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9792   },
9793
9794   /* VEX_LEN_0F3A6F_P_2 */
9795   {
9796     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9797   },
9798
9799   /* VEX_LEN_0F3A7A_P_2 */
9800   {
9801     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9802   },
9803
9804   /* VEX_LEN_0F3A7B_P_2 */
9805   {
9806     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9807   },
9808
9809   /* VEX_LEN_0F3A7E_P_2 */
9810   {
9811     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9812   },
9813
9814   /* VEX_LEN_0F3A7F_P_2 */
9815   {
9816     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9817   },
9818
9819   /* VEX_LEN_0F3ADF_P_2 */
9820   {
9821     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9822   },
9823
9824   /* VEX_LEN_0F3AF0_P_3 */
9825   {
9826     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9827   },
9828
9829   /* VEX_LEN_0FXOP_08_CC */
9830   {
9831      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9832   },
9833
9834   /* VEX_LEN_0FXOP_08_CD */
9835   {
9836      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9837   },
9838
9839   /* VEX_LEN_0FXOP_08_CE */
9840   {
9841      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9842   },
9843
9844   /* VEX_LEN_0FXOP_08_CF */
9845   {
9846      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9847   },
9848
9849   /* VEX_LEN_0FXOP_08_EC */
9850   {
9851      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9852   },
9853
9854   /* VEX_LEN_0FXOP_08_ED */
9855   {
9856      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9857   },
9858
9859   /* VEX_LEN_0FXOP_08_EE */
9860   {
9861      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9862   },
9863
9864   /* VEX_LEN_0FXOP_08_EF */
9865   {
9866      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9867   },
9868
9869   /* VEX_LEN_0FXOP_09_80 */
9870   {
9871     { "vfrczps",        { XM, EXxmm }, 0 },
9872     { "vfrczps",        { XM, EXymmq }, 0 },
9873   },
9874
9875   /* VEX_LEN_0FXOP_09_81 */
9876   {
9877     { "vfrczpd",        { XM, EXxmm }, 0 },
9878     { "vfrczpd",        { XM, EXymmq }, 0 },
9879   },
9880 };
9881
9882 static const struct dis386 evex_len_table[][3] = {
9883 #define NEED_EVEX_LEN_TABLE
9884 #include "i386-dis-evex.h"
9885 #undef NEED_EVEX_LEN_TABLE
9886 };
9887
9888 static const struct dis386 vex_w_table[][2] = {
9889   {
9890     /* VEX_W_0F41_P_0_LEN_1 */
9891     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9892     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9893   },
9894   {
9895     /* VEX_W_0F41_P_2_LEN_1 */
9896     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9897     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9898   },
9899   {
9900     /* VEX_W_0F42_P_0_LEN_1 */
9901     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9902     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9903   },
9904   {
9905     /* VEX_W_0F42_P_2_LEN_1 */
9906     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9907     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9908   },
9909   {
9910     /* VEX_W_0F44_P_0_LEN_0 */
9911     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9912     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9913   },
9914   {
9915     /* VEX_W_0F44_P_2_LEN_0 */
9916     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9917     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9918   },
9919   {
9920     /* VEX_W_0F45_P_0_LEN_1 */
9921     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9922     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9923   },
9924   {
9925     /* VEX_W_0F45_P_2_LEN_1 */
9926     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9927     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9928   },
9929   {
9930     /* VEX_W_0F46_P_0_LEN_1 */
9931     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9932     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9933   },
9934   {
9935     /* VEX_W_0F46_P_2_LEN_1 */
9936     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9937     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9938   },
9939   {
9940     /* VEX_W_0F47_P_0_LEN_1 */
9941     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9942     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9943   },
9944   {
9945     /* VEX_W_0F47_P_2_LEN_1 */
9946     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9947     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9948   },
9949   {
9950     /* VEX_W_0F4A_P_0_LEN_1 */
9951     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9952     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9953   },
9954   {
9955     /* VEX_W_0F4A_P_2_LEN_1 */
9956     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9957     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9958   },
9959   {
9960     /* VEX_W_0F4B_P_0_LEN_1 */
9961     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9962     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9963   },
9964   {
9965     /* VEX_W_0F4B_P_2_LEN_1 */
9966     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9967   },
9968   {
9969     /* VEX_W_0F90_P_0_LEN_0 */
9970     { "kmovw",          { MaskG, MaskE }, 0 },
9971     { "kmovq",          { MaskG, MaskE }, 0 },
9972   },
9973   {
9974     /* VEX_W_0F90_P_2_LEN_0 */
9975     { "kmovb",          { MaskG, MaskBDE }, 0 },
9976     { "kmovd",          { MaskG, MaskBDE }, 0 },
9977   },
9978   {
9979     /* VEX_W_0F91_P_0_LEN_0 */
9980     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9981     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9982   },
9983   {
9984     /* VEX_W_0F91_P_2_LEN_0 */
9985     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9986     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9987   },
9988   {
9989     /* VEX_W_0F92_P_0_LEN_0 */
9990     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9991   },
9992   {
9993     /* VEX_W_0F92_P_2_LEN_0 */
9994     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9995   },
9996   {
9997     /* VEX_W_0F93_P_0_LEN_0 */
9998     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9999   },
10000   {
10001     /* VEX_W_0F93_P_2_LEN_0 */
10002     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10003   },
10004   {
10005     /* VEX_W_0F98_P_0_LEN_0 */
10006     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10007     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10008   },
10009   {
10010     /* VEX_W_0F98_P_2_LEN_0 */
10011     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10012     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10013   },
10014   {
10015     /* VEX_W_0F99_P_0_LEN_0 */
10016     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10017     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10018   },
10019   {
10020     /* VEX_W_0F99_P_2_LEN_0 */
10021     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10022     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10023   },
10024   {
10025     /* VEX_W_0F380C_P_2  */
10026     { "vpermilps",      { XM, Vex, EXx }, 0 },
10027   },
10028   {
10029     /* VEX_W_0F380D_P_2  */
10030     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10031   },
10032   {
10033     /* VEX_W_0F380E_P_2  */
10034     { "vtestps",        { XM, EXx }, 0 },
10035   },
10036   {
10037     /* VEX_W_0F380F_P_2  */
10038     { "vtestpd",        { XM, EXx }, 0 },
10039   },
10040   {
10041     /* VEX_W_0F3816_P_2  */
10042     { "vpermps",        { XM, Vex, EXx }, 0 },
10043   },
10044   {
10045     /* VEX_W_0F3818_P_2 */
10046     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10047   },
10048   {
10049     /* VEX_W_0F3819_P_2 */
10050     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10051   },
10052   {
10053     /* VEX_W_0F381A_P_2_M_0 */
10054     { "vbroadcastf128", { XM, Mxmm }, 0 },
10055   },
10056   {
10057     /* VEX_W_0F382C_P_2_M_0 */
10058     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10059   },
10060   {
10061     /* VEX_W_0F382D_P_2_M_0 */
10062     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10063   },
10064   {
10065     /* VEX_W_0F382E_P_2_M_0 */
10066     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10067   },
10068   {
10069     /* VEX_W_0F382F_P_2_M_0 */
10070     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10071   },
10072   {
10073     /* VEX_W_0F3836_P_2  */
10074     { "vpermd",         { XM, Vex, EXx }, 0 },
10075   },
10076   {
10077     /* VEX_W_0F3846_P_2 */
10078     { "vpsravd",        { XM, Vex, EXx }, 0 },
10079   },
10080   {
10081     /* VEX_W_0F3858_P_2 */
10082     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10083   },
10084   {
10085     /* VEX_W_0F3859_P_2 */
10086     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10087   },
10088   {
10089     /* VEX_W_0F385A_P_2_M_0 */
10090     { "vbroadcasti128", { XM, Mxmm }, 0 },
10091   },
10092   {
10093     /* VEX_W_0F3878_P_2 */
10094     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10095   },
10096   {
10097     /* VEX_W_0F3879_P_2 */
10098     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10099   },
10100   {
10101     /* VEX_W_0F38CF_P_2 */
10102     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10103   },
10104   {
10105     /* VEX_W_0F3A00_P_2 */
10106     { Bad_Opcode },
10107     { "vpermq",         { XM, EXx, Ib }, 0 },
10108   },
10109   {
10110     /* VEX_W_0F3A01_P_2 */
10111     { Bad_Opcode },
10112     { "vpermpd",        { XM, EXx, Ib }, 0 },
10113   },
10114   {
10115     /* VEX_W_0F3A02_P_2 */
10116     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10117   },
10118   {
10119     /* VEX_W_0F3A04_P_2 */
10120     { "vpermilps",      { XM, EXx, Ib }, 0 },
10121   },
10122   {
10123     /* VEX_W_0F3A05_P_2 */
10124     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10125   },
10126   {
10127     /* VEX_W_0F3A06_P_2 */
10128     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10129   },
10130   {
10131     /* VEX_W_0F3A18_P_2 */
10132     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10133   },
10134   {
10135     /* VEX_W_0F3A19_P_2 */
10136     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10137   },
10138   {
10139     /* VEX_W_0F3A30_P_2_LEN_0 */
10140     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10141     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10142   },
10143   {
10144     /* VEX_W_0F3A31_P_2_LEN_0 */
10145     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10146     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10147   },
10148   {
10149     /* VEX_W_0F3A32_P_2_LEN_0 */
10150     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10151     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10152   },
10153   {
10154     /* VEX_W_0F3A33_P_2_LEN_0 */
10155     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10156     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10157   },
10158   {
10159     /* VEX_W_0F3A38_P_2 */
10160     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10161   },
10162   {
10163     /* VEX_W_0F3A39_P_2 */
10164     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10165   },
10166   {
10167     /* VEX_W_0F3A46_P_2 */
10168     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10169   },
10170   {
10171     /* VEX_W_0F3A48_P_2 */
10172     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10173     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10174   },
10175   {
10176     /* VEX_W_0F3A49_P_2 */
10177     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10178     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10179   },
10180   {
10181     /* VEX_W_0F3A4A_P_2 */
10182     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10183   },
10184   {
10185     /* VEX_W_0F3A4B_P_2 */
10186     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10187   },
10188   {
10189     /* VEX_W_0F3A4C_P_2 */
10190     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10191   },
10192   {
10193     /* VEX_W_0F3ACE_P_2 */
10194     { Bad_Opcode },
10195     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10196   },
10197   {
10198     /* VEX_W_0F3ACF_P_2 */
10199     { Bad_Opcode },
10200     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10201   },
10202 #define NEED_VEX_W_TABLE
10203 #include "i386-dis-evex.h"
10204 #undef NEED_VEX_W_TABLE
10205 };
10206
10207 static const struct dis386 mod_table[][2] = {
10208   {
10209     /* MOD_8D */
10210     { "leaS",           { Gv, M }, 0 },
10211   },
10212   {
10213     /* MOD_C6_REG_7 */
10214     { Bad_Opcode },
10215     { RM_TABLE (RM_C6_REG_7) },
10216   },
10217   {
10218     /* MOD_C7_REG_7 */
10219     { Bad_Opcode },
10220     { RM_TABLE (RM_C7_REG_7) },
10221   },
10222   {
10223     /* MOD_FF_REG_3 */
10224     { "Jcall^", { indirEp }, 0 },
10225   },
10226   {
10227     /* MOD_FF_REG_5 */
10228     { "Jjmp^", { indirEp }, 0 },
10229   },
10230   {
10231     /* MOD_0F01_REG_0 */
10232     { X86_64_TABLE (X86_64_0F01_REG_0) },
10233     { RM_TABLE (RM_0F01_REG_0) },
10234   },
10235   {
10236     /* MOD_0F01_REG_1 */
10237     { X86_64_TABLE (X86_64_0F01_REG_1) },
10238     { RM_TABLE (RM_0F01_REG_1) },
10239   },
10240   {
10241     /* MOD_0F01_REG_2 */
10242     { X86_64_TABLE (X86_64_0F01_REG_2) },
10243     { RM_TABLE (RM_0F01_REG_2) },
10244   },
10245   {
10246     /* MOD_0F01_REG_3 */
10247     { X86_64_TABLE (X86_64_0F01_REG_3) },
10248     { RM_TABLE (RM_0F01_REG_3) },
10249   },
10250   {
10251     /* MOD_0F01_REG_5 */
10252     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10253     { RM_TABLE (RM_0F01_REG_5) },
10254   },
10255   {
10256     /* MOD_0F01_REG_7 */
10257     { "invlpg",         { Mb }, 0 },
10258     { RM_TABLE (RM_0F01_REG_7) },
10259   },
10260   {
10261     /* MOD_0F12_PREFIX_0 */
10262     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10263     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10264   },
10265   {
10266     /* MOD_0F13 */
10267     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10268   },
10269   {
10270     /* MOD_0F16_PREFIX_0 */
10271     { "movhps",         { XM, EXq }, 0 },
10272     { "movlhps",        { XM, EXq }, 0 },
10273   },
10274   {
10275     /* MOD_0F17 */
10276     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10277   },
10278   {
10279     /* MOD_0F18_REG_0 */
10280     { "prefetchnta",    { Mb }, 0 },
10281   },
10282   {
10283     /* MOD_0F18_REG_1 */
10284     { "prefetcht0",     { Mb }, 0 },
10285   },
10286   {
10287     /* MOD_0F18_REG_2 */
10288     { "prefetcht1",     { Mb }, 0 },
10289   },
10290   {
10291     /* MOD_0F18_REG_3 */
10292     { "prefetcht2",     { Mb }, 0 },
10293   },
10294   {
10295     /* MOD_0F18_REG_4 */
10296     { "nop/reserved",   { Mb }, 0 },
10297   },
10298   {
10299     /* MOD_0F18_REG_5 */
10300     { "nop/reserved",   { Mb }, 0 },
10301   },
10302   {
10303     /* MOD_0F18_REG_6 */
10304     { "nop/reserved",   { Mb }, 0 },
10305   },
10306   {
10307     /* MOD_0F18_REG_7 */
10308     { "nop/reserved",   { Mb }, 0 },
10309   },
10310   {
10311     /* MOD_0F1A_PREFIX_0 */
10312     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10313     { "nopQ",           { Ev }, 0 },
10314   },
10315   {
10316     /* MOD_0F1B_PREFIX_0 */
10317     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10318     { "nopQ",           { Ev }, 0 },
10319   },
10320   {
10321     /* MOD_0F1B_PREFIX_1 */
10322     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10323     { "nopQ",           { Ev }, 0 },
10324   },
10325   {
10326     /* MOD_0F1C_PREFIX_0 */
10327     { REG_TABLE (REG_0F1C_MOD_0) },
10328     { "nopQ",           { Ev }, 0 },
10329   },
10330   {
10331     /* MOD_0F1E_PREFIX_1 */
10332     { "nopQ",           { Ev }, 0 },
10333     { REG_TABLE (REG_0F1E_MOD_3) },
10334   },
10335   {
10336     /* MOD_0F24 */
10337     { Bad_Opcode },
10338     { "movL",           { Rd, Td }, 0 },
10339   },
10340   {
10341     /* MOD_0F26 */
10342     { Bad_Opcode },
10343     { "movL",           { Td, Rd }, 0 },
10344   },
10345   {
10346     /* MOD_0F2B_PREFIX_0 */
10347     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10348   },
10349   {
10350     /* MOD_0F2B_PREFIX_1 */
10351     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10352   },
10353   {
10354     /* MOD_0F2B_PREFIX_2 */
10355     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10356   },
10357   {
10358     /* MOD_0F2B_PREFIX_3 */
10359     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10360   },
10361   {
10362     /* MOD_0F51 */
10363     { Bad_Opcode },
10364     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10365   },
10366   {
10367     /* MOD_0F71_REG_2 */
10368     { Bad_Opcode },
10369     { "psrlw",          { MS, Ib }, 0 },
10370   },
10371   {
10372     /* MOD_0F71_REG_4 */
10373     { Bad_Opcode },
10374     { "psraw",          { MS, Ib }, 0 },
10375   },
10376   {
10377     /* MOD_0F71_REG_6 */
10378     { Bad_Opcode },
10379     { "psllw",          { MS, Ib }, 0 },
10380   },
10381   {
10382     /* MOD_0F72_REG_2 */
10383     { Bad_Opcode },
10384     { "psrld",          { MS, Ib }, 0 },
10385   },
10386   {
10387     /* MOD_0F72_REG_4 */
10388     { Bad_Opcode },
10389     { "psrad",          { MS, Ib }, 0 },
10390   },
10391   {
10392     /* MOD_0F72_REG_6 */
10393     { Bad_Opcode },
10394     { "pslld",          { MS, Ib }, 0 },
10395   },
10396   {
10397     /* MOD_0F73_REG_2 */
10398     { Bad_Opcode },
10399     { "psrlq",          { MS, Ib }, 0 },
10400   },
10401   {
10402     /* MOD_0F73_REG_3 */
10403     { Bad_Opcode },
10404     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10405   },
10406   {
10407     /* MOD_0F73_REG_6 */
10408     { Bad_Opcode },
10409     { "psllq",          { MS, Ib }, 0 },
10410   },
10411   {
10412     /* MOD_0F73_REG_7 */
10413     { Bad_Opcode },
10414     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10415   },
10416   {
10417     /* MOD_0FAE_REG_0 */
10418     { "fxsave",         { FXSAVE }, 0 },
10419     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10420   },
10421   {
10422     /* MOD_0FAE_REG_1 */
10423     { "fxrstor",        { FXSAVE }, 0 },
10424     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10425   },
10426   {
10427     /* MOD_0FAE_REG_2 */
10428     { "ldmxcsr",        { Md }, 0 },
10429     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10430   },
10431   {
10432     /* MOD_0FAE_REG_3 */
10433     { "stmxcsr",        { Md }, 0 },
10434     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10435   },
10436   {
10437     /* MOD_0FAE_REG_4 */
10438     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10439     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10440   },
10441   {
10442     /* MOD_0FAE_REG_5 */
10443     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10444     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10445   },
10446   {
10447     /* MOD_0FAE_REG_6 */
10448     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10449     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10450   },
10451   {
10452     /* MOD_0FAE_REG_7 */
10453     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10454     { RM_TABLE (RM_0FAE_REG_7) },
10455   },
10456   {
10457     /* MOD_0FB2 */
10458     { "lssS",           { Gv, Mp }, 0 },
10459   },
10460   {
10461     /* MOD_0FB4 */
10462     { "lfsS",           { Gv, Mp }, 0 },
10463   },
10464   {
10465     /* MOD_0FB5 */
10466     { "lgsS",           { Gv, Mp }, 0 },
10467   },
10468   {
10469     /* MOD_0FC3 */
10470     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10471   },
10472   {
10473     /* MOD_0FC7_REG_3 */
10474     { "xrstors",        { FXSAVE }, 0 },
10475   },
10476   {
10477     /* MOD_0FC7_REG_4 */
10478     { "xsavec",         { FXSAVE }, 0 },
10479   },
10480   {
10481     /* MOD_0FC7_REG_5 */
10482     { "xsaves",         { FXSAVE }, 0 },
10483   },
10484   {
10485     /* MOD_0FC7_REG_6 */
10486     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10487     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10488   },
10489   {
10490     /* MOD_0FC7_REG_7 */
10491     { "vmptrst",        { Mq }, 0 },
10492     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10493   },
10494   {
10495     /* MOD_0FD7 */
10496     { Bad_Opcode },
10497     { "pmovmskb",       { Gdq, MS }, 0 },
10498   },
10499   {
10500     /* MOD_0FE7_PREFIX_2 */
10501     { "movntdq",        { Mx, XM }, 0 },
10502   },
10503   {
10504     /* MOD_0FF0_PREFIX_3 */
10505     { "lddqu",          { XM, M }, 0 },
10506   },
10507   {
10508     /* MOD_0F382A_PREFIX_2 */
10509     { "movntdqa",       { XM, Mx }, 0 },
10510   },
10511   {
10512     /* MOD_0F38F5_PREFIX_2 */
10513     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10514   },
10515   {
10516     /* MOD_0F38F6_PREFIX_0 */
10517     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10518   },
10519   {
10520     /* MOD_0F38F8_PREFIX_2 */
10521     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10522   },
10523   {
10524     /* MOD_0F38F9_PREFIX_0 */
10525     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10526   },
10527   {
10528     /* MOD_62_32BIT */
10529     { "bound{S|}",      { Gv, Ma }, 0 },
10530     { EVEX_TABLE (EVEX_0F) },
10531   },
10532   {
10533     /* MOD_C4_32BIT */
10534     { "lesS",           { Gv, Mp }, 0 },
10535     { VEX_C4_TABLE (VEX_0F) },
10536   },
10537   {
10538     /* MOD_C5_32BIT */
10539     { "ldsS",           { Gv, Mp }, 0 },
10540     { VEX_C5_TABLE (VEX_0F) },
10541   },
10542   {
10543     /* MOD_VEX_0F12_PREFIX_0 */
10544     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10545     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10546   },
10547   {
10548     /* MOD_VEX_0F13 */
10549     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10550   },
10551   {
10552     /* MOD_VEX_0F16_PREFIX_0 */
10553     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10554     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10555   },
10556   {
10557     /* MOD_VEX_0F17 */
10558     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10559   },
10560   {
10561     /* MOD_VEX_0F2B */
10562     { "vmovntpX",       { Mx, XM }, 0 },
10563   },
10564   {
10565     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10566     { Bad_Opcode },
10567     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10568   },
10569   {
10570     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10571     { Bad_Opcode },
10572     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10573   },
10574   {
10575     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10576     { Bad_Opcode },
10577     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10578   },
10579   {
10580     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10581     { Bad_Opcode },
10582     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10583   },
10584   {
10585     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10586     { Bad_Opcode },
10587     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10588   },
10589   {
10590     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10591     { Bad_Opcode },
10592     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10593   },
10594   {
10595     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10596     { Bad_Opcode },
10597     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10598   },
10599   {
10600     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10601     { Bad_Opcode },
10602     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10603   },
10604   {
10605     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10606     { Bad_Opcode },
10607     { "knotw",          { MaskG, MaskR }, 0 },
10608   },
10609   {
10610     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10611     { Bad_Opcode },
10612     { "knotq",          { MaskG, MaskR }, 0 },
10613   },
10614   {
10615     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10616     { Bad_Opcode },
10617     { "knotb",          { MaskG, MaskR }, 0 },
10618   },
10619   {
10620     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10621     { Bad_Opcode },
10622     { "knotd",          { MaskG, MaskR }, 0 },
10623   },
10624   {
10625     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10626     { Bad_Opcode },
10627     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10628   },
10629   {
10630     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10631     { Bad_Opcode },
10632     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10633   },
10634   {
10635     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10636     { Bad_Opcode },
10637     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10638   },
10639   {
10640     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10641     { Bad_Opcode },
10642     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10643   },
10644  {
10645     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10646     { Bad_Opcode },
10647     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10648   },
10649   {
10650     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10651     { Bad_Opcode },
10652     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10653   },
10654   {
10655     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10656     { Bad_Opcode },
10657     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10658   },
10659   {
10660     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10661     { Bad_Opcode },
10662     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10663   },
10664   {
10665     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10666     { Bad_Opcode },
10667     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10668   },
10669   {
10670     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10671     { Bad_Opcode },
10672     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10673   },
10674   {
10675     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10676     { Bad_Opcode },
10677     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10678   },
10679   {
10680     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10681     { Bad_Opcode },
10682     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10683   },
10684   {
10685     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10686     { Bad_Opcode },
10687     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10688   },
10689   {
10690     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10691     { Bad_Opcode },
10692     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10693   },
10694   {
10695     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10696     { Bad_Opcode },
10697     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10698   },
10699   {
10700     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10701     { Bad_Opcode },
10702     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10703   },
10704   {
10705     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10706     { Bad_Opcode },
10707     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10708   },
10709   {
10710     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10711     { Bad_Opcode },
10712     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10713   },
10714   {
10715     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10716     { Bad_Opcode },
10717     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10718   },
10719   {
10720     /* MOD_VEX_0F50 */
10721     { Bad_Opcode },
10722     { "vmovmskpX",      { Gdq, XS }, 0 },
10723   },
10724   {
10725     /* MOD_VEX_0F71_REG_2 */
10726     { Bad_Opcode },
10727     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10728   },
10729   {
10730     /* MOD_VEX_0F71_REG_4 */
10731     { Bad_Opcode },
10732     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10733   },
10734   {
10735     /* MOD_VEX_0F71_REG_6 */
10736     { Bad_Opcode },
10737     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10738   },
10739   {
10740     /* MOD_VEX_0F72_REG_2 */
10741     { Bad_Opcode },
10742     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10743   },
10744   {
10745     /* MOD_VEX_0F72_REG_4 */
10746     { Bad_Opcode },
10747     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10748   },
10749   {
10750     /* MOD_VEX_0F72_REG_6 */
10751     { Bad_Opcode },
10752     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10753   },
10754   {
10755     /* MOD_VEX_0F73_REG_2 */
10756     { Bad_Opcode },
10757     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10758   },
10759   {
10760     /* MOD_VEX_0F73_REG_3 */
10761     { Bad_Opcode },
10762     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10763   },
10764   {
10765     /* MOD_VEX_0F73_REG_6 */
10766     { Bad_Opcode },
10767     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10768   },
10769   {
10770     /* MOD_VEX_0F73_REG_7 */
10771     { Bad_Opcode },
10772     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10773   },
10774   {
10775     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10776     { "kmovw",          { Ew, MaskG }, 0 },
10777     { Bad_Opcode },
10778   },
10779   {
10780     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10781     { "kmovq",          { Eq, MaskG }, 0 },
10782     { Bad_Opcode },
10783   },
10784   {
10785     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10786     { "kmovb",          { Eb, MaskG }, 0 },
10787     { Bad_Opcode },
10788   },
10789   {
10790     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10791     { "kmovd",          { Ed, MaskG }, 0 },
10792     { Bad_Opcode },
10793   },
10794   {
10795     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10796     { Bad_Opcode },
10797     { "kmovw",          { MaskG, Rdq }, 0 },
10798   },
10799   {
10800     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10801     { Bad_Opcode },
10802     { "kmovb",          { MaskG, Rdq }, 0 },
10803   },
10804   {
10805     /* MOD_VEX_0F92_P_3_LEN_0 */
10806     { Bad_Opcode },
10807     { "kmovK",          { MaskG, Rdq }, 0 },
10808   },
10809   {
10810     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10811     { Bad_Opcode },
10812     { "kmovw",          { Gdq, MaskR }, 0 },
10813   },
10814   {
10815     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10816     { Bad_Opcode },
10817     { "kmovb",          { Gdq, MaskR }, 0 },
10818   },
10819   {
10820     /* MOD_VEX_0F93_P_3_LEN_0 */
10821     { Bad_Opcode },
10822     { "kmovK",          { Gdq, MaskR }, 0 },
10823   },
10824   {
10825     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10826     { Bad_Opcode },
10827     { "kortestw", { MaskG, MaskR }, 0 },
10828   },
10829   {
10830     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10831     { Bad_Opcode },
10832     { "kortestq", { MaskG, MaskR }, 0 },
10833   },
10834   {
10835     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10836     { Bad_Opcode },
10837     { "kortestb", { MaskG, MaskR }, 0 },
10838   },
10839   {
10840     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10841     { Bad_Opcode },
10842     { "kortestd", { MaskG, MaskR }, 0 },
10843   },
10844   {
10845     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10846     { Bad_Opcode },
10847     { "ktestw", { MaskG, MaskR }, 0 },
10848   },
10849   {
10850     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10851     { Bad_Opcode },
10852     { "ktestq", { MaskG, MaskR }, 0 },
10853   },
10854   {
10855     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10856     { Bad_Opcode },
10857     { "ktestb", { MaskG, MaskR }, 0 },
10858   },
10859   {
10860     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10861     { Bad_Opcode },
10862     { "ktestd", { MaskG, MaskR }, 0 },
10863   },
10864   {
10865     /* MOD_VEX_0FAE_REG_2 */
10866     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10867   },
10868   {
10869     /* MOD_VEX_0FAE_REG_3 */
10870     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10871   },
10872   {
10873     /* MOD_VEX_0FD7_PREFIX_2 */
10874     { Bad_Opcode },
10875     { "vpmovmskb",      { Gdq, XS }, 0 },
10876   },
10877   {
10878     /* MOD_VEX_0FE7_PREFIX_2 */
10879     { "vmovntdq",       { Mx, XM }, 0 },
10880   },
10881   {
10882     /* MOD_VEX_0FF0_PREFIX_3 */
10883     { "vlddqu",         { XM, M }, 0 },
10884   },
10885   {
10886     /* MOD_VEX_0F381A_PREFIX_2 */
10887     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10888   },
10889   {
10890     /* MOD_VEX_0F382A_PREFIX_2 */
10891     { "vmovntdqa",      { XM, Mx }, 0 },
10892   },
10893   {
10894     /* MOD_VEX_0F382C_PREFIX_2 */
10895     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10896   },
10897   {
10898     /* MOD_VEX_0F382D_PREFIX_2 */
10899     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10900   },
10901   {
10902     /* MOD_VEX_0F382E_PREFIX_2 */
10903     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10904   },
10905   {
10906     /* MOD_VEX_0F382F_PREFIX_2 */
10907     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10908   },
10909   {
10910     /* MOD_VEX_0F385A_PREFIX_2 */
10911     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10912   },
10913   {
10914     /* MOD_VEX_0F388C_PREFIX_2 */
10915     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10916   },
10917   {
10918     /* MOD_VEX_0F388E_PREFIX_2 */
10919     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10920   },
10921   {
10922     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10923     { Bad_Opcode },
10924     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10925   },
10926   {
10927     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10928     { Bad_Opcode },
10929     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10930   },
10931   {
10932     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10933     { Bad_Opcode },
10934     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10935   },
10936   {
10937     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10938     { Bad_Opcode },
10939     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10940   },
10941   {
10942     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10943     { Bad_Opcode },
10944     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10945   },
10946   {
10947     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10948     { Bad_Opcode },
10949     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10950   },
10951   {
10952     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10953     { Bad_Opcode },
10954     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10955   },
10956   {
10957     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10958     { Bad_Opcode },
10959     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10960   },
10961 #define NEED_MOD_TABLE
10962 #include "i386-dis-evex.h"
10963 #undef NEED_MOD_TABLE
10964 };
10965
10966 static const struct dis386 rm_table[][8] = {
10967   {
10968     /* RM_C6_REG_7 */
10969     { "xabort",         { Skip_MODRM, Ib }, 0 },
10970   },
10971   {
10972     /* RM_C7_REG_7 */
10973     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10974   },
10975   {
10976     /* RM_0F01_REG_0 */
10977     { "enclv",          { Skip_MODRM }, 0 },
10978     { "vmcall",         { Skip_MODRM }, 0 },
10979     { "vmlaunch",       { Skip_MODRM }, 0 },
10980     { "vmresume",       { Skip_MODRM }, 0 },
10981     { "vmxoff",         { Skip_MODRM }, 0 },
10982     { "pconfig",        { Skip_MODRM }, 0 },
10983   },
10984   {
10985     /* RM_0F01_REG_1 */
10986     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10987     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10988     { "clac",           { Skip_MODRM }, 0 },
10989     { "stac",           { Skip_MODRM }, 0 },
10990     { Bad_Opcode },
10991     { Bad_Opcode },
10992     { Bad_Opcode },
10993     { "encls",          { Skip_MODRM }, 0 },
10994   },
10995   {
10996     /* RM_0F01_REG_2 */
10997     { "xgetbv",         { Skip_MODRM }, 0 },
10998     { "xsetbv",         { Skip_MODRM }, 0 },
10999     { Bad_Opcode },
11000     { Bad_Opcode },
11001     { "vmfunc",         { Skip_MODRM }, 0 },
11002     { "xend",           { Skip_MODRM }, 0 },
11003     { "xtest",          { Skip_MODRM }, 0 },
11004     { "enclu",          { Skip_MODRM }, 0 },
11005   },
11006   {
11007     /* RM_0F01_REG_3 */
11008     { "vmrun",          { Skip_MODRM }, 0 },
11009     { "vmmcall",        { Skip_MODRM }, 0 },
11010     { "vmload",         { Skip_MODRM }, 0 },
11011     { "vmsave",         { Skip_MODRM }, 0 },
11012     { "stgi",           { Skip_MODRM }, 0 },
11013     { "clgi",           { Skip_MODRM }, 0 },
11014     { "skinit",         { Skip_MODRM }, 0 },
11015     { "invlpga",        { Skip_MODRM }, 0 },
11016   },
11017   {
11018     /* RM_0F01_REG_5 */
11019     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11020     { Bad_Opcode },
11021     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11022     { Bad_Opcode },
11023     { Bad_Opcode },
11024     { Bad_Opcode },
11025     { "rdpkru",         { Skip_MODRM }, 0 },
11026     { "wrpkru",         { Skip_MODRM }, 0 },
11027   },
11028   {
11029     /* RM_0F01_REG_7 */
11030     { "swapgs",         { Skip_MODRM }, 0  },
11031     { "rdtscp",         { Skip_MODRM }, 0  },
11032     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11033     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11034     { "clzero",         { Skip_MODRM }, 0  },
11035   },
11036   {
11037     /* RM_0F1E_MOD_3_REG_7 */
11038     { "nopQ",           { Ev }, 0 },
11039     { "nopQ",           { Ev }, 0 },
11040     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11041     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11042     { "nopQ",           { Ev }, 0 },
11043     { "nopQ",           { Ev }, 0 },
11044     { "nopQ",           { Ev }, 0 },
11045     { "nopQ",           { Ev }, 0 },
11046   },
11047   {
11048     /* RM_0FAE_REG_6 */
11049     { "mfence",         { Skip_MODRM }, 0 },
11050   },
11051   {
11052     /* RM_0FAE_REG_7 */
11053     { "sfence",         { Skip_MODRM }, 0 },
11054
11055   },
11056 };
11057
11058 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11059
11060 /* We use the high bit to indicate different name for the same
11061    prefix.  */
11062 #define REP_PREFIX      (0xf3 | 0x100)
11063 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11064 #define XRELEASE_PREFIX (0xf3 | 0x400)
11065 #define BND_PREFIX      (0xf2 | 0x400)
11066 #define NOTRACK_PREFIX  (0x3e | 0x100)
11067
11068 static int
11069 ckprefix (void)
11070 {
11071   int newrex, i, length;
11072   rex = 0;
11073   rex_ignored = 0;
11074   prefixes = 0;
11075   used_prefixes = 0;
11076   rex_used = 0;
11077   last_lock_prefix = -1;
11078   last_repz_prefix = -1;
11079   last_repnz_prefix = -1;
11080   last_data_prefix = -1;
11081   last_addr_prefix = -1;
11082   last_rex_prefix = -1;
11083   last_seg_prefix = -1;
11084   fwait_prefix = -1;
11085   active_seg_prefix = 0;
11086   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11087     all_prefixes[i] = 0;
11088   i = 0;
11089   length = 0;
11090   /* The maximum instruction length is 15bytes.  */
11091   while (length < MAX_CODE_LENGTH - 1)
11092     {
11093       FETCH_DATA (the_info, codep + 1);
11094       newrex = 0;
11095       switch (*codep)
11096         {
11097         /* REX prefixes family.  */
11098         case 0x40:
11099         case 0x41:
11100         case 0x42:
11101         case 0x43:
11102         case 0x44:
11103         case 0x45:
11104         case 0x46:
11105         case 0x47:
11106         case 0x48:
11107         case 0x49:
11108         case 0x4a:
11109         case 0x4b:
11110         case 0x4c:
11111         case 0x4d:
11112         case 0x4e:
11113         case 0x4f:
11114           if (address_mode == mode_64bit)
11115             newrex = *codep;
11116           else
11117             return 1;
11118           last_rex_prefix = i;
11119           break;
11120         case 0xf3:
11121           prefixes |= PREFIX_REPZ;
11122           last_repz_prefix = i;
11123           break;
11124         case 0xf2:
11125           prefixes |= PREFIX_REPNZ;
11126           last_repnz_prefix = i;
11127           break;
11128         case 0xf0:
11129           prefixes |= PREFIX_LOCK;
11130           last_lock_prefix = i;
11131           break;
11132         case 0x2e:
11133           prefixes |= PREFIX_CS;
11134           last_seg_prefix = i;
11135           active_seg_prefix = PREFIX_CS;
11136           break;
11137         case 0x36:
11138           prefixes |= PREFIX_SS;
11139           last_seg_prefix = i;
11140           active_seg_prefix = PREFIX_SS;
11141           break;
11142         case 0x3e:
11143           prefixes |= PREFIX_DS;
11144           last_seg_prefix = i;
11145           active_seg_prefix = PREFIX_DS;
11146           break;
11147         case 0x26:
11148           prefixes |= PREFIX_ES;
11149           last_seg_prefix = i;
11150           active_seg_prefix = PREFIX_ES;
11151           break;
11152         case 0x64:
11153           prefixes |= PREFIX_FS;
11154           last_seg_prefix = i;
11155           active_seg_prefix = PREFIX_FS;
11156           break;
11157         case 0x65:
11158           prefixes |= PREFIX_GS;
11159           last_seg_prefix = i;
11160           active_seg_prefix = PREFIX_GS;
11161           break;
11162         case 0x66:
11163           prefixes |= PREFIX_DATA;
11164           last_data_prefix = i;
11165           break;
11166         case 0x67:
11167           prefixes |= PREFIX_ADDR;
11168           last_addr_prefix = i;
11169           break;
11170         case FWAIT_OPCODE:
11171           /* fwait is really an instruction.  If there are prefixes
11172              before the fwait, they belong to the fwait, *not* to the
11173              following instruction.  */
11174           fwait_prefix = i;
11175           if (prefixes || rex)
11176             {
11177               prefixes |= PREFIX_FWAIT;
11178               codep++;
11179               /* This ensures that the previous REX prefixes are noticed
11180                  as unused prefixes, as in the return case below.  */
11181               rex_used = rex;
11182               return 1;
11183             }
11184           prefixes = PREFIX_FWAIT;
11185           break;
11186         default:
11187           return 1;
11188         }
11189       /* Rex is ignored when followed by another prefix.  */
11190       if (rex)
11191         {
11192           rex_used = rex;
11193           return 1;
11194         }
11195       if (*codep != FWAIT_OPCODE)
11196         all_prefixes[i++] = *codep;
11197       rex = newrex;
11198       codep++;
11199       length++;
11200     }
11201   return 0;
11202 }
11203
11204 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11205    prefix byte.  */
11206
11207 static const char *
11208 prefix_name (int pref, int sizeflag)
11209 {
11210   static const char *rexes [16] =
11211     {
11212       "rex",            /* 0x40 */
11213       "rex.B",          /* 0x41 */
11214       "rex.X",          /* 0x42 */
11215       "rex.XB",         /* 0x43 */
11216       "rex.R",          /* 0x44 */
11217       "rex.RB",         /* 0x45 */
11218       "rex.RX",         /* 0x46 */
11219       "rex.RXB",        /* 0x47 */
11220       "rex.W",          /* 0x48 */
11221       "rex.WB",         /* 0x49 */
11222       "rex.WX",         /* 0x4a */
11223       "rex.WXB",        /* 0x4b */
11224       "rex.WR",         /* 0x4c */
11225       "rex.WRB",        /* 0x4d */
11226       "rex.WRX",        /* 0x4e */
11227       "rex.WRXB",       /* 0x4f */
11228     };
11229
11230   switch (pref)
11231     {
11232     /* REX prefixes family.  */
11233     case 0x40:
11234     case 0x41:
11235     case 0x42:
11236     case 0x43:
11237     case 0x44:
11238     case 0x45:
11239     case 0x46:
11240     case 0x47:
11241     case 0x48:
11242     case 0x49:
11243     case 0x4a:
11244     case 0x4b:
11245     case 0x4c:
11246     case 0x4d:
11247     case 0x4e:
11248     case 0x4f:
11249       return rexes [pref - 0x40];
11250     case 0xf3:
11251       return "repz";
11252     case 0xf2:
11253       return "repnz";
11254     case 0xf0:
11255       return "lock";
11256     case 0x2e:
11257       return "cs";
11258     case 0x36:
11259       return "ss";
11260     case 0x3e:
11261       return "ds";
11262     case 0x26:
11263       return "es";
11264     case 0x64:
11265       return "fs";
11266     case 0x65:
11267       return "gs";
11268     case 0x66:
11269       return (sizeflag & DFLAG) ? "data16" : "data32";
11270     case 0x67:
11271       if (address_mode == mode_64bit)
11272         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11273       else
11274         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11275     case FWAIT_OPCODE:
11276       return "fwait";
11277     case REP_PREFIX:
11278       return "rep";
11279     case XACQUIRE_PREFIX:
11280       return "xacquire";
11281     case XRELEASE_PREFIX:
11282       return "xrelease";
11283     case BND_PREFIX:
11284       return "bnd";
11285     case NOTRACK_PREFIX:
11286       return "notrack";
11287     default:
11288       return NULL;
11289     }
11290 }
11291
11292 static char op_out[MAX_OPERANDS][100];
11293 static int op_ad, op_index[MAX_OPERANDS];
11294 static int two_source_ops;
11295 static bfd_vma op_address[MAX_OPERANDS];
11296 static bfd_vma op_riprel[MAX_OPERANDS];
11297 static bfd_vma start_pc;
11298
11299 /*
11300  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11301  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11302  *   section of the "Virtual 8086 Mode" chapter.)
11303  * 'pc' should be the address of this instruction, it will
11304  *   be used to print the target address if this is a relative jump or call
11305  * The function returns the length of this instruction in bytes.
11306  */
11307
11308 static char intel_syntax;
11309 static char intel_mnemonic = !SYSV386_COMPAT;
11310 static char open_char;
11311 static char close_char;
11312 static char separator_char;
11313 static char scale_char;
11314
11315 enum x86_64_isa
11316 {
11317   amd64 = 0,
11318   intel64
11319 };
11320
11321 static enum x86_64_isa isa64;
11322
11323 /* Here for backwards compatibility.  When gdb stops using
11324    print_insn_i386_att and print_insn_i386_intel these functions can
11325    disappear, and print_insn_i386 be merged into print_insn.  */
11326 int
11327 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11328 {
11329   intel_syntax = 0;
11330
11331   return print_insn (pc, info);
11332 }
11333
11334 int
11335 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11336 {
11337   intel_syntax = 1;
11338
11339   return print_insn (pc, info);
11340 }
11341
11342 int
11343 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11344 {
11345   intel_syntax = -1;
11346
11347   return print_insn (pc, info);
11348 }
11349
11350 void
11351 print_i386_disassembler_options (FILE *stream)
11352 {
11353   fprintf (stream, _("\n\
11354 The following i386/x86-64 specific disassembler options are supported for use\n\
11355 with the -M switch (multiple options should be separated by commas):\n"));
11356
11357   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11358   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11359   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11360   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11361   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11362   fprintf (stream, _("  att-mnemonic\n"
11363                      "              Display instruction in AT&T mnemonic\n"));
11364   fprintf (stream, _("  intel-mnemonic\n"
11365                      "              Display instruction in Intel mnemonic\n"));
11366   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11367   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11368   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11369   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11370   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11371   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11372   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11373   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11374 }
11375
11376 /* Bad opcode.  */
11377 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11378
11379 /* Get a pointer to struct dis386 with a valid name.  */
11380
11381 static const struct dis386 *
11382 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11383 {
11384   int vindex, vex_table_index;
11385
11386   if (dp->name != NULL)
11387     return dp;
11388
11389   switch (dp->op[0].bytemode)
11390     {
11391     case USE_REG_TABLE:
11392       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11393       break;
11394
11395     case USE_MOD_TABLE:
11396       vindex = modrm.mod == 0x3 ? 1 : 0;
11397       dp = &mod_table[dp->op[1].bytemode][vindex];
11398       break;
11399
11400     case USE_RM_TABLE:
11401       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11402       break;
11403
11404     case USE_PREFIX_TABLE:
11405       if (need_vex)
11406         {
11407           /* The prefix in VEX is implicit.  */
11408           switch (vex.prefix)
11409             {
11410             case 0:
11411               vindex = 0;
11412               break;
11413             case REPE_PREFIX_OPCODE:
11414               vindex = 1;
11415               break;
11416             case DATA_PREFIX_OPCODE:
11417               vindex = 2;
11418               break;
11419             case REPNE_PREFIX_OPCODE:
11420               vindex = 3;
11421               break;
11422             default:
11423               abort ();
11424               break;
11425             }
11426         }
11427       else
11428         {
11429           int last_prefix = -1;
11430           int prefix = 0;
11431           vindex = 0;
11432           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11433              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11434              last one wins.  */
11435           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11436             {
11437               if (last_repz_prefix > last_repnz_prefix)
11438                 {
11439                   vindex = 1;
11440                   prefix = PREFIX_REPZ;
11441                   last_prefix = last_repz_prefix;
11442                 }
11443               else
11444                 {
11445                   vindex = 3;
11446                   prefix = PREFIX_REPNZ;
11447                   last_prefix = last_repnz_prefix;
11448                 }
11449
11450               /* Check if prefix should be ignored.  */
11451               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11452                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11453                    & prefix) != 0)
11454                 vindex = 0;
11455             }
11456
11457           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11458             {
11459               vindex = 2;
11460               prefix = PREFIX_DATA;
11461               last_prefix = last_data_prefix;
11462             }
11463
11464           if (vindex != 0)
11465             {
11466               used_prefixes |= prefix;
11467               all_prefixes[last_prefix] = 0;
11468             }
11469         }
11470       dp = &prefix_table[dp->op[1].bytemode][vindex];
11471       break;
11472
11473     case USE_X86_64_TABLE:
11474       vindex = address_mode == mode_64bit ? 1 : 0;
11475       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11476       break;
11477
11478     case USE_3BYTE_TABLE:
11479       FETCH_DATA (info, codep + 2);
11480       vindex = *codep++;
11481       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11482       end_codep = codep;
11483       modrm.mod = (*codep >> 6) & 3;
11484       modrm.reg = (*codep >> 3) & 7;
11485       modrm.rm = *codep & 7;
11486       break;
11487
11488     case USE_VEX_LEN_TABLE:
11489       if (!need_vex)
11490         abort ();
11491
11492       switch (vex.length)
11493         {
11494         case 128:
11495           vindex = 0;
11496           break;
11497         case 256:
11498           vindex = 1;
11499           break;
11500         default:
11501           abort ();
11502           break;
11503         }
11504
11505       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11506       break;
11507
11508     case USE_EVEX_LEN_TABLE:
11509       if (!vex.evex)
11510         abort ();
11511
11512       switch (vex.length)
11513         {
11514         case 128:
11515           vindex = 0;
11516           break;
11517         case 256:
11518           vindex = 1;
11519           break;
11520         case 512:
11521           vindex = 2;
11522           break;
11523         default:
11524           abort ();
11525           break;
11526         }
11527
11528       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11529       break;
11530
11531     case USE_XOP_8F_TABLE:
11532       FETCH_DATA (info, codep + 3);
11533       /* All bits in the REX prefix are ignored.  */
11534       rex_ignored = rex;
11535       rex = ~(*codep >> 5) & 0x7;
11536
11537       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11538       switch ((*codep & 0x1f))
11539         {
11540         default:
11541           dp = &bad_opcode;
11542           return dp;
11543         case 0x8:
11544           vex_table_index = XOP_08;
11545           break;
11546         case 0x9:
11547           vex_table_index = XOP_09;
11548           break;
11549         case 0xa:
11550           vex_table_index = XOP_0A;
11551           break;
11552         }
11553       codep++;
11554       vex.w = *codep & 0x80;
11555       if (vex.w && address_mode == mode_64bit)
11556         rex |= REX_W;
11557
11558       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11559       if (address_mode != mode_64bit)
11560         {
11561           /* In 16/32-bit mode REX_B is silently ignored.  */
11562           rex &= ~REX_B;
11563         }
11564
11565       vex.length = (*codep & 0x4) ? 256 : 128;
11566       switch ((*codep & 0x3))
11567         {
11568         case 0:
11569           break;
11570         case 1:
11571           vex.prefix = DATA_PREFIX_OPCODE;
11572           break;
11573         case 2:
11574           vex.prefix = REPE_PREFIX_OPCODE;
11575           break;
11576         case 3:
11577           vex.prefix = REPNE_PREFIX_OPCODE;
11578           break;
11579         }
11580       need_vex = 1;
11581       need_vex_reg = 1;
11582       codep++;
11583       vindex = *codep++;
11584       dp = &xop_table[vex_table_index][vindex];
11585
11586       end_codep = codep;
11587       FETCH_DATA (info, codep + 1);
11588       modrm.mod = (*codep >> 6) & 3;
11589       modrm.reg = (*codep >> 3) & 7;
11590       modrm.rm = *codep & 7;
11591       break;
11592
11593     case USE_VEX_C4_TABLE:
11594       /* VEX prefix.  */
11595       FETCH_DATA (info, codep + 3);
11596       /* All bits in the REX prefix are ignored.  */
11597       rex_ignored = rex;
11598       rex = ~(*codep >> 5) & 0x7;
11599       switch ((*codep & 0x1f))
11600         {
11601         default:
11602           dp = &bad_opcode;
11603           return dp;
11604         case 0x1:
11605           vex_table_index = VEX_0F;
11606           break;
11607         case 0x2:
11608           vex_table_index = VEX_0F38;
11609           break;
11610         case 0x3:
11611           vex_table_index = VEX_0F3A;
11612           break;
11613         }
11614       codep++;
11615       vex.w = *codep & 0x80;
11616       if (address_mode == mode_64bit)
11617         {
11618           if (vex.w)
11619             rex |= REX_W;
11620         }
11621       else
11622         {
11623           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11624              is ignored, other REX bits are 0 and the highest bit in
11625              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11626           rex = 0;
11627         }
11628       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11629       vex.length = (*codep & 0x4) ? 256 : 128;
11630       switch ((*codep & 0x3))
11631         {
11632         case 0:
11633           break;
11634         case 1:
11635           vex.prefix = DATA_PREFIX_OPCODE;
11636           break;
11637         case 2:
11638           vex.prefix = REPE_PREFIX_OPCODE;
11639           break;
11640         case 3:
11641           vex.prefix = REPNE_PREFIX_OPCODE;
11642           break;
11643         }
11644       need_vex = 1;
11645       need_vex_reg = 1;
11646       codep++;
11647       vindex = *codep++;
11648       dp = &vex_table[vex_table_index][vindex];
11649       end_codep = codep;
11650       /* There is no MODRM byte for VEX0F 77.  */
11651       if (vex_table_index != VEX_0F || vindex != 0x77)
11652         {
11653           FETCH_DATA (info, codep + 1);
11654           modrm.mod = (*codep >> 6) & 3;
11655           modrm.reg = (*codep >> 3) & 7;
11656           modrm.rm = *codep & 7;
11657         }
11658       break;
11659
11660     case USE_VEX_C5_TABLE:
11661       /* VEX prefix.  */
11662       FETCH_DATA (info, codep + 2);
11663       /* All bits in the REX prefix are ignored.  */
11664       rex_ignored = rex;
11665       rex = (*codep & 0x80) ? 0 : REX_R;
11666
11667       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11668          VEX.vvvv is 1.  */
11669       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11670       vex.length = (*codep & 0x4) ? 256 : 128;
11671       switch ((*codep & 0x3))
11672         {
11673         case 0:
11674           break;
11675         case 1:
11676           vex.prefix = DATA_PREFIX_OPCODE;
11677           break;
11678         case 2:
11679           vex.prefix = REPE_PREFIX_OPCODE;
11680           break;
11681         case 3:
11682           vex.prefix = REPNE_PREFIX_OPCODE;
11683           break;
11684         }
11685       need_vex = 1;
11686       need_vex_reg = 1;
11687       codep++;
11688       vindex = *codep++;
11689       dp = &vex_table[dp->op[1].bytemode][vindex];
11690       end_codep = codep;
11691       /* There is no MODRM byte for VEX 77.  */
11692       if (vindex != 0x77)
11693         {
11694           FETCH_DATA (info, codep + 1);
11695           modrm.mod = (*codep >> 6) & 3;
11696           modrm.reg = (*codep >> 3) & 7;
11697           modrm.rm = *codep & 7;
11698         }
11699       break;
11700
11701     case USE_VEX_W_TABLE:
11702       if (!need_vex)
11703         abort ();
11704
11705       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11706       break;
11707
11708     case USE_EVEX_TABLE:
11709       two_source_ops = 0;
11710       /* EVEX prefix.  */
11711       vex.evex = 1;
11712       FETCH_DATA (info, codep + 4);
11713       /* All bits in the REX prefix are ignored.  */
11714       rex_ignored = rex;
11715       /* The first byte after 0x62.  */
11716       rex = ~(*codep >> 5) & 0x7;
11717       vex.r = *codep & 0x10;
11718       switch ((*codep & 0xf))
11719         {
11720         default:
11721           return &bad_opcode;
11722         case 0x1:
11723           vex_table_index = EVEX_0F;
11724           break;
11725         case 0x2:
11726           vex_table_index = EVEX_0F38;
11727           break;
11728         case 0x3:
11729           vex_table_index = EVEX_0F3A;
11730           break;
11731         }
11732
11733       /* The second byte after 0x62.  */
11734       codep++;
11735       vex.w = *codep & 0x80;
11736       if (vex.w && address_mode == mode_64bit)
11737         rex |= REX_W;
11738
11739       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11740
11741       /* The U bit.  */
11742       if (!(*codep & 0x4))
11743         return &bad_opcode;
11744
11745       switch ((*codep & 0x3))
11746         {
11747         case 0:
11748           break;
11749         case 1:
11750           vex.prefix = DATA_PREFIX_OPCODE;
11751           break;
11752         case 2:
11753           vex.prefix = REPE_PREFIX_OPCODE;
11754           break;
11755         case 3:
11756           vex.prefix = REPNE_PREFIX_OPCODE;
11757           break;
11758         }
11759
11760       /* The third byte after 0x62.  */
11761       codep++;
11762
11763       /* Remember the static rounding bits.  */
11764       vex.ll = (*codep >> 5) & 3;
11765       vex.b = (*codep & 0x10) != 0;
11766
11767       vex.v = *codep & 0x8;
11768       vex.mask_register_specifier = *codep & 0x7;
11769       vex.zeroing = *codep & 0x80;
11770
11771       if (address_mode != mode_64bit)
11772         {
11773           /* In 16/32-bit mode silently ignore following bits.  */
11774           rex &= ~REX_B;
11775           vex.r = 1;
11776           vex.v = 1;
11777         }
11778
11779       need_vex = 1;
11780       need_vex_reg = 1;
11781       codep++;
11782       vindex = *codep++;
11783       dp = &evex_table[vex_table_index][vindex];
11784       end_codep = codep;
11785       FETCH_DATA (info, codep + 1);
11786       modrm.mod = (*codep >> 6) & 3;
11787       modrm.reg = (*codep >> 3) & 7;
11788       modrm.rm = *codep & 7;
11789
11790       /* Set vector length.  */
11791       if (modrm.mod == 3 && vex.b)
11792         vex.length = 512;
11793       else
11794         {
11795           switch (vex.ll)
11796             {
11797             case 0x0:
11798               vex.length = 128;
11799               break;
11800             case 0x1:
11801               vex.length = 256;
11802               break;
11803             case 0x2:
11804               vex.length = 512;
11805               break;
11806             default:
11807               return &bad_opcode;
11808             }
11809         }
11810       break;
11811
11812     case 0:
11813       dp = &bad_opcode;
11814       break;
11815
11816     default:
11817       abort ();
11818     }
11819
11820   if (dp->name != NULL)
11821     return dp;
11822   else
11823     return get_valid_dis386 (dp, info);
11824 }
11825
11826 static void
11827 get_sib (disassemble_info *info, int sizeflag)
11828 {
11829   /* If modrm.mod == 3, operand must be register.  */
11830   if (need_modrm
11831       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11832       && modrm.mod != 3
11833       && modrm.rm == 4)
11834     {
11835       FETCH_DATA (info, codep + 2);
11836       sib.index = (codep [1] >> 3) & 7;
11837       sib.scale = (codep [1] >> 6) & 3;
11838       sib.base = codep [1] & 7;
11839     }
11840 }
11841
11842 static int
11843 print_insn (bfd_vma pc, disassemble_info *info)
11844 {
11845   const struct dis386 *dp;
11846   int i;
11847   char *op_txt[MAX_OPERANDS];
11848   int needcomma;
11849   int sizeflag, orig_sizeflag;
11850   const char *p;
11851   struct dis_private priv;
11852   int prefix_length;
11853
11854   priv.orig_sizeflag = AFLAG | DFLAG;
11855   if ((info->mach & bfd_mach_i386_i386) != 0)
11856     address_mode = mode_32bit;
11857   else if (info->mach == bfd_mach_i386_i8086)
11858     {
11859       address_mode = mode_16bit;
11860       priv.orig_sizeflag = 0;
11861     }
11862   else
11863     address_mode = mode_64bit;
11864
11865   if (intel_syntax == (char) -1)
11866     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11867
11868   for (p = info->disassembler_options; p != NULL; )
11869     {
11870       if (CONST_STRNEQ (p, "amd64"))
11871         isa64 = amd64;
11872       else if (CONST_STRNEQ (p, "intel64"))
11873         isa64 = intel64;
11874       else if (CONST_STRNEQ (p, "x86-64"))
11875         {
11876           address_mode = mode_64bit;
11877           priv.orig_sizeflag = AFLAG | DFLAG;
11878         }
11879       else if (CONST_STRNEQ (p, "i386"))
11880         {
11881           address_mode = mode_32bit;
11882           priv.orig_sizeflag = AFLAG | DFLAG;
11883         }
11884       else if (CONST_STRNEQ (p, "i8086"))
11885         {
11886           address_mode = mode_16bit;
11887           priv.orig_sizeflag = 0;
11888         }
11889       else if (CONST_STRNEQ (p, "intel"))
11890         {
11891           intel_syntax = 1;
11892           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11893             intel_mnemonic = 1;
11894         }
11895       else if (CONST_STRNEQ (p, "att"))
11896         {
11897           intel_syntax = 0;
11898           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11899             intel_mnemonic = 0;
11900         }
11901       else if (CONST_STRNEQ (p, "addr"))
11902         {
11903           if (address_mode == mode_64bit)
11904             {
11905               if (p[4] == '3' && p[5] == '2')
11906                 priv.orig_sizeflag &= ~AFLAG;
11907               else if (p[4] == '6' && p[5] == '4')
11908                 priv.orig_sizeflag |= AFLAG;
11909             }
11910           else
11911             {
11912               if (p[4] == '1' && p[5] == '6')
11913                 priv.orig_sizeflag &= ~AFLAG;
11914               else if (p[4] == '3' && p[5] == '2')
11915                 priv.orig_sizeflag |= AFLAG;
11916             }
11917         }
11918       else if (CONST_STRNEQ (p, "data"))
11919         {
11920           if (p[4] == '1' && p[5] == '6')
11921             priv.orig_sizeflag &= ~DFLAG;
11922           else if (p[4] == '3' && p[5] == '2')
11923             priv.orig_sizeflag |= DFLAG;
11924         }
11925       else if (CONST_STRNEQ (p, "suffix"))
11926         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11927
11928       p = strchr (p, ',');
11929       if (p != NULL)
11930         p++;
11931     }
11932
11933   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11934     {
11935       (*info->fprintf_func) (info->stream,
11936                              _("64-bit address is disabled"));
11937       return -1;
11938     }
11939
11940   if (intel_syntax)
11941     {
11942       names64 = intel_names64;
11943       names32 = intel_names32;
11944       names16 = intel_names16;
11945       names8 = intel_names8;
11946       names8rex = intel_names8rex;
11947       names_seg = intel_names_seg;
11948       names_mm = intel_names_mm;
11949       names_bnd = intel_names_bnd;
11950       names_xmm = intel_names_xmm;
11951       names_ymm = intel_names_ymm;
11952       names_zmm = intel_names_zmm;
11953       index64 = intel_index64;
11954       index32 = intel_index32;
11955       names_mask = intel_names_mask;
11956       index16 = intel_index16;
11957       open_char = '[';
11958       close_char = ']';
11959       separator_char = '+';
11960       scale_char = '*';
11961     }
11962   else
11963     {
11964       names64 = att_names64;
11965       names32 = att_names32;
11966       names16 = att_names16;
11967       names8 = att_names8;
11968       names8rex = att_names8rex;
11969       names_seg = att_names_seg;
11970       names_mm = att_names_mm;
11971       names_bnd = att_names_bnd;
11972       names_xmm = att_names_xmm;
11973       names_ymm = att_names_ymm;
11974       names_zmm = att_names_zmm;
11975       index64 = att_index64;
11976       index32 = att_index32;
11977       names_mask = att_names_mask;
11978       index16 = att_index16;
11979       open_char = '(';
11980       close_char =  ')';
11981       separator_char = ',';
11982       scale_char = ',';
11983     }
11984
11985   /* The output looks better if we put 7 bytes on a line, since that
11986      puts most long word instructions on a single line.  Use 8 bytes
11987      for Intel L1OM.  */
11988   if ((info->mach & bfd_mach_l1om) != 0)
11989     info->bytes_per_line = 8;
11990   else
11991     info->bytes_per_line = 7;
11992
11993   info->private_data = &priv;
11994   priv.max_fetched = priv.the_buffer;
11995   priv.insn_start = pc;
11996
11997   obuf[0] = 0;
11998   for (i = 0; i < MAX_OPERANDS; ++i)
11999     {
12000       op_out[i][0] = 0;
12001       op_index[i] = -1;
12002     }
12003
12004   the_info = info;
12005   start_pc = pc;
12006   start_codep = priv.the_buffer;
12007   codep = priv.the_buffer;
12008
12009   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12010     {
12011       const char *name;
12012
12013       /* Getting here means we tried for data but didn't get it.  That
12014          means we have an incomplete instruction of some sort.  Just
12015          print the first byte as a prefix or a .byte pseudo-op.  */
12016       if (codep > priv.the_buffer)
12017         {
12018           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12019           if (name != NULL)
12020             (*info->fprintf_func) (info->stream, "%s", name);
12021           else
12022             {
12023               /* Just print the first byte as a .byte instruction.  */
12024               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12025                                      (unsigned int) priv.the_buffer[0]);
12026             }
12027
12028           return 1;
12029         }
12030
12031       return -1;
12032     }
12033
12034   obufp = obuf;
12035   sizeflag = priv.orig_sizeflag;
12036
12037   if (!ckprefix () || rex_used)
12038     {
12039       /* Too many prefixes or unused REX prefixes.  */
12040       for (i = 0;
12041            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12042            i++)
12043         (*info->fprintf_func) (info->stream, "%s%s",
12044                                i == 0 ? "" : " ",
12045                                prefix_name (all_prefixes[i], sizeflag));
12046       return i;
12047     }
12048
12049   insn_codep = codep;
12050
12051   FETCH_DATA (info, codep + 1);
12052   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12053
12054   if (((prefixes & PREFIX_FWAIT)
12055        && ((*codep < 0xd8) || (*codep > 0xdf))))
12056     {
12057       /* Handle prefixes before fwait.  */
12058       for (i = 0; i < fwait_prefix && all_prefixes[i];
12059            i++)
12060         (*info->fprintf_func) (info->stream, "%s ",
12061                                prefix_name (all_prefixes[i], sizeflag));
12062       (*info->fprintf_func) (info->stream, "fwait");
12063       return i + 1;
12064     }
12065
12066   if (*codep == 0x0f)
12067     {
12068       unsigned char threebyte;
12069
12070       codep++;
12071       FETCH_DATA (info, codep + 1);
12072       threebyte = *codep;
12073       dp = &dis386_twobyte[threebyte];
12074       need_modrm = twobyte_has_modrm[*codep];
12075       codep++;
12076     }
12077   else
12078     {
12079       dp = &dis386[*codep];
12080       need_modrm = onebyte_has_modrm[*codep];
12081       codep++;
12082     }
12083
12084   /* Save sizeflag for printing the extra prefixes later before updating
12085      it for mnemonic and operand processing.  The prefix names depend
12086      only on the address mode.  */
12087   orig_sizeflag = sizeflag;
12088   if (prefixes & PREFIX_ADDR)
12089     sizeflag ^= AFLAG;
12090   if ((prefixes & PREFIX_DATA))
12091     sizeflag ^= DFLAG;
12092
12093   end_codep = codep;
12094   if (need_modrm)
12095     {
12096       FETCH_DATA (info, codep + 1);
12097       modrm.mod = (*codep >> 6) & 3;
12098       modrm.reg = (*codep >> 3) & 7;
12099       modrm.rm = *codep & 7;
12100     }
12101
12102   need_vex = 0;
12103   need_vex_reg = 0;
12104   vex_w_done = 0;
12105   memset (&vex, 0, sizeof (vex));
12106
12107   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12108     {
12109       get_sib (info, sizeflag);
12110       dofloat (sizeflag);
12111     }
12112   else
12113     {
12114       dp = get_valid_dis386 (dp, info);
12115       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12116         {
12117           get_sib (info, sizeflag);
12118           for (i = 0; i < MAX_OPERANDS; ++i)
12119             {
12120               obufp = op_out[i];
12121               op_ad = MAX_OPERANDS - 1 - i;
12122               if (dp->op[i].rtn)
12123                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12124               /* For EVEX instruction after the last operand masking
12125                  should be printed.  */
12126               if (i == 0 && vex.evex)
12127                 {
12128                   /* Don't print {%k0}.  */
12129                   if (vex.mask_register_specifier)
12130                     {
12131                       oappend ("{");
12132                       oappend (names_mask[vex.mask_register_specifier]);
12133                       oappend ("}");
12134                     }
12135                   if (vex.zeroing)
12136                     oappend ("{z}");
12137                 }
12138             }
12139         }
12140     }
12141
12142   /* Check if the REX prefix is used.  */
12143   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12144     all_prefixes[last_rex_prefix] = 0;
12145
12146   /* Check if the SEG prefix is used.  */
12147   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12148                    | PREFIX_FS | PREFIX_GS)) != 0
12149       && (used_prefixes & active_seg_prefix) != 0)
12150     all_prefixes[last_seg_prefix] = 0;
12151
12152   /* Check if the ADDR prefix is used.  */
12153   if ((prefixes & PREFIX_ADDR) != 0
12154       && (used_prefixes & PREFIX_ADDR) != 0)
12155     all_prefixes[last_addr_prefix] = 0;
12156
12157   /* Check if the DATA prefix is used.  */
12158   if ((prefixes & PREFIX_DATA) != 0
12159       && (used_prefixes & PREFIX_DATA) != 0)
12160     all_prefixes[last_data_prefix] = 0;
12161
12162   /* Print the extra prefixes.  */
12163   prefix_length = 0;
12164   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12165     if (all_prefixes[i])
12166       {
12167         const char *name;
12168         name = prefix_name (all_prefixes[i], orig_sizeflag);
12169         if (name == NULL)
12170           abort ();
12171         prefix_length += strlen (name) + 1;
12172         (*info->fprintf_func) (info->stream, "%s ", name);
12173       }
12174
12175   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12176      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12177      used by putop and MMX/SSE operand and may be overriden by the
12178      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12179      separately.  */
12180   if (dp->prefix_requirement == PREFIX_OPCODE
12181       && dp != &bad_opcode
12182       && (((prefixes
12183             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12184            && (used_prefixes
12185                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12186           || ((((prefixes
12187                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12188                 == PREFIX_DATA)
12189                && (used_prefixes & PREFIX_DATA) == 0))))
12190     {
12191       (*info->fprintf_func) (info->stream, "(bad)");
12192       return end_codep - priv.the_buffer;
12193     }
12194
12195   /* Check maximum code length.  */
12196   if ((codep - start_codep) > MAX_CODE_LENGTH)
12197     {
12198       (*info->fprintf_func) (info->stream, "(bad)");
12199       return MAX_CODE_LENGTH;
12200     }
12201
12202   obufp = mnemonicendp;
12203   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12204     oappend (" ");
12205   oappend (" ");
12206   (*info->fprintf_func) (info->stream, "%s", obuf);
12207
12208   /* The enter and bound instructions are printed with operands in the same
12209      order as the intel book; everything else is printed in reverse order.  */
12210   if (intel_syntax || two_source_ops)
12211     {
12212       bfd_vma riprel;
12213
12214       for (i = 0; i < MAX_OPERANDS; ++i)
12215         op_txt[i] = op_out[i];
12216
12217       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12218           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12219         {
12220           op_txt[2] = op_out[3];
12221           op_txt[3] = op_out[2];
12222         }
12223
12224       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12225         {
12226           op_ad = op_index[i];
12227           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12228           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12229           riprel = op_riprel[i];
12230           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12231           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12232         }
12233     }
12234   else
12235     {
12236       for (i = 0; i < MAX_OPERANDS; ++i)
12237         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12238     }
12239
12240   needcomma = 0;
12241   for (i = 0; i < MAX_OPERANDS; ++i)
12242     if (*op_txt[i])
12243       {
12244         if (needcomma)
12245           (*info->fprintf_func) (info->stream, ",");
12246         if (op_index[i] != -1 && !op_riprel[i])
12247           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12248         else
12249           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12250         needcomma = 1;
12251       }
12252
12253   for (i = 0; i < MAX_OPERANDS; i++)
12254     if (op_index[i] != -1 && op_riprel[i])
12255       {
12256         (*info->fprintf_func) (info->stream, "        # ");
12257         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12258                                                 + op_address[op_index[i]]), info);
12259         break;
12260       }
12261   return codep - priv.the_buffer;
12262 }
12263
12264 static const char *float_mem[] = {
12265   /* d8 */
12266   "fadd{s|}",
12267   "fmul{s|}",
12268   "fcom{s|}",
12269   "fcomp{s|}",
12270   "fsub{s|}",
12271   "fsubr{s|}",
12272   "fdiv{s|}",
12273   "fdivr{s|}",
12274   /* d9 */
12275   "fld{s|}",
12276   "(bad)",
12277   "fst{s|}",
12278   "fstp{s|}",
12279   "fldenvIC",
12280   "fldcw",
12281   "fNstenvIC",
12282   "fNstcw",
12283   /* da */
12284   "fiadd{l|}",
12285   "fimul{l|}",
12286   "ficom{l|}",
12287   "ficomp{l|}",
12288   "fisub{l|}",
12289   "fisubr{l|}",
12290   "fidiv{l|}",
12291   "fidivr{l|}",
12292   /* db */
12293   "fild{l|}",
12294   "fisttp{l|}",
12295   "fist{l|}",
12296   "fistp{l|}",
12297   "(bad)",
12298   "fld{t||t|}",
12299   "(bad)",
12300   "fstp{t||t|}",
12301   /* dc */
12302   "fadd{l|}",
12303   "fmul{l|}",
12304   "fcom{l|}",
12305   "fcomp{l|}",
12306   "fsub{l|}",
12307   "fsubr{l|}",
12308   "fdiv{l|}",
12309   "fdivr{l|}",
12310   /* dd */
12311   "fld{l|}",
12312   "fisttp{ll|}",
12313   "fst{l||}",
12314   "fstp{l|}",
12315   "frstorIC",
12316   "(bad)",
12317   "fNsaveIC",
12318   "fNstsw",
12319   /* de */
12320   "fiadd{s|}",
12321   "fimul{s|}",
12322   "ficom{s|}",
12323   "ficomp{s|}",
12324   "fisub{s|}",
12325   "fisubr{s|}",
12326   "fidiv{s|}",
12327   "fidivr{s|}",
12328   /* df */
12329   "fild{s|}",
12330   "fisttp{s|}",
12331   "fist{s|}",
12332   "fistp{s|}",
12333   "fbld",
12334   "fild{ll|}",
12335   "fbstp",
12336   "fistp{ll|}",
12337 };
12338
12339 static const unsigned char float_mem_mode[] = {
12340   /* d8 */
12341   d_mode,
12342   d_mode,
12343   d_mode,
12344   d_mode,
12345   d_mode,
12346   d_mode,
12347   d_mode,
12348   d_mode,
12349   /* d9 */
12350   d_mode,
12351   0,
12352   d_mode,
12353   d_mode,
12354   0,
12355   w_mode,
12356   0,
12357   w_mode,
12358   /* da */
12359   d_mode,
12360   d_mode,
12361   d_mode,
12362   d_mode,
12363   d_mode,
12364   d_mode,
12365   d_mode,
12366   d_mode,
12367   /* db */
12368   d_mode,
12369   d_mode,
12370   d_mode,
12371   d_mode,
12372   0,
12373   t_mode,
12374   0,
12375   t_mode,
12376   /* dc */
12377   q_mode,
12378   q_mode,
12379   q_mode,
12380   q_mode,
12381   q_mode,
12382   q_mode,
12383   q_mode,
12384   q_mode,
12385   /* dd */
12386   q_mode,
12387   q_mode,
12388   q_mode,
12389   q_mode,
12390   0,
12391   0,
12392   0,
12393   w_mode,
12394   /* de */
12395   w_mode,
12396   w_mode,
12397   w_mode,
12398   w_mode,
12399   w_mode,
12400   w_mode,
12401   w_mode,
12402   w_mode,
12403   /* df */
12404   w_mode,
12405   w_mode,
12406   w_mode,
12407   w_mode,
12408   t_mode,
12409   q_mode,
12410   t_mode,
12411   q_mode
12412 };
12413
12414 #define ST { OP_ST, 0 }
12415 #define STi { OP_STi, 0 }
12416
12417 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12418 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12419 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12420 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12421 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12422 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12423 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12424 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12425 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12426
12427 static const struct dis386 float_reg[][8] = {
12428   /* d8 */
12429   {
12430     { "fadd",   { ST, STi }, 0 },
12431     { "fmul",   { ST, STi }, 0 },
12432     { "fcom",   { STi }, 0 },
12433     { "fcomp",  { STi }, 0 },
12434     { "fsub",   { ST, STi }, 0 },
12435     { "fsubr",  { ST, STi }, 0 },
12436     { "fdiv",   { ST, STi }, 0 },
12437     { "fdivr",  { ST, STi }, 0 },
12438   },
12439   /* d9 */
12440   {
12441     { "fld",    { STi }, 0 },
12442     { "fxch",   { STi }, 0 },
12443     { FGRPd9_2 },
12444     { Bad_Opcode },
12445     { FGRPd9_4 },
12446     { FGRPd9_5 },
12447     { FGRPd9_6 },
12448     { FGRPd9_7 },
12449   },
12450   /* da */
12451   {
12452     { "fcmovb", { ST, STi }, 0 },
12453     { "fcmove", { ST, STi }, 0 },
12454     { "fcmovbe",{ ST, STi }, 0 },
12455     { "fcmovu", { ST, STi }, 0 },
12456     { Bad_Opcode },
12457     { FGRPda_5 },
12458     { Bad_Opcode },
12459     { Bad_Opcode },
12460   },
12461   /* db */
12462   {
12463     { "fcmovnb",{ ST, STi }, 0 },
12464     { "fcmovne",{ ST, STi }, 0 },
12465     { "fcmovnbe",{ ST, STi }, 0 },
12466     { "fcmovnu",{ ST, STi }, 0 },
12467     { FGRPdb_4 },
12468     { "fucomi", { ST, STi }, 0 },
12469     { "fcomi",  { ST, STi }, 0 },
12470     { Bad_Opcode },
12471   },
12472   /* dc */
12473   {
12474     { "fadd",   { STi, ST }, 0 },
12475     { "fmul",   { STi, ST }, 0 },
12476     { Bad_Opcode },
12477     { Bad_Opcode },
12478     { "fsub{!M|r}",     { STi, ST }, 0 },
12479     { "fsub{M|}",       { STi, ST }, 0 },
12480     { "fdiv{!M|r}",     { STi, ST }, 0 },
12481     { "fdiv{M|}",       { STi, ST }, 0 },
12482   },
12483   /* dd */
12484   {
12485     { "ffree",  { STi }, 0 },
12486     { Bad_Opcode },
12487     { "fst",    { STi }, 0 },
12488     { "fstp",   { STi }, 0 },
12489     { "fucom",  { STi }, 0 },
12490     { "fucomp", { STi }, 0 },
12491     { Bad_Opcode },
12492     { Bad_Opcode },
12493   },
12494   /* de */
12495   {
12496     { "faddp",  { STi, ST }, 0 },
12497     { "fmulp",  { STi, ST }, 0 },
12498     { Bad_Opcode },
12499     { FGRPde_3 },
12500     { "fsub{!M|r}p",    { STi, ST }, 0 },
12501     { "fsub{M|}p",      { STi, ST }, 0 },
12502     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12503     { "fdiv{M|}p",      { STi, ST }, 0 },
12504   },
12505   /* df */
12506   {
12507     { "ffreep", { STi }, 0 },
12508     { Bad_Opcode },
12509     { Bad_Opcode },
12510     { Bad_Opcode },
12511     { FGRPdf_4 },
12512     { "fucomip", { ST, STi }, 0 },
12513     { "fcomip", { ST, STi }, 0 },
12514     { Bad_Opcode },
12515   },
12516 };
12517
12518 static char *fgrps[][8] = {
12519   /* Bad opcode 0 */
12520   {
12521     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12522   },
12523
12524   /* d9_2  1 */
12525   {
12526     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12527   },
12528
12529   /* d9_4  2 */
12530   {
12531     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12532   },
12533
12534   /* d9_5  3 */
12535   {
12536     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12537   },
12538
12539   /* d9_6  4 */
12540   {
12541     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12542   },
12543
12544   /* d9_7  5 */
12545   {
12546     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12547   },
12548
12549   /* da_5  6 */
12550   {
12551     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12552   },
12553
12554   /* db_4  7 */
12555   {
12556     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12557     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12558   },
12559
12560   /* de_3  8 */
12561   {
12562     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12563   },
12564
12565   /* df_4  9 */
12566   {
12567     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12568   },
12569 };
12570
12571 static void
12572 swap_operand (void)
12573 {
12574   mnemonicendp[0] = '.';
12575   mnemonicendp[1] = 's';
12576   mnemonicendp += 2;
12577 }
12578
12579 static void
12580 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12581                int sizeflag ATTRIBUTE_UNUSED)
12582 {
12583   /* Skip mod/rm byte.  */
12584   MODRM_CHECK;
12585   codep++;
12586 }
12587
12588 static void
12589 dofloat (int sizeflag)
12590 {
12591   const struct dis386 *dp;
12592   unsigned char floatop;
12593
12594   floatop = codep[-1];
12595
12596   if (modrm.mod != 3)
12597     {
12598       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12599
12600       putop (float_mem[fp_indx], sizeflag);
12601       obufp = op_out[0];
12602       op_ad = 2;
12603       OP_E (float_mem_mode[fp_indx], sizeflag);
12604       return;
12605     }
12606   /* Skip mod/rm byte.  */
12607   MODRM_CHECK;
12608   codep++;
12609
12610   dp = &float_reg[floatop - 0xd8][modrm.reg];
12611   if (dp->name == NULL)
12612     {
12613       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12614
12615       /* Instruction fnstsw is only one with strange arg.  */
12616       if (floatop == 0xdf && codep[-1] == 0xe0)
12617         strcpy (op_out[0], names16[0]);
12618     }
12619   else
12620     {
12621       putop (dp->name, sizeflag);
12622
12623       obufp = op_out[0];
12624       op_ad = 2;
12625       if (dp->op[0].rtn)
12626         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12627
12628       obufp = op_out[1];
12629       op_ad = 1;
12630       if (dp->op[1].rtn)
12631         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12632     }
12633 }
12634
12635 /* Like oappend (below), but S is a string starting with '%'.
12636    In Intel syntax, the '%' is elided.  */
12637 static void
12638 oappend_maybe_intel (const char *s)
12639 {
12640   oappend (s + intel_syntax);
12641 }
12642
12643 static void
12644 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12645 {
12646   oappend_maybe_intel ("%st");
12647 }
12648
12649 static void
12650 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12651 {
12652   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12653   oappend_maybe_intel (scratchbuf);
12654 }
12655
12656 /* Capital letters in template are macros.  */
12657 static int
12658 putop (const char *in_template, int sizeflag)
12659 {
12660   const char *p;
12661   int alt = 0;
12662   int cond = 1;
12663   unsigned int l = 0, len = 1;
12664   char last[4];
12665
12666 #define SAVE_LAST(c)                    \
12667   if (l < len && l < sizeof (last))     \
12668     last[l++] = c;                      \
12669   else                                  \
12670     abort ();
12671
12672   for (p = in_template; *p; p++)
12673     {
12674       switch (*p)
12675         {
12676         default:
12677           *obufp++ = *p;
12678           break;
12679         case '%':
12680           len++;
12681           break;
12682         case '!':
12683           cond = 0;
12684           break;
12685         case '{':
12686           if (intel_syntax)
12687             {
12688               while (*++p != '|')
12689                 if (*p == '}' || *p == '\0')
12690                   abort ();
12691             }
12692           /* Fall through.  */
12693         case 'I':
12694           alt = 1;
12695           continue;
12696         case '|':
12697           while (*++p != '}')
12698             {
12699               if (*p == '\0')
12700                 abort ();
12701             }
12702           break;
12703         case '}':
12704           break;
12705         case 'A':
12706           if (intel_syntax)
12707             break;
12708           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12709             *obufp++ = 'b';
12710           break;
12711         case 'B':
12712           if (l == 0 && len == 1)
12713             {
12714 case_B:
12715               if (intel_syntax)
12716                 break;
12717               if (sizeflag & SUFFIX_ALWAYS)
12718                 *obufp++ = 'b';
12719             }
12720           else
12721             {
12722               if (l != 1
12723                   || len != 2
12724                   || last[0] != 'L')
12725                 {
12726                   SAVE_LAST (*p);
12727                   break;
12728                 }
12729
12730               if (address_mode == mode_64bit
12731                   && !(prefixes & PREFIX_ADDR))
12732                 {
12733                   *obufp++ = 'a';
12734                   *obufp++ = 'b';
12735                   *obufp++ = 's';
12736                 }
12737
12738               goto case_B;
12739             }
12740           break;
12741         case 'C':
12742           if (intel_syntax && !alt)
12743             break;
12744           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12745             {
12746               if (sizeflag & DFLAG)
12747                 *obufp++ = intel_syntax ? 'd' : 'l';
12748               else
12749                 *obufp++ = intel_syntax ? 'w' : 's';
12750               used_prefixes |= (prefixes & PREFIX_DATA);
12751             }
12752           break;
12753         case 'D':
12754           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12755             break;
12756           USED_REX (REX_W);
12757           if (modrm.mod == 3)
12758             {
12759               if (rex & REX_W)
12760                 *obufp++ = 'q';
12761               else
12762                 {
12763                   if (sizeflag & DFLAG)
12764                     *obufp++ = intel_syntax ? 'd' : 'l';
12765                   else
12766                     *obufp++ = 'w';
12767                   used_prefixes |= (prefixes & PREFIX_DATA);
12768                 }
12769             }
12770           else
12771             *obufp++ = 'w';
12772           break;
12773         case 'E':               /* For jcxz/jecxz */
12774           if (address_mode == mode_64bit)
12775             {
12776               if (sizeflag & AFLAG)
12777                 *obufp++ = 'r';
12778               else
12779                 *obufp++ = 'e';
12780             }
12781           else
12782             if (sizeflag & AFLAG)
12783               *obufp++ = 'e';
12784           used_prefixes |= (prefixes & PREFIX_ADDR);
12785           break;
12786         case 'F':
12787           if (intel_syntax)
12788             break;
12789           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12790             {
12791               if (sizeflag & AFLAG)
12792                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12793               else
12794                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12795               used_prefixes |= (prefixes & PREFIX_ADDR);
12796             }
12797           break;
12798         case 'G':
12799           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12800             break;
12801           if ((rex & REX_W) || (sizeflag & DFLAG))
12802             *obufp++ = 'l';
12803           else
12804             *obufp++ = 'w';
12805           if (!(rex & REX_W))
12806             used_prefixes |= (prefixes & PREFIX_DATA);
12807           break;
12808         case 'H':
12809           if (intel_syntax)
12810             break;
12811           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12812               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12813             {
12814               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12815               *obufp++ = ',';
12816               *obufp++ = 'p';
12817               if (prefixes & PREFIX_DS)
12818                 *obufp++ = 't';
12819               else
12820                 *obufp++ = 'n';
12821             }
12822           break;
12823         case 'J':
12824           if (intel_syntax)
12825             break;
12826           *obufp++ = 'l';
12827           break;
12828         case 'K':
12829           USED_REX (REX_W);
12830           if (rex & REX_W)
12831             *obufp++ = 'q';
12832           else
12833             *obufp++ = 'd';
12834           break;
12835         case 'Z':
12836           if (l != 0 || len != 1)
12837             {
12838               if (l != 1 || len != 2 || last[0] != 'X')
12839                 {
12840                   SAVE_LAST (*p);
12841                   break;
12842                 }
12843               if (!need_vex || !vex.evex)
12844                 abort ();
12845               if (intel_syntax
12846                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12847                 break;
12848               switch (vex.length)
12849                 {
12850                 case 128:
12851                   *obufp++ = 'x';
12852                   break;
12853                 case 256:
12854                   *obufp++ = 'y';
12855                   break;
12856                 case 512:
12857                   *obufp++ = 'z';
12858                   break;
12859                 default:
12860                   abort ();
12861                 }
12862               break;
12863             }
12864           if (intel_syntax)
12865             break;
12866           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12867             {
12868               *obufp++ = 'q';
12869               break;
12870             }
12871           /* Fall through.  */
12872           goto case_L;
12873         case 'L':
12874           if (l != 0 || len != 1)
12875             {
12876               SAVE_LAST (*p);
12877               break;
12878             }
12879 case_L:
12880           if (intel_syntax)
12881             break;
12882           if (sizeflag & SUFFIX_ALWAYS)
12883             *obufp++ = 'l';
12884           break;
12885         case 'M':
12886           if (intel_mnemonic != cond)
12887             *obufp++ = 'r';
12888           break;
12889         case 'N':
12890           if ((prefixes & PREFIX_FWAIT) == 0)
12891             *obufp++ = 'n';
12892           else
12893             used_prefixes |= PREFIX_FWAIT;
12894           break;
12895         case 'O':
12896           USED_REX (REX_W);
12897           if (rex & REX_W)
12898             *obufp++ = 'o';
12899           else if (intel_syntax && (sizeflag & DFLAG))
12900             *obufp++ = 'q';
12901           else
12902             *obufp++ = 'd';
12903           if (!(rex & REX_W))
12904             used_prefixes |= (prefixes & PREFIX_DATA);
12905           break;
12906         case '&':
12907           if (!intel_syntax
12908               && address_mode == mode_64bit
12909               && isa64 == intel64)
12910             {
12911               *obufp++ = 'q';
12912               break;
12913             }
12914           /* Fall through.  */
12915         case 'T':
12916           if (!intel_syntax
12917               && address_mode == mode_64bit
12918               && ((sizeflag & DFLAG) || (rex & REX_W)))
12919             {
12920               *obufp++ = 'q';
12921               break;
12922             }
12923           /* Fall through.  */
12924           goto case_P;
12925         case 'P':
12926           if (l == 0 && len == 1)
12927             {
12928 case_P:
12929               if (intel_syntax)
12930                 {
12931                   if ((rex & REX_W) == 0
12932                       && (prefixes & PREFIX_DATA))
12933                     {
12934                       if ((sizeflag & DFLAG) == 0)
12935                         *obufp++ = 'w';
12936                       used_prefixes |= (prefixes & PREFIX_DATA);
12937                     }
12938                   break;
12939                 }
12940               if ((prefixes & PREFIX_DATA)
12941                   || (rex & REX_W)
12942                   || (sizeflag & SUFFIX_ALWAYS))
12943                 {
12944                   USED_REX (REX_W);
12945                   if (rex & REX_W)
12946                     *obufp++ = 'q';
12947                   else
12948                     {
12949                       if (sizeflag & DFLAG)
12950                         *obufp++ = 'l';
12951                       else
12952                         *obufp++ = 'w';
12953                       used_prefixes |= (prefixes & PREFIX_DATA);
12954                     }
12955                 }
12956             }
12957           else
12958             {
12959               if (l != 1 || len != 2 || last[0] != 'L')
12960                 {
12961                   SAVE_LAST (*p);
12962                   break;
12963                 }
12964
12965               if ((prefixes & PREFIX_DATA)
12966                   || (rex & REX_W)
12967                   || (sizeflag & SUFFIX_ALWAYS))
12968                 {
12969                   USED_REX (REX_W);
12970                   if (rex & REX_W)
12971                     *obufp++ = 'q';
12972                   else
12973                     {
12974                       if (sizeflag & DFLAG)
12975                         *obufp++ = intel_syntax ? 'd' : 'l';
12976                       else
12977                         *obufp++ = 'w';
12978                       used_prefixes |= (prefixes & PREFIX_DATA);
12979                     }
12980                 }
12981             }
12982           break;
12983         case 'U':
12984           if (intel_syntax)
12985             break;
12986           if (address_mode == mode_64bit
12987               && ((sizeflag & DFLAG) || (rex & REX_W)))
12988             {
12989               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12990                 *obufp++ = 'q';
12991               break;
12992             }
12993           /* Fall through.  */
12994           goto case_Q;
12995         case 'Q':
12996           if (l == 0 && len == 1)
12997             {
12998 case_Q:
12999               if (intel_syntax && !alt)
13000                 break;
13001               USED_REX (REX_W);
13002               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13003                 {
13004                   if (rex & REX_W)
13005                     *obufp++ = 'q';
13006                   else
13007                     {
13008                       if (sizeflag & DFLAG)
13009                         *obufp++ = intel_syntax ? 'd' : 'l';
13010                       else
13011                         *obufp++ = 'w';
13012                       used_prefixes |= (prefixes & PREFIX_DATA);
13013                     }
13014                 }
13015             }
13016           else
13017             {
13018               if (l != 1 || len != 2 || last[0] != 'L')
13019                 {
13020                   SAVE_LAST (*p);
13021                   break;
13022                 }
13023               if (intel_syntax
13024                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13025                 break;
13026               if ((rex & REX_W))
13027                 {
13028                   USED_REX (REX_W);
13029                   *obufp++ = 'q';
13030                 }
13031               else
13032                 *obufp++ = 'l';
13033             }
13034           break;
13035         case 'R':
13036           USED_REX (REX_W);
13037           if (rex & REX_W)
13038             *obufp++ = 'q';
13039           else if (sizeflag & DFLAG)
13040             {
13041               if (intel_syntax)
13042                   *obufp++ = 'd';
13043               else
13044                   *obufp++ = 'l';
13045             }
13046           else
13047             *obufp++ = 'w';
13048           if (intel_syntax && !p[1]
13049               && ((rex & REX_W) || (sizeflag & DFLAG)))
13050             *obufp++ = 'e';
13051           if (!(rex & REX_W))
13052             used_prefixes |= (prefixes & PREFIX_DATA);
13053           break;
13054         case 'V':
13055           if (l == 0 && len == 1)
13056             {
13057               if (intel_syntax)
13058                 break;
13059               if (address_mode == mode_64bit
13060                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13061                 {
13062                   if (sizeflag & SUFFIX_ALWAYS)
13063                     *obufp++ = 'q';
13064                   break;
13065                 }
13066             }
13067           else
13068             {
13069               if (l != 1
13070                   || len != 2
13071                   || last[0] != 'L')
13072                 {
13073                   SAVE_LAST (*p);
13074                   break;
13075                 }
13076
13077               if (rex & REX_W)
13078                 {
13079                   *obufp++ = 'a';
13080                   *obufp++ = 'b';
13081                   *obufp++ = 's';
13082                 }
13083             }
13084           /* Fall through.  */
13085           goto case_S;
13086         case 'S':
13087           if (l == 0 && len == 1)
13088             {
13089 case_S:
13090               if (intel_syntax)
13091                 break;
13092               if (sizeflag & SUFFIX_ALWAYS)
13093                 {
13094                   if (rex & REX_W)
13095                     *obufp++ = 'q';
13096                   else
13097                     {
13098                       if (sizeflag & DFLAG)
13099                         *obufp++ = 'l';
13100                       else
13101                         *obufp++ = 'w';
13102                       used_prefixes |= (prefixes & PREFIX_DATA);
13103                     }
13104                 }
13105             }
13106           else
13107             {
13108               if (l != 1
13109                   || len != 2
13110                   || last[0] != 'L')
13111                 {
13112                   SAVE_LAST (*p);
13113                   break;
13114                 }
13115
13116               if (address_mode == mode_64bit
13117                   && !(prefixes & PREFIX_ADDR))
13118                 {
13119                   *obufp++ = 'a';
13120                   *obufp++ = 'b';
13121                   *obufp++ = 's';
13122                 }
13123
13124               goto case_S;
13125             }
13126           break;
13127         case 'X':
13128           if (l != 0 || len != 1)
13129             {
13130               SAVE_LAST (*p);
13131               break;
13132             }
13133           if (need_vex && vex.prefix)
13134             {
13135               if (vex.prefix == DATA_PREFIX_OPCODE)
13136                 *obufp++ = 'd';
13137               else
13138                 *obufp++ = 's';
13139             }
13140           else
13141             {
13142               if (prefixes & PREFIX_DATA)
13143                 *obufp++ = 'd';
13144               else
13145                 *obufp++ = 's';
13146               used_prefixes |= (prefixes & PREFIX_DATA);
13147             }
13148           break;
13149         case 'Y':
13150           if (l == 0 && len == 1)
13151             abort ();
13152           else
13153             {
13154               if (l != 1 || len != 2 || last[0] != 'X')
13155                 {
13156                   SAVE_LAST (*p);
13157                   break;
13158                 }
13159               if (!need_vex)
13160                 abort ();
13161               if (intel_syntax
13162                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13163                 break;
13164               switch (vex.length)
13165                 {
13166                 case 128:
13167                   *obufp++ = 'x';
13168                   break;
13169                 case 256:
13170                   *obufp++ = 'y';
13171                   break;
13172                 case 512:
13173                   if (!vex.evex)
13174                 default:
13175                     abort ();
13176                 }
13177             }
13178           break;
13179         case 'W':
13180           if (l == 0 && len == 1)
13181             {
13182               /* operand size flag for cwtl, cbtw */
13183               USED_REX (REX_W);
13184               if (rex & REX_W)
13185                 {
13186                   if (intel_syntax)
13187                     *obufp++ = 'd';
13188                   else
13189                     *obufp++ = 'l';
13190                 }
13191               else if (sizeflag & DFLAG)
13192                 *obufp++ = 'w';
13193               else
13194                 *obufp++ = 'b';
13195               if (!(rex & REX_W))
13196                 used_prefixes |= (prefixes & PREFIX_DATA);
13197             }
13198           else
13199             {
13200               if (l != 1
13201                   || len != 2
13202                   || (last[0] != 'X'
13203                       && last[0] != 'L'))
13204                 {
13205                   SAVE_LAST (*p);
13206                   break;
13207                 }
13208               if (!need_vex)
13209                 abort ();
13210               if (last[0] == 'X')
13211                 *obufp++ = vex.w ? 'd': 's';
13212               else
13213                 *obufp++ = vex.w ? 'q': 'd';
13214             }
13215           break;
13216         case '^':
13217           if (intel_syntax)
13218             break;
13219           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13220             {
13221               if (sizeflag & DFLAG)
13222                 *obufp++ = 'l';
13223               else
13224                 *obufp++ = 'w';
13225               used_prefixes |= (prefixes & PREFIX_DATA);
13226             }
13227           break;
13228         case '@':
13229           if (intel_syntax)
13230             break;
13231           if (address_mode == mode_64bit
13232               && (isa64 == intel64
13233                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13234               *obufp++ = 'q';
13235           else if ((prefixes & PREFIX_DATA))
13236             {
13237               if (!(sizeflag & DFLAG))
13238                 *obufp++ = 'w';
13239               used_prefixes |= (prefixes & PREFIX_DATA);
13240             }
13241           break;
13242         }
13243       alt = 0;
13244     }
13245   *obufp = 0;
13246   mnemonicendp = obufp;
13247   return 0;
13248 }
13249
13250 static void
13251 oappend (const char *s)
13252 {
13253   obufp = stpcpy (obufp, s);
13254 }
13255
13256 static void
13257 append_seg (void)
13258 {
13259   /* Only print the active segment register.  */
13260   if (!active_seg_prefix)
13261     return;
13262
13263   used_prefixes |= active_seg_prefix;
13264   switch (active_seg_prefix)
13265     {
13266     case PREFIX_CS:
13267       oappend_maybe_intel ("%cs:");
13268       break;
13269     case PREFIX_DS:
13270       oappend_maybe_intel ("%ds:");
13271       break;
13272     case PREFIX_SS:
13273       oappend_maybe_intel ("%ss:");
13274       break;
13275     case PREFIX_ES:
13276       oappend_maybe_intel ("%es:");
13277       break;
13278     case PREFIX_FS:
13279       oappend_maybe_intel ("%fs:");
13280       break;
13281     case PREFIX_GS:
13282       oappend_maybe_intel ("%gs:");
13283       break;
13284     default:
13285       break;
13286     }
13287 }
13288
13289 static void
13290 OP_indirE (int bytemode, int sizeflag)
13291 {
13292   if (!intel_syntax)
13293     oappend ("*");
13294   OP_E (bytemode, sizeflag);
13295 }
13296
13297 static void
13298 print_operand_value (char *buf, int hex, bfd_vma disp)
13299 {
13300   if (address_mode == mode_64bit)
13301     {
13302       if (hex)
13303         {
13304           char tmp[30];
13305           int i;
13306           buf[0] = '0';
13307           buf[1] = 'x';
13308           sprintf_vma (tmp, disp);
13309           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13310           strcpy (buf + 2, tmp + i);
13311         }
13312       else
13313         {
13314           bfd_signed_vma v = disp;
13315           char tmp[30];
13316           int i;
13317           if (v < 0)
13318             {
13319               *(buf++) = '-';
13320               v = -disp;
13321               /* Check for possible overflow on 0x8000000000000000.  */
13322               if (v < 0)
13323                 {
13324                   strcpy (buf, "9223372036854775808");
13325                   return;
13326                 }
13327             }
13328           if (!v)
13329             {
13330               strcpy (buf, "0");
13331               return;
13332             }
13333
13334           i = 0;
13335           tmp[29] = 0;
13336           while (v)
13337             {
13338               tmp[28 - i] = (v % 10) + '0';
13339               v /= 10;
13340               i++;
13341             }
13342           strcpy (buf, tmp + 29 - i);
13343         }
13344     }
13345   else
13346     {
13347       if (hex)
13348         sprintf (buf, "0x%x", (unsigned int) disp);
13349       else
13350         sprintf (buf, "%d", (int) disp);
13351     }
13352 }
13353
13354 /* Put DISP in BUF as signed hex number.  */
13355
13356 static void
13357 print_displacement (char *buf, bfd_vma disp)
13358 {
13359   bfd_signed_vma val = disp;
13360   char tmp[30];
13361   int i, j = 0;
13362
13363   if (val < 0)
13364     {
13365       buf[j++] = '-';
13366       val = -disp;
13367
13368       /* Check for possible overflow.  */
13369       if (val < 0)
13370         {
13371           switch (address_mode)
13372             {
13373             case mode_64bit:
13374               strcpy (buf + j, "0x8000000000000000");
13375               break;
13376             case mode_32bit:
13377               strcpy (buf + j, "0x80000000");
13378               break;
13379             case mode_16bit:
13380               strcpy (buf + j, "0x8000");
13381               break;
13382             }
13383           return;
13384         }
13385     }
13386
13387   buf[j++] = '0';
13388   buf[j++] = 'x';
13389
13390   sprintf_vma (tmp, (bfd_vma) val);
13391   for (i = 0; tmp[i] == '0'; i++)
13392     continue;
13393   if (tmp[i] == '\0')
13394     i--;
13395   strcpy (buf + j, tmp + i);
13396 }
13397
13398 static void
13399 intel_operand_size (int bytemode, int sizeflag)
13400 {
13401   if (vex.evex
13402       && vex.b
13403       && (bytemode == x_mode
13404           || bytemode == evex_half_bcst_xmmq_mode))
13405     {
13406       if (vex.w)
13407         oappend ("QWORD PTR ");
13408       else
13409         oappend ("DWORD PTR ");
13410       return;
13411     }
13412   switch (bytemode)
13413     {
13414     case b_mode:
13415     case b_swap_mode:
13416     case dqb_mode:
13417     case db_mode:
13418       oappend ("BYTE PTR ");
13419       break;
13420     case w_mode:
13421     case dw_mode:
13422     case dqw_mode:
13423       oappend ("WORD PTR ");
13424       break;
13425     case indir_v_mode:
13426       if (address_mode == mode_64bit && isa64 == intel64)
13427         {
13428           oappend ("QWORD PTR ");
13429           break;
13430         }
13431       /* Fall through.  */
13432     case stack_v_mode:
13433       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13434         {
13435           oappend ("QWORD PTR ");
13436           break;
13437         }
13438       /* Fall through.  */
13439     case v_mode:
13440     case v_swap_mode:
13441     case dq_mode:
13442       USED_REX (REX_W);
13443       if (rex & REX_W)
13444         oappend ("QWORD PTR ");
13445       else
13446         {
13447           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13448             oappend ("DWORD PTR ");
13449           else
13450             oappend ("WORD PTR ");
13451           used_prefixes |= (prefixes & PREFIX_DATA);
13452         }
13453       break;
13454     case z_mode:
13455       if ((rex & REX_W) || (sizeflag & DFLAG))
13456         *obufp++ = 'D';
13457       oappend ("WORD PTR ");
13458       if (!(rex & REX_W))
13459         used_prefixes |= (prefixes & PREFIX_DATA);
13460       break;
13461     case a_mode:
13462       if (sizeflag & DFLAG)
13463         oappend ("QWORD PTR ");
13464       else
13465         oappend ("DWORD PTR ");
13466       used_prefixes |= (prefixes & PREFIX_DATA);
13467       break;
13468     case d_mode:
13469     case d_scalar_mode:
13470     case d_scalar_swap_mode:
13471     case d_swap_mode:
13472     case dqd_mode:
13473       oappend ("DWORD PTR ");
13474       break;
13475     case q_mode:
13476     case q_scalar_mode:
13477     case q_scalar_swap_mode:
13478     case q_swap_mode:
13479       oappend ("QWORD PTR ");
13480       break;
13481     case dqa_mode:
13482     case m_mode:
13483       if (address_mode == mode_64bit)
13484         oappend ("QWORD PTR ");
13485       else
13486         oappend ("DWORD PTR ");
13487       break;
13488     case f_mode:
13489       if (sizeflag & DFLAG)
13490         oappend ("FWORD PTR ");
13491       else
13492         oappend ("DWORD PTR ");
13493       used_prefixes |= (prefixes & PREFIX_DATA);
13494       break;
13495     case t_mode:
13496       oappend ("TBYTE PTR ");
13497       break;
13498     case x_mode:
13499     case x_swap_mode:
13500     case evex_x_gscat_mode:
13501     case evex_x_nobcst_mode:
13502     case b_scalar_mode:
13503     case w_scalar_mode:
13504       if (need_vex)
13505         {
13506           switch (vex.length)
13507             {
13508             case 128:
13509               oappend ("XMMWORD PTR ");
13510               break;
13511             case 256:
13512               oappend ("YMMWORD PTR ");
13513               break;
13514             case 512:
13515               oappend ("ZMMWORD PTR ");
13516               break;
13517             default:
13518               abort ();
13519             }
13520         }
13521       else
13522         oappend ("XMMWORD PTR ");
13523       break;
13524     case xmm_mode:
13525       oappend ("XMMWORD PTR ");
13526       break;
13527     case ymm_mode:
13528       oappend ("YMMWORD PTR ");
13529       break;
13530     case xmmq_mode:
13531     case evex_half_bcst_xmmq_mode:
13532       if (!need_vex)
13533         abort ();
13534
13535       switch (vex.length)
13536         {
13537         case 128:
13538           oappend ("QWORD PTR ");
13539           break;
13540         case 256:
13541           oappend ("XMMWORD PTR ");
13542           break;
13543         case 512:
13544           oappend ("YMMWORD PTR ");
13545           break;
13546         default:
13547           abort ();
13548         }
13549       break;
13550     case xmm_mb_mode:
13551       if (!need_vex)
13552         abort ();
13553
13554       switch (vex.length)
13555         {
13556         case 128:
13557         case 256:
13558         case 512:
13559           oappend ("BYTE PTR ");
13560           break;
13561         default:
13562           abort ();
13563         }
13564       break;
13565     case xmm_mw_mode:
13566       if (!need_vex)
13567         abort ();
13568
13569       switch (vex.length)
13570         {
13571         case 128:
13572         case 256:
13573         case 512:
13574           oappend ("WORD PTR ");
13575           break;
13576         default:
13577           abort ();
13578         }
13579       break;
13580     case xmm_md_mode:
13581       if (!need_vex)
13582         abort ();
13583
13584       switch (vex.length)
13585         {
13586         case 128:
13587         case 256:
13588         case 512:
13589           oappend ("DWORD PTR ");
13590           break;
13591         default:
13592           abort ();
13593         }
13594       break;
13595     case xmm_mq_mode:
13596       if (!need_vex)
13597         abort ();
13598
13599       switch (vex.length)
13600         {
13601         case 128:
13602         case 256:
13603         case 512:
13604           oappend ("QWORD PTR ");
13605           break;
13606         default:
13607           abort ();
13608         }
13609       break;
13610     case xmmdw_mode:
13611       if (!need_vex)
13612         abort ();
13613
13614       switch (vex.length)
13615         {
13616         case 128:
13617           oappend ("WORD PTR ");
13618           break;
13619         case 256:
13620           oappend ("DWORD PTR ");
13621           break;
13622         case 512:
13623           oappend ("QWORD PTR ");
13624           break;
13625         default:
13626           abort ();
13627         }
13628       break;
13629     case xmmqd_mode:
13630       if (!need_vex)
13631         abort ();
13632
13633       switch (vex.length)
13634         {
13635         case 128:
13636           oappend ("DWORD PTR ");
13637           break;
13638         case 256:
13639           oappend ("QWORD PTR ");
13640           break;
13641         case 512:
13642           oappend ("XMMWORD PTR ");
13643           break;
13644         default:
13645           abort ();
13646         }
13647       break;
13648     case ymmq_mode:
13649       if (!need_vex)
13650         abort ();
13651
13652       switch (vex.length)
13653         {
13654         case 128:
13655           oappend ("QWORD PTR ");
13656           break;
13657         case 256:
13658           oappend ("YMMWORD PTR ");
13659           break;
13660         case 512:
13661           oappend ("ZMMWORD PTR ");
13662           break;
13663         default:
13664           abort ();
13665         }
13666       break;
13667     case ymmxmm_mode:
13668       if (!need_vex)
13669         abort ();
13670
13671       switch (vex.length)
13672         {
13673         case 128:
13674         case 256:
13675           oappend ("XMMWORD PTR ");
13676           break;
13677         default:
13678           abort ();
13679         }
13680       break;
13681     case o_mode:
13682       oappend ("OWORD PTR ");
13683       break;
13684     case xmm_mdq_mode:
13685     case vex_w_dq_mode:
13686     case vex_scalar_w_dq_mode:
13687       if (!need_vex)
13688         abort ();
13689
13690       if (vex.w)
13691         oappend ("QWORD PTR ");
13692       else
13693         oappend ("DWORD PTR ");
13694       break;
13695     case vex_vsib_d_w_dq_mode:
13696     case vex_vsib_q_w_dq_mode:
13697       if (!need_vex)
13698         abort ();
13699
13700       if (!vex.evex)
13701         {
13702           if (vex.w)
13703             oappend ("QWORD PTR ");
13704           else
13705             oappend ("DWORD PTR ");
13706         }
13707       else
13708         {
13709           switch (vex.length)
13710             {
13711             case 128:
13712               oappend ("XMMWORD PTR ");
13713               break;
13714             case 256:
13715               oappend ("YMMWORD PTR ");
13716               break;
13717             case 512:
13718               oappend ("ZMMWORD PTR ");
13719               break;
13720             default:
13721               abort ();
13722             }
13723         }
13724       break;
13725     case vex_vsib_q_w_d_mode:
13726     case vex_vsib_d_w_d_mode:
13727       if (!need_vex || !vex.evex)
13728         abort ();
13729
13730       switch (vex.length)
13731         {
13732         case 128:
13733           oappend ("QWORD PTR ");
13734           break;
13735         case 256:
13736           oappend ("XMMWORD PTR ");
13737           break;
13738         case 512:
13739           oappend ("YMMWORD PTR ");
13740           break;
13741         default:
13742           abort ();
13743         }
13744
13745       break;
13746     case mask_bd_mode:
13747       if (!need_vex || vex.length != 128)
13748         abort ();
13749       if (vex.w)
13750         oappend ("DWORD PTR ");
13751       else
13752         oappend ("BYTE PTR ");
13753       break;
13754     case mask_mode:
13755       if (!need_vex)
13756         abort ();
13757       if (vex.w)
13758         oappend ("QWORD PTR ");
13759       else
13760         oappend ("WORD PTR ");
13761       break;
13762     case v_bnd_mode:
13763     case v_bndmk_mode:
13764     default:
13765       break;
13766     }
13767 }
13768
13769 static void
13770 OP_E_register (int bytemode, int sizeflag)
13771 {
13772   int reg = modrm.rm;
13773   const char **names;
13774
13775   USED_REX (REX_B);
13776   if ((rex & REX_B))
13777     reg += 8;
13778
13779   if ((sizeflag & SUFFIX_ALWAYS)
13780       && (bytemode == b_swap_mode
13781           || bytemode == bnd_swap_mode
13782           || bytemode == v_swap_mode))
13783     swap_operand ();
13784
13785   switch (bytemode)
13786     {
13787     case b_mode:
13788     case b_swap_mode:
13789       USED_REX (0);
13790       if (rex)
13791         names = names8rex;
13792       else
13793         names = names8;
13794       break;
13795     case w_mode:
13796       names = names16;
13797       break;
13798     case d_mode:
13799     case dw_mode:
13800     case db_mode:
13801       names = names32;
13802       break;
13803     case q_mode:
13804       names = names64;
13805       break;
13806     case m_mode:
13807     case v_bnd_mode:
13808       names = address_mode == mode_64bit ? names64 : names32;
13809       break;
13810     case bnd_mode:
13811     case bnd_swap_mode:
13812       if (reg > 0x3)
13813         {
13814           oappend ("(bad)");
13815           return;
13816         }
13817       names = names_bnd;
13818       break;
13819     case indir_v_mode:
13820       if (address_mode == mode_64bit && isa64 == intel64)
13821         {
13822           names = names64;
13823           break;
13824         }
13825       /* Fall through.  */
13826     case stack_v_mode:
13827       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13828         {
13829           names = names64;
13830           break;
13831         }
13832       bytemode = v_mode;
13833       /* Fall through.  */
13834     case v_mode:
13835     case v_swap_mode:
13836     case dq_mode:
13837     case dqb_mode:
13838     case dqd_mode:
13839     case dqw_mode:
13840     case dqa_mode:
13841       USED_REX (REX_W);
13842       if (rex & REX_W)
13843         names = names64;
13844       else
13845         {
13846           if ((sizeflag & DFLAG)
13847               || (bytemode != v_mode
13848                   && bytemode != v_swap_mode))
13849             names = names32;
13850           else
13851             names = names16;
13852           used_prefixes |= (prefixes & PREFIX_DATA);
13853         }
13854       break;
13855     case va_mode:
13856       names = (address_mode == mode_64bit
13857                ? names64 : names32);
13858       if (!(prefixes & PREFIX_ADDR))
13859         names = (address_mode == mode_16bit
13860                      ? names16 : names);
13861       else
13862         {
13863           /* Remove "addr16/addr32".  */
13864           all_prefixes[last_addr_prefix] = 0;
13865           names = (address_mode != mode_32bit
13866                        ? names32 : names16);
13867           used_prefixes |= PREFIX_ADDR;
13868         }
13869       break;
13870     case mask_bd_mode:
13871     case mask_mode:
13872       if (reg > 0x7)
13873         {
13874           oappend ("(bad)");
13875           return;
13876         }
13877       names = names_mask;
13878       break;
13879     case 0:
13880       return;
13881     default:
13882       oappend (INTERNAL_DISASSEMBLER_ERROR);
13883       return;
13884     }
13885   oappend (names[reg]);
13886 }
13887
13888 static void
13889 OP_E_memory (int bytemode, int sizeflag)
13890 {
13891   bfd_vma disp = 0;
13892   int add = (rex & REX_B) ? 8 : 0;
13893   int riprel = 0;
13894   int shift;
13895
13896   if (vex.evex)
13897     {
13898       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13899       if (vex.b
13900           && bytemode != x_mode
13901           && bytemode != xmmq_mode
13902           && bytemode != evex_half_bcst_xmmq_mode)
13903         {
13904           BadOp ();
13905           return;
13906         }
13907       switch (bytemode)
13908         {
13909         case dqw_mode:
13910         case dw_mode:
13911           shift = 1;
13912           break;
13913         case dqb_mode:
13914         case db_mode:
13915           shift = 0;
13916           break;
13917         case dq_mode:
13918           if (address_mode != mode_64bit)
13919             {
13920               shift = 2;
13921               break;
13922             }
13923             /* fall through */
13924         case vex_vsib_d_w_dq_mode:
13925         case vex_vsib_d_w_d_mode:
13926         case vex_vsib_q_w_dq_mode:
13927         case vex_vsib_q_w_d_mode:
13928         case evex_x_gscat_mode:
13929         case xmm_mdq_mode:
13930           shift = vex.w ? 3 : 2;
13931           break;
13932         case x_mode:
13933         case evex_half_bcst_xmmq_mode:
13934         case xmmq_mode:
13935           if (vex.b)
13936             {
13937               shift = vex.w ? 3 : 2;
13938               break;
13939             }
13940           /* Fall through.  */
13941         case xmmqd_mode:
13942         case xmmdw_mode:
13943         case ymmq_mode:
13944         case evex_x_nobcst_mode:
13945         case x_swap_mode:
13946           switch (vex.length)
13947             {
13948             case 128:
13949               shift = 4;
13950               break;
13951             case 256:
13952               shift = 5;
13953               break;
13954             case 512:
13955               shift = 6;
13956               break;
13957             default:
13958               abort ();
13959             }
13960           break;
13961         case ymm_mode:
13962           shift = 5;
13963           break;
13964         case xmm_mode:
13965           shift = 4;
13966           break;
13967         case xmm_mq_mode:
13968         case q_mode:
13969         case q_scalar_mode:
13970         case q_swap_mode:
13971         case q_scalar_swap_mode:
13972           shift = 3;
13973           break;
13974         case dqd_mode:
13975         case xmm_md_mode:
13976         case d_mode:
13977         case d_scalar_mode:
13978         case d_swap_mode:
13979         case d_scalar_swap_mode:
13980           shift = 2;
13981           break;
13982         case w_scalar_mode:
13983         case xmm_mw_mode:
13984           shift = 1;
13985           break;
13986         case b_scalar_mode:
13987         case xmm_mb_mode:
13988           shift = 0;
13989           break;
13990         case dqa_mode:
13991           shift = address_mode == mode_64bit ? 3 : 2;
13992           break;
13993         default:
13994           abort ();
13995         }
13996       /* Make necessary corrections to shift for modes that need it.
13997          For these modes we currently have shift 4, 5 or 6 depending on
13998          vex.length (it corresponds to xmmword, ymmword or zmmword
13999          operand).  We might want to make it 3, 4 or 5 (e.g. for
14000          xmmq_mode).  In case of broadcast enabled the corrections
14001          aren't needed, as element size is always 32 or 64 bits.  */
14002       if (!vex.b
14003           && (bytemode == xmmq_mode
14004               || bytemode == evex_half_bcst_xmmq_mode))
14005         shift -= 1;
14006       else if (bytemode == xmmqd_mode)
14007         shift -= 2;
14008       else if (bytemode == xmmdw_mode)
14009         shift -= 3;
14010       else if (bytemode == ymmq_mode && vex.length == 128)
14011         shift -= 1;
14012     }
14013   else
14014     shift = 0;
14015
14016   USED_REX (REX_B);
14017   if (intel_syntax)
14018     intel_operand_size (bytemode, sizeflag);
14019   append_seg ();
14020
14021   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14022     {
14023       /* 32/64 bit address mode */
14024       int havedisp;
14025       int havesib;
14026       int havebase;
14027       int haveindex;
14028       int needindex;
14029       int needaddr32;
14030       int base, rbase;
14031       int vindex = 0;
14032       int scale = 0;
14033       int addr32flag = !((sizeflag & AFLAG)
14034                          || bytemode == v_bnd_mode
14035                          || bytemode == v_bndmk_mode
14036                          || bytemode == bnd_mode
14037                          || bytemode == bnd_swap_mode);
14038       const char **indexes64 = names64;
14039       const char **indexes32 = names32;
14040
14041       havesib = 0;
14042       havebase = 1;
14043       haveindex = 0;
14044       base = modrm.rm;
14045
14046       if (base == 4)
14047         {
14048           havesib = 1;
14049           vindex = sib.index;
14050           USED_REX (REX_X);
14051           if (rex & REX_X)
14052             vindex += 8;
14053           switch (bytemode)
14054             {
14055             case vex_vsib_d_w_dq_mode:
14056             case vex_vsib_d_w_d_mode:
14057             case vex_vsib_q_w_dq_mode:
14058             case vex_vsib_q_w_d_mode:
14059               if (!need_vex)
14060                 abort ();
14061               if (vex.evex)
14062                 {
14063                   if (!vex.v)
14064                     vindex += 16;
14065                 }
14066
14067               haveindex = 1;
14068               switch (vex.length)
14069                 {
14070                 case 128:
14071                   indexes64 = indexes32 = names_xmm;
14072                   break;
14073                 case 256:
14074                   if (!vex.w
14075                       || bytemode == vex_vsib_q_w_dq_mode
14076                       || bytemode == vex_vsib_q_w_d_mode)
14077                     indexes64 = indexes32 = names_ymm;
14078                   else
14079                     indexes64 = indexes32 = names_xmm;
14080                   break;
14081                 case 512:
14082                   if (!vex.w
14083                       || bytemode == vex_vsib_q_w_dq_mode
14084                       || bytemode == vex_vsib_q_w_d_mode)
14085                     indexes64 = indexes32 = names_zmm;
14086                   else
14087                     indexes64 = indexes32 = names_ymm;
14088                   break;
14089                 default:
14090                   abort ();
14091                 }
14092               break;
14093             default:
14094               haveindex = vindex != 4;
14095               break;
14096             }
14097           scale = sib.scale;
14098           base = sib.base;
14099           codep++;
14100         }
14101       rbase = base + add;
14102
14103       switch (modrm.mod)
14104         {
14105         case 0:
14106           if (base == 5)
14107             {
14108               havebase = 0;
14109               if (address_mode == mode_64bit && !havesib)
14110                 riprel = 1;
14111               disp = get32s ();
14112               if (riprel && bytemode == v_bndmk_mode)
14113                 {
14114                   oappend ("(bad)");
14115                   return;
14116                 }
14117             }
14118           break;
14119         case 1:
14120           FETCH_DATA (the_info, codep + 1);
14121           disp = *codep++;
14122           if ((disp & 0x80) != 0)
14123             disp -= 0x100;
14124           if (vex.evex && shift > 0)
14125             disp <<= shift;
14126           break;
14127         case 2:
14128           disp = get32s ();
14129           break;
14130         }
14131
14132       needindex = 0;
14133       needaddr32 = 0;
14134       if (havesib
14135           && !havebase
14136           && !haveindex
14137           && address_mode != mode_16bit)
14138         {
14139           if (address_mode == mode_64bit)
14140             {
14141               /* Display eiz instead of addr32.  */
14142               needindex = addr32flag;
14143               needaddr32 = 1;
14144             }
14145           else
14146             {
14147               /* In 32-bit mode, we need index register to tell [offset]
14148                  from [eiz*1 + offset].  */
14149               needindex = 1;
14150             }
14151         }
14152
14153       havedisp = (havebase
14154                   || needindex
14155                   || (havesib && (haveindex || scale != 0)));
14156
14157       if (!intel_syntax)
14158         if (modrm.mod != 0 || base == 5)
14159           {
14160             if (havedisp || riprel)
14161               print_displacement (scratchbuf, disp);
14162             else
14163               print_operand_value (scratchbuf, 1, disp);
14164             oappend (scratchbuf);
14165             if (riprel)
14166               {
14167                 set_op (disp, 1);
14168                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14169               }
14170           }
14171
14172       if ((havebase || haveindex || needaddr32 || riprel)
14173           && (bytemode != v_bnd_mode)
14174           && (bytemode != v_bndmk_mode)
14175           && (bytemode != bnd_mode)
14176           && (bytemode != bnd_swap_mode))
14177         used_prefixes |= PREFIX_ADDR;
14178
14179       if (havedisp || (intel_syntax && riprel))
14180         {
14181           *obufp++ = open_char;
14182           if (intel_syntax && riprel)
14183             {
14184               set_op (disp, 1);
14185               oappend (!addr32flag ? "rip" : "eip");
14186             }
14187           *obufp = '\0';
14188           if (havebase)
14189             oappend (address_mode == mode_64bit && !addr32flag
14190                      ? names64[rbase] : names32[rbase]);
14191           if (havesib)
14192             {
14193               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14194                  print index to tell base + index from base.  */
14195               if (scale != 0
14196                   || needindex
14197                   || haveindex
14198                   || (havebase && base != ESP_REG_NUM))
14199                 {
14200                   if (!intel_syntax || havebase)
14201                     {
14202                       *obufp++ = separator_char;
14203                       *obufp = '\0';
14204                     }
14205                   if (haveindex)
14206                     oappend (address_mode == mode_64bit && !addr32flag
14207                              ? indexes64[vindex] : indexes32[vindex]);
14208                   else
14209                     oappend (address_mode == mode_64bit && !addr32flag
14210                              ? index64 : index32);
14211
14212                   *obufp++ = scale_char;
14213                   *obufp = '\0';
14214                   sprintf (scratchbuf, "%d", 1 << scale);
14215                   oappend (scratchbuf);
14216                 }
14217             }
14218           if (intel_syntax
14219               && (disp || modrm.mod != 0 || base == 5))
14220             {
14221               if (!havedisp || (bfd_signed_vma) disp >= 0)
14222                 {
14223                   *obufp++ = '+';
14224                   *obufp = '\0';
14225                 }
14226               else if (modrm.mod != 1 && disp != -disp)
14227                 {
14228                   *obufp++ = '-';
14229                   *obufp = '\0';
14230                   disp = - (bfd_signed_vma) disp;
14231                 }
14232
14233               if (havedisp)
14234                 print_displacement (scratchbuf, disp);
14235               else
14236                 print_operand_value (scratchbuf, 1, disp);
14237               oappend (scratchbuf);
14238             }
14239
14240           *obufp++ = close_char;
14241           *obufp = '\0';
14242         }
14243       else if (intel_syntax)
14244         {
14245           if (modrm.mod != 0 || base == 5)
14246             {
14247               if (!active_seg_prefix)
14248                 {
14249                   oappend (names_seg[ds_reg - es_reg]);
14250                   oappend (":");
14251                 }
14252               print_operand_value (scratchbuf, 1, disp);
14253               oappend (scratchbuf);
14254             }
14255         }
14256     }
14257   else
14258     {
14259       /* 16 bit address mode */
14260       used_prefixes |= prefixes & PREFIX_ADDR;
14261       switch (modrm.mod)
14262         {
14263         case 0:
14264           if (modrm.rm == 6)
14265             {
14266               disp = get16 ();
14267               if ((disp & 0x8000) != 0)
14268                 disp -= 0x10000;
14269             }
14270           break;
14271         case 1:
14272           FETCH_DATA (the_info, codep + 1);
14273           disp = *codep++;
14274           if ((disp & 0x80) != 0)
14275             disp -= 0x100;
14276           if (vex.evex && shift > 0)
14277             disp <<= shift;
14278           break;
14279         case 2:
14280           disp = get16 ();
14281           if ((disp & 0x8000) != 0)
14282             disp -= 0x10000;
14283           break;
14284         }
14285
14286       if (!intel_syntax)
14287         if (modrm.mod != 0 || modrm.rm == 6)
14288           {
14289             print_displacement (scratchbuf, disp);
14290             oappend (scratchbuf);
14291           }
14292
14293       if (modrm.mod != 0 || modrm.rm != 6)
14294         {
14295           *obufp++ = open_char;
14296           *obufp = '\0';
14297           oappend (index16[modrm.rm]);
14298           if (intel_syntax
14299               && (disp || modrm.mod != 0 || modrm.rm == 6))
14300             {
14301               if ((bfd_signed_vma) disp >= 0)
14302                 {
14303                   *obufp++ = '+';
14304                   *obufp = '\0';
14305                 }
14306               else if (modrm.mod != 1)
14307                 {
14308                   *obufp++ = '-';
14309                   *obufp = '\0';
14310                   disp = - (bfd_signed_vma) disp;
14311                 }
14312
14313               print_displacement (scratchbuf, disp);
14314               oappend (scratchbuf);
14315             }
14316
14317           *obufp++ = close_char;
14318           *obufp = '\0';
14319         }
14320       else if (intel_syntax)
14321         {
14322           if (!active_seg_prefix)
14323             {
14324               oappend (names_seg[ds_reg - es_reg]);
14325               oappend (":");
14326             }
14327           print_operand_value (scratchbuf, 1, disp & 0xffff);
14328           oappend (scratchbuf);
14329         }
14330     }
14331   if (vex.evex && vex.b
14332       && (bytemode == x_mode
14333           || bytemode == xmmq_mode
14334           || bytemode == evex_half_bcst_xmmq_mode))
14335     {
14336       if (vex.w
14337           || bytemode == xmmq_mode
14338           || bytemode == evex_half_bcst_xmmq_mode)
14339         {
14340           switch (vex.length)
14341             {
14342             case 128:
14343               oappend ("{1to2}");
14344               break;
14345             case 256:
14346               oappend ("{1to4}");
14347               break;
14348             case 512:
14349               oappend ("{1to8}");
14350               break;
14351             default:
14352               abort ();
14353             }
14354         }
14355       else
14356         {
14357           switch (vex.length)
14358             {
14359             case 128:
14360               oappend ("{1to4}");
14361               break;
14362             case 256:
14363               oappend ("{1to8}");
14364               break;
14365             case 512:
14366               oappend ("{1to16}");
14367               break;
14368             default:
14369               abort ();
14370             }
14371         }
14372     }
14373 }
14374
14375 static void
14376 OP_E (int bytemode, int sizeflag)
14377 {
14378   /* Skip mod/rm byte.  */
14379   MODRM_CHECK;
14380   codep++;
14381
14382   if (modrm.mod == 3)
14383     OP_E_register (bytemode, sizeflag);
14384   else
14385     OP_E_memory (bytemode, sizeflag);
14386 }
14387
14388 static void
14389 OP_G (int bytemode, int sizeflag)
14390 {
14391   int add = 0;
14392   const char **names;
14393   USED_REX (REX_R);
14394   if (rex & REX_R)
14395     add += 8;
14396   switch (bytemode)
14397     {
14398     case b_mode:
14399       USED_REX (0);
14400       if (rex)
14401         oappend (names8rex[modrm.reg + add]);
14402       else
14403         oappend (names8[modrm.reg + add]);
14404       break;
14405     case w_mode:
14406       oappend (names16[modrm.reg + add]);
14407       break;
14408     case d_mode:
14409     case db_mode:
14410     case dw_mode:
14411       oappend (names32[modrm.reg + add]);
14412       break;
14413     case q_mode:
14414       oappend (names64[modrm.reg + add]);
14415       break;
14416     case bnd_mode:
14417       if (modrm.reg > 0x3)
14418         {
14419           oappend ("(bad)");
14420           return;
14421         }
14422       oappend (names_bnd[modrm.reg]);
14423       break;
14424     case v_mode:
14425     case dq_mode:
14426     case dqb_mode:
14427     case dqd_mode:
14428     case dqw_mode:
14429       USED_REX (REX_W);
14430       if (rex & REX_W)
14431         oappend (names64[modrm.reg + add]);
14432       else
14433         {
14434           if ((sizeflag & DFLAG) || bytemode != v_mode)
14435             oappend (names32[modrm.reg + add]);
14436           else
14437             oappend (names16[modrm.reg + add]);
14438           used_prefixes |= (prefixes & PREFIX_DATA);
14439         }
14440       break;
14441     case va_mode:
14442       names = (address_mode == mode_64bit
14443                ? names64 : names32);
14444       if (!(prefixes & PREFIX_ADDR))
14445         {
14446           if (address_mode == mode_16bit)
14447             names = names16;
14448         }
14449       else
14450         {
14451           /* Remove "addr16/addr32".  */
14452           all_prefixes[last_addr_prefix] = 0;
14453           names = (address_mode != mode_32bit
14454                        ? names32 : names16);
14455           used_prefixes |= PREFIX_ADDR;
14456         }
14457       oappend (names[modrm.reg + add]);
14458       break;
14459     case m_mode:
14460       if (address_mode == mode_64bit)
14461         oappend (names64[modrm.reg + add]);
14462       else
14463         oappend (names32[modrm.reg + add]);
14464       break;
14465     case mask_bd_mode:
14466     case mask_mode:
14467       if ((modrm.reg + add) > 0x7)
14468         {
14469           oappend ("(bad)");
14470           return;
14471         }
14472       oappend (names_mask[modrm.reg + add]);
14473       break;
14474     default:
14475       oappend (INTERNAL_DISASSEMBLER_ERROR);
14476       break;
14477     }
14478 }
14479
14480 static bfd_vma
14481 get64 (void)
14482 {
14483   bfd_vma x;
14484 #ifdef BFD64
14485   unsigned int a;
14486   unsigned int b;
14487
14488   FETCH_DATA (the_info, codep + 8);
14489   a = *codep++ & 0xff;
14490   a |= (*codep++ & 0xff) << 8;
14491   a |= (*codep++ & 0xff) << 16;
14492   a |= (*codep++ & 0xffu) << 24;
14493   b = *codep++ & 0xff;
14494   b |= (*codep++ & 0xff) << 8;
14495   b |= (*codep++ & 0xff) << 16;
14496   b |= (*codep++ & 0xffu) << 24;
14497   x = a + ((bfd_vma) b << 32);
14498 #else
14499   abort ();
14500   x = 0;
14501 #endif
14502   return x;
14503 }
14504
14505 static bfd_signed_vma
14506 get32 (void)
14507 {
14508   bfd_signed_vma x = 0;
14509
14510   FETCH_DATA (the_info, codep + 4);
14511   x = *codep++ & (bfd_signed_vma) 0xff;
14512   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14513   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14514   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14515   return x;
14516 }
14517
14518 static bfd_signed_vma
14519 get32s (void)
14520 {
14521   bfd_signed_vma x = 0;
14522
14523   FETCH_DATA (the_info, codep + 4);
14524   x = *codep++ & (bfd_signed_vma) 0xff;
14525   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14526   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14527   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14528
14529   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14530
14531   return x;
14532 }
14533
14534 static int
14535 get16 (void)
14536 {
14537   int x = 0;
14538
14539   FETCH_DATA (the_info, codep + 2);
14540   x = *codep++ & 0xff;
14541   x |= (*codep++ & 0xff) << 8;
14542   return x;
14543 }
14544
14545 static void
14546 set_op (bfd_vma op, int riprel)
14547 {
14548   op_index[op_ad] = op_ad;
14549   if (address_mode == mode_64bit)
14550     {
14551       op_address[op_ad] = op;
14552       op_riprel[op_ad] = riprel;
14553     }
14554   else
14555     {
14556       /* Mask to get a 32-bit address.  */
14557       op_address[op_ad] = op & 0xffffffff;
14558       op_riprel[op_ad] = riprel & 0xffffffff;
14559     }
14560 }
14561
14562 static void
14563 OP_REG (int code, int sizeflag)
14564 {
14565   const char *s;
14566   int add;
14567
14568   switch (code)
14569     {
14570     case es_reg: case ss_reg: case cs_reg:
14571     case ds_reg: case fs_reg: case gs_reg:
14572       oappend (names_seg[code - es_reg]);
14573       return;
14574     }
14575
14576   USED_REX (REX_B);
14577   if (rex & REX_B)
14578     add = 8;
14579   else
14580     add = 0;
14581
14582   switch (code)
14583     {
14584     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14585     case sp_reg: case bp_reg: case si_reg: case di_reg:
14586       s = names16[code - ax_reg + add];
14587       break;
14588     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14589     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14590       USED_REX (0);
14591       if (rex)
14592         s = names8rex[code - al_reg + add];
14593       else
14594         s = names8[code - al_reg];
14595       break;
14596     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14597     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14598       if (address_mode == mode_64bit
14599           && ((sizeflag & DFLAG) || (rex & REX_W)))
14600         {
14601           s = names64[code - rAX_reg + add];
14602           break;
14603         }
14604       code += eAX_reg - rAX_reg;
14605       /* Fall through.  */
14606     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14607     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14608       USED_REX (REX_W);
14609       if (rex & REX_W)
14610         s = names64[code - eAX_reg + add];
14611       else
14612         {
14613           if (sizeflag & DFLAG)
14614             s = names32[code - eAX_reg + add];
14615           else
14616             s = names16[code - eAX_reg + add];
14617           used_prefixes |= (prefixes & PREFIX_DATA);
14618         }
14619       break;
14620     default:
14621       s = INTERNAL_DISASSEMBLER_ERROR;
14622       break;
14623     }
14624   oappend (s);
14625 }
14626
14627 static void
14628 OP_IMREG (int code, int sizeflag)
14629 {
14630   const char *s;
14631
14632   switch (code)
14633     {
14634     case indir_dx_reg:
14635       if (intel_syntax)
14636         s = "dx";
14637       else
14638         s = "(%dx)";
14639       break;
14640     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14641     case sp_reg: case bp_reg: case si_reg: case di_reg:
14642       s = names16[code - ax_reg];
14643       break;
14644     case es_reg: case ss_reg: case cs_reg:
14645     case ds_reg: case fs_reg: case gs_reg:
14646       s = names_seg[code - es_reg];
14647       break;
14648     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14649     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14650       USED_REX (0);
14651       if (rex)
14652         s = names8rex[code - al_reg];
14653       else
14654         s = names8[code - al_reg];
14655       break;
14656     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14657     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14658       USED_REX (REX_W);
14659       if (rex & REX_W)
14660         s = names64[code - eAX_reg];
14661       else
14662         {
14663           if (sizeflag & DFLAG)
14664             s = names32[code - eAX_reg];
14665           else
14666             s = names16[code - eAX_reg];
14667           used_prefixes |= (prefixes & PREFIX_DATA);
14668         }
14669       break;
14670     case z_mode_ax_reg:
14671       if ((rex & REX_W) || (sizeflag & DFLAG))
14672         s = *names32;
14673       else
14674         s = *names16;
14675       if (!(rex & REX_W))
14676         used_prefixes |= (prefixes & PREFIX_DATA);
14677       break;
14678     default:
14679       s = INTERNAL_DISASSEMBLER_ERROR;
14680       break;
14681     }
14682   oappend (s);
14683 }
14684
14685 static void
14686 OP_I (int bytemode, int sizeflag)
14687 {
14688   bfd_signed_vma op;
14689   bfd_signed_vma mask = -1;
14690
14691   switch (bytemode)
14692     {
14693     case b_mode:
14694       FETCH_DATA (the_info, codep + 1);
14695       op = *codep++;
14696       mask = 0xff;
14697       break;
14698     case q_mode:
14699       if (address_mode == mode_64bit)
14700         {
14701           op = get32s ();
14702           break;
14703         }
14704       /* Fall through.  */
14705     case v_mode:
14706       USED_REX (REX_W);
14707       if (rex & REX_W)
14708         op = get32s ();
14709       else
14710         {
14711           if (sizeflag & DFLAG)
14712             {
14713               op = get32 ();
14714               mask = 0xffffffff;
14715             }
14716           else
14717             {
14718               op = get16 ();
14719               mask = 0xfffff;
14720             }
14721           used_prefixes |= (prefixes & PREFIX_DATA);
14722         }
14723       break;
14724     case w_mode:
14725       mask = 0xfffff;
14726       op = get16 ();
14727       break;
14728     case const_1_mode:
14729       if (intel_syntax)
14730         oappend ("1");
14731       return;
14732     default:
14733       oappend (INTERNAL_DISASSEMBLER_ERROR);
14734       return;
14735     }
14736
14737   op &= mask;
14738   scratchbuf[0] = '$';
14739   print_operand_value (scratchbuf + 1, 1, op);
14740   oappend_maybe_intel (scratchbuf);
14741   scratchbuf[0] = '\0';
14742 }
14743
14744 static void
14745 OP_I64 (int bytemode, int sizeflag)
14746 {
14747   bfd_signed_vma op;
14748   bfd_signed_vma mask = -1;
14749
14750   if (address_mode != mode_64bit)
14751     {
14752       OP_I (bytemode, sizeflag);
14753       return;
14754     }
14755
14756   switch (bytemode)
14757     {
14758     case b_mode:
14759       FETCH_DATA (the_info, codep + 1);
14760       op = *codep++;
14761       mask = 0xff;
14762       break;
14763     case v_mode:
14764       USED_REX (REX_W);
14765       if (rex & REX_W)
14766         op = get64 ();
14767       else
14768         {
14769           if (sizeflag & DFLAG)
14770             {
14771               op = get32 ();
14772               mask = 0xffffffff;
14773             }
14774           else
14775             {
14776               op = get16 ();
14777               mask = 0xfffff;
14778             }
14779           used_prefixes |= (prefixes & PREFIX_DATA);
14780         }
14781       break;
14782     case w_mode:
14783       mask = 0xfffff;
14784       op = get16 ();
14785       break;
14786     default:
14787       oappend (INTERNAL_DISASSEMBLER_ERROR);
14788       return;
14789     }
14790
14791   op &= mask;
14792   scratchbuf[0] = '$';
14793   print_operand_value (scratchbuf + 1, 1, op);
14794   oappend_maybe_intel (scratchbuf);
14795   scratchbuf[0] = '\0';
14796 }
14797
14798 static void
14799 OP_sI (int bytemode, int sizeflag)
14800 {
14801   bfd_signed_vma op;
14802
14803   switch (bytemode)
14804     {
14805     case b_mode:
14806     case b_T_mode:
14807       FETCH_DATA (the_info, codep + 1);
14808       op = *codep++;
14809       if ((op & 0x80) != 0)
14810         op -= 0x100;
14811       if (bytemode == b_T_mode)
14812         {
14813           if (address_mode != mode_64bit
14814               || !((sizeflag & DFLAG) || (rex & REX_W)))
14815             {
14816               /* The operand-size prefix is overridden by a REX prefix.  */
14817               if ((sizeflag & DFLAG) || (rex & REX_W))
14818                 op &= 0xffffffff;
14819               else
14820                 op &= 0xffff;
14821           }
14822         }
14823       else
14824         {
14825           if (!(rex & REX_W))
14826             {
14827               if (sizeflag & DFLAG)
14828                 op &= 0xffffffff;
14829               else
14830                 op &= 0xffff;
14831             }
14832         }
14833       break;
14834     case v_mode:
14835       /* The operand-size prefix is overridden by a REX prefix.  */
14836       if ((sizeflag & DFLAG) || (rex & REX_W))
14837         op = get32s ();
14838       else
14839         op = get16 ();
14840       break;
14841     default:
14842       oappend (INTERNAL_DISASSEMBLER_ERROR);
14843       return;
14844     }
14845
14846   scratchbuf[0] = '$';
14847   print_operand_value (scratchbuf + 1, 1, op);
14848   oappend_maybe_intel (scratchbuf);
14849 }
14850
14851 static void
14852 OP_J (int bytemode, int sizeflag)
14853 {
14854   bfd_vma disp;
14855   bfd_vma mask = -1;
14856   bfd_vma segment = 0;
14857
14858   switch (bytemode)
14859     {
14860     case b_mode:
14861       FETCH_DATA (the_info, codep + 1);
14862       disp = *codep++;
14863       if ((disp & 0x80) != 0)
14864         disp -= 0x100;
14865       break;
14866     case v_mode:
14867       if (isa64 == amd64)
14868         USED_REX (REX_W);
14869       if ((sizeflag & DFLAG)
14870           || (address_mode == mode_64bit
14871               && (isa64 != amd64 || (rex & REX_W))))
14872         disp = get32s ();
14873       else
14874         {
14875           disp = get16 ();
14876           if ((disp & 0x8000) != 0)
14877             disp -= 0x10000;
14878           /* In 16bit mode, address is wrapped around at 64k within
14879              the same segment.  Otherwise, a data16 prefix on a jump
14880              instruction means that the pc is masked to 16 bits after
14881              the displacement is added!  */
14882           mask = 0xffff;
14883           if ((prefixes & PREFIX_DATA) == 0)
14884             segment = ((start_pc + (codep - start_codep))
14885                        & ~((bfd_vma) 0xffff));
14886         }
14887       if (address_mode != mode_64bit
14888           || (isa64 == amd64 && !(rex & REX_W)))
14889         used_prefixes |= (prefixes & PREFIX_DATA);
14890       break;
14891     default:
14892       oappend (INTERNAL_DISASSEMBLER_ERROR);
14893       return;
14894     }
14895   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14896   set_op (disp, 0);
14897   print_operand_value (scratchbuf, 1, disp);
14898   oappend (scratchbuf);
14899 }
14900
14901 static void
14902 OP_SEG (int bytemode, int sizeflag)
14903 {
14904   if (bytemode == w_mode)
14905     oappend (names_seg[modrm.reg]);
14906   else
14907     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14908 }
14909
14910 static void
14911 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14912 {
14913   int seg, offset;
14914
14915   if (sizeflag & DFLAG)
14916     {
14917       offset = get32 ();
14918       seg = get16 ();
14919     }
14920   else
14921     {
14922       offset = get16 ();
14923       seg = get16 ();
14924     }
14925   used_prefixes |= (prefixes & PREFIX_DATA);
14926   if (intel_syntax)
14927     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14928   else
14929     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14930   oappend (scratchbuf);
14931 }
14932
14933 static void
14934 OP_OFF (int bytemode, int sizeflag)
14935 {
14936   bfd_vma off;
14937
14938   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14939     intel_operand_size (bytemode, sizeflag);
14940   append_seg ();
14941
14942   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14943     off = get32 ();
14944   else
14945     off = get16 ();
14946
14947   if (intel_syntax)
14948     {
14949       if (!active_seg_prefix)
14950         {
14951           oappend (names_seg[ds_reg - es_reg]);
14952           oappend (":");
14953         }
14954     }
14955   print_operand_value (scratchbuf, 1, off);
14956   oappend (scratchbuf);
14957 }
14958
14959 static void
14960 OP_OFF64 (int bytemode, int sizeflag)
14961 {
14962   bfd_vma off;
14963
14964   if (address_mode != mode_64bit
14965       || (prefixes & PREFIX_ADDR))
14966     {
14967       OP_OFF (bytemode, sizeflag);
14968       return;
14969     }
14970
14971   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14972     intel_operand_size (bytemode, sizeflag);
14973   append_seg ();
14974
14975   off = get64 ();
14976
14977   if (intel_syntax)
14978     {
14979       if (!active_seg_prefix)
14980         {
14981           oappend (names_seg[ds_reg - es_reg]);
14982           oappend (":");
14983         }
14984     }
14985   print_operand_value (scratchbuf, 1, off);
14986   oappend (scratchbuf);
14987 }
14988
14989 static void
14990 ptr_reg (int code, int sizeflag)
14991 {
14992   const char *s;
14993
14994   *obufp++ = open_char;
14995   used_prefixes |= (prefixes & PREFIX_ADDR);
14996   if (address_mode == mode_64bit)
14997     {
14998       if (!(sizeflag & AFLAG))
14999         s = names32[code - eAX_reg];
15000       else
15001         s = names64[code - eAX_reg];
15002     }
15003   else if (sizeflag & AFLAG)
15004     s = names32[code - eAX_reg];
15005   else
15006     s = names16[code - eAX_reg];
15007   oappend (s);
15008   *obufp++ = close_char;
15009   *obufp = 0;
15010 }
15011
15012 static void
15013 OP_ESreg (int code, int sizeflag)
15014 {
15015   if (intel_syntax)
15016     {
15017       switch (codep[-1])
15018         {
15019         case 0x6d:      /* insw/insl */
15020           intel_operand_size (z_mode, sizeflag);
15021           break;
15022         case 0xa5:      /* movsw/movsl/movsq */
15023         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15024         case 0xab:      /* stosw/stosl */
15025         case 0xaf:      /* scasw/scasl */
15026           intel_operand_size (v_mode, sizeflag);
15027           break;
15028         default:
15029           intel_operand_size (b_mode, sizeflag);
15030         }
15031     }
15032   oappend_maybe_intel ("%es:");
15033   ptr_reg (code, sizeflag);
15034 }
15035
15036 static void
15037 OP_DSreg (int code, int sizeflag)
15038 {
15039   if (intel_syntax)
15040     {
15041       switch (codep[-1])
15042         {
15043         case 0x6f:      /* outsw/outsl */
15044           intel_operand_size (z_mode, sizeflag);
15045           break;
15046         case 0xa5:      /* movsw/movsl/movsq */
15047         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15048         case 0xad:      /* lodsw/lodsl/lodsq */
15049           intel_operand_size (v_mode, sizeflag);
15050           break;
15051         default:
15052           intel_operand_size (b_mode, sizeflag);
15053         }
15054     }
15055   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15056      default segment register DS is printed.  */
15057   if (!active_seg_prefix)
15058     active_seg_prefix = PREFIX_DS;
15059   append_seg ();
15060   ptr_reg (code, sizeflag);
15061 }
15062
15063 static void
15064 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15065 {
15066   int add;
15067   if (rex & REX_R)
15068     {
15069       USED_REX (REX_R);
15070       add = 8;
15071     }
15072   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15073     {
15074       all_prefixes[last_lock_prefix] = 0;
15075       used_prefixes |= PREFIX_LOCK;
15076       add = 8;
15077     }
15078   else
15079     add = 0;
15080   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15081   oappend_maybe_intel (scratchbuf);
15082 }
15083
15084 static void
15085 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15086 {
15087   int add;
15088   USED_REX (REX_R);
15089   if (rex & REX_R)
15090     add = 8;
15091   else
15092     add = 0;
15093   if (intel_syntax)
15094     sprintf (scratchbuf, "db%d", modrm.reg + add);
15095   else
15096     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15097   oappend (scratchbuf);
15098 }
15099
15100 static void
15101 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15102 {
15103   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15104   oappend_maybe_intel (scratchbuf);
15105 }
15106
15107 static void
15108 OP_R (int bytemode, int sizeflag)
15109 {
15110   /* Skip mod/rm byte.  */
15111   MODRM_CHECK;
15112   codep++;
15113   OP_E_register (bytemode, sizeflag);
15114 }
15115
15116 static void
15117 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15118 {
15119   int reg = modrm.reg;
15120   const char **names;
15121
15122   used_prefixes |= (prefixes & PREFIX_DATA);
15123   if (prefixes & PREFIX_DATA)
15124     {
15125       names = names_xmm;
15126       USED_REX (REX_R);
15127       if (rex & REX_R)
15128         reg += 8;
15129     }
15130   else
15131     names = names_mm;
15132   oappend (names[reg]);
15133 }
15134
15135 static void
15136 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15137 {
15138   int reg = modrm.reg;
15139   const char **names;
15140
15141   USED_REX (REX_R);
15142   if (rex & REX_R)
15143     reg += 8;
15144   if (vex.evex)
15145     {
15146       if (!vex.r)
15147         reg += 16;
15148     }
15149
15150   if (need_vex
15151       && bytemode != xmm_mode
15152       && bytemode != xmmq_mode
15153       && bytemode != evex_half_bcst_xmmq_mode
15154       && bytemode != ymm_mode
15155       && bytemode != scalar_mode)
15156     {
15157       switch (vex.length)
15158         {
15159         case 128:
15160           names = names_xmm;
15161           break;
15162         case 256:
15163           if (vex.w
15164               || (bytemode != vex_vsib_q_w_dq_mode
15165                   && bytemode != vex_vsib_q_w_d_mode))
15166             names = names_ymm;
15167           else
15168             names = names_xmm;
15169           break;
15170         case 512:
15171           names = names_zmm;
15172           break;
15173         default:
15174           abort ();
15175         }
15176     }
15177   else if (bytemode == xmmq_mode
15178            || bytemode == evex_half_bcst_xmmq_mode)
15179     {
15180       switch (vex.length)
15181         {
15182         case 128:
15183         case 256:
15184           names = names_xmm;
15185           break;
15186         case 512:
15187           names = names_ymm;
15188           break;
15189         default:
15190           abort ();
15191         }
15192     }
15193   else if (bytemode == ymm_mode)
15194     names = names_ymm;
15195   else
15196     names = names_xmm;
15197   oappend (names[reg]);
15198 }
15199
15200 static void
15201 OP_EM (int bytemode, int sizeflag)
15202 {
15203   int reg;
15204   const char **names;
15205
15206   if (modrm.mod != 3)
15207     {
15208       if (intel_syntax
15209           && (bytemode == v_mode || bytemode == v_swap_mode))
15210         {
15211           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15212           used_prefixes |= (prefixes & PREFIX_DATA);
15213         }
15214       OP_E (bytemode, sizeflag);
15215       return;
15216     }
15217
15218   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15219     swap_operand ();
15220
15221   /* Skip mod/rm byte.  */
15222   MODRM_CHECK;
15223   codep++;
15224   used_prefixes |= (prefixes & PREFIX_DATA);
15225   reg = modrm.rm;
15226   if (prefixes & PREFIX_DATA)
15227     {
15228       names = names_xmm;
15229       USED_REX (REX_B);
15230       if (rex & REX_B)
15231         reg += 8;
15232     }
15233   else
15234     names = names_mm;
15235   oappend (names[reg]);
15236 }
15237
15238 /* cvt* are the only instructions in sse2 which have
15239    both SSE and MMX operands and also have 0x66 prefix
15240    in their opcode. 0x66 was originally used to differentiate
15241    between SSE and MMX instruction(operands). So we have to handle the
15242    cvt* separately using OP_EMC and OP_MXC */
15243 static void
15244 OP_EMC (int bytemode, int sizeflag)
15245 {
15246   if (modrm.mod != 3)
15247     {
15248       if (intel_syntax && bytemode == v_mode)
15249         {
15250           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15251           used_prefixes |= (prefixes & PREFIX_DATA);
15252         }
15253       OP_E (bytemode, sizeflag);
15254       return;
15255     }
15256
15257   /* Skip mod/rm byte.  */
15258   MODRM_CHECK;
15259   codep++;
15260   used_prefixes |= (prefixes & PREFIX_DATA);
15261   oappend (names_mm[modrm.rm]);
15262 }
15263
15264 static void
15265 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15266 {
15267   used_prefixes |= (prefixes & PREFIX_DATA);
15268   oappend (names_mm[modrm.reg]);
15269 }
15270
15271 static void
15272 OP_EX (int bytemode, int sizeflag)
15273 {
15274   int reg;
15275   const char **names;
15276
15277   /* Skip mod/rm byte.  */
15278   MODRM_CHECK;
15279   codep++;
15280
15281   if (modrm.mod != 3)
15282     {
15283       OP_E_memory (bytemode, sizeflag);
15284       return;
15285     }
15286
15287   reg = modrm.rm;
15288   USED_REX (REX_B);
15289   if (rex & REX_B)
15290     reg += 8;
15291   if (vex.evex)
15292     {
15293       USED_REX (REX_X);
15294       if ((rex & REX_X))
15295         reg += 16;
15296     }
15297
15298   if ((sizeflag & SUFFIX_ALWAYS)
15299       && (bytemode == x_swap_mode
15300           || bytemode == d_swap_mode
15301           || bytemode == d_scalar_swap_mode
15302           || bytemode == q_swap_mode
15303           || bytemode == q_scalar_swap_mode))
15304     swap_operand ();
15305
15306   if (need_vex
15307       && bytemode != xmm_mode
15308       && bytemode != xmmdw_mode
15309       && bytemode != xmmqd_mode
15310       && bytemode != xmm_mb_mode
15311       && bytemode != xmm_mw_mode
15312       && bytemode != xmm_md_mode
15313       && bytemode != xmm_mq_mode
15314       && bytemode != xmm_mdq_mode
15315       && bytemode != xmmq_mode
15316       && bytemode != evex_half_bcst_xmmq_mode
15317       && bytemode != ymm_mode
15318       && bytemode != d_scalar_mode
15319       && bytemode != d_scalar_swap_mode
15320       && bytemode != q_scalar_mode
15321       && bytemode != q_scalar_swap_mode
15322       && bytemode != vex_scalar_w_dq_mode)
15323     {
15324       switch (vex.length)
15325         {
15326         case 128:
15327           names = names_xmm;
15328           break;
15329         case 256:
15330           names = names_ymm;
15331           break;
15332         case 512:
15333           names = names_zmm;
15334           break;
15335         default:
15336           abort ();
15337         }
15338     }
15339   else if (bytemode == xmmq_mode
15340            || bytemode == evex_half_bcst_xmmq_mode)
15341     {
15342       switch (vex.length)
15343         {
15344         case 128:
15345         case 256:
15346           names = names_xmm;
15347           break;
15348         case 512:
15349           names = names_ymm;
15350           break;
15351         default:
15352           abort ();
15353         }
15354     }
15355   else if (bytemode == ymm_mode)
15356     names = names_ymm;
15357   else
15358     names = names_xmm;
15359   oappend (names[reg]);
15360 }
15361
15362 static void
15363 OP_MS (int bytemode, int sizeflag)
15364 {
15365   if (modrm.mod == 3)
15366     OP_EM (bytemode, sizeflag);
15367   else
15368     BadOp ();
15369 }
15370
15371 static void
15372 OP_XS (int bytemode, int sizeflag)
15373 {
15374   if (modrm.mod == 3)
15375     OP_EX (bytemode, sizeflag);
15376   else
15377     BadOp ();
15378 }
15379
15380 static void
15381 OP_M (int bytemode, int sizeflag)
15382 {
15383   if (modrm.mod == 3)
15384     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15385     BadOp ();
15386   else
15387     OP_E (bytemode, sizeflag);
15388 }
15389
15390 static void
15391 OP_0f07 (int bytemode, int sizeflag)
15392 {
15393   if (modrm.mod != 3 || modrm.rm != 0)
15394     BadOp ();
15395   else
15396     OP_E (bytemode, sizeflag);
15397 }
15398
15399 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15400    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15401
15402 static void
15403 NOP_Fixup1 (int bytemode, int sizeflag)
15404 {
15405   if ((prefixes & PREFIX_DATA) != 0
15406       || (rex != 0
15407           && rex != 0x48
15408           && address_mode == mode_64bit))
15409     OP_REG (bytemode, sizeflag);
15410   else
15411     strcpy (obuf, "nop");
15412 }
15413
15414 static void
15415 NOP_Fixup2 (int bytemode, int sizeflag)
15416 {
15417   if ((prefixes & PREFIX_DATA) != 0
15418       || (rex != 0
15419           && rex != 0x48
15420           && address_mode == mode_64bit))
15421     OP_IMREG (bytemode, sizeflag);
15422 }
15423
15424 static const char *const Suffix3DNow[] = {
15425 /* 00 */        NULL,           NULL,           NULL,           NULL,
15426 /* 04 */        NULL,           NULL,           NULL,           NULL,
15427 /* 08 */        NULL,           NULL,           NULL,           NULL,
15428 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15429 /* 10 */        NULL,           NULL,           NULL,           NULL,
15430 /* 14 */        NULL,           NULL,           NULL,           NULL,
15431 /* 18 */        NULL,           NULL,           NULL,           NULL,
15432 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15433 /* 20 */        NULL,           NULL,           NULL,           NULL,
15434 /* 24 */        NULL,           NULL,           NULL,           NULL,
15435 /* 28 */        NULL,           NULL,           NULL,           NULL,
15436 /* 2C */        NULL,           NULL,           NULL,           NULL,
15437 /* 30 */        NULL,           NULL,           NULL,           NULL,
15438 /* 34 */        NULL,           NULL,           NULL,           NULL,
15439 /* 38 */        NULL,           NULL,           NULL,           NULL,
15440 /* 3C */        NULL,           NULL,           NULL,           NULL,
15441 /* 40 */        NULL,           NULL,           NULL,           NULL,
15442 /* 44 */        NULL,           NULL,           NULL,           NULL,
15443 /* 48 */        NULL,           NULL,           NULL,           NULL,
15444 /* 4C */        NULL,           NULL,           NULL,           NULL,
15445 /* 50 */        NULL,           NULL,           NULL,           NULL,
15446 /* 54 */        NULL,           NULL,           NULL,           NULL,
15447 /* 58 */        NULL,           NULL,           NULL,           NULL,
15448 /* 5C */        NULL,           NULL,           NULL,           NULL,
15449 /* 60 */        NULL,           NULL,           NULL,           NULL,
15450 /* 64 */        NULL,           NULL,           NULL,           NULL,
15451 /* 68 */        NULL,           NULL,           NULL,           NULL,
15452 /* 6C */        NULL,           NULL,           NULL,           NULL,
15453 /* 70 */        NULL,           NULL,           NULL,           NULL,
15454 /* 74 */        NULL,           NULL,           NULL,           NULL,
15455 /* 78 */        NULL,           NULL,           NULL,           NULL,
15456 /* 7C */        NULL,           NULL,           NULL,           NULL,
15457 /* 80 */        NULL,           NULL,           NULL,           NULL,
15458 /* 84 */        NULL,           NULL,           NULL,           NULL,
15459 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15460 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15461 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15462 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15463 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15464 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15465 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15466 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15467 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15468 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15469 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15470 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15471 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15472 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15473 /* C0 */        NULL,           NULL,           NULL,           NULL,
15474 /* C4 */        NULL,           NULL,           NULL,           NULL,
15475 /* C8 */        NULL,           NULL,           NULL,           NULL,
15476 /* CC */        NULL,           NULL,           NULL,           NULL,
15477 /* D0 */        NULL,           NULL,           NULL,           NULL,
15478 /* D4 */        NULL,           NULL,           NULL,           NULL,
15479 /* D8 */        NULL,           NULL,           NULL,           NULL,
15480 /* DC */        NULL,           NULL,           NULL,           NULL,
15481 /* E0 */        NULL,           NULL,           NULL,           NULL,
15482 /* E4 */        NULL,           NULL,           NULL,           NULL,
15483 /* E8 */        NULL,           NULL,           NULL,           NULL,
15484 /* EC */        NULL,           NULL,           NULL,           NULL,
15485 /* F0 */        NULL,           NULL,           NULL,           NULL,
15486 /* F4 */        NULL,           NULL,           NULL,           NULL,
15487 /* F8 */        NULL,           NULL,           NULL,           NULL,
15488 /* FC */        NULL,           NULL,           NULL,           NULL,
15489 };
15490
15491 static void
15492 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15493 {
15494   const char *mnemonic;
15495
15496   FETCH_DATA (the_info, codep + 1);
15497   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15498      place where an 8-bit immediate would normally go.  ie. the last
15499      byte of the instruction.  */
15500   obufp = mnemonicendp;
15501   mnemonic = Suffix3DNow[*codep++ & 0xff];
15502   if (mnemonic)
15503     oappend (mnemonic);
15504   else
15505     {
15506       /* Since a variable sized modrm/sib chunk is between the start
15507          of the opcode (0x0f0f) and the opcode suffix, we need to do
15508          all the modrm processing first, and don't know until now that
15509          we have a bad opcode.  This necessitates some cleaning up.  */
15510       op_out[0][0] = '\0';
15511       op_out[1][0] = '\0';
15512       BadOp ();
15513     }
15514   mnemonicendp = obufp;
15515 }
15516
15517 static struct op simd_cmp_op[] =
15518 {
15519   { STRING_COMMA_LEN ("eq") },
15520   { STRING_COMMA_LEN ("lt") },
15521   { STRING_COMMA_LEN ("le") },
15522   { STRING_COMMA_LEN ("unord") },
15523   { STRING_COMMA_LEN ("neq") },
15524   { STRING_COMMA_LEN ("nlt") },
15525   { STRING_COMMA_LEN ("nle") },
15526   { STRING_COMMA_LEN ("ord") }
15527 };
15528
15529 static void
15530 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15531 {
15532   unsigned int cmp_type;
15533
15534   FETCH_DATA (the_info, codep + 1);
15535   cmp_type = *codep++ & 0xff;
15536   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15537     {
15538       char suffix [3];
15539       char *p = mnemonicendp - 2;
15540       suffix[0] = p[0];
15541       suffix[1] = p[1];
15542       suffix[2] = '\0';
15543       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15544       mnemonicendp += simd_cmp_op[cmp_type].len;
15545     }
15546   else
15547     {
15548       /* We have a reserved extension byte.  Output it directly.  */
15549       scratchbuf[0] = '$';
15550       print_operand_value (scratchbuf + 1, 1, cmp_type);
15551       oappend_maybe_intel (scratchbuf);
15552       scratchbuf[0] = '\0';
15553     }
15554 }
15555
15556 static void
15557 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15558           int sizeflag ATTRIBUTE_UNUSED)
15559 {
15560   /* mwaitx %eax,%ecx,%ebx */
15561   if (!intel_syntax)
15562     {
15563       const char **names = (address_mode == mode_64bit
15564                             ? names64 : names32);
15565       strcpy (op_out[0], names[0]);
15566       strcpy (op_out[1], names[1]);
15567       strcpy (op_out[2], names[3]);
15568       two_source_ops = 1;
15569     }
15570   /* Skip mod/rm byte.  */
15571   MODRM_CHECK;
15572   codep++;
15573 }
15574
15575 static void
15576 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15577           int sizeflag ATTRIBUTE_UNUSED)
15578 {
15579   /* mwait %eax,%ecx  */
15580   if (!intel_syntax)
15581     {
15582       const char **names = (address_mode == mode_64bit
15583                             ? names64 : names32);
15584       strcpy (op_out[0], names[0]);
15585       strcpy (op_out[1], names[1]);
15586       two_source_ops = 1;
15587     }
15588   /* Skip mod/rm byte.  */
15589   MODRM_CHECK;
15590   codep++;
15591 }
15592
15593 static void
15594 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15595             int sizeflag ATTRIBUTE_UNUSED)
15596 {
15597   /* monitor %eax,%ecx,%edx"  */
15598   if (!intel_syntax)
15599     {
15600       const char **op1_names;
15601       const char **names = (address_mode == mode_64bit
15602                             ? names64 : names32);
15603
15604       if (!(prefixes & PREFIX_ADDR))
15605         op1_names = (address_mode == mode_16bit
15606                      ? names16 : names);
15607       else
15608         {
15609           /* Remove "addr16/addr32".  */
15610           all_prefixes[last_addr_prefix] = 0;
15611           op1_names = (address_mode != mode_32bit
15612                        ? names32 : names16);
15613           used_prefixes |= PREFIX_ADDR;
15614         }
15615       strcpy (op_out[0], op1_names[0]);
15616       strcpy (op_out[1], names[1]);
15617       strcpy (op_out[2], names[2]);
15618       two_source_ops = 1;
15619     }
15620   /* Skip mod/rm byte.  */
15621   MODRM_CHECK;
15622   codep++;
15623 }
15624
15625 static void
15626 BadOp (void)
15627 {
15628   /* Throw away prefixes and 1st. opcode byte.  */
15629   codep = insn_codep + 1;
15630   oappend ("(bad)");
15631 }
15632
15633 static void
15634 REP_Fixup (int bytemode, int sizeflag)
15635 {
15636   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15637      lods and stos.  */
15638   if (prefixes & PREFIX_REPZ)
15639     all_prefixes[last_repz_prefix] = REP_PREFIX;
15640
15641   switch (bytemode)
15642     {
15643     case al_reg:
15644     case eAX_reg:
15645     case indir_dx_reg:
15646       OP_IMREG (bytemode, sizeflag);
15647       break;
15648     case eDI_reg:
15649       OP_ESreg (bytemode, sizeflag);
15650       break;
15651     case eSI_reg:
15652       OP_DSreg (bytemode, sizeflag);
15653       break;
15654     default:
15655       abort ();
15656       break;
15657     }
15658 }
15659
15660 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15661    "bnd".  */
15662
15663 static void
15664 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15665 {
15666   if (prefixes & PREFIX_REPNZ)
15667     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15668 }
15669
15670 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15671    "notrack".  */
15672
15673 static void
15674 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15675                int sizeflag ATTRIBUTE_UNUSED)
15676 {
15677   if (active_seg_prefix == PREFIX_DS
15678       && (address_mode != mode_64bit || last_data_prefix < 0))
15679     {
15680       /* NOTRACK prefix is only valid on indirect branch instructions.
15681          NB: DATA prefix is unsupported for Intel64.  */
15682       active_seg_prefix = 0;
15683       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15684     }
15685 }
15686
15687 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15688    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15689  */
15690
15691 static void
15692 HLE_Fixup1 (int bytemode, int sizeflag)
15693 {
15694   if (modrm.mod != 3
15695       && (prefixes & PREFIX_LOCK) != 0)
15696     {
15697       if (prefixes & PREFIX_REPZ)
15698         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15699       if (prefixes & PREFIX_REPNZ)
15700         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15701     }
15702
15703   OP_E (bytemode, sizeflag);
15704 }
15705
15706 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15707    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15708  */
15709
15710 static void
15711 HLE_Fixup2 (int bytemode, int sizeflag)
15712 {
15713   if (modrm.mod != 3)
15714     {
15715       if (prefixes & PREFIX_REPZ)
15716         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15717       if (prefixes & PREFIX_REPNZ)
15718         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15719     }
15720
15721   OP_E (bytemode, sizeflag);
15722 }
15723
15724 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15725    "xrelease" for memory operand.  No check for LOCK prefix.   */
15726
15727 static void
15728 HLE_Fixup3 (int bytemode, int sizeflag)
15729 {
15730   if (modrm.mod != 3
15731       && last_repz_prefix > last_repnz_prefix
15732       && (prefixes & PREFIX_REPZ) != 0)
15733     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15734
15735   OP_E (bytemode, sizeflag);
15736 }
15737
15738 static void
15739 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15740 {
15741   USED_REX (REX_W);
15742   if (rex & REX_W)
15743     {
15744       /* Change cmpxchg8b to cmpxchg16b.  */
15745       char *p = mnemonicendp - 2;
15746       mnemonicendp = stpcpy (p, "16b");
15747       bytemode = o_mode;
15748     }
15749   else if ((prefixes & PREFIX_LOCK) != 0)
15750     {
15751       if (prefixes & PREFIX_REPZ)
15752         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15753       if (prefixes & PREFIX_REPNZ)
15754         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15755     }
15756
15757   OP_M (bytemode, sizeflag);
15758 }
15759
15760 static void
15761 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15762 {
15763   const char **names;
15764
15765   if (need_vex)
15766     {
15767       switch (vex.length)
15768         {
15769         case 128:
15770           names = names_xmm;
15771           break;
15772         case 256:
15773           names = names_ymm;
15774           break;
15775         default:
15776           abort ();
15777         }
15778     }
15779   else
15780     names = names_xmm;
15781   oappend (names[reg]);
15782 }
15783
15784 static void
15785 CRC32_Fixup (int bytemode, int sizeflag)
15786 {
15787   /* Add proper suffix to "crc32".  */
15788   char *p = mnemonicendp;
15789
15790   switch (bytemode)
15791     {
15792     case b_mode:
15793       if (intel_syntax)
15794         goto skip;
15795
15796       *p++ = 'b';
15797       break;
15798     case v_mode:
15799       if (intel_syntax)
15800         goto skip;
15801
15802       USED_REX (REX_W);
15803       if (rex & REX_W)
15804         *p++ = 'q';
15805       else
15806         {
15807           if (sizeflag & DFLAG)
15808             *p++ = 'l';
15809           else
15810             *p++ = 'w';
15811           used_prefixes |= (prefixes & PREFIX_DATA);
15812         }
15813       break;
15814     default:
15815       oappend (INTERNAL_DISASSEMBLER_ERROR);
15816       break;
15817     }
15818   mnemonicendp = p;
15819   *p = '\0';
15820
15821 skip:
15822   if (modrm.mod == 3)
15823     {
15824       int add;
15825
15826       /* Skip mod/rm byte.  */
15827       MODRM_CHECK;
15828       codep++;
15829
15830       USED_REX (REX_B);
15831       add = (rex & REX_B) ? 8 : 0;
15832       if (bytemode == b_mode)
15833         {
15834           USED_REX (0);
15835           if (rex)
15836             oappend (names8rex[modrm.rm + add]);
15837           else
15838             oappend (names8[modrm.rm + add]);
15839         }
15840       else
15841         {
15842           USED_REX (REX_W);
15843           if (rex & REX_W)
15844             oappend (names64[modrm.rm + add]);
15845           else if ((prefixes & PREFIX_DATA))
15846             oappend (names16[modrm.rm + add]);
15847           else
15848             oappend (names32[modrm.rm + add]);
15849         }
15850     }
15851   else
15852     OP_E (bytemode, sizeflag);
15853 }
15854
15855 static void
15856 FXSAVE_Fixup (int bytemode, int sizeflag)
15857 {
15858   /* Add proper suffix to "fxsave" and "fxrstor".  */
15859   USED_REX (REX_W);
15860   if (rex & REX_W)
15861     {
15862       char *p = mnemonicendp;
15863       *p++ = '6';
15864       *p++ = '4';
15865       *p = '\0';
15866       mnemonicendp = p;
15867     }
15868   OP_M (bytemode, sizeflag);
15869 }
15870
15871 static void
15872 PCMPESTR_Fixup (int bytemode, int sizeflag)
15873 {
15874   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15875   if (!intel_syntax)
15876     {
15877       char *p = mnemonicendp;
15878
15879       USED_REX (REX_W);
15880       if (rex & REX_W)
15881         *p++ = 'q';
15882       else if (sizeflag & SUFFIX_ALWAYS)
15883         *p++ = 'l';
15884
15885       *p = '\0';
15886       mnemonicendp = p;
15887     }
15888
15889   OP_EX (bytemode, sizeflag);
15890 }
15891
15892 /* Display the destination register operand for instructions with
15893    VEX. */
15894
15895 static void
15896 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15897 {
15898   int reg;
15899   const char **names;
15900
15901   if (!need_vex)
15902     abort ();
15903
15904   if (!need_vex_reg)
15905     return;
15906
15907   reg = vex.register_specifier;
15908   if (address_mode != mode_64bit)
15909     reg &= 7;
15910   else if (vex.evex && !vex.v)
15911     reg += 16;
15912
15913   if (bytemode == vex_scalar_mode)
15914     {
15915       oappend (names_xmm[reg]);
15916       return;
15917     }
15918
15919   switch (vex.length)
15920     {
15921     case 128:
15922       switch (bytemode)
15923         {
15924         case vex_mode:
15925         case vex128_mode:
15926         case vex_vsib_q_w_dq_mode:
15927         case vex_vsib_q_w_d_mode:
15928           names = names_xmm;
15929           break;
15930         case dq_mode:
15931           if (rex & REX_W)
15932             names = names64;
15933           else
15934             names = names32;
15935           break;
15936         case mask_bd_mode:
15937         case mask_mode:
15938           if (reg > 0x7)
15939             {
15940               oappend ("(bad)");
15941               return;
15942             }
15943           names = names_mask;
15944           break;
15945         default:
15946           abort ();
15947           return;
15948         }
15949       break;
15950     case 256:
15951       switch (bytemode)
15952         {
15953         case vex_mode:
15954         case vex256_mode:
15955           names = names_ymm;
15956           break;
15957         case vex_vsib_q_w_dq_mode:
15958         case vex_vsib_q_w_d_mode:
15959           names = vex.w ? names_ymm : names_xmm;
15960           break;
15961         case mask_bd_mode:
15962         case mask_mode:
15963           if (reg > 0x7)
15964             {
15965               oappend ("(bad)");
15966               return;
15967             }
15968           names = names_mask;
15969           break;
15970         default:
15971           /* See PR binutils/20893 for a reproducer.  */
15972           oappend ("(bad)");
15973           return;
15974         }
15975       break;
15976     case 512:
15977       names = names_zmm;
15978       break;
15979     default:
15980       abort ();
15981       break;
15982     }
15983   oappend (names[reg]);
15984 }
15985
15986 /* Get the VEX immediate byte without moving codep.  */
15987
15988 static unsigned char
15989 get_vex_imm8 (int sizeflag, int opnum)
15990 {
15991   int bytes_before_imm = 0;
15992
15993   if (modrm.mod != 3)
15994     {
15995       /* There are SIB/displacement bytes.  */
15996       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15997         {
15998           /* 32/64 bit address mode */
15999           int base = modrm.rm;
16000
16001           /* Check SIB byte.  */
16002           if (base == 4)
16003             {
16004               FETCH_DATA (the_info, codep + 1);
16005               base = *codep & 7;
16006               /* When decoding the third source, don't increase
16007                  bytes_before_imm as this has already been incremented
16008                  by one in OP_E_memory while decoding the second
16009                  source operand.  */
16010               if (opnum == 0)
16011                 bytes_before_imm++;
16012             }
16013
16014           /* Don't increase bytes_before_imm when decoding the third source,
16015              it has already been incremented by OP_E_memory while decoding
16016              the second source operand.  */
16017           if (opnum == 0)
16018             {
16019               switch (modrm.mod)
16020                 {
16021                   case 0:
16022                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16023                        SIB == 5, there is a 4 byte displacement.  */
16024                     if (base != 5)
16025                       /* No displacement. */
16026                       break;
16027                     /* Fall through.  */
16028                   case 2:
16029                     /* 4 byte displacement.  */
16030                     bytes_before_imm += 4;
16031                     break;
16032                   case 1:
16033                     /* 1 byte displacement.  */
16034                     bytes_before_imm++;
16035                     break;
16036                 }
16037             }
16038         }
16039       else
16040         {
16041           /* 16 bit address mode */
16042           /* Don't increase bytes_before_imm when decoding the third source,
16043              it has already been incremented by OP_E_memory while decoding
16044              the second source operand.  */
16045           if (opnum == 0)
16046             {
16047               switch (modrm.mod)
16048                 {
16049                 case 0:
16050                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16051                   if (modrm.rm != 6)
16052                     /* No displacement. */
16053                     break;
16054                   /* Fall through.  */
16055                 case 2:
16056                   /* 2 byte displacement.  */
16057                   bytes_before_imm += 2;
16058                   break;
16059                 case 1:
16060                   /* 1 byte displacement: when decoding the third source,
16061                      don't increase bytes_before_imm as this has already
16062                      been incremented by one in OP_E_memory while decoding
16063                      the second source operand.  */
16064                   if (opnum == 0)
16065                     bytes_before_imm++;
16066
16067                   break;
16068                 }
16069             }
16070         }
16071     }
16072
16073   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16074   return codep [bytes_before_imm];
16075 }
16076
16077 static void
16078 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16079 {
16080   const char **names;
16081
16082   if (reg == -1 && modrm.mod != 3)
16083     {
16084       OP_E_memory (bytemode, sizeflag);
16085       return;
16086     }
16087   else
16088     {
16089       if (reg == -1)
16090         {
16091           reg = modrm.rm;
16092           USED_REX (REX_B);
16093           if (rex & REX_B)
16094             reg += 8;
16095         }
16096       if (address_mode != mode_64bit)
16097         reg &= 7;
16098     }
16099
16100   switch (vex.length)
16101     {
16102     case 128:
16103       names = names_xmm;
16104       break;
16105     case 256:
16106       names = names_ymm;
16107       break;
16108     default:
16109       abort ();
16110     }
16111   oappend (names[reg]);
16112 }
16113
16114 static void
16115 OP_EX_VexImmW (int bytemode, int sizeflag)
16116 {
16117   int reg = -1;
16118   static unsigned char vex_imm8;
16119
16120   if (vex_w_done == 0)
16121     {
16122       vex_w_done = 1;
16123
16124       /* Skip mod/rm byte.  */
16125       MODRM_CHECK;
16126       codep++;
16127
16128       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16129
16130       if (vex.w)
16131           reg = vex_imm8 >> 4;
16132
16133       OP_EX_VexReg (bytemode, sizeflag, reg);
16134     }
16135   else if (vex_w_done == 1)
16136     {
16137       vex_w_done = 2;
16138
16139       if (!vex.w)
16140           reg = vex_imm8 >> 4;
16141
16142       OP_EX_VexReg (bytemode, sizeflag, reg);
16143     }
16144   else
16145     {
16146       /* Output the imm8 directly.  */
16147       scratchbuf[0] = '$';
16148       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16149       oappend_maybe_intel (scratchbuf);
16150       scratchbuf[0] = '\0';
16151       codep++;
16152     }
16153 }
16154
16155 static void
16156 OP_Vex_2src (int bytemode, int sizeflag)
16157 {
16158   if (modrm.mod == 3)
16159     {
16160       int reg = modrm.rm;
16161       USED_REX (REX_B);
16162       if (rex & REX_B)
16163         reg += 8;
16164       oappend (names_xmm[reg]);
16165     }
16166   else
16167     {
16168       if (intel_syntax
16169           && (bytemode == v_mode || bytemode == v_swap_mode))
16170         {
16171           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16172           used_prefixes |= (prefixes & PREFIX_DATA);
16173         }
16174       OP_E (bytemode, sizeflag);
16175     }
16176 }
16177
16178 static void
16179 OP_Vex_2src_1 (int bytemode, int sizeflag)
16180 {
16181   if (modrm.mod == 3)
16182     {
16183       /* Skip mod/rm byte.   */
16184       MODRM_CHECK;
16185       codep++;
16186     }
16187
16188   if (vex.w)
16189     {
16190       unsigned int reg = vex.register_specifier;
16191
16192       if (address_mode != mode_64bit)
16193         reg &= 7;
16194       oappend (names_xmm[reg]);
16195     }
16196   else
16197     OP_Vex_2src (bytemode, sizeflag);
16198 }
16199
16200 static void
16201 OP_Vex_2src_2 (int bytemode, int sizeflag)
16202 {
16203   if (vex.w)
16204     OP_Vex_2src (bytemode, sizeflag);
16205   else
16206     {
16207       unsigned int reg = vex.register_specifier;
16208
16209       if (address_mode != mode_64bit)
16210         reg &= 7;
16211       oappend (names_xmm[reg]);
16212     }
16213 }
16214
16215 static void
16216 OP_EX_VexW (int bytemode, int sizeflag)
16217 {
16218   int reg = -1;
16219
16220   if (!vex_w_done)
16221     {
16222       /* Skip mod/rm byte.  */
16223       MODRM_CHECK;
16224       codep++;
16225
16226       if (vex.w)
16227         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16228     }
16229   else
16230     {
16231       if (!vex.w)
16232         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16233     }
16234
16235   OP_EX_VexReg (bytemode, sizeflag, reg);
16236
16237   if (vex_w_done)
16238     codep++;
16239   vex_w_done = 1;
16240 }
16241
16242 static void
16243 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16244 {
16245   int reg;
16246   const char **names;
16247
16248   FETCH_DATA (the_info, codep + 1);
16249   reg = *codep++;
16250
16251   if (bytemode != x_mode)
16252     abort ();
16253
16254   reg >>= 4;
16255   if (address_mode != mode_64bit)
16256     reg &= 7;
16257
16258   switch (vex.length)
16259     {
16260     case 128:
16261       names = names_xmm;
16262       break;
16263     case 256:
16264       names = names_ymm;
16265       break;
16266     default:
16267       abort ();
16268     }
16269   oappend (names[reg]);
16270 }
16271
16272 static void
16273 OP_XMM_VexW (int bytemode, int sizeflag)
16274 {
16275   /* Turn off the REX.W bit since it is used for swapping operands
16276      now.  */
16277   rex &= ~REX_W;
16278   OP_XMM (bytemode, sizeflag);
16279 }
16280
16281 static void
16282 OP_EX_Vex (int bytemode, int sizeflag)
16283 {
16284   if (modrm.mod != 3)
16285     {
16286       if (vex.register_specifier != 0)
16287         BadOp ();
16288       need_vex_reg = 0;
16289     }
16290   OP_EX (bytemode, sizeflag);
16291 }
16292
16293 static void
16294 OP_XMM_Vex (int bytemode, int sizeflag)
16295 {
16296   if (modrm.mod != 3)
16297     {
16298       if (vex.register_specifier != 0)
16299         BadOp ();
16300       need_vex_reg = 0;
16301     }
16302   OP_XMM (bytemode, sizeflag);
16303 }
16304
16305 static struct op vex_cmp_op[] =
16306 {
16307   { STRING_COMMA_LEN ("eq") },
16308   { STRING_COMMA_LEN ("lt") },
16309   { STRING_COMMA_LEN ("le") },
16310   { STRING_COMMA_LEN ("unord") },
16311   { STRING_COMMA_LEN ("neq") },
16312   { STRING_COMMA_LEN ("nlt") },
16313   { STRING_COMMA_LEN ("nle") },
16314   { STRING_COMMA_LEN ("ord") },
16315   { STRING_COMMA_LEN ("eq_uq") },
16316   { STRING_COMMA_LEN ("nge") },
16317   { STRING_COMMA_LEN ("ngt") },
16318   { STRING_COMMA_LEN ("false") },
16319   { STRING_COMMA_LEN ("neq_oq") },
16320   { STRING_COMMA_LEN ("ge") },
16321   { STRING_COMMA_LEN ("gt") },
16322   { STRING_COMMA_LEN ("true") },
16323   { STRING_COMMA_LEN ("eq_os") },
16324   { STRING_COMMA_LEN ("lt_oq") },
16325   { STRING_COMMA_LEN ("le_oq") },
16326   { STRING_COMMA_LEN ("unord_s") },
16327   { STRING_COMMA_LEN ("neq_us") },
16328   { STRING_COMMA_LEN ("nlt_uq") },
16329   { STRING_COMMA_LEN ("nle_uq") },
16330   { STRING_COMMA_LEN ("ord_s") },
16331   { STRING_COMMA_LEN ("eq_us") },
16332   { STRING_COMMA_LEN ("nge_uq") },
16333   { STRING_COMMA_LEN ("ngt_uq") },
16334   { STRING_COMMA_LEN ("false_os") },
16335   { STRING_COMMA_LEN ("neq_os") },
16336   { STRING_COMMA_LEN ("ge_oq") },
16337   { STRING_COMMA_LEN ("gt_oq") },
16338   { STRING_COMMA_LEN ("true_us") },
16339 };
16340
16341 static void
16342 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16343 {
16344   unsigned int cmp_type;
16345
16346   FETCH_DATA (the_info, codep + 1);
16347   cmp_type = *codep++ & 0xff;
16348   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16349     {
16350       char suffix [3];
16351       char *p = mnemonicendp - 2;
16352       suffix[0] = p[0];
16353       suffix[1] = p[1];
16354       suffix[2] = '\0';
16355       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16356       mnemonicendp += vex_cmp_op[cmp_type].len;
16357     }
16358   else
16359     {
16360       /* We have a reserved extension byte.  Output it directly.  */
16361       scratchbuf[0] = '$';
16362       print_operand_value (scratchbuf + 1, 1, cmp_type);
16363       oappend_maybe_intel (scratchbuf);
16364       scratchbuf[0] = '\0';
16365     }
16366 }
16367
16368 static void
16369 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16370              int sizeflag ATTRIBUTE_UNUSED)
16371 {
16372   unsigned int cmp_type;
16373
16374   if (!vex.evex)
16375     abort ();
16376
16377   FETCH_DATA (the_info, codep + 1);
16378   cmp_type = *codep++ & 0xff;
16379   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16380      If it's the case, print suffix, otherwise - print the immediate.  */
16381   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16382       && cmp_type != 3
16383       && cmp_type != 7)
16384     {
16385       char suffix [3];
16386       char *p = mnemonicendp - 2;
16387
16388       /* vpcmp* can have both one- and two-lettered suffix.  */
16389       if (p[0] == 'p')
16390         {
16391           p++;
16392           suffix[0] = p[0];
16393           suffix[1] = '\0';
16394         }
16395       else
16396         {
16397           suffix[0] = p[0];
16398           suffix[1] = p[1];
16399           suffix[2] = '\0';
16400         }
16401
16402       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16403       mnemonicendp += simd_cmp_op[cmp_type].len;
16404     }
16405   else
16406     {
16407       /* We have a reserved extension byte.  Output it directly.  */
16408       scratchbuf[0] = '$';
16409       print_operand_value (scratchbuf + 1, 1, cmp_type);
16410       oappend_maybe_intel (scratchbuf);
16411       scratchbuf[0] = '\0';
16412     }
16413 }
16414
16415 static const struct op xop_cmp_op[] =
16416 {
16417   { STRING_COMMA_LEN ("lt") },
16418   { STRING_COMMA_LEN ("le") },
16419   { STRING_COMMA_LEN ("gt") },
16420   { STRING_COMMA_LEN ("ge") },
16421   { STRING_COMMA_LEN ("eq") },
16422   { STRING_COMMA_LEN ("neq") },
16423   { STRING_COMMA_LEN ("false") },
16424   { STRING_COMMA_LEN ("true") }
16425 };
16426
16427 static void
16428 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16429              int sizeflag ATTRIBUTE_UNUSED)
16430 {
16431   unsigned int cmp_type;
16432
16433   FETCH_DATA (the_info, codep + 1);
16434   cmp_type = *codep++ & 0xff;
16435   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16436     {
16437       char suffix[3];
16438       char *p = mnemonicendp - 2;
16439
16440       /* vpcom* can have both one- and two-lettered suffix.  */
16441       if (p[0] == 'm')
16442         {
16443           p++;
16444           suffix[0] = p[0];
16445           suffix[1] = '\0';
16446         }
16447       else
16448         {
16449           suffix[0] = p[0];
16450           suffix[1] = p[1];
16451           suffix[2] = '\0';
16452         }
16453
16454       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16455       mnemonicendp += xop_cmp_op[cmp_type].len;
16456     }
16457   else
16458     {
16459       /* We have a reserved extension byte.  Output it directly.  */
16460       scratchbuf[0] = '$';
16461       print_operand_value (scratchbuf + 1, 1, cmp_type);
16462       oappend_maybe_intel (scratchbuf);
16463       scratchbuf[0] = '\0';
16464     }
16465 }
16466
16467 static const struct op pclmul_op[] =
16468 {
16469   { STRING_COMMA_LEN ("lql") },
16470   { STRING_COMMA_LEN ("hql") },
16471   { STRING_COMMA_LEN ("lqh") },
16472   { STRING_COMMA_LEN ("hqh") }
16473 };
16474
16475 static void
16476 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16477               int sizeflag ATTRIBUTE_UNUSED)
16478 {
16479   unsigned int pclmul_type;
16480
16481   FETCH_DATA (the_info, codep + 1);
16482   pclmul_type = *codep++ & 0xff;
16483   switch (pclmul_type)
16484     {
16485     case 0x10:
16486       pclmul_type = 2;
16487       break;
16488     case 0x11:
16489       pclmul_type = 3;
16490       break;
16491     default:
16492       break;
16493     }
16494   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16495     {
16496       char suffix [4];
16497       char *p = mnemonicendp - 3;
16498       suffix[0] = p[0];
16499       suffix[1] = p[1];
16500       suffix[2] = p[2];
16501       suffix[3] = '\0';
16502       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16503       mnemonicendp += pclmul_op[pclmul_type].len;
16504     }
16505   else
16506     {
16507       /* We have a reserved extension byte.  Output it directly.  */
16508       scratchbuf[0] = '$';
16509       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16510       oappend_maybe_intel (scratchbuf);
16511       scratchbuf[0] = '\0';
16512     }
16513 }
16514
16515 static void
16516 MOVBE_Fixup (int bytemode, int sizeflag)
16517 {
16518   /* Add proper suffix to "movbe".  */
16519   char *p = mnemonicendp;
16520
16521   switch (bytemode)
16522     {
16523     case v_mode:
16524       if (intel_syntax)
16525         goto skip;
16526
16527       USED_REX (REX_W);
16528       if (sizeflag & SUFFIX_ALWAYS)
16529         {
16530           if (rex & REX_W)
16531             *p++ = 'q';
16532           else
16533             {
16534               if (sizeflag & DFLAG)
16535                 *p++ = 'l';
16536               else
16537                 *p++ = 'w';
16538               used_prefixes |= (prefixes & PREFIX_DATA);
16539             }
16540         }
16541       break;
16542     default:
16543       oappend (INTERNAL_DISASSEMBLER_ERROR);
16544       break;
16545     }
16546   mnemonicendp = p;
16547   *p = '\0';
16548
16549 skip:
16550   OP_M (bytemode, sizeflag);
16551 }
16552
16553 static void
16554 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16555 {
16556   int reg;
16557   const char **names;
16558
16559   /* Skip mod/rm byte.  */
16560   MODRM_CHECK;
16561   codep++;
16562
16563   if (rex & REX_W)
16564     names = names64;
16565   else
16566     names = names32;
16567
16568   reg = modrm.rm;
16569   USED_REX (REX_B);
16570   if (rex & REX_B)
16571     reg += 8;
16572
16573   oappend (names[reg]);
16574 }
16575
16576 static void
16577 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16578 {
16579   const char **names;
16580   unsigned int reg = vex.register_specifier;
16581
16582   if (rex & REX_W)
16583     names = names64;
16584   else
16585     names = names32;
16586
16587   if (address_mode != mode_64bit)
16588     reg &= 7;
16589   oappend (names[reg]);
16590 }
16591
16592 static void
16593 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16594 {
16595   if (!vex.evex
16596       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16597     abort ();
16598
16599   USED_REX (REX_R);
16600   if ((rex & REX_R) != 0 || !vex.r)
16601     {
16602       BadOp ();
16603       return;
16604     }
16605
16606   oappend (names_mask [modrm.reg]);
16607 }
16608
16609 static void
16610 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16611 {
16612   if (!vex.evex
16613       || (bytemode != evex_rounding_mode
16614           && bytemode != evex_rounding_64_mode
16615           && bytemode != evex_sae_mode))
16616     abort ();
16617   if (modrm.mod == 3 && vex.b)
16618     switch (bytemode)
16619       {
16620       case evex_rounding_64_mode:
16621         if (address_mode != mode_64bit)
16622           {
16623             oappend ("(bad)");
16624             break;
16625           }
16626         /* Fall through.  */
16627       case evex_rounding_mode:
16628         oappend (names_rounding[vex.ll]);
16629         break;
16630       case evex_sae_mode:
16631         oappend ("{sae}");
16632         break;
16633       default:
16634         break;
16635       }
16636 }