opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 #define XX { NULL, 0 }
 225 #define Bad_Opcode NULL, { { NULL, 0 } }
 226
 227 #define Eb { OP_E, b_mode }
 228 #define Ebnd { OP_E, bnd_mode }
 229 #define EbS { OP_E, b_swap_mode }
 230 #define Ev { OP_E, v_mode }
 231 #define Ev_bnd { OP_E, v_bnd_mode }
 232 #define EvS { OP_E, v_swap_mode }
 233 #define Ed { OP_E, d_mode }
 234 #define Edq { OP_E, dq_mode }
 235 #define Edqw { OP_E, dqw_mode }
 236 #define EdqwS { OP_E, dqw_swap_mode }
 237 #define Edqb { OP_E, dqb_mode }
 238 #define Edb { OP_E, db_mode }
 239 #define Edw { OP_E, dw_mode }
 240 #define Edqd { OP_E, dqd_mode }
 241 #define Eq { OP_E, q_mode }
 242 #define indirEv { OP_indirE, stack_v_mode }
 243 #define indirEp { OP_indirE, f_mode }
 244 #define stackEv { OP_E, stack_v_mode }
 245 #define Em { OP_E, m_mode }
 246 #define Ew { OP_E, w_mode }
 247 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 248 #define Ma { OP_M, a_mode }
 249 #define Mb { OP_M, b_mode }
 250 #define Md { OP_M, d_mode }
 251 #define Mo { OP_M, o_mode }
 252 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 253 #define Mq { OP_M, q_mode }
 254 #define Mx { OP_M, x_mode }
 255 #define Mxmm { OP_M, xmm_mode }
 256 #define Gb { OP_G, b_mode }
 257 #define Gbnd { OP_G, bnd_mode }
 258 #define Gv { OP_G, v_mode }
 259 #define Gd { OP_G, d_mode }
 260 #define Gdq { OP_G, dq_mode }
 261 #define Gm { OP_G, m_mode }
 262 #define Gw { OP_G, w_mode }
 263 #define Rd { OP_R, d_mode }
 264 #define Rdq { OP_R, dq_mode }
 265 #define Rm { OP_R, m_mode }
 266 #define Ib { OP_I, b_mode }
 267 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 269 #define Iv { OP_I, v_mode }
 270 #define sIv { OP_sI, v_mode }
 271 #define Iq { OP_I, q_mode }
 272 #define Iv64 { OP_I64, v_mode }
 273 #define Iw { OP_I, w_mode }
 274 #define I1 { OP_I, const_1_mode }
 275 #define Jb { OP_J, b_mode }
 276 #define Jv { OP_J, v_mode }
 277 #define Cm { OP_C, m_mode }
 278 #define Dm { OP_D, m_mode }
 279 #define Td { OP_T, d_mode }
 280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 281
 282 #define RMeAX { OP_REG, eAX_reg }
 283 #define RMeBX { OP_REG, eBX_reg }
 284 #define RMeCX { OP_REG, eCX_reg }
 285 #define RMeDX { OP_REG, eDX_reg }
 286 #define RMeSP { OP_REG, eSP_reg }
 287 #define RMeBP { OP_REG, eBP_reg }
 288 #define RMeSI { OP_REG, eSI_reg }
 289 #define RMeDI { OP_REG, eDI_reg }
 290 #define RMrAX { OP_REG, rAX_reg }
 291 #define RMrBX { OP_REG, rBX_reg }
 292 #define RMrCX { OP_REG, rCX_reg }
 293 #define RMrDX { OP_REG, rDX_reg }
 294 #define RMrSP { OP_REG, rSP_reg }
 295 #define RMrBP { OP_REG, rBP_reg }
 296 #define RMrSI { OP_REG, rSI_reg }
 297 #define RMrDI { OP_REG, rDI_reg }
 298 #define RMAL { OP_REG, al_reg }
 299 #define RMCL { OP_REG, cl_reg }
 300 #define RMDL { OP_REG, dl_reg }
 301 #define RMBL { OP_REG, bl_reg }
 302 #define RMAH { OP_REG, ah_reg }
 303 #define RMCH { OP_REG, ch_reg }
 304 #define RMDH { OP_REG, dh_reg }
 305 #define RMBH { OP_REG, bh_reg }
 306 #define RMAX { OP_REG, ax_reg }
 307 #define RMDX { OP_REG, dx_reg }
 308
 309 #define eAX { OP_IMREG, eAX_reg }
 310 #define eBX { OP_IMREG, eBX_reg }
 311 #define eCX { OP_IMREG, eCX_reg }
 312 #define eDX { OP_IMREG, eDX_reg }
 313 #define eSP { OP_IMREG, eSP_reg }
 314 #define eBP { OP_IMREG, eBP_reg }
 315 #define eSI { OP_IMREG, eSI_reg }
 316 #define eDI { OP_IMREG, eDI_reg }
 317 #define AL { OP_IMREG, al_reg }
 318 #define CL { OP_IMREG, cl_reg }
 319 #define DL { OP_IMREG, dl_reg }
 320 #define BL { OP_IMREG, bl_reg }
 321 #define AH { OP_IMREG, ah_reg }
 322 #define CH { OP_IMREG, ch_reg }
 323 #define DH { OP_IMREG, dh_reg }
 324 #define BH { OP_IMREG, bh_reg }
 325 #define AX { OP_IMREG, ax_reg }
 326 #define DX { OP_IMREG, dx_reg }
 327 #define zAX { OP_IMREG, z_mode_ax_reg }
 328 #define indirDX { OP_IMREG, indir_dx_reg }
 329
 330 #define Sw { OP_SEG, w_mode }
 331 #define Sv { OP_SEG, v_mode }
 332 #define Ap { OP_DIR, 0 }
 333 #define Ob { OP_OFF64, b_mode }
 334 #define Ov { OP_OFF64, v_mode }
 335 #define Xb { OP_DSreg, eSI_reg }
 336 #define Xv { OP_DSreg, eSI_reg }
 337 #define Xz { OP_DSreg, eSI_reg }
 338 #define Yb { OP_ESreg, eDI_reg }
 339 #define Yv { OP_ESreg, eDI_reg }
 340 #define DSBX { OP_DSreg, eBX_reg }
 341
 342 #define es { OP_REG, es_reg }
 343 #define ss { OP_REG, ss_reg }
 344 #define cs { OP_REG, cs_reg }
 345 #define ds { OP_REG, ds_reg }
 346 #define fs { OP_REG, fs_reg }
 347 #define gs { OP_REG, gs_reg }
 348
 349 #define MX { OP_MMX, 0 }
 350 #define XM { OP_XMM, 0 }
 351 #define XMScalar { OP_XMM, scalar_mode }
 352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 353 #define XMM { OP_XMM, xmm_mode }
 354 #define XMxmmq { OP_XMM, xmmq_mode }
 355 #define EM { OP_EM, v_mode }
 356 #define EMS { OP_EM, v_swap_mode }
 357 #define EMd { OP_EM, d_mode }
 358 #define EMx { OP_EM, x_mode }
 359 #define EXw { OP_EX, w_mode }
 360 #define EXd { OP_EX, d_mode }
 361 #define EXdScalar { OP_EX, d_scalar_mode }
 362 #define EXdS { OP_EX, d_swap_mode }
 363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 364 #define EXq { OP_EX, q_mode }
 365 #define EXqScalar { OP_EX, q_scalar_mode }
 366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 367 #define EXqS { OP_EX, q_swap_mode }
 368 #define EXx { OP_EX, x_mode }
 369 #define EXxS { OP_EX, x_swap_mode }
 370 #define EXxmm { OP_EX, xmm_mode }
 371 #define EXymm { OP_EX, ymm_mode }
 372 #define EXxmmq { OP_EX, xmmq_mode }
 373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 376 #define EXxmm_md { OP_EX, xmm_md_mode }
 377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 379 #define EXxmmdw { OP_EX, xmmdw_mode }
 380 #define EXxmmqd { OP_EX, xmmqd_mode }
 381 #define EXymmq { OP_EX, ymmq_mode }
 382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 386 #define MS { OP_MS, v_mode }
 387 #define XS { OP_XS, v_mode }
 388 #define EMCq { OP_EMC, q_mode }
 389 #define MXC { OP_MXC, 0 }
 390 #define OPSUF { OP_3DNowSuffix, 0 }
 391 #define CMP { CMP_Fixup, 0 }
 392 #define XMM0 { XMM_Fixup, 0 }
 393 #define FXSAVE { FXSAVE_Fixup, 0 }
 394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 396
 397 #define Vex { OP_VEX, vex_mode }
 398 #define VexScalar { OP_VEX, vex_scalar_mode }
 399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 400 #define Vex128 { OP_VEX, vex128_mode }
 401 #define Vex256 { OP_VEX, vex256_mode }
 402 #define VexGdq { OP_VEX, dq_mode }
 403 #define VexI4 { VEXI4_Fixup, 0}
 404 #define EXdVex { OP_EX_Vex, d_mode }
 405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 407 #define EXqVex { OP_EX_Vex, q_mode }
 408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 410 #define EXVexW { OP_EX_VexW, x_mode }
 411 #define EXdVexW { OP_EX_VexW, d_mode }
 412 #define EXqVexW { OP_EX_VexW, q_mode }
 413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 414 #define XMVex { OP_XMM_Vex, 0 }
 415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 416 #define XMVexW { OP_XMM_VexW, 0 }
 417 #define XMVexI4 { OP_REG_VexI4, x_mode }
 418 #define PCLMUL { PCLMUL_Fixup, 0 }
 419 #define VZERO { VZERO_Fixup, 0 }
 420 #define VCMP { VCMP_Fixup, 0 }
 421 #define VPCMP { VPCMP_Fixup, 0 }
 422
 423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 425
 426 #define XMask { OP_Mask, mask_mode }
 427 #define MaskG { OP_G, mask_mode }
 428 #define MaskE { OP_E, mask_mode }
 429 #define MaskBDE { OP_E, mask_bd_mode }
 430 #define MaskR { OP_R, mask_mode }
 431 #define MaskVex { OP_VEX, mask_mode }
 432
 433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 437
 438 /* Used handle "rep" prefix for string instructions.  */
 439 #define Xbr { REP_Fixup, eSI_reg }
 440 #define Xvr { REP_Fixup, eSI_reg }
 441 #define Ybr { REP_Fixup, eDI_reg }
 442 #define Yvr { REP_Fixup, eDI_reg }
 443 #define Yzr { REP_Fixup, eDI_reg }
 444 #define indirDXr { REP_Fixup, indir_dx_reg }
 445 #define ALr { REP_Fixup, al_reg }
 446 #define eAXr { REP_Fixup, eAX_reg }
 447
 448 /* Used handle HLE prefix for lockable instructions.  */
 449 #define Ebh1 { HLE_Fixup1, b_mode }
 450 #define Evh1 { HLE_Fixup1, v_mode }
 451 #define Ebh2 { HLE_Fixup2, b_mode }
 452 #define Evh2 { HLE_Fixup2, v_mode }
 453 #define Ebh3 { HLE_Fixup3, b_mode }
 454 #define Evh3 { HLE_Fixup3, v_mode }
 455
 456 #define BND { BND_Fixup, 0 }
 457
 458 #define cond_jump_flag { NULL, cond_jump_mode }
 459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 460
 461 /* bits in sizeflag */
 462 #define SUFFIX_ALWAYS 4
 463 #define AFLAG 2
 464 #define DFLAG 1
 465
 466 enum
 467 {
 468   /* byte operand */
 469   b_mode = 1,
 470   /* byte operand with operand swapped */
 471   b_swap_mode,
 472   /* byte operand, sign extend like 'T' suffix */
 473   b_T_mode,
 474   /* operand size depends on prefixes */
 475   v_mode,
 476   /* operand size depends on prefixes with operand swapped */
 477   v_swap_mode,
 478   /* word operand */
 479   w_mode,
 480   /* double word operand  */
 481   d_mode,
 482   /* double word operand with operand swapped */
 483   d_swap_mode,
 484   /* quad word operand */
 485   q_mode,
 486   /* quad word operand with operand swapped */
 487   q_swap_mode,
 488   /* ten-byte operand */
 489   t_mode,
 490   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 491      broadcast enabled.  */
 492   x_mode,
 493   /* Similar to x_mode, but with different EVEX mem shifts.  */
 494   evex_x_gscat_mode,
 495   /* Similar to x_mode, but with disabled broadcast.  */
 496   evex_x_nobcst_mode,
 497   /* Similar to x_mode, but with operands swapped and disabled broadcast
 498      in EVEX.  */
 499   x_swap_mode,
 500   /* 16-byte XMM operand */
 501   xmm_mode,
 502   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 503      memory operand (depending on vector length).  Broadcast isn't
 504      allowed.  */
 505   xmmq_mode,
 506   /* Same as xmmq_mode, but broadcast is allowed.  */
 507   evex_half_bcst_xmmq_mode,
 508   /* XMM register or byte memory operand */
 509   xmm_mb_mode,
 510   /* XMM register or word memory operand */
 511   xmm_mw_mode,
 512   /* XMM register or double word memory operand */
 513   xmm_md_mode,
 514   /* XMM register or quad word memory operand */
 515   xmm_mq_mode,
 516   /* XMM register or double/quad word memory operand, depending on
 517      VEX.W.  */
 518   xmm_mdq_mode,
 519   /* 16-byte XMM, word, double word or quad word operand.  */
 520   xmmdw_mode,
 521   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 522   xmmqd_mode,
 523   /* 32-byte YMM operand */
 524   ymm_mode,
 525   /* quad word, ymmword or zmmword memory operand.  */
 526   ymmq_mode,
 527   /* 32-byte YMM or 16-byte word operand */
 528   ymmxmm_mode,
 529   /* d_mode in 32bit, q_mode in 64bit mode.  */
 530   m_mode,
 531   /* pair of v_mode operands */
 532   a_mode,
 533   cond_jump_mode,
 534   loop_jcxz_mode,
 535   v_bnd_mode,
 536   /* operand size depends on REX prefixes.  */
 537   dq_mode,
 538   /* registers like dq_mode, memory like w_mode.  */
 539   dqw_mode,
 540   dqw_swap_mode,
 541   bnd_mode,
 542   /* 4- or 6-byte pointer operand */
 543   f_mode,
 544   const_1_mode,
 545   /* v_mode for stack-related opcodes.  */
 546   stack_v_mode,
 547   /* non-quad operand size depends on prefixes */
 548   z_mode,
 549   /* 16-byte operand */
 550   o_mode,
 551   /* registers like dq_mode, memory like b_mode.  */
 552   dqb_mode,
 553   /* registers like d_mode, memory like b_mode.  */
 554   db_mode,
 555   /* registers like d_mode, memory like w_mode.  */
 556   dw_mode,
 557   /* registers like dq_mode, memory like d_mode.  */
 558   dqd_mode,
 559   /* normal vex mode */
 560   vex_mode,
 561   /* 128bit vex mode */
 562   vex128_mode,
 563   /* 256bit vex mode */
 564   vex256_mode,
 565   /* operand size depends on the VEX.W bit.  */
 566   vex_w_dq_mode,
 567
 568   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 569   vex_vsib_d_w_dq_mode,
 570   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 571   vex_vsib_d_w_d_mode,
 572   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 573   vex_vsib_q_w_dq_mode,
 574   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 575   vex_vsib_q_w_d_mode,
 576
 577   /* scalar, ignore vector length.  */
 578   scalar_mode,
 579   /* like d_mode, ignore vector length.  */
 580   d_scalar_mode,
 581   /* like d_swap_mode, ignore vector length.  */
 582   d_scalar_swap_mode,
 583   /* like q_mode, ignore vector length.  */
 584   q_scalar_mode,
 585   /* like q_swap_mode, ignore vector length.  */
 586   q_scalar_swap_mode,
 587   /* like vex_mode, ignore vector length.  */
 588   vex_scalar_mode,
 589   /* like vex_w_dq_mode, ignore vector length.  */
 590   vex_scalar_w_dq_mode,
 591
 592   /* Static rounding.  */
 593   evex_rounding_mode,
 594   /* Supress all exceptions.  */
 595   evex_sae_mode,
 596
 597   /* Mask register operand.  */
 598   mask_mode,
 599   /* Mask register operand.  */
 600   mask_bd_mode,
 601
 602   es_reg,
 603   cs_reg,
 604   ss_reg,
 605   ds_reg,
 606   fs_reg,
 607   gs_reg,
 608
 609   eAX_reg,
 610   eCX_reg,
 611   eDX_reg,
 612   eBX_reg,
 613   eSP_reg,
 614   eBP_reg,
 615   eSI_reg,
 616   eDI_reg,
 617
 618   al_reg,
 619   cl_reg,
 620   dl_reg,
 621   bl_reg,
 622   ah_reg,
 623   ch_reg,
 624   dh_reg,
 625   bh_reg,
 626
 627   ax_reg,
 628   cx_reg,
 629   dx_reg,
 630   bx_reg,
 631   sp_reg,
 632   bp_reg,
 633   si_reg,
 634   di_reg,
 635
 636   rAX_reg,
 637   rCX_reg,
 638   rDX_reg,
 639   rBX_reg,
 640   rSP_reg,
 641   rBP_reg,
 642   rSI_reg,
 643   rDI_reg,
 644
 645   z_mode_ax_reg,
 646   indir_dx_reg
 647 };
 648
 649 enum
 650 {
 651   FLOATCODE = 1,
 652   USE_REG_TABLE,
 653   USE_MOD_TABLE,
 654   USE_RM_TABLE,
 655   USE_PREFIX_TABLE,
 656   USE_X86_64_TABLE,
 657   USE_3BYTE_TABLE,
 658   USE_XOP_8F_TABLE,
 659   USE_VEX_C4_TABLE,
 660   USE_VEX_C5_TABLE,
 661   USE_VEX_LEN_TABLE,
 662   USE_VEX_W_TABLE,
 663   USE_EVEX_TABLE
 664 };
 665
 666 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 667
 668 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 669 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 670 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 671 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 672 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 673 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 674 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 675 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 676 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 677 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 678 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 679 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 680 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 681
 682 enum
 683 {
 684   REG_80 = 0,
 685   REG_81,
 686   REG_82,
 687   REG_8F,
 688   REG_C0,
 689   REG_C1,
 690   REG_C6,
 691   REG_C7,
 692   REG_D0,
 693   REG_D1,
 694   REG_D2,
 695   REG_D3,
 696   REG_F6,
 697   REG_F7,
 698   REG_FE,
 699   REG_FF,
 700   REG_0F00,
 701   REG_0F01,
 702   REG_0F0D,
 703   REG_0F18,
 704   REG_0F71,
 705   REG_0F72,
 706   REG_0F73,
 707   REG_0FA6,
 708   REG_0FA7,
 709   REG_0FAE,
 710   REG_0FBA,
 711   REG_0FC7,
 712   REG_VEX_0F71,
 713   REG_VEX_0F72,
 714   REG_VEX_0F73,
 715   REG_VEX_0FAE,
 716   REG_VEX_0F38F3,
 717   REG_XOP_LWPCB,
 718   REG_XOP_LWP,
 719   REG_XOP_TBM_01,
 720   REG_XOP_TBM_02,
 721
 722   REG_EVEX_0F71,
 723   REG_EVEX_0F72,
 724   REG_EVEX_0F73,
 725   REG_EVEX_0F38C6,
 726   REG_EVEX_0F38C7
 727 };
 728
 729 enum
 730 {
 731   MOD_8D = 0,
 732   MOD_C6_REG_7,
 733   MOD_C7_REG_7,
 734   MOD_FF_REG_3,
 735   MOD_FF_REG_5,
 736   MOD_0F01_REG_0,
 737   MOD_0F01_REG_1,
 738   MOD_0F01_REG_2,
 739   MOD_0F01_REG_3,
 740   MOD_0F01_REG_7,
 741   MOD_0F12_PREFIX_0,
 742   MOD_0F13,
 743   MOD_0F16_PREFIX_0,
 744   MOD_0F17,
 745   MOD_0F18_REG_0,
 746   MOD_0F18_REG_1,
 747   MOD_0F18_REG_2,
 748   MOD_0F18_REG_3,
 749   MOD_0F18_REG_4,
 750   MOD_0F18_REG_5,
 751   MOD_0F18_REG_6,
 752   MOD_0F18_REG_7,
 753   MOD_0F1A_PREFIX_0,
 754   MOD_0F1B_PREFIX_0,
 755   MOD_0F1B_PREFIX_1,
 756   MOD_0F24,
 757   MOD_0F26,
 758   MOD_0F2B_PREFIX_0,
 759   MOD_0F2B_PREFIX_1,
 760   MOD_0F2B_PREFIX_2,
 761   MOD_0F2B_PREFIX_3,
 762   MOD_0F51,
 763   MOD_0F71_REG_2,
 764   MOD_0F71_REG_4,
 765   MOD_0F71_REG_6,
 766   MOD_0F72_REG_2,
 767   MOD_0F72_REG_4,
 768   MOD_0F72_REG_6,
 769   MOD_0F73_REG_2,
 770   MOD_0F73_REG_3,
 771   MOD_0F73_REG_6,
 772   MOD_0F73_REG_7,
 773   MOD_0FAE_REG_0,
 774   MOD_0FAE_REG_1,
 775   MOD_0FAE_REG_2,
 776   MOD_0FAE_REG_3,
 777   MOD_0FAE_REG_4,
 778   MOD_0FAE_REG_5,
 779   MOD_0FAE_REG_6,
 780   MOD_0FAE_REG_7,
 781   MOD_0FB2,
 782   MOD_0FB4,
 783   MOD_0FB5,
 784   MOD_0FC7_REG_3,
 785   MOD_0FC7_REG_4,
 786   MOD_0FC7_REG_5,
 787   MOD_0FC7_REG_6,
 788   MOD_0FC7_REG_7,
 789   MOD_0FD7,
 790   MOD_0FE7_PREFIX_2,
 791   MOD_0FF0_PREFIX_3,
 792   MOD_0F382A_PREFIX_2,
 793   MOD_62_32BIT,
 794   MOD_C4_32BIT,
 795   MOD_C5_32BIT,
 796   MOD_VEX_0F12_PREFIX_0,
 797   MOD_VEX_0F13,
 798   MOD_VEX_0F16_PREFIX_0,
 799   MOD_VEX_0F17,
 800   MOD_VEX_0F2B,
 801   MOD_VEX_0F50,
 802   MOD_VEX_0F71_REG_2,
 803   MOD_VEX_0F71_REG_4,
 804   MOD_VEX_0F71_REG_6,
 805   MOD_VEX_0F72_REG_2,
 806   MOD_VEX_0F72_REG_4,
 807   MOD_VEX_0F72_REG_6,
 808   MOD_VEX_0F73_REG_2,
 809   MOD_VEX_0F73_REG_3,
 810   MOD_VEX_0F73_REG_6,
 811   MOD_VEX_0F73_REG_7,
 812   MOD_VEX_0FAE_REG_2,
 813   MOD_VEX_0FAE_REG_3,
 814   MOD_VEX_0FD7_PREFIX_2,
 815   MOD_VEX_0FE7_PREFIX_2,
 816   MOD_VEX_0FF0_PREFIX_3,
 817   MOD_VEX_0F381A_PREFIX_2,
 818   MOD_VEX_0F382A_PREFIX_2,
 819   MOD_VEX_0F382C_PREFIX_2,
 820   MOD_VEX_0F382D_PREFIX_2,
 821   MOD_VEX_0F382E_PREFIX_2,
 822   MOD_VEX_0F382F_PREFIX_2,
 823   MOD_VEX_0F385A_PREFIX_2,
 824   MOD_VEX_0F388C_PREFIX_2,
 825   MOD_VEX_0F388E_PREFIX_2,
 826
 827   MOD_EVEX_0F10_PREFIX_1,
 828   MOD_EVEX_0F10_PREFIX_3,
 829   MOD_EVEX_0F11_PREFIX_1,
 830   MOD_EVEX_0F11_PREFIX_3,
 831   MOD_EVEX_0F12_PREFIX_0,
 832   MOD_EVEX_0F16_PREFIX_0,
 833   MOD_EVEX_0F38C6_REG_1,
 834   MOD_EVEX_0F38C6_REG_2,
 835   MOD_EVEX_0F38C6_REG_5,
 836   MOD_EVEX_0F38C6_REG_6,
 837   MOD_EVEX_0F38C7_REG_1,
 838   MOD_EVEX_0F38C7_REG_2,
 839   MOD_EVEX_0F38C7_REG_5,
 840   MOD_EVEX_0F38C7_REG_6
 841 };
 842
 843 enum
 844 {
 845   RM_C6_REG_7 = 0,
 846   RM_C7_REG_7,
 847   RM_0F01_REG_0,
 848   RM_0F01_REG_1,
 849   RM_0F01_REG_2,
 850   RM_0F01_REG_3,
 851   RM_0F01_REG_7,
 852   RM_0FAE_REG_5,
 853   RM_0FAE_REG_6,
 854   RM_0FAE_REG_7
 855 };
 856
 857 enum
 858 {
 859   PREFIX_90 = 0,
 860   PREFIX_0F10,
 861   PREFIX_0F11,
 862   PREFIX_0F12,
 863   PREFIX_0F16,
 864   PREFIX_0F1A,
 865   PREFIX_0F1B,
 866   PREFIX_0F2A,
 867   PREFIX_0F2B,
 868   PREFIX_0F2C,
 869   PREFIX_0F2D,
 870   PREFIX_0F2E,
 871   PREFIX_0F2F,
 872   PREFIX_0F51,
 873   PREFIX_0F52,
 874   PREFIX_0F53,
 875   PREFIX_0F58,
 876   PREFIX_0F59,
 877   PREFIX_0F5A,
 878   PREFIX_0F5B,
 879   PREFIX_0F5C,
 880   PREFIX_0F5D,
 881   PREFIX_0F5E,
 882   PREFIX_0F5F,
 883   PREFIX_0F60,
 884   PREFIX_0F61,
 885   PREFIX_0F62,
 886   PREFIX_0F6C,
 887   PREFIX_0F6D,
 888   PREFIX_0F6F,
 889   PREFIX_0F70,
 890   PREFIX_0F73_REG_3,
 891   PREFIX_0F73_REG_7,
 892   PREFIX_0F78,
 893   PREFIX_0F79,
 894   PREFIX_0F7C,
 895   PREFIX_0F7D,
 896   PREFIX_0F7E,
 897   PREFIX_0F7F,
 898   PREFIX_0FAE_REG_0,
 899   PREFIX_0FAE_REG_1,
 900   PREFIX_0FAE_REG_2,
 901   PREFIX_0FAE_REG_3,
 902   PREFIX_0FAE_REG_6,
 903   PREFIX_0FAE_REG_7,
 904   PREFIX_RM_0_0FAE_REG_7,
 905   PREFIX_0FB8,
 906   PREFIX_0FBC,
 907   PREFIX_0FBD,
 908   PREFIX_0FC2,
 909   PREFIX_0FC3,
 910   PREFIX_0FC7_REG_6,
 911   PREFIX_0FD0,
 912   PREFIX_0FD6,
 913   PREFIX_0FE6,
 914   PREFIX_0FE7,
 915   PREFIX_0FF0,
 916   PREFIX_0FF7,
 917   PREFIX_0F3810,
 918   PREFIX_0F3814,
 919   PREFIX_0F3815,
 920   PREFIX_0F3817,
 921   PREFIX_0F3820,
 922   PREFIX_0F3821,
 923   PREFIX_0F3822,
 924   PREFIX_0F3823,
 925   PREFIX_0F3824,
 926   PREFIX_0F3825,
 927   PREFIX_0F3828,
 928   PREFIX_0F3829,
 929   PREFIX_0F382A,
 930   PREFIX_0F382B,
 931   PREFIX_0F3830,
 932   PREFIX_0F3831,
 933   PREFIX_0F3832,
 934   PREFIX_0F3833,
 935   PREFIX_0F3834,
 936   PREFIX_0F3835,
 937   PREFIX_0F3837,
 938   PREFIX_0F3838,
 939   PREFIX_0F3839,
 940   PREFIX_0F383A,
 941   PREFIX_0F383B,
 942   PREFIX_0F383C,
 943   PREFIX_0F383D,
 944   PREFIX_0F383E,
 945   PREFIX_0F383F,
 946   PREFIX_0F3840,
 947   PREFIX_0F3841,
 948   PREFIX_0F3880,
 949   PREFIX_0F3881,
 950   PREFIX_0F3882,
 951   PREFIX_0F38C8,
 952   PREFIX_0F38C9,
 953   PREFIX_0F38CA,
 954   PREFIX_0F38CB,
 955   PREFIX_0F38CC,
 956   PREFIX_0F38CD,
 957   PREFIX_0F38DB,
 958   PREFIX_0F38DC,
 959   PREFIX_0F38DD,
 960   PREFIX_0F38DE,
 961   PREFIX_0F38DF,
 962   PREFIX_0F38F0,
 963   PREFIX_0F38F1,
 964   PREFIX_0F38F6,
 965   PREFIX_0F3A08,
 966   PREFIX_0F3A09,
 967   PREFIX_0F3A0A,
 968   PREFIX_0F3A0B,
 969   PREFIX_0F3A0C,
 970   PREFIX_0F3A0D,
 971   PREFIX_0F3A0E,
 972   PREFIX_0F3A14,
 973   PREFIX_0F3A15,
 974   PREFIX_0F3A16,
 975   PREFIX_0F3A17,
 976   PREFIX_0F3A20,
 977   PREFIX_0F3A21,
 978   PREFIX_0F3A22,
 979   PREFIX_0F3A40,
 980   PREFIX_0F3A41,
 981   PREFIX_0F3A42,
 982   PREFIX_0F3A44,
 983   PREFIX_0F3A60,
 984   PREFIX_0F3A61,
 985   PREFIX_0F3A62,
 986   PREFIX_0F3A63,
 987   PREFIX_0F3ACC,
 988   PREFIX_0F3ADF,
 989   PREFIX_VEX_0F10,
 990   PREFIX_VEX_0F11,
 991   PREFIX_VEX_0F12,
 992   PREFIX_VEX_0F16,
 993   PREFIX_VEX_0F2A,
 994   PREFIX_VEX_0F2C,
 995   PREFIX_VEX_0F2D,
 996   PREFIX_VEX_0F2E,
 997   PREFIX_VEX_0F2F,
 998   PREFIX_VEX_0F41,
 999   PREFIX_VEX_0F42,
1000   PREFIX_VEX_0F44,
1001   PREFIX_VEX_0F45,
1002   PREFIX_VEX_0F46,
1003   PREFIX_VEX_0F47,
1004   PREFIX_VEX_0F4A,
1005   PREFIX_VEX_0F4B,
1006   PREFIX_VEX_0F51,
1007   PREFIX_VEX_0F52,
1008   PREFIX_VEX_0F53,
1009   PREFIX_VEX_0F58,
1010   PREFIX_VEX_0F59,
1011   PREFIX_VEX_0F5A,
1012   PREFIX_VEX_0F5B,
1013   PREFIX_VEX_0F5C,
1014   PREFIX_VEX_0F5D,
1015   PREFIX_VEX_0F5E,
1016   PREFIX_VEX_0F5F,
1017   PREFIX_VEX_0F60,
1018   PREFIX_VEX_0F61,
1019   PREFIX_VEX_0F62,
1020   PREFIX_VEX_0F63,
1021   PREFIX_VEX_0F64,
1022   PREFIX_VEX_0F65,
1023   PREFIX_VEX_0F66,
1024   PREFIX_VEX_0F67,
1025   PREFIX_VEX_0F68,
1026   PREFIX_VEX_0F69,
1027   PREFIX_VEX_0F6A,
1028   PREFIX_VEX_0F6B,
1029   PREFIX_VEX_0F6C,
1030   PREFIX_VEX_0F6D,
1031   PREFIX_VEX_0F6E,
1032   PREFIX_VEX_0F6F,
1033   PREFIX_VEX_0F70,
1034   PREFIX_VEX_0F71_REG_2,
1035   PREFIX_VEX_0F71_REG_4,
1036   PREFIX_VEX_0F71_REG_6,
1037   PREFIX_VEX_0F72_REG_2,
1038   PREFIX_VEX_0F72_REG_4,
1039   PREFIX_VEX_0F72_REG_6,
1040   PREFIX_VEX_0F73_REG_2,
1041   PREFIX_VEX_0F73_REG_3,
1042   PREFIX_VEX_0F73_REG_6,
1043   PREFIX_VEX_0F73_REG_7,
1044   PREFIX_VEX_0F74,
1045   PREFIX_VEX_0F75,
1046   PREFIX_VEX_0F76,
1047   PREFIX_VEX_0F77,
1048   PREFIX_VEX_0F7C,
1049   PREFIX_VEX_0F7D,
1050   PREFIX_VEX_0F7E,
1051   PREFIX_VEX_0F7F,
1052   PREFIX_VEX_0F90,
1053   PREFIX_VEX_0F91,
1054   PREFIX_VEX_0F92,
1055   PREFIX_VEX_0F93,
1056   PREFIX_VEX_0F98,
1057   PREFIX_VEX_0F99,
1058   PREFIX_VEX_0FC2,
1059   PREFIX_VEX_0FC4,
1060   PREFIX_VEX_0FC5,
1061   PREFIX_VEX_0FD0,
1062   PREFIX_VEX_0FD1,
1063   PREFIX_VEX_0FD2,
1064   PREFIX_VEX_0FD3,
1065   PREFIX_VEX_0FD4,
1066   PREFIX_VEX_0FD5,
1067   PREFIX_VEX_0FD6,
1068   PREFIX_VEX_0FD7,
1069   PREFIX_VEX_0FD8,
1070   PREFIX_VEX_0FD9,
1071   PREFIX_VEX_0FDA,
1072   PREFIX_VEX_0FDB,
1073   PREFIX_VEX_0FDC,
1074   PREFIX_VEX_0FDD,
1075   PREFIX_VEX_0FDE,
1076   PREFIX_VEX_0FDF,
1077   PREFIX_VEX_0FE0,
1078   PREFIX_VEX_0FE1,
1079   PREFIX_VEX_0FE2,
1080   PREFIX_VEX_0FE3,
1081   PREFIX_VEX_0FE4,
1082   PREFIX_VEX_0FE5,
1083   PREFIX_VEX_0FE6,
1084   PREFIX_VEX_0FE7,
1085   PREFIX_VEX_0FE8,
1086   PREFIX_VEX_0FE9,
1087   PREFIX_VEX_0FEA,
1088   PREFIX_VEX_0FEB,
1089   PREFIX_VEX_0FEC,
1090   PREFIX_VEX_0FED,
1091   PREFIX_VEX_0FEE,
1092   PREFIX_VEX_0FEF,
1093   PREFIX_VEX_0FF0,
1094   PREFIX_VEX_0FF1,
1095   PREFIX_VEX_0FF2,
1096   PREFIX_VEX_0FF3,
1097   PREFIX_VEX_0FF4,
1098   PREFIX_VEX_0FF5,
1099   PREFIX_VEX_0FF6,
1100   PREFIX_VEX_0FF7,
1101   PREFIX_VEX_0FF8,
1102   PREFIX_VEX_0FF9,
1103   PREFIX_VEX_0FFA,
1104   PREFIX_VEX_0FFB,
1105   PREFIX_VEX_0FFC,
1106   PREFIX_VEX_0FFD,
1107   PREFIX_VEX_0FFE,
1108   PREFIX_VEX_0F3800,
1109   PREFIX_VEX_0F3801,
1110   PREFIX_VEX_0F3802,
1111   PREFIX_VEX_0F3803,
1112   PREFIX_VEX_0F3804,
1113   PREFIX_VEX_0F3805,
1114   PREFIX_VEX_0F3806,
1115   PREFIX_VEX_0F3807,
1116   PREFIX_VEX_0F3808,
1117   PREFIX_VEX_0F3809,
1118   PREFIX_VEX_0F380A,
1119   PREFIX_VEX_0F380B,
1120   PREFIX_VEX_0F380C,
1121   PREFIX_VEX_0F380D,
1122   PREFIX_VEX_0F380E,
1123   PREFIX_VEX_0F380F,
1124   PREFIX_VEX_0F3813,
1125   PREFIX_VEX_0F3816,
1126   PREFIX_VEX_0F3817,
1127   PREFIX_VEX_0F3818,
1128   PREFIX_VEX_0F3819,
1129   PREFIX_VEX_0F381A,
1130   PREFIX_VEX_0F381C,
1131   PREFIX_VEX_0F381D,
1132   PREFIX_VEX_0F381E,
1133   PREFIX_VEX_0F3820,
1134   PREFIX_VEX_0F3821,
1135   PREFIX_VEX_0F3822,
1136   PREFIX_VEX_0F3823,
1137   PREFIX_VEX_0F3824,
1138   PREFIX_VEX_0F3825,
1139   PREFIX_VEX_0F3828,
1140   PREFIX_VEX_0F3829,
1141   PREFIX_VEX_0F382A,
1142   PREFIX_VEX_0F382B,
1143   PREFIX_VEX_0F382C,
1144   PREFIX_VEX_0F382D,
1145   PREFIX_VEX_0F382E,
1146   PREFIX_VEX_0F382F,
1147   PREFIX_VEX_0F3830,
1148   PREFIX_VEX_0F3831,
1149   PREFIX_VEX_0F3832,
1150   PREFIX_VEX_0F3833,
1151   PREFIX_VEX_0F3834,
1152   PREFIX_VEX_0F3835,
1153   PREFIX_VEX_0F3836,
1154   PREFIX_VEX_0F3837,
1155   PREFIX_VEX_0F3838,
1156   PREFIX_VEX_0F3839,
1157   PREFIX_VEX_0F383A,
1158   PREFIX_VEX_0F383B,
1159   PREFIX_VEX_0F383C,
1160   PREFIX_VEX_0F383D,
1161   PREFIX_VEX_0F383E,
1162   PREFIX_VEX_0F383F,
1163   PREFIX_VEX_0F3840,
1164   PREFIX_VEX_0F3841,
1165   PREFIX_VEX_0F3845,
1166   PREFIX_VEX_0F3846,
1167   PREFIX_VEX_0F3847,
1168   PREFIX_VEX_0F3858,
1169   PREFIX_VEX_0F3859,
1170   PREFIX_VEX_0F385A,
1171   PREFIX_VEX_0F3878,
1172   PREFIX_VEX_0F3879,
1173   PREFIX_VEX_0F388C,
1174   PREFIX_VEX_0F388E,
1175   PREFIX_VEX_0F3890,
1176   PREFIX_VEX_0F3891,
1177   PREFIX_VEX_0F3892,
1178   PREFIX_VEX_0F3893,
1179   PREFIX_VEX_0F3896,
1180   PREFIX_VEX_0F3897,
1181   PREFIX_VEX_0F3898,
1182   PREFIX_VEX_0F3899,
1183   PREFIX_VEX_0F389A,
1184   PREFIX_VEX_0F389B,
1185   PREFIX_VEX_0F389C,
1186   PREFIX_VEX_0F389D,
1187   PREFIX_VEX_0F389E,
1188   PREFIX_VEX_0F389F,
1189   PREFIX_VEX_0F38A6,
1190   PREFIX_VEX_0F38A7,
1191   PREFIX_VEX_0F38A8,
1192   PREFIX_VEX_0F38A9,
1193   PREFIX_VEX_0F38AA,
1194   PREFIX_VEX_0F38AB,
1195   PREFIX_VEX_0F38AC,
1196   PREFIX_VEX_0F38AD,
1197   PREFIX_VEX_0F38AE,
1198   PREFIX_VEX_0F38AF,
1199   PREFIX_VEX_0F38B6,
1200   PREFIX_VEX_0F38B7,
1201   PREFIX_VEX_0F38B8,
1202   PREFIX_VEX_0F38B9,
1203   PREFIX_VEX_0F38BA,
1204   PREFIX_VEX_0F38BB,
1205   PREFIX_VEX_0F38BC,
1206   PREFIX_VEX_0F38BD,
1207   PREFIX_VEX_0F38BE,
1208   PREFIX_VEX_0F38BF,
1209   PREFIX_VEX_0F38DB,
1210   PREFIX_VEX_0F38DC,
1211   PREFIX_VEX_0F38DD,
1212   PREFIX_VEX_0F38DE,
1213   PREFIX_VEX_0F38DF,
1214   PREFIX_VEX_0F38F2,
1215   PREFIX_VEX_0F38F3_REG_1,
1216   PREFIX_VEX_0F38F3_REG_2,
1217   PREFIX_VEX_0F38F3_REG_3,
1218   PREFIX_VEX_0F38F5,
1219   PREFIX_VEX_0F38F6,
1220   PREFIX_VEX_0F38F7,
1221   PREFIX_VEX_0F3A00,
1222   PREFIX_VEX_0F3A01,
1223   PREFIX_VEX_0F3A02,
1224   PREFIX_VEX_0F3A04,
1225   PREFIX_VEX_0F3A05,
1226   PREFIX_VEX_0F3A06,
1227   PREFIX_VEX_0F3A08,
1228   PREFIX_VEX_0F3A09,
1229   PREFIX_VEX_0F3A0A,
1230   PREFIX_VEX_0F3A0B,
1231   PREFIX_VEX_0F3A0C,
1232   PREFIX_VEX_0F3A0D,
1233   PREFIX_VEX_0F3A0E,
1234   PREFIX_VEX_0F3A0F,
1235   PREFIX_VEX_0F3A14,
1236   PREFIX_VEX_0F3A15,
1237   PREFIX_VEX_0F3A16,
1238   PREFIX_VEX_0F3A17,
1239   PREFIX_VEX_0F3A18,
1240   PREFIX_VEX_0F3A19,
1241   PREFIX_VEX_0F3A1D,
1242   PREFIX_VEX_0F3A20,
1243   PREFIX_VEX_0F3A21,
1244   PREFIX_VEX_0F3A22,
1245   PREFIX_VEX_0F3A30,
1246   PREFIX_VEX_0F3A31,
1247   PREFIX_VEX_0F3A32,
1248   PREFIX_VEX_0F3A33,
1249   PREFIX_VEX_0F3A38,
1250   PREFIX_VEX_0F3A39,
1251   PREFIX_VEX_0F3A40,
1252   PREFIX_VEX_0F3A41,
1253   PREFIX_VEX_0F3A42,
1254   PREFIX_VEX_0F3A44,
1255   PREFIX_VEX_0F3A46,
1256   PREFIX_VEX_0F3A48,
1257   PREFIX_VEX_0F3A49,
1258   PREFIX_VEX_0F3A4A,
1259   PREFIX_VEX_0F3A4B,
1260   PREFIX_VEX_0F3A4C,
1261   PREFIX_VEX_0F3A5C,
1262   PREFIX_VEX_0F3A5D,
1263   PREFIX_VEX_0F3A5E,
1264   PREFIX_VEX_0F3A5F,
1265   PREFIX_VEX_0F3A60,
1266   PREFIX_VEX_0F3A61,
1267   PREFIX_VEX_0F3A62,
1268   PREFIX_VEX_0F3A63,
1269   PREFIX_VEX_0F3A68,
1270   PREFIX_VEX_0F3A69,
1271   PREFIX_VEX_0F3A6A,
1272   PREFIX_VEX_0F3A6B,
1273   PREFIX_VEX_0F3A6C,
1274   PREFIX_VEX_0F3A6D,
1275   PREFIX_VEX_0F3A6E,
1276   PREFIX_VEX_0F3A6F,
1277   PREFIX_VEX_0F3A78,
1278   PREFIX_VEX_0F3A79,
1279   PREFIX_VEX_0F3A7A,
1280   PREFIX_VEX_0F3A7B,
1281   PREFIX_VEX_0F3A7C,
1282   PREFIX_VEX_0F3A7D,
1283   PREFIX_VEX_0F3A7E,
1284   PREFIX_VEX_0F3A7F,
1285   PREFIX_VEX_0F3ADF,
1286   PREFIX_VEX_0F3AF0,
1287
1288   PREFIX_EVEX_0F10,
1289   PREFIX_EVEX_0F11,
1290   PREFIX_EVEX_0F12,
1291   PREFIX_EVEX_0F13,
1292   PREFIX_EVEX_0F14,
1293   PREFIX_EVEX_0F15,
1294   PREFIX_EVEX_0F16,
1295   PREFIX_EVEX_0F17,
1296   PREFIX_EVEX_0F28,
1297   PREFIX_EVEX_0F29,
1298   PREFIX_EVEX_0F2A,
1299   PREFIX_EVEX_0F2B,
1300   PREFIX_EVEX_0F2C,
1301   PREFIX_EVEX_0F2D,
1302   PREFIX_EVEX_0F2E,
1303   PREFIX_EVEX_0F2F,
1304   PREFIX_EVEX_0F51,
1305   PREFIX_EVEX_0F54,
1306   PREFIX_EVEX_0F55,
1307   PREFIX_EVEX_0F56,
1308   PREFIX_EVEX_0F57,
1309   PREFIX_EVEX_0F58,
1310   PREFIX_EVEX_0F59,
1311   PREFIX_EVEX_0F5A,
1312   PREFIX_EVEX_0F5B,
1313   PREFIX_EVEX_0F5C,
1314   PREFIX_EVEX_0F5D,
1315   PREFIX_EVEX_0F5E,
1316   PREFIX_EVEX_0F5F,
1317   PREFIX_EVEX_0F60,
1318   PREFIX_EVEX_0F61,
1319   PREFIX_EVEX_0F62,
1320   PREFIX_EVEX_0F63,
1321   PREFIX_EVEX_0F64,
1322   PREFIX_EVEX_0F65,
1323   PREFIX_EVEX_0F66,
1324   PREFIX_EVEX_0F67,
1325   PREFIX_EVEX_0F68,
1326   PREFIX_EVEX_0F69,
1327   PREFIX_EVEX_0F6A,
1328   PREFIX_EVEX_0F6B,
1329   PREFIX_EVEX_0F6C,
1330   PREFIX_EVEX_0F6D,
1331   PREFIX_EVEX_0F6E,
1332   PREFIX_EVEX_0F6F,
1333   PREFIX_EVEX_0F70,
1334   PREFIX_EVEX_0F71_REG_2,
1335   PREFIX_EVEX_0F71_REG_4,
1336   PREFIX_EVEX_0F71_REG_6,
1337   PREFIX_EVEX_0F72_REG_0,
1338   PREFIX_EVEX_0F72_REG_1,
1339   PREFIX_EVEX_0F72_REG_2,
1340   PREFIX_EVEX_0F72_REG_4,
1341   PREFIX_EVEX_0F72_REG_6,
1342   PREFIX_EVEX_0F73_REG_2,
1343   PREFIX_EVEX_0F73_REG_3,
1344   PREFIX_EVEX_0F73_REG_6,
1345   PREFIX_EVEX_0F73_REG_7,
1346   PREFIX_EVEX_0F74,
1347   PREFIX_EVEX_0F75,
1348   PREFIX_EVEX_0F76,
1349   PREFIX_EVEX_0F78,
1350   PREFIX_EVEX_0F79,
1351   PREFIX_EVEX_0F7A,
1352   PREFIX_EVEX_0F7B,
1353   PREFIX_EVEX_0F7E,
1354   PREFIX_EVEX_0F7F,
1355   PREFIX_EVEX_0FC2,
1356   PREFIX_EVEX_0FC4,
1357   PREFIX_EVEX_0FC5,
1358   PREFIX_EVEX_0FC6,
1359   PREFIX_EVEX_0FD1,
1360   PREFIX_EVEX_0FD2,
1361   PREFIX_EVEX_0FD3,
1362   PREFIX_EVEX_0FD4,
1363   PREFIX_EVEX_0FD5,
1364   PREFIX_EVEX_0FD6,
1365   PREFIX_EVEX_0FD8,
1366   PREFIX_EVEX_0FD9,
1367   PREFIX_EVEX_0FDA,
1368   PREFIX_EVEX_0FDB,
1369   PREFIX_EVEX_0FDC,
1370   PREFIX_EVEX_0FDD,
1371   PREFIX_EVEX_0FDE,
1372   PREFIX_EVEX_0FDF,
1373   PREFIX_EVEX_0FE0,
1374   PREFIX_EVEX_0FE1,
1375   PREFIX_EVEX_0FE2,
1376   PREFIX_EVEX_0FE3,
1377   PREFIX_EVEX_0FE4,
1378   PREFIX_EVEX_0FE5,
1379   PREFIX_EVEX_0FE6,
1380   PREFIX_EVEX_0FE7,
1381   PREFIX_EVEX_0FE8,
1382   PREFIX_EVEX_0FE9,
1383   PREFIX_EVEX_0FEA,
1384   PREFIX_EVEX_0FEB,
1385   PREFIX_EVEX_0FEC,
1386   PREFIX_EVEX_0FED,
1387   PREFIX_EVEX_0FEE,
1388   PREFIX_EVEX_0FEF,
1389   PREFIX_EVEX_0FF1,
1390   PREFIX_EVEX_0FF2,
1391   PREFIX_EVEX_0FF3,
1392   PREFIX_EVEX_0FF4,
1393   PREFIX_EVEX_0FF5,
1394   PREFIX_EVEX_0FF6,
1395   PREFIX_EVEX_0FF8,
1396   PREFIX_EVEX_0FF9,
1397   PREFIX_EVEX_0FFA,
1398   PREFIX_EVEX_0FFB,
1399   PREFIX_EVEX_0FFC,
1400   PREFIX_EVEX_0FFD,
1401   PREFIX_EVEX_0FFE,
1402   PREFIX_EVEX_0F3800,
1403   PREFIX_EVEX_0F3804,
1404   PREFIX_EVEX_0F380B,
1405   PREFIX_EVEX_0F380C,
1406   PREFIX_EVEX_0F380D,
1407   PREFIX_EVEX_0F3810,
1408   PREFIX_EVEX_0F3811,
1409   PREFIX_EVEX_0F3812,
1410   PREFIX_EVEX_0F3813,
1411   PREFIX_EVEX_0F3814,
1412   PREFIX_EVEX_0F3815,
1413   PREFIX_EVEX_0F3816,
1414   PREFIX_EVEX_0F3818,
1415   PREFIX_EVEX_0F3819,
1416   PREFIX_EVEX_0F381A,
1417   PREFIX_EVEX_0F381B,
1418   PREFIX_EVEX_0F381C,
1419   PREFIX_EVEX_0F381D,
1420   PREFIX_EVEX_0F381E,
1421   PREFIX_EVEX_0F381F,
1422   PREFIX_EVEX_0F3820,
1423   PREFIX_EVEX_0F3821,
1424   PREFIX_EVEX_0F3822,
1425   PREFIX_EVEX_0F3823,
1426   PREFIX_EVEX_0F3824,
1427   PREFIX_EVEX_0F3825,
1428   PREFIX_EVEX_0F3826,
1429   PREFIX_EVEX_0F3827,
1430   PREFIX_EVEX_0F3828,
1431   PREFIX_EVEX_0F3829,
1432   PREFIX_EVEX_0F382A,
1433   PREFIX_EVEX_0F382B,
1434   PREFIX_EVEX_0F382C,
1435   PREFIX_EVEX_0F382D,
1436   PREFIX_EVEX_0F3830,
1437   PREFIX_EVEX_0F3831,
1438   PREFIX_EVEX_0F3832,
1439   PREFIX_EVEX_0F3833,
1440   PREFIX_EVEX_0F3834,
1441   PREFIX_EVEX_0F3835,
1442   PREFIX_EVEX_0F3836,
1443   PREFIX_EVEX_0F3837,
1444   PREFIX_EVEX_0F3838,
1445   PREFIX_EVEX_0F3839,
1446   PREFIX_EVEX_0F383A,
1447   PREFIX_EVEX_0F383B,
1448   PREFIX_EVEX_0F383C,
1449   PREFIX_EVEX_0F383D,
1450   PREFIX_EVEX_0F383E,
1451   PREFIX_EVEX_0F383F,
1452   PREFIX_EVEX_0F3840,
1453   PREFIX_EVEX_0F3842,
1454   PREFIX_EVEX_0F3843,
1455   PREFIX_EVEX_0F3844,
1456   PREFIX_EVEX_0F3845,
1457   PREFIX_EVEX_0F3846,
1458   PREFIX_EVEX_0F3847,
1459   PREFIX_EVEX_0F384C,
1460   PREFIX_EVEX_0F384D,
1461   PREFIX_EVEX_0F384E,
1462   PREFIX_EVEX_0F384F,
1463   PREFIX_EVEX_0F3858,
1464   PREFIX_EVEX_0F3859,
1465   PREFIX_EVEX_0F385A,
1466   PREFIX_EVEX_0F385B,
1467   PREFIX_EVEX_0F3864,
1468   PREFIX_EVEX_0F3865,
1469   PREFIX_EVEX_0F3866,
1470   PREFIX_EVEX_0F3875,
1471   PREFIX_EVEX_0F3876,
1472   PREFIX_EVEX_0F3877,
1473   PREFIX_EVEX_0F3878,
1474   PREFIX_EVEX_0F3879,
1475   PREFIX_EVEX_0F387A,
1476   PREFIX_EVEX_0F387B,
1477   PREFIX_EVEX_0F387C,
1478   PREFIX_EVEX_0F387D,
1479   PREFIX_EVEX_0F387E,
1480   PREFIX_EVEX_0F387F,
1481   PREFIX_EVEX_0F3888,
1482   PREFIX_EVEX_0F3889,
1483   PREFIX_EVEX_0F388A,
1484   PREFIX_EVEX_0F388B,
1485   PREFIX_EVEX_0F388D,
1486   PREFIX_EVEX_0F3890,
1487   PREFIX_EVEX_0F3891,
1488   PREFIX_EVEX_0F3892,
1489   PREFIX_EVEX_0F3893,
1490   PREFIX_EVEX_0F3896,
1491   PREFIX_EVEX_0F3897,
1492   PREFIX_EVEX_0F3898,
1493   PREFIX_EVEX_0F3899,
1494   PREFIX_EVEX_0F389A,
1495   PREFIX_EVEX_0F389B,
1496   PREFIX_EVEX_0F389C,
1497   PREFIX_EVEX_0F389D,
1498   PREFIX_EVEX_0F389E,
1499   PREFIX_EVEX_0F389F,
1500   PREFIX_EVEX_0F38A0,
1501   PREFIX_EVEX_0F38A1,
1502   PREFIX_EVEX_0F38A2,
1503   PREFIX_EVEX_0F38A3,
1504   PREFIX_EVEX_0F38A6,
1505   PREFIX_EVEX_0F38A7,
1506   PREFIX_EVEX_0F38A8,
1507   PREFIX_EVEX_0F38A9,
1508   PREFIX_EVEX_0F38AA,
1509   PREFIX_EVEX_0F38AB,
1510   PREFIX_EVEX_0F38AC,
1511   PREFIX_EVEX_0F38AD,
1512   PREFIX_EVEX_0F38AE,
1513   PREFIX_EVEX_0F38AF,
1514   PREFIX_EVEX_0F38B6,
1515   PREFIX_EVEX_0F38B7,
1516   PREFIX_EVEX_0F38B8,
1517   PREFIX_EVEX_0F38B9,
1518   PREFIX_EVEX_0F38BA,
1519   PREFIX_EVEX_0F38BB,
1520   PREFIX_EVEX_0F38BC,
1521   PREFIX_EVEX_0F38BD,
1522   PREFIX_EVEX_0F38BE,
1523   PREFIX_EVEX_0F38BF,
1524   PREFIX_EVEX_0F38C4,
1525   PREFIX_EVEX_0F38C6_REG_1,
1526   PREFIX_EVEX_0F38C6_REG_2,
1527   PREFIX_EVEX_0F38C6_REG_5,
1528   PREFIX_EVEX_0F38C6_REG_6,
1529   PREFIX_EVEX_0F38C7_REG_1,
1530   PREFIX_EVEX_0F38C7_REG_2,
1531   PREFIX_EVEX_0F38C7_REG_5,
1532   PREFIX_EVEX_0F38C7_REG_6,
1533   PREFIX_EVEX_0F38C8,
1534   PREFIX_EVEX_0F38CA,
1535   PREFIX_EVEX_0F38CB,
1536   PREFIX_EVEX_0F38CC,
1537   PREFIX_EVEX_0F38CD,
1538
1539   PREFIX_EVEX_0F3A00,
1540   PREFIX_EVEX_0F3A01,
1541   PREFIX_EVEX_0F3A03,
1542   PREFIX_EVEX_0F3A04,
1543   PREFIX_EVEX_0F3A05,
1544   PREFIX_EVEX_0F3A08,
1545   PREFIX_EVEX_0F3A09,
1546   PREFIX_EVEX_0F3A0A,
1547   PREFIX_EVEX_0F3A0B,
1548   PREFIX_EVEX_0F3A0F,
1549   PREFIX_EVEX_0F3A14,
1550   PREFIX_EVEX_0F3A15,
1551   PREFIX_EVEX_0F3A16,
1552   PREFIX_EVEX_0F3A17,
1553   PREFIX_EVEX_0F3A18,
1554   PREFIX_EVEX_0F3A19,
1555   PREFIX_EVEX_0F3A1A,
1556   PREFIX_EVEX_0F3A1B,
1557   PREFIX_EVEX_0F3A1D,
1558   PREFIX_EVEX_0F3A1E,
1559   PREFIX_EVEX_0F3A1F,
1560   PREFIX_EVEX_0F3A20,
1561   PREFIX_EVEX_0F3A21,
1562   PREFIX_EVEX_0F3A22,
1563   PREFIX_EVEX_0F3A23,
1564   PREFIX_EVEX_0F3A25,
1565   PREFIX_EVEX_0F3A26,
1566   PREFIX_EVEX_0F3A27,
1567   PREFIX_EVEX_0F3A38,
1568   PREFIX_EVEX_0F3A39,
1569   PREFIX_EVEX_0F3A3A,
1570   PREFIX_EVEX_0F3A3B,
1571   PREFIX_EVEX_0F3A3E,
1572   PREFIX_EVEX_0F3A3F,
1573   PREFIX_EVEX_0F3A42,
1574   PREFIX_EVEX_0F3A43,
1575   PREFIX_EVEX_0F3A50,
1576   PREFIX_EVEX_0F3A51,
1577   PREFIX_EVEX_0F3A54,
1578   PREFIX_EVEX_0F3A55,
1579   PREFIX_EVEX_0F3A56,
1580   PREFIX_EVEX_0F3A57,
1581   PREFIX_EVEX_0F3A66,
1582   PREFIX_EVEX_0F3A67
1583 };
1584
1585 enum
1586 {
1587   X86_64_06 = 0,
1588   X86_64_07,
1589   X86_64_0D,
1590   X86_64_16,
1591   X86_64_17,
1592   X86_64_1E,
1593   X86_64_1F,
1594   X86_64_27,
1595   X86_64_2F,
1596   X86_64_37,
1597   X86_64_3F,
1598   X86_64_60,
1599   X86_64_61,
1600   X86_64_62,
1601   X86_64_63,
1602   X86_64_6D,
1603   X86_64_6F,
1604   X86_64_9A,
1605   X86_64_C4,
1606   X86_64_C5,
1607   X86_64_CE,
1608   X86_64_D4,
1609   X86_64_D5,
1610   X86_64_EA,
1611   X86_64_0F01_REG_0,
1612   X86_64_0F01_REG_1,
1613   X86_64_0F01_REG_2,
1614   X86_64_0F01_REG_3
1615 };
1616
1617 enum
1618 {
1619   THREE_BYTE_0F38 = 0,
1620   THREE_BYTE_0F3A,
1621   THREE_BYTE_0F7A
1622 };
1623
1624 enum
1625 {
1626   XOP_08 = 0,
1627   XOP_09,
1628   XOP_0A
1629 };
1630
1631 enum
1632 {
1633   VEX_0F = 0,
1634   VEX_0F38,
1635   VEX_0F3A
1636 };
1637
1638 enum
1639 {
1640   EVEX_0F = 0,
1641   EVEX_0F38,
1642   EVEX_0F3A
1643 };
1644
1645 enum
1646 {
1647   VEX_LEN_0F10_P_1 = 0,
1648   VEX_LEN_0F10_P_3,
1649   VEX_LEN_0F11_P_1,
1650   VEX_LEN_0F11_P_3,
1651   VEX_LEN_0F12_P_0_M_0,
1652   VEX_LEN_0F12_P_0_M_1,
1653   VEX_LEN_0F12_P_2,
1654   VEX_LEN_0F13_M_0,
1655   VEX_LEN_0F16_P_0_M_0,
1656   VEX_LEN_0F16_P_0_M_1,
1657   VEX_LEN_0F16_P_2,
1658   VEX_LEN_0F17_M_0,
1659   VEX_LEN_0F2A_P_1,
1660   VEX_LEN_0F2A_P_3,
1661   VEX_LEN_0F2C_P_1,
1662   VEX_LEN_0F2C_P_3,
1663   VEX_LEN_0F2D_P_1,
1664   VEX_LEN_0F2D_P_3,
1665   VEX_LEN_0F2E_P_0,
1666   VEX_LEN_0F2E_P_2,
1667   VEX_LEN_0F2F_P_0,
1668   VEX_LEN_0F2F_P_2,
1669   VEX_LEN_0F41_P_0,
1670   VEX_LEN_0F41_P_2,
1671   VEX_LEN_0F42_P_0,
1672   VEX_LEN_0F42_P_2,
1673   VEX_LEN_0F44_P_0,
1674   VEX_LEN_0F44_P_2,
1675   VEX_LEN_0F45_P_0,
1676   VEX_LEN_0F45_P_2,
1677   VEX_LEN_0F46_P_0,
1678   VEX_LEN_0F46_P_2,
1679   VEX_LEN_0F47_P_0,
1680   VEX_LEN_0F47_P_2,
1681   VEX_LEN_0F4A_P_0,
1682   VEX_LEN_0F4A_P_2,
1683   VEX_LEN_0F4B_P_0,
1684   VEX_LEN_0F4B_P_2,
1685   VEX_LEN_0F51_P_1,
1686   VEX_LEN_0F51_P_3,
1687   VEX_LEN_0F52_P_1,
1688   VEX_LEN_0F53_P_1,
1689   VEX_LEN_0F58_P_1,
1690   VEX_LEN_0F58_P_3,
1691   VEX_LEN_0F59_P_1,
1692   VEX_LEN_0F59_P_3,
1693   VEX_LEN_0F5A_P_1,
1694   VEX_LEN_0F5A_P_3,
1695   VEX_LEN_0F5C_P_1,
1696   VEX_LEN_0F5C_P_3,
1697   VEX_LEN_0F5D_P_1,
1698   VEX_LEN_0F5D_P_3,
1699   VEX_LEN_0F5E_P_1,
1700   VEX_LEN_0F5E_P_3,
1701   VEX_LEN_0F5F_P_1,
1702   VEX_LEN_0F5F_P_3,
1703   VEX_LEN_0F6E_P_2,
1704   VEX_LEN_0F7E_P_1,
1705   VEX_LEN_0F7E_P_2,
1706   VEX_LEN_0F90_P_0,
1707   VEX_LEN_0F90_P_2,
1708   VEX_LEN_0F91_P_0,
1709   VEX_LEN_0F91_P_2,
1710   VEX_LEN_0F92_P_0,
1711   VEX_LEN_0F92_P_2,
1712   VEX_LEN_0F92_P_3,
1713   VEX_LEN_0F93_P_0,
1714   VEX_LEN_0F93_P_2,
1715   VEX_LEN_0F93_P_3,
1716   VEX_LEN_0F98_P_0,
1717   VEX_LEN_0F98_P_2,
1718   VEX_LEN_0F99_P_0,
1719   VEX_LEN_0F99_P_2,
1720   VEX_LEN_0FAE_R_2_M_0,
1721   VEX_LEN_0FAE_R_3_M_0,
1722   VEX_LEN_0FC2_P_1,
1723   VEX_LEN_0FC2_P_3,
1724   VEX_LEN_0FC4_P_2,
1725   VEX_LEN_0FC5_P_2,
1726   VEX_LEN_0FD6_P_2,
1727   VEX_LEN_0FF7_P_2,
1728   VEX_LEN_0F3816_P_2,
1729   VEX_LEN_0F3819_P_2,
1730   VEX_LEN_0F381A_P_2_M_0,
1731   VEX_LEN_0F3836_P_2,
1732   VEX_LEN_0F3841_P_2,
1733   VEX_LEN_0F385A_P_2_M_0,
1734   VEX_LEN_0F38DB_P_2,
1735   VEX_LEN_0F38DC_P_2,
1736   VEX_LEN_0F38DD_P_2,
1737   VEX_LEN_0F38DE_P_2,
1738   VEX_LEN_0F38DF_P_2,
1739   VEX_LEN_0F38F2_P_0,
1740   VEX_LEN_0F38F3_R_1_P_0,
1741   VEX_LEN_0F38F3_R_2_P_0,
1742   VEX_LEN_0F38F3_R_3_P_0,
1743   VEX_LEN_0F38F5_P_0,
1744   VEX_LEN_0F38F5_P_1,
1745   VEX_LEN_0F38F5_P_3,
1746   VEX_LEN_0F38F6_P_3,
1747   VEX_LEN_0F38F7_P_0,
1748   VEX_LEN_0F38F7_P_1,
1749   VEX_LEN_0F38F7_P_2,
1750   VEX_LEN_0F38F7_P_3,
1751   VEX_LEN_0F3A00_P_2,
1752   VEX_LEN_0F3A01_P_2,
1753   VEX_LEN_0F3A06_P_2,
1754   VEX_LEN_0F3A0A_P_2,
1755   VEX_LEN_0F3A0B_P_2,
1756   VEX_LEN_0F3A14_P_2,
1757   VEX_LEN_0F3A15_P_2,
1758   VEX_LEN_0F3A16_P_2,
1759   VEX_LEN_0F3A17_P_2,
1760   VEX_LEN_0F3A18_P_2,
1761   VEX_LEN_0F3A19_P_2,
1762   VEX_LEN_0F3A20_P_2,
1763   VEX_LEN_0F3A21_P_2,
1764   VEX_LEN_0F3A22_P_2,
1765   VEX_LEN_0F3A30_P_2,
1766   VEX_LEN_0F3A31_P_2,
1767   VEX_LEN_0F3A32_P_2,
1768   VEX_LEN_0F3A33_P_2,
1769   VEX_LEN_0F3A38_P_2,
1770   VEX_LEN_0F3A39_P_2,
1771   VEX_LEN_0F3A41_P_2,
1772   VEX_LEN_0F3A44_P_2,
1773   VEX_LEN_0F3A46_P_2,
1774   VEX_LEN_0F3A60_P_2,
1775   VEX_LEN_0F3A61_P_2,
1776   VEX_LEN_0F3A62_P_2,
1777   VEX_LEN_0F3A63_P_2,
1778   VEX_LEN_0F3A6A_P_2,
1779   VEX_LEN_0F3A6B_P_2,
1780   VEX_LEN_0F3A6E_P_2,
1781   VEX_LEN_0F3A6F_P_2,
1782   VEX_LEN_0F3A7A_P_2,
1783   VEX_LEN_0F3A7B_P_2,
1784   VEX_LEN_0F3A7E_P_2,
1785   VEX_LEN_0F3A7F_P_2,
1786   VEX_LEN_0F3ADF_P_2,
1787   VEX_LEN_0F3AF0_P_3,
1788   VEX_LEN_0FXOP_08_CC,
1789   VEX_LEN_0FXOP_08_CD,
1790   VEX_LEN_0FXOP_08_CE,
1791   VEX_LEN_0FXOP_08_CF,
1792   VEX_LEN_0FXOP_08_EC,
1793   VEX_LEN_0FXOP_08_ED,
1794   VEX_LEN_0FXOP_08_EE,
1795   VEX_LEN_0FXOP_08_EF,
1796   VEX_LEN_0FXOP_09_80,
1797   VEX_LEN_0FXOP_09_81
1798 };
1799
1800 enum
1801 {
1802   VEX_W_0F10_P_0 = 0,
1803   VEX_W_0F10_P_1,
1804   VEX_W_0F10_P_2,
1805   VEX_W_0F10_P_3,
1806   VEX_W_0F11_P_0,
1807   VEX_W_0F11_P_1,
1808   VEX_W_0F11_P_2,
1809   VEX_W_0F11_P_3,
1810   VEX_W_0F12_P_0_M_0,
1811   VEX_W_0F12_P_0_M_1,
1812   VEX_W_0F12_P_1,
1813   VEX_W_0F12_P_2,
1814   VEX_W_0F12_P_3,
1815   VEX_W_0F13_M_0,
1816   VEX_W_0F14,
1817   VEX_W_0F15,
1818   VEX_W_0F16_P_0_M_0,
1819   VEX_W_0F16_P_0_M_1,
1820   VEX_W_0F16_P_1,
1821   VEX_W_0F16_P_2,
1822   VEX_W_0F17_M_0,
1823   VEX_W_0F28,
1824   VEX_W_0F29,
1825   VEX_W_0F2B_M_0,
1826   VEX_W_0F2E_P_0,
1827   VEX_W_0F2E_P_2,
1828   VEX_W_0F2F_P_0,
1829   VEX_W_0F2F_P_2,
1830   VEX_W_0F41_P_0_LEN_1,
1831   VEX_W_0F41_P_2_LEN_1,
1832   VEX_W_0F42_P_0_LEN_1,
1833   VEX_W_0F42_P_2_LEN_1,
1834   VEX_W_0F44_P_0_LEN_0,
1835   VEX_W_0F44_P_2_LEN_0,
1836   VEX_W_0F45_P_0_LEN_1,
1837   VEX_W_0F45_P_2_LEN_1,
1838   VEX_W_0F46_P_0_LEN_1,
1839   VEX_W_0F46_P_2_LEN_1,
1840   VEX_W_0F47_P_0_LEN_1,
1841   VEX_W_0F47_P_2_LEN_1,
1842   VEX_W_0F4A_P_0_LEN_1,
1843   VEX_W_0F4A_P_2_LEN_1,
1844   VEX_W_0F4B_P_0_LEN_1,
1845   VEX_W_0F4B_P_2_LEN_1,
1846   VEX_W_0F50_M_0,
1847   VEX_W_0F51_P_0,
1848   VEX_W_0F51_P_1,
1849   VEX_W_0F51_P_2,
1850   VEX_W_0F51_P_3,
1851   VEX_W_0F52_P_0,
1852   VEX_W_0F52_P_1,
1853   VEX_W_0F53_P_0,
1854   VEX_W_0F53_P_1,
1855   VEX_W_0F58_P_0,
1856   VEX_W_0F58_P_1,
1857   VEX_W_0F58_P_2,
1858   VEX_W_0F58_P_3,
1859   VEX_W_0F59_P_0,
1860   VEX_W_0F59_P_1,
1861   VEX_W_0F59_P_2,
1862   VEX_W_0F59_P_3,
1863   VEX_W_0F5A_P_0,
1864   VEX_W_0F5A_P_1,
1865   VEX_W_0F5A_P_3,
1866   VEX_W_0F5B_P_0,
1867   VEX_W_0F5B_P_1,
1868   VEX_W_0F5B_P_2,
1869   VEX_W_0F5C_P_0,
1870   VEX_W_0F5C_P_1,
1871   VEX_W_0F5C_P_2,
1872   VEX_W_0F5C_P_3,
1873   VEX_W_0F5D_P_0,
1874   VEX_W_0F5D_P_1,
1875   VEX_W_0F5D_P_2,
1876   VEX_W_0F5D_P_3,
1877   VEX_W_0F5E_P_0,
1878   VEX_W_0F5E_P_1,
1879   VEX_W_0F5E_P_2,
1880   VEX_W_0F5E_P_3,
1881   VEX_W_0F5F_P_0,
1882   VEX_W_0F5F_P_1,
1883   VEX_W_0F5F_P_2,
1884   VEX_W_0F5F_P_3,
1885   VEX_W_0F60_P_2,
1886   VEX_W_0F61_P_2,
1887   VEX_W_0F62_P_2,
1888   VEX_W_0F63_P_2,
1889   VEX_W_0F64_P_2,
1890   VEX_W_0F65_P_2,
1891   VEX_W_0F66_P_2,
1892   VEX_W_0F67_P_2,
1893   VEX_W_0F68_P_2,
1894   VEX_W_0F69_P_2,
1895   VEX_W_0F6A_P_2,
1896   VEX_W_0F6B_P_2,
1897   VEX_W_0F6C_P_2,
1898   VEX_W_0F6D_P_2,
1899   VEX_W_0F6F_P_1,
1900   VEX_W_0F6F_P_2,
1901   VEX_W_0F70_P_1,
1902   VEX_W_0F70_P_2,
1903   VEX_W_0F70_P_3,
1904   VEX_W_0F71_R_2_P_2,
1905   VEX_W_0F71_R_4_P_2,
1906   VEX_W_0F71_R_6_P_2,
1907   VEX_W_0F72_R_2_P_2,
1908   VEX_W_0F72_R_4_P_2,
1909   VEX_W_0F72_R_6_P_2,
1910   VEX_W_0F73_R_2_P_2,
1911   VEX_W_0F73_R_3_P_2,
1912   VEX_W_0F73_R_6_P_2,
1913   VEX_W_0F73_R_7_P_2,
1914   VEX_W_0F74_P_2,
1915   VEX_W_0F75_P_2,
1916   VEX_W_0F76_P_2,
1917   VEX_W_0F77_P_0,
1918   VEX_W_0F7C_P_2,
1919   VEX_W_0F7C_P_3,
1920   VEX_W_0F7D_P_2,
1921   VEX_W_0F7D_P_3,
1922   VEX_W_0F7E_P_1,
1923   VEX_W_0F7F_P_1,
1924   VEX_W_0F7F_P_2,
1925   VEX_W_0F90_P_0_LEN_0,
1926   VEX_W_0F90_P_2_LEN_0,
1927   VEX_W_0F91_P_0_LEN_0,
1928   VEX_W_0F91_P_2_LEN_0,
1929   VEX_W_0F92_P_0_LEN_0,
1930   VEX_W_0F92_P_2_LEN_0,
1931   VEX_W_0F92_P_3_LEN_0,
1932   VEX_W_0F93_P_0_LEN_0,
1933   VEX_W_0F93_P_2_LEN_0,
1934   VEX_W_0F93_P_3_LEN_0,
1935   VEX_W_0F98_P_0_LEN_0,
1936   VEX_W_0F98_P_2_LEN_0,
1937   VEX_W_0F99_P_0_LEN_0,
1938   VEX_W_0F99_P_2_LEN_0,
1939   VEX_W_0FAE_R_2_M_0,
1940   VEX_W_0FAE_R_3_M_0,
1941   VEX_W_0FC2_P_0,
1942   VEX_W_0FC2_P_1,
1943   VEX_W_0FC2_P_2,
1944   VEX_W_0FC2_P_3,
1945   VEX_W_0FC4_P_2,
1946   VEX_W_0FC5_P_2,
1947   VEX_W_0FD0_P_2,
1948   VEX_W_0FD0_P_3,
1949   VEX_W_0FD1_P_2,
1950   VEX_W_0FD2_P_2,
1951   VEX_W_0FD3_P_2,
1952   VEX_W_0FD4_P_2,
1953   VEX_W_0FD5_P_2,
1954   VEX_W_0FD6_P_2,
1955   VEX_W_0FD7_P_2_M_1,
1956   VEX_W_0FD8_P_2,
1957   VEX_W_0FD9_P_2,
1958   VEX_W_0FDA_P_2,
1959   VEX_W_0FDB_P_2,
1960   VEX_W_0FDC_P_2,
1961   VEX_W_0FDD_P_2,
1962   VEX_W_0FDE_P_2,
1963   VEX_W_0FDF_P_2,
1964   VEX_W_0FE0_P_2,
1965   VEX_W_0FE1_P_2,
1966   VEX_W_0FE2_P_2,
1967   VEX_W_0FE3_P_2,
1968   VEX_W_0FE4_P_2,
1969   VEX_W_0FE5_P_2,
1970   VEX_W_0FE6_P_1,
1971   VEX_W_0FE6_P_2,
1972   VEX_W_0FE6_P_3,
1973   VEX_W_0FE7_P_2_M_0,
1974   VEX_W_0FE8_P_2,
1975   VEX_W_0FE9_P_2,
1976   VEX_W_0FEA_P_2,
1977   VEX_W_0FEB_P_2,
1978   VEX_W_0FEC_P_2,
1979   VEX_W_0FED_P_2,
1980   VEX_W_0FEE_P_2,
1981   VEX_W_0FEF_P_2,
1982   VEX_W_0FF0_P_3_M_0,
1983   VEX_W_0FF1_P_2,
1984   VEX_W_0FF2_P_2,
1985   VEX_W_0FF3_P_2,
1986   VEX_W_0FF4_P_2,
1987   VEX_W_0FF5_P_2,
1988   VEX_W_0FF6_P_2,
1989   VEX_W_0FF7_P_2,
1990   VEX_W_0FF8_P_2,
1991   VEX_W_0FF9_P_2,
1992   VEX_W_0FFA_P_2,
1993   VEX_W_0FFB_P_2,
1994   VEX_W_0FFC_P_2,
1995   VEX_W_0FFD_P_2,
1996   VEX_W_0FFE_P_2,
1997   VEX_W_0F3800_P_2,
1998   VEX_W_0F3801_P_2,
1999   VEX_W_0F3802_P_2,
2000   VEX_W_0F3803_P_2,
2001   VEX_W_0F3804_P_2,
2002   VEX_W_0F3805_P_2,
2003   VEX_W_0F3806_P_2,
2004   VEX_W_0F3807_P_2,
2005   VEX_W_0F3808_P_2,
2006   VEX_W_0F3809_P_2,
2007   VEX_W_0F380A_P_2,
2008   VEX_W_0F380B_P_2,
2009   VEX_W_0F380C_P_2,
2010   VEX_W_0F380D_P_2,
2011   VEX_W_0F380E_P_2,
2012   VEX_W_0F380F_P_2,
2013   VEX_W_0F3816_P_2,
2014   VEX_W_0F3817_P_2,
2015   VEX_W_0F3818_P_2,
2016   VEX_W_0F3819_P_2,
2017   VEX_W_0F381A_P_2_M_0,
2018   VEX_W_0F381C_P_2,
2019   VEX_W_0F381D_P_2,
2020   VEX_W_0F381E_P_2,
2021   VEX_W_0F3820_P_2,
2022   VEX_W_0F3821_P_2,
2023   VEX_W_0F3822_P_2,
2024   VEX_W_0F3823_P_2,
2025   VEX_W_0F3824_P_2,
2026   VEX_W_0F3825_P_2,
2027   VEX_W_0F3828_P_2,
2028   VEX_W_0F3829_P_2,
2029   VEX_W_0F382A_P_2_M_0,
2030   VEX_W_0F382B_P_2,
2031   VEX_W_0F382C_P_2_M_0,
2032   VEX_W_0F382D_P_2_M_0,
2033   VEX_W_0F382E_P_2_M_0,
2034   VEX_W_0F382F_P_2_M_0,
2035   VEX_W_0F3830_P_2,
2036   VEX_W_0F3831_P_2,
2037   VEX_W_0F3832_P_2,
2038   VEX_W_0F3833_P_2,
2039   VEX_W_0F3834_P_2,
2040   VEX_W_0F3835_P_2,
2041   VEX_W_0F3836_P_2,
2042   VEX_W_0F3837_P_2,
2043   VEX_W_0F3838_P_2,
2044   VEX_W_0F3839_P_2,
2045   VEX_W_0F383A_P_2,
2046   VEX_W_0F383B_P_2,
2047   VEX_W_0F383C_P_2,
2048   VEX_W_0F383D_P_2,
2049   VEX_W_0F383E_P_2,
2050   VEX_W_0F383F_P_2,
2051   VEX_W_0F3840_P_2,
2052   VEX_W_0F3841_P_2,
2053   VEX_W_0F3846_P_2,
2054   VEX_W_0F3858_P_2,
2055   VEX_W_0F3859_P_2,
2056   VEX_W_0F385A_P_2_M_0,
2057   VEX_W_0F3878_P_2,
2058   VEX_W_0F3879_P_2,
2059   VEX_W_0F38DB_P_2,
2060   VEX_W_0F38DC_P_2,
2061   VEX_W_0F38DD_P_2,
2062   VEX_W_0F38DE_P_2,
2063   VEX_W_0F38DF_P_2,
2064   VEX_W_0F3A00_P_2,
2065   VEX_W_0F3A01_P_2,
2066   VEX_W_0F3A02_P_2,
2067   VEX_W_0F3A04_P_2,
2068   VEX_W_0F3A05_P_2,
2069   VEX_W_0F3A06_P_2,
2070   VEX_W_0F3A08_P_2,
2071   VEX_W_0F3A09_P_2,
2072   VEX_W_0F3A0A_P_2,
2073   VEX_W_0F3A0B_P_2,
2074   VEX_W_0F3A0C_P_2,
2075   VEX_W_0F3A0D_P_2,
2076   VEX_W_0F3A0E_P_2,
2077   VEX_W_0F3A0F_P_2,
2078   VEX_W_0F3A14_P_2,
2079   VEX_W_0F3A15_P_2,
2080   VEX_W_0F3A18_P_2,
2081   VEX_W_0F3A19_P_2,
2082   VEX_W_0F3A20_P_2,
2083   VEX_W_0F3A21_P_2,
2084   VEX_W_0F3A30_P_2_LEN_0,
2085   VEX_W_0F3A31_P_2_LEN_0,
2086   VEX_W_0F3A32_P_2_LEN_0,
2087   VEX_W_0F3A33_P_2_LEN_0,
2088   VEX_W_0F3A38_P_2,
2089   VEX_W_0F3A39_P_2,
2090   VEX_W_0F3A40_P_2,
2091   VEX_W_0F3A41_P_2,
2092   VEX_W_0F3A42_P_2,
2093   VEX_W_0F3A44_P_2,
2094   VEX_W_0F3A46_P_2,
2095   VEX_W_0F3A48_P_2,
2096   VEX_W_0F3A49_P_2,
2097   VEX_W_0F3A4A_P_2,
2098   VEX_W_0F3A4B_P_2,
2099   VEX_W_0F3A4C_P_2,
2100   VEX_W_0F3A60_P_2,
2101   VEX_W_0F3A61_P_2,
2102   VEX_W_0F3A62_P_2,
2103   VEX_W_0F3A63_P_2,
2104   VEX_W_0F3ADF_P_2,
2105
2106   EVEX_W_0F10_P_0,
2107   EVEX_W_0F10_P_1_M_0,
2108   EVEX_W_0F10_P_1_M_1,
2109   EVEX_W_0F10_P_2,
2110   EVEX_W_0F10_P_3_M_0,
2111   EVEX_W_0F10_P_3_M_1,
2112   EVEX_W_0F11_P_0,
2113   EVEX_W_0F11_P_1_M_0,
2114   EVEX_W_0F11_P_1_M_1,
2115   EVEX_W_0F11_P_2,
2116   EVEX_W_0F11_P_3_M_0,
2117   EVEX_W_0F11_P_3_M_1,
2118   EVEX_W_0F12_P_0_M_0,
2119   EVEX_W_0F12_P_0_M_1,
2120   EVEX_W_0F12_P_1,
2121   EVEX_W_0F12_P_2,
2122   EVEX_W_0F12_P_3,
2123   EVEX_W_0F13_P_0,
2124   EVEX_W_0F13_P_2,
2125   EVEX_W_0F14_P_0,
2126   EVEX_W_0F14_P_2,
2127   EVEX_W_0F15_P_0,
2128   EVEX_W_0F15_P_2,
2129   EVEX_W_0F16_P_0_M_0,
2130   EVEX_W_0F16_P_0_M_1,
2131   EVEX_W_0F16_P_1,
2132   EVEX_W_0F16_P_2,
2133   EVEX_W_0F17_P_0,
2134   EVEX_W_0F17_P_2,
2135   EVEX_W_0F28_P_0,
2136   EVEX_W_0F28_P_2,
2137   EVEX_W_0F29_P_0,
2138   EVEX_W_0F29_P_2,
2139   EVEX_W_0F2A_P_1,
2140   EVEX_W_0F2A_P_3,
2141   EVEX_W_0F2B_P_0,
2142   EVEX_W_0F2B_P_2,
2143   EVEX_W_0F2E_P_0,
2144   EVEX_W_0F2E_P_2,
2145   EVEX_W_0F2F_P_0,
2146   EVEX_W_0F2F_P_2,
2147   EVEX_W_0F51_P_0,
2148   EVEX_W_0F51_P_1,
2149   EVEX_W_0F51_P_2,
2150   EVEX_W_0F51_P_3,
2151   EVEX_W_0F54_P_0,
2152   EVEX_W_0F54_P_2,
2153   EVEX_W_0F55_P_0,
2154   EVEX_W_0F55_P_2,
2155   EVEX_W_0F56_P_0,
2156   EVEX_W_0F56_P_2,
2157   EVEX_W_0F57_P_0,
2158   EVEX_W_0F57_P_2,
2159   EVEX_W_0F58_P_0,
2160   EVEX_W_0F58_P_1,
2161   EVEX_W_0F58_P_2,
2162   EVEX_W_0F58_P_3,
2163   EVEX_W_0F59_P_0,
2164   EVEX_W_0F59_P_1,
2165   EVEX_W_0F59_P_2,
2166   EVEX_W_0F59_P_3,
2167   EVEX_W_0F5A_P_0,
2168   EVEX_W_0F5A_P_1,
2169   EVEX_W_0F5A_P_2,
2170   EVEX_W_0F5A_P_3,
2171   EVEX_W_0F5B_P_0,
2172   EVEX_W_0F5B_P_1,
2173   EVEX_W_0F5B_P_2,
2174   EVEX_W_0F5C_P_0,
2175   EVEX_W_0F5C_P_1,
2176   EVEX_W_0F5C_P_2,
2177   EVEX_W_0F5C_P_3,
2178   EVEX_W_0F5D_P_0,
2179   EVEX_W_0F5D_P_1,
2180   EVEX_W_0F5D_P_2,
2181   EVEX_W_0F5D_P_3,
2182   EVEX_W_0F5E_P_0,
2183   EVEX_W_0F5E_P_1,
2184   EVEX_W_0F5E_P_2,
2185   EVEX_W_0F5E_P_3,
2186   EVEX_W_0F5F_P_0,
2187   EVEX_W_0F5F_P_1,
2188   EVEX_W_0F5F_P_2,
2189   EVEX_W_0F5F_P_3,
2190   EVEX_W_0F62_P_2,
2191   EVEX_W_0F66_P_2,
2192   EVEX_W_0F6A_P_2,
2193   EVEX_W_0F6B_P_2,
2194   EVEX_W_0F6C_P_2,
2195   EVEX_W_0F6D_P_2,
2196   EVEX_W_0F6E_P_2,
2197   EVEX_W_0F6F_P_1,
2198   EVEX_W_0F6F_P_2,
2199   EVEX_W_0F6F_P_3,
2200   EVEX_W_0F70_P_2,
2201   EVEX_W_0F72_R_2_P_2,
2202   EVEX_W_0F72_R_6_P_2,
2203   EVEX_W_0F73_R_2_P_2,
2204   EVEX_W_0F73_R_6_P_2,
2205   EVEX_W_0F76_P_2,
2206   EVEX_W_0F78_P_0,
2207   EVEX_W_0F78_P_2,
2208   EVEX_W_0F79_P_0,
2209   EVEX_W_0F79_P_2,
2210   EVEX_W_0F7A_P_1,
2211   EVEX_W_0F7A_P_2,
2212   EVEX_W_0F7A_P_3,
2213   EVEX_W_0F7B_P_1,
2214   EVEX_W_0F7B_P_2,
2215   EVEX_W_0F7B_P_3,
2216   EVEX_W_0F7E_P_1,
2217   EVEX_W_0F7E_P_2,
2218   EVEX_W_0F7F_P_1,
2219   EVEX_W_0F7F_P_2,
2220   EVEX_W_0F7F_P_3,
2221   EVEX_W_0FC2_P_0,
2222   EVEX_W_0FC2_P_1,
2223   EVEX_W_0FC2_P_2,
2224   EVEX_W_0FC2_P_3,
2225   EVEX_W_0FC6_P_0,
2226   EVEX_W_0FC6_P_2,
2227   EVEX_W_0FD2_P_2,
2228   EVEX_W_0FD3_P_2,
2229   EVEX_W_0FD4_P_2,
2230   EVEX_W_0FD6_P_2,
2231   EVEX_W_0FE6_P_1,
2232   EVEX_W_0FE6_P_2,
2233   EVEX_W_0FE6_P_3,
2234   EVEX_W_0FE7_P_2,
2235   EVEX_W_0FF2_P_2,
2236   EVEX_W_0FF3_P_2,
2237   EVEX_W_0FF4_P_2,
2238   EVEX_W_0FFA_P_2,
2239   EVEX_W_0FFB_P_2,
2240   EVEX_W_0FFE_P_2,
2241   EVEX_W_0F380C_P_2,
2242   EVEX_W_0F380D_P_2,
2243   EVEX_W_0F3810_P_1,
2244   EVEX_W_0F3810_P_2,
2245   EVEX_W_0F3811_P_1,
2246   EVEX_W_0F3811_P_2,
2247   EVEX_W_0F3812_P_1,
2248   EVEX_W_0F3812_P_2,
2249   EVEX_W_0F3813_P_1,
2250   EVEX_W_0F3813_P_2,
2251   EVEX_W_0F3814_P_1,
2252   EVEX_W_0F3815_P_1,
2253   EVEX_W_0F3818_P_2,
2254   EVEX_W_0F3819_P_2,
2255   EVEX_W_0F381A_P_2,
2256   EVEX_W_0F381B_P_2,
2257   EVEX_W_0F381E_P_2,
2258   EVEX_W_0F381F_P_2,
2259   EVEX_W_0F3820_P_1,
2260   EVEX_W_0F3821_P_1,
2261   EVEX_W_0F3822_P_1,
2262   EVEX_W_0F3823_P_1,
2263   EVEX_W_0F3824_P_1,
2264   EVEX_W_0F3825_P_1,
2265   EVEX_W_0F3825_P_2,
2266   EVEX_W_0F3826_P_1,
2267   EVEX_W_0F3826_P_2,
2268   EVEX_W_0F3828_P_1,
2269   EVEX_W_0F3828_P_2,
2270   EVEX_W_0F3829_P_1,
2271   EVEX_W_0F3829_P_2,
2272   EVEX_W_0F382A_P_1,
2273   EVEX_W_0F382A_P_2,
2274   EVEX_W_0F382B_P_2,
2275   EVEX_W_0F3830_P_1,
2276   EVEX_W_0F3831_P_1,
2277   EVEX_W_0F3832_P_1,
2278   EVEX_W_0F3833_P_1,
2279   EVEX_W_0F3834_P_1,
2280   EVEX_W_0F3835_P_1,
2281   EVEX_W_0F3835_P_2,
2282   EVEX_W_0F3837_P_2,
2283   EVEX_W_0F3838_P_1,
2284   EVEX_W_0F3839_P_1,
2285   EVEX_W_0F383A_P_1,
2286   EVEX_W_0F3840_P_2,
2287   EVEX_W_0F3858_P_2,
2288   EVEX_W_0F3859_P_2,
2289   EVEX_W_0F385A_P_2,
2290   EVEX_W_0F385B_P_2,
2291   EVEX_W_0F3866_P_2,
2292   EVEX_W_0F3875_P_2,
2293   EVEX_W_0F3878_P_2,
2294   EVEX_W_0F3879_P_2,
2295   EVEX_W_0F387A_P_2,
2296   EVEX_W_0F387B_P_2,
2297   EVEX_W_0F387D_P_2,
2298   EVEX_W_0F388D_P_2,
2299   EVEX_W_0F3891_P_2,
2300   EVEX_W_0F3893_P_2,
2301   EVEX_W_0F38A1_P_2,
2302   EVEX_W_0F38A3_P_2,
2303   EVEX_W_0F38C7_R_1_P_2,
2304   EVEX_W_0F38C7_R_2_P_2,
2305   EVEX_W_0F38C7_R_5_P_2,
2306   EVEX_W_0F38C7_R_6_P_2,
2307
2308   EVEX_W_0F3A00_P_2,
2309   EVEX_W_0F3A01_P_2,
2310   EVEX_W_0F3A04_P_2,
2311   EVEX_W_0F3A05_P_2,
2312   EVEX_W_0F3A08_P_2,
2313   EVEX_W_0F3A09_P_2,
2314   EVEX_W_0F3A0A_P_2,
2315   EVEX_W_0F3A0B_P_2,
2316   EVEX_W_0F3A16_P_2,
2317   EVEX_W_0F3A18_P_2,
2318   EVEX_W_0F3A19_P_2,
2319   EVEX_W_0F3A1A_P_2,
2320   EVEX_W_0F3A1B_P_2,
2321   EVEX_W_0F3A1D_P_2,
2322   EVEX_W_0F3A21_P_2,
2323   EVEX_W_0F3A22_P_2,
2324   EVEX_W_0F3A23_P_2,
2325   EVEX_W_0F3A38_P_2,
2326   EVEX_W_0F3A39_P_2,
2327   EVEX_W_0F3A3A_P_2,
2328   EVEX_W_0F3A3B_P_2,
2329   EVEX_W_0F3A3E_P_2,
2330   EVEX_W_0F3A3F_P_2,
2331   EVEX_W_0F3A42_P_2,
2332   EVEX_W_0F3A43_P_2,
2333   EVEX_W_0F3A50_P_2,
2334   EVEX_W_0F3A51_P_2,
2335   EVEX_W_0F3A56_P_2,
2336   EVEX_W_0F3A57_P_2,
2337   EVEX_W_0F3A66_P_2,
2338   EVEX_W_0F3A67_P_2
2339 };
2340
2341 typedef void (*op_rtn) (int bytemode, int sizeflag);
2342
2343 struct dis386 {
2344   const char *name;
2345   struct
2346     {
2347       op_rtn rtn;
2348       int bytemode;
2349     } op[MAX_OPERANDS];
2350 };
2351
2352 /* Upper case letters in the instruction names here are macros.
2353    'A' => print 'b' if no register operands or suffix_always is true
2354    'B' => print 'b' if suffix_always is true
2355    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2356           size prefix
2357    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2358           suffix_always is true
2359    'E' => print 'e' if 32-bit form of jcxz
2360    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2361    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2362    'H' => print ",pt" or ",pn" branch hint
2363    'I' => honor following macro letter even in Intel mode (implemented only
2364           for some of the macro letters)
2365    'J' => print 'l'
2366    'K' => print 'd' or 'q' if rex prefix is present.
2367    'L' => print 'l' if suffix_always is true
2368    'M' => print 'r' if intel_mnemonic is false.
2369    'N' => print 'n' if instruction has no wait "prefix"
2370    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2371    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2372           or suffix_always is true.  print 'q' if rex prefix is present.
2373    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2374           is true
2375    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2376    'S' => print 'w', 'l' or 'q' if suffix_always is true
2377    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2378    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2379    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2380    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2381    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2382    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2383           suffix_always is true.
2384    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2385    '!' => change condition from true to false or from false to true.
2386    '%' => add 1 upper case letter to the macro.
2387
2388    2 upper case letter macros:
2389    "XY" => print 'x' or 'y' if no register operands or suffix_always
2390            is true.
2391    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2392    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2393            or suffix_always is true
2394    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2395    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2396    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2397    "LW" => print 'd', 'q' depending on the VEX.W bit
2398    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2399            an operand size prefix, or suffix_always is true.  print
2400            'q' if rex prefix is present.
2401
2402    Many of the above letters print nothing in Intel mode.  See "putop"
2403    for the details.
2404
2405    Braces '{' and '}', and vertical bars '|', indicate alternative
2406    mnemonic strings for AT&T and Intel.  */
2407
2408 static const struct dis386 dis386[] = {
2409   /* 00 */
2410   { "addB",             { Ebh1, Gb } },
2411   { "addS",             { Evh1, Gv } },
2412   { "addB",             { Gb, EbS } },
2413   { "addS",             { Gv, EvS } },
2414   { "addB",             { AL, Ib } },
2415   { "addS",             { eAX, Iv } },
2416   { X86_64_TABLE (X86_64_06) },
2417   { X86_64_TABLE (X86_64_07) },
2418   /* 08 */
2419   { "orB",              { Ebh1, Gb } },
2420   { "orS",              { Evh1, Gv } },
2421   { "orB",              { Gb, EbS } },
2422   { "orS",              { Gv, EvS } },
2423   { "orB",              { AL, Ib } },
2424   { "orS",              { eAX, Iv } },
2425   { X86_64_TABLE (X86_64_0D) },
2426   { Bad_Opcode },       /* 0x0f extended opcode escape */
2427   /* 10 */
2428   { "adcB",             { Ebh1, Gb } },
2429   { "adcS",             { Evh1, Gv } },
2430   { "adcB",             { Gb, EbS } },
2431   { "adcS",             { Gv, EvS } },
2432   { "adcB",             { AL, Ib } },
2433   { "adcS",             { eAX, Iv } },
2434   { X86_64_TABLE (X86_64_16) },
2435   { X86_64_TABLE (X86_64_17) },
2436   /* 18 */
2437   { "sbbB",             { Ebh1, Gb } },
2438   { "sbbS",             { Evh1, Gv } },
2439   { "sbbB",             { Gb, EbS } },
2440   { "sbbS",             { Gv, EvS } },
2441   { "sbbB",             { AL, Ib } },
2442   { "sbbS",             { eAX, Iv } },
2443   { X86_64_TABLE (X86_64_1E) },
2444   { X86_64_TABLE (X86_64_1F) },
2445   /* 20 */
2446   { "andB",             { Ebh1, Gb } },
2447   { "andS",             { Evh1, Gv } },
2448   { "andB",             { Gb, EbS } },
2449   { "andS",             { Gv, EvS } },
2450   { "andB",             { AL, Ib } },
2451   { "andS",             { eAX, Iv } },
2452   { Bad_Opcode },       /* SEG ES prefix */
2453   { X86_64_TABLE (X86_64_27) },
2454   /* 28 */
2455   { "subB",             { Ebh1, Gb } },
2456   { "subS",             { Evh1, Gv } },
2457   { "subB",             { Gb, EbS } },
2458   { "subS",             { Gv, EvS } },
2459   { "subB",             { AL, Ib } },
2460   { "subS",             { eAX, Iv } },
2461   { Bad_Opcode },       /* SEG CS prefix */
2462   { X86_64_TABLE (X86_64_2F) },
2463   /* 30 */
2464   { "xorB",             { Ebh1, Gb } },
2465   { "xorS",             { Evh1, Gv } },
2466   { "xorB",             { Gb, EbS } },
2467   { "xorS",             { Gv, EvS } },
2468   { "xorB",             { AL, Ib } },
2469   { "xorS",             { eAX, Iv } },
2470   { Bad_Opcode },       /* SEG SS prefix */
2471   { X86_64_TABLE (X86_64_37) },
2472   /* 38 */
2473   { "cmpB",             { Eb, Gb } },
2474   { "cmpS",             { Ev, Gv } },
2475   { "cmpB",             { Gb, EbS } },
2476   { "cmpS",             { Gv, EvS } },
2477   { "cmpB",             { AL, Ib } },
2478   { "cmpS",             { eAX, Iv } },
2479   { Bad_Opcode },       /* SEG DS prefix */
2480   { X86_64_TABLE (X86_64_3F) },
2481   /* 40 */
2482   { "inc{S|}",          { RMeAX } },
2483   { "inc{S|}",          { RMeCX } },
2484   { "inc{S|}",          { RMeDX } },
2485   { "inc{S|}",          { RMeBX } },
2486   { "inc{S|}",          { RMeSP } },
2487   { "inc{S|}",          { RMeBP } },
2488   { "inc{S|}",          { RMeSI } },
2489   { "inc{S|}",          { RMeDI } },
2490   /* 48 */
2491   { "dec{S|}",          { RMeAX } },
2492   { "dec{S|}",          { RMeCX } },
2493   { "dec{S|}",          { RMeDX } },
2494   { "dec{S|}",          { RMeBX } },
2495   { "dec{S|}",          { RMeSP } },
2496   { "dec{S|}",          { RMeBP } },
2497   { "dec{S|}",          { RMeSI } },
2498   { "dec{S|}",          { RMeDI } },
2499   /* 50 */
2500   { "pushV",            { RMrAX } },
2501   { "pushV",            { RMrCX } },
2502   { "pushV",            { RMrDX } },
2503   { "pushV",            { RMrBX } },
2504   { "pushV",            { RMrSP } },
2505   { "pushV",            { RMrBP } },
2506   { "pushV",            { RMrSI } },
2507   { "pushV",            { RMrDI } },
2508   /* 58 */
2509   { "popV",             { RMrAX } },
2510   { "popV",             { RMrCX } },
2511   { "popV",             { RMrDX } },
2512   { "popV",             { RMrBX } },
2513   { "popV",             { RMrSP } },
2514   { "popV",             { RMrBP } },
2515   { "popV",             { RMrSI } },
2516   { "popV",             { RMrDI } },
2517   /* 60 */
2518   { X86_64_TABLE (X86_64_60) },
2519   { X86_64_TABLE (X86_64_61) },
2520   { X86_64_TABLE (X86_64_62) },
2521   { X86_64_TABLE (X86_64_63) },
2522   { Bad_Opcode },       /* seg fs */
2523   { Bad_Opcode },       /* seg gs */
2524   { Bad_Opcode },       /* op size prefix */
2525   { Bad_Opcode },       /* adr size prefix */
2526   /* 68 */
2527   { "pushT",            { sIv } },
2528   { "imulS",            { Gv, Ev, Iv } },
2529   { "pushT",            { sIbT } },
2530   { "imulS",            { Gv, Ev, sIb } },
2531   { "ins{b|}",          { Ybr, indirDX } },
2532   { X86_64_TABLE (X86_64_6D) },
2533   { "outs{b|}",         { indirDXr, Xb } },
2534   { X86_64_TABLE (X86_64_6F) },
2535   /* 70 */
2536   { "joH",              { Jb, BND, cond_jump_flag } },
2537   { "jnoH",             { Jb, BND, cond_jump_flag } },
2538   { "jbH",              { Jb, BND, cond_jump_flag } },
2539   { "jaeH",             { Jb, BND, cond_jump_flag } },
2540   { "jeH",              { Jb, BND, cond_jump_flag } },
2541   { "jneH",             { Jb, BND, cond_jump_flag } },
2542   { "jbeH",             { Jb, BND, cond_jump_flag } },
2543   { "jaH",              { Jb, BND, cond_jump_flag } },
2544   /* 78 */
2545   { "jsH",              { Jb, BND, cond_jump_flag } },
2546   { "jnsH",             { Jb, BND, cond_jump_flag } },
2547   { "jpH",              { Jb, BND, cond_jump_flag } },
2548   { "jnpH",             { Jb, BND, cond_jump_flag } },
2549   { "jlH",              { Jb, BND, cond_jump_flag } },
2550   { "jgeH",             { Jb, BND, cond_jump_flag } },
2551   { "jleH",             { Jb, BND, cond_jump_flag } },
2552   { "jgH",              { Jb, BND, cond_jump_flag } },
2553   /* 80 */
2554   { REG_TABLE (REG_80) },
2555   { REG_TABLE (REG_81) },
2556   { Bad_Opcode },
2557   { REG_TABLE (REG_82) },
2558   { "testB",            { Eb, Gb } },
2559   { "testS",            { Ev, Gv } },
2560   { "xchgB",            { Ebh2, Gb } },
2561   { "xchgS",            { Evh2, Gv } },
2562   /* 88 */
2563   { "movB",             { Ebh3, Gb } },
2564   { "movS",             { Evh3, Gv } },
2565   { "movB",             { Gb, EbS } },
2566   { "movS",             { Gv, EvS } },
2567   { "movD",             { Sv, Sw } },
2568   { MOD_TABLE (MOD_8D) },
2569   { "movD",             { Sw, Sv } },
2570   { REG_TABLE (REG_8F) },
2571   /* 90 */
2572   { PREFIX_TABLE (PREFIX_90) },
2573   { "xchgS",            { RMeCX, eAX } },
2574   { "xchgS",            { RMeDX, eAX } },
2575   { "xchgS",            { RMeBX, eAX } },
2576   { "xchgS",            { RMeSP, eAX } },
2577   { "xchgS",            { RMeBP, eAX } },
2578   { "xchgS",            { RMeSI, eAX } },
2579   { "xchgS",            { RMeDI, eAX } },
2580   /* 98 */
2581   { "cW{t|}R",          { XX } },
2582   { "cR{t|}O",          { XX } },
2583   { X86_64_TABLE (X86_64_9A) },
2584   { Bad_Opcode },       /* fwait */
2585   { "pushfT",           { XX } },
2586   { "popfT",            { XX } },
2587   { "sahf",             { XX } },
2588   { "lahf",             { XX } },
2589   /* a0 */
2590   { "mov%LB",           { AL, Ob } },
2591   { "mov%LS",           { eAX, Ov } },
2592   { "mov%LB",           { Ob, AL } },
2593   { "mov%LS",           { Ov, eAX } },
2594   { "movs{b|}",         { Ybr, Xb } },
2595   { "movs{R|}",         { Yvr, Xv } },
2596   { "cmps{b|}",         { Xb, Yb } },
2597   { "cmps{R|}",         { Xv, Yv } },
2598   /* a8 */
2599   { "testB",            { AL, Ib } },
2600   { "testS",            { eAX, Iv } },
2601   { "stosB",            { Ybr, AL } },
2602   { "stosS",            { Yvr, eAX } },
2603   { "lodsB",            { ALr, Xb } },
2604   { "lodsS",            { eAXr, Xv } },
2605   { "scasB",            { AL, Yb } },
2606   { "scasS",            { eAX, Yv } },
2607   /* b0 */
2608   { "movB",             { RMAL, Ib } },
2609   { "movB",             { RMCL, Ib } },
2610   { "movB",             { RMDL, Ib } },
2611   { "movB",             { RMBL, Ib } },
2612   { "movB",             { RMAH, Ib } },
2613   { "movB",             { RMCH, Ib } },
2614   { "movB",             { RMDH, Ib } },
2615   { "movB",             { RMBH, Ib } },
2616   /* b8 */
2617   { "mov%LV",           { RMeAX, Iv64 } },
2618   { "mov%LV",           { RMeCX, Iv64 } },
2619   { "mov%LV",           { RMeDX, Iv64 } },
2620   { "mov%LV",           { RMeBX, Iv64 } },
2621   { "mov%LV",           { RMeSP, Iv64 } },
2622   { "mov%LV",           { RMeBP, Iv64 } },
2623   { "mov%LV",           { RMeSI, Iv64 } },
2624   { "mov%LV",           { RMeDI, Iv64 } },
2625   /* c0 */
2626   { REG_TABLE (REG_C0) },
2627   { REG_TABLE (REG_C1) },
2628   { "retT",             { Iw, BND } },
2629   { "retT",             { BND } },
2630   { X86_64_TABLE (X86_64_C4) },
2631   { X86_64_TABLE (X86_64_C5) },
2632   { REG_TABLE (REG_C6) },
2633   { REG_TABLE (REG_C7) },
2634   /* c8 */
2635   { "enterT",           { Iw, Ib } },
2636   { "leaveT",           { XX } },
2637   { "Jret{|f}P",        { Iw } },
2638   { "Jret{|f}P",        { XX } },
2639   { "int3",             { XX } },
2640   { "int",              { Ib } },
2641   { X86_64_TABLE (X86_64_CE) },
2642   { "iret%LP",          { XX } },
2643   /* d0 */
2644   { REG_TABLE (REG_D0) },
2645   { REG_TABLE (REG_D1) },
2646   { REG_TABLE (REG_D2) },
2647   { REG_TABLE (REG_D3) },
2648   { X86_64_TABLE (X86_64_D4) },
2649   { X86_64_TABLE (X86_64_D5) },
2650   { Bad_Opcode },
2651   { "xlat",             { DSBX } },
2652   /* d8 */
2653   { FLOAT },
2654   { FLOAT },
2655   { FLOAT },
2656   { FLOAT },
2657   { FLOAT },
2658   { FLOAT },
2659   { FLOAT },
2660   { FLOAT },
2661   /* e0 */
2662   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2663   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2664   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2665   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2666   { "inB",              { AL, Ib } },
2667   { "inG",              { zAX, Ib } },
2668   { "outB",             { Ib, AL } },
2669   { "outG",             { Ib, zAX } },
2670   /* e8 */
2671   { "callT",            { Jv, BND } },
2672   { "jmpT",             { Jv, BND } },
2673   { X86_64_TABLE (X86_64_EA) },
2674   { "jmp",              { Jb, BND } },
2675   { "inB",              { AL, indirDX } },
2676   { "inG",              { zAX, indirDX } },
2677   { "outB",             { indirDX, AL } },
2678   { "outG",             { indirDX, zAX } },
2679   /* f0 */
2680   { Bad_Opcode },       /* lock prefix */
2681   { "icebp",            { XX } },
2682   { Bad_Opcode },       /* repne */
2683   { Bad_Opcode },       /* repz */
2684   { "hlt",              { XX } },
2685   { "cmc",              { XX } },
2686   { REG_TABLE (REG_F6) },
2687   { REG_TABLE (REG_F7) },
2688   /* f8 */
2689   { "clc",              { XX } },
2690   { "stc",              { XX } },
2691   { "cli",              { XX } },
2692   { "sti",              { XX } },
2693   { "cld",              { XX } },
2694   { "std",              { XX } },
2695   { REG_TABLE (REG_FE) },
2696   { REG_TABLE (REG_FF) },
2697 };
2698
2699 static const struct dis386 dis386_twobyte[] = {
2700   /* 00 */
2701   { REG_TABLE (REG_0F00 ) },
2702   { REG_TABLE (REG_0F01 ) },
2703   { "larS",             { Gv, Ew } },
2704   { "lslS",             { Gv, Ew } },
2705   { Bad_Opcode },
2706   { "syscall",          { XX } },
2707   { "clts",             { XX } },
2708   { "sysret%LP",                { XX } },
2709   /* 08 */
2710   { "invd",             { XX } },
2711   { "wbinvd",           { XX } },
2712   { Bad_Opcode },
2713   { "ud2",              { XX } },
2714   { Bad_Opcode },
2715   { REG_TABLE (REG_0F0D) },
2716   { "femms",            { XX } },
2717   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2718   /* 10 */
2719   { PREFIX_TABLE (PREFIX_0F10) },
2720   { PREFIX_TABLE (PREFIX_0F11) },
2721   { PREFIX_TABLE (PREFIX_0F12) },
2722   { MOD_TABLE (MOD_0F13) },
2723   { "unpcklpX",         { XM, EXx } },
2724   { "unpckhpX",         { XM, EXx } },
2725   { PREFIX_TABLE (PREFIX_0F16) },
2726   { MOD_TABLE (MOD_0F17) },
2727   /* 18 */
2728   { REG_TABLE (REG_0F18) },
2729   { "nopQ",             { Ev } },
2730   { PREFIX_TABLE (PREFIX_0F1A) },
2731   { PREFIX_TABLE (PREFIX_0F1B) },
2732   { "nopQ",             { Ev } },
2733   { "nopQ",             { Ev } },
2734   { "nopQ",             { Ev } },
2735   { "nopQ",             { Ev } },
2736   /* 20 */
2737   { "movZ",             { Rm, Cm } },
2738   { "movZ",             { Rm, Dm } },
2739   { "movZ",             { Cm, Rm } },
2740   { "movZ",             { Dm, Rm } },
2741   { MOD_TABLE (MOD_0F24) },
2742   { Bad_Opcode },
2743   { MOD_TABLE (MOD_0F26) },
2744   { Bad_Opcode },
2745   /* 28 */
2746   { "movapX",           { XM, EXx } },
2747   { "movapX",           { EXxS, XM } },
2748   { PREFIX_TABLE (PREFIX_0F2A) },
2749   { PREFIX_TABLE (PREFIX_0F2B) },
2750   { PREFIX_TABLE (PREFIX_0F2C) },
2751   { PREFIX_TABLE (PREFIX_0F2D) },
2752   { PREFIX_TABLE (PREFIX_0F2E) },
2753   { PREFIX_TABLE (PREFIX_0F2F) },
2754   /* 30 */
2755   { "wrmsr",            { XX } },
2756   { "rdtsc",            { XX } },
2757   { "rdmsr",            { XX } },
2758   { "rdpmc",            { XX } },
2759   { "sysenter",         { XX } },
2760   { "sysexit",          { XX } },
2761   { Bad_Opcode },
2762   { "getsec",           { XX } },
2763   /* 38 */
2764   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2765   { Bad_Opcode },
2766   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2767   { Bad_Opcode },
2768   { Bad_Opcode },
2769   { Bad_Opcode },
2770   { Bad_Opcode },
2771   { Bad_Opcode },
2772   /* 40 */
2773   { "cmovoS",           { Gv, Ev } },
2774   { "cmovnoS",          { Gv, Ev } },
2775   { "cmovbS",           { Gv, Ev } },
2776   { "cmovaeS",          { Gv, Ev } },
2777   { "cmoveS",           { Gv, Ev } },
2778   { "cmovneS",          { Gv, Ev } },
2779   { "cmovbeS",          { Gv, Ev } },
2780   { "cmovaS",           { Gv, Ev } },
2781   /* 48 */
2782   { "cmovsS",           { Gv, Ev } },
2783   { "cmovnsS",          { Gv, Ev } },
2784   { "cmovpS",           { Gv, Ev } },
2785   { "cmovnpS",          { Gv, Ev } },
2786   { "cmovlS",           { Gv, Ev } },
2787   { "cmovgeS",          { Gv, Ev } },
2788   { "cmovleS",          { Gv, Ev } },
2789   { "cmovgS",           { Gv, Ev } },
2790   /* 50 */
2791   { MOD_TABLE (MOD_0F51) },
2792   { PREFIX_TABLE (PREFIX_0F51) },
2793   { PREFIX_TABLE (PREFIX_0F52) },
2794   { PREFIX_TABLE (PREFIX_0F53) },
2795   { "andpX",            { XM, EXx } },
2796   { "andnpX",           { XM, EXx } },
2797   { "orpX",             { XM, EXx } },
2798   { "xorpX",            { XM, EXx } },
2799   /* 58 */
2800   { PREFIX_TABLE (PREFIX_0F58) },
2801   { PREFIX_TABLE (PREFIX_0F59) },
2802   { PREFIX_TABLE (PREFIX_0F5A) },
2803   { PREFIX_TABLE (PREFIX_0F5B) },
2804   { PREFIX_TABLE (PREFIX_0F5C) },
2805   { PREFIX_TABLE (PREFIX_0F5D) },
2806   { PREFIX_TABLE (PREFIX_0F5E) },
2807   { PREFIX_TABLE (PREFIX_0F5F) },
2808   /* 60 */
2809   { PREFIX_TABLE (PREFIX_0F60) },
2810   { PREFIX_TABLE (PREFIX_0F61) },
2811   { PREFIX_TABLE (PREFIX_0F62) },
2812   { "packsswb",         { MX, EM } },
2813   { "pcmpgtb",          { MX, EM } },
2814   { "pcmpgtw",          { MX, EM } },
2815   { "pcmpgtd",          { MX, EM } },
2816   { "packuswb",         { MX, EM } },
2817   /* 68 */
2818   { "punpckhbw",        { MX, EM } },
2819   { "punpckhwd",        { MX, EM } },
2820   { "punpckhdq",        { MX, EM } },
2821   { "packssdw",         { MX, EM } },
2822   { PREFIX_TABLE (PREFIX_0F6C) },
2823   { PREFIX_TABLE (PREFIX_0F6D) },
2824   { "movK",             { MX, Edq } },
2825   { PREFIX_TABLE (PREFIX_0F6F) },
2826   /* 70 */
2827   { PREFIX_TABLE (PREFIX_0F70) },
2828   { REG_TABLE (REG_0F71) },
2829   { REG_TABLE (REG_0F72) },
2830   { REG_TABLE (REG_0F73) },
2831   { "pcmpeqb",          { MX, EM } },
2832   { "pcmpeqw",          { MX, EM } },
2833   { "pcmpeqd",          { MX, EM } },
2834   { "emms",             { XX } },
2835   /* 78 */
2836   { PREFIX_TABLE (PREFIX_0F78) },
2837   { PREFIX_TABLE (PREFIX_0F79) },
2838   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2839   { Bad_Opcode },
2840   { PREFIX_TABLE (PREFIX_0F7C) },
2841   { PREFIX_TABLE (PREFIX_0F7D) },
2842   { PREFIX_TABLE (PREFIX_0F7E) },
2843   { PREFIX_TABLE (PREFIX_0F7F) },
2844   /* 80 */
2845   { "joH",              { Jv, BND, cond_jump_flag } },
2846   { "jnoH",             { Jv, BND, cond_jump_flag } },
2847   { "jbH",              { Jv, BND, cond_jump_flag } },
2848   { "jaeH",             { Jv, BND, cond_jump_flag } },
2849   { "jeH",              { Jv, BND, cond_jump_flag } },
2850   { "jneH",             { Jv, BND, cond_jump_flag } },
2851   { "jbeH",             { Jv, BND, cond_jump_flag } },
2852   { "jaH",              { Jv, BND, cond_jump_flag } },
2853   /* 88 */
2854   { "jsH",              { Jv, BND, cond_jump_flag } },
2855   { "jnsH",             { Jv, BND, cond_jump_flag } },
2856   { "jpH",              { Jv, BND, cond_jump_flag } },
2857   { "jnpH",             { Jv, BND, cond_jump_flag } },
2858   { "jlH",              { Jv, BND, cond_jump_flag } },
2859   { "jgeH",             { Jv, BND, cond_jump_flag } },
2860   { "jleH",             { Jv, BND, cond_jump_flag } },
2861   { "jgH",              { Jv, BND, cond_jump_flag } },
2862   /* 90 */
2863   { "seto",             { Eb } },
2864   { "setno",            { Eb } },
2865   { "setb",             { Eb } },
2866   { "setae",            { Eb } },
2867   { "sete",             { Eb } },
2868   { "setne",            { Eb } },
2869   { "setbe",            { Eb } },
2870   { "seta",             { Eb } },
2871   /* 98 */
2872   { "sets",             { Eb } },
2873   { "setns",            { Eb } },
2874   { "setp",             { Eb } },
2875   { "setnp",            { Eb } },
2876   { "setl",             { Eb } },
2877   { "setge",            { Eb } },
2878   { "setle",            { Eb } },
2879   { "setg",             { Eb } },
2880   /* a0 */
2881   { "pushT",            { fs } },
2882   { "popT",             { fs } },
2883   { "cpuid",            { XX } },
2884   { "btS",              { Ev, Gv } },
2885   { "shldS",            { Ev, Gv, Ib } },
2886   { "shldS",            { Ev, Gv, CL } },
2887   { REG_TABLE (REG_0FA6) },
2888   { REG_TABLE (REG_0FA7) },
2889   /* a8 */
2890   { "pushT",            { gs } },
2891   { "popT",             { gs } },
2892   { "rsm",              { XX } },
2893   { "btsS",             { Evh1, Gv } },
2894   { "shrdS",            { Ev, Gv, Ib } },
2895   { "shrdS",            { Ev, Gv, CL } },
2896   { REG_TABLE (REG_0FAE) },
2897   { "imulS",            { Gv, Ev } },
2898   /* b0 */
2899   { "cmpxchgB",         { Ebh1, Gb } },
2900   { "cmpxchgS",         { Evh1, Gv } },
2901   { MOD_TABLE (MOD_0FB2) },
2902   { "btrS",             { Evh1, Gv } },
2903   { MOD_TABLE (MOD_0FB4) },
2904   { MOD_TABLE (MOD_0FB5) },
2905   { "movz{bR|x}",       { Gv, Eb } },
2906   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2907   /* b8 */
2908   { PREFIX_TABLE (PREFIX_0FB8) },
2909   { "ud1",              { XX } },
2910   { REG_TABLE (REG_0FBA) },
2911   { "btcS",             { Evh1, Gv } },
2912   { PREFIX_TABLE (PREFIX_0FBC) },
2913   { PREFIX_TABLE (PREFIX_0FBD) },
2914   { "movs{bR|x}",       { Gv, Eb } },
2915   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2916   /* c0 */
2917   { "xaddB",            { Ebh1, Gb } },
2918   { "xaddS",            { Evh1, Gv } },
2919   { PREFIX_TABLE (PREFIX_0FC2) },
2920   { PREFIX_TABLE (PREFIX_0FC3) },
2921   { "pinsrw",           { MX, Edqw, Ib } },
2922   { "pextrw",           { Gdq, MS, Ib } },
2923   { "shufpX",           { XM, EXx, Ib } },
2924   { REG_TABLE (REG_0FC7) },
2925   /* c8 */
2926   { "bswap",            { RMeAX } },
2927   { "bswap",            { RMeCX } },
2928   { "bswap",            { RMeDX } },
2929   { "bswap",            { RMeBX } },
2930   { "bswap",            { RMeSP } },
2931   { "bswap",            { RMeBP } },
2932   { "bswap",            { RMeSI } },
2933   { "bswap",            { RMeDI } },
2934   /* d0 */
2935   { PREFIX_TABLE (PREFIX_0FD0) },
2936   { "psrlw",            { MX, EM } },
2937   { "psrld",            { MX, EM } },
2938   { "psrlq",            { MX, EM } },
2939   { "paddq",            { MX, EM } },
2940   { "pmullw",           { MX, EM } },
2941   { PREFIX_TABLE (PREFIX_0FD6) },
2942   { MOD_TABLE (MOD_0FD7) },
2943   /* d8 */
2944   { "psubusb",          { MX, EM } },
2945   { "psubusw",          { MX, EM } },
2946   { "pminub",           { MX, EM } },
2947   { "pand",             { MX, EM } },
2948   { "paddusb",          { MX, EM } },
2949   { "paddusw",          { MX, EM } },
2950   { "pmaxub",           { MX, EM } },
2951   { "pandn",            { MX, EM } },
2952   /* e0 */
2953   { "pavgb",            { MX, EM } },
2954   { "psraw",            { MX, EM } },
2955   { "psrad",            { MX, EM } },
2956   { "pavgw",            { MX, EM } },
2957   { "pmulhuw",          { MX, EM } },
2958   { "pmulhw",           { MX, EM } },
2959   { PREFIX_TABLE (PREFIX_0FE6) },
2960   { PREFIX_TABLE (PREFIX_0FE7) },
2961   /* e8 */
2962   { "psubsb",           { MX, EM } },
2963   { "psubsw",           { MX, EM } },
2964   { "pminsw",           { MX, EM } },
2965   { "por",              { MX, EM } },
2966   { "paddsb",           { MX, EM } },
2967   { "paddsw",           { MX, EM } },
2968   { "pmaxsw",           { MX, EM } },
2969   { "pxor",             { MX, EM } },
2970   /* f0 */
2971   { PREFIX_TABLE (PREFIX_0FF0) },
2972   { "psllw",            { MX, EM } },
2973   { "pslld",            { MX, EM } },
2974   { "psllq",            { MX, EM } },
2975   { "pmuludq",          { MX, EM } },
2976   { "pmaddwd",          { MX, EM } },
2977   { "psadbw",           { MX, EM } },
2978   { PREFIX_TABLE (PREFIX_0FF7) },
2979   /* f8 */
2980   { "psubb",            { MX, EM } },
2981   { "psubw",            { MX, EM } },
2982   { "psubd",            { MX, EM } },
2983   { "psubq",            { MX, EM } },
2984   { "paddb",            { MX, EM } },
2985   { "paddw",            { MX, EM } },
2986   { "paddd",            { MX, EM } },
2987   { Bad_Opcode },
2988 };
2989
2990 static const unsigned char onebyte_has_modrm[256] = {
2991   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2992   /*       -------------------------------        */
2993   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2994   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2995   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2996   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2997   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2998   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2999   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3000   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3001   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3002   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3003   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3004   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3005   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3006   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3007   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3008   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3009   /*       -------------------------------        */
3010   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3011 };
3012
3013 static const unsigned char twobyte_has_modrm[256] = {
3014   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3015   /*       -------------------------------        */
3016   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3017   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3018   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3019   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3020   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3021   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3022   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3023   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3024   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3025   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3026   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3027   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3028   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3029   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3030   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3031   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3032   /*       -------------------------------        */
3033   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3034 };
3035
3036 static const unsigned char twobyte_has_mandatory_prefix[256] = {
3037   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3038   /*       -------------------------------        */
3039   /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3040   /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3041   /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3042   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3043   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3044   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3045   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3046   /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3047   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3048   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3049   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3050   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3051   /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3052   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3053   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3054   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3055   /*       -------------------------------        */
3056   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3057 };
3058
3059 static char obuf[100];
3060 static char *obufp;
3061 static char *mnemonicendp;
3062 static char scratchbuf[100];
3063 static unsigned char *start_codep;
3064 static unsigned char *insn_codep;
3065 static unsigned char *codep;
3066 static unsigned char *end_codep;
3067 static int last_lock_prefix;
3068 static int last_repz_prefix;
3069 static int last_repnz_prefix;
3070 static int last_data_prefix;
3071 static int last_addr_prefix;
3072 static int last_rex_prefix;
3073 static int last_seg_prefix;
3074 static int fwait_prefix;
3075 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
3076 static int mandatory_prefix;
3077 /* The active segment register prefix.  */
3078 static int active_seg_prefix;
3079 #define MAX_CODE_LENGTH 15
3080 /* We can up to 14 prefixes since the maximum instruction length is
3081    15bytes.  */
3082 static int all_prefixes[MAX_CODE_LENGTH - 1];
3083 static disassemble_info *the_info;
3084 static struct
3085   {
3086     int mod;
3087     int reg;
3088     int rm;
3089   }
3090 modrm;
3091 static unsigned char need_modrm;
3092 static struct
3093   {
3094     int scale;
3095     int index;
3096     int base;
3097   }
3098 sib;
3099 static struct
3100   {
3101     int register_specifier;
3102     int length;
3103     int prefix;
3104     int w;
3105     int evex;
3106     int r;
3107     int v;
3108     int mask_register_specifier;
3109     int zeroing;
3110     int ll;
3111     int b;
3112   }
3113 vex;
3114 static unsigned char need_vex;
3115 static unsigned char need_vex_reg;
3116 static unsigned char vex_w_done;
3117
3118 struct op
3119   {
3120     const char *name;
3121     unsigned int len;
3122   };
3123
3124 /* If we are accessing mod/rm/reg without need_modrm set, then the
3125    values are stale.  Hitting this abort likely indicates that you
3126    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3127 #define MODRM_CHECK  if (!need_modrm) abort ()
3128
3129 static const char **names64;
3130 static const char **names32;
3131 static const char **names16;
3132 static const char **names8;
3133 static const char **names8rex;
3134 static const char **names_seg;
3135 static const char *index64;
3136 static const char *index32;
3137 static const char **index16;
3138 static const char **names_bnd;
3139
3140 static const char *intel_names64[] = {
3141   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3142   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3143 };
3144 static const char *intel_names32[] = {
3145   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3146   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3147 };
3148 static const char *intel_names16[] = {
3149   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3150   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3151 };
3152 static const char *intel_names8[] = {
3153   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3154 };
3155 static const char *intel_names8rex[] = {
3156   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3157   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3158 };
3159 static const char *intel_names_seg[] = {
3160   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3161 };
3162 static const char *intel_index64 = "riz";
3163 static const char *intel_index32 = "eiz";
3164 static const char *intel_index16[] = {
3165   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3166 };
3167
3168 static const char *att_names64[] = {
3169   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3170   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3171 };
3172 static const char *att_names32[] = {
3173   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3174   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3175 };
3176 static const char *att_names16[] = {
3177   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3178   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3179 };
3180 static const char *att_names8[] = {
3181   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3182 };
3183 static const char *att_names8rex[] = {
3184   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3185   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3186 };
3187 static const char *att_names_seg[] = {
3188   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3189 };
3190 static const char *att_index64 = "%riz";
3191 static const char *att_index32 = "%eiz";
3192 static const char *att_index16[] = {
3193   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3194 };
3195
3196 static const char **names_mm;
3197 static const char *intel_names_mm[] = {
3198   "mm0", "mm1", "mm2", "mm3",
3199   "mm4", "mm5", "mm6", "mm7"
3200 };
3201 static const char *att_names_mm[] = {
3202   "%mm0", "%mm1", "%mm2", "%mm3",
3203   "%mm4", "%mm5", "%mm6", "%mm7"
3204 };
3205
3206 static const char *intel_names_bnd[] = {
3207   "bnd0", "bnd1", "bnd2", "bnd3"
3208 };
3209
3210 static const char *att_names_bnd[] = {
3211   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3212 };
3213
3214 static const char **names_xmm;
3215 static const char *intel_names_xmm[] = {
3216   "xmm0", "xmm1", "xmm2", "xmm3",
3217   "xmm4", "xmm5", "xmm6", "xmm7",
3218   "xmm8", "xmm9", "xmm10", "xmm11",
3219   "xmm12", "xmm13", "xmm14", "xmm15",
3220   "xmm16", "xmm17", "xmm18", "xmm19",
3221   "xmm20", "xmm21", "xmm22", "xmm23",
3222   "xmm24", "xmm25", "xmm26", "xmm27",
3223   "xmm28", "xmm29", "xmm30", "xmm31"
3224 };
3225 static const char *att_names_xmm[] = {
3226   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3227   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3228   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3229   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3230   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3231   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3232   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3233   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3234 };
3235
3236 static const char **names_ymm;
3237 static const char *intel_names_ymm[] = {
3238   "ymm0", "ymm1", "ymm2", "ymm3",
3239   "ymm4", "ymm5", "ymm6", "ymm7",
3240   "ymm8", "ymm9", "ymm10", "ymm11",
3241   "ymm12", "ymm13", "ymm14", "ymm15",
3242   "ymm16", "ymm17", "ymm18", "ymm19",
3243   "ymm20", "ymm21", "ymm22", "ymm23",
3244   "ymm24", "ymm25", "ymm26", "ymm27",
3245   "ymm28", "ymm29", "ymm30", "ymm31"
3246 };
3247 static const char *att_names_ymm[] = {
3248   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3249   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3250   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3251   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3252   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3253   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3254   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3255   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3256 };
3257
3258 static const char **names_zmm;
3259 static const char *intel_names_zmm[] = {
3260   "zmm0", "zmm1", "zmm2", "zmm3",
3261   "zmm4", "zmm5", "zmm6", "zmm7",
3262   "zmm8", "zmm9", "zmm10", "zmm11",
3263   "zmm12", "zmm13", "zmm14", "zmm15",
3264   "zmm16", "zmm17", "zmm18", "zmm19",
3265   "zmm20", "zmm21", "zmm22", "zmm23",
3266   "zmm24", "zmm25", "zmm26", "zmm27",
3267   "zmm28", "zmm29", "zmm30", "zmm31"
3268 };
3269 static const char *att_names_zmm[] = {
3270   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3271   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3272   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3273   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3274   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3275   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3276   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3277   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3278 };
3279
3280 static const char **names_mask;
3281 static const char *intel_names_mask[] = {
3282   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3283 };
3284 static const char *att_names_mask[] = {
3285   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3286 };
3287
3288 static const char *names_rounding[] =
3289 {
3290   "{rn-sae}",
3291   "{rd-sae}",
3292   "{ru-sae}",
3293   "{rz-sae}"
3294 };
3295
3296 static const struct dis386 reg_table[][8] = {
3297   /* REG_80 */
3298   {
3299     { "addA",   { Ebh1, Ib } },
3300     { "orA",    { Ebh1, Ib } },
3301     { "adcA",   { Ebh1, Ib } },
3302     { "sbbA",   { Ebh1, Ib } },
3303     { "andA",   { Ebh1, Ib } },
3304     { "subA",   { Ebh1, Ib } },
3305     { "xorA",   { Ebh1, Ib } },
3306     { "cmpA",   { Eb, Ib } },
3307   },
3308   /* REG_81 */
3309   {
3310     { "addQ",   { Evh1, Iv } },
3311     { "orQ",    { Evh1, Iv } },
3312     { "adcQ",   { Evh1, Iv } },
3313     { "sbbQ",   { Evh1, Iv } },
3314     { "andQ",   { Evh1, Iv } },
3315     { "subQ",   { Evh1, Iv } },
3316     { "xorQ",   { Evh1, Iv } },
3317     { "cmpQ",   { Ev, Iv } },
3318   },
3319   /* REG_82 */
3320   {
3321     { "addQ",   { Evh1, sIb } },
3322     { "orQ",    { Evh1, sIb } },
3323     { "adcQ",   { Evh1, sIb } },
3324     { "sbbQ",   { Evh1, sIb } },
3325     { "andQ",   { Evh1, sIb } },
3326     { "subQ",   { Evh1, sIb } },
3327     { "xorQ",   { Evh1, sIb } },
3328     { "cmpQ",   { Ev, sIb } },
3329   },
3330   /* REG_8F */
3331   {
3332     { "popU",   { stackEv } },
3333     { XOP_8F_TABLE (XOP_09) },
3334     { Bad_Opcode },
3335     { Bad_Opcode },
3336     { Bad_Opcode },
3337     { XOP_8F_TABLE (XOP_09) },
3338   },
3339   /* REG_C0 */
3340   {
3341     { "rolA",   { Eb, Ib } },
3342     { "rorA",   { Eb, Ib } },
3343     { "rclA",   { Eb, Ib } },
3344     { "rcrA",   { Eb, Ib } },
3345     { "shlA",   { Eb, Ib } },
3346     { "shrA",   { Eb, Ib } },
3347     { Bad_Opcode },
3348     { "sarA",   { Eb, Ib } },
3349   },
3350   /* REG_C1 */
3351   {
3352     { "rolQ",   { Ev, Ib } },
3353     { "rorQ",   { Ev, Ib } },
3354     { "rclQ",   { Ev, Ib } },
3355     { "rcrQ",   { Ev, Ib } },
3356     { "shlQ",   { Ev, Ib } },
3357     { "shrQ",   { Ev, Ib } },
3358     { Bad_Opcode },
3359     { "sarQ",   { Ev, Ib } },
3360   },
3361   /* REG_C6 */
3362   {
3363     { "movA",   { Ebh3, Ib } },
3364     { Bad_Opcode },
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { Bad_Opcode },
3368     { Bad_Opcode },
3369     { Bad_Opcode },
3370     { MOD_TABLE (MOD_C6_REG_7) },
3371   },
3372   /* REG_C7 */
3373   {
3374     { "movQ",   { Evh3, Iv } },
3375     { Bad_Opcode },
3376     { Bad_Opcode },
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { MOD_TABLE (MOD_C7_REG_7) },
3382   },
3383   /* REG_D0 */
3384   {
3385     { "rolA",   { Eb, I1 } },
3386     { "rorA",   { Eb, I1 } },
3387     { "rclA",   { Eb, I1 } },
3388     { "rcrA",   { Eb, I1 } },
3389     { "shlA",   { Eb, I1 } },
3390     { "shrA",   { Eb, I1 } },
3391     { Bad_Opcode },
3392     { "sarA",   { Eb, I1 } },
3393   },
3394   /* REG_D1 */
3395   {
3396     { "rolQ",   { Ev, I1 } },
3397     { "rorQ",   { Ev, I1 } },
3398     { "rclQ",   { Ev, I1 } },
3399     { "rcrQ",   { Ev, I1 } },
3400     { "shlQ",   { Ev, I1 } },
3401     { "shrQ",   { Ev, I1 } },
3402     { Bad_Opcode },
3403     { "sarQ",   { Ev, I1 } },
3404   },
3405   /* REG_D2 */
3406   {
3407     { "rolA",   { Eb, CL } },
3408     { "rorA",   { Eb, CL } },
3409     { "rclA",   { Eb, CL } },
3410     { "rcrA",   { Eb, CL } },
3411     { "shlA",   { Eb, CL } },
3412     { "shrA",   { Eb, CL } },
3413     { Bad_Opcode },
3414     { "sarA",   { Eb, CL } },
3415   },
3416   /* REG_D3 */
3417   {
3418     { "rolQ",   { Ev, CL } },
3419     { "rorQ",   { Ev, CL } },
3420     { "rclQ",   { Ev, CL } },
3421     { "rcrQ",   { Ev, CL } },
3422     { "shlQ",   { Ev, CL } },
3423     { "shrQ",   { Ev, CL } },
3424     { Bad_Opcode },
3425     { "sarQ",   { Ev, CL } },
3426   },
3427   /* REG_F6 */
3428   {
3429     { "testA",  { Eb, Ib } },
3430     { Bad_Opcode },
3431     { "notA",   { Ebh1 } },
3432     { "negA",   { Ebh1 } },
3433     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3434     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3435     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3436     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3437   },
3438   /* REG_F7 */
3439   {
3440     { "testQ",  { Ev, Iv } },
3441     { Bad_Opcode },
3442     { "notQ",   { Evh1 } },
3443     { "negQ",   { Evh1 } },
3444     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3445     { "imulQ",  { Ev } },
3446     { "divQ",   { Ev } },
3447     { "idivQ",  { Ev } },
3448   },
3449   /* REG_FE */
3450   {
3451     { "incA",   { Ebh1 } },
3452     { "decA",   { Ebh1 } },
3453   },
3454   /* REG_FF */
3455   {
3456     { "incQ",   { Evh1 } },
3457     { "decQ",   { Evh1 } },
3458     { "call{T|}", { indirEv, BND } },
3459     { MOD_TABLE (MOD_FF_REG_3) },
3460     { "jmp{T|}", { indirEv, BND } },
3461     { MOD_TABLE (MOD_FF_REG_5) },
3462     { "pushU",  { stackEv } },
3463     { Bad_Opcode },
3464   },
3465   /* REG_0F00 */
3466   {
3467     { "sldtD",  { Sv } },
3468     { "strD",   { Sv } },
3469     { "lldt",   { Ew } },
3470     { "ltr",    { Ew } },
3471     { "verr",   { Ew } },
3472     { "verw",   { Ew } },
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475   },
3476   /* REG_0F01 */
3477   {
3478     { MOD_TABLE (MOD_0F01_REG_0) },
3479     { MOD_TABLE (MOD_0F01_REG_1) },
3480     { MOD_TABLE (MOD_0F01_REG_2) },
3481     { MOD_TABLE (MOD_0F01_REG_3) },
3482     { "smswD",  { Sv } },
3483     { Bad_Opcode },
3484     { "lmsw",   { Ew } },
3485     { MOD_TABLE (MOD_0F01_REG_7) },
3486   },
3487   /* REG_0F0D */
3488   {
3489     { "prefetch",       { Mb } },
3490     { "prefetchw",      { Mb } },
3491     { "prefetchwt1",    { Mb } },
3492     { "prefetch",       { Mb } },
3493     { "prefetch",       { Mb } },
3494     { "prefetch",       { Mb } },
3495     { "prefetch",       { Mb } },
3496     { "prefetch",       { Mb } },
3497   },
3498   /* REG_0F18 */
3499   {
3500     { MOD_TABLE (MOD_0F18_REG_0) },
3501     { MOD_TABLE (MOD_0F18_REG_1) },
3502     { MOD_TABLE (MOD_0F18_REG_2) },
3503     { MOD_TABLE (MOD_0F18_REG_3) },
3504     { MOD_TABLE (MOD_0F18_REG_4) },
3505     { MOD_TABLE (MOD_0F18_REG_5) },
3506     { MOD_TABLE (MOD_0F18_REG_6) },
3507     { MOD_TABLE (MOD_0F18_REG_7) },
3508   },
3509   /* REG_0F71 */
3510   {
3511     { Bad_Opcode },
3512     { Bad_Opcode },
3513     { MOD_TABLE (MOD_0F71_REG_2) },
3514     { Bad_Opcode },
3515     { MOD_TABLE (MOD_0F71_REG_4) },
3516     { Bad_Opcode },
3517     { MOD_TABLE (MOD_0F71_REG_6) },
3518   },
3519   /* REG_0F72 */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { MOD_TABLE (MOD_0F72_REG_2) },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_0F72_REG_4) },
3526     { Bad_Opcode },
3527     { MOD_TABLE (MOD_0F72_REG_6) },
3528   },
3529   /* REG_0F73 */
3530   {
3531     { Bad_Opcode },
3532     { Bad_Opcode },
3533     { MOD_TABLE (MOD_0F73_REG_2) },
3534     { MOD_TABLE (MOD_0F73_REG_3) },
3535     { Bad_Opcode },
3536     { Bad_Opcode },
3537     { MOD_TABLE (MOD_0F73_REG_6) },
3538     { MOD_TABLE (MOD_0F73_REG_7) },
3539   },
3540   /* REG_0FA6 */
3541   {
3542     { "montmul",        { { OP_0f07, 0 } } },
3543     { "xsha1",          { { OP_0f07, 0 } } },
3544     { "xsha256",        { { OP_0f07, 0 } } },
3545   },
3546   /* REG_0FA7 */
3547   {
3548     { "xstore-rng",     { { OP_0f07, 0 } } },
3549     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3550     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3551     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3552     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3553     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3554   },
3555   /* REG_0FAE */
3556   {
3557     { MOD_TABLE (MOD_0FAE_REG_0) },
3558     { MOD_TABLE (MOD_0FAE_REG_1) },
3559     { MOD_TABLE (MOD_0FAE_REG_2) },
3560     { MOD_TABLE (MOD_0FAE_REG_3) },
3561     { MOD_TABLE (MOD_0FAE_REG_4) },
3562     { MOD_TABLE (MOD_0FAE_REG_5) },
3563     { MOD_TABLE (MOD_0FAE_REG_6) },
3564     { MOD_TABLE (MOD_0FAE_REG_7) },
3565   },
3566   /* REG_0FBA */
3567   {
3568     { Bad_Opcode },
3569     { Bad_Opcode },
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { "btQ",    { Ev, Ib } },
3573     { "btsQ",   { Evh1, Ib } },
3574     { "btrQ",   { Evh1, Ib } },
3575     { "btcQ",   { Evh1, Ib } },
3576   },
3577   /* REG_0FC7 */
3578   {
3579     { Bad_Opcode },
3580     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3581     { Bad_Opcode },
3582     { MOD_TABLE (MOD_0FC7_REG_3) },
3583     { MOD_TABLE (MOD_0FC7_REG_4) },
3584     { MOD_TABLE (MOD_0FC7_REG_5) },
3585     { MOD_TABLE (MOD_0FC7_REG_6) },
3586     { MOD_TABLE (MOD_0FC7_REG_7) },
3587   },
3588   /* REG_VEX_0F71 */
3589   {
3590     { Bad_Opcode },
3591     { Bad_Opcode },
3592     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3593     { Bad_Opcode },
3594     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3595     { Bad_Opcode },
3596     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3597   },
3598   /* REG_VEX_0F72 */
3599   {
3600     { Bad_Opcode },
3601     { Bad_Opcode },
3602     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3603     { Bad_Opcode },
3604     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3605     { Bad_Opcode },
3606     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3607   },
3608   /* REG_VEX_0F73 */
3609   {
3610     { Bad_Opcode },
3611     { Bad_Opcode },
3612     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3613     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3617     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3618   },
3619   /* REG_VEX_0FAE */
3620   {
3621     { Bad_Opcode },
3622     { Bad_Opcode },
3623     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3624     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3625   },
3626   /* REG_VEX_0F38F3 */
3627   {
3628     { Bad_Opcode },
3629     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3630     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3631     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3632   },
3633   /* REG_XOP_LWPCB */
3634   {
3635     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3636     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3637   },
3638   /* REG_XOP_LWP */
3639   {
3640     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3641     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3642   },
3643   /* REG_XOP_TBM_01 */
3644   {
3645     { Bad_Opcode },
3646     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3647     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3648     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3649     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3650     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3651     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3652     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3653   },
3654   /* REG_XOP_TBM_02 */
3655   {
3656     { Bad_Opcode },
3657     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3658     { Bad_Opcode },
3659     { Bad_Opcode },
3660     { Bad_Opcode },
3661     { Bad_Opcode },
3662     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3663   },
3664 #define NEED_REG_TABLE
3665 #include "i386-dis-evex.h"
3666 #undef NEED_REG_TABLE
3667 };
3668
3669 static const struct dis386 prefix_table[][4] = {
3670   /* PREFIX_90 */
3671   {
3672     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3673     { "pause", { XX } },
3674     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3675   },
3676
3677   /* PREFIX_0F10 */
3678   {
3679     { "movups", { XM, EXx } },
3680     { "movss",  { XM, EXd } },
3681     { "movupd", { XM, EXx } },
3682     { "movsd",  { XM, EXq } },
3683   },
3684
3685   /* PREFIX_0F11 */
3686   {
3687     { "movups", { EXxS, XM } },
3688     { "movss",  { EXdS, XM } },
3689     { "movupd", { EXxS, XM } },
3690     { "movsd",  { EXqS, XM } },
3691   },
3692
3693   /* PREFIX_0F12 */
3694   {
3695     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3696     { "movsldup", { XM, EXx } },
3697     { "movlpd", { XM, EXq } },
3698     { "movddup", { XM, EXq } },
3699   },
3700
3701   /* PREFIX_0F16 */
3702   {
3703     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3704     { "movshdup", { XM, EXx } },
3705     { "movhpd", { XM, EXq } },
3706   },
3707
3708   /* PREFIX_0F1A */
3709   {
3710     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3711     { "bndcl",  { Gbnd, Ev_bnd } },
3712     { "bndmov", { Gbnd, Ebnd } },
3713     { "bndcu",  { Gbnd, Ev_bnd } },
3714   },
3715
3716   /* PREFIX_0F1B */
3717   {
3718     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3719     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3720     { "bndmov", { Ebnd, Gbnd } },
3721     { "bndcn",  { Gbnd, Ev_bnd } },
3722   },
3723
3724   /* PREFIX_0F2A */
3725   {
3726     { "cvtpi2ps", { XM, EMCq } },
3727     { "cvtsi2ss%LQ", { XM, Ev } },
3728     { "cvtpi2pd", { XM, EMCq } },
3729     { "cvtsi2sd%LQ", { XM, Ev } },
3730   },
3731
3732   /* PREFIX_0F2B */
3733   {
3734     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3735     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3736     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3737     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3738   },
3739
3740   /* PREFIX_0F2C */
3741   {
3742     { "cvttps2pi", { MXC, EXq } },
3743     { "cvttss2siY", { Gv, EXd } },
3744     { "cvttpd2pi", { MXC, EXx } },
3745     { "cvttsd2siY", { Gv, EXq } },
3746   },
3747
3748   /* PREFIX_0F2D */
3749   {
3750     { "cvtps2pi", { MXC, EXq } },
3751     { "cvtss2siY", { Gv, EXd } },
3752     { "cvtpd2pi", { MXC, EXx } },
3753     { "cvtsd2siY", { Gv, EXq } },
3754   },
3755
3756   /* PREFIX_0F2E */
3757   {
3758     { "ucomiss",{ XM, EXd } },
3759     { Bad_Opcode },
3760     { "ucomisd",{ XM, EXq } },
3761   },
3762
3763   /* PREFIX_0F2F */
3764   {
3765     { "comiss", { XM, EXd } },
3766     { Bad_Opcode },
3767     { "comisd", { XM, EXq } },
3768   },
3769
3770   /* PREFIX_0F51 */
3771   {
3772     { "sqrtps", { XM, EXx } },
3773     { "sqrtss", { XM, EXd } },
3774     { "sqrtpd", { XM, EXx } },
3775     { "sqrtsd", { XM, EXq } },
3776   },
3777
3778   /* PREFIX_0F52 */
3779   {
3780     { "rsqrtps",{ XM, EXx } },
3781     { "rsqrtss",{ XM, EXd } },
3782   },
3783
3784   /* PREFIX_0F53 */
3785   {
3786     { "rcpps",  { XM, EXx } },
3787     { "rcpss",  { XM, EXd } },
3788   },
3789
3790   /* PREFIX_0F58 */
3791   {
3792     { "addps", { XM, EXx } },
3793     { "addss", { XM, EXd } },
3794     { "addpd", { XM, EXx } },
3795     { "addsd", { XM, EXq } },
3796   },
3797
3798   /* PREFIX_0F59 */
3799   {
3800     { "mulps",  { XM, EXx } },
3801     { "mulss",  { XM, EXd } },
3802     { "mulpd",  { XM, EXx } },
3803     { "mulsd",  { XM, EXq } },
3804   },
3805
3806   /* PREFIX_0F5A */
3807   {
3808     { "cvtps2pd", { XM, EXq } },
3809     { "cvtss2sd", { XM, EXd } },
3810     { "cvtpd2ps", { XM, EXx } },
3811     { "cvtsd2ss", { XM, EXq } },
3812   },
3813
3814   /* PREFIX_0F5B */
3815   {
3816     { "cvtdq2ps", { XM, EXx } },
3817     { "cvttps2dq", { XM, EXx } },
3818     { "cvtps2dq", { XM, EXx } },
3819   },
3820
3821   /* PREFIX_0F5C */
3822   {
3823     { "subps",  { XM, EXx } },
3824     { "subss",  { XM, EXd } },
3825     { "subpd",  { XM, EXx } },
3826     { "subsd",  { XM, EXq } },
3827   },
3828
3829   /* PREFIX_0F5D */
3830   {
3831     { "minps",  { XM, EXx } },
3832     { "minss",  { XM, EXd } },
3833     { "minpd",  { XM, EXx } },
3834     { "minsd",  { XM, EXq } },
3835   },
3836
3837   /* PREFIX_0F5E */
3838   {
3839     { "divps",  { XM, EXx } },
3840     { "divss",  { XM, EXd } },
3841     { "divpd",  { XM, EXx } },
3842     { "divsd",  { XM, EXq } },
3843   },
3844
3845   /* PREFIX_0F5F */
3846   {
3847     { "maxps",  { XM, EXx } },
3848     { "maxss",  { XM, EXd } },
3849     { "maxpd",  { XM, EXx } },
3850     { "maxsd",  { XM, EXq } },
3851   },
3852
3853   /* PREFIX_0F60 */
3854   {
3855     { "punpcklbw",{ MX, EMd } },
3856     { Bad_Opcode },
3857     { "punpcklbw",{ MX, EMx } },
3858   },
3859
3860   /* PREFIX_0F61 */
3861   {
3862     { "punpcklwd",{ MX, EMd } },
3863     { Bad_Opcode },
3864     { "punpcklwd",{ MX, EMx } },
3865   },
3866
3867   /* PREFIX_0F62 */
3868   {
3869     { "punpckldq",{ MX, EMd } },
3870     { Bad_Opcode },
3871     { "punpckldq",{ MX, EMx } },
3872   },
3873
3874   /* PREFIX_0F6C */
3875   {
3876     { Bad_Opcode },
3877     { Bad_Opcode },
3878     { "punpcklqdq", { XM, EXx } },
3879   },
3880
3881   /* PREFIX_0F6D */
3882   {
3883     { Bad_Opcode },
3884     { Bad_Opcode },
3885     { "punpckhqdq", { XM, EXx } },
3886   },
3887
3888   /* PREFIX_0F6F */
3889   {
3890     { "movq",   { MX, EM } },
3891     { "movdqu", { XM, EXx } },
3892     { "movdqa", { XM, EXx } },
3893   },
3894
3895   /* PREFIX_0F70 */
3896   {
3897     { "pshufw", { MX, EM, Ib } },
3898     { "pshufhw",{ XM, EXx, Ib } },
3899     { "pshufd", { XM, EXx, Ib } },
3900     { "pshuflw",{ XM, EXx, Ib } },
3901   },
3902
3903   /* PREFIX_0F73_REG_3 */
3904   {
3905     { Bad_Opcode },
3906     { Bad_Opcode },
3907     { "psrldq", { XS, Ib } },
3908   },
3909
3910   /* PREFIX_0F73_REG_7 */
3911   {
3912     { Bad_Opcode },
3913     { Bad_Opcode },
3914     { "pslldq", { XS, Ib } },
3915   },
3916
3917   /* PREFIX_0F78 */
3918   {
3919     {"vmread",  { Em, Gm } },
3920     { Bad_Opcode },
3921     {"extrq",   { XS, Ib, Ib } },
3922     {"insertq", { XM, XS, Ib, Ib } },
3923   },
3924
3925   /* PREFIX_0F79 */
3926   {
3927     {"vmwrite", { Gm, Em } },
3928     { Bad_Opcode },
3929     {"extrq",   { XM, XS } },
3930     {"insertq", { XM, XS } },
3931   },
3932
3933   /* PREFIX_0F7C */
3934   {
3935     { Bad_Opcode },
3936     { Bad_Opcode },
3937     { "haddpd", { XM, EXx } },
3938     { "haddps", { XM, EXx } },
3939   },
3940
3941   /* PREFIX_0F7D */
3942   {
3943     { Bad_Opcode },
3944     { Bad_Opcode },
3945     { "hsubpd", { XM, EXx } },
3946     { "hsubps", { XM, EXx } },
3947   },
3948
3949   /* PREFIX_0F7E */
3950   {
3951     { "movK",   { Edq, MX } },
3952     { "movq",   { XM, EXq } },
3953     { "movK",   { Edq, XM } },
3954   },
3955
3956   /* PREFIX_0F7F */
3957   {
3958     { "movq",   { EMS, MX } },
3959     { "movdqu", { EXxS, XM } },
3960     { "movdqa", { EXxS, XM } },
3961   },
3962
3963   /* PREFIX_0FAE_REG_0 */
3964   {
3965     { Bad_Opcode },
3966     { "rdfsbase", { Ev } },
3967   },
3968
3969   /* PREFIX_0FAE_REG_1 */
3970   {
3971     { Bad_Opcode },
3972     { "rdgsbase", { Ev } },
3973   },
3974
3975   /* PREFIX_0FAE_REG_2 */
3976   {
3977     { Bad_Opcode },
3978     { "wrfsbase", { Ev } },
3979   },
3980
3981   /* PREFIX_0FAE_REG_3 */
3982   {
3983     { Bad_Opcode },
3984     { "wrgsbase", { Ev } },
3985   },
3986
3987   /* PREFIX_0FAE_REG_6 */
3988   {
3989     { "xsaveopt",      { FXSAVE } },
3990     { Bad_Opcode },
3991     { "clwb",   { Mb } },
3992   },
3993
3994   /* PREFIX_0FAE_REG_7 */
3995   {
3996     { "clflush",        { Mb } },
3997     { Bad_Opcode },
3998     { "clflushopt",     { Mb } },
3999   },
4000
4001   /* PREFIX_RM_0_0FAE_REG_7 */
4002   {
4003     { "sfence",         { Skip_MODRM } },
4004     { Bad_Opcode },
4005     { "pcommit",                { Skip_MODRM } },
4006   },
4007
4008   /* PREFIX_0FB8 */
4009   {
4010     { Bad_Opcode },
4011     { "popcntS", { Gv, Ev } },
4012   },
4013
4014   /* PREFIX_0FBC */
4015   {
4016     { "bsfS",   { Gv, Ev } },
4017     { "tzcntS", { Gv, Ev } },
4018     { "bsfS",   { Gv, Ev } },
4019   },
4020
4021   /* PREFIX_0FBD */
4022   {
4023     { "bsrS",   { Gv, Ev } },
4024     { "lzcntS", { Gv, Ev } },
4025     { "bsrS",   { Gv, Ev } },
4026   },
4027
4028   /* PREFIX_0FC2 */
4029   {
4030     { "cmpps",  { XM, EXx, CMP } },
4031     { "cmpss",  { XM, EXd, CMP } },
4032     { "cmppd",  { XM, EXx, CMP } },
4033     { "cmpsd",  { XM, EXq, CMP } },
4034   },
4035
4036   /* PREFIX_0FC3 */
4037   {
4038     { "movntiS", { Ma, Gv } },
4039   },
4040
4041   /* PREFIX_0FC7_REG_6 */
4042   {
4043     { "vmptrld",{ Mq } },
4044     { "vmxon",  { Mq } },
4045     { "vmclear",{ Mq } },
4046   },
4047
4048   /* PREFIX_0FD0 */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { "addsubpd", { XM, EXx } },
4053     { "addsubps", { XM, EXx } },
4054   },
4055
4056   /* PREFIX_0FD6 */
4057   {
4058     { Bad_Opcode },
4059     { "movq2dq",{ XM, MS } },
4060     { "movq",   { EXqS, XM } },
4061     { "movdq2q",{ MX, XS } },
4062   },
4063
4064   /* PREFIX_0FE6 */
4065   {
4066     { Bad_Opcode },
4067     { "cvtdq2pd", { XM, EXq } },
4068     { "cvttpd2dq", { XM, EXx } },
4069     { "cvtpd2dq", { XM, EXx } },
4070   },
4071
4072   /* PREFIX_0FE7 */
4073   {
4074     { "movntq", { Mq, MX } },
4075     { Bad_Opcode },
4076     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4077   },
4078
4079   /* PREFIX_0FF0 */
4080   {
4081     { Bad_Opcode },
4082     { Bad_Opcode },
4083     { Bad_Opcode },
4084     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4085   },
4086
4087   /* PREFIX_0FF7 */
4088   {
4089     { "maskmovq", { MX, MS } },
4090     { Bad_Opcode },
4091     { "maskmovdqu", { XM, XS } },
4092   },
4093
4094   /* PREFIX_0F3810 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { "pblendvb", { XM, EXx, XMM0 } },
4099   },
4100
4101   /* PREFIX_0F3814 */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { "blendvps", { XM, EXx, XMM0 } },
4106   },
4107
4108   /* PREFIX_0F3815 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { "blendvpd", { XM, EXx, XMM0 } },
4113   },
4114
4115   /* PREFIX_0F3817 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { "ptest",  { XM, EXx } },
4120   },
4121
4122   /* PREFIX_0F3820 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "pmovsxbw", { XM, EXq } },
4127   },
4128
4129   /* PREFIX_0F3821 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { "pmovsxbd", { XM, EXd } },
4134   },
4135
4136   /* PREFIX_0F3822 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "pmovsxbq", { XM, EXw } },
4141   },
4142
4143   /* PREFIX_0F3823 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "pmovsxwd", { XM, EXq } },
4148   },
4149
4150   /* PREFIX_0F3824 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "pmovsxwq", { XM, EXd } },
4155   },
4156
4157   /* PREFIX_0F3825 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "pmovsxdq", { XM, EXq } },
4162   },
4163
4164   /* PREFIX_0F3828 */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "pmuldq", { XM, EXx } },
4169   },
4170
4171   /* PREFIX_0F3829 */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { "pcmpeqq", { XM, EXx } },
4176   },
4177
4178   /* PREFIX_0F382A */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4183   },
4184
4185   /* PREFIX_0F382B */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "packusdw", { XM, EXx } },
4190   },
4191
4192   /* PREFIX_0F3830 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "pmovzxbw", { XM, EXq } },
4197   },
4198
4199   /* PREFIX_0F3831 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "pmovzxbd", { XM, EXd } },
4204   },
4205
4206   /* PREFIX_0F3832 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "pmovzxbq", { XM, EXw } },
4211   },
4212
4213   /* PREFIX_0F3833 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "pmovzxwd", { XM, EXq } },
4218   },
4219
4220   /* PREFIX_0F3834 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { "pmovzxwq", { XM, EXd } },
4225   },
4226
4227   /* PREFIX_0F3835 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "pmovzxdq", { XM, EXq } },
4232   },
4233
4234   /* PREFIX_0F3837 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "pcmpgtq", { XM, EXx } },
4239   },
4240
4241   /* PREFIX_0F3838 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pminsb", { XM, EXx } },
4246   },
4247
4248   /* PREFIX_0F3839 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pminsd", { XM, EXx } },
4253   },
4254
4255   /* PREFIX_0F383A */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pminuw", { XM, EXx } },
4260   },
4261
4262   /* PREFIX_0F383B */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pminud", { XM, EXx } },
4267   },
4268
4269   /* PREFIX_0F383C */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "pmaxsb", { XM, EXx } },
4274   },
4275
4276   /* PREFIX_0F383D */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "pmaxsd", { XM, EXx } },
4281   },
4282
4283   /* PREFIX_0F383E */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "pmaxuw", { XM, EXx } },
4288   },
4289
4290   /* PREFIX_0F383F */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "pmaxud", { XM, EXx } },
4295   },
4296
4297   /* PREFIX_0F3840 */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "pmulld", { XM, EXx } },
4302   },
4303
4304   /* PREFIX_0F3841 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "phminposuw", { XM, EXx } },
4309   },
4310
4311   /* PREFIX_0F3880 */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "invept", { Gm, Mo } },
4316   },
4317
4318   /* PREFIX_0F3881 */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "invvpid", { Gm, Mo } },
4323   },
4324
4325   /* PREFIX_0F3882 */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { "invpcid", { Gm, M } },
4330   },
4331
4332   /* PREFIX_0F38C8 */
4333   {
4334     { "sha1nexte", { XM, EXxmm } },
4335   },
4336
4337   /* PREFIX_0F38C9 */
4338   {
4339     { "sha1msg1", { XM, EXxmm } },
4340   },
4341
4342   /* PREFIX_0F38CA */
4343   {
4344     { "sha1msg2", { XM, EXxmm } },
4345   },
4346
4347   /* PREFIX_0F38CB */
4348   {
4349     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4350   },
4351
4352   /* PREFIX_0F38CC */
4353   {
4354     { "sha256msg1", { XM, EXxmm } },
4355   },
4356
4357   /* PREFIX_0F38CD */
4358   {
4359     { "sha256msg2", { XM, EXxmm } },
4360   },
4361
4362   /* PREFIX_0F38DB */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { "aesimc", { XM, EXx } },
4367   },
4368
4369   /* PREFIX_0F38DC */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { "aesenc", { XM, EXx } },
4374   },
4375
4376   /* PREFIX_0F38DD */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { "aesenclast", { XM, EXx } },
4381   },
4382
4383   /* PREFIX_0F38DE */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { "aesdec", { XM, EXx } },
4388   },
4389
4390   /* PREFIX_0F38DF */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { "aesdeclast", { XM, EXx } },
4395   },
4396
4397   /* PREFIX_0F38F0 */
4398   {
4399     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4400     { Bad_Opcode },
4401     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4402     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4403   },
4404
4405   /* PREFIX_0F38F1 */
4406   {
4407     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4408     { Bad_Opcode },
4409     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4410     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4411   },
4412
4413   /* PREFIX_0F38F6 */
4414   {
4415     { Bad_Opcode },
4416     { "adoxS",  { Gdq, Edq} },
4417     { "adcxS",  { Gdq, Edq} },
4418     { Bad_Opcode },
4419   },
4420
4421   /* PREFIX_0F3A08 */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { "roundps", { XM, EXx, Ib } },
4426   },
4427
4428   /* PREFIX_0F3A09 */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { "roundpd", { XM, EXx, Ib } },
4433   },
4434
4435   /* PREFIX_0F3A0A */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { "roundss", { XM, EXd, Ib } },
4440   },
4441
4442   /* PREFIX_0F3A0B */
4443   {
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { "roundsd", { XM, EXq, Ib } },
4447   },
4448
4449   /* PREFIX_0F3A0C */
4450   {
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { "blendps", { XM, EXx, Ib } },
4454   },
4455
4456   /* PREFIX_0F3A0D */
4457   {
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { "blendpd", { XM, EXx, Ib } },
4461   },
4462
4463   /* PREFIX_0F3A0E */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { "pblendw", { XM, EXx, Ib } },
4468   },
4469
4470   /* PREFIX_0F3A14 */
4471   {
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { "pextrb", { Edqb, XM, Ib } },
4475   },
4476
4477   /* PREFIX_0F3A15 */
4478   {
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { "pextrw", { Edqw, XM, Ib } },
4482   },
4483
4484   /* PREFIX_0F3A16 */
4485   {
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { "pextrK", { Edq, XM, Ib } },
4489   },
4490
4491   /* PREFIX_0F3A17 */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { "extractps", { Edqd, XM, Ib } },
4496   },
4497
4498   /* PREFIX_0F3A20 */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { "pinsrb", { XM, Edqb, Ib } },
4503   },
4504
4505   /* PREFIX_0F3A21 */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { "insertps", { XM, EXd, Ib } },
4510   },
4511
4512   /* PREFIX_0F3A22 */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { "pinsrK", { XM, Edq, Ib } },
4517   },
4518
4519   /* PREFIX_0F3A40 */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "dpps",   { XM, EXx, Ib } },
4524   },
4525
4526   /* PREFIX_0F3A41 */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "dppd",   { XM, EXx, Ib } },
4531   },
4532
4533   /* PREFIX_0F3A42 */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "mpsadbw", { XM, EXx, Ib } },
4538   },
4539
4540   /* PREFIX_0F3A44 */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "pclmulqdq", { XM, EXx, PCLMUL } },
4545   },
4546
4547   /* PREFIX_0F3A60 */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "pcmpestrm", { XM, EXx, Ib } },
4552   },
4553
4554   /* PREFIX_0F3A61 */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { "pcmpestri", { XM, EXx, Ib } },
4559   },
4560
4561   /* PREFIX_0F3A62 */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { "pcmpistrm", { XM, EXx, Ib } },
4566   },
4567
4568   /* PREFIX_0F3A63 */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { "pcmpistri", { XM, EXx, Ib } },
4573   },
4574
4575   /* PREFIX_0F3ACC */
4576   {
4577     { "sha1rnds4", { XM, EXxmm, Ib } },
4578   },
4579
4580   /* PREFIX_0F3ADF */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "aeskeygenassist", { XM, EXx, Ib } },
4585   },
4586
4587   /* PREFIX_VEX_0F10 */
4588   {
4589     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4590     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4591     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4592     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4593   },
4594
4595   /* PREFIX_VEX_0F11 */
4596   {
4597     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4598     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4599     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4600     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4601   },
4602
4603   /* PREFIX_VEX_0F12 */
4604   {
4605     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4606     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4607     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4608     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4609   },
4610
4611   /* PREFIX_VEX_0F16 */
4612   {
4613     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4614     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4615     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4616   },
4617
4618   /* PREFIX_VEX_0F2A */
4619   {
4620     { Bad_Opcode },
4621     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4622     { Bad_Opcode },
4623     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4624   },
4625
4626   /* PREFIX_VEX_0F2C */
4627   {
4628     { Bad_Opcode },
4629     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4630     { Bad_Opcode },
4631     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4632   },
4633
4634   /* PREFIX_VEX_0F2D */
4635   {
4636     { Bad_Opcode },
4637     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4638     { Bad_Opcode },
4639     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4640   },
4641
4642   /* PREFIX_VEX_0F2E */
4643   {
4644     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4645     { Bad_Opcode },
4646     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4647   },
4648
4649   /* PREFIX_VEX_0F2F */
4650   {
4651     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4652     { Bad_Opcode },
4653     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4654   },
4655
4656   /* PREFIX_VEX_0F41 */
4657   {
4658     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4659     { Bad_Opcode },
4660     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4661   },
4662
4663   /* PREFIX_VEX_0F42 */
4664   {
4665     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4666     { Bad_Opcode },
4667     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4668   },
4669
4670   /* PREFIX_VEX_0F44 */
4671   {
4672     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4673     { Bad_Opcode },
4674     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4675   },
4676
4677   /* PREFIX_VEX_0F45 */
4678   {
4679     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4680     { Bad_Opcode },
4681     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4682   },
4683
4684   /* PREFIX_VEX_0F46 */
4685   {
4686     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4687     { Bad_Opcode },
4688     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4689   },
4690
4691   /* PREFIX_VEX_0F47 */
4692   {
4693     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4694     { Bad_Opcode },
4695     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4696   },
4697
4698   /* PREFIX_VEX_0F4A */
4699   {
4700     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4701     { Bad_Opcode },
4702     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4703   },
4704
4705   /* PREFIX_VEX_0F4B */
4706   {
4707     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4708     { Bad_Opcode },
4709     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4710   },
4711
4712   /* PREFIX_VEX_0F51 */
4713   {
4714     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4715     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4716     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4717     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4718   },
4719
4720   /* PREFIX_VEX_0F52 */
4721   {
4722     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4723     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4724   },
4725
4726   /* PREFIX_VEX_0F53 */
4727   {
4728     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4729     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4730   },
4731
4732   /* PREFIX_VEX_0F58 */
4733   {
4734     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4735     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4736     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4737     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4738   },
4739
4740   /* PREFIX_VEX_0F59 */
4741   {
4742     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4743     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4744     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4745     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4746   },
4747
4748   /* PREFIX_VEX_0F5A */
4749   {
4750     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4751     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4752     { "vcvtpd2ps%XY", { XMM, EXx } },
4753     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4754   },
4755
4756   /* PREFIX_VEX_0F5B */
4757   {
4758     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4759     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4760     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4761   },
4762
4763   /* PREFIX_VEX_0F5C */
4764   {
4765     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4766     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4767     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4768     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4769   },
4770
4771   /* PREFIX_VEX_0F5D */
4772   {
4773     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4774     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4775     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4776     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4777   },
4778
4779   /* PREFIX_VEX_0F5E */
4780   {
4781     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4782     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4783     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4784     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4785   },
4786
4787   /* PREFIX_VEX_0F5F */
4788   {
4789     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4790     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4791     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4792     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4793   },
4794
4795   /* PREFIX_VEX_0F60 */
4796   {
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4800   },
4801
4802   /* PREFIX_VEX_0F61 */
4803   {
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4807   },
4808
4809   /* PREFIX_VEX_0F62 */
4810   {
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4814   },
4815
4816   /* PREFIX_VEX_0F63 */
4817   {
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4821   },
4822
4823   /* PREFIX_VEX_0F64 */
4824   {
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4828   },
4829
4830   /* PREFIX_VEX_0F65 */
4831   {
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4835   },
4836
4837   /* PREFIX_VEX_0F66 */
4838   {
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4842   },
4843
4844   /* PREFIX_VEX_0F67 */
4845   {
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4849   },
4850
4851   /* PREFIX_VEX_0F68 */
4852   {
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4856   },
4857
4858   /* PREFIX_VEX_0F69 */
4859   {
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4863   },
4864
4865   /* PREFIX_VEX_0F6A */
4866   {
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4870   },
4871
4872   /* PREFIX_VEX_0F6B */
4873   {
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4877   },
4878
4879   /* PREFIX_VEX_0F6C */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4884   },
4885
4886   /* PREFIX_VEX_0F6D */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4891   },
4892
4893   /* PREFIX_VEX_0F6E */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4898   },
4899
4900   /* PREFIX_VEX_0F6F */
4901   {
4902     { Bad_Opcode },
4903     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4904     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4905   },
4906
4907   /* PREFIX_VEX_0F70 */
4908   {
4909     { Bad_Opcode },
4910     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4911     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4912     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4913   },
4914
4915   /* PREFIX_VEX_0F71_REG_2 */
4916   {
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4920   },
4921
4922   /* PREFIX_VEX_0F71_REG_4 */
4923   {
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4927   },
4928
4929   /* PREFIX_VEX_0F71_REG_6 */
4930   {
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4934   },
4935
4936   /* PREFIX_VEX_0F72_REG_2 */
4937   {
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4941   },
4942
4943   /* PREFIX_VEX_0F72_REG_4 */
4944   {
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4948   },
4949
4950   /* PREFIX_VEX_0F72_REG_6 */
4951   {
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4955   },
4956
4957   /* PREFIX_VEX_0F73_REG_2 */
4958   {
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4962   },
4963
4964   /* PREFIX_VEX_0F73_REG_3 */
4965   {
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4969   },
4970
4971   /* PREFIX_VEX_0F73_REG_6 */
4972   {
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4976   },
4977
4978   /* PREFIX_VEX_0F73_REG_7 */
4979   {
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4983   },
4984
4985   /* PREFIX_VEX_0F74 */
4986   {
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4990   },
4991
4992   /* PREFIX_VEX_0F75 */
4993   {
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4997   },
4998
4999   /* PREFIX_VEX_0F76 */
5000   {
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5004   },
5005
5006   /* PREFIX_VEX_0F77 */
5007   {
5008     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5009   },
5010
5011   /* PREFIX_VEX_0F7C */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5016     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5017   },
5018
5019   /* PREFIX_VEX_0F7D */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5024     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5025   },
5026
5027   /* PREFIX_VEX_0F7E */
5028   {
5029     { Bad_Opcode },
5030     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5031     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5032   },
5033
5034   /* PREFIX_VEX_0F7F */
5035   {
5036     { Bad_Opcode },
5037     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5038     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5039   },
5040
5041   /* PREFIX_VEX_0F90 */
5042   {
5043     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5044     { Bad_Opcode },
5045     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5046   },
5047
5048   /* PREFIX_VEX_0F91 */
5049   {
5050     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5051     { Bad_Opcode },
5052     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5053   },
5054
5055   /* PREFIX_VEX_0F92 */
5056   {
5057     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5058     { Bad_Opcode },
5059     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5060     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5061   },
5062
5063   /* PREFIX_VEX_0F93 */
5064   {
5065     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5066     { Bad_Opcode },
5067     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5068     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5069   },
5070
5071   /* PREFIX_VEX_0F98 */
5072   {
5073     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5074     { Bad_Opcode },
5075     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5076   },
5077
5078   /* PREFIX_VEX_0F99 */
5079   {
5080     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5081     { Bad_Opcode },
5082     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5083   },
5084
5085   /* PREFIX_VEX_0FC2 */
5086   {
5087     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5088     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5089     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5090     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5091   },
5092
5093   /* PREFIX_VEX_0FC4 */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5098   },
5099
5100   /* PREFIX_VEX_0FC5 */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0FD0 */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5112     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5113   },
5114
5115   /* PREFIX_VEX_0FD1 */
5116   {
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5120   },
5121
5122   /* PREFIX_VEX_0FD2 */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5127   },
5128
5129   /* PREFIX_VEX_0FD3 */
5130   {
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5134   },
5135
5136   /* PREFIX_VEX_0FD4 */
5137   {
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5141   },
5142
5143   /* PREFIX_VEX_0FD5 */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0FD6 */
5151   {
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0FD7 */
5158   {
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5162   },
5163
5164   /* PREFIX_VEX_0FD8 */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5169   },
5170
5171   /* PREFIX_VEX_0FD9 */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5176   },
5177
5178   /* PREFIX_VEX_0FDA */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5183   },
5184
5185   /* PREFIX_VEX_0FDB */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5190   },
5191
5192   /* PREFIX_VEX_0FDC */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5197   },
5198
5199   /* PREFIX_VEX_0FDD */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5204   },
5205
5206   /* PREFIX_VEX_0FDE */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5211   },
5212
5213   /* PREFIX_VEX_0FDF */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5218   },
5219
5220   /* PREFIX_VEX_0FE0 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5225   },
5226
5227   /* PREFIX_VEX_0FE1 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5232   },
5233
5234   /* PREFIX_VEX_0FE2 */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5239   },
5240
5241   /* PREFIX_VEX_0FE3 */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5246   },
5247
5248   /* PREFIX_VEX_0FE4 */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5253   },
5254
5255   /* PREFIX_VEX_0FE5 */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5260   },
5261
5262   /* PREFIX_VEX_0FE6 */
5263   {
5264     { Bad_Opcode },
5265     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5266     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5267     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5268   },
5269
5270   /* PREFIX_VEX_0FE7 */
5271   {
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5275   },
5276
5277   /* PREFIX_VEX_0FE8 */
5278   {
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5282   },
5283
5284   /* PREFIX_VEX_0FE9 */
5285   {
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5289   },
5290
5291   /* PREFIX_VEX_0FEA */
5292   {
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5296   },
5297
5298   /* PREFIX_VEX_0FEB */
5299   {
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5303   },
5304
5305   /* PREFIX_VEX_0FEC */
5306   {
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5310   },
5311
5312   /* PREFIX_VEX_0FED */
5313   {
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5317   },
5318
5319   /* PREFIX_VEX_0FEE */
5320   {
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5324   },
5325
5326   /* PREFIX_VEX_0FEF */
5327   {
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5331   },
5332
5333   /* PREFIX_VEX_0FF0 */
5334   {
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5339   },
5340
5341   /* PREFIX_VEX_0FF1 */
5342   {
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5346   },
5347
5348   /* PREFIX_VEX_0FF2 */
5349   {
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5353   },
5354
5355   /* PREFIX_VEX_0FF3 */
5356   {
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5360   },
5361
5362   /* PREFIX_VEX_0FF4 */
5363   {
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5367   },
5368
5369   /* PREFIX_VEX_0FF5 */
5370   {
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5374   },
5375
5376   /* PREFIX_VEX_0FF6 */
5377   {
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5381   },
5382
5383   /* PREFIX_VEX_0FF7 */
5384   {
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5388   },
5389
5390   /* PREFIX_VEX_0FF8 */
5391   {
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5395   },
5396
5397   /* PREFIX_VEX_0FF9 */
5398   {
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5402   },
5403
5404   /* PREFIX_VEX_0FFA */
5405   {
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5409   },
5410
5411   /* PREFIX_VEX_0FFB */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5416   },
5417
5418   /* PREFIX_VEX_0FFC */
5419   {
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5423   },
5424
5425   /* PREFIX_VEX_0FFD */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5430   },
5431
5432   /* PREFIX_VEX_0FFE */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5437   },
5438
5439   /* PREFIX_VEX_0F3800 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5444   },
5445
5446   /* PREFIX_VEX_0F3801 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5451   },
5452
5453   /* PREFIX_VEX_0F3802 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5458   },
5459
5460   /* PREFIX_VEX_0F3803 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5465   },
5466
5467   /* PREFIX_VEX_0F3804 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5472   },
5473
5474   /* PREFIX_VEX_0F3805 */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5479   },
5480
5481   /* PREFIX_VEX_0F3806 */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5486   },
5487
5488   /* PREFIX_VEX_0F3807 */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5493   },
5494
5495   /* PREFIX_VEX_0F3808 */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5500   },
5501
5502   /* PREFIX_VEX_0F3809 */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5507   },
5508
5509   /* PREFIX_VEX_0F380A */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5514   },
5515
5516   /* PREFIX_VEX_0F380B */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0F380C */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0F380D */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5535   },
5536
5537   /* PREFIX_VEX_0F380E */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5542   },
5543
5544   /* PREFIX_VEX_0F380F */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5549   },
5550
5551   /* PREFIX_VEX_0F3813 */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { "vcvtph2ps", { XM, EXxmmq } },
5556   },
5557
5558   /* PREFIX_VEX_0F3816 */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5563   },
5564
5565   /* PREFIX_VEX_0F3817 */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5570   },
5571
5572   /* PREFIX_VEX_0F3818 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5577   },
5578
5579   /* PREFIX_VEX_0F3819 */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5584   },
5585
5586   /* PREFIX_VEX_0F381A */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5591   },
5592
5593   /* PREFIX_VEX_0F381C */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5598   },
5599
5600   /* PREFIX_VEX_0F381D */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5605   },
5606
5607   /* PREFIX_VEX_0F381E */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0F3820 */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5619   },
5620
5621   /* PREFIX_VEX_0F3821 */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5626   },
5627
5628   /* PREFIX_VEX_0F3822 */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5633   },
5634
5635   /* PREFIX_VEX_0F3823 */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5640   },
5641
5642   /* PREFIX_VEX_0F3824 */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5647   },
5648
5649   /* PREFIX_VEX_0F3825 */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5654   },
5655
5656   /* PREFIX_VEX_0F3828 */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5661   },
5662
5663   /* PREFIX_VEX_0F3829 */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5668   },
5669
5670   /* PREFIX_VEX_0F382A */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5675   },
5676
5677   /* PREFIX_VEX_0F382B */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5682   },
5683
5684   /* PREFIX_VEX_0F382C */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5689   },
5690
5691   /* PREFIX_VEX_0F382D */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5696   },
5697
5698   /* PREFIX_VEX_0F382E */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5703   },
5704
5705   /* PREFIX_VEX_0F382F */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5710   },
5711
5712   /* PREFIX_VEX_0F3830 */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5717   },
5718
5719   /* PREFIX_VEX_0F3831 */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5724   },
5725
5726   /* PREFIX_VEX_0F3832 */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5731   },
5732
5733   /* PREFIX_VEX_0F3833 */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5738   },
5739
5740   /* PREFIX_VEX_0F3834 */
5741   {
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5745   },
5746
5747   /* PREFIX_VEX_0F3835 */
5748   {
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5752   },
5753
5754   /* PREFIX_VEX_0F3836 */
5755   {
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5759   },
5760
5761   /* PREFIX_VEX_0F3837 */
5762   {
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5766   },
5767
5768   /* PREFIX_VEX_0F3838 */
5769   {
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5773   },
5774
5775   /* PREFIX_VEX_0F3839 */
5776   {
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5780   },
5781
5782   /* PREFIX_VEX_0F383A */
5783   {
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5787   },
5788
5789   /* PREFIX_VEX_0F383B */
5790   {
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5794   },
5795
5796   /* PREFIX_VEX_0F383C */
5797   {
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5801   },
5802
5803   /* PREFIX_VEX_0F383D */
5804   {
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5808   },
5809
5810   /* PREFIX_VEX_0F383E */
5811   {
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5815   },
5816
5817   /* PREFIX_VEX_0F383F */
5818   {
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5822   },
5823
5824   /* PREFIX_VEX_0F3840 */
5825   {
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5829   },
5830
5831   /* PREFIX_VEX_0F3841 */
5832   {
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5836   },
5837
5838   /* PREFIX_VEX_0F3845 */
5839   {
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { "vpsrlv%LW", { XM, Vex, EXx } },
5843   },
5844
5845   /* PREFIX_VEX_0F3846 */
5846   {
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5850   },
5851
5852   /* PREFIX_VEX_0F3847 */
5853   {
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { "vpsllv%LW", { XM, Vex, EXx } },
5857   },
5858
5859   /* PREFIX_VEX_0F3858 */
5860   {
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5864   },
5865
5866   /* PREFIX_VEX_0F3859 */
5867   {
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5871   },
5872
5873   /* PREFIX_VEX_0F385A */
5874   {
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5878   },
5879
5880   /* PREFIX_VEX_0F3878 */
5881   {
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5885   },
5886
5887   /* PREFIX_VEX_0F3879 */
5888   {
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5892   },
5893
5894   /* PREFIX_VEX_0F388C */
5895   {
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5899   },
5900
5901   /* PREFIX_VEX_0F388E */
5902   {
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5906   },
5907
5908   /* PREFIX_VEX_0F3890 */
5909   {
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5913   },
5914
5915   /* PREFIX_VEX_0F3891 */
5916   {
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5920   },
5921
5922   /* PREFIX_VEX_0F3892 */
5923   {
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5927   },
5928
5929   /* PREFIX_VEX_0F3893 */
5930   {
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5934   },
5935
5936   /* PREFIX_VEX_0F3896 */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5941   },
5942
5943   /* PREFIX_VEX_0F3897 */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5948   },
5949
5950   /* PREFIX_VEX_0F3898 */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { "vfmadd132p%XW", { XM, Vex, EXx } },
5955   },
5956
5957   /* PREFIX_VEX_0F3899 */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5962   },
5963
5964   /* PREFIX_VEX_0F389A */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { "vfmsub132p%XW", { XM, Vex, EXx } },
5969   },
5970
5971   /* PREFIX_VEX_0F389B */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5976   },
5977
5978   /* PREFIX_VEX_0F389C */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5983   },
5984
5985   /* PREFIX_VEX_0F389D */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5990   },
5991
5992   /* PREFIX_VEX_0F389E */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5997   },
5998
5999   /* PREFIX_VEX_0F389F */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6004   },
6005
6006   /* PREFIX_VEX_0F38A6 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
6011     { Bad_Opcode },
6012   },
6013
6014   /* PREFIX_VEX_0F38A7 */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
6019   },
6020
6021   /* PREFIX_VEX_0F38A8 */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { "vfmadd213p%XW", { XM, Vex, EXx } },
6026   },
6027
6028   /* PREFIX_VEX_0F38A9 */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6033   },
6034
6035   /* PREFIX_VEX_0F38AA */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { "vfmsub213p%XW", { XM, Vex, EXx } },
6040   },
6041
6042   /* PREFIX_VEX_0F38AB */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6047   },
6048
6049   /* PREFIX_VEX_0F38AC */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { "vfnmadd213p%XW", { XM, Vex, EXx } },
6054   },
6055
6056   /* PREFIX_VEX_0F38AD */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6061   },
6062
6063   /* PREFIX_VEX_0F38AE */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { "vfnmsub213p%XW", { XM, Vex, EXx } },
6068   },
6069
6070   /* PREFIX_VEX_0F38AF */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6075   },
6076
6077   /* PREFIX_VEX_0F38B6 */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
6082   },
6083
6084   /* PREFIX_VEX_0F38B7 */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
6089   },
6090
6091   /* PREFIX_VEX_0F38B8 */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vfmadd231p%XW", { XM, Vex, EXx } },
6096   },
6097
6098   /* PREFIX_VEX_0F38B9 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6103   },
6104
6105   /* PREFIX_VEX_0F38BA */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfmsub231p%XW", { XM, Vex, EXx } },
6110   },
6111
6112   /* PREFIX_VEX_0F38BB */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6117   },
6118
6119   /* PREFIX_VEX_0F38BC */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfnmadd231p%XW", { XM, Vex, EXx } },
6124   },
6125
6126   /* PREFIX_VEX_0F38BD */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6131   },
6132
6133   /* PREFIX_VEX_0F38BE */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfnmsub231p%XW", { XM, Vex, EXx } },
6138   },
6139
6140   /* PREFIX_VEX_0F38BF */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6145   },
6146
6147   /* PREFIX_VEX_0F38DB */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6152   },
6153
6154   /* PREFIX_VEX_0F38DC */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6159   },
6160
6161   /* PREFIX_VEX_0F38DD */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6166   },
6167
6168   /* PREFIX_VEX_0F38DE */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6173   },
6174
6175   /* PREFIX_VEX_0F38DF */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6180   },
6181
6182   /* PREFIX_VEX_0F38F2 */
6183   {
6184     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6185   },
6186
6187   /* PREFIX_VEX_0F38F3_REG_1 */
6188   {
6189     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6190   },
6191
6192   /* PREFIX_VEX_0F38F3_REG_2 */
6193   {
6194     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6195   },
6196
6197   /* PREFIX_VEX_0F38F3_REG_3 */
6198   {
6199     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6200   },
6201
6202   /* PREFIX_VEX_0F38F5 */
6203   {
6204     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6205     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6206     { Bad_Opcode },
6207     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6208   },
6209
6210   /* PREFIX_VEX_0F38F6 */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6216   },
6217
6218   /* PREFIX_VEX_0F38F7 */
6219   {
6220     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6221     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6222     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6223     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6224   },
6225
6226   /* PREFIX_VEX_0F3A00 */
6227   {
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6231   },
6232
6233   /* PREFIX_VEX_0F3A01 */
6234   {
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6238   },
6239
6240   /* PREFIX_VEX_0F3A02 */
6241   {
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6245   },
6246
6247   /* PREFIX_VEX_0F3A04 */
6248   {
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6252   },
6253
6254   /* PREFIX_VEX_0F3A05 */
6255   {
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6259   },
6260
6261   /* PREFIX_VEX_0F3A06 */
6262   {
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6266   },
6267
6268   /* PREFIX_VEX_0F3A08 */
6269   {
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6273   },
6274
6275   /* PREFIX_VEX_0F3A09 */
6276   {
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6280   },
6281
6282   /* PREFIX_VEX_0F3A0A */
6283   {
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6287   },
6288
6289   /* PREFIX_VEX_0F3A0B */
6290   {
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6294   },
6295
6296   /* PREFIX_VEX_0F3A0C */
6297   {
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6301   },
6302
6303   /* PREFIX_VEX_0F3A0D */
6304   {
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6308   },
6309
6310   /* PREFIX_VEX_0F3A0E */
6311   {
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6315   },
6316
6317   /* PREFIX_VEX_0F3A0F */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A14 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A15 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A16 */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A17 */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6350   },
6351
6352   /* PREFIX_VEX_0F3A18 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6357   },
6358
6359   /* PREFIX_VEX_0F3A19 */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6364   },
6365
6366   /* PREFIX_VEX_0F3A1D */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6371   },
6372
6373   /* PREFIX_VEX_0F3A20 */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6378   },
6379
6380   /* PREFIX_VEX_0F3A21 */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6385   },
6386
6387   /* PREFIX_VEX_0F3A22 */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6392   },
6393
6394   /* PREFIX_VEX_0F3A30 */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6399   },
6400
6401   /* PREFIX_VEX_0F3A31 */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6406   },
6407
6408   /* PREFIX_VEX_0F3A32 */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6413   },
6414
6415   /* PREFIX_VEX_0F3A33 */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A38 */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3A39 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A40 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A41 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A42 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A44 */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6462   },
6463
6464   /* PREFIX_VEX_0F3A46 */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A48 */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A49 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A4A */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A4B */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A4C */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A5C */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6511   },
6512
6513   /* PREFIX_VEX_0F3A5D */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6518   },
6519
6520   /* PREFIX_VEX_0F3A5E */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6525   },
6526
6527   /* PREFIX_VEX_0F3A5F */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6532   },
6533
6534   /* PREFIX_VEX_0F3A60 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6539     { Bad_Opcode },
6540   },
6541
6542   /* PREFIX_VEX_0F3A61 */
6543   {
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6547   },
6548
6549   /* PREFIX_VEX_0F3A62 */
6550   {
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6554   },
6555
6556   /* PREFIX_VEX_0F3A63 */
6557   {
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6561   },
6562
6563   /* PREFIX_VEX_0F3A68 */
6564   {
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6568   },
6569
6570   /* PREFIX_VEX_0F3A69 */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6575   },
6576
6577   /* PREFIX_VEX_0F3A6A */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6582   },
6583
6584   /* PREFIX_VEX_0F3A6B */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A6C */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6596   },
6597
6598   /* PREFIX_VEX_0F3A6D */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6603   },
6604
6605   /* PREFIX_VEX_0F3A6E */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6610   },
6611
6612   /* PREFIX_VEX_0F3A6F */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6617   },
6618
6619   /* PREFIX_VEX_0F3A78 */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6624   },
6625
6626   /* PREFIX_VEX_0F3A79 */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6631   },
6632
6633   /* PREFIX_VEX_0F3A7A */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A7B */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A7C */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6652     { Bad_Opcode },
6653   },
6654
6655   /* PREFIX_VEX_0F3A7D */
6656   {
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6660   },
6661
6662   /* PREFIX_VEX_0F3A7E */
6663   {
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6667   },
6668
6669   /* PREFIX_VEX_0F3A7F */
6670   {
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6674   },
6675
6676   /* PREFIX_VEX_0F3ADF */
6677   {
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6681   },
6682
6683   /* PREFIX_VEX_0F3AF0 */
6684   {
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6689   },
6690
6691 #define NEED_PREFIX_TABLE
6692 #include "i386-dis-evex.h"
6693 #undef NEED_PREFIX_TABLE
6694 };
6695
6696 static const struct dis386 x86_64_table[][2] = {
6697   /* X86_64_06 */
6698   {
6699     { "pushP", { es } },
6700   },
6701
6702   /* X86_64_07 */
6703   {
6704     { "popP", { es } },
6705   },
6706
6707   /* X86_64_0D */
6708   {
6709     { "pushP", { cs } },
6710   },
6711
6712   /* X86_64_16 */
6713   {
6714     { "pushP", { ss } },
6715   },
6716
6717   /* X86_64_17 */
6718   {
6719     { "popP", { ss } },
6720   },
6721
6722   /* X86_64_1E */
6723   {
6724     { "pushP", { ds } },
6725   },
6726
6727   /* X86_64_1F */
6728   {
6729     { "popP", { ds } },
6730   },
6731
6732   /* X86_64_27 */
6733   {
6734     { "daa", { XX } },
6735   },
6736
6737   /* X86_64_2F */
6738   {
6739     { "das", { XX } },
6740   },
6741
6742   /* X86_64_37 */
6743   {
6744     { "aaa", { XX } },
6745   },
6746
6747   /* X86_64_3F */
6748   {
6749     { "aas", { XX } },
6750   },
6751
6752   /* X86_64_60 */
6753   {
6754     { "pushaP", { XX } },
6755   },
6756
6757   /* X86_64_61 */
6758   {
6759     { "popaP", { XX } },
6760   },
6761
6762   /* X86_64_62 */
6763   {
6764     { MOD_TABLE (MOD_62_32BIT) },
6765     { EVEX_TABLE (EVEX_0F) },
6766   },
6767
6768   /* X86_64_63 */
6769   {
6770     { "arpl", { Ew, Gw } },
6771     { "movs{lq|xd}", { Gv, Ed } },
6772   },
6773
6774   /* X86_64_6D */
6775   {
6776     { "ins{R|}", { Yzr, indirDX } },
6777     { "ins{G|}", { Yzr, indirDX } },
6778   },
6779
6780   /* X86_64_6F */
6781   {
6782     { "outs{R|}", { indirDXr, Xz } },
6783     { "outs{G|}", { indirDXr, Xz } },
6784   },
6785
6786   /* X86_64_9A */
6787   {
6788     { "Jcall{T|}", { Ap } },
6789   },
6790
6791   /* X86_64_C4 */
6792   {
6793     { MOD_TABLE (MOD_C4_32BIT) },
6794     { VEX_C4_TABLE (VEX_0F) },
6795   },
6796
6797   /* X86_64_C5 */
6798   {
6799     { MOD_TABLE (MOD_C5_32BIT) },
6800     { VEX_C5_TABLE (VEX_0F) },
6801   },
6802
6803   /* X86_64_CE */
6804   {
6805     { "into", { XX } },
6806   },
6807
6808   /* X86_64_D4 */
6809   {
6810     { "aam", { Ib } },
6811   },
6812
6813   /* X86_64_D5 */
6814   {
6815     { "aad", { Ib } },
6816   },
6817
6818   /* X86_64_EA */
6819   {
6820     { "Jjmp{T|}", { Ap } },
6821   },
6822
6823   /* X86_64_0F01_REG_0 */
6824   {
6825     { "sgdt{Q|IQ}", { M } },
6826     { "sgdt", { M } },
6827   },
6828
6829   /* X86_64_0F01_REG_1 */
6830   {
6831     { "sidt{Q|IQ}", { M } },
6832     { "sidt", { M } },
6833   },
6834
6835   /* X86_64_0F01_REG_2 */
6836   {
6837     { "lgdt{Q|Q}", { M } },
6838     { "lgdt", { M } },
6839   },
6840
6841   /* X86_64_0F01_REG_3 */
6842   {
6843     { "lidt{Q|Q}", { M } },
6844     { "lidt", { M } },
6845   },
6846 };
6847
6848 static const struct dis386 three_byte_table[][256] = {
6849
6850   /* THREE_BYTE_0F38 */
6851   {
6852     /* 00 */
6853     { "pshufb",         { MX, EM } },
6854     { "phaddw",         { MX, EM } },
6855     { "phaddd",         { MX, EM } },
6856     { "phaddsw",        { MX, EM } },
6857     { "pmaddubsw",      { MX, EM } },
6858     { "phsubw",         { MX, EM } },
6859     { "phsubd",         { MX, EM } },
6860     { "phsubsw",        { MX, EM } },
6861     /* 08 */
6862     { "psignb",         { MX, EM } },
6863     { "psignw",         { MX, EM } },
6864     { "psignd",         { MX, EM } },
6865     { "pmulhrsw",       { MX, EM } },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     /* 10 */
6871     { PREFIX_TABLE (PREFIX_0F3810) },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { PREFIX_TABLE (PREFIX_0F3814) },
6876     { PREFIX_TABLE (PREFIX_0F3815) },
6877     { Bad_Opcode },
6878     { PREFIX_TABLE (PREFIX_0F3817) },
6879     /* 18 */
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { "pabsb",          { MX, EM } },
6885     { "pabsw",          { MX, EM } },
6886     { "pabsd",          { MX, EM } },
6887     { Bad_Opcode },
6888     /* 20 */
6889     { PREFIX_TABLE (PREFIX_0F3820) },
6890     { PREFIX_TABLE (PREFIX_0F3821) },
6891     { PREFIX_TABLE (PREFIX_0F3822) },
6892     { PREFIX_TABLE (PREFIX_0F3823) },
6893     { PREFIX_TABLE (PREFIX_0F3824) },
6894     { PREFIX_TABLE (PREFIX_0F3825) },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     /* 28 */
6898     { PREFIX_TABLE (PREFIX_0F3828) },
6899     { PREFIX_TABLE (PREFIX_0F3829) },
6900     { PREFIX_TABLE (PREFIX_0F382A) },
6901     { PREFIX_TABLE (PREFIX_0F382B) },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     /* 30 */
6907     { PREFIX_TABLE (PREFIX_0F3830) },
6908     { PREFIX_TABLE (PREFIX_0F3831) },
6909     { PREFIX_TABLE (PREFIX_0F3832) },
6910     { PREFIX_TABLE (PREFIX_0F3833) },
6911     { PREFIX_TABLE (PREFIX_0F3834) },
6912     { PREFIX_TABLE (PREFIX_0F3835) },
6913     { Bad_Opcode },
6914     { PREFIX_TABLE (PREFIX_0F3837) },
6915     /* 38 */
6916     { PREFIX_TABLE (PREFIX_0F3838) },
6917     { PREFIX_TABLE (PREFIX_0F3839) },
6918     { PREFIX_TABLE (PREFIX_0F383A) },
6919     { PREFIX_TABLE (PREFIX_0F383B) },
6920     { PREFIX_TABLE (PREFIX_0F383C) },
6921     { PREFIX_TABLE (PREFIX_0F383D) },
6922     { PREFIX_TABLE (PREFIX_0F383E) },
6923     { PREFIX_TABLE (PREFIX_0F383F) },
6924     /* 40 */
6925     { PREFIX_TABLE (PREFIX_0F3840) },
6926     { PREFIX_TABLE (PREFIX_0F3841) },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     /* 48 */
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     /* 50 */
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     /* 58 */
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     /* 60 */
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     /* 68 */
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     /* 70 */
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     /* 78 */
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     /* 80 */
6997     { PREFIX_TABLE (PREFIX_0F3880) },
6998     { PREFIX_TABLE (PREFIX_0F3881) },
6999     { PREFIX_TABLE (PREFIX_0F3882) },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     /* 88 */
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     /* 90 */
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     /* 98 */
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     /* a0 */
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     /* a8 */
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     /* b0 */
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     /* b8 */
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     /* c0 */
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     /* c8 */
7078     { PREFIX_TABLE (PREFIX_0F38C8) },
7079     { PREFIX_TABLE (PREFIX_0F38C9) },
7080     { PREFIX_TABLE (PREFIX_0F38CA) },
7081     { PREFIX_TABLE (PREFIX_0F38CB) },
7082     { PREFIX_TABLE (PREFIX_0F38CC) },
7083     { PREFIX_TABLE (PREFIX_0F38CD) },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     /* d0 */
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     /* d8 */
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { PREFIX_TABLE (PREFIX_0F38DB) },
7100     { PREFIX_TABLE (PREFIX_0F38DC) },
7101     { PREFIX_TABLE (PREFIX_0F38DD) },
7102     { PREFIX_TABLE (PREFIX_0F38DE) },
7103     { PREFIX_TABLE (PREFIX_0F38DF) },
7104     /* e0 */
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     /* e8 */
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     /* f0 */
7123     { PREFIX_TABLE (PREFIX_0F38F0) },
7124     { PREFIX_TABLE (PREFIX_0F38F1) },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { PREFIX_TABLE (PREFIX_0F38F6) },
7130     { Bad_Opcode },
7131     /* f8 */
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140   },
7141   /* THREE_BYTE_0F3A */
7142   {
7143     /* 00 */
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     /* 08 */
7153     { PREFIX_TABLE (PREFIX_0F3A08) },
7154     { PREFIX_TABLE (PREFIX_0F3A09) },
7155     { PREFIX_TABLE (PREFIX_0F3A0A) },
7156     { PREFIX_TABLE (PREFIX_0F3A0B) },
7157     { PREFIX_TABLE (PREFIX_0F3A0C) },
7158     { PREFIX_TABLE (PREFIX_0F3A0D) },
7159     { PREFIX_TABLE (PREFIX_0F3A0E) },
7160     { "palignr",        { MX, EM, Ib } },
7161     /* 10 */
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { PREFIX_TABLE (PREFIX_0F3A14) },
7167     { PREFIX_TABLE (PREFIX_0F3A15) },
7168     { PREFIX_TABLE (PREFIX_0F3A16) },
7169     { PREFIX_TABLE (PREFIX_0F3A17) },
7170     /* 18 */
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     /* 20 */
7180     { PREFIX_TABLE (PREFIX_0F3A20) },
7181     { PREFIX_TABLE (PREFIX_0F3A21) },
7182     { PREFIX_TABLE (PREFIX_0F3A22) },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     /* 28 */
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     /* 30 */
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     /* 38 */
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     /* 40 */
7216     { PREFIX_TABLE (PREFIX_0F3A40) },
7217     { PREFIX_TABLE (PREFIX_0F3A41) },
7218     { PREFIX_TABLE (PREFIX_0F3A42) },
7219     { Bad_Opcode },
7220     { PREFIX_TABLE (PREFIX_0F3A44) },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     /* 48 */
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     /* 50 */
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     /* 58 */
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     /* 60 */
7252     { PREFIX_TABLE (PREFIX_0F3A60) },
7253     { PREFIX_TABLE (PREFIX_0F3A61) },
7254     { PREFIX_TABLE (PREFIX_0F3A62) },
7255     { PREFIX_TABLE (PREFIX_0F3A63) },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     /* 68 */
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     /* 70 */
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     /* 78 */
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     /* 80 */
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     /* 88 */
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     /* 90 */
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     /* 98 */
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     /* a0 */
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     /* a8 */
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     /* b0 */
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     /* b8 */
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     /* c0 */
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     /* c8 */
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { PREFIX_TABLE (PREFIX_0F3ACC) },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     /* d0 */
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     /* d8 */
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { PREFIX_TABLE (PREFIX_0F3ADF) },
7395     /* e0 */
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     /* e8 */
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     /* f0 */
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     /* f8 */
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431   },
7432
7433   /* THREE_BYTE_0F7A */
7434   {
7435     /* 00 */
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     /* 08 */
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     /* 10 */
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     /* 18 */
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     /* 20 */
7472     { "ptest",          { XX } },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     /* 28 */
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     /* 30 */
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     /* 38 */
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     /* 40 */
7508     { Bad_Opcode },
7509     { "phaddbw",        { XM, EXq } },
7510     { "phaddbd",        { XM, EXq } },
7511     { "phaddbq",        { XM, EXq } },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { "phaddwd",        { XM, EXq } },
7515     { "phaddwq",        { XM, EXq } },
7516     /* 48 */
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { "phadddq",        { XM, EXq } },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     /* 50 */
7526     { Bad_Opcode },
7527     { "phaddubw",       { XM, EXq } },
7528     { "phaddubd",       { XM, EXq } },
7529     { "phaddubq",       { XM, EXq } },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { "phadduwd",       { XM, EXq } },
7533     { "phadduwq",       { XM, EXq } },
7534     /* 58 */
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { "phaddudq",       { XM, EXq } },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     /* 60 */
7544     { Bad_Opcode },
7545     { "phsubbw",        { XM, EXq } },
7546     { "phsubbd",        { XM, EXq } },
7547     { "phsubbq",        { XM, EXq } },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     /* 68 */
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     /* 70 */
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     /* 78 */
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     /* 80 */
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     /* 88 */
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     /* 90 */
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     /* 98 */
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     /* a0 */
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     /* a8 */
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     /* b0 */
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     /* b8 */
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     /* c0 */
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     /* c8 */
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     /* d0 */
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     /* d8 */
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     /* e0 */
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     /* e8 */
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     /* f0 */
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     /* f8 */
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723   },
7724 };
7725
7726 static const struct dis386 xop_table[][256] = {
7727   /* XOP_08 */
7728   {
7729     /* 00 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     /* 08 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     /* 10 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* 18 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     /* 20 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* 28 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* 30 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* 38 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* 40 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* 48 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* 50 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* 58 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* 60 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     /* 68 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 70 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     /* 78 */
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 80 */
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7880     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7881     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7882     /* 88 */
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7890     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7891     /* 90 */
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7898     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7899     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7900     /* 98 */
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7908     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7909     /* a0 */
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7913     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7917     { Bad_Opcode },
7918     /* a8 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* b0 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7935     { Bad_Opcode },
7936     /* b8 */
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* c0 */
7946     { "vprotb",         { XM, Vex_2src_1, Ib } },
7947     { "vprotw",         { XM, Vex_2src_1, Ib } },
7948     { "vprotd",         { XM, Vex_2src_1, Ib } },
7949     { "vprotq",         { XM, Vex_2src_1, Ib } },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* c8 */
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7960     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7961     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7962     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7963     /* d0 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* d8 */
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* e0 */
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* e8 */
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7996     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7997     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7998     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7999     /* f0 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     /* f8 */
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017   },
8018   /* XOP_09 */
8019   {
8020     /* 00 */
8021     { Bad_Opcode },
8022     { REG_TABLE (REG_XOP_TBM_01) },
8023     { REG_TABLE (REG_XOP_TBM_02) },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     /* 08 */
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     /* 10 */
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { REG_TABLE (REG_XOP_LWPCB) },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* 18 */
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     /* 20 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* 28 */
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     /* 30 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* 38 */
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     /* 40 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     /* 48 */
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     /* 50 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* 58 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* 60 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     /* 68 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     /* 70 */
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     /* 78 */
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* 80 */
8165     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8166     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8167     { "vfrczss",        { XM, EXd } },
8168     { "vfrczsd",        { XM, EXq } },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     /* 88 */
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     /* 90 */
8183     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
8184     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
8185     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
8186     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
8187     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
8188     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
8189     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
8190     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
8191     /* 98 */
8192     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
8193     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
8194     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
8195     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     /* a0 */
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     /* a8 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* b0 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* b8 */
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* c0 */
8237     { Bad_Opcode },
8238     { "vphaddbw",       { XM, EXxmm } },
8239     { "vphaddbd",       { XM, EXxmm } },
8240     { "vphaddbq",       { XM, EXxmm } },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { "vphaddwd",       { XM, EXxmm } },
8244     { "vphaddwq",       { XM, EXxmm } },
8245     /* c8 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { "vphadddq",       { XM, EXxmm } },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* d0 */
8255     { Bad_Opcode },
8256     { "vphaddubw",      { XM, EXxmm } },
8257     { "vphaddubd",      { XM, EXxmm } },
8258     { "vphaddubq",      { XM, EXxmm } },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { "vphadduwd",      { XM, EXxmm } },
8262     { "vphadduwq",      { XM, EXxmm } },
8263     /* d8 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { "vphaddudq",      { XM, EXxmm } },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* e0 */
8273     { Bad_Opcode },
8274     { "vphsubbw",       { XM, EXxmm } },
8275     { "vphsubwd",       { XM, EXxmm } },
8276     { "vphsubdq",       { XM, EXxmm } },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* e8 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* f0 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     /* f8 */
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308   },
8309   /* XOP_0A */
8310   {
8311     /* 00 */
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     /* 08 */
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     /* 10 */
8330     { "bextr",  { Gv, Ev, Iq } },
8331     { Bad_Opcode },
8332     { REG_TABLE (REG_XOP_LWP) },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     /* 18 */
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     /* 20 */
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     /* 28 */
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     /* 30 */
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     /* 38 */
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     /* 40 */
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     /* 48 */
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     /* 50 */
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     /* 58 */
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     /* 60 */
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     /* 68 */
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     /* 70 */
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     /* 78 */
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     /* 80 */
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     /* 88 */
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     /* 90 */
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     /* 98 */
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     /* a0 */
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     /* a8 */
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     /* b0 */
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     /* b8 */
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     /* c0 */
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     /* c8 */
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     /* d0 */
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     /* d8 */
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     /* e0 */
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     /* e8 */
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     /* f0 */
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     /* f8 */
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599   },
8600 };
8601
8602 static const struct dis386 vex_table[][256] = {
8603   /* VEX_0F */
8604   {
8605     /* 00 */
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     /* 08 */
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     /* 10 */
8624     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8627     { MOD_TABLE (MOD_VEX_0F13) },
8628     { VEX_W_TABLE (VEX_W_0F14) },
8629     { VEX_W_TABLE (VEX_W_0F15) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8631     { MOD_TABLE (MOD_VEX_0F17) },
8632     /* 18 */
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     /* 20 */
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     /* 28 */
8651     { VEX_W_TABLE (VEX_W_0F28) },
8652     { VEX_W_TABLE (VEX_W_0F29) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8654     { MOD_TABLE (MOD_VEX_0F2B) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8659     /* 30 */
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     /* 38 */
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     /* 40 */
8678     { Bad_Opcode },
8679     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8681     { Bad_Opcode },
8682     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8686     /* 48 */
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8690     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     /* 50 */
8696     { MOD_TABLE (MOD_VEX_0F50) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8700     { "vandpX",         { XM, Vex, EXx } },
8701     { "vandnpX",        { XM, Vex, EXx } },
8702     { "vorpX",          { XM, Vex, EXx } },
8703     { "vxorpX",         { XM, Vex, EXx } },
8704     /* 58 */
8705     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8713     /* 60 */
8714     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8722     /* 68 */
8723     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8731     /* 70 */
8732     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8733     { REG_TABLE (REG_VEX_0F71) },
8734     { REG_TABLE (REG_VEX_0F72) },
8735     { REG_TABLE (REG_VEX_0F73) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8740     /* 78 */
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8749     /* 80 */
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     /* 88 */
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     /* 90 */
8768     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     /* 98 */
8777     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     /* a0 */
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     /* a8 */
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { REG_TABLE (REG_VEX_0FAE) },
8802     { Bad_Opcode },
8803     /* b0 */
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     /* b8 */
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     /* c0 */
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8825     { Bad_Opcode },
8826     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8827     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8828     { "vshufpX",        { XM, Vex, EXx, Ib } },
8829     { Bad_Opcode },
8830     /* c8 */
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     /* d0 */
8840     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8841     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8842     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8843     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8847     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8848     /* d8 */
8849     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8850     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8851     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8856     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8857     /* e0 */
8858     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8859     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8866     /* e8 */
8867     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8875     /* f0 */
8876     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8877     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8878     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8880     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8881     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8882     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8883     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8884     /* f8 */
8885     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8886     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8889     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8892     { Bad_Opcode },
8893   },
8894   /* VEX_0F38 */
8895   {
8896     /* 00 */
8897     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8905     /* 08 */
8906     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8914     /* 10 */
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8923     /* 18 */
8924     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8927     { Bad_Opcode },
8928     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8931     { Bad_Opcode },
8932     /* 20 */
8933     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     /* 28 */
8942     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8950     /* 30 */
8951     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8959     /* 38 */
8960     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8968     /* 40 */
8969     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8977     /* 48 */
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     /* 50 */
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     /* 58 */
8996     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     /* 60 */
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     /* 68 */
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     /* 70 */
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     /* 78 */
9032     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     /* 80 */
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     /* 88 */
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9055     { Bad_Opcode },
9056     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9057     { Bad_Opcode },
9058     /* 90 */
9059     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9067     /* 98 */
9068     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9076     /* a0 */
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9085     /* a8 */
9086     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9094     /* b0 */
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9103     /* b8 */
9104     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9112     /* c0 */
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     /* c8 */
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     /* d0 */
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     /* d8 */
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9144     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9148     /* e0 */
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     /* e8 */
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     /* f0 */
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9170     { REG_TABLE (REG_VEX_0F38F3) },
9171     { Bad_Opcode },
9172     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9175     /* f8 */
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184   },
9185   /* VEX_0F3A */
9186   {
9187     /* 00 */
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9191     { Bad_Opcode },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9195     { Bad_Opcode },
9196     /* 08 */
9197     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9198     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9203     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9204     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9205     /* 10 */
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9211     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9213     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9214     /* 18 */
9215     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     /* 20 */
9224     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9225     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     /* 28 */
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     /* 30 */
9242     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     /* 38 */
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     /* 40 */
9260     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9261     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9263     { Bad_Opcode },
9264     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9265     { Bad_Opcode },
9266     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9267     { Bad_Opcode },
9268     /* 48 */
9269     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9270     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9271     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9272     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9273     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     /* 50 */
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     /* 58 */
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9295     /* 60 */
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9299     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     /* 68 */
9305     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9306     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9313     /* 70 */
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     /* 78 */
9323     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9324     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9325     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9326     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9327     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9328     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9329     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9330     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9331     /* 80 */
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     /* 88 */
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     /* 90 */
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     /* 98 */
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     /* a0 */
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     /* a8 */
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     /* b0 */
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     /* b8 */
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     /* c0 */
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     /* c8 */
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     /* d0 */
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     /* d8 */
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9439     /* e0 */
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     /* e8 */
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     /* f0 */
9458     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     /* f8 */
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475   },
9476 };
9477
9478 #define NEED_OPCODE_TABLE
9479 #include "i386-dis-evex.h"
9480 #undef NEED_OPCODE_TABLE
9481 static const struct dis386 vex_len_table[][2] = {
9482   /* VEX_LEN_0F10_P_1 */
9483   {
9484     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9485     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9486   },
9487
9488   /* VEX_LEN_0F10_P_3 */
9489   {
9490     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9491     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9492   },
9493
9494   /* VEX_LEN_0F11_P_1 */
9495   {
9496     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9497     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9498   },
9499
9500   /* VEX_LEN_0F11_P_3 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9503     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9504   },
9505
9506   /* VEX_LEN_0F12_P_0_M_0 */
9507   {
9508     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9509   },
9510
9511   /* VEX_LEN_0F12_P_0_M_1 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9514   },
9515
9516   /* VEX_LEN_0F12_P_2 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9519   },
9520
9521   /* VEX_LEN_0F13_M_0 */
9522   {
9523     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9524   },
9525
9526   /* VEX_LEN_0F16_P_0_M_0 */
9527   {
9528     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9529   },
9530
9531   /* VEX_LEN_0F16_P_0_M_1 */
9532   {
9533     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9534   },
9535
9536   /* VEX_LEN_0F16_P_2 */
9537   {
9538     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9539   },
9540
9541   /* VEX_LEN_0F17_M_0 */
9542   {
9543     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9544   },
9545
9546   /* VEX_LEN_0F2A_P_1 */
9547   {
9548     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9549     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9550   },
9551
9552   /* VEX_LEN_0F2A_P_3 */
9553   {
9554     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9555     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9556   },
9557
9558   /* VEX_LEN_0F2C_P_1 */
9559   {
9560     { "vcvttss2siY",    { Gv, EXdScalar } },
9561     { "vcvttss2siY",    { Gv, EXdScalar } },
9562   },
9563
9564   /* VEX_LEN_0F2C_P_3 */
9565   {
9566     { "vcvttsd2siY",    { Gv, EXqScalar } },
9567     { "vcvttsd2siY",    { Gv, EXqScalar } },
9568   },
9569
9570   /* VEX_LEN_0F2D_P_1 */
9571   {
9572     { "vcvtss2siY",     { Gv, EXdScalar } },
9573     { "vcvtss2siY",     { Gv, EXdScalar } },
9574   },
9575
9576   /* VEX_LEN_0F2D_P_3 */
9577   {
9578     { "vcvtsd2siY",     { Gv, EXqScalar } },
9579     { "vcvtsd2siY",     { Gv, EXqScalar } },
9580   },
9581
9582   /* VEX_LEN_0F2E_P_0 */
9583   {
9584     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9585     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9586   },
9587
9588   /* VEX_LEN_0F2E_P_2 */
9589   {
9590     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9591     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9592   },
9593
9594   /* VEX_LEN_0F2F_P_0 */
9595   {
9596     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9597     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9598   },
9599
9600   /* VEX_LEN_0F2F_P_2 */
9601   {
9602     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9603     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9604   },
9605
9606   /* VEX_LEN_0F41_P_0 */
9607   {
9608     { Bad_Opcode },
9609     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9610   },
9611   /* VEX_LEN_0F41_P_2 */
9612   {
9613     { Bad_Opcode },
9614     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9615   },
9616   /* VEX_LEN_0F42_P_0 */
9617   {
9618     { Bad_Opcode },
9619     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9620   },
9621   /* VEX_LEN_0F42_P_2 */
9622   {
9623     { Bad_Opcode },
9624     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9625   },
9626   /* VEX_LEN_0F44_P_0 */
9627   {
9628     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9629   },
9630   /* VEX_LEN_0F44_P_2 */
9631   {
9632     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9633   },
9634   /* VEX_LEN_0F45_P_0 */
9635   {
9636     { Bad_Opcode },
9637     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9638   },
9639   /* VEX_LEN_0F45_P_2 */
9640   {
9641     { Bad_Opcode },
9642     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9643   },
9644   /* VEX_LEN_0F46_P_0 */
9645   {
9646     { Bad_Opcode },
9647     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9648   },
9649   /* VEX_LEN_0F46_P_2 */
9650   {
9651     { Bad_Opcode },
9652     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9653   },
9654   /* VEX_LEN_0F47_P_0 */
9655   {
9656     { Bad_Opcode },
9657     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9658   },
9659   /* VEX_LEN_0F47_P_2 */
9660   {
9661     { Bad_Opcode },
9662     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9663   },
9664   /* VEX_LEN_0F4A_P_0 */
9665   {
9666     { Bad_Opcode },
9667     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9668   },
9669   /* VEX_LEN_0F4A_P_2 */
9670   {
9671     { Bad_Opcode },
9672     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9673   },
9674   /* VEX_LEN_0F4B_P_0 */
9675   {
9676     { Bad_Opcode },
9677     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9678   },
9679   /* VEX_LEN_0F4B_P_2 */
9680   {
9681     { Bad_Opcode },
9682     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9683   },
9684
9685   /* VEX_LEN_0F51_P_1 */
9686   {
9687     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9688     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9689   },
9690
9691   /* VEX_LEN_0F51_P_3 */
9692   {
9693     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9694     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9695   },
9696
9697   /* VEX_LEN_0F52_P_1 */
9698   {
9699     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9700     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9701   },
9702
9703   /* VEX_LEN_0F53_P_1 */
9704   {
9705     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9706     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9707   },
9708
9709   /* VEX_LEN_0F58_P_1 */
9710   {
9711     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9712     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9713   },
9714
9715   /* VEX_LEN_0F58_P_3 */
9716   {
9717     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9718     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9719   },
9720
9721   /* VEX_LEN_0F59_P_1 */
9722   {
9723     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9724     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9725   },
9726
9727   /* VEX_LEN_0F59_P_3 */
9728   {
9729     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9730     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9731   },
9732
9733   /* VEX_LEN_0F5A_P_1 */
9734   {
9735     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9736     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9737   },
9738
9739   /* VEX_LEN_0F5A_P_3 */
9740   {
9741     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9742     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9743   },
9744
9745   /* VEX_LEN_0F5C_P_1 */
9746   {
9747     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9748     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9749   },
9750
9751   /* VEX_LEN_0F5C_P_3 */
9752   {
9753     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9754     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9755   },
9756
9757   /* VEX_LEN_0F5D_P_1 */
9758   {
9759     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9760     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9761   },
9762
9763   /* VEX_LEN_0F5D_P_3 */
9764   {
9765     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9766     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9767   },
9768
9769   /* VEX_LEN_0F5E_P_1 */
9770   {
9771     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9772     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9773   },
9774
9775   /* VEX_LEN_0F5E_P_3 */
9776   {
9777     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9778     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9779   },
9780
9781   /* VEX_LEN_0F5F_P_1 */
9782   {
9783     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9784     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9785   },
9786
9787   /* VEX_LEN_0F5F_P_3 */
9788   {
9789     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9790     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9791   },
9792
9793   /* VEX_LEN_0F6E_P_2 */
9794   {
9795     { "vmovK",          { XMScalar, Edq } },
9796     { "vmovK",          { XMScalar, Edq } },
9797   },
9798
9799   /* VEX_LEN_0F7E_P_1 */
9800   {
9801     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9802     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9803   },
9804
9805   /* VEX_LEN_0F7E_P_2 */
9806   {
9807     { "vmovK",          { Edq, XMScalar } },
9808     { "vmovK",          { Edq, XMScalar } },
9809   },
9810
9811   /* VEX_LEN_0F90_P_0 */
9812   {
9813     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9814   },
9815
9816   /* VEX_LEN_0F90_P_2 */
9817   {
9818     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9819   },
9820
9821   /* VEX_LEN_0F91_P_0 */
9822   {
9823     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9824   },
9825
9826   /* VEX_LEN_0F91_P_2 */
9827   {
9828     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9829   },
9830
9831   /* VEX_LEN_0F92_P_0 */
9832   {
9833     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9834   },
9835
9836   /* VEX_LEN_0F92_P_2 */
9837   {
9838     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9839   },
9840
9841   /* VEX_LEN_0F92_P_3 */
9842   {
9843     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9844   },
9845
9846   /* VEX_LEN_0F93_P_0 */
9847   {
9848     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9849   },
9850
9851   /* VEX_LEN_0F93_P_2 */
9852   {
9853     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9854   },
9855
9856   /* VEX_LEN_0F93_P_3 */
9857   {
9858     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9859   },
9860
9861   /* VEX_LEN_0F98_P_0 */
9862   {
9863     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9864   },
9865
9866   /* VEX_LEN_0F98_P_2 */
9867   {
9868     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9869   },
9870
9871   /* VEX_LEN_0F99_P_0 */
9872   {
9873     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9874   },
9875
9876   /* VEX_LEN_0F99_P_2 */
9877   {
9878     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9879   },
9880
9881   /* VEX_LEN_0FAE_R_2_M_0 */
9882   {
9883     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9884   },
9885
9886   /* VEX_LEN_0FAE_R_3_M_0 */
9887   {
9888     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9889   },
9890
9891   /* VEX_LEN_0FC2_P_1 */
9892   {
9893     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9894     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9895   },
9896
9897   /* VEX_LEN_0FC2_P_3 */
9898   {
9899     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9900     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9901   },
9902
9903   /* VEX_LEN_0FC4_P_2 */
9904   {
9905     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9906   },
9907
9908   /* VEX_LEN_0FC5_P_2 */
9909   {
9910     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9911   },
9912
9913   /* VEX_LEN_0FD6_P_2 */
9914   {
9915     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9916     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9917   },
9918
9919   /* VEX_LEN_0FF7_P_2 */
9920   {
9921     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9922   },
9923
9924   /* VEX_LEN_0F3816_P_2 */
9925   {
9926     { Bad_Opcode },
9927     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9928   },
9929
9930   /* VEX_LEN_0F3819_P_2 */
9931   {
9932     { Bad_Opcode },
9933     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9934   },
9935
9936   /* VEX_LEN_0F381A_P_2_M_0 */
9937   {
9938     { Bad_Opcode },
9939     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9940   },
9941
9942   /* VEX_LEN_0F3836_P_2 */
9943   {
9944     { Bad_Opcode },
9945     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9946   },
9947
9948   /* VEX_LEN_0F3841_P_2 */
9949   {
9950     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9951   },
9952
9953   /* VEX_LEN_0F385A_P_2_M_0 */
9954   {
9955     { Bad_Opcode },
9956     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9957   },
9958
9959   /* VEX_LEN_0F38DB_P_2 */
9960   {
9961     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9962   },
9963
9964   /* VEX_LEN_0F38DC_P_2 */
9965   {
9966     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9967   },
9968
9969   /* VEX_LEN_0F38DD_P_2 */
9970   {
9971     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9972   },
9973
9974   /* VEX_LEN_0F38DE_P_2 */
9975   {
9976     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9977   },
9978
9979   /* VEX_LEN_0F38DF_P_2 */
9980   {
9981     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9982   },
9983
9984   /* VEX_LEN_0F38F2_P_0 */
9985   {
9986     { "andnS",          { Gdq, VexGdq, Edq } },
9987   },
9988
9989   /* VEX_LEN_0F38F3_R_1_P_0 */
9990   {
9991     { "blsrS",          { VexGdq, Edq } },
9992   },
9993
9994   /* VEX_LEN_0F38F3_R_2_P_0 */
9995   {
9996     { "blsmskS",        { VexGdq, Edq } },
9997   },
9998
9999   /* VEX_LEN_0F38F3_R_3_P_0 */
10000   {
10001     { "blsiS",          { VexGdq, Edq } },
10002   },
10003
10004   /* VEX_LEN_0F38F5_P_0 */
10005   {
10006     { "bzhiS",          { Gdq, Edq, VexGdq } },
10007   },
10008
10009   /* VEX_LEN_0F38F5_P_1 */
10010   {
10011     { "pextS",          { Gdq, VexGdq, Edq } },
10012   },
10013
10014   /* VEX_LEN_0F38F5_P_3 */
10015   {
10016     { "pdepS",          { Gdq, VexGdq, Edq } },
10017   },
10018
10019   /* VEX_LEN_0F38F6_P_3 */
10020   {
10021     { "mulxS",          { Gdq, VexGdq, Edq } },
10022   },
10023
10024   /* VEX_LEN_0F38F7_P_0 */
10025   {
10026     { "bextrS",         { Gdq, Edq, VexGdq } },
10027   },
10028
10029   /* VEX_LEN_0F38F7_P_1 */
10030   {
10031     { "sarxS",          { Gdq, Edq, VexGdq } },
10032   },
10033
10034   /* VEX_LEN_0F38F7_P_2 */
10035   {
10036     { "shlxS",          { Gdq, Edq, VexGdq } },
10037   },
10038
10039   /* VEX_LEN_0F38F7_P_3 */
10040   {
10041     { "shrxS",          { Gdq, Edq, VexGdq } },
10042   },
10043
10044   /* VEX_LEN_0F3A00_P_2 */
10045   {
10046     { Bad_Opcode },
10047     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10048   },
10049
10050   /* VEX_LEN_0F3A01_P_2 */
10051   {
10052     { Bad_Opcode },
10053     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10054   },
10055
10056   /* VEX_LEN_0F3A06_P_2 */
10057   {
10058     { Bad_Opcode },
10059     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10060   },
10061
10062   /* VEX_LEN_0F3A0A_P_2 */
10063   {
10064     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10065     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10066   },
10067
10068   /* VEX_LEN_0F3A0B_P_2 */
10069   {
10070     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10071     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10072   },
10073
10074   /* VEX_LEN_0F3A14_P_2 */
10075   {
10076     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10077   },
10078
10079   /* VEX_LEN_0F3A15_P_2 */
10080   {
10081     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10082   },
10083
10084   /* VEX_LEN_0F3A16_P_2  */
10085   {
10086     { "vpextrK",        { Edq, XM, Ib } },
10087   },
10088
10089   /* VEX_LEN_0F3A17_P_2 */
10090   {
10091     { "vextractps",     { Edqd, XM, Ib } },
10092   },
10093
10094   /* VEX_LEN_0F3A18_P_2 */
10095   {
10096     { Bad_Opcode },
10097     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10098   },
10099
10100   /* VEX_LEN_0F3A19_P_2 */
10101   {
10102     { Bad_Opcode },
10103     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10104   },
10105
10106   /* VEX_LEN_0F3A20_P_2 */
10107   {
10108     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10109   },
10110
10111   /* VEX_LEN_0F3A21_P_2 */
10112   {
10113     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10114   },
10115
10116   /* VEX_LEN_0F3A22_P_2 */
10117   {
10118     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
10119   },
10120
10121   /* VEX_LEN_0F3A30_P_2 */
10122   {
10123     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10124   },
10125
10126   /* VEX_LEN_0F3A31_P_2 */
10127   {
10128     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10129   },
10130
10131   /* VEX_LEN_0F3A32_P_2 */
10132   {
10133     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10134   },
10135
10136   /* VEX_LEN_0F3A33_P_2 */
10137   {
10138     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10139   },
10140
10141   /* VEX_LEN_0F3A38_P_2 */
10142   {
10143     { Bad_Opcode },
10144     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10145   },
10146
10147   /* VEX_LEN_0F3A39_P_2 */
10148   {
10149     { Bad_Opcode },
10150     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10151   },
10152
10153   /* VEX_LEN_0F3A41_P_2 */
10154   {
10155     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10156   },
10157
10158   /* VEX_LEN_0F3A44_P_2 */
10159   {
10160     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10161   },
10162
10163   /* VEX_LEN_0F3A46_P_2 */
10164   {
10165     { Bad_Opcode },
10166     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10167   },
10168
10169   /* VEX_LEN_0F3A60_P_2 */
10170   {
10171     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10172   },
10173
10174   /* VEX_LEN_0F3A61_P_2 */
10175   {
10176     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10177   },
10178
10179   /* VEX_LEN_0F3A62_P_2 */
10180   {
10181     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10182   },
10183
10184   /* VEX_LEN_0F3A63_P_2 */
10185   {
10186     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10187   },
10188
10189   /* VEX_LEN_0F3A6A_P_2 */
10190   {
10191     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10192   },
10193
10194   /* VEX_LEN_0F3A6B_P_2 */
10195   {
10196     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10197   },
10198
10199   /* VEX_LEN_0F3A6E_P_2 */
10200   {
10201     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10202   },
10203
10204   /* VEX_LEN_0F3A6F_P_2 */
10205   {
10206     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10207   },
10208
10209   /* VEX_LEN_0F3A7A_P_2 */
10210   {
10211     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10212   },
10213
10214   /* VEX_LEN_0F3A7B_P_2 */
10215   {
10216     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10217   },
10218
10219   /* VEX_LEN_0F3A7E_P_2 */
10220   {
10221     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10222   },
10223
10224   /* VEX_LEN_0F3A7F_P_2 */
10225   {
10226     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10227   },
10228
10229   /* VEX_LEN_0F3ADF_P_2 */
10230   {
10231     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10232   },
10233
10234   /* VEX_LEN_0F3AF0_P_3 */
10235   {
10236     { "rorxS",          { Gdq, Edq, Ib } },
10237   },
10238
10239   /* VEX_LEN_0FXOP_08_CC */
10240   {
10241      { "vpcomb",        { XM, Vex128, EXx, Ib } },
10242   },
10243
10244   /* VEX_LEN_0FXOP_08_CD */
10245   {
10246      { "vpcomw",        { XM, Vex128, EXx, Ib } },
10247   },
10248
10249   /* VEX_LEN_0FXOP_08_CE */
10250   {
10251      { "vpcomd",        { XM, Vex128, EXx, Ib } },
10252   },
10253
10254   /* VEX_LEN_0FXOP_08_CF */
10255   {
10256      { "vpcomq",        { XM, Vex128, EXx, Ib } },
10257   },
10258
10259   /* VEX_LEN_0FXOP_08_EC */
10260   {
10261      { "vpcomub",       { XM, Vex128, EXx, Ib } },
10262   },
10263
10264   /* VEX_LEN_0FXOP_08_ED */
10265   {
10266      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
10267   },
10268
10269   /* VEX_LEN_0FXOP_08_EE */
10270   {
10271      { "vpcomud",       { XM, Vex128, EXx, Ib } },
10272   },
10273
10274   /* VEX_LEN_0FXOP_08_EF */
10275   {
10276      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
10277   },
10278
10279   /* VEX_LEN_0FXOP_09_80 */
10280   {
10281     { "vfrczps",        { XM, EXxmm } },
10282     { "vfrczps",        { XM, EXymmq } },
10283   },
10284
10285   /* VEX_LEN_0FXOP_09_81 */
10286   {
10287     { "vfrczpd",        { XM, EXxmm } },
10288     { "vfrczpd",        { XM, EXymmq } },
10289   },
10290 };
10291
10292 static const struct dis386 vex_w_table[][2] = {
10293   {
10294     /* VEX_W_0F10_P_0 */
10295     { "vmovups",        { XM, EXx } },
10296   },
10297   {
10298     /* VEX_W_0F10_P_1 */
10299     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
10300   },
10301   {
10302     /* VEX_W_0F10_P_2 */
10303     { "vmovupd",        { XM, EXx } },
10304   },
10305   {
10306     /* VEX_W_0F10_P_3 */
10307     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
10308   },
10309   {
10310     /* VEX_W_0F11_P_0 */
10311     { "vmovups",        { EXxS, XM } },
10312   },
10313   {
10314     /* VEX_W_0F11_P_1 */
10315     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
10316   },
10317   {
10318     /* VEX_W_0F11_P_2 */
10319     { "vmovupd",        { EXxS, XM } },
10320   },
10321   {
10322     /* VEX_W_0F11_P_3 */
10323     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
10324   },
10325   {
10326     /* VEX_W_0F12_P_0_M_0 */
10327     { "vmovlps",        { XM, Vex128, EXq } },
10328   },
10329   {
10330     /* VEX_W_0F12_P_0_M_1 */
10331     { "vmovhlps",       { XM, Vex128, EXq } },
10332   },
10333   {
10334     /* VEX_W_0F12_P_1 */
10335     { "vmovsldup",      { XM, EXx } },
10336   },
10337   {
10338     /* VEX_W_0F12_P_2 */
10339     { "vmovlpd",        { XM, Vex128, EXq } },
10340   },
10341   {
10342     /* VEX_W_0F12_P_3 */
10343     { "vmovddup",       { XM, EXymmq } },
10344   },
10345   {
10346     /* VEX_W_0F13_M_0 */
10347     { "vmovlpX",        { EXq, XM } },
10348   },
10349   {
10350     /* VEX_W_0F14 */
10351     { "vunpcklpX",      { XM, Vex, EXx } },
10352   },
10353   {
10354     /* VEX_W_0F15 */
10355     { "vunpckhpX",      { XM, Vex, EXx } },
10356   },
10357   {
10358     /* VEX_W_0F16_P_0_M_0 */
10359     { "vmovhps",        { XM, Vex128, EXq } },
10360   },
10361   {
10362     /* VEX_W_0F16_P_0_M_1 */
10363     { "vmovlhps",       { XM, Vex128, EXq } },
10364   },
10365   {
10366     /* VEX_W_0F16_P_1 */
10367     { "vmovshdup",      { XM, EXx } },
10368   },
10369   {
10370     /* VEX_W_0F16_P_2 */
10371     { "vmovhpd",        { XM, Vex128, EXq } },
10372   },
10373   {
10374     /* VEX_W_0F17_M_0 */
10375     { "vmovhpX",        { EXq, XM } },
10376   },
10377   {
10378     /* VEX_W_0F28 */
10379     { "vmovapX",        { XM, EXx } },
10380   },
10381   {
10382     /* VEX_W_0F29 */
10383     { "vmovapX",        { EXxS, XM } },
10384   },
10385   {
10386     /* VEX_W_0F2B_M_0 */
10387     { "vmovntpX",       { Mx, XM } },
10388   },
10389   {
10390     /* VEX_W_0F2E_P_0 */
10391     { "vucomiss",       { XMScalar, EXdScalar } },
10392   },
10393   {
10394     /* VEX_W_0F2E_P_2 */
10395     { "vucomisd",       { XMScalar, EXqScalar } },
10396   },
10397   {
10398     /* VEX_W_0F2F_P_0 */
10399     { "vcomiss",        { XMScalar, EXdScalar } },
10400   },
10401   {
10402     /* VEX_W_0F2F_P_2 */
10403     { "vcomisd",        { XMScalar, EXqScalar } },
10404   },
10405   {
10406     /* VEX_W_0F41_P_0_LEN_1 */
10407     { "kandw",          { MaskG, MaskVex, MaskR } },
10408     { "kandq",          { MaskG, MaskVex, MaskR } },
10409   },
10410   {
10411     /* VEX_W_0F41_P_2_LEN_1 */
10412     { "kandb",          { MaskG, MaskVex, MaskR } },
10413     { "kandd",          { MaskG, MaskVex, MaskR } },
10414   },
10415   {
10416     /* VEX_W_0F42_P_0_LEN_1 */
10417     { "kandnw",         { MaskG, MaskVex, MaskR } },
10418     { "kandnq",         { MaskG, MaskVex, MaskR } },
10419   },
10420   {
10421     /* VEX_W_0F42_P_2_LEN_1 */
10422     { "kandnb",         { MaskG, MaskVex, MaskR } },
10423     { "kandnd",         { MaskG, MaskVex, MaskR } },
10424   },
10425   {
10426     /* VEX_W_0F44_P_0_LEN_0 */
10427     { "knotw",          { MaskG, MaskR } },
10428     { "knotq",          { MaskG, MaskR } },
10429   },
10430   {
10431     /* VEX_W_0F44_P_2_LEN_0 */
10432     { "knotb",          { MaskG, MaskR } },
10433     { "knotd",          { MaskG, MaskR } },
10434   },
10435   {
10436     /* VEX_W_0F45_P_0_LEN_1 */
10437     { "korw",           { MaskG, MaskVex, MaskR } },
10438     { "korq",           { MaskG, MaskVex, MaskR } },
10439   },
10440   {
10441     /* VEX_W_0F45_P_2_LEN_1 */
10442     { "korb",           { MaskG, MaskVex, MaskR } },
10443     { "kord",           { MaskG, MaskVex, MaskR } },
10444   },
10445   {
10446     /* VEX_W_0F46_P_0_LEN_1 */
10447     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10448     { "kxnorq",         { MaskG, MaskVex, MaskR } },
10449   },
10450   {
10451     /* VEX_W_0F46_P_2_LEN_1 */
10452     { "kxnorb",         { MaskG, MaskVex, MaskR } },
10453     { "kxnord",         { MaskG, MaskVex, MaskR } },
10454   },
10455   {
10456     /* VEX_W_0F47_P_0_LEN_1 */
10457     { "kxorw",          { MaskG, MaskVex, MaskR } },
10458     { "kxorq",          { MaskG, MaskVex, MaskR } },
10459   },
10460   {
10461     /* VEX_W_0F47_P_2_LEN_1 */
10462     { "kxorb",          { MaskG, MaskVex, MaskR } },
10463     { "kxord",          { MaskG, MaskVex, MaskR } },
10464   },
10465   {
10466     /* VEX_W_0F4A_P_0_LEN_1 */
10467     { "kaddw",          { MaskG, MaskVex, MaskR } },
10468     { "kaddq",          { MaskG, MaskVex, MaskR } },
10469   },
10470   {
10471     /* VEX_W_0F4A_P_2_LEN_1 */
10472     { "kaddb",          { MaskG, MaskVex, MaskR } },
10473     { "kaddd",          { MaskG, MaskVex, MaskR } },
10474   },
10475   {
10476     /* VEX_W_0F4B_P_0_LEN_1 */
10477     { "kunpckwd",       { MaskG, MaskVex, MaskR } },
10478     { "kunpckdq",       { MaskG, MaskVex, MaskR } },
10479   },
10480   {
10481     /* VEX_W_0F4B_P_2_LEN_1 */
10482     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10483   },
10484   {
10485     /* VEX_W_0F50_M_0 */
10486     { "vmovmskpX",      { Gdq, XS } },
10487   },
10488   {
10489     /* VEX_W_0F51_P_0 */
10490     { "vsqrtps",        { XM, EXx } },
10491   },
10492   {
10493     /* VEX_W_0F51_P_1 */
10494     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10495   },
10496   {
10497     /* VEX_W_0F51_P_2  */
10498     { "vsqrtpd",        { XM, EXx } },
10499   },
10500   {
10501     /* VEX_W_0F51_P_3 */
10502     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10503   },
10504   {
10505     /* VEX_W_0F52_P_0 */
10506     { "vrsqrtps",       { XM, EXx } },
10507   },
10508   {
10509     /* VEX_W_0F52_P_1 */
10510     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10511   },
10512   {
10513     /* VEX_W_0F53_P_0  */
10514     { "vrcpps",         { XM, EXx } },
10515   },
10516   {
10517     /* VEX_W_0F53_P_1  */
10518     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10519   },
10520   {
10521     /* VEX_W_0F58_P_0  */
10522     { "vaddps",         { XM, Vex, EXx } },
10523   },
10524   {
10525     /* VEX_W_0F58_P_1  */
10526     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10527   },
10528   {
10529     /* VEX_W_0F58_P_2  */
10530     { "vaddpd",         { XM, Vex, EXx } },
10531   },
10532   {
10533     /* VEX_W_0F58_P_3  */
10534     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10535   },
10536   {
10537     /* VEX_W_0F59_P_0  */
10538     { "vmulps",         { XM, Vex, EXx } },
10539   },
10540   {
10541     /* VEX_W_0F59_P_1  */
10542     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10543   },
10544   {
10545     /* VEX_W_0F59_P_2  */
10546     { "vmulpd",         { XM, Vex, EXx } },
10547   },
10548   {
10549     /* VEX_W_0F59_P_3  */
10550     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10551   },
10552   {
10553     /* VEX_W_0F5A_P_0  */
10554     { "vcvtps2pd",      { XM, EXxmmq } },
10555   },
10556   {
10557     /* VEX_W_0F5A_P_1  */
10558     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10559   },
10560   {
10561     /* VEX_W_0F5A_P_3  */
10562     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10563   },
10564   {
10565     /* VEX_W_0F5B_P_0  */
10566     { "vcvtdq2ps",      { XM, EXx } },
10567   },
10568   {
10569     /* VEX_W_0F5B_P_1  */
10570     { "vcvttps2dq",     { XM, EXx } },
10571   },
10572   {
10573     /* VEX_W_0F5B_P_2  */
10574     { "vcvtps2dq",      { XM, EXx } },
10575   },
10576   {
10577     /* VEX_W_0F5C_P_0  */
10578     { "vsubps",         { XM, Vex, EXx } },
10579   },
10580   {
10581     /* VEX_W_0F5C_P_1  */
10582     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10583   },
10584   {
10585     /* VEX_W_0F5C_P_2  */
10586     { "vsubpd",         { XM, Vex, EXx } },
10587   },
10588   {
10589     /* VEX_W_0F5C_P_3  */
10590     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10591   },
10592   {
10593     /* VEX_W_0F5D_P_0  */
10594     { "vminps",         { XM, Vex, EXx } },
10595   },
10596   {
10597     /* VEX_W_0F5D_P_1  */
10598     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10599   },
10600   {
10601     /* VEX_W_0F5D_P_2  */
10602     { "vminpd",         { XM, Vex, EXx } },
10603   },
10604   {
10605     /* VEX_W_0F5D_P_3  */
10606     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10607   },
10608   {
10609     /* VEX_W_0F5E_P_0  */
10610     { "vdivps",         { XM, Vex, EXx } },
10611   },
10612   {
10613     /* VEX_W_0F5E_P_1  */
10614     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10615   },
10616   {
10617     /* VEX_W_0F5E_P_2  */
10618     { "vdivpd",         { XM, Vex, EXx } },
10619   },
10620   {
10621     /* VEX_W_0F5E_P_3  */
10622     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10623   },
10624   {
10625     /* VEX_W_0F5F_P_0  */
10626     { "vmaxps",         { XM, Vex, EXx } },
10627   },
10628   {
10629     /* VEX_W_0F5F_P_1  */
10630     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10631   },
10632   {
10633     /* VEX_W_0F5F_P_2  */
10634     { "vmaxpd",         { XM, Vex, EXx } },
10635   },
10636   {
10637     /* VEX_W_0F5F_P_3  */
10638     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10639   },
10640   {
10641     /* VEX_W_0F60_P_2  */
10642     { "vpunpcklbw",     { XM, Vex, EXx } },
10643   },
10644   {
10645     /* VEX_W_0F61_P_2  */
10646     { "vpunpcklwd",     { XM, Vex, EXx } },
10647   },
10648   {
10649     /* VEX_W_0F62_P_2  */
10650     { "vpunpckldq",     { XM, Vex, EXx } },
10651   },
10652   {
10653     /* VEX_W_0F63_P_2  */
10654     { "vpacksswb",      { XM, Vex, EXx } },
10655   },
10656   {
10657     /* VEX_W_0F64_P_2  */
10658     { "vpcmpgtb",       { XM, Vex, EXx } },
10659   },
10660   {
10661     /* VEX_W_0F65_P_2  */
10662     { "vpcmpgtw",       { XM, Vex, EXx } },
10663   },
10664   {
10665     /* VEX_W_0F66_P_2  */
10666     { "vpcmpgtd",       { XM, Vex, EXx } },
10667   },
10668   {
10669     /* VEX_W_0F67_P_2  */
10670     { "vpackuswb",      { XM, Vex, EXx } },
10671   },
10672   {
10673     /* VEX_W_0F68_P_2  */
10674     { "vpunpckhbw",     { XM, Vex, EXx } },
10675   },
10676   {
10677     /* VEX_W_0F69_P_2  */
10678     { "vpunpckhwd",     { XM, Vex, EXx } },
10679   },
10680   {
10681     /* VEX_W_0F6A_P_2  */
10682     { "vpunpckhdq",     { XM, Vex, EXx } },
10683   },
10684   {
10685     /* VEX_W_0F6B_P_2  */
10686     { "vpackssdw",      { XM, Vex, EXx } },
10687   },
10688   {
10689     /* VEX_W_0F6C_P_2  */
10690     { "vpunpcklqdq",    { XM, Vex, EXx } },
10691   },
10692   {
10693     /* VEX_W_0F6D_P_2  */
10694     { "vpunpckhqdq",    { XM, Vex, EXx } },
10695   },
10696   {
10697     /* VEX_W_0F6F_P_1  */
10698     { "vmovdqu",        { XM, EXx } },
10699   },
10700   {
10701     /* VEX_W_0F6F_P_2  */
10702     { "vmovdqa",        { XM, EXx } },
10703   },
10704   {
10705     /* VEX_W_0F70_P_1 */
10706     { "vpshufhw",       { XM, EXx, Ib } },
10707   },
10708   {
10709     /* VEX_W_0F70_P_2 */
10710     { "vpshufd",        { XM, EXx, Ib } },
10711   },
10712   {
10713     /* VEX_W_0F70_P_3 */
10714     { "vpshuflw",       { XM, EXx, Ib } },
10715   },
10716   {
10717     /* VEX_W_0F71_R_2_P_2  */
10718     { "vpsrlw",         { Vex, XS, Ib } },
10719   },
10720   {
10721     /* VEX_W_0F71_R_4_P_2  */
10722     { "vpsraw",         { Vex, XS, Ib } },
10723   },
10724   {
10725     /* VEX_W_0F71_R_6_P_2  */
10726     { "vpsllw",         { Vex, XS, Ib } },
10727   },
10728   {
10729     /* VEX_W_0F72_R_2_P_2  */
10730     { "vpsrld",         { Vex, XS, Ib } },
10731   },
10732   {
10733     /* VEX_W_0F72_R_4_P_2  */
10734     { "vpsrad",         { Vex, XS, Ib } },
10735   },
10736   {
10737     /* VEX_W_0F72_R_6_P_2  */
10738     { "vpslld",         { Vex, XS, Ib } },
10739   },
10740   {
10741     /* VEX_W_0F73_R_2_P_2  */
10742     { "vpsrlq",         { Vex, XS, Ib } },
10743   },
10744   {
10745     /* VEX_W_0F73_R_3_P_2  */
10746     { "vpsrldq",        { Vex, XS, Ib } },
10747   },
10748   {
10749     /* VEX_W_0F73_R_6_P_2  */
10750     { "vpsllq",         { Vex, XS, Ib } },
10751   },
10752   {
10753     /* VEX_W_0F73_R_7_P_2  */
10754     { "vpslldq",        { Vex, XS, Ib } },
10755   },
10756   {
10757     /* VEX_W_0F74_P_2 */
10758     { "vpcmpeqb",       { XM, Vex, EXx } },
10759   },
10760   {
10761     /* VEX_W_0F75_P_2 */
10762     { "vpcmpeqw",       { XM, Vex, EXx } },
10763   },
10764   {
10765     /* VEX_W_0F76_P_2 */
10766     { "vpcmpeqd",       { XM, Vex, EXx } },
10767   },
10768   {
10769     /* VEX_W_0F77_P_0 */
10770     { "",               { VZERO } },
10771   },
10772   {
10773     /* VEX_W_0F7C_P_2 */
10774     { "vhaddpd",        { XM, Vex, EXx } },
10775   },
10776   {
10777     /* VEX_W_0F7C_P_3 */
10778     { "vhaddps",        { XM, Vex, EXx } },
10779   },
10780   {
10781     /* VEX_W_0F7D_P_2 */
10782     { "vhsubpd",        { XM, Vex, EXx } },
10783   },
10784   {
10785     /* VEX_W_0F7D_P_3 */
10786     { "vhsubps",        { XM, Vex, EXx } },
10787   },
10788   {
10789     /* VEX_W_0F7E_P_1 */
10790     { "vmovq",          { XMScalar, EXqScalar } },
10791   },
10792   {
10793     /* VEX_W_0F7F_P_1 */
10794     { "vmovdqu",        { EXxS, XM } },
10795   },
10796   {
10797     /* VEX_W_0F7F_P_2 */
10798     { "vmovdqa",        { EXxS, XM } },
10799   },
10800   {
10801     /* VEX_W_0F90_P_0_LEN_0 */
10802     { "kmovw",          { MaskG, MaskE } },
10803     { "kmovq",          { MaskG, MaskE } },
10804   },
10805   {
10806     /* VEX_W_0F90_P_2_LEN_0 */
10807     { "kmovb",          { MaskG, MaskBDE } },
10808     { "kmovd",          { MaskG, MaskBDE } },
10809   },
10810   {
10811     /* VEX_W_0F91_P_0_LEN_0 */
10812     { "kmovw",          { Ew, MaskG } },
10813     { "kmovq",          { Eq, MaskG } },
10814   },
10815   {
10816     /* VEX_W_0F91_P_2_LEN_0 */
10817     { "kmovb",          { Eb, MaskG } },
10818     { "kmovd",          { Ed, MaskG } },
10819   },
10820   {
10821     /* VEX_W_0F92_P_0_LEN_0 */
10822     { "kmovw",          { MaskG, Rdq } },
10823   },
10824   {
10825     /* VEX_W_0F92_P_2_LEN_0 */
10826     { "kmovb",          { MaskG, Rdq } },
10827   },
10828   {
10829     /* VEX_W_0F92_P_3_LEN_0 */
10830     { "kmovd",          { MaskG, Rdq } },
10831     { "kmovq",          { MaskG, Rdq } },
10832   },
10833   {
10834     /* VEX_W_0F93_P_0_LEN_0 */
10835     { "kmovw",          { Gdq, MaskR } },
10836   },
10837   {
10838     /* VEX_W_0F93_P_2_LEN_0 */
10839     { "kmovb",          { Gdq, MaskR } },
10840   },
10841   {
10842     /* VEX_W_0F93_P_3_LEN_0 */
10843     { "kmovd",          { Gdq, MaskR } },
10844     { "kmovq",          { Gdq, MaskR } },
10845   },
10846   {
10847     /* VEX_W_0F98_P_0_LEN_0 */
10848     { "kortestw",       { MaskG, MaskR } },
10849     { "kortestq",       { MaskG, MaskR } },
10850   },
10851   {
10852     /* VEX_W_0F98_P_2_LEN_0 */
10853     { "kortestb",       { MaskG, MaskR } },
10854     { "kortestd",       { MaskG, MaskR } },
10855   },
10856   {
10857     /* VEX_W_0F99_P_0_LEN_0 */
10858     { "ktestw", { MaskG, MaskR } },
10859     { "ktestq", { MaskG, MaskR } },
10860   },
10861   {
10862     /* VEX_W_0F99_P_2_LEN_0 */
10863     { "ktestb", { MaskG, MaskR } },
10864     { "ktestd", { MaskG, MaskR } },
10865   },
10866   {
10867     /* VEX_W_0FAE_R_2_M_0 */
10868     { "vldmxcsr",       { Md } },
10869   },
10870   {
10871     /* VEX_W_0FAE_R_3_M_0 */
10872     { "vstmxcsr",       { Md } },
10873   },
10874   {
10875     /* VEX_W_0FC2_P_0 */
10876     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10877   },
10878   {
10879     /* VEX_W_0FC2_P_1 */
10880     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10881   },
10882   {
10883     /* VEX_W_0FC2_P_2 */
10884     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10885   },
10886   {
10887     /* VEX_W_0FC2_P_3 */
10888     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10889   },
10890   {
10891     /* VEX_W_0FC4_P_2 */
10892     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10893   },
10894   {
10895     /* VEX_W_0FC5_P_2 */
10896     { "vpextrw",        { Gdq, XS, Ib } },
10897   },
10898   {
10899     /* VEX_W_0FD0_P_2 */
10900     { "vaddsubpd",      { XM, Vex, EXx } },
10901   },
10902   {
10903     /* VEX_W_0FD0_P_3 */
10904     { "vaddsubps",      { XM, Vex, EXx } },
10905   },
10906   {
10907     /* VEX_W_0FD1_P_2 */
10908     { "vpsrlw",         { XM, Vex, EXxmm } },
10909   },
10910   {
10911     /* VEX_W_0FD2_P_2 */
10912     { "vpsrld",         { XM, Vex, EXxmm } },
10913   },
10914   {
10915     /* VEX_W_0FD3_P_2 */
10916     { "vpsrlq",         { XM, Vex, EXxmm } },
10917   },
10918   {
10919     /* VEX_W_0FD4_P_2 */
10920     { "vpaddq",         { XM, Vex, EXx } },
10921   },
10922   {
10923     /* VEX_W_0FD5_P_2 */
10924     { "vpmullw",        { XM, Vex, EXx } },
10925   },
10926   {
10927     /* VEX_W_0FD6_P_2 */
10928     { "vmovq",          { EXqScalarS, XMScalar } },
10929   },
10930   {
10931     /* VEX_W_0FD7_P_2_M_1 */
10932     { "vpmovmskb",      { Gdq, XS } },
10933   },
10934   {
10935     /* VEX_W_0FD8_P_2 */
10936     { "vpsubusb",       { XM, Vex, EXx } },
10937   },
10938   {
10939     /* VEX_W_0FD9_P_2 */
10940     { "vpsubusw",       { XM, Vex, EXx } },
10941   },
10942   {
10943     /* VEX_W_0FDA_P_2 */
10944     { "vpminub",        { XM, Vex, EXx } },
10945   },
10946   {
10947     /* VEX_W_0FDB_P_2 */
10948     { "vpand",          { XM, Vex, EXx } },
10949   },
10950   {
10951     /* VEX_W_0FDC_P_2 */
10952     { "vpaddusb",       { XM, Vex, EXx } },
10953   },
10954   {
10955     /* VEX_W_0FDD_P_2 */
10956     { "vpaddusw",       { XM, Vex, EXx } },
10957   },
10958   {
10959     /* VEX_W_0FDE_P_2 */
10960     { "vpmaxub",        { XM, Vex, EXx } },
10961   },
10962   {
10963     /* VEX_W_0FDF_P_2 */
10964     { "vpandn",         { XM, Vex, EXx } },
10965   },
10966   {
10967     /* VEX_W_0FE0_P_2  */
10968     { "vpavgb",         { XM, Vex, EXx } },
10969   },
10970   {
10971     /* VEX_W_0FE1_P_2  */
10972     { "vpsraw",         { XM, Vex, EXxmm } },
10973   },
10974   {
10975     /* VEX_W_0FE2_P_2  */
10976     { "vpsrad",         { XM, Vex, EXxmm } },
10977   },
10978   {
10979     /* VEX_W_0FE3_P_2  */
10980     { "vpavgw",         { XM, Vex, EXx } },
10981   },
10982   {
10983     /* VEX_W_0FE4_P_2  */
10984     { "vpmulhuw",       { XM, Vex, EXx } },
10985   },
10986   {
10987     /* VEX_W_0FE5_P_2  */
10988     { "vpmulhw",        { XM, Vex, EXx } },
10989   },
10990   {
10991     /* VEX_W_0FE6_P_1  */
10992     { "vcvtdq2pd",      { XM, EXxmmq } },
10993   },
10994   {
10995     /* VEX_W_0FE6_P_2  */
10996     { "vcvttpd2dq%XY",  { XMM, EXx } },
10997   },
10998   {
10999     /* VEX_W_0FE6_P_3  */
11000     { "vcvtpd2dq%XY",   { XMM, EXx } },
11001   },
11002   {
11003     /* VEX_W_0FE7_P_2_M_0 */
11004     { "vmovntdq",       { Mx, XM } },
11005   },
11006   {
11007     /* VEX_W_0FE8_P_2  */
11008     { "vpsubsb",        { XM, Vex, EXx } },
11009   },
11010   {
11011     /* VEX_W_0FE9_P_2  */
11012     { "vpsubsw",        { XM, Vex, EXx } },
11013   },
11014   {
11015     /* VEX_W_0FEA_P_2  */
11016     { "vpminsw",        { XM, Vex, EXx } },
11017   },
11018   {
11019     /* VEX_W_0FEB_P_2  */
11020     { "vpor",           { XM, Vex, EXx } },
11021   },
11022   {
11023     /* VEX_W_0FEC_P_2  */
11024     { "vpaddsb",        { XM, Vex, EXx } },
11025   },
11026   {
11027     /* VEX_W_0FED_P_2  */
11028     { "vpaddsw",        { XM, Vex, EXx } },
11029   },
11030   {
11031     /* VEX_W_0FEE_P_2  */
11032     { "vpmaxsw",        { XM, Vex, EXx } },
11033   },
11034   {
11035     /* VEX_W_0FEF_P_2  */
11036     { "vpxor",          { XM, Vex, EXx } },
11037   },
11038   {
11039     /* VEX_W_0FF0_P_3_M_0 */
11040     { "vlddqu",         { XM, M } },
11041   },
11042   {
11043     /* VEX_W_0FF1_P_2 */
11044     { "vpsllw",         { XM, Vex, EXxmm } },
11045   },
11046   {
11047     /* VEX_W_0FF2_P_2 */
11048     { "vpslld",         { XM, Vex, EXxmm } },
11049   },
11050   {
11051     /* VEX_W_0FF3_P_2 */
11052     { "vpsllq",         { XM, Vex, EXxmm } },
11053   },
11054   {
11055     /* VEX_W_0FF4_P_2 */
11056     { "vpmuludq",       { XM, Vex, EXx } },
11057   },
11058   {
11059     /* VEX_W_0FF5_P_2 */
11060     { "vpmaddwd",       { XM, Vex, EXx } },
11061   },
11062   {
11063     /* VEX_W_0FF6_P_2 */
11064     { "vpsadbw",        { XM, Vex, EXx } },
11065   },
11066   {
11067     /* VEX_W_0FF7_P_2 */
11068     { "vmaskmovdqu",    { XM, XS } },
11069   },
11070   {
11071     /* VEX_W_0FF8_P_2 */
11072     { "vpsubb",         { XM, Vex, EXx } },
11073   },
11074   {
11075     /* VEX_W_0FF9_P_2 */
11076     { "vpsubw",         { XM, Vex, EXx } },
11077   },
11078   {
11079     /* VEX_W_0FFA_P_2 */
11080     { "vpsubd",         { XM, Vex, EXx } },
11081   },
11082   {
11083     /* VEX_W_0FFB_P_2 */
11084     { "vpsubq",         { XM, Vex, EXx } },
11085   },
11086   {
11087     /* VEX_W_0FFC_P_2 */
11088     { "vpaddb",         { XM, Vex, EXx } },
11089   },
11090   {
11091     /* VEX_W_0FFD_P_2 */
11092     { "vpaddw",         { XM, Vex, EXx } },
11093   },
11094   {
11095     /* VEX_W_0FFE_P_2 */
11096     { "vpaddd",         { XM, Vex, EXx } },
11097   },
11098   {
11099     /* VEX_W_0F3800_P_2  */
11100     { "vpshufb",        { XM, Vex, EXx } },
11101   },
11102   {
11103     /* VEX_W_0F3801_P_2  */
11104     { "vphaddw",        { XM, Vex, EXx } },
11105   },
11106   {
11107     /* VEX_W_0F3802_P_2  */
11108     { "vphaddd",        { XM, Vex, EXx } },
11109   },
11110   {
11111     /* VEX_W_0F3803_P_2  */
11112     { "vphaddsw",       { XM, Vex, EXx } },
11113   },
11114   {
11115     /* VEX_W_0F3804_P_2  */
11116     { "vpmaddubsw",     { XM, Vex, EXx } },
11117   },
11118   {
11119     /* VEX_W_0F3805_P_2  */
11120     { "vphsubw",        { XM, Vex, EXx } },
11121   },
11122   {
11123     /* VEX_W_0F3806_P_2  */
11124     { "vphsubd",        { XM, Vex, EXx } },
11125   },
11126   {
11127     /* VEX_W_0F3807_P_2  */
11128     { "vphsubsw",       { XM, Vex, EXx } },
11129   },
11130   {
11131     /* VEX_W_0F3808_P_2  */
11132     { "vpsignb",        { XM, Vex, EXx } },
11133   },
11134   {
11135     /* VEX_W_0F3809_P_2  */
11136     { "vpsignw",        { XM, Vex, EXx } },
11137   },
11138   {
11139     /* VEX_W_0F380A_P_2  */
11140     { "vpsignd",        { XM, Vex, EXx } },
11141   },
11142   {
11143     /* VEX_W_0F380B_P_2  */
11144     { "vpmulhrsw",      { XM, Vex, EXx } },
11145   },
11146   {
11147     /* VEX_W_0F380C_P_2  */
11148     { "vpermilps",      { XM, Vex, EXx } },
11149   },
11150   {
11151     /* VEX_W_0F380D_P_2  */
11152     { "vpermilpd",      { XM, Vex, EXx } },
11153   },
11154   {
11155     /* VEX_W_0F380E_P_2  */
11156     { "vtestps",        { XM, EXx } },
11157   },
11158   {
11159     /* VEX_W_0F380F_P_2  */
11160     { "vtestpd",        { XM, EXx } },
11161   },
11162   {
11163     /* VEX_W_0F3816_P_2  */
11164     { "vpermps",        { XM, Vex, EXx } },
11165   },
11166   {
11167     /* VEX_W_0F3817_P_2 */
11168     { "vptest",         { XM, EXx } },
11169   },
11170   {
11171     /* VEX_W_0F3818_P_2 */
11172     { "vbroadcastss",   { XM, EXxmm_md } },
11173   },
11174   {
11175     /* VEX_W_0F3819_P_2 */
11176     { "vbroadcastsd",   { XM, EXxmm_mq } },
11177   },
11178   {
11179     /* VEX_W_0F381A_P_2_M_0 */
11180     { "vbroadcastf128", { XM, Mxmm } },
11181   },
11182   {
11183     /* VEX_W_0F381C_P_2 */
11184     { "vpabsb",         { XM, EXx } },
11185   },
11186   {
11187     /* VEX_W_0F381D_P_2 */
11188     { "vpabsw",         { XM, EXx } },
11189   },
11190   {
11191     /* VEX_W_0F381E_P_2 */
11192     { "vpabsd",         { XM, EXx } },
11193   },
11194   {
11195     /* VEX_W_0F3820_P_2 */
11196     { "vpmovsxbw",      { XM, EXxmmq } },
11197   },
11198   {
11199     /* VEX_W_0F3821_P_2 */
11200     { "vpmovsxbd",      { XM, EXxmmqd } },
11201   },
11202   {
11203     /* VEX_W_0F3822_P_2 */
11204     { "vpmovsxbq",      { XM, EXxmmdw } },
11205   },
11206   {
11207     /* VEX_W_0F3823_P_2 */
11208     { "vpmovsxwd",      { XM, EXxmmq } },
11209   },
11210   {
11211     /* VEX_W_0F3824_P_2 */
11212     { "vpmovsxwq",      { XM, EXxmmqd } },
11213   },
11214   {
11215     /* VEX_W_0F3825_P_2 */
11216     { "vpmovsxdq",      { XM, EXxmmq } },
11217   },
11218   {
11219     /* VEX_W_0F3828_P_2 */
11220     { "vpmuldq",        { XM, Vex, EXx } },
11221   },
11222   {
11223     /* VEX_W_0F3829_P_2 */
11224     { "vpcmpeqq",       { XM, Vex, EXx } },
11225   },
11226   {
11227     /* VEX_W_0F382A_P_2_M_0 */
11228     { "vmovntdqa",      { XM, Mx } },
11229   },
11230   {
11231     /* VEX_W_0F382B_P_2 */
11232     { "vpackusdw",      { XM, Vex, EXx } },
11233   },
11234   {
11235     /* VEX_W_0F382C_P_2_M_0 */
11236     { "vmaskmovps",     { XM, Vex, Mx } },
11237   },
11238   {
11239     /* VEX_W_0F382D_P_2_M_0 */
11240     { "vmaskmovpd",     { XM, Vex, Mx } },
11241   },
11242   {
11243     /* VEX_W_0F382E_P_2_M_0 */
11244     { "vmaskmovps",     { Mx, Vex, XM } },
11245   },
11246   {
11247     /* VEX_W_0F382F_P_2_M_0 */
11248     { "vmaskmovpd",     { Mx, Vex, XM } },
11249   },
11250   {
11251     /* VEX_W_0F3830_P_2 */
11252     { "vpmovzxbw",      { XM, EXxmmq } },
11253   },
11254   {
11255     /* VEX_W_0F3831_P_2 */
11256     { "vpmovzxbd",      { XM, EXxmmqd } },
11257   },
11258   {
11259     /* VEX_W_0F3832_P_2 */
11260     { "vpmovzxbq",      { XM, EXxmmdw } },
11261   },
11262   {
11263     /* VEX_W_0F3833_P_2 */
11264     { "vpmovzxwd",      { XM, EXxmmq } },
11265   },
11266   {
11267     /* VEX_W_0F3834_P_2 */
11268     { "vpmovzxwq",      { XM, EXxmmqd } },
11269   },
11270   {
11271     /* VEX_W_0F3835_P_2 */
11272     { "vpmovzxdq",      { XM, EXxmmq } },
11273   },
11274   {
11275     /* VEX_W_0F3836_P_2  */
11276     { "vpermd",         { XM, Vex, EXx } },
11277   },
11278   {
11279     /* VEX_W_0F3837_P_2 */
11280     { "vpcmpgtq",       { XM, Vex, EXx } },
11281   },
11282   {
11283     /* VEX_W_0F3838_P_2 */
11284     { "vpminsb",        { XM, Vex, EXx } },
11285   },
11286   {
11287     /* VEX_W_0F3839_P_2 */
11288     { "vpminsd",        { XM, Vex, EXx } },
11289   },
11290   {
11291     /* VEX_W_0F383A_P_2 */
11292     { "vpminuw",        { XM, Vex, EXx } },
11293   },
11294   {
11295     /* VEX_W_0F383B_P_2 */
11296     { "vpminud",        { XM, Vex, EXx } },
11297   },
11298   {
11299     /* VEX_W_0F383C_P_2 */
11300     { "vpmaxsb",        { XM, Vex, EXx } },
11301   },
11302   {
11303     /* VEX_W_0F383D_P_2 */
11304     { "vpmaxsd",        { XM, Vex, EXx } },
11305   },
11306   {
11307     /* VEX_W_0F383E_P_2 */
11308     { "vpmaxuw",        { XM, Vex, EXx } },
11309   },
11310   {
11311     /* VEX_W_0F383F_P_2 */
11312     { "vpmaxud",        { XM, Vex, EXx } },
11313   },
11314   {
11315     /* VEX_W_0F3840_P_2 */
11316     { "vpmulld",        { XM, Vex, EXx } },
11317   },
11318   {
11319     /* VEX_W_0F3841_P_2 */
11320     { "vphminposuw",    { XM, EXx } },
11321   },
11322   {
11323     /* VEX_W_0F3846_P_2 */
11324     { "vpsravd",        { XM, Vex, EXx } },
11325   },
11326   {
11327     /* VEX_W_0F3858_P_2 */
11328     { "vpbroadcastd", { XM, EXxmm_md } },
11329   },
11330   {
11331     /* VEX_W_0F3859_P_2 */
11332     { "vpbroadcastq",   { XM, EXxmm_mq } },
11333   },
11334   {
11335     /* VEX_W_0F385A_P_2_M_0 */
11336     { "vbroadcasti128", { XM, Mxmm } },
11337   },
11338   {
11339     /* VEX_W_0F3878_P_2 */
11340     { "vpbroadcastb",   { XM, EXxmm_mb } },
11341   },
11342   {
11343     /* VEX_W_0F3879_P_2 */
11344     { "vpbroadcastw",   { XM, EXxmm_mw } },
11345   },
11346   {
11347     /* VEX_W_0F38DB_P_2 */
11348     { "vaesimc",        { XM, EXx } },
11349   },
11350   {
11351     /* VEX_W_0F38DC_P_2 */
11352     { "vaesenc",        { XM, Vex128, EXx } },
11353   },
11354   {
11355     /* VEX_W_0F38DD_P_2 */
11356     { "vaesenclast",    { XM, Vex128, EXx } },
11357   },
11358   {
11359     /* VEX_W_0F38DE_P_2 */
11360     { "vaesdec",        { XM, Vex128, EXx } },
11361   },
11362   {
11363     /* VEX_W_0F38DF_P_2 */
11364     { "vaesdeclast",    { XM, Vex128, EXx } },
11365   },
11366   {
11367     /* VEX_W_0F3A00_P_2 */
11368     { Bad_Opcode },
11369     { "vpermq",         { XM, EXx, Ib } },
11370   },
11371   {
11372     /* VEX_W_0F3A01_P_2 */
11373     { Bad_Opcode },
11374     { "vpermpd",        { XM, EXx, Ib } },
11375   },
11376   {
11377     /* VEX_W_0F3A02_P_2 */
11378     { "vpblendd",       { XM, Vex, EXx, Ib } },
11379   },
11380   {
11381     /* VEX_W_0F3A04_P_2 */
11382     { "vpermilps",      { XM, EXx, Ib } },
11383   },
11384   {
11385     /* VEX_W_0F3A05_P_2 */
11386     { "vpermilpd",      { XM, EXx, Ib } },
11387   },
11388   {
11389     /* VEX_W_0F3A06_P_2 */
11390     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
11391   },
11392   {
11393     /* VEX_W_0F3A08_P_2 */
11394     { "vroundps",       { XM, EXx, Ib } },
11395   },
11396   {
11397     /* VEX_W_0F3A09_P_2 */
11398     { "vroundpd",       { XM, EXx, Ib } },
11399   },
11400   {
11401     /* VEX_W_0F3A0A_P_2 */
11402     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
11403   },
11404   {
11405     /* VEX_W_0F3A0B_P_2 */
11406     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
11407   },
11408   {
11409     /* VEX_W_0F3A0C_P_2 */
11410     { "vblendps",       { XM, Vex, EXx, Ib } },
11411   },
11412   {
11413     /* VEX_W_0F3A0D_P_2 */
11414     { "vblendpd",       { XM, Vex, EXx, Ib } },
11415   },
11416   {
11417     /* VEX_W_0F3A0E_P_2 */
11418     { "vpblendw",       { XM, Vex, EXx, Ib } },
11419   },
11420   {
11421     /* VEX_W_0F3A0F_P_2 */
11422     { "vpalignr",       { XM, Vex, EXx, Ib } },
11423   },
11424   {
11425     /* VEX_W_0F3A14_P_2 */
11426     { "vpextrb",        { Edqb, XM, Ib } },
11427   },
11428   {
11429     /* VEX_W_0F3A15_P_2 */
11430     { "vpextrw",        { Edqw, XM, Ib } },
11431   },
11432   {
11433     /* VEX_W_0F3A18_P_2 */
11434     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
11435   },
11436   {
11437     /* VEX_W_0F3A19_P_2 */
11438     { "vextractf128",   { EXxmm, XM, Ib } },
11439   },
11440   {
11441     /* VEX_W_0F3A20_P_2 */
11442     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
11443   },
11444   {
11445     /* VEX_W_0F3A21_P_2 */
11446     { "vinsertps",      { XM, Vex128, EXd, Ib } },
11447   },
11448   {
11449     /* VEX_W_0F3A30_P_2_LEN_0 */
11450     { "kshiftrb",       { MaskG, MaskR, Ib } },
11451     { "kshiftrw",       { MaskG, MaskR, Ib } },
11452   },
11453   {
11454     /* VEX_W_0F3A31_P_2_LEN_0 */
11455     { "kshiftrd",       { MaskG, MaskR, Ib } },
11456     { "kshiftrq",       { MaskG, MaskR, Ib } },
11457   },
11458   {
11459     /* VEX_W_0F3A32_P_2_LEN_0 */
11460     { "kshiftlb",       { MaskG, MaskR, Ib } },
11461     { "kshiftlw",       { MaskG, MaskR, Ib } },
11462   },
11463   {
11464     /* VEX_W_0F3A33_P_2_LEN_0 */
11465     { "kshiftld",       { MaskG, MaskR, Ib } },
11466     { "kshiftlq",       { MaskG, MaskR, Ib } },
11467   },
11468   {
11469     /* VEX_W_0F3A38_P_2 */
11470     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
11471   },
11472   {
11473     /* VEX_W_0F3A39_P_2 */
11474     { "vextracti128",   { EXxmm, XM, Ib } },
11475   },
11476   {
11477     /* VEX_W_0F3A40_P_2 */
11478     { "vdpps",          { XM, Vex, EXx, Ib } },
11479   },
11480   {
11481     /* VEX_W_0F3A41_P_2 */
11482     { "vdppd",          { XM, Vex128, EXx, Ib } },
11483   },
11484   {
11485     /* VEX_W_0F3A42_P_2 */
11486     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
11487   },
11488   {
11489     /* VEX_W_0F3A44_P_2 */
11490     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
11491   },
11492   {
11493     /* VEX_W_0F3A46_P_2 */
11494     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11495   },
11496   {
11497     /* VEX_W_0F3A48_P_2 */
11498     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11499     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11500   },
11501   {
11502     /* VEX_W_0F3A49_P_2 */
11503     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11504     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11505   },
11506   {
11507     /* VEX_W_0F3A4A_P_2 */
11508     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11509   },
11510   {
11511     /* VEX_W_0F3A4B_P_2 */
11512     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11513   },
11514   {
11515     /* VEX_W_0F3A4C_P_2 */
11516     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11517   },
11518   {
11519     /* VEX_W_0F3A60_P_2 */
11520     { "vpcmpestrm",     { XM, EXx, Ib } },
11521   },
11522   {
11523     /* VEX_W_0F3A61_P_2 */
11524     { "vpcmpestri",     { XM, EXx, Ib } },
11525   },
11526   {
11527     /* VEX_W_0F3A62_P_2 */
11528     { "vpcmpistrm",     { XM, EXx, Ib } },
11529   },
11530   {
11531     /* VEX_W_0F3A63_P_2 */
11532     { "vpcmpistri",     { XM, EXx, Ib } },
11533   },
11534   {
11535     /* VEX_W_0F3ADF_P_2 */
11536     { "vaeskeygenassist", { XM, EXx, Ib } },
11537   },
11538 #define NEED_VEX_W_TABLE
11539 #include "i386-dis-evex.h"
11540 #undef NEED_VEX_W_TABLE
11541 };
11542
11543 static const struct dis386 mod_table[][2] = {
11544   {
11545     /* MOD_8D */
11546     { "leaS",           { Gv, M } },
11547   },
11548   {
11549     /* MOD_C6_REG_7 */
11550     { Bad_Opcode },
11551     { RM_TABLE (RM_C6_REG_7) },
11552   },
11553   {
11554     /* MOD_C7_REG_7 */
11555     { Bad_Opcode },
11556     { RM_TABLE (RM_C7_REG_7) },
11557   },
11558   {
11559     /* MOD_FF_REG_3 */
11560     { "Jcall{T|}", { indirEp } },
11561   },
11562   {
11563     /* MOD_FF_REG_5 */
11564     { "Jjmp{T|}", { indirEp } },
11565   },
11566   {
11567     /* MOD_0F01_REG_0 */
11568     { X86_64_TABLE (X86_64_0F01_REG_0) },
11569     { RM_TABLE (RM_0F01_REG_0) },
11570   },
11571   {
11572     /* MOD_0F01_REG_1 */
11573     { X86_64_TABLE (X86_64_0F01_REG_1) },
11574     { RM_TABLE (RM_0F01_REG_1) },
11575   },
11576   {
11577     /* MOD_0F01_REG_2 */
11578     { X86_64_TABLE (X86_64_0F01_REG_2) },
11579     { RM_TABLE (RM_0F01_REG_2) },
11580   },
11581   {
11582     /* MOD_0F01_REG_3 */
11583     { X86_64_TABLE (X86_64_0F01_REG_3) },
11584     { RM_TABLE (RM_0F01_REG_3) },
11585   },
11586   {
11587     /* MOD_0F01_REG_7 */
11588     { "invlpg",         { Mb } },
11589     { RM_TABLE (RM_0F01_REG_7) },
11590   },
11591   {
11592     /* MOD_0F12_PREFIX_0 */
11593     { "movlps",         { XM, EXq } },
11594     { "movhlps",        { XM, EXq } },
11595   },
11596   {
11597     /* MOD_0F13 */
11598     { "movlpX",         { EXq, XM } },
11599   },
11600   {
11601     /* MOD_0F16_PREFIX_0 */
11602     { "movhps",         { XM, EXq } },
11603     { "movlhps",        { XM, EXq } },
11604   },
11605   {
11606     /* MOD_0F17 */
11607     { "movhpX",         { EXq, XM } },
11608   },
11609   {
11610     /* MOD_0F18_REG_0 */
11611     { "prefetchnta",    { Mb } },
11612   },
11613   {
11614     /* MOD_0F18_REG_1 */
11615     { "prefetcht0",     { Mb } },
11616   },
11617   {
11618     /* MOD_0F18_REG_2 */
11619     { "prefetcht1",     { Mb } },
11620   },
11621   {
11622     /* MOD_0F18_REG_3 */
11623     { "prefetcht2",     { Mb } },
11624   },
11625   {
11626     /* MOD_0F18_REG_4 */
11627     { "nop/reserved",   { Mb } },
11628   },
11629   {
11630     /* MOD_0F18_REG_5 */
11631     { "nop/reserved",   { Mb } },
11632   },
11633   {
11634     /* MOD_0F18_REG_6 */
11635     { "nop/reserved",   { Mb } },
11636   },
11637   {
11638     /* MOD_0F18_REG_7 */
11639     { "nop/reserved",   { Mb } },
11640   },
11641   {
11642     /* MOD_0F1A_PREFIX_0 */
11643     { "bndldx",         { Gbnd, Ev_bnd } },
11644     { "nopQ",           { Ev } },
11645   },
11646   {
11647     /* MOD_0F1B_PREFIX_0 */
11648     { "bndstx",         { Ev_bnd, Gbnd } },
11649     { "nopQ",           { Ev } },
11650   },
11651   {
11652     /* MOD_0F1B_PREFIX_1 */
11653     { "bndmk",          { Gbnd, Ev_bnd } },
11654     { "nopQ",           { Ev } },
11655   },
11656   {
11657     /* MOD_0F24 */
11658     { Bad_Opcode },
11659     { "movL",           { Rd, Td } },
11660   },
11661   {
11662     /* MOD_0F26 */
11663     { Bad_Opcode },
11664     { "movL",           { Td, Rd } },
11665   },
11666   {
11667     /* MOD_0F2B_PREFIX_0 */
11668     {"movntps",         { Mx, XM } },
11669   },
11670   {
11671     /* MOD_0F2B_PREFIX_1 */
11672     {"movntss",         { Md, XM } },
11673   },
11674   {
11675     /* MOD_0F2B_PREFIX_2 */
11676     {"movntpd",         { Mx, XM } },
11677   },
11678   {
11679     /* MOD_0F2B_PREFIX_3 */
11680     {"movntsd",         { Mq, XM } },
11681   },
11682   {
11683     /* MOD_0F51 */
11684     { Bad_Opcode },
11685     { "movmskpX",       { Gdq, XS } },
11686   },
11687   {
11688     /* MOD_0F71_REG_2 */
11689     { Bad_Opcode },
11690     { "psrlw",          { MS, Ib } },
11691   },
11692   {
11693     /* MOD_0F71_REG_4 */
11694     { Bad_Opcode },
11695     { "psraw",          { MS, Ib } },
11696   },
11697   {
11698     /* MOD_0F71_REG_6 */
11699     { Bad_Opcode },
11700     { "psllw",          { MS, Ib } },
11701   },
11702   {
11703     /* MOD_0F72_REG_2 */
11704     { Bad_Opcode },
11705     { "psrld",          { MS, Ib } },
11706   },
11707   {
11708     /* MOD_0F72_REG_4 */
11709     { Bad_Opcode },
11710     { "psrad",          { MS, Ib } },
11711   },
11712   {
11713     /* MOD_0F72_REG_6 */
11714     { Bad_Opcode },
11715     { "pslld",          { MS, Ib } },
11716   },
11717   {
11718     /* MOD_0F73_REG_2 */
11719     { Bad_Opcode },
11720     { "psrlq",          { MS, Ib } },
11721   },
11722   {
11723     /* MOD_0F73_REG_3 */
11724     { Bad_Opcode },
11725     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11726   },
11727   {
11728     /* MOD_0F73_REG_6 */
11729     { Bad_Opcode },
11730     { "psllq",          { MS, Ib } },
11731   },
11732   {
11733     /* MOD_0F73_REG_7 */
11734     { Bad_Opcode },
11735     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11736   },
11737   {
11738     /* MOD_0FAE_REG_0 */
11739     { "fxsave",         { FXSAVE } },
11740     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11741   },
11742   {
11743     /* MOD_0FAE_REG_1 */
11744     { "fxrstor",        { FXSAVE } },
11745     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11746   },
11747   {
11748     /* MOD_0FAE_REG_2 */
11749     { "ldmxcsr",        { Md } },
11750     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11751   },
11752   {
11753     /* MOD_0FAE_REG_3 */
11754     { "stmxcsr",        { Md } },
11755     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11756   },
11757   {
11758     /* MOD_0FAE_REG_4 */
11759     { "xsave",          { FXSAVE } },
11760   },
11761   {
11762     /* MOD_0FAE_REG_5 */
11763     { "xrstor",         { FXSAVE } },
11764     { RM_TABLE (RM_0FAE_REG_5) },
11765   },
11766   {
11767     /* MOD_0FAE_REG_6 */
11768     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11769     { RM_TABLE (RM_0FAE_REG_6) },
11770   },
11771   {
11772     /* MOD_0FAE_REG_7 */
11773     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11774     { RM_TABLE (RM_0FAE_REG_7) },
11775   },
11776   {
11777     /* MOD_0FB2 */
11778     { "lssS",           { Gv, Mp } },
11779   },
11780   {
11781     /* MOD_0FB4 */
11782     { "lfsS",           { Gv, Mp } },
11783   },
11784   {
11785     /* MOD_0FB5 */
11786     { "lgsS",           { Gv, Mp } },
11787   },
11788   {
11789     /* MOD_0FC7_REG_3 */
11790     { "xrstors",                { FXSAVE } },
11791   },
11792   {
11793     /* MOD_0FC7_REG_4 */
11794     { "xsavec",         { FXSAVE } },
11795   },
11796   {
11797     /* MOD_0FC7_REG_5 */
11798     { "xsaves",         { FXSAVE } },
11799   },
11800   {
11801     /* MOD_0FC7_REG_6 */
11802     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11803     { "rdrand",         { Ev } },
11804   },
11805   {
11806     /* MOD_0FC7_REG_7 */
11807     { "vmptrst",        { Mq } },
11808     { "rdseed",         { Ev } },
11809   },
11810   {
11811     /* MOD_0FD7 */
11812     { Bad_Opcode },
11813     { "pmovmskb",       { Gdq, MS } },
11814   },
11815   {
11816     /* MOD_0FE7_PREFIX_2 */
11817     { "movntdq",        { Mx, XM } },
11818   },
11819   {
11820     /* MOD_0FF0_PREFIX_3 */
11821     { "lddqu",          { XM, M } },
11822   },
11823   {
11824     /* MOD_0F382A_PREFIX_2 */
11825     { "movntdqa",       { XM, Mx } },
11826   },
11827   {
11828     /* MOD_62_32BIT */
11829     { "bound{S|}",      { Gv, Ma } },
11830     { EVEX_TABLE (EVEX_0F) },
11831   },
11832   {
11833     /* MOD_C4_32BIT */
11834     { "lesS",           { Gv, Mp } },
11835     { VEX_C4_TABLE (VEX_0F) },
11836   },
11837   {
11838     /* MOD_C5_32BIT */
11839     { "ldsS",           { Gv, Mp } },
11840     { VEX_C5_TABLE (VEX_0F) },
11841   },
11842   {
11843     /* MOD_VEX_0F12_PREFIX_0 */
11844     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11845     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11846   },
11847   {
11848     /* MOD_VEX_0F13 */
11849     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11850   },
11851   {
11852     /* MOD_VEX_0F16_PREFIX_0 */
11853     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11854     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11855   },
11856   {
11857     /* MOD_VEX_0F17 */
11858     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11859   },
11860   {
11861     /* MOD_VEX_0F2B */
11862     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11863   },
11864   {
11865     /* MOD_VEX_0F50 */
11866     { Bad_Opcode },
11867     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11868   },
11869   {
11870     /* MOD_VEX_0F71_REG_2 */
11871     { Bad_Opcode },
11872     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11873   },
11874   {
11875     /* MOD_VEX_0F71_REG_4 */
11876     { Bad_Opcode },
11877     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11878   },
11879   {
11880     /* MOD_VEX_0F71_REG_6 */
11881     { Bad_Opcode },
11882     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11883   },
11884   {
11885     /* MOD_VEX_0F72_REG_2 */
11886     { Bad_Opcode },
11887     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11888   },
11889   {
11890     /* MOD_VEX_0F72_REG_4 */
11891     { Bad_Opcode },
11892     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11893   },
11894   {
11895     /* MOD_VEX_0F72_REG_6 */
11896     { Bad_Opcode },
11897     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11898   },
11899   {
11900     /* MOD_VEX_0F73_REG_2 */
11901     { Bad_Opcode },
11902     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11903   },
11904   {
11905     /* MOD_VEX_0F73_REG_3 */
11906     { Bad_Opcode },
11907     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11908   },
11909   {
11910     /* MOD_VEX_0F73_REG_6 */
11911     { Bad_Opcode },
11912     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11913   },
11914   {
11915     /* MOD_VEX_0F73_REG_7 */
11916     { Bad_Opcode },
11917     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11918   },
11919   {
11920     /* MOD_VEX_0FAE_REG_2 */
11921     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11922   },
11923   {
11924     /* MOD_VEX_0FAE_REG_3 */
11925     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11926   },
11927   {
11928     /* MOD_VEX_0FD7_PREFIX_2 */
11929     { Bad_Opcode },
11930     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11931   },
11932   {
11933     /* MOD_VEX_0FE7_PREFIX_2 */
11934     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11935   },
11936   {
11937     /* MOD_VEX_0FF0_PREFIX_3 */
11938     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11939   },
11940   {
11941     /* MOD_VEX_0F381A_PREFIX_2 */
11942     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11943   },
11944   {
11945     /* MOD_VEX_0F382A_PREFIX_2 */
11946     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11947   },
11948   {
11949     /* MOD_VEX_0F382C_PREFIX_2 */
11950     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11951   },
11952   {
11953     /* MOD_VEX_0F382D_PREFIX_2 */
11954     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11955   },
11956   {
11957     /* MOD_VEX_0F382E_PREFIX_2 */
11958     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11959   },
11960   {
11961     /* MOD_VEX_0F382F_PREFIX_2 */
11962     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11963   },
11964   {
11965     /* MOD_VEX_0F385A_PREFIX_2 */
11966     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11967   },
11968   {
11969     /* MOD_VEX_0F388C_PREFIX_2 */
11970     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11971   },
11972   {
11973     /* MOD_VEX_0F388E_PREFIX_2 */
11974     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11975   },
11976 #define NEED_MOD_TABLE
11977 #include "i386-dis-evex.h"
11978 #undef NEED_MOD_TABLE
11979 };
11980
11981 static const struct dis386 rm_table[][8] = {
11982   {
11983     /* RM_C6_REG_7 */
11984     { "xabort",         { Skip_MODRM, Ib } },
11985   },
11986   {
11987     /* RM_C7_REG_7 */
11988     { "xbeginT",        { Skip_MODRM, Jv } },
11989   },
11990   {
11991     /* RM_0F01_REG_0 */
11992     { Bad_Opcode },
11993     { "vmcall",         { Skip_MODRM } },
11994     { "vmlaunch",       { Skip_MODRM } },
11995     { "vmresume",       { Skip_MODRM } },
11996     { "vmxoff",         { Skip_MODRM } },
11997   },
11998   {
11999     /* RM_0F01_REG_1 */
12000     { "monitor",        { { OP_Monitor, 0 } } },
12001     { "mwait",          { { OP_Mwait, 0 } } },
12002     { "clac",           { Skip_MODRM } },
12003     { "stac",           { Skip_MODRM } },
12004     { Bad_Opcode },
12005     { Bad_Opcode },
12006     { Bad_Opcode },
12007     { "encls",          { Skip_MODRM } },
12008   },
12009   {
12010     /* RM_0F01_REG_2 */
12011     { "xgetbv",         { Skip_MODRM } },
12012     { "xsetbv",         { Skip_MODRM } },
12013     { Bad_Opcode },
12014     { Bad_Opcode },
12015     { "vmfunc",         { Skip_MODRM } },
12016     { "xend",           { Skip_MODRM } },
12017     { "xtest",          { Skip_MODRM } },
12018     { "enclu",          { Skip_MODRM } },
12019   },
12020   {
12021     /* RM_0F01_REG_3 */
12022     { "vmrun",          { Skip_MODRM } },
12023     { "vmmcall",        { Skip_MODRM } },
12024     { "vmload",         { Skip_MODRM } },
12025     { "vmsave",         { Skip_MODRM } },
12026     { "stgi",           { Skip_MODRM } },
12027     { "clgi",           { Skip_MODRM } },
12028     { "skinit",         { Skip_MODRM } },
12029     { "invlpga",        { Skip_MODRM } },
12030   },
12031   {
12032     /* RM_0F01_REG_7 */
12033     { "swapgs",         { Skip_MODRM } },
12034     { "rdtscp",         { Skip_MODRM } },
12035   },
12036   {
12037     /* RM_0FAE_REG_5 */
12038     { "lfence",         { Skip_MODRM } },
12039   },
12040   {
12041     /* RM_0FAE_REG_6 */
12042     { "mfence",         { Skip_MODRM } },
12043   },
12044   {
12045     /* RM_0FAE_REG_7 */
12046     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12047   },
12048 };
12049
12050 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12051
12052 /* We use the high bit to indicate different name for the same
12053    prefix.  */
12054 #define REP_PREFIX      (0xf3 | 0x100)
12055 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12056 #define XRELEASE_PREFIX (0xf3 | 0x400)
12057 #define BND_PREFIX      (0xf2 | 0x400)
12058
12059 static int
12060 ckprefix (void)
12061 {
12062   int newrex, i, length;
12063   rex = 0;
12064   rex_ignored = 0;
12065   prefixes = 0;
12066   used_prefixes = 0;
12067   rex_used = 0;
12068   last_lock_prefix = -1;
12069   last_repz_prefix = -1;
12070   last_repnz_prefix = -1;
12071   last_data_prefix = -1;
12072   last_addr_prefix = -1;
12073   last_rex_prefix = -1;
12074   last_seg_prefix = -1;
12075   fwait_prefix = -1;
12076   active_seg_prefix = 0;
12077   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12078     all_prefixes[i] = 0;
12079   i = 0;
12080   length = 0;
12081   /* The maximum instruction length is 15bytes.  */
12082   while (length < MAX_CODE_LENGTH - 1)
12083     {
12084       FETCH_DATA (the_info, codep + 1);
12085       newrex = 0;
12086       switch (*codep)
12087         {
12088         /* REX prefixes family.  */
12089         case 0x40:
12090         case 0x41:
12091         case 0x42:
12092         case 0x43:
12093         case 0x44:
12094         case 0x45:
12095         case 0x46:
12096         case 0x47:
12097         case 0x48:
12098         case 0x49:
12099         case 0x4a:
12100         case 0x4b:
12101         case 0x4c:
12102         case 0x4d:
12103         case 0x4e:
12104         case 0x4f:
12105           if (address_mode == mode_64bit)
12106             newrex = *codep;
12107           else
12108             return 1;
12109           last_rex_prefix = i;
12110           break;
12111         case 0xf3:
12112           prefixes |= PREFIX_REPZ;
12113           last_repz_prefix = i;
12114           break;
12115         case 0xf2:
12116           prefixes |= PREFIX_REPNZ;
12117           last_repnz_prefix = i;
12118           break;
12119         case 0xf0:
12120           prefixes |= PREFIX_LOCK;
12121           last_lock_prefix = i;
12122           break;
12123         case 0x2e:
12124           prefixes |= PREFIX_CS;
12125           last_seg_prefix = i;
12126           active_seg_prefix = PREFIX_CS;
12127           break;
12128         case 0x36:
12129           prefixes |= PREFIX_SS;
12130           last_seg_prefix = i;
12131           active_seg_prefix = PREFIX_SS;
12132           break;
12133         case 0x3e:
12134           prefixes |= PREFIX_DS;
12135           last_seg_prefix = i;
12136           active_seg_prefix = PREFIX_DS;
12137           break;
12138         case 0x26:
12139           prefixes |= PREFIX_ES;
12140           last_seg_prefix = i;
12141           active_seg_prefix = PREFIX_ES;
12142           break;
12143         case 0x64:
12144           prefixes |= PREFIX_FS;
12145           last_seg_prefix = i;
12146           active_seg_prefix = PREFIX_FS;
12147           break;
12148         case 0x65:
12149           prefixes |= PREFIX_GS;
12150           last_seg_prefix = i;
12151           active_seg_prefix = PREFIX_GS;
12152           break;
12153         case 0x66:
12154           prefixes |= PREFIX_DATA;
12155           last_data_prefix = i;
12156           break;
12157         case 0x67:
12158           prefixes |= PREFIX_ADDR;
12159           last_addr_prefix = i;
12160           break;
12161         case FWAIT_OPCODE:
12162           /* fwait is really an instruction.  If there are prefixes
12163              before the fwait, they belong to the fwait, *not* to the
12164              following instruction.  */
12165           fwait_prefix = i;
12166           if (prefixes || rex)
12167             {
12168               prefixes |= PREFIX_FWAIT;
12169               codep++;
12170               /* This ensures that the previous REX prefixes are noticed
12171                  as unused prefixes, as in the return case below.  */
12172               rex_used = rex;
12173               return 1;
12174             }
12175           prefixes = PREFIX_FWAIT;
12176           break;
12177         default:
12178           return 1;
12179         }
12180       /* Rex is ignored when followed by another prefix.  */
12181       if (rex)
12182         {
12183           rex_used = rex;
12184           return 1;
12185         }
12186       if (*codep != FWAIT_OPCODE)
12187         all_prefixes[i++] = *codep;
12188       rex = newrex;
12189       codep++;
12190       length++;
12191     }
12192   return 0;
12193 }
12194
12195 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12196    prefix byte.  */
12197
12198 static const char *
12199 prefix_name (int pref, int sizeflag)
12200 {
12201   static const char *rexes [16] =
12202     {
12203       "rex",            /* 0x40 */
12204       "rex.B",          /* 0x41 */
12205       "rex.X",          /* 0x42 */
12206       "rex.XB",         /* 0x43 */
12207       "rex.R",          /* 0x44 */
12208       "rex.RB",         /* 0x45 */
12209       "rex.RX",         /* 0x46 */
12210       "rex.RXB",        /* 0x47 */
12211       "rex.W",          /* 0x48 */
12212       "rex.WB",         /* 0x49 */
12213       "rex.WX",         /* 0x4a */
12214       "rex.WXB",        /* 0x4b */
12215       "rex.WR",         /* 0x4c */
12216       "rex.WRB",        /* 0x4d */
12217       "rex.WRX",        /* 0x4e */
12218       "rex.WRXB",       /* 0x4f */
12219     };
12220
12221   switch (pref)
12222     {
12223     /* REX prefixes family.  */
12224     case 0x40:
12225     case 0x41:
12226     case 0x42:
12227     case 0x43:
12228     case 0x44:
12229     case 0x45:
12230     case 0x46:
12231     case 0x47:
12232     case 0x48:
12233     case 0x49:
12234     case 0x4a:
12235     case 0x4b:
12236     case 0x4c:
12237     case 0x4d:
12238     case 0x4e:
12239     case 0x4f:
12240       return rexes [pref - 0x40];
12241     case 0xf3:
12242       return "repz";
12243     case 0xf2:
12244       return "repnz";
12245     case 0xf0:
12246       return "lock";
12247     case 0x2e:
12248       return "cs";
12249     case 0x36:
12250       return "ss";
12251     case 0x3e:
12252       return "ds";
12253     case 0x26:
12254       return "es";
12255     case 0x64:
12256       return "fs";
12257     case 0x65:
12258       return "gs";
12259     case 0x66:
12260       return (sizeflag & DFLAG) ? "data16" : "data32";
12261     case 0x67:
12262       if (address_mode == mode_64bit)
12263         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12264       else
12265         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12266     case FWAIT_OPCODE:
12267       return "fwait";
12268     case REP_PREFIX:
12269       return "rep";
12270     case XACQUIRE_PREFIX:
12271       return "xacquire";
12272     case XRELEASE_PREFIX:
12273       return "xrelease";
12274     case BND_PREFIX:
12275       return "bnd";
12276     default:
12277       return NULL;
12278     }
12279 }
12280
12281 static char op_out[MAX_OPERANDS][100];
12282 static int op_ad, op_index[MAX_OPERANDS];
12283 static int two_source_ops;
12284 static bfd_vma op_address[MAX_OPERANDS];
12285 static bfd_vma op_riprel[MAX_OPERANDS];
12286 static bfd_vma start_pc;
12287
12288 /*
12289  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12290  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12291  *   section of the "Virtual 8086 Mode" chapter.)
12292  * 'pc' should be the address of this instruction, it will
12293  *   be used to print the target address if this is a relative jump or call
12294  * The function returns the length of this instruction in bytes.
12295  */
12296
12297 static char intel_syntax;
12298 static char intel_mnemonic = !SYSV386_COMPAT;
12299 static char open_char;
12300 static char close_char;
12301 static char separator_char;
12302 static char scale_char;
12303
12304 /* Here for backwards compatibility.  When gdb stops using
12305    print_insn_i386_att and print_insn_i386_intel these functions can
12306    disappear, and print_insn_i386 be merged into print_insn.  */
12307 int
12308 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12309 {
12310   intel_syntax = 0;
12311
12312   return print_insn (pc, info);
12313 }
12314
12315 int
12316 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12317 {
12318   intel_syntax = 1;
12319
12320   return print_insn (pc, info);
12321 }
12322
12323 int
12324 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12325 {
12326   intel_syntax = -1;
12327
12328   return print_insn (pc, info);
12329 }
12330
12331 void
12332 print_i386_disassembler_options (FILE *stream)
12333 {
12334   fprintf (stream, _("\n\
12335 The following i386/x86-64 specific disassembler options are supported for use\n\
12336 with the -M switch (multiple options should be separated by commas):\n"));
12337
12338   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12339   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12340   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12341   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12342   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12343   fprintf (stream, _("  att-mnemonic\n"
12344                      "              Display instruction in AT&T mnemonic\n"));
12345   fprintf (stream, _("  intel-mnemonic\n"
12346                      "              Display instruction in Intel mnemonic\n"));
12347   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12348   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12349   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12350   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12351   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12352   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12353 }
12354
12355 /* Bad opcode.  */
12356 static const struct dis386 bad_opcode = { "(bad)", { XX } };
12357
12358 /* Get a pointer to struct dis386 with a valid name.  */
12359
12360 static const struct dis386 *
12361 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12362 {
12363   int vindex, vex_table_index;
12364
12365   if (dp->name != NULL)
12366     return dp;
12367
12368   switch (dp->op[0].bytemode)
12369     {
12370     case USE_REG_TABLE:
12371       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12372       break;
12373
12374     case USE_MOD_TABLE:
12375       vindex = modrm.mod == 0x3 ? 1 : 0;
12376       dp = &mod_table[dp->op[1].bytemode][vindex];
12377       break;
12378
12379     case USE_RM_TABLE:
12380       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12381       break;
12382
12383     case USE_PREFIX_TABLE:
12384       if (need_vex)
12385         {
12386           /* The prefix in VEX is implicit.  */
12387           switch (vex.prefix)
12388             {
12389             case 0:
12390               vindex = 0;
12391               break;
12392             case REPE_PREFIX_OPCODE:
12393               vindex = 1;
12394               break;
12395             case DATA_PREFIX_OPCODE:
12396               vindex = 2;
12397               break;
12398             case REPNE_PREFIX_OPCODE:
12399               vindex = 3;
12400               break;
12401             default:
12402               abort ();
12403               break;
12404             }
12405         }
12406       else
12407         {
12408           int last_prefix = -1;
12409           int prefix = 0;
12410           vindex = 0;
12411           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12412              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12413              last one wins.  */
12414           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12415             {
12416               if (last_repz_prefix > last_repnz_prefix)
12417                 {
12418                   vindex = 1;
12419                   prefix = PREFIX_REPZ;
12420                   last_prefix = last_repz_prefix;
12421                 }
12422               else
12423                 {
12424                   vindex = 3;
12425                   prefix = PREFIX_REPNZ;
12426                   last_prefix = last_repnz_prefix;
12427                 }
12428
12429               /* Ignore the invalid index if it isn't mandatory.  */
12430               if (!mandatory_prefix
12431                   && (prefix_table[dp->op[1].bytemode][vindex].name
12432                       == NULL)
12433                   && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12434                       == 0))
12435                 vindex = 0;
12436             }
12437
12438           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12439             {
12440               vindex = 2;
12441               prefix = PREFIX_DATA;
12442               last_prefix = last_data_prefix;
12443             }
12444
12445           if (vindex != 0)
12446             {
12447               used_prefixes |= prefix;
12448               all_prefixes[last_prefix] = 0;
12449             }
12450         }
12451       dp = &prefix_table[dp->op[1].bytemode][vindex];
12452       break;
12453
12454     case USE_X86_64_TABLE:
12455       vindex = address_mode == mode_64bit ? 1 : 0;
12456       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12457       break;
12458
12459     case USE_3BYTE_TABLE:
12460       FETCH_DATA (info, codep + 2);
12461       vindex = *codep++;
12462       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12463       end_codep = codep;
12464       modrm.mod = (*codep >> 6) & 3;
12465       modrm.reg = (*codep >> 3) & 7;
12466       modrm.rm = *codep & 7;
12467       break;
12468
12469     case USE_VEX_LEN_TABLE:
12470       if (!need_vex)
12471         abort ();
12472
12473       switch (vex.length)
12474         {
12475         case 128:
12476           vindex = 0;
12477           break;
12478         case 256:
12479           vindex = 1;
12480           break;
12481         default:
12482           abort ();
12483           break;
12484         }
12485
12486       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12487       break;
12488
12489     case USE_XOP_8F_TABLE:
12490       FETCH_DATA (info, codep + 3);
12491       /* All bits in the REX prefix are ignored.  */
12492       rex_ignored = rex;
12493       rex = ~(*codep >> 5) & 0x7;
12494
12495       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12496       switch ((*codep & 0x1f))
12497         {
12498         default:
12499           dp = &bad_opcode;
12500           return dp;
12501         case 0x8:
12502           vex_table_index = XOP_08;
12503           break;
12504         case 0x9:
12505           vex_table_index = XOP_09;
12506           break;
12507         case 0xa:
12508           vex_table_index = XOP_0A;
12509           break;
12510         }
12511       codep++;
12512       vex.w = *codep & 0x80;
12513       if (vex.w && address_mode == mode_64bit)
12514         rex |= REX_W;
12515
12516       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12517       if (address_mode != mode_64bit
12518           && vex.register_specifier > 0x7)
12519         {
12520           dp = &bad_opcode;
12521           return dp;
12522         }
12523
12524       vex.length = (*codep & 0x4) ? 256 : 128;
12525       switch ((*codep & 0x3))
12526         {
12527         case 0:
12528           vex.prefix = 0;
12529           break;
12530         case 1:
12531           vex.prefix = DATA_PREFIX_OPCODE;
12532           break;
12533         case 2:
12534           vex.prefix = REPE_PREFIX_OPCODE;
12535           break;
12536         case 3:
12537           vex.prefix = REPNE_PREFIX_OPCODE;
12538           break;
12539         }
12540       need_vex = 1;
12541       need_vex_reg = 1;
12542       codep++;
12543       vindex = *codep++;
12544       dp = &xop_table[vex_table_index][vindex];
12545
12546       end_codep = codep;
12547       FETCH_DATA (info, codep + 1);
12548       modrm.mod = (*codep >> 6) & 3;
12549       modrm.reg = (*codep >> 3) & 7;
12550       modrm.rm = *codep & 7;
12551       break;
12552
12553     case USE_VEX_C4_TABLE:
12554       /* VEX prefix.  */
12555       FETCH_DATA (info, codep + 3);
12556       /* All bits in the REX prefix are ignored.  */
12557       rex_ignored = rex;
12558       rex = ~(*codep >> 5) & 0x7;
12559       switch ((*codep & 0x1f))
12560         {
12561         default:
12562           dp = &bad_opcode;
12563           return dp;
12564         case 0x1:
12565           vex_table_index = VEX_0F;
12566           break;
12567         case 0x2:
12568           vex_table_index = VEX_0F38;
12569           break;
12570         case 0x3:
12571           vex_table_index = VEX_0F3A;
12572           break;
12573         }
12574       codep++;
12575       vex.w = *codep & 0x80;
12576       if (vex.w && address_mode == mode_64bit)
12577         rex |= REX_W;
12578
12579       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12580       if (address_mode != mode_64bit
12581           && vex.register_specifier > 0x7)
12582         {
12583           dp = &bad_opcode;
12584           return dp;
12585         }
12586
12587       vex.length = (*codep & 0x4) ? 256 : 128;
12588       switch ((*codep & 0x3))
12589         {
12590         case 0:
12591           vex.prefix = 0;
12592           break;
12593         case 1:
12594           vex.prefix = DATA_PREFIX_OPCODE;
12595           break;
12596         case 2:
12597           vex.prefix = REPE_PREFIX_OPCODE;
12598           break;
12599         case 3:
12600           vex.prefix = REPNE_PREFIX_OPCODE;
12601           break;
12602         }
12603       need_vex = 1;
12604       need_vex_reg = 1;
12605       codep++;
12606       vindex = *codep++;
12607       dp = &vex_table[vex_table_index][vindex];
12608       end_codep = codep;
12609       /* There is no MODRM byte for VEX [82|77].  */
12610       if (vindex != 0x77 && vindex != 0x82)
12611         {
12612           FETCH_DATA (info, codep + 1);
12613           modrm.mod = (*codep >> 6) & 3;
12614           modrm.reg = (*codep >> 3) & 7;
12615           modrm.rm = *codep & 7;
12616         }
12617       break;
12618
12619     case USE_VEX_C5_TABLE:
12620       /* VEX prefix.  */
12621       FETCH_DATA (info, codep + 2);
12622       /* All bits in the REX prefix are ignored.  */
12623       rex_ignored = rex;
12624       rex = (*codep & 0x80) ? 0 : REX_R;
12625
12626       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12627       if (address_mode != mode_64bit
12628           && vex.register_specifier > 0x7)
12629         {
12630           dp = &bad_opcode;
12631           return dp;
12632         }
12633
12634       vex.w = 0;
12635
12636       vex.length = (*codep & 0x4) ? 256 : 128;
12637       switch ((*codep & 0x3))
12638         {
12639         case 0:
12640           vex.prefix = 0;
12641           break;
12642         case 1:
12643           vex.prefix = DATA_PREFIX_OPCODE;
12644           break;
12645         case 2:
12646           vex.prefix = REPE_PREFIX_OPCODE;
12647           break;
12648         case 3:
12649           vex.prefix = REPNE_PREFIX_OPCODE;
12650           break;
12651         }
12652       need_vex = 1;
12653       need_vex_reg = 1;
12654       codep++;
12655       vindex = *codep++;
12656       dp = &vex_table[dp->op[1].bytemode][vindex];
12657       end_codep = codep;
12658       /* There is no MODRM byte for VEX [82|77].  */
12659       if (vindex != 0x77 && vindex != 0x82)
12660         {
12661           FETCH_DATA (info, codep + 1);
12662           modrm.mod = (*codep >> 6) & 3;
12663           modrm.reg = (*codep >> 3) & 7;
12664           modrm.rm = *codep & 7;
12665         }
12666       break;
12667
12668     case USE_VEX_W_TABLE:
12669       if (!need_vex)
12670         abort ();
12671
12672       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12673       break;
12674
12675     case USE_EVEX_TABLE:
12676       two_source_ops = 0;
12677       /* EVEX prefix.  */
12678       vex.evex = 1;
12679       FETCH_DATA (info, codep + 4);
12680       /* All bits in the REX prefix are ignored.  */
12681       rex_ignored = rex;
12682       /* The first byte after 0x62.  */
12683       rex = ~(*codep >> 5) & 0x7;
12684       vex.r = *codep & 0x10;
12685       switch ((*codep & 0xf))
12686         {
12687         default:
12688           return &bad_opcode;
12689         case 0x1:
12690           vex_table_index = EVEX_0F;
12691           break;
12692         case 0x2:
12693           vex_table_index = EVEX_0F38;
12694           break;
12695         case 0x3:
12696           vex_table_index = EVEX_0F3A;
12697           break;
12698         }
12699
12700       /* The second byte after 0x62.  */
12701       codep++;
12702       vex.w = *codep & 0x80;
12703       if (vex.w && address_mode == mode_64bit)
12704         rex |= REX_W;
12705
12706       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12707       if (address_mode != mode_64bit)
12708         {
12709           /* In 16/32-bit mode silently ignore following bits.  */
12710           rex &= ~REX_B;
12711           vex.r = 1;
12712           vex.v = 1;
12713           vex.register_specifier &= 0x7;
12714         }
12715
12716       /* The U bit.  */
12717       if (!(*codep & 0x4))
12718         return &bad_opcode;
12719
12720       switch ((*codep & 0x3))
12721         {
12722         case 0:
12723           vex.prefix = 0;
12724           break;
12725         case 1:
12726           vex.prefix = DATA_PREFIX_OPCODE;
12727           break;
12728         case 2:
12729           vex.prefix = REPE_PREFIX_OPCODE;
12730           break;
12731         case 3:
12732           vex.prefix = REPNE_PREFIX_OPCODE;
12733           break;
12734         }
12735
12736       /* The third byte after 0x62.  */
12737       codep++;
12738
12739       /* Remember the static rounding bits.  */
12740       vex.ll = (*codep >> 5) & 3;
12741       vex.b = (*codep & 0x10) != 0;
12742
12743       vex.v = *codep & 0x8;
12744       vex.mask_register_specifier = *codep & 0x7;
12745       vex.zeroing = *codep & 0x80;
12746
12747       need_vex = 1;
12748       need_vex_reg = 1;
12749       codep++;
12750       vindex = *codep++;
12751       dp = &evex_table[vex_table_index][vindex];
12752       end_codep = codep;
12753       FETCH_DATA (info, codep + 1);
12754       modrm.mod = (*codep >> 6) & 3;
12755       modrm.reg = (*codep >> 3) & 7;
12756       modrm.rm = *codep & 7;
12757
12758       /* Set vector length.  */
12759       if (modrm.mod == 3 && vex.b)
12760         vex.length = 512;
12761       else
12762         {
12763           switch (vex.ll)
12764             {
12765             case 0x0:
12766               vex.length = 128;
12767               break;
12768             case 0x1:
12769               vex.length = 256;
12770               break;
12771             case 0x2:
12772               vex.length = 512;
12773               break;
12774             default:
12775               return &bad_opcode;
12776             }
12777         }
12778       break;
12779
12780     case 0:
12781       dp = &bad_opcode;
12782       break;
12783
12784     default:
12785       abort ();
12786     }
12787
12788   if (dp->name != NULL)
12789     return dp;
12790   else
12791     return get_valid_dis386 (dp, info);
12792 }
12793
12794 static void
12795 get_sib (disassemble_info *info, int sizeflag)
12796 {
12797   /* If modrm.mod == 3, operand must be register.  */
12798   if (need_modrm
12799       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12800       && modrm.mod != 3
12801       && modrm.rm == 4)
12802     {
12803       FETCH_DATA (info, codep + 2);
12804       sib.index = (codep [1] >> 3) & 7;
12805       sib.scale = (codep [1] >> 6) & 3;
12806       sib.base = codep [1] & 7;
12807     }
12808 }
12809
12810 static int
12811 print_insn (bfd_vma pc, disassemble_info *info)
12812 {
12813   const struct dis386 *dp;
12814   int i;
12815   char *op_txt[MAX_OPERANDS];
12816   int needcomma;
12817   int sizeflag, orig_sizeflag;
12818   const char *p;
12819   struct dis_private priv;
12820   int prefix_length;
12821
12822   priv.orig_sizeflag = AFLAG | DFLAG;
12823   if ((info->mach & bfd_mach_i386_i386) != 0)
12824     address_mode = mode_32bit;
12825   else if (info->mach == bfd_mach_i386_i8086)
12826     {
12827       address_mode = mode_16bit;
12828       priv.orig_sizeflag = 0;
12829     }
12830   else
12831     address_mode = mode_64bit;
12832
12833   if (intel_syntax == (char) -1)
12834     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12835
12836   for (p = info->disassembler_options; p != NULL; )
12837     {
12838       if (CONST_STRNEQ (p, "x86-64"))
12839         {
12840           address_mode = mode_64bit;
12841           priv.orig_sizeflag = AFLAG | DFLAG;
12842         }
12843       else if (CONST_STRNEQ (p, "i386"))
12844         {
12845           address_mode = mode_32bit;
12846           priv.orig_sizeflag = AFLAG | DFLAG;
12847         }
12848       else if (CONST_STRNEQ (p, "i8086"))
12849         {
12850           address_mode = mode_16bit;
12851           priv.orig_sizeflag = 0;
12852         }
12853       else if (CONST_STRNEQ (p, "intel"))
12854         {
12855           intel_syntax = 1;
12856           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12857             intel_mnemonic = 1;
12858         }
12859       else if (CONST_STRNEQ (p, "att"))
12860         {
12861           intel_syntax = 0;
12862           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12863             intel_mnemonic = 0;
12864         }
12865       else if (CONST_STRNEQ (p, "addr"))
12866         {
12867           if (address_mode == mode_64bit)
12868             {
12869               if (p[4] == '3' && p[5] == '2')
12870                 priv.orig_sizeflag &= ~AFLAG;
12871               else if (p[4] == '6' && p[5] == '4')
12872                 priv.orig_sizeflag |= AFLAG;
12873             }
12874           else
12875             {
12876               if (p[4] == '1' && p[5] == '6')
12877                 priv.orig_sizeflag &= ~AFLAG;
12878               else if (p[4] == '3' && p[5] == '2')
12879                 priv.orig_sizeflag |= AFLAG;
12880             }
12881         }
12882       else if (CONST_STRNEQ (p, "data"))
12883         {
12884           if (p[4] == '1' && p[5] == '6')
12885             priv.orig_sizeflag &= ~DFLAG;
12886           else if (p[4] == '3' && p[5] == '2')
12887             priv.orig_sizeflag |= DFLAG;
12888         }
12889       else if (CONST_STRNEQ (p, "suffix"))
12890         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12891
12892       p = strchr (p, ',');
12893       if (p != NULL)
12894         p++;
12895     }
12896
12897   if (intel_syntax)
12898     {
12899       names64 = intel_names64;
12900       names32 = intel_names32;
12901       names16 = intel_names16;
12902       names8 = intel_names8;
12903       names8rex = intel_names8rex;
12904       names_seg = intel_names_seg;
12905       names_mm = intel_names_mm;
12906       names_bnd = intel_names_bnd;
12907       names_xmm = intel_names_xmm;
12908       names_ymm = intel_names_ymm;
12909       names_zmm = intel_names_zmm;
12910       index64 = intel_index64;
12911       index32 = intel_index32;
12912       names_mask = intel_names_mask;
12913       index16 = intel_index16;
12914       open_char = '[';
12915       close_char = ']';
12916       separator_char = '+';
12917       scale_char = '*';
12918     }
12919   else
12920     {
12921       names64 = att_names64;
12922       names32 = att_names32;
12923       names16 = att_names16;
12924       names8 = att_names8;
12925       names8rex = att_names8rex;
12926       names_seg = att_names_seg;
12927       names_mm = att_names_mm;
12928       names_bnd = att_names_bnd;
12929       names_xmm = att_names_xmm;
12930       names_ymm = att_names_ymm;
12931       names_zmm = att_names_zmm;
12932       index64 = att_index64;
12933       index32 = att_index32;
12934       names_mask = att_names_mask;
12935       index16 = att_index16;
12936       open_char = '(';
12937       close_char =  ')';
12938       separator_char = ',';
12939       scale_char = ',';
12940     }
12941
12942   /* The output looks better if we put 7 bytes on a line, since that
12943      puts most long word instructions on a single line.  Use 8 bytes
12944      for Intel L1OM.  */
12945   if ((info->mach & bfd_mach_l1om) != 0)
12946     info->bytes_per_line = 8;
12947   else
12948     info->bytes_per_line = 7;
12949
12950   info->private_data = &priv;
12951   priv.max_fetched = priv.the_buffer;
12952   priv.insn_start = pc;
12953
12954   obuf[0] = 0;
12955   for (i = 0; i < MAX_OPERANDS; ++i)
12956     {
12957       op_out[i][0] = 0;
12958       op_index[i] = -1;
12959     }
12960
12961   the_info = info;
12962   start_pc = pc;
12963   start_codep = priv.the_buffer;
12964   codep = priv.the_buffer;
12965
12966   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12967     {
12968       const char *name;
12969
12970       /* Getting here means we tried for data but didn't get it.  That
12971          means we have an incomplete instruction of some sort.  Just
12972          print the first byte as a prefix or a .byte pseudo-op.  */
12973       if (codep > priv.the_buffer)
12974         {
12975           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12976           if (name != NULL)
12977             (*info->fprintf_func) (info->stream, "%s", name);
12978           else
12979             {
12980               /* Just print the first byte as a .byte instruction.  */
12981               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12982                                      (unsigned int) priv.the_buffer[0]);
12983             }
12984
12985           return 1;
12986         }
12987
12988       return -1;
12989     }
12990
12991   obufp = obuf;
12992   sizeflag = priv.orig_sizeflag;
12993
12994   if (!ckprefix () || rex_used)
12995     {
12996       /* Too many prefixes or unused REX prefixes.  */
12997       for (i = 0;
12998            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12999            i++)
13000         (*info->fprintf_func) (info->stream, "%s%s",
13001                                i == 0 ? "" : " ",
13002                                prefix_name (all_prefixes[i], sizeflag));
13003       return i;
13004     }
13005
13006   insn_codep = codep;
13007
13008   FETCH_DATA (info, codep + 1);
13009   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13010
13011   if (((prefixes & PREFIX_FWAIT)
13012        && ((*codep < 0xd8) || (*codep > 0xdf))))
13013     {
13014       /* Handle prefixes before fwait.  */
13015       for (i = 0; i < fwait_prefix && all_prefixes[i];
13016            i++)
13017         (*info->fprintf_func) (info->stream, "%s ",
13018                                prefix_name (all_prefixes[i], sizeflag));
13019       (*info->fprintf_func) (info->stream, "fwait");
13020       return i + 1;
13021     }
13022
13023   if (*codep == 0x0f)
13024     {
13025       unsigned char threebyte;
13026       FETCH_DATA (info, codep + 2);
13027       threebyte = *++codep;
13028       dp = &dis386_twobyte[threebyte];
13029       need_modrm = twobyte_has_modrm[*codep];
13030       mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
13031       codep++;
13032     }
13033   else
13034     {
13035       dp = &dis386[*codep];
13036       need_modrm = onebyte_has_modrm[*codep];
13037       mandatory_prefix = 0;
13038       codep++;
13039     }
13040
13041   /* Save sizeflag for printing the extra prefixes later before updating
13042      it for mnemonic and operand processing.  The prefix names depend
13043      only on the address mode.  */
13044   orig_sizeflag = sizeflag;
13045   if (prefixes & PREFIX_ADDR)
13046     sizeflag ^= AFLAG;
13047   if ((prefixes & PREFIX_DATA))
13048     sizeflag ^= DFLAG;
13049
13050   end_codep = codep;
13051   if (need_modrm)
13052     {
13053       FETCH_DATA (info, codep + 1);
13054       modrm.mod = (*codep >> 6) & 3;
13055       modrm.reg = (*codep >> 3) & 7;
13056       modrm.rm = *codep & 7;
13057     }
13058
13059   need_vex = 0;
13060   need_vex_reg = 0;
13061   vex_w_done = 0;
13062   vex.evex = 0;
13063
13064   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13065     {
13066       get_sib (info, sizeflag);
13067       dofloat (sizeflag);
13068     }
13069   else
13070     {
13071       dp = get_valid_dis386 (dp, info);
13072       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13073         {
13074           get_sib (info, sizeflag);
13075           for (i = 0; i < MAX_OPERANDS; ++i)
13076             {
13077               obufp = op_out[i];
13078               op_ad = MAX_OPERANDS - 1 - i;
13079               if (dp->op[i].rtn)
13080                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13081               /* For EVEX instruction after the last operand masking
13082                  should be printed.  */
13083               if (i == 0 && vex.evex)
13084                 {
13085                   /* Don't print {%k0}.  */
13086                   if (vex.mask_register_specifier)
13087                     {
13088                       oappend ("{");
13089                       oappend (names_mask[vex.mask_register_specifier]);
13090                       oappend ("}");
13091                     }
13092                   if (vex.zeroing)
13093                     oappend ("{z}");
13094                 }
13095             }
13096         }
13097     }
13098
13099   /* Check if the REX prefix is used.  */
13100   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13101     all_prefixes[last_rex_prefix] = 0;
13102
13103   /* Check if the SEG prefix is used.  */
13104   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13105                    | PREFIX_FS | PREFIX_GS)) != 0
13106       && (used_prefixes & active_seg_prefix) != 0)
13107     all_prefixes[last_seg_prefix] = 0;
13108
13109   /* Check if the ADDR prefix is used.  */
13110   if ((prefixes & PREFIX_ADDR) != 0
13111       && (used_prefixes & PREFIX_ADDR) != 0)
13112     all_prefixes[last_addr_prefix] = 0;
13113
13114   /* Check if the DATA prefix is used.  */
13115   if ((prefixes & PREFIX_DATA) != 0
13116       && (used_prefixes & PREFIX_DATA) != 0)
13117     all_prefixes[last_data_prefix] = 0;
13118
13119   /* Print the extra prefixes.  */
13120   prefix_length = 0;
13121   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13122     if (all_prefixes[i])
13123       {
13124         const char *name;
13125         name = prefix_name (all_prefixes[i], orig_sizeflag);
13126         if (name == NULL)
13127           abort ();
13128         prefix_length += strlen (name) + 1;
13129         (*info->fprintf_func) (info->stream, "%s ", name);
13130       }
13131
13132   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13133      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13134      used by putop and MMX/SSE operand and may be overriden by the
13135      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13136      separately.  */
13137   if (mandatory_prefix
13138       && dp != &bad_opcode
13139       && (((prefixes
13140             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13141            && (used_prefixes
13142                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13143           || ((((prefixes
13144                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13145                 == PREFIX_DATA)
13146                && (used_prefixes & PREFIX_DATA) == 0))))
13147     {
13148       (*info->fprintf_func) (info->stream, "(bad)");
13149       return end_codep - priv.the_buffer;
13150     }
13151
13152   /* Check maximum code length.  */
13153   if ((codep - start_codep) > MAX_CODE_LENGTH)
13154     {
13155       (*info->fprintf_func) (info->stream, "(bad)");
13156       return MAX_CODE_LENGTH;
13157     }
13158
13159   obufp = mnemonicendp;
13160   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13161     oappend (" ");
13162   oappend (" ");
13163   (*info->fprintf_func) (info->stream, "%s", obuf);
13164
13165   /* The enter and bound instructions are printed with operands in the same
13166      order as the intel book; everything else is printed in reverse order.  */
13167   if (intel_syntax || two_source_ops)
13168     {
13169       bfd_vma riprel;
13170
13171       for (i = 0; i < MAX_OPERANDS; ++i)
13172         op_txt[i] = op_out[i];
13173
13174       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13175         {
13176           op_ad = op_index[i];
13177           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13178           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13179           riprel = op_riprel[i];
13180           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13181           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13182         }
13183     }
13184   else
13185     {
13186       for (i = 0; i < MAX_OPERANDS; ++i)
13187         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13188     }
13189
13190   needcomma = 0;
13191   for (i = 0; i < MAX_OPERANDS; ++i)
13192     if (*op_txt[i])
13193       {
13194         if (needcomma)
13195           (*info->fprintf_func) (info->stream, ",");
13196         if (op_index[i] != -1 && !op_riprel[i])
13197           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13198         else
13199           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13200         needcomma = 1;
13201       }
13202
13203   for (i = 0; i < MAX_OPERANDS; i++)
13204     if (op_index[i] != -1 && op_riprel[i])
13205       {
13206         (*info->fprintf_func) (info->stream, "        # ");
13207         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13208                                                 + op_address[op_index[i]]), info);
13209         break;
13210       }
13211   return codep - priv.the_buffer;
13212 }
13213
13214 static const char *float_mem[] = {
13215   /* d8 */
13216   "fadd{s|}",
13217   "fmul{s|}",
13218   "fcom{s|}",
13219   "fcomp{s|}",
13220   "fsub{s|}",
13221   "fsubr{s|}",
13222   "fdiv{s|}",
13223   "fdivr{s|}",
13224   /* d9 */
13225   "fld{s|}",
13226   "(bad)",
13227   "fst{s|}",
13228   "fstp{s|}",
13229   "fldenvIC",
13230   "fldcw",
13231   "fNstenvIC",
13232   "fNstcw",
13233   /* da */
13234   "fiadd{l|}",
13235   "fimul{l|}",
13236   "ficom{l|}",
13237   "ficomp{l|}",
13238   "fisub{l|}",
13239   "fisubr{l|}",
13240   "fidiv{l|}",
13241   "fidivr{l|}",
13242   /* db */
13243   "fild{l|}",
13244   "fisttp{l|}",
13245   "fist{l|}",
13246   "fistp{l|}",
13247   "(bad)",
13248   "fld{t||t|}",
13249   "(bad)",
13250   "fstp{t||t|}",
13251   /* dc */
13252   "fadd{l|}",
13253   "fmul{l|}",
13254   "fcom{l|}",
13255   "fcomp{l|}",
13256   "fsub{l|}",
13257   "fsubr{l|}",
13258   "fdiv{l|}",
13259   "fdivr{l|}",
13260   /* dd */
13261   "fld{l|}",
13262   "fisttp{ll|}",
13263   "fst{l||}",
13264   "fstp{l|}",
13265   "frstorIC",
13266   "(bad)",
13267   "fNsaveIC",
13268   "fNstsw",
13269   /* de */
13270   "fiadd",
13271   "fimul",
13272   "ficom",
13273   "ficomp",
13274   "fisub",
13275   "fisubr",
13276   "fidiv",
13277   "fidivr",
13278   /* df */
13279   "fild",
13280   "fisttp",
13281   "fist",
13282   "fistp",
13283   "fbld",
13284   "fild{ll|}",
13285   "fbstp",
13286   "fistp{ll|}",
13287 };
13288
13289 static const unsigned char float_mem_mode[] = {
13290   /* d8 */
13291   d_mode,
13292   d_mode,
13293   d_mode,
13294   d_mode,
13295   d_mode,
13296   d_mode,
13297   d_mode,
13298   d_mode,
13299   /* d9 */
13300   d_mode,
13301   0,
13302   d_mode,
13303   d_mode,
13304   0,
13305   w_mode,
13306   0,
13307   w_mode,
13308   /* da */
13309   d_mode,
13310   d_mode,
13311   d_mode,
13312   d_mode,
13313   d_mode,
13314   d_mode,
13315   d_mode,
13316   d_mode,
13317   /* db */
13318   d_mode,
13319   d_mode,
13320   d_mode,
13321   d_mode,
13322   0,
13323   t_mode,
13324   0,
13325   t_mode,
13326   /* dc */
13327   q_mode,
13328   q_mode,
13329   q_mode,
13330   q_mode,
13331   q_mode,
13332   q_mode,
13333   q_mode,
13334   q_mode,
13335   /* dd */
13336   q_mode,
13337   q_mode,
13338   q_mode,
13339   q_mode,
13340   0,
13341   0,
13342   0,
13343   w_mode,
13344   /* de */
13345   w_mode,
13346   w_mode,
13347   w_mode,
13348   w_mode,
13349   w_mode,
13350   w_mode,
13351   w_mode,
13352   w_mode,
13353   /* df */
13354   w_mode,
13355   w_mode,
13356   w_mode,
13357   w_mode,
13358   t_mode,
13359   q_mode,
13360   t_mode,
13361   q_mode
13362 };
13363
13364 #define ST { OP_ST, 0 }
13365 #define STi { OP_STi, 0 }
13366
13367 #define FGRPd9_2 NULL, { { NULL, 0 } }
13368 #define FGRPd9_4 NULL, { { NULL, 1 } }
13369 #define FGRPd9_5 NULL, { { NULL, 2 } }
13370 #define FGRPd9_6 NULL, { { NULL, 3 } }
13371 #define FGRPd9_7 NULL, { { NULL, 4 } }
13372 #define FGRPda_5 NULL, { { NULL, 5 } }
13373 #define FGRPdb_4 NULL, { { NULL, 6 } }
13374 #define FGRPde_3 NULL, { { NULL, 7 } }
13375 #define FGRPdf_4 NULL, { { NULL, 8 } }
13376
13377 static const struct dis386 float_reg[][8] = {
13378   /* d8 */
13379   {
13380     { "fadd",   { ST, STi } },
13381     { "fmul",   { ST, STi } },
13382     { "fcom",   { STi } },
13383     { "fcomp",  { STi } },
13384     { "fsub",   { ST, STi } },
13385     { "fsubr",  { ST, STi } },
13386     { "fdiv",   { ST, STi } },
13387     { "fdivr",  { ST, STi } },
13388   },
13389   /* d9 */
13390   {
13391     { "fld",    { STi } },
13392     { "fxch",   { STi } },
13393     { FGRPd9_2 },
13394     { Bad_Opcode },
13395     { FGRPd9_4 },
13396     { FGRPd9_5 },
13397     { FGRPd9_6 },
13398     { FGRPd9_7 },
13399   },
13400   /* da */
13401   {
13402     { "fcmovb", { ST, STi } },
13403     { "fcmove", { ST, STi } },
13404     { "fcmovbe",{ ST, STi } },
13405     { "fcmovu", { ST, STi } },
13406     { Bad_Opcode },
13407     { FGRPda_5 },
13408     { Bad_Opcode },
13409     { Bad_Opcode },
13410   },
13411   /* db */
13412   {
13413     { "fcmovnb",{ ST, STi } },
13414     { "fcmovne",{ ST, STi } },
13415     { "fcmovnbe",{ ST, STi } },
13416     { "fcmovnu",{ ST, STi } },
13417     { FGRPdb_4 },
13418     { "fucomi", { ST, STi } },
13419     { "fcomi",  { ST, STi } },
13420     { Bad_Opcode },
13421   },
13422   /* dc */
13423   {
13424     { "fadd",   { STi, ST } },
13425     { "fmul",   { STi, ST } },
13426     { Bad_Opcode },
13427     { Bad_Opcode },
13428     { "fsub!M", { STi, ST } },
13429     { "fsubM",  { STi, ST } },
13430     { "fdiv!M", { STi, ST } },
13431     { "fdivM",  { STi, ST } },
13432   },
13433   /* dd */
13434   {
13435     { "ffree",  { STi } },
13436     { Bad_Opcode },
13437     { "fst",    { STi } },
13438     { "fstp",   { STi } },
13439     { "fucom",  { STi } },
13440     { "fucomp", { STi } },
13441     { Bad_Opcode },
13442     { Bad_Opcode },
13443   },
13444   /* de */
13445   {
13446     { "faddp",  { STi, ST } },
13447     { "fmulp",  { STi, ST } },
13448     { Bad_Opcode },
13449     { FGRPde_3 },
13450     { "fsub!Mp", { STi, ST } },
13451     { "fsubMp", { STi, ST } },
13452     { "fdiv!Mp", { STi, ST } },
13453     { "fdivMp", { STi, ST } },
13454   },
13455   /* df */
13456   {
13457     { "ffreep", { STi } },
13458     { Bad_Opcode },
13459     { Bad_Opcode },
13460     { Bad_Opcode },
13461     { FGRPdf_4 },
13462     { "fucomip", { ST, STi } },
13463     { "fcomip", { ST, STi } },
13464     { Bad_Opcode },
13465   },
13466 };
13467
13468 static char *fgrps[][8] = {
13469   /* d9_2  0 */
13470   {
13471     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13472   },
13473
13474   /* d9_4  1 */
13475   {
13476     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13477   },
13478
13479   /* d9_5  2 */
13480   {
13481     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13482   },
13483
13484   /* d9_6  3 */
13485   {
13486     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13487   },
13488
13489   /* d9_7  4 */
13490   {
13491     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13492   },
13493
13494   /* da_5  5 */
13495   {
13496     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13497   },
13498
13499   /* db_4  6 */
13500   {
13501     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13502     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13503   },
13504
13505   /* de_3  7 */
13506   {
13507     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13508   },
13509
13510   /* df_4  8 */
13511   {
13512     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13513   },
13514 };
13515
13516 static void
13517 swap_operand (void)
13518 {
13519   mnemonicendp[0] = '.';
13520   mnemonicendp[1] = 's';
13521   mnemonicendp += 2;
13522 }
13523
13524 static void
13525 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13526                int sizeflag ATTRIBUTE_UNUSED)
13527 {
13528   /* Skip mod/rm byte.  */
13529   MODRM_CHECK;
13530   codep++;
13531 }
13532
13533 static void
13534 dofloat (int sizeflag)
13535 {
13536   const struct dis386 *dp;
13537   unsigned char floatop;
13538
13539   floatop = codep[-1];
13540
13541   if (modrm.mod != 3)
13542     {
13543       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13544
13545       putop (float_mem[fp_indx], sizeflag);
13546       obufp = op_out[0];
13547       op_ad = 2;
13548       OP_E (float_mem_mode[fp_indx], sizeflag);
13549       return;
13550     }
13551   /* Skip mod/rm byte.  */
13552   MODRM_CHECK;
13553   codep++;
13554
13555   dp = &float_reg[floatop - 0xd8][modrm.reg];
13556   if (dp->name == NULL)
13557     {
13558       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13559
13560       /* Instruction fnstsw is only one with strange arg.  */
13561       if (floatop == 0xdf && codep[-1] == 0xe0)
13562         strcpy (op_out[0], names16[0]);
13563     }
13564   else
13565     {
13566       putop (dp->name, sizeflag);
13567
13568       obufp = op_out[0];
13569       op_ad = 2;
13570       if (dp->op[0].rtn)
13571         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13572
13573       obufp = op_out[1];
13574       op_ad = 1;
13575       if (dp->op[1].rtn)
13576         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13577     }
13578 }
13579
13580 /* Like oappend (below), but S is a string starting with '%'.
13581    In Intel syntax, the '%' is elided.  */
13582 static void
13583 oappend_maybe_intel (const char *s)
13584 {
13585   oappend (s + intel_syntax);
13586 }
13587
13588 static void
13589 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13590 {
13591   oappend_maybe_intel ("%st");
13592 }
13593
13594 static void
13595 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13596 {
13597   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13598   oappend_maybe_intel (scratchbuf);
13599 }
13600
13601 /* Capital letters in template are macros.  */
13602 static int
13603 putop (const char *in_template, int sizeflag)
13604 {
13605   const char *p;
13606   int alt = 0;
13607   int cond = 1;
13608   unsigned int l = 0, len = 1;
13609   char last[4];
13610
13611 #define SAVE_LAST(c)                    \
13612   if (l < len && l < sizeof (last))     \
13613     last[l++] = c;                      \
13614   else                                  \
13615     abort ();
13616
13617   for (p = in_template; *p; p++)
13618     {
13619       switch (*p)
13620         {
13621         default:
13622           *obufp++ = *p;
13623           break;
13624         case '%':
13625           len++;
13626           break;
13627         case '!':
13628           cond = 0;
13629           break;
13630         case '{':
13631           alt = 0;
13632           if (intel_syntax)
13633             {
13634               while (*++p != '|')
13635                 if (*p == '}' || *p == '\0')
13636                   abort ();
13637             }
13638           /* Fall through.  */
13639         case 'I':
13640           alt = 1;
13641           continue;
13642         case '|':
13643           while (*++p != '}')
13644             {
13645               if (*p == '\0')
13646                 abort ();
13647             }
13648           break;
13649         case '}':
13650           break;
13651         case 'A':
13652           if (intel_syntax)
13653             break;
13654           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13655             *obufp++ = 'b';
13656           break;
13657         case 'B':
13658           if (l == 0 && len == 1)
13659             {
13660 case_B:
13661               if (intel_syntax)
13662                 break;
13663               if (sizeflag & SUFFIX_ALWAYS)
13664                 *obufp++ = 'b';
13665             }
13666           else
13667             {
13668               if (l != 1
13669                   || len != 2
13670                   || last[0] != 'L')
13671                 {
13672                   SAVE_LAST (*p);
13673                   break;
13674                 }
13675
13676               if (address_mode == mode_64bit
13677                   && !(prefixes & PREFIX_ADDR))
13678                 {
13679                   *obufp++ = 'a';
13680                   *obufp++ = 'b';
13681                   *obufp++ = 's';
13682                 }
13683
13684               goto case_B;
13685             }
13686           break;
13687         case 'C':
13688           if (intel_syntax && !alt)
13689             break;
13690           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13691             {
13692               if (sizeflag & DFLAG)
13693                 *obufp++ = intel_syntax ? 'd' : 'l';
13694               else
13695                 *obufp++ = intel_syntax ? 'w' : 's';
13696               used_prefixes |= (prefixes & PREFIX_DATA);
13697             }
13698           break;
13699         case 'D':
13700           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13701             break;
13702           USED_REX (REX_W);
13703           if (modrm.mod == 3)
13704             {
13705               if (rex & REX_W)
13706                 *obufp++ = 'q';
13707               else
13708                 {
13709                   if (sizeflag & DFLAG)
13710                     *obufp++ = intel_syntax ? 'd' : 'l';
13711                   else
13712                     *obufp++ = 'w';
13713                   used_prefixes |= (prefixes & PREFIX_DATA);
13714                 }
13715             }
13716           else
13717             *obufp++ = 'w';
13718           break;
13719         case 'E':               /* For jcxz/jecxz */
13720           if (address_mode == mode_64bit)
13721             {
13722               if (sizeflag & AFLAG)
13723                 *obufp++ = 'r';
13724               else
13725                 *obufp++ = 'e';
13726             }
13727           else
13728             if (sizeflag & AFLAG)
13729               *obufp++ = 'e';
13730           used_prefixes |= (prefixes & PREFIX_ADDR);
13731           break;
13732         case 'F':
13733           if (intel_syntax)
13734             break;
13735           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13736             {
13737               if (sizeflag & AFLAG)
13738                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13739               else
13740                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13741               used_prefixes |= (prefixes & PREFIX_ADDR);
13742             }
13743           break;
13744         case 'G':
13745           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13746             break;
13747           if ((rex & REX_W) || (sizeflag & DFLAG))
13748             *obufp++ = 'l';
13749           else
13750             *obufp++ = 'w';
13751           if (!(rex & REX_W))
13752             used_prefixes |= (prefixes & PREFIX_DATA);
13753           break;
13754         case 'H':
13755           if (intel_syntax)
13756             break;
13757           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13758               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13759             {
13760               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13761               *obufp++ = ',';
13762               *obufp++ = 'p';
13763               if (prefixes & PREFIX_DS)
13764                 *obufp++ = 't';
13765               else
13766                 *obufp++ = 'n';
13767             }
13768           break;
13769         case 'J':
13770           if (intel_syntax)
13771             break;
13772           *obufp++ = 'l';
13773           break;
13774         case 'K':
13775           USED_REX (REX_W);
13776           if (rex & REX_W)
13777             *obufp++ = 'q';
13778           else
13779             *obufp++ = 'd';
13780           break;
13781         case 'Z':
13782           if (intel_syntax)
13783             break;
13784           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13785             {
13786               *obufp++ = 'q';
13787               break;
13788             }
13789           /* Fall through.  */
13790           goto case_L;
13791         case 'L':
13792           if (l != 0 || len != 1)
13793             {
13794               SAVE_LAST (*p);
13795               break;
13796             }
13797 case_L:
13798           if (intel_syntax)
13799             break;
13800           if (sizeflag & SUFFIX_ALWAYS)
13801             *obufp++ = 'l';
13802           break;
13803         case 'M':
13804           if (intel_mnemonic != cond)
13805             *obufp++ = 'r';
13806           break;
13807         case 'N':
13808           if ((prefixes & PREFIX_FWAIT) == 0)
13809             *obufp++ = 'n';
13810           else
13811             used_prefixes |= PREFIX_FWAIT;
13812           break;
13813         case 'O':
13814           USED_REX (REX_W);
13815           if (rex & REX_W)
13816             *obufp++ = 'o';
13817           else if (intel_syntax && (sizeflag & DFLAG))
13818             *obufp++ = 'q';
13819           else
13820             *obufp++ = 'd';
13821           if (!(rex & REX_W))
13822             used_prefixes |= (prefixes & PREFIX_DATA);
13823           break;
13824         case 'T':
13825           if (!intel_syntax
13826               && address_mode == mode_64bit
13827               && ((sizeflag & DFLAG) || (rex & REX_W)))
13828             {
13829               *obufp++ = 'q';
13830               break;
13831             }
13832           /* Fall through.  */
13833           goto case_P;
13834         case 'P':
13835           if (l == 0 && len == 1)
13836             {
13837 case_P:
13838               if (intel_syntax)
13839                 {
13840                   if ((rex & REX_W) == 0
13841                       && (prefixes & PREFIX_DATA))
13842                     {
13843                       if ((sizeflag & DFLAG) == 0)
13844                         *obufp++ = 'w';
13845                       used_prefixes |= (prefixes & PREFIX_DATA);
13846                     }
13847                   break;
13848                 }
13849               if ((prefixes & PREFIX_DATA)
13850                   || (rex & REX_W)
13851                   || (sizeflag & SUFFIX_ALWAYS))
13852                 {
13853                   USED_REX (REX_W);
13854                   if (rex & REX_W)
13855                     *obufp++ = 'q';
13856                   else
13857                     {
13858                       if (sizeflag & DFLAG)
13859                         *obufp++ = 'l';
13860                       else
13861                         *obufp++ = 'w';
13862                       used_prefixes |= (prefixes & PREFIX_DATA);
13863                     }
13864                 }
13865             }
13866           else
13867             {
13868               if (l != 1 || len != 2 || last[0] != 'L')
13869                 {
13870                   SAVE_LAST (*p);
13871                   break;
13872                 }
13873
13874               if ((prefixes & PREFIX_DATA)
13875                   || (rex & REX_W)
13876                   || (sizeflag & SUFFIX_ALWAYS))
13877                 {
13878                   USED_REX (REX_W);
13879                   if (rex & REX_W)
13880                     *obufp++ = 'q';
13881                   else
13882                     {
13883                       if (sizeflag & DFLAG)
13884                         *obufp++ = intel_syntax ? 'd' : 'l';
13885                       else
13886                         *obufp++ = 'w';
13887                       used_prefixes |= (prefixes & PREFIX_DATA);
13888                     }
13889                 }
13890             }
13891           break;
13892         case 'U':
13893           if (intel_syntax)
13894             break;
13895           if (address_mode == mode_64bit
13896               && ((sizeflag & DFLAG) || (rex & REX_W)))
13897             {
13898               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13899                 *obufp++ = 'q';
13900               break;
13901             }
13902           /* Fall through.  */
13903           goto case_Q;
13904         case 'Q':
13905           if (l == 0 && len == 1)
13906             {
13907 case_Q:
13908               if (intel_syntax && !alt)
13909                 break;
13910               USED_REX (REX_W);
13911               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13912                 {
13913                   if (rex & REX_W)
13914                     *obufp++ = 'q';
13915                   else
13916                     {
13917                       if (sizeflag & DFLAG)
13918                         *obufp++ = intel_syntax ? 'd' : 'l';
13919                       else
13920                         *obufp++ = 'w';
13921                       used_prefixes |= (prefixes & PREFIX_DATA);
13922                     }
13923                 }
13924             }
13925           else
13926             {
13927               if (l != 1 || len != 2 || last[0] != 'L')
13928                 {
13929                   SAVE_LAST (*p);
13930                   break;
13931                 }
13932               if (intel_syntax
13933                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13934                 break;
13935               if ((rex & REX_W))
13936                 {
13937                   USED_REX (REX_W);
13938                   *obufp++ = 'q';
13939                 }
13940               else
13941                 *obufp++ = 'l';
13942             }
13943           break;
13944         case 'R':
13945           USED_REX (REX_W);
13946           if (rex & REX_W)
13947             *obufp++ = 'q';
13948           else if (sizeflag & DFLAG)
13949             {
13950               if (intel_syntax)
13951                   *obufp++ = 'd';
13952               else
13953                   *obufp++ = 'l';
13954             }
13955           else
13956             *obufp++ = 'w';
13957           if (intel_syntax && !p[1]
13958               && ((rex & REX_W) || (sizeflag & DFLAG)))
13959             *obufp++ = 'e';
13960           if (!(rex & REX_W))
13961             used_prefixes |= (prefixes & PREFIX_DATA);
13962           break;
13963         case 'V':
13964           if (l == 0 && len == 1)
13965             {
13966               if (intel_syntax)
13967                 break;
13968               if (address_mode == mode_64bit
13969                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13970                 {
13971                   if (sizeflag & SUFFIX_ALWAYS)
13972                     *obufp++ = 'q';
13973                   break;
13974                 }
13975             }
13976           else
13977             {
13978               if (l != 1
13979                   || len != 2
13980                   || last[0] != 'L')
13981                 {
13982                   SAVE_LAST (*p);
13983                   break;
13984                 }
13985
13986               if (rex & REX_W)
13987                 {
13988                   *obufp++ = 'a';
13989                   *obufp++ = 'b';
13990                   *obufp++ = 's';
13991                 }
13992             }
13993           /* Fall through.  */
13994           goto case_S;
13995         case 'S':
13996           if (l == 0 && len == 1)
13997             {
13998 case_S:
13999               if (intel_syntax)
14000                 break;
14001               if (sizeflag & SUFFIX_ALWAYS)
14002                 {
14003                   if (rex & REX_W)
14004                     *obufp++ = 'q';
14005                   else
14006                     {
14007                       if (sizeflag & DFLAG)
14008                         *obufp++ = 'l';
14009                       else
14010                         *obufp++ = 'w';
14011                       used_prefixes |= (prefixes & PREFIX_DATA);
14012                     }
14013                 }
14014             }
14015           else
14016             {
14017               if (l != 1
14018                   || len != 2
14019                   || last[0] != 'L')
14020                 {
14021                   SAVE_LAST (*p);
14022                   break;
14023                 }
14024
14025               if (address_mode == mode_64bit
14026                   && !(prefixes & PREFIX_ADDR))
14027                 {
14028                   *obufp++ = 'a';
14029                   *obufp++ = 'b';
14030                   *obufp++ = 's';
14031                 }
14032
14033               goto case_S;
14034             }
14035           break;
14036         case 'X':
14037           if (l != 0 || len != 1)
14038             {
14039               SAVE_LAST (*p);
14040               break;
14041             }
14042           if (need_vex && vex.prefix)
14043             {
14044               if (vex.prefix == DATA_PREFIX_OPCODE)
14045                 *obufp++ = 'd';
14046               else
14047                 *obufp++ = 's';
14048             }
14049           else
14050             {
14051               if (prefixes & PREFIX_DATA)
14052                 *obufp++ = 'd';
14053               else
14054                 *obufp++ = 's';
14055               used_prefixes |= (prefixes & PREFIX_DATA);
14056             }
14057           break;
14058         case 'Y':
14059           if (l == 0 && len == 1)
14060             {
14061               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14062                 break;
14063               if (rex & REX_W)
14064                 {
14065                   USED_REX (REX_W);
14066                   *obufp++ = 'q';
14067                 }
14068               break;
14069             }
14070           else
14071             {
14072               if (l != 1 || len != 2 || last[0] != 'X')
14073                 {
14074                   SAVE_LAST (*p);
14075                   break;
14076                 }
14077               if (!need_vex)
14078                 abort ();
14079               if (intel_syntax
14080                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14081                 break;
14082               switch (vex.length)
14083                 {
14084                 case 128:
14085                   *obufp++ = 'x';
14086                   break;
14087                 case 256:
14088                   *obufp++ = 'y';
14089                   break;
14090                 default:
14091                   abort ();
14092                 }
14093             }
14094           break;
14095         case 'W':
14096           if (l == 0 && len == 1)
14097             {
14098               /* operand size flag for cwtl, cbtw */
14099               USED_REX (REX_W);
14100               if (rex & REX_W)
14101                 {
14102                   if (intel_syntax)
14103                     *obufp++ = 'd';
14104                   else
14105                     *obufp++ = 'l';
14106                 }
14107               else if (sizeflag & DFLAG)
14108                 *obufp++ = 'w';
14109               else
14110                 *obufp++ = 'b';
14111               if (!(rex & REX_W))
14112                 used_prefixes |= (prefixes & PREFIX_DATA);
14113             }
14114           else
14115             {
14116               if (l != 1
14117                   || len != 2
14118                   || (last[0] != 'X'
14119                       && last[0] != 'L'))
14120                 {
14121                   SAVE_LAST (*p);
14122                   break;
14123                 }
14124               if (!need_vex)
14125                 abort ();
14126               if (last[0] == 'X')
14127                 *obufp++ = vex.w ? 'd': 's';
14128               else
14129                 *obufp++ = vex.w ? 'q': 'd';
14130             }
14131           break;
14132         }
14133       alt = 0;
14134     }
14135   *obufp = 0;
14136   mnemonicendp = obufp;
14137   return 0;
14138 }
14139
14140 static void
14141 oappend (const char *s)
14142 {
14143   obufp = stpcpy (obufp, s);
14144 }
14145
14146 static void
14147 append_seg (void)
14148 {
14149   /* Only print the active segment register.  */
14150   if (!active_seg_prefix)
14151     return;
14152
14153   used_prefixes |= active_seg_prefix;
14154   switch (active_seg_prefix)
14155     {
14156     case PREFIX_CS:
14157       oappend_maybe_intel ("%cs:");
14158       break;
14159     case PREFIX_DS:
14160       oappend_maybe_intel ("%ds:");
14161       break;
14162     case PREFIX_SS:
14163       oappend_maybe_intel ("%ss:");
14164       break;
14165     case PREFIX_ES:
14166       oappend_maybe_intel ("%es:");
14167       break;
14168     case PREFIX_FS:
14169       oappend_maybe_intel ("%fs:");
14170       break;
14171     case PREFIX_GS:
14172       oappend_maybe_intel ("%gs:");
14173       break;
14174     default:
14175       break;
14176     }
14177 }
14178
14179 static void
14180 OP_indirE (int bytemode, int sizeflag)
14181 {
14182   if (!intel_syntax)
14183     oappend ("*");
14184   OP_E (bytemode, sizeflag);
14185 }
14186
14187 static void
14188 print_operand_value (char *buf, int hex, bfd_vma disp)
14189 {
14190   if (address_mode == mode_64bit)
14191     {
14192       if (hex)
14193         {
14194           char tmp[30];
14195           int i;
14196           buf[0] = '0';
14197           buf[1] = 'x';
14198           sprintf_vma (tmp, disp);
14199           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14200           strcpy (buf + 2, tmp + i);
14201         }
14202       else
14203         {
14204           bfd_signed_vma v = disp;
14205           char tmp[30];
14206           int i;
14207           if (v < 0)
14208             {
14209               *(buf++) = '-';
14210               v = -disp;
14211               /* Check for possible overflow on 0x8000000000000000.  */
14212               if (v < 0)
14213                 {
14214                   strcpy (buf, "9223372036854775808");
14215                   return;
14216                 }
14217             }
14218           if (!v)
14219             {
14220               strcpy (buf, "0");
14221               return;
14222             }
14223
14224           i = 0;
14225           tmp[29] = 0;
14226           while (v)
14227             {
14228               tmp[28 - i] = (v % 10) + '0';
14229               v /= 10;
14230               i++;
14231             }
14232           strcpy (buf, tmp + 29 - i);
14233         }
14234     }
14235   else
14236     {
14237       if (hex)
14238         sprintf (buf, "0x%x", (unsigned int) disp);
14239       else
14240         sprintf (buf, "%d", (int) disp);
14241     }
14242 }
14243
14244 /* Put DISP in BUF as signed hex number.  */
14245
14246 static void
14247 print_displacement (char *buf, bfd_vma disp)
14248 {
14249   bfd_signed_vma val = disp;
14250   char tmp[30];
14251   int i, j = 0;
14252
14253   if (val < 0)
14254     {
14255       buf[j++] = '-';
14256       val = -disp;
14257
14258       /* Check for possible overflow.  */
14259       if (val < 0)
14260         {
14261           switch (address_mode)
14262             {
14263             case mode_64bit:
14264               strcpy (buf + j, "0x8000000000000000");
14265               break;
14266             case mode_32bit:
14267               strcpy (buf + j, "0x80000000");
14268               break;
14269             case mode_16bit:
14270               strcpy (buf + j, "0x8000");
14271               break;
14272             }
14273           return;
14274         }
14275     }
14276
14277   buf[j++] = '0';
14278   buf[j++] = 'x';
14279
14280   sprintf_vma (tmp, (bfd_vma) val);
14281   for (i = 0; tmp[i] == '0'; i++)
14282     continue;
14283   if (tmp[i] == '\0')
14284     i--;
14285   strcpy (buf + j, tmp + i);
14286 }
14287
14288 static void
14289 intel_operand_size (int bytemode, int sizeflag)
14290 {
14291   if (vex.evex
14292       && vex.b
14293       && (bytemode == x_mode
14294           || bytemode == evex_half_bcst_xmmq_mode))
14295     {
14296       if (vex.w)
14297         oappend ("QWORD PTR ");
14298       else
14299         oappend ("DWORD PTR ");
14300       return;
14301     }
14302   switch (bytemode)
14303     {
14304     case b_mode:
14305     case b_swap_mode:
14306     case dqb_mode:
14307     case db_mode:
14308       oappend ("BYTE PTR ");
14309       break;
14310     case w_mode:
14311     case dw_mode:
14312     case dqw_mode:
14313     case dqw_swap_mode:
14314       oappend ("WORD PTR ");
14315       break;
14316     case stack_v_mode:
14317       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14318         {
14319           oappend ("QWORD PTR ");
14320           break;
14321         }
14322       /* FALLTHRU */
14323     case v_mode:
14324     case v_swap_mode:
14325     case dq_mode:
14326       USED_REX (REX_W);
14327       if (rex & REX_W)
14328         oappend ("QWORD PTR ");
14329       else
14330         {
14331           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14332             oappend ("DWORD PTR ");
14333           else
14334             oappend ("WORD PTR ");
14335           used_prefixes |= (prefixes & PREFIX_DATA);
14336         }
14337       break;
14338     case z_mode:
14339       if ((rex & REX_W) || (sizeflag & DFLAG))
14340         *obufp++ = 'D';
14341       oappend ("WORD PTR ");
14342       if (!(rex & REX_W))
14343         used_prefixes |= (prefixes & PREFIX_DATA);
14344       break;
14345     case a_mode:
14346       if (sizeflag & DFLAG)
14347         oappend ("QWORD PTR ");
14348       else
14349         oappend ("DWORD PTR ");
14350       used_prefixes |= (prefixes & PREFIX_DATA);
14351       break;
14352     case d_mode:
14353     case d_scalar_mode:
14354     case d_scalar_swap_mode:
14355     case d_swap_mode:
14356     case dqd_mode:
14357       oappend ("DWORD PTR ");
14358       break;
14359     case q_mode:
14360     case q_scalar_mode:
14361     case q_scalar_swap_mode:
14362     case q_swap_mode:
14363       oappend ("QWORD PTR ");
14364       break;
14365     case m_mode:
14366       if (address_mode == mode_64bit)
14367         oappend ("QWORD PTR ");
14368       else
14369         oappend ("DWORD PTR ");
14370       break;
14371     case f_mode:
14372       if (sizeflag & DFLAG)
14373         oappend ("FWORD PTR ");
14374       else
14375         oappend ("DWORD PTR ");
14376       used_prefixes |= (prefixes & PREFIX_DATA);
14377       break;
14378     case t_mode:
14379       oappend ("TBYTE PTR ");
14380       break;
14381     case x_mode:
14382     case x_swap_mode:
14383     case evex_x_gscat_mode:
14384     case evex_x_nobcst_mode:
14385       if (need_vex)
14386         {
14387           switch (vex.length)
14388             {
14389             case 128:
14390               oappend ("XMMWORD PTR ");
14391               break;
14392             case 256:
14393               oappend ("YMMWORD PTR ");
14394               break;
14395             case 512:
14396               oappend ("ZMMWORD PTR ");
14397               break;
14398             default:
14399               abort ();
14400             }
14401         }
14402       else
14403         oappend ("XMMWORD PTR ");
14404       break;
14405     case xmm_mode:
14406       oappend ("XMMWORD PTR ");
14407       break;
14408     case ymm_mode:
14409       oappend ("YMMWORD PTR ");
14410       break;
14411     case xmmq_mode:
14412     case evex_half_bcst_xmmq_mode:
14413       if (!need_vex)
14414         abort ();
14415
14416       switch (vex.length)
14417         {
14418         case 128:
14419           oappend ("QWORD PTR ");
14420           break;
14421         case 256:
14422           oappend ("XMMWORD PTR ");
14423           break;
14424         case 512:
14425           oappend ("YMMWORD PTR ");
14426           break;
14427         default:
14428           abort ();
14429         }
14430       break;
14431     case xmm_mb_mode:
14432       if (!need_vex)
14433         abort ();
14434
14435       switch (vex.length)
14436         {
14437         case 128:
14438         case 256:
14439         case 512:
14440           oappend ("BYTE PTR ");
14441           break;
14442         default:
14443           abort ();
14444         }
14445       break;
14446     case xmm_mw_mode:
14447       if (!need_vex)
14448         abort ();
14449
14450       switch (vex.length)
14451         {
14452         case 128:
14453         case 256:
14454         case 512:
14455           oappend ("WORD PTR ");
14456           break;
14457         default:
14458           abort ();
14459         }
14460       break;
14461     case xmm_md_mode:
14462       if (!need_vex)
14463         abort ();
14464
14465       switch (vex.length)
14466         {
14467         case 128:
14468         case 256:
14469         case 512:
14470           oappend ("DWORD PTR ");
14471           break;
14472         default:
14473           abort ();
14474         }
14475       break;
14476     case xmm_mq_mode:
14477       if (!need_vex)
14478         abort ();
14479
14480       switch (vex.length)
14481         {
14482         case 128:
14483         case 256:
14484         case 512:
14485           oappend ("QWORD PTR ");
14486           break;
14487         default:
14488           abort ();
14489         }
14490       break;
14491     case xmmdw_mode:
14492       if (!need_vex)
14493         abort ();
14494
14495       switch (vex.length)
14496         {
14497         case 128:
14498           oappend ("WORD PTR ");
14499           break;
14500         case 256:
14501           oappend ("DWORD PTR ");
14502           break;
14503         case 512:
14504           oappend ("QWORD PTR ");
14505           break;
14506         default:
14507           abort ();
14508         }
14509       break;
14510     case xmmqd_mode:
14511       if (!need_vex)
14512         abort ();
14513
14514       switch (vex.length)
14515         {
14516         case 128:
14517           oappend ("DWORD PTR ");
14518           break;
14519         case 256:
14520           oappend ("QWORD PTR ");
14521           break;
14522         case 512:
14523           oappend ("XMMWORD PTR ");
14524           break;
14525         default:
14526           abort ();
14527         }
14528       break;
14529     case ymmq_mode:
14530       if (!need_vex)
14531         abort ();
14532
14533       switch (vex.length)
14534         {
14535         case 128:
14536           oappend ("QWORD PTR ");
14537           break;
14538         case 256:
14539           oappend ("YMMWORD PTR ");
14540           break;
14541         case 512:
14542           oappend ("ZMMWORD PTR ");
14543           break;
14544         default:
14545           abort ();
14546         }
14547       break;
14548     case ymmxmm_mode:
14549       if (!need_vex)
14550         abort ();
14551
14552       switch (vex.length)
14553         {
14554         case 128:
14555         case 256:
14556           oappend ("XMMWORD PTR ");
14557           break;
14558         default:
14559           abort ();
14560         }
14561       break;
14562     case o_mode:
14563       oappend ("OWORD PTR ");
14564       break;
14565     case xmm_mdq_mode:
14566     case vex_w_dq_mode:
14567     case vex_scalar_w_dq_mode:
14568       if (!need_vex)
14569         abort ();
14570
14571       if (vex.w)
14572         oappend ("QWORD PTR ");
14573       else
14574         oappend ("DWORD PTR ");
14575       break;
14576     case vex_vsib_d_w_dq_mode:
14577     case vex_vsib_q_w_dq_mode:
14578       if (!need_vex)
14579         abort ();
14580
14581       if (!vex.evex)
14582         {
14583           if (vex.w)
14584             oappend ("QWORD PTR ");
14585           else
14586             oappend ("DWORD PTR ");
14587         }
14588       else
14589         {
14590           switch (vex.length)
14591             {
14592             case 128:
14593               oappend ("XMMWORD PTR ");
14594               break;
14595             case 256:
14596               oappend ("YMMWORD PTR ");
14597               break;
14598             case 512:
14599               oappend ("ZMMWORD PTR ");
14600               break;
14601             default:
14602               abort ();
14603             }
14604         }
14605       break;
14606     case vex_vsib_q_w_d_mode:
14607     case vex_vsib_d_w_d_mode:
14608       if (!need_vex || !vex.evex)
14609         abort ();
14610
14611       switch (vex.length)
14612         {
14613         case 128:
14614           oappend ("QWORD PTR ");
14615           break;
14616         case 256:
14617           oappend ("XMMWORD PTR ");
14618           break;
14619         case 512:
14620           oappend ("YMMWORD PTR ");
14621           break;
14622         default:
14623           abort ();
14624         }
14625
14626       break;
14627     case mask_bd_mode:
14628       if (!need_vex || vex.length != 128)
14629         abort ();
14630       if (vex.w)
14631         oappend ("DWORD PTR ");
14632       else
14633         oappend ("BYTE PTR ");
14634       break;
14635     case mask_mode:
14636       if (!need_vex)
14637         abort ();
14638       if (vex.w)
14639         oappend ("QWORD PTR ");
14640       else
14641         oappend ("WORD PTR ");
14642       break;
14643     case v_bnd_mode:
14644     default:
14645       break;
14646     }
14647 }
14648
14649 static void
14650 OP_E_register (int bytemode, int sizeflag)
14651 {
14652   int reg = modrm.rm;
14653   const char **names;
14654
14655   USED_REX (REX_B);
14656   if ((rex & REX_B))
14657     reg += 8;
14658
14659   if ((sizeflag & SUFFIX_ALWAYS)
14660       && (bytemode == b_swap_mode
14661           || bytemode == v_swap_mode
14662           || bytemode == dqw_swap_mode))
14663     swap_operand ();
14664
14665   switch (bytemode)
14666     {
14667     case b_mode:
14668     case b_swap_mode:
14669       USED_REX (0);
14670       if (rex)
14671         names = names8rex;
14672       else
14673         names = names8;
14674       break;
14675     case w_mode:
14676       names = names16;
14677       break;
14678     case d_mode:
14679     case dw_mode:
14680     case db_mode:
14681       names = names32;
14682       break;
14683     case q_mode:
14684       names = names64;
14685       break;
14686     case m_mode:
14687     case v_bnd_mode:
14688       names = address_mode == mode_64bit ? names64 : names32;
14689       break;
14690     case bnd_mode:
14691       names = names_bnd;
14692       break;
14693     case stack_v_mode:
14694       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14695         {
14696           names = names64;
14697           break;
14698         }
14699       bytemode = v_mode;
14700       /* FALLTHRU */
14701     case v_mode:
14702     case v_swap_mode:
14703     case dq_mode:
14704     case dqb_mode:
14705     case dqd_mode:
14706     case dqw_mode:
14707     case dqw_swap_mode:
14708       USED_REX (REX_W);
14709       if (rex & REX_W)
14710         names = names64;
14711       else
14712         {
14713           if ((sizeflag & DFLAG)
14714               || (bytemode != v_mode
14715                   && bytemode != v_swap_mode))
14716             names = names32;
14717           else
14718             names = names16;
14719           used_prefixes |= (prefixes & PREFIX_DATA);
14720         }
14721       break;
14722     case mask_bd_mode:
14723     case mask_mode:
14724       names = names_mask;
14725       break;
14726     case 0:
14727       return;
14728     default:
14729       oappend (INTERNAL_DISASSEMBLER_ERROR);
14730       return;
14731     }
14732   oappend (names[reg]);
14733 }
14734
14735 static void
14736 OP_E_memory (int bytemode, int sizeflag)
14737 {
14738   bfd_vma disp = 0;
14739   int add = (rex & REX_B) ? 8 : 0;
14740   int riprel = 0;
14741   int shift;
14742
14743   if (vex.evex)
14744     {
14745       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14746       if (vex.b
14747           && bytemode != x_mode
14748           && bytemode != xmmq_mode
14749           && bytemode != evex_half_bcst_xmmq_mode)
14750         {
14751           BadOp ();
14752           return;
14753         }
14754       switch (bytemode)
14755         {
14756         case dqw_mode:
14757         case dw_mode:
14758         case dqw_swap_mode:
14759           shift = 1;
14760           break;
14761         case dqb_mode:
14762         case db_mode:
14763           shift = 0;
14764           break;
14765         case vex_vsib_d_w_dq_mode:
14766         case vex_vsib_d_w_d_mode:
14767         case vex_vsib_q_w_dq_mode:
14768         case vex_vsib_q_w_d_mode:
14769         case evex_x_gscat_mode:
14770         case xmm_mdq_mode:
14771           shift = vex.w ? 3 : 2;
14772           break;
14773         case x_mode:
14774         case evex_half_bcst_xmmq_mode:
14775         case xmmq_mode:
14776           if (vex.b)
14777             {
14778               shift = vex.w ? 3 : 2;
14779               break;
14780             }
14781           /* Fall through if vex.b == 0.  */
14782         case xmmqd_mode:
14783         case xmmdw_mode:
14784         case ymmq_mode:
14785         case evex_x_nobcst_mode:
14786         case x_swap_mode:
14787           switch (vex.length)
14788             {
14789             case 128:
14790               shift = 4;
14791               break;
14792             case 256:
14793               shift = 5;
14794               break;
14795             case 512:
14796               shift = 6;
14797               break;
14798             default:
14799               abort ();
14800             }
14801           break;
14802         case ymm_mode:
14803           shift = 5;
14804           break;
14805         case xmm_mode:
14806           shift = 4;
14807           break;
14808         case xmm_mq_mode:
14809         case q_mode:
14810         case q_scalar_mode:
14811         case q_swap_mode:
14812         case q_scalar_swap_mode:
14813           shift = 3;
14814           break;
14815         case dqd_mode:
14816         case xmm_md_mode:
14817         case d_mode:
14818         case d_scalar_mode:
14819         case d_swap_mode:
14820         case d_scalar_swap_mode:
14821           shift = 2;
14822           break;
14823         case xmm_mw_mode:
14824           shift = 1;
14825           break;
14826         case xmm_mb_mode:
14827           shift = 0;
14828           break;
14829         default:
14830           abort ();
14831         }
14832       /* Make necessary corrections to shift for modes that need it.
14833          For these modes we currently have shift 4, 5 or 6 depending on
14834          vex.length (it corresponds to xmmword, ymmword or zmmword
14835          operand).  We might want to make it 3, 4 or 5 (e.g. for
14836          xmmq_mode).  In case of broadcast enabled the corrections
14837          aren't needed, as element size is always 32 or 64 bits.  */
14838       if (!vex.b
14839           && (bytemode == xmmq_mode
14840               || bytemode == evex_half_bcst_xmmq_mode))
14841         shift -= 1;
14842       else if (bytemode == xmmqd_mode)
14843         shift -= 2;
14844       else if (bytemode == xmmdw_mode)
14845         shift -= 3;
14846       else if (bytemode == ymmq_mode && vex.length == 128)
14847         shift -= 1;
14848     }
14849   else
14850     shift = 0;
14851
14852   USED_REX (REX_B);
14853   if (intel_syntax)
14854     intel_operand_size (bytemode, sizeflag);
14855   append_seg ();
14856
14857   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14858     {
14859       /* 32/64 bit address mode */
14860       int havedisp;
14861       int havesib;
14862       int havebase;
14863       int haveindex;
14864       int needindex;
14865       int base, rbase;
14866       int vindex = 0;
14867       int scale = 0;
14868       int addr32flag = !((sizeflag & AFLAG)
14869                          || bytemode == v_bnd_mode
14870                          || bytemode == bnd_mode);
14871       const char **indexes64 = names64;
14872       const char **indexes32 = names32;
14873
14874       havesib = 0;
14875       havebase = 1;
14876       haveindex = 0;
14877       base = modrm.rm;
14878
14879       if (base == 4)
14880         {
14881           havesib = 1;
14882           vindex = sib.index;
14883           USED_REX (REX_X);
14884           if (rex & REX_X)
14885             vindex += 8;
14886           switch (bytemode)
14887             {
14888             case vex_vsib_d_w_dq_mode:
14889             case vex_vsib_d_w_d_mode:
14890             case vex_vsib_q_w_dq_mode:
14891             case vex_vsib_q_w_d_mode:
14892               if (!need_vex)
14893                 abort ();
14894               if (vex.evex)
14895                 {
14896                   if (!vex.v)
14897                     vindex += 16;
14898                 }
14899
14900               haveindex = 1;
14901               switch (vex.length)
14902                 {
14903                 case 128:
14904                   indexes64 = indexes32 = names_xmm;
14905                   break;
14906                 case 256:
14907                   if (!vex.w
14908                       || bytemode == vex_vsib_q_w_dq_mode
14909                       || bytemode == vex_vsib_q_w_d_mode)
14910                     indexes64 = indexes32 = names_ymm;
14911                   else
14912                     indexes64 = indexes32 = names_xmm;
14913                   break;
14914                 case 512:
14915                   if (!vex.w
14916                       || bytemode == vex_vsib_q_w_dq_mode
14917                       || bytemode == vex_vsib_q_w_d_mode)
14918                     indexes64 = indexes32 = names_zmm;
14919                   else
14920                     indexes64 = indexes32 = names_ymm;
14921                   break;
14922                 default:
14923                   abort ();
14924                 }
14925               break;
14926             default:
14927               haveindex = vindex != 4;
14928               break;
14929             }
14930           scale = sib.scale;
14931           base = sib.base;
14932           codep++;
14933         }
14934       rbase = base + add;
14935
14936       switch (modrm.mod)
14937         {
14938         case 0:
14939           if (base == 5)
14940             {
14941               havebase = 0;
14942               if (address_mode == mode_64bit && !havesib)
14943                 riprel = 1;
14944               disp = get32s ();
14945             }
14946           break;
14947         case 1:
14948           FETCH_DATA (the_info, codep + 1);
14949           disp = *codep++;
14950           if ((disp & 0x80) != 0)
14951             disp -= 0x100;
14952           if (vex.evex && shift > 0)
14953             disp <<= shift;
14954           break;
14955         case 2:
14956           disp = get32s ();
14957           break;
14958         }
14959
14960       /* In 32bit mode, we need index register to tell [offset] from
14961          [eiz*1 + offset].  */
14962       needindex = (havesib
14963                    && !havebase
14964                    && !haveindex
14965                    && address_mode == mode_32bit);
14966       havedisp = (havebase
14967                   || needindex
14968                   || (havesib && (haveindex || scale != 0)));
14969
14970       if (!intel_syntax)
14971         if (modrm.mod != 0 || base == 5)
14972           {
14973             if (havedisp || riprel)
14974               print_displacement (scratchbuf, disp);
14975             else
14976               print_operand_value (scratchbuf, 1, disp);
14977             oappend (scratchbuf);
14978             if (riprel)
14979               {
14980                 set_op (disp, 1);
14981                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14982               }
14983           }
14984
14985       if ((havebase || haveindex || riprel)
14986           && (bytemode != v_bnd_mode)
14987           && (bytemode != bnd_mode))
14988         used_prefixes |= PREFIX_ADDR;
14989
14990       if (havedisp || (intel_syntax && riprel))
14991         {
14992           *obufp++ = open_char;
14993           if (intel_syntax && riprel)
14994             {
14995               set_op (disp, 1);
14996               oappend (sizeflag & AFLAG ? "rip" : "eip");
14997             }
14998           *obufp = '\0';
14999           if (havebase)
15000             oappend (address_mode == mode_64bit && !addr32flag
15001                      ? names64[rbase] : names32[rbase]);
15002           if (havesib)
15003             {
15004               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15005                  print index to tell base + index from base.  */
15006               if (scale != 0
15007                   || needindex
15008                   || haveindex
15009                   || (havebase && base != ESP_REG_NUM))
15010                 {
15011                   if (!intel_syntax || havebase)
15012                     {
15013                       *obufp++ = separator_char;
15014                       *obufp = '\0';
15015                     }
15016                   if (haveindex)
15017                     oappend (address_mode == mode_64bit && !addr32flag
15018                              ? indexes64[vindex] : indexes32[vindex]);
15019                   else
15020                     oappend (address_mode == mode_64bit && !addr32flag
15021                              ? index64 : index32);
15022
15023                   *obufp++ = scale_char;
15024                   *obufp = '\0';
15025                   sprintf (scratchbuf, "%d", 1 << scale);
15026                   oappend (scratchbuf);
15027                 }
15028             }
15029           if (intel_syntax
15030               && (disp || modrm.mod != 0 || base == 5))
15031             {
15032               if (!havedisp || (bfd_signed_vma) disp >= 0)
15033                 {
15034                   *obufp++ = '+';
15035                   *obufp = '\0';
15036                 }
15037               else if (modrm.mod != 1 && disp != -disp)
15038                 {
15039                   *obufp++ = '-';
15040                   *obufp = '\0';
15041                   disp = - (bfd_signed_vma) disp;
15042                 }
15043
15044               if (havedisp)
15045                 print_displacement (scratchbuf, disp);
15046               else
15047                 print_operand_value (scratchbuf, 1, disp);
15048               oappend (scratchbuf);
15049             }
15050
15051           *obufp++ = close_char;
15052           *obufp = '\0';
15053         }
15054       else if (intel_syntax)
15055         {
15056           if (modrm.mod != 0 || base == 5)
15057             {
15058               if (!active_seg_prefix)
15059                 {
15060                   oappend (names_seg[ds_reg - es_reg]);
15061                   oappend (":");
15062                 }
15063               print_operand_value (scratchbuf, 1, disp);
15064               oappend (scratchbuf);
15065             }
15066         }
15067     }
15068   else
15069     {
15070       /* 16 bit address mode */
15071       used_prefixes |= prefixes & PREFIX_ADDR;
15072       switch (modrm.mod)
15073         {
15074         case 0:
15075           if (modrm.rm == 6)
15076             {
15077               disp = get16 ();
15078               if ((disp & 0x8000) != 0)
15079                 disp -= 0x10000;
15080             }
15081           break;
15082         case 1:
15083           FETCH_DATA (the_info, codep + 1);
15084           disp = *codep++;
15085           if ((disp & 0x80) != 0)
15086             disp -= 0x100;
15087           break;
15088         case 2:
15089           disp = get16 ();
15090           if ((disp & 0x8000) != 0)
15091             disp -= 0x10000;
15092           break;
15093         }
15094
15095       if (!intel_syntax)
15096         if (modrm.mod != 0 || modrm.rm == 6)
15097           {
15098             print_displacement (scratchbuf, disp);
15099             oappend (scratchbuf);
15100           }
15101
15102       if (modrm.mod != 0 || modrm.rm != 6)
15103         {
15104           *obufp++ = open_char;
15105           *obufp = '\0';
15106           oappend (index16[modrm.rm]);
15107           if (intel_syntax
15108               && (disp || modrm.mod != 0 || modrm.rm == 6))
15109             {
15110               if ((bfd_signed_vma) disp >= 0)
15111                 {
15112                   *obufp++ = '+';
15113                   *obufp = '\0';
15114                 }
15115               else if (modrm.mod != 1)
15116                 {
15117                   *obufp++ = '-';
15118                   *obufp = '\0';
15119                   disp = - (bfd_signed_vma) disp;
15120                 }
15121
15122               print_displacement (scratchbuf, disp);
15123               oappend (scratchbuf);
15124             }
15125
15126           *obufp++ = close_char;
15127           *obufp = '\0';
15128         }
15129       else if (intel_syntax)
15130         {
15131           if (!active_seg_prefix)
15132             {
15133               oappend (names_seg[ds_reg - es_reg]);
15134               oappend (":");
15135             }
15136           print_operand_value (scratchbuf, 1, disp & 0xffff);
15137           oappend (scratchbuf);
15138         }
15139     }
15140   if (vex.evex && vex.b
15141       && (bytemode == x_mode
15142           || bytemode == xmmq_mode
15143           || bytemode == evex_half_bcst_xmmq_mode))
15144     {
15145       if (vex.w
15146           || bytemode == xmmq_mode
15147           || bytemode == evex_half_bcst_xmmq_mode)
15148         {
15149           switch (vex.length)
15150             {
15151             case 128:
15152               oappend ("{1to2}");
15153               break;
15154             case 256:
15155               oappend ("{1to4}");
15156               break;
15157             case 512:
15158               oappend ("{1to8}");
15159               break;
15160             default:
15161               abort ();
15162             }
15163         }
15164       else
15165         {
15166           switch (vex.length)
15167             {
15168             case 128:
15169               oappend ("{1to4}");
15170               break;
15171             case 256:
15172               oappend ("{1to8}");
15173               break;
15174             case 512:
15175               oappend ("{1to16}");
15176               break;
15177             default:
15178               abort ();
15179             }
15180         }
15181     }
15182 }
15183
15184 static void
15185 OP_E (int bytemode, int sizeflag)
15186 {
15187   /* Skip mod/rm byte.  */
15188   MODRM_CHECK;
15189   codep++;
15190
15191   if (modrm.mod == 3)
15192     OP_E_register (bytemode, sizeflag);
15193   else
15194     OP_E_memory (bytemode, sizeflag);
15195 }
15196
15197 static void
15198 OP_G (int bytemode, int sizeflag)
15199 {
15200   int add = 0;
15201   USED_REX (REX_R);
15202   if (rex & REX_R)
15203     add += 8;
15204   switch (bytemode)
15205     {
15206     case b_mode:
15207       USED_REX (0);
15208       if (rex)
15209         oappend (names8rex[modrm.reg + add]);
15210       else
15211         oappend (names8[modrm.reg + add]);
15212       break;
15213     case w_mode:
15214       oappend (names16[modrm.reg + add]);
15215       break;
15216     case d_mode:
15217     case db_mode:
15218     case dw_mode:
15219       oappend (names32[modrm.reg + add]);
15220       break;
15221     case q_mode:
15222       oappend (names64[modrm.reg + add]);
15223       break;
15224     case bnd_mode:
15225       oappend (names_bnd[modrm.reg]);
15226       break;
15227     case v_mode:
15228     case dq_mode:
15229     case dqb_mode:
15230     case dqd_mode:
15231     case dqw_mode:
15232     case dqw_swap_mode:
15233       USED_REX (REX_W);
15234       if (rex & REX_W)
15235         oappend (names64[modrm.reg + add]);
15236       else
15237         {
15238           if ((sizeflag & DFLAG) || bytemode != v_mode)
15239             oappend (names32[modrm.reg + add]);
15240           else
15241             oappend (names16[modrm.reg + add]);
15242           used_prefixes |= (prefixes & PREFIX_DATA);
15243         }
15244       break;
15245     case m_mode:
15246       if (address_mode == mode_64bit)
15247         oappend (names64[modrm.reg + add]);
15248       else
15249         oappend (names32[modrm.reg + add]);
15250       break;
15251     case mask_bd_mode:
15252     case mask_mode:
15253       oappend (names_mask[modrm.reg + add]);
15254       break;
15255     default:
15256       oappend (INTERNAL_DISASSEMBLER_ERROR);
15257       break;
15258     }
15259 }
15260
15261 static bfd_vma
15262 get64 (void)
15263 {
15264   bfd_vma x;
15265 #ifdef BFD64
15266   unsigned int a;
15267   unsigned int b;
15268
15269   FETCH_DATA (the_info, codep + 8);
15270   a = *codep++ & 0xff;
15271   a |= (*codep++ & 0xff) << 8;
15272   a |= (*codep++ & 0xff) << 16;
15273   a |= (*codep++ & 0xff) << 24;
15274   b = *codep++ & 0xff;
15275   b |= (*codep++ & 0xff) << 8;
15276   b |= (*codep++ & 0xff) << 16;
15277   b |= (*codep++ & 0xff) << 24;
15278   x = a + ((bfd_vma) b << 32);
15279 #else
15280   abort ();
15281   x = 0;
15282 #endif
15283   return x;
15284 }
15285
15286 static bfd_signed_vma
15287 get32 (void)
15288 {
15289   bfd_signed_vma x = 0;
15290
15291   FETCH_DATA (the_info, codep + 4);
15292   x = *codep++ & (bfd_signed_vma) 0xff;
15293   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15294   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15295   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15296   return x;
15297 }
15298
15299 static bfd_signed_vma
15300 get32s (void)
15301 {
15302   bfd_signed_vma x = 0;
15303
15304   FETCH_DATA (the_info, codep + 4);
15305   x = *codep++ & (bfd_signed_vma) 0xff;
15306   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15307   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15308   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15309
15310   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15311
15312   return x;
15313 }
15314
15315 static int
15316 get16 (void)
15317 {
15318   int x = 0;
15319
15320   FETCH_DATA (the_info, codep + 2);
15321   x = *codep++ & 0xff;
15322   x |= (*codep++ & 0xff) << 8;
15323   return x;
15324 }
15325
15326 static void
15327 set_op (bfd_vma op, int riprel)
15328 {
15329   op_index[op_ad] = op_ad;
15330   if (address_mode == mode_64bit)
15331     {
15332       op_address[op_ad] = op;
15333       op_riprel[op_ad] = riprel;
15334     }
15335   else
15336     {
15337       /* Mask to get a 32-bit address.  */
15338       op_address[op_ad] = op & 0xffffffff;
15339       op_riprel[op_ad] = riprel & 0xffffffff;
15340     }
15341 }
15342
15343 static void
15344 OP_REG (int code, int sizeflag)
15345 {
15346   const char *s;
15347   int add;
15348
15349   switch (code)
15350     {
15351     case es_reg: case ss_reg: case cs_reg:
15352     case ds_reg: case fs_reg: case gs_reg:
15353       oappend (names_seg[code - es_reg]);
15354       return;
15355     }
15356
15357   USED_REX (REX_B);
15358   if (rex & REX_B)
15359     add = 8;
15360   else
15361     add = 0;
15362
15363   switch (code)
15364     {
15365     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15366     case sp_reg: case bp_reg: case si_reg: case di_reg:
15367       s = names16[code - ax_reg + add];
15368       break;
15369     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15370     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15371       USED_REX (0);
15372       if (rex)
15373         s = names8rex[code - al_reg + add];
15374       else
15375         s = names8[code - al_reg];
15376       break;
15377     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15378     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15379       if (address_mode == mode_64bit
15380           && ((sizeflag & DFLAG) || (rex & REX_W)))
15381         {
15382           s = names64[code - rAX_reg + add];
15383           break;
15384         }
15385       code += eAX_reg - rAX_reg;
15386       /* Fall through.  */
15387     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15388     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15389       USED_REX (REX_W);
15390       if (rex & REX_W)
15391         s = names64[code - eAX_reg + add];
15392       else
15393         {
15394           if (sizeflag & DFLAG)
15395             s = names32[code - eAX_reg + add];
15396           else
15397             s = names16[code - eAX_reg + add];
15398           used_prefixes |= (prefixes & PREFIX_DATA);
15399         }
15400       break;
15401     default:
15402       s = INTERNAL_DISASSEMBLER_ERROR;
15403       break;
15404     }
15405   oappend (s);
15406 }
15407
15408 static void
15409 OP_IMREG (int code, int sizeflag)
15410 {
15411   const char *s;
15412
15413   switch (code)
15414     {
15415     case indir_dx_reg:
15416       if (intel_syntax)
15417         s = "dx";
15418       else
15419         s = "(%dx)";
15420       break;
15421     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15422     case sp_reg: case bp_reg: case si_reg: case di_reg:
15423       s = names16[code - ax_reg];
15424       break;
15425     case es_reg: case ss_reg: case cs_reg:
15426     case ds_reg: case fs_reg: case gs_reg:
15427       s = names_seg[code - es_reg];
15428       break;
15429     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15430     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15431       USED_REX (0);
15432       if (rex)
15433         s = names8rex[code - al_reg];
15434       else
15435         s = names8[code - al_reg];
15436       break;
15437     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15438     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15439       USED_REX (REX_W);
15440       if (rex & REX_W)
15441         s = names64[code - eAX_reg];
15442       else
15443         {
15444           if (sizeflag & DFLAG)
15445             s = names32[code - eAX_reg];
15446           else
15447             s = names16[code - eAX_reg];
15448           used_prefixes |= (prefixes & PREFIX_DATA);
15449         }
15450       break;
15451     case z_mode_ax_reg:
15452       if ((rex & REX_W) || (sizeflag & DFLAG))
15453         s = *names32;
15454       else
15455         s = *names16;
15456       if (!(rex & REX_W))
15457         used_prefixes |= (prefixes & PREFIX_DATA);
15458       break;
15459     default:
15460       s = INTERNAL_DISASSEMBLER_ERROR;
15461       break;
15462     }
15463   oappend (s);
15464 }
15465
15466 static void
15467 OP_I (int bytemode, int sizeflag)
15468 {
15469   bfd_signed_vma op;
15470   bfd_signed_vma mask = -1;
15471
15472   switch (bytemode)
15473     {
15474     case b_mode:
15475       FETCH_DATA (the_info, codep + 1);
15476       op = *codep++;
15477       mask = 0xff;
15478       break;
15479     case q_mode:
15480       if (address_mode == mode_64bit)
15481         {
15482           op = get32s ();
15483           break;
15484         }
15485       /* Fall through.  */
15486     case v_mode:
15487       USED_REX (REX_W);
15488       if (rex & REX_W)
15489         op = get32s ();
15490       else
15491         {
15492           if (sizeflag & DFLAG)
15493             {
15494               op = get32 ();
15495               mask = 0xffffffff;
15496             }
15497           else
15498             {
15499               op = get16 ();
15500               mask = 0xfffff;
15501             }
15502           used_prefixes |= (prefixes & PREFIX_DATA);
15503         }
15504       break;
15505     case w_mode:
15506       mask = 0xfffff;
15507       op = get16 ();
15508       break;
15509     case const_1_mode:
15510       if (intel_syntax)
15511         oappend ("1");
15512       return;
15513     default:
15514       oappend (INTERNAL_DISASSEMBLER_ERROR);
15515       return;
15516     }
15517
15518   op &= mask;
15519   scratchbuf[0] = '$';
15520   print_operand_value (scratchbuf + 1, 1, op);
15521   oappend_maybe_intel (scratchbuf);
15522   scratchbuf[0] = '\0';
15523 }
15524
15525 static void
15526 OP_I64 (int bytemode, int sizeflag)
15527 {
15528   bfd_signed_vma op;
15529   bfd_signed_vma mask = -1;
15530
15531   if (address_mode != mode_64bit)
15532     {
15533       OP_I (bytemode, sizeflag);
15534       return;
15535     }
15536
15537   switch (bytemode)
15538     {
15539     case b_mode:
15540       FETCH_DATA (the_info, codep + 1);
15541       op = *codep++;
15542       mask = 0xff;
15543       break;
15544     case v_mode:
15545       USED_REX (REX_W);
15546       if (rex & REX_W)
15547         op = get64 ();
15548       else
15549         {
15550           if (sizeflag & DFLAG)
15551             {
15552               op = get32 ();
15553               mask = 0xffffffff;
15554             }
15555           else
15556             {
15557               op = get16 ();
15558               mask = 0xfffff;
15559             }
15560           used_prefixes |= (prefixes & PREFIX_DATA);
15561         }
15562       break;
15563     case w_mode:
15564       mask = 0xfffff;
15565       op = get16 ();
15566       break;
15567     default:
15568       oappend (INTERNAL_DISASSEMBLER_ERROR);
15569       return;
15570     }
15571
15572   op &= mask;
15573   scratchbuf[0] = '$';
15574   print_operand_value (scratchbuf + 1, 1, op);
15575   oappend_maybe_intel (scratchbuf);
15576   scratchbuf[0] = '\0';
15577 }
15578
15579 static void
15580 OP_sI (int bytemode, int sizeflag)
15581 {
15582   bfd_signed_vma op;
15583
15584   switch (bytemode)
15585     {
15586     case b_mode:
15587     case b_T_mode:
15588       FETCH_DATA (the_info, codep + 1);
15589       op = *codep++;
15590       if ((op & 0x80) != 0)
15591         op -= 0x100;
15592       if (bytemode == b_T_mode)
15593         {
15594           if (address_mode != mode_64bit
15595               || !((sizeflag & DFLAG) || (rex & REX_W)))
15596             {
15597               /* The operand-size prefix is overridden by a REX prefix.  */
15598               if ((sizeflag & DFLAG) || (rex & REX_W))
15599                 op &= 0xffffffff;
15600               else
15601                 op &= 0xffff;
15602           }
15603         }
15604       else
15605         {
15606           if (!(rex & REX_W))
15607             {
15608               if (sizeflag & DFLAG)
15609                 op &= 0xffffffff;
15610               else
15611                 op &= 0xffff;
15612             }
15613         }
15614       break;
15615     case v_mode:
15616       /* The operand-size prefix is overridden by a REX prefix.  */
15617       if ((sizeflag & DFLAG) || (rex & REX_W))
15618         op = get32s ();
15619       else
15620         op = get16 ();
15621       break;
15622     default:
15623       oappend (INTERNAL_DISASSEMBLER_ERROR);
15624       return;
15625     }
15626
15627   scratchbuf[0] = '$';
15628   print_operand_value (scratchbuf + 1, 1, op);
15629   oappend_maybe_intel (scratchbuf);
15630 }
15631
15632 static void
15633 OP_J (int bytemode, int sizeflag)
15634 {
15635   bfd_vma disp;
15636   bfd_vma mask = -1;
15637   bfd_vma segment = 0;
15638
15639   switch (bytemode)
15640     {
15641     case b_mode:
15642       FETCH_DATA (the_info, codep + 1);
15643       disp = *codep++;
15644       if ((disp & 0x80) != 0)
15645         disp -= 0x100;
15646       break;
15647     case v_mode:
15648       USED_REX (REX_W);
15649       if ((sizeflag & DFLAG) || (rex & REX_W))
15650         disp = get32s ();
15651       else
15652         {
15653           disp = get16 ();
15654           if ((disp & 0x8000) != 0)
15655             disp -= 0x10000;
15656           /* In 16bit mode, address is wrapped around at 64k within
15657              the same segment.  Otherwise, a data16 prefix on a jump
15658              instruction means that the pc is masked to 16 bits after
15659              the displacement is added!  */
15660           mask = 0xffff;
15661           if ((prefixes & PREFIX_DATA) == 0)
15662             segment = ((start_pc + codep - start_codep)
15663                        & ~((bfd_vma) 0xffff));
15664         }
15665       if (!(rex & REX_W))
15666         used_prefixes |= (prefixes & PREFIX_DATA);
15667       break;
15668     default:
15669       oappend (INTERNAL_DISASSEMBLER_ERROR);
15670       return;
15671     }
15672   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15673   set_op (disp, 0);
15674   print_operand_value (scratchbuf, 1, disp);
15675   oappend (scratchbuf);
15676 }
15677
15678 static void
15679 OP_SEG (int bytemode, int sizeflag)
15680 {
15681   if (bytemode == w_mode)
15682     oappend (names_seg[modrm.reg]);
15683   else
15684     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15685 }
15686
15687 static void
15688 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15689 {
15690   int seg, offset;
15691
15692   if (sizeflag & DFLAG)
15693     {
15694       offset = get32 ();
15695       seg = get16 ();
15696     }
15697   else
15698     {
15699       offset = get16 ();
15700       seg = get16 ();
15701     }
15702   used_prefixes |= (prefixes & PREFIX_DATA);
15703   if (intel_syntax)
15704     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15705   else
15706     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15707   oappend (scratchbuf);
15708 }
15709
15710 static void
15711 OP_OFF (int bytemode, int sizeflag)
15712 {
15713   bfd_vma off;
15714
15715   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15716     intel_operand_size (bytemode, sizeflag);
15717   append_seg ();
15718
15719   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15720     off = get32 ();
15721   else
15722     off = get16 ();
15723
15724   if (intel_syntax)
15725     {
15726       if (!active_seg_prefix)
15727         {
15728           oappend (names_seg[ds_reg - es_reg]);
15729           oappend (":");
15730         }
15731     }
15732   print_operand_value (scratchbuf, 1, off);
15733   oappend (scratchbuf);
15734 }
15735
15736 static void
15737 OP_OFF64 (int bytemode, int sizeflag)
15738 {
15739   bfd_vma off;
15740
15741   if (address_mode != mode_64bit
15742       || (prefixes & PREFIX_ADDR))
15743     {
15744       OP_OFF (bytemode, sizeflag);
15745       return;
15746     }
15747
15748   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15749     intel_operand_size (bytemode, sizeflag);
15750   append_seg ();
15751
15752   off = get64 ();
15753
15754   if (intel_syntax)
15755     {
15756       if (!active_seg_prefix)
15757         {
15758           oappend (names_seg[ds_reg - es_reg]);
15759           oappend (":");
15760         }
15761     }
15762   print_operand_value (scratchbuf, 1, off);
15763   oappend (scratchbuf);
15764 }
15765
15766 static void
15767 ptr_reg (int code, int sizeflag)
15768 {
15769   const char *s;
15770
15771   *obufp++ = open_char;
15772   used_prefixes |= (prefixes & PREFIX_ADDR);
15773   if (address_mode == mode_64bit)
15774     {
15775       if (!(sizeflag & AFLAG))
15776         s = names32[code - eAX_reg];
15777       else
15778         s = names64[code - eAX_reg];
15779     }
15780   else if (sizeflag & AFLAG)
15781     s = names32[code - eAX_reg];
15782   else
15783     s = names16[code - eAX_reg];
15784   oappend (s);
15785   *obufp++ = close_char;
15786   *obufp = 0;
15787 }
15788
15789 static void
15790 OP_ESreg (int code, int sizeflag)
15791 {
15792   if (intel_syntax)
15793     {
15794       switch (codep[-1])
15795         {
15796         case 0x6d:      /* insw/insl */
15797           intel_operand_size (z_mode, sizeflag);
15798           break;
15799         case 0xa5:      /* movsw/movsl/movsq */
15800         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15801         case 0xab:      /* stosw/stosl */
15802         case 0xaf:      /* scasw/scasl */
15803           intel_operand_size (v_mode, sizeflag);
15804           break;
15805         default:
15806           intel_operand_size (b_mode, sizeflag);
15807         }
15808     }
15809   oappend_maybe_intel ("%es:");
15810   ptr_reg (code, sizeflag);
15811 }
15812
15813 static void
15814 OP_DSreg (int code, int sizeflag)
15815 {
15816   if (intel_syntax)
15817     {
15818       switch (codep[-1])
15819         {
15820         case 0x6f:      /* outsw/outsl */
15821           intel_operand_size (z_mode, sizeflag);
15822           break;
15823         case 0xa5:      /* movsw/movsl/movsq */
15824         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15825         case 0xad:      /* lodsw/lodsl/lodsq */
15826           intel_operand_size (v_mode, sizeflag);
15827           break;
15828         default:
15829           intel_operand_size (b_mode, sizeflag);
15830         }
15831     }
15832   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15833      default segment register DS is printed.  */
15834   if (!active_seg_prefix)
15835     active_seg_prefix = PREFIX_DS;
15836   append_seg ();
15837   ptr_reg (code, sizeflag);
15838 }
15839
15840 static void
15841 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15842 {
15843   int add;
15844   if (rex & REX_R)
15845     {
15846       USED_REX (REX_R);
15847       add = 8;
15848     }
15849   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15850     {
15851       all_prefixes[last_lock_prefix] = 0;
15852       used_prefixes |= PREFIX_LOCK;
15853       add = 8;
15854     }
15855   else
15856     add = 0;
15857   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15858   oappend_maybe_intel (scratchbuf);
15859 }
15860
15861 static void
15862 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15863 {
15864   int add;
15865   USED_REX (REX_R);
15866   if (rex & REX_R)
15867     add = 8;
15868   else
15869     add = 0;
15870   if (intel_syntax)
15871     sprintf (scratchbuf, "db%d", modrm.reg + add);
15872   else
15873     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15874   oappend (scratchbuf);
15875 }
15876
15877 static void
15878 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15879 {
15880   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15881   oappend_maybe_intel (scratchbuf);
15882 }
15883
15884 static void
15885 OP_R (int bytemode, int sizeflag)
15886 {
15887   /* Skip mod/rm byte.  */
15888   MODRM_CHECK;
15889   codep++;
15890   OP_E_register (bytemode, sizeflag);
15891 }
15892
15893 static void
15894 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15895 {
15896   int reg = modrm.reg;
15897   const char **names;
15898
15899   used_prefixes |= (prefixes & PREFIX_DATA);
15900   if (prefixes & PREFIX_DATA)
15901     {
15902       names = names_xmm;
15903       USED_REX (REX_R);
15904       if (rex & REX_R)
15905         reg += 8;
15906     }
15907   else
15908     names = names_mm;
15909   oappend (names[reg]);
15910 }
15911
15912 static void
15913 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15914 {
15915   int reg = modrm.reg;
15916   const char **names;
15917
15918   USED_REX (REX_R);
15919   if (rex & REX_R)
15920     reg += 8;
15921   if (vex.evex)
15922     {
15923       if (!vex.r)
15924         reg += 16;
15925     }
15926
15927   if (need_vex
15928       && bytemode != xmm_mode
15929       && bytemode != xmmq_mode
15930       && bytemode != evex_half_bcst_xmmq_mode
15931       && bytemode != ymm_mode
15932       && bytemode != scalar_mode)
15933     {
15934       switch (vex.length)
15935         {
15936         case 128:
15937           names = names_xmm;
15938           break;
15939         case 256:
15940           if (vex.w
15941               || (bytemode != vex_vsib_q_w_dq_mode
15942                   && bytemode != vex_vsib_q_w_d_mode))
15943             names = names_ymm;
15944           else
15945             names = names_xmm;
15946           break;
15947         case 512:
15948           names = names_zmm;
15949           break;
15950         default:
15951           abort ();
15952         }
15953     }
15954   else if (bytemode == xmmq_mode
15955            || bytemode == evex_half_bcst_xmmq_mode)
15956     {
15957       switch (vex.length)
15958         {
15959         case 128:
15960         case 256:
15961           names = names_xmm;
15962           break;
15963         case 512:
15964           names = names_ymm;
15965           break;
15966         default:
15967           abort ();
15968         }
15969     }
15970   else if (bytemode == ymm_mode)
15971     names = names_ymm;
15972   else
15973     names = names_xmm;
15974   oappend (names[reg]);
15975 }
15976
15977 static void
15978 OP_EM (int bytemode, int sizeflag)
15979 {
15980   int reg;
15981   const char **names;
15982
15983   if (modrm.mod != 3)
15984     {
15985       if (intel_syntax
15986           && (bytemode == v_mode || bytemode == v_swap_mode))
15987         {
15988           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15989           used_prefixes |= (prefixes & PREFIX_DATA);
15990         }
15991       OP_E (bytemode, sizeflag);
15992       return;
15993     }
15994
15995   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15996     swap_operand ();
15997
15998   /* Skip mod/rm byte.  */
15999   MODRM_CHECK;
16000   codep++;
16001   used_prefixes |= (prefixes & PREFIX_DATA);
16002   reg = modrm.rm;
16003   if (prefixes & PREFIX_DATA)
16004     {
16005       names = names_xmm;
16006       USED_REX (REX_B);
16007       if (rex & REX_B)
16008         reg += 8;
16009     }
16010   else
16011     names = names_mm;
16012   oappend (names[reg]);
16013 }
16014
16015 /* cvt* are the only instructions in sse2 which have
16016    both SSE and MMX operands and also have 0x66 prefix
16017    in their opcode. 0x66 was originally used to differentiate
16018    between SSE and MMX instruction(operands). So we have to handle the
16019    cvt* separately using OP_EMC and OP_MXC */
16020 static void
16021 OP_EMC (int bytemode, int sizeflag)
16022 {
16023   if (modrm.mod != 3)
16024     {
16025       if (intel_syntax && bytemode == v_mode)
16026         {
16027           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16028           used_prefixes |= (prefixes & PREFIX_DATA);
16029         }
16030       OP_E (bytemode, sizeflag);
16031       return;
16032     }
16033
16034   /* Skip mod/rm byte.  */
16035   MODRM_CHECK;
16036   codep++;
16037   used_prefixes |= (prefixes & PREFIX_DATA);
16038   oappend (names_mm[modrm.rm]);
16039 }
16040
16041 static void
16042 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16043 {
16044   used_prefixes |= (prefixes & PREFIX_DATA);
16045   oappend (names_mm[modrm.reg]);
16046 }
16047
16048 static void
16049 OP_EX (int bytemode, int sizeflag)
16050 {
16051   int reg;
16052   const char **names;
16053
16054   /* Skip mod/rm byte.  */
16055   MODRM_CHECK;
16056   codep++;
16057
16058   if (modrm.mod != 3)
16059     {
16060       OP_E_memory (bytemode, sizeflag);
16061       return;
16062     }
16063
16064   reg = modrm.rm;
16065   USED_REX (REX_B);
16066   if (rex & REX_B)
16067     reg += 8;
16068   if (vex.evex)
16069     {
16070       USED_REX (REX_X);
16071       if ((rex & REX_X))
16072         reg += 16;
16073     }
16074
16075   if ((sizeflag & SUFFIX_ALWAYS)
16076       && (bytemode == x_swap_mode
16077           || bytemode == d_swap_mode
16078           || bytemode == dqw_swap_mode
16079           || bytemode == d_scalar_swap_mode
16080           || bytemode == q_swap_mode
16081           || bytemode == q_scalar_swap_mode))
16082     swap_operand ();
16083
16084   if (need_vex
16085       && bytemode != xmm_mode
16086       && bytemode != xmmdw_mode
16087       && bytemode != xmmqd_mode
16088       && bytemode != xmm_mb_mode
16089       && bytemode != xmm_mw_mode
16090       && bytemode != xmm_md_mode
16091       && bytemode != xmm_mq_mode
16092       && bytemode != xmm_mdq_mode
16093       && bytemode != xmmq_mode
16094       && bytemode != evex_half_bcst_xmmq_mode
16095       && bytemode != ymm_mode
16096       && bytemode != d_scalar_mode
16097       && bytemode != d_scalar_swap_mode
16098       && bytemode != q_scalar_mode
16099       && bytemode != q_scalar_swap_mode
16100       && bytemode != vex_scalar_w_dq_mode)
16101     {
16102       switch (vex.length)
16103         {
16104         case 128:
16105           names = names_xmm;
16106           break;
16107         case 256:
16108           names = names_ymm;
16109           break;
16110         case 512:
16111           names = names_zmm;
16112           break;
16113         default:
16114           abort ();
16115         }
16116     }
16117   else if (bytemode == xmmq_mode
16118            || bytemode == evex_half_bcst_xmmq_mode)
16119     {
16120       switch (vex.length)
16121         {
16122         case 128:
16123         case 256:
16124           names = names_xmm;
16125           break;
16126         case 512:
16127           names = names_ymm;
16128           break;
16129         default:
16130           abort ();
16131         }
16132     }
16133   else if (bytemode == ymm_mode)
16134     names = names_ymm;
16135   else
16136     names = names_xmm;
16137   oappend (names[reg]);
16138 }
16139
16140 static void
16141 OP_MS (int bytemode, int sizeflag)
16142 {
16143   if (modrm.mod == 3)
16144     OP_EM (bytemode, sizeflag);
16145   else
16146     BadOp ();
16147 }
16148
16149 static void
16150 OP_XS (int bytemode, int sizeflag)
16151 {
16152   if (modrm.mod == 3)
16153     OP_EX (bytemode, sizeflag);
16154   else
16155     BadOp ();
16156 }
16157
16158 static void
16159 OP_M (int bytemode, int sizeflag)
16160 {
16161   if (modrm.mod == 3)
16162     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16163     BadOp ();
16164   else
16165     OP_E (bytemode, sizeflag);
16166 }
16167
16168 static void
16169 OP_0f07 (int bytemode, int sizeflag)
16170 {
16171   if (modrm.mod != 3 || modrm.rm != 0)
16172     BadOp ();
16173   else
16174     OP_E (bytemode, sizeflag);
16175 }
16176
16177 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16178    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16179
16180 static void
16181 NOP_Fixup1 (int bytemode, int sizeflag)
16182 {
16183   if ((prefixes & PREFIX_DATA) != 0
16184       || (rex != 0
16185           && rex != 0x48
16186           && address_mode == mode_64bit))
16187     OP_REG (bytemode, sizeflag);
16188   else
16189     strcpy (obuf, "nop");
16190 }
16191
16192 static void
16193 NOP_Fixup2 (int bytemode, int sizeflag)
16194 {
16195   if ((prefixes & PREFIX_DATA) != 0
16196       || (rex != 0
16197           && rex != 0x48
16198           && address_mode == mode_64bit))
16199     OP_IMREG (bytemode, sizeflag);
16200 }
16201
16202 static const char *const Suffix3DNow[] = {
16203 /* 00 */        NULL,           NULL,           NULL,           NULL,
16204 /* 04 */        NULL,           NULL,           NULL,           NULL,
16205 /* 08 */        NULL,           NULL,           NULL,           NULL,
16206 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16207 /* 10 */        NULL,           NULL,           NULL,           NULL,
16208 /* 14 */        NULL,           NULL,           NULL,           NULL,
16209 /* 18 */        NULL,           NULL,           NULL,           NULL,
16210 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16211 /* 20 */        NULL,           NULL,           NULL,           NULL,
16212 /* 24 */        NULL,           NULL,           NULL,           NULL,
16213 /* 28 */        NULL,           NULL,           NULL,           NULL,
16214 /* 2C */        NULL,           NULL,           NULL,           NULL,
16215 /* 30 */        NULL,           NULL,           NULL,           NULL,
16216 /* 34 */        NULL,           NULL,           NULL,           NULL,
16217 /* 38 */        NULL,           NULL,           NULL,           NULL,
16218 /* 3C */        NULL,           NULL,           NULL,           NULL,
16219 /* 40 */        NULL,           NULL,           NULL,           NULL,
16220 /* 44 */        NULL,           NULL,           NULL,           NULL,
16221 /* 48 */        NULL,           NULL,           NULL,           NULL,
16222 /* 4C */        NULL,           NULL,           NULL,           NULL,
16223 /* 50 */        NULL,           NULL,           NULL,           NULL,
16224 /* 54 */        NULL,           NULL,           NULL,           NULL,
16225 /* 58 */        NULL,           NULL,           NULL,           NULL,
16226 /* 5C */        NULL,           NULL,           NULL,           NULL,
16227 /* 60 */        NULL,           NULL,           NULL,           NULL,
16228 /* 64 */        NULL,           NULL,           NULL,           NULL,
16229 /* 68 */        NULL,           NULL,           NULL,           NULL,
16230 /* 6C */        NULL,           NULL,           NULL,           NULL,
16231 /* 70 */        NULL,           NULL,           NULL,           NULL,
16232 /* 74 */        NULL,           NULL,           NULL,           NULL,
16233 /* 78 */        NULL,           NULL,           NULL,           NULL,
16234 /* 7C */        NULL,           NULL,           NULL,           NULL,
16235 /* 80 */        NULL,           NULL,           NULL,           NULL,
16236 /* 84 */        NULL,           NULL,           NULL,           NULL,
16237 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16238 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16239 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16240 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16241 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16242 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16243 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16244 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16245 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16246 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16247 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16248 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16249 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16250 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16251 /* C0 */        NULL,           NULL,           NULL,           NULL,
16252 /* C4 */        NULL,           NULL,           NULL,           NULL,
16253 /* C8 */        NULL,           NULL,           NULL,           NULL,
16254 /* CC */        NULL,           NULL,           NULL,           NULL,
16255 /* D0 */        NULL,           NULL,           NULL,           NULL,
16256 /* D4 */        NULL,           NULL,           NULL,           NULL,
16257 /* D8 */        NULL,           NULL,           NULL,           NULL,
16258 /* DC */        NULL,           NULL,           NULL,           NULL,
16259 /* E0 */        NULL,           NULL,           NULL,           NULL,
16260 /* E4 */        NULL,           NULL,           NULL,           NULL,
16261 /* E8 */        NULL,           NULL,           NULL,           NULL,
16262 /* EC */        NULL,           NULL,           NULL,           NULL,
16263 /* F0 */        NULL,           NULL,           NULL,           NULL,
16264 /* F4 */        NULL,           NULL,           NULL,           NULL,
16265 /* F8 */        NULL,           NULL,           NULL,           NULL,
16266 /* FC */        NULL,           NULL,           NULL,           NULL,
16267 };
16268
16269 static void
16270 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16271 {
16272   const char *mnemonic;
16273
16274   FETCH_DATA (the_info, codep + 1);
16275   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16276      place where an 8-bit immediate would normally go.  ie. the last
16277      byte of the instruction.  */
16278   obufp = mnemonicendp;
16279   mnemonic = Suffix3DNow[*codep++ & 0xff];
16280   if (mnemonic)
16281     oappend (mnemonic);
16282   else
16283     {
16284       /* Since a variable sized modrm/sib chunk is between the start
16285          of the opcode (0x0f0f) and the opcode suffix, we need to do
16286          all the modrm processing first, and don't know until now that
16287          we have a bad opcode.  This necessitates some cleaning up.  */
16288       op_out[0][0] = '\0';
16289       op_out[1][0] = '\0';
16290       BadOp ();
16291     }
16292   mnemonicendp = obufp;
16293 }
16294
16295 static struct op simd_cmp_op[] =
16296 {
16297   { STRING_COMMA_LEN ("eq") },
16298   { STRING_COMMA_LEN ("lt") },
16299   { STRING_COMMA_LEN ("le") },
16300   { STRING_COMMA_LEN ("unord") },
16301   { STRING_COMMA_LEN ("neq") },
16302   { STRING_COMMA_LEN ("nlt") },
16303   { STRING_COMMA_LEN ("nle") },
16304   { STRING_COMMA_LEN ("ord") }
16305 };
16306
16307 static void
16308 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16309 {
16310   unsigned int cmp_type;
16311
16312   FETCH_DATA (the_info, codep + 1);
16313   cmp_type = *codep++ & 0xff;
16314   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16315     {
16316       char suffix [3];
16317       char *p = mnemonicendp - 2;
16318       suffix[0] = p[0];
16319       suffix[1] = p[1];
16320       suffix[2] = '\0';
16321       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16322       mnemonicendp += simd_cmp_op[cmp_type].len;
16323     }
16324   else
16325     {
16326       /* We have a reserved extension byte.  Output it directly.  */
16327       scratchbuf[0] = '$';
16328       print_operand_value (scratchbuf + 1, 1, cmp_type);
16329       oappend_maybe_intel (scratchbuf);
16330       scratchbuf[0] = '\0';
16331     }
16332 }
16333
16334 static void
16335 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16336           int sizeflag ATTRIBUTE_UNUSED)
16337 {
16338   /* mwait %eax,%ecx  */
16339   if (!intel_syntax)
16340     {
16341       const char **names = (address_mode == mode_64bit
16342                             ? names64 : names32);
16343       strcpy (op_out[0], names[0]);
16344       strcpy (op_out[1], names[1]);
16345       two_source_ops = 1;
16346     }
16347   /* Skip mod/rm byte.  */
16348   MODRM_CHECK;
16349   codep++;
16350 }
16351
16352 static void
16353 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16354             int sizeflag ATTRIBUTE_UNUSED)
16355 {
16356   /* monitor %eax,%ecx,%edx"  */
16357   if (!intel_syntax)
16358     {
16359       const char **op1_names;
16360       const char **names = (address_mode == mode_64bit
16361                             ? names64 : names32);
16362
16363       if (!(prefixes & PREFIX_ADDR))
16364         op1_names = (address_mode == mode_16bit
16365                      ? names16 : names);
16366       else
16367         {
16368           /* Remove "addr16/addr32".  */
16369           all_prefixes[last_addr_prefix] = 0;
16370           op1_names = (address_mode != mode_32bit
16371                        ? names32 : names16);
16372           used_prefixes |= PREFIX_ADDR;
16373         }
16374       strcpy (op_out[0], op1_names[0]);
16375       strcpy (op_out[1], names[1]);
16376       strcpy (op_out[2], names[2]);
16377       two_source_ops = 1;
16378     }
16379   /* Skip mod/rm byte.  */
16380   MODRM_CHECK;
16381   codep++;
16382 }
16383
16384 static void
16385 BadOp (void)
16386 {
16387   /* Throw away prefixes and 1st. opcode byte.  */
16388   codep = insn_codep + 1;
16389   oappend ("(bad)");
16390 }
16391
16392 static void
16393 REP_Fixup (int bytemode, int sizeflag)
16394 {
16395   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16396      lods and stos.  */
16397   if (prefixes & PREFIX_REPZ)
16398     all_prefixes[last_repz_prefix] = REP_PREFIX;
16399
16400   switch (bytemode)
16401     {
16402     case al_reg:
16403     case eAX_reg:
16404     case indir_dx_reg:
16405       OP_IMREG (bytemode, sizeflag);
16406       break;
16407     case eDI_reg:
16408       OP_ESreg (bytemode, sizeflag);
16409       break;
16410     case eSI_reg:
16411       OP_DSreg (bytemode, sizeflag);
16412       break;
16413     default:
16414       abort ();
16415       break;
16416     }
16417 }
16418
16419 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16420    "bnd".  */
16421
16422 static void
16423 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16424 {
16425   if (prefixes & PREFIX_REPNZ)
16426     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16427 }
16428
16429 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16430    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16431  */
16432
16433 static void
16434 HLE_Fixup1 (int bytemode, int sizeflag)
16435 {
16436   if (modrm.mod != 3
16437       && (prefixes & PREFIX_LOCK) != 0)
16438     {
16439       if (prefixes & PREFIX_REPZ)
16440         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16441       if (prefixes & PREFIX_REPNZ)
16442         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16443     }
16444
16445   OP_E (bytemode, sizeflag);
16446 }
16447
16448 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16449    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16450  */
16451
16452 static void
16453 HLE_Fixup2 (int bytemode, int sizeflag)
16454 {
16455   if (modrm.mod != 3)
16456     {
16457       if (prefixes & PREFIX_REPZ)
16458         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16459       if (prefixes & PREFIX_REPNZ)
16460         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16461     }
16462
16463   OP_E (bytemode, sizeflag);
16464 }
16465
16466 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16467    "xrelease" for memory operand.  No check for LOCK prefix.   */
16468
16469 static void
16470 HLE_Fixup3 (int bytemode, int sizeflag)
16471 {
16472   if (modrm.mod != 3
16473       && last_repz_prefix > last_repnz_prefix
16474       && (prefixes & PREFIX_REPZ) != 0)
16475     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16476
16477   OP_E (bytemode, sizeflag);
16478 }
16479
16480 static void
16481 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16482 {
16483   USED_REX (REX_W);
16484   if (rex & REX_W)
16485     {
16486       /* Change cmpxchg8b to cmpxchg16b.  */
16487       char *p = mnemonicendp - 2;
16488       mnemonicendp = stpcpy (p, "16b");
16489       bytemode = o_mode;
16490     }
16491   else if ((prefixes & PREFIX_LOCK) != 0)
16492     {
16493       if (prefixes & PREFIX_REPZ)
16494         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16495       if (prefixes & PREFIX_REPNZ)
16496         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16497     }
16498
16499   OP_M (bytemode, sizeflag);
16500 }
16501
16502 static void
16503 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16504 {
16505   const char **names;
16506
16507   if (need_vex)
16508     {
16509       switch (vex.length)
16510         {
16511         case 128:
16512           names = names_xmm;
16513           break;
16514         case 256:
16515           names = names_ymm;
16516           break;
16517         default:
16518           abort ();
16519         }
16520     }
16521   else
16522     names = names_xmm;
16523   oappend (names[reg]);
16524 }
16525
16526 static void
16527 CRC32_Fixup (int bytemode, int sizeflag)
16528 {
16529   /* Add proper suffix to "crc32".  */
16530   char *p = mnemonicendp;
16531
16532   switch (bytemode)
16533     {
16534     case b_mode:
16535       if (intel_syntax)
16536         goto skip;
16537
16538       *p++ = 'b';
16539       break;
16540     case v_mode:
16541       if (intel_syntax)
16542         goto skip;
16543
16544       USED_REX (REX_W);
16545       if (rex & REX_W)
16546         *p++ = 'q';
16547       else
16548         {
16549           if (sizeflag & DFLAG)
16550             *p++ = 'l';
16551           else
16552             *p++ = 'w';
16553           used_prefixes |= (prefixes & PREFIX_DATA);
16554         }
16555       break;
16556     default:
16557       oappend (INTERNAL_DISASSEMBLER_ERROR);
16558       break;
16559     }
16560   mnemonicendp = p;
16561   *p = '\0';
16562
16563 skip:
16564   if (modrm.mod == 3)
16565     {
16566       int add;
16567
16568       /* Skip mod/rm byte.  */
16569       MODRM_CHECK;
16570       codep++;
16571
16572       USED_REX (REX_B);
16573       add = (rex & REX_B) ? 8 : 0;
16574       if (bytemode == b_mode)
16575         {
16576           USED_REX (0);
16577           if (rex)
16578             oappend (names8rex[modrm.rm + add]);
16579           else
16580             oappend (names8[modrm.rm + add]);
16581         }
16582       else
16583         {
16584           USED_REX (REX_W);
16585           if (rex & REX_W)
16586             oappend (names64[modrm.rm + add]);
16587           else if ((prefixes & PREFIX_DATA))
16588             oappend (names16[modrm.rm + add]);
16589           else
16590             oappend (names32[modrm.rm + add]);
16591         }
16592     }
16593   else
16594     OP_E (bytemode, sizeflag);
16595 }
16596
16597 static void
16598 FXSAVE_Fixup (int bytemode, int sizeflag)
16599 {
16600   /* Add proper suffix to "fxsave" and "fxrstor".  */
16601   USED_REX (REX_W);
16602   if (rex & REX_W)
16603     {
16604       char *p = mnemonicendp;
16605       *p++ = '6';
16606       *p++ = '4';
16607       *p = '\0';
16608       mnemonicendp = p;
16609     }
16610   OP_M (bytemode, sizeflag);
16611 }
16612
16613 /* Display the destination register operand for instructions with
16614    VEX. */
16615
16616 static void
16617 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16618 {
16619   int reg;
16620   const char **names;
16621
16622   if (!need_vex)
16623     abort ();
16624
16625   if (!need_vex_reg)
16626     return;
16627
16628   reg = vex.register_specifier;
16629   if (vex.evex)
16630     {
16631       if (!vex.v)
16632         reg += 16;
16633     }
16634
16635   if (bytemode == vex_scalar_mode)
16636     {
16637       oappend (names_xmm[reg]);
16638       return;
16639     }
16640
16641   switch (vex.length)
16642     {
16643     case 128:
16644       switch (bytemode)
16645         {
16646         case vex_mode:
16647         case vex128_mode:
16648         case vex_vsib_q_w_dq_mode:
16649         case vex_vsib_q_w_d_mode:
16650           names = names_xmm;
16651           break;
16652         case dq_mode:
16653           if (vex.w)
16654             names = names64;
16655           else
16656             names = names32;
16657           break;
16658         case mask_bd_mode:
16659         case mask_mode:
16660           names = names_mask;
16661           break;
16662         default:
16663           abort ();
16664           return;
16665         }
16666       break;
16667     case 256:
16668       switch (bytemode)
16669         {
16670         case vex_mode:
16671         case vex256_mode:
16672           names = names_ymm;
16673           break;
16674         case vex_vsib_q_w_dq_mode:
16675         case vex_vsib_q_w_d_mode:
16676           names = vex.w ? names_ymm : names_xmm;
16677           break;
16678         case mask_bd_mode:
16679         case mask_mode:
16680           names = names_mask;
16681           break;
16682         default:
16683           abort ();
16684           return;
16685         }
16686       break;
16687     case 512:
16688       names = names_zmm;
16689       break;
16690     default:
16691       abort ();
16692       break;
16693     }
16694   oappend (names[reg]);
16695 }
16696
16697 /* Get the VEX immediate byte without moving codep.  */
16698
16699 static unsigned char
16700 get_vex_imm8 (int sizeflag, int opnum)
16701 {
16702   int bytes_before_imm = 0;
16703
16704   if (modrm.mod != 3)
16705     {
16706       /* There are SIB/displacement bytes.  */
16707       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16708         {
16709           /* 32/64 bit address mode */
16710           int base = modrm.rm;
16711
16712           /* Check SIB byte.  */
16713           if (base == 4)
16714             {
16715               FETCH_DATA (the_info, codep + 1);
16716               base = *codep & 7;
16717               /* When decoding the third source, don't increase
16718                  bytes_before_imm as this has already been incremented
16719                  by one in OP_E_memory while decoding the second
16720                  source operand.  */
16721               if (opnum == 0)
16722                 bytes_before_imm++;
16723             }
16724
16725           /* Don't increase bytes_before_imm when decoding the third source,
16726              it has already been incremented by OP_E_memory while decoding
16727              the second source operand.  */
16728           if (opnum == 0)
16729             {
16730               switch (modrm.mod)
16731                 {
16732                   case 0:
16733                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16734                        SIB == 5, there is a 4 byte displacement.  */
16735                     if (base != 5)
16736                       /* No displacement. */
16737                       break;
16738                   case 2:
16739                     /* 4 byte displacement.  */
16740                     bytes_before_imm += 4;
16741                     break;
16742                   case 1:
16743                     /* 1 byte displacement.  */
16744                     bytes_before_imm++;
16745                     break;
16746                 }
16747             }
16748         }
16749       else
16750         {
16751           /* 16 bit address mode */
16752           /* Don't increase bytes_before_imm when decoding the third source,
16753              it has already been incremented by OP_E_memory while decoding
16754              the second source operand.  */
16755           if (opnum == 0)
16756             {
16757               switch (modrm.mod)
16758                 {
16759                 case 0:
16760                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16761                   if (modrm.rm != 6)
16762                     /* No displacement. */
16763                     break;
16764                 case 2:
16765                   /* 2 byte displacement.  */
16766                   bytes_before_imm += 2;
16767                   break;
16768                 case 1:
16769                   /* 1 byte displacement: when decoding the third source,
16770                      don't increase bytes_before_imm as this has already
16771                      been incremented by one in OP_E_memory while decoding
16772                      the second source operand.  */
16773                   if (opnum == 0)
16774                     bytes_before_imm++;
16775
16776                   break;
16777                 }
16778             }
16779         }
16780     }
16781
16782   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16783   return codep [bytes_before_imm];
16784 }
16785
16786 static void
16787 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16788 {
16789   const char **names;
16790
16791   if (reg == -1 && modrm.mod != 3)
16792     {
16793       OP_E_memory (bytemode, sizeflag);
16794       return;
16795     }
16796   else
16797     {
16798       if (reg == -1)
16799         {
16800           reg = modrm.rm;
16801           USED_REX (REX_B);
16802           if (rex & REX_B)
16803             reg += 8;
16804         }
16805       else if (reg > 7 && address_mode != mode_64bit)
16806         BadOp ();
16807     }
16808
16809   switch (vex.length)
16810     {
16811     case 128:
16812       names = names_xmm;
16813       break;
16814     case 256:
16815       names = names_ymm;
16816       break;
16817     default:
16818       abort ();
16819     }
16820   oappend (names[reg]);
16821 }
16822
16823 static void
16824 OP_EX_VexImmW (int bytemode, int sizeflag)
16825 {
16826   int reg = -1;
16827   static unsigned char vex_imm8;
16828
16829   if (vex_w_done == 0)
16830     {
16831       vex_w_done = 1;
16832
16833       /* Skip mod/rm byte.  */
16834       MODRM_CHECK;
16835       codep++;
16836
16837       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16838
16839       if (vex.w)
16840           reg = vex_imm8 >> 4;
16841
16842       OP_EX_VexReg (bytemode, sizeflag, reg);
16843     }
16844   else if (vex_w_done == 1)
16845     {
16846       vex_w_done = 2;
16847
16848       if (!vex.w)
16849           reg = vex_imm8 >> 4;
16850
16851       OP_EX_VexReg (bytemode, sizeflag, reg);
16852     }
16853   else
16854     {
16855       /* Output the imm8 directly.  */
16856       scratchbuf[0] = '$';
16857       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16858       oappend_maybe_intel (scratchbuf);
16859       scratchbuf[0] = '\0';
16860       codep++;
16861     }
16862 }
16863
16864 static void
16865 OP_Vex_2src (int bytemode, int sizeflag)
16866 {
16867   if (modrm.mod == 3)
16868     {
16869       int reg = modrm.rm;
16870       USED_REX (REX_B);
16871       if (rex & REX_B)
16872         reg += 8;
16873       oappend (names_xmm[reg]);
16874     }
16875   else
16876     {
16877       if (intel_syntax
16878           && (bytemode == v_mode || bytemode == v_swap_mode))
16879         {
16880           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16881           used_prefixes |= (prefixes & PREFIX_DATA);
16882         }
16883       OP_E (bytemode, sizeflag);
16884     }
16885 }
16886
16887 static void
16888 OP_Vex_2src_1 (int bytemode, int sizeflag)
16889 {
16890   if (modrm.mod == 3)
16891     {
16892       /* Skip mod/rm byte.   */
16893       MODRM_CHECK;
16894       codep++;
16895     }
16896
16897   if (vex.w)
16898     oappend (names_xmm[vex.register_specifier]);
16899   else
16900     OP_Vex_2src (bytemode, sizeflag);
16901 }
16902
16903 static void
16904 OP_Vex_2src_2 (int bytemode, int sizeflag)
16905 {
16906   if (vex.w)
16907     OP_Vex_2src (bytemode, sizeflag);
16908   else
16909     oappend (names_xmm[vex.register_specifier]);
16910 }
16911
16912 static void
16913 OP_EX_VexW (int bytemode, int sizeflag)
16914 {
16915   int reg = -1;
16916
16917   if (!vex_w_done)
16918     {
16919       vex_w_done = 1;
16920
16921       /* Skip mod/rm byte.  */
16922       MODRM_CHECK;
16923       codep++;
16924
16925       if (vex.w)
16926         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16927     }
16928   else
16929     {
16930       if (!vex.w)
16931         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16932     }
16933
16934   OP_EX_VexReg (bytemode, sizeflag, reg);
16935 }
16936
16937 static void
16938 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16939              int sizeflag ATTRIBUTE_UNUSED)
16940 {
16941   /* Skip the immediate byte and check for invalid bits.  */
16942   FETCH_DATA (the_info, codep + 1);
16943   if (*codep++ & 0xf)
16944     BadOp ();
16945 }
16946
16947 static void
16948 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16949 {
16950   int reg;
16951   const char **names;
16952
16953   FETCH_DATA (the_info, codep + 1);
16954   reg = *codep++;
16955
16956   if (bytemode != x_mode)
16957     abort ();
16958
16959   if (reg & 0xf)
16960       BadOp ();
16961
16962   reg >>= 4;
16963   if (reg > 7 && address_mode != mode_64bit)
16964     BadOp ();
16965
16966   switch (vex.length)
16967     {
16968     case 128:
16969       names = names_xmm;
16970       break;
16971     case 256:
16972       names = names_ymm;
16973       break;
16974     default:
16975       abort ();
16976     }
16977   oappend (names[reg]);
16978 }
16979
16980 static void
16981 OP_XMM_VexW (int bytemode, int sizeflag)
16982 {
16983   /* Turn off the REX.W bit since it is used for swapping operands
16984      now.  */
16985   rex &= ~REX_W;
16986   OP_XMM (bytemode, sizeflag);
16987 }
16988
16989 static void
16990 OP_EX_Vex (int bytemode, int sizeflag)
16991 {
16992   if (modrm.mod != 3)
16993     {
16994       if (vex.register_specifier != 0)
16995         BadOp ();
16996       need_vex_reg = 0;
16997     }
16998   OP_EX (bytemode, sizeflag);
16999 }
17000
17001 static void
17002 OP_XMM_Vex (int bytemode, int sizeflag)
17003 {
17004   if (modrm.mod != 3)
17005     {
17006       if (vex.register_specifier != 0)
17007         BadOp ();
17008       need_vex_reg = 0;
17009     }
17010   OP_XMM (bytemode, sizeflag);
17011 }
17012
17013 static void
17014 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17015 {
17016   switch (vex.length)
17017     {
17018     case 128:
17019       mnemonicendp = stpcpy (obuf, "vzeroupper");
17020       break;
17021     case 256:
17022       mnemonicendp = stpcpy (obuf, "vzeroall");
17023       break;
17024     default:
17025       abort ();
17026     }
17027 }
17028
17029 static struct op vex_cmp_op[] =
17030 {
17031   { STRING_COMMA_LEN ("eq") },
17032   { STRING_COMMA_LEN ("lt") },
17033   { STRING_COMMA_LEN ("le") },
17034   { STRING_COMMA_LEN ("unord") },
17035   { STRING_COMMA_LEN ("neq") },
17036   { STRING_COMMA_LEN ("nlt") },
17037   { STRING_COMMA_LEN ("nle") },
17038   { STRING_COMMA_LEN ("ord") },
17039   { STRING_COMMA_LEN ("eq_uq") },
17040   { STRING_COMMA_LEN ("nge") },
17041   { STRING_COMMA_LEN ("ngt") },
17042   { STRING_COMMA_LEN ("false") },
17043   { STRING_COMMA_LEN ("neq_oq") },
17044   { STRING_COMMA_LEN ("ge") },
17045   { STRING_COMMA_LEN ("gt") },
17046   { STRING_COMMA_LEN ("true") },
17047   { STRING_COMMA_LEN ("eq_os") },
17048   { STRING_COMMA_LEN ("lt_oq") },
17049   { STRING_COMMA_LEN ("le_oq") },
17050   { STRING_COMMA_LEN ("unord_s") },
17051   { STRING_COMMA_LEN ("neq_us") },
17052   { STRING_COMMA_LEN ("nlt_uq") },
17053   { STRING_COMMA_LEN ("nle_uq") },
17054   { STRING_COMMA_LEN ("ord_s") },
17055   { STRING_COMMA_LEN ("eq_us") },
17056   { STRING_COMMA_LEN ("nge_uq") },
17057   { STRING_COMMA_LEN ("ngt_uq") },
17058   { STRING_COMMA_LEN ("false_os") },
17059   { STRING_COMMA_LEN ("neq_os") },
17060   { STRING_COMMA_LEN ("ge_oq") },
17061   { STRING_COMMA_LEN ("gt_oq") },
17062   { STRING_COMMA_LEN ("true_us") },
17063 };
17064
17065 static void
17066 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17067 {
17068   unsigned int cmp_type;
17069
17070   FETCH_DATA (the_info, codep + 1);
17071   cmp_type = *codep++ & 0xff;
17072   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17073     {
17074       char suffix [3];
17075       char *p = mnemonicendp - 2;
17076       suffix[0] = p[0];
17077       suffix[1] = p[1];
17078       suffix[2] = '\0';
17079       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17080       mnemonicendp += vex_cmp_op[cmp_type].len;
17081     }
17082   else
17083     {
17084       /* We have a reserved extension byte.  Output it directly.  */
17085       scratchbuf[0] = '$';
17086       print_operand_value (scratchbuf + 1, 1, cmp_type);
17087       oappend_maybe_intel (scratchbuf);
17088       scratchbuf[0] = '\0';
17089     }
17090 }
17091
17092 static void
17093 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17094              int sizeflag ATTRIBUTE_UNUSED)
17095 {
17096   unsigned int cmp_type;
17097
17098   if (!vex.evex)
17099     abort ();
17100
17101   FETCH_DATA (the_info, codep + 1);
17102   cmp_type = *codep++ & 0xff;
17103   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17104      If it's the case, print suffix, otherwise - print the immediate.  */
17105   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17106       && cmp_type != 3
17107       && cmp_type != 7)
17108     {
17109       char suffix [3];
17110       char *p = mnemonicendp - 2;
17111
17112       /* vpcmp* can have both one- and two-lettered suffix.  */
17113       if (p[0] == 'p')
17114         {
17115           p++;
17116           suffix[0] = p[0];
17117           suffix[1] = '\0';
17118         }
17119       else
17120         {
17121           suffix[0] = p[0];
17122           suffix[1] = p[1];
17123           suffix[2] = '\0';
17124         }
17125
17126       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17127       mnemonicendp += simd_cmp_op[cmp_type].len;
17128     }
17129   else
17130     {
17131       /* We have a reserved extension byte.  Output it directly.  */
17132       scratchbuf[0] = '$';
17133       print_operand_value (scratchbuf + 1, 1, cmp_type);
17134       oappend_maybe_intel (scratchbuf);
17135       scratchbuf[0] = '\0';
17136     }
17137 }
17138
17139 static const struct op pclmul_op[] =
17140 {
17141   { STRING_COMMA_LEN ("lql") },
17142   { STRING_COMMA_LEN ("hql") },
17143   { STRING_COMMA_LEN ("lqh") },
17144   { STRING_COMMA_LEN ("hqh") }
17145 };
17146
17147 static void
17148 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17149               int sizeflag ATTRIBUTE_UNUSED)
17150 {
17151   unsigned int pclmul_type;
17152
17153   FETCH_DATA (the_info, codep + 1);
17154   pclmul_type = *codep++ & 0xff;
17155   switch (pclmul_type)
17156     {
17157     case 0x10:
17158       pclmul_type = 2;
17159       break;
17160     case 0x11:
17161       pclmul_type = 3;
17162       break;
17163     default:
17164       break;
17165     }
17166   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17167     {
17168       char suffix [4];
17169       char *p = mnemonicendp - 3;
17170       suffix[0] = p[0];
17171       suffix[1] = p[1];
17172       suffix[2] = p[2];
17173       suffix[3] = '\0';
17174       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17175       mnemonicendp += pclmul_op[pclmul_type].len;
17176     }
17177   else
17178     {
17179       /* We have a reserved extension byte.  Output it directly.  */
17180       scratchbuf[0] = '$';
17181       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17182       oappend_maybe_intel (scratchbuf);
17183       scratchbuf[0] = '\0';
17184     }
17185 }
17186
17187 static void
17188 MOVBE_Fixup (int bytemode, int sizeflag)
17189 {
17190   /* Add proper suffix to "movbe".  */
17191   char *p = mnemonicendp;
17192
17193   switch (bytemode)
17194     {
17195     case v_mode:
17196       if (intel_syntax)
17197         goto skip;
17198
17199       USED_REX (REX_W);
17200       if (sizeflag & SUFFIX_ALWAYS)
17201         {
17202           if (rex & REX_W)
17203             *p++ = 'q';
17204           else
17205             {
17206               if (sizeflag & DFLAG)
17207                 *p++ = 'l';
17208               else
17209                 *p++ = 'w';
17210               used_prefixes |= (prefixes & PREFIX_DATA);
17211             }
17212         }
17213       break;
17214     default:
17215       oappend (INTERNAL_DISASSEMBLER_ERROR);
17216       break;
17217     }
17218   mnemonicendp = p;
17219   *p = '\0';
17220
17221 skip:
17222   OP_M (bytemode, sizeflag);
17223 }
17224
17225 static void
17226 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17227 {
17228   int reg;
17229   const char **names;
17230
17231   /* Skip mod/rm byte.  */
17232   MODRM_CHECK;
17233   codep++;
17234
17235   if (vex.w)
17236     names = names64;
17237   else
17238     names = names32;
17239
17240   reg = modrm.rm;
17241   USED_REX (REX_B);
17242   if (rex & REX_B)
17243     reg += 8;
17244
17245   oappend (names[reg]);
17246 }
17247
17248 static void
17249 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17250 {
17251   const char **names;
17252
17253   if (vex.w)
17254     names = names64;
17255   else
17256     names = names32;
17257
17258   oappend (names[vex.register_specifier]);
17259 }
17260
17261 static void
17262 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17263 {
17264   if (!vex.evex
17265       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17266     abort ();
17267
17268   USED_REX (REX_R);
17269   if ((rex & REX_R) != 0 || !vex.r)
17270     {
17271       BadOp ();
17272       return;
17273     }
17274
17275   oappend (names_mask [modrm.reg]);
17276 }
17277
17278 static void
17279 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17280 {
17281   if (!vex.evex
17282       || (bytemode != evex_rounding_mode
17283           && bytemode != evex_sae_mode))
17284     abort ();
17285   if (modrm.mod == 3 && vex.b)
17286     switch (bytemode)
17287       {
17288       case evex_rounding_mode:
17289         oappend (names_rounding[vex.ll]);
17290         break;
17291       case evex_sae_mode:
17292         oappend ("{sae}");
17293         break;
17294       default:
17295         break;
17296       }
17297 }