opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VZERO_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mx { OP_M, x_mode }
 276 #define Mxmm { OP_M, xmm_mode }
 277 #define Gb { OP_G, b_mode }
 278 #define Gbnd { OP_G, bnd_mode }
 279 #define Gv { OP_G, v_mode }
 280 #define Gd { OP_G, d_mode }
 281 #define Gdq { OP_G, dq_mode }
 282 #define Gm { OP_G, m_mode }
 283 #define Gw { OP_G, w_mode }
 284 #define Rd { OP_R, d_mode }
 285 #define Rdq { OP_R, dq_mode }
 286 #define Rm { OP_R, m_mode }
 287 #define Ib { OP_I, b_mode }
 288 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 289 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 290 #define Iv { OP_I, v_mode }
 291 #define sIv { OP_sI, v_mode }
 292 #define Iq { OP_I, q_mode }
 293 #define Iv64 { OP_I64, v_mode }
 294 #define Iw { OP_I, w_mode }
 295 #define I1 { OP_I, const_1_mode }
 296 #define Jb { OP_J, b_mode }
 297 #define Jv { OP_J, v_mode }
 298 #define Cm { OP_C, m_mode }
 299 #define Dm { OP_D, m_mode }
 300 #define Td { OP_T, d_mode }
 301 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 302
 303 #define RMeAX { OP_REG, eAX_reg }
 304 #define RMeBX { OP_REG, eBX_reg }
 305 #define RMeCX { OP_REG, eCX_reg }
 306 #define RMeDX { OP_REG, eDX_reg }
 307 #define RMeSP { OP_REG, eSP_reg }
 308 #define RMeBP { OP_REG, eBP_reg }
 309 #define RMeSI { OP_REG, eSI_reg }
 310 #define RMeDI { OP_REG, eDI_reg }
 311 #define RMrAX { OP_REG, rAX_reg }
 312 #define RMrBX { OP_REG, rBX_reg }
 313 #define RMrCX { OP_REG, rCX_reg }
 314 #define RMrDX { OP_REG, rDX_reg }
 315 #define RMrSP { OP_REG, rSP_reg }
 316 #define RMrBP { OP_REG, rBP_reg }
 317 #define RMrSI { OP_REG, rSI_reg }
 318 #define RMrDI { OP_REG, rDI_reg }
 319 #define RMAL { OP_REG, al_reg }
 320 #define RMCL { OP_REG, cl_reg }
 321 #define RMDL { OP_REG, dl_reg }
 322 #define RMBL { OP_REG, bl_reg }
 323 #define RMAH { OP_REG, ah_reg }
 324 #define RMCH { OP_REG, ch_reg }
 325 #define RMDH { OP_REG, dh_reg }
 326 #define RMBH { OP_REG, bh_reg }
 327 #define RMAX { OP_REG, ax_reg }
 328 #define RMDX { OP_REG, dx_reg }
 329
 330 #define eAX { OP_IMREG, eAX_reg }
 331 #define eBX { OP_IMREG, eBX_reg }
 332 #define eCX { OP_IMREG, eCX_reg }
 333 #define eDX { OP_IMREG, eDX_reg }
 334 #define eSP { OP_IMREG, eSP_reg }
 335 #define eBP { OP_IMREG, eBP_reg }
 336 #define eSI { OP_IMREG, eSI_reg }
 337 #define eDI { OP_IMREG, eDI_reg }
 338 #define AL { OP_IMREG, al_reg }
 339 #define CL { OP_IMREG, cl_reg }
 340 #define DL { OP_IMREG, dl_reg }
 341 #define BL { OP_IMREG, bl_reg }
 342 #define AH { OP_IMREG, ah_reg }
 343 #define CH { OP_IMREG, ch_reg }
 344 #define DH { OP_IMREG, dh_reg }
 345 #define BH { OP_IMREG, bh_reg }
 346 #define AX { OP_IMREG, ax_reg }
 347 #define DX { OP_IMREG, dx_reg }
 348 #define zAX { OP_IMREG, z_mode_ax_reg }
 349 #define indirDX { OP_IMREG, indir_dx_reg }
 350
 351 #define Sw { OP_SEG, w_mode }
 352 #define Sv { OP_SEG, v_mode }
 353 #define Ap { OP_DIR, 0 }
 354 #define Ob { OP_OFF64, b_mode }
 355 #define Ov { OP_OFF64, v_mode }
 356 #define Xb { OP_DSreg, eSI_reg }
 357 #define Xv { OP_DSreg, eSI_reg }
 358 #define Xz { OP_DSreg, eSI_reg }
 359 #define Yb { OP_ESreg, eDI_reg }
 360 #define Yv { OP_ESreg, eDI_reg }
 361 #define DSBX { OP_DSreg, eBX_reg }
 362
 363 #define es { OP_REG, es_reg }
 364 #define ss { OP_REG, ss_reg }
 365 #define cs { OP_REG, cs_reg }
 366 #define ds { OP_REG, ds_reg }
 367 #define fs { OP_REG, fs_reg }
 368 #define gs { OP_REG, gs_reg }
 369
 370 #define MX { OP_MMX, 0 }
 371 #define XM { OP_XMM, 0 }
 372 #define XMScalar { OP_XMM, scalar_mode }
 373 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 374 #define XMM { OP_XMM, xmm_mode }
 375 #define XMxmmq { OP_XMM, xmmq_mode }
 376 #define EM { OP_EM, v_mode }
 377 #define EMS { OP_EM, v_swap_mode }
 378 #define EMd { OP_EM, d_mode }
 379 #define EMx { OP_EM, x_mode }
 380 #define EXbScalar { OP_EX, b_scalar_mode }
 381 #define EXw { OP_EX, w_mode }
 382 #define EXwScalar { OP_EX, w_scalar_mode }
 383 #define EXd { OP_EX, d_mode }
 384 #define EXdScalar { OP_EX, d_scalar_mode }
 385 #define EXdS { OP_EX, d_swap_mode }
 386 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 387 #define EXq { OP_EX, q_mode }
 388 #define EXqScalar { OP_EX, q_scalar_mode }
 389 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 390 #define EXqS { OP_EX, q_swap_mode }
 391 #define EXx { OP_EX, x_mode }
 392 #define EXxS { OP_EX, x_swap_mode }
 393 #define EXxmm { OP_EX, xmm_mode }
 394 #define EXymm { OP_EX, ymm_mode }
 395 #define EXxmmq { OP_EX, xmmq_mode }
 396 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 397 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 398 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 399 #define EXxmm_md { OP_EX, xmm_md_mode }
 400 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 401 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 402 #define EXxmmdw { OP_EX, xmmdw_mode }
 403 #define EXxmmqd { OP_EX, xmmqd_mode }
 404 #define EXymmq { OP_EX, ymmq_mode }
 405 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 406 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 407 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 408 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 409 #define MS { OP_MS, v_mode }
 410 #define XS { OP_XS, v_mode }
 411 #define EMCq { OP_EMC, q_mode }
 412 #define MXC { OP_MXC, 0 }
 413 #define OPSUF { OP_3DNowSuffix, 0 }
 414 #define CMP { CMP_Fixup, 0 }
 415 #define XMM0 { XMM_Fixup, 0 }
 416 #define FXSAVE { FXSAVE_Fixup, 0 }
 417 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 418 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 419
 420 #define Vex { OP_VEX, vex_mode }
 421 #define VexScalar { OP_VEX, vex_scalar_mode }
 422 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 423 #define Vex128 { OP_VEX, vex128_mode }
 424 #define Vex256 { OP_VEX, vex256_mode }
 425 #define VexGdq { OP_VEX, dq_mode }
 426 #define EXdVex { OP_EX_Vex, d_mode }
 427 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 429 #define EXqVex { OP_EX_Vex, q_mode }
 430 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 432 #define EXVexW { OP_EX_VexW, x_mode }
 433 #define EXdVexW { OP_EX_VexW, d_mode }
 434 #define EXqVexW { OP_EX_VexW, q_mode }
 435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 436 #define XMVex { OP_XMM_Vex, 0 }
 437 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 438 #define XMVexW { OP_XMM_VexW, 0 }
 439 #define XMVexI4 { OP_REG_VexI4, x_mode }
 440 #define PCLMUL { PCLMUL_Fixup, 0 }
 441 #define VZERO { VZERO_Fixup, 0 }
 442 #define VCMP { VCMP_Fixup, 0 }
 443 #define VPCMP { VPCMP_Fixup, 0 }
 444 #define VPCOM { VPCOM_Fixup, 0 }
 445
 446 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 447 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 448
 449 #define XMask { OP_Mask, mask_mode }
 450 #define MaskG { OP_G, mask_mode }
 451 #define MaskE { OP_E, mask_mode }
 452 #define MaskBDE { OP_E, mask_bd_mode }
 453 #define MaskR { OP_R, mask_mode }
 454 #define MaskVex { OP_VEX, mask_mode }
 455
 456 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 457 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 458 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 459 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 460
 461 /* Used handle "rep" prefix for string instructions.  */
 462 #define Xbr { REP_Fixup, eSI_reg }
 463 #define Xvr { REP_Fixup, eSI_reg }
 464 #define Ybr { REP_Fixup, eDI_reg }
 465 #define Yvr { REP_Fixup, eDI_reg }
 466 #define Yzr { REP_Fixup, eDI_reg }
 467 #define indirDXr { REP_Fixup, indir_dx_reg }
 468 #define ALr { REP_Fixup, al_reg }
 469 #define eAXr { REP_Fixup, eAX_reg }
 470
 471 /* Used handle HLE prefix for lockable instructions.  */
 472 #define Ebh1 { HLE_Fixup1, b_mode }
 473 #define Evh1 { HLE_Fixup1, v_mode }
 474 #define Ebh2 { HLE_Fixup2, b_mode }
 475 #define Evh2 { HLE_Fixup2, v_mode }
 476 #define Ebh3 { HLE_Fixup3, b_mode }
 477 #define Evh3 { HLE_Fixup3, v_mode }
 478
 479 #define BND { BND_Fixup, 0 }
 480 #define NOTRACK { NOTRACK_Fixup, 0 }
 481
 482 #define cond_jump_flag { NULL, cond_jump_mode }
 483 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 484
 485 /* bits in sizeflag */
 486 #define SUFFIX_ALWAYS 4
 487 #define AFLAG 2
 488 #define DFLAG 1
 489
 490 enum
 491 {
 492   /* byte operand */
 493   b_mode = 1,
 494   /* byte operand with operand swapped */
 495   b_swap_mode,
 496   /* byte operand, sign extend like 'T' suffix */
 497   b_T_mode,
 498   /* operand size depends on prefixes */
 499   v_mode,
 500   /* operand size depends on prefixes with operand swapped */
 501   v_swap_mode,
 502   /* word operand */
 503   w_mode,
 504   /* double word operand  */
 505   d_mode,
 506   /* double word operand with operand swapped */
 507   d_swap_mode,
 508   /* quad word operand */
 509   q_mode,
 510   /* quad word operand with operand swapped */
 511   q_swap_mode,
 512   /* ten-byte operand */
 513   t_mode,
 514   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 515      broadcast enabled.  */
 516   x_mode,
 517   /* Similar to x_mode, but with different EVEX mem shifts.  */
 518   evex_x_gscat_mode,
 519   /* Similar to x_mode, but with disabled broadcast.  */
 520   evex_x_nobcst_mode,
 521   /* Similar to x_mode, but with operands swapped and disabled broadcast
 522      in EVEX.  */
 523   x_swap_mode,
 524   /* 16-byte XMM operand */
 525   xmm_mode,
 526   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 527      memory operand (depending on vector length).  Broadcast isn't
 528      allowed.  */
 529   xmmq_mode,
 530   /* Same as xmmq_mode, but broadcast is allowed.  */
 531   evex_half_bcst_xmmq_mode,
 532   /* XMM register or byte memory operand */
 533   xmm_mb_mode,
 534   /* XMM register or word memory operand */
 535   xmm_mw_mode,
 536   /* XMM register or double word memory operand */
 537   xmm_md_mode,
 538   /* XMM register or quad word memory operand */
 539   xmm_mq_mode,
 540   /* XMM register or double/quad word memory operand, depending on
 541      VEX.W.  */
 542   xmm_mdq_mode,
 543   /* 16-byte XMM, word, double word or quad word operand.  */
 544   xmmdw_mode,
 545   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 546   xmmqd_mode,
 547   /* 32-byte YMM operand */
 548   ymm_mode,
 549   /* quad word, ymmword or zmmword memory operand.  */
 550   ymmq_mode,
 551   /* 32-byte YMM or 16-byte word operand */
 552   ymmxmm_mode,
 553   /* d_mode in 32bit, q_mode in 64bit mode.  */
 554   m_mode,
 555   /* pair of v_mode operands */
 556   a_mode,
 557   cond_jump_mode,
 558   loop_jcxz_mode,
 559   v_bnd_mode,
 560   /* operand size depends on REX prefixes.  */
 561   dq_mode,
 562   /* registers like dq_mode, memory like w_mode.  */
 563   dqw_mode,
 564   /* bounds operand */
 565   bnd_mode,
 566   /* bounds operand with operand swapped */
 567   bnd_swap_mode,
 568   /* 4- or 6-byte pointer operand */
 569   f_mode,
 570   const_1_mode,
 571   /* v_mode for indirect branch opcodes.  */
 572   indir_v_mode,
 573   /* v_mode for stack-related opcodes.  */
 574   stack_v_mode,
 575   /* non-quad operand size depends on prefixes */
 576   z_mode,
 577   /* 16-byte operand */
 578   o_mode,
 579   /* registers like dq_mode, memory like b_mode.  */
 580   dqb_mode,
 581   /* registers like d_mode, memory like b_mode.  */
 582   db_mode,
 583   /* registers like d_mode, memory like w_mode.  */
 584   dw_mode,
 585   /* registers like dq_mode, memory like d_mode.  */
 586   dqd_mode,
 587   /* normal vex mode */
 588   vex_mode,
 589   /* 128bit vex mode */
 590   vex128_mode,
 591   /* 256bit vex mode */
 592   vex256_mode,
 593   /* operand size depends on the VEX.W bit.  */
 594   vex_w_dq_mode,
 595
 596   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 597   vex_vsib_d_w_dq_mode,
 598   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 599   vex_vsib_d_w_d_mode,
 600   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 601   vex_vsib_q_w_dq_mode,
 602   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 603   vex_vsib_q_w_d_mode,
 604
 605   /* scalar, ignore vector length.  */
 606   scalar_mode,
 607   /* like b_mode, ignore vector length.  */
 608   b_scalar_mode,
 609   /* like w_mode, ignore vector length.  */
 610   w_scalar_mode,
 611   /* like d_mode, ignore vector length.  */
 612   d_scalar_mode,
 613   /* like d_swap_mode, ignore vector length.  */
 614   d_scalar_swap_mode,
 615   /* like q_mode, ignore vector length.  */
 616   q_scalar_mode,
 617   /* like q_swap_mode, ignore vector length.  */
 618   q_scalar_swap_mode,
 619   /* like vex_mode, ignore vector length.  */
 620   vex_scalar_mode,
 621   /* like vex_w_dq_mode, ignore vector length.  */
 622   vex_scalar_w_dq_mode,
 623
 624   /* Static rounding.  */
 625   evex_rounding_mode,
 626   /* Supress all exceptions.  */
 627   evex_sae_mode,
 628
 629   /* Mask register operand.  */
 630   mask_mode,
 631   /* Mask register operand.  */
 632   mask_bd_mode,
 633
 634   es_reg,
 635   cs_reg,
 636   ss_reg,
 637   ds_reg,
 638   fs_reg,
 639   gs_reg,
 640
 641   eAX_reg,
 642   eCX_reg,
 643   eDX_reg,
 644   eBX_reg,
 645   eSP_reg,
 646   eBP_reg,
 647   eSI_reg,
 648   eDI_reg,
 649
 650   al_reg,
 651   cl_reg,
 652   dl_reg,
 653   bl_reg,
 654   ah_reg,
 655   ch_reg,
 656   dh_reg,
 657   bh_reg,
 658
 659   ax_reg,
 660   cx_reg,
 661   dx_reg,
 662   bx_reg,
 663   sp_reg,
 664   bp_reg,
 665   si_reg,
 666   di_reg,
 667
 668   rAX_reg,
 669   rCX_reg,
 670   rDX_reg,
 671   rBX_reg,
 672   rSP_reg,
 673   rBP_reg,
 674   rSI_reg,
 675   rDI_reg,
 676
 677   z_mode_ax_reg,
 678   indir_dx_reg
 679 };
 680
 681 enum
 682 {
 683   FLOATCODE = 1,
 684   USE_REG_TABLE,
 685   USE_MOD_TABLE,
 686   USE_RM_TABLE,
 687   USE_PREFIX_TABLE,
 688   USE_X86_64_TABLE,
 689   USE_3BYTE_TABLE,
 690   USE_XOP_8F_TABLE,
 691   USE_VEX_C4_TABLE,
 692   USE_VEX_C5_TABLE,
 693   USE_VEX_LEN_TABLE,
 694   USE_VEX_W_TABLE,
 695   USE_EVEX_TABLE
 696 };
 697
 698 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 699
 700 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 701 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 702 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 703 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 704 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 705 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 706 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 707 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 708 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 709 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 710 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 711 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 712 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 713 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 714 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 715
 716 enum
 717 {
 718   REG_80 = 0,
 719   REG_81,
 720   REG_83,
 721   REG_8F,
 722   REG_C0,
 723   REG_C1,
 724   REG_C6,
 725   REG_C7,
 726   REG_D0,
 727   REG_D1,
 728   REG_D2,
 729   REG_D3,
 730   REG_F6,
 731   REG_F7,
 732   REG_FE,
 733   REG_FF,
 734   REG_0F00,
 735   REG_0F01,
 736   REG_0F0D,
 737   REG_0F18,
 738   REG_0F1E_MOD_3,
 739   REG_0F71,
 740   REG_0F72,
 741   REG_0F73,
 742   REG_0FA6,
 743   REG_0FA7,
 744   REG_0FAE,
 745   REG_0FBA,
 746   REG_0FC7,
 747   REG_VEX_0F71,
 748   REG_VEX_0F72,
 749   REG_VEX_0F73,
 750   REG_VEX_0FAE,
 751   REG_VEX_0F38F3,
 752   REG_XOP_LWPCB,
 753   REG_XOP_LWP,
 754   REG_XOP_TBM_01,
 755   REG_XOP_TBM_02,
 756
 757   REG_EVEX_0F71,
 758   REG_EVEX_0F72,
 759   REG_EVEX_0F73,
 760   REG_EVEX_0F38C6,
 761   REG_EVEX_0F38C7
 762 };
 763
 764 enum
 765 {
 766   MOD_8D = 0,
 767   MOD_C6_REG_7,
 768   MOD_C7_REG_7,
 769   MOD_FF_REG_3,
 770   MOD_FF_REG_5,
 771   MOD_0F01_REG_0,
 772   MOD_0F01_REG_1,
 773   MOD_0F01_REG_2,
 774   MOD_0F01_REG_3,
 775   MOD_0F01_REG_5,
 776   MOD_0F01_REG_7,
 777   MOD_0F12_PREFIX_0,
 778   MOD_0F13,
 779   MOD_0F16_PREFIX_0,
 780   MOD_0F17,
 781   MOD_0F18_REG_0,
 782   MOD_0F18_REG_1,
 783   MOD_0F18_REG_2,
 784   MOD_0F18_REG_3,
 785   MOD_0F18_REG_4,
 786   MOD_0F18_REG_5,
 787   MOD_0F18_REG_6,
 788   MOD_0F18_REG_7,
 789   MOD_0F1A_PREFIX_0,
 790   MOD_0F1B_PREFIX_0,
 791   MOD_0F1B_PREFIX_1,
 792   MOD_0F1E_PREFIX_1,
 793   MOD_0F24,
 794   MOD_0F26,
 795   MOD_0F2B_PREFIX_0,
 796   MOD_0F2B_PREFIX_1,
 797   MOD_0F2B_PREFIX_2,
 798   MOD_0F2B_PREFIX_3,
 799   MOD_0F51,
 800   MOD_0F71_REG_2,
 801   MOD_0F71_REG_4,
 802   MOD_0F71_REG_6,
 803   MOD_0F72_REG_2,
 804   MOD_0F72_REG_4,
 805   MOD_0F72_REG_6,
 806   MOD_0F73_REG_2,
 807   MOD_0F73_REG_3,
 808   MOD_0F73_REG_6,
 809   MOD_0F73_REG_7,
 810   MOD_0FAE_REG_0,
 811   MOD_0FAE_REG_1,
 812   MOD_0FAE_REG_2,
 813   MOD_0FAE_REG_3,
 814   MOD_0FAE_REG_4,
 815   MOD_0FAE_REG_5,
 816   MOD_0FAE_REG_6,
 817   MOD_0FAE_REG_7,
 818   MOD_0FB2,
 819   MOD_0FB4,
 820   MOD_0FB5,
 821   MOD_0FC3,
 822   MOD_0FC7_REG_3,
 823   MOD_0FC7_REG_4,
 824   MOD_0FC7_REG_5,
 825   MOD_0FC7_REG_6,
 826   MOD_0FC7_REG_7,
 827   MOD_0FD7,
 828   MOD_0FE7_PREFIX_2,
 829   MOD_0FF0_PREFIX_3,
 830   MOD_0F382A_PREFIX_2,
 831   MOD_0F38F5_PREFIX_2,
 832   MOD_0F38F6_PREFIX_0,
 833   MOD_62_32BIT,
 834   MOD_C4_32BIT,
 835   MOD_C5_32BIT,
 836   MOD_VEX_0F12_PREFIX_0,
 837   MOD_VEX_0F13,
 838   MOD_VEX_0F16_PREFIX_0,
 839   MOD_VEX_0F17,
 840   MOD_VEX_0F2B,
 841   MOD_VEX_W_0_0F41_P_0_LEN_1,
 842   MOD_VEX_W_1_0F41_P_0_LEN_1,
 843   MOD_VEX_W_0_0F41_P_2_LEN_1,
 844   MOD_VEX_W_1_0F41_P_2_LEN_1,
 845   MOD_VEX_W_0_0F42_P_0_LEN_1,
 846   MOD_VEX_W_1_0F42_P_0_LEN_1,
 847   MOD_VEX_W_0_0F42_P_2_LEN_1,
 848   MOD_VEX_W_1_0F42_P_2_LEN_1,
 849   MOD_VEX_W_0_0F44_P_0_LEN_1,
 850   MOD_VEX_W_1_0F44_P_0_LEN_1,
 851   MOD_VEX_W_0_0F44_P_2_LEN_1,
 852   MOD_VEX_W_1_0F44_P_2_LEN_1,
 853   MOD_VEX_W_0_0F45_P_0_LEN_1,
 854   MOD_VEX_W_1_0F45_P_0_LEN_1,
 855   MOD_VEX_W_0_0F45_P_2_LEN_1,
 856   MOD_VEX_W_1_0F45_P_2_LEN_1,
 857   MOD_VEX_W_0_0F46_P_0_LEN_1,
 858   MOD_VEX_W_1_0F46_P_0_LEN_1,
 859   MOD_VEX_W_0_0F46_P_2_LEN_1,
 860   MOD_VEX_W_1_0F46_P_2_LEN_1,
 861   MOD_VEX_W_0_0F47_P_0_LEN_1,
 862   MOD_VEX_W_1_0F47_P_0_LEN_1,
 863   MOD_VEX_W_0_0F47_P_2_LEN_1,
 864   MOD_VEX_W_1_0F47_P_2_LEN_1,
 865   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 866   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 867   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 868   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 869   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 870   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 871   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 872   MOD_VEX_0F50,
 873   MOD_VEX_0F71_REG_2,
 874   MOD_VEX_0F71_REG_4,
 875   MOD_VEX_0F71_REG_6,
 876   MOD_VEX_0F72_REG_2,
 877   MOD_VEX_0F72_REG_4,
 878   MOD_VEX_0F72_REG_6,
 879   MOD_VEX_0F73_REG_2,
 880   MOD_VEX_0F73_REG_3,
 881   MOD_VEX_0F73_REG_6,
 882   MOD_VEX_0F73_REG_7,
 883   MOD_VEX_W_0_0F91_P_0_LEN_0,
 884   MOD_VEX_W_1_0F91_P_0_LEN_0,
 885   MOD_VEX_W_0_0F91_P_2_LEN_0,
 886   MOD_VEX_W_1_0F91_P_2_LEN_0,
 887   MOD_VEX_W_0_0F92_P_0_LEN_0,
 888   MOD_VEX_W_0_0F92_P_2_LEN_0,
 889   MOD_VEX_W_0_0F92_P_3_LEN_0,
 890   MOD_VEX_W_1_0F92_P_3_LEN_0,
 891   MOD_VEX_W_0_0F93_P_0_LEN_0,
 892   MOD_VEX_W_0_0F93_P_2_LEN_0,
 893   MOD_VEX_W_0_0F93_P_3_LEN_0,
 894   MOD_VEX_W_1_0F93_P_3_LEN_0,
 895   MOD_VEX_W_0_0F98_P_0_LEN_0,
 896   MOD_VEX_W_1_0F98_P_0_LEN_0,
 897   MOD_VEX_W_0_0F98_P_2_LEN_0,
 898   MOD_VEX_W_1_0F98_P_2_LEN_0,
 899   MOD_VEX_W_0_0F99_P_0_LEN_0,
 900   MOD_VEX_W_1_0F99_P_0_LEN_0,
 901   MOD_VEX_W_0_0F99_P_2_LEN_0,
 902   MOD_VEX_W_1_0F99_P_2_LEN_0,
 903   MOD_VEX_0FAE_REG_2,
 904   MOD_VEX_0FAE_REG_3,
 905   MOD_VEX_0FD7_PREFIX_2,
 906   MOD_VEX_0FE7_PREFIX_2,
 907   MOD_VEX_0FF0_PREFIX_3,
 908   MOD_VEX_0F381A_PREFIX_2,
 909   MOD_VEX_0F382A_PREFIX_2,
 910   MOD_VEX_0F382C_PREFIX_2,
 911   MOD_VEX_0F382D_PREFIX_2,
 912   MOD_VEX_0F382E_PREFIX_2,
 913   MOD_VEX_0F382F_PREFIX_2,
 914   MOD_VEX_0F385A_PREFIX_2,
 915   MOD_VEX_0F388C_PREFIX_2,
 916   MOD_VEX_0F388E_PREFIX_2,
 917   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 919   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 923   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 925
 926   MOD_EVEX_0F10_PREFIX_1,
 927   MOD_EVEX_0F10_PREFIX_3,
 928   MOD_EVEX_0F11_PREFIX_1,
 929   MOD_EVEX_0F11_PREFIX_3,
 930   MOD_EVEX_0F12_PREFIX_0,
 931   MOD_EVEX_0F16_PREFIX_0,
 932   MOD_EVEX_0F38C6_REG_1,
 933   MOD_EVEX_0F38C6_REG_2,
 934   MOD_EVEX_0F38C6_REG_5,
 935   MOD_EVEX_0F38C6_REG_6,
 936   MOD_EVEX_0F38C7_REG_1,
 937   MOD_EVEX_0F38C7_REG_2,
 938   MOD_EVEX_0F38C7_REG_5,
 939   MOD_EVEX_0F38C7_REG_6
 940 };
 941
 942 enum
 943 {
 944   RM_C6_REG_7 = 0,
 945   RM_C7_REG_7,
 946   RM_0F01_REG_0,
 947   RM_0F01_REG_1,
 948   RM_0F01_REG_2,
 949   RM_0F01_REG_3,
 950   RM_0F01_REG_5,
 951   RM_0F01_REG_7,
 952   RM_0F1E_MOD_3_REG_7,
 953   RM_0FAE_REG_6,
 954   RM_0FAE_REG_7
 955 };
 956
 957 enum
 958 {
 959   PREFIX_90 = 0,
 960   PREFIX_MOD_0_0F01_REG_5,
 961   PREFIX_MOD_3_0F01_REG_5_RM_0,
 962   PREFIX_MOD_3_0F01_REG_5_RM_2,
 963   PREFIX_0F09,
 964   PREFIX_0F10,
 965   PREFIX_0F11,
 966   PREFIX_0F12,
 967   PREFIX_0F16,
 968   PREFIX_0F1A,
 969   PREFIX_0F1B,
 970   PREFIX_0F1E,
 971   PREFIX_0F2A,
 972   PREFIX_0F2B,
 973   PREFIX_0F2C,
 974   PREFIX_0F2D,
 975   PREFIX_0F2E,
 976   PREFIX_0F2F,
 977   PREFIX_0F51,
 978   PREFIX_0F52,
 979   PREFIX_0F53,
 980   PREFIX_0F58,
 981   PREFIX_0F59,
 982   PREFIX_0F5A,
 983   PREFIX_0F5B,
 984   PREFIX_0F5C,
 985   PREFIX_0F5D,
 986   PREFIX_0F5E,
 987   PREFIX_0F5F,
 988   PREFIX_0F60,
 989   PREFIX_0F61,
 990   PREFIX_0F62,
 991   PREFIX_0F6C,
 992   PREFIX_0F6D,
 993   PREFIX_0F6F,
 994   PREFIX_0F70,
 995   PREFIX_0F73_REG_3,
 996   PREFIX_0F73_REG_7,
 997   PREFIX_0F78,
 998   PREFIX_0F79,
 999   PREFIX_0F7C,
1000   PREFIX_0F7D,
1001   PREFIX_0F7E,
1002   PREFIX_0F7F,
1003   PREFIX_0FAE_REG_0,
1004   PREFIX_0FAE_REG_1,
1005   PREFIX_0FAE_REG_2,
1006   PREFIX_0FAE_REG_3,
1007   PREFIX_MOD_0_0FAE_REG_4,
1008   PREFIX_MOD_3_0FAE_REG_4,
1009   PREFIX_MOD_0_0FAE_REG_5,
1010   PREFIX_MOD_3_0FAE_REG_5,
1011   PREFIX_0FAE_REG_6,
1012   PREFIX_0FAE_REG_7,
1013   PREFIX_0FB8,
1014   PREFIX_0FBC,
1015   PREFIX_0FBD,
1016   PREFIX_0FC2,
1017   PREFIX_MOD_0_0FC3,
1018   PREFIX_MOD_0_0FC7_REG_6,
1019   PREFIX_MOD_3_0FC7_REG_6,
1020   PREFIX_MOD_3_0FC7_REG_7,
1021   PREFIX_0FD0,
1022   PREFIX_0FD6,
1023   PREFIX_0FE6,
1024   PREFIX_0FE7,
1025   PREFIX_0FF0,
1026   PREFIX_0FF7,
1027   PREFIX_0F3810,
1028   PREFIX_0F3814,
1029   PREFIX_0F3815,
1030   PREFIX_0F3817,
1031   PREFIX_0F3820,
1032   PREFIX_0F3821,
1033   PREFIX_0F3822,
1034   PREFIX_0F3823,
1035   PREFIX_0F3824,
1036   PREFIX_0F3825,
1037   PREFIX_0F3828,
1038   PREFIX_0F3829,
1039   PREFIX_0F382A,
1040   PREFIX_0F382B,
1041   PREFIX_0F3830,
1042   PREFIX_0F3831,
1043   PREFIX_0F3832,
1044   PREFIX_0F3833,
1045   PREFIX_0F3834,
1046   PREFIX_0F3835,
1047   PREFIX_0F3837,
1048   PREFIX_0F3838,
1049   PREFIX_0F3839,
1050   PREFIX_0F383A,
1051   PREFIX_0F383B,
1052   PREFIX_0F383C,
1053   PREFIX_0F383D,
1054   PREFIX_0F383E,
1055   PREFIX_0F383F,
1056   PREFIX_0F3840,
1057   PREFIX_0F3841,
1058   PREFIX_0F3880,
1059   PREFIX_0F3881,
1060   PREFIX_0F3882,
1061   PREFIX_0F38C8,
1062   PREFIX_0F38C9,
1063   PREFIX_0F38CA,
1064   PREFIX_0F38CB,
1065   PREFIX_0F38CC,
1066   PREFIX_0F38CD,
1067   PREFIX_0F38CF,
1068   PREFIX_0F38DB,
1069   PREFIX_0F38DC,
1070   PREFIX_0F38DD,
1071   PREFIX_0F38DE,
1072   PREFIX_0F38DF,
1073   PREFIX_0F38F0,
1074   PREFIX_0F38F1,
1075   PREFIX_0F38F5,
1076   PREFIX_0F38F6,
1077   PREFIX_0F3A08,
1078   PREFIX_0F3A09,
1079   PREFIX_0F3A0A,
1080   PREFIX_0F3A0B,
1081   PREFIX_0F3A0C,
1082   PREFIX_0F3A0D,
1083   PREFIX_0F3A0E,
1084   PREFIX_0F3A14,
1085   PREFIX_0F3A15,
1086   PREFIX_0F3A16,
1087   PREFIX_0F3A17,
1088   PREFIX_0F3A20,
1089   PREFIX_0F3A21,
1090   PREFIX_0F3A22,
1091   PREFIX_0F3A40,
1092   PREFIX_0F3A41,
1093   PREFIX_0F3A42,
1094   PREFIX_0F3A44,
1095   PREFIX_0F3A60,
1096   PREFIX_0F3A61,
1097   PREFIX_0F3A62,
1098   PREFIX_0F3A63,
1099   PREFIX_0F3ACC,
1100   PREFIX_0F3ACE,
1101   PREFIX_0F3ACF,
1102   PREFIX_0F3ADF,
1103   PREFIX_VEX_0F10,
1104   PREFIX_VEX_0F11,
1105   PREFIX_VEX_0F12,
1106   PREFIX_VEX_0F16,
1107   PREFIX_VEX_0F2A,
1108   PREFIX_VEX_0F2C,
1109   PREFIX_VEX_0F2D,
1110   PREFIX_VEX_0F2E,
1111   PREFIX_VEX_0F2F,
1112   PREFIX_VEX_0F41,
1113   PREFIX_VEX_0F42,
1114   PREFIX_VEX_0F44,
1115   PREFIX_VEX_0F45,
1116   PREFIX_VEX_0F46,
1117   PREFIX_VEX_0F47,
1118   PREFIX_VEX_0F4A,
1119   PREFIX_VEX_0F4B,
1120   PREFIX_VEX_0F51,
1121   PREFIX_VEX_0F52,
1122   PREFIX_VEX_0F53,
1123   PREFIX_VEX_0F58,
1124   PREFIX_VEX_0F59,
1125   PREFIX_VEX_0F5A,
1126   PREFIX_VEX_0F5B,
1127   PREFIX_VEX_0F5C,
1128   PREFIX_VEX_0F5D,
1129   PREFIX_VEX_0F5E,
1130   PREFIX_VEX_0F5F,
1131   PREFIX_VEX_0F60,
1132   PREFIX_VEX_0F61,
1133   PREFIX_VEX_0F62,
1134   PREFIX_VEX_0F63,
1135   PREFIX_VEX_0F64,
1136   PREFIX_VEX_0F65,
1137   PREFIX_VEX_0F66,
1138   PREFIX_VEX_0F67,
1139   PREFIX_VEX_0F68,
1140   PREFIX_VEX_0F69,
1141   PREFIX_VEX_0F6A,
1142   PREFIX_VEX_0F6B,
1143   PREFIX_VEX_0F6C,
1144   PREFIX_VEX_0F6D,
1145   PREFIX_VEX_0F6E,
1146   PREFIX_VEX_0F6F,
1147   PREFIX_VEX_0F70,
1148   PREFIX_VEX_0F71_REG_2,
1149   PREFIX_VEX_0F71_REG_4,
1150   PREFIX_VEX_0F71_REG_6,
1151   PREFIX_VEX_0F72_REG_2,
1152   PREFIX_VEX_0F72_REG_4,
1153   PREFIX_VEX_0F72_REG_6,
1154   PREFIX_VEX_0F73_REG_2,
1155   PREFIX_VEX_0F73_REG_3,
1156   PREFIX_VEX_0F73_REG_6,
1157   PREFIX_VEX_0F73_REG_7,
1158   PREFIX_VEX_0F74,
1159   PREFIX_VEX_0F75,
1160   PREFIX_VEX_0F76,
1161   PREFIX_VEX_0F77,
1162   PREFIX_VEX_0F7C,
1163   PREFIX_VEX_0F7D,
1164   PREFIX_VEX_0F7E,
1165   PREFIX_VEX_0F7F,
1166   PREFIX_VEX_0F90,
1167   PREFIX_VEX_0F91,
1168   PREFIX_VEX_0F92,
1169   PREFIX_VEX_0F93,
1170   PREFIX_VEX_0F98,
1171   PREFIX_VEX_0F99,
1172   PREFIX_VEX_0FC2,
1173   PREFIX_VEX_0FC4,
1174   PREFIX_VEX_0FC5,
1175   PREFIX_VEX_0FD0,
1176   PREFIX_VEX_0FD1,
1177   PREFIX_VEX_0FD2,
1178   PREFIX_VEX_0FD3,
1179   PREFIX_VEX_0FD4,
1180   PREFIX_VEX_0FD5,
1181   PREFIX_VEX_0FD6,
1182   PREFIX_VEX_0FD7,
1183   PREFIX_VEX_0FD8,
1184   PREFIX_VEX_0FD9,
1185   PREFIX_VEX_0FDA,
1186   PREFIX_VEX_0FDB,
1187   PREFIX_VEX_0FDC,
1188   PREFIX_VEX_0FDD,
1189   PREFIX_VEX_0FDE,
1190   PREFIX_VEX_0FDF,
1191   PREFIX_VEX_0FE0,
1192   PREFIX_VEX_0FE1,
1193   PREFIX_VEX_0FE2,
1194   PREFIX_VEX_0FE3,
1195   PREFIX_VEX_0FE4,
1196   PREFIX_VEX_0FE5,
1197   PREFIX_VEX_0FE6,
1198   PREFIX_VEX_0FE7,
1199   PREFIX_VEX_0FE8,
1200   PREFIX_VEX_0FE9,
1201   PREFIX_VEX_0FEA,
1202   PREFIX_VEX_0FEB,
1203   PREFIX_VEX_0FEC,
1204   PREFIX_VEX_0FED,
1205   PREFIX_VEX_0FEE,
1206   PREFIX_VEX_0FEF,
1207   PREFIX_VEX_0FF0,
1208   PREFIX_VEX_0FF1,
1209   PREFIX_VEX_0FF2,
1210   PREFIX_VEX_0FF3,
1211   PREFIX_VEX_0FF4,
1212   PREFIX_VEX_0FF5,
1213   PREFIX_VEX_0FF6,
1214   PREFIX_VEX_0FF7,
1215   PREFIX_VEX_0FF8,
1216   PREFIX_VEX_0FF9,
1217   PREFIX_VEX_0FFA,
1218   PREFIX_VEX_0FFB,
1219   PREFIX_VEX_0FFC,
1220   PREFIX_VEX_0FFD,
1221   PREFIX_VEX_0FFE,
1222   PREFIX_VEX_0F3800,
1223   PREFIX_VEX_0F3801,
1224   PREFIX_VEX_0F3802,
1225   PREFIX_VEX_0F3803,
1226   PREFIX_VEX_0F3804,
1227   PREFIX_VEX_0F3805,
1228   PREFIX_VEX_0F3806,
1229   PREFIX_VEX_0F3807,
1230   PREFIX_VEX_0F3808,
1231   PREFIX_VEX_0F3809,
1232   PREFIX_VEX_0F380A,
1233   PREFIX_VEX_0F380B,
1234   PREFIX_VEX_0F380C,
1235   PREFIX_VEX_0F380D,
1236   PREFIX_VEX_0F380E,
1237   PREFIX_VEX_0F380F,
1238   PREFIX_VEX_0F3813,
1239   PREFIX_VEX_0F3816,
1240   PREFIX_VEX_0F3817,
1241   PREFIX_VEX_0F3818,
1242   PREFIX_VEX_0F3819,
1243   PREFIX_VEX_0F381A,
1244   PREFIX_VEX_0F381C,
1245   PREFIX_VEX_0F381D,
1246   PREFIX_VEX_0F381E,
1247   PREFIX_VEX_0F3820,
1248   PREFIX_VEX_0F3821,
1249   PREFIX_VEX_0F3822,
1250   PREFIX_VEX_0F3823,
1251   PREFIX_VEX_0F3824,
1252   PREFIX_VEX_0F3825,
1253   PREFIX_VEX_0F3828,
1254   PREFIX_VEX_0F3829,
1255   PREFIX_VEX_0F382A,
1256   PREFIX_VEX_0F382B,
1257   PREFIX_VEX_0F382C,
1258   PREFIX_VEX_0F382D,
1259   PREFIX_VEX_0F382E,
1260   PREFIX_VEX_0F382F,
1261   PREFIX_VEX_0F3830,
1262   PREFIX_VEX_0F3831,
1263   PREFIX_VEX_0F3832,
1264   PREFIX_VEX_0F3833,
1265   PREFIX_VEX_0F3834,
1266   PREFIX_VEX_0F3835,
1267   PREFIX_VEX_0F3836,
1268   PREFIX_VEX_0F3837,
1269   PREFIX_VEX_0F3838,
1270   PREFIX_VEX_0F3839,
1271   PREFIX_VEX_0F383A,
1272   PREFIX_VEX_0F383B,
1273   PREFIX_VEX_0F383C,
1274   PREFIX_VEX_0F383D,
1275   PREFIX_VEX_0F383E,
1276   PREFIX_VEX_0F383F,
1277   PREFIX_VEX_0F3840,
1278   PREFIX_VEX_0F3841,
1279   PREFIX_VEX_0F3845,
1280   PREFIX_VEX_0F3846,
1281   PREFIX_VEX_0F3847,
1282   PREFIX_VEX_0F3858,
1283   PREFIX_VEX_0F3859,
1284   PREFIX_VEX_0F385A,
1285   PREFIX_VEX_0F3878,
1286   PREFIX_VEX_0F3879,
1287   PREFIX_VEX_0F388C,
1288   PREFIX_VEX_0F388E,
1289   PREFIX_VEX_0F3890,
1290   PREFIX_VEX_0F3891,
1291   PREFIX_VEX_0F3892,
1292   PREFIX_VEX_0F3893,
1293   PREFIX_VEX_0F3896,
1294   PREFIX_VEX_0F3897,
1295   PREFIX_VEX_0F3898,
1296   PREFIX_VEX_0F3899,
1297   PREFIX_VEX_0F389A,
1298   PREFIX_VEX_0F389B,
1299   PREFIX_VEX_0F389C,
1300   PREFIX_VEX_0F389D,
1301   PREFIX_VEX_0F389E,
1302   PREFIX_VEX_0F389F,
1303   PREFIX_VEX_0F38A6,
1304   PREFIX_VEX_0F38A7,
1305   PREFIX_VEX_0F38A8,
1306   PREFIX_VEX_0F38A9,
1307   PREFIX_VEX_0F38AA,
1308   PREFIX_VEX_0F38AB,
1309   PREFIX_VEX_0F38AC,
1310   PREFIX_VEX_0F38AD,
1311   PREFIX_VEX_0F38AE,
1312   PREFIX_VEX_0F38AF,
1313   PREFIX_VEX_0F38B6,
1314   PREFIX_VEX_0F38B7,
1315   PREFIX_VEX_0F38B8,
1316   PREFIX_VEX_0F38B9,
1317   PREFIX_VEX_0F38BA,
1318   PREFIX_VEX_0F38BB,
1319   PREFIX_VEX_0F38BC,
1320   PREFIX_VEX_0F38BD,
1321   PREFIX_VEX_0F38BE,
1322   PREFIX_VEX_0F38BF,
1323   PREFIX_VEX_0F38CF,
1324   PREFIX_VEX_0F38DB,
1325   PREFIX_VEX_0F38DC,
1326   PREFIX_VEX_0F38DD,
1327   PREFIX_VEX_0F38DE,
1328   PREFIX_VEX_0F38DF,
1329   PREFIX_VEX_0F38F2,
1330   PREFIX_VEX_0F38F3_REG_1,
1331   PREFIX_VEX_0F38F3_REG_2,
1332   PREFIX_VEX_0F38F3_REG_3,
1333   PREFIX_VEX_0F38F5,
1334   PREFIX_VEX_0F38F6,
1335   PREFIX_VEX_0F38F7,
1336   PREFIX_VEX_0F3A00,
1337   PREFIX_VEX_0F3A01,
1338   PREFIX_VEX_0F3A02,
1339   PREFIX_VEX_0F3A04,
1340   PREFIX_VEX_0F3A05,
1341   PREFIX_VEX_0F3A06,
1342   PREFIX_VEX_0F3A08,
1343   PREFIX_VEX_0F3A09,
1344   PREFIX_VEX_0F3A0A,
1345   PREFIX_VEX_0F3A0B,
1346   PREFIX_VEX_0F3A0C,
1347   PREFIX_VEX_0F3A0D,
1348   PREFIX_VEX_0F3A0E,
1349   PREFIX_VEX_0F3A0F,
1350   PREFIX_VEX_0F3A14,
1351   PREFIX_VEX_0F3A15,
1352   PREFIX_VEX_0F3A16,
1353   PREFIX_VEX_0F3A17,
1354   PREFIX_VEX_0F3A18,
1355   PREFIX_VEX_0F3A19,
1356   PREFIX_VEX_0F3A1D,
1357   PREFIX_VEX_0F3A20,
1358   PREFIX_VEX_0F3A21,
1359   PREFIX_VEX_0F3A22,
1360   PREFIX_VEX_0F3A30,
1361   PREFIX_VEX_0F3A31,
1362   PREFIX_VEX_0F3A32,
1363   PREFIX_VEX_0F3A33,
1364   PREFIX_VEX_0F3A38,
1365   PREFIX_VEX_0F3A39,
1366   PREFIX_VEX_0F3A40,
1367   PREFIX_VEX_0F3A41,
1368   PREFIX_VEX_0F3A42,
1369   PREFIX_VEX_0F3A44,
1370   PREFIX_VEX_0F3A46,
1371   PREFIX_VEX_0F3A48,
1372   PREFIX_VEX_0F3A49,
1373   PREFIX_VEX_0F3A4A,
1374   PREFIX_VEX_0F3A4B,
1375   PREFIX_VEX_0F3A4C,
1376   PREFIX_VEX_0F3A5C,
1377   PREFIX_VEX_0F3A5D,
1378   PREFIX_VEX_0F3A5E,
1379   PREFIX_VEX_0F3A5F,
1380   PREFIX_VEX_0F3A60,
1381   PREFIX_VEX_0F3A61,
1382   PREFIX_VEX_0F3A62,
1383   PREFIX_VEX_0F3A63,
1384   PREFIX_VEX_0F3A68,
1385   PREFIX_VEX_0F3A69,
1386   PREFIX_VEX_0F3A6A,
1387   PREFIX_VEX_0F3A6B,
1388   PREFIX_VEX_0F3A6C,
1389   PREFIX_VEX_0F3A6D,
1390   PREFIX_VEX_0F3A6E,
1391   PREFIX_VEX_0F3A6F,
1392   PREFIX_VEX_0F3A78,
1393   PREFIX_VEX_0F3A79,
1394   PREFIX_VEX_0F3A7A,
1395   PREFIX_VEX_0F3A7B,
1396   PREFIX_VEX_0F3A7C,
1397   PREFIX_VEX_0F3A7D,
1398   PREFIX_VEX_0F3A7E,
1399   PREFIX_VEX_0F3A7F,
1400   PREFIX_VEX_0F3ACE,
1401   PREFIX_VEX_0F3ACF,
1402   PREFIX_VEX_0F3ADF,
1403   PREFIX_VEX_0F3AF0,
1404
1405   PREFIX_EVEX_0F10,
1406   PREFIX_EVEX_0F11,
1407   PREFIX_EVEX_0F12,
1408   PREFIX_EVEX_0F13,
1409   PREFIX_EVEX_0F14,
1410   PREFIX_EVEX_0F15,
1411   PREFIX_EVEX_0F16,
1412   PREFIX_EVEX_0F17,
1413   PREFIX_EVEX_0F28,
1414   PREFIX_EVEX_0F29,
1415   PREFIX_EVEX_0F2A,
1416   PREFIX_EVEX_0F2B,
1417   PREFIX_EVEX_0F2C,
1418   PREFIX_EVEX_0F2D,
1419   PREFIX_EVEX_0F2E,
1420   PREFIX_EVEX_0F2F,
1421   PREFIX_EVEX_0F51,
1422   PREFIX_EVEX_0F54,
1423   PREFIX_EVEX_0F55,
1424   PREFIX_EVEX_0F56,
1425   PREFIX_EVEX_0F57,
1426   PREFIX_EVEX_0F58,
1427   PREFIX_EVEX_0F59,
1428   PREFIX_EVEX_0F5A,
1429   PREFIX_EVEX_0F5B,
1430   PREFIX_EVEX_0F5C,
1431   PREFIX_EVEX_0F5D,
1432   PREFIX_EVEX_0F5E,
1433   PREFIX_EVEX_0F5F,
1434   PREFIX_EVEX_0F60,
1435   PREFIX_EVEX_0F61,
1436   PREFIX_EVEX_0F62,
1437   PREFIX_EVEX_0F63,
1438   PREFIX_EVEX_0F64,
1439   PREFIX_EVEX_0F65,
1440   PREFIX_EVEX_0F66,
1441   PREFIX_EVEX_0F67,
1442   PREFIX_EVEX_0F68,
1443   PREFIX_EVEX_0F69,
1444   PREFIX_EVEX_0F6A,
1445   PREFIX_EVEX_0F6B,
1446   PREFIX_EVEX_0F6C,
1447   PREFIX_EVEX_0F6D,
1448   PREFIX_EVEX_0F6E,
1449   PREFIX_EVEX_0F6F,
1450   PREFIX_EVEX_0F70,
1451   PREFIX_EVEX_0F71_REG_2,
1452   PREFIX_EVEX_0F71_REG_4,
1453   PREFIX_EVEX_0F71_REG_6,
1454   PREFIX_EVEX_0F72_REG_0,
1455   PREFIX_EVEX_0F72_REG_1,
1456   PREFIX_EVEX_0F72_REG_2,
1457   PREFIX_EVEX_0F72_REG_4,
1458   PREFIX_EVEX_0F72_REG_6,
1459   PREFIX_EVEX_0F73_REG_2,
1460   PREFIX_EVEX_0F73_REG_3,
1461   PREFIX_EVEX_0F73_REG_6,
1462   PREFIX_EVEX_0F73_REG_7,
1463   PREFIX_EVEX_0F74,
1464   PREFIX_EVEX_0F75,
1465   PREFIX_EVEX_0F76,
1466   PREFIX_EVEX_0F78,
1467   PREFIX_EVEX_0F79,
1468   PREFIX_EVEX_0F7A,
1469   PREFIX_EVEX_0F7B,
1470   PREFIX_EVEX_0F7E,
1471   PREFIX_EVEX_0F7F,
1472   PREFIX_EVEX_0FC2,
1473   PREFIX_EVEX_0FC4,
1474   PREFIX_EVEX_0FC5,
1475   PREFIX_EVEX_0FC6,
1476   PREFIX_EVEX_0FD1,
1477   PREFIX_EVEX_0FD2,
1478   PREFIX_EVEX_0FD3,
1479   PREFIX_EVEX_0FD4,
1480   PREFIX_EVEX_0FD5,
1481   PREFIX_EVEX_0FD6,
1482   PREFIX_EVEX_0FD8,
1483   PREFIX_EVEX_0FD9,
1484   PREFIX_EVEX_0FDA,
1485   PREFIX_EVEX_0FDB,
1486   PREFIX_EVEX_0FDC,
1487   PREFIX_EVEX_0FDD,
1488   PREFIX_EVEX_0FDE,
1489   PREFIX_EVEX_0FDF,
1490   PREFIX_EVEX_0FE0,
1491   PREFIX_EVEX_0FE1,
1492   PREFIX_EVEX_0FE2,
1493   PREFIX_EVEX_0FE3,
1494   PREFIX_EVEX_0FE4,
1495   PREFIX_EVEX_0FE5,
1496   PREFIX_EVEX_0FE6,
1497   PREFIX_EVEX_0FE7,
1498   PREFIX_EVEX_0FE8,
1499   PREFIX_EVEX_0FE9,
1500   PREFIX_EVEX_0FEA,
1501   PREFIX_EVEX_0FEB,
1502   PREFIX_EVEX_0FEC,
1503   PREFIX_EVEX_0FED,
1504   PREFIX_EVEX_0FEE,
1505   PREFIX_EVEX_0FEF,
1506   PREFIX_EVEX_0FF1,
1507   PREFIX_EVEX_0FF2,
1508   PREFIX_EVEX_0FF3,
1509   PREFIX_EVEX_0FF4,
1510   PREFIX_EVEX_0FF5,
1511   PREFIX_EVEX_0FF6,
1512   PREFIX_EVEX_0FF8,
1513   PREFIX_EVEX_0FF9,
1514   PREFIX_EVEX_0FFA,
1515   PREFIX_EVEX_0FFB,
1516   PREFIX_EVEX_0FFC,
1517   PREFIX_EVEX_0FFD,
1518   PREFIX_EVEX_0FFE,
1519   PREFIX_EVEX_0F3800,
1520   PREFIX_EVEX_0F3804,
1521   PREFIX_EVEX_0F380B,
1522   PREFIX_EVEX_0F380C,
1523   PREFIX_EVEX_0F380D,
1524   PREFIX_EVEX_0F3810,
1525   PREFIX_EVEX_0F3811,
1526   PREFIX_EVEX_0F3812,
1527   PREFIX_EVEX_0F3813,
1528   PREFIX_EVEX_0F3814,
1529   PREFIX_EVEX_0F3815,
1530   PREFIX_EVEX_0F3816,
1531   PREFIX_EVEX_0F3818,
1532   PREFIX_EVEX_0F3819,
1533   PREFIX_EVEX_0F381A,
1534   PREFIX_EVEX_0F381B,
1535   PREFIX_EVEX_0F381C,
1536   PREFIX_EVEX_0F381D,
1537   PREFIX_EVEX_0F381E,
1538   PREFIX_EVEX_0F381F,
1539   PREFIX_EVEX_0F3820,
1540   PREFIX_EVEX_0F3821,
1541   PREFIX_EVEX_0F3822,
1542   PREFIX_EVEX_0F3823,
1543   PREFIX_EVEX_0F3824,
1544   PREFIX_EVEX_0F3825,
1545   PREFIX_EVEX_0F3826,
1546   PREFIX_EVEX_0F3827,
1547   PREFIX_EVEX_0F3828,
1548   PREFIX_EVEX_0F3829,
1549   PREFIX_EVEX_0F382A,
1550   PREFIX_EVEX_0F382B,
1551   PREFIX_EVEX_0F382C,
1552   PREFIX_EVEX_0F382D,
1553   PREFIX_EVEX_0F3830,
1554   PREFIX_EVEX_0F3831,
1555   PREFIX_EVEX_0F3832,
1556   PREFIX_EVEX_0F3833,
1557   PREFIX_EVEX_0F3834,
1558   PREFIX_EVEX_0F3835,
1559   PREFIX_EVEX_0F3836,
1560   PREFIX_EVEX_0F3837,
1561   PREFIX_EVEX_0F3838,
1562   PREFIX_EVEX_0F3839,
1563   PREFIX_EVEX_0F383A,
1564   PREFIX_EVEX_0F383B,
1565   PREFIX_EVEX_0F383C,
1566   PREFIX_EVEX_0F383D,
1567   PREFIX_EVEX_0F383E,
1568   PREFIX_EVEX_0F383F,
1569   PREFIX_EVEX_0F3840,
1570   PREFIX_EVEX_0F3842,
1571   PREFIX_EVEX_0F3843,
1572   PREFIX_EVEX_0F3844,
1573   PREFIX_EVEX_0F3845,
1574   PREFIX_EVEX_0F3846,
1575   PREFIX_EVEX_0F3847,
1576   PREFIX_EVEX_0F384C,
1577   PREFIX_EVEX_0F384D,
1578   PREFIX_EVEX_0F384E,
1579   PREFIX_EVEX_0F384F,
1580   PREFIX_EVEX_0F3850,
1581   PREFIX_EVEX_0F3851,
1582   PREFIX_EVEX_0F3852,
1583   PREFIX_EVEX_0F3853,
1584   PREFIX_EVEX_0F3854,
1585   PREFIX_EVEX_0F3855,
1586   PREFIX_EVEX_0F3858,
1587   PREFIX_EVEX_0F3859,
1588   PREFIX_EVEX_0F385A,
1589   PREFIX_EVEX_0F385B,
1590   PREFIX_EVEX_0F3862,
1591   PREFIX_EVEX_0F3863,
1592   PREFIX_EVEX_0F3864,
1593   PREFIX_EVEX_0F3865,
1594   PREFIX_EVEX_0F3866,
1595   PREFIX_EVEX_0F3870,
1596   PREFIX_EVEX_0F3871,
1597   PREFIX_EVEX_0F3872,
1598   PREFIX_EVEX_0F3873,
1599   PREFIX_EVEX_0F3875,
1600   PREFIX_EVEX_0F3876,
1601   PREFIX_EVEX_0F3877,
1602   PREFIX_EVEX_0F3878,
1603   PREFIX_EVEX_0F3879,
1604   PREFIX_EVEX_0F387A,
1605   PREFIX_EVEX_0F387B,
1606   PREFIX_EVEX_0F387C,
1607   PREFIX_EVEX_0F387D,
1608   PREFIX_EVEX_0F387E,
1609   PREFIX_EVEX_0F387F,
1610   PREFIX_EVEX_0F3883,
1611   PREFIX_EVEX_0F3888,
1612   PREFIX_EVEX_0F3889,
1613   PREFIX_EVEX_0F388A,
1614   PREFIX_EVEX_0F388B,
1615   PREFIX_EVEX_0F388D,
1616   PREFIX_EVEX_0F388F,
1617   PREFIX_EVEX_0F3890,
1618   PREFIX_EVEX_0F3891,
1619   PREFIX_EVEX_0F3892,
1620   PREFIX_EVEX_0F3893,
1621   PREFIX_EVEX_0F3896,
1622   PREFIX_EVEX_0F3897,
1623   PREFIX_EVEX_0F3898,
1624   PREFIX_EVEX_0F3899,
1625   PREFIX_EVEX_0F389A,
1626   PREFIX_EVEX_0F389B,
1627   PREFIX_EVEX_0F389C,
1628   PREFIX_EVEX_0F389D,
1629   PREFIX_EVEX_0F389E,
1630   PREFIX_EVEX_0F389F,
1631   PREFIX_EVEX_0F38A0,
1632   PREFIX_EVEX_0F38A1,
1633   PREFIX_EVEX_0F38A2,
1634   PREFIX_EVEX_0F38A3,
1635   PREFIX_EVEX_0F38A6,
1636   PREFIX_EVEX_0F38A7,
1637   PREFIX_EVEX_0F38A8,
1638   PREFIX_EVEX_0F38A9,
1639   PREFIX_EVEX_0F38AA,
1640   PREFIX_EVEX_0F38AB,
1641   PREFIX_EVEX_0F38AC,
1642   PREFIX_EVEX_0F38AD,
1643   PREFIX_EVEX_0F38AE,
1644   PREFIX_EVEX_0F38AF,
1645   PREFIX_EVEX_0F38B4,
1646   PREFIX_EVEX_0F38B5,
1647   PREFIX_EVEX_0F38B6,
1648   PREFIX_EVEX_0F38B7,
1649   PREFIX_EVEX_0F38B8,
1650   PREFIX_EVEX_0F38B9,
1651   PREFIX_EVEX_0F38BA,
1652   PREFIX_EVEX_0F38BB,
1653   PREFIX_EVEX_0F38BC,
1654   PREFIX_EVEX_0F38BD,
1655   PREFIX_EVEX_0F38BE,
1656   PREFIX_EVEX_0F38BF,
1657   PREFIX_EVEX_0F38C4,
1658   PREFIX_EVEX_0F38C6_REG_1,
1659   PREFIX_EVEX_0F38C6_REG_2,
1660   PREFIX_EVEX_0F38C6_REG_5,
1661   PREFIX_EVEX_0F38C6_REG_6,
1662   PREFIX_EVEX_0F38C7_REG_1,
1663   PREFIX_EVEX_0F38C7_REG_2,
1664   PREFIX_EVEX_0F38C7_REG_5,
1665   PREFIX_EVEX_0F38C7_REG_6,
1666   PREFIX_EVEX_0F38C8,
1667   PREFIX_EVEX_0F38CA,
1668   PREFIX_EVEX_0F38CB,
1669   PREFIX_EVEX_0F38CC,
1670   PREFIX_EVEX_0F38CD,
1671   PREFIX_EVEX_0F38CF,
1672   PREFIX_EVEX_0F38DC,
1673   PREFIX_EVEX_0F38DD,
1674   PREFIX_EVEX_0F38DE,
1675   PREFIX_EVEX_0F38DF,
1676
1677   PREFIX_EVEX_0F3A00,
1678   PREFIX_EVEX_0F3A01,
1679   PREFIX_EVEX_0F3A03,
1680   PREFIX_EVEX_0F3A04,
1681   PREFIX_EVEX_0F3A05,
1682   PREFIX_EVEX_0F3A08,
1683   PREFIX_EVEX_0F3A09,
1684   PREFIX_EVEX_0F3A0A,
1685   PREFIX_EVEX_0F3A0B,
1686   PREFIX_EVEX_0F3A0F,
1687   PREFIX_EVEX_0F3A14,
1688   PREFIX_EVEX_0F3A15,
1689   PREFIX_EVEX_0F3A16,
1690   PREFIX_EVEX_0F3A17,
1691   PREFIX_EVEX_0F3A18,
1692   PREFIX_EVEX_0F3A19,
1693   PREFIX_EVEX_0F3A1A,
1694   PREFIX_EVEX_0F3A1B,
1695   PREFIX_EVEX_0F3A1D,
1696   PREFIX_EVEX_0F3A1E,
1697   PREFIX_EVEX_0F3A1F,
1698   PREFIX_EVEX_0F3A20,
1699   PREFIX_EVEX_0F3A21,
1700   PREFIX_EVEX_0F3A22,
1701   PREFIX_EVEX_0F3A23,
1702   PREFIX_EVEX_0F3A25,
1703   PREFIX_EVEX_0F3A26,
1704   PREFIX_EVEX_0F3A27,
1705   PREFIX_EVEX_0F3A38,
1706   PREFIX_EVEX_0F3A39,
1707   PREFIX_EVEX_0F3A3A,
1708   PREFIX_EVEX_0F3A3B,
1709   PREFIX_EVEX_0F3A3E,
1710   PREFIX_EVEX_0F3A3F,
1711   PREFIX_EVEX_0F3A42,
1712   PREFIX_EVEX_0F3A43,
1713   PREFIX_EVEX_0F3A44,
1714   PREFIX_EVEX_0F3A50,
1715   PREFIX_EVEX_0F3A51,
1716   PREFIX_EVEX_0F3A54,
1717   PREFIX_EVEX_0F3A55,
1718   PREFIX_EVEX_0F3A56,
1719   PREFIX_EVEX_0F3A57,
1720   PREFIX_EVEX_0F3A66,
1721   PREFIX_EVEX_0F3A67,
1722   PREFIX_EVEX_0F3A70,
1723   PREFIX_EVEX_0F3A71,
1724   PREFIX_EVEX_0F3A72,
1725   PREFIX_EVEX_0F3A73,
1726   PREFIX_EVEX_0F3ACE,
1727   PREFIX_EVEX_0F3ACF
1728 };
1729
1730 enum
1731 {
1732   X86_64_06 = 0,
1733   X86_64_07,
1734   X86_64_0D,
1735   X86_64_16,
1736   X86_64_17,
1737   X86_64_1E,
1738   X86_64_1F,
1739   X86_64_27,
1740   X86_64_2F,
1741   X86_64_37,
1742   X86_64_3F,
1743   X86_64_60,
1744   X86_64_61,
1745   X86_64_62,
1746   X86_64_63,
1747   X86_64_6D,
1748   X86_64_6F,
1749   X86_64_82,
1750   X86_64_9A,
1751   X86_64_C4,
1752   X86_64_C5,
1753   X86_64_CE,
1754   X86_64_D4,
1755   X86_64_D5,
1756   X86_64_E8,
1757   X86_64_E9,
1758   X86_64_EA,
1759   X86_64_0F01_REG_0,
1760   X86_64_0F01_REG_1,
1761   X86_64_0F01_REG_2,
1762   X86_64_0F01_REG_3
1763 };
1764
1765 enum
1766 {
1767   THREE_BYTE_0F38 = 0,
1768   THREE_BYTE_0F3A
1769 };
1770
1771 enum
1772 {
1773   XOP_08 = 0,
1774   XOP_09,
1775   XOP_0A
1776 };
1777
1778 enum
1779 {
1780   VEX_0F = 0,
1781   VEX_0F38,
1782   VEX_0F3A
1783 };
1784
1785 enum
1786 {
1787   EVEX_0F = 0,
1788   EVEX_0F38,
1789   EVEX_0F3A
1790 };
1791
1792 enum
1793 {
1794   VEX_LEN_0F10_P_1 = 0,
1795   VEX_LEN_0F10_P_3,
1796   VEX_LEN_0F11_P_1,
1797   VEX_LEN_0F11_P_3,
1798   VEX_LEN_0F12_P_0_M_0,
1799   VEX_LEN_0F12_P_0_M_1,
1800   VEX_LEN_0F12_P_2,
1801   VEX_LEN_0F13_M_0,
1802   VEX_LEN_0F16_P_0_M_0,
1803   VEX_LEN_0F16_P_0_M_1,
1804   VEX_LEN_0F16_P_2,
1805   VEX_LEN_0F17_M_0,
1806   VEX_LEN_0F2A_P_1,
1807   VEX_LEN_0F2A_P_3,
1808   VEX_LEN_0F2C_P_1,
1809   VEX_LEN_0F2C_P_3,
1810   VEX_LEN_0F2D_P_1,
1811   VEX_LEN_0F2D_P_3,
1812   VEX_LEN_0F2E_P_0,
1813   VEX_LEN_0F2E_P_2,
1814   VEX_LEN_0F2F_P_0,
1815   VEX_LEN_0F2F_P_2,
1816   VEX_LEN_0F41_P_0,
1817   VEX_LEN_0F41_P_2,
1818   VEX_LEN_0F42_P_0,
1819   VEX_LEN_0F42_P_2,
1820   VEX_LEN_0F44_P_0,
1821   VEX_LEN_0F44_P_2,
1822   VEX_LEN_0F45_P_0,
1823   VEX_LEN_0F45_P_2,
1824   VEX_LEN_0F46_P_0,
1825   VEX_LEN_0F46_P_2,
1826   VEX_LEN_0F47_P_0,
1827   VEX_LEN_0F47_P_2,
1828   VEX_LEN_0F4A_P_0,
1829   VEX_LEN_0F4A_P_2,
1830   VEX_LEN_0F4B_P_0,
1831   VEX_LEN_0F4B_P_2,
1832   VEX_LEN_0F51_P_1,
1833   VEX_LEN_0F51_P_3,
1834   VEX_LEN_0F52_P_1,
1835   VEX_LEN_0F53_P_1,
1836   VEX_LEN_0F58_P_1,
1837   VEX_LEN_0F58_P_3,
1838   VEX_LEN_0F59_P_1,
1839   VEX_LEN_0F59_P_3,
1840   VEX_LEN_0F5A_P_1,
1841   VEX_LEN_0F5A_P_3,
1842   VEX_LEN_0F5C_P_1,
1843   VEX_LEN_0F5C_P_3,
1844   VEX_LEN_0F5D_P_1,
1845   VEX_LEN_0F5D_P_3,
1846   VEX_LEN_0F5E_P_1,
1847   VEX_LEN_0F5E_P_3,
1848   VEX_LEN_0F5F_P_1,
1849   VEX_LEN_0F5F_P_3,
1850   VEX_LEN_0F6E_P_2,
1851   VEX_LEN_0F7E_P_1,
1852   VEX_LEN_0F7E_P_2,
1853   VEX_LEN_0F90_P_0,
1854   VEX_LEN_0F90_P_2,
1855   VEX_LEN_0F91_P_0,
1856   VEX_LEN_0F91_P_2,
1857   VEX_LEN_0F92_P_0,
1858   VEX_LEN_0F92_P_2,
1859   VEX_LEN_0F92_P_3,
1860   VEX_LEN_0F93_P_0,
1861   VEX_LEN_0F93_P_2,
1862   VEX_LEN_0F93_P_3,
1863   VEX_LEN_0F98_P_0,
1864   VEX_LEN_0F98_P_2,
1865   VEX_LEN_0F99_P_0,
1866   VEX_LEN_0F99_P_2,
1867   VEX_LEN_0FAE_R_2_M_0,
1868   VEX_LEN_0FAE_R_3_M_0,
1869   VEX_LEN_0FC2_P_1,
1870   VEX_LEN_0FC2_P_3,
1871   VEX_LEN_0FC4_P_2,
1872   VEX_LEN_0FC5_P_2,
1873   VEX_LEN_0FD6_P_2,
1874   VEX_LEN_0FF7_P_2,
1875   VEX_LEN_0F3816_P_2,
1876   VEX_LEN_0F3819_P_2,
1877   VEX_LEN_0F381A_P_2_M_0,
1878   VEX_LEN_0F3836_P_2,
1879   VEX_LEN_0F3841_P_2,
1880   VEX_LEN_0F385A_P_2_M_0,
1881   VEX_LEN_0F38DB_P_2,
1882   VEX_LEN_0F38F2_P_0,
1883   VEX_LEN_0F38F3_R_1_P_0,
1884   VEX_LEN_0F38F3_R_2_P_0,
1885   VEX_LEN_0F38F3_R_3_P_0,
1886   VEX_LEN_0F38F5_P_0,
1887   VEX_LEN_0F38F5_P_1,
1888   VEX_LEN_0F38F5_P_3,
1889   VEX_LEN_0F38F6_P_3,
1890   VEX_LEN_0F38F7_P_0,
1891   VEX_LEN_0F38F7_P_1,
1892   VEX_LEN_0F38F7_P_2,
1893   VEX_LEN_0F38F7_P_3,
1894   VEX_LEN_0F3A00_P_2,
1895   VEX_LEN_0F3A01_P_2,
1896   VEX_LEN_0F3A06_P_2,
1897   VEX_LEN_0F3A0A_P_2,
1898   VEX_LEN_0F3A0B_P_2,
1899   VEX_LEN_0F3A14_P_2,
1900   VEX_LEN_0F3A15_P_2,
1901   VEX_LEN_0F3A16_P_2,
1902   VEX_LEN_0F3A17_P_2,
1903   VEX_LEN_0F3A18_P_2,
1904   VEX_LEN_0F3A19_P_2,
1905   VEX_LEN_0F3A20_P_2,
1906   VEX_LEN_0F3A21_P_2,
1907   VEX_LEN_0F3A22_P_2,
1908   VEX_LEN_0F3A30_P_2,
1909   VEX_LEN_0F3A31_P_2,
1910   VEX_LEN_0F3A32_P_2,
1911   VEX_LEN_0F3A33_P_2,
1912   VEX_LEN_0F3A38_P_2,
1913   VEX_LEN_0F3A39_P_2,
1914   VEX_LEN_0F3A41_P_2,
1915   VEX_LEN_0F3A46_P_2,
1916   VEX_LEN_0F3A60_P_2,
1917   VEX_LEN_0F3A61_P_2,
1918   VEX_LEN_0F3A62_P_2,
1919   VEX_LEN_0F3A63_P_2,
1920   VEX_LEN_0F3A6A_P_2,
1921   VEX_LEN_0F3A6B_P_2,
1922   VEX_LEN_0F3A6E_P_2,
1923   VEX_LEN_0F3A6F_P_2,
1924   VEX_LEN_0F3A7A_P_2,
1925   VEX_LEN_0F3A7B_P_2,
1926   VEX_LEN_0F3A7E_P_2,
1927   VEX_LEN_0F3A7F_P_2,
1928   VEX_LEN_0F3ADF_P_2,
1929   VEX_LEN_0F3AF0_P_3,
1930   VEX_LEN_0FXOP_08_CC,
1931   VEX_LEN_0FXOP_08_CD,
1932   VEX_LEN_0FXOP_08_CE,
1933   VEX_LEN_0FXOP_08_CF,
1934   VEX_LEN_0FXOP_08_EC,
1935   VEX_LEN_0FXOP_08_ED,
1936   VEX_LEN_0FXOP_08_EE,
1937   VEX_LEN_0FXOP_08_EF,
1938   VEX_LEN_0FXOP_09_80,
1939   VEX_LEN_0FXOP_09_81
1940 };
1941
1942 enum
1943 {
1944   VEX_W_0F10_P_0 = 0,
1945   VEX_W_0F10_P_1,
1946   VEX_W_0F10_P_2,
1947   VEX_W_0F10_P_3,
1948   VEX_W_0F11_P_0,
1949   VEX_W_0F11_P_1,
1950   VEX_W_0F11_P_2,
1951   VEX_W_0F11_P_3,
1952   VEX_W_0F12_P_0_M_0,
1953   VEX_W_0F12_P_0_M_1,
1954   VEX_W_0F12_P_1,
1955   VEX_W_0F12_P_2,
1956   VEX_W_0F12_P_3,
1957   VEX_W_0F13_M_0,
1958   VEX_W_0F14,
1959   VEX_W_0F15,
1960   VEX_W_0F16_P_0_M_0,
1961   VEX_W_0F16_P_0_M_1,
1962   VEX_W_0F16_P_1,
1963   VEX_W_0F16_P_2,
1964   VEX_W_0F17_M_0,
1965   VEX_W_0F28,
1966   VEX_W_0F29,
1967   VEX_W_0F2B_M_0,
1968   VEX_W_0F2E_P_0,
1969   VEX_W_0F2E_P_2,
1970   VEX_W_0F2F_P_0,
1971   VEX_W_0F2F_P_2,
1972   VEX_W_0F41_P_0_LEN_1,
1973   VEX_W_0F41_P_2_LEN_1,
1974   VEX_W_0F42_P_0_LEN_1,
1975   VEX_W_0F42_P_2_LEN_1,
1976   VEX_W_0F44_P_0_LEN_0,
1977   VEX_W_0F44_P_2_LEN_0,
1978   VEX_W_0F45_P_0_LEN_1,
1979   VEX_W_0F45_P_2_LEN_1,
1980   VEX_W_0F46_P_0_LEN_1,
1981   VEX_W_0F46_P_2_LEN_1,
1982   VEX_W_0F47_P_0_LEN_1,
1983   VEX_W_0F47_P_2_LEN_1,
1984   VEX_W_0F4A_P_0_LEN_1,
1985   VEX_W_0F4A_P_2_LEN_1,
1986   VEX_W_0F4B_P_0_LEN_1,
1987   VEX_W_0F4B_P_2_LEN_1,
1988   VEX_W_0F50_M_0,
1989   VEX_W_0F51_P_0,
1990   VEX_W_0F51_P_1,
1991   VEX_W_0F51_P_2,
1992   VEX_W_0F51_P_3,
1993   VEX_W_0F52_P_0,
1994   VEX_W_0F52_P_1,
1995   VEX_W_0F53_P_0,
1996   VEX_W_0F53_P_1,
1997   VEX_W_0F58_P_0,
1998   VEX_W_0F58_P_1,
1999   VEX_W_0F58_P_2,
2000   VEX_W_0F58_P_3,
2001   VEX_W_0F59_P_0,
2002   VEX_W_0F59_P_1,
2003   VEX_W_0F59_P_2,
2004   VEX_W_0F59_P_3,
2005   VEX_W_0F5A_P_0,
2006   VEX_W_0F5A_P_1,
2007   VEX_W_0F5A_P_3,
2008   VEX_W_0F5B_P_0,
2009   VEX_W_0F5B_P_1,
2010   VEX_W_0F5B_P_2,
2011   VEX_W_0F5C_P_0,
2012   VEX_W_0F5C_P_1,
2013   VEX_W_0F5C_P_2,
2014   VEX_W_0F5C_P_3,
2015   VEX_W_0F5D_P_0,
2016   VEX_W_0F5D_P_1,
2017   VEX_W_0F5D_P_2,
2018   VEX_W_0F5D_P_3,
2019   VEX_W_0F5E_P_0,
2020   VEX_W_0F5E_P_1,
2021   VEX_W_0F5E_P_2,
2022   VEX_W_0F5E_P_3,
2023   VEX_W_0F5F_P_0,
2024   VEX_W_0F5F_P_1,
2025   VEX_W_0F5F_P_2,
2026   VEX_W_0F5F_P_3,
2027   VEX_W_0F60_P_2,
2028   VEX_W_0F61_P_2,
2029   VEX_W_0F62_P_2,
2030   VEX_W_0F63_P_2,
2031   VEX_W_0F64_P_2,
2032   VEX_W_0F65_P_2,
2033   VEX_W_0F66_P_2,
2034   VEX_W_0F67_P_2,
2035   VEX_W_0F68_P_2,
2036   VEX_W_0F69_P_2,
2037   VEX_W_0F6A_P_2,
2038   VEX_W_0F6B_P_2,
2039   VEX_W_0F6C_P_2,
2040   VEX_W_0F6D_P_2,
2041   VEX_W_0F6F_P_1,
2042   VEX_W_0F6F_P_2,
2043   VEX_W_0F70_P_1,
2044   VEX_W_0F70_P_2,
2045   VEX_W_0F70_P_3,
2046   VEX_W_0F71_R_2_P_2,
2047   VEX_W_0F71_R_4_P_2,
2048   VEX_W_0F71_R_6_P_2,
2049   VEX_W_0F72_R_2_P_2,
2050   VEX_W_0F72_R_4_P_2,
2051   VEX_W_0F72_R_6_P_2,
2052   VEX_W_0F73_R_2_P_2,
2053   VEX_W_0F73_R_3_P_2,
2054   VEX_W_0F73_R_6_P_2,
2055   VEX_W_0F73_R_7_P_2,
2056   VEX_W_0F74_P_2,
2057   VEX_W_0F75_P_2,
2058   VEX_W_0F76_P_2,
2059   VEX_W_0F77_P_0,
2060   VEX_W_0F7C_P_2,
2061   VEX_W_0F7C_P_3,
2062   VEX_W_0F7D_P_2,
2063   VEX_W_0F7D_P_3,
2064   VEX_W_0F7E_P_1,
2065   VEX_W_0F7F_P_1,
2066   VEX_W_0F7F_P_2,
2067   VEX_W_0F90_P_0_LEN_0,
2068   VEX_W_0F90_P_2_LEN_0,
2069   VEX_W_0F91_P_0_LEN_0,
2070   VEX_W_0F91_P_2_LEN_0,
2071   VEX_W_0F92_P_0_LEN_0,
2072   VEX_W_0F92_P_2_LEN_0,
2073   VEX_W_0F92_P_3_LEN_0,
2074   VEX_W_0F93_P_0_LEN_0,
2075   VEX_W_0F93_P_2_LEN_0,
2076   VEX_W_0F93_P_3_LEN_0,
2077   VEX_W_0F98_P_0_LEN_0,
2078   VEX_W_0F98_P_2_LEN_0,
2079   VEX_W_0F99_P_0_LEN_0,
2080   VEX_W_0F99_P_2_LEN_0,
2081   VEX_W_0FAE_R_2_M_0,
2082   VEX_W_0FAE_R_3_M_0,
2083   VEX_W_0FC2_P_0,
2084   VEX_W_0FC2_P_1,
2085   VEX_W_0FC2_P_2,
2086   VEX_W_0FC2_P_3,
2087   VEX_W_0FC4_P_2,
2088   VEX_W_0FC5_P_2,
2089   VEX_W_0FD0_P_2,
2090   VEX_W_0FD0_P_3,
2091   VEX_W_0FD1_P_2,
2092   VEX_W_0FD2_P_2,
2093   VEX_W_0FD3_P_2,
2094   VEX_W_0FD4_P_2,
2095   VEX_W_0FD5_P_2,
2096   VEX_W_0FD6_P_2,
2097   VEX_W_0FD7_P_2_M_1,
2098   VEX_W_0FD8_P_2,
2099   VEX_W_0FD9_P_2,
2100   VEX_W_0FDA_P_2,
2101   VEX_W_0FDB_P_2,
2102   VEX_W_0FDC_P_2,
2103   VEX_W_0FDD_P_2,
2104   VEX_W_0FDE_P_2,
2105   VEX_W_0FDF_P_2,
2106   VEX_W_0FE0_P_2,
2107   VEX_W_0FE1_P_2,
2108   VEX_W_0FE2_P_2,
2109   VEX_W_0FE3_P_2,
2110   VEX_W_0FE4_P_2,
2111   VEX_W_0FE5_P_2,
2112   VEX_W_0FE6_P_1,
2113   VEX_W_0FE6_P_2,
2114   VEX_W_0FE6_P_3,
2115   VEX_W_0FE7_P_2_M_0,
2116   VEX_W_0FE8_P_2,
2117   VEX_W_0FE9_P_2,
2118   VEX_W_0FEA_P_2,
2119   VEX_W_0FEB_P_2,
2120   VEX_W_0FEC_P_2,
2121   VEX_W_0FED_P_2,
2122   VEX_W_0FEE_P_2,
2123   VEX_W_0FEF_P_2,
2124   VEX_W_0FF0_P_3_M_0,
2125   VEX_W_0FF1_P_2,
2126   VEX_W_0FF2_P_2,
2127   VEX_W_0FF3_P_2,
2128   VEX_W_0FF4_P_2,
2129   VEX_W_0FF5_P_2,
2130   VEX_W_0FF6_P_2,
2131   VEX_W_0FF7_P_2,
2132   VEX_W_0FF8_P_2,
2133   VEX_W_0FF9_P_2,
2134   VEX_W_0FFA_P_2,
2135   VEX_W_0FFB_P_2,
2136   VEX_W_0FFC_P_2,
2137   VEX_W_0FFD_P_2,
2138   VEX_W_0FFE_P_2,
2139   VEX_W_0F3800_P_2,
2140   VEX_W_0F3801_P_2,
2141   VEX_W_0F3802_P_2,
2142   VEX_W_0F3803_P_2,
2143   VEX_W_0F3804_P_2,
2144   VEX_W_0F3805_P_2,
2145   VEX_W_0F3806_P_2,
2146   VEX_W_0F3807_P_2,
2147   VEX_W_0F3808_P_2,
2148   VEX_W_0F3809_P_2,
2149   VEX_W_0F380A_P_2,
2150   VEX_W_0F380B_P_2,
2151   VEX_W_0F380C_P_2,
2152   VEX_W_0F380D_P_2,
2153   VEX_W_0F380E_P_2,
2154   VEX_W_0F380F_P_2,
2155   VEX_W_0F3816_P_2,
2156   VEX_W_0F3817_P_2,
2157   VEX_W_0F3818_P_2,
2158   VEX_W_0F3819_P_2,
2159   VEX_W_0F381A_P_2_M_0,
2160   VEX_W_0F381C_P_2,
2161   VEX_W_0F381D_P_2,
2162   VEX_W_0F381E_P_2,
2163   VEX_W_0F3820_P_2,
2164   VEX_W_0F3821_P_2,
2165   VEX_W_0F3822_P_2,
2166   VEX_W_0F3823_P_2,
2167   VEX_W_0F3824_P_2,
2168   VEX_W_0F3825_P_2,
2169   VEX_W_0F3828_P_2,
2170   VEX_W_0F3829_P_2,
2171   VEX_W_0F382A_P_2_M_0,
2172   VEX_W_0F382B_P_2,
2173   VEX_W_0F382C_P_2_M_0,
2174   VEX_W_0F382D_P_2_M_0,
2175   VEX_W_0F382E_P_2_M_0,
2176   VEX_W_0F382F_P_2_M_0,
2177   VEX_W_0F3830_P_2,
2178   VEX_W_0F3831_P_2,
2179   VEX_W_0F3832_P_2,
2180   VEX_W_0F3833_P_2,
2181   VEX_W_0F3834_P_2,
2182   VEX_W_0F3835_P_2,
2183   VEX_W_0F3836_P_2,
2184   VEX_W_0F3837_P_2,
2185   VEX_W_0F3838_P_2,
2186   VEX_W_0F3839_P_2,
2187   VEX_W_0F383A_P_2,
2188   VEX_W_0F383B_P_2,
2189   VEX_W_0F383C_P_2,
2190   VEX_W_0F383D_P_2,
2191   VEX_W_0F383E_P_2,
2192   VEX_W_0F383F_P_2,
2193   VEX_W_0F3840_P_2,
2194   VEX_W_0F3841_P_2,
2195   VEX_W_0F3846_P_2,
2196   VEX_W_0F3858_P_2,
2197   VEX_W_0F3859_P_2,
2198   VEX_W_0F385A_P_2_M_0,
2199   VEX_W_0F3878_P_2,
2200   VEX_W_0F3879_P_2,
2201   VEX_W_0F38CF_P_2,
2202   VEX_W_0F38DB_P_2,
2203   VEX_W_0F3A00_P_2,
2204   VEX_W_0F3A01_P_2,
2205   VEX_W_0F3A02_P_2,
2206   VEX_W_0F3A04_P_2,
2207   VEX_W_0F3A05_P_2,
2208   VEX_W_0F3A06_P_2,
2209   VEX_W_0F3A08_P_2,
2210   VEX_W_0F3A09_P_2,
2211   VEX_W_0F3A0A_P_2,
2212   VEX_W_0F3A0B_P_2,
2213   VEX_W_0F3A0C_P_2,
2214   VEX_W_0F3A0D_P_2,
2215   VEX_W_0F3A0E_P_2,
2216   VEX_W_0F3A0F_P_2,
2217   VEX_W_0F3A14_P_2,
2218   VEX_W_0F3A15_P_2,
2219   VEX_W_0F3A18_P_2,
2220   VEX_W_0F3A19_P_2,
2221   VEX_W_0F3A20_P_2,
2222   VEX_W_0F3A21_P_2,
2223   VEX_W_0F3A30_P_2_LEN_0,
2224   VEX_W_0F3A31_P_2_LEN_0,
2225   VEX_W_0F3A32_P_2_LEN_0,
2226   VEX_W_0F3A33_P_2_LEN_0,
2227   VEX_W_0F3A38_P_2,
2228   VEX_W_0F3A39_P_2,
2229   VEX_W_0F3A40_P_2,
2230   VEX_W_0F3A41_P_2,
2231   VEX_W_0F3A42_P_2,
2232   VEX_W_0F3A46_P_2,
2233   VEX_W_0F3A48_P_2,
2234   VEX_W_0F3A49_P_2,
2235   VEX_W_0F3A4A_P_2,
2236   VEX_W_0F3A4B_P_2,
2237   VEX_W_0F3A4C_P_2,
2238   VEX_W_0F3A62_P_2,
2239   VEX_W_0F3A63_P_2,
2240   VEX_W_0F3ACE_P_2,
2241   VEX_W_0F3ACF_P_2,
2242   VEX_W_0F3ADF_P_2,
2243
2244   EVEX_W_0F10_P_0,
2245   EVEX_W_0F10_P_1_M_0,
2246   EVEX_W_0F10_P_1_M_1,
2247   EVEX_W_0F10_P_2,
2248   EVEX_W_0F10_P_3_M_0,
2249   EVEX_W_0F10_P_3_M_1,
2250   EVEX_W_0F11_P_0,
2251   EVEX_W_0F11_P_1_M_0,
2252   EVEX_W_0F11_P_1_M_1,
2253   EVEX_W_0F11_P_2,
2254   EVEX_W_0F11_P_3_M_0,
2255   EVEX_W_0F11_P_3_M_1,
2256   EVEX_W_0F12_P_0_M_0,
2257   EVEX_W_0F12_P_0_M_1,
2258   EVEX_W_0F12_P_1,
2259   EVEX_W_0F12_P_2,
2260   EVEX_W_0F12_P_3,
2261   EVEX_W_0F13_P_0,
2262   EVEX_W_0F13_P_2,
2263   EVEX_W_0F14_P_0,
2264   EVEX_W_0F14_P_2,
2265   EVEX_W_0F15_P_0,
2266   EVEX_W_0F15_P_2,
2267   EVEX_W_0F16_P_0_M_0,
2268   EVEX_W_0F16_P_0_M_1,
2269   EVEX_W_0F16_P_1,
2270   EVEX_W_0F16_P_2,
2271   EVEX_W_0F17_P_0,
2272   EVEX_W_0F17_P_2,
2273   EVEX_W_0F28_P_0,
2274   EVEX_W_0F28_P_2,
2275   EVEX_W_0F29_P_0,
2276   EVEX_W_0F29_P_2,
2277   EVEX_W_0F2A_P_1,
2278   EVEX_W_0F2A_P_3,
2279   EVEX_W_0F2B_P_0,
2280   EVEX_W_0F2B_P_2,
2281   EVEX_W_0F2E_P_0,
2282   EVEX_W_0F2E_P_2,
2283   EVEX_W_0F2F_P_0,
2284   EVEX_W_0F2F_P_2,
2285   EVEX_W_0F51_P_0,
2286   EVEX_W_0F51_P_1,
2287   EVEX_W_0F51_P_2,
2288   EVEX_W_0F51_P_3,
2289   EVEX_W_0F54_P_0,
2290   EVEX_W_0F54_P_2,
2291   EVEX_W_0F55_P_0,
2292   EVEX_W_0F55_P_2,
2293   EVEX_W_0F56_P_0,
2294   EVEX_W_0F56_P_2,
2295   EVEX_W_0F57_P_0,
2296   EVEX_W_0F57_P_2,
2297   EVEX_W_0F58_P_0,
2298   EVEX_W_0F58_P_1,
2299   EVEX_W_0F58_P_2,
2300   EVEX_W_0F58_P_3,
2301   EVEX_W_0F59_P_0,
2302   EVEX_W_0F59_P_1,
2303   EVEX_W_0F59_P_2,
2304   EVEX_W_0F59_P_3,
2305   EVEX_W_0F5A_P_0,
2306   EVEX_W_0F5A_P_1,
2307   EVEX_W_0F5A_P_2,
2308   EVEX_W_0F5A_P_3,
2309   EVEX_W_0F5B_P_0,
2310   EVEX_W_0F5B_P_1,
2311   EVEX_W_0F5B_P_2,
2312   EVEX_W_0F5C_P_0,
2313   EVEX_W_0F5C_P_1,
2314   EVEX_W_0F5C_P_2,
2315   EVEX_W_0F5C_P_3,
2316   EVEX_W_0F5D_P_0,
2317   EVEX_W_0F5D_P_1,
2318   EVEX_W_0F5D_P_2,
2319   EVEX_W_0F5D_P_3,
2320   EVEX_W_0F5E_P_0,
2321   EVEX_W_0F5E_P_1,
2322   EVEX_W_0F5E_P_2,
2323   EVEX_W_0F5E_P_3,
2324   EVEX_W_0F5F_P_0,
2325   EVEX_W_0F5F_P_1,
2326   EVEX_W_0F5F_P_2,
2327   EVEX_W_0F5F_P_3,
2328   EVEX_W_0F62_P_2,
2329   EVEX_W_0F66_P_2,
2330   EVEX_W_0F6A_P_2,
2331   EVEX_W_0F6B_P_2,
2332   EVEX_W_0F6C_P_2,
2333   EVEX_W_0F6D_P_2,
2334   EVEX_W_0F6E_P_2,
2335   EVEX_W_0F6F_P_1,
2336   EVEX_W_0F6F_P_2,
2337   EVEX_W_0F6F_P_3,
2338   EVEX_W_0F70_P_2,
2339   EVEX_W_0F72_R_2_P_2,
2340   EVEX_W_0F72_R_6_P_2,
2341   EVEX_W_0F73_R_2_P_2,
2342   EVEX_W_0F73_R_6_P_2,
2343   EVEX_W_0F76_P_2,
2344   EVEX_W_0F78_P_0,
2345   EVEX_W_0F78_P_2,
2346   EVEX_W_0F79_P_0,
2347   EVEX_W_0F79_P_2,
2348   EVEX_W_0F7A_P_1,
2349   EVEX_W_0F7A_P_2,
2350   EVEX_W_0F7A_P_3,
2351   EVEX_W_0F7B_P_1,
2352   EVEX_W_0F7B_P_2,
2353   EVEX_W_0F7B_P_3,
2354   EVEX_W_0F7E_P_1,
2355   EVEX_W_0F7E_P_2,
2356   EVEX_W_0F7F_P_1,
2357   EVEX_W_0F7F_P_2,
2358   EVEX_W_0F7F_P_3,
2359   EVEX_W_0FC2_P_0,
2360   EVEX_W_0FC2_P_1,
2361   EVEX_W_0FC2_P_2,
2362   EVEX_W_0FC2_P_3,
2363   EVEX_W_0FC6_P_0,
2364   EVEX_W_0FC6_P_2,
2365   EVEX_W_0FD2_P_2,
2366   EVEX_W_0FD3_P_2,
2367   EVEX_W_0FD4_P_2,
2368   EVEX_W_0FD6_P_2,
2369   EVEX_W_0FE6_P_1,
2370   EVEX_W_0FE6_P_2,
2371   EVEX_W_0FE6_P_3,
2372   EVEX_W_0FE7_P_2,
2373   EVEX_W_0FF2_P_2,
2374   EVEX_W_0FF3_P_2,
2375   EVEX_W_0FF4_P_2,
2376   EVEX_W_0FFA_P_2,
2377   EVEX_W_0FFB_P_2,
2378   EVEX_W_0FFE_P_2,
2379   EVEX_W_0F380C_P_2,
2380   EVEX_W_0F380D_P_2,
2381   EVEX_W_0F3810_P_1,
2382   EVEX_W_0F3810_P_2,
2383   EVEX_W_0F3811_P_1,
2384   EVEX_W_0F3811_P_2,
2385   EVEX_W_0F3812_P_1,
2386   EVEX_W_0F3812_P_2,
2387   EVEX_W_0F3813_P_1,
2388   EVEX_W_0F3813_P_2,
2389   EVEX_W_0F3814_P_1,
2390   EVEX_W_0F3815_P_1,
2391   EVEX_W_0F3818_P_2,
2392   EVEX_W_0F3819_P_2,
2393   EVEX_W_0F381A_P_2,
2394   EVEX_W_0F381B_P_2,
2395   EVEX_W_0F381E_P_2,
2396   EVEX_W_0F381F_P_2,
2397   EVEX_W_0F3820_P_1,
2398   EVEX_W_0F3821_P_1,
2399   EVEX_W_0F3822_P_1,
2400   EVEX_W_0F3823_P_1,
2401   EVEX_W_0F3824_P_1,
2402   EVEX_W_0F3825_P_1,
2403   EVEX_W_0F3825_P_2,
2404   EVEX_W_0F3826_P_1,
2405   EVEX_W_0F3826_P_2,
2406   EVEX_W_0F3828_P_1,
2407   EVEX_W_0F3828_P_2,
2408   EVEX_W_0F3829_P_1,
2409   EVEX_W_0F3829_P_2,
2410   EVEX_W_0F382A_P_1,
2411   EVEX_W_0F382A_P_2,
2412   EVEX_W_0F382B_P_2,
2413   EVEX_W_0F3830_P_1,
2414   EVEX_W_0F3831_P_1,
2415   EVEX_W_0F3832_P_1,
2416   EVEX_W_0F3833_P_1,
2417   EVEX_W_0F3834_P_1,
2418   EVEX_W_0F3835_P_1,
2419   EVEX_W_0F3835_P_2,
2420   EVEX_W_0F3837_P_2,
2421   EVEX_W_0F3838_P_1,
2422   EVEX_W_0F3839_P_1,
2423   EVEX_W_0F383A_P_1,
2424   EVEX_W_0F3840_P_2,
2425   EVEX_W_0F3854_P_2,
2426   EVEX_W_0F3855_P_2,
2427   EVEX_W_0F3858_P_2,
2428   EVEX_W_0F3859_P_2,
2429   EVEX_W_0F385A_P_2,
2430   EVEX_W_0F385B_P_2,
2431   EVEX_W_0F3862_P_2,
2432   EVEX_W_0F3863_P_2,
2433   EVEX_W_0F3866_P_2,
2434   EVEX_W_0F3870_P_2,
2435   EVEX_W_0F3871_P_2,
2436   EVEX_W_0F3872_P_2,
2437   EVEX_W_0F3873_P_2,
2438   EVEX_W_0F3875_P_2,
2439   EVEX_W_0F3878_P_2,
2440   EVEX_W_0F3879_P_2,
2441   EVEX_W_0F387A_P_2,
2442   EVEX_W_0F387B_P_2,
2443   EVEX_W_0F387D_P_2,
2444   EVEX_W_0F3883_P_2,
2445   EVEX_W_0F388D_P_2,
2446   EVEX_W_0F3891_P_2,
2447   EVEX_W_0F3893_P_2,
2448   EVEX_W_0F38A1_P_2,
2449   EVEX_W_0F38A3_P_2,
2450   EVEX_W_0F38C7_R_1_P_2,
2451   EVEX_W_0F38C7_R_2_P_2,
2452   EVEX_W_0F38C7_R_5_P_2,
2453   EVEX_W_0F38C7_R_6_P_2,
2454
2455   EVEX_W_0F3A00_P_2,
2456   EVEX_W_0F3A01_P_2,
2457   EVEX_W_0F3A04_P_2,
2458   EVEX_W_0F3A05_P_2,
2459   EVEX_W_0F3A08_P_2,
2460   EVEX_W_0F3A09_P_2,
2461   EVEX_W_0F3A0A_P_2,
2462   EVEX_W_0F3A0B_P_2,
2463   EVEX_W_0F3A16_P_2,
2464   EVEX_W_0F3A18_P_2,
2465   EVEX_W_0F3A19_P_2,
2466   EVEX_W_0F3A1A_P_2,
2467   EVEX_W_0F3A1B_P_2,
2468   EVEX_W_0F3A1D_P_2,
2469   EVEX_W_0F3A21_P_2,
2470   EVEX_W_0F3A22_P_2,
2471   EVEX_W_0F3A23_P_2,
2472   EVEX_W_0F3A38_P_2,
2473   EVEX_W_0F3A39_P_2,
2474   EVEX_W_0F3A3A_P_2,
2475   EVEX_W_0F3A3B_P_2,
2476   EVEX_W_0F3A3E_P_2,
2477   EVEX_W_0F3A3F_P_2,
2478   EVEX_W_0F3A42_P_2,
2479   EVEX_W_0F3A43_P_2,
2480   EVEX_W_0F3A50_P_2,
2481   EVEX_W_0F3A51_P_2,
2482   EVEX_W_0F3A56_P_2,
2483   EVEX_W_0F3A57_P_2,
2484   EVEX_W_0F3A66_P_2,
2485   EVEX_W_0F3A67_P_2,
2486   EVEX_W_0F3A70_P_2,
2487   EVEX_W_0F3A71_P_2,
2488   EVEX_W_0F3A72_P_2,
2489   EVEX_W_0F3A73_P_2,
2490   EVEX_W_0F3ACE_P_2,
2491   EVEX_W_0F3ACF_P_2
2492 };
2493
2494 typedef void (*op_rtn) (int bytemode, int sizeflag);
2495
2496 struct dis386 {
2497   const char *name;
2498   struct
2499     {
2500       op_rtn rtn;
2501       int bytemode;
2502     } op[MAX_OPERANDS];
2503   unsigned int prefix_requirement;
2504 };
2505
2506 /* Upper case letters in the instruction names here are macros.
2507    'A' => print 'b' if no register operands or suffix_always is true
2508    'B' => print 'b' if suffix_always is true
2509    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2510           size prefix
2511    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2512           suffix_always is true
2513    'E' => print 'e' if 32-bit form of jcxz
2514    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2515    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2516    'H' => print ",pt" or ",pn" branch hint
2517    'I' => honor following macro letter even in Intel mode (implemented only
2518           for some of the macro letters)
2519    'J' => print 'l'
2520    'K' => print 'd' or 'q' if rex prefix is present.
2521    'L' => print 'l' if suffix_always is true
2522    'M' => print 'r' if intel_mnemonic is false.
2523    'N' => print 'n' if instruction has no wait "prefix"
2524    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2525    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2526           or suffix_always is true.  print 'q' if rex prefix is present.
2527    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2528           is true
2529    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2530    'S' => print 'w', 'l' or 'q' if suffix_always is true
2531    'T' => print 'q' in 64bit mode if instruction has no operand size
2532           prefix and behave as 'P' otherwise
2533    'U' => print 'q' in 64bit mode if instruction has no operand size
2534           prefix and behave as 'Q' otherwise
2535    'V' => print 'q' in 64bit mode if instruction has no operand size
2536           prefix and behave as 'S' otherwise
2537    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2538    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2539    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2540           suffix_always is true.
2541    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2542    '!' => change condition from true to false or from false to true.
2543    '%' => add 1 upper case letter to the macro.
2544    '^' => print 'w' or 'l' depending on operand size prefix or
2545           suffix_always is true (lcall/ljmp).
2546    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2547           on operand size prefix.
2548    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2549           has no operand size prefix for AMD64 ISA, behave as 'P'
2550           otherwise
2551
2552    2 upper case letter macros:
2553    "XY" => print 'x' or 'y' if suffix_always is true or no register
2554            operands and no broadcast.
2555    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2556            register operands and no broadcast.
2557    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2558    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2559            or suffix_always is true
2560    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2561    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2562    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2563    "LW" => print 'd', 'q' depending on the VEX.W bit
2564    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2565            an operand size prefix, or suffix_always is true.  print
2566            'q' if rex prefix is present.
2567
2568    Many of the above letters print nothing in Intel mode.  See "putop"
2569    for the details.
2570
2571    Braces '{' and '}', and vertical bars '|', indicate alternative
2572    mnemonic strings for AT&T and Intel.  */
2573
2574 static const struct dis386 dis386[] = {
2575   /* 00 */
2576   { "addB",             { Ebh1, Gb }, 0 },
2577   { "addS",             { Evh1, Gv }, 0 },
2578   { "addB",             { Gb, EbS }, 0 },
2579   { "addS",             { Gv, EvS }, 0 },
2580   { "addB",             { AL, Ib }, 0 },
2581   { "addS",             { eAX, Iv }, 0 },
2582   { X86_64_TABLE (X86_64_06) },
2583   { X86_64_TABLE (X86_64_07) },
2584   /* 08 */
2585   { "orB",              { Ebh1, Gb }, 0 },
2586   { "orS",              { Evh1, Gv }, 0 },
2587   { "orB",              { Gb, EbS }, 0 },
2588   { "orS",              { Gv, EvS }, 0 },
2589   { "orB",              { AL, Ib }, 0 },
2590   { "orS",              { eAX, Iv }, 0 },
2591   { X86_64_TABLE (X86_64_0D) },
2592   { Bad_Opcode },       /* 0x0f extended opcode escape */
2593   /* 10 */
2594   { "adcB",             { Ebh1, Gb }, 0 },
2595   { "adcS",             { Evh1, Gv }, 0 },
2596   { "adcB",             { Gb, EbS }, 0 },
2597   { "adcS",             { Gv, EvS }, 0 },
2598   { "adcB",             { AL, Ib }, 0 },
2599   { "adcS",             { eAX, Iv }, 0 },
2600   { X86_64_TABLE (X86_64_16) },
2601   { X86_64_TABLE (X86_64_17) },
2602   /* 18 */
2603   { "sbbB",             { Ebh1, Gb }, 0 },
2604   { "sbbS",             { Evh1, Gv }, 0 },
2605   { "sbbB",             { Gb, EbS }, 0 },
2606   { "sbbS",             { Gv, EvS }, 0 },
2607   { "sbbB",             { AL, Ib }, 0 },
2608   { "sbbS",             { eAX, Iv }, 0 },
2609   { X86_64_TABLE (X86_64_1E) },
2610   { X86_64_TABLE (X86_64_1F) },
2611   /* 20 */
2612   { "andB",             { Ebh1, Gb }, 0 },
2613   { "andS",             { Evh1, Gv }, 0 },
2614   { "andB",             { Gb, EbS }, 0 },
2615   { "andS",             { Gv, EvS }, 0 },
2616   { "andB",             { AL, Ib }, 0 },
2617   { "andS",             { eAX, Iv }, 0 },
2618   { Bad_Opcode },       /* SEG ES prefix */
2619   { X86_64_TABLE (X86_64_27) },
2620   /* 28 */
2621   { "subB",             { Ebh1, Gb }, 0 },
2622   { "subS",             { Evh1, Gv }, 0 },
2623   { "subB",             { Gb, EbS }, 0 },
2624   { "subS",             { Gv, EvS }, 0 },
2625   { "subB",             { AL, Ib }, 0 },
2626   { "subS",             { eAX, Iv }, 0 },
2627   { Bad_Opcode },       /* SEG CS prefix */
2628   { X86_64_TABLE (X86_64_2F) },
2629   /* 30 */
2630   { "xorB",             { Ebh1, Gb }, 0 },
2631   { "xorS",             { Evh1, Gv }, 0 },
2632   { "xorB",             { Gb, EbS }, 0 },
2633   { "xorS",             { Gv, EvS }, 0 },
2634   { "xorB",             { AL, Ib }, 0 },
2635   { "xorS",             { eAX, Iv }, 0 },
2636   { Bad_Opcode },       /* SEG SS prefix */
2637   { X86_64_TABLE (X86_64_37) },
2638   /* 38 */
2639   { "cmpB",             { Eb, Gb }, 0 },
2640   { "cmpS",             { Ev, Gv }, 0 },
2641   { "cmpB",             { Gb, EbS }, 0 },
2642   { "cmpS",             { Gv, EvS }, 0 },
2643   { "cmpB",             { AL, Ib }, 0 },
2644   { "cmpS",             { eAX, Iv }, 0 },
2645   { Bad_Opcode },       /* SEG DS prefix */
2646   { X86_64_TABLE (X86_64_3F) },
2647   /* 40 */
2648   { "inc{S|}",          { RMeAX }, 0 },
2649   { "inc{S|}",          { RMeCX }, 0 },
2650   { "inc{S|}",          { RMeDX }, 0 },
2651   { "inc{S|}",          { RMeBX }, 0 },
2652   { "inc{S|}",          { RMeSP }, 0 },
2653   { "inc{S|}",          { RMeBP }, 0 },
2654   { "inc{S|}",          { RMeSI }, 0 },
2655   { "inc{S|}",          { RMeDI }, 0 },
2656   /* 48 */
2657   { "dec{S|}",          { RMeAX }, 0 },
2658   { "dec{S|}",          { RMeCX }, 0 },
2659   { "dec{S|}",          { RMeDX }, 0 },
2660   { "dec{S|}",          { RMeBX }, 0 },
2661   { "dec{S|}",          { RMeSP }, 0 },
2662   { "dec{S|}",          { RMeBP }, 0 },
2663   { "dec{S|}",          { RMeSI }, 0 },
2664   { "dec{S|}",          { RMeDI }, 0 },
2665   /* 50 */
2666   { "pushV",            { RMrAX }, 0 },
2667   { "pushV",            { RMrCX }, 0 },
2668   { "pushV",            { RMrDX }, 0 },
2669   { "pushV",            { RMrBX }, 0 },
2670   { "pushV",            { RMrSP }, 0 },
2671   { "pushV",            { RMrBP }, 0 },
2672   { "pushV",            { RMrSI }, 0 },
2673   { "pushV",            { RMrDI }, 0 },
2674   /* 58 */
2675   { "popV",             { RMrAX }, 0 },
2676   { "popV",             { RMrCX }, 0 },
2677   { "popV",             { RMrDX }, 0 },
2678   { "popV",             { RMrBX }, 0 },
2679   { "popV",             { RMrSP }, 0 },
2680   { "popV",             { RMrBP }, 0 },
2681   { "popV",             { RMrSI }, 0 },
2682   { "popV",             { RMrDI }, 0 },
2683   /* 60 */
2684   { X86_64_TABLE (X86_64_60) },
2685   { X86_64_TABLE (X86_64_61) },
2686   { X86_64_TABLE (X86_64_62) },
2687   { X86_64_TABLE (X86_64_63) },
2688   { Bad_Opcode },       /* seg fs */
2689   { Bad_Opcode },       /* seg gs */
2690   { Bad_Opcode },       /* op size prefix */
2691   { Bad_Opcode },       /* adr size prefix */
2692   /* 68 */
2693   { "pushT",            { sIv }, 0 },
2694   { "imulS",            { Gv, Ev, Iv }, 0 },
2695   { "pushT",            { sIbT }, 0 },
2696   { "imulS",            { Gv, Ev, sIb }, 0 },
2697   { "ins{b|}",          { Ybr, indirDX }, 0 },
2698   { X86_64_TABLE (X86_64_6D) },
2699   { "outs{b|}",         { indirDXr, Xb }, 0 },
2700   { X86_64_TABLE (X86_64_6F) },
2701   /* 70 */
2702   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2703   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2704   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2705   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2706   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2707   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2708   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2709   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2710   /* 78 */
2711   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2712   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2713   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2714   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2715   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2716   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2717   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2718   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2719   /* 80 */
2720   { REG_TABLE (REG_80) },
2721   { REG_TABLE (REG_81) },
2722   { X86_64_TABLE (X86_64_82) },
2723   { REG_TABLE (REG_83) },
2724   { "testB",            { Eb, Gb }, 0 },
2725   { "testS",            { Ev, Gv }, 0 },
2726   { "xchgB",            { Ebh2, Gb }, 0 },
2727   { "xchgS",            { Evh2, Gv }, 0 },
2728   /* 88 */
2729   { "movB",             { Ebh3, Gb }, 0 },
2730   { "movS",             { Evh3, Gv }, 0 },
2731   { "movB",             { Gb, EbS }, 0 },
2732   { "movS",             { Gv, EvS }, 0 },
2733   { "movD",             { Sv, Sw }, 0 },
2734   { MOD_TABLE (MOD_8D) },
2735   { "movD",             { Sw, Sv }, 0 },
2736   { REG_TABLE (REG_8F) },
2737   /* 90 */
2738   { PREFIX_TABLE (PREFIX_90) },
2739   { "xchgS",            { RMeCX, eAX }, 0 },
2740   { "xchgS",            { RMeDX, eAX }, 0 },
2741   { "xchgS",            { RMeBX, eAX }, 0 },
2742   { "xchgS",            { RMeSP, eAX }, 0 },
2743   { "xchgS",            { RMeBP, eAX }, 0 },
2744   { "xchgS",            { RMeSI, eAX }, 0 },
2745   { "xchgS",            { RMeDI, eAX }, 0 },
2746   /* 98 */
2747   { "cW{t|}R",          { XX }, 0 },
2748   { "cR{t|}O",          { XX }, 0 },
2749   { X86_64_TABLE (X86_64_9A) },
2750   { Bad_Opcode },       /* fwait */
2751   { "pushfT",           { XX }, 0 },
2752   { "popfT",            { XX }, 0 },
2753   { "sahf",             { XX }, 0 },
2754   { "lahf",             { XX }, 0 },
2755   /* a0 */
2756   { "mov%LB",           { AL, Ob }, 0 },
2757   { "mov%LS",           { eAX, Ov }, 0 },
2758   { "mov%LB",           { Ob, AL }, 0 },
2759   { "mov%LS",           { Ov, eAX }, 0 },
2760   { "movs{b|}",         { Ybr, Xb }, 0 },
2761   { "movs{R|}",         { Yvr, Xv }, 0 },
2762   { "cmps{b|}",         { Xb, Yb }, 0 },
2763   { "cmps{R|}",         { Xv, Yv }, 0 },
2764   /* a8 */
2765   { "testB",            { AL, Ib }, 0 },
2766   { "testS",            { eAX, Iv }, 0 },
2767   { "stosB",            { Ybr, AL }, 0 },
2768   { "stosS",            { Yvr, eAX }, 0 },
2769   { "lodsB",            { ALr, Xb }, 0 },
2770   { "lodsS",            { eAXr, Xv }, 0 },
2771   { "scasB",            { AL, Yb }, 0 },
2772   { "scasS",            { eAX, Yv }, 0 },
2773   /* b0 */
2774   { "movB",             { RMAL, Ib }, 0 },
2775   { "movB",             { RMCL, Ib }, 0 },
2776   { "movB",             { RMDL, Ib }, 0 },
2777   { "movB",             { RMBL, Ib }, 0 },
2778   { "movB",             { RMAH, Ib }, 0 },
2779   { "movB",             { RMCH, Ib }, 0 },
2780   { "movB",             { RMDH, Ib }, 0 },
2781   { "movB",             { RMBH, Ib }, 0 },
2782   /* b8 */
2783   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2784   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2785   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2786   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2787   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2788   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2789   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2790   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2791   /* c0 */
2792   { REG_TABLE (REG_C0) },
2793   { REG_TABLE (REG_C1) },
2794   { "retT",             { Iw, BND }, 0 },
2795   { "retT",             { BND }, 0 },
2796   { X86_64_TABLE (X86_64_C4) },
2797   { X86_64_TABLE (X86_64_C5) },
2798   { REG_TABLE (REG_C6) },
2799   { REG_TABLE (REG_C7) },
2800   /* c8 */
2801   { "enterT",           { Iw, Ib }, 0 },
2802   { "leaveT",           { XX }, 0 },
2803   { "Jret{|f}P",        { Iw }, 0 },
2804   { "Jret{|f}P",        { XX }, 0 },
2805   { "int3",             { XX }, 0 },
2806   { "int",              { Ib }, 0 },
2807   { X86_64_TABLE (X86_64_CE) },
2808   { "iret%LP",          { XX }, 0 },
2809   /* d0 */
2810   { REG_TABLE (REG_D0) },
2811   { REG_TABLE (REG_D1) },
2812   { REG_TABLE (REG_D2) },
2813   { REG_TABLE (REG_D3) },
2814   { X86_64_TABLE (X86_64_D4) },
2815   { X86_64_TABLE (X86_64_D5) },
2816   { Bad_Opcode },
2817   { "xlat",             { DSBX }, 0 },
2818   /* d8 */
2819   { FLOAT },
2820   { FLOAT },
2821   { FLOAT },
2822   { FLOAT },
2823   { FLOAT },
2824   { FLOAT },
2825   { FLOAT },
2826   { FLOAT },
2827   /* e0 */
2828   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2829   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2830   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2831   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2832   { "inB",              { AL, Ib }, 0 },
2833   { "inG",              { zAX, Ib }, 0 },
2834   { "outB",             { Ib, AL }, 0 },
2835   { "outG",             { Ib, zAX }, 0 },
2836   /* e8 */
2837   { X86_64_TABLE (X86_64_E8) },
2838   { X86_64_TABLE (X86_64_E9) },
2839   { X86_64_TABLE (X86_64_EA) },
2840   { "jmp",              { Jb, BND }, 0 },
2841   { "inB",              { AL, indirDX }, 0 },
2842   { "inG",              { zAX, indirDX }, 0 },
2843   { "outB",             { indirDX, AL }, 0 },
2844   { "outG",             { indirDX, zAX }, 0 },
2845   /* f0 */
2846   { Bad_Opcode },       /* lock prefix */
2847   { "icebp",            { XX }, 0 },
2848   { Bad_Opcode },       /* repne */
2849   { Bad_Opcode },       /* repz */
2850   { "hlt",              { XX }, 0 },
2851   { "cmc",              { XX }, 0 },
2852   { REG_TABLE (REG_F6) },
2853   { REG_TABLE (REG_F7) },
2854   /* f8 */
2855   { "clc",              { XX }, 0 },
2856   { "stc",              { XX }, 0 },
2857   { "cli",              { XX }, 0 },
2858   { "sti",              { XX }, 0 },
2859   { "cld",              { XX }, 0 },
2860   { "std",              { XX }, 0 },
2861   { REG_TABLE (REG_FE) },
2862   { REG_TABLE (REG_FF) },
2863 };
2864
2865 static const struct dis386 dis386_twobyte[] = {
2866   /* 00 */
2867   { REG_TABLE (REG_0F00 ) },
2868   { REG_TABLE (REG_0F01 ) },
2869   { "larS",             { Gv, Ew }, 0 },
2870   { "lslS",             { Gv, Ew }, 0 },
2871   { Bad_Opcode },
2872   { "syscall",          { XX }, 0 },
2873   { "clts",             { XX }, 0 },
2874   { "sysret%LP",                { XX }, 0 },
2875   /* 08 */
2876   { "invd",             { XX }, 0 },
2877   { PREFIX_TABLE (PREFIX_0F09) },
2878   { Bad_Opcode },
2879   { "ud2",              { XX }, 0 },
2880   { Bad_Opcode },
2881   { REG_TABLE (REG_0F0D) },
2882   { "femms",            { XX }, 0 },
2883   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2884   /* 10 */
2885   { PREFIX_TABLE (PREFIX_0F10) },
2886   { PREFIX_TABLE (PREFIX_0F11) },
2887   { PREFIX_TABLE (PREFIX_0F12) },
2888   { MOD_TABLE (MOD_0F13) },
2889   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2890   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2891   { PREFIX_TABLE (PREFIX_0F16) },
2892   { MOD_TABLE (MOD_0F17) },
2893   /* 18 */
2894   { REG_TABLE (REG_0F18) },
2895   { "nopQ",             { Ev }, 0 },
2896   { PREFIX_TABLE (PREFIX_0F1A) },
2897   { PREFIX_TABLE (PREFIX_0F1B) },
2898   { "nopQ",             { Ev }, 0 },
2899   { "nopQ",             { Ev }, 0 },
2900   { PREFIX_TABLE (PREFIX_0F1E) },
2901   { "nopQ",             { Ev }, 0 },
2902   /* 20 */
2903   { "movZ",             { Rm, Cm }, 0 },
2904   { "movZ",             { Rm, Dm }, 0 },
2905   { "movZ",             { Cm, Rm }, 0 },
2906   { "movZ",             { Dm, Rm }, 0 },
2907   { MOD_TABLE (MOD_0F24) },
2908   { Bad_Opcode },
2909   { MOD_TABLE (MOD_0F26) },
2910   { Bad_Opcode },
2911   /* 28 */
2912   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2913   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2914   { PREFIX_TABLE (PREFIX_0F2A) },
2915   { PREFIX_TABLE (PREFIX_0F2B) },
2916   { PREFIX_TABLE (PREFIX_0F2C) },
2917   { PREFIX_TABLE (PREFIX_0F2D) },
2918   { PREFIX_TABLE (PREFIX_0F2E) },
2919   { PREFIX_TABLE (PREFIX_0F2F) },
2920   /* 30 */
2921   { "wrmsr",            { XX }, 0 },
2922   { "rdtsc",            { XX }, 0 },
2923   { "rdmsr",            { XX }, 0 },
2924   { "rdpmc",            { XX }, 0 },
2925   { "sysenter",         { XX }, 0 },
2926   { "sysexit",          { XX }, 0 },
2927   { Bad_Opcode },
2928   { "getsec",           { XX }, 0 },
2929   /* 38 */
2930   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2931   { Bad_Opcode },
2932   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2933   { Bad_Opcode },
2934   { Bad_Opcode },
2935   { Bad_Opcode },
2936   { Bad_Opcode },
2937   { Bad_Opcode },
2938   /* 40 */
2939   { "cmovoS",           { Gv, Ev }, 0 },
2940   { "cmovnoS",          { Gv, Ev }, 0 },
2941   { "cmovbS",           { Gv, Ev }, 0 },
2942   { "cmovaeS",          { Gv, Ev }, 0 },
2943   { "cmoveS",           { Gv, Ev }, 0 },
2944   { "cmovneS",          { Gv, Ev }, 0 },
2945   { "cmovbeS",          { Gv, Ev }, 0 },
2946   { "cmovaS",           { Gv, Ev }, 0 },
2947   /* 48 */
2948   { "cmovsS",           { Gv, Ev }, 0 },
2949   { "cmovnsS",          { Gv, Ev }, 0 },
2950   { "cmovpS",           { Gv, Ev }, 0 },
2951   { "cmovnpS",          { Gv, Ev }, 0 },
2952   { "cmovlS",           { Gv, Ev }, 0 },
2953   { "cmovgeS",          { Gv, Ev }, 0 },
2954   { "cmovleS",          { Gv, Ev }, 0 },
2955   { "cmovgS",           { Gv, Ev }, 0 },
2956   /* 50 */
2957   { MOD_TABLE (MOD_0F51) },
2958   { PREFIX_TABLE (PREFIX_0F51) },
2959   { PREFIX_TABLE (PREFIX_0F52) },
2960   { PREFIX_TABLE (PREFIX_0F53) },
2961   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2962   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2963   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2964   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2965   /* 58 */
2966   { PREFIX_TABLE (PREFIX_0F58) },
2967   { PREFIX_TABLE (PREFIX_0F59) },
2968   { PREFIX_TABLE (PREFIX_0F5A) },
2969   { PREFIX_TABLE (PREFIX_0F5B) },
2970   { PREFIX_TABLE (PREFIX_0F5C) },
2971   { PREFIX_TABLE (PREFIX_0F5D) },
2972   { PREFIX_TABLE (PREFIX_0F5E) },
2973   { PREFIX_TABLE (PREFIX_0F5F) },
2974   /* 60 */
2975   { PREFIX_TABLE (PREFIX_0F60) },
2976   { PREFIX_TABLE (PREFIX_0F61) },
2977   { PREFIX_TABLE (PREFIX_0F62) },
2978   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2979   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2980   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2981   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2982   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2983   /* 68 */
2984   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2985   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2986   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2987   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2988   { PREFIX_TABLE (PREFIX_0F6C) },
2989   { PREFIX_TABLE (PREFIX_0F6D) },
2990   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2991   { PREFIX_TABLE (PREFIX_0F6F) },
2992   /* 70 */
2993   { PREFIX_TABLE (PREFIX_0F70) },
2994   { REG_TABLE (REG_0F71) },
2995   { REG_TABLE (REG_0F72) },
2996   { REG_TABLE (REG_0F73) },
2997   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2998   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2999   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
3000   { "emms",             { XX }, PREFIX_OPCODE },
3001   /* 78 */
3002   { PREFIX_TABLE (PREFIX_0F78) },
3003   { PREFIX_TABLE (PREFIX_0F79) },
3004   { Bad_Opcode },
3005   { Bad_Opcode },
3006   { PREFIX_TABLE (PREFIX_0F7C) },
3007   { PREFIX_TABLE (PREFIX_0F7D) },
3008   { PREFIX_TABLE (PREFIX_0F7E) },
3009   { PREFIX_TABLE (PREFIX_0F7F) },
3010   /* 80 */
3011   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3012   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3013   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3014   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3015   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3016   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3017   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3018   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3019   /* 88 */
3020   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3021   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3022   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3023   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3024   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3025   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3026   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3027   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3028   /* 90 */
3029   { "seto",             { Eb }, 0 },
3030   { "setno",            { Eb }, 0 },
3031   { "setb",             { Eb }, 0 },
3032   { "setae",            { Eb }, 0 },
3033   { "sete",             { Eb }, 0 },
3034   { "setne",            { Eb }, 0 },
3035   { "setbe",            { Eb }, 0 },
3036   { "seta",             { Eb }, 0 },
3037   /* 98 */
3038   { "sets",             { Eb }, 0 },
3039   { "setns",            { Eb }, 0 },
3040   { "setp",             { Eb }, 0 },
3041   { "setnp",            { Eb }, 0 },
3042   { "setl",             { Eb }, 0 },
3043   { "setge",            { Eb }, 0 },
3044   { "setle",            { Eb }, 0 },
3045   { "setg",             { Eb }, 0 },
3046   /* a0 */
3047   { "pushT",            { fs }, 0 },
3048   { "popT",             { fs }, 0 },
3049   { "cpuid",            { XX }, 0 },
3050   { "btS",              { Ev, Gv }, 0 },
3051   { "shldS",            { Ev, Gv, Ib }, 0 },
3052   { "shldS",            { Ev, Gv, CL }, 0 },
3053   { REG_TABLE (REG_0FA6) },
3054   { REG_TABLE (REG_0FA7) },
3055   /* a8 */
3056   { "pushT",            { gs }, 0 },
3057   { "popT",             { gs }, 0 },
3058   { "rsm",              { XX }, 0 },
3059   { "btsS",             { Evh1, Gv }, 0 },
3060   { "shrdS",            { Ev, Gv, Ib }, 0 },
3061   { "shrdS",            { Ev, Gv, CL }, 0 },
3062   { REG_TABLE (REG_0FAE) },
3063   { "imulS",            { Gv, Ev }, 0 },
3064   /* b0 */
3065   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3066   { "cmpxchgS",         { Evh1, Gv }, 0 },
3067   { MOD_TABLE (MOD_0FB2) },
3068   { "btrS",             { Evh1, Gv }, 0 },
3069   { MOD_TABLE (MOD_0FB4) },
3070   { MOD_TABLE (MOD_0FB5) },
3071   { "movz{bR|x}",       { Gv, Eb }, 0 },
3072   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3073   /* b8 */
3074   { PREFIX_TABLE (PREFIX_0FB8) },
3075   { "ud1S",             { Gv, Ev }, 0 },
3076   { REG_TABLE (REG_0FBA) },
3077   { "btcS",             { Evh1, Gv }, 0 },
3078   { PREFIX_TABLE (PREFIX_0FBC) },
3079   { PREFIX_TABLE (PREFIX_0FBD) },
3080   { "movs{bR|x}",       { Gv, Eb }, 0 },
3081   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3082   /* c0 */
3083   { "xaddB",            { Ebh1, Gb }, 0 },
3084   { "xaddS",            { Evh1, Gv }, 0 },
3085   { PREFIX_TABLE (PREFIX_0FC2) },
3086   { MOD_TABLE (MOD_0FC3) },
3087   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3088   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3089   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3090   { REG_TABLE (REG_0FC7) },
3091   /* c8 */
3092   { "bswap",            { RMeAX }, 0 },
3093   { "bswap",            { RMeCX }, 0 },
3094   { "bswap",            { RMeDX }, 0 },
3095   { "bswap",            { RMeBX }, 0 },
3096   { "bswap",            { RMeSP }, 0 },
3097   { "bswap",            { RMeBP }, 0 },
3098   { "bswap",            { RMeSI }, 0 },
3099   { "bswap",            { RMeDI }, 0 },
3100   /* d0 */
3101   { PREFIX_TABLE (PREFIX_0FD0) },
3102   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3103   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3104   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3105   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3106   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3107   { PREFIX_TABLE (PREFIX_0FD6) },
3108   { MOD_TABLE (MOD_0FD7) },
3109   /* d8 */
3110   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3111   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3112   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3113   { "pand",             { MX, EM }, PREFIX_OPCODE },
3114   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3115   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3116   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3117   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3118   /* e0 */
3119   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3120   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3121   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3122   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3123   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3124   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3125   { PREFIX_TABLE (PREFIX_0FE6) },
3126   { PREFIX_TABLE (PREFIX_0FE7) },
3127   /* e8 */
3128   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3129   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3130   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3131   { "por",              { MX, EM }, PREFIX_OPCODE },
3132   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3133   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3134   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3135   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3136   /* f0 */
3137   { PREFIX_TABLE (PREFIX_0FF0) },
3138   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3139   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3140   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3141   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3142   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3143   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3144   { PREFIX_TABLE (PREFIX_0FF7) },
3145   /* f8 */
3146   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3147   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3148   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3149   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3150   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3151   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3152   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3153   { "ud0S",             { Gv, Ev }, 0 },
3154 };
3155
3156 static const unsigned char onebyte_has_modrm[256] = {
3157   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3158   /*       -------------------------------        */
3159   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3160   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3161   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3162   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3163   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3164   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3165   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3166   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3167   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3168   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3169   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3170   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3171   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3172   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3173   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3174   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3175   /*       -------------------------------        */
3176   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3177 };
3178
3179 static const unsigned char twobyte_has_modrm[256] = {
3180   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3181   /*       -------------------------------        */
3182   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3183   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3184   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3185   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3186   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3187   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3188   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3189   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3190   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3191   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3192   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3193   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3194   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3195   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3196   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3197   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
3198   /*       -------------------------------        */
3199   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3200 };
3201
3202 static char obuf[100];
3203 static char *obufp;
3204 static char *mnemonicendp;
3205 static char scratchbuf[100];
3206 static unsigned char *start_codep;
3207 static unsigned char *insn_codep;
3208 static unsigned char *codep;
3209 static unsigned char *end_codep;
3210 static int last_lock_prefix;
3211 static int last_repz_prefix;
3212 static int last_repnz_prefix;
3213 static int last_data_prefix;
3214 static int last_addr_prefix;
3215 static int last_rex_prefix;
3216 static int last_seg_prefix;
3217 static int fwait_prefix;
3218 /* The active segment register prefix.  */
3219 static int active_seg_prefix;
3220 #define MAX_CODE_LENGTH 15
3221 /* We can up to 14 prefixes since the maximum instruction length is
3222    15bytes.  */
3223 static int all_prefixes[MAX_CODE_LENGTH - 1];
3224 static disassemble_info *the_info;
3225 static struct
3226   {
3227     int mod;
3228     int reg;
3229     int rm;
3230   }
3231 modrm;
3232 static unsigned char need_modrm;
3233 static struct
3234   {
3235     int scale;
3236     int index;
3237     int base;
3238   }
3239 sib;
3240 static struct
3241   {
3242     int register_specifier;
3243     int length;
3244     int prefix;
3245     int w;
3246     int evex;
3247     int r;
3248     int v;
3249     int mask_register_specifier;
3250     int zeroing;
3251     int ll;
3252     int b;
3253   }
3254 vex;
3255 static unsigned char need_vex;
3256 static unsigned char need_vex_reg;
3257 static unsigned char vex_w_done;
3258
3259 struct op
3260   {
3261     const char *name;
3262     unsigned int len;
3263   };
3264
3265 /* If we are accessing mod/rm/reg without need_modrm set, then the
3266    values are stale.  Hitting this abort likely indicates that you
3267    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3268 #define MODRM_CHECK  if (!need_modrm) abort ()
3269
3270 static const char **names64;
3271 static const char **names32;
3272 static const char **names16;
3273 static const char **names8;
3274 static const char **names8rex;
3275 static const char **names_seg;
3276 static const char *index64;
3277 static const char *index32;
3278 static const char **index16;
3279 static const char **names_bnd;
3280
3281 static const char *intel_names64[] = {
3282   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3283   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3284 };
3285 static const char *intel_names32[] = {
3286   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3287   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3288 };
3289 static const char *intel_names16[] = {
3290   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3291   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3292 };
3293 static const char *intel_names8[] = {
3294   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3295 };
3296 static const char *intel_names8rex[] = {
3297   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3298   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3299 };
3300 static const char *intel_names_seg[] = {
3301   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3302 };
3303 static const char *intel_index64 = "riz";
3304 static const char *intel_index32 = "eiz";
3305 static const char *intel_index16[] = {
3306   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3307 };
3308
3309 static const char *att_names64[] = {
3310   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3311   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3312 };
3313 static const char *att_names32[] = {
3314   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3315   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3316 };
3317 static const char *att_names16[] = {
3318   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3319   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3320 };
3321 static const char *att_names8[] = {
3322   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3323 };
3324 static const char *att_names8rex[] = {
3325   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3326   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3327 };
3328 static const char *att_names_seg[] = {
3329   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3330 };
3331 static const char *att_index64 = "%riz";
3332 static const char *att_index32 = "%eiz";
3333 static const char *att_index16[] = {
3334   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3335 };
3336
3337 static const char **names_mm;
3338 static const char *intel_names_mm[] = {
3339   "mm0", "mm1", "mm2", "mm3",
3340   "mm4", "mm5", "mm6", "mm7"
3341 };
3342 static const char *att_names_mm[] = {
3343   "%mm0", "%mm1", "%mm2", "%mm3",
3344   "%mm4", "%mm5", "%mm6", "%mm7"
3345 };
3346
3347 static const char *intel_names_bnd[] = {
3348   "bnd0", "bnd1", "bnd2", "bnd3"
3349 };
3350
3351 static const char *att_names_bnd[] = {
3352   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3353 };
3354
3355 static const char **names_xmm;
3356 static const char *intel_names_xmm[] = {
3357   "xmm0", "xmm1", "xmm2", "xmm3",
3358   "xmm4", "xmm5", "xmm6", "xmm7",
3359   "xmm8", "xmm9", "xmm10", "xmm11",
3360   "xmm12", "xmm13", "xmm14", "xmm15",
3361   "xmm16", "xmm17", "xmm18", "xmm19",
3362   "xmm20", "xmm21", "xmm22", "xmm23",
3363   "xmm24", "xmm25", "xmm26", "xmm27",
3364   "xmm28", "xmm29", "xmm30", "xmm31"
3365 };
3366 static const char *att_names_xmm[] = {
3367   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3368   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3369   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3370   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3371   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3372   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3373   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3374   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3375 };
3376
3377 static const char **names_ymm;
3378 static const char *intel_names_ymm[] = {
3379   "ymm0", "ymm1", "ymm2", "ymm3",
3380   "ymm4", "ymm5", "ymm6", "ymm7",
3381   "ymm8", "ymm9", "ymm10", "ymm11",
3382   "ymm12", "ymm13", "ymm14", "ymm15",
3383   "ymm16", "ymm17", "ymm18", "ymm19",
3384   "ymm20", "ymm21", "ymm22", "ymm23",
3385   "ymm24", "ymm25", "ymm26", "ymm27",
3386   "ymm28", "ymm29", "ymm30", "ymm31"
3387 };
3388 static const char *att_names_ymm[] = {
3389   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3390   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3391   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3392   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3393   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3394   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3395   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3396   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3397 };
3398
3399 static const char **names_zmm;
3400 static const char *intel_names_zmm[] = {
3401   "zmm0", "zmm1", "zmm2", "zmm3",
3402   "zmm4", "zmm5", "zmm6", "zmm7",
3403   "zmm8", "zmm9", "zmm10", "zmm11",
3404   "zmm12", "zmm13", "zmm14", "zmm15",
3405   "zmm16", "zmm17", "zmm18", "zmm19",
3406   "zmm20", "zmm21", "zmm22", "zmm23",
3407   "zmm24", "zmm25", "zmm26", "zmm27",
3408   "zmm28", "zmm29", "zmm30", "zmm31"
3409 };
3410 static const char *att_names_zmm[] = {
3411   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3412   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3413   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3414   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3415   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3416   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3417   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3418   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3419 };
3420
3421 static const char **names_mask;
3422 static const char *intel_names_mask[] = {
3423   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3424 };
3425 static const char *att_names_mask[] = {
3426   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3427 };
3428
3429 static const char *names_rounding[] =
3430 {
3431   "{rn-sae}",
3432   "{rd-sae}",
3433   "{ru-sae}",
3434   "{rz-sae}"
3435 };
3436
3437 static const struct dis386 reg_table[][8] = {
3438   /* REG_80 */
3439   {
3440     { "addA",   { Ebh1, Ib }, 0 },
3441     { "orA",    { Ebh1, Ib }, 0 },
3442     { "adcA",   { Ebh1, Ib }, 0 },
3443     { "sbbA",   { Ebh1, Ib }, 0 },
3444     { "andA",   { Ebh1, Ib }, 0 },
3445     { "subA",   { Ebh1, Ib }, 0 },
3446     { "xorA",   { Ebh1, Ib }, 0 },
3447     { "cmpA",   { Eb, Ib }, 0 },
3448   },
3449   /* REG_81 */
3450   {
3451     { "addQ",   { Evh1, Iv }, 0 },
3452     { "orQ",    { Evh1, Iv }, 0 },
3453     { "adcQ",   { Evh1, Iv }, 0 },
3454     { "sbbQ",   { Evh1, Iv }, 0 },
3455     { "andQ",   { Evh1, Iv }, 0 },
3456     { "subQ",   { Evh1, Iv }, 0 },
3457     { "xorQ",   { Evh1, Iv }, 0 },
3458     { "cmpQ",   { Ev, Iv }, 0 },
3459   },
3460   /* REG_83 */
3461   {
3462     { "addQ",   { Evh1, sIb }, 0 },
3463     { "orQ",    { Evh1, sIb }, 0 },
3464     { "adcQ",   { Evh1, sIb }, 0 },
3465     { "sbbQ",   { Evh1, sIb }, 0 },
3466     { "andQ",   { Evh1, sIb }, 0 },
3467     { "subQ",   { Evh1, sIb }, 0 },
3468     { "xorQ",   { Evh1, sIb }, 0 },
3469     { "cmpQ",   { Ev, sIb }, 0 },
3470   },
3471   /* REG_8F */
3472   {
3473     { "popU",   { stackEv }, 0 },
3474     { XOP_8F_TABLE (XOP_09) },
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { XOP_8F_TABLE (XOP_09) },
3479   },
3480   /* REG_C0 */
3481   {
3482     { "rolA",   { Eb, Ib }, 0 },
3483     { "rorA",   { Eb, Ib }, 0 },
3484     { "rclA",   { Eb, Ib }, 0 },
3485     { "rcrA",   { Eb, Ib }, 0 },
3486     { "shlA",   { Eb, Ib }, 0 },
3487     { "shrA",   { Eb, Ib }, 0 },
3488     { "shlA",   { Eb, Ib }, 0 },
3489     { "sarA",   { Eb, Ib }, 0 },
3490   },
3491   /* REG_C1 */
3492   {
3493     { "rolQ",   { Ev, Ib }, 0 },
3494     { "rorQ",   { Ev, Ib }, 0 },
3495     { "rclQ",   { Ev, Ib }, 0 },
3496     { "rcrQ",   { Ev, Ib }, 0 },
3497     { "shlQ",   { Ev, Ib }, 0 },
3498     { "shrQ",   { Ev, Ib }, 0 },
3499     { "shlQ",   { Ev, Ib }, 0 },
3500     { "sarQ",   { Ev, Ib }, 0 },
3501   },
3502   /* REG_C6 */
3503   {
3504     { "movA",   { Ebh3, Ib }, 0 },
3505     { Bad_Opcode },
3506     { Bad_Opcode },
3507     { Bad_Opcode },
3508     { Bad_Opcode },
3509     { Bad_Opcode },
3510     { Bad_Opcode },
3511     { MOD_TABLE (MOD_C6_REG_7) },
3512   },
3513   /* REG_C7 */
3514   {
3515     { "movQ",   { Evh3, Iv }, 0 },
3516     { Bad_Opcode },
3517     { Bad_Opcode },
3518     { Bad_Opcode },
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { Bad_Opcode },
3522     { MOD_TABLE (MOD_C7_REG_7) },
3523   },
3524   /* REG_D0 */
3525   {
3526     { "rolA",   { Eb, I1 }, 0 },
3527     { "rorA",   { Eb, I1 }, 0 },
3528     { "rclA",   { Eb, I1 }, 0 },
3529     { "rcrA",   { Eb, I1 }, 0 },
3530     { "shlA",   { Eb, I1 }, 0 },
3531     { "shrA",   { Eb, I1 }, 0 },
3532     { "shlA",   { Eb, I1 }, 0 },
3533     { "sarA",   { Eb, I1 }, 0 },
3534   },
3535   /* REG_D1 */
3536   {
3537     { "rolQ",   { Ev, I1 }, 0 },
3538     { "rorQ",   { Ev, I1 }, 0 },
3539     { "rclQ",   { Ev, I1 }, 0 },
3540     { "rcrQ",   { Ev, I1 }, 0 },
3541     { "shlQ",   { Ev, I1 }, 0 },
3542     { "shrQ",   { Ev, I1 }, 0 },
3543     { "shlQ",   { Ev, I1 }, 0 },
3544     { "sarQ",   { Ev, I1 }, 0 },
3545   },
3546   /* REG_D2 */
3547   {
3548     { "rolA",   { Eb, CL }, 0 },
3549     { "rorA",   { Eb, CL }, 0 },
3550     { "rclA",   { Eb, CL }, 0 },
3551     { "rcrA",   { Eb, CL }, 0 },
3552     { "shlA",   { Eb, CL }, 0 },
3553     { "shrA",   { Eb, CL }, 0 },
3554     { "shlA",   { Eb, CL }, 0 },
3555     { "sarA",   { Eb, CL }, 0 },
3556   },
3557   /* REG_D3 */
3558   {
3559     { "rolQ",   { Ev, CL }, 0 },
3560     { "rorQ",   { Ev, CL }, 0 },
3561     { "rclQ",   { Ev, CL }, 0 },
3562     { "rcrQ",   { Ev, CL }, 0 },
3563     { "shlQ",   { Ev, CL }, 0 },
3564     { "shrQ",   { Ev, CL }, 0 },
3565     { "shlQ",   { Ev, CL }, 0 },
3566     { "sarQ",   { Ev, CL }, 0 },
3567   },
3568   /* REG_F6 */
3569   {
3570     { "testA",  { Eb, Ib }, 0 },
3571     { "testA",  { Eb, Ib }, 0 },
3572     { "notA",   { Ebh1 }, 0 },
3573     { "negA",   { Ebh1 }, 0 },
3574     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3575     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3576     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3577     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3578   },
3579   /* REG_F7 */
3580   {
3581     { "testQ",  { Ev, Iv }, 0 },
3582     { "testQ",  { Ev, Iv }, 0 },
3583     { "notQ",   { Evh1 }, 0 },
3584     { "negQ",   { Evh1 }, 0 },
3585     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3586     { "imulQ",  { Ev }, 0 },
3587     { "divQ",   { Ev }, 0 },
3588     { "idivQ",  { Ev }, 0 },
3589   },
3590   /* REG_FE */
3591   {
3592     { "incA",   { Ebh1 }, 0 },
3593     { "decA",   { Ebh1 }, 0 },
3594   },
3595   /* REG_FF */
3596   {
3597     { "incQ",   { Evh1 }, 0 },
3598     { "decQ",   { Evh1 }, 0 },
3599     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3600     { MOD_TABLE (MOD_FF_REG_3) },
3601     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3602     { MOD_TABLE (MOD_FF_REG_5) },
3603     { "pushU",  { stackEv }, 0 },
3604     { Bad_Opcode },
3605   },
3606   /* REG_0F00 */
3607   {
3608     { "sldtD",  { Sv }, 0 },
3609     { "strD",   { Sv }, 0 },
3610     { "lldt",   { Ew }, 0 },
3611     { "ltr",    { Ew }, 0 },
3612     { "verr",   { Ew }, 0 },
3613     { "verw",   { Ew }, 0 },
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616   },
3617   /* REG_0F01 */
3618   {
3619     { MOD_TABLE (MOD_0F01_REG_0) },
3620     { MOD_TABLE (MOD_0F01_REG_1) },
3621     { MOD_TABLE (MOD_0F01_REG_2) },
3622     { MOD_TABLE (MOD_0F01_REG_3) },
3623     { "smswD",  { Sv }, 0 },
3624     { MOD_TABLE (MOD_0F01_REG_5) },
3625     { "lmsw",   { Ew }, 0 },
3626     { MOD_TABLE (MOD_0F01_REG_7) },
3627   },
3628   /* REG_0F0D */
3629   {
3630     { "prefetch",       { Mb }, 0 },
3631     { "prefetchw",      { Mb }, 0 },
3632     { "prefetchwt1",    { Mb }, 0 },
3633     { "prefetch",       { Mb }, 0 },
3634     { "prefetch",       { Mb }, 0 },
3635     { "prefetch",       { Mb }, 0 },
3636     { "prefetch",       { Mb }, 0 },
3637     { "prefetch",       { Mb }, 0 },
3638   },
3639   /* REG_0F18 */
3640   {
3641     { MOD_TABLE (MOD_0F18_REG_0) },
3642     { MOD_TABLE (MOD_0F18_REG_1) },
3643     { MOD_TABLE (MOD_0F18_REG_2) },
3644     { MOD_TABLE (MOD_0F18_REG_3) },
3645     { MOD_TABLE (MOD_0F18_REG_4) },
3646     { MOD_TABLE (MOD_0F18_REG_5) },
3647     { MOD_TABLE (MOD_0F18_REG_6) },
3648     { MOD_TABLE (MOD_0F18_REG_7) },
3649   },
3650   /* REG_0F1E_MOD_3 */
3651   {
3652     { "nopQ",           { Ev }, 0 },
3653     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3654     { "nopQ",           { Ev }, 0 },
3655     { "nopQ",           { Ev }, 0 },
3656     { "nopQ",           { Ev }, 0 },
3657     { "nopQ",           { Ev }, 0 },
3658     { "nopQ",           { Ev }, 0 },
3659     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3660   },
3661   /* REG_0F71 */
3662   {
3663     { Bad_Opcode },
3664     { Bad_Opcode },
3665     { MOD_TABLE (MOD_0F71_REG_2) },
3666     { Bad_Opcode },
3667     { MOD_TABLE (MOD_0F71_REG_4) },
3668     { Bad_Opcode },
3669     { MOD_TABLE (MOD_0F71_REG_6) },
3670   },
3671   /* REG_0F72 */
3672   {
3673     { Bad_Opcode },
3674     { Bad_Opcode },
3675     { MOD_TABLE (MOD_0F72_REG_2) },
3676     { Bad_Opcode },
3677     { MOD_TABLE (MOD_0F72_REG_4) },
3678     { Bad_Opcode },
3679     { MOD_TABLE (MOD_0F72_REG_6) },
3680   },
3681   /* REG_0F73 */
3682   {
3683     { Bad_Opcode },
3684     { Bad_Opcode },
3685     { MOD_TABLE (MOD_0F73_REG_2) },
3686     { MOD_TABLE (MOD_0F73_REG_3) },
3687     { Bad_Opcode },
3688     { Bad_Opcode },
3689     { MOD_TABLE (MOD_0F73_REG_6) },
3690     { MOD_TABLE (MOD_0F73_REG_7) },
3691   },
3692   /* REG_0FA6 */
3693   {
3694     { "montmul",        { { OP_0f07, 0 } }, 0 },
3695     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3696     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3697   },
3698   /* REG_0FA7 */
3699   {
3700     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3701     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3702     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3703     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3704     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3705     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3706   },
3707   /* REG_0FAE */
3708   {
3709     { MOD_TABLE (MOD_0FAE_REG_0) },
3710     { MOD_TABLE (MOD_0FAE_REG_1) },
3711     { MOD_TABLE (MOD_0FAE_REG_2) },
3712     { MOD_TABLE (MOD_0FAE_REG_3) },
3713     { MOD_TABLE (MOD_0FAE_REG_4) },
3714     { MOD_TABLE (MOD_0FAE_REG_5) },
3715     { MOD_TABLE (MOD_0FAE_REG_6) },
3716     { MOD_TABLE (MOD_0FAE_REG_7) },
3717   },
3718   /* REG_0FBA */
3719   {
3720     { Bad_Opcode },
3721     { Bad_Opcode },
3722     { Bad_Opcode },
3723     { Bad_Opcode },
3724     { "btQ",    { Ev, Ib }, 0 },
3725     { "btsQ",   { Evh1, Ib }, 0 },
3726     { "btrQ",   { Evh1, Ib }, 0 },
3727     { "btcQ",   { Evh1, Ib }, 0 },
3728   },
3729   /* REG_0FC7 */
3730   {
3731     { Bad_Opcode },
3732     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3733     { Bad_Opcode },
3734     { MOD_TABLE (MOD_0FC7_REG_3) },
3735     { MOD_TABLE (MOD_0FC7_REG_4) },
3736     { MOD_TABLE (MOD_0FC7_REG_5) },
3737     { MOD_TABLE (MOD_0FC7_REG_6) },
3738     { MOD_TABLE (MOD_0FC7_REG_7) },
3739   },
3740   /* REG_VEX_0F71 */
3741   {
3742     { Bad_Opcode },
3743     { Bad_Opcode },
3744     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3745     { Bad_Opcode },
3746     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3747     { Bad_Opcode },
3748     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3749   },
3750   /* REG_VEX_0F72 */
3751   {
3752     { Bad_Opcode },
3753     { Bad_Opcode },
3754     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3755     { Bad_Opcode },
3756     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3757     { Bad_Opcode },
3758     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3759   },
3760   /* REG_VEX_0F73 */
3761   {
3762     { Bad_Opcode },
3763     { Bad_Opcode },
3764     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3765     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3766     { Bad_Opcode },
3767     { Bad_Opcode },
3768     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3769     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3770   },
3771   /* REG_VEX_0FAE */
3772   {
3773     { Bad_Opcode },
3774     { Bad_Opcode },
3775     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3776     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3777   },
3778   /* REG_VEX_0F38F3 */
3779   {
3780     { Bad_Opcode },
3781     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3782     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3783     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3784   },
3785   /* REG_XOP_LWPCB */
3786   {
3787     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3788     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3789   },
3790   /* REG_XOP_LWP */
3791   {
3792     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3793     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3794   },
3795   /* REG_XOP_TBM_01 */
3796   {
3797     { Bad_Opcode },
3798     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3799     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3800     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3801     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3802     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3803     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3804     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3805   },
3806   /* REG_XOP_TBM_02 */
3807   {
3808     { Bad_Opcode },
3809     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3810     { Bad_Opcode },
3811     { Bad_Opcode },
3812     { Bad_Opcode },
3813     { Bad_Opcode },
3814     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3815   },
3816 #define NEED_REG_TABLE
3817 #include "i386-dis-evex.h"
3818 #undef NEED_REG_TABLE
3819 };
3820
3821 static const struct dis386 prefix_table[][4] = {
3822   /* PREFIX_90 */
3823   {
3824     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3825     { "pause", { XX }, 0 },
3826     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3827     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3828   },
3829
3830   /* PREFIX_MOD_0_0F01_REG_5 */
3831   {
3832     { Bad_Opcode },
3833     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3834   },
3835
3836   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3837   {
3838     { Bad_Opcode },
3839     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3843   {
3844     { Bad_Opcode },
3845     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3846   },
3847
3848   /* PREFIX_0F09 */
3849   {
3850     { "wbinvd",   { XX }, 0 },
3851     { "wbnoinvd", { XX }, 0 },
3852   },
3853
3854   /* PREFIX_0F10 */
3855   {
3856     { "movups", { XM, EXx }, PREFIX_OPCODE },
3857     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3858     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3859     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3860   },
3861
3862   /* PREFIX_0F11 */
3863   {
3864     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3865     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3866     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3867     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3868   },
3869
3870   /* PREFIX_0F12 */
3871   {
3872     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3873     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3874     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3875     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3876   },
3877
3878   /* PREFIX_0F16 */
3879   {
3880     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3881     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3882     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3883   },
3884
3885   /* PREFIX_0F1A */
3886   {
3887     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3888     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3889     { "bndmov", { Gbnd, Ebnd }, 0 },
3890     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3891   },
3892
3893   /* PREFIX_0F1B */
3894   {
3895     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3896     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3897     { "bndmov", { EbndS, Gbnd }, 0 },
3898     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3899   },
3900
3901   /* PREFIX_0F1E */
3902   {
3903     { "nopQ",   { Ev }, PREFIX_OPCODE },
3904     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3905     { "nopQ",   { Ev }, PREFIX_OPCODE },
3906     { "nopQ",   { Ev }, PREFIX_OPCODE },
3907   },
3908
3909   /* PREFIX_0F2A */
3910   {
3911     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3912     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3913     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3914     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3915   },
3916
3917   /* PREFIX_0F2B */
3918   {
3919     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3920     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3921     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3922     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3923   },
3924
3925   /* PREFIX_0F2C */
3926   {
3927     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3928     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3929     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3930     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3931   },
3932
3933   /* PREFIX_0F2D */
3934   {
3935     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3936     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3937     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3938     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3939   },
3940
3941   /* PREFIX_0F2E */
3942   {
3943     { "ucomiss",{ XM, EXd }, 0 },
3944     { Bad_Opcode },
3945     { "ucomisd",{ XM, EXq }, 0 },
3946   },
3947
3948   /* PREFIX_0F2F */
3949   {
3950     { "comiss", { XM, EXd }, 0 },
3951     { Bad_Opcode },
3952     { "comisd", { XM, EXq }, 0 },
3953   },
3954
3955   /* PREFIX_0F51 */
3956   {
3957     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3958     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3959     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3960     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3961   },
3962
3963   /* PREFIX_0F52 */
3964   {
3965     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3966     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3967   },
3968
3969   /* PREFIX_0F53 */
3970   {
3971     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3972     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3973   },
3974
3975   /* PREFIX_0F58 */
3976   {
3977     { "addps", { XM, EXx }, PREFIX_OPCODE },
3978     { "addss", { XM, EXd }, PREFIX_OPCODE },
3979     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3980     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3981   },
3982
3983   /* PREFIX_0F59 */
3984   {
3985     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3986     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3987     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3988     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3989   },
3990
3991   /* PREFIX_0F5A */
3992   {
3993     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3994     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3995     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3996     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3997   },
3998
3999   /* PREFIX_0F5B */
4000   {
4001     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
4002     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
4003     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4004   },
4005
4006   /* PREFIX_0F5C */
4007   {
4008     { "subps",  { XM, EXx }, PREFIX_OPCODE },
4009     { "subss",  { XM, EXd }, PREFIX_OPCODE },
4010     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
4011     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
4012   },
4013
4014   /* PREFIX_0F5D */
4015   {
4016     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4017     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4018     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4019     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4020   },
4021
4022   /* PREFIX_0F5E */
4023   {
4024     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4025     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4026     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4027     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4028   },
4029
4030   /* PREFIX_0F5F */
4031   {
4032     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4033     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4034     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4035     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4036   },
4037
4038   /* PREFIX_0F60 */
4039   {
4040     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4041     { Bad_Opcode },
4042     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4043   },
4044
4045   /* PREFIX_0F61 */
4046   {
4047     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4048     { Bad_Opcode },
4049     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4050   },
4051
4052   /* PREFIX_0F62 */
4053   {
4054     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4055     { Bad_Opcode },
4056     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4057   },
4058
4059   /* PREFIX_0F6C */
4060   {
4061     { Bad_Opcode },
4062     { Bad_Opcode },
4063     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4064   },
4065
4066   /* PREFIX_0F6D */
4067   {
4068     { Bad_Opcode },
4069     { Bad_Opcode },
4070     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4071   },
4072
4073   /* PREFIX_0F6F */
4074   {
4075     { "movq",   { MX, EM }, PREFIX_OPCODE },
4076     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4077     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4078   },
4079
4080   /* PREFIX_0F70 */
4081   {
4082     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4083     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4084     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4085     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4086   },
4087
4088   /* PREFIX_0F73_REG_3 */
4089   {
4090     { Bad_Opcode },
4091     { Bad_Opcode },
4092     { "psrldq", { XS, Ib }, 0 },
4093   },
4094
4095   /* PREFIX_0F73_REG_7 */
4096   {
4097     { Bad_Opcode },
4098     { Bad_Opcode },
4099     { "pslldq", { XS, Ib }, 0 },
4100   },
4101
4102   /* PREFIX_0F78 */
4103   {
4104     {"vmread",  { Em, Gm }, 0 },
4105     { Bad_Opcode },
4106     {"extrq",   { XS, Ib, Ib }, 0 },
4107     {"insertq", { XM, XS, Ib, Ib }, 0 },
4108   },
4109
4110   /* PREFIX_0F79 */
4111   {
4112     {"vmwrite", { Gm, Em }, 0 },
4113     { Bad_Opcode },
4114     {"extrq",   { XM, XS }, 0 },
4115     {"insertq", { XM, XS }, 0 },
4116   },
4117
4118   /* PREFIX_0F7C */
4119   {
4120     { Bad_Opcode },
4121     { Bad_Opcode },
4122     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4123     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4124   },
4125
4126   /* PREFIX_0F7D */
4127   {
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4131     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F7E */
4135   {
4136     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4137     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4138     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F7F */
4142   {
4143     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4144     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4145     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0FAE_REG_0 */
4149   {
4150     { Bad_Opcode },
4151     { "rdfsbase", { Ev }, 0 },
4152   },
4153
4154   /* PREFIX_0FAE_REG_1 */
4155   {
4156     { Bad_Opcode },
4157     { "rdgsbase", { Ev }, 0 },
4158   },
4159
4160   /* PREFIX_0FAE_REG_2 */
4161   {
4162     { Bad_Opcode },
4163     { "wrfsbase", { Ev }, 0 },
4164   },
4165
4166   /* PREFIX_0FAE_REG_3 */
4167   {
4168     { Bad_Opcode },
4169     { "wrgsbase", { Ev }, 0 },
4170   },
4171
4172   /* PREFIX_MOD_0_0FAE_REG_4 */
4173   {
4174     { "xsave",  { FXSAVE }, 0 },
4175     { "ptwrite%LQ", { Edq }, 0 },
4176   },
4177
4178   /* PREFIX_MOD_3_0FAE_REG_4 */
4179   {
4180     { Bad_Opcode },
4181     { "ptwrite%LQ", { Edq }, 0 },
4182   },
4183
4184   /* PREFIX_MOD_0_0FAE_REG_5 */
4185   {
4186     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4187   },
4188
4189   /* PREFIX_MOD_3_0FAE_REG_5 */
4190   {
4191     { "lfence",         { Skip_MODRM }, 0 },
4192     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4193   },
4194
4195   /* PREFIX_0FAE_REG_6 */
4196   {
4197     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4198     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4199     { "clwb",   { Mb }, PREFIX_OPCODE },
4200   },
4201
4202   /* PREFIX_0FAE_REG_7 */
4203   {
4204     { "clflush",        { Mb }, 0 },
4205     { Bad_Opcode },
4206     { "clflushopt",     { Mb }, 0 },
4207   },
4208
4209   /* PREFIX_0FB8 */
4210   {
4211     { Bad_Opcode },
4212     { "popcntS", { Gv, Ev }, 0 },
4213   },
4214
4215   /* PREFIX_0FBC */
4216   {
4217     { "bsfS",   { Gv, Ev }, 0 },
4218     { "tzcntS", { Gv, Ev }, 0 },
4219     { "bsfS",   { Gv, Ev }, 0 },
4220   },
4221
4222   /* PREFIX_0FBD */
4223   {
4224     { "bsrS",   { Gv, Ev }, 0 },
4225     { "lzcntS", { Gv, Ev }, 0 },
4226     { "bsrS",   { Gv, Ev }, 0 },
4227   },
4228
4229   /* PREFIX_0FC2 */
4230   {
4231     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4232     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4233     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4234     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4235   },
4236
4237   /* PREFIX_MOD_0_0FC3 */
4238   {
4239     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4240   },
4241
4242   /* PREFIX_MOD_0_0FC7_REG_6 */
4243   {
4244     { "vmptrld",{ Mq }, 0 },
4245     { "vmxon",  { Mq }, 0 },
4246     { "vmclear",{ Mq }, 0 },
4247   },
4248
4249   /* PREFIX_MOD_3_0FC7_REG_6 */
4250   {
4251     { "rdrand", { Ev }, 0 },
4252     { Bad_Opcode },
4253     { "rdrand", { Ev }, 0 }
4254   },
4255
4256   /* PREFIX_MOD_3_0FC7_REG_7 */
4257   {
4258     { "rdseed", { Ev }, 0 },
4259     { "rdpid",  { Em }, 0 },
4260     { "rdseed", { Ev }, 0 },
4261   },
4262
4263   /* PREFIX_0FD0 */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { "addsubpd", { XM, EXx }, 0 },
4268     { "addsubps", { XM, EXx }, 0 },
4269   },
4270
4271   /* PREFIX_0FD6 */
4272   {
4273     { Bad_Opcode },
4274     { "movq2dq",{ XM, MS }, 0 },
4275     { "movq",   { EXqS, XM }, 0 },
4276     { "movdq2q",{ MX, XS }, 0 },
4277   },
4278
4279   /* PREFIX_0FE6 */
4280   {
4281     { Bad_Opcode },
4282     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4283     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4284     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4285   },
4286
4287   /* PREFIX_0FE7 */
4288   {
4289     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4290     { Bad_Opcode },
4291     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4292   },
4293
4294   /* PREFIX_0FF0 */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4300   },
4301
4302   /* PREFIX_0FF7 */
4303   {
4304     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4305     { Bad_Opcode },
4306     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F3810 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F3814 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3815 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3817 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3820 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F3821 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F3822 */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F3823 */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F3824 */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4370   },
4371
4372   /* PREFIX_0F3825 */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4377   },
4378
4379   /* PREFIX_0F3828 */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4384   },
4385
4386   /* PREFIX_0F3829 */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F382A */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4398   },
4399
4400   /* PREFIX_0F382B */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4405   },
4406
4407   /* PREFIX_0F3830 */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F3831 */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4419   },
4420
4421   /* PREFIX_0F3832 */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F3833 */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4433   },
4434
4435   /* PREFIX_0F3834 */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4440   },
4441
4442   /* PREFIX_0F3835 */
4443   {
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4447   },
4448
4449   /* PREFIX_0F3837 */
4450   {
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4454   },
4455
4456   /* PREFIX_0F3838 */
4457   {
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4461   },
4462
4463   /* PREFIX_0F3839 */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4468   },
4469
4470   /* PREFIX_0F383A */
4471   {
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4475   },
4476
4477   /* PREFIX_0F383B */
4478   {
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4482   },
4483
4484   /* PREFIX_0F383C */
4485   {
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4489   },
4490
4491   /* PREFIX_0F383D */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4496   },
4497
4498   /* PREFIX_0F383E */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4503   },
4504
4505   /* PREFIX_0F383F */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4510   },
4511
4512   /* PREFIX_0F3840 */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4517   },
4518
4519   /* PREFIX_0F3841 */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F3880 */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F3881 */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F3882 */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F38C8 */
4548   {
4549     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F38C9 */
4553   {
4554     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4555   },
4556
4557   /* PREFIX_0F38CA */
4558   {
4559     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4560   },
4561
4562   /* PREFIX_0F38CB */
4563   {
4564     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F38CC */
4568   {
4569     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4570   },
4571
4572   /* PREFIX_0F38CD */
4573   {
4574     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4575   },
4576
4577   /* PREFIX_0F38CF */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4582   },
4583
4584   /* PREFIX_0F38DB */
4585   {
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4589   },
4590
4591   /* PREFIX_0F38DC */
4592   {
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4596   },
4597
4598   /* PREFIX_0F38DD */
4599   {
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4603   },
4604
4605   /* PREFIX_0F38DE */
4606   {
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4610   },
4611
4612   /* PREFIX_0F38DF */
4613   {
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4617   },
4618
4619   /* PREFIX_0F38F0 */
4620   {
4621     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4622     { Bad_Opcode },
4623     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4624     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4625   },
4626
4627   /* PREFIX_0F38F1 */
4628   {
4629     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4630     { Bad_Opcode },
4631     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4632     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4633   },
4634
4635   /* PREFIX_0F38F5 */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4640   },
4641
4642   /* PREFIX_0F38F6 */
4643   {
4644     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4645     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4646     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4647     { Bad_Opcode },
4648   },
4649
4650   /* PREFIX_0F3A08 */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4655   },
4656
4657   /* PREFIX_0F3A09 */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4662   },
4663
4664   /* PREFIX_0F3A0A */
4665   {
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4669   },
4670
4671   /* PREFIX_0F3A0B */
4672   {
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4676   },
4677
4678   /* PREFIX_0F3A0C */
4679   {
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4683   },
4684
4685   /* PREFIX_0F3A0D */
4686   {
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4690   },
4691
4692   /* PREFIX_0F3A0E */
4693   {
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4697   },
4698
4699   /* PREFIX_0F3A14 */
4700   {
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4704   },
4705
4706   /* PREFIX_0F3A15 */
4707   {
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4711   },
4712
4713   /* PREFIX_0F3A16 */
4714   {
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4718   },
4719
4720   /* PREFIX_0F3A17 */
4721   {
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4725   },
4726
4727   /* PREFIX_0F3A20 */
4728   {
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4732   },
4733
4734   /* PREFIX_0F3A21 */
4735   {
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4739   },
4740
4741   /* PREFIX_0F3A22 */
4742   {
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4746   },
4747
4748   /* PREFIX_0F3A40 */
4749   {
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4753   },
4754
4755   /* PREFIX_0F3A41 */
4756   {
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4760   },
4761
4762   /* PREFIX_0F3A42 */
4763   {
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4767   },
4768
4769   /* PREFIX_0F3A44 */
4770   {
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4774   },
4775
4776   /* PREFIX_0F3A60 */
4777   {
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4781   },
4782
4783   /* PREFIX_0F3A61 */
4784   {
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4788   },
4789
4790   /* PREFIX_0F3A62 */
4791   {
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4795   },
4796
4797   /* PREFIX_0F3A63 */
4798   {
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4802   },
4803
4804   /* PREFIX_0F3ACC */
4805   {
4806     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4807   },
4808
4809   /* PREFIX_0F3ACE */
4810   {
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4814   },
4815
4816   /* PREFIX_0F3ACF */
4817   {
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4821   },
4822
4823   /* PREFIX_0F3ADF */
4824   {
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4828   },
4829
4830   /* PREFIX_VEX_0F10 */
4831   {
4832     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4833     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4834     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4835     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4836   },
4837
4838   /* PREFIX_VEX_0F11 */
4839   {
4840     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4841     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4842     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4843     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4844   },
4845
4846   /* PREFIX_VEX_0F12 */
4847   {
4848     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4849     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4850     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4851     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4852   },
4853
4854   /* PREFIX_VEX_0F16 */
4855   {
4856     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4857     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4858     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4859   },
4860
4861   /* PREFIX_VEX_0F2A */
4862   {
4863     { Bad_Opcode },
4864     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4865     { Bad_Opcode },
4866     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4867   },
4868
4869   /* PREFIX_VEX_0F2C */
4870   {
4871     { Bad_Opcode },
4872     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4873     { Bad_Opcode },
4874     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4875   },
4876
4877   /* PREFIX_VEX_0F2D */
4878   {
4879     { Bad_Opcode },
4880     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4881     { Bad_Opcode },
4882     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4883   },
4884
4885   /* PREFIX_VEX_0F2E */
4886   {
4887     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4888     { Bad_Opcode },
4889     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4890   },
4891
4892   /* PREFIX_VEX_0F2F */
4893   {
4894     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4895     { Bad_Opcode },
4896     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4897   },
4898
4899   /* PREFIX_VEX_0F41 */
4900   {
4901     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4902     { Bad_Opcode },
4903     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4904   },
4905
4906   /* PREFIX_VEX_0F42 */
4907   {
4908     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4909     { Bad_Opcode },
4910     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4911   },
4912
4913   /* PREFIX_VEX_0F44 */
4914   {
4915     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4916     { Bad_Opcode },
4917     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4918   },
4919
4920   /* PREFIX_VEX_0F45 */
4921   {
4922     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4923     { Bad_Opcode },
4924     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4925   },
4926
4927   /* PREFIX_VEX_0F46 */
4928   {
4929     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4930     { Bad_Opcode },
4931     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_0F47 */
4935   {
4936     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4937     { Bad_Opcode },
4938     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_0F4A */
4942   {
4943     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4944     { Bad_Opcode },
4945     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_0F4B */
4949   {
4950     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4951     { Bad_Opcode },
4952     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_0F51 */
4956   {
4957     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4958     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4959     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4960     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4961   },
4962
4963   /* PREFIX_VEX_0F52 */
4964   {
4965     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4966     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4967   },
4968
4969   /* PREFIX_VEX_0F53 */
4970   {
4971     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4972     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4973   },
4974
4975   /* PREFIX_VEX_0F58 */
4976   {
4977     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4978     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4979     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4980     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4981   },
4982
4983   /* PREFIX_VEX_0F59 */
4984   {
4985     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4986     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4987     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4988     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4989   },
4990
4991   /* PREFIX_VEX_0F5A */
4992   {
4993     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4994     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4995     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4996     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4997   },
4998
4999   /* PREFIX_VEX_0F5B */
5000   {
5001     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
5002     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
5003     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5004   },
5005
5006   /* PREFIX_VEX_0F5C */
5007   {
5008     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5009     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5010     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5011     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5012   },
5013
5014   /* PREFIX_VEX_0F5D */
5015   {
5016     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5017     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5018     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5019     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5020   },
5021
5022   /* PREFIX_VEX_0F5E */
5023   {
5024     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5025     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5026     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5027     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5028   },
5029
5030   /* PREFIX_VEX_0F5F */
5031   {
5032     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5033     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5034     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5035     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5036   },
5037
5038   /* PREFIX_VEX_0F60 */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5043   },
5044
5045   /* PREFIX_VEX_0F61 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5050   },
5051
5052   /* PREFIX_VEX_0F62 */
5053   {
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5057   },
5058
5059   /* PREFIX_VEX_0F63 */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5064   },
5065
5066   /* PREFIX_VEX_0F64 */
5067   {
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5071   },
5072
5073   /* PREFIX_VEX_0F65 */
5074   {
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5078   },
5079
5080   /* PREFIX_VEX_0F66 */
5081   {
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5085   },
5086
5087   /* PREFIX_VEX_0F67 */
5088   {
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_0F68 */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0F69 */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0F6A */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5113   },
5114
5115   /* PREFIX_VEX_0F6B */
5116   {
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5120   },
5121
5122   /* PREFIX_VEX_0F6C */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5127   },
5128
5129   /* PREFIX_VEX_0F6D */
5130   {
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5134   },
5135
5136   /* PREFIX_VEX_0F6E */
5137   {
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5141   },
5142
5143   /* PREFIX_VEX_0F6F */
5144   {
5145     { Bad_Opcode },
5146     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5147     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0F70 */
5151   {
5152     { Bad_Opcode },
5153     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5154     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5155     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5156   },
5157
5158   /* PREFIX_VEX_0F71_REG_2 */
5159   {
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5163   },
5164
5165   /* PREFIX_VEX_0F71_REG_4 */
5166   {
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5170   },
5171
5172   /* PREFIX_VEX_0F71_REG_6 */
5173   {
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5177   },
5178
5179   /* PREFIX_VEX_0F72_REG_2 */
5180   {
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5184   },
5185
5186   /* PREFIX_VEX_0F72_REG_4 */
5187   {
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5191   },
5192
5193   /* PREFIX_VEX_0F72_REG_6 */
5194   {
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5198   },
5199
5200   /* PREFIX_VEX_0F73_REG_2 */
5201   {
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5205   },
5206
5207   /* PREFIX_VEX_0F73_REG_3 */
5208   {
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5212   },
5213
5214   /* PREFIX_VEX_0F73_REG_6 */
5215   {
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5219   },
5220
5221   /* PREFIX_VEX_0F73_REG_7 */
5222   {
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5226   },
5227
5228   /* PREFIX_VEX_0F74 */
5229   {
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5233   },
5234
5235   /* PREFIX_VEX_0F75 */
5236   {
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5240   },
5241
5242   /* PREFIX_VEX_0F76 */
5243   {
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5247   },
5248
5249   /* PREFIX_VEX_0F77 */
5250   {
5251     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5252   },
5253
5254   /* PREFIX_VEX_0F7C */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5259     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5260   },
5261
5262   /* PREFIX_VEX_0F7D */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5267     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5268   },
5269
5270   /* PREFIX_VEX_0F7E */
5271   {
5272     { Bad_Opcode },
5273     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5274     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5275   },
5276
5277   /* PREFIX_VEX_0F7F */
5278   {
5279     { Bad_Opcode },
5280     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5281     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5282   },
5283
5284   /* PREFIX_VEX_0F90 */
5285   {
5286     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5287     { Bad_Opcode },
5288     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5289   },
5290
5291   /* PREFIX_VEX_0F91 */
5292   {
5293     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5294     { Bad_Opcode },
5295     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5296   },
5297
5298   /* PREFIX_VEX_0F92 */
5299   {
5300     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5301     { Bad_Opcode },
5302     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5303     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5304   },
5305
5306   /* PREFIX_VEX_0F93 */
5307   {
5308     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5309     { Bad_Opcode },
5310     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5311     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5312   },
5313
5314   /* PREFIX_VEX_0F98 */
5315   {
5316     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5317     { Bad_Opcode },
5318     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5319   },
5320
5321   /* PREFIX_VEX_0F99 */
5322   {
5323     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5324     { Bad_Opcode },
5325     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5326   },
5327
5328   /* PREFIX_VEX_0FC2 */
5329   {
5330     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5331     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5332     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5333     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5334   },
5335
5336   /* PREFIX_VEX_0FC4 */
5337   {
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5341   },
5342
5343   /* PREFIX_VEX_0FC5 */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5348   },
5349
5350   /* PREFIX_VEX_0FD0 */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5355     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5356   },
5357
5358   /* PREFIX_VEX_0FD1 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5363   },
5364
5365   /* PREFIX_VEX_0FD2 */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5370   },
5371
5372   /* PREFIX_VEX_0FD3 */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5377   },
5378
5379   /* PREFIX_VEX_0FD4 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5384   },
5385
5386   /* PREFIX_VEX_0FD5 */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5391   },
5392
5393   /* PREFIX_VEX_0FD6 */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5398   },
5399
5400   /* PREFIX_VEX_0FD7 */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5405   },
5406
5407   /* PREFIX_VEX_0FD8 */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5412   },
5413
5414   /* PREFIX_VEX_0FD9 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5419   },
5420
5421   /* PREFIX_VEX_0FDA */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5426   },
5427
5428   /* PREFIX_VEX_0FDB */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5433   },
5434
5435   /* PREFIX_VEX_0FDC */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5440   },
5441
5442   /* PREFIX_VEX_0FDD */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5447   },
5448
5449   /* PREFIX_VEX_0FDE */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5454   },
5455
5456   /* PREFIX_VEX_0FDF */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5461   },
5462
5463   /* PREFIX_VEX_0FE0 */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5468   },
5469
5470   /* PREFIX_VEX_0FE1 */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5475   },
5476
5477   /* PREFIX_VEX_0FE2 */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5482   },
5483
5484   /* PREFIX_VEX_0FE3 */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5489   },
5490
5491   /* PREFIX_VEX_0FE4 */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5496   },
5497
5498   /* PREFIX_VEX_0FE5 */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5503   },
5504
5505   /* PREFIX_VEX_0FE6 */
5506   {
5507     { Bad_Opcode },
5508     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5509     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5510     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5511   },
5512
5513   /* PREFIX_VEX_0FE7 */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5518   },
5519
5520   /* PREFIX_VEX_0FE8 */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5525   },
5526
5527   /* PREFIX_VEX_0FE9 */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5532   },
5533
5534   /* PREFIX_VEX_0FEA */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5539   },
5540
5541   /* PREFIX_VEX_0FEB */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5546   },
5547
5548   /* PREFIX_VEX_0FEC */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5553   },
5554
5555   /* PREFIX_VEX_0FED */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5560   },
5561
5562   /* PREFIX_VEX_0FEE */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5567   },
5568
5569   /* PREFIX_VEX_0FEF */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5574   },
5575
5576   /* PREFIX_VEX_0FF0 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5582   },
5583
5584   /* PREFIX_VEX_0FF1 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0FF2 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0FF3 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0FF4 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0FF5 */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0FF6 */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0FF7 */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0FF8 */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0FF9 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0FFA */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0FFB */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5659   },
5660
5661   /* PREFIX_VEX_0FFC */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0FFD */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5673   },
5674
5675   /* PREFIX_VEX_0FFE */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5680   },
5681
5682   /* PREFIX_VEX_0F3800 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5687   },
5688
5689   /* PREFIX_VEX_0F3801 */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5694   },
5695
5696   /* PREFIX_VEX_0F3802 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5701   },
5702
5703   /* PREFIX_VEX_0F3803 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5708   },
5709
5710   /* PREFIX_VEX_0F3804 */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5715   },
5716
5717   /* PREFIX_VEX_0F3805 */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5722   },
5723
5724   /* PREFIX_VEX_0F3806 */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5729   },
5730
5731   /* PREFIX_VEX_0F3807 */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F3808 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F3809 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F380A */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F380B */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F380C */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F380D */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F380E */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F380F */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F3813 */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5799   },
5800
5801   /* PREFIX_VEX_0F3816 */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F3817 */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F3818 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5820   },
5821
5822   /* PREFIX_VEX_0F3819 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5827   },
5828
5829   /* PREFIX_VEX_0F381A */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5834   },
5835
5836   /* PREFIX_VEX_0F381C */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5841   },
5842
5843   /* PREFIX_VEX_0F381D */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5848   },
5849
5850   /* PREFIX_VEX_0F381E */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5855   },
5856
5857   /* PREFIX_VEX_0F3820 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5862   },
5863
5864   /* PREFIX_VEX_0F3821 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5869   },
5870
5871   /* PREFIX_VEX_0F3822 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5876   },
5877
5878   /* PREFIX_VEX_0F3823 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5883   },
5884
5885   /* PREFIX_VEX_0F3824 */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F3825 */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F3828 */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F3829 */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F382A */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F382B */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F382C */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F382D */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F382E */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5946   },
5947
5948   /* PREFIX_VEX_0F382F */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5953   },
5954
5955   /* PREFIX_VEX_0F3830 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5960   },
5961
5962   /* PREFIX_VEX_0F3831 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5967   },
5968
5969   /* PREFIX_VEX_0F3832 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5974   },
5975
5976   /* PREFIX_VEX_0F3833 */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5981   },
5982
5983   /* PREFIX_VEX_0F3834 */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5988   },
5989
5990   /* PREFIX_VEX_0F3835 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5995   },
5996
5997   /* PREFIX_VEX_0F3836 */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
6002   },
6003
6004   /* PREFIX_VEX_0F3837 */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6009   },
6010
6011   /* PREFIX_VEX_0F3838 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6016   },
6017
6018   /* PREFIX_VEX_0F3839 */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6023   },
6024
6025   /* PREFIX_VEX_0F383A */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6030   },
6031
6032   /* PREFIX_VEX_0F383B */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6037   },
6038
6039   /* PREFIX_VEX_0F383C */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6044   },
6045
6046   /* PREFIX_VEX_0F383D */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6051   },
6052
6053   /* PREFIX_VEX_0F383E */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6058   },
6059
6060   /* PREFIX_VEX_0F383F */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6065   },
6066
6067   /* PREFIX_VEX_0F3840 */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6072   },
6073
6074   /* PREFIX_VEX_0F3841 */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6079   },
6080
6081   /* PREFIX_VEX_0F3845 */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F3846 */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6093   },
6094
6095   /* PREFIX_VEX_0F3847 */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6100   },
6101
6102   /* PREFIX_VEX_0F3858 */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6107   },
6108
6109   /* PREFIX_VEX_0F3859 */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6114   },
6115
6116   /* PREFIX_VEX_0F385A */
6117   {
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6121   },
6122
6123   /* PREFIX_VEX_0F3878 */
6124   {
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6128   },
6129
6130   /* PREFIX_VEX_0F3879 */
6131   {
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6135   },
6136
6137   /* PREFIX_VEX_0F388C */
6138   {
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6142   },
6143
6144   /* PREFIX_VEX_0F388E */
6145   {
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6149   },
6150
6151   /* PREFIX_VEX_0F3890 */
6152   {
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6156   },
6157
6158   /* PREFIX_VEX_0F3891 */
6159   {
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6163   },
6164
6165   /* PREFIX_VEX_0F3892 */
6166   {
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6170   },
6171
6172   /* PREFIX_VEX_0F3893 */
6173   {
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6177   },
6178
6179   /* PREFIX_VEX_0F3896 */
6180   {
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6184   },
6185
6186   /* PREFIX_VEX_0F3897 */
6187   {
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6191   },
6192
6193   /* PREFIX_VEX_0F3898 */
6194   {
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6198   },
6199
6200   /* PREFIX_VEX_0F3899 */
6201   {
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6205   },
6206
6207   /* PREFIX_VEX_0F389A */
6208   {
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6212   },
6213
6214   /* PREFIX_VEX_0F389B */
6215   {
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6219   },
6220
6221   /* PREFIX_VEX_0F389C */
6222   {
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6226   },
6227
6228   /* PREFIX_VEX_0F389D */
6229   {
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6233   },
6234
6235   /* PREFIX_VEX_0F389E */
6236   {
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6240   },
6241
6242   /* PREFIX_VEX_0F389F */
6243   {
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6247   },
6248
6249   /* PREFIX_VEX_0F38A6 */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6254     { Bad_Opcode },
6255   },
6256
6257   /* PREFIX_VEX_0F38A7 */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6262   },
6263
6264   /* PREFIX_VEX_0F38A8 */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6269   },
6270
6271   /* PREFIX_VEX_0F38A9 */
6272   {
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6276   },
6277
6278   /* PREFIX_VEX_0F38AA */
6279   {
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6283   },
6284
6285   /* PREFIX_VEX_0F38AB */
6286   {
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6290   },
6291
6292   /* PREFIX_VEX_0F38AC */
6293   {
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6297   },
6298
6299   /* PREFIX_VEX_0F38AD */
6300   {
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6304   },
6305
6306   /* PREFIX_VEX_0F38AE */
6307   {
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6311   },
6312
6313   /* PREFIX_VEX_0F38AF */
6314   {
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6318   },
6319
6320   /* PREFIX_VEX_0F38B6 */
6321   {
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6325   },
6326
6327   /* PREFIX_VEX_0F38B7 */
6328   {
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6332   },
6333
6334   /* PREFIX_VEX_0F38B8 */
6335   {
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6339   },
6340
6341   /* PREFIX_VEX_0F38B9 */
6342   {
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6346   },
6347
6348   /* PREFIX_VEX_0F38BA */
6349   {
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6353   },
6354
6355   /* PREFIX_VEX_0F38BB */
6356   {
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6360   },
6361
6362   /* PREFIX_VEX_0F38BC */
6363   {
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6367   },
6368
6369   /* PREFIX_VEX_0F38BD */
6370   {
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6374   },
6375
6376   /* PREFIX_VEX_0F38BE */
6377   {
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6381   },
6382
6383   /* PREFIX_VEX_0F38BF */
6384   {
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6388   },
6389
6390   /* PREFIX_VEX_0F38CF */
6391   {
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6395   },
6396
6397   /* PREFIX_VEX_0F38DB */
6398   {
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6402   },
6403
6404   /* PREFIX_VEX_0F38DC */
6405   {
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { "vaesenc",        { XM, Vex, EXx }, 0 },
6409   },
6410
6411   /* PREFIX_VEX_0F38DD */
6412   {
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6416   },
6417
6418   /* PREFIX_VEX_0F38DE */
6419   {
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { "vaesdec",        { XM, Vex, EXx }, 0 },
6423   },
6424
6425   /* PREFIX_VEX_0F38DF */
6426   {
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6430   },
6431
6432   /* PREFIX_VEX_0F38F2 */
6433   {
6434     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6435   },
6436
6437   /* PREFIX_VEX_0F38F3_REG_1 */
6438   {
6439     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6440   },
6441
6442   /* PREFIX_VEX_0F38F3_REG_2 */
6443   {
6444     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6445   },
6446
6447   /* PREFIX_VEX_0F38F3_REG_3 */
6448   {
6449     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6450   },
6451
6452   /* PREFIX_VEX_0F38F5 */
6453   {
6454     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6455     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6456     { Bad_Opcode },
6457     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6458   },
6459
6460   /* PREFIX_VEX_0F38F6 */
6461   {
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6466   },
6467
6468   /* PREFIX_VEX_0F38F7 */
6469   {
6470     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6471     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6472     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6473     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A00 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A01 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A02 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A04 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A05 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A06 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A08 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A09 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A0A */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A0B */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A0C */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6551   },
6552
6553   /* PREFIX_VEX_0F3A0D */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A0E */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6565   },
6566
6567   /* PREFIX_VEX_0F3A0F */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A14 */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A15 */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6586   },
6587
6588   /* PREFIX_VEX_0F3A16 */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6593   },
6594
6595   /* PREFIX_VEX_0F3A17 */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6600   },
6601
6602   /* PREFIX_VEX_0F3A18 */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6607   },
6608
6609   /* PREFIX_VEX_0F3A19 */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6614   },
6615
6616   /* PREFIX_VEX_0F3A1D */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6621   },
6622
6623   /* PREFIX_VEX_0F3A20 */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6628   },
6629
6630   /* PREFIX_VEX_0F3A21 */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6635   },
6636
6637   /* PREFIX_VEX_0F3A22 */
6638   {
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6642   },
6643
6644   /* PREFIX_VEX_0F3A30 */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6649   },
6650
6651   /* PREFIX_VEX_0F3A31 */
6652   {
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6656   },
6657
6658   /* PREFIX_VEX_0F3A32 */
6659   {
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6663   },
6664
6665   /* PREFIX_VEX_0F3A33 */
6666   {
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6670   },
6671
6672   /* PREFIX_VEX_0F3A38 */
6673   {
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6677   },
6678
6679   /* PREFIX_VEX_0F3A39 */
6680   {
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6684   },
6685
6686   /* PREFIX_VEX_0F3A40 */
6687   {
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6691   },
6692
6693   /* PREFIX_VEX_0F3A41 */
6694   {
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6698   },
6699
6700   /* PREFIX_VEX_0F3A42 */
6701   {
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6705   },
6706
6707   /* PREFIX_VEX_0F3A44 */
6708   {
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6712   },
6713
6714   /* PREFIX_VEX_0F3A46 */
6715   {
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6719   },
6720
6721   /* PREFIX_VEX_0F3A48 */
6722   {
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6726   },
6727
6728   /* PREFIX_VEX_0F3A49 */
6729   {
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6733   },
6734
6735   /* PREFIX_VEX_0F3A4A */
6736   {
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6740   },
6741
6742   /* PREFIX_VEX_0F3A4B */
6743   {
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6747   },
6748
6749   /* PREFIX_VEX_0F3A4C */
6750   {
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6754   },
6755
6756   /* PREFIX_VEX_0F3A5C */
6757   {
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6761   },
6762
6763   /* PREFIX_VEX_0F3A5D */
6764   {
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6768   },
6769
6770   /* PREFIX_VEX_0F3A5E */
6771   {
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6775   },
6776
6777   /* PREFIX_VEX_0F3A5F */
6778   {
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6782   },
6783
6784   /* PREFIX_VEX_0F3A60 */
6785   {
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6789     { Bad_Opcode },
6790   },
6791
6792   /* PREFIX_VEX_0F3A61 */
6793   {
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6797   },
6798
6799   /* PREFIX_VEX_0F3A62 */
6800   {
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6804   },
6805
6806   /* PREFIX_VEX_0F3A63 */
6807   {
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6811   },
6812
6813   /* PREFIX_VEX_0F3A68 */
6814   {
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6818   },
6819
6820   /* PREFIX_VEX_0F3A69 */
6821   {
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6825   },
6826
6827   /* PREFIX_VEX_0F3A6A */
6828   {
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6832   },
6833
6834   /* PREFIX_VEX_0F3A6B */
6835   {
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6839   },
6840
6841   /* PREFIX_VEX_0F3A6C */
6842   {
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6846   },
6847
6848   /* PREFIX_VEX_0F3A6D */
6849   {
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6853   },
6854
6855   /* PREFIX_VEX_0F3A6E */
6856   {
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6860   },
6861
6862   /* PREFIX_VEX_0F3A6F */
6863   {
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6867   },
6868
6869   /* PREFIX_VEX_0F3A78 */
6870   {
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6874   },
6875
6876   /* PREFIX_VEX_0F3A79 */
6877   {
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6881   },
6882
6883   /* PREFIX_VEX_0F3A7A */
6884   {
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6888   },
6889
6890   /* PREFIX_VEX_0F3A7B */
6891   {
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6895   },
6896
6897   /* PREFIX_VEX_0F3A7C */
6898   {
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6902     { Bad_Opcode },
6903   },
6904
6905   /* PREFIX_VEX_0F3A7D */
6906   {
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6910   },
6911
6912   /* PREFIX_VEX_0F3A7E */
6913   {
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6917   },
6918
6919   /* PREFIX_VEX_0F3A7F */
6920   {
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6924   },
6925
6926   /* PREFIX_VEX_0F3ACE */
6927   {
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6931   },
6932
6933   /* PREFIX_VEX_0F3ACF */
6934   {
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6938   },
6939
6940   /* PREFIX_VEX_0F3ADF */
6941   {
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6945   },
6946
6947   /* PREFIX_VEX_0F3AF0 */
6948   {
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6953   },
6954
6955 #define NEED_PREFIX_TABLE
6956 #include "i386-dis-evex.h"
6957 #undef NEED_PREFIX_TABLE
6958 };
6959
6960 static const struct dis386 x86_64_table[][2] = {
6961   /* X86_64_06 */
6962   {
6963     { "pushP", { es }, 0 },
6964   },
6965
6966   /* X86_64_07 */
6967   {
6968     { "popP", { es }, 0 },
6969   },
6970
6971   /* X86_64_0D */
6972   {
6973     { "pushP", { cs }, 0 },
6974   },
6975
6976   /* X86_64_16 */
6977   {
6978     { "pushP", { ss }, 0 },
6979   },
6980
6981   /* X86_64_17 */
6982   {
6983     { "popP", { ss }, 0 },
6984   },
6985
6986   /* X86_64_1E */
6987   {
6988     { "pushP", { ds }, 0 },
6989   },
6990
6991   /* X86_64_1F */
6992   {
6993     { "popP", { ds }, 0 },
6994   },
6995
6996   /* X86_64_27 */
6997   {
6998     { "daa", { XX }, 0 },
6999   },
7000
7001   /* X86_64_2F */
7002   {
7003     { "das", { XX }, 0 },
7004   },
7005
7006   /* X86_64_37 */
7007   {
7008     { "aaa", { XX }, 0 },
7009   },
7010
7011   /* X86_64_3F */
7012   {
7013     { "aas", { XX }, 0 },
7014   },
7015
7016   /* X86_64_60 */
7017   {
7018     { "pushaP", { XX }, 0 },
7019   },
7020
7021   /* X86_64_61 */
7022   {
7023     { "popaP", { XX }, 0 },
7024   },
7025
7026   /* X86_64_62 */
7027   {
7028     { MOD_TABLE (MOD_62_32BIT) },
7029     { EVEX_TABLE (EVEX_0F) },
7030   },
7031
7032   /* X86_64_63 */
7033   {
7034     { "arpl", { Ew, Gw }, 0 },
7035     { "movs{lq|xd}", { Gv, Ed }, 0 },
7036   },
7037
7038   /* X86_64_6D */
7039   {
7040     { "ins{R|}", { Yzr, indirDX }, 0 },
7041     { "ins{G|}", { Yzr, indirDX }, 0 },
7042   },
7043
7044   /* X86_64_6F */
7045   {
7046     { "outs{R|}", { indirDXr, Xz }, 0 },
7047     { "outs{G|}", { indirDXr, Xz }, 0 },
7048   },
7049
7050   /* X86_64_82 */
7051   {
7052     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7053     { REG_TABLE (REG_80) },
7054   },
7055
7056   /* X86_64_9A */
7057   {
7058     { "Jcall{T|}", { Ap }, 0 },
7059   },
7060
7061   /* X86_64_C4 */
7062   {
7063     { MOD_TABLE (MOD_C4_32BIT) },
7064     { VEX_C4_TABLE (VEX_0F) },
7065   },
7066
7067   /* X86_64_C5 */
7068   {
7069     { MOD_TABLE (MOD_C5_32BIT) },
7070     { VEX_C5_TABLE (VEX_0F) },
7071   },
7072
7073   /* X86_64_CE */
7074   {
7075     { "into", { XX }, 0 },
7076   },
7077
7078   /* X86_64_D4 */
7079   {
7080     { "aam", { Ib }, 0 },
7081   },
7082
7083   /* X86_64_D5 */
7084   {
7085     { "aad", { Ib }, 0 },
7086   },
7087
7088   /* X86_64_E8 */
7089   {
7090     { "callP",          { Jv, BND }, 0 },
7091     { "call@",          { Jv, BND }, 0 }
7092   },
7093
7094   /* X86_64_E9 */
7095   {
7096     { "jmpP",           { Jv, BND }, 0 },
7097     { "jmp@",           { Jv, BND }, 0 }
7098   },
7099
7100   /* X86_64_EA */
7101   {
7102     { "Jjmp{T|}", { Ap }, 0 },
7103   },
7104
7105   /* X86_64_0F01_REG_0 */
7106   {
7107     { "sgdt{Q|IQ}", { M }, 0 },
7108     { "sgdt", { M }, 0 },
7109   },
7110
7111   /* X86_64_0F01_REG_1 */
7112   {
7113     { "sidt{Q|IQ}", { M }, 0 },
7114     { "sidt", { M }, 0 },
7115   },
7116
7117   /* X86_64_0F01_REG_2 */
7118   {
7119     { "lgdt{Q|Q}", { M }, 0 },
7120     { "lgdt", { M }, 0 },
7121   },
7122
7123   /* X86_64_0F01_REG_3 */
7124   {
7125     { "lidt{Q|Q}", { M }, 0 },
7126     { "lidt", { M }, 0 },
7127   },
7128 };
7129
7130 static const struct dis386 three_byte_table[][256] = {
7131
7132   /* THREE_BYTE_0F38 */
7133   {
7134     /* 00 */
7135     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7136     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7137     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7138     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7139     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7140     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7141     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7142     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7143     /* 08 */
7144     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7145     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7146     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7147     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     /* 10 */
7153     { PREFIX_TABLE (PREFIX_0F3810) },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { PREFIX_TABLE (PREFIX_0F3814) },
7158     { PREFIX_TABLE (PREFIX_0F3815) },
7159     { Bad_Opcode },
7160     { PREFIX_TABLE (PREFIX_0F3817) },
7161     /* 18 */
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7167     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7168     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7169     { Bad_Opcode },
7170     /* 20 */
7171     { PREFIX_TABLE (PREFIX_0F3820) },
7172     { PREFIX_TABLE (PREFIX_0F3821) },
7173     { PREFIX_TABLE (PREFIX_0F3822) },
7174     { PREFIX_TABLE (PREFIX_0F3823) },
7175     { PREFIX_TABLE (PREFIX_0F3824) },
7176     { PREFIX_TABLE (PREFIX_0F3825) },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     /* 28 */
7180     { PREFIX_TABLE (PREFIX_0F3828) },
7181     { PREFIX_TABLE (PREFIX_0F3829) },
7182     { PREFIX_TABLE (PREFIX_0F382A) },
7183     { PREFIX_TABLE (PREFIX_0F382B) },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     /* 30 */
7189     { PREFIX_TABLE (PREFIX_0F3830) },
7190     { PREFIX_TABLE (PREFIX_0F3831) },
7191     { PREFIX_TABLE (PREFIX_0F3832) },
7192     { PREFIX_TABLE (PREFIX_0F3833) },
7193     { PREFIX_TABLE (PREFIX_0F3834) },
7194     { PREFIX_TABLE (PREFIX_0F3835) },
7195     { Bad_Opcode },
7196     { PREFIX_TABLE (PREFIX_0F3837) },
7197     /* 38 */
7198     { PREFIX_TABLE (PREFIX_0F3838) },
7199     { PREFIX_TABLE (PREFIX_0F3839) },
7200     { PREFIX_TABLE (PREFIX_0F383A) },
7201     { PREFIX_TABLE (PREFIX_0F383B) },
7202     { PREFIX_TABLE (PREFIX_0F383C) },
7203     { PREFIX_TABLE (PREFIX_0F383D) },
7204     { PREFIX_TABLE (PREFIX_0F383E) },
7205     { PREFIX_TABLE (PREFIX_0F383F) },
7206     /* 40 */
7207     { PREFIX_TABLE (PREFIX_0F3840) },
7208     { PREFIX_TABLE (PREFIX_0F3841) },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     /* 48 */
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     /* 50 */
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     /* 58 */
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     /* 60 */
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     /* 68 */
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     /* 70 */
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     /* 78 */
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     /* 80 */
7279     { PREFIX_TABLE (PREFIX_0F3880) },
7280     { PREFIX_TABLE (PREFIX_0F3881) },
7281     { PREFIX_TABLE (PREFIX_0F3882) },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     /* 88 */
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     /* 90 */
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     /* 98 */
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     /* a0 */
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     /* a8 */
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     /* b0 */
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     /* b8 */
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     /* c0 */
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     /* c8 */
7360     { PREFIX_TABLE (PREFIX_0F38C8) },
7361     { PREFIX_TABLE (PREFIX_0F38C9) },
7362     { PREFIX_TABLE (PREFIX_0F38CA) },
7363     { PREFIX_TABLE (PREFIX_0F38CB) },
7364     { PREFIX_TABLE (PREFIX_0F38CC) },
7365     { PREFIX_TABLE (PREFIX_0F38CD) },
7366     { Bad_Opcode },
7367     { PREFIX_TABLE (PREFIX_0F38CF) },
7368     /* d0 */
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     /* d8 */
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { PREFIX_TABLE (PREFIX_0F38DB) },
7382     { PREFIX_TABLE (PREFIX_0F38DC) },
7383     { PREFIX_TABLE (PREFIX_0F38DD) },
7384     { PREFIX_TABLE (PREFIX_0F38DE) },
7385     { PREFIX_TABLE (PREFIX_0F38DF) },
7386     /* e0 */
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     /* e8 */
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     /* f0 */
7405     { PREFIX_TABLE (PREFIX_0F38F0) },
7406     { PREFIX_TABLE (PREFIX_0F38F1) },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { PREFIX_TABLE (PREFIX_0F38F5) },
7411     { PREFIX_TABLE (PREFIX_0F38F6) },
7412     { Bad_Opcode },
7413     /* f8 */
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422   },
7423   /* THREE_BYTE_0F3A */
7424   {
7425     /* 00 */
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     /* 08 */
7435     { PREFIX_TABLE (PREFIX_0F3A08) },
7436     { PREFIX_TABLE (PREFIX_0F3A09) },
7437     { PREFIX_TABLE (PREFIX_0F3A0A) },
7438     { PREFIX_TABLE (PREFIX_0F3A0B) },
7439     { PREFIX_TABLE (PREFIX_0F3A0C) },
7440     { PREFIX_TABLE (PREFIX_0F3A0D) },
7441     { PREFIX_TABLE (PREFIX_0F3A0E) },
7442     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7443     /* 10 */
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { PREFIX_TABLE (PREFIX_0F3A14) },
7449     { PREFIX_TABLE (PREFIX_0F3A15) },
7450     { PREFIX_TABLE (PREFIX_0F3A16) },
7451     { PREFIX_TABLE (PREFIX_0F3A17) },
7452     /* 18 */
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     /* 20 */
7462     { PREFIX_TABLE (PREFIX_0F3A20) },
7463     { PREFIX_TABLE (PREFIX_0F3A21) },
7464     { PREFIX_TABLE (PREFIX_0F3A22) },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     /* 28 */
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     /* 30 */
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     /* 38 */
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     /* 40 */
7498     { PREFIX_TABLE (PREFIX_0F3A40) },
7499     { PREFIX_TABLE (PREFIX_0F3A41) },
7500     { PREFIX_TABLE (PREFIX_0F3A42) },
7501     { Bad_Opcode },
7502     { PREFIX_TABLE (PREFIX_0F3A44) },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     /* 48 */
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     /* 50 */
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     /* 58 */
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     /* 60 */
7534     { PREFIX_TABLE (PREFIX_0F3A60) },
7535     { PREFIX_TABLE (PREFIX_0F3A61) },
7536     { PREFIX_TABLE (PREFIX_0F3A62) },
7537     { PREFIX_TABLE (PREFIX_0F3A63) },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     /* 68 */
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     /* 70 */
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     /* 78 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* 80 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* 88 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* 90 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* 98 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     /* a0 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* a8 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* b0 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* b8 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* c0 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     /* c8 */
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { PREFIX_TABLE (PREFIX_0F3ACC) },
7656     { Bad_Opcode },
7657     { PREFIX_TABLE (PREFIX_0F3ACE) },
7658     { PREFIX_TABLE (PREFIX_0F3ACF) },
7659     /* d0 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     /* d8 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { PREFIX_TABLE (PREFIX_0F3ADF) },
7677     /* e0 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     /* e8 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     /* f0 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     /* f8 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713   },
7714 };
7715
7716 static const struct dis386 xop_table[][256] = {
7717   /* XOP_08 */
7718   {
7719     /* 00 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     /* 08 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     /* 10 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     /* 18 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     /* 20 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     /* 28 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     /* 30 */
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     /* 38 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     /* 40 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     /* 48 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     /* 50 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* 58 */
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     /* 60 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* 68 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     /* 70 */
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     /* 78 */
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     /* 80 */
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7870     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7871     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7872     /* 88 */
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7880     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7881     /* 90 */
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7888     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7889     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7890     /* 98 */
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7898     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7899     /* a0 */
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7903     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7907     { Bad_Opcode },
7908     /* a8 */
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     /* b0 */
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7925     { Bad_Opcode },
7926     /* b8 */
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     /* c0 */
7936     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7937     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7938     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7939     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     /* c8 */
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7950     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7951     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7952     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7953     /* d0 */
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     /* d8 */
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     /* e0 */
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     /* e8 */
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7986     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7987     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7988     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7989     /* f0 */
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     /* f8 */
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007   },
8008   /* XOP_09 */
8009   {
8010     /* 00 */
8011     { Bad_Opcode },
8012     { REG_TABLE (REG_XOP_TBM_01) },
8013     { REG_TABLE (REG_XOP_TBM_02) },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     /* 08 */
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     /* 10 */
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { REG_TABLE (REG_XOP_LWPCB) },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     /* 18 */
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* 20 */
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* 28 */
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     /* 30 */
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     /* 38 */
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* 40 */
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     /* 48 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     /* 50 */
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     /* 58 */
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     /* 60 */
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     /* 68 */
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     /* 70 */
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     /* 78 */
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     /* 80 */
8155     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8156     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8157     { "vfrczss",        { XM, EXd }, 0 },
8158     { "vfrczsd",        { XM, EXq }, 0 },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     /* 88 */
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     /* 90 */
8173     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8174     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8175     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8176     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8177     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8178     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8179     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8180     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8181     /* 98 */
8182     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8183     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8184     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8185     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     /* a0 */
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     /* a8 */
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     /* b0 */
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     /* b8 */
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     /* c0 */
8227     { Bad_Opcode },
8228     { "vphaddbw",       { XM, EXxmm }, 0 },
8229     { "vphaddbd",       { XM, EXxmm }, 0 },
8230     { "vphaddbq",       { XM, EXxmm }, 0 },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { "vphaddwd",       { XM, EXxmm }, 0 },
8234     { "vphaddwq",       { XM, EXxmm }, 0 },
8235     /* c8 */
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { "vphadddq",       { XM, EXxmm }, 0 },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     /* d0 */
8245     { Bad_Opcode },
8246     { "vphaddubw",      { XM, EXxmm }, 0 },
8247     { "vphaddubd",      { XM, EXxmm }, 0 },
8248     { "vphaddubq",      { XM, EXxmm }, 0 },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { "vphadduwd",      { XM, EXxmm }, 0 },
8252     { "vphadduwq",      { XM, EXxmm }, 0 },
8253     /* d8 */
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { "vphaddudq",      { XM, EXxmm }, 0 },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     /* e0 */
8263     { Bad_Opcode },
8264     { "vphsubbw",       { XM, EXxmm }, 0 },
8265     { "vphsubwd",       { XM, EXxmm }, 0 },
8266     { "vphsubdq",       { XM, EXxmm }, 0 },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     /* e8 */
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     /* f0 */
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     /* f8 */
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298   },
8299   /* XOP_0A */
8300   {
8301     /* 00 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     /* 08 */
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* 10 */
8320     { "bextr",  { Gv, Ev, Iq }, 0 },
8321     { Bad_Opcode },
8322     { REG_TABLE (REG_XOP_LWP) },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* 18 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* 20 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     /* 28 */
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* 30 */
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     /* 38 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* 40 */
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* 48 */
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     /* 50 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     /* 58 */
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     /* 60 */
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     /* 68 */
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     /* 70 */
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     /* 78 */
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     /* 80 */
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     /* 88 */
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     /* 90 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     /* 98 */
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     /* a0 */
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     /* a8 */
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     /* b0 */
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     /* b8 */
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     /* c0 */
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     /* c8 */
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     /* d0 */
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     /* d8 */
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     /* e0 */
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     /* e8 */
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     /* f0 */
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     /* f8 */
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589   },
8590 };
8591
8592 static const struct dis386 vex_table[][256] = {
8593   /* VEX_0F */
8594   {
8595     /* 00 */
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     /* 08 */
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     /* 10 */
8614     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8617     { MOD_TABLE (MOD_VEX_0F13) },
8618     { VEX_W_TABLE (VEX_W_0F14) },
8619     { VEX_W_TABLE (VEX_W_0F15) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8621     { MOD_TABLE (MOD_VEX_0F17) },
8622     /* 18 */
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     /* 20 */
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     /* 28 */
8641     { VEX_W_TABLE (VEX_W_0F28) },
8642     { VEX_W_TABLE (VEX_W_0F29) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8644     { MOD_TABLE (MOD_VEX_0F2B) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8649     /* 30 */
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     /* 38 */
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     /* 40 */
8668     { Bad_Opcode },
8669     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8671     { Bad_Opcode },
8672     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8676     /* 48 */
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     /* 50 */
8686     { MOD_TABLE (MOD_VEX_0F50) },
8687     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8688     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8689     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8690     { "vandpX",         { XM, Vex, EXx }, 0 },
8691     { "vandnpX",        { XM, Vex, EXx }, 0 },
8692     { "vorpX",          { XM, Vex, EXx }, 0 },
8693     { "vxorpX",         { XM, Vex, EXx }, 0 },
8694     /* 58 */
8695     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8703     /* 60 */
8704     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8712     /* 68 */
8713     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8721     /* 70 */
8722     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8723     { REG_TABLE (REG_VEX_0F71) },
8724     { REG_TABLE (REG_VEX_0F72) },
8725     { REG_TABLE (REG_VEX_0F73) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8730     /* 78 */
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8739     /* 80 */
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     /* 88 */
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     /* 90 */
8758     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     /* 98 */
8767     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     /* a0 */
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     /* a8 */
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { REG_TABLE (REG_VEX_0FAE) },
8792     { Bad_Opcode },
8793     /* b0 */
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     /* b8 */
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     /* c0 */
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8815     { Bad_Opcode },
8816     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8817     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8818     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8819     { Bad_Opcode },
8820     /* c8 */
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     /* d0 */
8830     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8831     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8832     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8833     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8834     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8835     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8836     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8837     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8838     /* d8 */
8839     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8840     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8841     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8842     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8843     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8847     /* e0 */
8848     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8849     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8850     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8851     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8856     /* e8 */
8857     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8859     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8865     /* f0 */
8866     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8874     /* f8 */
8875     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8877     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8878     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8880     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8881     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8882     { Bad_Opcode },
8883   },
8884   /* VEX_0F38 */
8885   {
8886     /* 00 */
8887     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8895     /* 08 */
8896     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8904     /* 10 */
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8913     /* 18 */
8914     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8917     { Bad_Opcode },
8918     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8921     { Bad_Opcode },
8922     /* 20 */
8923     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     /* 28 */
8932     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8940     /* 30 */
8941     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8949     /* 38 */
8950     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8958     /* 40 */
8959     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8967     /* 48 */
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     /* 50 */
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     /* 58 */
8986     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     /* 60 */
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     /* 68 */
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     /* 70 */
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     /* 78 */
9022     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     /* 80 */
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     /* 88 */
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9045     { Bad_Opcode },
9046     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9047     { Bad_Opcode },
9048     /* 90 */
9049     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9057     /* 98 */
9058     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9066     /* a0 */
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9075     /* a8 */
9076     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9082     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9084     /* b0 */
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9093     /* b8 */
9094     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9102     /* c0 */
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     /* c8 */
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9120     /* d0 */
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     /* d8 */
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9138     /* e0 */
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     /* e8 */
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     /* f0 */
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9160     { REG_TABLE (REG_VEX_0F38F3) },
9161     { Bad_Opcode },
9162     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9163     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9164     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9165     /* f8 */
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174   },
9175   /* VEX_0F3A */
9176   {
9177     /* 00 */
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9180     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9181     { Bad_Opcode },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9185     { Bad_Opcode },
9186     /* 08 */
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9195     /* 10 */
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9203     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9204     /* 18 */
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9206     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     /* 20 */
9214     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9215     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     /* 28 */
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     /* 30 */
9232     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9233     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9234     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     /* 38 */
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9242     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     /* 40 */
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9253     { Bad_Opcode },
9254     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9255     { Bad_Opcode },
9256     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9257     { Bad_Opcode },
9258     /* 48 */
9259     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9260     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9261     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9263     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     /* 50 */
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     /* 58 */
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9282     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9285     /* 60 */
9286     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9288     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     /* 68 */
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9299     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9301     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9302     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9303     /* 70 */
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     /* 78 */
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9318     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9319     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9320     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9321     /* 80 */
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     /* 88 */
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     /* 90 */
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     /* 98 */
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     /* a0 */
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     /* a8 */
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     /* b0 */
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     /* b8 */
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     /* c0 */
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     /* c8 */
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9410     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9411     /* d0 */
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     /* d8 */
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9429     /* e0 */
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     /* e8 */
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     /* f0 */
9448     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     /* f8 */
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465   },
9466 };
9467
9468 #define NEED_OPCODE_TABLE
9469 #include "i386-dis-evex.h"
9470 #undef NEED_OPCODE_TABLE
9471 static const struct dis386 vex_len_table[][2] = {
9472   /* VEX_LEN_0F10_P_1 */
9473   {
9474     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9475     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9476   },
9477
9478   /* VEX_LEN_0F10_P_3 */
9479   {
9480     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9481     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9482   },
9483
9484   /* VEX_LEN_0F11_P_1 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9487     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9488   },
9489
9490   /* VEX_LEN_0F11_P_3 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9493     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9494   },
9495
9496   /* VEX_LEN_0F12_P_0_M_0 */
9497   {
9498     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9499   },
9500
9501   /* VEX_LEN_0F12_P_0_M_1 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9504   },
9505
9506   /* VEX_LEN_0F12_P_2 */
9507   {
9508     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9509   },
9510
9511   /* VEX_LEN_0F13_M_0 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9514   },
9515
9516   /* VEX_LEN_0F16_P_0_M_0 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9519   },
9520
9521   /* VEX_LEN_0F16_P_0_M_1 */
9522   {
9523     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9524   },
9525
9526   /* VEX_LEN_0F16_P_2 */
9527   {
9528     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9529   },
9530
9531   /* VEX_LEN_0F17_M_0 */
9532   {
9533     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9534   },
9535
9536   /* VEX_LEN_0F2A_P_1 */
9537   {
9538     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9539     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9540   },
9541
9542   /* VEX_LEN_0F2A_P_3 */
9543   {
9544     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9545     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9546   },
9547
9548   /* VEX_LEN_0F2C_P_1 */
9549   {
9550     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9551     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9552   },
9553
9554   /* VEX_LEN_0F2C_P_3 */
9555   {
9556     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9557     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9558   },
9559
9560   /* VEX_LEN_0F2D_P_1 */
9561   {
9562     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9563     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9564   },
9565
9566   /* VEX_LEN_0F2D_P_3 */
9567   {
9568     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9569     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9570   },
9571
9572   /* VEX_LEN_0F2E_P_0 */
9573   {
9574     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9575     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9576   },
9577
9578   /* VEX_LEN_0F2E_P_2 */
9579   {
9580     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9581     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9582   },
9583
9584   /* VEX_LEN_0F2F_P_0 */
9585   {
9586     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9587     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9588   },
9589
9590   /* VEX_LEN_0F2F_P_2 */
9591   {
9592     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9593     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9594   },
9595
9596   /* VEX_LEN_0F41_P_0 */
9597   {
9598     { Bad_Opcode },
9599     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9600   },
9601   /* VEX_LEN_0F41_P_2 */
9602   {
9603     { Bad_Opcode },
9604     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9605   },
9606   /* VEX_LEN_0F42_P_0 */
9607   {
9608     { Bad_Opcode },
9609     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9610   },
9611   /* VEX_LEN_0F42_P_2 */
9612   {
9613     { Bad_Opcode },
9614     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9615   },
9616   /* VEX_LEN_0F44_P_0 */
9617   {
9618     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9619   },
9620   /* VEX_LEN_0F44_P_2 */
9621   {
9622     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9623   },
9624   /* VEX_LEN_0F45_P_0 */
9625   {
9626     { Bad_Opcode },
9627     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9628   },
9629   /* VEX_LEN_0F45_P_2 */
9630   {
9631     { Bad_Opcode },
9632     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9633   },
9634   /* VEX_LEN_0F46_P_0 */
9635   {
9636     { Bad_Opcode },
9637     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9638   },
9639   /* VEX_LEN_0F46_P_2 */
9640   {
9641     { Bad_Opcode },
9642     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9643   },
9644   /* VEX_LEN_0F47_P_0 */
9645   {
9646     { Bad_Opcode },
9647     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9648   },
9649   /* VEX_LEN_0F47_P_2 */
9650   {
9651     { Bad_Opcode },
9652     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9653   },
9654   /* VEX_LEN_0F4A_P_0 */
9655   {
9656     { Bad_Opcode },
9657     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9658   },
9659   /* VEX_LEN_0F4A_P_2 */
9660   {
9661     { Bad_Opcode },
9662     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9663   },
9664   /* VEX_LEN_0F4B_P_0 */
9665   {
9666     { Bad_Opcode },
9667     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9668   },
9669   /* VEX_LEN_0F4B_P_2 */
9670   {
9671     { Bad_Opcode },
9672     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9673   },
9674
9675   /* VEX_LEN_0F51_P_1 */
9676   {
9677     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9678     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9679   },
9680
9681   /* VEX_LEN_0F51_P_3 */
9682   {
9683     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9684     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9685   },
9686
9687   /* VEX_LEN_0F52_P_1 */
9688   {
9689     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9690     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9691   },
9692
9693   /* VEX_LEN_0F53_P_1 */
9694   {
9695     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9696     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9697   },
9698
9699   /* VEX_LEN_0F58_P_1 */
9700   {
9701     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9702     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9703   },
9704
9705   /* VEX_LEN_0F58_P_3 */
9706   {
9707     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9708     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9709   },
9710
9711   /* VEX_LEN_0F59_P_1 */
9712   {
9713     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9714     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9715   },
9716
9717   /* VEX_LEN_0F59_P_3 */
9718   {
9719     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9720     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9721   },
9722
9723   /* VEX_LEN_0F5A_P_1 */
9724   {
9725     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9726     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9727   },
9728
9729   /* VEX_LEN_0F5A_P_3 */
9730   {
9731     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9732     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9733   },
9734
9735   /* VEX_LEN_0F5C_P_1 */
9736   {
9737     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9738     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9739   },
9740
9741   /* VEX_LEN_0F5C_P_3 */
9742   {
9743     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9744     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9745   },
9746
9747   /* VEX_LEN_0F5D_P_1 */
9748   {
9749     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9750     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9751   },
9752
9753   /* VEX_LEN_0F5D_P_3 */
9754   {
9755     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9756     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9757   },
9758
9759   /* VEX_LEN_0F5E_P_1 */
9760   {
9761     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9762     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9763   },
9764
9765   /* VEX_LEN_0F5E_P_3 */
9766   {
9767     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9768     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9769   },
9770
9771   /* VEX_LEN_0F5F_P_1 */
9772   {
9773     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9774     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9775   },
9776
9777   /* VEX_LEN_0F5F_P_3 */
9778   {
9779     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9780     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9781   },
9782
9783   /* VEX_LEN_0F6E_P_2 */
9784   {
9785     { "vmovK",          { XMScalar, Edq }, 0 },
9786     { "vmovK",          { XMScalar, Edq }, 0 },
9787   },
9788
9789   /* VEX_LEN_0F7E_P_1 */
9790   {
9791     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9792     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9793   },
9794
9795   /* VEX_LEN_0F7E_P_2 */
9796   {
9797     { "vmovK",          { Edq, XMScalar }, 0 },
9798     { "vmovK",          { Edq, XMScalar }, 0 },
9799   },
9800
9801   /* VEX_LEN_0F90_P_0 */
9802   {
9803     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9804   },
9805
9806   /* VEX_LEN_0F90_P_2 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9809   },
9810
9811   /* VEX_LEN_0F91_P_0 */
9812   {
9813     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9814   },
9815
9816   /* VEX_LEN_0F91_P_2 */
9817   {
9818     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9819   },
9820
9821   /* VEX_LEN_0F92_P_0 */
9822   {
9823     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9824   },
9825
9826   /* VEX_LEN_0F92_P_2 */
9827   {
9828     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9829   },
9830
9831   /* VEX_LEN_0F92_P_3 */
9832   {
9833     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9834   },
9835
9836   /* VEX_LEN_0F93_P_0 */
9837   {
9838     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9839   },
9840
9841   /* VEX_LEN_0F93_P_2 */
9842   {
9843     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9844   },
9845
9846   /* VEX_LEN_0F93_P_3 */
9847   {
9848     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9849   },
9850
9851   /* VEX_LEN_0F98_P_0 */
9852   {
9853     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9854   },
9855
9856   /* VEX_LEN_0F98_P_2 */
9857   {
9858     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9859   },
9860
9861   /* VEX_LEN_0F99_P_0 */
9862   {
9863     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9864   },
9865
9866   /* VEX_LEN_0F99_P_2 */
9867   {
9868     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9869   },
9870
9871   /* VEX_LEN_0FAE_R_2_M_0 */
9872   {
9873     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9874   },
9875
9876   /* VEX_LEN_0FAE_R_3_M_0 */
9877   {
9878     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9879   },
9880
9881   /* VEX_LEN_0FC2_P_1 */
9882   {
9883     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9884     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9885   },
9886
9887   /* VEX_LEN_0FC2_P_3 */
9888   {
9889     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9890     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9891   },
9892
9893   /* VEX_LEN_0FC4_P_2 */
9894   {
9895     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9896   },
9897
9898   /* VEX_LEN_0FC5_P_2 */
9899   {
9900     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9901   },
9902
9903   /* VEX_LEN_0FD6_P_2 */
9904   {
9905     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9906     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9907   },
9908
9909   /* VEX_LEN_0FF7_P_2 */
9910   {
9911     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9912   },
9913
9914   /* VEX_LEN_0F3816_P_2 */
9915   {
9916     { Bad_Opcode },
9917     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9918   },
9919
9920   /* VEX_LEN_0F3819_P_2 */
9921   {
9922     { Bad_Opcode },
9923     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9924   },
9925
9926   /* VEX_LEN_0F381A_P_2_M_0 */
9927   {
9928     { Bad_Opcode },
9929     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9930   },
9931
9932   /* VEX_LEN_0F3836_P_2 */
9933   {
9934     { Bad_Opcode },
9935     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9936   },
9937
9938   /* VEX_LEN_0F3841_P_2 */
9939   {
9940     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9941   },
9942
9943   /* VEX_LEN_0F385A_P_2_M_0 */
9944   {
9945     { Bad_Opcode },
9946     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9947   },
9948
9949   /* VEX_LEN_0F38DB_P_2 */
9950   {
9951     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9952   },
9953
9954   /* VEX_LEN_0F38F2_P_0 */
9955   {
9956     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9957   },
9958
9959   /* VEX_LEN_0F38F3_R_1_P_0 */
9960   {
9961     { "blsrS",          { VexGdq, Edq }, 0 },
9962   },
9963
9964   /* VEX_LEN_0F38F3_R_2_P_0 */
9965   {
9966     { "blsmskS",        { VexGdq, Edq }, 0 },
9967   },
9968
9969   /* VEX_LEN_0F38F3_R_3_P_0 */
9970   {
9971     { "blsiS",          { VexGdq, Edq }, 0 },
9972   },
9973
9974   /* VEX_LEN_0F38F5_P_0 */
9975   {
9976     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9977   },
9978
9979   /* VEX_LEN_0F38F5_P_1 */
9980   {
9981     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9982   },
9983
9984   /* VEX_LEN_0F38F5_P_3 */
9985   {
9986     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9987   },
9988
9989   /* VEX_LEN_0F38F6_P_3 */
9990   {
9991     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9992   },
9993
9994   /* VEX_LEN_0F38F7_P_0 */
9995   {
9996     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9997   },
9998
9999   /* VEX_LEN_0F38F7_P_1 */
10000   {
10001     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10002   },
10003
10004   /* VEX_LEN_0F38F7_P_2 */
10005   {
10006     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10007   },
10008
10009   /* VEX_LEN_0F38F7_P_3 */
10010   {
10011     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10012   },
10013
10014   /* VEX_LEN_0F3A00_P_2 */
10015   {
10016     { Bad_Opcode },
10017     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10018   },
10019
10020   /* VEX_LEN_0F3A01_P_2 */
10021   {
10022     { Bad_Opcode },
10023     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10024   },
10025
10026   /* VEX_LEN_0F3A06_P_2 */
10027   {
10028     { Bad_Opcode },
10029     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10030   },
10031
10032   /* VEX_LEN_0F3A0A_P_2 */
10033   {
10034     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10035     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10036   },
10037
10038   /* VEX_LEN_0F3A0B_P_2 */
10039   {
10040     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10041     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10042   },
10043
10044   /* VEX_LEN_0F3A14_P_2 */
10045   {
10046     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10047   },
10048
10049   /* VEX_LEN_0F3A15_P_2 */
10050   {
10051     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10052   },
10053
10054   /* VEX_LEN_0F3A16_P_2  */
10055   {
10056     { "vpextrK",        { Edq, XM, Ib }, 0 },
10057   },
10058
10059   /* VEX_LEN_0F3A17_P_2 */
10060   {
10061     { "vextractps",     { Edqd, XM, Ib }, 0 },
10062   },
10063
10064   /* VEX_LEN_0F3A18_P_2 */
10065   {
10066     { Bad_Opcode },
10067     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10068   },
10069
10070   /* VEX_LEN_0F3A19_P_2 */
10071   {
10072     { Bad_Opcode },
10073     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10074   },
10075
10076   /* VEX_LEN_0F3A20_P_2 */
10077   {
10078     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10079   },
10080
10081   /* VEX_LEN_0F3A21_P_2 */
10082   {
10083     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10084   },
10085
10086   /* VEX_LEN_0F3A22_P_2 */
10087   {
10088     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10089   },
10090
10091   /* VEX_LEN_0F3A30_P_2 */
10092   {
10093     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10094   },
10095
10096   /* VEX_LEN_0F3A31_P_2 */
10097   {
10098     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10099   },
10100
10101   /* VEX_LEN_0F3A32_P_2 */
10102   {
10103     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10104   },
10105
10106   /* VEX_LEN_0F3A33_P_2 */
10107   {
10108     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10109   },
10110
10111   /* VEX_LEN_0F3A38_P_2 */
10112   {
10113     { Bad_Opcode },
10114     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10115   },
10116
10117   /* VEX_LEN_0F3A39_P_2 */
10118   {
10119     { Bad_Opcode },
10120     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10121   },
10122
10123   /* VEX_LEN_0F3A41_P_2 */
10124   {
10125     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10126   },
10127
10128   /* VEX_LEN_0F3A46_P_2 */
10129   {
10130     { Bad_Opcode },
10131     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10132   },
10133
10134   /* VEX_LEN_0F3A60_P_2 */
10135   {
10136     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10137   },
10138
10139   /* VEX_LEN_0F3A61_P_2 */
10140   {
10141     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10142   },
10143
10144   /* VEX_LEN_0F3A62_P_2 */
10145   {
10146     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10147   },
10148
10149   /* VEX_LEN_0F3A63_P_2 */
10150   {
10151     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10152   },
10153
10154   /* VEX_LEN_0F3A6A_P_2 */
10155   {
10156     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10157   },
10158
10159   /* VEX_LEN_0F3A6B_P_2 */
10160   {
10161     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10162   },
10163
10164   /* VEX_LEN_0F3A6E_P_2 */
10165   {
10166     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10167   },
10168
10169   /* VEX_LEN_0F3A6F_P_2 */
10170   {
10171     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10172   },
10173
10174   /* VEX_LEN_0F3A7A_P_2 */
10175   {
10176     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10177   },
10178
10179   /* VEX_LEN_0F3A7B_P_2 */
10180   {
10181     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10182   },
10183
10184   /* VEX_LEN_0F3A7E_P_2 */
10185   {
10186     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10187   },
10188
10189   /* VEX_LEN_0F3A7F_P_2 */
10190   {
10191     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10192   },
10193
10194   /* VEX_LEN_0F3ADF_P_2 */
10195   {
10196     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10197   },
10198
10199   /* VEX_LEN_0F3AF0_P_3 */
10200   {
10201     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10202   },
10203
10204   /* VEX_LEN_0FXOP_08_CC */
10205   {
10206      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10207   },
10208
10209   /* VEX_LEN_0FXOP_08_CD */
10210   {
10211      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10212   },
10213
10214   /* VEX_LEN_0FXOP_08_CE */
10215   {
10216      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10217   },
10218
10219   /* VEX_LEN_0FXOP_08_CF */
10220   {
10221      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10222   },
10223
10224   /* VEX_LEN_0FXOP_08_EC */
10225   {
10226      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10227   },
10228
10229   /* VEX_LEN_0FXOP_08_ED */
10230   {
10231      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10232   },
10233
10234   /* VEX_LEN_0FXOP_08_EE */
10235   {
10236      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10237   },
10238
10239   /* VEX_LEN_0FXOP_08_EF */
10240   {
10241      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10242   },
10243
10244   /* VEX_LEN_0FXOP_09_80 */
10245   {
10246     { "vfrczps",        { XM, EXxmm }, 0 },
10247     { "vfrczps",        { XM, EXymmq }, 0 },
10248   },
10249
10250   /* VEX_LEN_0FXOP_09_81 */
10251   {
10252     { "vfrczpd",        { XM, EXxmm }, 0 },
10253     { "vfrczpd",        { XM, EXymmq }, 0 },
10254   },
10255 };
10256
10257 static const struct dis386 vex_w_table[][2] = {
10258   {
10259     /* VEX_W_0F10_P_0 */
10260     { "vmovups",        { XM, EXx }, 0 },
10261   },
10262   {
10263     /* VEX_W_0F10_P_1 */
10264     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10265   },
10266   {
10267     /* VEX_W_0F10_P_2 */
10268     { "vmovupd",        { XM, EXx }, 0 },
10269   },
10270   {
10271     /* VEX_W_0F10_P_3 */
10272     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10273   },
10274   {
10275     /* VEX_W_0F11_P_0 */
10276     { "vmovups",        { EXxS, XM }, 0 },
10277   },
10278   {
10279     /* VEX_W_0F11_P_1 */
10280     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10281   },
10282   {
10283     /* VEX_W_0F11_P_2 */
10284     { "vmovupd",        { EXxS, XM }, 0 },
10285   },
10286   {
10287     /* VEX_W_0F11_P_3 */
10288     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10289   },
10290   {
10291     /* VEX_W_0F12_P_0_M_0 */
10292     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10293   },
10294   {
10295     /* VEX_W_0F12_P_0_M_1 */
10296     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10297   },
10298   {
10299     /* VEX_W_0F12_P_1 */
10300     { "vmovsldup",      { XM, EXx }, 0 },
10301   },
10302   {
10303     /* VEX_W_0F12_P_2 */
10304     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10305   },
10306   {
10307     /* VEX_W_0F12_P_3 */
10308     { "vmovddup",       { XM, EXymmq }, 0 },
10309   },
10310   {
10311     /* VEX_W_0F13_M_0 */
10312     { "vmovlpX",        { EXq, XM }, 0 },
10313   },
10314   {
10315     /* VEX_W_0F14 */
10316     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10317   },
10318   {
10319     /* VEX_W_0F15 */
10320     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10321   },
10322   {
10323     /* VEX_W_0F16_P_0_M_0 */
10324     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10325   },
10326   {
10327     /* VEX_W_0F16_P_0_M_1 */
10328     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10329   },
10330   {
10331     /* VEX_W_0F16_P_1 */
10332     { "vmovshdup",      { XM, EXx }, 0 },
10333   },
10334   {
10335     /* VEX_W_0F16_P_2 */
10336     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10337   },
10338   {
10339     /* VEX_W_0F17_M_0 */
10340     { "vmovhpX",        { EXq, XM }, 0 },
10341   },
10342   {
10343     /* VEX_W_0F28 */
10344     { "vmovapX",        { XM, EXx }, 0 },
10345   },
10346   {
10347     /* VEX_W_0F29 */
10348     { "vmovapX",        { EXxS, XM }, 0 },
10349   },
10350   {
10351     /* VEX_W_0F2B_M_0 */
10352     { "vmovntpX",       { Mx, XM }, 0 },
10353   },
10354   {
10355     /* VEX_W_0F2E_P_0 */
10356     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10357   },
10358   {
10359     /* VEX_W_0F2E_P_2 */
10360     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10361   },
10362   {
10363     /* VEX_W_0F2F_P_0 */
10364     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10365   },
10366   {
10367     /* VEX_W_0F2F_P_2 */
10368     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10369   },
10370   {
10371     /* VEX_W_0F41_P_0_LEN_1 */
10372     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10373     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10374   },
10375   {
10376     /* VEX_W_0F41_P_2_LEN_1 */
10377     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10378     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10379   },
10380   {
10381     /* VEX_W_0F42_P_0_LEN_1 */
10382     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10383     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10384   },
10385   {
10386     /* VEX_W_0F42_P_2_LEN_1 */
10387     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10388     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10389   },
10390   {
10391     /* VEX_W_0F44_P_0_LEN_0 */
10392     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10393     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10394   },
10395   {
10396     /* VEX_W_0F44_P_2_LEN_0 */
10397     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10398     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10399   },
10400   {
10401     /* VEX_W_0F45_P_0_LEN_1 */
10402     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10403     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10404   },
10405   {
10406     /* VEX_W_0F45_P_2_LEN_1 */
10407     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10408     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10409   },
10410   {
10411     /* VEX_W_0F46_P_0_LEN_1 */
10412     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10413     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10414   },
10415   {
10416     /* VEX_W_0F46_P_2_LEN_1 */
10417     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10418     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10419   },
10420   {
10421     /* VEX_W_0F47_P_0_LEN_1 */
10422     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10423     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10424   },
10425   {
10426     /* VEX_W_0F47_P_2_LEN_1 */
10427     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10428     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10429   },
10430   {
10431     /* VEX_W_0F4A_P_0_LEN_1 */
10432     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10433     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10434   },
10435   {
10436     /* VEX_W_0F4A_P_2_LEN_1 */
10437     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10438     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10439   },
10440   {
10441     /* VEX_W_0F4B_P_0_LEN_1 */
10442     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10443     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10444   },
10445   {
10446     /* VEX_W_0F4B_P_2_LEN_1 */
10447     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10448   },
10449   {
10450     /* VEX_W_0F50_M_0 */
10451     { "vmovmskpX",      { Gdq, XS }, 0 },
10452   },
10453   {
10454     /* VEX_W_0F51_P_0 */
10455     { "vsqrtps",        { XM, EXx }, 0 },
10456   },
10457   {
10458     /* VEX_W_0F51_P_1 */
10459     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10460   },
10461   {
10462     /* VEX_W_0F51_P_2  */
10463     { "vsqrtpd",        { XM, EXx }, 0 },
10464   },
10465   {
10466     /* VEX_W_0F51_P_3 */
10467     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10468   },
10469   {
10470     /* VEX_W_0F52_P_0 */
10471     { "vrsqrtps",       { XM, EXx }, 0 },
10472   },
10473   {
10474     /* VEX_W_0F52_P_1 */
10475     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F53_P_0  */
10479     { "vrcpps",         { XM, EXx }, 0 },
10480   },
10481   {
10482     /* VEX_W_0F53_P_1  */
10483     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F58_P_0  */
10487     { "vaddps",         { XM, Vex, EXx }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F58_P_1  */
10491     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F58_P_2  */
10495     { "vaddpd",         { XM, Vex, EXx }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F58_P_3  */
10499     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10500   },
10501   {
10502     /* VEX_W_0F59_P_0  */
10503     { "vmulps",         { XM, Vex, EXx }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F59_P_1  */
10507     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F59_P_2  */
10511     { "vmulpd",         { XM, Vex, EXx }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F59_P_3  */
10515     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F5A_P_0  */
10519     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F5A_P_1  */
10523     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F5A_P_3  */
10527     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F5B_P_0  */
10531     { "vcvtdq2ps",      { XM, EXx }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F5B_P_1  */
10535     { "vcvttps2dq",     { XM, EXx }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F5B_P_2  */
10539     { "vcvtps2dq",      { XM, EXx }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F5C_P_0  */
10543     { "vsubps",         { XM, Vex, EXx }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F5C_P_1  */
10547     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F5C_P_2  */
10551     { "vsubpd",         { XM, Vex, EXx }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F5C_P_3  */
10555     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F5D_P_0  */
10559     { "vminps",         { XM, Vex, EXx }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F5D_P_1  */
10563     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F5D_P_2  */
10567     { "vminpd",         { XM, Vex, EXx }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F5D_P_3  */
10571     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F5E_P_0  */
10575     { "vdivps",         { XM, Vex, EXx }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F5E_P_1  */
10579     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F5E_P_2  */
10583     { "vdivpd",         { XM, Vex, EXx }, 0 },
10584   },
10585   {
10586     /* VEX_W_0F5E_P_3  */
10587     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F5F_P_0  */
10591     { "vmaxps",         { XM, Vex, EXx }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F5F_P_1  */
10595     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F5F_P_2  */
10599     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F5F_P_3  */
10603     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F60_P_2  */
10607     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F61_P_2  */
10611     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F62_P_2  */
10615     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F63_P_2  */
10619     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F64_P_2  */
10623     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F65_P_2  */
10627     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F66_P_2  */
10631     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F67_P_2  */
10635     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10636   },
10637   {
10638     /* VEX_W_0F68_P_2  */
10639     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10640   },
10641   {
10642     /* VEX_W_0F69_P_2  */
10643     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10644   },
10645   {
10646     /* VEX_W_0F6A_P_2  */
10647     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10648   },
10649   {
10650     /* VEX_W_0F6B_P_2  */
10651     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10652   },
10653   {
10654     /* VEX_W_0F6C_P_2  */
10655     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10656   },
10657   {
10658     /* VEX_W_0F6D_P_2  */
10659     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10660   },
10661   {
10662     /* VEX_W_0F6F_P_1  */
10663     { "vmovdqu",        { XM, EXx }, 0 },
10664   },
10665   {
10666     /* VEX_W_0F6F_P_2  */
10667     { "vmovdqa",        { XM, EXx }, 0 },
10668   },
10669   {
10670     /* VEX_W_0F70_P_1 */
10671     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10672   },
10673   {
10674     /* VEX_W_0F70_P_2 */
10675     { "vpshufd",        { XM, EXx, Ib }, 0 },
10676   },
10677   {
10678     /* VEX_W_0F70_P_3 */
10679     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10680   },
10681   {
10682     /* VEX_W_0F71_R_2_P_2  */
10683     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10684   },
10685   {
10686     /* VEX_W_0F71_R_4_P_2  */
10687     { "vpsraw",         { Vex, XS, Ib }, 0 },
10688   },
10689   {
10690     /* VEX_W_0F71_R_6_P_2  */
10691     { "vpsllw",         { Vex, XS, Ib }, 0 },
10692   },
10693   {
10694     /* VEX_W_0F72_R_2_P_2  */
10695     { "vpsrld",         { Vex, XS, Ib }, 0 },
10696   },
10697   {
10698     /* VEX_W_0F72_R_4_P_2  */
10699     { "vpsrad",         { Vex, XS, Ib }, 0 },
10700   },
10701   {
10702     /* VEX_W_0F72_R_6_P_2  */
10703     { "vpslld",         { Vex, XS, Ib }, 0 },
10704   },
10705   {
10706     /* VEX_W_0F73_R_2_P_2  */
10707     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10708   },
10709   {
10710     /* VEX_W_0F73_R_3_P_2  */
10711     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10712   },
10713   {
10714     /* VEX_W_0F73_R_6_P_2  */
10715     { "vpsllq",         { Vex, XS, Ib }, 0 },
10716   },
10717   {
10718     /* VEX_W_0F73_R_7_P_2  */
10719     { "vpslldq",        { Vex, XS, Ib }, 0 },
10720   },
10721   {
10722     /* VEX_W_0F74_P_2 */
10723     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10724   },
10725   {
10726     /* VEX_W_0F75_P_2 */
10727     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10728   },
10729   {
10730     /* VEX_W_0F76_P_2 */
10731     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10732   },
10733   {
10734     /* VEX_W_0F77_P_0 */
10735     { "",               { VZERO }, 0 },
10736   },
10737   {
10738     /* VEX_W_0F7C_P_2 */
10739     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10740   },
10741   {
10742     /* VEX_W_0F7C_P_3 */
10743     { "vhaddps",        { XM, Vex, EXx }, 0 },
10744   },
10745   {
10746     /* VEX_W_0F7D_P_2 */
10747     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10748   },
10749   {
10750     /* VEX_W_0F7D_P_3 */
10751     { "vhsubps",        { XM, Vex, EXx }, 0 },
10752   },
10753   {
10754     /* VEX_W_0F7E_P_1 */
10755     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10756   },
10757   {
10758     /* VEX_W_0F7F_P_1 */
10759     { "vmovdqu",        { EXxS, XM }, 0 },
10760   },
10761   {
10762     /* VEX_W_0F7F_P_2 */
10763     { "vmovdqa",        { EXxS, XM }, 0 },
10764   },
10765   {
10766     /* VEX_W_0F90_P_0_LEN_0 */
10767     { "kmovw",          { MaskG, MaskE }, 0 },
10768     { "kmovq",          { MaskG, MaskE }, 0 },
10769   },
10770   {
10771     /* VEX_W_0F90_P_2_LEN_0 */
10772     { "kmovb",          { MaskG, MaskBDE }, 0 },
10773     { "kmovd",          { MaskG, MaskBDE }, 0 },
10774   },
10775   {
10776     /* VEX_W_0F91_P_0_LEN_0 */
10777     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10778     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10779   },
10780   {
10781     /* VEX_W_0F91_P_2_LEN_0 */
10782     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10783     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10784   },
10785   {
10786     /* VEX_W_0F92_P_0_LEN_0 */
10787     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10788   },
10789   {
10790     /* VEX_W_0F92_P_2_LEN_0 */
10791     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10792   },
10793   {
10794     /* VEX_W_0F92_P_3_LEN_0 */
10795     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10796     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10797   },
10798   {
10799     /* VEX_W_0F93_P_0_LEN_0 */
10800     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10801   },
10802   {
10803     /* VEX_W_0F93_P_2_LEN_0 */
10804     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10805   },
10806   {
10807     /* VEX_W_0F93_P_3_LEN_0 */
10808     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10809     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10810   },
10811   {
10812     /* VEX_W_0F98_P_0_LEN_0 */
10813     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10814     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10815   },
10816   {
10817     /* VEX_W_0F98_P_2_LEN_0 */
10818     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10819     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10820   },
10821   {
10822     /* VEX_W_0F99_P_0_LEN_0 */
10823     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10824     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10825   },
10826   {
10827     /* VEX_W_0F99_P_2_LEN_0 */
10828     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10829     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10830   },
10831   {
10832     /* VEX_W_0FAE_R_2_M_0 */
10833     { "vldmxcsr",       { Md }, 0 },
10834   },
10835   {
10836     /* VEX_W_0FAE_R_3_M_0 */
10837     { "vstmxcsr",       { Md }, 0 },
10838   },
10839   {
10840     /* VEX_W_0FC2_P_0 */
10841     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10842   },
10843   {
10844     /* VEX_W_0FC2_P_1 */
10845     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10846   },
10847   {
10848     /* VEX_W_0FC2_P_2 */
10849     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10850   },
10851   {
10852     /* VEX_W_0FC2_P_3 */
10853     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10854   },
10855   {
10856     /* VEX_W_0FC4_P_2 */
10857     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10858   },
10859   {
10860     /* VEX_W_0FC5_P_2 */
10861     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10862   },
10863   {
10864     /* VEX_W_0FD0_P_2 */
10865     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10866   },
10867   {
10868     /* VEX_W_0FD0_P_3 */
10869     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10870   },
10871   {
10872     /* VEX_W_0FD1_P_2 */
10873     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10874   },
10875   {
10876     /* VEX_W_0FD2_P_2 */
10877     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10878   },
10879   {
10880     /* VEX_W_0FD3_P_2 */
10881     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10882   },
10883   {
10884     /* VEX_W_0FD4_P_2 */
10885     { "vpaddq",         { XM, Vex, EXx }, 0 },
10886   },
10887   {
10888     /* VEX_W_0FD5_P_2 */
10889     { "vpmullw",        { XM, Vex, EXx }, 0 },
10890   },
10891   {
10892     /* VEX_W_0FD6_P_2 */
10893     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10894   },
10895   {
10896     /* VEX_W_0FD7_P_2_M_1 */
10897     { "vpmovmskb",      { Gdq, XS }, 0 },
10898   },
10899   {
10900     /* VEX_W_0FD8_P_2 */
10901     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10902   },
10903   {
10904     /* VEX_W_0FD9_P_2 */
10905     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10906   },
10907   {
10908     /* VEX_W_0FDA_P_2 */
10909     { "vpminub",        { XM, Vex, EXx }, 0 },
10910   },
10911   {
10912     /* VEX_W_0FDB_P_2 */
10913     { "vpand",          { XM, Vex, EXx }, 0 },
10914   },
10915   {
10916     /* VEX_W_0FDC_P_2 */
10917     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10918   },
10919   {
10920     /* VEX_W_0FDD_P_2 */
10921     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10922   },
10923   {
10924     /* VEX_W_0FDE_P_2 */
10925     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10926   },
10927   {
10928     /* VEX_W_0FDF_P_2 */
10929     { "vpandn",         { XM, Vex, EXx }, 0 },
10930   },
10931   {
10932     /* VEX_W_0FE0_P_2  */
10933     { "vpavgb",         { XM, Vex, EXx }, 0 },
10934   },
10935   {
10936     /* VEX_W_0FE1_P_2  */
10937     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10938   },
10939   {
10940     /* VEX_W_0FE2_P_2  */
10941     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10942   },
10943   {
10944     /* VEX_W_0FE3_P_2  */
10945     { "vpavgw",         { XM, Vex, EXx }, 0 },
10946   },
10947   {
10948     /* VEX_W_0FE4_P_2  */
10949     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10950   },
10951   {
10952     /* VEX_W_0FE5_P_2  */
10953     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10954   },
10955   {
10956     /* VEX_W_0FE6_P_1  */
10957     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10958   },
10959   {
10960     /* VEX_W_0FE6_P_2  */
10961     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10962   },
10963   {
10964     /* VEX_W_0FE6_P_3  */
10965     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10966   },
10967   {
10968     /* VEX_W_0FE7_P_2_M_0 */
10969     { "vmovntdq",       { Mx, XM }, 0 },
10970   },
10971   {
10972     /* VEX_W_0FE8_P_2  */
10973     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10974   },
10975   {
10976     /* VEX_W_0FE9_P_2  */
10977     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10978   },
10979   {
10980     /* VEX_W_0FEA_P_2  */
10981     { "vpminsw",        { XM, Vex, EXx }, 0 },
10982   },
10983   {
10984     /* VEX_W_0FEB_P_2  */
10985     { "vpor",           { XM, Vex, EXx }, 0 },
10986   },
10987   {
10988     /* VEX_W_0FEC_P_2  */
10989     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10990   },
10991   {
10992     /* VEX_W_0FED_P_2  */
10993     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10994   },
10995   {
10996     /* VEX_W_0FEE_P_2  */
10997     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10998   },
10999   {
11000     /* VEX_W_0FEF_P_2  */
11001     { "vpxor",          { XM, Vex, EXx }, 0 },
11002   },
11003   {
11004     /* VEX_W_0FF0_P_3_M_0 */
11005     { "vlddqu",         { XM, M }, 0 },
11006   },
11007   {
11008     /* VEX_W_0FF1_P_2 */
11009     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11010   },
11011   {
11012     /* VEX_W_0FF2_P_2 */
11013     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11014   },
11015   {
11016     /* VEX_W_0FF3_P_2 */
11017     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11018   },
11019   {
11020     /* VEX_W_0FF4_P_2 */
11021     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11022   },
11023   {
11024     /* VEX_W_0FF5_P_2 */
11025     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11026   },
11027   {
11028     /* VEX_W_0FF6_P_2 */
11029     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11030   },
11031   {
11032     /* VEX_W_0FF7_P_2 */
11033     { "vmaskmovdqu",    { XM, XS }, 0 },
11034   },
11035   {
11036     /* VEX_W_0FF8_P_2 */
11037     { "vpsubb",         { XM, Vex, EXx }, 0 },
11038   },
11039   {
11040     /* VEX_W_0FF9_P_2 */
11041     { "vpsubw",         { XM, Vex, EXx }, 0 },
11042   },
11043   {
11044     /* VEX_W_0FFA_P_2 */
11045     { "vpsubd",         { XM, Vex, EXx }, 0 },
11046   },
11047   {
11048     /* VEX_W_0FFB_P_2 */
11049     { "vpsubq",         { XM, Vex, EXx }, 0 },
11050   },
11051   {
11052     /* VEX_W_0FFC_P_2 */
11053     { "vpaddb",         { XM, Vex, EXx }, 0 },
11054   },
11055   {
11056     /* VEX_W_0FFD_P_2 */
11057     { "vpaddw",         { XM, Vex, EXx }, 0 },
11058   },
11059   {
11060     /* VEX_W_0FFE_P_2 */
11061     { "vpaddd",         { XM, Vex, EXx }, 0 },
11062   },
11063   {
11064     /* VEX_W_0F3800_P_2  */
11065     { "vpshufb",        { XM, Vex, EXx }, 0 },
11066   },
11067   {
11068     /* VEX_W_0F3801_P_2  */
11069     { "vphaddw",        { XM, Vex, EXx }, 0 },
11070   },
11071   {
11072     /* VEX_W_0F3802_P_2  */
11073     { "vphaddd",        { XM, Vex, EXx }, 0 },
11074   },
11075   {
11076     /* VEX_W_0F3803_P_2  */
11077     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11078   },
11079   {
11080     /* VEX_W_0F3804_P_2  */
11081     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11082   },
11083   {
11084     /* VEX_W_0F3805_P_2  */
11085     { "vphsubw",        { XM, Vex, EXx }, 0 },
11086   },
11087   {
11088     /* VEX_W_0F3806_P_2  */
11089     { "vphsubd",        { XM, Vex, EXx }, 0 },
11090   },
11091   {
11092     /* VEX_W_0F3807_P_2  */
11093     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11094   },
11095   {
11096     /* VEX_W_0F3808_P_2  */
11097     { "vpsignb",        { XM, Vex, EXx }, 0 },
11098   },
11099   {
11100     /* VEX_W_0F3809_P_2  */
11101     { "vpsignw",        { XM, Vex, EXx }, 0 },
11102   },
11103   {
11104     /* VEX_W_0F380A_P_2  */
11105     { "vpsignd",        { XM, Vex, EXx }, 0 },
11106   },
11107   {
11108     /* VEX_W_0F380B_P_2  */
11109     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11110   },
11111   {
11112     /* VEX_W_0F380C_P_2  */
11113     { "vpermilps",      { XM, Vex, EXx }, 0 },
11114   },
11115   {
11116     /* VEX_W_0F380D_P_2  */
11117     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0F380E_P_2  */
11121     { "vtestps",        { XM, EXx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0F380F_P_2  */
11125     { "vtestpd",        { XM, EXx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0F3816_P_2  */
11129     { "vpermps",        { XM, Vex, EXx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0F3817_P_2 */
11133     { "vptest",         { XM, EXx }, 0 },
11134   },
11135   {
11136     /* VEX_W_0F3818_P_2 */
11137     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11138   },
11139   {
11140     /* VEX_W_0F3819_P_2 */
11141     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11142   },
11143   {
11144     /* VEX_W_0F381A_P_2_M_0 */
11145     { "vbroadcastf128", { XM, Mxmm }, 0 },
11146   },
11147   {
11148     /* VEX_W_0F381C_P_2 */
11149     { "vpabsb",         { XM, EXx }, 0 },
11150   },
11151   {
11152     /* VEX_W_0F381D_P_2 */
11153     { "vpabsw",         { XM, EXx }, 0 },
11154   },
11155   {
11156     /* VEX_W_0F381E_P_2 */
11157     { "vpabsd",         { XM, EXx }, 0 },
11158   },
11159   {
11160     /* VEX_W_0F3820_P_2 */
11161     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11162   },
11163   {
11164     /* VEX_W_0F3821_P_2 */
11165     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11166   },
11167   {
11168     /* VEX_W_0F3822_P_2 */
11169     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11170   },
11171   {
11172     /* VEX_W_0F3823_P_2 */
11173     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11174   },
11175   {
11176     /* VEX_W_0F3824_P_2 */
11177     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11178   },
11179   {
11180     /* VEX_W_0F3825_P_2 */
11181     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11182   },
11183   {
11184     /* VEX_W_0F3828_P_2 */
11185     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0F3829_P_2 */
11189     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11190   },
11191   {
11192     /* VEX_W_0F382A_P_2_M_0 */
11193     { "vmovntdqa",      { XM, Mx }, 0 },
11194   },
11195   {
11196     /* VEX_W_0F382B_P_2 */
11197     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F382C_P_2_M_0 */
11201     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11202   },
11203   {
11204     /* VEX_W_0F382D_P_2_M_0 */
11205     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11206   },
11207   {
11208     /* VEX_W_0F382E_P_2_M_0 */
11209     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11210   },
11211   {
11212     /* VEX_W_0F382F_P_2_M_0 */
11213     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11214   },
11215   {
11216     /* VEX_W_0F3830_P_2 */
11217     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11218   },
11219   {
11220     /* VEX_W_0F3831_P_2 */
11221     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11222   },
11223   {
11224     /* VEX_W_0F3832_P_2 */
11225     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11226   },
11227   {
11228     /* VEX_W_0F3833_P_2 */
11229     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11230   },
11231   {
11232     /* VEX_W_0F3834_P_2 */
11233     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11234   },
11235   {
11236     /* VEX_W_0F3835_P_2 */
11237     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11238   },
11239   {
11240     /* VEX_W_0F3836_P_2  */
11241     { "vpermd",         { XM, Vex, EXx }, 0 },
11242   },
11243   {
11244     /* VEX_W_0F3837_P_2 */
11245     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11246   },
11247   {
11248     /* VEX_W_0F3838_P_2 */
11249     { "vpminsb",        { XM, Vex, EXx }, 0 },
11250   },
11251   {
11252     /* VEX_W_0F3839_P_2 */
11253     { "vpminsd",        { XM, Vex, EXx }, 0 },
11254   },
11255   {
11256     /* VEX_W_0F383A_P_2 */
11257     { "vpminuw",        { XM, Vex, EXx }, 0 },
11258   },
11259   {
11260     /* VEX_W_0F383B_P_2 */
11261     { "vpminud",        { XM, Vex, EXx }, 0 },
11262   },
11263   {
11264     /* VEX_W_0F383C_P_2 */
11265     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11266   },
11267   {
11268     /* VEX_W_0F383D_P_2 */
11269     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11270   },
11271   {
11272     /* VEX_W_0F383E_P_2 */
11273     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11274   },
11275   {
11276     /* VEX_W_0F383F_P_2 */
11277     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11278   },
11279   {
11280     /* VEX_W_0F3840_P_2 */
11281     { "vpmulld",        { XM, Vex, EXx }, 0 },
11282   },
11283   {
11284     /* VEX_W_0F3841_P_2 */
11285     { "vphminposuw",    { XM, EXx }, 0 },
11286   },
11287   {
11288     /* VEX_W_0F3846_P_2 */
11289     { "vpsravd",        { XM, Vex, EXx }, 0 },
11290   },
11291   {
11292     /* VEX_W_0F3858_P_2 */
11293     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11294   },
11295   {
11296     /* VEX_W_0F3859_P_2 */
11297     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11298   },
11299   {
11300     /* VEX_W_0F385A_P_2_M_0 */
11301     { "vbroadcasti128", { XM, Mxmm }, 0 },
11302   },
11303   {
11304     /* VEX_W_0F3878_P_2 */
11305     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11306   },
11307   {
11308     /* VEX_W_0F3879_P_2 */
11309     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11310   },
11311   {
11312     /* VEX_W_0F38CF_P_2 */
11313     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11314   },
11315   {
11316     /* VEX_W_0F38DB_P_2 */
11317     { "vaesimc",        { XM, EXx }, 0 },
11318   },
11319   {
11320     /* VEX_W_0F3A00_P_2 */
11321     { Bad_Opcode },
11322     { "vpermq",         { XM, EXx, Ib }, 0 },
11323   },
11324   {
11325     /* VEX_W_0F3A01_P_2 */
11326     { Bad_Opcode },
11327     { "vpermpd",        { XM, EXx, Ib }, 0 },
11328   },
11329   {
11330     /* VEX_W_0F3A02_P_2 */
11331     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11332   },
11333   {
11334     /* VEX_W_0F3A04_P_2 */
11335     { "vpermilps",      { XM, EXx, Ib }, 0 },
11336   },
11337   {
11338     /* VEX_W_0F3A05_P_2 */
11339     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11340   },
11341   {
11342     /* VEX_W_0F3A06_P_2 */
11343     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11344   },
11345   {
11346     /* VEX_W_0F3A08_P_2 */
11347     { "vroundps",       { XM, EXx, Ib }, 0 },
11348   },
11349   {
11350     /* VEX_W_0F3A09_P_2 */
11351     { "vroundpd",       { XM, EXx, Ib }, 0 },
11352   },
11353   {
11354     /* VEX_W_0F3A0A_P_2 */
11355     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11356   },
11357   {
11358     /* VEX_W_0F3A0B_P_2 */
11359     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11360   },
11361   {
11362     /* VEX_W_0F3A0C_P_2 */
11363     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11364   },
11365   {
11366     /* VEX_W_0F3A0D_P_2 */
11367     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11368   },
11369   {
11370     /* VEX_W_0F3A0E_P_2 */
11371     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11372   },
11373   {
11374     /* VEX_W_0F3A0F_P_2 */
11375     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F3A14_P_2 */
11379     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11380   },
11381   {
11382     /* VEX_W_0F3A15_P_2 */
11383     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F3A18_P_2 */
11387     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11388   },
11389   {
11390     /* VEX_W_0F3A19_P_2 */
11391     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11392   },
11393   {
11394     /* VEX_W_0F3A20_P_2 */
11395     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11396   },
11397   {
11398     /* VEX_W_0F3A21_P_2 */
11399     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11400   },
11401   {
11402     /* VEX_W_0F3A30_P_2_LEN_0 */
11403     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11404     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11405   },
11406   {
11407     /* VEX_W_0F3A31_P_2_LEN_0 */
11408     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11409     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11410   },
11411   {
11412     /* VEX_W_0F3A32_P_2_LEN_0 */
11413     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11414     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11415   },
11416   {
11417     /* VEX_W_0F3A33_P_2_LEN_0 */
11418     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11419     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11420   },
11421   {
11422     /* VEX_W_0F3A38_P_2 */
11423     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11424   },
11425   {
11426     /* VEX_W_0F3A39_P_2 */
11427     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11428   },
11429   {
11430     /* VEX_W_0F3A40_P_2 */
11431     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11432   },
11433   {
11434     /* VEX_W_0F3A41_P_2 */
11435     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11436   },
11437   {
11438     /* VEX_W_0F3A42_P_2 */
11439     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3A46_P_2 */
11443     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11444   },
11445   {
11446     /* VEX_W_0F3A48_P_2 */
11447     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11448     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11449   },
11450   {
11451     /* VEX_W_0F3A49_P_2 */
11452     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11453     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11454   },
11455   {
11456     /* VEX_W_0F3A4A_P_2 */
11457     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11458   },
11459   {
11460     /* VEX_W_0F3A4B_P_2 */
11461     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11462   },
11463   {
11464     /* VEX_W_0F3A4C_P_2 */
11465     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11466   },
11467   {
11468     /* VEX_W_0F3A62_P_2 */
11469     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11470   },
11471   {
11472     /* VEX_W_0F3A63_P_2 */
11473     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11474   },
11475   {
11476     /* VEX_W_0F3ACE_P_2 */
11477     { Bad_Opcode },
11478     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11479   },
11480   {
11481     /* VEX_W_0F3ACF_P_2 */
11482     { Bad_Opcode },
11483     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11484   },
11485   {
11486     /* VEX_W_0F3ADF_P_2 */
11487     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11488   },
11489 #define NEED_VEX_W_TABLE
11490 #include "i386-dis-evex.h"
11491 #undef NEED_VEX_W_TABLE
11492 };
11493
11494 static const struct dis386 mod_table[][2] = {
11495   {
11496     /* MOD_8D */
11497     { "leaS",           { Gv, M }, 0 },
11498   },
11499   {
11500     /* MOD_C6_REG_7 */
11501     { Bad_Opcode },
11502     { RM_TABLE (RM_C6_REG_7) },
11503   },
11504   {
11505     /* MOD_C7_REG_7 */
11506     { Bad_Opcode },
11507     { RM_TABLE (RM_C7_REG_7) },
11508   },
11509   {
11510     /* MOD_FF_REG_3 */
11511     { "Jcall^", { indirEp }, 0 },
11512   },
11513   {
11514     /* MOD_FF_REG_5 */
11515     { "Jjmp^", { indirEp }, 0 },
11516   },
11517   {
11518     /* MOD_0F01_REG_0 */
11519     { X86_64_TABLE (X86_64_0F01_REG_0) },
11520     { RM_TABLE (RM_0F01_REG_0) },
11521   },
11522   {
11523     /* MOD_0F01_REG_1 */
11524     { X86_64_TABLE (X86_64_0F01_REG_1) },
11525     { RM_TABLE (RM_0F01_REG_1) },
11526   },
11527   {
11528     /* MOD_0F01_REG_2 */
11529     { X86_64_TABLE (X86_64_0F01_REG_2) },
11530     { RM_TABLE (RM_0F01_REG_2) },
11531   },
11532   {
11533     /* MOD_0F01_REG_3 */
11534     { X86_64_TABLE (X86_64_0F01_REG_3) },
11535     { RM_TABLE (RM_0F01_REG_3) },
11536   },
11537   {
11538     /* MOD_0F01_REG_5 */
11539     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11540     { RM_TABLE (RM_0F01_REG_5) },
11541   },
11542   {
11543     /* MOD_0F01_REG_7 */
11544     { "invlpg",         { Mb }, 0 },
11545     { RM_TABLE (RM_0F01_REG_7) },
11546   },
11547   {
11548     /* MOD_0F12_PREFIX_0 */
11549     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11550     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11551   },
11552   {
11553     /* MOD_0F13 */
11554     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11555   },
11556   {
11557     /* MOD_0F16_PREFIX_0 */
11558     { "movhps",         { XM, EXq }, 0 },
11559     { "movlhps",        { XM, EXq }, 0 },
11560   },
11561   {
11562     /* MOD_0F17 */
11563     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11564   },
11565   {
11566     /* MOD_0F18_REG_0 */
11567     { "prefetchnta",    { Mb }, 0 },
11568   },
11569   {
11570     /* MOD_0F18_REG_1 */
11571     { "prefetcht0",     { Mb }, 0 },
11572   },
11573   {
11574     /* MOD_0F18_REG_2 */
11575     { "prefetcht1",     { Mb }, 0 },
11576   },
11577   {
11578     /* MOD_0F18_REG_3 */
11579     { "prefetcht2",     { Mb }, 0 },
11580   },
11581   {
11582     /* MOD_0F18_REG_4 */
11583     { "nop/reserved",   { Mb }, 0 },
11584   },
11585   {
11586     /* MOD_0F18_REG_5 */
11587     { "nop/reserved",   { Mb }, 0 },
11588   },
11589   {
11590     /* MOD_0F18_REG_6 */
11591     { "nop/reserved",   { Mb }, 0 },
11592   },
11593   {
11594     /* MOD_0F18_REG_7 */
11595     { "nop/reserved",   { Mb }, 0 },
11596   },
11597   {
11598     /* MOD_0F1A_PREFIX_0 */
11599     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11600     { "nopQ",           { Ev }, 0 },
11601   },
11602   {
11603     /* MOD_0F1B_PREFIX_0 */
11604     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11605     { "nopQ",           { Ev }, 0 },
11606   },
11607   {
11608     /* MOD_0F1B_PREFIX_1 */
11609     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11610     { "nopQ",           { Ev }, 0 },
11611   },
11612   {
11613     /* MOD_0F1E_PREFIX_1 */
11614     { "nopQ",           { Ev }, 0 },
11615     { REG_TABLE (REG_0F1E_MOD_3) },
11616   },
11617   {
11618     /* MOD_0F24 */
11619     { Bad_Opcode },
11620     { "movL",           { Rd, Td }, 0 },
11621   },
11622   {
11623     /* MOD_0F26 */
11624     { Bad_Opcode },
11625     { "movL",           { Td, Rd }, 0 },
11626   },
11627   {
11628     /* MOD_0F2B_PREFIX_0 */
11629     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11630   },
11631   {
11632     /* MOD_0F2B_PREFIX_1 */
11633     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11634   },
11635   {
11636     /* MOD_0F2B_PREFIX_2 */
11637     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11638   },
11639   {
11640     /* MOD_0F2B_PREFIX_3 */
11641     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11642   },
11643   {
11644     /* MOD_0F51 */
11645     { Bad_Opcode },
11646     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11647   },
11648   {
11649     /* MOD_0F71_REG_2 */
11650     { Bad_Opcode },
11651     { "psrlw",          { MS, Ib }, 0 },
11652   },
11653   {
11654     /* MOD_0F71_REG_4 */
11655     { Bad_Opcode },
11656     { "psraw",          { MS, Ib }, 0 },
11657   },
11658   {
11659     /* MOD_0F71_REG_6 */
11660     { Bad_Opcode },
11661     { "psllw",          { MS, Ib }, 0 },
11662   },
11663   {
11664     /* MOD_0F72_REG_2 */
11665     { Bad_Opcode },
11666     { "psrld",          { MS, Ib }, 0 },
11667   },
11668   {
11669     /* MOD_0F72_REG_4 */
11670     { Bad_Opcode },
11671     { "psrad",          { MS, Ib }, 0 },
11672   },
11673   {
11674     /* MOD_0F72_REG_6 */
11675     { Bad_Opcode },
11676     { "pslld",          { MS, Ib }, 0 },
11677   },
11678   {
11679     /* MOD_0F73_REG_2 */
11680     { Bad_Opcode },
11681     { "psrlq",          { MS, Ib }, 0 },
11682   },
11683   {
11684     /* MOD_0F73_REG_3 */
11685     { Bad_Opcode },
11686     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11687   },
11688   {
11689     /* MOD_0F73_REG_6 */
11690     { Bad_Opcode },
11691     { "psllq",          { MS, Ib }, 0 },
11692   },
11693   {
11694     /* MOD_0F73_REG_7 */
11695     { Bad_Opcode },
11696     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11697   },
11698   {
11699     /* MOD_0FAE_REG_0 */
11700     { "fxsave",         { FXSAVE }, 0 },
11701     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11702   },
11703   {
11704     /* MOD_0FAE_REG_1 */
11705     { "fxrstor",        { FXSAVE }, 0 },
11706     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11707   },
11708   {
11709     /* MOD_0FAE_REG_2 */
11710     { "ldmxcsr",        { Md }, 0 },
11711     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11712   },
11713   {
11714     /* MOD_0FAE_REG_3 */
11715     { "stmxcsr",        { Md }, 0 },
11716     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11717   },
11718   {
11719     /* MOD_0FAE_REG_4 */
11720     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11721     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11722   },
11723   {
11724     /* MOD_0FAE_REG_5 */
11725     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11726     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11727   },
11728   {
11729     /* MOD_0FAE_REG_6 */
11730     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11731     { RM_TABLE (RM_0FAE_REG_6) },
11732   },
11733   {
11734     /* MOD_0FAE_REG_7 */
11735     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11736     { RM_TABLE (RM_0FAE_REG_7) },
11737   },
11738   {
11739     /* MOD_0FB2 */
11740     { "lssS",           { Gv, Mp }, 0 },
11741   },
11742   {
11743     /* MOD_0FB4 */
11744     { "lfsS",           { Gv, Mp }, 0 },
11745   },
11746   {
11747     /* MOD_0FB5 */
11748     { "lgsS",           { Gv, Mp }, 0 },
11749   },
11750   {
11751     /* MOD_0FC3 */
11752     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11753   },
11754   {
11755     /* MOD_0FC7_REG_3 */
11756     { "xrstors",        { FXSAVE }, 0 },
11757   },
11758   {
11759     /* MOD_0FC7_REG_4 */
11760     { "xsavec",         { FXSAVE }, 0 },
11761   },
11762   {
11763     /* MOD_0FC7_REG_5 */
11764     { "xsaves",         { FXSAVE }, 0 },
11765   },
11766   {
11767     /* MOD_0FC7_REG_6 */
11768     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11769     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11770   },
11771   {
11772     /* MOD_0FC7_REG_7 */
11773     { "vmptrst",        { Mq }, 0 },
11774     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11775   },
11776   {
11777     /* MOD_0FD7 */
11778     { Bad_Opcode },
11779     { "pmovmskb",       { Gdq, MS }, 0 },
11780   },
11781   {
11782     /* MOD_0FE7_PREFIX_2 */
11783     { "movntdq",        { Mx, XM }, 0 },
11784   },
11785   {
11786     /* MOD_0FF0_PREFIX_3 */
11787     { "lddqu",          { XM, M }, 0 },
11788   },
11789   {
11790     /* MOD_0F382A_PREFIX_2 */
11791     { "movntdqa",       { XM, Mx }, 0 },
11792   },
11793   {
11794     /* MOD_0F38F5_PREFIX_2 */
11795     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11796   },
11797   {
11798     /* MOD_0F38F6_PREFIX_0 */
11799     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11800   },
11801   {
11802     /* MOD_62_32BIT */
11803     { "bound{S|}",      { Gv, Ma }, 0 },
11804     { EVEX_TABLE (EVEX_0F) },
11805   },
11806   {
11807     /* MOD_C4_32BIT */
11808     { "lesS",           { Gv, Mp }, 0 },
11809     { VEX_C4_TABLE (VEX_0F) },
11810   },
11811   {
11812     /* MOD_C5_32BIT */
11813     { "ldsS",           { Gv, Mp }, 0 },
11814     { VEX_C5_TABLE (VEX_0F) },
11815   },
11816   {
11817     /* MOD_VEX_0F12_PREFIX_0 */
11818     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11819     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11820   },
11821   {
11822     /* MOD_VEX_0F13 */
11823     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11824   },
11825   {
11826     /* MOD_VEX_0F16_PREFIX_0 */
11827     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11828     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11829   },
11830   {
11831     /* MOD_VEX_0F17 */
11832     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11833   },
11834   {
11835     /* MOD_VEX_0F2B */
11836     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11837   },
11838   {
11839     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11840     { Bad_Opcode },
11841     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11842   },
11843   {
11844     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11845     { Bad_Opcode },
11846     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11847   },
11848   {
11849     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11850     { Bad_Opcode },
11851     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11852   },
11853   {
11854     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11855     { Bad_Opcode },
11856     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11857   },
11858   {
11859     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11860     { Bad_Opcode },
11861     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11862   },
11863   {
11864     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11865     { Bad_Opcode },
11866     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11867   },
11868   {
11869     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11870     { Bad_Opcode },
11871     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11872   },
11873   {
11874     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11875     { Bad_Opcode },
11876     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11877   },
11878   {
11879     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11880     { Bad_Opcode },
11881     { "knotw",          { MaskG, MaskR }, 0 },
11882   },
11883   {
11884     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11885     { Bad_Opcode },
11886     { "knotq",          { MaskG, MaskR }, 0 },
11887   },
11888   {
11889     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11890     { Bad_Opcode },
11891     { "knotb",          { MaskG, MaskR }, 0 },
11892   },
11893   {
11894     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11895     { Bad_Opcode },
11896     { "knotd",          { MaskG, MaskR }, 0 },
11897   },
11898   {
11899     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11900     { Bad_Opcode },
11901     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11902   },
11903   {
11904     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11905     { Bad_Opcode },
11906     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11907   },
11908   {
11909     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11910     { Bad_Opcode },
11911     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11912   },
11913   {
11914     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11915     { Bad_Opcode },
11916     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11917   },
11918  {
11919     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11920     { Bad_Opcode },
11921     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11922   },
11923   {
11924     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11925     { Bad_Opcode },
11926     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11927   },
11928   {
11929     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11930     { Bad_Opcode },
11931     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11932   },
11933   {
11934     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11935     { Bad_Opcode },
11936     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11937   },
11938   {
11939     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11940     { Bad_Opcode },
11941     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11942   },
11943   {
11944     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11945     { Bad_Opcode },
11946     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11947   },
11948   {
11949     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11950     { Bad_Opcode },
11951     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11952   },
11953   {
11954     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11955     { Bad_Opcode },
11956     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11957   },
11958   {
11959     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11960     { Bad_Opcode },
11961     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11962   },
11963   {
11964     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11965     { Bad_Opcode },
11966     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11967   },
11968   {
11969     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11970     { Bad_Opcode },
11971     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11972   },
11973   {
11974     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11975     { Bad_Opcode },
11976     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11977   },
11978   {
11979     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11980     { Bad_Opcode },
11981     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11982   },
11983   {
11984     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11985     { Bad_Opcode },
11986     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11987   },
11988   {
11989     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11990     { Bad_Opcode },
11991     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11992   },
11993   {
11994     /* MOD_VEX_0F50 */
11995     { Bad_Opcode },
11996     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11997   },
11998   {
11999     /* MOD_VEX_0F71_REG_2 */
12000     { Bad_Opcode },
12001     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12002   },
12003   {
12004     /* MOD_VEX_0F71_REG_4 */
12005     { Bad_Opcode },
12006     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12007   },
12008   {
12009     /* MOD_VEX_0F71_REG_6 */
12010     { Bad_Opcode },
12011     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12012   },
12013   {
12014     /* MOD_VEX_0F72_REG_2 */
12015     { Bad_Opcode },
12016     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12017   },
12018   {
12019     /* MOD_VEX_0F72_REG_4 */
12020     { Bad_Opcode },
12021     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12022   },
12023   {
12024     /* MOD_VEX_0F72_REG_6 */
12025     { Bad_Opcode },
12026     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12027   },
12028   {
12029     /* MOD_VEX_0F73_REG_2 */
12030     { Bad_Opcode },
12031     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12032   },
12033   {
12034     /* MOD_VEX_0F73_REG_3 */
12035     { Bad_Opcode },
12036     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12037   },
12038   {
12039     /* MOD_VEX_0F73_REG_6 */
12040     { Bad_Opcode },
12041     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12042   },
12043   {
12044     /* MOD_VEX_0F73_REG_7 */
12045     { Bad_Opcode },
12046     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12047   },
12048   {
12049     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12050     { "kmovw",          { Ew, MaskG }, 0 },
12051     { Bad_Opcode },
12052   },
12053   {
12054     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12055     { "kmovq",          { Eq, MaskG }, 0 },
12056     { Bad_Opcode },
12057   },
12058   {
12059     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12060     { "kmovb",          { Eb, MaskG }, 0 },
12061     { Bad_Opcode },
12062   },
12063   {
12064     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12065     { "kmovd",          { Ed, MaskG }, 0 },
12066     { Bad_Opcode },
12067   },
12068   {
12069     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12070     { Bad_Opcode },
12071     { "kmovw",          { MaskG, Rdq }, 0 },
12072   },
12073   {
12074     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12075     { Bad_Opcode },
12076     { "kmovb",          { MaskG, Rdq }, 0 },
12077   },
12078   {
12079     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12080     { Bad_Opcode },
12081     { "kmovd",          { MaskG, Rdq }, 0 },
12082   },
12083   {
12084     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12085     { Bad_Opcode },
12086     { "kmovq",          { MaskG, Rdq }, 0 },
12087   },
12088   {
12089     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12090     { Bad_Opcode },
12091     { "kmovw",          { Gdq, MaskR }, 0 },
12092   },
12093   {
12094     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12095     { Bad_Opcode },
12096     { "kmovb",          { Gdq, MaskR }, 0 },
12097   },
12098   {
12099     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12100     { Bad_Opcode },
12101     { "kmovd",          { Gdq, MaskR }, 0 },
12102   },
12103   {
12104     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12105     { Bad_Opcode },
12106     { "kmovq",          { Gdq, MaskR }, 0 },
12107   },
12108   {
12109     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12110     { Bad_Opcode },
12111     { "kortestw", { MaskG, MaskR }, 0 },
12112   },
12113   {
12114     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12115     { Bad_Opcode },
12116     { "kortestq", { MaskG, MaskR }, 0 },
12117   },
12118   {
12119     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12120     { Bad_Opcode },
12121     { "kortestb", { MaskG, MaskR }, 0 },
12122   },
12123   {
12124     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12125     { Bad_Opcode },
12126     { "kortestd", { MaskG, MaskR }, 0 },
12127   },
12128   {
12129     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12130     { Bad_Opcode },
12131     { "ktestw", { MaskG, MaskR }, 0 },
12132   },
12133   {
12134     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12135     { Bad_Opcode },
12136     { "ktestq", { MaskG, MaskR }, 0 },
12137   },
12138   {
12139     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12140     { Bad_Opcode },
12141     { "ktestb", { MaskG, MaskR }, 0 },
12142   },
12143   {
12144     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12145     { Bad_Opcode },
12146     { "ktestd", { MaskG, MaskR }, 0 },
12147   },
12148   {
12149     /* MOD_VEX_0FAE_REG_2 */
12150     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12151   },
12152   {
12153     /* MOD_VEX_0FAE_REG_3 */
12154     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12155   },
12156   {
12157     /* MOD_VEX_0FD7_PREFIX_2 */
12158     { Bad_Opcode },
12159     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12160   },
12161   {
12162     /* MOD_VEX_0FE7_PREFIX_2 */
12163     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12164   },
12165   {
12166     /* MOD_VEX_0FF0_PREFIX_3 */
12167     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12168   },
12169   {
12170     /* MOD_VEX_0F381A_PREFIX_2 */
12171     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12172   },
12173   {
12174     /* MOD_VEX_0F382A_PREFIX_2 */
12175     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12176   },
12177   {
12178     /* MOD_VEX_0F382C_PREFIX_2 */
12179     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12180   },
12181   {
12182     /* MOD_VEX_0F382D_PREFIX_2 */
12183     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12184   },
12185   {
12186     /* MOD_VEX_0F382E_PREFIX_2 */
12187     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12188   },
12189   {
12190     /* MOD_VEX_0F382F_PREFIX_2 */
12191     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12192   },
12193   {
12194     /* MOD_VEX_0F385A_PREFIX_2 */
12195     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12196   },
12197   {
12198     /* MOD_VEX_0F388C_PREFIX_2 */
12199     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12200   },
12201   {
12202     /* MOD_VEX_0F388E_PREFIX_2 */
12203     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12204   },
12205   {
12206     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12207     { Bad_Opcode },
12208     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12209   },
12210   {
12211     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12212     { Bad_Opcode },
12213     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12214   },
12215   {
12216     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12217     { Bad_Opcode },
12218     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12219   },
12220   {
12221     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12222     { Bad_Opcode },
12223     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12224   },
12225   {
12226     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12227     { Bad_Opcode },
12228     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12229   },
12230   {
12231     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12232     { Bad_Opcode },
12233     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12234   },
12235   {
12236     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12237     { Bad_Opcode },
12238     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12239   },
12240   {
12241     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12242     { Bad_Opcode },
12243     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12244   },
12245 #define NEED_MOD_TABLE
12246 #include "i386-dis-evex.h"
12247 #undef NEED_MOD_TABLE
12248 };
12249
12250 static const struct dis386 rm_table[][8] = {
12251   {
12252     /* RM_C6_REG_7 */
12253     { "xabort",         { Skip_MODRM, Ib }, 0 },
12254   },
12255   {
12256     /* RM_C7_REG_7 */
12257     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12258   },
12259   {
12260     /* RM_0F01_REG_0 */
12261     { Bad_Opcode },
12262     { "vmcall",         { Skip_MODRM }, 0 },
12263     { "vmlaunch",       { Skip_MODRM }, 0 },
12264     { "vmresume",       { Skip_MODRM }, 0 },
12265     { "vmxoff",         { Skip_MODRM }, 0 },
12266     { "pconfig",        { Skip_MODRM }, 0 },
12267   },
12268   {
12269     /* RM_0F01_REG_1 */
12270     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12271     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12272     { "clac",           { Skip_MODRM }, 0 },
12273     { "stac",           { Skip_MODRM }, 0 },
12274     { Bad_Opcode },
12275     { Bad_Opcode },
12276     { Bad_Opcode },
12277     { "encls",          { Skip_MODRM }, 0 },
12278   },
12279   {
12280     /* RM_0F01_REG_2 */
12281     { "xgetbv",         { Skip_MODRM }, 0 },
12282     { "xsetbv",         { Skip_MODRM }, 0 },
12283     { Bad_Opcode },
12284     { Bad_Opcode },
12285     { "vmfunc",         { Skip_MODRM }, 0 },
12286     { "xend",           { Skip_MODRM }, 0 },
12287     { "xtest",          { Skip_MODRM }, 0 },
12288     { "enclu",          { Skip_MODRM }, 0 },
12289   },
12290   {
12291     /* RM_0F01_REG_3 */
12292     { "vmrun",          { Skip_MODRM }, 0 },
12293     { "vmmcall",        { Skip_MODRM }, 0 },
12294     { "vmload",         { Skip_MODRM }, 0 },
12295     { "vmsave",         { Skip_MODRM }, 0 },
12296     { "stgi",           { Skip_MODRM }, 0 },
12297     { "clgi",           { Skip_MODRM }, 0 },
12298     { "skinit",         { Skip_MODRM }, 0 },
12299     { "invlpga",        { Skip_MODRM }, 0 },
12300   },
12301   {
12302     /* RM_0F01_REG_5 */
12303     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12304     { Bad_Opcode },
12305     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12306     { Bad_Opcode },
12307     { Bad_Opcode },
12308     { Bad_Opcode },
12309     { "rdpkru",         { Skip_MODRM }, 0 },
12310     { "wrpkru",         { Skip_MODRM }, 0 },
12311   },
12312   {
12313     /* RM_0F01_REG_7 */
12314     { "swapgs",         { Skip_MODRM }, 0  },
12315     { "rdtscp",         { Skip_MODRM }, 0  },
12316     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12317     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12318     { "clzero",         { Skip_MODRM }, 0  },
12319   },
12320   {
12321     /* RM_0F1E_MOD_3_REG_7 */
12322     { "nopQ",           { Ev }, 0 },
12323     { "nopQ",           { Ev }, 0 },
12324     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12325     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12326     { "nopQ",           { Ev }, 0 },
12327     { "nopQ",           { Ev }, 0 },
12328     { "nopQ",           { Ev }, 0 },
12329     { "nopQ",           { Ev }, 0 },
12330   },
12331   {
12332     /* RM_0FAE_REG_6 */
12333     { "mfence",         { Skip_MODRM }, 0 },
12334   },
12335   {
12336     /* RM_0FAE_REG_7 */
12337     { "sfence",         { Skip_MODRM }, 0 },
12338
12339   },
12340 };
12341
12342 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12343
12344 /* We use the high bit to indicate different name for the same
12345    prefix.  */
12346 #define REP_PREFIX      (0xf3 | 0x100)
12347 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12348 #define XRELEASE_PREFIX (0xf3 | 0x400)
12349 #define BND_PREFIX      (0xf2 | 0x400)
12350 #define NOTRACK_PREFIX  (0x3e | 0x100)
12351
12352 static int
12353 ckprefix (void)
12354 {
12355   int newrex, i, length;
12356   rex = 0;
12357   rex_ignored = 0;
12358   prefixes = 0;
12359   used_prefixes = 0;
12360   rex_used = 0;
12361   last_lock_prefix = -1;
12362   last_repz_prefix = -1;
12363   last_repnz_prefix = -1;
12364   last_data_prefix = -1;
12365   last_addr_prefix = -1;
12366   last_rex_prefix = -1;
12367   last_seg_prefix = -1;
12368   fwait_prefix = -1;
12369   active_seg_prefix = 0;
12370   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12371     all_prefixes[i] = 0;
12372   i = 0;
12373   length = 0;
12374   /* The maximum instruction length is 15bytes.  */
12375   while (length < MAX_CODE_LENGTH - 1)
12376     {
12377       FETCH_DATA (the_info, codep + 1);
12378       newrex = 0;
12379       switch (*codep)
12380         {
12381         /* REX prefixes family.  */
12382         case 0x40:
12383         case 0x41:
12384         case 0x42:
12385         case 0x43:
12386         case 0x44:
12387         case 0x45:
12388         case 0x46:
12389         case 0x47:
12390         case 0x48:
12391         case 0x49:
12392         case 0x4a:
12393         case 0x4b:
12394         case 0x4c:
12395         case 0x4d:
12396         case 0x4e:
12397         case 0x4f:
12398           if (address_mode == mode_64bit)
12399             newrex = *codep;
12400           else
12401             return 1;
12402           last_rex_prefix = i;
12403           break;
12404         case 0xf3:
12405           prefixes |= PREFIX_REPZ;
12406           last_repz_prefix = i;
12407           break;
12408         case 0xf2:
12409           prefixes |= PREFIX_REPNZ;
12410           last_repnz_prefix = i;
12411           break;
12412         case 0xf0:
12413           prefixes |= PREFIX_LOCK;
12414           last_lock_prefix = i;
12415           break;
12416         case 0x2e:
12417           prefixes |= PREFIX_CS;
12418           last_seg_prefix = i;
12419           active_seg_prefix = PREFIX_CS;
12420           break;
12421         case 0x36:
12422           prefixes |= PREFIX_SS;
12423           last_seg_prefix = i;
12424           active_seg_prefix = PREFIX_SS;
12425           break;
12426         case 0x3e:
12427           prefixes |= PREFIX_DS;
12428           last_seg_prefix = i;
12429           active_seg_prefix = PREFIX_DS;
12430           break;
12431         case 0x26:
12432           prefixes |= PREFIX_ES;
12433           last_seg_prefix = i;
12434           active_seg_prefix = PREFIX_ES;
12435           break;
12436         case 0x64:
12437           prefixes |= PREFIX_FS;
12438           last_seg_prefix = i;
12439           active_seg_prefix = PREFIX_FS;
12440           break;
12441         case 0x65:
12442           prefixes |= PREFIX_GS;
12443           last_seg_prefix = i;
12444           active_seg_prefix = PREFIX_GS;
12445           break;
12446         case 0x66:
12447           prefixes |= PREFIX_DATA;
12448           last_data_prefix = i;
12449           break;
12450         case 0x67:
12451           prefixes |= PREFIX_ADDR;
12452           last_addr_prefix = i;
12453           break;
12454         case FWAIT_OPCODE:
12455           /* fwait is really an instruction.  If there are prefixes
12456              before the fwait, they belong to the fwait, *not* to the
12457              following instruction.  */
12458           fwait_prefix = i;
12459           if (prefixes || rex)
12460             {
12461               prefixes |= PREFIX_FWAIT;
12462               codep++;
12463               /* This ensures that the previous REX prefixes are noticed
12464                  as unused prefixes, as in the return case below.  */
12465               rex_used = rex;
12466               return 1;
12467             }
12468           prefixes = PREFIX_FWAIT;
12469           break;
12470         default:
12471           return 1;
12472         }
12473       /* Rex is ignored when followed by another prefix.  */
12474       if (rex)
12475         {
12476           rex_used = rex;
12477           return 1;
12478         }
12479       if (*codep != FWAIT_OPCODE)
12480         all_prefixes[i++] = *codep;
12481       rex = newrex;
12482       codep++;
12483       length++;
12484     }
12485   return 0;
12486 }
12487
12488 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12489    prefix byte.  */
12490
12491 static const char *
12492 prefix_name (int pref, int sizeflag)
12493 {
12494   static const char *rexes [16] =
12495     {
12496       "rex",            /* 0x40 */
12497       "rex.B",          /* 0x41 */
12498       "rex.X",          /* 0x42 */
12499       "rex.XB",         /* 0x43 */
12500       "rex.R",          /* 0x44 */
12501       "rex.RB",         /* 0x45 */
12502       "rex.RX",         /* 0x46 */
12503       "rex.RXB",        /* 0x47 */
12504       "rex.W",          /* 0x48 */
12505       "rex.WB",         /* 0x49 */
12506       "rex.WX",         /* 0x4a */
12507       "rex.WXB",        /* 0x4b */
12508       "rex.WR",         /* 0x4c */
12509       "rex.WRB",        /* 0x4d */
12510       "rex.WRX",        /* 0x4e */
12511       "rex.WRXB",       /* 0x4f */
12512     };
12513
12514   switch (pref)
12515     {
12516     /* REX prefixes family.  */
12517     case 0x40:
12518     case 0x41:
12519     case 0x42:
12520     case 0x43:
12521     case 0x44:
12522     case 0x45:
12523     case 0x46:
12524     case 0x47:
12525     case 0x48:
12526     case 0x49:
12527     case 0x4a:
12528     case 0x4b:
12529     case 0x4c:
12530     case 0x4d:
12531     case 0x4e:
12532     case 0x4f:
12533       return rexes [pref - 0x40];
12534     case 0xf3:
12535       return "repz";
12536     case 0xf2:
12537       return "repnz";
12538     case 0xf0:
12539       return "lock";
12540     case 0x2e:
12541       return "cs";
12542     case 0x36:
12543       return "ss";
12544     case 0x3e:
12545       return "ds";
12546     case 0x26:
12547       return "es";
12548     case 0x64:
12549       return "fs";
12550     case 0x65:
12551       return "gs";
12552     case 0x66:
12553       return (sizeflag & DFLAG) ? "data16" : "data32";
12554     case 0x67:
12555       if (address_mode == mode_64bit)
12556         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12557       else
12558         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12559     case FWAIT_OPCODE:
12560       return "fwait";
12561     case REP_PREFIX:
12562       return "rep";
12563     case XACQUIRE_PREFIX:
12564       return "xacquire";
12565     case XRELEASE_PREFIX:
12566       return "xrelease";
12567     case BND_PREFIX:
12568       return "bnd";
12569     case NOTRACK_PREFIX:
12570       return "notrack";
12571     default:
12572       return NULL;
12573     }
12574 }
12575
12576 static char op_out[MAX_OPERANDS][100];
12577 static int op_ad, op_index[MAX_OPERANDS];
12578 static int two_source_ops;
12579 static bfd_vma op_address[MAX_OPERANDS];
12580 static bfd_vma op_riprel[MAX_OPERANDS];
12581 static bfd_vma start_pc;
12582
12583 /*
12584  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12585  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12586  *   section of the "Virtual 8086 Mode" chapter.)
12587  * 'pc' should be the address of this instruction, it will
12588  *   be used to print the target address if this is a relative jump or call
12589  * The function returns the length of this instruction in bytes.
12590  */
12591
12592 static char intel_syntax;
12593 static char intel_mnemonic = !SYSV386_COMPAT;
12594 static char open_char;
12595 static char close_char;
12596 static char separator_char;
12597 static char scale_char;
12598
12599 enum x86_64_isa
12600 {
12601   amd64 = 0,
12602   intel64
12603 };
12604
12605 static enum x86_64_isa isa64;
12606
12607 /* Here for backwards compatibility.  When gdb stops using
12608    print_insn_i386_att and print_insn_i386_intel these functions can
12609    disappear, and print_insn_i386 be merged into print_insn.  */
12610 int
12611 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12612 {
12613   intel_syntax = 0;
12614
12615   return print_insn (pc, info);
12616 }
12617
12618 int
12619 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12620 {
12621   intel_syntax = 1;
12622
12623   return print_insn (pc, info);
12624 }
12625
12626 int
12627 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12628 {
12629   intel_syntax = -1;
12630
12631   return print_insn (pc, info);
12632 }
12633
12634 void
12635 print_i386_disassembler_options (FILE *stream)
12636 {
12637   fprintf (stream, _("\n\
12638 The following i386/x86-64 specific disassembler options are supported for use\n\
12639 with the -M switch (multiple options should be separated by commas):\n"));
12640
12641   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12642   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12643   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12644   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12645   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12646   fprintf (stream, _("  att-mnemonic\n"
12647                      "              Display instruction in AT&T mnemonic\n"));
12648   fprintf (stream, _("  intel-mnemonic\n"
12649                      "              Display instruction in Intel mnemonic\n"));
12650   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12651   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12652   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12653   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12654   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12655   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12656   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12657   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12658 }
12659
12660 /* Bad opcode.  */
12661 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12662
12663 /* Get a pointer to struct dis386 with a valid name.  */
12664
12665 static const struct dis386 *
12666 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12667 {
12668   int vindex, vex_table_index;
12669
12670   if (dp->name != NULL)
12671     return dp;
12672
12673   switch (dp->op[0].bytemode)
12674     {
12675     case USE_REG_TABLE:
12676       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12677       break;
12678
12679     case USE_MOD_TABLE:
12680       vindex = modrm.mod == 0x3 ? 1 : 0;
12681       dp = &mod_table[dp->op[1].bytemode][vindex];
12682       break;
12683
12684     case USE_RM_TABLE:
12685       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12686       break;
12687
12688     case USE_PREFIX_TABLE:
12689       if (need_vex)
12690         {
12691           /* The prefix in VEX is implicit.  */
12692           switch (vex.prefix)
12693             {
12694             case 0:
12695               vindex = 0;
12696               break;
12697             case REPE_PREFIX_OPCODE:
12698               vindex = 1;
12699               break;
12700             case DATA_PREFIX_OPCODE:
12701               vindex = 2;
12702               break;
12703             case REPNE_PREFIX_OPCODE:
12704               vindex = 3;
12705               break;
12706             default:
12707               abort ();
12708               break;
12709             }
12710         }
12711       else
12712         {
12713           int last_prefix = -1;
12714           int prefix = 0;
12715           vindex = 0;
12716           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12717              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12718              last one wins.  */
12719           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12720             {
12721               if (last_repz_prefix > last_repnz_prefix)
12722                 {
12723                   vindex = 1;
12724                   prefix = PREFIX_REPZ;
12725                   last_prefix = last_repz_prefix;
12726                 }
12727               else
12728                 {
12729                   vindex = 3;
12730                   prefix = PREFIX_REPNZ;
12731                   last_prefix = last_repnz_prefix;
12732                 }
12733
12734               /* Check if prefix should be ignored.  */
12735               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12736                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12737                    & prefix) != 0)
12738                 vindex = 0;
12739             }
12740
12741           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12742             {
12743               vindex = 2;
12744               prefix = PREFIX_DATA;
12745               last_prefix = last_data_prefix;
12746             }
12747
12748           if (vindex != 0)
12749             {
12750               used_prefixes |= prefix;
12751               all_prefixes[last_prefix] = 0;
12752             }
12753         }
12754       dp = &prefix_table[dp->op[1].bytemode][vindex];
12755       break;
12756
12757     case USE_X86_64_TABLE:
12758       vindex = address_mode == mode_64bit ? 1 : 0;
12759       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12760       break;
12761
12762     case USE_3BYTE_TABLE:
12763       FETCH_DATA (info, codep + 2);
12764       vindex = *codep++;
12765       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12766       end_codep = codep;
12767       modrm.mod = (*codep >> 6) & 3;
12768       modrm.reg = (*codep >> 3) & 7;
12769       modrm.rm = *codep & 7;
12770       break;
12771
12772     case USE_VEX_LEN_TABLE:
12773       if (!need_vex)
12774         abort ();
12775
12776       switch (vex.length)
12777         {
12778         case 128:
12779           vindex = 0;
12780           break;
12781         case 256:
12782           vindex = 1;
12783           break;
12784         default:
12785           abort ();
12786           break;
12787         }
12788
12789       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12790       break;
12791
12792     case USE_XOP_8F_TABLE:
12793       FETCH_DATA (info, codep + 3);
12794       /* All bits in the REX prefix are ignored.  */
12795       rex_ignored = rex;
12796       rex = ~(*codep >> 5) & 0x7;
12797
12798       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12799       switch ((*codep & 0x1f))
12800         {
12801         default:
12802           dp = &bad_opcode;
12803           return dp;
12804         case 0x8:
12805           vex_table_index = XOP_08;
12806           break;
12807         case 0x9:
12808           vex_table_index = XOP_09;
12809           break;
12810         case 0xa:
12811           vex_table_index = XOP_0A;
12812           break;
12813         }
12814       codep++;
12815       vex.w = *codep & 0x80;
12816       if (vex.w && address_mode == mode_64bit)
12817         rex |= REX_W;
12818
12819       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12820       if (address_mode != mode_64bit)
12821         {
12822           /* In 16/32-bit mode REX_B is silently ignored.  */
12823           rex &= ~REX_B;
12824         }
12825
12826       vex.length = (*codep & 0x4) ? 256 : 128;
12827       switch ((*codep & 0x3))
12828         {
12829         case 0:
12830           vex.prefix = 0;
12831           break;
12832         case 1:
12833           vex.prefix = DATA_PREFIX_OPCODE;
12834           break;
12835         case 2:
12836           vex.prefix = REPE_PREFIX_OPCODE;
12837           break;
12838         case 3:
12839           vex.prefix = REPNE_PREFIX_OPCODE;
12840           break;
12841         }
12842       need_vex = 1;
12843       need_vex_reg = 1;
12844       codep++;
12845       vindex = *codep++;
12846       dp = &xop_table[vex_table_index][vindex];
12847
12848       end_codep = codep;
12849       FETCH_DATA (info, codep + 1);
12850       modrm.mod = (*codep >> 6) & 3;
12851       modrm.reg = (*codep >> 3) & 7;
12852       modrm.rm = *codep & 7;
12853       break;
12854
12855     case USE_VEX_C4_TABLE:
12856       /* VEX prefix.  */
12857       FETCH_DATA (info, codep + 3);
12858       /* All bits in the REX prefix are ignored.  */
12859       rex_ignored = rex;
12860       rex = ~(*codep >> 5) & 0x7;
12861       switch ((*codep & 0x1f))
12862         {
12863         default:
12864           dp = &bad_opcode;
12865           return dp;
12866         case 0x1:
12867           vex_table_index = VEX_0F;
12868           break;
12869         case 0x2:
12870           vex_table_index = VEX_0F38;
12871           break;
12872         case 0x3:
12873           vex_table_index = VEX_0F3A;
12874           break;
12875         }
12876       codep++;
12877       vex.w = *codep & 0x80;
12878       if (address_mode == mode_64bit)
12879         {
12880           if (vex.w)
12881             rex |= REX_W;
12882         }
12883       else
12884         {
12885           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12886              is ignored, other REX bits are 0 and the highest bit in
12887              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12888           rex = 0;
12889         }
12890       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12891       vex.length = (*codep & 0x4) ? 256 : 128;
12892       switch ((*codep & 0x3))
12893         {
12894         case 0:
12895           vex.prefix = 0;
12896           break;
12897         case 1:
12898           vex.prefix = DATA_PREFIX_OPCODE;
12899           break;
12900         case 2:
12901           vex.prefix = REPE_PREFIX_OPCODE;
12902           break;
12903         case 3:
12904           vex.prefix = REPNE_PREFIX_OPCODE;
12905           break;
12906         }
12907       need_vex = 1;
12908       need_vex_reg = 1;
12909       codep++;
12910       vindex = *codep++;
12911       dp = &vex_table[vex_table_index][vindex];
12912       end_codep = codep;
12913       /* There is no MODRM byte for VEX0F 77.  */
12914       if (vex_table_index != VEX_0F || vindex != 0x77)
12915         {
12916           FETCH_DATA (info, codep + 1);
12917           modrm.mod = (*codep >> 6) & 3;
12918           modrm.reg = (*codep >> 3) & 7;
12919           modrm.rm = *codep & 7;
12920         }
12921       break;
12922
12923     case USE_VEX_C5_TABLE:
12924       /* VEX prefix.  */
12925       FETCH_DATA (info, codep + 2);
12926       /* All bits in the REX prefix are ignored.  */
12927       rex_ignored = rex;
12928       rex = (*codep & 0x80) ? 0 : REX_R;
12929
12930       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12931          VEX.vvvv is 1.  */
12932       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12933       vex.w = 0;
12934       vex.length = (*codep & 0x4) ? 256 : 128;
12935       switch ((*codep & 0x3))
12936         {
12937         case 0:
12938           vex.prefix = 0;
12939           break;
12940         case 1:
12941           vex.prefix = DATA_PREFIX_OPCODE;
12942           break;
12943         case 2:
12944           vex.prefix = REPE_PREFIX_OPCODE;
12945           break;
12946         case 3:
12947           vex.prefix = REPNE_PREFIX_OPCODE;
12948           break;
12949         }
12950       need_vex = 1;
12951       need_vex_reg = 1;
12952       codep++;
12953       vindex = *codep++;
12954       dp = &vex_table[dp->op[1].bytemode][vindex];
12955       end_codep = codep;
12956       /* There is no MODRM byte for VEX 77.  */
12957       if (vindex != 0x77)
12958         {
12959           FETCH_DATA (info, codep + 1);
12960           modrm.mod = (*codep >> 6) & 3;
12961           modrm.reg = (*codep >> 3) & 7;
12962           modrm.rm = *codep & 7;
12963         }
12964       break;
12965
12966     case USE_VEX_W_TABLE:
12967       if (!need_vex)
12968         abort ();
12969
12970       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12971       break;
12972
12973     case USE_EVEX_TABLE:
12974       two_source_ops = 0;
12975       /* EVEX prefix.  */
12976       vex.evex = 1;
12977       FETCH_DATA (info, codep + 4);
12978       /* All bits in the REX prefix are ignored.  */
12979       rex_ignored = rex;
12980       /* The first byte after 0x62.  */
12981       rex = ~(*codep >> 5) & 0x7;
12982       vex.r = *codep & 0x10;
12983       switch ((*codep & 0xf))
12984         {
12985         default:
12986           return &bad_opcode;
12987         case 0x1:
12988           vex_table_index = EVEX_0F;
12989           break;
12990         case 0x2:
12991           vex_table_index = EVEX_0F38;
12992           break;
12993         case 0x3:
12994           vex_table_index = EVEX_0F3A;
12995           break;
12996         }
12997
12998       /* The second byte after 0x62.  */
12999       codep++;
13000       vex.w = *codep & 0x80;
13001       if (vex.w && address_mode == mode_64bit)
13002         rex |= REX_W;
13003
13004       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13005
13006       /* The U bit.  */
13007       if (!(*codep & 0x4))
13008         return &bad_opcode;
13009
13010       switch ((*codep & 0x3))
13011         {
13012         case 0:
13013           vex.prefix = 0;
13014           break;
13015         case 1:
13016           vex.prefix = DATA_PREFIX_OPCODE;
13017           break;
13018         case 2:
13019           vex.prefix = REPE_PREFIX_OPCODE;
13020           break;
13021         case 3:
13022           vex.prefix = REPNE_PREFIX_OPCODE;
13023           break;
13024         }
13025
13026       /* The third byte after 0x62.  */
13027       codep++;
13028
13029       /* Remember the static rounding bits.  */
13030       vex.ll = (*codep >> 5) & 3;
13031       vex.b = (*codep & 0x10) != 0;
13032
13033       vex.v = *codep & 0x8;
13034       vex.mask_register_specifier = *codep & 0x7;
13035       vex.zeroing = *codep & 0x80;
13036
13037       if (address_mode != mode_64bit)
13038         {
13039           /* In 16/32-bit mode silently ignore following bits.  */
13040           rex &= ~REX_B;
13041           vex.r = 1;
13042           vex.v = 1;
13043         }
13044
13045       need_vex = 1;
13046       need_vex_reg = 1;
13047       codep++;
13048       vindex = *codep++;
13049       dp = &evex_table[vex_table_index][vindex];
13050       end_codep = codep;
13051       FETCH_DATA (info, codep + 1);
13052       modrm.mod = (*codep >> 6) & 3;
13053       modrm.reg = (*codep >> 3) & 7;
13054       modrm.rm = *codep & 7;
13055
13056       /* Set vector length.  */
13057       if (modrm.mod == 3 && vex.b)
13058         vex.length = 512;
13059       else
13060         {
13061           switch (vex.ll)
13062             {
13063             case 0x0:
13064               vex.length = 128;
13065               break;
13066             case 0x1:
13067               vex.length = 256;
13068               break;
13069             case 0x2:
13070               vex.length = 512;
13071               break;
13072             default:
13073               return &bad_opcode;
13074             }
13075         }
13076       break;
13077
13078     case 0:
13079       dp = &bad_opcode;
13080       break;
13081
13082     default:
13083       abort ();
13084     }
13085
13086   if (dp->name != NULL)
13087     return dp;
13088   else
13089     return get_valid_dis386 (dp, info);
13090 }
13091
13092 static void
13093 get_sib (disassemble_info *info, int sizeflag)
13094 {
13095   /* If modrm.mod == 3, operand must be register.  */
13096   if (need_modrm
13097       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13098       && modrm.mod != 3
13099       && modrm.rm == 4)
13100     {
13101       FETCH_DATA (info, codep + 2);
13102       sib.index = (codep [1] >> 3) & 7;
13103       sib.scale = (codep [1] >> 6) & 3;
13104       sib.base = codep [1] & 7;
13105     }
13106 }
13107
13108 static int
13109 print_insn (bfd_vma pc, disassemble_info *info)
13110 {
13111   const struct dis386 *dp;
13112   int i;
13113   char *op_txt[MAX_OPERANDS];
13114   int needcomma;
13115   int sizeflag, orig_sizeflag;
13116   const char *p;
13117   struct dis_private priv;
13118   int prefix_length;
13119
13120   priv.orig_sizeflag = AFLAG | DFLAG;
13121   if ((info->mach & bfd_mach_i386_i386) != 0)
13122     address_mode = mode_32bit;
13123   else if (info->mach == bfd_mach_i386_i8086)
13124     {
13125       address_mode = mode_16bit;
13126       priv.orig_sizeflag = 0;
13127     }
13128   else
13129     address_mode = mode_64bit;
13130
13131   if (intel_syntax == (char) -1)
13132     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13133
13134   for (p = info->disassembler_options; p != NULL; )
13135     {
13136       if (CONST_STRNEQ (p, "amd64"))
13137         isa64 = amd64;
13138       else if (CONST_STRNEQ (p, "intel64"))
13139         isa64 = intel64;
13140       else if (CONST_STRNEQ (p, "x86-64"))
13141         {
13142           address_mode = mode_64bit;
13143           priv.orig_sizeflag = AFLAG | DFLAG;
13144         }
13145       else if (CONST_STRNEQ (p, "i386"))
13146         {
13147           address_mode = mode_32bit;
13148           priv.orig_sizeflag = AFLAG | DFLAG;
13149         }
13150       else if (CONST_STRNEQ (p, "i8086"))
13151         {
13152           address_mode = mode_16bit;
13153           priv.orig_sizeflag = 0;
13154         }
13155       else if (CONST_STRNEQ (p, "intel"))
13156         {
13157           intel_syntax = 1;
13158           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13159             intel_mnemonic = 1;
13160         }
13161       else if (CONST_STRNEQ (p, "att"))
13162         {
13163           intel_syntax = 0;
13164           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13165             intel_mnemonic = 0;
13166         }
13167       else if (CONST_STRNEQ (p, "addr"))
13168         {
13169           if (address_mode == mode_64bit)
13170             {
13171               if (p[4] == '3' && p[5] == '2')
13172                 priv.orig_sizeflag &= ~AFLAG;
13173               else if (p[4] == '6' && p[5] == '4')
13174                 priv.orig_sizeflag |= AFLAG;
13175             }
13176           else
13177             {
13178               if (p[4] == '1' && p[5] == '6')
13179                 priv.orig_sizeflag &= ~AFLAG;
13180               else if (p[4] == '3' && p[5] == '2')
13181                 priv.orig_sizeflag |= AFLAG;
13182             }
13183         }
13184       else if (CONST_STRNEQ (p, "data"))
13185         {
13186           if (p[4] == '1' && p[5] == '6')
13187             priv.orig_sizeflag &= ~DFLAG;
13188           else if (p[4] == '3' && p[5] == '2')
13189             priv.orig_sizeflag |= DFLAG;
13190         }
13191       else if (CONST_STRNEQ (p, "suffix"))
13192         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13193
13194       p = strchr (p, ',');
13195       if (p != NULL)
13196         p++;
13197     }
13198
13199   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13200     {
13201       (*info->fprintf_func) (info->stream,
13202                              _("64-bit address is disabled"));
13203       return -1;
13204     }
13205
13206   if (intel_syntax)
13207     {
13208       names64 = intel_names64;
13209       names32 = intel_names32;
13210       names16 = intel_names16;
13211       names8 = intel_names8;
13212       names8rex = intel_names8rex;
13213       names_seg = intel_names_seg;
13214       names_mm = intel_names_mm;
13215       names_bnd = intel_names_bnd;
13216       names_xmm = intel_names_xmm;
13217       names_ymm = intel_names_ymm;
13218       names_zmm = intel_names_zmm;
13219       index64 = intel_index64;
13220       index32 = intel_index32;
13221       names_mask = intel_names_mask;
13222       index16 = intel_index16;
13223       open_char = '[';
13224       close_char = ']';
13225       separator_char = '+';
13226       scale_char = '*';
13227     }
13228   else
13229     {
13230       names64 = att_names64;
13231       names32 = att_names32;
13232       names16 = att_names16;
13233       names8 = att_names8;
13234       names8rex = att_names8rex;
13235       names_seg = att_names_seg;
13236       names_mm = att_names_mm;
13237       names_bnd = att_names_bnd;
13238       names_xmm = att_names_xmm;
13239       names_ymm = att_names_ymm;
13240       names_zmm = att_names_zmm;
13241       index64 = att_index64;
13242       index32 = att_index32;
13243       names_mask = att_names_mask;
13244       index16 = att_index16;
13245       open_char = '(';
13246       close_char =  ')';
13247       separator_char = ',';
13248       scale_char = ',';
13249     }
13250
13251   /* The output looks better if we put 7 bytes on a line, since that
13252      puts most long word instructions on a single line.  Use 8 bytes
13253      for Intel L1OM.  */
13254   if ((info->mach & bfd_mach_l1om) != 0)
13255     info->bytes_per_line = 8;
13256   else
13257     info->bytes_per_line = 7;
13258
13259   info->private_data = &priv;
13260   priv.max_fetched = priv.the_buffer;
13261   priv.insn_start = pc;
13262
13263   obuf[0] = 0;
13264   for (i = 0; i < MAX_OPERANDS; ++i)
13265     {
13266       op_out[i][0] = 0;
13267       op_index[i] = -1;
13268     }
13269
13270   the_info = info;
13271   start_pc = pc;
13272   start_codep = priv.the_buffer;
13273   codep = priv.the_buffer;
13274
13275   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13276     {
13277       const char *name;
13278
13279       /* Getting here means we tried for data but didn't get it.  That
13280          means we have an incomplete instruction of some sort.  Just
13281          print the first byte as a prefix or a .byte pseudo-op.  */
13282       if (codep > priv.the_buffer)
13283         {
13284           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13285           if (name != NULL)
13286             (*info->fprintf_func) (info->stream, "%s", name);
13287           else
13288             {
13289               /* Just print the first byte as a .byte instruction.  */
13290               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13291                                      (unsigned int) priv.the_buffer[0]);
13292             }
13293
13294           return 1;
13295         }
13296
13297       return -1;
13298     }
13299
13300   obufp = obuf;
13301   sizeflag = priv.orig_sizeflag;
13302
13303   if (!ckprefix () || rex_used)
13304     {
13305       /* Too many prefixes or unused REX prefixes.  */
13306       for (i = 0;
13307            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13308            i++)
13309         (*info->fprintf_func) (info->stream, "%s%s",
13310                                i == 0 ? "" : " ",
13311                                prefix_name (all_prefixes[i], sizeflag));
13312       return i;
13313     }
13314
13315   insn_codep = codep;
13316
13317   FETCH_DATA (info, codep + 1);
13318   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13319
13320   if (((prefixes & PREFIX_FWAIT)
13321        && ((*codep < 0xd8) || (*codep > 0xdf))))
13322     {
13323       /* Handle prefixes before fwait.  */
13324       for (i = 0; i < fwait_prefix && all_prefixes[i];
13325            i++)
13326         (*info->fprintf_func) (info->stream, "%s ",
13327                                prefix_name (all_prefixes[i], sizeflag));
13328       (*info->fprintf_func) (info->stream, "fwait");
13329       return i + 1;
13330     }
13331
13332   if (*codep == 0x0f)
13333     {
13334       unsigned char threebyte;
13335
13336       codep++;
13337       FETCH_DATA (info, codep + 1);
13338       threebyte = *codep;
13339       dp = &dis386_twobyte[threebyte];
13340       need_modrm = twobyte_has_modrm[*codep];
13341       codep++;
13342     }
13343   else
13344     {
13345       dp = &dis386[*codep];
13346       need_modrm = onebyte_has_modrm[*codep];
13347       codep++;
13348     }
13349
13350   /* Save sizeflag for printing the extra prefixes later before updating
13351      it for mnemonic and operand processing.  The prefix names depend
13352      only on the address mode.  */
13353   orig_sizeflag = sizeflag;
13354   if (prefixes & PREFIX_ADDR)
13355     sizeflag ^= AFLAG;
13356   if ((prefixes & PREFIX_DATA))
13357     sizeflag ^= DFLAG;
13358
13359   end_codep = codep;
13360   if (need_modrm)
13361     {
13362       FETCH_DATA (info, codep + 1);
13363       modrm.mod = (*codep >> 6) & 3;
13364       modrm.reg = (*codep >> 3) & 7;
13365       modrm.rm = *codep & 7;
13366     }
13367
13368   need_vex = 0;
13369   need_vex_reg = 0;
13370   vex_w_done = 0;
13371   vex.evex = 0;
13372
13373   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13374     {
13375       get_sib (info, sizeflag);
13376       dofloat (sizeflag);
13377     }
13378   else
13379     {
13380       dp = get_valid_dis386 (dp, info);
13381       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13382         {
13383           get_sib (info, sizeflag);
13384           for (i = 0; i < MAX_OPERANDS; ++i)
13385             {
13386               obufp = op_out[i];
13387               op_ad = MAX_OPERANDS - 1 - i;
13388               if (dp->op[i].rtn)
13389                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13390               /* For EVEX instruction after the last operand masking
13391                  should be printed.  */
13392               if (i == 0 && vex.evex)
13393                 {
13394                   /* Don't print {%k0}.  */
13395                   if (vex.mask_register_specifier)
13396                     {
13397                       oappend ("{");
13398                       oappend (names_mask[vex.mask_register_specifier]);
13399                       oappend ("}");
13400                     }
13401                   if (vex.zeroing)
13402                     oappend ("{z}");
13403                 }
13404             }
13405         }
13406     }
13407
13408   /* Check if the REX prefix is used.  */
13409   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13410     all_prefixes[last_rex_prefix] = 0;
13411
13412   /* Check if the SEG prefix is used.  */
13413   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13414                    | PREFIX_FS | PREFIX_GS)) != 0
13415       && (used_prefixes & active_seg_prefix) != 0)
13416     all_prefixes[last_seg_prefix] = 0;
13417
13418   /* Check if the ADDR prefix is used.  */
13419   if ((prefixes & PREFIX_ADDR) != 0
13420       && (used_prefixes & PREFIX_ADDR) != 0)
13421     all_prefixes[last_addr_prefix] = 0;
13422
13423   /* Check if the DATA prefix is used.  */
13424   if ((prefixes & PREFIX_DATA) != 0
13425       && (used_prefixes & PREFIX_DATA) != 0)
13426     all_prefixes[last_data_prefix] = 0;
13427
13428   /* Print the extra prefixes.  */
13429   prefix_length = 0;
13430   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13431     if (all_prefixes[i])
13432       {
13433         const char *name;
13434         name = prefix_name (all_prefixes[i], orig_sizeflag);
13435         if (name == NULL)
13436           abort ();
13437         prefix_length += strlen (name) + 1;
13438         (*info->fprintf_func) (info->stream, "%s ", name);
13439       }
13440
13441   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13442      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13443      used by putop and MMX/SSE operand and may be overriden by the
13444      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13445      separately.  */
13446   if (dp->prefix_requirement == PREFIX_OPCODE
13447       && dp != &bad_opcode
13448       && (((prefixes
13449             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13450            && (used_prefixes
13451                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13452           || ((((prefixes
13453                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13454                 == PREFIX_DATA)
13455                && (used_prefixes & PREFIX_DATA) == 0))))
13456     {
13457       (*info->fprintf_func) (info->stream, "(bad)");
13458       return end_codep - priv.the_buffer;
13459     }
13460
13461   /* Check maximum code length.  */
13462   if ((codep - start_codep) > MAX_CODE_LENGTH)
13463     {
13464       (*info->fprintf_func) (info->stream, "(bad)");
13465       return MAX_CODE_LENGTH;
13466     }
13467
13468   obufp = mnemonicendp;
13469   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13470     oappend (" ");
13471   oappend (" ");
13472   (*info->fprintf_func) (info->stream, "%s", obuf);
13473
13474   /* The enter and bound instructions are printed with operands in the same
13475      order as the intel book; everything else is printed in reverse order.  */
13476   if (intel_syntax || two_source_ops)
13477     {
13478       bfd_vma riprel;
13479
13480       for (i = 0; i < MAX_OPERANDS; ++i)
13481         op_txt[i] = op_out[i];
13482
13483       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13484           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13485         {
13486           op_txt[2] = op_out[3];
13487           op_txt[3] = op_out[2];
13488         }
13489
13490       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13491         {
13492           op_ad = op_index[i];
13493           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13494           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13495           riprel = op_riprel[i];
13496           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13497           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13498         }
13499     }
13500   else
13501     {
13502       for (i = 0; i < MAX_OPERANDS; ++i)
13503         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13504     }
13505
13506   needcomma = 0;
13507   for (i = 0; i < MAX_OPERANDS; ++i)
13508     if (*op_txt[i])
13509       {
13510         if (needcomma)
13511           (*info->fprintf_func) (info->stream, ",");
13512         if (op_index[i] != -1 && !op_riprel[i])
13513           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13514         else
13515           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13516         needcomma = 1;
13517       }
13518
13519   for (i = 0; i < MAX_OPERANDS; i++)
13520     if (op_index[i] != -1 && op_riprel[i])
13521       {
13522         (*info->fprintf_func) (info->stream, "        # ");
13523         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13524                                                 + op_address[op_index[i]]), info);
13525         break;
13526       }
13527   return codep - priv.the_buffer;
13528 }
13529
13530 static const char *float_mem[] = {
13531   /* d8 */
13532   "fadd{s|}",
13533   "fmul{s|}",
13534   "fcom{s|}",
13535   "fcomp{s|}",
13536   "fsub{s|}",
13537   "fsubr{s|}",
13538   "fdiv{s|}",
13539   "fdivr{s|}",
13540   /* d9 */
13541   "fld{s|}",
13542   "(bad)",
13543   "fst{s|}",
13544   "fstp{s|}",
13545   "fldenvIC",
13546   "fldcw",
13547   "fNstenvIC",
13548   "fNstcw",
13549   /* da */
13550   "fiadd{l|}",
13551   "fimul{l|}",
13552   "ficom{l|}",
13553   "ficomp{l|}",
13554   "fisub{l|}",
13555   "fisubr{l|}",
13556   "fidiv{l|}",
13557   "fidivr{l|}",
13558   /* db */
13559   "fild{l|}",
13560   "fisttp{l|}",
13561   "fist{l|}",
13562   "fistp{l|}",
13563   "(bad)",
13564   "fld{t||t|}",
13565   "(bad)",
13566   "fstp{t||t|}",
13567   /* dc */
13568   "fadd{l|}",
13569   "fmul{l|}",
13570   "fcom{l|}",
13571   "fcomp{l|}",
13572   "fsub{l|}",
13573   "fsubr{l|}",
13574   "fdiv{l|}",
13575   "fdivr{l|}",
13576   /* dd */
13577   "fld{l|}",
13578   "fisttp{ll|}",
13579   "fst{l||}",
13580   "fstp{l|}",
13581   "frstorIC",
13582   "(bad)",
13583   "fNsaveIC",
13584   "fNstsw",
13585   /* de */
13586   "fiadd{s|}",
13587   "fimul{s|}",
13588   "ficom{s|}",
13589   "ficomp{s|}",
13590   "fisub{s|}",
13591   "fisubr{s|}",
13592   "fidiv{s|}",
13593   "fidivr{s|}",
13594   /* df */
13595   "fild{s|}",
13596   "fisttp{s|}",
13597   "fist{s|}",
13598   "fistp{s|}",
13599   "fbld",
13600   "fild{ll|}",
13601   "fbstp",
13602   "fistp{ll|}",
13603 };
13604
13605 static const unsigned char float_mem_mode[] = {
13606   /* d8 */
13607   d_mode,
13608   d_mode,
13609   d_mode,
13610   d_mode,
13611   d_mode,
13612   d_mode,
13613   d_mode,
13614   d_mode,
13615   /* d9 */
13616   d_mode,
13617   0,
13618   d_mode,
13619   d_mode,
13620   0,
13621   w_mode,
13622   0,
13623   w_mode,
13624   /* da */
13625   d_mode,
13626   d_mode,
13627   d_mode,
13628   d_mode,
13629   d_mode,
13630   d_mode,
13631   d_mode,
13632   d_mode,
13633   /* db */
13634   d_mode,
13635   d_mode,
13636   d_mode,
13637   d_mode,
13638   0,
13639   t_mode,
13640   0,
13641   t_mode,
13642   /* dc */
13643   q_mode,
13644   q_mode,
13645   q_mode,
13646   q_mode,
13647   q_mode,
13648   q_mode,
13649   q_mode,
13650   q_mode,
13651   /* dd */
13652   q_mode,
13653   q_mode,
13654   q_mode,
13655   q_mode,
13656   0,
13657   0,
13658   0,
13659   w_mode,
13660   /* de */
13661   w_mode,
13662   w_mode,
13663   w_mode,
13664   w_mode,
13665   w_mode,
13666   w_mode,
13667   w_mode,
13668   w_mode,
13669   /* df */
13670   w_mode,
13671   w_mode,
13672   w_mode,
13673   w_mode,
13674   t_mode,
13675   q_mode,
13676   t_mode,
13677   q_mode
13678 };
13679
13680 #define ST { OP_ST, 0 }
13681 #define STi { OP_STi, 0 }
13682
13683 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13684 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13685 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13686 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13687 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13688 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13689 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13690 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13691 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13692
13693 static const struct dis386 float_reg[][8] = {
13694   /* d8 */
13695   {
13696     { "fadd",   { ST, STi }, 0 },
13697     { "fmul",   { ST, STi }, 0 },
13698     { "fcom",   { STi }, 0 },
13699     { "fcomp",  { STi }, 0 },
13700     { "fsub",   { ST, STi }, 0 },
13701     { "fsubr",  { ST, STi }, 0 },
13702     { "fdiv",   { ST, STi }, 0 },
13703     { "fdivr",  { ST, STi }, 0 },
13704   },
13705   /* d9 */
13706   {
13707     { "fld",    { STi }, 0 },
13708     { "fxch",   { STi }, 0 },
13709     { FGRPd9_2 },
13710     { Bad_Opcode },
13711     { FGRPd9_4 },
13712     { FGRPd9_5 },
13713     { FGRPd9_6 },
13714     { FGRPd9_7 },
13715   },
13716   /* da */
13717   {
13718     { "fcmovb", { ST, STi }, 0 },
13719     { "fcmove", { ST, STi }, 0 },
13720     { "fcmovbe",{ ST, STi }, 0 },
13721     { "fcmovu", { ST, STi }, 0 },
13722     { Bad_Opcode },
13723     { FGRPda_5 },
13724     { Bad_Opcode },
13725     { Bad_Opcode },
13726   },
13727   /* db */
13728   {
13729     { "fcmovnb",{ ST, STi }, 0 },
13730     { "fcmovne",{ ST, STi }, 0 },
13731     { "fcmovnbe",{ ST, STi }, 0 },
13732     { "fcmovnu",{ ST, STi }, 0 },
13733     { FGRPdb_4 },
13734     { "fucomi", { ST, STi }, 0 },
13735     { "fcomi",  { ST, STi }, 0 },
13736     { Bad_Opcode },
13737   },
13738   /* dc */
13739   {
13740     { "fadd",   { STi, ST }, 0 },
13741     { "fmul",   { STi, ST }, 0 },
13742     { Bad_Opcode },
13743     { Bad_Opcode },
13744     { "fsub{!M|r}",     { STi, ST }, 0 },
13745     { "fsub{M|}",       { STi, ST }, 0 },
13746     { "fdiv{!M|r}",     { STi, ST }, 0 },
13747     { "fdiv{M|}",       { STi, ST }, 0 },
13748   },
13749   /* dd */
13750   {
13751     { "ffree",  { STi }, 0 },
13752     { Bad_Opcode },
13753     { "fst",    { STi }, 0 },
13754     { "fstp",   { STi }, 0 },
13755     { "fucom",  { STi }, 0 },
13756     { "fucomp", { STi }, 0 },
13757     { Bad_Opcode },
13758     { Bad_Opcode },
13759   },
13760   /* de */
13761   {
13762     { "faddp",  { STi, ST }, 0 },
13763     { "fmulp",  { STi, ST }, 0 },
13764     { Bad_Opcode },
13765     { FGRPde_3 },
13766     { "fsub{!M|r}p",    { STi, ST }, 0 },
13767     { "fsub{M|}p",      { STi, ST }, 0 },
13768     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13769     { "fdiv{M|}p",      { STi, ST }, 0 },
13770   },
13771   /* df */
13772   {
13773     { "ffreep", { STi }, 0 },
13774     { Bad_Opcode },
13775     { Bad_Opcode },
13776     { Bad_Opcode },
13777     { FGRPdf_4 },
13778     { "fucomip", { ST, STi }, 0 },
13779     { "fcomip", { ST, STi }, 0 },
13780     { Bad_Opcode },
13781   },
13782 };
13783
13784 static char *fgrps[][8] = {
13785   /* Bad opcode 0 */
13786   {
13787     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13788   },
13789
13790   /* d9_2  1 */
13791   {
13792     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13793   },
13794
13795   /* d9_4  2 */
13796   {
13797     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13798   },
13799
13800   /* d9_5  3 */
13801   {
13802     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13803   },
13804
13805   /* d9_6  4 */
13806   {
13807     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13808   },
13809
13810   /* d9_7  5 */
13811   {
13812     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13813   },
13814
13815   /* da_5  6 */
13816   {
13817     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13818   },
13819
13820   /* db_4  7 */
13821   {
13822     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13823     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13824   },
13825
13826   /* de_3  8 */
13827   {
13828     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13829   },
13830
13831   /* df_4  9 */
13832   {
13833     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13834   },
13835 };
13836
13837 static void
13838 swap_operand (void)
13839 {
13840   mnemonicendp[0] = '.';
13841   mnemonicendp[1] = 's';
13842   mnemonicendp += 2;
13843 }
13844
13845 static void
13846 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13847                int sizeflag ATTRIBUTE_UNUSED)
13848 {
13849   /* Skip mod/rm byte.  */
13850   MODRM_CHECK;
13851   codep++;
13852 }
13853
13854 static void
13855 dofloat (int sizeflag)
13856 {
13857   const struct dis386 *dp;
13858   unsigned char floatop;
13859
13860   floatop = codep[-1];
13861
13862   if (modrm.mod != 3)
13863     {
13864       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13865
13866       putop (float_mem[fp_indx], sizeflag);
13867       obufp = op_out[0];
13868       op_ad = 2;
13869       OP_E (float_mem_mode[fp_indx], sizeflag);
13870       return;
13871     }
13872   /* Skip mod/rm byte.  */
13873   MODRM_CHECK;
13874   codep++;
13875
13876   dp = &float_reg[floatop - 0xd8][modrm.reg];
13877   if (dp->name == NULL)
13878     {
13879       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13880
13881       /* Instruction fnstsw is only one with strange arg.  */
13882       if (floatop == 0xdf && codep[-1] == 0xe0)
13883         strcpy (op_out[0], names16[0]);
13884     }
13885   else
13886     {
13887       putop (dp->name, sizeflag);
13888
13889       obufp = op_out[0];
13890       op_ad = 2;
13891       if (dp->op[0].rtn)
13892         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13893
13894       obufp = op_out[1];
13895       op_ad = 1;
13896       if (dp->op[1].rtn)
13897         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13898     }
13899 }
13900
13901 /* Like oappend (below), but S is a string starting with '%'.
13902    In Intel syntax, the '%' is elided.  */
13903 static void
13904 oappend_maybe_intel (const char *s)
13905 {
13906   oappend (s + intel_syntax);
13907 }
13908
13909 static void
13910 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13911 {
13912   oappend_maybe_intel ("%st");
13913 }
13914
13915 static void
13916 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13917 {
13918   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13919   oappend_maybe_intel (scratchbuf);
13920 }
13921
13922 /* Capital letters in template are macros.  */
13923 static int
13924 putop (const char *in_template, int sizeflag)
13925 {
13926   const char *p;
13927   int alt = 0;
13928   int cond = 1;
13929   unsigned int l = 0, len = 1;
13930   char last[4];
13931
13932 #define SAVE_LAST(c)                    \
13933   if (l < len && l < sizeof (last))     \
13934     last[l++] = c;                      \
13935   else                                  \
13936     abort ();
13937
13938   for (p = in_template; *p; p++)
13939     {
13940       switch (*p)
13941         {
13942         default:
13943           *obufp++ = *p;
13944           break;
13945         case '%':
13946           len++;
13947           break;
13948         case '!':
13949           cond = 0;
13950           break;
13951         case '{':
13952           if (intel_syntax)
13953             {
13954               while (*++p != '|')
13955                 if (*p == '}' || *p == '\0')
13956                   abort ();
13957             }
13958           /* Fall through.  */
13959         case 'I':
13960           alt = 1;
13961           continue;
13962         case '|':
13963           while (*++p != '}')
13964             {
13965               if (*p == '\0')
13966                 abort ();
13967             }
13968           break;
13969         case '}':
13970           break;
13971         case 'A':
13972           if (intel_syntax)
13973             break;
13974           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13975             *obufp++ = 'b';
13976           break;
13977         case 'B':
13978           if (l == 0 && len == 1)
13979             {
13980 case_B:
13981               if (intel_syntax)
13982                 break;
13983               if (sizeflag & SUFFIX_ALWAYS)
13984                 *obufp++ = 'b';
13985             }
13986           else
13987             {
13988               if (l != 1
13989                   || len != 2
13990                   || last[0] != 'L')
13991                 {
13992                   SAVE_LAST (*p);
13993                   break;
13994                 }
13995
13996               if (address_mode == mode_64bit
13997                   && !(prefixes & PREFIX_ADDR))
13998                 {
13999                   *obufp++ = 'a';
14000                   *obufp++ = 'b';
14001                   *obufp++ = 's';
14002                 }
14003
14004               goto case_B;
14005             }
14006           break;
14007         case 'C':
14008           if (intel_syntax && !alt)
14009             break;
14010           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14011             {
14012               if (sizeflag & DFLAG)
14013                 *obufp++ = intel_syntax ? 'd' : 'l';
14014               else
14015                 *obufp++ = intel_syntax ? 'w' : 's';
14016               used_prefixes |= (prefixes & PREFIX_DATA);
14017             }
14018           break;
14019         case 'D':
14020           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14021             break;
14022           USED_REX (REX_W);
14023           if (modrm.mod == 3)
14024             {
14025               if (rex & REX_W)
14026                 *obufp++ = 'q';
14027               else
14028                 {
14029                   if (sizeflag & DFLAG)
14030                     *obufp++ = intel_syntax ? 'd' : 'l';
14031                   else
14032                     *obufp++ = 'w';
14033                   used_prefixes |= (prefixes & PREFIX_DATA);
14034                 }
14035             }
14036           else
14037             *obufp++ = 'w';
14038           break;
14039         case 'E':               /* For jcxz/jecxz */
14040           if (address_mode == mode_64bit)
14041             {
14042               if (sizeflag & AFLAG)
14043                 *obufp++ = 'r';
14044               else
14045                 *obufp++ = 'e';
14046             }
14047           else
14048             if (sizeflag & AFLAG)
14049               *obufp++ = 'e';
14050           used_prefixes |= (prefixes & PREFIX_ADDR);
14051           break;
14052         case 'F':
14053           if (intel_syntax)
14054             break;
14055           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14056             {
14057               if (sizeflag & AFLAG)
14058                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14059               else
14060                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14061               used_prefixes |= (prefixes & PREFIX_ADDR);
14062             }
14063           break;
14064         case 'G':
14065           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14066             break;
14067           if ((rex & REX_W) || (sizeflag & DFLAG))
14068             *obufp++ = 'l';
14069           else
14070             *obufp++ = 'w';
14071           if (!(rex & REX_W))
14072             used_prefixes |= (prefixes & PREFIX_DATA);
14073           break;
14074         case 'H':
14075           if (intel_syntax)
14076             break;
14077           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14078               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14079             {
14080               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14081               *obufp++ = ',';
14082               *obufp++ = 'p';
14083               if (prefixes & PREFIX_DS)
14084                 *obufp++ = 't';
14085               else
14086                 *obufp++ = 'n';
14087             }
14088           break;
14089         case 'J':
14090           if (intel_syntax)
14091             break;
14092           *obufp++ = 'l';
14093           break;
14094         case 'K':
14095           USED_REX (REX_W);
14096           if (rex & REX_W)
14097             *obufp++ = 'q';
14098           else
14099             *obufp++ = 'd';
14100           break;
14101         case 'Z':
14102           if (l != 0 || len != 1)
14103             {
14104               if (l != 1 || len != 2 || last[0] != 'X')
14105                 {
14106                   SAVE_LAST (*p);
14107                   break;
14108                 }
14109               if (!need_vex || !vex.evex)
14110                 abort ();
14111               if (intel_syntax
14112                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14113                 break;
14114               switch (vex.length)
14115                 {
14116                 case 128:
14117                   *obufp++ = 'x';
14118                   break;
14119                 case 256:
14120                   *obufp++ = 'y';
14121                   break;
14122                 case 512:
14123                   *obufp++ = 'z';
14124                   break;
14125                 default:
14126                   abort ();
14127                 }
14128               break;
14129             }
14130           if (intel_syntax)
14131             break;
14132           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14133             {
14134               *obufp++ = 'q';
14135               break;
14136             }
14137           /* Fall through.  */
14138           goto case_L;
14139         case 'L':
14140           if (l != 0 || len != 1)
14141             {
14142               SAVE_LAST (*p);
14143               break;
14144             }
14145 case_L:
14146           if (intel_syntax)
14147             break;
14148           if (sizeflag & SUFFIX_ALWAYS)
14149             *obufp++ = 'l';
14150           break;
14151         case 'M':
14152           if (intel_mnemonic != cond)
14153             *obufp++ = 'r';
14154           break;
14155         case 'N':
14156           if ((prefixes & PREFIX_FWAIT) == 0)
14157             *obufp++ = 'n';
14158           else
14159             used_prefixes |= PREFIX_FWAIT;
14160           break;
14161         case 'O':
14162           USED_REX (REX_W);
14163           if (rex & REX_W)
14164             *obufp++ = 'o';
14165           else if (intel_syntax && (sizeflag & DFLAG))
14166             *obufp++ = 'q';
14167           else
14168             *obufp++ = 'd';
14169           if (!(rex & REX_W))
14170             used_prefixes |= (prefixes & PREFIX_DATA);
14171           break;
14172         case '&':
14173           if (!intel_syntax
14174               && address_mode == mode_64bit
14175               && isa64 == intel64)
14176             {
14177               *obufp++ = 'q';
14178               break;
14179             }
14180           /* Fall through.  */
14181         case 'T':
14182           if (!intel_syntax
14183               && address_mode == mode_64bit
14184               && ((sizeflag & DFLAG) || (rex & REX_W)))
14185             {
14186               *obufp++ = 'q';
14187               break;
14188             }
14189           /* Fall through.  */
14190           goto case_P;
14191         case 'P':
14192           if (l == 0 && len == 1)
14193             {
14194 case_P:
14195               if (intel_syntax)
14196                 {
14197                   if ((rex & REX_W) == 0
14198                       && (prefixes & PREFIX_DATA))
14199                     {
14200                       if ((sizeflag & DFLAG) == 0)
14201                         *obufp++ = 'w';
14202                       used_prefixes |= (prefixes & PREFIX_DATA);
14203                     }
14204                   break;
14205                 }
14206               if ((prefixes & PREFIX_DATA)
14207                   || (rex & REX_W)
14208                   || (sizeflag & SUFFIX_ALWAYS))
14209                 {
14210                   USED_REX (REX_W);
14211                   if (rex & REX_W)
14212                     *obufp++ = 'q';
14213                   else
14214                     {
14215                       if (sizeflag & DFLAG)
14216                         *obufp++ = 'l';
14217                       else
14218                         *obufp++ = 'w';
14219                       used_prefixes |= (prefixes & PREFIX_DATA);
14220                     }
14221                 }
14222             }
14223           else
14224             {
14225               if (l != 1 || len != 2 || last[0] != 'L')
14226                 {
14227                   SAVE_LAST (*p);
14228                   break;
14229                 }
14230
14231               if ((prefixes & PREFIX_DATA)
14232                   || (rex & REX_W)
14233                   || (sizeflag & SUFFIX_ALWAYS))
14234                 {
14235                   USED_REX (REX_W);
14236                   if (rex & REX_W)
14237                     *obufp++ = 'q';
14238                   else
14239                     {
14240                       if (sizeflag & DFLAG)
14241                         *obufp++ = intel_syntax ? 'd' : 'l';
14242                       else
14243                         *obufp++ = 'w';
14244                       used_prefixes |= (prefixes & PREFIX_DATA);
14245                     }
14246                 }
14247             }
14248           break;
14249         case 'U':
14250           if (intel_syntax)
14251             break;
14252           if (address_mode == mode_64bit
14253               && ((sizeflag & DFLAG) || (rex & REX_W)))
14254             {
14255               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14256                 *obufp++ = 'q';
14257               break;
14258             }
14259           /* Fall through.  */
14260           goto case_Q;
14261         case 'Q':
14262           if (l == 0 && len == 1)
14263             {
14264 case_Q:
14265               if (intel_syntax && !alt)
14266                 break;
14267               USED_REX (REX_W);
14268               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14269                 {
14270                   if (rex & REX_W)
14271                     *obufp++ = 'q';
14272                   else
14273                     {
14274                       if (sizeflag & DFLAG)
14275                         *obufp++ = intel_syntax ? 'd' : 'l';
14276                       else
14277                         *obufp++ = 'w';
14278                       used_prefixes |= (prefixes & PREFIX_DATA);
14279                     }
14280                 }
14281             }
14282           else
14283             {
14284               if (l != 1 || len != 2 || last[0] != 'L')
14285                 {
14286                   SAVE_LAST (*p);
14287                   break;
14288                 }
14289               if (intel_syntax
14290                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14291                 break;
14292               if ((rex & REX_W))
14293                 {
14294                   USED_REX (REX_W);
14295                   *obufp++ = 'q';
14296                 }
14297               else
14298                 *obufp++ = 'l';
14299             }
14300           break;
14301         case 'R':
14302           USED_REX (REX_W);
14303           if (rex & REX_W)
14304             *obufp++ = 'q';
14305           else if (sizeflag & DFLAG)
14306             {
14307               if (intel_syntax)
14308                   *obufp++ = 'd';
14309               else
14310                   *obufp++ = 'l';
14311             }
14312           else
14313             *obufp++ = 'w';
14314           if (intel_syntax && !p[1]
14315               && ((rex & REX_W) || (sizeflag & DFLAG)))
14316             *obufp++ = 'e';
14317           if (!(rex & REX_W))
14318             used_prefixes |= (prefixes & PREFIX_DATA);
14319           break;
14320         case 'V':
14321           if (l == 0 && len == 1)
14322             {
14323               if (intel_syntax)
14324                 break;
14325               if (address_mode == mode_64bit
14326                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14327                 {
14328                   if (sizeflag & SUFFIX_ALWAYS)
14329                     *obufp++ = 'q';
14330                   break;
14331                 }
14332             }
14333           else
14334             {
14335               if (l != 1
14336                   || len != 2
14337                   || last[0] != 'L')
14338                 {
14339                   SAVE_LAST (*p);
14340                   break;
14341                 }
14342
14343               if (rex & REX_W)
14344                 {
14345                   *obufp++ = 'a';
14346                   *obufp++ = 'b';
14347                   *obufp++ = 's';
14348                 }
14349             }
14350           /* Fall through.  */
14351           goto case_S;
14352         case 'S':
14353           if (l == 0 && len == 1)
14354             {
14355 case_S:
14356               if (intel_syntax)
14357                 break;
14358               if (sizeflag & SUFFIX_ALWAYS)
14359                 {
14360                   if (rex & REX_W)
14361                     *obufp++ = 'q';
14362                   else
14363                     {
14364                       if (sizeflag & DFLAG)
14365                         *obufp++ = 'l';
14366                       else
14367                         *obufp++ = 'w';
14368                       used_prefixes |= (prefixes & PREFIX_DATA);
14369                     }
14370                 }
14371             }
14372           else
14373             {
14374               if (l != 1
14375                   || len != 2
14376                   || last[0] != 'L')
14377                 {
14378                   SAVE_LAST (*p);
14379                   break;
14380                 }
14381
14382               if (address_mode == mode_64bit
14383                   && !(prefixes & PREFIX_ADDR))
14384                 {
14385                   *obufp++ = 'a';
14386                   *obufp++ = 'b';
14387                   *obufp++ = 's';
14388                 }
14389
14390               goto case_S;
14391             }
14392           break;
14393         case 'X':
14394           if (l != 0 || len != 1)
14395             {
14396               SAVE_LAST (*p);
14397               break;
14398             }
14399           if (need_vex && vex.prefix)
14400             {
14401               if (vex.prefix == DATA_PREFIX_OPCODE)
14402                 *obufp++ = 'd';
14403               else
14404                 *obufp++ = 's';
14405             }
14406           else
14407             {
14408               if (prefixes & PREFIX_DATA)
14409                 *obufp++ = 'd';
14410               else
14411                 *obufp++ = 's';
14412               used_prefixes |= (prefixes & PREFIX_DATA);
14413             }
14414           break;
14415         case 'Y':
14416           if (l == 0 && len == 1)
14417             {
14418               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14419                 break;
14420               if (rex & REX_W)
14421                 {
14422                   USED_REX (REX_W);
14423                   *obufp++ = 'q';
14424                 }
14425               break;
14426             }
14427           else
14428             {
14429               if (l != 1 || len != 2 || last[0] != 'X')
14430                 {
14431                   SAVE_LAST (*p);
14432                   break;
14433                 }
14434               if (!need_vex)
14435                 abort ();
14436               if (intel_syntax
14437                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14438                 break;
14439               switch (vex.length)
14440                 {
14441                 case 128:
14442                   *obufp++ = 'x';
14443                   break;
14444                 case 256:
14445                   *obufp++ = 'y';
14446                   break;
14447                 case 512:
14448                   if (!vex.evex)
14449                 default:
14450                     abort ();
14451                 }
14452             }
14453           break;
14454         case 'W':
14455           if (l == 0 && len == 1)
14456             {
14457               /* operand size flag for cwtl, cbtw */
14458               USED_REX (REX_W);
14459               if (rex & REX_W)
14460                 {
14461                   if (intel_syntax)
14462                     *obufp++ = 'd';
14463                   else
14464                     *obufp++ = 'l';
14465                 }
14466               else if (sizeflag & DFLAG)
14467                 *obufp++ = 'w';
14468               else
14469                 *obufp++ = 'b';
14470               if (!(rex & REX_W))
14471                 used_prefixes |= (prefixes & PREFIX_DATA);
14472             }
14473           else
14474             {
14475               if (l != 1
14476                   || len != 2
14477                   || (last[0] != 'X'
14478                       && last[0] != 'L'))
14479                 {
14480                   SAVE_LAST (*p);
14481                   break;
14482                 }
14483               if (!need_vex)
14484                 abort ();
14485               if (last[0] == 'X')
14486                 *obufp++ = vex.w ? 'd': 's';
14487               else
14488                 *obufp++ = vex.w ? 'q': 'd';
14489             }
14490           break;
14491         case '^':
14492           if (intel_syntax)
14493             break;
14494           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14495             {
14496               if (sizeflag & DFLAG)
14497                 *obufp++ = 'l';
14498               else
14499                 *obufp++ = 'w';
14500               used_prefixes |= (prefixes & PREFIX_DATA);
14501             }
14502           break;
14503         case '@':
14504           if (intel_syntax)
14505             break;
14506           if (address_mode == mode_64bit
14507               && (isa64 == intel64
14508                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14509               *obufp++ = 'q';
14510           else if ((prefixes & PREFIX_DATA))
14511             {
14512               if (!(sizeflag & DFLAG))
14513                 *obufp++ = 'w';
14514               used_prefixes |= (prefixes & PREFIX_DATA);
14515             }
14516           break;
14517         }
14518       alt = 0;
14519     }
14520   *obufp = 0;
14521   mnemonicendp = obufp;
14522   return 0;
14523 }
14524
14525 static void
14526 oappend (const char *s)
14527 {
14528   obufp = stpcpy (obufp, s);
14529 }
14530
14531 static void
14532 append_seg (void)
14533 {
14534   /* Only print the active segment register.  */
14535   if (!active_seg_prefix)
14536     return;
14537
14538   used_prefixes |= active_seg_prefix;
14539   switch (active_seg_prefix)
14540     {
14541     case PREFIX_CS:
14542       oappend_maybe_intel ("%cs:");
14543       break;
14544     case PREFIX_DS:
14545       oappend_maybe_intel ("%ds:");
14546       break;
14547     case PREFIX_SS:
14548       oappend_maybe_intel ("%ss:");
14549       break;
14550     case PREFIX_ES:
14551       oappend_maybe_intel ("%es:");
14552       break;
14553     case PREFIX_FS:
14554       oappend_maybe_intel ("%fs:");
14555       break;
14556     case PREFIX_GS:
14557       oappend_maybe_intel ("%gs:");
14558       break;
14559     default:
14560       break;
14561     }
14562 }
14563
14564 static void
14565 OP_indirE (int bytemode, int sizeflag)
14566 {
14567   if (!intel_syntax)
14568     oappend ("*");
14569   OP_E (bytemode, sizeflag);
14570 }
14571
14572 static void
14573 print_operand_value (char *buf, int hex, bfd_vma disp)
14574 {
14575   if (address_mode == mode_64bit)
14576     {
14577       if (hex)
14578         {
14579           char tmp[30];
14580           int i;
14581           buf[0] = '0';
14582           buf[1] = 'x';
14583           sprintf_vma (tmp, disp);
14584           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14585           strcpy (buf + 2, tmp + i);
14586         }
14587       else
14588         {
14589           bfd_signed_vma v = disp;
14590           char tmp[30];
14591           int i;
14592           if (v < 0)
14593             {
14594               *(buf++) = '-';
14595               v = -disp;
14596               /* Check for possible overflow on 0x8000000000000000.  */
14597               if (v < 0)
14598                 {
14599                   strcpy (buf, "9223372036854775808");
14600                   return;
14601                 }
14602             }
14603           if (!v)
14604             {
14605               strcpy (buf, "0");
14606               return;
14607             }
14608
14609           i = 0;
14610           tmp[29] = 0;
14611           while (v)
14612             {
14613               tmp[28 - i] = (v % 10) + '0';
14614               v /= 10;
14615               i++;
14616             }
14617           strcpy (buf, tmp + 29 - i);
14618         }
14619     }
14620   else
14621     {
14622       if (hex)
14623         sprintf (buf, "0x%x", (unsigned int) disp);
14624       else
14625         sprintf (buf, "%d", (int) disp);
14626     }
14627 }
14628
14629 /* Put DISP in BUF as signed hex number.  */
14630
14631 static void
14632 print_displacement (char *buf, bfd_vma disp)
14633 {
14634   bfd_signed_vma val = disp;
14635   char tmp[30];
14636   int i, j = 0;
14637
14638   if (val < 0)
14639     {
14640       buf[j++] = '-';
14641       val = -disp;
14642
14643       /* Check for possible overflow.  */
14644       if (val < 0)
14645         {
14646           switch (address_mode)
14647             {
14648             case mode_64bit:
14649               strcpy (buf + j, "0x8000000000000000");
14650               break;
14651             case mode_32bit:
14652               strcpy (buf + j, "0x80000000");
14653               break;
14654             case mode_16bit:
14655               strcpy (buf + j, "0x8000");
14656               break;
14657             }
14658           return;
14659         }
14660     }
14661
14662   buf[j++] = '0';
14663   buf[j++] = 'x';
14664
14665   sprintf_vma (tmp, (bfd_vma) val);
14666   for (i = 0; tmp[i] == '0'; i++)
14667     continue;
14668   if (tmp[i] == '\0')
14669     i--;
14670   strcpy (buf + j, tmp + i);
14671 }
14672
14673 static void
14674 intel_operand_size (int bytemode, int sizeflag)
14675 {
14676   if (vex.evex
14677       && vex.b
14678       && (bytemode == x_mode
14679           || bytemode == evex_half_bcst_xmmq_mode))
14680     {
14681       if (vex.w)
14682         oappend ("QWORD PTR ");
14683       else
14684         oappend ("DWORD PTR ");
14685       return;
14686     }
14687   switch (bytemode)
14688     {
14689     case b_mode:
14690     case b_swap_mode:
14691     case dqb_mode:
14692     case db_mode:
14693       oappend ("BYTE PTR ");
14694       break;
14695     case w_mode:
14696     case dw_mode:
14697     case dqw_mode:
14698       oappend ("WORD PTR ");
14699       break;
14700     case indir_v_mode:
14701       if (address_mode == mode_64bit && isa64 == intel64)
14702         {
14703           oappend ("QWORD PTR ");
14704           break;
14705         }
14706       /* Fall through.  */
14707     case stack_v_mode:
14708       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14709         {
14710           oappend ("QWORD PTR ");
14711           break;
14712         }
14713       /* Fall through.  */
14714     case v_mode:
14715     case v_swap_mode:
14716     case dq_mode:
14717       USED_REX (REX_W);
14718       if (rex & REX_W)
14719         oappend ("QWORD PTR ");
14720       else
14721         {
14722           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14723             oappend ("DWORD PTR ");
14724           else
14725             oappend ("WORD PTR ");
14726           used_prefixes |= (prefixes & PREFIX_DATA);
14727         }
14728       break;
14729     case z_mode:
14730       if ((rex & REX_W) || (sizeflag & DFLAG))
14731         *obufp++ = 'D';
14732       oappend ("WORD PTR ");
14733       if (!(rex & REX_W))
14734         used_prefixes |= (prefixes & PREFIX_DATA);
14735       break;
14736     case a_mode:
14737       if (sizeflag & DFLAG)
14738         oappend ("QWORD PTR ");
14739       else
14740         oappend ("DWORD PTR ");
14741       used_prefixes |= (prefixes & PREFIX_DATA);
14742       break;
14743     case d_mode:
14744     case d_scalar_mode:
14745     case d_scalar_swap_mode:
14746     case d_swap_mode:
14747     case dqd_mode:
14748       oappend ("DWORD PTR ");
14749       break;
14750     case q_mode:
14751     case q_scalar_mode:
14752     case q_scalar_swap_mode:
14753     case q_swap_mode:
14754       oappend ("QWORD PTR ");
14755       break;
14756     case m_mode:
14757       if (address_mode == mode_64bit)
14758         oappend ("QWORD PTR ");
14759       else
14760         oappend ("DWORD PTR ");
14761       break;
14762     case f_mode:
14763       if (sizeflag & DFLAG)
14764         oappend ("FWORD PTR ");
14765       else
14766         oappend ("DWORD PTR ");
14767       used_prefixes |= (prefixes & PREFIX_DATA);
14768       break;
14769     case t_mode:
14770       oappend ("TBYTE PTR ");
14771       break;
14772     case x_mode:
14773     case x_swap_mode:
14774     case evex_x_gscat_mode:
14775     case evex_x_nobcst_mode:
14776     case b_scalar_mode:
14777     case w_scalar_mode:
14778       if (need_vex)
14779         {
14780           switch (vex.length)
14781             {
14782             case 128:
14783               oappend ("XMMWORD PTR ");
14784               break;
14785             case 256:
14786               oappend ("YMMWORD PTR ");
14787               break;
14788             case 512:
14789               oappend ("ZMMWORD PTR ");
14790               break;
14791             default:
14792               abort ();
14793             }
14794         }
14795       else
14796         oappend ("XMMWORD PTR ");
14797       break;
14798     case xmm_mode:
14799       oappend ("XMMWORD PTR ");
14800       break;
14801     case ymm_mode:
14802       oappend ("YMMWORD PTR ");
14803       break;
14804     case xmmq_mode:
14805     case evex_half_bcst_xmmq_mode:
14806       if (!need_vex)
14807         abort ();
14808
14809       switch (vex.length)
14810         {
14811         case 128:
14812           oappend ("QWORD PTR ");
14813           break;
14814         case 256:
14815           oappend ("XMMWORD PTR ");
14816           break;
14817         case 512:
14818           oappend ("YMMWORD PTR ");
14819           break;
14820         default:
14821           abort ();
14822         }
14823       break;
14824     case xmm_mb_mode:
14825       if (!need_vex)
14826         abort ();
14827
14828       switch (vex.length)
14829         {
14830         case 128:
14831         case 256:
14832         case 512:
14833           oappend ("BYTE PTR ");
14834           break;
14835         default:
14836           abort ();
14837         }
14838       break;
14839     case xmm_mw_mode:
14840       if (!need_vex)
14841         abort ();
14842
14843       switch (vex.length)
14844         {
14845         case 128:
14846         case 256:
14847         case 512:
14848           oappend ("WORD PTR ");
14849           break;
14850         default:
14851           abort ();
14852         }
14853       break;
14854     case xmm_md_mode:
14855       if (!need_vex)
14856         abort ();
14857
14858       switch (vex.length)
14859         {
14860         case 128:
14861         case 256:
14862         case 512:
14863           oappend ("DWORD PTR ");
14864           break;
14865         default:
14866           abort ();
14867         }
14868       break;
14869     case xmm_mq_mode:
14870       if (!need_vex)
14871         abort ();
14872
14873       switch (vex.length)
14874         {
14875         case 128:
14876         case 256:
14877         case 512:
14878           oappend ("QWORD PTR ");
14879           break;
14880         default:
14881           abort ();
14882         }
14883       break;
14884     case xmmdw_mode:
14885       if (!need_vex)
14886         abort ();
14887
14888       switch (vex.length)
14889         {
14890         case 128:
14891           oappend ("WORD PTR ");
14892           break;
14893         case 256:
14894           oappend ("DWORD PTR ");
14895           break;
14896         case 512:
14897           oappend ("QWORD PTR ");
14898           break;
14899         default:
14900           abort ();
14901         }
14902       break;
14903     case xmmqd_mode:
14904       if (!need_vex)
14905         abort ();
14906
14907       switch (vex.length)
14908         {
14909         case 128:
14910           oappend ("DWORD PTR ");
14911           break;
14912         case 256:
14913           oappend ("QWORD PTR ");
14914           break;
14915         case 512:
14916           oappend ("XMMWORD PTR ");
14917           break;
14918         default:
14919           abort ();
14920         }
14921       break;
14922     case ymmq_mode:
14923       if (!need_vex)
14924         abort ();
14925
14926       switch (vex.length)
14927         {
14928         case 128:
14929           oappend ("QWORD PTR ");
14930           break;
14931         case 256:
14932           oappend ("YMMWORD PTR ");
14933           break;
14934         case 512:
14935           oappend ("ZMMWORD PTR ");
14936           break;
14937         default:
14938           abort ();
14939         }
14940       break;
14941     case ymmxmm_mode:
14942       if (!need_vex)
14943         abort ();
14944
14945       switch (vex.length)
14946         {
14947         case 128:
14948         case 256:
14949           oappend ("XMMWORD PTR ");
14950           break;
14951         default:
14952           abort ();
14953         }
14954       break;
14955     case o_mode:
14956       oappend ("OWORD PTR ");
14957       break;
14958     case xmm_mdq_mode:
14959     case vex_w_dq_mode:
14960     case vex_scalar_w_dq_mode:
14961       if (!need_vex)
14962         abort ();
14963
14964       if (vex.w)
14965         oappend ("QWORD PTR ");
14966       else
14967         oappend ("DWORD PTR ");
14968       break;
14969     case vex_vsib_d_w_dq_mode:
14970     case vex_vsib_q_w_dq_mode:
14971       if (!need_vex)
14972         abort ();
14973
14974       if (!vex.evex)
14975         {
14976           if (vex.w)
14977             oappend ("QWORD PTR ");
14978           else
14979             oappend ("DWORD PTR ");
14980         }
14981       else
14982         {
14983           switch (vex.length)
14984             {
14985             case 128:
14986               oappend ("XMMWORD PTR ");
14987               break;
14988             case 256:
14989               oappend ("YMMWORD PTR ");
14990               break;
14991             case 512:
14992               oappend ("ZMMWORD PTR ");
14993               break;
14994             default:
14995               abort ();
14996             }
14997         }
14998       break;
14999     case vex_vsib_q_w_d_mode:
15000     case vex_vsib_d_w_d_mode:
15001       if (!need_vex || !vex.evex)
15002         abort ();
15003
15004       switch (vex.length)
15005         {
15006         case 128:
15007           oappend ("QWORD PTR ");
15008           break;
15009         case 256:
15010           oappend ("XMMWORD PTR ");
15011           break;
15012         case 512:
15013           oappend ("YMMWORD PTR ");
15014           break;
15015         default:
15016           abort ();
15017         }
15018
15019       break;
15020     case mask_bd_mode:
15021       if (!need_vex || vex.length != 128)
15022         abort ();
15023       if (vex.w)
15024         oappend ("DWORD PTR ");
15025       else
15026         oappend ("BYTE PTR ");
15027       break;
15028     case mask_mode:
15029       if (!need_vex)
15030         abort ();
15031       if (vex.w)
15032         oappend ("QWORD PTR ");
15033       else
15034         oappend ("WORD PTR ");
15035       break;
15036     case v_bnd_mode:
15037     default:
15038       break;
15039     }
15040 }
15041
15042 static void
15043 OP_E_register (int bytemode, int sizeflag)
15044 {
15045   int reg = modrm.rm;
15046   const char **names;
15047
15048   USED_REX (REX_B);
15049   if ((rex & REX_B))
15050     reg += 8;
15051
15052   if ((sizeflag & SUFFIX_ALWAYS)
15053       && (bytemode == b_swap_mode
15054           || bytemode == bnd_swap_mode
15055           || bytemode == v_swap_mode))
15056     swap_operand ();
15057
15058   switch (bytemode)
15059     {
15060     case b_mode:
15061     case b_swap_mode:
15062       USED_REX (0);
15063       if (rex)
15064         names = names8rex;
15065       else
15066         names = names8;
15067       break;
15068     case w_mode:
15069       names = names16;
15070       break;
15071     case d_mode:
15072     case dw_mode:
15073     case db_mode:
15074       names = names32;
15075       break;
15076     case q_mode:
15077       names = names64;
15078       break;
15079     case m_mode:
15080     case v_bnd_mode:
15081       names = address_mode == mode_64bit ? names64 : names32;
15082       break;
15083     case bnd_mode:
15084     case bnd_swap_mode:
15085       if (reg > 0x3)
15086         {
15087           oappend ("(bad)");
15088           return;
15089         }
15090       names = names_bnd;
15091       break;
15092     case indir_v_mode:
15093       if (address_mode == mode_64bit && isa64 == intel64)
15094         {
15095           names = names64;
15096           break;
15097         }
15098       /* Fall through.  */
15099     case stack_v_mode:
15100       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15101         {
15102           names = names64;
15103           break;
15104         }
15105       bytemode = v_mode;
15106       /* Fall through.  */
15107     case v_mode:
15108     case v_swap_mode:
15109     case dq_mode:
15110     case dqb_mode:
15111     case dqd_mode:
15112     case dqw_mode:
15113       USED_REX (REX_W);
15114       if (rex & REX_W)
15115         names = names64;
15116       else
15117         {
15118           if ((sizeflag & DFLAG)
15119               || (bytemode != v_mode
15120                   && bytemode != v_swap_mode))
15121             names = names32;
15122           else
15123             names = names16;
15124           used_prefixes |= (prefixes & PREFIX_DATA);
15125         }
15126       break;
15127     case mask_bd_mode:
15128     case mask_mode:
15129       if (reg > 0x7)
15130         {
15131           oappend ("(bad)");
15132           return;
15133         }
15134       names = names_mask;
15135       break;
15136     case 0:
15137       return;
15138     default:
15139       oappend (INTERNAL_DISASSEMBLER_ERROR);
15140       return;
15141     }
15142   oappend (names[reg]);
15143 }
15144
15145 static void
15146 OP_E_memory (int bytemode, int sizeflag)
15147 {
15148   bfd_vma disp = 0;
15149   int add = (rex & REX_B) ? 8 : 0;
15150   int riprel = 0;
15151   int shift;
15152
15153   if (vex.evex)
15154     {
15155       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15156       if (vex.b
15157           && bytemode != x_mode
15158           && bytemode != xmmq_mode
15159           && bytemode != evex_half_bcst_xmmq_mode)
15160         {
15161           BadOp ();
15162           return;
15163         }
15164       switch (bytemode)
15165         {
15166         case dqw_mode:
15167         case dw_mode:
15168           shift = 1;
15169           break;
15170         case dqb_mode:
15171         case db_mode:
15172           shift = 0;
15173           break;
15174         case vex_vsib_d_w_dq_mode:
15175         case vex_vsib_d_w_d_mode:
15176         case vex_vsib_q_w_dq_mode:
15177         case vex_vsib_q_w_d_mode:
15178         case evex_x_gscat_mode:
15179         case xmm_mdq_mode:
15180           shift = vex.w ? 3 : 2;
15181           break;
15182         case x_mode:
15183         case evex_half_bcst_xmmq_mode:
15184         case xmmq_mode:
15185           if (vex.b)
15186             {
15187               shift = vex.w ? 3 : 2;
15188               break;
15189             }
15190           /* Fall through.  */
15191         case xmmqd_mode:
15192         case xmmdw_mode:
15193         case ymmq_mode:
15194         case evex_x_nobcst_mode:
15195         case x_swap_mode:
15196           switch (vex.length)
15197             {
15198             case 128:
15199               shift = 4;
15200               break;
15201             case 256:
15202               shift = 5;
15203               break;
15204             case 512:
15205               shift = 6;
15206               break;
15207             default:
15208               abort ();
15209             }
15210           break;
15211         case ymm_mode:
15212           shift = 5;
15213           break;
15214         case xmm_mode:
15215           shift = 4;
15216           break;
15217         case xmm_mq_mode:
15218         case q_mode:
15219         case q_scalar_mode:
15220         case q_swap_mode:
15221         case q_scalar_swap_mode:
15222           shift = 3;
15223           break;
15224         case dqd_mode:
15225         case xmm_md_mode:
15226         case d_mode:
15227         case d_scalar_mode:
15228         case d_swap_mode:
15229         case d_scalar_swap_mode:
15230           shift = 2;
15231           break;
15232     case w_scalar_mode:
15233         case xmm_mw_mode:
15234           shift = 1;
15235           break;
15236     case b_scalar_mode:
15237         case xmm_mb_mode:
15238           shift = 0;
15239           break;
15240         default:
15241           abort ();
15242         }
15243       /* Make necessary corrections to shift for modes that need it.
15244          For these modes we currently have shift 4, 5 or 6 depending on
15245          vex.length (it corresponds to xmmword, ymmword or zmmword
15246          operand).  We might want to make it 3, 4 or 5 (e.g. for
15247          xmmq_mode).  In case of broadcast enabled the corrections
15248          aren't needed, as element size is always 32 or 64 bits.  */
15249       if (!vex.b
15250           && (bytemode == xmmq_mode
15251               || bytemode == evex_half_bcst_xmmq_mode))
15252         shift -= 1;
15253       else if (bytemode == xmmqd_mode)
15254         shift -= 2;
15255       else if (bytemode == xmmdw_mode)
15256         shift -= 3;
15257       else if (bytemode == ymmq_mode && vex.length == 128)
15258         shift -= 1;
15259     }
15260   else
15261     shift = 0;
15262
15263   USED_REX (REX_B);
15264   if (intel_syntax)
15265     intel_operand_size (bytemode, sizeflag);
15266   append_seg ();
15267
15268   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15269     {
15270       /* 32/64 bit address mode */
15271       int havedisp;
15272       int havesib;
15273       int havebase;
15274       int haveindex;
15275       int needindex;
15276       int base, rbase;
15277       int vindex = 0;
15278       int scale = 0;
15279       int addr32flag = !((sizeflag & AFLAG)
15280                          || bytemode == v_bnd_mode
15281                          || bytemode == bnd_mode
15282                          || bytemode == bnd_swap_mode);
15283       const char **indexes64 = names64;
15284       const char **indexes32 = names32;
15285
15286       havesib = 0;
15287       havebase = 1;
15288       haveindex = 0;
15289       base = modrm.rm;
15290
15291       if (base == 4)
15292         {
15293           havesib = 1;
15294           vindex = sib.index;
15295           USED_REX (REX_X);
15296           if (rex & REX_X)
15297             vindex += 8;
15298           switch (bytemode)
15299             {
15300             case vex_vsib_d_w_dq_mode:
15301             case vex_vsib_d_w_d_mode:
15302             case vex_vsib_q_w_dq_mode:
15303             case vex_vsib_q_w_d_mode:
15304               if (!need_vex)
15305                 abort ();
15306               if (vex.evex)
15307                 {
15308                   if (!vex.v)
15309                     vindex += 16;
15310                 }
15311
15312               haveindex = 1;
15313               switch (vex.length)
15314                 {
15315                 case 128:
15316                   indexes64 = indexes32 = names_xmm;
15317                   break;
15318                 case 256:
15319                   if (!vex.w
15320                       || bytemode == vex_vsib_q_w_dq_mode
15321                       || bytemode == vex_vsib_q_w_d_mode)
15322                     indexes64 = indexes32 = names_ymm;
15323                   else
15324                     indexes64 = indexes32 = names_xmm;
15325                   break;
15326                 case 512:
15327                   if (!vex.w
15328                       || bytemode == vex_vsib_q_w_dq_mode
15329                       || bytemode == vex_vsib_q_w_d_mode)
15330                     indexes64 = indexes32 = names_zmm;
15331                   else
15332                     indexes64 = indexes32 = names_ymm;
15333                   break;
15334                 default:
15335                   abort ();
15336                 }
15337               break;
15338             default:
15339               haveindex = vindex != 4;
15340               break;
15341             }
15342           scale = sib.scale;
15343           base = sib.base;
15344           codep++;
15345         }
15346       rbase = base + add;
15347
15348       switch (modrm.mod)
15349         {
15350         case 0:
15351           if (base == 5)
15352             {
15353               havebase = 0;
15354               if (address_mode == mode_64bit && !havesib)
15355                 riprel = 1;
15356               disp = get32s ();
15357             }
15358           break;
15359         case 1:
15360           FETCH_DATA (the_info, codep + 1);
15361           disp = *codep++;
15362           if ((disp & 0x80) != 0)
15363             disp -= 0x100;
15364           if (vex.evex && shift > 0)
15365             disp <<= shift;
15366           break;
15367         case 2:
15368           disp = get32s ();
15369           break;
15370         }
15371
15372       /* In 32bit mode, we need index register to tell [offset] from
15373          [eiz*1 + offset].  */
15374       needindex = (havesib
15375                    && !havebase
15376                    && !haveindex
15377                    && address_mode == mode_32bit);
15378       havedisp = (havebase
15379                   || needindex
15380                   || (havesib && (haveindex || scale != 0)));
15381
15382       if (!intel_syntax)
15383         if (modrm.mod != 0 || base == 5)
15384           {
15385             if (havedisp || riprel)
15386               print_displacement (scratchbuf, disp);
15387             else
15388               print_operand_value (scratchbuf, 1, disp);
15389             oappend (scratchbuf);
15390             if (riprel)
15391               {
15392                 set_op (disp, 1);
15393                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15394               }
15395           }
15396
15397       if ((havebase || haveindex || riprel)
15398           && (bytemode != v_bnd_mode)
15399           && (bytemode != bnd_mode)
15400           && (bytemode != bnd_swap_mode))
15401         used_prefixes |= PREFIX_ADDR;
15402
15403       if (havedisp || (intel_syntax && riprel))
15404         {
15405           *obufp++ = open_char;
15406           if (intel_syntax && riprel)
15407             {
15408               set_op (disp, 1);
15409               oappend (!addr32flag ? "rip" : "eip");
15410             }
15411           *obufp = '\0';
15412           if (havebase)
15413             oappend (address_mode == mode_64bit && !addr32flag
15414                      ? names64[rbase] : names32[rbase]);
15415           if (havesib)
15416             {
15417               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15418                  print index to tell base + index from base.  */
15419               if (scale != 0
15420                   || needindex
15421                   || haveindex
15422                   || (havebase && base != ESP_REG_NUM))
15423                 {
15424                   if (!intel_syntax || havebase)
15425                     {
15426                       *obufp++ = separator_char;
15427                       *obufp = '\0';
15428                     }
15429                   if (haveindex)
15430                     oappend (address_mode == mode_64bit && !addr32flag
15431                              ? indexes64[vindex] : indexes32[vindex]);
15432                   else
15433                     oappend (address_mode == mode_64bit && !addr32flag
15434                              ? index64 : index32);
15435
15436                   *obufp++ = scale_char;
15437                   *obufp = '\0';
15438                   sprintf (scratchbuf, "%d", 1 << scale);
15439                   oappend (scratchbuf);
15440                 }
15441             }
15442           if (intel_syntax
15443               && (disp || modrm.mod != 0 || base == 5))
15444             {
15445               if (!havedisp || (bfd_signed_vma) disp >= 0)
15446                 {
15447                   *obufp++ = '+';
15448                   *obufp = '\0';
15449                 }
15450               else if (modrm.mod != 1 && disp != -disp)
15451                 {
15452                   *obufp++ = '-';
15453                   *obufp = '\0';
15454                   disp = - (bfd_signed_vma) disp;
15455                 }
15456
15457               if (havedisp)
15458                 print_displacement (scratchbuf, disp);
15459               else
15460                 print_operand_value (scratchbuf, 1, disp);
15461               oappend (scratchbuf);
15462             }
15463
15464           *obufp++ = close_char;
15465           *obufp = '\0';
15466         }
15467       else if (intel_syntax)
15468         {
15469           if (modrm.mod != 0 || base == 5)
15470             {
15471               if (!active_seg_prefix)
15472                 {
15473                   oappend (names_seg[ds_reg - es_reg]);
15474                   oappend (":");
15475                 }
15476               print_operand_value (scratchbuf, 1, disp);
15477               oappend (scratchbuf);
15478             }
15479         }
15480     }
15481   else
15482     {
15483       /* 16 bit address mode */
15484       used_prefixes |= prefixes & PREFIX_ADDR;
15485       switch (modrm.mod)
15486         {
15487         case 0:
15488           if (modrm.rm == 6)
15489             {
15490               disp = get16 ();
15491               if ((disp & 0x8000) != 0)
15492                 disp -= 0x10000;
15493             }
15494           break;
15495         case 1:
15496           FETCH_DATA (the_info, codep + 1);
15497           disp = *codep++;
15498           if ((disp & 0x80) != 0)
15499             disp -= 0x100;
15500           if (vex.evex && shift > 0)
15501             disp <<= shift;
15502           break;
15503         case 2:
15504           disp = get16 ();
15505           if ((disp & 0x8000) != 0)
15506             disp -= 0x10000;
15507           break;
15508         }
15509
15510       if (!intel_syntax)
15511         if (modrm.mod != 0 || modrm.rm == 6)
15512           {
15513             print_displacement (scratchbuf, disp);
15514             oappend (scratchbuf);
15515           }
15516
15517       if (modrm.mod != 0 || modrm.rm != 6)
15518         {
15519           *obufp++ = open_char;
15520           *obufp = '\0';
15521           oappend (index16[modrm.rm]);
15522           if (intel_syntax
15523               && (disp || modrm.mod != 0 || modrm.rm == 6))
15524             {
15525               if ((bfd_signed_vma) disp >= 0)
15526                 {
15527                   *obufp++ = '+';
15528                   *obufp = '\0';
15529                 }
15530               else if (modrm.mod != 1)
15531                 {
15532                   *obufp++ = '-';
15533                   *obufp = '\0';
15534                   disp = - (bfd_signed_vma) disp;
15535                 }
15536
15537               print_displacement (scratchbuf, disp);
15538               oappend (scratchbuf);
15539             }
15540
15541           *obufp++ = close_char;
15542           *obufp = '\0';
15543         }
15544       else if (intel_syntax)
15545         {
15546           if (!active_seg_prefix)
15547             {
15548               oappend (names_seg[ds_reg - es_reg]);
15549               oappend (":");
15550             }
15551           print_operand_value (scratchbuf, 1, disp & 0xffff);
15552           oappend (scratchbuf);
15553         }
15554     }
15555   if (vex.evex && vex.b
15556       && (bytemode == x_mode
15557           || bytemode == xmmq_mode
15558           || bytemode == evex_half_bcst_xmmq_mode))
15559     {
15560       if (vex.w
15561           || bytemode == xmmq_mode
15562           || bytemode == evex_half_bcst_xmmq_mode)
15563         {
15564           switch (vex.length)
15565             {
15566             case 128:
15567               oappend ("{1to2}");
15568               break;
15569             case 256:
15570               oappend ("{1to4}");
15571               break;
15572             case 512:
15573               oappend ("{1to8}");
15574               break;
15575             default:
15576               abort ();
15577             }
15578         }
15579       else
15580         {
15581           switch (vex.length)
15582             {
15583             case 128:
15584               oappend ("{1to4}");
15585               break;
15586             case 256:
15587               oappend ("{1to8}");
15588               break;
15589             case 512:
15590               oappend ("{1to16}");
15591               break;
15592             default:
15593               abort ();
15594             }
15595         }
15596     }
15597 }
15598
15599 static void
15600 OP_E (int bytemode, int sizeflag)
15601 {
15602   /* Skip mod/rm byte.  */
15603   MODRM_CHECK;
15604   codep++;
15605
15606   if (modrm.mod == 3)
15607     OP_E_register (bytemode, sizeflag);
15608   else
15609     OP_E_memory (bytemode, sizeflag);
15610 }
15611
15612 static void
15613 OP_G (int bytemode, int sizeflag)
15614 {
15615   int add = 0;
15616   USED_REX (REX_R);
15617   if (rex & REX_R)
15618     add += 8;
15619   switch (bytemode)
15620     {
15621     case b_mode:
15622       USED_REX (0);
15623       if (rex)
15624         oappend (names8rex[modrm.reg + add]);
15625       else
15626         oappend (names8[modrm.reg + add]);
15627       break;
15628     case w_mode:
15629       oappend (names16[modrm.reg + add]);
15630       break;
15631     case d_mode:
15632     case db_mode:
15633     case dw_mode:
15634       oappend (names32[modrm.reg + add]);
15635       break;
15636     case q_mode:
15637       oappend (names64[modrm.reg + add]);
15638       break;
15639     case bnd_mode:
15640       if (modrm.reg > 0x3)
15641         {
15642           oappend ("(bad)");
15643           return;
15644         }
15645       oappend (names_bnd[modrm.reg]);
15646       break;
15647     case v_mode:
15648     case dq_mode:
15649     case dqb_mode:
15650     case dqd_mode:
15651     case dqw_mode:
15652       USED_REX (REX_W);
15653       if (rex & REX_W)
15654         oappend (names64[modrm.reg + add]);
15655       else
15656         {
15657           if ((sizeflag & DFLAG) || bytemode != v_mode)
15658             oappend (names32[modrm.reg + add]);
15659           else
15660             oappend (names16[modrm.reg + add]);
15661           used_prefixes |= (prefixes & PREFIX_DATA);
15662         }
15663       break;
15664     case m_mode:
15665       if (address_mode == mode_64bit)
15666         oappend (names64[modrm.reg + add]);
15667       else
15668         oappend (names32[modrm.reg + add]);
15669       break;
15670     case mask_bd_mode:
15671     case mask_mode:
15672       if ((modrm.reg + add) > 0x7)
15673         {
15674           oappend ("(bad)");
15675           return;
15676         }
15677       oappend (names_mask[modrm.reg + add]);
15678       break;
15679     default:
15680       oappend (INTERNAL_DISASSEMBLER_ERROR);
15681       break;
15682     }
15683 }
15684
15685 static bfd_vma
15686 get64 (void)
15687 {
15688   bfd_vma x;
15689 #ifdef BFD64
15690   unsigned int a;
15691   unsigned int b;
15692
15693   FETCH_DATA (the_info, codep + 8);
15694   a = *codep++ & 0xff;
15695   a |= (*codep++ & 0xff) << 8;
15696   a |= (*codep++ & 0xff) << 16;
15697   a |= (*codep++ & 0xffu) << 24;
15698   b = *codep++ & 0xff;
15699   b |= (*codep++ & 0xff) << 8;
15700   b |= (*codep++ & 0xff) << 16;
15701   b |= (*codep++ & 0xffu) << 24;
15702   x = a + ((bfd_vma) b << 32);
15703 #else
15704   abort ();
15705   x = 0;
15706 #endif
15707   return x;
15708 }
15709
15710 static bfd_signed_vma
15711 get32 (void)
15712 {
15713   bfd_signed_vma x = 0;
15714
15715   FETCH_DATA (the_info, codep + 4);
15716   x = *codep++ & (bfd_signed_vma) 0xff;
15717   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15718   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15719   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15720   return x;
15721 }
15722
15723 static bfd_signed_vma
15724 get32s (void)
15725 {
15726   bfd_signed_vma x = 0;
15727
15728   FETCH_DATA (the_info, codep + 4);
15729   x = *codep++ & (bfd_signed_vma) 0xff;
15730   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15731   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15732   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15733
15734   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15735
15736   return x;
15737 }
15738
15739 static int
15740 get16 (void)
15741 {
15742   int x = 0;
15743
15744   FETCH_DATA (the_info, codep + 2);
15745   x = *codep++ & 0xff;
15746   x |= (*codep++ & 0xff) << 8;
15747   return x;
15748 }
15749
15750 static void
15751 set_op (bfd_vma op, int riprel)
15752 {
15753   op_index[op_ad] = op_ad;
15754   if (address_mode == mode_64bit)
15755     {
15756       op_address[op_ad] = op;
15757       op_riprel[op_ad] = riprel;
15758     }
15759   else
15760     {
15761       /* Mask to get a 32-bit address.  */
15762       op_address[op_ad] = op & 0xffffffff;
15763       op_riprel[op_ad] = riprel & 0xffffffff;
15764     }
15765 }
15766
15767 static void
15768 OP_REG (int code, int sizeflag)
15769 {
15770   const char *s;
15771   int add;
15772
15773   switch (code)
15774     {
15775     case es_reg: case ss_reg: case cs_reg:
15776     case ds_reg: case fs_reg: case gs_reg:
15777       oappend (names_seg[code - es_reg]);
15778       return;
15779     }
15780
15781   USED_REX (REX_B);
15782   if (rex & REX_B)
15783     add = 8;
15784   else
15785     add = 0;
15786
15787   switch (code)
15788     {
15789     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15790     case sp_reg: case bp_reg: case si_reg: case di_reg:
15791       s = names16[code - ax_reg + add];
15792       break;
15793     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15794     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15795       USED_REX (0);
15796       if (rex)
15797         s = names8rex[code - al_reg + add];
15798       else
15799         s = names8[code - al_reg];
15800       break;
15801     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15802     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15803       if (address_mode == mode_64bit
15804           && ((sizeflag & DFLAG) || (rex & REX_W)))
15805         {
15806           s = names64[code - rAX_reg + add];
15807           break;
15808         }
15809       code += eAX_reg - rAX_reg;
15810       /* Fall through.  */
15811     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15812     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15813       USED_REX (REX_W);
15814       if (rex & REX_W)
15815         s = names64[code - eAX_reg + add];
15816       else
15817         {
15818           if (sizeflag & DFLAG)
15819             s = names32[code - eAX_reg + add];
15820           else
15821             s = names16[code - eAX_reg + add];
15822           used_prefixes |= (prefixes & PREFIX_DATA);
15823         }
15824       break;
15825     default:
15826       s = INTERNAL_DISASSEMBLER_ERROR;
15827       break;
15828     }
15829   oappend (s);
15830 }
15831
15832 static void
15833 OP_IMREG (int code, int sizeflag)
15834 {
15835   const char *s;
15836
15837   switch (code)
15838     {
15839     case indir_dx_reg:
15840       if (intel_syntax)
15841         s = "dx";
15842       else
15843         s = "(%dx)";
15844       break;
15845     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15846     case sp_reg: case bp_reg: case si_reg: case di_reg:
15847       s = names16[code - ax_reg];
15848       break;
15849     case es_reg: case ss_reg: case cs_reg:
15850     case ds_reg: case fs_reg: case gs_reg:
15851       s = names_seg[code - es_reg];
15852       break;
15853     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15854     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15855       USED_REX (0);
15856       if (rex)
15857         s = names8rex[code - al_reg];
15858       else
15859         s = names8[code - al_reg];
15860       break;
15861     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15862     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15863       USED_REX (REX_W);
15864       if (rex & REX_W)
15865         s = names64[code - eAX_reg];
15866       else
15867         {
15868           if (sizeflag & DFLAG)
15869             s = names32[code - eAX_reg];
15870           else
15871             s = names16[code - eAX_reg];
15872           used_prefixes |= (prefixes & PREFIX_DATA);
15873         }
15874       break;
15875     case z_mode_ax_reg:
15876       if ((rex & REX_W) || (sizeflag & DFLAG))
15877         s = *names32;
15878       else
15879         s = *names16;
15880       if (!(rex & REX_W))
15881         used_prefixes |= (prefixes & PREFIX_DATA);
15882       break;
15883     default:
15884       s = INTERNAL_DISASSEMBLER_ERROR;
15885       break;
15886     }
15887   oappend (s);
15888 }
15889
15890 static void
15891 OP_I (int bytemode, int sizeflag)
15892 {
15893   bfd_signed_vma op;
15894   bfd_signed_vma mask = -1;
15895
15896   switch (bytemode)
15897     {
15898     case b_mode:
15899       FETCH_DATA (the_info, codep + 1);
15900       op = *codep++;
15901       mask = 0xff;
15902       break;
15903     case q_mode:
15904       if (address_mode == mode_64bit)
15905         {
15906           op = get32s ();
15907           break;
15908         }
15909       /* Fall through.  */
15910     case v_mode:
15911       USED_REX (REX_W);
15912       if (rex & REX_W)
15913         op = get32s ();
15914       else
15915         {
15916           if (sizeflag & DFLAG)
15917             {
15918               op = get32 ();
15919               mask = 0xffffffff;
15920             }
15921           else
15922             {
15923               op = get16 ();
15924               mask = 0xfffff;
15925             }
15926           used_prefixes |= (prefixes & PREFIX_DATA);
15927         }
15928       break;
15929     case w_mode:
15930       mask = 0xfffff;
15931       op = get16 ();
15932       break;
15933     case const_1_mode:
15934       if (intel_syntax)
15935         oappend ("1");
15936       return;
15937     default:
15938       oappend (INTERNAL_DISASSEMBLER_ERROR);
15939       return;
15940     }
15941
15942   op &= mask;
15943   scratchbuf[0] = '$';
15944   print_operand_value (scratchbuf + 1, 1, op);
15945   oappend_maybe_intel (scratchbuf);
15946   scratchbuf[0] = '\0';
15947 }
15948
15949 static void
15950 OP_I64 (int bytemode, int sizeflag)
15951 {
15952   bfd_signed_vma op;
15953   bfd_signed_vma mask = -1;
15954
15955   if (address_mode != mode_64bit)
15956     {
15957       OP_I (bytemode, sizeflag);
15958       return;
15959     }
15960
15961   switch (bytemode)
15962     {
15963     case b_mode:
15964       FETCH_DATA (the_info, codep + 1);
15965       op = *codep++;
15966       mask = 0xff;
15967       break;
15968     case v_mode:
15969       USED_REX (REX_W);
15970       if (rex & REX_W)
15971         op = get64 ();
15972       else
15973         {
15974           if (sizeflag & DFLAG)
15975             {
15976               op = get32 ();
15977               mask = 0xffffffff;
15978             }
15979           else
15980             {
15981               op = get16 ();
15982               mask = 0xfffff;
15983             }
15984           used_prefixes |= (prefixes & PREFIX_DATA);
15985         }
15986       break;
15987     case w_mode:
15988       mask = 0xfffff;
15989       op = get16 ();
15990       break;
15991     default:
15992       oappend (INTERNAL_DISASSEMBLER_ERROR);
15993       return;
15994     }
15995
15996   op &= mask;
15997   scratchbuf[0] = '$';
15998   print_operand_value (scratchbuf + 1, 1, op);
15999   oappend_maybe_intel (scratchbuf);
16000   scratchbuf[0] = '\0';
16001 }
16002
16003 static void
16004 OP_sI (int bytemode, int sizeflag)
16005 {
16006   bfd_signed_vma op;
16007
16008   switch (bytemode)
16009     {
16010     case b_mode:
16011     case b_T_mode:
16012       FETCH_DATA (the_info, codep + 1);
16013       op = *codep++;
16014       if ((op & 0x80) != 0)
16015         op -= 0x100;
16016       if (bytemode == b_T_mode)
16017         {
16018           if (address_mode != mode_64bit
16019               || !((sizeflag & DFLAG) || (rex & REX_W)))
16020             {
16021               /* The operand-size prefix is overridden by a REX prefix.  */
16022               if ((sizeflag & DFLAG) || (rex & REX_W))
16023                 op &= 0xffffffff;
16024               else
16025                 op &= 0xffff;
16026           }
16027         }
16028       else
16029         {
16030           if (!(rex & REX_W))
16031             {
16032               if (sizeflag & DFLAG)
16033                 op &= 0xffffffff;
16034               else
16035                 op &= 0xffff;
16036             }
16037         }
16038       break;
16039     case v_mode:
16040       /* The operand-size prefix is overridden by a REX prefix.  */
16041       if ((sizeflag & DFLAG) || (rex & REX_W))
16042         op = get32s ();
16043       else
16044         op = get16 ();
16045       break;
16046     default:
16047       oappend (INTERNAL_DISASSEMBLER_ERROR);
16048       return;
16049     }
16050
16051   scratchbuf[0] = '$';
16052   print_operand_value (scratchbuf + 1, 1, op);
16053   oappend_maybe_intel (scratchbuf);
16054 }
16055
16056 static void
16057 OP_J (int bytemode, int sizeflag)
16058 {
16059   bfd_vma disp;
16060   bfd_vma mask = -1;
16061   bfd_vma segment = 0;
16062
16063   switch (bytemode)
16064     {
16065     case b_mode:
16066       FETCH_DATA (the_info, codep + 1);
16067       disp = *codep++;
16068       if ((disp & 0x80) != 0)
16069         disp -= 0x100;
16070       break;
16071     case v_mode:
16072       if (isa64 == amd64)
16073         USED_REX (REX_W);
16074       if ((sizeflag & DFLAG)
16075           || (address_mode == mode_64bit
16076               && (isa64 != amd64 || (rex & REX_W))))
16077         disp = get32s ();
16078       else
16079         {
16080           disp = get16 ();
16081           if ((disp & 0x8000) != 0)
16082             disp -= 0x10000;
16083           /* In 16bit mode, address is wrapped around at 64k within
16084              the same segment.  Otherwise, a data16 prefix on a jump
16085              instruction means that the pc is masked to 16 bits after
16086              the displacement is added!  */
16087           mask = 0xffff;
16088           if ((prefixes & PREFIX_DATA) == 0)
16089             segment = ((start_pc + (codep - start_codep))
16090                        & ~((bfd_vma) 0xffff));
16091         }
16092       if (address_mode != mode_64bit
16093           || (isa64 == amd64 && !(rex & REX_W)))
16094         used_prefixes |= (prefixes & PREFIX_DATA);
16095       break;
16096     default:
16097       oappend (INTERNAL_DISASSEMBLER_ERROR);
16098       return;
16099     }
16100   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16101   set_op (disp, 0);
16102   print_operand_value (scratchbuf, 1, disp);
16103   oappend (scratchbuf);
16104 }
16105
16106 static void
16107 OP_SEG (int bytemode, int sizeflag)
16108 {
16109   if (bytemode == w_mode)
16110     oappend (names_seg[modrm.reg]);
16111   else
16112     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16113 }
16114
16115 static void
16116 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16117 {
16118   int seg, offset;
16119
16120   if (sizeflag & DFLAG)
16121     {
16122       offset = get32 ();
16123       seg = get16 ();
16124     }
16125   else
16126     {
16127       offset = get16 ();
16128       seg = get16 ();
16129     }
16130   used_prefixes |= (prefixes & PREFIX_DATA);
16131   if (intel_syntax)
16132     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16133   else
16134     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16135   oappend (scratchbuf);
16136 }
16137
16138 static void
16139 OP_OFF (int bytemode, int sizeflag)
16140 {
16141   bfd_vma off;
16142
16143   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16144     intel_operand_size (bytemode, sizeflag);
16145   append_seg ();
16146
16147   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16148     off = get32 ();
16149   else
16150     off = get16 ();
16151
16152   if (intel_syntax)
16153     {
16154       if (!active_seg_prefix)
16155         {
16156           oappend (names_seg[ds_reg - es_reg]);
16157           oappend (":");
16158         }
16159     }
16160   print_operand_value (scratchbuf, 1, off);
16161   oappend (scratchbuf);
16162 }
16163
16164 static void
16165 OP_OFF64 (int bytemode, int sizeflag)
16166 {
16167   bfd_vma off;
16168
16169   if (address_mode != mode_64bit
16170       || (prefixes & PREFIX_ADDR))
16171     {
16172       OP_OFF (bytemode, sizeflag);
16173       return;
16174     }
16175
16176   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16177     intel_operand_size (bytemode, sizeflag);
16178   append_seg ();
16179
16180   off = get64 ();
16181
16182   if (intel_syntax)
16183     {
16184       if (!active_seg_prefix)
16185         {
16186           oappend (names_seg[ds_reg - es_reg]);
16187           oappend (":");
16188         }
16189     }
16190   print_operand_value (scratchbuf, 1, off);
16191   oappend (scratchbuf);
16192 }
16193
16194 static void
16195 ptr_reg (int code, int sizeflag)
16196 {
16197   const char *s;
16198
16199   *obufp++ = open_char;
16200   used_prefixes |= (prefixes & PREFIX_ADDR);
16201   if (address_mode == mode_64bit)
16202     {
16203       if (!(sizeflag & AFLAG))
16204         s = names32[code - eAX_reg];
16205       else
16206         s = names64[code - eAX_reg];
16207     }
16208   else if (sizeflag & AFLAG)
16209     s = names32[code - eAX_reg];
16210   else
16211     s = names16[code - eAX_reg];
16212   oappend (s);
16213   *obufp++ = close_char;
16214   *obufp = 0;
16215 }
16216
16217 static void
16218 OP_ESreg (int code, int sizeflag)
16219 {
16220   if (intel_syntax)
16221     {
16222       switch (codep[-1])
16223         {
16224         case 0x6d:      /* insw/insl */
16225           intel_operand_size (z_mode, sizeflag);
16226           break;
16227         case 0xa5:      /* movsw/movsl/movsq */
16228         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16229         case 0xab:      /* stosw/stosl */
16230         case 0xaf:      /* scasw/scasl */
16231           intel_operand_size (v_mode, sizeflag);
16232           break;
16233         default:
16234           intel_operand_size (b_mode, sizeflag);
16235         }
16236     }
16237   oappend_maybe_intel ("%es:");
16238   ptr_reg (code, sizeflag);
16239 }
16240
16241 static void
16242 OP_DSreg (int code, int sizeflag)
16243 {
16244   if (intel_syntax)
16245     {
16246       switch (codep[-1])
16247         {
16248         case 0x6f:      /* outsw/outsl */
16249           intel_operand_size (z_mode, sizeflag);
16250           break;
16251         case 0xa5:      /* movsw/movsl/movsq */
16252         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16253         case 0xad:      /* lodsw/lodsl/lodsq */
16254           intel_operand_size (v_mode, sizeflag);
16255           break;
16256         default:
16257           intel_operand_size (b_mode, sizeflag);
16258         }
16259     }
16260   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16261      default segment register DS is printed.  */
16262   if (!active_seg_prefix)
16263     active_seg_prefix = PREFIX_DS;
16264   append_seg ();
16265   ptr_reg (code, sizeflag);
16266 }
16267
16268 static void
16269 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16270 {
16271   int add;
16272   if (rex & REX_R)
16273     {
16274       USED_REX (REX_R);
16275       add = 8;
16276     }
16277   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16278     {
16279       all_prefixes[last_lock_prefix] = 0;
16280       used_prefixes |= PREFIX_LOCK;
16281       add = 8;
16282     }
16283   else
16284     add = 0;
16285   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16286   oappend_maybe_intel (scratchbuf);
16287 }
16288
16289 static void
16290 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16291 {
16292   int add;
16293   USED_REX (REX_R);
16294   if (rex & REX_R)
16295     add = 8;
16296   else
16297     add = 0;
16298   if (intel_syntax)
16299     sprintf (scratchbuf, "db%d", modrm.reg + add);
16300   else
16301     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16302   oappend (scratchbuf);
16303 }
16304
16305 static void
16306 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16307 {
16308   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16309   oappend_maybe_intel (scratchbuf);
16310 }
16311
16312 static void
16313 OP_R (int bytemode, int sizeflag)
16314 {
16315   /* Skip mod/rm byte.  */
16316   MODRM_CHECK;
16317   codep++;
16318   OP_E_register (bytemode, sizeflag);
16319 }
16320
16321 static void
16322 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16323 {
16324   int reg = modrm.reg;
16325   const char **names;
16326
16327   used_prefixes |= (prefixes & PREFIX_DATA);
16328   if (prefixes & PREFIX_DATA)
16329     {
16330       names = names_xmm;
16331       USED_REX (REX_R);
16332       if (rex & REX_R)
16333         reg += 8;
16334     }
16335   else
16336     names = names_mm;
16337   oappend (names[reg]);
16338 }
16339
16340 static void
16341 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16342 {
16343   int reg = modrm.reg;
16344   const char **names;
16345
16346   USED_REX (REX_R);
16347   if (rex & REX_R)
16348     reg += 8;
16349   if (vex.evex)
16350     {
16351       if (!vex.r)
16352         reg += 16;
16353     }
16354
16355   if (need_vex
16356       && bytemode != xmm_mode
16357       && bytemode != xmmq_mode
16358       && bytemode != evex_half_bcst_xmmq_mode
16359       && bytemode != ymm_mode
16360       && bytemode != scalar_mode)
16361     {
16362       switch (vex.length)
16363         {
16364         case 128:
16365           names = names_xmm;
16366           break;
16367         case 256:
16368           if (vex.w
16369               || (bytemode != vex_vsib_q_w_dq_mode
16370                   && bytemode != vex_vsib_q_w_d_mode))
16371             names = names_ymm;
16372           else
16373             names = names_xmm;
16374           break;
16375         case 512:
16376           names = names_zmm;
16377           break;
16378         default:
16379           abort ();
16380         }
16381     }
16382   else if (bytemode == xmmq_mode
16383            || bytemode == evex_half_bcst_xmmq_mode)
16384     {
16385       switch (vex.length)
16386         {
16387         case 128:
16388         case 256:
16389           names = names_xmm;
16390           break;
16391         case 512:
16392           names = names_ymm;
16393           break;
16394         default:
16395           abort ();
16396         }
16397     }
16398   else if (bytemode == ymm_mode)
16399     names = names_ymm;
16400   else
16401     names = names_xmm;
16402   oappend (names[reg]);
16403 }
16404
16405 static void
16406 OP_EM (int bytemode, int sizeflag)
16407 {
16408   int reg;
16409   const char **names;
16410
16411   if (modrm.mod != 3)
16412     {
16413       if (intel_syntax
16414           && (bytemode == v_mode || bytemode == v_swap_mode))
16415         {
16416           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16417           used_prefixes |= (prefixes & PREFIX_DATA);
16418         }
16419       OP_E (bytemode, sizeflag);
16420       return;
16421     }
16422
16423   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16424     swap_operand ();
16425
16426   /* Skip mod/rm byte.  */
16427   MODRM_CHECK;
16428   codep++;
16429   used_prefixes |= (prefixes & PREFIX_DATA);
16430   reg = modrm.rm;
16431   if (prefixes & PREFIX_DATA)
16432     {
16433       names = names_xmm;
16434       USED_REX (REX_B);
16435       if (rex & REX_B)
16436         reg += 8;
16437     }
16438   else
16439     names = names_mm;
16440   oappend (names[reg]);
16441 }
16442
16443 /* cvt* are the only instructions in sse2 which have
16444    both SSE and MMX operands and also have 0x66 prefix
16445    in their opcode. 0x66 was originally used to differentiate
16446    between SSE and MMX instruction(operands). So we have to handle the
16447    cvt* separately using OP_EMC and OP_MXC */
16448 static void
16449 OP_EMC (int bytemode, int sizeflag)
16450 {
16451   if (modrm.mod != 3)
16452     {
16453       if (intel_syntax && bytemode == v_mode)
16454         {
16455           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16456           used_prefixes |= (prefixes & PREFIX_DATA);
16457         }
16458       OP_E (bytemode, sizeflag);
16459       return;
16460     }
16461
16462   /* Skip mod/rm byte.  */
16463   MODRM_CHECK;
16464   codep++;
16465   used_prefixes |= (prefixes & PREFIX_DATA);
16466   oappend (names_mm[modrm.rm]);
16467 }
16468
16469 static void
16470 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16471 {
16472   used_prefixes |= (prefixes & PREFIX_DATA);
16473   oappend (names_mm[modrm.reg]);
16474 }
16475
16476 static void
16477 OP_EX (int bytemode, int sizeflag)
16478 {
16479   int reg;
16480   const char **names;
16481
16482   /* Skip mod/rm byte.  */
16483   MODRM_CHECK;
16484   codep++;
16485
16486   if (modrm.mod != 3)
16487     {
16488       OP_E_memory (bytemode, sizeflag);
16489       return;
16490     }
16491
16492   reg = modrm.rm;
16493   USED_REX (REX_B);
16494   if (rex & REX_B)
16495     reg += 8;
16496   if (vex.evex)
16497     {
16498       USED_REX (REX_X);
16499       if ((rex & REX_X))
16500         reg += 16;
16501     }
16502
16503   if ((sizeflag & SUFFIX_ALWAYS)
16504       && (bytemode == x_swap_mode
16505           || bytemode == d_swap_mode
16506           || bytemode == d_scalar_swap_mode
16507           || bytemode == q_swap_mode
16508           || bytemode == q_scalar_swap_mode))
16509     swap_operand ();
16510
16511   if (need_vex
16512       && bytemode != xmm_mode
16513       && bytemode != xmmdw_mode
16514       && bytemode != xmmqd_mode
16515       && bytemode != xmm_mb_mode
16516       && bytemode != xmm_mw_mode
16517       && bytemode != xmm_md_mode
16518       && bytemode != xmm_mq_mode
16519       && bytemode != xmm_mdq_mode
16520       && bytemode != xmmq_mode
16521       && bytemode != evex_half_bcst_xmmq_mode
16522       && bytemode != ymm_mode
16523       && bytemode != d_scalar_mode
16524       && bytemode != d_scalar_swap_mode
16525       && bytemode != q_scalar_mode
16526       && bytemode != q_scalar_swap_mode
16527       && bytemode != vex_scalar_w_dq_mode)
16528     {
16529       switch (vex.length)
16530         {
16531         case 128:
16532           names = names_xmm;
16533           break;
16534         case 256:
16535           names = names_ymm;
16536           break;
16537         case 512:
16538           names = names_zmm;
16539           break;
16540         default:
16541           abort ();
16542         }
16543     }
16544   else if (bytemode == xmmq_mode
16545            || bytemode == evex_half_bcst_xmmq_mode)
16546     {
16547       switch (vex.length)
16548         {
16549         case 128:
16550         case 256:
16551           names = names_xmm;
16552           break;
16553         case 512:
16554           names = names_ymm;
16555           break;
16556         default:
16557           abort ();
16558         }
16559     }
16560   else if (bytemode == ymm_mode)
16561     names = names_ymm;
16562   else
16563     names = names_xmm;
16564   oappend (names[reg]);
16565 }
16566
16567 static void
16568 OP_MS (int bytemode, int sizeflag)
16569 {
16570   if (modrm.mod == 3)
16571     OP_EM (bytemode, sizeflag);
16572   else
16573     BadOp ();
16574 }
16575
16576 static void
16577 OP_XS (int bytemode, int sizeflag)
16578 {
16579   if (modrm.mod == 3)
16580     OP_EX (bytemode, sizeflag);
16581   else
16582     BadOp ();
16583 }
16584
16585 static void
16586 OP_M (int bytemode, int sizeflag)
16587 {
16588   if (modrm.mod == 3)
16589     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16590     BadOp ();
16591   else
16592     OP_E (bytemode, sizeflag);
16593 }
16594
16595 static void
16596 OP_0f07 (int bytemode, int sizeflag)
16597 {
16598   if (modrm.mod != 3 || modrm.rm != 0)
16599     BadOp ();
16600   else
16601     OP_E (bytemode, sizeflag);
16602 }
16603
16604 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16605    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16606
16607 static void
16608 NOP_Fixup1 (int bytemode, int sizeflag)
16609 {
16610   if ((prefixes & PREFIX_DATA) != 0
16611       || (rex != 0
16612           && rex != 0x48
16613           && address_mode == mode_64bit))
16614     OP_REG (bytemode, sizeflag);
16615   else
16616     strcpy (obuf, "nop");
16617 }
16618
16619 static void
16620 NOP_Fixup2 (int bytemode, int sizeflag)
16621 {
16622   if ((prefixes & PREFIX_DATA) != 0
16623       || (rex != 0
16624           && rex != 0x48
16625           && address_mode == mode_64bit))
16626     OP_IMREG (bytemode, sizeflag);
16627 }
16628
16629 static const char *const Suffix3DNow[] = {
16630 /* 00 */        NULL,           NULL,           NULL,           NULL,
16631 /* 04 */        NULL,           NULL,           NULL,           NULL,
16632 /* 08 */        NULL,           NULL,           NULL,           NULL,
16633 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16634 /* 10 */        NULL,           NULL,           NULL,           NULL,
16635 /* 14 */        NULL,           NULL,           NULL,           NULL,
16636 /* 18 */        NULL,           NULL,           NULL,           NULL,
16637 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16638 /* 20 */        NULL,           NULL,           NULL,           NULL,
16639 /* 24 */        NULL,           NULL,           NULL,           NULL,
16640 /* 28 */        NULL,           NULL,           NULL,           NULL,
16641 /* 2C */        NULL,           NULL,           NULL,           NULL,
16642 /* 30 */        NULL,           NULL,           NULL,           NULL,
16643 /* 34 */        NULL,           NULL,           NULL,           NULL,
16644 /* 38 */        NULL,           NULL,           NULL,           NULL,
16645 /* 3C */        NULL,           NULL,           NULL,           NULL,
16646 /* 40 */        NULL,           NULL,           NULL,           NULL,
16647 /* 44 */        NULL,           NULL,           NULL,           NULL,
16648 /* 48 */        NULL,           NULL,           NULL,           NULL,
16649 /* 4C */        NULL,           NULL,           NULL,           NULL,
16650 /* 50 */        NULL,           NULL,           NULL,           NULL,
16651 /* 54 */        NULL,           NULL,           NULL,           NULL,
16652 /* 58 */        NULL,           NULL,           NULL,           NULL,
16653 /* 5C */        NULL,           NULL,           NULL,           NULL,
16654 /* 60 */        NULL,           NULL,           NULL,           NULL,
16655 /* 64 */        NULL,           NULL,           NULL,           NULL,
16656 /* 68 */        NULL,           NULL,           NULL,           NULL,
16657 /* 6C */        NULL,           NULL,           NULL,           NULL,
16658 /* 70 */        NULL,           NULL,           NULL,           NULL,
16659 /* 74 */        NULL,           NULL,           NULL,           NULL,
16660 /* 78 */        NULL,           NULL,           NULL,           NULL,
16661 /* 7C */        NULL,           NULL,           NULL,           NULL,
16662 /* 80 */        NULL,           NULL,           NULL,           NULL,
16663 /* 84 */        NULL,           NULL,           NULL,           NULL,
16664 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16665 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16666 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16667 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16668 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16669 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16670 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16671 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16672 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16673 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16674 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16675 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16676 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16677 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16678 /* C0 */        NULL,           NULL,           NULL,           NULL,
16679 /* C4 */        NULL,           NULL,           NULL,           NULL,
16680 /* C8 */        NULL,           NULL,           NULL,           NULL,
16681 /* CC */        NULL,           NULL,           NULL,           NULL,
16682 /* D0 */        NULL,           NULL,           NULL,           NULL,
16683 /* D4 */        NULL,           NULL,           NULL,           NULL,
16684 /* D8 */        NULL,           NULL,           NULL,           NULL,
16685 /* DC */        NULL,           NULL,           NULL,           NULL,
16686 /* E0 */        NULL,           NULL,           NULL,           NULL,
16687 /* E4 */        NULL,           NULL,           NULL,           NULL,
16688 /* E8 */        NULL,           NULL,           NULL,           NULL,
16689 /* EC */        NULL,           NULL,           NULL,           NULL,
16690 /* F0 */        NULL,           NULL,           NULL,           NULL,
16691 /* F4 */        NULL,           NULL,           NULL,           NULL,
16692 /* F8 */        NULL,           NULL,           NULL,           NULL,
16693 /* FC */        NULL,           NULL,           NULL,           NULL,
16694 };
16695
16696 static void
16697 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16698 {
16699   const char *mnemonic;
16700
16701   FETCH_DATA (the_info, codep + 1);
16702   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16703      place where an 8-bit immediate would normally go.  ie. the last
16704      byte of the instruction.  */
16705   obufp = mnemonicendp;
16706   mnemonic = Suffix3DNow[*codep++ & 0xff];
16707   if (mnemonic)
16708     oappend (mnemonic);
16709   else
16710     {
16711       /* Since a variable sized modrm/sib chunk is between the start
16712          of the opcode (0x0f0f) and the opcode suffix, we need to do
16713          all the modrm processing first, and don't know until now that
16714          we have a bad opcode.  This necessitates some cleaning up.  */
16715       op_out[0][0] = '\0';
16716       op_out[1][0] = '\0';
16717       BadOp ();
16718     }
16719   mnemonicendp = obufp;
16720 }
16721
16722 static struct op simd_cmp_op[] =
16723 {
16724   { STRING_COMMA_LEN ("eq") },
16725   { STRING_COMMA_LEN ("lt") },
16726   { STRING_COMMA_LEN ("le") },
16727   { STRING_COMMA_LEN ("unord") },
16728   { STRING_COMMA_LEN ("neq") },
16729   { STRING_COMMA_LEN ("nlt") },
16730   { STRING_COMMA_LEN ("nle") },
16731   { STRING_COMMA_LEN ("ord") }
16732 };
16733
16734 static void
16735 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16736 {
16737   unsigned int cmp_type;
16738
16739   FETCH_DATA (the_info, codep + 1);
16740   cmp_type = *codep++ & 0xff;
16741   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16742     {
16743       char suffix [3];
16744       char *p = mnemonicendp - 2;
16745       suffix[0] = p[0];
16746       suffix[1] = p[1];
16747       suffix[2] = '\0';
16748       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16749       mnemonicendp += simd_cmp_op[cmp_type].len;
16750     }
16751   else
16752     {
16753       /* We have a reserved extension byte.  Output it directly.  */
16754       scratchbuf[0] = '$';
16755       print_operand_value (scratchbuf + 1, 1, cmp_type);
16756       oappend_maybe_intel (scratchbuf);
16757       scratchbuf[0] = '\0';
16758     }
16759 }
16760
16761 static void
16762 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16763           int sizeflag ATTRIBUTE_UNUSED)
16764 {
16765   /* mwaitx %eax,%ecx,%ebx */
16766   if (!intel_syntax)
16767     {
16768       const char **names = (address_mode == mode_64bit
16769                             ? names64 : names32);
16770       strcpy (op_out[0], names[0]);
16771       strcpy (op_out[1], names[1]);
16772       strcpy (op_out[2], names[3]);
16773       two_source_ops = 1;
16774     }
16775   /* Skip mod/rm byte.  */
16776   MODRM_CHECK;
16777   codep++;
16778 }
16779
16780 static void
16781 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16782           int sizeflag ATTRIBUTE_UNUSED)
16783 {
16784   /* mwait %eax,%ecx  */
16785   if (!intel_syntax)
16786     {
16787       const char **names = (address_mode == mode_64bit
16788                             ? names64 : names32);
16789       strcpy (op_out[0], names[0]);
16790       strcpy (op_out[1], names[1]);
16791       two_source_ops = 1;
16792     }
16793   /* Skip mod/rm byte.  */
16794   MODRM_CHECK;
16795   codep++;
16796 }
16797
16798 static void
16799 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16800             int sizeflag ATTRIBUTE_UNUSED)
16801 {
16802   /* monitor %eax,%ecx,%edx"  */
16803   if (!intel_syntax)
16804     {
16805       const char **op1_names;
16806       const char **names = (address_mode == mode_64bit
16807                             ? names64 : names32);
16808
16809       if (!(prefixes & PREFIX_ADDR))
16810         op1_names = (address_mode == mode_16bit
16811                      ? names16 : names);
16812       else
16813         {
16814           /* Remove "addr16/addr32".  */
16815           all_prefixes[last_addr_prefix] = 0;
16816           op1_names = (address_mode != mode_32bit
16817                        ? names32 : names16);
16818           used_prefixes |= PREFIX_ADDR;
16819         }
16820       strcpy (op_out[0], op1_names[0]);
16821       strcpy (op_out[1], names[1]);
16822       strcpy (op_out[2], names[2]);
16823       two_source_ops = 1;
16824     }
16825   /* Skip mod/rm byte.  */
16826   MODRM_CHECK;
16827   codep++;
16828 }
16829
16830 static void
16831 BadOp (void)
16832 {
16833   /* Throw away prefixes and 1st. opcode byte.  */
16834   codep = insn_codep + 1;
16835   oappend ("(bad)");
16836 }
16837
16838 static void
16839 REP_Fixup (int bytemode, int sizeflag)
16840 {
16841   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16842      lods and stos.  */
16843   if (prefixes & PREFIX_REPZ)
16844     all_prefixes[last_repz_prefix] = REP_PREFIX;
16845
16846   switch (bytemode)
16847     {
16848     case al_reg:
16849     case eAX_reg:
16850     case indir_dx_reg:
16851       OP_IMREG (bytemode, sizeflag);
16852       break;
16853     case eDI_reg:
16854       OP_ESreg (bytemode, sizeflag);
16855       break;
16856     case eSI_reg:
16857       OP_DSreg (bytemode, sizeflag);
16858       break;
16859     default:
16860       abort ();
16861       break;
16862     }
16863 }
16864
16865 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16866    "bnd".  */
16867
16868 static void
16869 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16870 {
16871   if (prefixes & PREFIX_REPNZ)
16872     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16873 }
16874
16875 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16876    "notrack".  */
16877
16878 static void
16879 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16880                int sizeflag ATTRIBUTE_UNUSED)
16881 {
16882   if (active_seg_prefix == PREFIX_DS
16883       && (address_mode != mode_64bit || last_data_prefix < 0))
16884     {
16885       /* NOTRACK prefix is only valid on indirect branch instructions.
16886          NB: DATA prefix is unsupported for Intel64.  */
16887       active_seg_prefix = 0;
16888       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16889     }
16890 }
16891
16892 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16893    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16894  */
16895
16896 static void
16897 HLE_Fixup1 (int bytemode, int sizeflag)
16898 {
16899   if (modrm.mod != 3
16900       && (prefixes & PREFIX_LOCK) != 0)
16901     {
16902       if (prefixes & PREFIX_REPZ)
16903         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16904       if (prefixes & PREFIX_REPNZ)
16905         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16906     }
16907
16908   OP_E (bytemode, sizeflag);
16909 }
16910
16911 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16912    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16913  */
16914
16915 static void
16916 HLE_Fixup2 (int bytemode, int sizeflag)
16917 {
16918   if (modrm.mod != 3)
16919     {
16920       if (prefixes & PREFIX_REPZ)
16921         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16922       if (prefixes & PREFIX_REPNZ)
16923         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16924     }
16925
16926   OP_E (bytemode, sizeflag);
16927 }
16928
16929 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16930    "xrelease" for memory operand.  No check for LOCK prefix.   */
16931
16932 static void
16933 HLE_Fixup3 (int bytemode, int sizeflag)
16934 {
16935   if (modrm.mod != 3
16936       && last_repz_prefix > last_repnz_prefix
16937       && (prefixes & PREFIX_REPZ) != 0)
16938     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16939
16940   OP_E (bytemode, sizeflag);
16941 }
16942
16943 static void
16944 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16945 {
16946   USED_REX (REX_W);
16947   if (rex & REX_W)
16948     {
16949       /* Change cmpxchg8b to cmpxchg16b.  */
16950       char *p = mnemonicendp - 2;
16951       mnemonicendp = stpcpy (p, "16b");
16952       bytemode = o_mode;
16953     }
16954   else if ((prefixes & PREFIX_LOCK) != 0)
16955     {
16956       if (prefixes & PREFIX_REPZ)
16957         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16958       if (prefixes & PREFIX_REPNZ)
16959         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16960     }
16961
16962   OP_M (bytemode, sizeflag);
16963 }
16964
16965 static void
16966 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16967 {
16968   const char **names;
16969
16970   if (need_vex)
16971     {
16972       switch (vex.length)
16973         {
16974         case 128:
16975           names = names_xmm;
16976           break;
16977         case 256:
16978           names = names_ymm;
16979           break;
16980         default:
16981           abort ();
16982         }
16983     }
16984   else
16985     names = names_xmm;
16986   oappend (names[reg]);
16987 }
16988
16989 static void
16990 CRC32_Fixup (int bytemode, int sizeflag)
16991 {
16992   /* Add proper suffix to "crc32".  */
16993   char *p = mnemonicendp;
16994
16995   switch (bytemode)
16996     {
16997     case b_mode:
16998       if (intel_syntax)
16999         goto skip;
17000
17001       *p++ = 'b';
17002       break;
17003     case v_mode:
17004       if (intel_syntax)
17005         goto skip;
17006
17007       USED_REX (REX_W);
17008       if (rex & REX_W)
17009         *p++ = 'q';
17010       else
17011         {
17012           if (sizeflag & DFLAG)
17013             *p++ = 'l';
17014           else
17015             *p++ = 'w';
17016           used_prefixes |= (prefixes & PREFIX_DATA);
17017         }
17018       break;
17019     default:
17020       oappend (INTERNAL_DISASSEMBLER_ERROR);
17021       break;
17022     }
17023   mnemonicendp = p;
17024   *p = '\0';
17025
17026 skip:
17027   if (modrm.mod == 3)
17028     {
17029       int add;
17030
17031       /* Skip mod/rm byte.  */
17032       MODRM_CHECK;
17033       codep++;
17034
17035       USED_REX (REX_B);
17036       add = (rex & REX_B) ? 8 : 0;
17037       if (bytemode == b_mode)
17038         {
17039           USED_REX (0);
17040           if (rex)
17041             oappend (names8rex[modrm.rm + add]);
17042           else
17043             oappend (names8[modrm.rm + add]);
17044         }
17045       else
17046         {
17047           USED_REX (REX_W);
17048           if (rex & REX_W)
17049             oappend (names64[modrm.rm + add]);
17050           else if ((prefixes & PREFIX_DATA))
17051             oappend (names16[modrm.rm + add]);
17052           else
17053             oappend (names32[modrm.rm + add]);
17054         }
17055     }
17056   else
17057     OP_E (bytemode, sizeflag);
17058 }
17059
17060 static void
17061 FXSAVE_Fixup (int bytemode, int sizeflag)
17062 {
17063   /* Add proper suffix to "fxsave" and "fxrstor".  */
17064   USED_REX (REX_W);
17065   if (rex & REX_W)
17066     {
17067       char *p = mnemonicendp;
17068       *p++ = '6';
17069       *p++ = '4';
17070       *p = '\0';
17071       mnemonicendp = p;
17072     }
17073   OP_M (bytemode, sizeflag);
17074 }
17075
17076 static void
17077 PCMPESTR_Fixup (int bytemode, int sizeflag)
17078 {
17079   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17080   if (!intel_syntax)
17081     {
17082       char *p = mnemonicendp;
17083
17084       USED_REX (REX_W);
17085       if (rex & REX_W)
17086         *p++ = 'q';
17087       else if (sizeflag & SUFFIX_ALWAYS)
17088         *p++ = 'l';
17089
17090       *p = '\0';
17091       mnemonicendp = p;
17092     }
17093
17094   OP_EX (bytemode, sizeflag);
17095 }
17096
17097 /* Display the destination register operand for instructions with
17098    VEX. */
17099
17100 static void
17101 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17102 {
17103   int reg;
17104   const char **names;
17105
17106   if (!need_vex)
17107     abort ();
17108
17109   if (!need_vex_reg)
17110     return;
17111
17112   reg = vex.register_specifier;
17113   if (address_mode != mode_64bit)
17114     reg &= 7;
17115   else if (vex.evex && !vex.v)
17116     reg += 16;
17117
17118   if (bytemode == vex_scalar_mode)
17119     {
17120       oappend (names_xmm[reg]);
17121       return;
17122     }
17123
17124   switch (vex.length)
17125     {
17126     case 128:
17127       switch (bytemode)
17128         {
17129         case vex_mode:
17130         case vex128_mode:
17131         case vex_vsib_q_w_dq_mode:
17132         case vex_vsib_q_w_d_mode:
17133           names = names_xmm;
17134           break;
17135         case dq_mode:
17136           if (rex & REX_W)
17137             names = names64;
17138           else
17139             names = names32;
17140           break;
17141         case mask_bd_mode:
17142         case mask_mode:
17143           if (reg > 0x7)
17144             {
17145               oappend ("(bad)");
17146               return;
17147             }
17148           names = names_mask;
17149           break;
17150         default:
17151           abort ();
17152           return;
17153         }
17154       break;
17155     case 256:
17156       switch (bytemode)
17157         {
17158         case vex_mode:
17159         case vex256_mode:
17160           names = names_ymm;
17161           break;
17162         case vex_vsib_q_w_dq_mode:
17163         case vex_vsib_q_w_d_mode:
17164           names = vex.w ? names_ymm : names_xmm;
17165           break;
17166         case mask_bd_mode:
17167         case mask_mode:
17168           if (reg > 0x7)
17169             {
17170               oappend ("(bad)");
17171               return;
17172             }
17173           names = names_mask;
17174           break;
17175         default:
17176           /* See PR binutils/20893 for a reproducer.  */
17177           oappend ("(bad)");
17178           return;
17179         }
17180       break;
17181     case 512:
17182       names = names_zmm;
17183       break;
17184     default:
17185       abort ();
17186       break;
17187     }
17188   oappend (names[reg]);
17189 }
17190
17191 /* Get the VEX immediate byte without moving codep.  */
17192
17193 static unsigned char
17194 get_vex_imm8 (int sizeflag, int opnum)
17195 {
17196   int bytes_before_imm = 0;
17197
17198   if (modrm.mod != 3)
17199     {
17200       /* There are SIB/displacement bytes.  */
17201       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17202         {
17203           /* 32/64 bit address mode */
17204           int base = modrm.rm;
17205
17206           /* Check SIB byte.  */
17207           if (base == 4)
17208             {
17209               FETCH_DATA (the_info, codep + 1);
17210               base = *codep & 7;
17211               /* When decoding the third source, don't increase
17212                  bytes_before_imm as this has already been incremented
17213                  by one in OP_E_memory while decoding the second
17214                  source operand.  */
17215               if (opnum == 0)
17216                 bytes_before_imm++;
17217             }
17218
17219           /* Don't increase bytes_before_imm when decoding the third source,
17220              it has already been incremented by OP_E_memory while decoding
17221              the second source operand.  */
17222           if (opnum == 0)
17223             {
17224               switch (modrm.mod)
17225                 {
17226                   case 0:
17227                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17228                        SIB == 5, there is a 4 byte displacement.  */
17229                     if (base != 5)
17230                       /* No displacement. */
17231                       break;
17232                     /* Fall through.  */
17233                   case 2:
17234                     /* 4 byte displacement.  */
17235                     bytes_before_imm += 4;
17236                     break;
17237                   case 1:
17238                     /* 1 byte displacement.  */
17239                     bytes_before_imm++;
17240                     break;
17241                 }
17242             }
17243         }
17244       else
17245         {
17246           /* 16 bit address mode */
17247           /* Don't increase bytes_before_imm when decoding the third source,
17248              it has already been incremented by OP_E_memory while decoding
17249              the second source operand.  */
17250           if (opnum == 0)
17251             {
17252               switch (modrm.mod)
17253                 {
17254                 case 0:
17255                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17256                   if (modrm.rm != 6)
17257                     /* No displacement. */
17258                     break;
17259                   /* Fall through.  */
17260                 case 2:
17261                   /* 2 byte displacement.  */
17262                   bytes_before_imm += 2;
17263                   break;
17264                 case 1:
17265                   /* 1 byte displacement: when decoding the third source,
17266                      don't increase bytes_before_imm as this has already
17267                      been incremented by one in OP_E_memory while decoding
17268                      the second source operand.  */
17269                   if (opnum == 0)
17270                     bytes_before_imm++;
17271
17272                   break;
17273                 }
17274             }
17275         }
17276     }
17277
17278   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17279   return codep [bytes_before_imm];
17280 }
17281
17282 static void
17283 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17284 {
17285   const char **names;
17286
17287   if (reg == -1 && modrm.mod != 3)
17288     {
17289       OP_E_memory (bytemode, sizeflag);
17290       return;
17291     }
17292   else
17293     {
17294       if (reg == -1)
17295         {
17296           reg = modrm.rm;
17297           USED_REX (REX_B);
17298           if (rex & REX_B)
17299             reg += 8;
17300         }
17301       if (address_mode != mode_64bit)
17302         reg &= 7;
17303     }
17304
17305   switch (vex.length)
17306     {
17307     case 128:
17308       names = names_xmm;
17309       break;
17310     case 256:
17311       names = names_ymm;
17312       break;
17313     default:
17314       abort ();
17315     }
17316   oappend (names[reg]);
17317 }
17318
17319 static void
17320 OP_EX_VexImmW (int bytemode, int sizeflag)
17321 {
17322   int reg = -1;
17323   static unsigned char vex_imm8;
17324
17325   if (vex_w_done == 0)
17326     {
17327       vex_w_done = 1;
17328
17329       /* Skip mod/rm byte.  */
17330       MODRM_CHECK;
17331       codep++;
17332
17333       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17334
17335       if (vex.w)
17336           reg = vex_imm8 >> 4;
17337
17338       OP_EX_VexReg (bytemode, sizeflag, reg);
17339     }
17340   else if (vex_w_done == 1)
17341     {
17342       vex_w_done = 2;
17343
17344       if (!vex.w)
17345           reg = vex_imm8 >> 4;
17346
17347       OP_EX_VexReg (bytemode, sizeflag, reg);
17348     }
17349   else
17350     {
17351       /* Output the imm8 directly.  */
17352       scratchbuf[0] = '$';
17353       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17354       oappend_maybe_intel (scratchbuf);
17355       scratchbuf[0] = '\0';
17356       codep++;
17357     }
17358 }
17359
17360 static void
17361 OP_Vex_2src (int bytemode, int sizeflag)
17362 {
17363   if (modrm.mod == 3)
17364     {
17365       int reg = modrm.rm;
17366       USED_REX (REX_B);
17367       if (rex & REX_B)
17368         reg += 8;
17369       oappend (names_xmm[reg]);
17370     }
17371   else
17372     {
17373       if (intel_syntax
17374           && (bytemode == v_mode || bytemode == v_swap_mode))
17375         {
17376           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17377           used_prefixes |= (prefixes & PREFIX_DATA);
17378         }
17379       OP_E (bytemode, sizeflag);
17380     }
17381 }
17382
17383 static void
17384 OP_Vex_2src_1 (int bytemode, int sizeflag)
17385 {
17386   if (modrm.mod == 3)
17387     {
17388       /* Skip mod/rm byte.   */
17389       MODRM_CHECK;
17390       codep++;
17391     }
17392
17393   if (vex.w)
17394     {
17395       unsigned int reg = vex.register_specifier;
17396
17397       if (address_mode != mode_64bit)
17398         reg &= 7;
17399       oappend (names_xmm[reg]);
17400     }
17401   else
17402     OP_Vex_2src (bytemode, sizeflag);
17403 }
17404
17405 static void
17406 OP_Vex_2src_2 (int bytemode, int sizeflag)
17407 {
17408   if (vex.w)
17409     OP_Vex_2src (bytemode, sizeflag);
17410   else
17411     {
17412       unsigned int reg = vex.register_specifier;
17413
17414       if (address_mode != mode_64bit)
17415         reg &= 7;
17416       oappend (names_xmm[reg]);
17417     }
17418 }
17419
17420 static void
17421 OP_EX_VexW (int bytemode, int sizeflag)
17422 {
17423   int reg = -1;
17424
17425   if (!vex_w_done)
17426     {
17427       /* Skip mod/rm byte.  */
17428       MODRM_CHECK;
17429       codep++;
17430
17431       if (vex.w)
17432         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17433     }
17434   else
17435     {
17436       if (!vex.w)
17437         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17438     }
17439
17440   OP_EX_VexReg (bytemode, sizeflag, reg);
17441
17442   if (vex_w_done)
17443     codep++;
17444   vex_w_done = 1;
17445 }
17446
17447 static void
17448 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17449 {
17450   int reg;
17451   const char **names;
17452
17453   FETCH_DATA (the_info, codep + 1);
17454   reg = *codep++;
17455
17456   if (bytemode != x_mode)
17457     abort ();
17458
17459   reg >>= 4;
17460   if (address_mode != mode_64bit)
17461     reg &= 7;
17462
17463   switch (vex.length)
17464     {
17465     case 128:
17466       names = names_xmm;
17467       break;
17468     case 256:
17469       names = names_ymm;
17470       break;
17471     default:
17472       abort ();
17473     }
17474   oappend (names[reg]);
17475 }
17476
17477 static void
17478 OP_XMM_VexW (int bytemode, int sizeflag)
17479 {
17480   /* Turn off the REX.W bit since it is used for swapping operands
17481      now.  */
17482   rex &= ~REX_W;
17483   OP_XMM (bytemode, sizeflag);
17484 }
17485
17486 static void
17487 OP_EX_Vex (int bytemode, int sizeflag)
17488 {
17489   if (modrm.mod != 3)
17490     {
17491       if (vex.register_specifier != 0)
17492         BadOp ();
17493       need_vex_reg = 0;
17494     }
17495   OP_EX (bytemode, sizeflag);
17496 }
17497
17498 static void
17499 OP_XMM_Vex (int bytemode, int sizeflag)
17500 {
17501   if (modrm.mod != 3)
17502     {
17503       if (vex.register_specifier != 0)
17504         BadOp ();
17505       need_vex_reg = 0;
17506     }
17507   OP_XMM (bytemode, sizeflag);
17508 }
17509
17510 static void
17511 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17512 {
17513   switch (vex.length)
17514     {
17515     case 128:
17516       mnemonicendp = stpcpy (obuf, "vzeroupper");
17517       break;
17518     case 256:
17519       mnemonicendp = stpcpy (obuf, "vzeroall");
17520       break;
17521     default:
17522       abort ();
17523     }
17524 }
17525
17526 static struct op vex_cmp_op[] =
17527 {
17528   { STRING_COMMA_LEN ("eq") },
17529   { STRING_COMMA_LEN ("lt") },
17530   { STRING_COMMA_LEN ("le") },
17531   { STRING_COMMA_LEN ("unord") },
17532   { STRING_COMMA_LEN ("neq") },
17533   { STRING_COMMA_LEN ("nlt") },
17534   { STRING_COMMA_LEN ("nle") },
17535   { STRING_COMMA_LEN ("ord") },
17536   { STRING_COMMA_LEN ("eq_uq") },
17537   { STRING_COMMA_LEN ("nge") },
17538   { STRING_COMMA_LEN ("ngt") },
17539   { STRING_COMMA_LEN ("false") },
17540   { STRING_COMMA_LEN ("neq_oq") },
17541   { STRING_COMMA_LEN ("ge") },
17542   { STRING_COMMA_LEN ("gt") },
17543   { STRING_COMMA_LEN ("true") },
17544   { STRING_COMMA_LEN ("eq_os") },
17545   { STRING_COMMA_LEN ("lt_oq") },
17546   { STRING_COMMA_LEN ("le_oq") },
17547   { STRING_COMMA_LEN ("unord_s") },
17548   { STRING_COMMA_LEN ("neq_us") },
17549   { STRING_COMMA_LEN ("nlt_uq") },
17550   { STRING_COMMA_LEN ("nle_uq") },
17551   { STRING_COMMA_LEN ("ord_s") },
17552   { STRING_COMMA_LEN ("eq_us") },
17553   { STRING_COMMA_LEN ("nge_uq") },
17554   { STRING_COMMA_LEN ("ngt_uq") },
17555   { STRING_COMMA_LEN ("false_os") },
17556   { STRING_COMMA_LEN ("neq_os") },
17557   { STRING_COMMA_LEN ("ge_oq") },
17558   { STRING_COMMA_LEN ("gt_oq") },
17559   { STRING_COMMA_LEN ("true_us") },
17560 };
17561
17562 static void
17563 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17564 {
17565   unsigned int cmp_type;
17566
17567   FETCH_DATA (the_info, codep + 1);
17568   cmp_type = *codep++ & 0xff;
17569   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17570     {
17571       char suffix [3];
17572       char *p = mnemonicendp - 2;
17573       suffix[0] = p[0];
17574       suffix[1] = p[1];
17575       suffix[2] = '\0';
17576       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17577       mnemonicendp += vex_cmp_op[cmp_type].len;
17578     }
17579   else
17580     {
17581       /* We have a reserved extension byte.  Output it directly.  */
17582       scratchbuf[0] = '$';
17583       print_operand_value (scratchbuf + 1, 1, cmp_type);
17584       oappend_maybe_intel (scratchbuf);
17585       scratchbuf[0] = '\0';
17586     }
17587 }
17588
17589 static void
17590 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17591              int sizeflag ATTRIBUTE_UNUSED)
17592 {
17593   unsigned int cmp_type;
17594
17595   if (!vex.evex)
17596     abort ();
17597
17598   FETCH_DATA (the_info, codep + 1);
17599   cmp_type = *codep++ & 0xff;
17600   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17601      If it's the case, print suffix, otherwise - print the immediate.  */
17602   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17603       && cmp_type != 3
17604       && cmp_type != 7)
17605     {
17606       char suffix [3];
17607       char *p = mnemonicendp - 2;
17608
17609       /* vpcmp* can have both one- and two-lettered suffix.  */
17610       if (p[0] == 'p')
17611         {
17612           p++;
17613           suffix[0] = p[0];
17614           suffix[1] = '\0';
17615         }
17616       else
17617         {
17618           suffix[0] = p[0];
17619           suffix[1] = p[1];
17620           suffix[2] = '\0';
17621         }
17622
17623       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17624       mnemonicendp += simd_cmp_op[cmp_type].len;
17625     }
17626   else
17627     {
17628       /* We have a reserved extension byte.  Output it directly.  */
17629       scratchbuf[0] = '$';
17630       print_operand_value (scratchbuf + 1, 1, cmp_type);
17631       oappend_maybe_intel (scratchbuf);
17632       scratchbuf[0] = '\0';
17633     }
17634 }
17635
17636 static const struct op xop_cmp_op[] =
17637 {
17638   { STRING_COMMA_LEN ("lt") },
17639   { STRING_COMMA_LEN ("le") },
17640   { STRING_COMMA_LEN ("gt") },
17641   { STRING_COMMA_LEN ("ge") },
17642   { STRING_COMMA_LEN ("eq") },
17643   { STRING_COMMA_LEN ("neq") },
17644   { STRING_COMMA_LEN ("false") },
17645   { STRING_COMMA_LEN ("true") }
17646 };
17647
17648 static void
17649 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17650              int sizeflag ATTRIBUTE_UNUSED)
17651 {
17652   unsigned int cmp_type;
17653
17654   FETCH_DATA (the_info, codep + 1);
17655   cmp_type = *codep++ & 0xff;
17656   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17657     {
17658       char suffix[3];
17659       char *p = mnemonicendp - 2;
17660
17661       /* vpcom* can have both one- and two-lettered suffix.  */
17662       if (p[0] == 'm')
17663         {
17664           p++;
17665           suffix[0] = p[0];
17666           suffix[1] = '\0';
17667         }
17668       else
17669         {
17670           suffix[0] = p[0];
17671           suffix[1] = p[1];
17672           suffix[2] = '\0';
17673         }
17674
17675       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17676       mnemonicendp += xop_cmp_op[cmp_type].len;
17677     }
17678   else
17679     {
17680       /* We have a reserved extension byte.  Output it directly.  */
17681       scratchbuf[0] = '$';
17682       print_operand_value (scratchbuf + 1, 1, cmp_type);
17683       oappend_maybe_intel (scratchbuf);
17684       scratchbuf[0] = '\0';
17685     }
17686 }
17687
17688 static const struct op pclmul_op[] =
17689 {
17690   { STRING_COMMA_LEN ("lql") },
17691   { STRING_COMMA_LEN ("hql") },
17692   { STRING_COMMA_LEN ("lqh") },
17693   { STRING_COMMA_LEN ("hqh") }
17694 };
17695
17696 static void
17697 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17698               int sizeflag ATTRIBUTE_UNUSED)
17699 {
17700   unsigned int pclmul_type;
17701
17702   FETCH_DATA (the_info, codep + 1);
17703   pclmul_type = *codep++ & 0xff;
17704   switch (pclmul_type)
17705     {
17706     case 0x10:
17707       pclmul_type = 2;
17708       break;
17709     case 0x11:
17710       pclmul_type = 3;
17711       break;
17712     default:
17713       break;
17714     }
17715   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17716     {
17717       char suffix [4];
17718       char *p = mnemonicendp - 3;
17719       suffix[0] = p[0];
17720       suffix[1] = p[1];
17721       suffix[2] = p[2];
17722       suffix[3] = '\0';
17723       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17724       mnemonicendp += pclmul_op[pclmul_type].len;
17725     }
17726   else
17727     {
17728       /* We have a reserved extension byte.  Output it directly.  */
17729       scratchbuf[0] = '$';
17730       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17731       oappend_maybe_intel (scratchbuf);
17732       scratchbuf[0] = '\0';
17733     }
17734 }
17735
17736 static void
17737 MOVBE_Fixup (int bytemode, int sizeflag)
17738 {
17739   /* Add proper suffix to "movbe".  */
17740   char *p = mnemonicendp;
17741
17742   switch (bytemode)
17743     {
17744     case v_mode:
17745       if (intel_syntax)
17746         goto skip;
17747
17748       USED_REX (REX_W);
17749       if (sizeflag & SUFFIX_ALWAYS)
17750         {
17751           if (rex & REX_W)
17752             *p++ = 'q';
17753           else
17754             {
17755               if (sizeflag & DFLAG)
17756                 *p++ = 'l';
17757               else
17758                 *p++ = 'w';
17759               used_prefixes |= (prefixes & PREFIX_DATA);
17760             }
17761         }
17762       break;
17763     default:
17764       oappend (INTERNAL_DISASSEMBLER_ERROR);
17765       break;
17766     }
17767   mnemonicendp = p;
17768   *p = '\0';
17769
17770 skip:
17771   OP_M (bytemode, sizeflag);
17772 }
17773
17774 static void
17775 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17776 {
17777   int reg;
17778   const char **names;
17779
17780   /* Skip mod/rm byte.  */
17781   MODRM_CHECK;
17782   codep++;
17783
17784   if (rex & REX_W)
17785     names = names64;
17786   else
17787     names = names32;
17788
17789   reg = modrm.rm;
17790   USED_REX (REX_B);
17791   if (rex & REX_B)
17792     reg += 8;
17793
17794   oappend (names[reg]);
17795 }
17796
17797 static void
17798 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17799 {
17800   const char **names;
17801   unsigned int reg = vex.register_specifier;
17802
17803   if (rex & REX_W)
17804     names = names64;
17805   else
17806     names = names32;
17807
17808   if (address_mode != mode_64bit)
17809     reg &= 7;
17810   oappend (names[reg]);
17811 }
17812
17813 static void
17814 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17815 {
17816   if (!vex.evex
17817       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17818     abort ();
17819
17820   USED_REX (REX_R);
17821   if ((rex & REX_R) != 0 || !vex.r)
17822     {
17823       BadOp ();
17824       return;
17825     }
17826
17827   oappend (names_mask [modrm.reg]);
17828 }
17829
17830 static void
17831 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17832 {
17833   if (!vex.evex
17834       || (bytemode != evex_rounding_mode
17835           && bytemode != evex_sae_mode))
17836     abort ();
17837   if (modrm.mod == 3 && vex.b)
17838     switch (bytemode)
17839       {
17840       case evex_rounding_mode:
17841         oappend (names_rounding[vex.ll]);
17842         break;
17843       case evex_sae_mode:
17844         oappend ("{sae}");
17845         break;
17846       default:
17847         break;
17848       }
17849 }